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drm/i915: Keep plane->state updated on pageflip
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 */
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
902 }
903
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906 {
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
910 return intel_crtc->config->cpu_transcoder;
911 }
912
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914 {
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930 }
931
932 /*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
946 *
947 */
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
949 {
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
954
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
957
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
961 WARN(1, "pipe_off wait timed out\n");
962 } else {
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
966 }
967 }
968
969 /*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978 {
979 u32 bit;
980
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
996 switch (port->port) {
997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016 return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1022 {
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058 if (crtc->config->shared_dpll < 0)
1059 return NULL;
1060
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
1068 {
1069 bool cur_state;
1070 struct intel_dpll_hw_state hw_state;
1071
1072 if (WARN (!pll,
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1074 return;
1075
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084 {
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
1090
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110 {
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133 return;
1134
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1137 return;
1138
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
1166 bool locked = true;
1167
1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
1185 } else {
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1198 pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209 else
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231 state = true;
1232
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 struct drm_device *dev = dev_priv->dev;
1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
1280 return;
1281 }
1282
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1292 }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, sprite;
1300 u32 val;
1301
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1329 }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340 u32 val;
1341 bool enabled;
1342
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
1353 {
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1439 {
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1444
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452 {
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 int reg;
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 pipe_name(pipe));
1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1512 {
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1551 {
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1584
1585 mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597 return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
1644
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
1705 if (pipe == PIPE_B)
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715 u32 val;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1750 {
1751 u32 port_mask;
1752 int dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1766 break;
1767 default:
1768 BUG();
1769 }
1770
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793 }
1794
1795 /**
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1813 return;
1814
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1818
1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 return;
1823 }
1824 WARN_ON(pll->on);
1825
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1830 pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1842 return;
1843
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1845 return;
1846
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1850
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853 return;
1854 }
1855
1856 assert_shared_dpll_enabled(dev_priv, pll);
1857 WARN_ON(!pll->on);
1858 if (--pll->active)
1859 return;
1860
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1863 pll->on = false;
1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
1870 {
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1875
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1894 }
1895
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907 }
1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1926 {
1927 u32 val, pipeconf_val;
1928
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941 val = TRANS_ENABLE;
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
1957 {
1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987 u32 val;
1988
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2005 *
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
2016 enum pipe pch_transcoder;
2017 int reg;
2018 u32 val;
2019
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2023
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
2039 else {
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 return;
2055 }
2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2058 POSTING_READ(reg);
2059 }
2060
2061 /**
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2064 *
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
2115 {
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
2121 }
2122
2123 /**
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140 if (intel_crtc->primary_enabled)
2141 return;
2142
2143 intel_crtc->primary_enabled = true;
2144
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2161 *
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2166 {
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171 if (WARN_ON(!intel_crtc->active))
2172 return;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188 #endif
2189 return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2194 {
2195 int tile_height;
2196
2197 tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2198 return ALIGN(height, tile_height);
2199 }
2200
2201 int
2202 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2203 struct drm_framebuffer *fb,
2204 struct intel_engine_cs *pipelined)
2205 {
2206 struct drm_device *dev = fb->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2209 u32 alignment;
2210 int ret;
2211
2212 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2213
2214 switch (obj->tiling_mode) {
2215 case I915_TILING_NONE:
2216 if (INTEL_INFO(dev)->gen >= 9)
2217 alignment = 256 * 1024;
2218 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2219 alignment = 128 * 1024;
2220 else if (INTEL_INFO(dev)->gen >= 4)
2221 alignment = 4 * 1024;
2222 else
2223 alignment = 64 * 1024;
2224 break;
2225 case I915_TILING_X:
2226 if (INTEL_INFO(dev)->gen >= 9)
2227 alignment = 256 * 1024;
2228 else {
2229 /* pin() will align the object as required by fence */
2230 alignment = 0;
2231 }
2232 break;
2233 case I915_TILING_Y:
2234 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2235 return -EINVAL;
2236 default:
2237 BUG();
2238 }
2239
2240 /* Note that the w/a also requires 64 PTE of padding following the
2241 * bo. We currently fill all unused PTE with the shadow page and so
2242 * we should always have valid PTE following the scanout preventing
2243 * the VT-d warning.
2244 */
2245 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2246 alignment = 256 * 1024;
2247
2248 /*
2249 * Global gtt pte registers are special registers which actually forward
2250 * writes to a chunk of system memory. Which means that there is no risk
2251 * that the register values disappear as soon as we call
2252 * intel_runtime_pm_put(), so it is correct to wrap only the
2253 * pin/unpin/fence and not more.
2254 */
2255 intel_runtime_pm_get(dev_priv);
2256
2257 dev_priv->mm.interruptible = false;
2258 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2259 if (ret)
2260 goto err_interruptible;
2261
2262 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2263 * fence, whereas 965+ only requires a fence if using
2264 * framebuffer compression. For simplicity, we always install
2265 * a fence as the cost is not that onerous.
2266 */
2267 ret = i915_gem_object_get_fence(obj);
2268 if (ret)
2269 goto err_unpin;
2270
2271 i915_gem_object_pin_fence(obj);
2272
2273 dev_priv->mm.interruptible = true;
2274 intel_runtime_pm_put(dev_priv);
2275 return 0;
2276
2277 err_unpin:
2278 i915_gem_object_unpin_from_display_plane(obj);
2279 err_interruptible:
2280 dev_priv->mm.interruptible = true;
2281 intel_runtime_pm_put(dev_priv);
2282 return ret;
2283 }
2284
2285 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2286 {
2287 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2288
2289 i915_gem_object_unpin_fence(obj);
2290 i915_gem_object_unpin_from_display_plane(obj);
2291 }
2292
2293 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2294 * is assumed to be a power-of-two. */
2295 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2296 unsigned int tiling_mode,
2297 unsigned int cpp,
2298 unsigned int pitch)
2299 {
2300 if (tiling_mode != I915_TILING_NONE) {
2301 unsigned int tile_rows, tiles;
2302
2303 tile_rows = *y / 8;
2304 *y %= 8;
2305
2306 tiles = *x / (512/cpp);
2307 *x %= 512/cpp;
2308
2309 return tile_rows * pitch * 8 + tiles * 4096;
2310 } else {
2311 unsigned int offset;
2312
2313 offset = *y * pitch + *x * cpp;
2314 *y = 0;
2315 *x = (offset & 4095) / cpp;
2316 return offset & -4096;
2317 }
2318 }
2319
2320 static int i9xx_format_to_fourcc(int format)
2321 {
2322 switch (format) {
2323 case DISPPLANE_8BPP:
2324 return DRM_FORMAT_C8;
2325 case DISPPLANE_BGRX555:
2326 return DRM_FORMAT_XRGB1555;
2327 case DISPPLANE_BGRX565:
2328 return DRM_FORMAT_RGB565;
2329 default:
2330 case DISPPLANE_BGRX888:
2331 return DRM_FORMAT_XRGB8888;
2332 case DISPPLANE_RGBX888:
2333 return DRM_FORMAT_XBGR8888;
2334 case DISPPLANE_BGRX101010:
2335 return DRM_FORMAT_XRGB2101010;
2336 case DISPPLANE_RGBX101010:
2337 return DRM_FORMAT_XBGR2101010;
2338 }
2339 }
2340
2341 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2342 {
2343 switch (format) {
2344 case PLANE_CTL_FORMAT_RGB_565:
2345 return DRM_FORMAT_RGB565;
2346 default:
2347 case PLANE_CTL_FORMAT_XRGB_8888:
2348 if (rgb_order) {
2349 if (alpha)
2350 return DRM_FORMAT_ABGR8888;
2351 else
2352 return DRM_FORMAT_XBGR8888;
2353 } else {
2354 if (alpha)
2355 return DRM_FORMAT_ARGB8888;
2356 else
2357 return DRM_FORMAT_XRGB8888;
2358 }
2359 case PLANE_CTL_FORMAT_XRGB_2101010:
2360 if (rgb_order)
2361 return DRM_FORMAT_XBGR2101010;
2362 else
2363 return DRM_FORMAT_XRGB2101010;
2364 }
2365 }
2366
2367 static bool
2368 intel_alloc_plane_obj(struct intel_crtc *crtc,
2369 struct intel_initial_plane_config *plane_config)
2370 {
2371 struct drm_device *dev = crtc->base.dev;
2372 struct drm_i915_gem_object *obj = NULL;
2373 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2374 u32 base = plane_config->base;
2375
2376 if (plane_config->size == 0)
2377 return false;
2378
2379 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2380 plane_config->size);
2381 if (!obj)
2382 return false;
2383
2384 obj->tiling_mode = plane_config->tiling;
2385 if (obj->tiling_mode == I915_TILING_X)
2386 obj->stride = crtc->base.primary->fb->pitches[0];
2387
2388 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2389 mode_cmd.width = crtc->base.primary->fb->width;
2390 mode_cmd.height = crtc->base.primary->fb->height;
2391 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2392
2393 mutex_lock(&dev->struct_mutex);
2394
2395 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2396 &mode_cmd, obj)) {
2397 DRM_DEBUG_KMS("intel fb init failed\n");
2398 goto out_unref_obj;
2399 }
2400
2401 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2402 mutex_unlock(&dev->struct_mutex);
2403
2404 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2405 return true;
2406
2407 out_unref_obj:
2408 drm_gem_object_unreference(&obj->base);
2409 mutex_unlock(&dev->struct_mutex);
2410 return false;
2411 }
2412
2413 static void
2414 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2415 struct intel_initial_plane_config *plane_config)
2416 {
2417 struct drm_device *dev = intel_crtc->base.dev;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct drm_crtc *c;
2420 struct intel_crtc *i;
2421 struct drm_i915_gem_object *obj;
2422
2423 if (!intel_crtc->base.primary->fb)
2424 return;
2425
2426 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2427 return;
2428
2429 kfree(intel_crtc->base.primary->fb);
2430 intel_crtc->base.primary->fb = NULL;
2431
2432 /*
2433 * Failed to alloc the obj, check to see if we should share
2434 * an fb with another CRTC instead
2435 */
2436 for_each_crtc(dev, c) {
2437 i = to_intel_crtc(c);
2438
2439 if (c == &intel_crtc->base)
2440 continue;
2441
2442 if (!i->active)
2443 continue;
2444
2445 obj = intel_fb_obj(c->primary->fb);
2446 if (obj == NULL)
2447 continue;
2448
2449 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2450 if (obj->tiling_mode != I915_TILING_NONE)
2451 dev_priv->preserve_bios_swizzle = true;
2452
2453 drm_framebuffer_reference(c->primary->fb);
2454 intel_crtc->base.primary->fb = c->primary->fb;
2455 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2456 break;
2457 }
2458 }
2459 }
2460
2461 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2462 struct drm_framebuffer *fb,
2463 int x, int y)
2464 {
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 struct drm_i915_gem_object *obj;
2469 int plane = intel_crtc->plane;
2470 unsigned long linear_offset;
2471 u32 dspcntr;
2472 u32 reg = DSPCNTR(plane);
2473 int pixel_size;
2474
2475 if (!intel_crtc->primary_enabled) {
2476 I915_WRITE(reg, 0);
2477 if (INTEL_INFO(dev)->gen >= 4)
2478 I915_WRITE(DSPSURF(plane), 0);
2479 else
2480 I915_WRITE(DSPADDR(plane), 0);
2481 POSTING_READ(reg);
2482 return;
2483 }
2484
2485 obj = intel_fb_obj(fb);
2486 if (WARN_ON(obj == NULL))
2487 return;
2488
2489 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2490
2491 dspcntr = DISPPLANE_GAMMA_ENABLE;
2492
2493 dspcntr |= DISPLAY_PLANE_ENABLE;
2494
2495 if (INTEL_INFO(dev)->gen < 4) {
2496 if (intel_crtc->pipe == PIPE_B)
2497 dspcntr |= DISPPLANE_SEL_PIPE_B;
2498
2499 /* pipesrc and dspsize control the size that is scaled from,
2500 * which should always be the user's requested size.
2501 */
2502 I915_WRITE(DSPSIZE(plane),
2503 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2504 (intel_crtc->config->pipe_src_w - 1));
2505 I915_WRITE(DSPPOS(plane), 0);
2506 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2507 I915_WRITE(PRIMSIZE(plane),
2508 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2509 (intel_crtc->config->pipe_src_w - 1));
2510 I915_WRITE(PRIMPOS(plane), 0);
2511 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2512 }
2513
2514 switch (fb->pixel_format) {
2515 case DRM_FORMAT_C8:
2516 dspcntr |= DISPPLANE_8BPP;
2517 break;
2518 case DRM_FORMAT_XRGB1555:
2519 case DRM_FORMAT_ARGB1555:
2520 dspcntr |= DISPPLANE_BGRX555;
2521 break;
2522 case DRM_FORMAT_RGB565:
2523 dspcntr |= DISPPLANE_BGRX565;
2524 break;
2525 case DRM_FORMAT_XRGB8888:
2526 case DRM_FORMAT_ARGB8888:
2527 dspcntr |= DISPPLANE_BGRX888;
2528 break;
2529 case DRM_FORMAT_XBGR8888:
2530 case DRM_FORMAT_ABGR8888:
2531 dspcntr |= DISPPLANE_RGBX888;
2532 break;
2533 case DRM_FORMAT_XRGB2101010:
2534 case DRM_FORMAT_ARGB2101010:
2535 dspcntr |= DISPPLANE_BGRX101010;
2536 break;
2537 case DRM_FORMAT_XBGR2101010:
2538 case DRM_FORMAT_ABGR2101010:
2539 dspcntr |= DISPPLANE_RGBX101010;
2540 break;
2541 default:
2542 BUG();
2543 }
2544
2545 if (INTEL_INFO(dev)->gen >= 4 &&
2546 obj->tiling_mode != I915_TILING_NONE)
2547 dspcntr |= DISPPLANE_TILED;
2548
2549 if (IS_G4X(dev))
2550 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2551
2552 linear_offset = y * fb->pitches[0] + x * pixel_size;
2553
2554 if (INTEL_INFO(dev)->gen >= 4) {
2555 intel_crtc->dspaddr_offset =
2556 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2557 pixel_size,
2558 fb->pitches[0]);
2559 linear_offset -= intel_crtc->dspaddr_offset;
2560 } else {
2561 intel_crtc->dspaddr_offset = linear_offset;
2562 }
2563
2564 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2565 dspcntr |= DISPPLANE_ROTATE_180;
2566
2567 x += (intel_crtc->config->pipe_src_w - 1);
2568 y += (intel_crtc->config->pipe_src_h - 1);
2569
2570 /* Finding the last pixel of the last line of the display
2571 data and adding to linear_offset*/
2572 linear_offset +=
2573 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2574 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2575 }
2576
2577 I915_WRITE(reg, dspcntr);
2578
2579 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2580 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2581 fb->pitches[0]);
2582 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2583 if (INTEL_INFO(dev)->gen >= 4) {
2584 I915_WRITE(DSPSURF(plane),
2585 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2586 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2587 I915_WRITE(DSPLINOFF(plane), linear_offset);
2588 } else
2589 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2590 POSTING_READ(reg);
2591 }
2592
2593 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2594 struct drm_framebuffer *fb,
2595 int x, int y)
2596 {
2597 struct drm_device *dev = crtc->dev;
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2600 struct drm_i915_gem_object *obj;
2601 int plane = intel_crtc->plane;
2602 unsigned long linear_offset;
2603 u32 dspcntr;
2604 u32 reg = DSPCNTR(plane);
2605 int pixel_size;
2606
2607 if (!intel_crtc->primary_enabled) {
2608 I915_WRITE(reg, 0);
2609 I915_WRITE(DSPSURF(plane), 0);
2610 POSTING_READ(reg);
2611 return;
2612 }
2613
2614 obj = intel_fb_obj(fb);
2615 if (WARN_ON(obj == NULL))
2616 return;
2617
2618 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2619
2620 dspcntr = DISPPLANE_GAMMA_ENABLE;
2621
2622 dspcntr |= DISPLAY_PLANE_ENABLE;
2623
2624 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2625 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2626
2627 switch (fb->pixel_format) {
2628 case DRM_FORMAT_C8:
2629 dspcntr |= DISPPLANE_8BPP;
2630 break;
2631 case DRM_FORMAT_RGB565:
2632 dspcntr |= DISPPLANE_BGRX565;
2633 break;
2634 case DRM_FORMAT_XRGB8888:
2635 case DRM_FORMAT_ARGB8888:
2636 dspcntr |= DISPPLANE_BGRX888;
2637 break;
2638 case DRM_FORMAT_XBGR8888:
2639 case DRM_FORMAT_ABGR8888:
2640 dspcntr |= DISPPLANE_RGBX888;
2641 break;
2642 case DRM_FORMAT_XRGB2101010:
2643 case DRM_FORMAT_ARGB2101010:
2644 dspcntr |= DISPPLANE_BGRX101010;
2645 break;
2646 case DRM_FORMAT_XBGR2101010:
2647 case DRM_FORMAT_ABGR2101010:
2648 dspcntr |= DISPPLANE_RGBX101010;
2649 break;
2650 default:
2651 BUG();
2652 }
2653
2654 if (obj->tiling_mode != I915_TILING_NONE)
2655 dspcntr |= DISPPLANE_TILED;
2656
2657 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2658 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2659
2660 linear_offset = y * fb->pitches[0] + x * pixel_size;
2661 intel_crtc->dspaddr_offset =
2662 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2663 pixel_size,
2664 fb->pitches[0]);
2665 linear_offset -= intel_crtc->dspaddr_offset;
2666 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2667 dspcntr |= DISPPLANE_ROTATE_180;
2668
2669 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2670 x += (intel_crtc->config->pipe_src_w - 1);
2671 y += (intel_crtc->config->pipe_src_h - 1);
2672
2673 /* Finding the last pixel of the last line of the display
2674 data and adding to linear_offset*/
2675 linear_offset +=
2676 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2677 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2678 }
2679 }
2680
2681 I915_WRITE(reg, dspcntr);
2682
2683 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2684 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2685 fb->pitches[0]);
2686 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2687 I915_WRITE(DSPSURF(plane),
2688 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2689 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2690 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2691 } else {
2692 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2693 I915_WRITE(DSPLINOFF(plane), linear_offset);
2694 }
2695 POSTING_READ(reg);
2696 }
2697
2698 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2699 struct drm_framebuffer *fb,
2700 int x, int y)
2701 {
2702 struct drm_device *dev = crtc->dev;
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2705 struct intel_framebuffer *intel_fb;
2706 struct drm_i915_gem_object *obj;
2707 int pipe = intel_crtc->pipe;
2708 u32 plane_ctl, stride;
2709
2710 if (!intel_crtc->primary_enabled) {
2711 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2712 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2713 POSTING_READ(PLANE_CTL(pipe, 0));
2714 return;
2715 }
2716
2717 plane_ctl = PLANE_CTL_ENABLE |
2718 PLANE_CTL_PIPE_GAMMA_ENABLE |
2719 PLANE_CTL_PIPE_CSC_ENABLE;
2720
2721 switch (fb->pixel_format) {
2722 case DRM_FORMAT_RGB565:
2723 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2724 break;
2725 case DRM_FORMAT_XRGB8888:
2726 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2727 break;
2728 case DRM_FORMAT_XBGR8888:
2729 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2730 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2731 break;
2732 case DRM_FORMAT_XRGB2101010:
2733 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2734 break;
2735 case DRM_FORMAT_XBGR2101010:
2736 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2737 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2738 break;
2739 default:
2740 BUG();
2741 }
2742
2743 intel_fb = to_intel_framebuffer(fb);
2744 obj = intel_fb->obj;
2745
2746 /*
2747 * The stride is either expressed as a multiple of 64 bytes chunks for
2748 * linear buffers or in number of tiles for tiled buffers.
2749 */
2750 switch (obj->tiling_mode) {
2751 case I915_TILING_NONE:
2752 stride = fb->pitches[0] >> 6;
2753 break;
2754 case I915_TILING_X:
2755 plane_ctl |= PLANE_CTL_TILED_X;
2756 stride = fb->pitches[0] >> 9;
2757 break;
2758 default:
2759 BUG();
2760 }
2761
2762 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2763 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2764 plane_ctl |= PLANE_CTL_ROTATE_180;
2765
2766 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2767
2768 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2769 i915_gem_obj_ggtt_offset(obj),
2770 x, y, fb->width, fb->height,
2771 fb->pitches[0]);
2772
2773 I915_WRITE(PLANE_POS(pipe, 0), 0);
2774 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2775 I915_WRITE(PLANE_SIZE(pipe, 0),
2776 (intel_crtc->config->pipe_src_h - 1) << 16 |
2777 (intel_crtc->config->pipe_src_w - 1));
2778 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2779 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2780
2781 POSTING_READ(PLANE_SURF(pipe, 0));
2782 }
2783
2784 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2785 static int
2786 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2787 int x, int y, enum mode_set_atomic state)
2788 {
2789 struct drm_device *dev = crtc->dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791
2792 if (dev_priv->display.disable_fbc)
2793 dev_priv->display.disable_fbc(dev);
2794
2795 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2796
2797 return 0;
2798 }
2799
2800 static void intel_complete_page_flips(struct drm_device *dev)
2801 {
2802 struct drm_crtc *crtc;
2803
2804 for_each_crtc(dev, crtc) {
2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806 enum plane plane = intel_crtc->plane;
2807
2808 intel_prepare_page_flip(dev, plane);
2809 intel_finish_page_flip_plane(dev, plane);
2810 }
2811 }
2812
2813 static void intel_update_primary_planes(struct drm_device *dev)
2814 {
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct drm_crtc *crtc;
2817
2818 for_each_crtc(dev, crtc) {
2819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2820
2821 drm_modeset_lock(&crtc->mutex, NULL);
2822 /*
2823 * FIXME: Once we have proper support for primary planes (and
2824 * disabling them without disabling the entire crtc) allow again
2825 * a NULL crtc->primary->fb.
2826 */
2827 if (intel_crtc->active && crtc->primary->fb)
2828 dev_priv->display.update_primary_plane(crtc,
2829 crtc->primary->fb,
2830 crtc->x,
2831 crtc->y);
2832 drm_modeset_unlock(&crtc->mutex);
2833 }
2834 }
2835
2836 void intel_prepare_reset(struct drm_device *dev)
2837 {
2838 struct drm_i915_private *dev_priv = to_i915(dev);
2839 struct intel_crtc *crtc;
2840
2841 /* no reset support for gen2 */
2842 if (IS_GEN2(dev))
2843 return;
2844
2845 /* reset doesn't touch the display */
2846 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2847 return;
2848
2849 drm_modeset_lock_all(dev);
2850
2851 /*
2852 * Disabling the crtcs gracefully seems nicer. Also the
2853 * g33 docs say we should at least disable all the planes.
2854 */
2855 for_each_intel_crtc(dev, crtc) {
2856 if (crtc->active)
2857 dev_priv->display.crtc_disable(&crtc->base);
2858 }
2859 }
2860
2861 void intel_finish_reset(struct drm_device *dev)
2862 {
2863 struct drm_i915_private *dev_priv = to_i915(dev);
2864
2865 /*
2866 * Flips in the rings will be nuked by the reset,
2867 * so complete all pending flips so that user space
2868 * will get its events and not get stuck.
2869 */
2870 intel_complete_page_flips(dev);
2871
2872 /* no reset support for gen2 */
2873 if (IS_GEN2(dev))
2874 return;
2875
2876 /* reset doesn't touch the display */
2877 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2878 /*
2879 * Flips in the rings have been nuked by the reset,
2880 * so update the base address of all primary
2881 * planes to the the last fb to make sure we're
2882 * showing the correct fb after a reset.
2883 */
2884 intel_update_primary_planes(dev);
2885 return;
2886 }
2887
2888 /*
2889 * The display has been reset as well,
2890 * so need a full re-initialization.
2891 */
2892 intel_runtime_pm_disable_interrupts(dev_priv);
2893 intel_runtime_pm_enable_interrupts(dev_priv);
2894
2895 intel_modeset_init_hw(dev);
2896
2897 spin_lock_irq(&dev_priv->irq_lock);
2898 if (dev_priv->display.hpd_irq_setup)
2899 dev_priv->display.hpd_irq_setup(dev);
2900 spin_unlock_irq(&dev_priv->irq_lock);
2901
2902 intel_modeset_setup_hw_state(dev, true);
2903
2904 intel_hpd_init(dev_priv);
2905
2906 drm_modeset_unlock_all(dev);
2907 }
2908
2909 static int
2910 intel_finish_fb(struct drm_framebuffer *old_fb)
2911 {
2912 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2913 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2914 bool was_interruptible = dev_priv->mm.interruptible;
2915 int ret;
2916
2917 /* Big Hammer, we also need to ensure that any pending
2918 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2919 * current scanout is retired before unpinning the old
2920 * framebuffer.
2921 *
2922 * This should only fail upon a hung GPU, in which case we
2923 * can safely continue.
2924 */
2925 dev_priv->mm.interruptible = false;
2926 ret = i915_gem_object_finish_gpu(obj);
2927 dev_priv->mm.interruptible = was_interruptible;
2928
2929 return ret;
2930 }
2931
2932 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2933 {
2934 struct drm_device *dev = crtc->dev;
2935 struct drm_i915_private *dev_priv = dev->dev_private;
2936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2937 bool pending;
2938
2939 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2940 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2941 return false;
2942
2943 spin_lock_irq(&dev->event_lock);
2944 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2945 spin_unlock_irq(&dev->event_lock);
2946
2947 return pending;
2948 }
2949
2950 static void intel_update_pipe_size(struct intel_crtc *crtc)
2951 {
2952 struct drm_device *dev = crtc->base.dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 const struct drm_display_mode *adjusted_mode;
2955
2956 if (!i915.fastboot)
2957 return;
2958
2959 /*
2960 * Update pipe size and adjust fitter if needed: the reason for this is
2961 * that in compute_mode_changes we check the native mode (not the pfit
2962 * mode) to see if we can flip rather than do a full mode set. In the
2963 * fastboot case, we'll flip, but if we don't update the pipesrc and
2964 * pfit state, we'll end up with a big fb scanned out into the wrong
2965 * sized surface.
2966 *
2967 * To fix this properly, we need to hoist the checks up into
2968 * compute_mode_changes (or above), check the actual pfit state and
2969 * whether the platform allows pfit disable with pipe active, and only
2970 * then update the pipesrc and pfit state, even on the flip path.
2971 */
2972
2973 adjusted_mode = &crtc->config->base.adjusted_mode;
2974
2975 I915_WRITE(PIPESRC(crtc->pipe),
2976 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2977 (adjusted_mode->crtc_vdisplay - 1));
2978 if (!crtc->config->pch_pfit.enabled &&
2979 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2980 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2981 I915_WRITE(PF_CTL(crtc->pipe), 0);
2982 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2983 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2984 }
2985 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
2986 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
2987 }
2988
2989 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2990 {
2991 struct drm_device *dev = crtc->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2994 int pipe = intel_crtc->pipe;
2995 u32 reg, temp;
2996
2997 /* enable normal train */
2998 reg = FDI_TX_CTL(pipe);
2999 temp = I915_READ(reg);
3000 if (IS_IVYBRIDGE(dev)) {
3001 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3002 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3003 } else {
3004 temp &= ~FDI_LINK_TRAIN_NONE;
3005 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3006 }
3007 I915_WRITE(reg, temp);
3008
3009 reg = FDI_RX_CTL(pipe);
3010 temp = I915_READ(reg);
3011 if (HAS_PCH_CPT(dev)) {
3012 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3013 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3014 } else {
3015 temp &= ~FDI_LINK_TRAIN_NONE;
3016 temp |= FDI_LINK_TRAIN_NONE;
3017 }
3018 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3019
3020 /* wait one idle pattern time */
3021 POSTING_READ(reg);
3022 udelay(1000);
3023
3024 /* IVB wants error correction enabled */
3025 if (IS_IVYBRIDGE(dev))
3026 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3027 FDI_FE_ERRC_ENABLE);
3028 }
3029
3030 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3031 {
3032 return crtc->base.enabled && crtc->active &&
3033 crtc->config->has_pch_encoder;
3034 }
3035
3036 static void ivb_modeset_global_resources(struct drm_device *dev)
3037 {
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct intel_crtc *pipe_B_crtc =
3040 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3041 struct intel_crtc *pipe_C_crtc =
3042 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3043 uint32_t temp;
3044
3045 /*
3046 * When everything is off disable fdi C so that we could enable fdi B
3047 * with all lanes. Note that we don't care about enabled pipes without
3048 * an enabled pch encoder.
3049 */
3050 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3051 !pipe_has_enabled_pch(pipe_C_crtc)) {
3052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3053 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3054
3055 temp = I915_READ(SOUTH_CHICKEN1);
3056 temp &= ~FDI_BC_BIFURCATION_SELECT;
3057 DRM_DEBUG_KMS("disabling fdi C rx\n");
3058 I915_WRITE(SOUTH_CHICKEN1, temp);
3059 }
3060 }
3061
3062 /* The FDI link training functions for ILK/Ibexpeak. */
3063 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3064 {
3065 struct drm_device *dev = crtc->dev;
3066 struct drm_i915_private *dev_priv = dev->dev_private;
3067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3068 int pipe = intel_crtc->pipe;
3069 u32 reg, temp, tries;
3070
3071 /* FDI needs bits from pipe first */
3072 assert_pipe_enabled(dev_priv, pipe);
3073
3074 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3075 for train result */
3076 reg = FDI_RX_IMR(pipe);
3077 temp = I915_READ(reg);
3078 temp &= ~FDI_RX_SYMBOL_LOCK;
3079 temp &= ~FDI_RX_BIT_LOCK;
3080 I915_WRITE(reg, temp);
3081 I915_READ(reg);
3082 udelay(150);
3083
3084 /* enable CPU FDI TX and PCH FDI RX */
3085 reg = FDI_TX_CTL(pipe);
3086 temp = I915_READ(reg);
3087 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3088 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3089 temp &= ~FDI_LINK_TRAIN_NONE;
3090 temp |= FDI_LINK_TRAIN_PATTERN_1;
3091 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3092
3093 reg = FDI_RX_CTL(pipe);
3094 temp = I915_READ(reg);
3095 temp &= ~FDI_LINK_TRAIN_NONE;
3096 temp |= FDI_LINK_TRAIN_PATTERN_1;
3097 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3098
3099 POSTING_READ(reg);
3100 udelay(150);
3101
3102 /* Ironlake workaround, enable clock pointer after FDI enable*/
3103 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3104 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3105 FDI_RX_PHASE_SYNC_POINTER_EN);
3106
3107 reg = FDI_RX_IIR(pipe);
3108 for (tries = 0; tries < 5; tries++) {
3109 temp = I915_READ(reg);
3110 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3111
3112 if ((temp & FDI_RX_BIT_LOCK)) {
3113 DRM_DEBUG_KMS("FDI train 1 done.\n");
3114 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3115 break;
3116 }
3117 }
3118 if (tries == 5)
3119 DRM_ERROR("FDI train 1 fail!\n");
3120
3121 /* Train 2 */
3122 reg = FDI_TX_CTL(pipe);
3123 temp = I915_READ(reg);
3124 temp &= ~FDI_LINK_TRAIN_NONE;
3125 temp |= FDI_LINK_TRAIN_PATTERN_2;
3126 I915_WRITE(reg, temp);
3127
3128 reg = FDI_RX_CTL(pipe);
3129 temp = I915_READ(reg);
3130 temp &= ~FDI_LINK_TRAIN_NONE;
3131 temp |= FDI_LINK_TRAIN_PATTERN_2;
3132 I915_WRITE(reg, temp);
3133
3134 POSTING_READ(reg);
3135 udelay(150);
3136
3137 reg = FDI_RX_IIR(pipe);
3138 for (tries = 0; tries < 5; tries++) {
3139 temp = I915_READ(reg);
3140 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3141
3142 if (temp & FDI_RX_SYMBOL_LOCK) {
3143 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3144 DRM_DEBUG_KMS("FDI train 2 done.\n");
3145 break;
3146 }
3147 }
3148 if (tries == 5)
3149 DRM_ERROR("FDI train 2 fail!\n");
3150
3151 DRM_DEBUG_KMS("FDI train done\n");
3152
3153 }
3154
3155 static const int snb_b_fdi_train_param[] = {
3156 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3157 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3158 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3159 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3160 };
3161
3162 /* The FDI link training functions for SNB/Cougarpoint. */
3163 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3164 {
3165 struct drm_device *dev = crtc->dev;
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168 int pipe = intel_crtc->pipe;
3169 u32 reg, temp, i, retry;
3170
3171 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3172 for train result */
3173 reg = FDI_RX_IMR(pipe);
3174 temp = I915_READ(reg);
3175 temp &= ~FDI_RX_SYMBOL_LOCK;
3176 temp &= ~FDI_RX_BIT_LOCK;
3177 I915_WRITE(reg, temp);
3178
3179 POSTING_READ(reg);
3180 udelay(150);
3181
3182 /* enable CPU FDI TX and PCH FDI RX */
3183 reg = FDI_TX_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3186 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3187 temp &= ~FDI_LINK_TRAIN_NONE;
3188 temp |= FDI_LINK_TRAIN_PATTERN_1;
3189 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3190 /* SNB-B */
3191 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3192 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3193
3194 I915_WRITE(FDI_RX_MISC(pipe),
3195 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3196
3197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 if (HAS_PCH_CPT(dev)) {
3200 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3201 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3202 } else {
3203 temp &= ~FDI_LINK_TRAIN_NONE;
3204 temp |= FDI_LINK_TRAIN_PATTERN_1;
3205 }
3206 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3207
3208 POSTING_READ(reg);
3209 udelay(150);
3210
3211 for (i = 0; i < 4; i++) {
3212 reg = FDI_TX_CTL(pipe);
3213 temp = I915_READ(reg);
3214 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3215 temp |= snb_b_fdi_train_param[i];
3216 I915_WRITE(reg, temp);
3217
3218 POSTING_READ(reg);
3219 udelay(500);
3220
3221 for (retry = 0; retry < 5; retry++) {
3222 reg = FDI_RX_IIR(pipe);
3223 temp = I915_READ(reg);
3224 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3225 if (temp & FDI_RX_BIT_LOCK) {
3226 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3227 DRM_DEBUG_KMS("FDI train 1 done.\n");
3228 break;
3229 }
3230 udelay(50);
3231 }
3232 if (retry < 5)
3233 break;
3234 }
3235 if (i == 4)
3236 DRM_ERROR("FDI train 1 fail!\n");
3237
3238 /* Train 2 */
3239 reg = FDI_TX_CTL(pipe);
3240 temp = I915_READ(reg);
3241 temp &= ~FDI_LINK_TRAIN_NONE;
3242 temp |= FDI_LINK_TRAIN_PATTERN_2;
3243 if (IS_GEN6(dev)) {
3244 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3245 /* SNB-B */
3246 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3247 }
3248 I915_WRITE(reg, temp);
3249
3250 reg = FDI_RX_CTL(pipe);
3251 temp = I915_READ(reg);
3252 if (HAS_PCH_CPT(dev)) {
3253 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3254 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3255 } else {
3256 temp &= ~FDI_LINK_TRAIN_NONE;
3257 temp |= FDI_LINK_TRAIN_PATTERN_2;
3258 }
3259 I915_WRITE(reg, temp);
3260
3261 POSTING_READ(reg);
3262 udelay(150);
3263
3264 for (i = 0; i < 4; i++) {
3265 reg = FDI_TX_CTL(pipe);
3266 temp = I915_READ(reg);
3267 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3268 temp |= snb_b_fdi_train_param[i];
3269 I915_WRITE(reg, temp);
3270
3271 POSTING_READ(reg);
3272 udelay(500);
3273
3274 for (retry = 0; retry < 5; retry++) {
3275 reg = FDI_RX_IIR(pipe);
3276 temp = I915_READ(reg);
3277 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3278 if (temp & FDI_RX_SYMBOL_LOCK) {
3279 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3280 DRM_DEBUG_KMS("FDI train 2 done.\n");
3281 break;
3282 }
3283 udelay(50);
3284 }
3285 if (retry < 5)
3286 break;
3287 }
3288 if (i == 4)
3289 DRM_ERROR("FDI train 2 fail!\n");
3290
3291 DRM_DEBUG_KMS("FDI train done.\n");
3292 }
3293
3294 /* Manual link training for Ivy Bridge A0 parts */
3295 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3296 {
3297 struct drm_device *dev = crtc->dev;
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3300 int pipe = intel_crtc->pipe;
3301 u32 reg, temp, i, j;
3302
3303 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3304 for train result */
3305 reg = FDI_RX_IMR(pipe);
3306 temp = I915_READ(reg);
3307 temp &= ~FDI_RX_SYMBOL_LOCK;
3308 temp &= ~FDI_RX_BIT_LOCK;
3309 I915_WRITE(reg, temp);
3310
3311 POSTING_READ(reg);
3312 udelay(150);
3313
3314 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3315 I915_READ(FDI_RX_IIR(pipe)));
3316
3317 /* Try each vswing and preemphasis setting twice before moving on */
3318 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3319 /* disable first in case we need to retry */
3320 reg = FDI_TX_CTL(pipe);
3321 temp = I915_READ(reg);
3322 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3323 temp &= ~FDI_TX_ENABLE;
3324 I915_WRITE(reg, temp);
3325
3326 reg = FDI_RX_CTL(pipe);
3327 temp = I915_READ(reg);
3328 temp &= ~FDI_LINK_TRAIN_AUTO;
3329 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3330 temp &= ~FDI_RX_ENABLE;
3331 I915_WRITE(reg, temp);
3332
3333 /* enable CPU FDI TX and PCH FDI RX */
3334 reg = FDI_TX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3337 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3338 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3340 temp |= snb_b_fdi_train_param[j/2];
3341 temp |= FDI_COMPOSITE_SYNC;
3342 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3343
3344 I915_WRITE(FDI_RX_MISC(pipe),
3345 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3346
3347 reg = FDI_RX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3350 temp |= FDI_COMPOSITE_SYNC;
3351 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3352
3353 POSTING_READ(reg);
3354 udelay(1); /* should be 0.5us */
3355
3356 for (i = 0; i < 4; i++) {
3357 reg = FDI_RX_IIR(pipe);
3358 temp = I915_READ(reg);
3359 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3360
3361 if (temp & FDI_RX_BIT_LOCK ||
3362 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3363 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3364 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3365 i);
3366 break;
3367 }
3368 udelay(1); /* should be 0.5us */
3369 }
3370 if (i == 4) {
3371 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3372 continue;
3373 }
3374
3375 /* Train 2 */
3376 reg = FDI_TX_CTL(pipe);
3377 temp = I915_READ(reg);
3378 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3379 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3380 I915_WRITE(reg, temp);
3381
3382 reg = FDI_RX_CTL(pipe);
3383 temp = I915_READ(reg);
3384 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3385 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3386 I915_WRITE(reg, temp);
3387
3388 POSTING_READ(reg);
3389 udelay(2); /* should be 1.5us */
3390
3391 for (i = 0; i < 4; i++) {
3392 reg = FDI_RX_IIR(pipe);
3393 temp = I915_READ(reg);
3394 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3395
3396 if (temp & FDI_RX_SYMBOL_LOCK ||
3397 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3398 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3399 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3400 i);
3401 goto train_done;
3402 }
3403 udelay(2); /* should be 1.5us */
3404 }
3405 if (i == 4)
3406 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3407 }
3408
3409 train_done:
3410 DRM_DEBUG_KMS("FDI train done.\n");
3411 }
3412
3413 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3414 {
3415 struct drm_device *dev = intel_crtc->base.dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 int pipe = intel_crtc->pipe;
3418 u32 reg, temp;
3419
3420
3421 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
3424 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3426 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3427 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3428
3429 POSTING_READ(reg);
3430 udelay(200);
3431
3432 /* Switch from Rawclk to PCDclk */
3433 temp = I915_READ(reg);
3434 I915_WRITE(reg, temp | FDI_PCDCLK);
3435
3436 POSTING_READ(reg);
3437 udelay(200);
3438
3439 /* Enable CPU FDI TX PLL, always on for Ironlake */
3440 reg = FDI_TX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3443 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3444
3445 POSTING_READ(reg);
3446 udelay(100);
3447 }
3448 }
3449
3450 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3451 {
3452 struct drm_device *dev = intel_crtc->base.dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 int pipe = intel_crtc->pipe;
3455 u32 reg, temp;
3456
3457 /* Switch from PCDclk to Rawclk */
3458 reg = FDI_RX_CTL(pipe);
3459 temp = I915_READ(reg);
3460 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3461
3462 /* Disable CPU FDI TX PLL */
3463 reg = FDI_TX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3466
3467 POSTING_READ(reg);
3468 udelay(100);
3469
3470 reg = FDI_RX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3473
3474 /* Wait for the clocks to turn off. */
3475 POSTING_READ(reg);
3476 udelay(100);
3477 }
3478
3479 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3480 {
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484 int pipe = intel_crtc->pipe;
3485 u32 reg, temp;
3486
3487 /* disable CPU FDI tx and PCH FDI rx */
3488 reg = FDI_TX_CTL(pipe);
3489 temp = I915_READ(reg);
3490 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3491 POSTING_READ(reg);
3492
3493 reg = FDI_RX_CTL(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~(0x7 << 16);
3496 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3497 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3498
3499 POSTING_READ(reg);
3500 udelay(100);
3501
3502 /* Ironlake workaround, disable clock pointer after downing FDI */
3503 if (HAS_PCH_IBX(dev))
3504 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3505
3506 /* still set train pattern 1 */
3507 reg = FDI_TX_CTL(pipe);
3508 temp = I915_READ(reg);
3509 temp &= ~FDI_LINK_TRAIN_NONE;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1;
3511 I915_WRITE(reg, temp);
3512
3513 reg = FDI_RX_CTL(pipe);
3514 temp = I915_READ(reg);
3515 if (HAS_PCH_CPT(dev)) {
3516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3518 } else {
3519 temp &= ~FDI_LINK_TRAIN_NONE;
3520 temp |= FDI_LINK_TRAIN_PATTERN_1;
3521 }
3522 /* BPC in FDI rx is consistent with that in PIPECONF */
3523 temp &= ~(0x07 << 16);
3524 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3525 I915_WRITE(reg, temp);
3526
3527 POSTING_READ(reg);
3528 udelay(100);
3529 }
3530
3531 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3532 {
3533 struct intel_crtc *crtc;
3534
3535 /* Note that we don't need to be called with mode_config.lock here
3536 * as our list of CRTC objects is static for the lifetime of the
3537 * device and so cannot disappear as we iterate. Similarly, we can
3538 * happily treat the predicates as racy, atomic checks as userspace
3539 * cannot claim and pin a new fb without at least acquring the
3540 * struct_mutex and so serialising with us.
3541 */
3542 for_each_intel_crtc(dev, crtc) {
3543 if (atomic_read(&crtc->unpin_work_count) == 0)
3544 continue;
3545
3546 if (crtc->unpin_work)
3547 intel_wait_for_vblank(dev, crtc->pipe);
3548
3549 return true;
3550 }
3551
3552 return false;
3553 }
3554
3555 static void page_flip_completed(struct intel_crtc *intel_crtc)
3556 {
3557 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3558 struct intel_unpin_work *work = intel_crtc->unpin_work;
3559
3560 /* ensure that the unpin work is consistent wrt ->pending. */
3561 smp_rmb();
3562 intel_crtc->unpin_work = NULL;
3563
3564 if (work->event)
3565 drm_send_vblank_event(intel_crtc->base.dev,
3566 intel_crtc->pipe,
3567 work->event);
3568
3569 drm_crtc_vblank_put(&intel_crtc->base);
3570
3571 wake_up_all(&dev_priv->pending_flip_queue);
3572 queue_work(dev_priv->wq, &work->work);
3573
3574 trace_i915_flip_complete(intel_crtc->plane,
3575 work->pending_flip_obj);
3576 }
3577
3578 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3579 {
3580 struct drm_device *dev = crtc->dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582
3583 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3584 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3585 !intel_crtc_has_pending_flip(crtc),
3586 60*HZ) == 0)) {
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588
3589 spin_lock_irq(&dev->event_lock);
3590 if (intel_crtc->unpin_work) {
3591 WARN_ONCE(1, "Removing stuck page flip\n");
3592 page_flip_completed(intel_crtc);
3593 }
3594 spin_unlock_irq(&dev->event_lock);
3595 }
3596
3597 if (crtc->primary->fb) {
3598 mutex_lock(&dev->struct_mutex);
3599 intel_finish_fb(crtc->primary->fb);
3600 mutex_unlock(&dev->struct_mutex);
3601 }
3602 }
3603
3604 /* Program iCLKIP clock to the desired frequency */
3605 static void lpt_program_iclkip(struct drm_crtc *crtc)
3606 {
3607 struct drm_device *dev = crtc->dev;
3608 struct drm_i915_private *dev_priv = dev->dev_private;
3609 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3610 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3611 u32 temp;
3612
3613 mutex_lock(&dev_priv->dpio_lock);
3614
3615 /* It is necessary to ungate the pixclk gate prior to programming
3616 * the divisors, and gate it back when it is done.
3617 */
3618 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3619
3620 /* Disable SSCCTL */
3621 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3622 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3623 SBI_SSCCTL_DISABLE,
3624 SBI_ICLK);
3625
3626 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3627 if (clock == 20000) {
3628 auxdiv = 1;
3629 divsel = 0x41;
3630 phaseinc = 0x20;
3631 } else {
3632 /* The iCLK virtual clock root frequency is in MHz,
3633 * but the adjusted_mode->crtc_clock in in KHz. To get the
3634 * divisors, it is necessary to divide one by another, so we
3635 * convert the virtual clock precision to KHz here for higher
3636 * precision.
3637 */
3638 u32 iclk_virtual_root_freq = 172800 * 1000;
3639 u32 iclk_pi_range = 64;
3640 u32 desired_divisor, msb_divisor_value, pi_value;
3641
3642 desired_divisor = (iclk_virtual_root_freq / clock);
3643 msb_divisor_value = desired_divisor / iclk_pi_range;
3644 pi_value = desired_divisor % iclk_pi_range;
3645
3646 auxdiv = 0;
3647 divsel = msb_divisor_value - 2;
3648 phaseinc = pi_value;
3649 }
3650
3651 /* This should not happen with any sane values */
3652 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3653 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3654 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3655 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3656
3657 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3658 clock,
3659 auxdiv,
3660 divsel,
3661 phasedir,
3662 phaseinc);
3663
3664 /* Program SSCDIVINTPHASE6 */
3665 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3666 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3667 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3668 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3669 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3670 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3671 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3672 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3673
3674 /* Program SSCAUXDIV */
3675 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3676 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3677 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3678 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3679
3680 /* Enable modulator and associated divider */
3681 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3682 temp &= ~SBI_SSCCTL_DISABLE;
3683 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3684
3685 /* Wait for initialization time */
3686 udelay(24);
3687
3688 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3689
3690 mutex_unlock(&dev_priv->dpio_lock);
3691 }
3692
3693 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3694 enum pipe pch_transcoder)
3695 {
3696 struct drm_device *dev = crtc->base.dev;
3697 struct drm_i915_private *dev_priv = dev->dev_private;
3698 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3699
3700 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3701 I915_READ(HTOTAL(cpu_transcoder)));
3702 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3703 I915_READ(HBLANK(cpu_transcoder)));
3704 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3705 I915_READ(HSYNC(cpu_transcoder)));
3706
3707 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3708 I915_READ(VTOTAL(cpu_transcoder)));
3709 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3710 I915_READ(VBLANK(cpu_transcoder)));
3711 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3712 I915_READ(VSYNC(cpu_transcoder)));
3713 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3714 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3715 }
3716
3717 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3718 {
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 uint32_t temp;
3721
3722 temp = I915_READ(SOUTH_CHICKEN1);
3723 if (temp & FDI_BC_BIFURCATION_SELECT)
3724 return;
3725
3726 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3727 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3728
3729 temp |= FDI_BC_BIFURCATION_SELECT;
3730 DRM_DEBUG_KMS("enabling fdi C rx\n");
3731 I915_WRITE(SOUTH_CHICKEN1, temp);
3732 POSTING_READ(SOUTH_CHICKEN1);
3733 }
3734
3735 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3736 {
3737 struct drm_device *dev = intel_crtc->base.dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739
3740 switch (intel_crtc->pipe) {
3741 case PIPE_A:
3742 break;
3743 case PIPE_B:
3744 if (intel_crtc->config->fdi_lanes > 2)
3745 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3746 else
3747 cpt_enable_fdi_bc_bifurcation(dev);
3748
3749 break;
3750 case PIPE_C:
3751 cpt_enable_fdi_bc_bifurcation(dev);
3752
3753 break;
3754 default:
3755 BUG();
3756 }
3757 }
3758
3759 /*
3760 * Enable PCH resources required for PCH ports:
3761 * - PCH PLLs
3762 * - FDI training & RX/TX
3763 * - update transcoder timings
3764 * - DP transcoding bits
3765 * - transcoder
3766 */
3767 static void ironlake_pch_enable(struct drm_crtc *crtc)
3768 {
3769 struct drm_device *dev = crtc->dev;
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3772 int pipe = intel_crtc->pipe;
3773 u32 reg, temp;
3774
3775 assert_pch_transcoder_disabled(dev_priv, pipe);
3776
3777 if (IS_IVYBRIDGE(dev))
3778 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3779
3780 /* Write the TU size bits before fdi link training, so that error
3781 * detection works. */
3782 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3783 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3784
3785 /* For PCH output, training FDI link */
3786 dev_priv->display.fdi_link_train(crtc);
3787
3788 /* We need to program the right clock selection before writing the pixel
3789 * mutliplier into the DPLL. */
3790 if (HAS_PCH_CPT(dev)) {
3791 u32 sel;
3792
3793 temp = I915_READ(PCH_DPLL_SEL);
3794 temp |= TRANS_DPLL_ENABLE(pipe);
3795 sel = TRANS_DPLLB_SEL(pipe);
3796 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3797 temp |= sel;
3798 else
3799 temp &= ~sel;
3800 I915_WRITE(PCH_DPLL_SEL, temp);
3801 }
3802
3803 /* XXX: pch pll's can be enabled any time before we enable the PCH
3804 * transcoder, and we actually should do this to not upset any PCH
3805 * transcoder that already use the clock when we share it.
3806 *
3807 * Note that enable_shared_dpll tries to do the right thing, but
3808 * get_shared_dpll unconditionally resets the pll - we need that to have
3809 * the right LVDS enable sequence. */
3810 intel_enable_shared_dpll(intel_crtc);
3811
3812 /* set transcoder timing, panel must allow it */
3813 assert_panel_unlocked(dev_priv, pipe);
3814 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3815
3816 intel_fdi_normal_train(crtc);
3817
3818 /* For PCH DP, enable TRANS_DP_CTL */
3819 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3820 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3821 reg = TRANS_DP_CTL(pipe);
3822 temp = I915_READ(reg);
3823 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3824 TRANS_DP_SYNC_MASK |
3825 TRANS_DP_BPC_MASK);
3826 temp |= (TRANS_DP_OUTPUT_ENABLE |
3827 TRANS_DP_ENH_FRAMING);
3828 temp |= bpc << 9; /* same format but at 11:9 */
3829
3830 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3831 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3832 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3833 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3834
3835 switch (intel_trans_dp_port_sel(crtc)) {
3836 case PCH_DP_B:
3837 temp |= TRANS_DP_PORT_SEL_B;
3838 break;
3839 case PCH_DP_C:
3840 temp |= TRANS_DP_PORT_SEL_C;
3841 break;
3842 case PCH_DP_D:
3843 temp |= TRANS_DP_PORT_SEL_D;
3844 break;
3845 default:
3846 BUG();
3847 }
3848
3849 I915_WRITE(reg, temp);
3850 }
3851
3852 ironlake_enable_pch_transcoder(dev_priv, pipe);
3853 }
3854
3855 static void lpt_pch_enable(struct drm_crtc *crtc)
3856 {
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3860 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3861
3862 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3863
3864 lpt_program_iclkip(crtc);
3865
3866 /* Set transcoder timing. */
3867 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3868
3869 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3870 }
3871
3872 void intel_put_shared_dpll(struct intel_crtc *crtc)
3873 {
3874 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3875
3876 if (pll == NULL)
3877 return;
3878
3879 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3880 WARN(1, "bad %s crtc mask\n", pll->name);
3881 return;
3882 }
3883
3884 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3885 if (pll->config.crtc_mask == 0) {
3886 WARN_ON(pll->on);
3887 WARN_ON(pll->active);
3888 }
3889
3890 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3891 }
3892
3893 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3894 struct intel_crtc_state *crtc_state)
3895 {
3896 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3897 struct intel_shared_dpll *pll;
3898 enum intel_dpll_id i;
3899
3900 if (HAS_PCH_IBX(dev_priv->dev)) {
3901 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3902 i = (enum intel_dpll_id) crtc->pipe;
3903 pll = &dev_priv->shared_dplls[i];
3904
3905 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3906 crtc->base.base.id, pll->name);
3907
3908 WARN_ON(pll->new_config->crtc_mask);
3909
3910 goto found;
3911 }
3912
3913 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3914 pll = &dev_priv->shared_dplls[i];
3915
3916 /* Only want to check enabled timings first */
3917 if (pll->new_config->crtc_mask == 0)
3918 continue;
3919
3920 if (memcmp(&crtc_state->dpll_hw_state,
3921 &pll->new_config->hw_state,
3922 sizeof(pll->new_config->hw_state)) == 0) {
3923 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3924 crtc->base.base.id, pll->name,
3925 pll->new_config->crtc_mask,
3926 pll->active);
3927 goto found;
3928 }
3929 }
3930
3931 /* Ok no matching timings, maybe there's a free one? */
3932 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3933 pll = &dev_priv->shared_dplls[i];
3934 if (pll->new_config->crtc_mask == 0) {
3935 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3936 crtc->base.base.id, pll->name);
3937 goto found;
3938 }
3939 }
3940
3941 return NULL;
3942
3943 found:
3944 if (pll->new_config->crtc_mask == 0)
3945 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3946
3947 crtc_state->shared_dpll = i;
3948 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3949 pipe_name(crtc->pipe));
3950
3951 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3952
3953 return pll;
3954 }
3955
3956 /**
3957 * intel_shared_dpll_start_config - start a new PLL staged config
3958 * @dev_priv: DRM device
3959 * @clear_pipes: mask of pipes that will have their PLLs freed
3960 *
3961 * Starts a new PLL staged config, copying the current config but
3962 * releasing the references of pipes specified in clear_pipes.
3963 */
3964 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3965 unsigned clear_pipes)
3966 {
3967 struct intel_shared_dpll *pll;
3968 enum intel_dpll_id i;
3969
3970 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3971 pll = &dev_priv->shared_dplls[i];
3972
3973 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3974 GFP_KERNEL);
3975 if (!pll->new_config)
3976 goto cleanup;
3977
3978 pll->new_config->crtc_mask &= ~clear_pipes;
3979 }
3980
3981 return 0;
3982
3983 cleanup:
3984 while (--i >= 0) {
3985 pll = &dev_priv->shared_dplls[i];
3986 kfree(pll->new_config);
3987 pll->new_config = NULL;
3988 }
3989
3990 return -ENOMEM;
3991 }
3992
3993 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3994 {
3995 struct intel_shared_dpll *pll;
3996 enum intel_dpll_id i;
3997
3998 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3999 pll = &dev_priv->shared_dplls[i];
4000
4001 WARN_ON(pll->new_config == &pll->config);
4002
4003 pll->config = *pll->new_config;
4004 kfree(pll->new_config);
4005 pll->new_config = NULL;
4006 }
4007 }
4008
4009 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4010 {
4011 struct intel_shared_dpll *pll;
4012 enum intel_dpll_id i;
4013
4014 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4015 pll = &dev_priv->shared_dplls[i];
4016
4017 WARN_ON(pll->new_config == &pll->config);
4018
4019 kfree(pll->new_config);
4020 pll->new_config = NULL;
4021 }
4022 }
4023
4024 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4025 {
4026 struct drm_i915_private *dev_priv = dev->dev_private;
4027 int dslreg = PIPEDSL(pipe);
4028 u32 temp;
4029
4030 temp = I915_READ(dslreg);
4031 udelay(500);
4032 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4033 if (wait_for(I915_READ(dslreg) != temp, 5))
4034 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4035 }
4036 }
4037
4038 static void skylake_pfit_enable(struct intel_crtc *crtc)
4039 {
4040 struct drm_device *dev = crtc->base.dev;
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042 int pipe = crtc->pipe;
4043
4044 if (crtc->config->pch_pfit.enabled) {
4045 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4046 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4047 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4048 }
4049 }
4050
4051 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4052 {
4053 struct drm_device *dev = crtc->base.dev;
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 int pipe = crtc->pipe;
4056
4057 if (crtc->config->pch_pfit.enabled) {
4058 /* Force use of hard-coded filter coefficients
4059 * as some pre-programmed values are broken,
4060 * e.g. x201.
4061 */
4062 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4063 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4064 PF_PIPE_SEL_IVB(pipe));
4065 else
4066 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4067 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4068 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4069 }
4070 }
4071
4072 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4073 {
4074 struct drm_device *dev = crtc->dev;
4075 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4076 struct drm_plane *plane;
4077 struct intel_plane *intel_plane;
4078
4079 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4080 intel_plane = to_intel_plane(plane);
4081 if (intel_plane->pipe == pipe)
4082 intel_plane_restore(&intel_plane->base);
4083 }
4084 }
4085
4086 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4087 {
4088 struct drm_device *dev = crtc->dev;
4089 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4090 struct drm_plane *plane;
4091 struct intel_plane *intel_plane;
4092
4093 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4094 intel_plane = to_intel_plane(plane);
4095 if (intel_plane->pipe == pipe)
4096 plane->funcs->disable_plane(plane);
4097 }
4098 }
4099
4100 void hsw_enable_ips(struct intel_crtc *crtc)
4101 {
4102 struct drm_device *dev = crtc->base.dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104
4105 if (!crtc->config->ips_enabled)
4106 return;
4107
4108 /* We can only enable IPS after we enable a plane and wait for a vblank */
4109 intel_wait_for_vblank(dev, crtc->pipe);
4110
4111 assert_plane_enabled(dev_priv, crtc->plane);
4112 if (IS_BROADWELL(dev)) {
4113 mutex_lock(&dev_priv->rps.hw_lock);
4114 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4115 mutex_unlock(&dev_priv->rps.hw_lock);
4116 /* Quoting Art Runyan: "its not safe to expect any particular
4117 * value in IPS_CTL bit 31 after enabling IPS through the
4118 * mailbox." Moreover, the mailbox may return a bogus state,
4119 * so we need to just enable it and continue on.
4120 */
4121 } else {
4122 I915_WRITE(IPS_CTL, IPS_ENABLE);
4123 /* The bit only becomes 1 in the next vblank, so this wait here
4124 * is essentially intel_wait_for_vblank. If we don't have this
4125 * and don't wait for vblanks until the end of crtc_enable, then
4126 * the HW state readout code will complain that the expected
4127 * IPS_CTL value is not the one we read. */
4128 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4129 DRM_ERROR("Timed out waiting for IPS enable\n");
4130 }
4131 }
4132
4133 void hsw_disable_ips(struct intel_crtc *crtc)
4134 {
4135 struct drm_device *dev = crtc->base.dev;
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137
4138 if (!crtc->config->ips_enabled)
4139 return;
4140
4141 assert_plane_enabled(dev_priv, crtc->plane);
4142 if (IS_BROADWELL(dev)) {
4143 mutex_lock(&dev_priv->rps.hw_lock);
4144 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4145 mutex_unlock(&dev_priv->rps.hw_lock);
4146 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4147 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4148 DRM_ERROR("Timed out waiting for IPS disable\n");
4149 } else {
4150 I915_WRITE(IPS_CTL, 0);
4151 POSTING_READ(IPS_CTL);
4152 }
4153
4154 /* We need to wait for a vblank before we can disable the plane. */
4155 intel_wait_for_vblank(dev, crtc->pipe);
4156 }
4157
4158 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4159 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4160 {
4161 struct drm_device *dev = crtc->dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4164 enum pipe pipe = intel_crtc->pipe;
4165 int palreg = PALETTE(pipe);
4166 int i;
4167 bool reenable_ips = false;
4168
4169 /* The clocks have to be on to load the palette. */
4170 if (!crtc->enabled || !intel_crtc->active)
4171 return;
4172
4173 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4174 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4175 assert_dsi_pll_enabled(dev_priv);
4176 else
4177 assert_pll_enabled(dev_priv, pipe);
4178 }
4179
4180 /* use legacy palette for Ironlake */
4181 if (!HAS_GMCH_DISPLAY(dev))
4182 palreg = LGC_PALETTE(pipe);
4183
4184 /* Workaround : Do not read or write the pipe palette/gamma data while
4185 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4186 */
4187 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4188 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4189 GAMMA_MODE_MODE_SPLIT)) {
4190 hsw_disable_ips(intel_crtc);
4191 reenable_ips = true;
4192 }
4193
4194 for (i = 0; i < 256; i++) {
4195 I915_WRITE(palreg + 4 * i,
4196 (intel_crtc->lut_r[i] << 16) |
4197 (intel_crtc->lut_g[i] << 8) |
4198 intel_crtc->lut_b[i]);
4199 }
4200
4201 if (reenable_ips)
4202 hsw_enable_ips(intel_crtc);
4203 }
4204
4205 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4206 {
4207 if (!enable && intel_crtc->overlay) {
4208 struct drm_device *dev = intel_crtc->base.dev;
4209 struct drm_i915_private *dev_priv = dev->dev_private;
4210
4211 mutex_lock(&dev->struct_mutex);
4212 dev_priv->mm.interruptible = false;
4213 (void) intel_overlay_switch_off(intel_crtc->overlay);
4214 dev_priv->mm.interruptible = true;
4215 mutex_unlock(&dev->struct_mutex);
4216 }
4217
4218 /* Let userspace switch the overlay on again. In most cases userspace
4219 * has to recompute where to put it anyway.
4220 */
4221 }
4222
4223 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4224 {
4225 struct drm_device *dev = crtc->dev;
4226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4227 int pipe = intel_crtc->pipe;
4228
4229 intel_enable_primary_hw_plane(crtc->primary, crtc);
4230 intel_enable_sprite_planes(crtc);
4231 intel_crtc_update_cursor(crtc, true);
4232 intel_crtc_dpms_overlay(intel_crtc, true);
4233
4234 hsw_enable_ips(intel_crtc);
4235
4236 mutex_lock(&dev->struct_mutex);
4237 intel_fbc_update(dev);
4238 mutex_unlock(&dev->struct_mutex);
4239
4240 /*
4241 * FIXME: Once we grow proper nuclear flip support out of this we need
4242 * to compute the mask of flip planes precisely. For the time being
4243 * consider this a flip from a NULL plane.
4244 */
4245 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4246 }
4247
4248 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4249 {
4250 struct drm_device *dev = crtc->dev;
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253 int pipe = intel_crtc->pipe;
4254 int plane = intel_crtc->plane;
4255
4256 intel_crtc_wait_for_pending_flips(crtc);
4257
4258 if (dev_priv->fbc.plane == plane)
4259 intel_fbc_disable(dev);
4260
4261 hsw_disable_ips(intel_crtc);
4262
4263 intel_crtc_dpms_overlay(intel_crtc, false);
4264 intel_crtc_update_cursor(crtc, false);
4265 intel_disable_sprite_planes(crtc);
4266 intel_disable_primary_hw_plane(crtc->primary, crtc);
4267
4268 /*
4269 * FIXME: Once we grow proper nuclear flip support out of this we need
4270 * to compute the mask of flip planes precisely. For the time being
4271 * consider this a flip to a NULL plane.
4272 */
4273 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4274 }
4275
4276 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4277 {
4278 struct drm_device *dev = crtc->dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4281 struct intel_encoder *encoder;
4282 int pipe = intel_crtc->pipe;
4283
4284 WARN_ON(!crtc->enabled);
4285
4286 if (intel_crtc->active)
4287 return;
4288
4289 if (intel_crtc->config->has_pch_encoder)
4290 intel_prepare_shared_dpll(intel_crtc);
4291
4292 if (intel_crtc->config->has_dp_encoder)
4293 intel_dp_set_m_n(intel_crtc);
4294
4295 intel_set_pipe_timings(intel_crtc);
4296
4297 if (intel_crtc->config->has_pch_encoder) {
4298 intel_cpu_transcoder_set_m_n(intel_crtc,
4299 &intel_crtc->config->fdi_m_n, NULL);
4300 }
4301
4302 ironlake_set_pipeconf(crtc);
4303
4304 intel_crtc->active = true;
4305
4306 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4307 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4308
4309 for_each_encoder_on_crtc(dev, crtc, encoder)
4310 if (encoder->pre_enable)
4311 encoder->pre_enable(encoder);
4312
4313 if (intel_crtc->config->has_pch_encoder) {
4314 /* Note: FDI PLL enabling _must_ be done before we enable the
4315 * cpu pipes, hence this is separate from all the other fdi/pch
4316 * enabling. */
4317 ironlake_fdi_pll_enable(intel_crtc);
4318 } else {
4319 assert_fdi_tx_disabled(dev_priv, pipe);
4320 assert_fdi_rx_disabled(dev_priv, pipe);
4321 }
4322
4323 ironlake_pfit_enable(intel_crtc);
4324
4325 /*
4326 * On ILK+ LUT must be loaded before the pipe is running but with
4327 * clocks enabled
4328 */
4329 intel_crtc_load_lut(crtc);
4330
4331 intel_update_watermarks(crtc);
4332 intel_enable_pipe(intel_crtc);
4333
4334 if (intel_crtc->config->has_pch_encoder)
4335 ironlake_pch_enable(crtc);
4336
4337 assert_vblank_disabled(crtc);
4338 drm_crtc_vblank_on(crtc);
4339
4340 for_each_encoder_on_crtc(dev, crtc, encoder)
4341 encoder->enable(encoder);
4342
4343 if (HAS_PCH_CPT(dev))
4344 cpt_verify_modeset(dev, intel_crtc->pipe);
4345
4346 intel_crtc_enable_planes(crtc);
4347 }
4348
4349 /* IPS only exists on ULT machines and is tied to pipe A. */
4350 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4351 {
4352 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4353 }
4354
4355 /*
4356 * This implements the workaround described in the "notes" section of the mode
4357 * set sequence documentation. When going from no pipes or single pipe to
4358 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4359 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4360 */
4361 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4362 {
4363 struct drm_device *dev = crtc->base.dev;
4364 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4365
4366 /* We want to get the other_active_crtc only if there's only 1 other
4367 * active crtc. */
4368 for_each_intel_crtc(dev, crtc_it) {
4369 if (!crtc_it->active || crtc_it == crtc)
4370 continue;
4371
4372 if (other_active_crtc)
4373 return;
4374
4375 other_active_crtc = crtc_it;
4376 }
4377 if (!other_active_crtc)
4378 return;
4379
4380 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4381 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4382 }
4383
4384 static void haswell_crtc_enable(struct drm_crtc *crtc)
4385 {
4386 struct drm_device *dev = crtc->dev;
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4389 struct intel_encoder *encoder;
4390 int pipe = intel_crtc->pipe;
4391
4392 WARN_ON(!crtc->enabled);
4393
4394 if (intel_crtc->active)
4395 return;
4396
4397 if (intel_crtc_to_shared_dpll(intel_crtc))
4398 intel_enable_shared_dpll(intel_crtc);
4399
4400 if (intel_crtc->config->has_dp_encoder)
4401 intel_dp_set_m_n(intel_crtc);
4402
4403 intel_set_pipe_timings(intel_crtc);
4404
4405 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4406 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4407 intel_crtc->config->pixel_multiplier - 1);
4408 }
4409
4410 if (intel_crtc->config->has_pch_encoder) {
4411 intel_cpu_transcoder_set_m_n(intel_crtc,
4412 &intel_crtc->config->fdi_m_n, NULL);
4413 }
4414
4415 haswell_set_pipeconf(crtc);
4416
4417 intel_set_pipe_csc(crtc);
4418
4419 intel_crtc->active = true;
4420
4421 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4422 for_each_encoder_on_crtc(dev, crtc, encoder)
4423 if (encoder->pre_enable)
4424 encoder->pre_enable(encoder);
4425
4426 if (intel_crtc->config->has_pch_encoder) {
4427 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4428 true);
4429 dev_priv->display.fdi_link_train(crtc);
4430 }
4431
4432 intel_ddi_enable_pipe_clock(intel_crtc);
4433
4434 if (IS_SKYLAKE(dev))
4435 skylake_pfit_enable(intel_crtc);
4436 else
4437 ironlake_pfit_enable(intel_crtc);
4438
4439 /*
4440 * On ILK+ LUT must be loaded before the pipe is running but with
4441 * clocks enabled
4442 */
4443 intel_crtc_load_lut(crtc);
4444
4445 intel_ddi_set_pipe_settings(crtc);
4446 intel_ddi_enable_transcoder_func(crtc);
4447
4448 intel_update_watermarks(crtc);
4449 intel_enable_pipe(intel_crtc);
4450
4451 if (intel_crtc->config->has_pch_encoder)
4452 lpt_pch_enable(crtc);
4453
4454 if (intel_crtc->config->dp_encoder_is_mst)
4455 intel_ddi_set_vc_payload_alloc(crtc, true);
4456
4457 assert_vblank_disabled(crtc);
4458 drm_crtc_vblank_on(crtc);
4459
4460 for_each_encoder_on_crtc(dev, crtc, encoder) {
4461 encoder->enable(encoder);
4462 intel_opregion_notify_encoder(encoder, true);
4463 }
4464
4465 /* If we change the relative order between pipe/planes enabling, we need
4466 * to change the workaround. */
4467 haswell_mode_set_planes_workaround(intel_crtc);
4468 intel_crtc_enable_planes(crtc);
4469 }
4470
4471 static void skylake_pfit_disable(struct intel_crtc *crtc)
4472 {
4473 struct drm_device *dev = crtc->base.dev;
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475 int pipe = crtc->pipe;
4476
4477 /* To avoid upsetting the power well on haswell only disable the pfit if
4478 * it's in use. The hw state code will make sure we get this right. */
4479 if (crtc->config->pch_pfit.enabled) {
4480 I915_WRITE(PS_CTL(pipe), 0);
4481 I915_WRITE(PS_WIN_POS(pipe), 0);
4482 I915_WRITE(PS_WIN_SZ(pipe), 0);
4483 }
4484 }
4485
4486 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4487 {
4488 struct drm_device *dev = crtc->base.dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 int pipe = crtc->pipe;
4491
4492 /* To avoid upsetting the power well on haswell only disable the pfit if
4493 * it's in use. The hw state code will make sure we get this right. */
4494 if (crtc->config->pch_pfit.enabled) {
4495 I915_WRITE(PF_CTL(pipe), 0);
4496 I915_WRITE(PF_WIN_POS(pipe), 0);
4497 I915_WRITE(PF_WIN_SZ(pipe), 0);
4498 }
4499 }
4500
4501 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4502 {
4503 struct drm_device *dev = crtc->dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4506 struct intel_encoder *encoder;
4507 int pipe = intel_crtc->pipe;
4508 u32 reg, temp;
4509
4510 if (!intel_crtc->active)
4511 return;
4512
4513 intel_crtc_disable_planes(crtc);
4514
4515 for_each_encoder_on_crtc(dev, crtc, encoder)
4516 encoder->disable(encoder);
4517
4518 drm_crtc_vblank_off(crtc);
4519 assert_vblank_disabled(crtc);
4520
4521 if (intel_crtc->config->has_pch_encoder)
4522 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4523
4524 intel_disable_pipe(intel_crtc);
4525
4526 ironlake_pfit_disable(intel_crtc);
4527
4528 for_each_encoder_on_crtc(dev, crtc, encoder)
4529 if (encoder->post_disable)
4530 encoder->post_disable(encoder);
4531
4532 if (intel_crtc->config->has_pch_encoder) {
4533 ironlake_fdi_disable(crtc);
4534
4535 ironlake_disable_pch_transcoder(dev_priv, pipe);
4536
4537 if (HAS_PCH_CPT(dev)) {
4538 /* disable TRANS_DP_CTL */
4539 reg = TRANS_DP_CTL(pipe);
4540 temp = I915_READ(reg);
4541 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4542 TRANS_DP_PORT_SEL_MASK);
4543 temp |= TRANS_DP_PORT_SEL_NONE;
4544 I915_WRITE(reg, temp);
4545
4546 /* disable DPLL_SEL */
4547 temp = I915_READ(PCH_DPLL_SEL);
4548 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4549 I915_WRITE(PCH_DPLL_SEL, temp);
4550 }
4551
4552 /* disable PCH DPLL */
4553 intel_disable_shared_dpll(intel_crtc);
4554
4555 ironlake_fdi_pll_disable(intel_crtc);
4556 }
4557
4558 intel_crtc->active = false;
4559 intel_update_watermarks(crtc);
4560
4561 mutex_lock(&dev->struct_mutex);
4562 intel_fbc_update(dev);
4563 mutex_unlock(&dev->struct_mutex);
4564 }
4565
4566 static void haswell_crtc_disable(struct drm_crtc *crtc)
4567 {
4568 struct drm_device *dev = crtc->dev;
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4571 struct intel_encoder *encoder;
4572 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4573
4574 if (!intel_crtc->active)
4575 return;
4576
4577 intel_crtc_disable_planes(crtc);
4578
4579 for_each_encoder_on_crtc(dev, crtc, encoder) {
4580 intel_opregion_notify_encoder(encoder, false);
4581 encoder->disable(encoder);
4582 }
4583
4584 drm_crtc_vblank_off(crtc);
4585 assert_vblank_disabled(crtc);
4586
4587 if (intel_crtc->config->has_pch_encoder)
4588 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4589 false);
4590 intel_disable_pipe(intel_crtc);
4591
4592 if (intel_crtc->config->dp_encoder_is_mst)
4593 intel_ddi_set_vc_payload_alloc(crtc, false);
4594
4595 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4596
4597 if (IS_SKYLAKE(dev))
4598 skylake_pfit_disable(intel_crtc);
4599 else
4600 ironlake_pfit_disable(intel_crtc);
4601
4602 intel_ddi_disable_pipe_clock(intel_crtc);
4603
4604 if (intel_crtc->config->has_pch_encoder) {
4605 lpt_disable_pch_transcoder(dev_priv);
4606 intel_ddi_fdi_disable(crtc);
4607 }
4608
4609 for_each_encoder_on_crtc(dev, crtc, encoder)
4610 if (encoder->post_disable)
4611 encoder->post_disable(encoder);
4612
4613 intel_crtc->active = false;
4614 intel_update_watermarks(crtc);
4615
4616 mutex_lock(&dev->struct_mutex);
4617 intel_fbc_update(dev);
4618 mutex_unlock(&dev->struct_mutex);
4619
4620 if (intel_crtc_to_shared_dpll(intel_crtc))
4621 intel_disable_shared_dpll(intel_crtc);
4622 }
4623
4624 static void ironlake_crtc_off(struct drm_crtc *crtc)
4625 {
4626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4627 intel_put_shared_dpll(intel_crtc);
4628 }
4629
4630
4631 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4632 {
4633 struct drm_device *dev = crtc->base.dev;
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 struct intel_crtc_state *pipe_config = crtc->config;
4636
4637 if (!pipe_config->gmch_pfit.control)
4638 return;
4639
4640 /*
4641 * The panel fitter should only be adjusted whilst the pipe is disabled,
4642 * according to register description and PRM.
4643 */
4644 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4645 assert_pipe_disabled(dev_priv, crtc->pipe);
4646
4647 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4648 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4649
4650 /* Border color in case we don't scale up to the full screen. Black by
4651 * default, change to something else for debugging. */
4652 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4653 }
4654
4655 static enum intel_display_power_domain port_to_power_domain(enum port port)
4656 {
4657 switch (port) {
4658 case PORT_A:
4659 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4660 case PORT_B:
4661 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4662 case PORT_C:
4663 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4664 case PORT_D:
4665 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4666 default:
4667 WARN_ON_ONCE(1);
4668 return POWER_DOMAIN_PORT_OTHER;
4669 }
4670 }
4671
4672 #define for_each_power_domain(domain, mask) \
4673 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4674 if ((1 << (domain)) & (mask))
4675
4676 enum intel_display_power_domain
4677 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4678 {
4679 struct drm_device *dev = intel_encoder->base.dev;
4680 struct intel_digital_port *intel_dig_port;
4681
4682 switch (intel_encoder->type) {
4683 case INTEL_OUTPUT_UNKNOWN:
4684 /* Only DDI platforms should ever use this output type */
4685 WARN_ON_ONCE(!HAS_DDI(dev));
4686 case INTEL_OUTPUT_DISPLAYPORT:
4687 case INTEL_OUTPUT_HDMI:
4688 case INTEL_OUTPUT_EDP:
4689 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4690 return port_to_power_domain(intel_dig_port->port);
4691 case INTEL_OUTPUT_DP_MST:
4692 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4693 return port_to_power_domain(intel_dig_port->port);
4694 case INTEL_OUTPUT_ANALOG:
4695 return POWER_DOMAIN_PORT_CRT;
4696 case INTEL_OUTPUT_DSI:
4697 return POWER_DOMAIN_PORT_DSI;
4698 default:
4699 return POWER_DOMAIN_PORT_OTHER;
4700 }
4701 }
4702
4703 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4704 {
4705 struct drm_device *dev = crtc->dev;
4706 struct intel_encoder *intel_encoder;
4707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4708 enum pipe pipe = intel_crtc->pipe;
4709 unsigned long mask;
4710 enum transcoder transcoder;
4711
4712 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4713
4714 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4715 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4716 if (intel_crtc->config->pch_pfit.enabled ||
4717 intel_crtc->config->pch_pfit.force_thru)
4718 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4719
4720 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4721 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4722
4723 return mask;
4724 }
4725
4726 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4727 {
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4730 struct intel_crtc *crtc;
4731
4732 /*
4733 * First get all needed power domains, then put all unneeded, to avoid
4734 * any unnecessary toggling of the power wells.
4735 */
4736 for_each_intel_crtc(dev, crtc) {
4737 enum intel_display_power_domain domain;
4738
4739 if (!crtc->base.enabled)
4740 continue;
4741
4742 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4743
4744 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4745 intel_display_power_get(dev_priv, domain);
4746 }
4747
4748 if (dev_priv->display.modeset_global_resources)
4749 dev_priv->display.modeset_global_resources(dev);
4750
4751 for_each_intel_crtc(dev, crtc) {
4752 enum intel_display_power_domain domain;
4753
4754 for_each_power_domain(domain, crtc->enabled_power_domains)
4755 intel_display_power_put(dev_priv, domain);
4756
4757 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4758 }
4759
4760 intel_display_set_init_power(dev_priv, false);
4761 }
4762
4763 /* returns HPLL frequency in kHz */
4764 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4765 {
4766 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4767
4768 /* Obtain SKU information */
4769 mutex_lock(&dev_priv->dpio_lock);
4770 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4771 CCK_FUSE_HPLL_FREQ_MASK;
4772 mutex_unlock(&dev_priv->dpio_lock);
4773
4774 return vco_freq[hpll_freq] * 1000;
4775 }
4776
4777 static void vlv_update_cdclk(struct drm_device *dev)
4778 {
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4780
4781 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4782 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4783 dev_priv->vlv_cdclk_freq);
4784
4785 /*
4786 * Program the gmbus_freq based on the cdclk frequency.
4787 * BSpec erroneously claims we should aim for 4MHz, but
4788 * in fact 1MHz is the correct frequency.
4789 */
4790 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4791 }
4792
4793 /* Adjust CDclk dividers to allow high res or save power if possible */
4794 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4795 {
4796 struct drm_i915_private *dev_priv = dev->dev_private;
4797 u32 val, cmd;
4798
4799 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4800
4801 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4802 cmd = 2;
4803 else if (cdclk == 266667)
4804 cmd = 1;
4805 else
4806 cmd = 0;
4807
4808 mutex_lock(&dev_priv->rps.hw_lock);
4809 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4810 val &= ~DSPFREQGUAR_MASK;
4811 val |= (cmd << DSPFREQGUAR_SHIFT);
4812 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4813 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4814 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4815 50)) {
4816 DRM_ERROR("timed out waiting for CDclk change\n");
4817 }
4818 mutex_unlock(&dev_priv->rps.hw_lock);
4819
4820 if (cdclk == 400000) {
4821 u32 divider;
4822
4823 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4824
4825 mutex_lock(&dev_priv->dpio_lock);
4826 /* adjust cdclk divider */
4827 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4828 val &= ~DISPLAY_FREQUENCY_VALUES;
4829 val |= divider;
4830 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4831
4832 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4833 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4834 50))
4835 DRM_ERROR("timed out waiting for CDclk change\n");
4836 mutex_unlock(&dev_priv->dpio_lock);
4837 }
4838
4839 mutex_lock(&dev_priv->dpio_lock);
4840 /* adjust self-refresh exit latency value */
4841 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4842 val &= ~0x7f;
4843
4844 /*
4845 * For high bandwidth configs, we set a higher latency in the bunit
4846 * so that the core display fetch happens in time to avoid underruns.
4847 */
4848 if (cdclk == 400000)
4849 val |= 4500 / 250; /* 4.5 usec */
4850 else
4851 val |= 3000 / 250; /* 3.0 usec */
4852 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4853 mutex_unlock(&dev_priv->dpio_lock);
4854
4855 vlv_update_cdclk(dev);
4856 }
4857
4858 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4859 {
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 u32 val, cmd;
4862
4863 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4864
4865 switch (cdclk) {
4866 case 400000:
4867 cmd = 3;
4868 break;
4869 case 333333:
4870 case 320000:
4871 cmd = 2;
4872 break;
4873 case 266667:
4874 cmd = 1;
4875 break;
4876 case 200000:
4877 cmd = 0;
4878 break;
4879 default:
4880 MISSING_CASE(cdclk);
4881 return;
4882 }
4883
4884 mutex_lock(&dev_priv->rps.hw_lock);
4885 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4886 val &= ~DSPFREQGUAR_MASK_CHV;
4887 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4888 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4889 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4890 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4891 50)) {
4892 DRM_ERROR("timed out waiting for CDclk change\n");
4893 }
4894 mutex_unlock(&dev_priv->rps.hw_lock);
4895
4896 vlv_update_cdclk(dev);
4897 }
4898
4899 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4900 int max_pixclk)
4901 {
4902 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4903
4904 /* FIXME: Punit isn't quite ready yet */
4905 if (IS_CHERRYVIEW(dev_priv->dev))
4906 return 400000;
4907
4908 /*
4909 * Really only a few cases to deal with, as only 4 CDclks are supported:
4910 * 200MHz
4911 * 267MHz
4912 * 320/333MHz (depends on HPLL freq)
4913 * 400MHz
4914 * So we check to see whether we're above 90% of the lower bin and
4915 * adjust if needed.
4916 *
4917 * We seem to get an unstable or solid color picture at 200MHz.
4918 * Not sure what's wrong. For now use 200MHz only when all pipes
4919 * are off.
4920 */
4921 if (max_pixclk > freq_320*9/10)
4922 return 400000;
4923 else if (max_pixclk > 266667*9/10)
4924 return freq_320;
4925 else if (max_pixclk > 0)
4926 return 266667;
4927 else
4928 return 200000;
4929 }
4930
4931 /* compute the max pixel clock for new configuration */
4932 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4933 {
4934 struct drm_device *dev = dev_priv->dev;
4935 struct intel_crtc *intel_crtc;
4936 int max_pixclk = 0;
4937
4938 for_each_intel_crtc(dev, intel_crtc) {
4939 if (intel_crtc->new_enabled)
4940 max_pixclk = max(max_pixclk,
4941 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4942 }
4943
4944 return max_pixclk;
4945 }
4946
4947 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4948 unsigned *prepare_pipes)
4949 {
4950 struct drm_i915_private *dev_priv = dev->dev_private;
4951 struct intel_crtc *intel_crtc;
4952 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4953
4954 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4955 dev_priv->vlv_cdclk_freq)
4956 return;
4957
4958 /* disable/enable all currently active pipes while we change cdclk */
4959 for_each_intel_crtc(dev, intel_crtc)
4960 if (intel_crtc->base.enabled)
4961 *prepare_pipes |= (1 << intel_crtc->pipe);
4962 }
4963
4964 static void valleyview_modeset_global_resources(struct drm_device *dev)
4965 {
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4968 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4969
4970 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4971 /*
4972 * FIXME: We can end up here with all power domains off, yet
4973 * with a CDCLK frequency other than the minimum. To account
4974 * for this take the PIPE-A power domain, which covers the HW
4975 * blocks needed for the following programming. This can be
4976 * removed once it's guaranteed that we get here either with
4977 * the minimum CDCLK set, or the required power domains
4978 * enabled.
4979 */
4980 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4981
4982 if (IS_CHERRYVIEW(dev))
4983 cherryview_set_cdclk(dev, req_cdclk);
4984 else
4985 valleyview_set_cdclk(dev, req_cdclk);
4986
4987 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4988 }
4989 }
4990
4991 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4992 {
4993 struct drm_device *dev = crtc->dev;
4994 struct drm_i915_private *dev_priv = to_i915(dev);
4995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4996 struct intel_encoder *encoder;
4997 int pipe = intel_crtc->pipe;
4998 bool is_dsi;
4999
5000 WARN_ON(!crtc->enabled);
5001
5002 if (intel_crtc->active)
5003 return;
5004
5005 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5006
5007 if (!is_dsi) {
5008 if (IS_CHERRYVIEW(dev))
5009 chv_prepare_pll(intel_crtc, intel_crtc->config);
5010 else
5011 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5012 }
5013
5014 if (intel_crtc->config->has_dp_encoder)
5015 intel_dp_set_m_n(intel_crtc);
5016
5017 intel_set_pipe_timings(intel_crtc);
5018
5019 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5020 struct drm_i915_private *dev_priv = dev->dev_private;
5021
5022 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5023 I915_WRITE(CHV_CANVAS(pipe), 0);
5024 }
5025
5026 i9xx_set_pipeconf(intel_crtc);
5027
5028 intel_crtc->active = true;
5029
5030 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5031
5032 for_each_encoder_on_crtc(dev, crtc, encoder)
5033 if (encoder->pre_pll_enable)
5034 encoder->pre_pll_enable(encoder);
5035
5036 if (!is_dsi) {
5037 if (IS_CHERRYVIEW(dev))
5038 chv_enable_pll(intel_crtc, intel_crtc->config);
5039 else
5040 vlv_enable_pll(intel_crtc, intel_crtc->config);
5041 }
5042
5043 for_each_encoder_on_crtc(dev, crtc, encoder)
5044 if (encoder->pre_enable)
5045 encoder->pre_enable(encoder);
5046
5047 i9xx_pfit_enable(intel_crtc);
5048
5049 intel_crtc_load_lut(crtc);
5050
5051 intel_update_watermarks(crtc);
5052 intel_enable_pipe(intel_crtc);
5053
5054 assert_vblank_disabled(crtc);
5055 drm_crtc_vblank_on(crtc);
5056
5057 for_each_encoder_on_crtc(dev, crtc, encoder)
5058 encoder->enable(encoder);
5059
5060 intel_crtc_enable_planes(crtc);
5061
5062 /* Underruns don't raise interrupts, so check manually. */
5063 i9xx_check_fifo_underruns(dev_priv);
5064 }
5065
5066 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5067 {
5068 struct drm_device *dev = crtc->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070
5071 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5072 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5073 }
5074
5075 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5076 {
5077 struct drm_device *dev = crtc->dev;
5078 struct drm_i915_private *dev_priv = to_i915(dev);
5079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5080 struct intel_encoder *encoder;
5081 int pipe = intel_crtc->pipe;
5082
5083 WARN_ON(!crtc->enabled);
5084
5085 if (intel_crtc->active)
5086 return;
5087
5088 i9xx_set_pll_dividers(intel_crtc);
5089
5090 if (intel_crtc->config->has_dp_encoder)
5091 intel_dp_set_m_n(intel_crtc);
5092
5093 intel_set_pipe_timings(intel_crtc);
5094
5095 i9xx_set_pipeconf(intel_crtc);
5096
5097 intel_crtc->active = true;
5098
5099 if (!IS_GEN2(dev))
5100 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5101
5102 for_each_encoder_on_crtc(dev, crtc, encoder)
5103 if (encoder->pre_enable)
5104 encoder->pre_enable(encoder);
5105
5106 i9xx_enable_pll(intel_crtc);
5107
5108 i9xx_pfit_enable(intel_crtc);
5109
5110 intel_crtc_load_lut(crtc);
5111
5112 intel_update_watermarks(crtc);
5113 intel_enable_pipe(intel_crtc);
5114
5115 assert_vblank_disabled(crtc);
5116 drm_crtc_vblank_on(crtc);
5117
5118 for_each_encoder_on_crtc(dev, crtc, encoder)
5119 encoder->enable(encoder);
5120
5121 intel_crtc_enable_planes(crtc);
5122
5123 /*
5124 * Gen2 reports pipe underruns whenever all planes are disabled.
5125 * So don't enable underrun reporting before at least some planes
5126 * are enabled.
5127 * FIXME: Need to fix the logic to work when we turn off all planes
5128 * but leave the pipe running.
5129 */
5130 if (IS_GEN2(dev))
5131 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5132
5133 /* Underruns don't raise interrupts, so check manually. */
5134 i9xx_check_fifo_underruns(dev_priv);
5135 }
5136
5137 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5138 {
5139 struct drm_device *dev = crtc->base.dev;
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141
5142 if (!crtc->config->gmch_pfit.control)
5143 return;
5144
5145 assert_pipe_disabled(dev_priv, crtc->pipe);
5146
5147 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5148 I915_READ(PFIT_CONTROL));
5149 I915_WRITE(PFIT_CONTROL, 0);
5150 }
5151
5152 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5153 {
5154 struct drm_device *dev = crtc->dev;
5155 struct drm_i915_private *dev_priv = dev->dev_private;
5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5157 struct intel_encoder *encoder;
5158 int pipe = intel_crtc->pipe;
5159
5160 if (!intel_crtc->active)
5161 return;
5162
5163 /*
5164 * Gen2 reports pipe underruns whenever all planes are disabled.
5165 * So diasble underrun reporting before all the planes get disabled.
5166 * FIXME: Need to fix the logic to work when we turn off all planes
5167 * but leave the pipe running.
5168 */
5169 if (IS_GEN2(dev))
5170 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5171
5172 /*
5173 * Vblank time updates from the shadow to live plane control register
5174 * are blocked if the memory self-refresh mode is active at that
5175 * moment. So to make sure the plane gets truly disabled, disable
5176 * first the self-refresh mode. The self-refresh enable bit in turn
5177 * will be checked/applied by the HW only at the next frame start
5178 * event which is after the vblank start event, so we need to have a
5179 * wait-for-vblank between disabling the plane and the pipe.
5180 */
5181 intel_set_memory_cxsr(dev_priv, false);
5182 intel_crtc_disable_planes(crtc);
5183
5184 /*
5185 * On gen2 planes are double buffered but the pipe isn't, so we must
5186 * wait for planes to fully turn off before disabling the pipe.
5187 * We also need to wait on all gmch platforms because of the
5188 * self-refresh mode constraint explained above.
5189 */
5190 intel_wait_for_vblank(dev, pipe);
5191
5192 for_each_encoder_on_crtc(dev, crtc, encoder)
5193 encoder->disable(encoder);
5194
5195 drm_crtc_vblank_off(crtc);
5196 assert_vblank_disabled(crtc);
5197
5198 intel_disable_pipe(intel_crtc);
5199
5200 i9xx_pfit_disable(intel_crtc);
5201
5202 for_each_encoder_on_crtc(dev, crtc, encoder)
5203 if (encoder->post_disable)
5204 encoder->post_disable(encoder);
5205
5206 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5207 if (IS_CHERRYVIEW(dev))
5208 chv_disable_pll(dev_priv, pipe);
5209 else if (IS_VALLEYVIEW(dev))
5210 vlv_disable_pll(dev_priv, pipe);
5211 else
5212 i9xx_disable_pll(intel_crtc);
5213 }
5214
5215 if (!IS_GEN2(dev))
5216 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5217
5218 intel_crtc->active = false;
5219 intel_update_watermarks(crtc);
5220
5221 mutex_lock(&dev->struct_mutex);
5222 intel_fbc_update(dev);
5223 mutex_unlock(&dev->struct_mutex);
5224 }
5225
5226 static void i9xx_crtc_off(struct drm_crtc *crtc)
5227 {
5228 }
5229
5230 /* Master function to enable/disable CRTC and corresponding power wells */
5231 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5232 {
5233 struct drm_device *dev = crtc->dev;
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236 enum intel_display_power_domain domain;
5237 unsigned long domains;
5238
5239 if (enable) {
5240 if (!intel_crtc->active) {
5241 domains = get_crtc_power_domains(crtc);
5242 for_each_power_domain(domain, domains)
5243 intel_display_power_get(dev_priv, domain);
5244 intel_crtc->enabled_power_domains = domains;
5245
5246 dev_priv->display.crtc_enable(crtc);
5247 }
5248 } else {
5249 if (intel_crtc->active) {
5250 dev_priv->display.crtc_disable(crtc);
5251
5252 domains = intel_crtc->enabled_power_domains;
5253 for_each_power_domain(domain, domains)
5254 intel_display_power_put(dev_priv, domain);
5255 intel_crtc->enabled_power_domains = 0;
5256 }
5257 }
5258 }
5259
5260 /**
5261 * Sets the power management mode of the pipe and plane.
5262 */
5263 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5264 {
5265 struct drm_device *dev = crtc->dev;
5266 struct intel_encoder *intel_encoder;
5267 bool enable = false;
5268
5269 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5270 enable |= intel_encoder->connectors_active;
5271
5272 intel_crtc_control(crtc, enable);
5273 }
5274
5275 static void intel_crtc_disable(struct drm_crtc *crtc)
5276 {
5277 struct drm_device *dev = crtc->dev;
5278 struct drm_connector *connector;
5279 struct drm_i915_private *dev_priv = dev->dev_private;
5280
5281 /* crtc should still be enabled when we disable it. */
5282 WARN_ON(!crtc->enabled);
5283
5284 dev_priv->display.crtc_disable(crtc);
5285 dev_priv->display.off(crtc);
5286
5287 crtc->primary->funcs->disable_plane(crtc->primary);
5288
5289 /* Update computed state. */
5290 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5291 if (!connector->encoder || !connector->encoder->crtc)
5292 continue;
5293
5294 if (connector->encoder->crtc != crtc)
5295 continue;
5296
5297 connector->dpms = DRM_MODE_DPMS_OFF;
5298 to_intel_encoder(connector->encoder)->connectors_active = false;
5299 }
5300 }
5301
5302 void intel_encoder_destroy(struct drm_encoder *encoder)
5303 {
5304 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5305
5306 drm_encoder_cleanup(encoder);
5307 kfree(intel_encoder);
5308 }
5309
5310 /* Simple dpms helper for encoders with just one connector, no cloning and only
5311 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5312 * state of the entire output pipe. */
5313 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5314 {
5315 if (mode == DRM_MODE_DPMS_ON) {
5316 encoder->connectors_active = true;
5317
5318 intel_crtc_update_dpms(encoder->base.crtc);
5319 } else {
5320 encoder->connectors_active = false;
5321
5322 intel_crtc_update_dpms(encoder->base.crtc);
5323 }
5324 }
5325
5326 /* Cross check the actual hw state with our own modeset state tracking (and it's
5327 * internal consistency). */
5328 static void intel_connector_check_state(struct intel_connector *connector)
5329 {
5330 if (connector->get_hw_state(connector)) {
5331 struct intel_encoder *encoder = connector->encoder;
5332 struct drm_crtc *crtc;
5333 bool encoder_enabled;
5334 enum pipe pipe;
5335
5336 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5337 connector->base.base.id,
5338 connector->base.name);
5339
5340 /* there is no real hw state for MST connectors */
5341 if (connector->mst_port)
5342 return;
5343
5344 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5345 "wrong connector dpms state\n");
5346 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5347 "active connector not linked to encoder\n");
5348
5349 if (encoder) {
5350 I915_STATE_WARN(!encoder->connectors_active,
5351 "encoder->connectors_active not set\n");
5352
5353 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5354 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5355 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5356 return;
5357
5358 crtc = encoder->base.crtc;
5359
5360 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5361 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5362 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5363 "encoder active on the wrong pipe\n");
5364 }
5365 }
5366 }
5367
5368 /* Even simpler default implementation, if there's really no special case to
5369 * consider. */
5370 void intel_connector_dpms(struct drm_connector *connector, int mode)
5371 {
5372 /* All the simple cases only support two dpms states. */
5373 if (mode != DRM_MODE_DPMS_ON)
5374 mode = DRM_MODE_DPMS_OFF;
5375
5376 if (mode == connector->dpms)
5377 return;
5378
5379 connector->dpms = mode;
5380
5381 /* Only need to change hw state when actually enabled */
5382 if (connector->encoder)
5383 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5384
5385 intel_modeset_check_state(connector->dev);
5386 }
5387
5388 /* Simple connector->get_hw_state implementation for encoders that support only
5389 * one connector and no cloning and hence the encoder state determines the state
5390 * of the connector. */
5391 bool intel_connector_get_hw_state(struct intel_connector *connector)
5392 {
5393 enum pipe pipe = 0;
5394 struct intel_encoder *encoder = connector->encoder;
5395
5396 return encoder->get_hw_state(encoder, &pipe);
5397 }
5398
5399 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5400 struct intel_crtc_state *pipe_config)
5401 {
5402 struct drm_i915_private *dev_priv = dev->dev_private;
5403 struct intel_crtc *pipe_B_crtc =
5404 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5405
5406 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5407 pipe_name(pipe), pipe_config->fdi_lanes);
5408 if (pipe_config->fdi_lanes > 4) {
5409 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5410 pipe_name(pipe), pipe_config->fdi_lanes);
5411 return false;
5412 }
5413
5414 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5415 if (pipe_config->fdi_lanes > 2) {
5416 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5417 pipe_config->fdi_lanes);
5418 return false;
5419 } else {
5420 return true;
5421 }
5422 }
5423
5424 if (INTEL_INFO(dev)->num_pipes == 2)
5425 return true;
5426
5427 /* Ivybridge 3 pipe is really complicated */
5428 switch (pipe) {
5429 case PIPE_A:
5430 return true;
5431 case PIPE_B:
5432 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5433 pipe_config->fdi_lanes > 2) {
5434 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5435 pipe_name(pipe), pipe_config->fdi_lanes);
5436 return false;
5437 }
5438 return true;
5439 case PIPE_C:
5440 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5441 pipe_B_crtc->config->fdi_lanes <= 2) {
5442 if (pipe_config->fdi_lanes > 2) {
5443 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5444 pipe_name(pipe), pipe_config->fdi_lanes);
5445 return false;
5446 }
5447 } else {
5448 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5449 return false;
5450 }
5451 return true;
5452 default:
5453 BUG();
5454 }
5455 }
5456
5457 #define RETRY 1
5458 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5459 struct intel_crtc_state *pipe_config)
5460 {
5461 struct drm_device *dev = intel_crtc->base.dev;
5462 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5463 int lane, link_bw, fdi_dotclock;
5464 bool setup_ok, needs_recompute = false;
5465
5466 retry:
5467 /* FDI is a binary signal running at ~2.7GHz, encoding
5468 * each output octet as 10 bits. The actual frequency
5469 * is stored as a divider into a 100MHz clock, and the
5470 * mode pixel clock is stored in units of 1KHz.
5471 * Hence the bw of each lane in terms of the mode signal
5472 * is:
5473 */
5474 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5475
5476 fdi_dotclock = adjusted_mode->crtc_clock;
5477
5478 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5479 pipe_config->pipe_bpp);
5480
5481 pipe_config->fdi_lanes = lane;
5482
5483 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5484 link_bw, &pipe_config->fdi_m_n);
5485
5486 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5487 intel_crtc->pipe, pipe_config);
5488 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5489 pipe_config->pipe_bpp -= 2*3;
5490 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5491 pipe_config->pipe_bpp);
5492 needs_recompute = true;
5493 pipe_config->bw_constrained = true;
5494
5495 goto retry;
5496 }
5497
5498 if (needs_recompute)
5499 return RETRY;
5500
5501 return setup_ok ? 0 : -EINVAL;
5502 }
5503
5504 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5505 struct intel_crtc_state *pipe_config)
5506 {
5507 pipe_config->ips_enabled = i915.enable_ips &&
5508 hsw_crtc_supports_ips(crtc) &&
5509 pipe_config->pipe_bpp <= 24;
5510 }
5511
5512 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5513 struct intel_crtc_state *pipe_config)
5514 {
5515 struct drm_device *dev = crtc->base.dev;
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5518
5519 /* FIXME should check pixel clock limits on all platforms */
5520 if (INTEL_INFO(dev)->gen < 4) {
5521 int clock_limit =
5522 dev_priv->display.get_display_clock_speed(dev);
5523
5524 /*
5525 * Enable pixel doubling when the dot clock
5526 * is > 90% of the (display) core speed.
5527 *
5528 * GDG double wide on either pipe,
5529 * otherwise pipe A only.
5530 */
5531 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5532 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5533 clock_limit *= 2;
5534 pipe_config->double_wide = true;
5535 }
5536
5537 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5538 return -EINVAL;
5539 }
5540
5541 /*
5542 * Pipe horizontal size must be even in:
5543 * - DVO ganged mode
5544 * - LVDS dual channel mode
5545 * - Double wide pipe
5546 */
5547 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5548 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5549 pipe_config->pipe_src_w &= ~1;
5550
5551 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5552 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5553 */
5554 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5555 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5556 return -EINVAL;
5557
5558 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5559 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5560 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5561 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5562 * for lvds. */
5563 pipe_config->pipe_bpp = 8*3;
5564 }
5565
5566 if (HAS_IPS(dev))
5567 hsw_compute_ips_config(crtc, pipe_config);
5568
5569 if (pipe_config->has_pch_encoder)
5570 return ironlake_fdi_compute_config(crtc, pipe_config);
5571
5572 return 0;
5573 }
5574
5575 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5576 {
5577 struct drm_i915_private *dev_priv = dev->dev_private;
5578 u32 val;
5579 int divider;
5580
5581 /* FIXME: Punit isn't quite ready yet */
5582 if (IS_CHERRYVIEW(dev))
5583 return 400000;
5584
5585 if (dev_priv->hpll_freq == 0)
5586 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5587
5588 mutex_lock(&dev_priv->dpio_lock);
5589 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5590 mutex_unlock(&dev_priv->dpio_lock);
5591
5592 divider = val & DISPLAY_FREQUENCY_VALUES;
5593
5594 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5595 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5596 "cdclk change in progress\n");
5597
5598 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5599 }
5600
5601 static int i945_get_display_clock_speed(struct drm_device *dev)
5602 {
5603 return 400000;
5604 }
5605
5606 static int i915_get_display_clock_speed(struct drm_device *dev)
5607 {
5608 return 333000;
5609 }
5610
5611 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5612 {
5613 return 200000;
5614 }
5615
5616 static int pnv_get_display_clock_speed(struct drm_device *dev)
5617 {
5618 u16 gcfgc = 0;
5619
5620 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5621
5622 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5623 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5624 return 267000;
5625 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5626 return 333000;
5627 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5628 return 444000;
5629 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5630 return 200000;
5631 default:
5632 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5633 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5634 return 133000;
5635 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5636 return 167000;
5637 }
5638 }
5639
5640 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5641 {
5642 u16 gcfgc = 0;
5643
5644 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5645
5646 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5647 return 133000;
5648 else {
5649 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5650 case GC_DISPLAY_CLOCK_333_MHZ:
5651 return 333000;
5652 default:
5653 case GC_DISPLAY_CLOCK_190_200_MHZ:
5654 return 190000;
5655 }
5656 }
5657 }
5658
5659 static int i865_get_display_clock_speed(struct drm_device *dev)
5660 {
5661 return 266000;
5662 }
5663
5664 static int i855_get_display_clock_speed(struct drm_device *dev)
5665 {
5666 u16 hpllcc = 0;
5667 /* Assume that the hardware is in the high speed state. This
5668 * should be the default.
5669 */
5670 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5671 case GC_CLOCK_133_200:
5672 case GC_CLOCK_100_200:
5673 return 200000;
5674 case GC_CLOCK_166_250:
5675 return 250000;
5676 case GC_CLOCK_100_133:
5677 return 133000;
5678 }
5679
5680 /* Shouldn't happen */
5681 return 0;
5682 }
5683
5684 static int i830_get_display_clock_speed(struct drm_device *dev)
5685 {
5686 return 133000;
5687 }
5688
5689 static void
5690 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5691 {
5692 while (*num > DATA_LINK_M_N_MASK ||
5693 *den > DATA_LINK_M_N_MASK) {
5694 *num >>= 1;
5695 *den >>= 1;
5696 }
5697 }
5698
5699 static void compute_m_n(unsigned int m, unsigned int n,
5700 uint32_t *ret_m, uint32_t *ret_n)
5701 {
5702 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5703 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5704 intel_reduce_m_n_ratio(ret_m, ret_n);
5705 }
5706
5707 void
5708 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5709 int pixel_clock, int link_clock,
5710 struct intel_link_m_n *m_n)
5711 {
5712 m_n->tu = 64;
5713
5714 compute_m_n(bits_per_pixel * pixel_clock,
5715 link_clock * nlanes * 8,
5716 &m_n->gmch_m, &m_n->gmch_n);
5717
5718 compute_m_n(pixel_clock, link_clock,
5719 &m_n->link_m, &m_n->link_n);
5720 }
5721
5722 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5723 {
5724 if (i915.panel_use_ssc >= 0)
5725 return i915.panel_use_ssc != 0;
5726 return dev_priv->vbt.lvds_use_ssc
5727 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5728 }
5729
5730 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5731 {
5732 struct drm_device *dev = crtc->base.dev;
5733 struct drm_i915_private *dev_priv = dev->dev_private;
5734 int refclk;
5735
5736 if (IS_VALLEYVIEW(dev)) {
5737 refclk = 100000;
5738 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5739 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5740 refclk = dev_priv->vbt.lvds_ssc_freq;
5741 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5742 } else if (!IS_GEN2(dev)) {
5743 refclk = 96000;
5744 } else {
5745 refclk = 48000;
5746 }
5747
5748 return refclk;
5749 }
5750
5751 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5752 {
5753 return (1 << dpll->n) << 16 | dpll->m2;
5754 }
5755
5756 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5757 {
5758 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5759 }
5760
5761 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5762 struct intel_crtc_state *crtc_state,
5763 intel_clock_t *reduced_clock)
5764 {
5765 struct drm_device *dev = crtc->base.dev;
5766 u32 fp, fp2 = 0;
5767
5768 if (IS_PINEVIEW(dev)) {
5769 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5770 if (reduced_clock)
5771 fp2 = pnv_dpll_compute_fp(reduced_clock);
5772 } else {
5773 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5774 if (reduced_clock)
5775 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5776 }
5777
5778 crtc_state->dpll_hw_state.fp0 = fp;
5779
5780 crtc->lowfreq_avail = false;
5781 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5782 reduced_clock && i915.powersave) {
5783 crtc_state->dpll_hw_state.fp1 = fp2;
5784 crtc->lowfreq_avail = true;
5785 } else {
5786 crtc_state->dpll_hw_state.fp1 = fp;
5787 }
5788 }
5789
5790 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5791 pipe)
5792 {
5793 u32 reg_val;
5794
5795 /*
5796 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5797 * and set it to a reasonable value instead.
5798 */
5799 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5800 reg_val &= 0xffffff00;
5801 reg_val |= 0x00000030;
5802 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5803
5804 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5805 reg_val &= 0x8cffffff;
5806 reg_val = 0x8c000000;
5807 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5808
5809 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5810 reg_val &= 0xffffff00;
5811 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5812
5813 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5814 reg_val &= 0x00ffffff;
5815 reg_val |= 0xb0000000;
5816 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5817 }
5818
5819 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5820 struct intel_link_m_n *m_n)
5821 {
5822 struct drm_device *dev = crtc->base.dev;
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 int pipe = crtc->pipe;
5825
5826 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5827 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5828 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5829 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5830 }
5831
5832 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5833 struct intel_link_m_n *m_n,
5834 struct intel_link_m_n *m2_n2)
5835 {
5836 struct drm_device *dev = crtc->base.dev;
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 int pipe = crtc->pipe;
5839 enum transcoder transcoder = crtc->config->cpu_transcoder;
5840
5841 if (INTEL_INFO(dev)->gen >= 5) {
5842 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5843 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5844 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5845 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5846 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5847 * for gen < 8) and if DRRS is supported (to make sure the
5848 * registers are not unnecessarily accessed).
5849 */
5850 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5851 crtc->config->has_drrs) {
5852 I915_WRITE(PIPE_DATA_M2(transcoder),
5853 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5854 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5855 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5856 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5857 }
5858 } else {
5859 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5860 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5861 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5862 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5863 }
5864 }
5865
5866 void intel_dp_set_m_n(struct intel_crtc *crtc)
5867 {
5868 if (crtc->config->has_pch_encoder)
5869 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5870 else
5871 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5872 &crtc->config->dp_m2_n2);
5873 }
5874
5875 static void vlv_update_pll(struct intel_crtc *crtc,
5876 struct intel_crtc_state *pipe_config)
5877 {
5878 u32 dpll, dpll_md;
5879
5880 /*
5881 * Enable DPIO clock input. We should never disable the reference
5882 * clock for pipe B, since VGA hotplug / manual detection depends
5883 * on it.
5884 */
5885 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5886 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5887 /* We should never disable this, set it here for state tracking */
5888 if (crtc->pipe == PIPE_B)
5889 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5890 dpll |= DPLL_VCO_ENABLE;
5891 pipe_config->dpll_hw_state.dpll = dpll;
5892
5893 dpll_md = (pipe_config->pixel_multiplier - 1)
5894 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5895 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5896 }
5897
5898 static void vlv_prepare_pll(struct intel_crtc *crtc,
5899 const struct intel_crtc_state *pipe_config)
5900 {
5901 struct drm_device *dev = crtc->base.dev;
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903 int pipe = crtc->pipe;
5904 u32 mdiv;
5905 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5906 u32 coreclk, reg_val;
5907
5908 mutex_lock(&dev_priv->dpio_lock);
5909
5910 bestn = pipe_config->dpll.n;
5911 bestm1 = pipe_config->dpll.m1;
5912 bestm2 = pipe_config->dpll.m2;
5913 bestp1 = pipe_config->dpll.p1;
5914 bestp2 = pipe_config->dpll.p2;
5915
5916 /* See eDP HDMI DPIO driver vbios notes doc */
5917
5918 /* PLL B needs special handling */
5919 if (pipe == PIPE_B)
5920 vlv_pllb_recal_opamp(dev_priv, pipe);
5921
5922 /* Set up Tx target for periodic Rcomp update */
5923 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5924
5925 /* Disable target IRef on PLL */
5926 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5927 reg_val &= 0x00ffffff;
5928 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5929
5930 /* Disable fast lock */
5931 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5932
5933 /* Set idtafcrecal before PLL is enabled */
5934 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5935 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5936 mdiv |= ((bestn << DPIO_N_SHIFT));
5937 mdiv |= (1 << DPIO_K_SHIFT);
5938
5939 /*
5940 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5941 * but we don't support that).
5942 * Note: don't use the DAC post divider as it seems unstable.
5943 */
5944 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5946
5947 mdiv |= DPIO_ENABLE_CALIBRATION;
5948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5949
5950 /* Set HBR and RBR LPF coefficients */
5951 if (pipe_config->port_clock == 162000 ||
5952 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5953 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5955 0x009f0003);
5956 else
5957 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5958 0x00d0000f);
5959
5960 if (pipe_config->has_dp_encoder) {
5961 /* Use SSC source */
5962 if (pipe == PIPE_A)
5963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5964 0x0df40000);
5965 else
5966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5967 0x0df70000);
5968 } else { /* HDMI or VGA */
5969 /* Use bend source */
5970 if (pipe == PIPE_A)
5971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5972 0x0df70000);
5973 else
5974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5975 0x0df40000);
5976 }
5977
5978 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5979 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5980 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5981 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5982 coreclk |= 0x01000000;
5983 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5984
5985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5986 mutex_unlock(&dev_priv->dpio_lock);
5987 }
5988
5989 static void chv_update_pll(struct intel_crtc *crtc,
5990 struct intel_crtc_state *pipe_config)
5991 {
5992 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5993 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5994 DPLL_VCO_ENABLE;
5995 if (crtc->pipe != PIPE_A)
5996 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5997
5998 pipe_config->dpll_hw_state.dpll_md =
5999 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6000 }
6001
6002 static void chv_prepare_pll(struct intel_crtc *crtc,
6003 const struct intel_crtc_state *pipe_config)
6004 {
6005 struct drm_device *dev = crtc->base.dev;
6006 struct drm_i915_private *dev_priv = dev->dev_private;
6007 int pipe = crtc->pipe;
6008 int dpll_reg = DPLL(crtc->pipe);
6009 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6010 u32 loopfilter, intcoeff;
6011 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6012 int refclk;
6013
6014 bestn = pipe_config->dpll.n;
6015 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6016 bestm1 = pipe_config->dpll.m1;
6017 bestm2 = pipe_config->dpll.m2 >> 22;
6018 bestp1 = pipe_config->dpll.p1;
6019 bestp2 = pipe_config->dpll.p2;
6020
6021 /*
6022 * Enable Refclk and SSC
6023 */
6024 I915_WRITE(dpll_reg,
6025 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6026
6027 mutex_lock(&dev_priv->dpio_lock);
6028
6029 /* p1 and p2 divider */
6030 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6031 5 << DPIO_CHV_S1_DIV_SHIFT |
6032 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6033 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6034 1 << DPIO_CHV_K_DIV_SHIFT);
6035
6036 /* Feedback post-divider - m2 */
6037 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6038
6039 /* Feedback refclk divider - n and m1 */
6040 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6041 DPIO_CHV_M1_DIV_BY_2 |
6042 1 << DPIO_CHV_N_DIV_SHIFT);
6043
6044 /* M2 fraction division */
6045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6046
6047 /* M2 fraction division enable */
6048 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6049 DPIO_CHV_FRAC_DIV_EN |
6050 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6051
6052 /* Loop filter */
6053 refclk = i9xx_get_refclk(crtc, 0);
6054 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6055 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6056 if (refclk == 100000)
6057 intcoeff = 11;
6058 else if (refclk == 38400)
6059 intcoeff = 10;
6060 else
6061 intcoeff = 9;
6062 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6063 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6064
6065 /* AFC Recal */
6066 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6067 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6068 DPIO_AFC_RECAL);
6069
6070 mutex_unlock(&dev_priv->dpio_lock);
6071 }
6072
6073 /**
6074 * vlv_force_pll_on - forcibly enable just the PLL
6075 * @dev_priv: i915 private structure
6076 * @pipe: pipe PLL to enable
6077 * @dpll: PLL configuration
6078 *
6079 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6080 * in cases where we need the PLL enabled even when @pipe is not going to
6081 * be enabled.
6082 */
6083 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6084 const struct dpll *dpll)
6085 {
6086 struct intel_crtc *crtc =
6087 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6088 struct intel_crtc_state pipe_config = {
6089 .pixel_multiplier = 1,
6090 .dpll = *dpll,
6091 };
6092
6093 if (IS_CHERRYVIEW(dev)) {
6094 chv_update_pll(crtc, &pipe_config);
6095 chv_prepare_pll(crtc, &pipe_config);
6096 chv_enable_pll(crtc, &pipe_config);
6097 } else {
6098 vlv_update_pll(crtc, &pipe_config);
6099 vlv_prepare_pll(crtc, &pipe_config);
6100 vlv_enable_pll(crtc, &pipe_config);
6101 }
6102 }
6103
6104 /**
6105 * vlv_force_pll_off - forcibly disable just the PLL
6106 * @dev_priv: i915 private structure
6107 * @pipe: pipe PLL to disable
6108 *
6109 * Disable the PLL for @pipe. To be used in cases where we need
6110 * the PLL enabled even when @pipe is not going to be enabled.
6111 */
6112 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6113 {
6114 if (IS_CHERRYVIEW(dev))
6115 chv_disable_pll(to_i915(dev), pipe);
6116 else
6117 vlv_disable_pll(to_i915(dev), pipe);
6118 }
6119
6120 static void i9xx_update_pll(struct intel_crtc *crtc,
6121 struct intel_crtc_state *crtc_state,
6122 intel_clock_t *reduced_clock,
6123 int num_connectors)
6124 {
6125 struct drm_device *dev = crtc->base.dev;
6126 struct drm_i915_private *dev_priv = dev->dev_private;
6127 u32 dpll;
6128 bool is_sdvo;
6129 struct dpll *clock = &crtc_state->dpll;
6130
6131 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6132
6133 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6134 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6135
6136 dpll = DPLL_VGA_MODE_DIS;
6137
6138 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6139 dpll |= DPLLB_MODE_LVDS;
6140 else
6141 dpll |= DPLLB_MODE_DAC_SERIAL;
6142
6143 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6144 dpll |= (crtc_state->pixel_multiplier - 1)
6145 << SDVO_MULTIPLIER_SHIFT_HIRES;
6146 }
6147
6148 if (is_sdvo)
6149 dpll |= DPLL_SDVO_HIGH_SPEED;
6150
6151 if (crtc_state->has_dp_encoder)
6152 dpll |= DPLL_SDVO_HIGH_SPEED;
6153
6154 /* compute bitmask from p1 value */
6155 if (IS_PINEVIEW(dev))
6156 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6157 else {
6158 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6159 if (IS_G4X(dev) && reduced_clock)
6160 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6161 }
6162 switch (clock->p2) {
6163 case 5:
6164 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6165 break;
6166 case 7:
6167 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6168 break;
6169 case 10:
6170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6171 break;
6172 case 14:
6173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6174 break;
6175 }
6176 if (INTEL_INFO(dev)->gen >= 4)
6177 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6178
6179 if (crtc_state->sdvo_tv_clock)
6180 dpll |= PLL_REF_INPUT_TVCLKINBC;
6181 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6182 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6183 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6184 else
6185 dpll |= PLL_REF_INPUT_DREFCLK;
6186
6187 dpll |= DPLL_VCO_ENABLE;
6188 crtc_state->dpll_hw_state.dpll = dpll;
6189
6190 if (INTEL_INFO(dev)->gen >= 4) {
6191 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6192 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6193 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6194 }
6195 }
6196
6197 static void i8xx_update_pll(struct intel_crtc *crtc,
6198 struct intel_crtc_state *crtc_state,
6199 intel_clock_t *reduced_clock,
6200 int num_connectors)
6201 {
6202 struct drm_device *dev = crtc->base.dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 u32 dpll;
6205 struct dpll *clock = &crtc_state->dpll;
6206
6207 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6208
6209 dpll = DPLL_VGA_MODE_DIS;
6210
6211 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6212 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6213 } else {
6214 if (clock->p1 == 2)
6215 dpll |= PLL_P1_DIVIDE_BY_TWO;
6216 else
6217 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6218 if (clock->p2 == 4)
6219 dpll |= PLL_P2_DIVIDE_BY_4;
6220 }
6221
6222 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6223 dpll |= DPLL_DVO_2X_MODE;
6224
6225 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6226 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6227 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6228 else
6229 dpll |= PLL_REF_INPUT_DREFCLK;
6230
6231 dpll |= DPLL_VCO_ENABLE;
6232 crtc_state->dpll_hw_state.dpll = dpll;
6233 }
6234
6235 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6236 {
6237 struct drm_device *dev = intel_crtc->base.dev;
6238 struct drm_i915_private *dev_priv = dev->dev_private;
6239 enum pipe pipe = intel_crtc->pipe;
6240 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6241 struct drm_display_mode *adjusted_mode =
6242 &intel_crtc->config->base.adjusted_mode;
6243 uint32_t crtc_vtotal, crtc_vblank_end;
6244 int vsyncshift = 0;
6245
6246 /* We need to be careful not to changed the adjusted mode, for otherwise
6247 * the hw state checker will get angry at the mismatch. */
6248 crtc_vtotal = adjusted_mode->crtc_vtotal;
6249 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6250
6251 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6252 /* the chip adds 2 halflines automatically */
6253 crtc_vtotal -= 1;
6254 crtc_vblank_end -= 1;
6255
6256 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6257 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6258 else
6259 vsyncshift = adjusted_mode->crtc_hsync_start -
6260 adjusted_mode->crtc_htotal / 2;
6261 if (vsyncshift < 0)
6262 vsyncshift += adjusted_mode->crtc_htotal;
6263 }
6264
6265 if (INTEL_INFO(dev)->gen > 3)
6266 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6267
6268 I915_WRITE(HTOTAL(cpu_transcoder),
6269 (adjusted_mode->crtc_hdisplay - 1) |
6270 ((adjusted_mode->crtc_htotal - 1) << 16));
6271 I915_WRITE(HBLANK(cpu_transcoder),
6272 (adjusted_mode->crtc_hblank_start - 1) |
6273 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6274 I915_WRITE(HSYNC(cpu_transcoder),
6275 (adjusted_mode->crtc_hsync_start - 1) |
6276 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6277
6278 I915_WRITE(VTOTAL(cpu_transcoder),
6279 (adjusted_mode->crtc_vdisplay - 1) |
6280 ((crtc_vtotal - 1) << 16));
6281 I915_WRITE(VBLANK(cpu_transcoder),
6282 (adjusted_mode->crtc_vblank_start - 1) |
6283 ((crtc_vblank_end - 1) << 16));
6284 I915_WRITE(VSYNC(cpu_transcoder),
6285 (adjusted_mode->crtc_vsync_start - 1) |
6286 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6287
6288 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6289 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6290 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6291 * bits. */
6292 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6293 (pipe == PIPE_B || pipe == PIPE_C))
6294 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6295
6296 /* pipesrc controls the size that is scaled from, which should
6297 * always be the user's requested size.
6298 */
6299 I915_WRITE(PIPESRC(pipe),
6300 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6301 (intel_crtc->config->pipe_src_h - 1));
6302 }
6303
6304 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6305 struct intel_crtc_state *pipe_config)
6306 {
6307 struct drm_device *dev = crtc->base.dev;
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6309 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6310 uint32_t tmp;
6311
6312 tmp = I915_READ(HTOTAL(cpu_transcoder));
6313 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6314 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6315 tmp = I915_READ(HBLANK(cpu_transcoder));
6316 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6317 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6318 tmp = I915_READ(HSYNC(cpu_transcoder));
6319 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6320 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6321
6322 tmp = I915_READ(VTOTAL(cpu_transcoder));
6323 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6324 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6325 tmp = I915_READ(VBLANK(cpu_transcoder));
6326 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6327 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6328 tmp = I915_READ(VSYNC(cpu_transcoder));
6329 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6330 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6331
6332 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6333 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6334 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6335 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6336 }
6337
6338 tmp = I915_READ(PIPESRC(crtc->pipe));
6339 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6340 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6341
6342 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6343 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6344 }
6345
6346 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6347 struct intel_crtc_state *pipe_config)
6348 {
6349 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6350 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6351 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6352 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6353
6354 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6355 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6356 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6357 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6358
6359 mode->flags = pipe_config->base.adjusted_mode.flags;
6360
6361 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6362 mode->flags |= pipe_config->base.adjusted_mode.flags;
6363 }
6364
6365 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6366 {
6367 struct drm_device *dev = intel_crtc->base.dev;
6368 struct drm_i915_private *dev_priv = dev->dev_private;
6369 uint32_t pipeconf;
6370
6371 pipeconf = 0;
6372
6373 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6374 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6375 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6376
6377 if (intel_crtc->config->double_wide)
6378 pipeconf |= PIPECONF_DOUBLE_WIDE;
6379
6380 /* only g4x and later have fancy bpc/dither controls */
6381 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6382 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6383 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6384 pipeconf |= PIPECONF_DITHER_EN |
6385 PIPECONF_DITHER_TYPE_SP;
6386
6387 switch (intel_crtc->config->pipe_bpp) {
6388 case 18:
6389 pipeconf |= PIPECONF_6BPC;
6390 break;
6391 case 24:
6392 pipeconf |= PIPECONF_8BPC;
6393 break;
6394 case 30:
6395 pipeconf |= PIPECONF_10BPC;
6396 break;
6397 default:
6398 /* Case prevented by intel_choose_pipe_bpp_dither. */
6399 BUG();
6400 }
6401 }
6402
6403 if (HAS_PIPE_CXSR(dev)) {
6404 if (intel_crtc->lowfreq_avail) {
6405 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6406 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6407 } else {
6408 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6409 }
6410 }
6411
6412 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6413 if (INTEL_INFO(dev)->gen < 4 ||
6414 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6415 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6416 else
6417 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6418 } else
6419 pipeconf |= PIPECONF_PROGRESSIVE;
6420
6421 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6422 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6423
6424 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6425 POSTING_READ(PIPECONF(intel_crtc->pipe));
6426 }
6427
6428 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6429 struct intel_crtc_state *crtc_state)
6430 {
6431 struct drm_device *dev = crtc->base.dev;
6432 struct drm_i915_private *dev_priv = dev->dev_private;
6433 int refclk, num_connectors = 0;
6434 intel_clock_t clock, reduced_clock;
6435 bool ok, has_reduced_clock = false;
6436 bool is_lvds = false, is_dsi = false;
6437 struct intel_encoder *encoder;
6438 const intel_limit_t *limit;
6439
6440 for_each_intel_encoder(dev, encoder) {
6441 if (encoder->new_crtc != crtc)
6442 continue;
6443
6444 switch (encoder->type) {
6445 case INTEL_OUTPUT_LVDS:
6446 is_lvds = true;
6447 break;
6448 case INTEL_OUTPUT_DSI:
6449 is_dsi = true;
6450 break;
6451 default:
6452 break;
6453 }
6454
6455 num_connectors++;
6456 }
6457
6458 if (is_dsi)
6459 return 0;
6460
6461 if (!crtc_state->clock_set) {
6462 refclk = i9xx_get_refclk(crtc, num_connectors);
6463
6464 /*
6465 * Returns a set of divisors for the desired target clock with
6466 * the given refclk, or FALSE. The returned values represent
6467 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6468 * 2) / p1 / p2.
6469 */
6470 limit = intel_limit(crtc, refclk);
6471 ok = dev_priv->display.find_dpll(limit, crtc,
6472 crtc_state->port_clock,
6473 refclk, NULL, &clock);
6474 if (!ok) {
6475 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6476 return -EINVAL;
6477 }
6478
6479 if (is_lvds && dev_priv->lvds_downclock_avail) {
6480 /*
6481 * Ensure we match the reduced clock's P to the target
6482 * clock. If the clocks don't match, we can't switch
6483 * the display clock by using the FP0/FP1. In such case
6484 * we will disable the LVDS downclock feature.
6485 */
6486 has_reduced_clock =
6487 dev_priv->display.find_dpll(limit, crtc,
6488 dev_priv->lvds_downclock,
6489 refclk, &clock,
6490 &reduced_clock);
6491 }
6492 /* Compat-code for transition, will disappear. */
6493 crtc_state->dpll.n = clock.n;
6494 crtc_state->dpll.m1 = clock.m1;
6495 crtc_state->dpll.m2 = clock.m2;
6496 crtc_state->dpll.p1 = clock.p1;
6497 crtc_state->dpll.p2 = clock.p2;
6498 }
6499
6500 if (IS_GEN2(dev)) {
6501 i8xx_update_pll(crtc, crtc_state,
6502 has_reduced_clock ? &reduced_clock : NULL,
6503 num_connectors);
6504 } else if (IS_CHERRYVIEW(dev)) {
6505 chv_update_pll(crtc, crtc_state);
6506 } else if (IS_VALLEYVIEW(dev)) {
6507 vlv_update_pll(crtc, crtc_state);
6508 } else {
6509 i9xx_update_pll(crtc, crtc_state,
6510 has_reduced_clock ? &reduced_clock : NULL,
6511 num_connectors);
6512 }
6513
6514 return 0;
6515 }
6516
6517 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6518 struct intel_crtc_state *pipe_config)
6519 {
6520 struct drm_device *dev = crtc->base.dev;
6521 struct drm_i915_private *dev_priv = dev->dev_private;
6522 uint32_t tmp;
6523
6524 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6525 return;
6526
6527 tmp = I915_READ(PFIT_CONTROL);
6528 if (!(tmp & PFIT_ENABLE))
6529 return;
6530
6531 /* Check whether the pfit is attached to our pipe. */
6532 if (INTEL_INFO(dev)->gen < 4) {
6533 if (crtc->pipe != PIPE_B)
6534 return;
6535 } else {
6536 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6537 return;
6538 }
6539
6540 pipe_config->gmch_pfit.control = tmp;
6541 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6542 if (INTEL_INFO(dev)->gen < 5)
6543 pipe_config->gmch_pfit.lvds_border_bits =
6544 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6545 }
6546
6547 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6548 struct intel_crtc_state *pipe_config)
6549 {
6550 struct drm_device *dev = crtc->base.dev;
6551 struct drm_i915_private *dev_priv = dev->dev_private;
6552 int pipe = pipe_config->cpu_transcoder;
6553 intel_clock_t clock;
6554 u32 mdiv;
6555 int refclk = 100000;
6556
6557 /* In case of MIPI DPLL will not even be used */
6558 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6559 return;
6560
6561 mutex_lock(&dev_priv->dpio_lock);
6562 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6563 mutex_unlock(&dev_priv->dpio_lock);
6564
6565 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6566 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6567 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6568 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6569 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6570
6571 vlv_clock(refclk, &clock);
6572
6573 /* clock.dot is the fast clock */
6574 pipe_config->port_clock = clock.dot / 5;
6575 }
6576
6577 static void
6578 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6579 struct intel_initial_plane_config *plane_config)
6580 {
6581 struct drm_device *dev = crtc->base.dev;
6582 struct drm_i915_private *dev_priv = dev->dev_private;
6583 u32 val, base, offset;
6584 int pipe = crtc->pipe, plane = crtc->plane;
6585 int fourcc, pixel_format;
6586 int aligned_height;
6587 struct drm_framebuffer *fb;
6588 struct intel_framebuffer *intel_fb;
6589
6590 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6591 if (!intel_fb) {
6592 DRM_DEBUG_KMS("failed to alloc fb\n");
6593 return;
6594 }
6595
6596 fb = &intel_fb->base;
6597
6598 val = I915_READ(DSPCNTR(plane));
6599
6600 if (INTEL_INFO(dev)->gen >= 4)
6601 if (val & DISPPLANE_TILED)
6602 plane_config->tiling = I915_TILING_X;
6603
6604 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6605 fourcc = i9xx_format_to_fourcc(pixel_format);
6606 fb->pixel_format = fourcc;
6607 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6608
6609 if (INTEL_INFO(dev)->gen >= 4) {
6610 if (plane_config->tiling)
6611 offset = I915_READ(DSPTILEOFF(plane));
6612 else
6613 offset = I915_READ(DSPLINOFF(plane));
6614 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6615 } else {
6616 base = I915_READ(DSPADDR(plane));
6617 }
6618 plane_config->base = base;
6619
6620 val = I915_READ(PIPESRC(pipe));
6621 fb->width = ((val >> 16) & 0xfff) + 1;
6622 fb->height = ((val >> 0) & 0xfff) + 1;
6623
6624 val = I915_READ(DSPSTRIDE(pipe));
6625 fb->pitches[0] = val & 0xffffffc0;
6626
6627 aligned_height = intel_fb_align_height(dev, fb->height,
6628 plane_config->tiling);
6629
6630 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6631
6632 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6633 pipe_name(pipe), plane, fb->width, fb->height,
6634 fb->bits_per_pixel, base, fb->pitches[0],
6635 plane_config->size);
6636
6637 crtc->base.primary->fb = fb;
6638 }
6639
6640 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6641 struct intel_crtc_state *pipe_config)
6642 {
6643 struct drm_device *dev = crtc->base.dev;
6644 struct drm_i915_private *dev_priv = dev->dev_private;
6645 int pipe = pipe_config->cpu_transcoder;
6646 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6647 intel_clock_t clock;
6648 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6649 int refclk = 100000;
6650
6651 mutex_lock(&dev_priv->dpio_lock);
6652 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6653 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6654 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6655 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6656 mutex_unlock(&dev_priv->dpio_lock);
6657
6658 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6659 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6660 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6661 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6662 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6663
6664 chv_clock(refclk, &clock);
6665
6666 /* clock.dot is the fast clock */
6667 pipe_config->port_clock = clock.dot / 5;
6668 }
6669
6670 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6671 struct intel_crtc_state *pipe_config)
6672 {
6673 struct drm_device *dev = crtc->base.dev;
6674 struct drm_i915_private *dev_priv = dev->dev_private;
6675 uint32_t tmp;
6676
6677 if (!intel_display_power_is_enabled(dev_priv,
6678 POWER_DOMAIN_PIPE(crtc->pipe)))
6679 return false;
6680
6681 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6682 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6683
6684 tmp = I915_READ(PIPECONF(crtc->pipe));
6685 if (!(tmp & PIPECONF_ENABLE))
6686 return false;
6687
6688 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6689 switch (tmp & PIPECONF_BPC_MASK) {
6690 case PIPECONF_6BPC:
6691 pipe_config->pipe_bpp = 18;
6692 break;
6693 case PIPECONF_8BPC:
6694 pipe_config->pipe_bpp = 24;
6695 break;
6696 case PIPECONF_10BPC:
6697 pipe_config->pipe_bpp = 30;
6698 break;
6699 default:
6700 break;
6701 }
6702 }
6703
6704 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6705 pipe_config->limited_color_range = true;
6706
6707 if (INTEL_INFO(dev)->gen < 4)
6708 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6709
6710 intel_get_pipe_timings(crtc, pipe_config);
6711
6712 i9xx_get_pfit_config(crtc, pipe_config);
6713
6714 if (INTEL_INFO(dev)->gen >= 4) {
6715 tmp = I915_READ(DPLL_MD(crtc->pipe));
6716 pipe_config->pixel_multiplier =
6717 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6718 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6719 pipe_config->dpll_hw_state.dpll_md = tmp;
6720 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6721 tmp = I915_READ(DPLL(crtc->pipe));
6722 pipe_config->pixel_multiplier =
6723 ((tmp & SDVO_MULTIPLIER_MASK)
6724 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6725 } else {
6726 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6727 * port and will be fixed up in the encoder->get_config
6728 * function. */
6729 pipe_config->pixel_multiplier = 1;
6730 }
6731 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6732 if (!IS_VALLEYVIEW(dev)) {
6733 /*
6734 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6735 * on 830. Filter it out here so that we don't
6736 * report errors due to that.
6737 */
6738 if (IS_I830(dev))
6739 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6740
6741 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6742 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6743 } else {
6744 /* Mask out read-only status bits. */
6745 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6746 DPLL_PORTC_READY_MASK |
6747 DPLL_PORTB_READY_MASK);
6748 }
6749
6750 if (IS_CHERRYVIEW(dev))
6751 chv_crtc_clock_get(crtc, pipe_config);
6752 else if (IS_VALLEYVIEW(dev))
6753 vlv_crtc_clock_get(crtc, pipe_config);
6754 else
6755 i9xx_crtc_clock_get(crtc, pipe_config);
6756
6757 return true;
6758 }
6759
6760 static void ironlake_init_pch_refclk(struct drm_device *dev)
6761 {
6762 struct drm_i915_private *dev_priv = dev->dev_private;
6763 struct intel_encoder *encoder;
6764 u32 val, final;
6765 bool has_lvds = false;
6766 bool has_cpu_edp = false;
6767 bool has_panel = false;
6768 bool has_ck505 = false;
6769 bool can_ssc = false;
6770
6771 /* We need to take the global config into account */
6772 for_each_intel_encoder(dev, encoder) {
6773 switch (encoder->type) {
6774 case INTEL_OUTPUT_LVDS:
6775 has_panel = true;
6776 has_lvds = true;
6777 break;
6778 case INTEL_OUTPUT_EDP:
6779 has_panel = true;
6780 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6781 has_cpu_edp = true;
6782 break;
6783 default:
6784 break;
6785 }
6786 }
6787
6788 if (HAS_PCH_IBX(dev)) {
6789 has_ck505 = dev_priv->vbt.display_clock_mode;
6790 can_ssc = has_ck505;
6791 } else {
6792 has_ck505 = false;
6793 can_ssc = true;
6794 }
6795
6796 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6797 has_panel, has_lvds, has_ck505);
6798
6799 /* Ironlake: try to setup display ref clock before DPLL
6800 * enabling. This is only under driver's control after
6801 * PCH B stepping, previous chipset stepping should be
6802 * ignoring this setting.
6803 */
6804 val = I915_READ(PCH_DREF_CONTROL);
6805
6806 /* As we must carefully and slowly disable/enable each source in turn,
6807 * compute the final state we want first and check if we need to
6808 * make any changes at all.
6809 */
6810 final = val;
6811 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6812 if (has_ck505)
6813 final |= DREF_NONSPREAD_CK505_ENABLE;
6814 else
6815 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6816
6817 final &= ~DREF_SSC_SOURCE_MASK;
6818 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6819 final &= ~DREF_SSC1_ENABLE;
6820
6821 if (has_panel) {
6822 final |= DREF_SSC_SOURCE_ENABLE;
6823
6824 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6825 final |= DREF_SSC1_ENABLE;
6826
6827 if (has_cpu_edp) {
6828 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6829 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6830 else
6831 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6832 } else
6833 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6834 } else {
6835 final |= DREF_SSC_SOURCE_DISABLE;
6836 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6837 }
6838
6839 if (final == val)
6840 return;
6841
6842 /* Always enable nonspread source */
6843 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6844
6845 if (has_ck505)
6846 val |= DREF_NONSPREAD_CK505_ENABLE;
6847 else
6848 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6849
6850 if (has_panel) {
6851 val &= ~DREF_SSC_SOURCE_MASK;
6852 val |= DREF_SSC_SOURCE_ENABLE;
6853
6854 /* SSC must be turned on before enabling the CPU output */
6855 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6856 DRM_DEBUG_KMS("Using SSC on panel\n");
6857 val |= DREF_SSC1_ENABLE;
6858 } else
6859 val &= ~DREF_SSC1_ENABLE;
6860
6861 /* Get SSC going before enabling the outputs */
6862 I915_WRITE(PCH_DREF_CONTROL, val);
6863 POSTING_READ(PCH_DREF_CONTROL);
6864 udelay(200);
6865
6866 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6867
6868 /* Enable CPU source on CPU attached eDP */
6869 if (has_cpu_edp) {
6870 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6871 DRM_DEBUG_KMS("Using SSC on eDP\n");
6872 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6873 } else
6874 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6875 } else
6876 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6877
6878 I915_WRITE(PCH_DREF_CONTROL, val);
6879 POSTING_READ(PCH_DREF_CONTROL);
6880 udelay(200);
6881 } else {
6882 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6883
6884 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6885
6886 /* Turn off CPU output */
6887 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6888
6889 I915_WRITE(PCH_DREF_CONTROL, val);
6890 POSTING_READ(PCH_DREF_CONTROL);
6891 udelay(200);
6892
6893 /* Turn off the SSC source */
6894 val &= ~DREF_SSC_SOURCE_MASK;
6895 val |= DREF_SSC_SOURCE_DISABLE;
6896
6897 /* Turn off SSC1 */
6898 val &= ~DREF_SSC1_ENABLE;
6899
6900 I915_WRITE(PCH_DREF_CONTROL, val);
6901 POSTING_READ(PCH_DREF_CONTROL);
6902 udelay(200);
6903 }
6904
6905 BUG_ON(val != final);
6906 }
6907
6908 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6909 {
6910 uint32_t tmp;
6911
6912 tmp = I915_READ(SOUTH_CHICKEN2);
6913 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6914 I915_WRITE(SOUTH_CHICKEN2, tmp);
6915
6916 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6917 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6918 DRM_ERROR("FDI mPHY reset assert timeout\n");
6919
6920 tmp = I915_READ(SOUTH_CHICKEN2);
6921 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6922 I915_WRITE(SOUTH_CHICKEN2, tmp);
6923
6924 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6925 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6926 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6927 }
6928
6929 /* WaMPhyProgramming:hsw */
6930 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6931 {
6932 uint32_t tmp;
6933
6934 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6935 tmp &= ~(0xFF << 24);
6936 tmp |= (0x12 << 24);
6937 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6938
6939 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6940 tmp |= (1 << 11);
6941 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6942
6943 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6944 tmp |= (1 << 11);
6945 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6946
6947 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6948 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6949 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6950
6951 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6952 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6953 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6954
6955 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6956 tmp &= ~(7 << 13);
6957 tmp |= (5 << 13);
6958 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6959
6960 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6961 tmp &= ~(7 << 13);
6962 tmp |= (5 << 13);
6963 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6964
6965 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6966 tmp &= ~0xFF;
6967 tmp |= 0x1C;
6968 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6969
6970 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6971 tmp &= ~0xFF;
6972 tmp |= 0x1C;
6973 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6974
6975 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6976 tmp &= ~(0xFF << 16);
6977 tmp |= (0x1C << 16);
6978 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6979
6980 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6981 tmp &= ~(0xFF << 16);
6982 tmp |= (0x1C << 16);
6983 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6984
6985 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6986 tmp |= (1 << 27);
6987 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6988
6989 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6990 tmp |= (1 << 27);
6991 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6992
6993 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6994 tmp &= ~(0xF << 28);
6995 tmp |= (4 << 28);
6996 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6997
6998 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6999 tmp &= ~(0xF << 28);
7000 tmp |= (4 << 28);
7001 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7002 }
7003
7004 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7005 * Programming" based on the parameters passed:
7006 * - Sequence to enable CLKOUT_DP
7007 * - Sequence to enable CLKOUT_DP without spread
7008 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7009 */
7010 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7011 bool with_fdi)
7012 {
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 uint32_t reg, tmp;
7015
7016 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7017 with_spread = true;
7018 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7019 with_fdi, "LP PCH doesn't have FDI\n"))
7020 with_fdi = false;
7021
7022 mutex_lock(&dev_priv->dpio_lock);
7023
7024 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7025 tmp &= ~SBI_SSCCTL_DISABLE;
7026 tmp |= SBI_SSCCTL_PATHALT;
7027 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7028
7029 udelay(24);
7030
7031 if (with_spread) {
7032 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7033 tmp &= ~SBI_SSCCTL_PATHALT;
7034 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7035
7036 if (with_fdi) {
7037 lpt_reset_fdi_mphy(dev_priv);
7038 lpt_program_fdi_mphy(dev_priv);
7039 }
7040 }
7041
7042 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7043 SBI_GEN0 : SBI_DBUFF0;
7044 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7045 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7046 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7047
7048 mutex_unlock(&dev_priv->dpio_lock);
7049 }
7050
7051 /* Sequence to disable CLKOUT_DP */
7052 static void lpt_disable_clkout_dp(struct drm_device *dev)
7053 {
7054 struct drm_i915_private *dev_priv = dev->dev_private;
7055 uint32_t reg, tmp;
7056
7057 mutex_lock(&dev_priv->dpio_lock);
7058
7059 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7060 SBI_GEN0 : SBI_DBUFF0;
7061 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7062 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7063 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7064
7065 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7066 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7067 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7068 tmp |= SBI_SSCCTL_PATHALT;
7069 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7070 udelay(32);
7071 }
7072 tmp |= SBI_SSCCTL_DISABLE;
7073 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7074 }
7075
7076 mutex_unlock(&dev_priv->dpio_lock);
7077 }
7078
7079 static void lpt_init_pch_refclk(struct drm_device *dev)
7080 {
7081 struct intel_encoder *encoder;
7082 bool has_vga = false;
7083
7084 for_each_intel_encoder(dev, encoder) {
7085 switch (encoder->type) {
7086 case INTEL_OUTPUT_ANALOG:
7087 has_vga = true;
7088 break;
7089 default:
7090 break;
7091 }
7092 }
7093
7094 if (has_vga)
7095 lpt_enable_clkout_dp(dev, true, true);
7096 else
7097 lpt_disable_clkout_dp(dev);
7098 }
7099
7100 /*
7101 * Initialize reference clocks when the driver loads
7102 */
7103 void intel_init_pch_refclk(struct drm_device *dev)
7104 {
7105 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7106 ironlake_init_pch_refclk(dev);
7107 else if (HAS_PCH_LPT(dev))
7108 lpt_init_pch_refclk(dev);
7109 }
7110
7111 static int ironlake_get_refclk(struct drm_crtc *crtc)
7112 {
7113 struct drm_device *dev = crtc->dev;
7114 struct drm_i915_private *dev_priv = dev->dev_private;
7115 struct intel_encoder *encoder;
7116 int num_connectors = 0;
7117 bool is_lvds = false;
7118
7119 for_each_intel_encoder(dev, encoder) {
7120 if (encoder->new_crtc != to_intel_crtc(crtc))
7121 continue;
7122
7123 switch (encoder->type) {
7124 case INTEL_OUTPUT_LVDS:
7125 is_lvds = true;
7126 break;
7127 default:
7128 break;
7129 }
7130 num_connectors++;
7131 }
7132
7133 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7134 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7135 dev_priv->vbt.lvds_ssc_freq);
7136 return dev_priv->vbt.lvds_ssc_freq;
7137 }
7138
7139 return 120000;
7140 }
7141
7142 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7143 {
7144 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7146 int pipe = intel_crtc->pipe;
7147 uint32_t val;
7148
7149 val = 0;
7150
7151 switch (intel_crtc->config->pipe_bpp) {
7152 case 18:
7153 val |= PIPECONF_6BPC;
7154 break;
7155 case 24:
7156 val |= PIPECONF_8BPC;
7157 break;
7158 case 30:
7159 val |= PIPECONF_10BPC;
7160 break;
7161 case 36:
7162 val |= PIPECONF_12BPC;
7163 break;
7164 default:
7165 /* Case prevented by intel_choose_pipe_bpp_dither. */
7166 BUG();
7167 }
7168
7169 if (intel_crtc->config->dither)
7170 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7171
7172 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7173 val |= PIPECONF_INTERLACED_ILK;
7174 else
7175 val |= PIPECONF_PROGRESSIVE;
7176
7177 if (intel_crtc->config->limited_color_range)
7178 val |= PIPECONF_COLOR_RANGE_SELECT;
7179
7180 I915_WRITE(PIPECONF(pipe), val);
7181 POSTING_READ(PIPECONF(pipe));
7182 }
7183
7184 /*
7185 * Set up the pipe CSC unit.
7186 *
7187 * Currently only full range RGB to limited range RGB conversion
7188 * is supported, but eventually this should handle various
7189 * RGB<->YCbCr scenarios as well.
7190 */
7191 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7192 {
7193 struct drm_device *dev = crtc->dev;
7194 struct drm_i915_private *dev_priv = dev->dev_private;
7195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7196 int pipe = intel_crtc->pipe;
7197 uint16_t coeff = 0x7800; /* 1.0 */
7198
7199 /*
7200 * TODO: Check what kind of values actually come out of the pipe
7201 * with these coeff/postoff values and adjust to get the best
7202 * accuracy. Perhaps we even need to take the bpc value into
7203 * consideration.
7204 */
7205
7206 if (intel_crtc->config->limited_color_range)
7207 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7208
7209 /*
7210 * GY/GU and RY/RU should be the other way around according
7211 * to BSpec, but reality doesn't agree. Just set them up in
7212 * a way that results in the correct picture.
7213 */
7214 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7215 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7216
7217 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7218 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7219
7220 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7221 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7222
7223 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7224 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7225 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7226
7227 if (INTEL_INFO(dev)->gen > 6) {
7228 uint16_t postoff = 0;
7229
7230 if (intel_crtc->config->limited_color_range)
7231 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7232
7233 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7234 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7235 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7236
7237 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7238 } else {
7239 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7240
7241 if (intel_crtc->config->limited_color_range)
7242 mode |= CSC_BLACK_SCREEN_OFFSET;
7243
7244 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7245 }
7246 }
7247
7248 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7249 {
7250 struct drm_device *dev = crtc->dev;
7251 struct drm_i915_private *dev_priv = dev->dev_private;
7252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7253 enum pipe pipe = intel_crtc->pipe;
7254 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7255 uint32_t val;
7256
7257 val = 0;
7258
7259 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7260 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7261
7262 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7263 val |= PIPECONF_INTERLACED_ILK;
7264 else
7265 val |= PIPECONF_PROGRESSIVE;
7266
7267 I915_WRITE(PIPECONF(cpu_transcoder), val);
7268 POSTING_READ(PIPECONF(cpu_transcoder));
7269
7270 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7271 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7272
7273 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7274 val = 0;
7275
7276 switch (intel_crtc->config->pipe_bpp) {
7277 case 18:
7278 val |= PIPEMISC_DITHER_6_BPC;
7279 break;
7280 case 24:
7281 val |= PIPEMISC_DITHER_8_BPC;
7282 break;
7283 case 30:
7284 val |= PIPEMISC_DITHER_10_BPC;
7285 break;
7286 case 36:
7287 val |= PIPEMISC_DITHER_12_BPC;
7288 break;
7289 default:
7290 /* Case prevented by pipe_config_set_bpp. */
7291 BUG();
7292 }
7293
7294 if (intel_crtc->config->dither)
7295 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7296
7297 I915_WRITE(PIPEMISC(pipe), val);
7298 }
7299 }
7300
7301 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7302 struct intel_crtc_state *crtc_state,
7303 intel_clock_t *clock,
7304 bool *has_reduced_clock,
7305 intel_clock_t *reduced_clock)
7306 {
7307 struct drm_device *dev = crtc->dev;
7308 struct drm_i915_private *dev_priv = dev->dev_private;
7309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7310 int refclk;
7311 const intel_limit_t *limit;
7312 bool ret, is_lvds = false;
7313
7314 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7315
7316 refclk = ironlake_get_refclk(crtc);
7317
7318 /*
7319 * Returns a set of divisors for the desired target clock with the given
7320 * refclk, or FALSE. The returned values represent the clock equation:
7321 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7322 */
7323 limit = intel_limit(intel_crtc, refclk);
7324 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7325 crtc_state->port_clock,
7326 refclk, NULL, clock);
7327 if (!ret)
7328 return false;
7329
7330 if (is_lvds && dev_priv->lvds_downclock_avail) {
7331 /*
7332 * Ensure we match the reduced clock's P to the target clock.
7333 * If the clocks don't match, we can't switch the display clock
7334 * by using the FP0/FP1. In such case we will disable the LVDS
7335 * downclock feature.
7336 */
7337 *has_reduced_clock =
7338 dev_priv->display.find_dpll(limit, intel_crtc,
7339 dev_priv->lvds_downclock,
7340 refclk, clock,
7341 reduced_clock);
7342 }
7343
7344 return true;
7345 }
7346
7347 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7348 {
7349 /*
7350 * Account for spread spectrum to avoid
7351 * oversubscribing the link. Max center spread
7352 * is 2.5%; use 5% for safety's sake.
7353 */
7354 u32 bps = target_clock * bpp * 21 / 20;
7355 return DIV_ROUND_UP(bps, link_bw * 8);
7356 }
7357
7358 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7359 {
7360 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7361 }
7362
7363 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7364 struct intel_crtc_state *crtc_state,
7365 u32 *fp,
7366 intel_clock_t *reduced_clock, u32 *fp2)
7367 {
7368 struct drm_crtc *crtc = &intel_crtc->base;
7369 struct drm_device *dev = crtc->dev;
7370 struct drm_i915_private *dev_priv = dev->dev_private;
7371 struct intel_encoder *intel_encoder;
7372 uint32_t dpll;
7373 int factor, num_connectors = 0;
7374 bool is_lvds = false, is_sdvo = false;
7375
7376 for_each_intel_encoder(dev, intel_encoder) {
7377 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7378 continue;
7379
7380 switch (intel_encoder->type) {
7381 case INTEL_OUTPUT_LVDS:
7382 is_lvds = true;
7383 break;
7384 case INTEL_OUTPUT_SDVO:
7385 case INTEL_OUTPUT_HDMI:
7386 is_sdvo = true;
7387 break;
7388 default:
7389 break;
7390 }
7391
7392 num_connectors++;
7393 }
7394
7395 /* Enable autotuning of the PLL clock (if permissible) */
7396 factor = 21;
7397 if (is_lvds) {
7398 if ((intel_panel_use_ssc(dev_priv) &&
7399 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7400 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7401 factor = 25;
7402 } else if (crtc_state->sdvo_tv_clock)
7403 factor = 20;
7404
7405 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7406 *fp |= FP_CB_TUNE;
7407
7408 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7409 *fp2 |= FP_CB_TUNE;
7410
7411 dpll = 0;
7412
7413 if (is_lvds)
7414 dpll |= DPLLB_MODE_LVDS;
7415 else
7416 dpll |= DPLLB_MODE_DAC_SERIAL;
7417
7418 dpll |= (crtc_state->pixel_multiplier - 1)
7419 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7420
7421 if (is_sdvo)
7422 dpll |= DPLL_SDVO_HIGH_SPEED;
7423 if (crtc_state->has_dp_encoder)
7424 dpll |= DPLL_SDVO_HIGH_SPEED;
7425
7426 /* compute bitmask from p1 value */
7427 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7428 /* also FPA1 */
7429 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7430
7431 switch (crtc_state->dpll.p2) {
7432 case 5:
7433 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7434 break;
7435 case 7:
7436 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7437 break;
7438 case 10:
7439 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7440 break;
7441 case 14:
7442 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7443 break;
7444 }
7445
7446 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7447 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7448 else
7449 dpll |= PLL_REF_INPUT_DREFCLK;
7450
7451 return dpll | DPLL_VCO_ENABLE;
7452 }
7453
7454 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7455 struct intel_crtc_state *crtc_state)
7456 {
7457 struct drm_device *dev = crtc->base.dev;
7458 intel_clock_t clock, reduced_clock;
7459 u32 dpll = 0, fp = 0, fp2 = 0;
7460 bool ok, has_reduced_clock = false;
7461 bool is_lvds = false;
7462 struct intel_shared_dpll *pll;
7463
7464 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7465
7466 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7467 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7468
7469 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7470 &has_reduced_clock, &reduced_clock);
7471 if (!ok && !crtc_state->clock_set) {
7472 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7473 return -EINVAL;
7474 }
7475 /* Compat-code for transition, will disappear. */
7476 if (!crtc_state->clock_set) {
7477 crtc_state->dpll.n = clock.n;
7478 crtc_state->dpll.m1 = clock.m1;
7479 crtc_state->dpll.m2 = clock.m2;
7480 crtc_state->dpll.p1 = clock.p1;
7481 crtc_state->dpll.p2 = clock.p2;
7482 }
7483
7484 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7485 if (crtc_state->has_pch_encoder) {
7486 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7487 if (has_reduced_clock)
7488 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7489
7490 dpll = ironlake_compute_dpll(crtc, crtc_state,
7491 &fp, &reduced_clock,
7492 has_reduced_clock ? &fp2 : NULL);
7493
7494 crtc_state->dpll_hw_state.dpll = dpll;
7495 crtc_state->dpll_hw_state.fp0 = fp;
7496 if (has_reduced_clock)
7497 crtc_state->dpll_hw_state.fp1 = fp2;
7498 else
7499 crtc_state->dpll_hw_state.fp1 = fp;
7500
7501 pll = intel_get_shared_dpll(crtc, crtc_state);
7502 if (pll == NULL) {
7503 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7504 pipe_name(crtc->pipe));
7505 return -EINVAL;
7506 }
7507 }
7508
7509 if (is_lvds && has_reduced_clock && i915.powersave)
7510 crtc->lowfreq_avail = true;
7511 else
7512 crtc->lowfreq_avail = false;
7513
7514 return 0;
7515 }
7516
7517 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7518 struct intel_link_m_n *m_n)
7519 {
7520 struct drm_device *dev = crtc->base.dev;
7521 struct drm_i915_private *dev_priv = dev->dev_private;
7522 enum pipe pipe = crtc->pipe;
7523
7524 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7525 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7526 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7527 & ~TU_SIZE_MASK;
7528 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7529 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7530 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7531 }
7532
7533 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7534 enum transcoder transcoder,
7535 struct intel_link_m_n *m_n,
7536 struct intel_link_m_n *m2_n2)
7537 {
7538 struct drm_device *dev = crtc->base.dev;
7539 struct drm_i915_private *dev_priv = dev->dev_private;
7540 enum pipe pipe = crtc->pipe;
7541
7542 if (INTEL_INFO(dev)->gen >= 5) {
7543 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7544 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7545 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7546 & ~TU_SIZE_MASK;
7547 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7548 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7549 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7550 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7551 * gen < 8) and if DRRS is supported (to make sure the
7552 * registers are not unnecessarily read).
7553 */
7554 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7555 crtc->config->has_drrs) {
7556 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7557 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7558 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7559 & ~TU_SIZE_MASK;
7560 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7561 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7562 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7563 }
7564 } else {
7565 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7566 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7567 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7568 & ~TU_SIZE_MASK;
7569 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7570 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7571 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7572 }
7573 }
7574
7575 void intel_dp_get_m_n(struct intel_crtc *crtc,
7576 struct intel_crtc_state *pipe_config)
7577 {
7578 if (pipe_config->has_pch_encoder)
7579 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7580 else
7581 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7582 &pipe_config->dp_m_n,
7583 &pipe_config->dp_m2_n2);
7584 }
7585
7586 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7587 struct intel_crtc_state *pipe_config)
7588 {
7589 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7590 &pipe_config->fdi_m_n, NULL);
7591 }
7592
7593 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7594 struct intel_crtc_state *pipe_config)
7595 {
7596 struct drm_device *dev = crtc->base.dev;
7597 struct drm_i915_private *dev_priv = dev->dev_private;
7598 uint32_t tmp;
7599
7600 tmp = I915_READ(PS_CTL(crtc->pipe));
7601
7602 if (tmp & PS_ENABLE) {
7603 pipe_config->pch_pfit.enabled = true;
7604 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7605 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7606 }
7607 }
7608
7609 static void
7610 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7611 struct intel_initial_plane_config *plane_config)
7612 {
7613 struct drm_device *dev = crtc->base.dev;
7614 struct drm_i915_private *dev_priv = dev->dev_private;
7615 u32 val, base, offset, stride_mult;
7616 int pipe = crtc->pipe;
7617 int fourcc, pixel_format;
7618 int aligned_height;
7619 struct drm_framebuffer *fb;
7620 struct intel_framebuffer *intel_fb;
7621
7622 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7623 if (!intel_fb) {
7624 DRM_DEBUG_KMS("failed to alloc fb\n");
7625 return;
7626 }
7627
7628 fb = &intel_fb->base;
7629
7630 val = I915_READ(PLANE_CTL(pipe, 0));
7631 if (val & PLANE_CTL_TILED_MASK)
7632 plane_config->tiling = I915_TILING_X;
7633
7634 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7635 fourcc = skl_format_to_fourcc(pixel_format,
7636 val & PLANE_CTL_ORDER_RGBX,
7637 val & PLANE_CTL_ALPHA_MASK);
7638 fb->pixel_format = fourcc;
7639 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7640
7641 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7642 plane_config->base = base;
7643
7644 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7645
7646 val = I915_READ(PLANE_SIZE(pipe, 0));
7647 fb->height = ((val >> 16) & 0xfff) + 1;
7648 fb->width = ((val >> 0) & 0x1fff) + 1;
7649
7650 val = I915_READ(PLANE_STRIDE(pipe, 0));
7651 switch (plane_config->tiling) {
7652 case I915_TILING_NONE:
7653 stride_mult = 64;
7654 break;
7655 case I915_TILING_X:
7656 stride_mult = 512;
7657 break;
7658 default:
7659 MISSING_CASE(plane_config->tiling);
7660 goto error;
7661 }
7662 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7663
7664 aligned_height = intel_fb_align_height(dev, fb->height,
7665 plane_config->tiling);
7666
7667 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7668
7669 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7670 pipe_name(pipe), fb->width, fb->height,
7671 fb->bits_per_pixel, base, fb->pitches[0],
7672 plane_config->size);
7673
7674 crtc->base.primary->fb = fb;
7675 return;
7676
7677 error:
7678 kfree(fb);
7679 }
7680
7681 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7682 struct intel_crtc_state *pipe_config)
7683 {
7684 struct drm_device *dev = crtc->base.dev;
7685 struct drm_i915_private *dev_priv = dev->dev_private;
7686 uint32_t tmp;
7687
7688 tmp = I915_READ(PF_CTL(crtc->pipe));
7689
7690 if (tmp & PF_ENABLE) {
7691 pipe_config->pch_pfit.enabled = true;
7692 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7693 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7694
7695 /* We currently do not free assignements of panel fitters on
7696 * ivb/hsw (since we don't use the higher upscaling modes which
7697 * differentiates them) so just WARN about this case for now. */
7698 if (IS_GEN7(dev)) {
7699 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7700 PF_PIPE_SEL_IVB(crtc->pipe));
7701 }
7702 }
7703 }
7704
7705 static void
7706 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7707 struct intel_initial_plane_config *plane_config)
7708 {
7709 struct drm_device *dev = crtc->base.dev;
7710 struct drm_i915_private *dev_priv = dev->dev_private;
7711 u32 val, base, offset;
7712 int pipe = crtc->pipe;
7713 int fourcc, pixel_format;
7714 int aligned_height;
7715 struct drm_framebuffer *fb;
7716 struct intel_framebuffer *intel_fb;
7717
7718 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7719 if (!intel_fb) {
7720 DRM_DEBUG_KMS("failed to alloc fb\n");
7721 return;
7722 }
7723
7724 fb = &intel_fb->base;
7725
7726 val = I915_READ(DSPCNTR(pipe));
7727
7728 if (INTEL_INFO(dev)->gen >= 4)
7729 if (val & DISPPLANE_TILED)
7730 plane_config->tiling = I915_TILING_X;
7731
7732 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7733 fourcc = i9xx_format_to_fourcc(pixel_format);
7734 fb->pixel_format = fourcc;
7735 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7736
7737 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7738 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7739 offset = I915_READ(DSPOFFSET(pipe));
7740 } else {
7741 if (plane_config->tiling)
7742 offset = I915_READ(DSPTILEOFF(pipe));
7743 else
7744 offset = I915_READ(DSPLINOFF(pipe));
7745 }
7746 plane_config->base = base;
7747
7748 val = I915_READ(PIPESRC(pipe));
7749 fb->width = ((val >> 16) & 0xfff) + 1;
7750 fb->height = ((val >> 0) & 0xfff) + 1;
7751
7752 val = I915_READ(DSPSTRIDE(pipe));
7753 fb->pitches[0] = val & 0xffffffc0;
7754
7755 aligned_height = intel_fb_align_height(dev, fb->height,
7756 plane_config->tiling);
7757
7758 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7759
7760 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7761 pipe_name(pipe), fb->width, fb->height,
7762 fb->bits_per_pixel, base, fb->pitches[0],
7763 plane_config->size);
7764
7765 crtc->base.primary->fb = fb;
7766 }
7767
7768 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7769 struct intel_crtc_state *pipe_config)
7770 {
7771 struct drm_device *dev = crtc->base.dev;
7772 struct drm_i915_private *dev_priv = dev->dev_private;
7773 uint32_t tmp;
7774
7775 if (!intel_display_power_is_enabled(dev_priv,
7776 POWER_DOMAIN_PIPE(crtc->pipe)))
7777 return false;
7778
7779 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7780 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7781
7782 tmp = I915_READ(PIPECONF(crtc->pipe));
7783 if (!(tmp & PIPECONF_ENABLE))
7784 return false;
7785
7786 switch (tmp & PIPECONF_BPC_MASK) {
7787 case PIPECONF_6BPC:
7788 pipe_config->pipe_bpp = 18;
7789 break;
7790 case PIPECONF_8BPC:
7791 pipe_config->pipe_bpp = 24;
7792 break;
7793 case PIPECONF_10BPC:
7794 pipe_config->pipe_bpp = 30;
7795 break;
7796 case PIPECONF_12BPC:
7797 pipe_config->pipe_bpp = 36;
7798 break;
7799 default:
7800 break;
7801 }
7802
7803 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7804 pipe_config->limited_color_range = true;
7805
7806 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7807 struct intel_shared_dpll *pll;
7808
7809 pipe_config->has_pch_encoder = true;
7810
7811 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7812 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7813 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7814
7815 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7816
7817 if (HAS_PCH_IBX(dev_priv->dev)) {
7818 pipe_config->shared_dpll =
7819 (enum intel_dpll_id) crtc->pipe;
7820 } else {
7821 tmp = I915_READ(PCH_DPLL_SEL);
7822 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7823 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7824 else
7825 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7826 }
7827
7828 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7829
7830 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7831 &pipe_config->dpll_hw_state));
7832
7833 tmp = pipe_config->dpll_hw_state.dpll;
7834 pipe_config->pixel_multiplier =
7835 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7836 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7837
7838 ironlake_pch_clock_get(crtc, pipe_config);
7839 } else {
7840 pipe_config->pixel_multiplier = 1;
7841 }
7842
7843 intel_get_pipe_timings(crtc, pipe_config);
7844
7845 ironlake_get_pfit_config(crtc, pipe_config);
7846
7847 return true;
7848 }
7849
7850 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7851 {
7852 struct drm_device *dev = dev_priv->dev;
7853 struct intel_crtc *crtc;
7854
7855 for_each_intel_crtc(dev, crtc)
7856 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7857 pipe_name(crtc->pipe));
7858
7859 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7860 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7861 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7862 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7863 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7864 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7865 "CPU PWM1 enabled\n");
7866 if (IS_HASWELL(dev))
7867 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7868 "CPU PWM2 enabled\n");
7869 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7870 "PCH PWM1 enabled\n");
7871 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7872 "Utility pin enabled\n");
7873 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7874
7875 /*
7876 * In theory we can still leave IRQs enabled, as long as only the HPD
7877 * interrupts remain enabled. We used to check for that, but since it's
7878 * gen-specific and since we only disable LCPLL after we fully disable
7879 * the interrupts, the check below should be enough.
7880 */
7881 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7882 }
7883
7884 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7885 {
7886 struct drm_device *dev = dev_priv->dev;
7887
7888 if (IS_HASWELL(dev))
7889 return I915_READ(D_COMP_HSW);
7890 else
7891 return I915_READ(D_COMP_BDW);
7892 }
7893
7894 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7895 {
7896 struct drm_device *dev = dev_priv->dev;
7897
7898 if (IS_HASWELL(dev)) {
7899 mutex_lock(&dev_priv->rps.hw_lock);
7900 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7901 val))
7902 DRM_ERROR("Failed to write to D_COMP\n");
7903 mutex_unlock(&dev_priv->rps.hw_lock);
7904 } else {
7905 I915_WRITE(D_COMP_BDW, val);
7906 POSTING_READ(D_COMP_BDW);
7907 }
7908 }
7909
7910 /*
7911 * This function implements pieces of two sequences from BSpec:
7912 * - Sequence for display software to disable LCPLL
7913 * - Sequence for display software to allow package C8+
7914 * The steps implemented here are just the steps that actually touch the LCPLL
7915 * register. Callers should take care of disabling all the display engine
7916 * functions, doing the mode unset, fixing interrupts, etc.
7917 */
7918 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7919 bool switch_to_fclk, bool allow_power_down)
7920 {
7921 uint32_t val;
7922
7923 assert_can_disable_lcpll(dev_priv);
7924
7925 val = I915_READ(LCPLL_CTL);
7926
7927 if (switch_to_fclk) {
7928 val |= LCPLL_CD_SOURCE_FCLK;
7929 I915_WRITE(LCPLL_CTL, val);
7930
7931 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7932 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7933 DRM_ERROR("Switching to FCLK failed\n");
7934
7935 val = I915_READ(LCPLL_CTL);
7936 }
7937
7938 val |= LCPLL_PLL_DISABLE;
7939 I915_WRITE(LCPLL_CTL, val);
7940 POSTING_READ(LCPLL_CTL);
7941
7942 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7943 DRM_ERROR("LCPLL still locked\n");
7944
7945 val = hsw_read_dcomp(dev_priv);
7946 val |= D_COMP_COMP_DISABLE;
7947 hsw_write_dcomp(dev_priv, val);
7948 ndelay(100);
7949
7950 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7951 1))
7952 DRM_ERROR("D_COMP RCOMP still in progress\n");
7953
7954 if (allow_power_down) {
7955 val = I915_READ(LCPLL_CTL);
7956 val |= LCPLL_POWER_DOWN_ALLOW;
7957 I915_WRITE(LCPLL_CTL, val);
7958 POSTING_READ(LCPLL_CTL);
7959 }
7960 }
7961
7962 /*
7963 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7964 * source.
7965 */
7966 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7967 {
7968 uint32_t val;
7969
7970 val = I915_READ(LCPLL_CTL);
7971
7972 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7973 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7974 return;
7975
7976 /*
7977 * Make sure we're not on PC8 state before disabling PC8, otherwise
7978 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7979 */
7980 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7981
7982 if (val & LCPLL_POWER_DOWN_ALLOW) {
7983 val &= ~LCPLL_POWER_DOWN_ALLOW;
7984 I915_WRITE(LCPLL_CTL, val);
7985 POSTING_READ(LCPLL_CTL);
7986 }
7987
7988 val = hsw_read_dcomp(dev_priv);
7989 val |= D_COMP_COMP_FORCE;
7990 val &= ~D_COMP_COMP_DISABLE;
7991 hsw_write_dcomp(dev_priv, val);
7992
7993 val = I915_READ(LCPLL_CTL);
7994 val &= ~LCPLL_PLL_DISABLE;
7995 I915_WRITE(LCPLL_CTL, val);
7996
7997 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7998 DRM_ERROR("LCPLL not locked yet\n");
7999
8000 if (val & LCPLL_CD_SOURCE_FCLK) {
8001 val = I915_READ(LCPLL_CTL);
8002 val &= ~LCPLL_CD_SOURCE_FCLK;
8003 I915_WRITE(LCPLL_CTL, val);
8004
8005 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8006 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8007 DRM_ERROR("Switching back to LCPLL failed\n");
8008 }
8009
8010 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8011 }
8012
8013 /*
8014 * Package states C8 and deeper are really deep PC states that can only be
8015 * reached when all the devices on the system allow it, so even if the graphics
8016 * device allows PC8+, it doesn't mean the system will actually get to these
8017 * states. Our driver only allows PC8+ when going into runtime PM.
8018 *
8019 * The requirements for PC8+ are that all the outputs are disabled, the power
8020 * well is disabled and most interrupts are disabled, and these are also
8021 * requirements for runtime PM. When these conditions are met, we manually do
8022 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8023 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8024 * hang the machine.
8025 *
8026 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8027 * the state of some registers, so when we come back from PC8+ we need to
8028 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8029 * need to take care of the registers kept by RC6. Notice that this happens even
8030 * if we don't put the device in PCI D3 state (which is what currently happens
8031 * because of the runtime PM support).
8032 *
8033 * For more, read "Display Sequences for Package C8" on the hardware
8034 * documentation.
8035 */
8036 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8037 {
8038 struct drm_device *dev = dev_priv->dev;
8039 uint32_t val;
8040
8041 DRM_DEBUG_KMS("Enabling package C8+\n");
8042
8043 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8044 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8045 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8046 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8047 }
8048
8049 lpt_disable_clkout_dp(dev);
8050 hsw_disable_lcpll(dev_priv, true, true);
8051 }
8052
8053 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8054 {
8055 struct drm_device *dev = dev_priv->dev;
8056 uint32_t val;
8057
8058 DRM_DEBUG_KMS("Disabling package C8+\n");
8059
8060 hsw_restore_lcpll(dev_priv);
8061 lpt_init_pch_refclk(dev);
8062
8063 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8064 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8065 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8066 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8067 }
8068
8069 intel_prepare_ddi(dev);
8070 }
8071
8072 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8073 struct intel_crtc_state *crtc_state)
8074 {
8075 if (!intel_ddi_pll_select(crtc, crtc_state))
8076 return -EINVAL;
8077
8078 crtc->lowfreq_avail = false;
8079
8080 return 0;
8081 }
8082
8083 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8084 enum port port,
8085 struct intel_crtc_state *pipe_config)
8086 {
8087 u32 temp, dpll_ctl1;
8088
8089 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8090 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8091
8092 switch (pipe_config->ddi_pll_sel) {
8093 case SKL_DPLL0:
8094 /*
8095 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8096 * of the shared DPLL framework and thus needs to be read out
8097 * separately
8098 */
8099 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8100 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8101 break;
8102 case SKL_DPLL1:
8103 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8104 break;
8105 case SKL_DPLL2:
8106 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8107 break;
8108 case SKL_DPLL3:
8109 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8110 break;
8111 }
8112 }
8113
8114 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8115 enum port port,
8116 struct intel_crtc_state *pipe_config)
8117 {
8118 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8119
8120 switch (pipe_config->ddi_pll_sel) {
8121 case PORT_CLK_SEL_WRPLL1:
8122 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8123 break;
8124 case PORT_CLK_SEL_WRPLL2:
8125 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8126 break;
8127 }
8128 }
8129
8130 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8131 struct intel_crtc_state *pipe_config)
8132 {
8133 struct drm_device *dev = crtc->base.dev;
8134 struct drm_i915_private *dev_priv = dev->dev_private;
8135 struct intel_shared_dpll *pll;
8136 enum port port;
8137 uint32_t tmp;
8138
8139 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8140
8141 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8142
8143 if (IS_SKYLAKE(dev))
8144 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8145 else
8146 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8147
8148 if (pipe_config->shared_dpll >= 0) {
8149 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8150
8151 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8152 &pipe_config->dpll_hw_state));
8153 }
8154
8155 /*
8156 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8157 * DDI E. So just check whether this pipe is wired to DDI E and whether
8158 * the PCH transcoder is on.
8159 */
8160 if (INTEL_INFO(dev)->gen < 9 &&
8161 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8162 pipe_config->has_pch_encoder = true;
8163
8164 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8165 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8166 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8167
8168 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8169 }
8170 }
8171
8172 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8173 struct intel_crtc_state *pipe_config)
8174 {
8175 struct drm_device *dev = crtc->base.dev;
8176 struct drm_i915_private *dev_priv = dev->dev_private;
8177 enum intel_display_power_domain pfit_domain;
8178 uint32_t tmp;
8179
8180 if (!intel_display_power_is_enabled(dev_priv,
8181 POWER_DOMAIN_PIPE(crtc->pipe)))
8182 return false;
8183
8184 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8185 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8186
8187 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8188 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8189 enum pipe trans_edp_pipe;
8190 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8191 default:
8192 WARN(1, "unknown pipe linked to edp transcoder\n");
8193 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8194 case TRANS_DDI_EDP_INPUT_A_ON:
8195 trans_edp_pipe = PIPE_A;
8196 break;
8197 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8198 trans_edp_pipe = PIPE_B;
8199 break;
8200 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8201 trans_edp_pipe = PIPE_C;
8202 break;
8203 }
8204
8205 if (trans_edp_pipe == crtc->pipe)
8206 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8207 }
8208
8209 if (!intel_display_power_is_enabled(dev_priv,
8210 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8211 return false;
8212
8213 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8214 if (!(tmp & PIPECONF_ENABLE))
8215 return false;
8216
8217 haswell_get_ddi_port_state(crtc, pipe_config);
8218
8219 intel_get_pipe_timings(crtc, pipe_config);
8220
8221 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8222 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8223 if (IS_SKYLAKE(dev))
8224 skylake_get_pfit_config(crtc, pipe_config);
8225 else
8226 ironlake_get_pfit_config(crtc, pipe_config);
8227 }
8228
8229 if (IS_HASWELL(dev))
8230 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8231 (I915_READ(IPS_CTL) & IPS_ENABLE);
8232
8233 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8234 pipe_config->pixel_multiplier =
8235 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8236 } else {
8237 pipe_config->pixel_multiplier = 1;
8238 }
8239
8240 return true;
8241 }
8242
8243 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8244 {
8245 struct drm_device *dev = crtc->dev;
8246 struct drm_i915_private *dev_priv = dev->dev_private;
8247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8248 uint32_t cntl = 0, size = 0;
8249
8250 if (base) {
8251 unsigned int width = intel_crtc->cursor_width;
8252 unsigned int height = intel_crtc->cursor_height;
8253 unsigned int stride = roundup_pow_of_two(width) * 4;
8254
8255 switch (stride) {
8256 default:
8257 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8258 width, stride);
8259 stride = 256;
8260 /* fallthrough */
8261 case 256:
8262 case 512:
8263 case 1024:
8264 case 2048:
8265 break;
8266 }
8267
8268 cntl |= CURSOR_ENABLE |
8269 CURSOR_GAMMA_ENABLE |
8270 CURSOR_FORMAT_ARGB |
8271 CURSOR_STRIDE(stride);
8272
8273 size = (height << 12) | width;
8274 }
8275
8276 if (intel_crtc->cursor_cntl != 0 &&
8277 (intel_crtc->cursor_base != base ||
8278 intel_crtc->cursor_size != size ||
8279 intel_crtc->cursor_cntl != cntl)) {
8280 /* On these chipsets we can only modify the base/size/stride
8281 * whilst the cursor is disabled.
8282 */
8283 I915_WRITE(_CURACNTR, 0);
8284 POSTING_READ(_CURACNTR);
8285 intel_crtc->cursor_cntl = 0;
8286 }
8287
8288 if (intel_crtc->cursor_base != base) {
8289 I915_WRITE(_CURABASE, base);
8290 intel_crtc->cursor_base = base;
8291 }
8292
8293 if (intel_crtc->cursor_size != size) {
8294 I915_WRITE(CURSIZE, size);
8295 intel_crtc->cursor_size = size;
8296 }
8297
8298 if (intel_crtc->cursor_cntl != cntl) {
8299 I915_WRITE(_CURACNTR, cntl);
8300 POSTING_READ(_CURACNTR);
8301 intel_crtc->cursor_cntl = cntl;
8302 }
8303 }
8304
8305 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8306 {
8307 struct drm_device *dev = crtc->dev;
8308 struct drm_i915_private *dev_priv = dev->dev_private;
8309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8310 int pipe = intel_crtc->pipe;
8311 uint32_t cntl;
8312
8313 cntl = 0;
8314 if (base) {
8315 cntl = MCURSOR_GAMMA_ENABLE;
8316 switch (intel_crtc->cursor_width) {
8317 case 64:
8318 cntl |= CURSOR_MODE_64_ARGB_AX;
8319 break;
8320 case 128:
8321 cntl |= CURSOR_MODE_128_ARGB_AX;
8322 break;
8323 case 256:
8324 cntl |= CURSOR_MODE_256_ARGB_AX;
8325 break;
8326 default:
8327 MISSING_CASE(intel_crtc->cursor_width);
8328 return;
8329 }
8330 cntl |= pipe << 28; /* Connect to correct pipe */
8331
8332 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8333 cntl |= CURSOR_PIPE_CSC_ENABLE;
8334 }
8335
8336 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8337 cntl |= CURSOR_ROTATE_180;
8338
8339 if (intel_crtc->cursor_cntl != cntl) {
8340 I915_WRITE(CURCNTR(pipe), cntl);
8341 POSTING_READ(CURCNTR(pipe));
8342 intel_crtc->cursor_cntl = cntl;
8343 }
8344
8345 /* and commit changes on next vblank */
8346 I915_WRITE(CURBASE(pipe), base);
8347 POSTING_READ(CURBASE(pipe));
8348
8349 intel_crtc->cursor_base = base;
8350 }
8351
8352 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8353 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8354 bool on)
8355 {
8356 struct drm_device *dev = crtc->dev;
8357 struct drm_i915_private *dev_priv = dev->dev_private;
8358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8359 int pipe = intel_crtc->pipe;
8360 int x = crtc->cursor_x;
8361 int y = crtc->cursor_y;
8362 u32 base = 0, pos = 0;
8363
8364 if (on)
8365 base = intel_crtc->cursor_addr;
8366
8367 if (x >= intel_crtc->config->pipe_src_w)
8368 base = 0;
8369
8370 if (y >= intel_crtc->config->pipe_src_h)
8371 base = 0;
8372
8373 if (x < 0) {
8374 if (x + intel_crtc->cursor_width <= 0)
8375 base = 0;
8376
8377 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8378 x = -x;
8379 }
8380 pos |= x << CURSOR_X_SHIFT;
8381
8382 if (y < 0) {
8383 if (y + intel_crtc->cursor_height <= 0)
8384 base = 0;
8385
8386 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8387 y = -y;
8388 }
8389 pos |= y << CURSOR_Y_SHIFT;
8390
8391 if (base == 0 && intel_crtc->cursor_base == 0)
8392 return;
8393
8394 I915_WRITE(CURPOS(pipe), pos);
8395
8396 /* ILK+ do this automagically */
8397 if (HAS_GMCH_DISPLAY(dev) &&
8398 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8399 base += (intel_crtc->cursor_height *
8400 intel_crtc->cursor_width - 1) * 4;
8401 }
8402
8403 if (IS_845G(dev) || IS_I865G(dev))
8404 i845_update_cursor(crtc, base);
8405 else
8406 i9xx_update_cursor(crtc, base);
8407 }
8408
8409 static bool cursor_size_ok(struct drm_device *dev,
8410 uint32_t width, uint32_t height)
8411 {
8412 if (width == 0 || height == 0)
8413 return false;
8414
8415 /*
8416 * 845g/865g are special in that they are only limited by
8417 * the width of their cursors, the height is arbitrary up to
8418 * the precision of the register. Everything else requires
8419 * square cursors, limited to a few power-of-two sizes.
8420 */
8421 if (IS_845G(dev) || IS_I865G(dev)) {
8422 if ((width & 63) != 0)
8423 return false;
8424
8425 if (width > (IS_845G(dev) ? 64 : 512))
8426 return false;
8427
8428 if (height > 1023)
8429 return false;
8430 } else {
8431 switch (width | height) {
8432 case 256:
8433 case 128:
8434 if (IS_GEN2(dev))
8435 return false;
8436 case 64:
8437 break;
8438 default:
8439 return false;
8440 }
8441 }
8442
8443 return true;
8444 }
8445
8446 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8447 u16 *blue, uint32_t start, uint32_t size)
8448 {
8449 int end = (start + size > 256) ? 256 : start + size, i;
8450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8451
8452 for (i = start; i < end; i++) {
8453 intel_crtc->lut_r[i] = red[i] >> 8;
8454 intel_crtc->lut_g[i] = green[i] >> 8;
8455 intel_crtc->lut_b[i] = blue[i] >> 8;
8456 }
8457
8458 intel_crtc_load_lut(crtc);
8459 }
8460
8461 /* VESA 640x480x72Hz mode to set on the pipe */
8462 static struct drm_display_mode load_detect_mode = {
8463 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8464 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8465 };
8466
8467 struct drm_framebuffer *
8468 __intel_framebuffer_create(struct drm_device *dev,
8469 struct drm_mode_fb_cmd2 *mode_cmd,
8470 struct drm_i915_gem_object *obj)
8471 {
8472 struct intel_framebuffer *intel_fb;
8473 int ret;
8474
8475 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8476 if (!intel_fb) {
8477 drm_gem_object_unreference(&obj->base);
8478 return ERR_PTR(-ENOMEM);
8479 }
8480
8481 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8482 if (ret)
8483 goto err;
8484
8485 return &intel_fb->base;
8486 err:
8487 drm_gem_object_unreference(&obj->base);
8488 kfree(intel_fb);
8489
8490 return ERR_PTR(ret);
8491 }
8492
8493 static struct drm_framebuffer *
8494 intel_framebuffer_create(struct drm_device *dev,
8495 struct drm_mode_fb_cmd2 *mode_cmd,
8496 struct drm_i915_gem_object *obj)
8497 {
8498 struct drm_framebuffer *fb;
8499 int ret;
8500
8501 ret = i915_mutex_lock_interruptible(dev);
8502 if (ret)
8503 return ERR_PTR(ret);
8504 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8505 mutex_unlock(&dev->struct_mutex);
8506
8507 return fb;
8508 }
8509
8510 static u32
8511 intel_framebuffer_pitch_for_width(int width, int bpp)
8512 {
8513 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8514 return ALIGN(pitch, 64);
8515 }
8516
8517 static u32
8518 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8519 {
8520 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8521 return PAGE_ALIGN(pitch * mode->vdisplay);
8522 }
8523
8524 static struct drm_framebuffer *
8525 intel_framebuffer_create_for_mode(struct drm_device *dev,
8526 struct drm_display_mode *mode,
8527 int depth, int bpp)
8528 {
8529 struct drm_i915_gem_object *obj;
8530 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8531
8532 obj = i915_gem_alloc_object(dev,
8533 intel_framebuffer_size_for_mode(mode, bpp));
8534 if (obj == NULL)
8535 return ERR_PTR(-ENOMEM);
8536
8537 mode_cmd.width = mode->hdisplay;
8538 mode_cmd.height = mode->vdisplay;
8539 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8540 bpp);
8541 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8542
8543 return intel_framebuffer_create(dev, &mode_cmd, obj);
8544 }
8545
8546 static struct drm_framebuffer *
8547 mode_fits_in_fbdev(struct drm_device *dev,
8548 struct drm_display_mode *mode)
8549 {
8550 #ifdef CONFIG_DRM_I915_FBDEV
8551 struct drm_i915_private *dev_priv = dev->dev_private;
8552 struct drm_i915_gem_object *obj;
8553 struct drm_framebuffer *fb;
8554
8555 if (!dev_priv->fbdev)
8556 return NULL;
8557
8558 if (!dev_priv->fbdev->fb)
8559 return NULL;
8560
8561 obj = dev_priv->fbdev->fb->obj;
8562 BUG_ON(!obj);
8563
8564 fb = &dev_priv->fbdev->fb->base;
8565 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8566 fb->bits_per_pixel))
8567 return NULL;
8568
8569 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8570 return NULL;
8571
8572 return fb;
8573 #else
8574 return NULL;
8575 #endif
8576 }
8577
8578 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8579 struct drm_display_mode *mode,
8580 struct intel_load_detect_pipe *old,
8581 struct drm_modeset_acquire_ctx *ctx)
8582 {
8583 struct intel_crtc *intel_crtc;
8584 struct intel_encoder *intel_encoder =
8585 intel_attached_encoder(connector);
8586 struct drm_crtc *possible_crtc;
8587 struct drm_encoder *encoder = &intel_encoder->base;
8588 struct drm_crtc *crtc = NULL;
8589 struct drm_device *dev = encoder->dev;
8590 struct drm_framebuffer *fb;
8591 struct drm_mode_config *config = &dev->mode_config;
8592 int ret, i = -1;
8593
8594 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8595 connector->base.id, connector->name,
8596 encoder->base.id, encoder->name);
8597
8598 retry:
8599 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8600 if (ret)
8601 goto fail_unlock;
8602
8603 /*
8604 * Algorithm gets a little messy:
8605 *
8606 * - if the connector already has an assigned crtc, use it (but make
8607 * sure it's on first)
8608 *
8609 * - try to find the first unused crtc that can drive this connector,
8610 * and use that if we find one
8611 */
8612
8613 /* See if we already have a CRTC for this connector */
8614 if (encoder->crtc) {
8615 crtc = encoder->crtc;
8616
8617 ret = drm_modeset_lock(&crtc->mutex, ctx);
8618 if (ret)
8619 goto fail_unlock;
8620 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8621 if (ret)
8622 goto fail_unlock;
8623
8624 old->dpms_mode = connector->dpms;
8625 old->load_detect_temp = false;
8626
8627 /* Make sure the crtc and connector are running */
8628 if (connector->dpms != DRM_MODE_DPMS_ON)
8629 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8630
8631 return true;
8632 }
8633
8634 /* Find an unused one (if possible) */
8635 for_each_crtc(dev, possible_crtc) {
8636 i++;
8637 if (!(encoder->possible_crtcs & (1 << i)))
8638 continue;
8639 if (possible_crtc->enabled)
8640 continue;
8641 /* This can occur when applying the pipe A quirk on resume. */
8642 if (to_intel_crtc(possible_crtc)->new_enabled)
8643 continue;
8644
8645 crtc = possible_crtc;
8646 break;
8647 }
8648
8649 /*
8650 * If we didn't find an unused CRTC, don't use any.
8651 */
8652 if (!crtc) {
8653 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8654 goto fail_unlock;
8655 }
8656
8657 ret = drm_modeset_lock(&crtc->mutex, ctx);
8658 if (ret)
8659 goto fail_unlock;
8660 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8661 if (ret)
8662 goto fail_unlock;
8663 intel_encoder->new_crtc = to_intel_crtc(crtc);
8664 to_intel_connector(connector)->new_encoder = intel_encoder;
8665
8666 intel_crtc = to_intel_crtc(crtc);
8667 intel_crtc->new_enabled = true;
8668 intel_crtc->new_config = intel_crtc->config;
8669 old->dpms_mode = connector->dpms;
8670 old->load_detect_temp = true;
8671 old->release_fb = NULL;
8672
8673 if (!mode)
8674 mode = &load_detect_mode;
8675
8676 /* We need a framebuffer large enough to accommodate all accesses
8677 * that the plane may generate whilst we perform load detection.
8678 * We can not rely on the fbcon either being present (we get called
8679 * during its initialisation to detect all boot displays, or it may
8680 * not even exist) or that it is large enough to satisfy the
8681 * requested mode.
8682 */
8683 fb = mode_fits_in_fbdev(dev, mode);
8684 if (fb == NULL) {
8685 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8686 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8687 old->release_fb = fb;
8688 } else
8689 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8690 if (IS_ERR(fb)) {
8691 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8692 goto fail;
8693 }
8694
8695 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8696 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8697 if (old->release_fb)
8698 old->release_fb->funcs->destroy(old->release_fb);
8699 goto fail;
8700 }
8701
8702 /* let the connector get through one full cycle before testing */
8703 intel_wait_for_vblank(dev, intel_crtc->pipe);
8704 return true;
8705
8706 fail:
8707 intel_crtc->new_enabled = crtc->enabled;
8708 if (intel_crtc->new_enabled)
8709 intel_crtc->new_config = intel_crtc->config;
8710 else
8711 intel_crtc->new_config = NULL;
8712 fail_unlock:
8713 if (ret == -EDEADLK) {
8714 drm_modeset_backoff(ctx);
8715 goto retry;
8716 }
8717
8718 return false;
8719 }
8720
8721 void intel_release_load_detect_pipe(struct drm_connector *connector,
8722 struct intel_load_detect_pipe *old)
8723 {
8724 struct intel_encoder *intel_encoder =
8725 intel_attached_encoder(connector);
8726 struct drm_encoder *encoder = &intel_encoder->base;
8727 struct drm_crtc *crtc = encoder->crtc;
8728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8729
8730 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8731 connector->base.id, connector->name,
8732 encoder->base.id, encoder->name);
8733
8734 if (old->load_detect_temp) {
8735 to_intel_connector(connector)->new_encoder = NULL;
8736 intel_encoder->new_crtc = NULL;
8737 intel_crtc->new_enabled = false;
8738 intel_crtc->new_config = NULL;
8739 intel_set_mode(crtc, NULL, 0, 0, NULL);
8740
8741 if (old->release_fb) {
8742 drm_framebuffer_unregister_private(old->release_fb);
8743 drm_framebuffer_unreference(old->release_fb);
8744 }
8745
8746 return;
8747 }
8748
8749 /* Switch crtc and encoder back off if necessary */
8750 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8751 connector->funcs->dpms(connector, old->dpms_mode);
8752 }
8753
8754 static int i9xx_pll_refclk(struct drm_device *dev,
8755 const struct intel_crtc_state *pipe_config)
8756 {
8757 struct drm_i915_private *dev_priv = dev->dev_private;
8758 u32 dpll = pipe_config->dpll_hw_state.dpll;
8759
8760 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8761 return dev_priv->vbt.lvds_ssc_freq;
8762 else if (HAS_PCH_SPLIT(dev))
8763 return 120000;
8764 else if (!IS_GEN2(dev))
8765 return 96000;
8766 else
8767 return 48000;
8768 }
8769
8770 /* Returns the clock of the currently programmed mode of the given pipe. */
8771 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8772 struct intel_crtc_state *pipe_config)
8773 {
8774 struct drm_device *dev = crtc->base.dev;
8775 struct drm_i915_private *dev_priv = dev->dev_private;
8776 int pipe = pipe_config->cpu_transcoder;
8777 u32 dpll = pipe_config->dpll_hw_state.dpll;
8778 u32 fp;
8779 intel_clock_t clock;
8780 int refclk = i9xx_pll_refclk(dev, pipe_config);
8781
8782 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8783 fp = pipe_config->dpll_hw_state.fp0;
8784 else
8785 fp = pipe_config->dpll_hw_state.fp1;
8786
8787 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8788 if (IS_PINEVIEW(dev)) {
8789 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8790 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8791 } else {
8792 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8793 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8794 }
8795
8796 if (!IS_GEN2(dev)) {
8797 if (IS_PINEVIEW(dev))
8798 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8799 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8800 else
8801 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8802 DPLL_FPA01_P1_POST_DIV_SHIFT);
8803
8804 switch (dpll & DPLL_MODE_MASK) {
8805 case DPLLB_MODE_DAC_SERIAL:
8806 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8807 5 : 10;
8808 break;
8809 case DPLLB_MODE_LVDS:
8810 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8811 7 : 14;
8812 break;
8813 default:
8814 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8815 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8816 return;
8817 }
8818
8819 if (IS_PINEVIEW(dev))
8820 pineview_clock(refclk, &clock);
8821 else
8822 i9xx_clock(refclk, &clock);
8823 } else {
8824 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8825 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8826
8827 if (is_lvds) {
8828 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8829 DPLL_FPA01_P1_POST_DIV_SHIFT);
8830
8831 if (lvds & LVDS_CLKB_POWER_UP)
8832 clock.p2 = 7;
8833 else
8834 clock.p2 = 14;
8835 } else {
8836 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8837 clock.p1 = 2;
8838 else {
8839 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8840 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8841 }
8842 if (dpll & PLL_P2_DIVIDE_BY_4)
8843 clock.p2 = 4;
8844 else
8845 clock.p2 = 2;
8846 }
8847
8848 i9xx_clock(refclk, &clock);
8849 }
8850
8851 /*
8852 * This value includes pixel_multiplier. We will use
8853 * port_clock to compute adjusted_mode.crtc_clock in the
8854 * encoder's get_config() function.
8855 */
8856 pipe_config->port_clock = clock.dot;
8857 }
8858
8859 int intel_dotclock_calculate(int link_freq,
8860 const struct intel_link_m_n *m_n)
8861 {
8862 /*
8863 * The calculation for the data clock is:
8864 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8865 * But we want to avoid losing precison if possible, so:
8866 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8867 *
8868 * and the link clock is simpler:
8869 * link_clock = (m * link_clock) / n
8870 */
8871
8872 if (!m_n->link_n)
8873 return 0;
8874
8875 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8876 }
8877
8878 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8879 struct intel_crtc_state *pipe_config)
8880 {
8881 struct drm_device *dev = crtc->base.dev;
8882
8883 /* read out port_clock from the DPLL */
8884 i9xx_crtc_clock_get(crtc, pipe_config);
8885
8886 /*
8887 * This value does not include pixel_multiplier.
8888 * We will check that port_clock and adjusted_mode.crtc_clock
8889 * agree once we know their relationship in the encoder's
8890 * get_config() function.
8891 */
8892 pipe_config->base.adjusted_mode.crtc_clock =
8893 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8894 &pipe_config->fdi_m_n);
8895 }
8896
8897 /** Returns the currently programmed mode of the given pipe. */
8898 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8899 struct drm_crtc *crtc)
8900 {
8901 struct drm_i915_private *dev_priv = dev->dev_private;
8902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8903 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8904 struct drm_display_mode *mode;
8905 struct intel_crtc_state pipe_config;
8906 int htot = I915_READ(HTOTAL(cpu_transcoder));
8907 int hsync = I915_READ(HSYNC(cpu_transcoder));
8908 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8909 int vsync = I915_READ(VSYNC(cpu_transcoder));
8910 enum pipe pipe = intel_crtc->pipe;
8911
8912 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8913 if (!mode)
8914 return NULL;
8915
8916 /*
8917 * Construct a pipe_config sufficient for getting the clock info
8918 * back out of crtc_clock_get.
8919 *
8920 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8921 * to use a real value here instead.
8922 */
8923 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8924 pipe_config.pixel_multiplier = 1;
8925 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8926 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8927 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8928 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8929
8930 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8931 mode->hdisplay = (htot & 0xffff) + 1;
8932 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8933 mode->hsync_start = (hsync & 0xffff) + 1;
8934 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8935 mode->vdisplay = (vtot & 0xffff) + 1;
8936 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8937 mode->vsync_start = (vsync & 0xffff) + 1;
8938 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8939
8940 drm_mode_set_name(mode);
8941
8942 return mode;
8943 }
8944
8945 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8946 {
8947 struct drm_device *dev = crtc->dev;
8948 struct drm_i915_private *dev_priv = dev->dev_private;
8949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8950
8951 if (!HAS_GMCH_DISPLAY(dev))
8952 return;
8953
8954 if (!dev_priv->lvds_downclock_avail)
8955 return;
8956
8957 /*
8958 * Since this is called by a timer, we should never get here in
8959 * the manual case.
8960 */
8961 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8962 int pipe = intel_crtc->pipe;
8963 int dpll_reg = DPLL(pipe);
8964 int dpll;
8965
8966 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8967
8968 assert_panel_unlocked(dev_priv, pipe);
8969
8970 dpll = I915_READ(dpll_reg);
8971 dpll |= DISPLAY_RATE_SELECT_FPA1;
8972 I915_WRITE(dpll_reg, dpll);
8973 intel_wait_for_vblank(dev, pipe);
8974 dpll = I915_READ(dpll_reg);
8975 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8976 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8977 }
8978
8979 }
8980
8981 void intel_mark_busy(struct drm_device *dev)
8982 {
8983 struct drm_i915_private *dev_priv = dev->dev_private;
8984
8985 if (dev_priv->mm.busy)
8986 return;
8987
8988 intel_runtime_pm_get(dev_priv);
8989 i915_update_gfx_val(dev_priv);
8990 dev_priv->mm.busy = true;
8991 }
8992
8993 void intel_mark_idle(struct drm_device *dev)
8994 {
8995 struct drm_i915_private *dev_priv = dev->dev_private;
8996 struct drm_crtc *crtc;
8997
8998 if (!dev_priv->mm.busy)
8999 return;
9000
9001 dev_priv->mm.busy = false;
9002
9003 if (!i915.powersave)
9004 goto out;
9005
9006 for_each_crtc(dev, crtc) {
9007 if (!crtc->primary->fb)
9008 continue;
9009
9010 intel_decrease_pllclock(crtc);
9011 }
9012
9013 if (INTEL_INFO(dev)->gen >= 6)
9014 gen6_rps_idle(dev->dev_private);
9015
9016 out:
9017 intel_runtime_pm_put(dev_priv);
9018 }
9019
9020 static void intel_crtc_set_state(struct intel_crtc *crtc,
9021 struct intel_crtc_state *crtc_state)
9022 {
9023 kfree(crtc->config);
9024 crtc->config = crtc_state;
9025 crtc->base.state = &crtc_state->base;
9026 }
9027
9028 static void intel_crtc_destroy(struct drm_crtc *crtc)
9029 {
9030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9031 struct drm_device *dev = crtc->dev;
9032 struct intel_unpin_work *work;
9033
9034 spin_lock_irq(&dev->event_lock);
9035 work = intel_crtc->unpin_work;
9036 intel_crtc->unpin_work = NULL;
9037 spin_unlock_irq(&dev->event_lock);
9038
9039 if (work) {
9040 cancel_work_sync(&work->work);
9041 kfree(work);
9042 }
9043
9044 intel_crtc_set_state(intel_crtc, NULL);
9045 drm_crtc_cleanup(crtc);
9046
9047 kfree(intel_crtc);
9048 }
9049
9050 static void intel_unpin_work_fn(struct work_struct *__work)
9051 {
9052 struct intel_unpin_work *work =
9053 container_of(__work, struct intel_unpin_work, work);
9054 struct drm_device *dev = work->crtc->dev;
9055 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9056
9057 mutex_lock(&dev->struct_mutex);
9058 intel_unpin_fb_obj(work->old_fb_obj);
9059 drm_gem_object_unreference(&work->pending_flip_obj->base);
9060 drm_gem_object_unreference(&work->old_fb_obj->base);
9061
9062 intel_fbc_update(dev);
9063
9064 if (work->flip_queued_req)
9065 i915_gem_request_assign(&work->flip_queued_req, NULL);
9066 mutex_unlock(&dev->struct_mutex);
9067
9068 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9069
9070 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9071 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9072
9073 kfree(work);
9074 }
9075
9076 static void do_intel_finish_page_flip(struct drm_device *dev,
9077 struct drm_crtc *crtc)
9078 {
9079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9080 struct intel_unpin_work *work;
9081 unsigned long flags;
9082
9083 /* Ignore early vblank irqs */
9084 if (intel_crtc == NULL)
9085 return;
9086
9087 /*
9088 * This is called both by irq handlers and the reset code (to complete
9089 * lost pageflips) so needs the full irqsave spinlocks.
9090 */
9091 spin_lock_irqsave(&dev->event_lock, flags);
9092 work = intel_crtc->unpin_work;
9093
9094 /* Ensure we don't miss a work->pending update ... */
9095 smp_rmb();
9096
9097 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9098 spin_unlock_irqrestore(&dev->event_lock, flags);
9099 return;
9100 }
9101
9102 page_flip_completed(intel_crtc);
9103
9104 spin_unlock_irqrestore(&dev->event_lock, flags);
9105 }
9106
9107 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9108 {
9109 struct drm_i915_private *dev_priv = dev->dev_private;
9110 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9111
9112 do_intel_finish_page_flip(dev, crtc);
9113 }
9114
9115 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9116 {
9117 struct drm_i915_private *dev_priv = dev->dev_private;
9118 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9119
9120 do_intel_finish_page_flip(dev, crtc);
9121 }
9122
9123 /* Is 'a' after or equal to 'b'? */
9124 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9125 {
9126 return !((a - b) & 0x80000000);
9127 }
9128
9129 static bool page_flip_finished(struct intel_crtc *crtc)
9130 {
9131 struct drm_device *dev = crtc->base.dev;
9132 struct drm_i915_private *dev_priv = dev->dev_private;
9133
9134 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9135 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9136 return true;
9137
9138 /*
9139 * The relevant registers doen't exist on pre-ctg.
9140 * As the flip done interrupt doesn't trigger for mmio
9141 * flips on gmch platforms, a flip count check isn't
9142 * really needed there. But since ctg has the registers,
9143 * include it in the check anyway.
9144 */
9145 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9146 return true;
9147
9148 /*
9149 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9150 * used the same base address. In that case the mmio flip might
9151 * have completed, but the CS hasn't even executed the flip yet.
9152 *
9153 * A flip count check isn't enough as the CS might have updated
9154 * the base address just after start of vblank, but before we
9155 * managed to process the interrupt. This means we'd complete the
9156 * CS flip too soon.
9157 *
9158 * Combining both checks should get us a good enough result. It may
9159 * still happen that the CS flip has been executed, but has not
9160 * yet actually completed. But in case the base address is the same
9161 * anyway, we don't really care.
9162 */
9163 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9164 crtc->unpin_work->gtt_offset &&
9165 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9166 crtc->unpin_work->flip_count);
9167 }
9168
9169 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9170 {
9171 struct drm_i915_private *dev_priv = dev->dev_private;
9172 struct intel_crtc *intel_crtc =
9173 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9174 unsigned long flags;
9175
9176
9177 /*
9178 * This is called both by irq handlers and the reset code (to complete
9179 * lost pageflips) so needs the full irqsave spinlocks.
9180 *
9181 * NB: An MMIO update of the plane base pointer will also
9182 * generate a page-flip completion irq, i.e. every modeset
9183 * is also accompanied by a spurious intel_prepare_page_flip().
9184 */
9185 spin_lock_irqsave(&dev->event_lock, flags);
9186 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9187 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9188 spin_unlock_irqrestore(&dev->event_lock, flags);
9189 }
9190
9191 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9192 {
9193 /* Ensure that the work item is consistent when activating it ... */
9194 smp_wmb();
9195 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9196 /* and that it is marked active as soon as the irq could fire. */
9197 smp_wmb();
9198 }
9199
9200 static int intel_gen2_queue_flip(struct drm_device *dev,
9201 struct drm_crtc *crtc,
9202 struct drm_framebuffer *fb,
9203 struct drm_i915_gem_object *obj,
9204 struct intel_engine_cs *ring,
9205 uint32_t flags)
9206 {
9207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9208 u32 flip_mask;
9209 int ret;
9210
9211 ret = intel_ring_begin(ring, 6);
9212 if (ret)
9213 return ret;
9214
9215 /* Can't queue multiple flips, so wait for the previous
9216 * one to finish before executing the next.
9217 */
9218 if (intel_crtc->plane)
9219 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9220 else
9221 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9222 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9223 intel_ring_emit(ring, MI_NOOP);
9224 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9225 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9226 intel_ring_emit(ring, fb->pitches[0]);
9227 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9228 intel_ring_emit(ring, 0); /* aux display base address, unused */
9229
9230 intel_mark_page_flip_active(intel_crtc);
9231 __intel_ring_advance(ring);
9232 return 0;
9233 }
9234
9235 static int intel_gen3_queue_flip(struct drm_device *dev,
9236 struct drm_crtc *crtc,
9237 struct drm_framebuffer *fb,
9238 struct drm_i915_gem_object *obj,
9239 struct intel_engine_cs *ring,
9240 uint32_t flags)
9241 {
9242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9243 u32 flip_mask;
9244 int ret;
9245
9246 ret = intel_ring_begin(ring, 6);
9247 if (ret)
9248 return ret;
9249
9250 if (intel_crtc->plane)
9251 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9252 else
9253 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9254 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9255 intel_ring_emit(ring, MI_NOOP);
9256 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9257 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9258 intel_ring_emit(ring, fb->pitches[0]);
9259 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9260 intel_ring_emit(ring, MI_NOOP);
9261
9262 intel_mark_page_flip_active(intel_crtc);
9263 __intel_ring_advance(ring);
9264 return 0;
9265 }
9266
9267 static int intel_gen4_queue_flip(struct drm_device *dev,
9268 struct drm_crtc *crtc,
9269 struct drm_framebuffer *fb,
9270 struct drm_i915_gem_object *obj,
9271 struct intel_engine_cs *ring,
9272 uint32_t flags)
9273 {
9274 struct drm_i915_private *dev_priv = dev->dev_private;
9275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9276 uint32_t pf, pipesrc;
9277 int ret;
9278
9279 ret = intel_ring_begin(ring, 4);
9280 if (ret)
9281 return ret;
9282
9283 /* i965+ uses the linear or tiled offsets from the
9284 * Display Registers (which do not change across a page-flip)
9285 * so we need only reprogram the base address.
9286 */
9287 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9288 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9289 intel_ring_emit(ring, fb->pitches[0]);
9290 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9291 obj->tiling_mode);
9292
9293 /* XXX Enabling the panel-fitter across page-flip is so far
9294 * untested on non-native modes, so ignore it for now.
9295 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9296 */
9297 pf = 0;
9298 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9299 intel_ring_emit(ring, pf | pipesrc);
9300
9301 intel_mark_page_flip_active(intel_crtc);
9302 __intel_ring_advance(ring);
9303 return 0;
9304 }
9305
9306 static int intel_gen6_queue_flip(struct drm_device *dev,
9307 struct drm_crtc *crtc,
9308 struct drm_framebuffer *fb,
9309 struct drm_i915_gem_object *obj,
9310 struct intel_engine_cs *ring,
9311 uint32_t flags)
9312 {
9313 struct drm_i915_private *dev_priv = dev->dev_private;
9314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9315 uint32_t pf, pipesrc;
9316 int ret;
9317
9318 ret = intel_ring_begin(ring, 4);
9319 if (ret)
9320 return ret;
9321
9322 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9323 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9324 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9325 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9326
9327 /* Contrary to the suggestions in the documentation,
9328 * "Enable Panel Fitter" does not seem to be required when page
9329 * flipping with a non-native mode, and worse causes a normal
9330 * modeset to fail.
9331 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9332 */
9333 pf = 0;
9334 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9335 intel_ring_emit(ring, pf | pipesrc);
9336
9337 intel_mark_page_flip_active(intel_crtc);
9338 __intel_ring_advance(ring);
9339 return 0;
9340 }
9341
9342 static int intel_gen7_queue_flip(struct drm_device *dev,
9343 struct drm_crtc *crtc,
9344 struct drm_framebuffer *fb,
9345 struct drm_i915_gem_object *obj,
9346 struct intel_engine_cs *ring,
9347 uint32_t flags)
9348 {
9349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9350 uint32_t plane_bit = 0;
9351 int len, ret;
9352
9353 switch (intel_crtc->plane) {
9354 case PLANE_A:
9355 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9356 break;
9357 case PLANE_B:
9358 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9359 break;
9360 case PLANE_C:
9361 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9362 break;
9363 default:
9364 WARN_ONCE(1, "unknown plane in flip command\n");
9365 return -ENODEV;
9366 }
9367
9368 len = 4;
9369 if (ring->id == RCS) {
9370 len += 6;
9371 /*
9372 * On Gen 8, SRM is now taking an extra dword to accommodate
9373 * 48bits addresses, and we need a NOOP for the batch size to
9374 * stay even.
9375 */
9376 if (IS_GEN8(dev))
9377 len += 2;
9378 }
9379
9380 /*
9381 * BSpec MI_DISPLAY_FLIP for IVB:
9382 * "The full packet must be contained within the same cache line."
9383 *
9384 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9385 * cacheline, if we ever start emitting more commands before
9386 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9387 * then do the cacheline alignment, and finally emit the
9388 * MI_DISPLAY_FLIP.
9389 */
9390 ret = intel_ring_cacheline_align(ring);
9391 if (ret)
9392 return ret;
9393
9394 ret = intel_ring_begin(ring, len);
9395 if (ret)
9396 return ret;
9397
9398 /* Unmask the flip-done completion message. Note that the bspec says that
9399 * we should do this for both the BCS and RCS, and that we must not unmask
9400 * more than one flip event at any time (or ensure that one flip message
9401 * can be sent by waiting for flip-done prior to queueing new flips).
9402 * Experimentation says that BCS works despite DERRMR masking all
9403 * flip-done completion events and that unmasking all planes at once
9404 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9405 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9406 */
9407 if (ring->id == RCS) {
9408 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9409 intel_ring_emit(ring, DERRMR);
9410 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9411 DERRMR_PIPEB_PRI_FLIP_DONE |
9412 DERRMR_PIPEC_PRI_FLIP_DONE));
9413 if (IS_GEN8(dev))
9414 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9415 MI_SRM_LRM_GLOBAL_GTT);
9416 else
9417 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9418 MI_SRM_LRM_GLOBAL_GTT);
9419 intel_ring_emit(ring, DERRMR);
9420 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9421 if (IS_GEN8(dev)) {
9422 intel_ring_emit(ring, 0);
9423 intel_ring_emit(ring, MI_NOOP);
9424 }
9425 }
9426
9427 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9428 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9429 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9430 intel_ring_emit(ring, (MI_NOOP));
9431
9432 intel_mark_page_flip_active(intel_crtc);
9433 __intel_ring_advance(ring);
9434 return 0;
9435 }
9436
9437 static bool use_mmio_flip(struct intel_engine_cs *ring,
9438 struct drm_i915_gem_object *obj)
9439 {
9440 /*
9441 * This is not being used for older platforms, because
9442 * non-availability of flip done interrupt forces us to use
9443 * CS flips. Older platforms derive flip done using some clever
9444 * tricks involving the flip_pending status bits and vblank irqs.
9445 * So using MMIO flips there would disrupt this mechanism.
9446 */
9447
9448 if (ring == NULL)
9449 return true;
9450
9451 if (INTEL_INFO(ring->dev)->gen < 5)
9452 return false;
9453
9454 if (i915.use_mmio_flip < 0)
9455 return false;
9456 else if (i915.use_mmio_flip > 0)
9457 return true;
9458 else if (i915.enable_execlists)
9459 return true;
9460 else
9461 return ring != i915_gem_request_get_ring(obj->last_read_req);
9462 }
9463
9464 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9465 {
9466 struct drm_device *dev = intel_crtc->base.dev;
9467 struct drm_i915_private *dev_priv = dev->dev_private;
9468 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9469 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9470 struct drm_i915_gem_object *obj = intel_fb->obj;
9471 const enum pipe pipe = intel_crtc->pipe;
9472 u32 ctl, stride;
9473
9474 ctl = I915_READ(PLANE_CTL(pipe, 0));
9475 ctl &= ~PLANE_CTL_TILED_MASK;
9476 if (obj->tiling_mode == I915_TILING_X)
9477 ctl |= PLANE_CTL_TILED_X;
9478
9479 /*
9480 * The stride is either expressed as a multiple of 64 bytes chunks for
9481 * linear buffers or in number of tiles for tiled buffers.
9482 */
9483 stride = fb->pitches[0] >> 6;
9484 if (obj->tiling_mode == I915_TILING_X)
9485 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9486
9487 /*
9488 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9489 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9490 */
9491 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9492 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9493
9494 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9495 POSTING_READ(PLANE_SURF(pipe, 0));
9496 }
9497
9498 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9499 {
9500 struct drm_device *dev = intel_crtc->base.dev;
9501 struct drm_i915_private *dev_priv = dev->dev_private;
9502 struct intel_framebuffer *intel_fb =
9503 to_intel_framebuffer(intel_crtc->base.primary->fb);
9504 struct drm_i915_gem_object *obj = intel_fb->obj;
9505 u32 dspcntr;
9506 u32 reg;
9507
9508 reg = DSPCNTR(intel_crtc->plane);
9509 dspcntr = I915_READ(reg);
9510
9511 if (obj->tiling_mode != I915_TILING_NONE)
9512 dspcntr |= DISPPLANE_TILED;
9513 else
9514 dspcntr &= ~DISPPLANE_TILED;
9515
9516 I915_WRITE(reg, dspcntr);
9517
9518 I915_WRITE(DSPSURF(intel_crtc->plane),
9519 intel_crtc->unpin_work->gtt_offset);
9520 POSTING_READ(DSPSURF(intel_crtc->plane));
9521
9522 }
9523
9524 /*
9525 * XXX: This is the temporary way to update the plane registers until we get
9526 * around to using the usual plane update functions for MMIO flips
9527 */
9528 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9529 {
9530 struct drm_device *dev = intel_crtc->base.dev;
9531 bool atomic_update;
9532 u32 start_vbl_count;
9533
9534 intel_mark_page_flip_active(intel_crtc);
9535
9536 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9537
9538 if (INTEL_INFO(dev)->gen >= 9)
9539 skl_do_mmio_flip(intel_crtc);
9540 else
9541 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9542 ilk_do_mmio_flip(intel_crtc);
9543
9544 if (atomic_update)
9545 intel_pipe_update_end(intel_crtc, start_vbl_count);
9546 }
9547
9548 static void intel_mmio_flip_work_func(struct work_struct *work)
9549 {
9550 struct intel_crtc *crtc =
9551 container_of(work, struct intel_crtc, mmio_flip.work);
9552 struct intel_mmio_flip *mmio_flip;
9553
9554 mmio_flip = &crtc->mmio_flip;
9555 if (mmio_flip->req)
9556 WARN_ON(__i915_wait_request(mmio_flip->req,
9557 crtc->reset_counter,
9558 false, NULL, NULL) != 0);
9559
9560 intel_do_mmio_flip(crtc);
9561 if (mmio_flip->req) {
9562 mutex_lock(&crtc->base.dev->struct_mutex);
9563 i915_gem_request_assign(&mmio_flip->req, NULL);
9564 mutex_unlock(&crtc->base.dev->struct_mutex);
9565 }
9566 }
9567
9568 static int intel_queue_mmio_flip(struct drm_device *dev,
9569 struct drm_crtc *crtc,
9570 struct drm_framebuffer *fb,
9571 struct drm_i915_gem_object *obj,
9572 struct intel_engine_cs *ring,
9573 uint32_t flags)
9574 {
9575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9576
9577 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9578 obj->last_write_req);
9579
9580 schedule_work(&intel_crtc->mmio_flip.work);
9581
9582 return 0;
9583 }
9584
9585 static int intel_gen9_queue_flip(struct drm_device *dev,
9586 struct drm_crtc *crtc,
9587 struct drm_framebuffer *fb,
9588 struct drm_i915_gem_object *obj,
9589 struct intel_engine_cs *ring,
9590 uint32_t flags)
9591 {
9592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9593 uint32_t plane = 0, stride;
9594 int ret;
9595
9596 switch(intel_crtc->pipe) {
9597 case PIPE_A:
9598 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9599 break;
9600 case PIPE_B:
9601 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9602 break;
9603 case PIPE_C:
9604 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9605 break;
9606 default:
9607 WARN_ONCE(1, "unknown plane in flip command\n");
9608 return -ENODEV;
9609 }
9610
9611 switch (obj->tiling_mode) {
9612 case I915_TILING_NONE:
9613 stride = fb->pitches[0] >> 6;
9614 break;
9615 case I915_TILING_X:
9616 stride = fb->pitches[0] >> 9;
9617 break;
9618 default:
9619 WARN_ONCE(1, "unknown tiling in flip command\n");
9620 return -ENODEV;
9621 }
9622
9623 ret = intel_ring_begin(ring, 10);
9624 if (ret)
9625 return ret;
9626
9627 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9628 intel_ring_emit(ring, DERRMR);
9629 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9630 DERRMR_PIPEB_PRI_FLIP_DONE |
9631 DERRMR_PIPEC_PRI_FLIP_DONE));
9632 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9633 MI_SRM_LRM_GLOBAL_GTT);
9634 intel_ring_emit(ring, DERRMR);
9635 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9636 intel_ring_emit(ring, 0);
9637
9638 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9639 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9640 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9641
9642 intel_mark_page_flip_active(intel_crtc);
9643 __intel_ring_advance(ring);
9644
9645 return 0;
9646 }
9647
9648 static int intel_default_queue_flip(struct drm_device *dev,
9649 struct drm_crtc *crtc,
9650 struct drm_framebuffer *fb,
9651 struct drm_i915_gem_object *obj,
9652 struct intel_engine_cs *ring,
9653 uint32_t flags)
9654 {
9655 return -ENODEV;
9656 }
9657
9658 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9659 struct drm_crtc *crtc)
9660 {
9661 struct drm_i915_private *dev_priv = dev->dev_private;
9662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9663 struct intel_unpin_work *work = intel_crtc->unpin_work;
9664 u32 addr;
9665
9666 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9667 return true;
9668
9669 if (!work->enable_stall_check)
9670 return false;
9671
9672 if (work->flip_ready_vblank == 0) {
9673 if (work->flip_queued_req &&
9674 !i915_gem_request_completed(work->flip_queued_req, true))
9675 return false;
9676
9677 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9678 }
9679
9680 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9681 return false;
9682
9683 /* Potential stall - if we see that the flip has happened,
9684 * assume a missed interrupt. */
9685 if (INTEL_INFO(dev)->gen >= 4)
9686 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9687 else
9688 addr = I915_READ(DSPADDR(intel_crtc->plane));
9689
9690 /* There is a potential issue here with a false positive after a flip
9691 * to the same address. We could address this by checking for a
9692 * non-incrementing frame counter.
9693 */
9694 return addr == work->gtt_offset;
9695 }
9696
9697 void intel_check_page_flip(struct drm_device *dev, int pipe)
9698 {
9699 struct drm_i915_private *dev_priv = dev->dev_private;
9700 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9702
9703 WARN_ON(!in_irq());
9704
9705 if (crtc == NULL)
9706 return;
9707
9708 spin_lock(&dev->event_lock);
9709 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9710 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9711 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9712 page_flip_completed(intel_crtc);
9713 }
9714 spin_unlock(&dev->event_lock);
9715 }
9716
9717 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9718 struct drm_framebuffer *fb,
9719 struct drm_pending_vblank_event *event,
9720 uint32_t page_flip_flags)
9721 {
9722 struct drm_device *dev = crtc->dev;
9723 struct drm_i915_private *dev_priv = dev->dev_private;
9724 struct drm_framebuffer *old_fb = crtc->primary->fb;
9725 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9727 struct drm_plane *primary = crtc->primary;
9728 enum pipe pipe = intel_crtc->pipe;
9729 struct intel_unpin_work *work;
9730 struct intel_engine_cs *ring;
9731 int ret;
9732
9733 /*
9734 * drm_mode_page_flip_ioctl() should already catch this, but double
9735 * check to be safe. In the future we may enable pageflipping from
9736 * a disabled primary plane.
9737 */
9738 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9739 return -EBUSY;
9740
9741 /* Can't change pixel format via MI display flips. */
9742 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9743 return -EINVAL;
9744
9745 /*
9746 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9747 * Note that pitch changes could also affect these register.
9748 */
9749 if (INTEL_INFO(dev)->gen > 3 &&
9750 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9751 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9752 return -EINVAL;
9753
9754 if (i915_terminally_wedged(&dev_priv->gpu_error))
9755 goto out_hang;
9756
9757 work = kzalloc(sizeof(*work), GFP_KERNEL);
9758 if (work == NULL)
9759 return -ENOMEM;
9760
9761 work->event = event;
9762 work->crtc = crtc;
9763 work->old_fb_obj = intel_fb_obj(old_fb);
9764 INIT_WORK(&work->work, intel_unpin_work_fn);
9765
9766 ret = drm_crtc_vblank_get(crtc);
9767 if (ret)
9768 goto free_work;
9769
9770 /* We borrow the event spin lock for protecting unpin_work */
9771 spin_lock_irq(&dev->event_lock);
9772 if (intel_crtc->unpin_work) {
9773 /* Before declaring the flip queue wedged, check if
9774 * the hardware completed the operation behind our backs.
9775 */
9776 if (__intel_pageflip_stall_check(dev, crtc)) {
9777 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9778 page_flip_completed(intel_crtc);
9779 } else {
9780 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9781 spin_unlock_irq(&dev->event_lock);
9782
9783 drm_crtc_vblank_put(crtc);
9784 kfree(work);
9785 return -EBUSY;
9786 }
9787 }
9788 intel_crtc->unpin_work = work;
9789 spin_unlock_irq(&dev->event_lock);
9790
9791 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9792 flush_workqueue(dev_priv->wq);
9793
9794 ret = i915_mutex_lock_interruptible(dev);
9795 if (ret)
9796 goto cleanup;
9797
9798 /* Reference the objects for the scheduled work. */
9799 drm_gem_object_reference(&work->old_fb_obj->base);
9800 drm_gem_object_reference(&obj->base);
9801
9802 crtc->primary->fb = fb;
9803
9804 /* Keep state structure in sync */
9805 if (crtc->primary->state->fb)
9806 drm_framebuffer_unreference(crtc->primary->state->fb);
9807 crtc->primary->state->fb = fb;
9808 if (crtc->primary->state->fb)
9809 drm_framebuffer_reference(crtc->primary->state->fb);
9810
9811 work->pending_flip_obj = obj;
9812
9813 atomic_inc(&intel_crtc->unpin_work_count);
9814 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9815
9816 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9817 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9818
9819 if (IS_VALLEYVIEW(dev)) {
9820 ring = &dev_priv->ring[BCS];
9821 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9822 /* vlv: DISPLAY_FLIP fails to change tiling */
9823 ring = NULL;
9824 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9825 ring = &dev_priv->ring[BCS];
9826 } else if (INTEL_INFO(dev)->gen >= 7) {
9827 ring = i915_gem_request_get_ring(obj->last_read_req);
9828 if (ring == NULL || ring->id != RCS)
9829 ring = &dev_priv->ring[BCS];
9830 } else {
9831 ring = &dev_priv->ring[RCS];
9832 }
9833
9834 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9835 if (ret)
9836 goto cleanup_pending;
9837
9838 work->gtt_offset =
9839 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9840
9841 if (use_mmio_flip(ring, obj)) {
9842 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9843 page_flip_flags);
9844 if (ret)
9845 goto cleanup_unpin;
9846
9847 i915_gem_request_assign(&work->flip_queued_req,
9848 obj->last_write_req);
9849 } else {
9850 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9851 page_flip_flags);
9852 if (ret)
9853 goto cleanup_unpin;
9854
9855 i915_gem_request_assign(&work->flip_queued_req,
9856 intel_ring_get_request(ring));
9857 }
9858
9859 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9860 work->enable_stall_check = true;
9861
9862 i915_gem_track_fb(work->old_fb_obj, obj,
9863 INTEL_FRONTBUFFER_PRIMARY(pipe));
9864
9865 intel_fbc_disable(dev);
9866 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9867 mutex_unlock(&dev->struct_mutex);
9868
9869 trace_i915_flip_request(intel_crtc->plane, obj);
9870
9871 return 0;
9872
9873 cleanup_unpin:
9874 intel_unpin_fb_obj(obj);
9875 cleanup_pending:
9876 atomic_dec(&intel_crtc->unpin_work_count);
9877 crtc->primary->fb = old_fb;
9878 drm_gem_object_unreference(&work->old_fb_obj->base);
9879 drm_gem_object_unreference(&obj->base);
9880 mutex_unlock(&dev->struct_mutex);
9881
9882 cleanup:
9883 spin_lock_irq(&dev->event_lock);
9884 intel_crtc->unpin_work = NULL;
9885 spin_unlock_irq(&dev->event_lock);
9886
9887 drm_crtc_vblank_put(crtc);
9888 free_work:
9889 kfree(work);
9890
9891 if (ret == -EIO) {
9892 out_hang:
9893 ret = intel_plane_restore(primary);
9894 if (ret == 0 && event) {
9895 spin_lock_irq(&dev->event_lock);
9896 drm_send_vblank_event(dev, pipe, event);
9897 spin_unlock_irq(&dev->event_lock);
9898 }
9899 }
9900 return ret;
9901 }
9902
9903 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9904 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9905 .load_lut = intel_crtc_load_lut,
9906 .atomic_begin = intel_begin_crtc_commit,
9907 .atomic_flush = intel_finish_crtc_commit,
9908 };
9909
9910 /**
9911 * intel_modeset_update_staged_output_state
9912 *
9913 * Updates the staged output configuration state, e.g. after we've read out the
9914 * current hw state.
9915 */
9916 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9917 {
9918 struct intel_crtc *crtc;
9919 struct intel_encoder *encoder;
9920 struct intel_connector *connector;
9921
9922 list_for_each_entry(connector, &dev->mode_config.connector_list,
9923 base.head) {
9924 connector->new_encoder =
9925 to_intel_encoder(connector->base.encoder);
9926 }
9927
9928 for_each_intel_encoder(dev, encoder) {
9929 encoder->new_crtc =
9930 to_intel_crtc(encoder->base.crtc);
9931 }
9932
9933 for_each_intel_crtc(dev, crtc) {
9934 crtc->new_enabled = crtc->base.enabled;
9935
9936 if (crtc->new_enabled)
9937 crtc->new_config = crtc->config;
9938 else
9939 crtc->new_config = NULL;
9940 }
9941 }
9942
9943 /**
9944 * intel_modeset_commit_output_state
9945 *
9946 * This function copies the stage display pipe configuration to the real one.
9947 */
9948 static void intel_modeset_commit_output_state(struct drm_device *dev)
9949 {
9950 struct intel_crtc *crtc;
9951 struct intel_encoder *encoder;
9952 struct intel_connector *connector;
9953
9954 list_for_each_entry(connector, &dev->mode_config.connector_list,
9955 base.head) {
9956 connector->base.encoder = &connector->new_encoder->base;
9957 }
9958
9959 for_each_intel_encoder(dev, encoder) {
9960 encoder->base.crtc = &encoder->new_crtc->base;
9961 }
9962
9963 for_each_intel_crtc(dev, crtc) {
9964 crtc->base.enabled = crtc->new_enabled;
9965 }
9966 }
9967
9968 static void
9969 connected_sink_compute_bpp(struct intel_connector *connector,
9970 struct intel_crtc_state *pipe_config)
9971 {
9972 int bpp = pipe_config->pipe_bpp;
9973
9974 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9975 connector->base.base.id,
9976 connector->base.name);
9977
9978 /* Don't use an invalid EDID bpc value */
9979 if (connector->base.display_info.bpc &&
9980 connector->base.display_info.bpc * 3 < bpp) {
9981 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9982 bpp, connector->base.display_info.bpc*3);
9983 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9984 }
9985
9986 /* Clamp bpp to 8 on screens without EDID 1.4 */
9987 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9988 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9989 bpp);
9990 pipe_config->pipe_bpp = 24;
9991 }
9992 }
9993
9994 static int
9995 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9996 struct drm_framebuffer *fb,
9997 struct intel_crtc_state *pipe_config)
9998 {
9999 struct drm_device *dev = crtc->base.dev;
10000 struct intel_connector *connector;
10001 int bpp;
10002
10003 switch (fb->pixel_format) {
10004 case DRM_FORMAT_C8:
10005 bpp = 8*3; /* since we go through a colormap */
10006 break;
10007 case DRM_FORMAT_XRGB1555:
10008 case DRM_FORMAT_ARGB1555:
10009 /* checked in intel_framebuffer_init already */
10010 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10011 return -EINVAL;
10012 case DRM_FORMAT_RGB565:
10013 bpp = 6*3; /* min is 18bpp */
10014 break;
10015 case DRM_FORMAT_XBGR8888:
10016 case DRM_FORMAT_ABGR8888:
10017 /* checked in intel_framebuffer_init already */
10018 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10019 return -EINVAL;
10020 case DRM_FORMAT_XRGB8888:
10021 case DRM_FORMAT_ARGB8888:
10022 bpp = 8*3;
10023 break;
10024 case DRM_FORMAT_XRGB2101010:
10025 case DRM_FORMAT_ARGB2101010:
10026 case DRM_FORMAT_XBGR2101010:
10027 case DRM_FORMAT_ABGR2101010:
10028 /* checked in intel_framebuffer_init already */
10029 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10030 return -EINVAL;
10031 bpp = 10*3;
10032 break;
10033 /* TODO: gen4+ supports 16 bpc floating point, too. */
10034 default:
10035 DRM_DEBUG_KMS("unsupported depth\n");
10036 return -EINVAL;
10037 }
10038
10039 pipe_config->pipe_bpp = bpp;
10040
10041 /* Clamp display bpp to EDID value */
10042 list_for_each_entry(connector, &dev->mode_config.connector_list,
10043 base.head) {
10044 if (!connector->new_encoder ||
10045 connector->new_encoder->new_crtc != crtc)
10046 continue;
10047
10048 connected_sink_compute_bpp(connector, pipe_config);
10049 }
10050
10051 return bpp;
10052 }
10053
10054 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10055 {
10056 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10057 "type: 0x%x flags: 0x%x\n",
10058 mode->crtc_clock,
10059 mode->crtc_hdisplay, mode->crtc_hsync_start,
10060 mode->crtc_hsync_end, mode->crtc_htotal,
10061 mode->crtc_vdisplay, mode->crtc_vsync_start,
10062 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10063 }
10064
10065 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10066 struct intel_crtc_state *pipe_config,
10067 const char *context)
10068 {
10069 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10070 context, pipe_name(crtc->pipe));
10071
10072 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10073 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10074 pipe_config->pipe_bpp, pipe_config->dither);
10075 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10076 pipe_config->has_pch_encoder,
10077 pipe_config->fdi_lanes,
10078 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10079 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10080 pipe_config->fdi_m_n.tu);
10081 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10082 pipe_config->has_dp_encoder,
10083 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10084 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10085 pipe_config->dp_m_n.tu);
10086
10087 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10088 pipe_config->has_dp_encoder,
10089 pipe_config->dp_m2_n2.gmch_m,
10090 pipe_config->dp_m2_n2.gmch_n,
10091 pipe_config->dp_m2_n2.link_m,
10092 pipe_config->dp_m2_n2.link_n,
10093 pipe_config->dp_m2_n2.tu);
10094
10095 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10096 pipe_config->has_audio,
10097 pipe_config->has_infoframe);
10098
10099 DRM_DEBUG_KMS("requested mode:\n");
10100 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10101 DRM_DEBUG_KMS("adjusted mode:\n");
10102 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10103 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10104 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10105 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10106 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10107 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10108 pipe_config->gmch_pfit.control,
10109 pipe_config->gmch_pfit.pgm_ratios,
10110 pipe_config->gmch_pfit.lvds_border_bits);
10111 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10112 pipe_config->pch_pfit.pos,
10113 pipe_config->pch_pfit.size,
10114 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10115 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10116 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10117 }
10118
10119 static bool encoders_cloneable(const struct intel_encoder *a,
10120 const struct intel_encoder *b)
10121 {
10122 /* masks could be asymmetric, so check both ways */
10123 return a == b || (a->cloneable & (1 << b->type) &&
10124 b->cloneable & (1 << a->type));
10125 }
10126
10127 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10128 struct intel_encoder *encoder)
10129 {
10130 struct drm_device *dev = crtc->base.dev;
10131 struct intel_encoder *source_encoder;
10132
10133 for_each_intel_encoder(dev, source_encoder) {
10134 if (source_encoder->new_crtc != crtc)
10135 continue;
10136
10137 if (!encoders_cloneable(encoder, source_encoder))
10138 return false;
10139 }
10140
10141 return true;
10142 }
10143
10144 static bool check_encoder_cloning(struct intel_crtc *crtc)
10145 {
10146 struct drm_device *dev = crtc->base.dev;
10147 struct intel_encoder *encoder;
10148
10149 for_each_intel_encoder(dev, encoder) {
10150 if (encoder->new_crtc != crtc)
10151 continue;
10152
10153 if (!check_single_encoder_cloning(crtc, encoder))
10154 return false;
10155 }
10156
10157 return true;
10158 }
10159
10160 static bool check_digital_port_conflicts(struct drm_device *dev)
10161 {
10162 struct intel_connector *connector;
10163 unsigned int used_ports = 0;
10164
10165 /*
10166 * Walk the connector list instead of the encoder
10167 * list to detect the problem on ddi platforms
10168 * where there's just one encoder per digital port.
10169 */
10170 list_for_each_entry(connector,
10171 &dev->mode_config.connector_list, base.head) {
10172 struct intel_encoder *encoder = connector->new_encoder;
10173
10174 if (!encoder)
10175 continue;
10176
10177 WARN_ON(!encoder->new_crtc);
10178
10179 switch (encoder->type) {
10180 unsigned int port_mask;
10181 case INTEL_OUTPUT_UNKNOWN:
10182 if (WARN_ON(!HAS_DDI(dev)))
10183 break;
10184 case INTEL_OUTPUT_DISPLAYPORT:
10185 case INTEL_OUTPUT_HDMI:
10186 case INTEL_OUTPUT_EDP:
10187 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10188
10189 /* the same port mustn't appear more than once */
10190 if (used_ports & port_mask)
10191 return false;
10192
10193 used_ports |= port_mask;
10194 default:
10195 break;
10196 }
10197 }
10198
10199 return true;
10200 }
10201
10202 static struct intel_crtc_state *
10203 intel_modeset_pipe_config(struct drm_crtc *crtc,
10204 struct drm_framebuffer *fb,
10205 struct drm_display_mode *mode)
10206 {
10207 struct drm_device *dev = crtc->dev;
10208 struct intel_encoder *encoder;
10209 struct intel_crtc_state *pipe_config;
10210 int plane_bpp, ret = -EINVAL;
10211 bool retry = true;
10212
10213 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10214 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10215 return ERR_PTR(-EINVAL);
10216 }
10217
10218 if (!check_digital_port_conflicts(dev)) {
10219 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10220 return ERR_PTR(-EINVAL);
10221 }
10222
10223 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10224 if (!pipe_config)
10225 return ERR_PTR(-ENOMEM);
10226
10227 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10228 drm_mode_copy(&pipe_config->base.mode, mode);
10229
10230 pipe_config->cpu_transcoder =
10231 (enum transcoder) to_intel_crtc(crtc)->pipe;
10232 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10233
10234 /*
10235 * Sanitize sync polarity flags based on requested ones. If neither
10236 * positive or negative polarity is requested, treat this as meaning
10237 * negative polarity.
10238 */
10239 if (!(pipe_config->base.adjusted_mode.flags &
10240 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10241 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10242
10243 if (!(pipe_config->base.adjusted_mode.flags &
10244 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10245 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10246
10247 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10248 * plane pixel format and any sink constraints into account. Returns the
10249 * source plane bpp so that dithering can be selected on mismatches
10250 * after encoders and crtc also have had their say. */
10251 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10252 fb, pipe_config);
10253 if (plane_bpp < 0)
10254 goto fail;
10255
10256 /*
10257 * Determine the real pipe dimensions. Note that stereo modes can
10258 * increase the actual pipe size due to the frame doubling and
10259 * insertion of additional space for blanks between the frame. This
10260 * is stored in the crtc timings. We use the requested mode to do this
10261 * computation to clearly distinguish it from the adjusted mode, which
10262 * can be changed by the connectors in the below retry loop.
10263 */
10264 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10265 &pipe_config->pipe_src_w,
10266 &pipe_config->pipe_src_h);
10267
10268 encoder_retry:
10269 /* Ensure the port clock defaults are reset when retrying. */
10270 pipe_config->port_clock = 0;
10271 pipe_config->pixel_multiplier = 1;
10272
10273 /* Fill in default crtc timings, allow encoders to overwrite them. */
10274 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10275 CRTC_STEREO_DOUBLE);
10276
10277 /* Pass our mode to the connectors and the CRTC to give them a chance to
10278 * adjust it according to limitations or connector properties, and also
10279 * a chance to reject the mode entirely.
10280 */
10281 for_each_intel_encoder(dev, encoder) {
10282
10283 if (&encoder->new_crtc->base != crtc)
10284 continue;
10285
10286 if (!(encoder->compute_config(encoder, pipe_config))) {
10287 DRM_DEBUG_KMS("Encoder config failure\n");
10288 goto fail;
10289 }
10290 }
10291
10292 /* Set default port clock if not overwritten by the encoder. Needs to be
10293 * done afterwards in case the encoder adjusts the mode. */
10294 if (!pipe_config->port_clock)
10295 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10296 * pipe_config->pixel_multiplier;
10297
10298 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10299 if (ret < 0) {
10300 DRM_DEBUG_KMS("CRTC fixup failed\n");
10301 goto fail;
10302 }
10303
10304 if (ret == RETRY) {
10305 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10306 ret = -EINVAL;
10307 goto fail;
10308 }
10309
10310 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10311 retry = false;
10312 goto encoder_retry;
10313 }
10314
10315 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10316 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10317 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10318
10319 return pipe_config;
10320 fail:
10321 kfree(pipe_config);
10322 return ERR_PTR(ret);
10323 }
10324
10325 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10326 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10327 static void
10328 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10329 unsigned *prepare_pipes, unsigned *disable_pipes)
10330 {
10331 struct intel_crtc *intel_crtc;
10332 struct drm_device *dev = crtc->dev;
10333 struct intel_encoder *encoder;
10334 struct intel_connector *connector;
10335 struct drm_crtc *tmp_crtc;
10336
10337 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10338
10339 /* Check which crtcs have changed outputs connected to them, these need
10340 * to be part of the prepare_pipes mask. We don't (yet) support global
10341 * modeset across multiple crtcs, so modeset_pipes will only have one
10342 * bit set at most. */
10343 list_for_each_entry(connector, &dev->mode_config.connector_list,
10344 base.head) {
10345 if (connector->base.encoder == &connector->new_encoder->base)
10346 continue;
10347
10348 if (connector->base.encoder) {
10349 tmp_crtc = connector->base.encoder->crtc;
10350
10351 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10352 }
10353
10354 if (connector->new_encoder)
10355 *prepare_pipes |=
10356 1 << connector->new_encoder->new_crtc->pipe;
10357 }
10358
10359 for_each_intel_encoder(dev, encoder) {
10360 if (encoder->base.crtc == &encoder->new_crtc->base)
10361 continue;
10362
10363 if (encoder->base.crtc) {
10364 tmp_crtc = encoder->base.crtc;
10365
10366 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10367 }
10368
10369 if (encoder->new_crtc)
10370 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10371 }
10372
10373 /* Check for pipes that will be enabled/disabled ... */
10374 for_each_intel_crtc(dev, intel_crtc) {
10375 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10376 continue;
10377
10378 if (!intel_crtc->new_enabled)
10379 *disable_pipes |= 1 << intel_crtc->pipe;
10380 else
10381 *prepare_pipes |= 1 << intel_crtc->pipe;
10382 }
10383
10384
10385 /* set_mode is also used to update properties on life display pipes. */
10386 intel_crtc = to_intel_crtc(crtc);
10387 if (intel_crtc->new_enabled)
10388 *prepare_pipes |= 1 << intel_crtc->pipe;
10389
10390 /*
10391 * For simplicity do a full modeset on any pipe where the output routing
10392 * changed. We could be more clever, but that would require us to be
10393 * more careful with calling the relevant encoder->mode_set functions.
10394 */
10395 if (*prepare_pipes)
10396 *modeset_pipes = *prepare_pipes;
10397
10398 /* ... and mask these out. */
10399 *modeset_pipes &= ~(*disable_pipes);
10400 *prepare_pipes &= ~(*disable_pipes);
10401
10402 /*
10403 * HACK: We don't (yet) fully support global modesets. intel_set_config
10404 * obies this rule, but the modeset restore mode of
10405 * intel_modeset_setup_hw_state does not.
10406 */
10407 *modeset_pipes &= 1 << intel_crtc->pipe;
10408 *prepare_pipes &= 1 << intel_crtc->pipe;
10409
10410 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10411 *modeset_pipes, *prepare_pipes, *disable_pipes);
10412 }
10413
10414 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10415 {
10416 struct drm_encoder *encoder;
10417 struct drm_device *dev = crtc->dev;
10418
10419 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10420 if (encoder->crtc == crtc)
10421 return true;
10422
10423 return false;
10424 }
10425
10426 static void
10427 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10428 {
10429 struct drm_i915_private *dev_priv = dev->dev_private;
10430 struct intel_encoder *intel_encoder;
10431 struct intel_crtc *intel_crtc;
10432 struct drm_connector *connector;
10433
10434 intel_shared_dpll_commit(dev_priv);
10435
10436 for_each_intel_encoder(dev, intel_encoder) {
10437 if (!intel_encoder->base.crtc)
10438 continue;
10439
10440 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10441
10442 if (prepare_pipes & (1 << intel_crtc->pipe))
10443 intel_encoder->connectors_active = false;
10444 }
10445
10446 intel_modeset_commit_output_state(dev);
10447
10448 /* Double check state. */
10449 for_each_intel_crtc(dev, intel_crtc) {
10450 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10451 WARN_ON(intel_crtc->new_config &&
10452 intel_crtc->new_config != intel_crtc->config);
10453 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10454 }
10455
10456 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10457 if (!connector->encoder || !connector->encoder->crtc)
10458 continue;
10459
10460 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10461
10462 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10463 struct drm_property *dpms_property =
10464 dev->mode_config.dpms_property;
10465
10466 connector->dpms = DRM_MODE_DPMS_ON;
10467 drm_object_property_set_value(&connector->base,
10468 dpms_property,
10469 DRM_MODE_DPMS_ON);
10470
10471 intel_encoder = to_intel_encoder(connector->encoder);
10472 intel_encoder->connectors_active = true;
10473 }
10474 }
10475
10476 }
10477
10478 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10479 {
10480 int diff;
10481
10482 if (clock1 == clock2)
10483 return true;
10484
10485 if (!clock1 || !clock2)
10486 return false;
10487
10488 diff = abs(clock1 - clock2);
10489
10490 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10491 return true;
10492
10493 return false;
10494 }
10495
10496 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10497 list_for_each_entry((intel_crtc), \
10498 &(dev)->mode_config.crtc_list, \
10499 base.head) \
10500 if (mask & (1 <<(intel_crtc)->pipe))
10501
10502 static bool
10503 intel_pipe_config_compare(struct drm_device *dev,
10504 struct intel_crtc_state *current_config,
10505 struct intel_crtc_state *pipe_config)
10506 {
10507 #define PIPE_CONF_CHECK_X(name) \
10508 if (current_config->name != pipe_config->name) { \
10509 DRM_ERROR("mismatch in " #name " " \
10510 "(expected 0x%08x, found 0x%08x)\n", \
10511 current_config->name, \
10512 pipe_config->name); \
10513 return false; \
10514 }
10515
10516 #define PIPE_CONF_CHECK_I(name) \
10517 if (current_config->name != pipe_config->name) { \
10518 DRM_ERROR("mismatch in " #name " " \
10519 "(expected %i, found %i)\n", \
10520 current_config->name, \
10521 pipe_config->name); \
10522 return false; \
10523 }
10524
10525 /* This is required for BDW+ where there is only one set of registers for
10526 * switching between high and low RR.
10527 * This macro can be used whenever a comparison has to be made between one
10528 * hw state and multiple sw state variables.
10529 */
10530 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10531 if ((current_config->name != pipe_config->name) && \
10532 (current_config->alt_name != pipe_config->name)) { \
10533 DRM_ERROR("mismatch in " #name " " \
10534 "(expected %i or %i, found %i)\n", \
10535 current_config->name, \
10536 current_config->alt_name, \
10537 pipe_config->name); \
10538 return false; \
10539 }
10540
10541 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10542 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10543 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10544 "(expected %i, found %i)\n", \
10545 current_config->name & (mask), \
10546 pipe_config->name & (mask)); \
10547 return false; \
10548 }
10549
10550 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10551 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10552 DRM_ERROR("mismatch in " #name " " \
10553 "(expected %i, found %i)\n", \
10554 current_config->name, \
10555 pipe_config->name); \
10556 return false; \
10557 }
10558
10559 #define PIPE_CONF_QUIRK(quirk) \
10560 ((current_config->quirks | pipe_config->quirks) & (quirk))
10561
10562 PIPE_CONF_CHECK_I(cpu_transcoder);
10563
10564 PIPE_CONF_CHECK_I(has_pch_encoder);
10565 PIPE_CONF_CHECK_I(fdi_lanes);
10566 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10567 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10568 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10569 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10570 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10571
10572 PIPE_CONF_CHECK_I(has_dp_encoder);
10573
10574 if (INTEL_INFO(dev)->gen < 8) {
10575 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10576 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10577 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10578 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10579 PIPE_CONF_CHECK_I(dp_m_n.tu);
10580
10581 if (current_config->has_drrs) {
10582 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10583 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10584 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10585 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10586 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10587 }
10588 } else {
10589 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10590 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10591 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10592 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10593 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10594 }
10595
10596 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10597 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10598 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10599 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10600 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10601 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10602
10603 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10604 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10605 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10606 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10607 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10608 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10609
10610 PIPE_CONF_CHECK_I(pixel_multiplier);
10611 PIPE_CONF_CHECK_I(has_hdmi_sink);
10612 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10613 IS_VALLEYVIEW(dev))
10614 PIPE_CONF_CHECK_I(limited_color_range);
10615 PIPE_CONF_CHECK_I(has_infoframe);
10616
10617 PIPE_CONF_CHECK_I(has_audio);
10618
10619 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10620 DRM_MODE_FLAG_INTERLACE);
10621
10622 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10623 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10624 DRM_MODE_FLAG_PHSYNC);
10625 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10626 DRM_MODE_FLAG_NHSYNC);
10627 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10628 DRM_MODE_FLAG_PVSYNC);
10629 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10630 DRM_MODE_FLAG_NVSYNC);
10631 }
10632
10633 PIPE_CONF_CHECK_I(pipe_src_w);
10634 PIPE_CONF_CHECK_I(pipe_src_h);
10635
10636 /*
10637 * FIXME: BIOS likes to set up a cloned config with lvds+external
10638 * screen. Since we don't yet re-compute the pipe config when moving
10639 * just the lvds port away to another pipe the sw tracking won't match.
10640 *
10641 * Proper atomic modesets with recomputed global state will fix this.
10642 * Until then just don't check gmch state for inherited modes.
10643 */
10644 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10645 PIPE_CONF_CHECK_I(gmch_pfit.control);
10646 /* pfit ratios are autocomputed by the hw on gen4+ */
10647 if (INTEL_INFO(dev)->gen < 4)
10648 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10649 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10650 }
10651
10652 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10653 if (current_config->pch_pfit.enabled) {
10654 PIPE_CONF_CHECK_I(pch_pfit.pos);
10655 PIPE_CONF_CHECK_I(pch_pfit.size);
10656 }
10657
10658 /* BDW+ don't expose a synchronous way to read the state */
10659 if (IS_HASWELL(dev))
10660 PIPE_CONF_CHECK_I(ips_enabled);
10661
10662 PIPE_CONF_CHECK_I(double_wide);
10663
10664 PIPE_CONF_CHECK_X(ddi_pll_sel);
10665
10666 PIPE_CONF_CHECK_I(shared_dpll);
10667 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10668 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10669 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10670 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10671 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10672 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10673 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10674 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10675
10676 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10677 PIPE_CONF_CHECK_I(pipe_bpp);
10678
10679 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10680 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10681
10682 #undef PIPE_CONF_CHECK_X
10683 #undef PIPE_CONF_CHECK_I
10684 #undef PIPE_CONF_CHECK_I_ALT
10685 #undef PIPE_CONF_CHECK_FLAGS
10686 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10687 #undef PIPE_CONF_QUIRK
10688
10689 return true;
10690 }
10691
10692 static void check_wm_state(struct drm_device *dev)
10693 {
10694 struct drm_i915_private *dev_priv = dev->dev_private;
10695 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10696 struct intel_crtc *intel_crtc;
10697 int plane;
10698
10699 if (INTEL_INFO(dev)->gen < 9)
10700 return;
10701
10702 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10703 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10704
10705 for_each_intel_crtc(dev, intel_crtc) {
10706 struct skl_ddb_entry *hw_entry, *sw_entry;
10707 const enum pipe pipe = intel_crtc->pipe;
10708
10709 if (!intel_crtc->active)
10710 continue;
10711
10712 /* planes */
10713 for_each_plane(pipe, plane) {
10714 hw_entry = &hw_ddb.plane[pipe][plane];
10715 sw_entry = &sw_ddb->plane[pipe][plane];
10716
10717 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10718 continue;
10719
10720 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10721 "(expected (%u,%u), found (%u,%u))\n",
10722 pipe_name(pipe), plane + 1,
10723 sw_entry->start, sw_entry->end,
10724 hw_entry->start, hw_entry->end);
10725 }
10726
10727 /* cursor */
10728 hw_entry = &hw_ddb.cursor[pipe];
10729 sw_entry = &sw_ddb->cursor[pipe];
10730
10731 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10732 continue;
10733
10734 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10735 "(expected (%u,%u), found (%u,%u))\n",
10736 pipe_name(pipe),
10737 sw_entry->start, sw_entry->end,
10738 hw_entry->start, hw_entry->end);
10739 }
10740 }
10741
10742 static void
10743 check_connector_state(struct drm_device *dev)
10744 {
10745 struct intel_connector *connector;
10746
10747 list_for_each_entry(connector, &dev->mode_config.connector_list,
10748 base.head) {
10749 /* This also checks the encoder/connector hw state with the
10750 * ->get_hw_state callbacks. */
10751 intel_connector_check_state(connector);
10752
10753 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10754 "connector's staged encoder doesn't match current encoder\n");
10755 }
10756 }
10757
10758 static void
10759 check_encoder_state(struct drm_device *dev)
10760 {
10761 struct intel_encoder *encoder;
10762 struct intel_connector *connector;
10763
10764 for_each_intel_encoder(dev, encoder) {
10765 bool enabled = false;
10766 bool active = false;
10767 enum pipe pipe, tracked_pipe;
10768
10769 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10770 encoder->base.base.id,
10771 encoder->base.name);
10772
10773 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10774 "encoder's stage crtc doesn't match current crtc\n");
10775 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10776 "encoder's active_connectors set, but no crtc\n");
10777
10778 list_for_each_entry(connector, &dev->mode_config.connector_list,
10779 base.head) {
10780 if (connector->base.encoder != &encoder->base)
10781 continue;
10782 enabled = true;
10783 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10784 active = true;
10785 }
10786 /*
10787 * for MST connectors if we unplug the connector is gone
10788 * away but the encoder is still connected to a crtc
10789 * until a modeset happens in response to the hotplug.
10790 */
10791 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10792 continue;
10793
10794 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10795 "encoder's enabled state mismatch "
10796 "(expected %i, found %i)\n",
10797 !!encoder->base.crtc, enabled);
10798 I915_STATE_WARN(active && !encoder->base.crtc,
10799 "active encoder with no crtc\n");
10800
10801 I915_STATE_WARN(encoder->connectors_active != active,
10802 "encoder's computed active state doesn't match tracked active state "
10803 "(expected %i, found %i)\n", active, encoder->connectors_active);
10804
10805 active = encoder->get_hw_state(encoder, &pipe);
10806 I915_STATE_WARN(active != encoder->connectors_active,
10807 "encoder's hw state doesn't match sw tracking "
10808 "(expected %i, found %i)\n",
10809 encoder->connectors_active, active);
10810
10811 if (!encoder->base.crtc)
10812 continue;
10813
10814 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10815 I915_STATE_WARN(active && pipe != tracked_pipe,
10816 "active encoder's pipe doesn't match"
10817 "(expected %i, found %i)\n",
10818 tracked_pipe, pipe);
10819
10820 }
10821 }
10822
10823 static void
10824 check_crtc_state(struct drm_device *dev)
10825 {
10826 struct drm_i915_private *dev_priv = dev->dev_private;
10827 struct intel_crtc *crtc;
10828 struct intel_encoder *encoder;
10829 struct intel_crtc_state pipe_config;
10830
10831 for_each_intel_crtc(dev, crtc) {
10832 bool enabled = false;
10833 bool active = false;
10834
10835 memset(&pipe_config, 0, sizeof(pipe_config));
10836
10837 DRM_DEBUG_KMS("[CRTC:%d]\n",
10838 crtc->base.base.id);
10839
10840 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10841 "active crtc, but not enabled in sw tracking\n");
10842
10843 for_each_intel_encoder(dev, encoder) {
10844 if (encoder->base.crtc != &crtc->base)
10845 continue;
10846 enabled = true;
10847 if (encoder->connectors_active)
10848 active = true;
10849 }
10850
10851 I915_STATE_WARN(active != crtc->active,
10852 "crtc's computed active state doesn't match tracked active state "
10853 "(expected %i, found %i)\n", active, crtc->active);
10854 I915_STATE_WARN(enabled != crtc->base.enabled,
10855 "crtc's computed enabled state doesn't match tracked enabled state "
10856 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10857
10858 active = dev_priv->display.get_pipe_config(crtc,
10859 &pipe_config);
10860
10861 /* hw state is inconsistent with the pipe quirk */
10862 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10863 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10864 active = crtc->active;
10865
10866 for_each_intel_encoder(dev, encoder) {
10867 enum pipe pipe;
10868 if (encoder->base.crtc != &crtc->base)
10869 continue;
10870 if (encoder->get_hw_state(encoder, &pipe))
10871 encoder->get_config(encoder, &pipe_config);
10872 }
10873
10874 I915_STATE_WARN(crtc->active != active,
10875 "crtc active state doesn't match with hw state "
10876 "(expected %i, found %i)\n", crtc->active, active);
10877
10878 if (active &&
10879 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10880 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10881 intel_dump_pipe_config(crtc, &pipe_config,
10882 "[hw state]");
10883 intel_dump_pipe_config(crtc, crtc->config,
10884 "[sw state]");
10885 }
10886 }
10887 }
10888
10889 static void
10890 check_shared_dpll_state(struct drm_device *dev)
10891 {
10892 struct drm_i915_private *dev_priv = dev->dev_private;
10893 struct intel_crtc *crtc;
10894 struct intel_dpll_hw_state dpll_hw_state;
10895 int i;
10896
10897 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10898 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10899 int enabled_crtcs = 0, active_crtcs = 0;
10900 bool active;
10901
10902 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10903
10904 DRM_DEBUG_KMS("%s\n", pll->name);
10905
10906 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10907
10908 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10909 "more active pll users than references: %i vs %i\n",
10910 pll->active, hweight32(pll->config.crtc_mask));
10911 I915_STATE_WARN(pll->active && !pll->on,
10912 "pll in active use but not on in sw tracking\n");
10913 I915_STATE_WARN(pll->on && !pll->active,
10914 "pll in on but not on in use in sw tracking\n");
10915 I915_STATE_WARN(pll->on != active,
10916 "pll on state mismatch (expected %i, found %i)\n",
10917 pll->on, active);
10918
10919 for_each_intel_crtc(dev, crtc) {
10920 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10921 enabled_crtcs++;
10922 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10923 active_crtcs++;
10924 }
10925 I915_STATE_WARN(pll->active != active_crtcs,
10926 "pll active crtcs mismatch (expected %i, found %i)\n",
10927 pll->active, active_crtcs);
10928 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10929 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10930 hweight32(pll->config.crtc_mask), enabled_crtcs);
10931
10932 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10933 sizeof(dpll_hw_state)),
10934 "pll hw state mismatch\n");
10935 }
10936 }
10937
10938 void
10939 intel_modeset_check_state(struct drm_device *dev)
10940 {
10941 check_wm_state(dev);
10942 check_connector_state(dev);
10943 check_encoder_state(dev);
10944 check_crtc_state(dev);
10945 check_shared_dpll_state(dev);
10946 }
10947
10948 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10949 int dotclock)
10950 {
10951 /*
10952 * FDI already provided one idea for the dotclock.
10953 * Yell if the encoder disagrees.
10954 */
10955 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10956 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10957 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10958 }
10959
10960 static void update_scanline_offset(struct intel_crtc *crtc)
10961 {
10962 struct drm_device *dev = crtc->base.dev;
10963
10964 /*
10965 * The scanline counter increments at the leading edge of hsync.
10966 *
10967 * On most platforms it starts counting from vtotal-1 on the
10968 * first active line. That means the scanline counter value is
10969 * always one less than what we would expect. Ie. just after
10970 * start of vblank, which also occurs at start of hsync (on the
10971 * last active line), the scanline counter will read vblank_start-1.
10972 *
10973 * On gen2 the scanline counter starts counting from 1 instead
10974 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10975 * to keep the value positive), instead of adding one.
10976 *
10977 * On HSW+ the behaviour of the scanline counter depends on the output
10978 * type. For DP ports it behaves like most other platforms, but on HDMI
10979 * there's an extra 1 line difference. So we need to add two instead of
10980 * one to the value.
10981 */
10982 if (IS_GEN2(dev)) {
10983 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10984 int vtotal;
10985
10986 vtotal = mode->crtc_vtotal;
10987 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10988 vtotal /= 2;
10989
10990 crtc->scanline_offset = vtotal - 1;
10991 } else if (HAS_DDI(dev) &&
10992 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10993 crtc->scanline_offset = 2;
10994 } else
10995 crtc->scanline_offset = 1;
10996 }
10997
10998 static struct intel_crtc_state *
10999 intel_modeset_compute_config(struct drm_crtc *crtc,
11000 struct drm_display_mode *mode,
11001 struct drm_framebuffer *fb,
11002 unsigned *modeset_pipes,
11003 unsigned *prepare_pipes,
11004 unsigned *disable_pipes)
11005 {
11006 struct intel_crtc_state *pipe_config = NULL;
11007
11008 intel_modeset_affected_pipes(crtc, modeset_pipes,
11009 prepare_pipes, disable_pipes);
11010
11011 if ((*modeset_pipes) == 0)
11012 goto out;
11013
11014 /*
11015 * Note this needs changes when we start tracking multiple modes
11016 * and crtcs. At that point we'll need to compute the whole config
11017 * (i.e. one pipe_config for each crtc) rather than just the one
11018 * for this crtc.
11019 */
11020 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11021 if (IS_ERR(pipe_config)) {
11022 goto out;
11023 }
11024 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11025 "[modeset]");
11026
11027 out:
11028 return pipe_config;
11029 }
11030
11031 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11032 unsigned modeset_pipes,
11033 unsigned disable_pipes)
11034 {
11035 struct drm_i915_private *dev_priv = to_i915(dev);
11036 unsigned clear_pipes = modeset_pipes | disable_pipes;
11037 struct intel_crtc *intel_crtc;
11038 int ret = 0;
11039
11040 if (!dev_priv->display.crtc_compute_clock)
11041 return 0;
11042
11043 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11044 if (ret)
11045 goto done;
11046
11047 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11048 struct intel_crtc_state *state = intel_crtc->new_config;
11049 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11050 state);
11051 if (ret) {
11052 intel_shared_dpll_abort_config(dev_priv);
11053 goto done;
11054 }
11055 }
11056
11057 done:
11058 return ret;
11059 }
11060
11061 static int __intel_set_mode(struct drm_crtc *crtc,
11062 struct drm_display_mode *mode,
11063 int x, int y, struct drm_framebuffer *fb,
11064 struct intel_crtc_state *pipe_config,
11065 unsigned modeset_pipes,
11066 unsigned prepare_pipes,
11067 unsigned disable_pipes)
11068 {
11069 struct drm_device *dev = crtc->dev;
11070 struct drm_i915_private *dev_priv = dev->dev_private;
11071 struct drm_display_mode *saved_mode;
11072 struct intel_crtc *intel_crtc;
11073 int ret = 0;
11074
11075 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11076 if (!saved_mode)
11077 return -ENOMEM;
11078
11079 *saved_mode = crtc->mode;
11080
11081 if (modeset_pipes)
11082 to_intel_crtc(crtc)->new_config = pipe_config;
11083
11084 /*
11085 * See if the config requires any additional preparation, e.g.
11086 * to adjust global state with pipes off. We need to do this
11087 * here so we can get the modeset_pipe updated config for the new
11088 * mode set on this crtc. For other crtcs we need to use the
11089 * adjusted_mode bits in the crtc directly.
11090 */
11091 if (IS_VALLEYVIEW(dev)) {
11092 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11093
11094 /* may have added more to prepare_pipes than we should */
11095 prepare_pipes &= ~disable_pipes;
11096 }
11097
11098 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11099 if (ret)
11100 goto done;
11101
11102 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11103 intel_crtc_disable(&intel_crtc->base);
11104
11105 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11106 if (intel_crtc->base.enabled)
11107 dev_priv->display.crtc_disable(&intel_crtc->base);
11108 }
11109
11110 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11111 * to set it here already despite that we pass it down the callchain.
11112 *
11113 * Note we'll need to fix this up when we start tracking multiple
11114 * pipes; here we assume a single modeset_pipe and only track the
11115 * single crtc and mode.
11116 */
11117 if (modeset_pipes) {
11118 crtc->mode = *mode;
11119 /* mode_set/enable/disable functions rely on a correct pipe
11120 * config. */
11121 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11122
11123 /*
11124 * Calculate and store various constants which
11125 * are later needed by vblank and swap-completion
11126 * timestamping. They are derived from true hwmode.
11127 */
11128 drm_calc_timestamping_constants(crtc,
11129 &pipe_config->base.adjusted_mode);
11130 }
11131
11132 /* Only after disabling all output pipelines that will be changed can we
11133 * update the the output configuration. */
11134 intel_modeset_update_state(dev, prepare_pipes);
11135
11136 modeset_update_crtc_power_domains(dev);
11137
11138 /* Set up the DPLL and any encoders state that needs to adjust or depend
11139 * on the DPLL.
11140 */
11141 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11142 struct drm_plane *primary = intel_crtc->base.primary;
11143 int vdisplay, hdisplay;
11144
11145 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11146 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11147 fb, 0, 0,
11148 hdisplay, vdisplay,
11149 x << 16, y << 16,
11150 hdisplay << 16, vdisplay << 16);
11151 }
11152
11153 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11154 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11155 update_scanline_offset(intel_crtc);
11156
11157 dev_priv->display.crtc_enable(&intel_crtc->base);
11158 }
11159
11160 /* FIXME: add subpixel order */
11161 done:
11162 if (ret && crtc->enabled)
11163 crtc->mode = *saved_mode;
11164
11165 kfree(saved_mode);
11166 return ret;
11167 }
11168
11169 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11170 struct drm_display_mode *mode,
11171 int x, int y, struct drm_framebuffer *fb,
11172 struct intel_crtc_state *pipe_config,
11173 unsigned modeset_pipes,
11174 unsigned prepare_pipes,
11175 unsigned disable_pipes)
11176 {
11177 int ret;
11178
11179 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11180 prepare_pipes, disable_pipes);
11181
11182 if (ret == 0)
11183 intel_modeset_check_state(crtc->dev);
11184
11185 return ret;
11186 }
11187
11188 static int intel_set_mode(struct drm_crtc *crtc,
11189 struct drm_display_mode *mode,
11190 int x, int y, struct drm_framebuffer *fb)
11191 {
11192 struct intel_crtc_state *pipe_config;
11193 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11194
11195 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11196 &modeset_pipes,
11197 &prepare_pipes,
11198 &disable_pipes);
11199
11200 if (IS_ERR(pipe_config))
11201 return PTR_ERR(pipe_config);
11202
11203 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11204 modeset_pipes, prepare_pipes,
11205 disable_pipes);
11206 }
11207
11208 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11209 {
11210 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11211 }
11212
11213 #undef for_each_intel_crtc_masked
11214
11215 static void intel_set_config_free(struct intel_set_config *config)
11216 {
11217 if (!config)
11218 return;
11219
11220 kfree(config->save_connector_encoders);
11221 kfree(config->save_encoder_crtcs);
11222 kfree(config->save_crtc_enabled);
11223 kfree(config);
11224 }
11225
11226 static int intel_set_config_save_state(struct drm_device *dev,
11227 struct intel_set_config *config)
11228 {
11229 struct drm_crtc *crtc;
11230 struct drm_encoder *encoder;
11231 struct drm_connector *connector;
11232 int count;
11233
11234 config->save_crtc_enabled =
11235 kcalloc(dev->mode_config.num_crtc,
11236 sizeof(bool), GFP_KERNEL);
11237 if (!config->save_crtc_enabled)
11238 return -ENOMEM;
11239
11240 config->save_encoder_crtcs =
11241 kcalloc(dev->mode_config.num_encoder,
11242 sizeof(struct drm_crtc *), GFP_KERNEL);
11243 if (!config->save_encoder_crtcs)
11244 return -ENOMEM;
11245
11246 config->save_connector_encoders =
11247 kcalloc(dev->mode_config.num_connector,
11248 sizeof(struct drm_encoder *), GFP_KERNEL);
11249 if (!config->save_connector_encoders)
11250 return -ENOMEM;
11251
11252 /* Copy data. Note that driver private data is not affected.
11253 * Should anything bad happen only the expected state is
11254 * restored, not the drivers personal bookkeeping.
11255 */
11256 count = 0;
11257 for_each_crtc(dev, crtc) {
11258 config->save_crtc_enabled[count++] = crtc->enabled;
11259 }
11260
11261 count = 0;
11262 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11263 config->save_encoder_crtcs[count++] = encoder->crtc;
11264 }
11265
11266 count = 0;
11267 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11268 config->save_connector_encoders[count++] = connector->encoder;
11269 }
11270
11271 return 0;
11272 }
11273
11274 static void intel_set_config_restore_state(struct drm_device *dev,
11275 struct intel_set_config *config)
11276 {
11277 struct intel_crtc *crtc;
11278 struct intel_encoder *encoder;
11279 struct intel_connector *connector;
11280 int count;
11281
11282 count = 0;
11283 for_each_intel_crtc(dev, crtc) {
11284 crtc->new_enabled = config->save_crtc_enabled[count++];
11285
11286 if (crtc->new_enabled)
11287 crtc->new_config = crtc->config;
11288 else
11289 crtc->new_config = NULL;
11290 }
11291
11292 count = 0;
11293 for_each_intel_encoder(dev, encoder) {
11294 encoder->new_crtc =
11295 to_intel_crtc(config->save_encoder_crtcs[count++]);
11296 }
11297
11298 count = 0;
11299 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11300 connector->new_encoder =
11301 to_intel_encoder(config->save_connector_encoders[count++]);
11302 }
11303 }
11304
11305 static bool
11306 is_crtc_connector_off(struct drm_mode_set *set)
11307 {
11308 int i;
11309
11310 if (set->num_connectors == 0)
11311 return false;
11312
11313 if (WARN_ON(set->connectors == NULL))
11314 return false;
11315
11316 for (i = 0; i < set->num_connectors; i++)
11317 if (set->connectors[i]->encoder &&
11318 set->connectors[i]->encoder->crtc == set->crtc &&
11319 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11320 return true;
11321
11322 return false;
11323 }
11324
11325 static void
11326 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11327 struct intel_set_config *config)
11328 {
11329
11330 /* We should be able to check here if the fb has the same properties
11331 * and then just flip_or_move it */
11332 if (is_crtc_connector_off(set)) {
11333 config->mode_changed = true;
11334 } else if (set->crtc->primary->fb != set->fb) {
11335 /*
11336 * If we have no fb, we can only flip as long as the crtc is
11337 * active, otherwise we need a full mode set. The crtc may
11338 * be active if we've only disabled the primary plane, or
11339 * in fastboot situations.
11340 */
11341 if (set->crtc->primary->fb == NULL) {
11342 struct intel_crtc *intel_crtc =
11343 to_intel_crtc(set->crtc);
11344
11345 if (intel_crtc->active) {
11346 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11347 config->fb_changed = true;
11348 } else {
11349 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11350 config->mode_changed = true;
11351 }
11352 } else if (set->fb == NULL) {
11353 config->mode_changed = true;
11354 } else if (set->fb->pixel_format !=
11355 set->crtc->primary->fb->pixel_format) {
11356 config->mode_changed = true;
11357 } else {
11358 config->fb_changed = true;
11359 }
11360 }
11361
11362 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11363 config->fb_changed = true;
11364
11365 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11366 DRM_DEBUG_KMS("modes are different, full mode set\n");
11367 drm_mode_debug_printmodeline(&set->crtc->mode);
11368 drm_mode_debug_printmodeline(set->mode);
11369 config->mode_changed = true;
11370 }
11371
11372 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11373 set->crtc->base.id, config->mode_changed, config->fb_changed);
11374 }
11375
11376 static int
11377 intel_modeset_stage_output_state(struct drm_device *dev,
11378 struct drm_mode_set *set,
11379 struct intel_set_config *config)
11380 {
11381 struct intel_connector *connector;
11382 struct intel_encoder *encoder;
11383 struct intel_crtc *crtc;
11384 int ro;
11385
11386 /* The upper layers ensure that we either disable a crtc or have a list
11387 * of connectors. For paranoia, double-check this. */
11388 WARN_ON(!set->fb && (set->num_connectors != 0));
11389 WARN_ON(set->fb && (set->num_connectors == 0));
11390
11391 list_for_each_entry(connector, &dev->mode_config.connector_list,
11392 base.head) {
11393 /* Otherwise traverse passed in connector list and get encoders
11394 * for them. */
11395 for (ro = 0; ro < set->num_connectors; ro++) {
11396 if (set->connectors[ro] == &connector->base) {
11397 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11398 break;
11399 }
11400 }
11401
11402 /* If we disable the crtc, disable all its connectors. Also, if
11403 * the connector is on the changing crtc but not on the new
11404 * connector list, disable it. */
11405 if ((!set->fb || ro == set->num_connectors) &&
11406 connector->base.encoder &&
11407 connector->base.encoder->crtc == set->crtc) {
11408 connector->new_encoder = NULL;
11409
11410 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11411 connector->base.base.id,
11412 connector->base.name);
11413 }
11414
11415
11416 if (&connector->new_encoder->base != connector->base.encoder) {
11417 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11418 config->mode_changed = true;
11419 }
11420 }
11421 /* connector->new_encoder is now updated for all connectors. */
11422
11423 /* Update crtc of enabled connectors. */
11424 list_for_each_entry(connector, &dev->mode_config.connector_list,
11425 base.head) {
11426 struct drm_crtc *new_crtc;
11427
11428 if (!connector->new_encoder)
11429 continue;
11430
11431 new_crtc = connector->new_encoder->base.crtc;
11432
11433 for (ro = 0; ro < set->num_connectors; ro++) {
11434 if (set->connectors[ro] == &connector->base)
11435 new_crtc = set->crtc;
11436 }
11437
11438 /* Make sure the new CRTC will work with the encoder */
11439 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11440 new_crtc)) {
11441 return -EINVAL;
11442 }
11443 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11444
11445 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11446 connector->base.base.id,
11447 connector->base.name,
11448 new_crtc->base.id);
11449 }
11450
11451 /* Check for any encoders that needs to be disabled. */
11452 for_each_intel_encoder(dev, encoder) {
11453 int num_connectors = 0;
11454 list_for_each_entry(connector,
11455 &dev->mode_config.connector_list,
11456 base.head) {
11457 if (connector->new_encoder == encoder) {
11458 WARN_ON(!connector->new_encoder->new_crtc);
11459 num_connectors++;
11460 }
11461 }
11462
11463 if (num_connectors == 0)
11464 encoder->new_crtc = NULL;
11465 else if (num_connectors > 1)
11466 return -EINVAL;
11467
11468 /* Only now check for crtc changes so we don't miss encoders
11469 * that will be disabled. */
11470 if (&encoder->new_crtc->base != encoder->base.crtc) {
11471 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11472 config->mode_changed = true;
11473 }
11474 }
11475 /* Now we've also updated encoder->new_crtc for all encoders. */
11476 list_for_each_entry(connector, &dev->mode_config.connector_list,
11477 base.head) {
11478 if (connector->new_encoder)
11479 if (connector->new_encoder != connector->encoder)
11480 connector->encoder = connector->new_encoder;
11481 }
11482 for_each_intel_crtc(dev, crtc) {
11483 crtc->new_enabled = false;
11484
11485 for_each_intel_encoder(dev, encoder) {
11486 if (encoder->new_crtc == crtc) {
11487 crtc->new_enabled = true;
11488 break;
11489 }
11490 }
11491
11492 if (crtc->new_enabled != crtc->base.enabled) {
11493 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11494 crtc->new_enabled ? "en" : "dis");
11495 config->mode_changed = true;
11496 }
11497
11498 if (crtc->new_enabled)
11499 crtc->new_config = crtc->config;
11500 else
11501 crtc->new_config = NULL;
11502 }
11503
11504 return 0;
11505 }
11506
11507 static void disable_crtc_nofb(struct intel_crtc *crtc)
11508 {
11509 struct drm_device *dev = crtc->base.dev;
11510 struct intel_encoder *encoder;
11511 struct intel_connector *connector;
11512
11513 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11514 pipe_name(crtc->pipe));
11515
11516 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11517 if (connector->new_encoder &&
11518 connector->new_encoder->new_crtc == crtc)
11519 connector->new_encoder = NULL;
11520 }
11521
11522 for_each_intel_encoder(dev, encoder) {
11523 if (encoder->new_crtc == crtc)
11524 encoder->new_crtc = NULL;
11525 }
11526
11527 crtc->new_enabled = false;
11528 crtc->new_config = NULL;
11529 }
11530
11531 static int intel_crtc_set_config(struct drm_mode_set *set)
11532 {
11533 struct drm_device *dev;
11534 struct drm_mode_set save_set;
11535 struct intel_set_config *config;
11536 struct intel_crtc_state *pipe_config;
11537 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11538 int ret;
11539
11540 BUG_ON(!set);
11541 BUG_ON(!set->crtc);
11542 BUG_ON(!set->crtc->helper_private);
11543
11544 /* Enforce sane interface api - has been abused by the fb helper. */
11545 BUG_ON(!set->mode && set->fb);
11546 BUG_ON(set->fb && set->num_connectors == 0);
11547
11548 if (set->fb) {
11549 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11550 set->crtc->base.id, set->fb->base.id,
11551 (int)set->num_connectors, set->x, set->y);
11552 } else {
11553 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11554 }
11555
11556 dev = set->crtc->dev;
11557
11558 ret = -ENOMEM;
11559 config = kzalloc(sizeof(*config), GFP_KERNEL);
11560 if (!config)
11561 goto out_config;
11562
11563 ret = intel_set_config_save_state(dev, config);
11564 if (ret)
11565 goto out_config;
11566
11567 save_set.crtc = set->crtc;
11568 save_set.mode = &set->crtc->mode;
11569 save_set.x = set->crtc->x;
11570 save_set.y = set->crtc->y;
11571 save_set.fb = set->crtc->primary->fb;
11572
11573 /* Compute whether we need a full modeset, only an fb base update or no
11574 * change at all. In the future we might also check whether only the
11575 * mode changed, e.g. for LVDS where we only change the panel fitter in
11576 * such cases. */
11577 intel_set_config_compute_mode_changes(set, config);
11578
11579 ret = intel_modeset_stage_output_state(dev, set, config);
11580 if (ret)
11581 goto fail;
11582
11583 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11584 set->fb,
11585 &modeset_pipes,
11586 &prepare_pipes,
11587 &disable_pipes);
11588 if (IS_ERR(pipe_config)) {
11589 ret = PTR_ERR(pipe_config);
11590 goto fail;
11591 } else if (pipe_config) {
11592 if (pipe_config->has_audio !=
11593 to_intel_crtc(set->crtc)->config->has_audio)
11594 config->mode_changed = true;
11595
11596 /*
11597 * Note we have an issue here with infoframes: current code
11598 * only updates them on the full mode set path per hw
11599 * requirements. So here we should be checking for any
11600 * required changes and forcing a mode set.
11601 */
11602 }
11603
11604 /* set_mode will free it in the mode_changed case */
11605 if (!config->mode_changed)
11606 kfree(pipe_config);
11607
11608 intel_update_pipe_size(to_intel_crtc(set->crtc));
11609
11610 if (config->mode_changed) {
11611 ret = intel_set_mode_pipes(set->crtc, set->mode,
11612 set->x, set->y, set->fb, pipe_config,
11613 modeset_pipes, prepare_pipes,
11614 disable_pipes);
11615 } else if (config->fb_changed) {
11616 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11617 struct drm_plane *primary = set->crtc->primary;
11618 int vdisplay, hdisplay;
11619
11620 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11621 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11622 0, 0, hdisplay, vdisplay,
11623 set->x << 16, set->y << 16,
11624 hdisplay << 16, vdisplay << 16);
11625
11626 /*
11627 * We need to make sure the primary plane is re-enabled if it
11628 * has previously been turned off.
11629 */
11630 if (!intel_crtc->primary_enabled && ret == 0) {
11631 WARN_ON(!intel_crtc->active);
11632 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11633 }
11634
11635 /*
11636 * In the fastboot case this may be our only check of the
11637 * state after boot. It would be better to only do it on
11638 * the first update, but we don't have a nice way of doing that
11639 * (and really, set_config isn't used much for high freq page
11640 * flipping, so increasing its cost here shouldn't be a big
11641 * deal).
11642 */
11643 if (i915.fastboot && ret == 0)
11644 intel_modeset_check_state(set->crtc->dev);
11645 }
11646
11647 if (ret) {
11648 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11649 set->crtc->base.id, ret);
11650 fail:
11651 intel_set_config_restore_state(dev, config);
11652
11653 /*
11654 * HACK: if the pipe was on, but we didn't have a framebuffer,
11655 * force the pipe off to avoid oopsing in the modeset code
11656 * due to fb==NULL. This should only happen during boot since
11657 * we don't yet reconstruct the FB from the hardware state.
11658 */
11659 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11660 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11661
11662 /* Try to restore the config */
11663 if (config->mode_changed &&
11664 intel_set_mode(save_set.crtc, save_set.mode,
11665 save_set.x, save_set.y, save_set.fb))
11666 DRM_ERROR("failed to restore config after modeset failure\n");
11667 }
11668
11669 out_config:
11670 intel_set_config_free(config);
11671 return ret;
11672 }
11673
11674 static const struct drm_crtc_funcs intel_crtc_funcs = {
11675 .gamma_set = intel_crtc_gamma_set,
11676 .set_config = intel_crtc_set_config,
11677 .destroy = intel_crtc_destroy,
11678 .page_flip = intel_crtc_page_flip,
11679 .atomic_duplicate_state = intel_crtc_duplicate_state,
11680 .atomic_destroy_state = intel_crtc_destroy_state,
11681 };
11682
11683 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11684 struct intel_shared_dpll *pll,
11685 struct intel_dpll_hw_state *hw_state)
11686 {
11687 uint32_t val;
11688
11689 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11690 return false;
11691
11692 val = I915_READ(PCH_DPLL(pll->id));
11693 hw_state->dpll = val;
11694 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11695 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11696
11697 return val & DPLL_VCO_ENABLE;
11698 }
11699
11700 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11701 struct intel_shared_dpll *pll)
11702 {
11703 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11704 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11705 }
11706
11707 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11708 struct intel_shared_dpll *pll)
11709 {
11710 /* PCH refclock must be enabled first */
11711 ibx_assert_pch_refclk_enabled(dev_priv);
11712
11713 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11714
11715 /* Wait for the clocks to stabilize. */
11716 POSTING_READ(PCH_DPLL(pll->id));
11717 udelay(150);
11718
11719 /* The pixel multiplier can only be updated once the
11720 * DPLL is enabled and the clocks are stable.
11721 *
11722 * So write it again.
11723 */
11724 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11725 POSTING_READ(PCH_DPLL(pll->id));
11726 udelay(200);
11727 }
11728
11729 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11730 struct intel_shared_dpll *pll)
11731 {
11732 struct drm_device *dev = dev_priv->dev;
11733 struct intel_crtc *crtc;
11734
11735 /* Make sure no transcoder isn't still depending on us. */
11736 for_each_intel_crtc(dev, crtc) {
11737 if (intel_crtc_to_shared_dpll(crtc) == pll)
11738 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11739 }
11740
11741 I915_WRITE(PCH_DPLL(pll->id), 0);
11742 POSTING_READ(PCH_DPLL(pll->id));
11743 udelay(200);
11744 }
11745
11746 static char *ibx_pch_dpll_names[] = {
11747 "PCH DPLL A",
11748 "PCH DPLL B",
11749 };
11750
11751 static void ibx_pch_dpll_init(struct drm_device *dev)
11752 {
11753 struct drm_i915_private *dev_priv = dev->dev_private;
11754 int i;
11755
11756 dev_priv->num_shared_dpll = 2;
11757
11758 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11759 dev_priv->shared_dplls[i].id = i;
11760 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11761 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11762 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11763 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11764 dev_priv->shared_dplls[i].get_hw_state =
11765 ibx_pch_dpll_get_hw_state;
11766 }
11767 }
11768
11769 static void intel_shared_dpll_init(struct drm_device *dev)
11770 {
11771 struct drm_i915_private *dev_priv = dev->dev_private;
11772
11773 if (HAS_DDI(dev))
11774 intel_ddi_pll_init(dev);
11775 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11776 ibx_pch_dpll_init(dev);
11777 else
11778 dev_priv->num_shared_dpll = 0;
11779
11780 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11781 }
11782
11783 /**
11784 * intel_prepare_plane_fb - Prepare fb for usage on plane
11785 * @plane: drm plane to prepare for
11786 * @fb: framebuffer to prepare for presentation
11787 *
11788 * Prepares a framebuffer for usage on a display plane. Generally this
11789 * involves pinning the underlying object and updating the frontbuffer tracking
11790 * bits. Some older platforms need special physical address handling for
11791 * cursor planes.
11792 *
11793 * Returns 0 on success, negative error code on failure.
11794 */
11795 int
11796 intel_prepare_plane_fb(struct drm_plane *plane,
11797 struct drm_framebuffer *fb)
11798 {
11799 struct drm_device *dev = plane->dev;
11800 struct intel_plane *intel_plane = to_intel_plane(plane);
11801 enum pipe pipe = intel_plane->pipe;
11802 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11803 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11804 unsigned frontbuffer_bits = 0;
11805 int ret = 0;
11806
11807 if (!obj)
11808 return 0;
11809
11810 switch (plane->type) {
11811 case DRM_PLANE_TYPE_PRIMARY:
11812 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11813 break;
11814 case DRM_PLANE_TYPE_CURSOR:
11815 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11816 break;
11817 case DRM_PLANE_TYPE_OVERLAY:
11818 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11819 break;
11820 }
11821
11822 mutex_lock(&dev->struct_mutex);
11823
11824 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11825 INTEL_INFO(dev)->cursor_needs_physical) {
11826 int align = IS_I830(dev) ? 16 * 1024 : 256;
11827 ret = i915_gem_object_attach_phys(obj, align);
11828 if (ret)
11829 DRM_DEBUG_KMS("failed to attach phys object\n");
11830 } else {
11831 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11832 }
11833
11834 if (ret == 0)
11835 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11836
11837 mutex_unlock(&dev->struct_mutex);
11838
11839 return ret;
11840 }
11841
11842 /**
11843 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11844 * @plane: drm plane to clean up for
11845 * @fb: old framebuffer that was on plane
11846 *
11847 * Cleans up a framebuffer that has just been removed from a plane.
11848 */
11849 void
11850 intel_cleanup_plane_fb(struct drm_plane *plane,
11851 struct drm_framebuffer *fb)
11852 {
11853 struct drm_device *dev = plane->dev;
11854 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11855
11856 if (WARN_ON(!obj))
11857 return;
11858
11859 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11860 !INTEL_INFO(dev)->cursor_needs_physical) {
11861 mutex_lock(&dev->struct_mutex);
11862 intel_unpin_fb_obj(obj);
11863 mutex_unlock(&dev->struct_mutex);
11864 }
11865 }
11866
11867 static int
11868 intel_check_primary_plane(struct drm_plane *plane,
11869 struct intel_plane_state *state)
11870 {
11871 struct drm_device *dev = plane->dev;
11872 struct drm_i915_private *dev_priv = dev->dev_private;
11873 struct drm_crtc *crtc = state->base.crtc;
11874 struct intel_crtc *intel_crtc;
11875 struct drm_framebuffer *fb = state->base.fb;
11876 struct drm_rect *dest = &state->dst;
11877 struct drm_rect *src = &state->src;
11878 const struct drm_rect *clip = &state->clip;
11879 int ret;
11880
11881 crtc = crtc ? crtc : plane->crtc;
11882 intel_crtc = to_intel_crtc(crtc);
11883
11884 ret = drm_plane_helper_check_update(plane, crtc, fb,
11885 src, dest, clip,
11886 DRM_PLANE_HELPER_NO_SCALING,
11887 DRM_PLANE_HELPER_NO_SCALING,
11888 false, true, &state->visible);
11889 if (ret)
11890 return ret;
11891
11892 if (intel_crtc->active) {
11893 intel_crtc->atomic.wait_for_flips = true;
11894
11895 /*
11896 * FBC does not work on some platforms for rotated
11897 * planes, so disable it when rotation is not 0 and
11898 * update it when rotation is set back to 0.
11899 *
11900 * FIXME: This is redundant with the fbc update done in
11901 * the primary plane enable function except that that
11902 * one is done too late. We eventually need to unify
11903 * this.
11904 */
11905 if (intel_crtc->primary_enabled &&
11906 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11907 dev_priv->fbc.plane == intel_crtc->plane &&
11908 state->base.rotation != BIT(DRM_ROTATE_0)) {
11909 intel_crtc->atomic.disable_fbc = true;
11910 }
11911
11912 if (state->visible) {
11913 /*
11914 * BDW signals flip done immediately if the plane
11915 * is disabled, even if the plane enable is already
11916 * armed to occur at the next vblank :(
11917 */
11918 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11919 intel_crtc->atomic.wait_vblank = true;
11920 }
11921
11922 intel_crtc->atomic.fb_bits |=
11923 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11924
11925 intel_crtc->atomic.update_fbc = true;
11926 }
11927
11928 return 0;
11929 }
11930
11931 static void
11932 intel_commit_primary_plane(struct drm_plane *plane,
11933 struct intel_plane_state *state)
11934 {
11935 struct drm_crtc *crtc = state->base.crtc;
11936 struct drm_framebuffer *fb = state->base.fb;
11937 struct drm_device *dev = plane->dev;
11938 struct drm_i915_private *dev_priv = dev->dev_private;
11939 struct intel_crtc *intel_crtc;
11940 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11941 struct intel_plane *intel_plane = to_intel_plane(plane);
11942 struct drm_rect *src = &state->src;
11943
11944 crtc = crtc ? crtc : plane->crtc;
11945 intel_crtc = to_intel_crtc(crtc);
11946
11947 plane->fb = fb;
11948 crtc->x = src->x1 >> 16;
11949 crtc->y = src->y1 >> 16;
11950
11951 intel_plane->obj = obj;
11952
11953 if (intel_crtc->active) {
11954 if (state->visible) {
11955 /* FIXME: kill this fastboot hack */
11956 intel_update_pipe_size(intel_crtc);
11957
11958 intel_crtc->primary_enabled = true;
11959
11960 dev_priv->display.update_primary_plane(crtc, plane->fb,
11961 crtc->x, crtc->y);
11962 } else {
11963 /*
11964 * If clipping results in a non-visible primary plane,
11965 * we'll disable the primary plane. Note that this is
11966 * a bit different than what happens if userspace
11967 * explicitly disables the plane by passing fb=0
11968 * because plane->fb still gets set and pinned.
11969 */
11970 intel_disable_primary_hw_plane(plane, crtc);
11971 }
11972 }
11973 }
11974
11975 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11976 {
11977 struct drm_device *dev = crtc->dev;
11978 struct drm_i915_private *dev_priv = dev->dev_private;
11979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11980 struct intel_plane *intel_plane;
11981 struct drm_plane *p;
11982 unsigned fb_bits = 0;
11983
11984 /* Track fb's for any planes being disabled */
11985 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11986 intel_plane = to_intel_plane(p);
11987
11988 if (intel_crtc->atomic.disabled_planes &
11989 (1 << drm_plane_index(p))) {
11990 switch (p->type) {
11991 case DRM_PLANE_TYPE_PRIMARY:
11992 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
11993 break;
11994 case DRM_PLANE_TYPE_CURSOR:
11995 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
11996 break;
11997 case DRM_PLANE_TYPE_OVERLAY:
11998 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
11999 break;
12000 }
12001
12002 mutex_lock(&dev->struct_mutex);
12003 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12004 mutex_unlock(&dev->struct_mutex);
12005 }
12006 }
12007
12008 if (intel_crtc->atomic.wait_for_flips)
12009 intel_crtc_wait_for_pending_flips(crtc);
12010
12011 if (intel_crtc->atomic.disable_fbc)
12012 intel_fbc_disable(dev);
12013
12014 if (intel_crtc->atomic.pre_disable_primary)
12015 intel_pre_disable_primary(crtc);
12016
12017 if (intel_crtc->atomic.update_wm)
12018 intel_update_watermarks(crtc);
12019
12020 intel_runtime_pm_get(dev_priv);
12021
12022 /* Perform vblank evasion around commit operation */
12023 if (intel_crtc->active)
12024 intel_crtc->atomic.evade =
12025 intel_pipe_update_start(intel_crtc,
12026 &intel_crtc->atomic.start_vbl_count);
12027 }
12028
12029 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12030 {
12031 struct drm_device *dev = crtc->dev;
12032 struct drm_i915_private *dev_priv = dev->dev_private;
12033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12034 struct drm_plane *p;
12035
12036 if (intel_crtc->atomic.evade)
12037 intel_pipe_update_end(intel_crtc,
12038 intel_crtc->atomic.start_vbl_count);
12039
12040 intel_runtime_pm_put(dev_priv);
12041
12042 if (intel_crtc->atomic.wait_vblank)
12043 intel_wait_for_vblank(dev, intel_crtc->pipe);
12044
12045 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12046
12047 if (intel_crtc->atomic.update_fbc) {
12048 mutex_lock(&dev->struct_mutex);
12049 intel_fbc_update(dev);
12050 mutex_unlock(&dev->struct_mutex);
12051 }
12052
12053 if (intel_crtc->atomic.post_enable_primary)
12054 intel_post_enable_primary(crtc);
12055
12056 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12057 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12058 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12059 false, false);
12060
12061 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12062 }
12063
12064 /**
12065 * intel_plane_destroy - destroy a plane
12066 * @plane: plane to destroy
12067 *
12068 * Common destruction function for all types of planes (primary, cursor,
12069 * sprite).
12070 */
12071 void intel_plane_destroy(struct drm_plane *plane)
12072 {
12073 struct intel_plane *intel_plane = to_intel_plane(plane);
12074 drm_plane_cleanup(plane);
12075 kfree(intel_plane);
12076 }
12077
12078 const struct drm_plane_funcs intel_plane_funcs = {
12079 .update_plane = drm_plane_helper_update,
12080 .disable_plane = drm_plane_helper_disable,
12081 .destroy = intel_plane_destroy,
12082 .set_property = drm_atomic_helper_plane_set_property,
12083 .atomic_get_property = intel_plane_atomic_get_property,
12084 .atomic_set_property = intel_plane_atomic_set_property,
12085 .atomic_duplicate_state = intel_plane_duplicate_state,
12086 .atomic_destroy_state = intel_plane_destroy_state,
12087
12088 };
12089
12090 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12091 int pipe)
12092 {
12093 struct intel_plane *primary;
12094 struct intel_plane_state *state;
12095 const uint32_t *intel_primary_formats;
12096 int num_formats;
12097
12098 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12099 if (primary == NULL)
12100 return NULL;
12101
12102 state = intel_create_plane_state(&primary->base);
12103 if (!state) {
12104 kfree(primary);
12105 return NULL;
12106 }
12107 primary->base.state = &state->base;
12108
12109 primary->can_scale = false;
12110 primary->max_downscale = 1;
12111 primary->pipe = pipe;
12112 primary->plane = pipe;
12113 primary->check_plane = intel_check_primary_plane;
12114 primary->commit_plane = intel_commit_primary_plane;
12115 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12116 primary->plane = !pipe;
12117
12118 if (INTEL_INFO(dev)->gen <= 3) {
12119 intel_primary_formats = intel_primary_formats_gen2;
12120 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12121 } else {
12122 intel_primary_formats = intel_primary_formats_gen4;
12123 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12124 }
12125
12126 drm_universal_plane_init(dev, &primary->base, 0,
12127 &intel_plane_funcs,
12128 intel_primary_formats, num_formats,
12129 DRM_PLANE_TYPE_PRIMARY);
12130
12131 if (INTEL_INFO(dev)->gen >= 4) {
12132 if (!dev->mode_config.rotation_property)
12133 dev->mode_config.rotation_property =
12134 drm_mode_create_rotation_property(dev,
12135 BIT(DRM_ROTATE_0) |
12136 BIT(DRM_ROTATE_180));
12137 if (dev->mode_config.rotation_property)
12138 drm_object_attach_property(&primary->base.base,
12139 dev->mode_config.rotation_property,
12140 state->base.rotation);
12141 }
12142
12143 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12144
12145 return &primary->base;
12146 }
12147
12148 static int
12149 intel_check_cursor_plane(struct drm_plane *plane,
12150 struct intel_plane_state *state)
12151 {
12152 struct drm_crtc *crtc = state->base.crtc;
12153 struct drm_device *dev = plane->dev;
12154 struct drm_framebuffer *fb = state->base.fb;
12155 struct drm_rect *dest = &state->dst;
12156 struct drm_rect *src = &state->src;
12157 const struct drm_rect *clip = &state->clip;
12158 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12159 struct intel_crtc *intel_crtc;
12160 unsigned stride;
12161 int ret;
12162
12163 crtc = crtc ? crtc : plane->crtc;
12164 intel_crtc = to_intel_crtc(crtc);
12165
12166 ret = drm_plane_helper_check_update(plane, crtc, fb,
12167 src, dest, clip,
12168 DRM_PLANE_HELPER_NO_SCALING,
12169 DRM_PLANE_HELPER_NO_SCALING,
12170 true, true, &state->visible);
12171 if (ret)
12172 return ret;
12173
12174
12175 /* if we want to turn off the cursor ignore width and height */
12176 if (!obj)
12177 goto finish;
12178
12179 /* Check for which cursor types we support */
12180 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12181 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12182 state->base.crtc_w, state->base.crtc_h);
12183 return -EINVAL;
12184 }
12185
12186 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12187 if (obj->base.size < stride * state->base.crtc_h) {
12188 DRM_DEBUG_KMS("buffer is too small\n");
12189 return -ENOMEM;
12190 }
12191
12192 if (fb == crtc->cursor->fb)
12193 return 0;
12194
12195 /* we only need to pin inside GTT if cursor is non-phy */
12196 mutex_lock(&dev->struct_mutex);
12197 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12198 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12199 ret = -EINVAL;
12200 }
12201 mutex_unlock(&dev->struct_mutex);
12202
12203 finish:
12204 if (intel_crtc->active) {
12205 if (intel_crtc->cursor_width != state->base.crtc_w)
12206 intel_crtc->atomic.update_wm = true;
12207
12208 intel_crtc->atomic.fb_bits |=
12209 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12210 }
12211
12212 return ret;
12213 }
12214
12215 static void
12216 intel_commit_cursor_plane(struct drm_plane *plane,
12217 struct intel_plane_state *state)
12218 {
12219 struct drm_crtc *crtc = state->base.crtc;
12220 struct drm_device *dev = plane->dev;
12221 struct intel_crtc *intel_crtc;
12222 struct intel_plane *intel_plane = to_intel_plane(plane);
12223 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12224 uint32_t addr;
12225
12226 crtc = crtc ? crtc : plane->crtc;
12227 intel_crtc = to_intel_crtc(crtc);
12228
12229 plane->fb = state->base.fb;
12230 crtc->cursor_x = state->base.crtc_x;
12231 crtc->cursor_y = state->base.crtc_y;
12232
12233 intel_plane->obj = obj;
12234
12235 if (intel_crtc->cursor_bo == obj)
12236 goto update;
12237
12238 if (!obj)
12239 addr = 0;
12240 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12241 addr = i915_gem_obj_ggtt_offset(obj);
12242 else
12243 addr = obj->phys_handle->busaddr;
12244
12245 intel_crtc->cursor_addr = addr;
12246 intel_crtc->cursor_bo = obj;
12247 update:
12248 intel_crtc->cursor_width = state->base.crtc_w;
12249 intel_crtc->cursor_height = state->base.crtc_h;
12250
12251 if (intel_crtc->active)
12252 intel_crtc_update_cursor(crtc, state->visible);
12253 }
12254
12255 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12256 int pipe)
12257 {
12258 struct intel_plane *cursor;
12259 struct intel_plane_state *state;
12260
12261 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12262 if (cursor == NULL)
12263 return NULL;
12264
12265 state = intel_create_plane_state(&cursor->base);
12266 if (!state) {
12267 kfree(cursor);
12268 return NULL;
12269 }
12270 cursor->base.state = &state->base;
12271
12272 cursor->can_scale = false;
12273 cursor->max_downscale = 1;
12274 cursor->pipe = pipe;
12275 cursor->plane = pipe;
12276 cursor->check_plane = intel_check_cursor_plane;
12277 cursor->commit_plane = intel_commit_cursor_plane;
12278
12279 drm_universal_plane_init(dev, &cursor->base, 0,
12280 &intel_plane_funcs,
12281 intel_cursor_formats,
12282 ARRAY_SIZE(intel_cursor_formats),
12283 DRM_PLANE_TYPE_CURSOR);
12284
12285 if (INTEL_INFO(dev)->gen >= 4) {
12286 if (!dev->mode_config.rotation_property)
12287 dev->mode_config.rotation_property =
12288 drm_mode_create_rotation_property(dev,
12289 BIT(DRM_ROTATE_0) |
12290 BIT(DRM_ROTATE_180));
12291 if (dev->mode_config.rotation_property)
12292 drm_object_attach_property(&cursor->base.base,
12293 dev->mode_config.rotation_property,
12294 state->base.rotation);
12295 }
12296
12297 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12298
12299 return &cursor->base;
12300 }
12301
12302 static void intel_crtc_init(struct drm_device *dev, int pipe)
12303 {
12304 struct drm_i915_private *dev_priv = dev->dev_private;
12305 struct intel_crtc *intel_crtc;
12306 struct intel_crtc_state *crtc_state = NULL;
12307 struct drm_plane *primary = NULL;
12308 struct drm_plane *cursor = NULL;
12309 int i, ret;
12310
12311 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12312 if (intel_crtc == NULL)
12313 return;
12314
12315 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12316 if (!crtc_state)
12317 goto fail;
12318 intel_crtc_set_state(intel_crtc, crtc_state);
12319
12320 primary = intel_primary_plane_create(dev, pipe);
12321 if (!primary)
12322 goto fail;
12323
12324 cursor = intel_cursor_plane_create(dev, pipe);
12325 if (!cursor)
12326 goto fail;
12327
12328 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12329 cursor, &intel_crtc_funcs);
12330 if (ret)
12331 goto fail;
12332
12333 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12334 for (i = 0; i < 256; i++) {
12335 intel_crtc->lut_r[i] = i;
12336 intel_crtc->lut_g[i] = i;
12337 intel_crtc->lut_b[i] = i;
12338 }
12339
12340 /*
12341 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12342 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12343 */
12344 intel_crtc->pipe = pipe;
12345 intel_crtc->plane = pipe;
12346 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12347 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12348 intel_crtc->plane = !pipe;
12349 }
12350
12351 intel_crtc->cursor_base = ~0;
12352 intel_crtc->cursor_cntl = ~0;
12353 intel_crtc->cursor_size = ~0;
12354
12355 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12356 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12357 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12358 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12359
12360 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12361
12362 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12363
12364 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12365 return;
12366
12367 fail:
12368 if (primary)
12369 drm_plane_cleanup(primary);
12370 if (cursor)
12371 drm_plane_cleanup(cursor);
12372 kfree(crtc_state);
12373 kfree(intel_crtc);
12374 }
12375
12376 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12377 {
12378 struct drm_encoder *encoder = connector->base.encoder;
12379 struct drm_device *dev = connector->base.dev;
12380
12381 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12382
12383 if (!encoder || WARN_ON(!encoder->crtc))
12384 return INVALID_PIPE;
12385
12386 return to_intel_crtc(encoder->crtc)->pipe;
12387 }
12388
12389 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12390 struct drm_file *file)
12391 {
12392 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12393 struct drm_crtc *drmmode_crtc;
12394 struct intel_crtc *crtc;
12395
12396 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12397 return -ENODEV;
12398
12399 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12400
12401 if (!drmmode_crtc) {
12402 DRM_ERROR("no such CRTC id\n");
12403 return -ENOENT;
12404 }
12405
12406 crtc = to_intel_crtc(drmmode_crtc);
12407 pipe_from_crtc_id->pipe = crtc->pipe;
12408
12409 return 0;
12410 }
12411
12412 static int intel_encoder_clones(struct intel_encoder *encoder)
12413 {
12414 struct drm_device *dev = encoder->base.dev;
12415 struct intel_encoder *source_encoder;
12416 int index_mask = 0;
12417 int entry = 0;
12418
12419 for_each_intel_encoder(dev, source_encoder) {
12420 if (encoders_cloneable(encoder, source_encoder))
12421 index_mask |= (1 << entry);
12422
12423 entry++;
12424 }
12425
12426 return index_mask;
12427 }
12428
12429 static bool has_edp_a(struct drm_device *dev)
12430 {
12431 struct drm_i915_private *dev_priv = dev->dev_private;
12432
12433 if (!IS_MOBILE(dev))
12434 return false;
12435
12436 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12437 return false;
12438
12439 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12440 return false;
12441
12442 return true;
12443 }
12444
12445 static bool intel_crt_present(struct drm_device *dev)
12446 {
12447 struct drm_i915_private *dev_priv = dev->dev_private;
12448
12449 if (INTEL_INFO(dev)->gen >= 9)
12450 return false;
12451
12452 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12453 return false;
12454
12455 if (IS_CHERRYVIEW(dev))
12456 return false;
12457
12458 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12459 return false;
12460
12461 return true;
12462 }
12463
12464 static void intel_setup_outputs(struct drm_device *dev)
12465 {
12466 struct drm_i915_private *dev_priv = dev->dev_private;
12467 struct intel_encoder *encoder;
12468 struct drm_connector *connector;
12469 bool dpd_is_edp = false;
12470
12471 intel_lvds_init(dev);
12472
12473 if (intel_crt_present(dev))
12474 intel_crt_init(dev);
12475
12476 if (HAS_DDI(dev)) {
12477 int found;
12478
12479 /* Haswell uses DDI functions to detect digital outputs */
12480 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12481 /* DDI A only supports eDP */
12482 if (found)
12483 intel_ddi_init(dev, PORT_A);
12484
12485 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12486 * register */
12487 found = I915_READ(SFUSE_STRAP);
12488
12489 if (found & SFUSE_STRAP_DDIB_DETECTED)
12490 intel_ddi_init(dev, PORT_B);
12491 if (found & SFUSE_STRAP_DDIC_DETECTED)
12492 intel_ddi_init(dev, PORT_C);
12493 if (found & SFUSE_STRAP_DDID_DETECTED)
12494 intel_ddi_init(dev, PORT_D);
12495 } else if (HAS_PCH_SPLIT(dev)) {
12496 int found;
12497 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12498
12499 if (has_edp_a(dev))
12500 intel_dp_init(dev, DP_A, PORT_A);
12501
12502 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12503 /* PCH SDVOB multiplex with HDMIB */
12504 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12505 if (!found)
12506 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12507 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12508 intel_dp_init(dev, PCH_DP_B, PORT_B);
12509 }
12510
12511 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12512 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12513
12514 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12515 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12516
12517 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12518 intel_dp_init(dev, PCH_DP_C, PORT_C);
12519
12520 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12521 intel_dp_init(dev, PCH_DP_D, PORT_D);
12522 } else if (IS_VALLEYVIEW(dev)) {
12523 /*
12524 * The DP_DETECTED bit is the latched state of the DDC
12525 * SDA pin at boot. However since eDP doesn't require DDC
12526 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12527 * eDP ports may have been muxed to an alternate function.
12528 * Thus we can't rely on the DP_DETECTED bit alone to detect
12529 * eDP ports. Consult the VBT as well as DP_DETECTED to
12530 * detect eDP ports.
12531 */
12532 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12533 !intel_dp_is_edp(dev, PORT_B))
12534 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12535 PORT_B);
12536 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12537 intel_dp_is_edp(dev, PORT_B))
12538 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12539
12540 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12541 !intel_dp_is_edp(dev, PORT_C))
12542 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12543 PORT_C);
12544 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12545 intel_dp_is_edp(dev, PORT_C))
12546 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12547
12548 if (IS_CHERRYVIEW(dev)) {
12549 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12550 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12551 PORT_D);
12552 /* eDP not supported on port D, so don't check VBT */
12553 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12554 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12555 }
12556
12557 intel_dsi_init(dev);
12558 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12559 bool found = false;
12560
12561 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12562 DRM_DEBUG_KMS("probing SDVOB\n");
12563 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12564 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12565 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12566 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12567 }
12568
12569 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12570 intel_dp_init(dev, DP_B, PORT_B);
12571 }
12572
12573 /* Before G4X SDVOC doesn't have its own detect register */
12574
12575 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12576 DRM_DEBUG_KMS("probing SDVOC\n");
12577 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12578 }
12579
12580 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12581
12582 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12583 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12584 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12585 }
12586 if (SUPPORTS_INTEGRATED_DP(dev))
12587 intel_dp_init(dev, DP_C, PORT_C);
12588 }
12589
12590 if (SUPPORTS_INTEGRATED_DP(dev) &&
12591 (I915_READ(DP_D) & DP_DETECTED))
12592 intel_dp_init(dev, DP_D, PORT_D);
12593 } else if (IS_GEN2(dev))
12594 intel_dvo_init(dev);
12595
12596 if (SUPPORTS_TV(dev))
12597 intel_tv_init(dev);
12598
12599 /*
12600 * FIXME: We don't have full atomic support yet, but we want to be
12601 * able to enable/test plane updates via the atomic interface in the
12602 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12603 * will take some atomic codepaths to lookup properties during
12604 * drmModeGetConnector() that unconditionally dereference
12605 * connector->state.
12606 *
12607 * We create a dummy connector state here for each connector to ensure
12608 * the DRM core doesn't try to dereference a NULL connector->state.
12609 * The actual connector properties will never be updated or contain
12610 * useful information, but since we're doing this specifically for
12611 * testing/debug of the plane operations (and only when a specific
12612 * kernel module option is given), that shouldn't really matter.
12613 *
12614 * Once atomic support for crtc's + connectors lands, this loop should
12615 * be removed since we'll be setting up real connector state, which
12616 * will contain Intel-specific properties.
12617 */
12618 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12619 list_for_each_entry(connector,
12620 &dev->mode_config.connector_list,
12621 head) {
12622 if (!WARN_ON(connector->state)) {
12623 connector->state =
12624 kzalloc(sizeof(*connector->state),
12625 GFP_KERNEL);
12626 }
12627 }
12628 }
12629
12630 intel_psr_init(dev);
12631
12632 for_each_intel_encoder(dev, encoder) {
12633 encoder->base.possible_crtcs = encoder->crtc_mask;
12634 encoder->base.possible_clones =
12635 intel_encoder_clones(encoder);
12636 }
12637
12638 intel_init_pch_refclk(dev);
12639
12640 drm_helper_move_panel_connectors_to_head(dev);
12641 }
12642
12643 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12644 {
12645 struct drm_device *dev = fb->dev;
12646 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12647
12648 drm_framebuffer_cleanup(fb);
12649 mutex_lock(&dev->struct_mutex);
12650 WARN_ON(!intel_fb->obj->framebuffer_references--);
12651 drm_gem_object_unreference(&intel_fb->obj->base);
12652 mutex_unlock(&dev->struct_mutex);
12653 kfree(intel_fb);
12654 }
12655
12656 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12657 struct drm_file *file,
12658 unsigned int *handle)
12659 {
12660 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12661 struct drm_i915_gem_object *obj = intel_fb->obj;
12662
12663 return drm_gem_handle_create(file, &obj->base, handle);
12664 }
12665
12666 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12667 .destroy = intel_user_framebuffer_destroy,
12668 .create_handle = intel_user_framebuffer_create_handle,
12669 };
12670
12671 static int intel_framebuffer_init(struct drm_device *dev,
12672 struct intel_framebuffer *intel_fb,
12673 struct drm_mode_fb_cmd2 *mode_cmd,
12674 struct drm_i915_gem_object *obj)
12675 {
12676 int aligned_height;
12677 int pitch_limit;
12678 int ret;
12679
12680 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12681
12682 if (obj->tiling_mode == I915_TILING_Y) {
12683 DRM_DEBUG("hardware does not support tiling Y\n");
12684 return -EINVAL;
12685 }
12686
12687 if (mode_cmd->pitches[0] & 63) {
12688 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12689 mode_cmd->pitches[0]);
12690 return -EINVAL;
12691 }
12692
12693 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12694 pitch_limit = 32*1024;
12695 } else if (INTEL_INFO(dev)->gen >= 4) {
12696 if (obj->tiling_mode)
12697 pitch_limit = 16*1024;
12698 else
12699 pitch_limit = 32*1024;
12700 } else if (INTEL_INFO(dev)->gen >= 3) {
12701 if (obj->tiling_mode)
12702 pitch_limit = 8*1024;
12703 else
12704 pitch_limit = 16*1024;
12705 } else
12706 /* XXX DSPC is limited to 4k tiled */
12707 pitch_limit = 8*1024;
12708
12709 if (mode_cmd->pitches[0] > pitch_limit) {
12710 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12711 obj->tiling_mode ? "tiled" : "linear",
12712 mode_cmd->pitches[0], pitch_limit);
12713 return -EINVAL;
12714 }
12715
12716 if (obj->tiling_mode != I915_TILING_NONE &&
12717 mode_cmd->pitches[0] != obj->stride) {
12718 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12719 mode_cmd->pitches[0], obj->stride);
12720 return -EINVAL;
12721 }
12722
12723 /* Reject formats not supported by any plane early. */
12724 switch (mode_cmd->pixel_format) {
12725 case DRM_FORMAT_C8:
12726 case DRM_FORMAT_RGB565:
12727 case DRM_FORMAT_XRGB8888:
12728 case DRM_FORMAT_ARGB8888:
12729 break;
12730 case DRM_FORMAT_XRGB1555:
12731 case DRM_FORMAT_ARGB1555:
12732 if (INTEL_INFO(dev)->gen > 3) {
12733 DRM_DEBUG("unsupported pixel format: %s\n",
12734 drm_get_format_name(mode_cmd->pixel_format));
12735 return -EINVAL;
12736 }
12737 break;
12738 case DRM_FORMAT_XBGR8888:
12739 case DRM_FORMAT_ABGR8888:
12740 case DRM_FORMAT_XRGB2101010:
12741 case DRM_FORMAT_ARGB2101010:
12742 case DRM_FORMAT_XBGR2101010:
12743 case DRM_FORMAT_ABGR2101010:
12744 if (INTEL_INFO(dev)->gen < 4) {
12745 DRM_DEBUG("unsupported pixel format: %s\n",
12746 drm_get_format_name(mode_cmd->pixel_format));
12747 return -EINVAL;
12748 }
12749 break;
12750 case DRM_FORMAT_YUYV:
12751 case DRM_FORMAT_UYVY:
12752 case DRM_FORMAT_YVYU:
12753 case DRM_FORMAT_VYUY:
12754 if (INTEL_INFO(dev)->gen < 5) {
12755 DRM_DEBUG("unsupported pixel format: %s\n",
12756 drm_get_format_name(mode_cmd->pixel_format));
12757 return -EINVAL;
12758 }
12759 break;
12760 default:
12761 DRM_DEBUG("unsupported pixel format: %s\n",
12762 drm_get_format_name(mode_cmd->pixel_format));
12763 return -EINVAL;
12764 }
12765
12766 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12767 if (mode_cmd->offsets[0] != 0)
12768 return -EINVAL;
12769
12770 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12771 obj->tiling_mode);
12772 /* FIXME drm helper for size checks (especially planar formats)? */
12773 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12774 return -EINVAL;
12775
12776 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12777 intel_fb->obj = obj;
12778 intel_fb->obj->framebuffer_references++;
12779
12780 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12781 if (ret) {
12782 DRM_ERROR("framebuffer init failed %d\n", ret);
12783 return ret;
12784 }
12785
12786 return 0;
12787 }
12788
12789 static struct drm_framebuffer *
12790 intel_user_framebuffer_create(struct drm_device *dev,
12791 struct drm_file *filp,
12792 struct drm_mode_fb_cmd2 *mode_cmd)
12793 {
12794 struct drm_i915_gem_object *obj;
12795
12796 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12797 mode_cmd->handles[0]));
12798 if (&obj->base == NULL)
12799 return ERR_PTR(-ENOENT);
12800
12801 return intel_framebuffer_create(dev, mode_cmd, obj);
12802 }
12803
12804 #ifndef CONFIG_DRM_I915_FBDEV
12805 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12806 {
12807 }
12808 #endif
12809
12810 static const struct drm_mode_config_funcs intel_mode_funcs = {
12811 .fb_create = intel_user_framebuffer_create,
12812 .output_poll_changed = intel_fbdev_output_poll_changed,
12813 .atomic_check = intel_atomic_check,
12814 .atomic_commit = intel_atomic_commit,
12815 };
12816
12817 /* Set up chip specific display functions */
12818 static void intel_init_display(struct drm_device *dev)
12819 {
12820 struct drm_i915_private *dev_priv = dev->dev_private;
12821
12822 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12823 dev_priv->display.find_dpll = g4x_find_best_dpll;
12824 else if (IS_CHERRYVIEW(dev))
12825 dev_priv->display.find_dpll = chv_find_best_dpll;
12826 else if (IS_VALLEYVIEW(dev))
12827 dev_priv->display.find_dpll = vlv_find_best_dpll;
12828 else if (IS_PINEVIEW(dev))
12829 dev_priv->display.find_dpll = pnv_find_best_dpll;
12830 else
12831 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12832
12833 if (INTEL_INFO(dev)->gen >= 9) {
12834 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12835 dev_priv->display.get_initial_plane_config =
12836 skylake_get_initial_plane_config;
12837 dev_priv->display.crtc_compute_clock =
12838 haswell_crtc_compute_clock;
12839 dev_priv->display.crtc_enable = haswell_crtc_enable;
12840 dev_priv->display.crtc_disable = haswell_crtc_disable;
12841 dev_priv->display.off = ironlake_crtc_off;
12842 dev_priv->display.update_primary_plane =
12843 skylake_update_primary_plane;
12844 } else if (HAS_DDI(dev)) {
12845 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12846 dev_priv->display.get_initial_plane_config =
12847 ironlake_get_initial_plane_config;
12848 dev_priv->display.crtc_compute_clock =
12849 haswell_crtc_compute_clock;
12850 dev_priv->display.crtc_enable = haswell_crtc_enable;
12851 dev_priv->display.crtc_disable = haswell_crtc_disable;
12852 dev_priv->display.off = ironlake_crtc_off;
12853 dev_priv->display.update_primary_plane =
12854 ironlake_update_primary_plane;
12855 } else if (HAS_PCH_SPLIT(dev)) {
12856 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12857 dev_priv->display.get_initial_plane_config =
12858 ironlake_get_initial_plane_config;
12859 dev_priv->display.crtc_compute_clock =
12860 ironlake_crtc_compute_clock;
12861 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12862 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12863 dev_priv->display.off = ironlake_crtc_off;
12864 dev_priv->display.update_primary_plane =
12865 ironlake_update_primary_plane;
12866 } else if (IS_VALLEYVIEW(dev)) {
12867 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12868 dev_priv->display.get_initial_plane_config =
12869 i9xx_get_initial_plane_config;
12870 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12871 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12872 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12873 dev_priv->display.off = i9xx_crtc_off;
12874 dev_priv->display.update_primary_plane =
12875 i9xx_update_primary_plane;
12876 } else {
12877 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12878 dev_priv->display.get_initial_plane_config =
12879 i9xx_get_initial_plane_config;
12880 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12881 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12882 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12883 dev_priv->display.off = i9xx_crtc_off;
12884 dev_priv->display.update_primary_plane =
12885 i9xx_update_primary_plane;
12886 }
12887
12888 /* Returns the core display clock speed */
12889 if (IS_VALLEYVIEW(dev))
12890 dev_priv->display.get_display_clock_speed =
12891 valleyview_get_display_clock_speed;
12892 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12893 dev_priv->display.get_display_clock_speed =
12894 i945_get_display_clock_speed;
12895 else if (IS_I915G(dev))
12896 dev_priv->display.get_display_clock_speed =
12897 i915_get_display_clock_speed;
12898 else if (IS_I945GM(dev) || IS_845G(dev))
12899 dev_priv->display.get_display_clock_speed =
12900 i9xx_misc_get_display_clock_speed;
12901 else if (IS_PINEVIEW(dev))
12902 dev_priv->display.get_display_clock_speed =
12903 pnv_get_display_clock_speed;
12904 else if (IS_I915GM(dev))
12905 dev_priv->display.get_display_clock_speed =
12906 i915gm_get_display_clock_speed;
12907 else if (IS_I865G(dev))
12908 dev_priv->display.get_display_clock_speed =
12909 i865_get_display_clock_speed;
12910 else if (IS_I85X(dev))
12911 dev_priv->display.get_display_clock_speed =
12912 i855_get_display_clock_speed;
12913 else /* 852, 830 */
12914 dev_priv->display.get_display_clock_speed =
12915 i830_get_display_clock_speed;
12916
12917 if (IS_GEN5(dev)) {
12918 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12919 } else if (IS_GEN6(dev)) {
12920 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12921 } else if (IS_IVYBRIDGE(dev)) {
12922 /* FIXME: detect B0+ stepping and use auto training */
12923 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12924 dev_priv->display.modeset_global_resources =
12925 ivb_modeset_global_resources;
12926 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12927 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12928 } else if (IS_VALLEYVIEW(dev)) {
12929 dev_priv->display.modeset_global_resources =
12930 valleyview_modeset_global_resources;
12931 }
12932
12933 /* Default just returns -ENODEV to indicate unsupported */
12934 dev_priv->display.queue_flip = intel_default_queue_flip;
12935
12936 switch (INTEL_INFO(dev)->gen) {
12937 case 2:
12938 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12939 break;
12940
12941 case 3:
12942 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12943 break;
12944
12945 case 4:
12946 case 5:
12947 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12948 break;
12949
12950 case 6:
12951 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12952 break;
12953 case 7:
12954 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12955 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12956 break;
12957 case 9:
12958 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12959 break;
12960 }
12961
12962 intel_panel_init_backlight_funcs(dev);
12963
12964 mutex_init(&dev_priv->pps_mutex);
12965 }
12966
12967 /*
12968 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12969 * resume, or other times. This quirk makes sure that's the case for
12970 * affected systems.
12971 */
12972 static void quirk_pipea_force(struct drm_device *dev)
12973 {
12974 struct drm_i915_private *dev_priv = dev->dev_private;
12975
12976 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12977 DRM_INFO("applying pipe a force quirk\n");
12978 }
12979
12980 static void quirk_pipeb_force(struct drm_device *dev)
12981 {
12982 struct drm_i915_private *dev_priv = dev->dev_private;
12983
12984 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12985 DRM_INFO("applying pipe b force quirk\n");
12986 }
12987
12988 /*
12989 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12990 */
12991 static void quirk_ssc_force_disable(struct drm_device *dev)
12992 {
12993 struct drm_i915_private *dev_priv = dev->dev_private;
12994 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12995 DRM_INFO("applying lvds SSC disable quirk\n");
12996 }
12997
12998 /*
12999 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13000 * brightness value
13001 */
13002 static void quirk_invert_brightness(struct drm_device *dev)
13003 {
13004 struct drm_i915_private *dev_priv = dev->dev_private;
13005 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13006 DRM_INFO("applying inverted panel brightness quirk\n");
13007 }
13008
13009 /* Some VBT's incorrectly indicate no backlight is present */
13010 static void quirk_backlight_present(struct drm_device *dev)
13011 {
13012 struct drm_i915_private *dev_priv = dev->dev_private;
13013 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13014 DRM_INFO("applying backlight present quirk\n");
13015 }
13016
13017 struct intel_quirk {
13018 int device;
13019 int subsystem_vendor;
13020 int subsystem_device;
13021 void (*hook)(struct drm_device *dev);
13022 };
13023
13024 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13025 struct intel_dmi_quirk {
13026 void (*hook)(struct drm_device *dev);
13027 const struct dmi_system_id (*dmi_id_list)[];
13028 };
13029
13030 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13031 {
13032 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13033 return 1;
13034 }
13035
13036 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13037 {
13038 .dmi_id_list = &(const struct dmi_system_id[]) {
13039 {
13040 .callback = intel_dmi_reverse_brightness,
13041 .ident = "NCR Corporation",
13042 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13043 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13044 },
13045 },
13046 { } /* terminating entry */
13047 },
13048 .hook = quirk_invert_brightness,
13049 },
13050 };
13051
13052 static struct intel_quirk intel_quirks[] = {
13053 /* HP Mini needs pipe A force quirk (LP: #322104) */
13054 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13055
13056 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13057 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13058
13059 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13060 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13061
13062 /* 830 needs to leave pipe A & dpll A up */
13063 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13064
13065 /* 830 needs to leave pipe B & dpll B up */
13066 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13067
13068 /* Lenovo U160 cannot use SSC on LVDS */
13069 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13070
13071 /* Sony Vaio Y cannot use SSC on LVDS */
13072 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13073
13074 /* Acer Aspire 5734Z must invert backlight brightness */
13075 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13076
13077 /* Acer/eMachines G725 */
13078 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13079
13080 /* Acer/eMachines e725 */
13081 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13082
13083 /* Acer/Packard Bell NCL20 */
13084 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13085
13086 /* Acer Aspire 4736Z */
13087 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13088
13089 /* Acer Aspire 5336 */
13090 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13091
13092 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13093 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13094
13095 /* Acer C720 Chromebook (Core i3 4005U) */
13096 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13097
13098 /* Apple Macbook 2,1 (Core 2 T7400) */
13099 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13100
13101 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13102 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13103
13104 /* HP Chromebook 14 (Celeron 2955U) */
13105 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13106 };
13107
13108 static void intel_init_quirks(struct drm_device *dev)
13109 {
13110 struct pci_dev *d = dev->pdev;
13111 int i;
13112
13113 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13114 struct intel_quirk *q = &intel_quirks[i];
13115
13116 if (d->device == q->device &&
13117 (d->subsystem_vendor == q->subsystem_vendor ||
13118 q->subsystem_vendor == PCI_ANY_ID) &&
13119 (d->subsystem_device == q->subsystem_device ||
13120 q->subsystem_device == PCI_ANY_ID))
13121 q->hook(dev);
13122 }
13123 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13124 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13125 intel_dmi_quirks[i].hook(dev);
13126 }
13127 }
13128
13129 /* Disable the VGA plane that we never use */
13130 static void i915_disable_vga(struct drm_device *dev)
13131 {
13132 struct drm_i915_private *dev_priv = dev->dev_private;
13133 u8 sr1;
13134 u32 vga_reg = i915_vgacntrl_reg(dev);
13135
13136 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13137 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13138 outb(SR01, VGA_SR_INDEX);
13139 sr1 = inb(VGA_SR_DATA);
13140 outb(sr1 | 1<<5, VGA_SR_DATA);
13141 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13142 udelay(300);
13143
13144 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13145 POSTING_READ(vga_reg);
13146 }
13147
13148 void intel_modeset_init_hw(struct drm_device *dev)
13149 {
13150 intel_prepare_ddi(dev);
13151
13152 if (IS_VALLEYVIEW(dev))
13153 vlv_update_cdclk(dev);
13154
13155 intel_init_clock_gating(dev);
13156
13157 intel_enable_gt_powersave(dev);
13158 }
13159
13160 void intel_modeset_init(struct drm_device *dev)
13161 {
13162 struct drm_i915_private *dev_priv = dev->dev_private;
13163 int sprite, ret;
13164 enum pipe pipe;
13165 struct intel_crtc *crtc;
13166
13167 drm_mode_config_init(dev);
13168
13169 dev->mode_config.min_width = 0;
13170 dev->mode_config.min_height = 0;
13171
13172 dev->mode_config.preferred_depth = 24;
13173 dev->mode_config.prefer_shadow = 1;
13174
13175 dev->mode_config.funcs = &intel_mode_funcs;
13176
13177 intel_init_quirks(dev);
13178
13179 intel_init_pm(dev);
13180
13181 if (INTEL_INFO(dev)->num_pipes == 0)
13182 return;
13183
13184 intel_init_display(dev);
13185 intel_init_audio(dev);
13186
13187 if (IS_GEN2(dev)) {
13188 dev->mode_config.max_width = 2048;
13189 dev->mode_config.max_height = 2048;
13190 } else if (IS_GEN3(dev)) {
13191 dev->mode_config.max_width = 4096;
13192 dev->mode_config.max_height = 4096;
13193 } else {
13194 dev->mode_config.max_width = 8192;
13195 dev->mode_config.max_height = 8192;
13196 }
13197
13198 if (IS_845G(dev) || IS_I865G(dev)) {
13199 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13200 dev->mode_config.cursor_height = 1023;
13201 } else if (IS_GEN2(dev)) {
13202 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13203 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13204 } else {
13205 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13206 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13207 }
13208
13209 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13210
13211 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13212 INTEL_INFO(dev)->num_pipes,
13213 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13214
13215 for_each_pipe(dev_priv, pipe) {
13216 intel_crtc_init(dev, pipe);
13217 for_each_sprite(pipe, sprite) {
13218 ret = intel_plane_init(dev, pipe, sprite);
13219 if (ret)
13220 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13221 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13222 }
13223 }
13224
13225 intel_init_dpio(dev);
13226
13227 intel_shared_dpll_init(dev);
13228
13229 /* Just disable it once at startup */
13230 i915_disable_vga(dev);
13231 intel_setup_outputs(dev);
13232
13233 /* Just in case the BIOS is doing something questionable. */
13234 intel_fbc_disable(dev);
13235
13236 drm_modeset_lock_all(dev);
13237 intel_modeset_setup_hw_state(dev, false);
13238 drm_modeset_unlock_all(dev);
13239
13240 for_each_intel_crtc(dev, crtc) {
13241 if (!crtc->active)
13242 continue;
13243
13244 /*
13245 * Note that reserving the BIOS fb up front prevents us
13246 * from stuffing other stolen allocations like the ring
13247 * on top. This prevents some ugliness at boot time, and
13248 * can even allow for smooth boot transitions if the BIOS
13249 * fb is large enough for the active pipe configuration.
13250 */
13251 if (dev_priv->display.get_initial_plane_config) {
13252 dev_priv->display.get_initial_plane_config(crtc,
13253 &crtc->plane_config);
13254 /*
13255 * If the fb is shared between multiple heads, we'll
13256 * just get the first one.
13257 */
13258 intel_find_plane_obj(crtc, &crtc->plane_config);
13259 }
13260 }
13261 }
13262
13263 static void intel_enable_pipe_a(struct drm_device *dev)
13264 {
13265 struct intel_connector *connector;
13266 struct drm_connector *crt = NULL;
13267 struct intel_load_detect_pipe load_detect_temp;
13268 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13269
13270 /* We can't just switch on the pipe A, we need to set things up with a
13271 * proper mode and output configuration. As a gross hack, enable pipe A
13272 * by enabling the load detect pipe once. */
13273 list_for_each_entry(connector,
13274 &dev->mode_config.connector_list,
13275 base.head) {
13276 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13277 crt = &connector->base;
13278 break;
13279 }
13280 }
13281
13282 if (!crt)
13283 return;
13284
13285 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13286 intel_release_load_detect_pipe(crt, &load_detect_temp);
13287 }
13288
13289 static bool
13290 intel_check_plane_mapping(struct intel_crtc *crtc)
13291 {
13292 struct drm_device *dev = crtc->base.dev;
13293 struct drm_i915_private *dev_priv = dev->dev_private;
13294 u32 reg, val;
13295
13296 if (INTEL_INFO(dev)->num_pipes == 1)
13297 return true;
13298
13299 reg = DSPCNTR(!crtc->plane);
13300 val = I915_READ(reg);
13301
13302 if ((val & DISPLAY_PLANE_ENABLE) &&
13303 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13304 return false;
13305
13306 return true;
13307 }
13308
13309 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13310 {
13311 struct drm_device *dev = crtc->base.dev;
13312 struct drm_i915_private *dev_priv = dev->dev_private;
13313 u32 reg;
13314
13315 /* Clear any frame start delays used for debugging left by the BIOS */
13316 reg = PIPECONF(crtc->config->cpu_transcoder);
13317 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13318
13319 /* restore vblank interrupts to correct state */
13320 if (crtc->active) {
13321 update_scanline_offset(crtc);
13322 drm_vblank_on(dev, crtc->pipe);
13323 } else
13324 drm_vblank_off(dev, crtc->pipe);
13325
13326 /* We need to sanitize the plane -> pipe mapping first because this will
13327 * disable the crtc (and hence change the state) if it is wrong. Note
13328 * that gen4+ has a fixed plane -> pipe mapping. */
13329 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13330 struct intel_connector *connector;
13331 bool plane;
13332
13333 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13334 crtc->base.base.id);
13335
13336 /* Pipe has the wrong plane attached and the plane is active.
13337 * Temporarily change the plane mapping and disable everything
13338 * ... */
13339 plane = crtc->plane;
13340 crtc->plane = !plane;
13341 crtc->primary_enabled = true;
13342 dev_priv->display.crtc_disable(&crtc->base);
13343 crtc->plane = plane;
13344
13345 /* ... and break all links. */
13346 list_for_each_entry(connector, &dev->mode_config.connector_list,
13347 base.head) {
13348 if (connector->encoder->base.crtc != &crtc->base)
13349 continue;
13350
13351 connector->base.dpms = DRM_MODE_DPMS_OFF;
13352 connector->base.encoder = NULL;
13353 }
13354 /* multiple connectors may have the same encoder:
13355 * handle them and break crtc link separately */
13356 list_for_each_entry(connector, &dev->mode_config.connector_list,
13357 base.head)
13358 if (connector->encoder->base.crtc == &crtc->base) {
13359 connector->encoder->base.crtc = NULL;
13360 connector->encoder->connectors_active = false;
13361 }
13362
13363 WARN_ON(crtc->active);
13364 crtc->base.enabled = false;
13365 }
13366
13367 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13368 crtc->pipe == PIPE_A && !crtc->active) {
13369 /* BIOS forgot to enable pipe A, this mostly happens after
13370 * resume. Force-enable the pipe to fix this, the update_dpms
13371 * call below we restore the pipe to the right state, but leave
13372 * the required bits on. */
13373 intel_enable_pipe_a(dev);
13374 }
13375
13376 /* Adjust the state of the output pipe according to whether we
13377 * have active connectors/encoders. */
13378 intel_crtc_update_dpms(&crtc->base);
13379
13380 if (crtc->active != crtc->base.enabled) {
13381 struct intel_encoder *encoder;
13382
13383 /* This can happen either due to bugs in the get_hw_state
13384 * functions or because the pipe is force-enabled due to the
13385 * pipe A quirk. */
13386 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13387 crtc->base.base.id,
13388 crtc->base.enabled ? "enabled" : "disabled",
13389 crtc->active ? "enabled" : "disabled");
13390
13391 crtc->base.enabled = crtc->active;
13392
13393 /* Because we only establish the connector -> encoder ->
13394 * crtc links if something is active, this means the
13395 * crtc is now deactivated. Break the links. connector
13396 * -> encoder links are only establish when things are
13397 * actually up, hence no need to break them. */
13398 WARN_ON(crtc->active);
13399
13400 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13401 WARN_ON(encoder->connectors_active);
13402 encoder->base.crtc = NULL;
13403 }
13404 }
13405
13406 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13407 /*
13408 * We start out with underrun reporting disabled to avoid races.
13409 * For correct bookkeeping mark this on active crtcs.
13410 *
13411 * Also on gmch platforms we dont have any hardware bits to
13412 * disable the underrun reporting. Which means we need to start
13413 * out with underrun reporting disabled also on inactive pipes,
13414 * since otherwise we'll complain about the garbage we read when
13415 * e.g. coming up after runtime pm.
13416 *
13417 * No protection against concurrent access is required - at
13418 * worst a fifo underrun happens which also sets this to false.
13419 */
13420 crtc->cpu_fifo_underrun_disabled = true;
13421 crtc->pch_fifo_underrun_disabled = true;
13422 }
13423 }
13424
13425 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13426 {
13427 struct intel_connector *connector;
13428 struct drm_device *dev = encoder->base.dev;
13429
13430 /* We need to check both for a crtc link (meaning that the
13431 * encoder is active and trying to read from a pipe) and the
13432 * pipe itself being active. */
13433 bool has_active_crtc = encoder->base.crtc &&
13434 to_intel_crtc(encoder->base.crtc)->active;
13435
13436 if (encoder->connectors_active && !has_active_crtc) {
13437 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13438 encoder->base.base.id,
13439 encoder->base.name);
13440
13441 /* Connector is active, but has no active pipe. This is
13442 * fallout from our resume register restoring. Disable
13443 * the encoder manually again. */
13444 if (encoder->base.crtc) {
13445 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13446 encoder->base.base.id,
13447 encoder->base.name);
13448 encoder->disable(encoder);
13449 if (encoder->post_disable)
13450 encoder->post_disable(encoder);
13451 }
13452 encoder->base.crtc = NULL;
13453 encoder->connectors_active = false;
13454
13455 /* Inconsistent output/port/pipe state happens presumably due to
13456 * a bug in one of the get_hw_state functions. Or someplace else
13457 * in our code, like the register restore mess on resume. Clamp
13458 * things to off as a safer default. */
13459 list_for_each_entry(connector,
13460 &dev->mode_config.connector_list,
13461 base.head) {
13462 if (connector->encoder != encoder)
13463 continue;
13464 connector->base.dpms = DRM_MODE_DPMS_OFF;
13465 connector->base.encoder = NULL;
13466 }
13467 }
13468 /* Enabled encoders without active connectors will be fixed in
13469 * the crtc fixup. */
13470 }
13471
13472 void i915_redisable_vga_power_on(struct drm_device *dev)
13473 {
13474 struct drm_i915_private *dev_priv = dev->dev_private;
13475 u32 vga_reg = i915_vgacntrl_reg(dev);
13476
13477 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13478 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13479 i915_disable_vga(dev);
13480 }
13481 }
13482
13483 void i915_redisable_vga(struct drm_device *dev)
13484 {
13485 struct drm_i915_private *dev_priv = dev->dev_private;
13486
13487 /* This function can be called both from intel_modeset_setup_hw_state or
13488 * at a very early point in our resume sequence, where the power well
13489 * structures are not yet restored. Since this function is at a very
13490 * paranoid "someone might have enabled VGA while we were not looking"
13491 * level, just check if the power well is enabled instead of trying to
13492 * follow the "don't touch the power well if we don't need it" policy
13493 * the rest of the driver uses. */
13494 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13495 return;
13496
13497 i915_redisable_vga_power_on(dev);
13498 }
13499
13500 static bool primary_get_hw_state(struct intel_crtc *crtc)
13501 {
13502 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13503
13504 if (!crtc->active)
13505 return false;
13506
13507 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13508 }
13509
13510 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13511 {
13512 struct drm_i915_private *dev_priv = dev->dev_private;
13513 enum pipe pipe;
13514 struct intel_crtc *crtc;
13515 struct intel_encoder *encoder;
13516 struct intel_connector *connector;
13517 int i;
13518
13519 for_each_intel_crtc(dev, crtc) {
13520 memset(crtc->config, 0, sizeof(*crtc->config));
13521
13522 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13523
13524 crtc->active = dev_priv->display.get_pipe_config(crtc,
13525 crtc->config);
13526
13527 crtc->base.enabled = crtc->active;
13528 crtc->primary_enabled = primary_get_hw_state(crtc);
13529
13530 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13531 crtc->base.base.id,
13532 crtc->active ? "enabled" : "disabled");
13533 }
13534
13535 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13536 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13537
13538 pll->on = pll->get_hw_state(dev_priv, pll,
13539 &pll->config.hw_state);
13540 pll->active = 0;
13541 pll->config.crtc_mask = 0;
13542 for_each_intel_crtc(dev, crtc) {
13543 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13544 pll->active++;
13545 pll->config.crtc_mask |= 1 << crtc->pipe;
13546 }
13547 }
13548
13549 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13550 pll->name, pll->config.crtc_mask, pll->on);
13551
13552 if (pll->config.crtc_mask)
13553 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13554 }
13555
13556 for_each_intel_encoder(dev, encoder) {
13557 pipe = 0;
13558
13559 if (encoder->get_hw_state(encoder, &pipe)) {
13560 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13561 encoder->base.crtc = &crtc->base;
13562 encoder->get_config(encoder, crtc->config);
13563 } else {
13564 encoder->base.crtc = NULL;
13565 }
13566
13567 encoder->connectors_active = false;
13568 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13569 encoder->base.base.id,
13570 encoder->base.name,
13571 encoder->base.crtc ? "enabled" : "disabled",
13572 pipe_name(pipe));
13573 }
13574
13575 list_for_each_entry(connector, &dev->mode_config.connector_list,
13576 base.head) {
13577 if (connector->get_hw_state(connector)) {
13578 connector->base.dpms = DRM_MODE_DPMS_ON;
13579 connector->encoder->connectors_active = true;
13580 connector->base.encoder = &connector->encoder->base;
13581 } else {
13582 connector->base.dpms = DRM_MODE_DPMS_OFF;
13583 connector->base.encoder = NULL;
13584 }
13585 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13586 connector->base.base.id,
13587 connector->base.name,
13588 connector->base.encoder ? "enabled" : "disabled");
13589 }
13590 }
13591
13592 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13593 * and i915 state tracking structures. */
13594 void intel_modeset_setup_hw_state(struct drm_device *dev,
13595 bool force_restore)
13596 {
13597 struct drm_i915_private *dev_priv = dev->dev_private;
13598 enum pipe pipe;
13599 struct intel_crtc *crtc;
13600 struct intel_encoder *encoder;
13601 int i;
13602
13603 intel_modeset_readout_hw_state(dev);
13604
13605 /*
13606 * Now that we have the config, copy it to each CRTC struct
13607 * Note that this could go away if we move to using crtc_config
13608 * checking everywhere.
13609 */
13610 for_each_intel_crtc(dev, crtc) {
13611 if (crtc->active && i915.fastboot) {
13612 intel_mode_from_pipe_config(&crtc->base.mode,
13613 crtc->config);
13614 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13615 crtc->base.base.id);
13616 drm_mode_debug_printmodeline(&crtc->base.mode);
13617 }
13618 }
13619
13620 /* HW state is read out, now we need to sanitize this mess. */
13621 for_each_intel_encoder(dev, encoder) {
13622 intel_sanitize_encoder(encoder);
13623 }
13624
13625 for_each_pipe(dev_priv, pipe) {
13626 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13627 intel_sanitize_crtc(crtc);
13628 intel_dump_pipe_config(crtc, crtc->config,
13629 "[setup_hw_state]");
13630 }
13631
13632 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13633 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13634
13635 if (!pll->on || pll->active)
13636 continue;
13637
13638 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13639
13640 pll->disable(dev_priv, pll);
13641 pll->on = false;
13642 }
13643
13644 if (IS_GEN9(dev))
13645 skl_wm_get_hw_state(dev);
13646 else if (HAS_PCH_SPLIT(dev))
13647 ilk_wm_get_hw_state(dev);
13648
13649 if (force_restore) {
13650 i915_redisable_vga(dev);
13651
13652 /*
13653 * We need to use raw interfaces for restoring state to avoid
13654 * checking (bogus) intermediate states.
13655 */
13656 for_each_pipe(dev_priv, pipe) {
13657 struct drm_crtc *crtc =
13658 dev_priv->pipe_to_crtc_mapping[pipe];
13659
13660 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13661 crtc->primary->fb);
13662 }
13663 } else {
13664 intel_modeset_update_staged_output_state(dev);
13665 }
13666
13667 intel_modeset_check_state(dev);
13668 }
13669
13670 void intel_modeset_gem_init(struct drm_device *dev)
13671 {
13672 struct drm_i915_private *dev_priv = dev->dev_private;
13673 struct drm_crtc *c;
13674 struct drm_i915_gem_object *obj;
13675
13676 mutex_lock(&dev->struct_mutex);
13677 intel_init_gt_powersave(dev);
13678 mutex_unlock(&dev->struct_mutex);
13679
13680 /*
13681 * There may be no VBT; and if the BIOS enabled SSC we can
13682 * just keep using it to avoid unnecessary flicker. Whereas if the
13683 * BIOS isn't using it, don't assume it will work even if the VBT
13684 * indicates as much.
13685 */
13686 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13687 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13688 DREF_SSC1_ENABLE);
13689
13690 intel_modeset_init_hw(dev);
13691
13692 intel_setup_overlay(dev);
13693
13694 /*
13695 * Make sure any fbs we allocated at startup are properly
13696 * pinned & fenced. When we do the allocation it's too early
13697 * for this.
13698 */
13699 mutex_lock(&dev->struct_mutex);
13700 for_each_crtc(dev, c) {
13701 obj = intel_fb_obj(c->primary->fb);
13702 if (obj == NULL)
13703 continue;
13704
13705 if (intel_pin_and_fence_fb_obj(c->primary,
13706 c->primary->fb,
13707 NULL)) {
13708 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13709 to_intel_crtc(c)->pipe);
13710 drm_framebuffer_unreference(c->primary->fb);
13711 c->primary->fb = NULL;
13712 }
13713 }
13714 mutex_unlock(&dev->struct_mutex);
13715
13716 intel_backlight_register(dev);
13717 }
13718
13719 void intel_connector_unregister(struct intel_connector *intel_connector)
13720 {
13721 struct drm_connector *connector = &intel_connector->base;
13722
13723 intel_panel_destroy_backlight(connector);
13724 drm_connector_unregister(connector);
13725 }
13726
13727 void intel_modeset_cleanup(struct drm_device *dev)
13728 {
13729 struct drm_i915_private *dev_priv = dev->dev_private;
13730 struct drm_connector *connector;
13731
13732 intel_disable_gt_powersave(dev);
13733
13734 intel_backlight_unregister(dev);
13735
13736 /*
13737 * Interrupts and polling as the first thing to avoid creating havoc.
13738 * Too much stuff here (turning of connectors, ...) would
13739 * experience fancy races otherwise.
13740 */
13741 intel_irq_uninstall(dev_priv);
13742
13743 /*
13744 * Due to the hpd irq storm handling the hotplug work can re-arm the
13745 * poll handlers. Hence disable polling after hpd handling is shut down.
13746 */
13747 drm_kms_helper_poll_fini(dev);
13748
13749 mutex_lock(&dev->struct_mutex);
13750
13751 intel_unregister_dsm_handler();
13752
13753 intel_fbc_disable(dev);
13754
13755 ironlake_teardown_rc6(dev);
13756
13757 mutex_unlock(&dev->struct_mutex);
13758
13759 /* flush any delayed tasks or pending work */
13760 flush_scheduled_work();
13761
13762 /* destroy the backlight and sysfs files before encoders/connectors */
13763 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13764 struct intel_connector *intel_connector;
13765
13766 intel_connector = to_intel_connector(connector);
13767 intel_connector->unregister(intel_connector);
13768 }
13769
13770 drm_mode_config_cleanup(dev);
13771
13772 intel_cleanup_overlay(dev);
13773
13774 mutex_lock(&dev->struct_mutex);
13775 intel_cleanup_gt_powersave(dev);
13776 mutex_unlock(&dev->struct_mutex);
13777 }
13778
13779 /*
13780 * Return which encoder is currently attached for connector.
13781 */
13782 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13783 {
13784 return &intel_attached_encoder(connector)->base;
13785 }
13786
13787 void intel_connector_attach_encoder(struct intel_connector *connector,
13788 struct intel_encoder *encoder)
13789 {
13790 connector->encoder = encoder;
13791 drm_mode_connector_attach_encoder(&connector->base,
13792 &encoder->base);
13793 }
13794
13795 /*
13796 * set vga decode state - true == enable VGA decode
13797 */
13798 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13799 {
13800 struct drm_i915_private *dev_priv = dev->dev_private;
13801 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13802 u16 gmch_ctrl;
13803
13804 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13805 DRM_ERROR("failed to read control word\n");
13806 return -EIO;
13807 }
13808
13809 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13810 return 0;
13811
13812 if (state)
13813 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13814 else
13815 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13816
13817 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13818 DRM_ERROR("failed to write control word\n");
13819 return -EIO;
13820 }
13821
13822 return 0;
13823 }
13824
13825 struct intel_display_error_state {
13826
13827 u32 power_well_driver;
13828
13829 int num_transcoders;
13830
13831 struct intel_cursor_error_state {
13832 u32 control;
13833 u32 position;
13834 u32 base;
13835 u32 size;
13836 } cursor[I915_MAX_PIPES];
13837
13838 struct intel_pipe_error_state {
13839 bool power_domain_on;
13840 u32 source;
13841 u32 stat;
13842 } pipe[I915_MAX_PIPES];
13843
13844 struct intel_plane_error_state {
13845 u32 control;
13846 u32 stride;
13847 u32 size;
13848 u32 pos;
13849 u32 addr;
13850 u32 surface;
13851 u32 tile_offset;
13852 } plane[I915_MAX_PIPES];
13853
13854 struct intel_transcoder_error_state {
13855 bool power_domain_on;
13856 enum transcoder cpu_transcoder;
13857
13858 u32 conf;
13859
13860 u32 htotal;
13861 u32 hblank;
13862 u32 hsync;
13863 u32 vtotal;
13864 u32 vblank;
13865 u32 vsync;
13866 } transcoder[4];
13867 };
13868
13869 struct intel_display_error_state *
13870 intel_display_capture_error_state(struct drm_device *dev)
13871 {
13872 struct drm_i915_private *dev_priv = dev->dev_private;
13873 struct intel_display_error_state *error;
13874 int transcoders[] = {
13875 TRANSCODER_A,
13876 TRANSCODER_B,
13877 TRANSCODER_C,
13878 TRANSCODER_EDP,
13879 };
13880 int i;
13881
13882 if (INTEL_INFO(dev)->num_pipes == 0)
13883 return NULL;
13884
13885 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13886 if (error == NULL)
13887 return NULL;
13888
13889 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13890 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13891
13892 for_each_pipe(dev_priv, i) {
13893 error->pipe[i].power_domain_on =
13894 __intel_display_power_is_enabled(dev_priv,
13895 POWER_DOMAIN_PIPE(i));
13896 if (!error->pipe[i].power_domain_on)
13897 continue;
13898
13899 error->cursor[i].control = I915_READ(CURCNTR(i));
13900 error->cursor[i].position = I915_READ(CURPOS(i));
13901 error->cursor[i].base = I915_READ(CURBASE(i));
13902
13903 error->plane[i].control = I915_READ(DSPCNTR(i));
13904 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13905 if (INTEL_INFO(dev)->gen <= 3) {
13906 error->plane[i].size = I915_READ(DSPSIZE(i));
13907 error->plane[i].pos = I915_READ(DSPPOS(i));
13908 }
13909 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13910 error->plane[i].addr = I915_READ(DSPADDR(i));
13911 if (INTEL_INFO(dev)->gen >= 4) {
13912 error->plane[i].surface = I915_READ(DSPSURF(i));
13913 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13914 }
13915
13916 error->pipe[i].source = I915_READ(PIPESRC(i));
13917
13918 if (HAS_GMCH_DISPLAY(dev))
13919 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13920 }
13921
13922 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13923 if (HAS_DDI(dev_priv->dev))
13924 error->num_transcoders++; /* Account for eDP. */
13925
13926 for (i = 0; i < error->num_transcoders; i++) {
13927 enum transcoder cpu_transcoder = transcoders[i];
13928
13929 error->transcoder[i].power_domain_on =
13930 __intel_display_power_is_enabled(dev_priv,
13931 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13932 if (!error->transcoder[i].power_domain_on)
13933 continue;
13934
13935 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13936
13937 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13938 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13939 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13940 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13941 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13942 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13943 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13944 }
13945
13946 return error;
13947 }
13948
13949 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13950
13951 void
13952 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13953 struct drm_device *dev,
13954 struct intel_display_error_state *error)
13955 {
13956 struct drm_i915_private *dev_priv = dev->dev_private;
13957 int i;
13958
13959 if (!error)
13960 return;
13961
13962 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13963 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13964 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13965 error->power_well_driver);
13966 for_each_pipe(dev_priv, i) {
13967 err_printf(m, "Pipe [%d]:\n", i);
13968 err_printf(m, " Power: %s\n",
13969 error->pipe[i].power_domain_on ? "on" : "off");
13970 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13971 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13972
13973 err_printf(m, "Plane [%d]:\n", i);
13974 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13975 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13976 if (INTEL_INFO(dev)->gen <= 3) {
13977 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13978 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13979 }
13980 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13981 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13982 if (INTEL_INFO(dev)->gen >= 4) {
13983 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13984 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13985 }
13986
13987 err_printf(m, "Cursor [%d]:\n", i);
13988 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13989 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13990 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13991 }
13992
13993 for (i = 0; i < error->num_transcoders; i++) {
13994 err_printf(m, "CPU transcoder: %c\n",
13995 transcoder_name(error->transcoder[i].cpu_transcoder));
13996 err_printf(m, " Power: %s\n",
13997 error->transcoder[i].power_domain_on ? "on" : "off");
13998 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13999 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14000 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14001 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14002 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14003 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14004 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14005 }
14006 }
14007
14008 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14009 {
14010 struct intel_crtc *crtc;
14011
14012 for_each_intel_crtc(dev, crtc) {
14013 struct intel_unpin_work *work;
14014
14015 spin_lock_irq(&dev->event_lock);
14016
14017 work = crtc->unpin_work;
14018
14019 if (work && work->event &&
14020 work->event->base.file_priv == file) {
14021 kfree(work->event);
14022 work->event = NULL;
14023 }
14024
14025 spin_unlock_irq(&dev->event_lock);
14026 }
14027 }
Linux kernel - Deliverables
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