2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats
[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats
[] = {
62 DRM_FORMAT_XRGB2101010
,
63 DRM_FORMAT_XBGR2101010
,
66 static const uint32_t skl_primary_formats
[] = {
73 DRM_FORMAT_XRGB2101010
,
74 DRM_FORMAT_XBGR2101010
,
82 static const uint32_t intel_cursor_formats
[] = {
86 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
88 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
89 struct intel_crtc_state
*pipe_config
);
90 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
91 struct intel_crtc_state
*pipe_config
);
93 static int intel_framebuffer_init(struct drm_device
*dev
,
94 struct intel_framebuffer
*ifb
,
95 struct drm_mode_fb_cmd2
*mode_cmd
,
96 struct drm_i915_gem_object
*obj
);
97 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
98 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
100 struct intel_link_m_n
*m_n
,
101 struct intel_link_m_n
*m2_n2
);
102 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
103 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
104 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
105 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
106 const struct intel_crtc_state
*pipe_config
);
107 static void chv_prepare_pll(struct intel_crtc
*crtc
,
108 const struct intel_crtc_state
*pipe_config
);
109 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
110 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
111 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
112 struct intel_crtc_state
*crtc_state
);
113 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
115 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
123 int p2_slow
, p2_fast
;
126 typedef struct intel_limit intel_limit_t
;
128 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
133 intel_pch_rawclk(struct drm_device
*dev
)
135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
137 WARN_ON(!HAS_PCH_SPLIT(dev
));
139 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
142 /* hrawclock is 1/4 the FSB frequency */
143 int intel_hrawclk(struct drm_device
*dev
)
145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
148 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
149 if (IS_VALLEYVIEW(dev
))
152 clkcfg
= I915_READ(CLKCFG
);
153 switch (clkcfg
& CLKCFG_FSB_MASK
) {
162 case CLKCFG_FSB_1067
:
164 case CLKCFG_FSB_1333
:
166 /* these two are just a guess; one of them might be right */
167 case CLKCFG_FSB_1600
:
168 case CLKCFG_FSB_1600_ALT
:
175 static inline u32
/* units of 100MHz */
176 intel_fdi_link_freq(struct drm_device
*dev
)
179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
180 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
185 static const intel_limit_t intel_limits_i8xx_dac
= {
186 .dot
= { .min
= 25000, .max
= 350000 },
187 .vco
= { .min
= 908000, .max
= 1512000 },
188 .n
= { .min
= 2, .max
= 16 },
189 .m
= { .min
= 96, .max
= 140 },
190 .m1
= { .min
= 18, .max
= 26 },
191 .m2
= { .min
= 6, .max
= 16 },
192 .p
= { .min
= 4, .max
= 128 },
193 .p1
= { .min
= 2, .max
= 33 },
194 .p2
= { .dot_limit
= 165000,
195 .p2_slow
= 4, .p2_fast
= 2 },
198 static const intel_limit_t intel_limits_i8xx_dvo
= {
199 .dot
= { .min
= 25000, .max
= 350000 },
200 .vco
= { .min
= 908000, .max
= 1512000 },
201 .n
= { .min
= 2, .max
= 16 },
202 .m
= { .min
= 96, .max
= 140 },
203 .m1
= { .min
= 18, .max
= 26 },
204 .m2
= { .min
= 6, .max
= 16 },
205 .p
= { .min
= 4, .max
= 128 },
206 .p1
= { .min
= 2, .max
= 33 },
207 .p2
= { .dot_limit
= 165000,
208 .p2_slow
= 4, .p2_fast
= 4 },
211 static const intel_limit_t intel_limits_i8xx_lvds
= {
212 .dot
= { .min
= 25000, .max
= 350000 },
213 .vco
= { .min
= 908000, .max
= 1512000 },
214 .n
= { .min
= 2, .max
= 16 },
215 .m
= { .min
= 96, .max
= 140 },
216 .m1
= { .min
= 18, .max
= 26 },
217 .m2
= { .min
= 6, .max
= 16 },
218 .p
= { .min
= 4, .max
= 128 },
219 .p1
= { .min
= 1, .max
= 6 },
220 .p2
= { .dot_limit
= 165000,
221 .p2_slow
= 14, .p2_fast
= 7 },
224 static const intel_limit_t intel_limits_i9xx_sdvo
= {
225 .dot
= { .min
= 20000, .max
= 400000 },
226 .vco
= { .min
= 1400000, .max
= 2800000 },
227 .n
= { .min
= 1, .max
= 6 },
228 .m
= { .min
= 70, .max
= 120 },
229 .m1
= { .min
= 8, .max
= 18 },
230 .m2
= { .min
= 3, .max
= 7 },
231 .p
= { .min
= 5, .max
= 80 },
232 .p1
= { .min
= 1, .max
= 8 },
233 .p2
= { .dot_limit
= 200000,
234 .p2_slow
= 10, .p2_fast
= 5 },
237 static const intel_limit_t intel_limits_i9xx_lvds
= {
238 .dot
= { .min
= 20000, .max
= 400000 },
239 .vco
= { .min
= 1400000, .max
= 2800000 },
240 .n
= { .min
= 1, .max
= 6 },
241 .m
= { .min
= 70, .max
= 120 },
242 .m1
= { .min
= 8, .max
= 18 },
243 .m2
= { .min
= 3, .max
= 7 },
244 .p
= { .min
= 7, .max
= 98 },
245 .p1
= { .min
= 1, .max
= 8 },
246 .p2
= { .dot_limit
= 112000,
247 .p2_slow
= 14, .p2_fast
= 7 },
251 static const intel_limit_t intel_limits_g4x_sdvo
= {
252 .dot
= { .min
= 25000, .max
= 270000 },
253 .vco
= { .min
= 1750000, .max
= 3500000},
254 .n
= { .min
= 1, .max
= 4 },
255 .m
= { .min
= 104, .max
= 138 },
256 .m1
= { .min
= 17, .max
= 23 },
257 .m2
= { .min
= 5, .max
= 11 },
258 .p
= { .min
= 10, .max
= 30 },
259 .p1
= { .min
= 1, .max
= 3},
260 .p2
= { .dot_limit
= 270000,
266 static const intel_limit_t intel_limits_g4x_hdmi
= {
267 .dot
= { .min
= 22000, .max
= 400000 },
268 .vco
= { .min
= 1750000, .max
= 3500000},
269 .n
= { .min
= 1, .max
= 4 },
270 .m
= { .min
= 104, .max
= 138 },
271 .m1
= { .min
= 16, .max
= 23 },
272 .m2
= { .min
= 5, .max
= 11 },
273 .p
= { .min
= 5, .max
= 80 },
274 .p1
= { .min
= 1, .max
= 8},
275 .p2
= { .dot_limit
= 165000,
276 .p2_slow
= 10, .p2_fast
= 5 },
279 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
280 .dot
= { .min
= 20000, .max
= 115000 },
281 .vco
= { .min
= 1750000, .max
= 3500000 },
282 .n
= { .min
= 1, .max
= 3 },
283 .m
= { .min
= 104, .max
= 138 },
284 .m1
= { .min
= 17, .max
= 23 },
285 .m2
= { .min
= 5, .max
= 11 },
286 .p
= { .min
= 28, .max
= 112 },
287 .p1
= { .min
= 2, .max
= 8 },
288 .p2
= { .dot_limit
= 0,
289 .p2_slow
= 14, .p2_fast
= 14
293 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
294 .dot
= { .min
= 80000, .max
= 224000 },
295 .vco
= { .min
= 1750000, .max
= 3500000 },
296 .n
= { .min
= 1, .max
= 3 },
297 .m
= { .min
= 104, .max
= 138 },
298 .m1
= { .min
= 17, .max
= 23 },
299 .m2
= { .min
= 5, .max
= 11 },
300 .p
= { .min
= 14, .max
= 42 },
301 .p1
= { .min
= 2, .max
= 6 },
302 .p2
= { .dot_limit
= 0,
303 .p2_slow
= 7, .p2_fast
= 7
307 static const intel_limit_t intel_limits_pineview_sdvo
= {
308 .dot
= { .min
= 20000, .max
= 400000},
309 .vco
= { .min
= 1700000, .max
= 3500000 },
310 /* Pineview's Ncounter is a ring counter */
311 .n
= { .min
= 3, .max
= 6 },
312 .m
= { .min
= 2, .max
= 256 },
313 /* Pineview only has one combined m divider, which we treat as m2. */
314 .m1
= { .min
= 0, .max
= 0 },
315 .m2
= { .min
= 0, .max
= 254 },
316 .p
= { .min
= 5, .max
= 80 },
317 .p1
= { .min
= 1, .max
= 8 },
318 .p2
= { .dot_limit
= 200000,
319 .p2_slow
= 10, .p2_fast
= 5 },
322 static const intel_limit_t intel_limits_pineview_lvds
= {
323 .dot
= { .min
= 20000, .max
= 400000 },
324 .vco
= { .min
= 1700000, .max
= 3500000 },
325 .n
= { .min
= 3, .max
= 6 },
326 .m
= { .min
= 2, .max
= 256 },
327 .m1
= { .min
= 0, .max
= 0 },
328 .m2
= { .min
= 0, .max
= 254 },
329 .p
= { .min
= 7, .max
= 112 },
330 .p1
= { .min
= 1, .max
= 8 },
331 .p2
= { .dot_limit
= 112000,
332 .p2_slow
= 14, .p2_fast
= 14 },
335 /* Ironlake / Sandybridge
337 * We calculate clock using (register_value + 2) for N/M1/M2, so here
338 * the range value for them is (actual_value - 2).
340 static const intel_limit_t intel_limits_ironlake_dac
= {
341 .dot
= { .min
= 25000, .max
= 350000 },
342 .vco
= { .min
= 1760000, .max
= 3510000 },
343 .n
= { .min
= 1, .max
= 5 },
344 .m
= { .min
= 79, .max
= 127 },
345 .m1
= { .min
= 12, .max
= 22 },
346 .m2
= { .min
= 5, .max
= 9 },
347 .p
= { .min
= 5, .max
= 80 },
348 .p1
= { .min
= 1, .max
= 8 },
349 .p2
= { .dot_limit
= 225000,
350 .p2_slow
= 10, .p2_fast
= 5 },
353 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000 },
356 .n
= { .min
= 1, .max
= 3 },
357 .m
= { .min
= 79, .max
= 118 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 28, .max
= 112 },
361 .p1
= { .min
= 2, .max
= 8 },
362 .p2
= { .dot_limit
= 225000,
363 .p2_slow
= 14, .p2_fast
= 14 },
366 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
367 .dot
= { .min
= 25000, .max
= 350000 },
368 .vco
= { .min
= 1760000, .max
= 3510000 },
369 .n
= { .min
= 1, .max
= 3 },
370 .m
= { .min
= 79, .max
= 127 },
371 .m1
= { .min
= 12, .max
= 22 },
372 .m2
= { .min
= 5, .max
= 9 },
373 .p
= { .min
= 14, .max
= 56 },
374 .p1
= { .min
= 2, .max
= 8 },
375 .p2
= { .dot_limit
= 225000,
376 .p2_slow
= 7, .p2_fast
= 7 },
379 /* LVDS 100mhz refclk limits. */
380 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
381 .dot
= { .min
= 25000, .max
= 350000 },
382 .vco
= { .min
= 1760000, .max
= 3510000 },
383 .n
= { .min
= 1, .max
= 2 },
384 .m
= { .min
= 79, .max
= 126 },
385 .m1
= { .min
= 12, .max
= 22 },
386 .m2
= { .min
= 5, .max
= 9 },
387 .p
= { .min
= 28, .max
= 112 },
388 .p1
= { .min
= 2, .max
= 8 },
389 .p2
= { .dot_limit
= 225000,
390 .p2_slow
= 14, .p2_fast
= 14 },
393 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
394 .dot
= { .min
= 25000, .max
= 350000 },
395 .vco
= { .min
= 1760000, .max
= 3510000 },
396 .n
= { .min
= 1, .max
= 3 },
397 .m
= { .min
= 79, .max
= 126 },
398 .m1
= { .min
= 12, .max
= 22 },
399 .m2
= { .min
= 5, .max
= 9 },
400 .p
= { .min
= 14, .max
= 42 },
401 .p1
= { .min
= 2, .max
= 6 },
402 .p2
= { .dot_limit
= 225000,
403 .p2_slow
= 7, .p2_fast
= 7 },
406 static const intel_limit_t intel_limits_vlv
= {
408 * These are the data rate limits (measured in fast clocks)
409 * since those are the strictest limits we have. The fast
410 * clock and actual rate limits are more relaxed, so checking
411 * them would make no difference.
413 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
414 .vco
= { .min
= 4000000, .max
= 6000000 },
415 .n
= { .min
= 1, .max
= 7 },
416 .m1
= { .min
= 2, .max
= 3 },
417 .m2
= { .min
= 11, .max
= 156 },
418 .p1
= { .min
= 2, .max
= 3 },
419 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
422 static const intel_limit_t intel_limits_chv
= {
424 * These are the data rate limits (measured in fast clocks)
425 * since those are the strictest limits we have. The fast
426 * clock and actual rate limits are more relaxed, so checking
427 * them would make no difference.
429 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
430 .vco
= { .min
= 4800000, .max
= 6480000 },
431 .n
= { .min
= 1, .max
= 1 },
432 .m1
= { .min
= 2, .max
= 2 },
433 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
434 .p1
= { .min
= 2, .max
= 4 },
435 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
438 static const intel_limit_t intel_limits_bxt
= {
439 /* FIXME: find real dot limits */
440 .dot
= { .min
= 0, .max
= INT_MAX
},
441 .vco
= { .min
= 4800000, .max
= 6700000 },
442 .n
= { .min
= 1, .max
= 1 },
443 .m1
= { .min
= 2, .max
= 2 },
444 /* FIXME: find real m2 limits */
445 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
446 .p1
= { .min
= 2, .max
= 4 },
447 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
451 needs_modeset(struct drm_crtc_state
*state
)
453 return drm_atomic_crtc_needs_modeset(state
);
457 * Returns whether any output on the specified pipe is of the specified type
459 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
461 struct drm_device
*dev
= crtc
->base
.dev
;
462 struct intel_encoder
*encoder
;
464 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
465 if (encoder
->type
== type
)
472 * Returns whether any output on the specified pipe will have the specified
473 * type after a staged modeset is complete, i.e., the same as
474 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
477 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
480 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
481 struct drm_connector
*connector
;
482 struct drm_connector_state
*connector_state
;
483 struct intel_encoder
*encoder
;
484 int i
, num_connectors
= 0;
486 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
487 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
492 encoder
= to_intel_encoder(connector_state
->best_encoder
);
493 if (encoder
->type
== type
)
497 WARN_ON(num_connectors
== 0);
502 static const intel_limit_t
*
503 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
505 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
506 const intel_limit_t
*limit
;
508 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
509 if (intel_is_dual_link_lvds(dev
)) {
510 if (refclk
== 100000)
511 limit
= &intel_limits_ironlake_dual_lvds_100m
;
513 limit
= &intel_limits_ironlake_dual_lvds
;
515 if (refclk
== 100000)
516 limit
= &intel_limits_ironlake_single_lvds_100m
;
518 limit
= &intel_limits_ironlake_single_lvds
;
521 limit
= &intel_limits_ironlake_dac
;
526 static const intel_limit_t
*
527 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
529 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
530 const intel_limit_t
*limit
;
532 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
533 if (intel_is_dual_link_lvds(dev
))
534 limit
= &intel_limits_g4x_dual_channel_lvds
;
536 limit
= &intel_limits_g4x_single_channel_lvds
;
537 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
538 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
539 limit
= &intel_limits_g4x_hdmi
;
540 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
541 limit
= &intel_limits_g4x_sdvo
;
542 } else /* The option is for other outputs */
543 limit
= &intel_limits_i9xx_sdvo
;
548 static const intel_limit_t
*
549 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
551 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
552 const intel_limit_t
*limit
;
555 limit
= &intel_limits_bxt
;
556 else if (HAS_PCH_SPLIT(dev
))
557 limit
= intel_ironlake_limit(crtc_state
, refclk
);
558 else if (IS_G4X(dev
)) {
559 limit
= intel_g4x_limit(crtc_state
);
560 } else if (IS_PINEVIEW(dev
)) {
561 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
562 limit
= &intel_limits_pineview_lvds
;
564 limit
= &intel_limits_pineview_sdvo
;
565 } else if (IS_CHERRYVIEW(dev
)) {
566 limit
= &intel_limits_chv
;
567 } else if (IS_VALLEYVIEW(dev
)) {
568 limit
= &intel_limits_vlv
;
569 } else if (!IS_GEN2(dev
)) {
570 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
571 limit
= &intel_limits_i9xx_lvds
;
573 limit
= &intel_limits_i9xx_sdvo
;
575 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
576 limit
= &intel_limits_i8xx_lvds
;
577 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
578 limit
= &intel_limits_i8xx_dvo
;
580 limit
= &intel_limits_i8xx_dac
;
586 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
587 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
588 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
589 * The helpers' return value is the rate of the clock that is fed to the
590 * display engine's pipe which can be the above fast dot clock rate or a
591 * divided-down version of it.
593 /* m1 is reserved as 0 in Pineview, n is a ring counter */
594 static int pnv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
596 clock
->m
= clock
->m2
+ 2;
597 clock
->p
= clock
->p1
* clock
->p2
;
598 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
600 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
601 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
606 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
608 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
611 static int i9xx_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
613 clock
->m
= i9xx_dpll_compute_m(clock
);
614 clock
->p
= clock
->p1
* clock
->p2
;
615 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
617 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
618 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
623 static int vlv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
625 clock
->m
= clock
->m1
* clock
->m2
;
626 clock
->p
= clock
->p1
* clock
->p2
;
627 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
629 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
630 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
632 return clock
->dot
/ 5;
635 int chv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
637 clock
->m
= clock
->m1
* clock
->m2
;
638 clock
->p
= clock
->p1
* clock
->p2
;
639 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
641 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
643 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
645 return clock
->dot
/ 5;
648 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
650 * Returns whether the given set of divisors are valid for a given refclk with
651 * the given connectors.
654 static bool intel_PLL_is_valid(struct drm_device
*dev
,
655 const intel_limit_t
*limit
,
656 const intel_clock_t
*clock
)
658 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
659 INTELPllInvalid("n out of range\n");
660 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
661 INTELPllInvalid("p1 out of range\n");
662 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
663 INTELPllInvalid("m2 out of range\n");
664 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
665 INTELPllInvalid("m1 out of range\n");
667 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
668 if (clock
->m1
<= clock
->m2
)
669 INTELPllInvalid("m1 <= m2\n");
671 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
672 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
673 INTELPllInvalid("p out of range\n");
674 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
675 INTELPllInvalid("m out of range\n");
678 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
679 INTELPllInvalid("vco out of range\n");
680 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
681 * connector, etc., rather than just a single range.
683 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
684 INTELPllInvalid("dot out of range\n");
690 i9xx_select_p2_div(const intel_limit_t
*limit
,
691 const struct intel_crtc_state
*crtc_state
,
694 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
696 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
698 * For LVDS just rely on its current settings for dual-channel.
699 * We haven't figured out how to reliably set up different
700 * single/dual channel state, if we even can.
702 if (intel_is_dual_link_lvds(dev
))
703 return limit
->p2
.p2_fast
;
705 return limit
->p2
.p2_slow
;
707 if (target
< limit
->p2
.dot_limit
)
708 return limit
->p2
.p2_slow
;
710 return limit
->p2
.p2_fast
;
715 i9xx_find_best_dpll(const intel_limit_t
*limit
,
716 struct intel_crtc_state
*crtc_state
,
717 int target
, int refclk
, intel_clock_t
*match_clock
,
718 intel_clock_t
*best_clock
)
720 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
724 memset(best_clock
, 0, sizeof(*best_clock
));
726 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
728 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
730 for (clock
.m2
= limit
->m2
.min
;
731 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
732 if (clock
.m2
>= clock
.m1
)
734 for (clock
.n
= limit
->n
.min
;
735 clock
.n
<= limit
->n
.max
; clock
.n
++) {
736 for (clock
.p1
= limit
->p1
.min
;
737 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
740 i9xx_calc_dpll_params(refclk
, &clock
);
741 if (!intel_PLL_is_valid(dev
, limit
,
745 clock
.p
!= match_clock
->p
)
748 this_err
= abs(clock
.dot
- target
);
749 if (this_err
< err
) {
758 return (err
!= target
);
762 pnv_find_best_dpll(const intel_limit_t
*limit
,
763 struct intel_crtc_state
*crtc_state
,
764 int target
, int refclk
, intel_clock_t
*match_clock
,
765 intel_clock_t
*best_clock
)
767 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
771 memset(best_clock
, 0, sizeof(*best_clock
));
773 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
775 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
777 for (clock
.m2
= limit
->m2
.min
;
778 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
779 for (clock
.n
= limit
->n
.min
;
780 clock
.n
<= limit
->n
.max
; clock
.n
++) {
781 for (clock
.p1
= limit
->p1
.min
;
782 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
785 pnv_calc_dpll_params(refclk
, &clock
);
786 if (!intel_PLL_is_valid(dev
, limit
,
790 clock
.p
!= match_clock
->p
)
793 this_err
= abs(clock
.dot
- target
);
794 if (this_err
< err
) {
803 return (err
!= target
);
807 g4x_find_best_dpll(const intel_limit_t
*limit
,
808 struct intel_crtc_state
*crtc_state
,
809 int target
, int refclk
, intel_clock_t
*match_clock
,
810 intel_clock_t
*best_clock
)
812 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
816 /* approximately equals target * 0.00585 */
817 int err_most
= (target
>> 8) + (target
>> 9);
819 memset(best_clock
, 0, sizeof(*best_clock
));
821 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
823 max_n
= limit
->n
.max
;
824 /* based on hardware requirement, prefer smaller n to precision */
825 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
826 /* based on hardware requirement, prefere larger m1,m2 */
827 for (clock
.m1
= limit
->m1
.max
;
828 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
829 for (clock
.m2
= limit
->m2
.max
;
830 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
831 for (clock
.p1
= limit
->p1
.max
;
832 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
835 i9xx_calc_dpll_params(refclk
, &clock
);
836 if (!intel_PLL_is_valid(dev
, limit
,
840 this_err
= abs(clock
.dot
- target
);
841 if (this_err
< err_most
) {
855 * Check if the calculated PLL configuration is more optimal compared to the
856 * best configuration and error found so far. Return the calculated error.
858 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
859 const intel_clock_t
*calculated_clock
,
860 const intel_clock_t
*best_clock
,
861 unsigned int best_error_ppm
,
862 unsigned int *error_ppm
)
865 * For CHV ignore the error and consider only the P value.
866 * Prefer a bigger P value based on HW requirements.
868 if (IS_CHERRYVIEW(dev
)) {
871 return calculated_clock
->p
> best_clock
->p
;
874 if (WARN_ON_ONCE(!target_freq
))
877 *error_ppm
= div_u64(1000000ULL *
878 abs(target_freq
- calculated_clock
->dot
),
881 * Prefer a better P value over a better (smaller) error if the error
882 * is small. Ensure this preference for future configurations too by
883 * setting the error to 0.
885 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
891 return *error_ppm
+ 10 < best_error_ppm
;
895 vlv_find_best_dpll(const intel_limit_t
*limit
,
896 struct intel_crtc_state
*crtc_state
,
897 int target
, int refclk
, intel_clock_t
*match_clock
,
898 intel_clock_t
*best_clock
)
900 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
901 struct drm_device
*dev
= crtc
->base
.dev
;
903 unsigned int bestppm
= 1000000;
904 /* min update 19.2 MHz */
905 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
908 target
*= 5; /* fast clock */
910 memset(best_clock
, 0, sizeof(*best_clock
));
912 /* based on hardware requirement, prefer smaller n to precision */
913 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
914 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
915 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
916 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
917 clock
.p
= clock
.p1
* clock
.p2
;
918 /* based on hardware requirement, prefer bigger m1,m2 values */
919 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
922 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
925 vlv_calc_dpll_params(refclk
, &clock
);
927 if (!intel_PLL_is_valid(dev
, limit
,
931 if (!vlv_PLL_is_optimal(dev
, target
,
949 chv_find_best_dpll(const intel_limit_t
*limit
,
950 struct intel_crtc_state
*crtc_state
,
951 int target
, int refclk
, intel_clock_t
*match_clock
,
952 intel_clock_t
*best_clock
)
954 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
955 struct drm_device
*dev
= crtc
->base
.dev
;
956 unsigned int best_error_ppm
;
961 memset(best_clock
, 0, sizeof(*best_clock
));
962 best_error_ppm
= 1000000;
965 * Based on hardware doc, the n always set to 1, and m1 always
966 * set to 2. If requires to support 200Mhz refclk, we need to
967 * revisit this because n may not 1 anymore.
969 clock
.n
= 1, clock
.m1
= 2;
970 target
*= 5; /* fast clock */
972 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
973 for (clock
.p2
= limit
->p2
.p2_fast
;
974 clock
.p2
>= limit
->p2
.p2_slow
;
975 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
976 unsigned int error_ppm
;
978 clock
.p
= clock
.p1
* clock
.p2
;
980 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
981 clock
.n
) << 22, refclk
* clock
.m1
);
983 if (m2
> INT_MAX
/clock
.m1
)
988 chv_calc_dpll_params(refclk
, &clock
);
990 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
993 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
994 best_error_ppm
, &error_ppm
))
998 best_error_ppm
= error_ppm
;
1006 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1007 intel_clock_t
*best_clock
)
1009 int refclk
= i9xx_get_refclk(crtc_state
, 0);
1011 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
1012 target_clock
, refclk
, NULL
, best_clock
);
1015 bool intel_crtc_active(struct drm_crtc
*crtc
)
1017 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1019 /* Be paranoid as we can arrive here with only partial
1020 * state retrieved from the hardware during setup.
1022 * We can ditch the adjusted_mode.crtc_clock check as soon
1023 * as Haswell has gained clock readout/fastboot support.
1025 * We can ditch the crtc->primary->fb check as soon as we can
1026 * properly reconstruct framebuffers.
1028 * FIXME: The intel_crtc->active here should be switched to
1029 * crtc->state->active once we have proper CRTC states wired up
1032 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1033 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1036 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1039 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1040 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1042 return intel_crtc
->config
->cpu_transcoder
;
1045 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1048 u32 reg
= PIPEDSL(pipe
);
1053 line_mask
= DSL_LINEMASK_GEN2
;
1055 line_mask
= DSL_LINEMASK_GEN3
;
1057 line1
= I915_READ(reg
) & line_mask
;
1059 line2
= I915_READ(reg
) & line_mask
;
1061 return line1
== line2
;
1065 * intel_wait_for_pipe_off - wait for pipe to turn off
1066 * @crtc: crtc whose pipe to wait for
1068 * After disabling a pipe, we can't wait for vblank in the usual way,
1069 * spinning on the vblank interrupt status bit, since we won't actually
1070 * see an interrupt when the pipe is disabled.
1072 * On Gen4 and above:
1073 * wait for the pipe register state bit to turn off
1076 * wait for the display line value to settle (it usually
1077 * ends up stopping at the start of the next frame).
1080 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1082 struct drm_device
*dev
= crtc
->base
.dev
;
1083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1084 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1085 enum pipe pipe
= crtc
->pipe
;
1087 if (INTEL_INFO(dev
)->gen
>= 4) {
1088 int reg
= PIPECONF(cpu_transcoder
);
1090 /* Wait for the Pipe State to go off */
1091 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1093 WARN(1, "pipe_off wait timed out\n");
1095 /* Wait for the display line to settle */
1096 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1097 WARN(1, "pipe_off wait timed out\n");
1101 static const char *state_string(bool enabled
)
1103 return enabled
? "on" : "off";
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private
*dev_priv
,
1108 enum pipe pipe
, bool state
)
1115 val
= I915_READ(reg
);
1116 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1117 I915_STATE_WARN(cur_state
!= state
,
1118 "PLL state assertion failure (expected %s, current %s)\n",
1119 state_string(state
), state_string(cur_state
));
1122 /* XXX: the dsi pll is shared between MIPI DSI ports */
1123 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1128 mutex_lock(&dev_priv
->sb_lock
);
1129 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1130 mutex_unlock(&dev_priv
->sb_lock
);
1132 cur_state
= val
& DSI_PLL_VCO_EN
;
1133 I915_STATE_WARN(cur_state
!= state
,
1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state
), state_string(cur_state
));
1137 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1140 struct intel_shared_dpll
*
1141 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1143 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1145 if (crtc
->config
->shared_dpll
< 0)
1148 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1152 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1153 struct intel_shared_dpll
*pll
,
1157 struct intel_dpll_hw_state hw_state
;
1160 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1163 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1164 I915_STATE_WARN(cur_state
!= state
,
1165 "%s assertion failure (expected %s, current %s)\n",
1166 pll
->name
, state_string(state
), state_string(cur_state
));
1169 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1170 enum pipe pipe
, bool state
)
1175 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1178 if (HAS_DDI(dev_priv
->dev
)) {
1179 /* DDI does not have a specific FDI_TX register */
1180 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1181 val
= I915_READ(reg
);
1182 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1184 reg
= FDI_TX_CTL(pipe
);
1185 val
= I915_READ(reg
);
1186 cur_state
= !!(val
& FDI_TX_ENABLE
);
1188 I915_STATE_WARN(cur_state
!= state
,
1189 "FDI TX state assertion failure (expected %s, current %s)\n",
1190 state_string(state
), state_string(cur_state
));
1192 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1195 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1196 enum pipe pipe
, bool state
)
1202 reg
= FDI_RX_CTL(pipe
);
1203 val
= I915_READ(reg
);
1204 cur_state
= !!(val
& FDI_RX_ENABLE
);
1205 I915_STATE_WARN(cur_state
!= state
,
1206 "FDI RX state assertion failure (expected %s, current %s)\n",
1207 state_string(state
), state_string(cur_state
));
1209 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1212 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1218 /* ILK FDI PLL is always enabled */
1219 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1222 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1223 if (HAS_DDI(dev_priv
->dev
))
1226 reg
= FDI_TX_CTL(pipe
);
1227 val
= I915_READ(reg
);
1228 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1231 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1232 enum pipe pipe
, bool state
)
1238 reg
= FDI_RX_CTL(pipe
);
1239 val
= I915_READ(reg
);
1240 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1241 I915_STATE_WARN(cur_state
!= state
,
1242 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243 state_string(state
), state_string(cur_state
));
1246 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1249 struct drm_device
*dev
= dev_priv
->dev
;
1252 enum pipe panel_pipe
= PIPE_A
;
1255 if (WARN_ON(HAS_DDI(dev
)))
1258 if (HAS_PCH_SPLIT(dev
)) {
1261 pp_reg
= PCH_PP_CONTROL
;
1262 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1264 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1265 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1266 panel_pipe
= PIPE_B
;
1267 /* XXX: else fix for eDP */
1268 } else if (IS_VALLEYVIEW(dev
)) {
1269 /* presumably write lock depends on pipe, not port select */
1270 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1273 pp_reg
= PP_CONTROL
;
1274 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1275 panel_pipe
= PIPE_B
;
1278 val
= I915_READ(pp_reg
);
1279 if (!(val
& PANEL_POWER_ON
) ||
1280 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1283 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1284 "panel assertion failure, pipe %c regs locked\n",
1288 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1289 enum pipe pipe
, bool state
)
1291 struct drm_device
*dev
= dev_priv
->dev
;
1294 if (IS_845G(dev
) || IS_I865G(dev
))
1295 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1297 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1299 I915_STATE_WARN(cur_state
!= state
,
1300 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1303 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1306 void assert_pipe(struct drm_i915_private
*dev_priv
,
1307 enum pipe pipe
, bool state
)
1312 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1315 /* if we need the pipe quirk it must be always on */
1316 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1317 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1320 if (!intel_display_power_is_enabled(dev_priv
,
1321 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1324 reg
= PIPECONF(cpu_transcoder
);
1325 val
= I915_READ(reg
);
1326 cur_state
= !!(val
& PIPECONF_ENABLE
);
1329 I915_STATE_WARN(cur_state
!= state
,
1330 "pipe %c assertion failure (expected %s, current %s)\n",
1331 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1334 static void assert_plane(struct drm_i915_private
*dev_priv
,
1335 enum plane plane
, bool state
)
1341 reg
= DSPCNTR(plane
);
1342 val
= I915_READ(reg
);
1343 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1344 I915_STATE_WARN(cur_state
!= state
,
1345 "plane %c assertion failure (expected %s, current %s)\n",
1346 plane_name(plane
), state_string(state
), state_string(cur_state
));
1349 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1352 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1355 struct drm_device
*dev
= dev_priv
->dev
;
1360 /* Primary planes are fixed to pipes on gen4+ */
1361 if (INTEL_INFO(dev
)->gen
>= 4) {
1362 reg
= DSPCNTR(pipe
);
1363 val
= I915_READ(reg
);
1364 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1365 "plane %c assertion failure, should be disabled but not\n",
1370 /* Need to check both planes against the pipe */
1371 for_each_pipe(dev_priv
, i
) {
1373 val
= I915_READ(reg
);
1374 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1375 DISPPLANE_SEL_PIPE_SHIFT
;
1376 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1377 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378 plane_name(i
), pipe_name(pipe
));
1382 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1385 struct drm_device
*dev
= dev_priv
->dev
;
1389 if (INTEL_INFO(dev
)->gen
>= 9) {
1390 for_each_sprite(dev_priv
, pipe
, sprite
) {
1391 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1392 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1393 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394 sprite
, pipe_name(pipe
));
1396 } else if (IS_VALLEYVIEW(dev
)) {
1397 for_each_sprite(dev_priv
, pipe
, sprite
) {
1398 reg
= SPCNTR(pipe
, sprite
);
1399 val
= I915_READ(reg
);
1400 I915_STATE_WARN(val
& SP_ENABLE
,
1401 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1402 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1404 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1406 val
= I915_READ(reg
);
1407 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1409 plane_name(pipe
), pipe_name(pipe
));
1410 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1411 reg
= DVSCNTR(pipe
);
1412 val
= I915_READ(reg
);
1413 I915_STATE_WARN(val
& DVS_ENABLE
,
1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415 plane_name(pipe
), pipe_name(pipe
));
1419 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1421 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1422 drm_crtc_vblank_put(crtc
);
1425 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1430 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1432 val
= I915_READ(PCH_DREF_CONTROL
);
1433 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1434 DREF_SUPERSPREAD_SOURCE_MASK
));
1435 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1438 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1445 reg
= PCH_TRANSCONF(pipe
);
1446 val
= I915_READ(reg
);
1447 enabled
= !!(val
& TRANS_ENABLE
);
1448 I915_STATE_WARN(enabled
,
1449 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1453 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1454 enum pipe pipe
, u32 port_sel
, u32 val
)
1456 if ((val
& DP_PORT_EN
) == 0)
1459 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1460 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1461 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1462 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1464 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1465 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1468 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1474 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1475 enum pipe pipe
, u32 val
)
1477 if ((val
& SDVO_ENABLE
) == 0)
1480 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1481 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1483 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1484 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1487 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1493 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1494 enum pipe pipe
, u32 val
)
1496 if ((val
& LVDS_PORT_EN
) == 0)
1499 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1500 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1503 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1509 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1510 enum pipe pipe
, u32 val
)
1512 if ((val
& ADPA_DAC_ENABLE
) == 0)
1514 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1515 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1518 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1524 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1525 enum pipe pipe
, int reg
, u32 port_sel
)
1527 u32 val
= I915_READ(reg
);
1528 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1529 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1530 reg
, pipe_name(pipe
));
1532 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1533 && (val
& DP_PIPEB_SELECT
),
1534 "IBX PCH dp port still using transcoder B\n");
1537 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1538 enum pipe pipe
, int reg
)
1540 u32 val
= I915_READ(reg
);
1541 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1542 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1543 reg
, pipe_name(pipe
));
1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1546 && (val
& SDVO_PIPE_B_SELECT
),
1547 "IBX PCH hdmi port still using transcoder B\n");
1550 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1556 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1557 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1558 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1561 val
= I915_READ(reg
);
1562 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1563 "PCH VGA enabled on transcoder %c, should be disabled\n",
1567 val
= I915_READ(reg
);
1568 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1572 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1573 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1574 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1577 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1578 const struct intel_crtc_state
*pipe_config
)
1580 struct drm_device
*dev
= crtc
->base
.dev
;
1581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 int reg
= DPLL(crtc
->pipe
);
1583 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1585 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1587 /* No really, not for ILK+ */
1588 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1590 /* PLL is protected by panel, make sure we can write it */
1591 if (IS_MOBILE(dev_priv
->dev
))
1592 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1594 I915_WRITE(reg
, dpll
);
1598 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1599 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1601 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1602 POSTING_READ(DPLL_MD(crtc
->pipe
));
1604 /* We do this three times for luck */
1605 I915_WRITE(reg
, dpll
);
1607 udelay(150); /* wait for warmup */
1608 I915_WRITE(reg
, dpll
);
1610 udelay(150); /* wait for warmup */
1611 I915_WRITE(reg
, dpll
);
1613 udelay(150); /* wait for warmup */
1616 static void chv_enable_pll(struct intel_crtc
*crtc
,
1617 const struct intel_crtc_state
*pipe_config
)
1619 struct drm_device
*dev
= crtc
->base
.dev
;
1620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1621 int pipe
= crtc
->pipe
;
1622 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1625 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1627 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1629 mutex_lock(&dev_priv
->sb_lock
);
1631 /* Enable back the 10bit clock to display controller */
1632 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1633 tmp
|= DPIO_DCLKP_EN
;
1634 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1636 mutex_unlock(&dev_priv
->sb_lock
);
1639 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1646 /* Check PLL is locked */
1647 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1648 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1650 /* not sure when this should be written */
1651 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1652 POSTING_READ(DPLL_MD(pipe
));
1655 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1657 struct intel_crtc
*crtc
;
1660 for_each_intel_crtc(dev
, crtc
)
1661 count
+= crtc
->base
.state
->active
&&
1662 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1667 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1669 struct drm_device
*dev
= crtc
->base
.dev
;
1670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1671 int reg
= DPLL(crtc
->pipe
);
1672 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1674 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1676 /* No really, not for ILK+ */
1677 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1679 /* PLL is protected by panel, make sure we can write it */
1680 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1681 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1683 /* Enable DVO 2x clock on both PLLs if necessary */
1684 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1686 * It appears to be important that we don't enable this
1687 * for the current pipe before otherwise configuring the
1688 * PLL. No idea how this should be handled if multiple
1689 * DVO outputs are enabled simultaneosly.
1691 dpll
|= DPLL_DVO_2X_MODE
;
1692 I915_WRITE(DPLL(!crtc
->pipe
),
1693 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1696 /* Wait for the clocks to stabilize. */
1700 if (INTEL_INFO(dev
)->gen
>= 4) {
1701 I915_WRITE(DPLL_MD(crtc
->pipe
),
1702 crtc
->config
->dpll_hw_state
.dpll_md
);
1704 /* The pixel multiplier can only be updated once the
1705 * DPLL is enabled and the clocks are stable.
1707 * So write it again.
1709 I915_WRITE(reg
, dpll
);
1712 /* We do this three times for luck */
1713 I915_WRITE(reg
, dpll
);
1715 udelay(150); /* wait for warmup */
1716 I915_WRITE(reg
, dpll
);
1718 udelay(150); /* wait for warmup */
1719 I915_WRITE(reg
, dpll
);
1721 udelay(150); /* wait for warmup */
1725 * i9xx_disable_pll - disable a PLL
1726 * @dev_priv: i915 private structure
1727 * @pipe: pipe PLL to disable
1729 * Disable the PLL for @pipe, making sure the pipe is off first.
1731 * Note! This is for pre-ILK only.
1733 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1735 struct drm_device
*dev
= crtc
->base
.dev
;
1736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1737 enum pipe pipe
= crtc
->pipe
;
1739 /* Disable DVO 2x clock on both PLLs if necessary */
1741 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1742 !intel_num_dvo_pipes(dev
)) {
1743 I915_WRITE(DPLL(PIPE_B
),
1744 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1745 I915_WRITE(DPLL(PIPE_A
),
1746 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1749 /* Don't disable pipe or pipe PLLs if needed */
1750 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1751 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1754 /* Make sure the pipe isn't still relying on us */
1755 assert_pipe_disabled(dev_priv
, pipe
);
1757 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1758 POSTING_READ(DPLL(pipe
));
1761 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1765 /* Make sure the pipe isn't still relying on us */
1766 assert_pipe_disabled(dev_priv
, pipe
);
1769 * Leave integrated clock source and reference clock enabled for pipe B.
1770 * The latter is needed for VGA hotplug / manual detection.
1772 val
= DPLL_VGA_MODE_DIS
;
1774 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REF_CLK_ENABLE_VLV
;
1775 I915_WRITE(DPLL(pipe
), val
);
1776 POSTING_READ(DPLL(pipe
));
1780 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1782 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv
, pipe
);
1788 /* Set PLL en = 0 */
1789 val
= DPLL_SSC_REF_CLK_CHV
|
1790 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1792 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1793 I915_WRITE(DPLL(pipe
), val
);
1794 POSTING_READ(DPLL(pipe
));
1796 mutex_lock(&dev_priv
->sb_lock
);
1798 /* Disable 10bit clock to display controller */
1799 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1800 val
&= ~DPIO_DCLKP_EN
;
1801 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1803 mutex_unlock(&dev_priv
->sb_lock
);
1806 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1807 struct intel_digital_port
*dport
,
1808 unsigned int expected_mask
)
1813 switch (dport
->port
) {
1815 port_mask
= DPLL_PORTB_READY_MASK
;
1819 port_mask
= DPLL_PORTC_READY_MASK
;
1821 expected_mask
<<= 4;
1824 port_mask
= DPLL_PORTD_READY_MASK
;
1825 dpll_reg
= DPIO_PHY_STATUS
;
1831 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1832 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1833 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1836 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1838 struct drm_device
*dev
= crtc
->base
.dev
;
1839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1840 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1842 if (WARN_ON(pll
== NULL
))
1845 WARN_ON(!pll
->config
.crtc_mask
);
1846 if (pll
->active
== 0) {
1847 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1849 assert_shared_dpll_disabled(dev_priv
, pll
);
1851 pll
->mode_set(dev_priv
, pll
);
1856 * intel_enable_shared_dpll - enable PCH PLL
1857 * @dev_priv: i915 private structure
1858 * @pipe: pipe PLL to enable
1860 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1861 * drives the transcoder clock.
1863 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1865 struct drm_device
*dev
= crtc
->base
.dev
;
1866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1869 if (WARN_ON(pll
== NULL
))
1872 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1875 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1876 pll
->name
, pll
->active
, pll
->on
,
1877 crtc
->base
.base
.id
);
1879 if (pll
->active
++) {
1881 assert_shared_dpll_enabled(dev_priv
, pll
);
1886 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1888 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1889 pll
->enable(dev_priv
, pll
);
1893 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1895 struct drm_device
*dev
= crtc
->base
.dev
;
1896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1897 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1899 /* PCH only available on ILK+ */
1900 if (INTEL_INFO(dev
)->gen
< 5)
1906 if (WARN_ON(!(pll
->config
.crtc_mask
& (1 << drm_crtc_index(&crtc
->base
)))))
1909 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1910 pll
->name
, pll
->active
, pll
->on
,
1911 crtc
->base
.base
.id
);
1913 if (WARN_ON(pll
->active
== 0)) {
1914 assert_shared_dpll_disabled(dev_priv
, pll
);
1918 assert_shared_dpll_enabled(dev_priv
, pll
);
1923 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1924 pll
->disable(dev_priv
, pll
);
1927 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1930 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1933 struct drm_device
*dev
= dev_priv
->dev
;
1934 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1936 uint32_t reg
, val
, pipeconf_val
;
1938 /* PCH only available on ILK+ */
1939 BUG_ON(!HAS_PCH_SPLIT(dev
));
1941 /* Make sure PCH DPLL is enabled */
1942 assert_shared_dpll_enabled(dev_priv
,
1943 intel_crtc_to_shared_dpll(intel_crtc
));
1945 /* FDI must be feeding us bits for PCH ports */
1946 assert_fdi_tx_enabled(dev_priv
, pipe
);
1947 assert_fdi_rx_enabled(dev_priv
, pipe
);
1949 if (HAS_PCH_CPT(dev
)) {
1950 /* Workaround: Set the timing override bit before enabling the
1951 * pch transcoder. */
1952 reg
= TRANS_CHICKEN2(pipe
);
1953 val
= I915_READ(reg
);
1954 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1955 I915_WRITE(reg
, val
);
1958 reg
= PCH_TRANSCONF(pipe
);
1959 val
= I915_READ(reg
);
1960 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1962 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1964 * Make the BPC in transcoder be consistent with
1965 * that in pipeconf reg. For HDMI we must use 8bpc
1966 * here for both 8bpc and 12bpc.
1968 val
&= ~PIPECONF_BPC_MASK
;
1969 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_HDMI
))
1970 val
|= PIPECONF_8BPC
;
1972 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1975 val
&= ~TRANS_INTERLACE_MASK
;
1976 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1977 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1978 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1979 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1981 val
|= TRANS_INTERLACED
;
1983 val
|= TRANS_PROGRESSIVE
;
1985 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1986 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1987 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1990 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1991 enum transcoder cpu_transcoder
)
1993 u32 val
, pipeconf_val
;
1995 /* PCH only available on ILK+ */
1996 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1998 /* FDI must be feeding us bits for PCH ports */
1999 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2000 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2002 /* Workaround: set timing override bit. */
2003 val
= I915_READ(_TRANSA_CHICKEN2
);
2004 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2005 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2008 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2010 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2011 PIPECONF_INTERLACED_ILK
)
2012 val
|= TRANS_INTERLACED
;
2014 val
|= TRANS_PROGRESSIVE
;
2016 I915_WRITE(LPT_TRANSCONF
, val
);
2017 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2018 DRM_ERROR("Failed to enable PCH transcoder\n");
2021 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2024 struct drm_device
*dev
= dev_priv
->dev
;
2027 /* FDI relies on the transcoder */
2028 assert_fdi_tx_disabled(dev_priv
, pipe
);
2029 assert_fdi_rx_disabled(dev_priv
, pipe
);
2031 /* Ports must be off as well */
2032 assert_pch_ports_disabled(dev_priv
, pipe
);
2034 reg
= PCH_TRANSCONF(pipe
);
2035 val
= I915_READ(reg
);
2036 val
&= ~TRANS_ENABLE
;
2037 I915_WRITE(reg
, val
);
2038 /* wait for PCH transcoder off, transcoder state */
2039 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2040 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2042 if (!HAS_PCH_IBX(dev
)) {
2043 /* Workaround: Clear the timing override chicken bit again. */
2044 reg
= TRANS_CHICKEN2(pipe
);
2045 val
= I915_READ(reg
);
2046 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2047 I915_WRITE(reg
, val
);
2051 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2055 val
= I915_READ(LPT_TRANSCONF
);
2056 val
&= ~TRANS_ENABLE
;
2057 I915_WRITE(LPT_TRANSCONF
, val
);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2060 DRM_ERROR("Failed to disable PCH transcoder\n");
2062 /* Workaround: clear timing override bit. */
2063 val
= I915_READ(_TRANSA_CHICKEN2
);
2064 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2065 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2069 * intel_enable_pipe - enable a pipe, asserting requirements
2070 * @crtc: crtc responsible for the pipe
2072 * Enable @crtc's pipe, making sure that various hardware specific requirements
2073 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2075 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2077 struct drm_device
*dev
= crtc
->base
.dev
;
2078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2079 enum pipe pipe
= crtc
->pipe
;
2080 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2082 enum pipe pch_transcoder
;
2086 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
2088 assert_planes_disabled(dev_priv
, pipe
);
2089 assert_cursor_disabled(dev_priv
, pipe
);
2090 assert_sprites_disabled(dev_priv
, pipe
);
2092 if (HAS_PCH_LPT(dev_priv
->dev
))
2093 pch_transcoder
= TRANSCODER_A
;
2095 pch_transcoder
= pipe
;
2098 * A pipe without a PLL won't actually be able to drive bits from
2099 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2102 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2103 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2104 assert_dsi_pll_enabled(dev_priv
);
2106 assert_pll_enabled(dev_priv
, pipe
);
2108 if (crtc
->config
->has_pch_encoder
) {
2109 /* if driving the PCH, we need FDI enabled */
2110 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2111 assert_fdi_tx_pll_enabled(dev_priv
,
2112 (enum pipe
) cpu_transcoder
);
2114 /* FIXME: assert CPU port conditions for SNB+ */
2117 reg
= PIPECONF(cpu_transcoder
);
2118 val
= I915_READ(reg
);
2119 if (val
& PIPECONF_ENABLE
) {
2120 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2121 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2125 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2130 * intel_disable_pipe - disable a pipe, asserting requirements
2131 * @crtc: crtc whose pipes is to be disabled
2133 * Disable the pipe of @crtc, making sure that various hardware
2134 * specific requirements are met, if applicable, e.g. plane
2135 * disabled, panel fitter off, etc.
2137 * Will wait until the pipe has shut down before returning.
2139 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2141 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2142 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2143 enum pipe pipe
= crtc
->pipe
;
2147 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2150 * Make sure planes won't keep trying to pump pixels to us,
2151 * or we might hang the display.
2153 assert_planes_disabled(dev_priv
, pipe
);
2154 assert_cursor_disabled(dev_priv
, pipe
);
2155 assert_sprites_disabled(dev_priv
, pipe
);
2157 reg
= PIPECONF(cpu_transcoder
);
2158 val
= I915_READ(reg
);
2159 if ((val
& PIPECONF_ENABLE
) == 0)
2163 * Double wide has implications for planes
2164 * so best keep it disabled when not needed.
2166 if (crtc
->config
->double_wide
)
2167 val
&= ~PIPECONF_DOUBLE_WIDE
;
2169 /* Don't disable pipe or pipe PLLs if needed */
2170 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2171 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2172 val
&= ~PIPECONF_ENABLE
;
2174 I915_WRITE(reg
, val
);
2175 if ((val
& PIPECONF_ENABLE
) == 0)
2176 intel_wait_for_pipe_off(crtc
);
2179 static bool need_vtd_wa(struct drm_device
*dev
)
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2189 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2190 uint64_t fb_format_modifier
)
2192 unsigned int tile_height
;
2193 uint32_t pixel_bytes
;
2195 switch (fb_format_modifier
) {
2196 case DRM_FORMAT_MOD_NONE
:
2199 case I915_FORMAT_MOD_X_TILED
:
2200 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2202 case I915_FORMAT_MOD_Y_TILED
:
2205 case I915_FORMAT_MOD_Yf_TILED
:
2206 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2207 switch (pixel_bytes
) {
2221 "128-bit pixels are not supported for display!");
2227 MISSING_CASE(fb_format_modifier
);
2236 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2237 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2239 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2240 fb_format_modifier
));
2244 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2245 const struct drm_plane_state
*plane_state
)
2247 struct intel_rotation_info
*info
= &view
->rotation_info
;
2248 unsigned int tile_height
, tile_pitch
;
2250 *view
= i915_ggtt_view_normal
;
2255 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2258 *view
= i915_ggtt_view_rotated
;
2260 info
->height
= fb
->height
;
2261 info
->pixel_format
= fb
->pixel_format
;
2262 info
->pitch
= fb
->pitches
[0];
2263 info
->fb_modifier
= fb
->modifier
[0];
2265 tile_height
= intel_tile_height(fb
->dev
, fb
->pixel_format
,
2267 tile_pitch
= PAGE_SIZE
/ tile_height
;
2268 info
->width_pages
= DIV_ROUND_UP(fb
->pitches
[0], tile_pitch
);
2269 info
->height_pages
= DIV_ROUND_UP(fb
->height
, tile_height
);
2270 info
->size
= info
->width_pages
* info
->height_pages
* PAGE_SIZE
;
2275 static unsigned int intel_linear_alignment(struct drm_i915_private
*dev_priv
)
2277 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2279 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2280 IS_VALLEYVIEW(dev_priv
))
2282 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2289 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2290 struct drm_framebuffer
*fb
,
2291 const struct drm_plane_state
*plane_state
,
2292 struct intel_engine_cs
*pipelined
,
2293 struct drm_i915_gem_request
**pipelined_request
)
2295 struct drm_device
*dev
= fb
->dev
;
2296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2297 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2298 struct i915_ggtt_view view
;
2302 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2304 switch (fb
->modifier
[0]) {
2305 case DRM_FORMAT_MOD_NONE
:
2306 alignment
= intel_linear_alignment(dev_priv
);
2308 case I915_FORMAT_MOD_X_TILED
:
2309 if (INTEL_INFO(dev
)->gen
>= 9)
2310 alignment
= 256 * 1024;
2312 /* pin() will align the object as required by fence */
2316 case I915_FORMAT_MOD_Y_TILED
:
2317 case I915_FORMAT_MOD_Yf_TILED
:
2318 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2319 "Y tiling bo slipped through, driver bug!\n"))
2321 alignment
= 1 * 1024 * 1024;
2324 MISSING_CASE(fb
->modifier
[0]);
2328 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2332 /* Note that the w/a also requires 64 PTE of padding following the
2333 * bo. We currently fill all unused PTE with the shadow page and so
2334 * we should always have valid PTE following the scanout preventing
2337 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2338 alignment
= 256 * 1024;
2341 * Global gtt pte registers are special registers which actually forward
2342 * writes to a chunk of system memory. Which means that there is no risk
2343 * that the register values disappear as soon as we call
2344 * intel_runtime_pm_put(), so it is correct to wrap only the
2345 * pin/unpin/fence and not more.
2347 intel_runtime_pm_get(dev_priv
);
2349 dev_priv
->mm
.interruptible
= false;
2350 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2351 pipelined_request
, &view
);
2353 goto err_interruptible
;
2355 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2356 * fence, whereas 965+ only requires a fence if using
2357 * framebuffer compression. For simplicity, we always install
2358 * a fence as the cost is not that onerous.
2360 ret
= i915_gem_object_get_fence(obj
);
2361 if (ret
== -EDEADLK
) {
2363 * -EDEADLK means there are no free fences
2366 * This is propagated to atomic, but it uses
2367 * -EDEADLK to force a locking recovery, so
2368 * change the returned error to -EBUSY.
2375 i915_gem_object_pin_fence(obj
);
2377 dev_priv
->mm
.interruptible
= true;
2378 intel_runtime_pm_put(dev_priv
);
2382 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2384 dev_priv
->mm
.interruptible
= true;
2385 intel_runtime_pm_put(dev_priv
);
2389 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2390 const struct drm_plane_state
*plane_state
)
2392 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2393 struct i915_ggtt_view view
;
2396 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2398 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2399 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2401 i915_gem_object_unpin_fence(obj
);
2402 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2405 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2406 * is assumed to be a power-of-two. */
2407 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private
*dev_priv
,
2409 unsigned int tiling_mode
,
2413 if (tiling_mode
!= I915_TILING_NONE
) {
2414 unsigned int tile_rows
, tiles
;
2419 tiles
= *x
/ (512/cpp
);
2422 return tile_rows
* pitch
* 8 + tiles
* 4096;
2424 unsigned int alignment
= intel_linear_alignment(dev_priv
) - 1;
2425 unsigned int offset
;
2427 offset
= *y
* pitch
+ *x
* cpp
;
2428 *y
= (offset
& alignment
) / pitch
;
2429 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2430 return offset
& ~alignment
;
2434 static int i9xx_format_to_fourcc(int format
)
2437 case DISPPLANE_8BPP
:
2438 return DRM_FORMAT_C8
;
2439 case DISPPLANE_BGRX555
:
2440 return DRM_FORMAT_XRGB1555
;
2441 case DISPPLANE_BGRX565
:
2442 return DRM_FORMAT_RGB565
;
2444 case DISPPLANE_BGRX888
:
2445 return DRM_FORMAT_XRGB8888
;
2446 case DISPPLANE_RGBX888
:
2447 return DRM_FORMAT_XBGR8888
;
2448 case DISPPLANE_BGRX101010
:
2449 return DRM_FORMAT_XRGB2101010
;
2450 case DISPPLANE_RGBX101010
:
2451 return DRM_FORMAT_XBGR2101010
;
2455 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2458 case PLANE_CTL_FORMAT_RGB_565
:
2459 return DRM_FORMAT_RGB565
;
2461 case PLANE_CTL_FORMAT_XRGB_8888
:
2464 return DRM_FORMAT_ABGR8888
;
2466 return DRM_FORMAT_XBGR8888
;
2469 return DRM_FORMAT_ARGB8888
;
2471 return DRM_FORMAT_XRGB8888
;
2473 case PLANE_CTL_FORMAT_XRGB_2101010
:
2475 return DRM_FORMAT_XBGR2101010
;
2477 return DRM_FORMAT_XRGB2101010
;
2482 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2483 struct intel_initial_plane_config
*plane_config
)
2485 struct drm_device
*dev
= crtc
->base
.dev
;
2486 struct drm_i915_gem_object
*obj
= NULL
;
2487 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2488 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2489 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2490 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2493 size_aligned
-= base_aligned
;
2495 if (plane_config
->size
== 0)
2498 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2505 obj
->tiling_mode
= plane_config
->tiling
;
2506 if (obj
->tiling_mode
== I915_TILING_X
)
2507 obj
->stride
= fb
->pitches
[0];
2509 mode_cmd
.pixel_format
= fb
->pixel_format
;
2510 mode_cmd
.width
= fb
->width
;
2511 mode_cmd
.height
= fb
->height
;
2512 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2513 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2514 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2516 mutex_lock(&dev
->struct_mutex
);
2517 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2519 DRM_DEBUG_KMS("intel fb init failed\n");
2522 mutex_unlock(&dev
->struct_mutex
);
2524 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2528 drm_gem_object_unreference(&obj
->base
);
2529 mutex_unlock(&dev
->struct_mutex
);
2533 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2535 update_state_fb(struct drm_plane
*plane
)
2537 if (plane
->fb
== plane
->state
->fb
)
2540 if (plane
->state
->fb
)
2541 drm_framebuffer_unreference(plane
->state
->fb
);
2542 plane
->state
->fb
= plane
->fb
;
2543 if (plane
->state
->fb
)
2544 drm_framebuffer_reference(plane
->state
->fb
);
2548 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2549 struct intel_initial_plane_config
*plane_config
)
2551 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2554 struct intel_crtc
*i
;
2555 struct drm_i915_gem_object
*obj
;
2556 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2557 struct drm_plane_state
*plane_state
= primary
->state
;
2558 struct drm_framebuffer
*fb
;
2560 if (!plane_config
->fb
)
2563 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2564 fb
= &plane_config
->fb
->base
;
2568 kfree(plane_config
->fb
);
2571 * Failed to alloc the obj, check to see if we should share
2572 * an fb with another CRTC instead
2574 for_each_crtc(dev
, c
) {
2575 i
= to_intel_crtc(c
);
2577 if (c
== &intel_crtc
->base
)
2583 fb
= c
->primary
->fb
;
2587 obj
= intel_fb_obj(fb
);
2588 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2589 drm_framebuffer_reference(fb
);
2597 plane_state
->src_x
= plane_state
->src_y
= 0;
2598 plane_state
->src_w
= fb
->width
<< 16;
2599 plane_state
->src_h
= fb
->height
<< 16;
2601 plane_state
->crtc_x
= plane_state
->src_y
= 0;
2602 plane_state
->crtc_w
= fb
->width
;
2603 plane_state
->crtc_h
= fb
->height
;
2605 obj
= intel_fb_obj(fb
);
2606 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2607 dev_priv
->preserve_bios_swizzle
= true;
2609 drm_framebuffer_reference(fb
);
2610 primary
->fb
= primary
->state
->fb
= fb
;
2611 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2612 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2613 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2616 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2617 struct drm_framebuffer
*fb
,
2620 struct drm_device
*dev
= crtc
->dev
;
2621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2622 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2623 struct drm_plane
*primary
= crtc
->primary
;
2624 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2625 struct drm_i915_gem_object
*obj
;
2626 int plane
= intel_crtc
->plane
;
2627 unsigned long linear_offset
;
2629 u32 reg
= DSPCNTR(plane
);
2632 if (!visible
|| !fb
) {
2634 if (INTEL_INFO(dev
)->gen
>= 4)
2635 I915_WRITE(DSPSURF(plane
), 0);
2637 I915_WRITE(DSPADDR(plane
), 0);
2642 obj
= intel_fb_obj(fb
);
2643 if (WARN_ON(obj
== NULL
))
2646 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2648 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2650 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2652 if (INTEL_INFO(dev
)->gen
< 4) {
2653 if (intel_crtc
->pipe
== PIPE_B
)
2654 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2656 /* pipesrc and dspsize control the size that is scaled from,
2657 * which should always be the user's requested size.
2659 I915_WRITE(DSPSIZE(plane
),
2660 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2661 (intel_crtc
->config
->pipe_src_w
- 1));
2662 I915_WRITE(DSPPOS(plane
), 0);
2663 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2664 I915_WRITE(PRIMSIZE(plane
),
2665 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2666 (intel_crtc
->config
->pipe_src_w
- 1));
2667 I915_WRITE(PRIMPOS(plane
), 0);
2668 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2671 switch (fb
->pixel_format
) {
2673 dspcntr
|= DISPPLANE_8BPP
;
2675 case DRM_FORMAT_XRGB1555
:
2676 dspcntr
|= DISPPLANE_BGRX555
;
2678 case DRM_FORMAT_RGB565
:
2679 dspcntr
|= DISPPLANE_BGRX565
;
2681 case DRM_FORMAT_XRGB8888
:
2682 dspcntr
|= DISPPLANE_BGRX888
;
2684 case DRM_FORMAT_XBGR8888
:
2685 dspcntr
|= DISPPLANE_RGBX888
;
2687 case DRM_FORMAT_XRGB2101010
:
2688 dspcntr
|= DISPPLANE_BGRX101010
;
2690 case DRM_FORMAT_XBGR2101010
:
2691 dspcntr
|= DISPPLANE_RGBX101010
;
2697 if (INTEL_INFO(dev
)->gen
>= 4 &&
2698 obj
->tiling_mode
!= I915_TILING_NONE
)
2699 dspcntr
|= DISPPLANE_TILED
;
2702 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2704 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2706 if (INTEL_INFO(dev
)->gen
>= 4) {
2707 intel_crtc
->dspaddr_offset
=
2708 intel_gen4_compute_page_offset(dev_priv
,
2709 &x
, &y
, obj
->tiling_mode
,
2712 linear_offset
-= intel_crtc
->dspaddr_offset
;
2714 intel_crtc
->dspaddr_offset
= linear_offset
;
2717 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2718 dspcntr
|= DISPPLANE_ROTATE_180
;
2720 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2721 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2723 /* Finding the last pixel of the last line of the display
2724 data and adding to linear_offset*/
2726 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2727 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2730 I915_WRITE(reg
, dspcntr
);
2732 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2733 if (INTEL_INFO(dev
)->gen
>= 4) {
2734 I915_WRITE(DSPSURF(plane
),
2735 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2736 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2737 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2739 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2743 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2744 struct drm_framebuffer
*fb
,
2747 struct drm_device
*dev
= crtc
->dev
;
2748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2749 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2750 struct drm_plane
*primary
= crtc
->primary
;
2751 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2752 struct drm_i915_gem_object
*obj
;
2753 int plane
= intel_crtc
->plane
;
2754 unsigned long linear_offset
;
2756 u32 reg
= DSPCNTR(plane
);
2759 if (!visible
|| !fb
) {
2761 I915_WRITE(DSPSURF(plane
), 0);
2766 obj
= intel_fb_obj(fb
);
2767 if (WARN_ON(obj
== NULL
))
2770 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2772 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2774 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2776 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2777 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2779 switch (fb
->pixel_format
) {
2781 dspcntr
|= DISPPLANE_8BPP
;
2783 case DRM_FORMAT_RGB565
:
2784 dspcntr
|= DISPPLANE_BGRX565
;
2786 case DRM_FORMAT_XRGB8888
:
2787 dspcntr
|= DISPPLANE_BGRX888
;
2789 case DRM_FORMAT_XBGR8888
:
2790 dspcntr
|= DISPPLANE_RGBX888
;
2792 case DRM_FORMAT_XRGB2101010
:
2793 dspcntr
|= DISPPLANE_BGRX101010
;
2795 case DRM_FORMAT_XBGR2101010
:
2796 dspcntr
|= DISPPLANE_RGBX101010
;
2802 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2803 dspcntr
|= DISPPLANE_TILED
;
2805 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2806 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2808 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2809 intel_crtc
->dspaddr_offset
=
2810 intel_gen4_compute_page_offset(dev_priv
,
2811 &x
, &y
, obj
->tiling_mode
,
2814 linear_offset
-= intel_crtc
->dspaddr_offset
;
2815 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2816 dspcntr
|= DISPPLANE_ROTATE_180
;
2818 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2819 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2820 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2822 /* Finding the last pixel of the last line of the display
2823 data and adding to linear_offset*/
2825 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2826 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2830 I915_WRITE(reg
, dspcntr
);
2832 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2833 I915_WRITE(DSPSURF(plane
),
2834 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2835 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2836 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2838 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2839 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2844 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2845 uint32_t pixel_format
)
2847 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2850 * The stride is either expressed as a multiple of 64 bytes
2851 * chunks for linear buffers or in number of tiles for tiled
2854 switch (fb_modifier
) {
2855 case DRM_FORMAT_MOD_NONE
:
2857 case I915_FORMAT_MOD_X_TILED
:
2858 if (INTEL_INFO(dev
)->gen
== 2)
2861 case I915_FORMAT_MOD_Y_TILED
:
2862 /* No need to check for old gens and Y tiling since this is
2863 * about the display engine and those will be blocked before
2867 case I915_FORMAT_MOD_Yf_TILED
:
2868 if (bits_per_pixel
== 8)
2873 MISSING_CASE(fb_modifier
);
2878 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2879 struct drm_i915_gem_object
*obj
)
2881 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2883 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2884 view
= &i915_ggtt_view_rotated
;
2886 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2889 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2891 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2894 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2895 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2896 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2900 * This function detaches (aka. unbinds) unused scalers in hardware
2902 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2904 struct intel_crtc_scaler_state
*scaler_state
;
2907 scaler_state
= &intel_crtc
->config
->scaler_state
;
2909 /* loop through and disable scalers that aren't in use */
2910 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2911 if (!scaler_state
->scalers
[i
].in_use
)
2912 skl_detach_scaler(intel_crtc
, i
);
2916 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2918 switch (pixel_format
) {
2920 return PLANE_CTL_FORMAT_INDEXED
;
2921 case DRM_FORMAT_RGB565
:
2922 return PLANE_CTL_FORMAT_RGB_565
;
2923 case DRM_FORMAT_XBGR8888
:
2924 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2925 case DRM_FORMAT_XRGB8888
:
2926 return PLANE_CTL_FORMAT_XRGB_8888
;
2928 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2929 * to be already pre-multiplied. We need to add a knob (or a different
2930 * DRM_FORMAT) for user-space to configure that.
2932 case DRM_FORMAT_ABGR8888
:
2933 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2934 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2935 case DRM_FORMAT_ARGB8888
:
2936 return PLANE_CTL_FORMAT_XRGB_8888
|
2937 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2938 case DRM_FORMAT_XRGB2101010
:
2939 return PLANE_CTL_FORMAT_XRGB_2101010
;
2940 case DRM_FORMAT_XBGR2101010
:
2941 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2942 case DRM_FORMAT_YUYV
:
2943 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2944 case DRM_FORMAT_YVYU
:
2945 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2946 case DRM_FORMAT_UYVY
:
2947 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2948 case DRM_FORMAT_VYUY
:
2949 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2951 MISSING_CASE(pixel_format
);
2957 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2959 switch (fb_modifier
) {
2960 case DRM_FORMAT_MOD_NONE
:
2962 case I915_FORMAT_MOD_X_TILED
:
2963 return PLANE_CTL_TILED_X
;
2964 case I915_FORMAT_MOD_Y_TILED
:
2965 return PLANE_CTL_TILED_Y
;
2966 case I915_FORMAT_MOD_Yf_TILED
:
2967 return PLANE_CTL_TILED_YF
;
2969 MISSING_CASE(fb_modifier
);
2975 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2978 case BIT(DRM_ROTATE_0
):
2981 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2982 * while i915 HW rotation is clockwise, thats why this swapping.
2984 case BIT(DRM_ROTATE_90
):
2985 return PLANE_CTL_ROTATE_270
;
2986 case BIT(DRM_ROTATE_180
):
2987 return PLANE_CTL_ROTATE_180
;
2988 case BIT(DRM_ROTATE_270
):
2989 return PLANE_CTL_ROTATE_90
;
2991 MISSING_CASE(rotation
);
2997 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2998 struct drm_framebuffer
*fb
,
3001 struct drm_device
*dev
= crtc
->dev
;
3002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3003 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3004 struct drm_plane
*plane
= crtc
->primary
;
3005 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3006 struct drm_i915_gem_object
*obj
;
3007 int pipe
= intel_crtc
->pipe
;
3008 u32 plane_ctl
, stride_div
, stride
;
3009 u32 tile_height
, plane_offset
, plane_size
;
3010 unsigned int rotation
;
3011 int x_offset
, y_offset
;
3012 unsigned long surf_addr
;
3013 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3014 struct intel_plane_state
*plane_state
;
3015 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3016 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3019 plane_state
= to_intel_plane_state(plane
->state
);
3021 if (!visible
|| !fb
) {
3022 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3023 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3024 POSTING_READ(PLANE_CTL(pipe
, 0));
3028 plane_ctl
= PLANE_CTL_ENABLE
|
3029 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3030 PLANE_CTL_PIPE_CSC_ENABLE
;
3032 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3033 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3034 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3036 rotation
= plane
->state
->rotation
;
3037 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3039 obj
= intel_fb_obj(fb
);
3040 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3042 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3045 * FIXME: intel_plane_state->src, dst aren't set when transitional
3046 * update_plane helpers are called from legacy paths.
3047 * Once full atomic crtc is available, below check can be avoided.
3049 if (drm_rect_width(&plane_state
->src
)) {
3050 scaler_id
= plane_state
->scaler_id
;
3051 src_x
= plane_state
->src
.x1
>> 16;
3052 src_y
= plane_state
->src
.y1
>> 16;
3053 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3054 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3055 dst_x
= plane_state
->dst
.x1
;
3056 dst_y
= plane_state
->dst
.y1
;
3057 dst_w
= drm_rect_width(&plane_state
->dst
);
3058 dst_h
= drm_rect_height(&plane_state
->dst
);
3060 WARN_ON(x
!= src_x
|| y
!= src_y
);
3062 src_w
= intel_crtc
->config
->pipe_src_w
;
3063 src_h
= intel_crtc
->config
->pipe_src_h
;
3066 if (intel_rotation_90_or_270(rotation
)) {
3067 /* stride = Surface height in tiles */
3068 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3070 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3071 x_offset
= stride
* tile_height
- y
- src_h
;
3073 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3075 stride
= fb
->pitches
[0] / stride_div
;
3078 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3080 plane_offset
= y_offset
<< 16 | x_offset
;
3082 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3083 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3084 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3085 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3087 if (scaler_id
>= 0) {
3088 uint32_t ps_ctrl
= 0;
3090 WARN_ON(!dst_w
|| !dst_h
);
3091 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3092 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3093 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3094 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3095 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3096 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3097 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3099 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3102 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3104 POSTING_READ(PLANE_SURF(pipe
, 0));
3107 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3109 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3110 int x
, int y
, enum mode_set_atomic state
)
3112 struct drm_device
*dev
= crtc
->dev
;
3113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3115 if (dev_priv
->fbc
.disable_fbc
)
3116 dev_priv
->fbc
.disable_fbc(dev_priv
);
3118 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3123 static void intel_complete_page_flips(struct drm_device
*dev
)
3125 struct drm_crtc
*crtc
;
3127 for_each_crtc(dev
, crtc
) {
3128 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3129 enum plane plane
= intel_crtc
->plane
;
3131 intel_prepare_page_flip(dev
, plane
);
3132 intel_finish_page_flip_plane(dev
, plane
);
3136 static void intel_update_primary_planes(struct drm_device
*dev
)
3138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3139 struct drm_crtc
*crtc
;
3141 for_each_crtc(dev
, crtc
) {
3142 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3144 drm_modeset_lock(&crtc
->mutex
, NULL
);
3146 * FIXME: Once we have proper support for primary planes (and
3147 * disabling them without disabling the entire crtc) allow again
3148 * a NULL crtc->primary->fb.
3150 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3151 dev_priv
->display
.update_primary_plane(crtc
,
3155 drm_modeset_unlock(&crtc
->mutex
);
3159 void intel_prepare_reset(struct drm_device
*dev
)
3161 /* no reset support for gen2 */
3165 /* reset doesn't touch the display */
3166 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3169 drm_modeset_lock_all(dev
);
3171 * Disabling the crtcs gracefully seems nicer. Also the
3172 * g33 docs say we should at least disable all the planes.
3174 intel_display_suspend(dev
);
3177 void intel_finish_reset(struct drm_device
*dev
)
3179 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3182 * Flips in the rings will be nuked by the reset,
3183 * so complete all pending flips so that user space
3184 * will get its events and not get stuck.
3186 intel_complete_page_flips(dev
);
3188 /* no reset support for gen2 */
3192 /* reset doesn't touch the display */
3193 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3195 * Flips in the rings have been nuked by the reset,
3196 * so update the base address of all primary
3197 * planes to the the last fb to make sure we're
3198 * showing the correct fb after a reset.
3200 intel_update_primary_planes(dev
);
3205 * The display has been reset as well,
3206 * so need a full re-initialization.
3208 intel_runtime_pm_disable_interrupts(dev_priv
);
3209 intel_runtime_pm_enable_interrupts(dev_priv
);
3211 intel_modeset_init_hw(dev
);
3213 spin_lock_irq(&dev_priv
->irq_lock
);
3214 if (dev_priv
->display
.hpd_irq_setup
)
3215 dev_priv
->display
.hpd_irq_setup(dev
);
3216 spin_unlock_irq(&dev_priv
->irq_lock
);
3218 intel_display_resume(dev
);
3220 intel_hpd_init(dev_priv
);
3222 drm_modeset_unlock_all(dev
);
3226 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3228 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3229 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3230 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3233 /* Big Hammer, we also need to ensure that any pending
3234 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3235 * current scanout is retired before unpinning the old
3236 * framebuffer. Note that we rely on userspace rendering
3237 * into the buffer attached to the pipe they are waiting
3238 * on. If not, userspace generates a GPU hang with IPEHR
3239 * point to the MI_WAIT_FOR_EVENT.
3241 * This should only fail upon a hung GPU, in which case we
3242 * can safely continue.
3244 dev_priv
->mm
.interruptible
= false;
3245 ret
= i915_gem_object_wait_rendering(obj
, true);
3246 dev_priv
->mm
.interruptible
= was_interruptible
;
3251 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3253 struct drm_device
*dev
= crtc
->dev
;
3254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3255 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3258 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3259 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3262 spin_lock_irq(&dev
->event_lock
);
3263 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3264 spin_unlock_irq(&dev
->event_lock
);
3269 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3271 struct drm_device
*dev
= crtc
->base
.dev
;
3272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3273 const struct drm_display_mode
*adjusted_mode
;
3279 * Update pipe size and adjust fitter if needed: the reason for this is
3280 * that in compute_mode_changes we check the native mode (not the pfit
3281 * mode) to see if we can flip rather than do a full mode set. In the
3282 * fastboot case, we'll flip, but if we don't update the pipesrc and
3283 * pfit state, we'll end up with a big fb scanned out into the wrong
3286 * To fix this properly, we need to hoist the checks up into
3287 * compute_mode_changes (or above), check the actual pfit state and
3288 * whether the platform allows pfit disable with pipe active, and only
3289 * then update the pipesrc and pfit state, even on the flip path.
3292 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3294 I915_WRITE(PIPESRC(crtc
->pipe
),
3295 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3296 (adjusted_mode
->crtc_vdisplay
- 1));
3297 if (!crtc
->config
->pch_pfit
.enabled
&&
3298 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3299 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3300 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3301 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3302 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3304 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3305 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3308 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3310 struct drm_device
*dev
= crtc
->dev
;
3311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3313 int pipe
= intel_crtc
->pipe
;
3316 /* enable normal train */
3317 reg
= FDI_TX_CTL(pipe
);
3318 temp
= I915_READ(reg
);
3319 if (IS_IVYBRIDGE(dev
)) {
3320 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3321 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3323 temp
&= ~FDI_LINK_TRAIN_NONE
;
3324 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3326 I915_WRITE(reg
, temp
);
3328 reg
= FDI_RX_CTL(pipe
);
3329 temp
= I915_READ(reg
);
3330 if (HAS_PCH_CPT(dev
)) {
3331 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3332 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3334 temp
&= ~FDI_LINK_TRAIN_NONE
;
3335 temp
|= FDI_LINK_TRAIN_NONE
;
3337 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3339 /* wait one idle pattern time */
3343 /* IVB wants error correction enabled */
3344 if (IS_IVYBRIDGE(dev
))
3345 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3346 FDI_FE_ERRC_ENABLE
);
3349 /* The FDI link training functions for ILK/Ibexpeak. */
3350 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3352 struct drm_device
*dev
= crtc
->dev
;
3353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3354 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3355 int pipe
= intel_crtc
->pipe
;
3356 u32 reg
, temp
, tries
;
3358 /* FDI needs bits from pipe first */
3359 assert_pipe_enabled(dev_priv
, pipe
);
3361 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3363 reg
= FDI_RX_IMR(pipe
);
3364 temp
= I915_READ(reg
);
3365 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3366 temp
&= ~FDI_RX_BIT_LOCK
;
3367 I915_WRITE(reg
, temp
);
3371 /* enable CPU FDI TX and PCH FDI RX */
3372 reg
= FDI_TX_CTL(pipe
);
3373 temp
= I915_READ(reg
);
3374 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3375 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3376 temp
&= ~FDI_LINK_TRAIN_NONE
;
3377 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3378 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3380 reg
= FDI_RX_CTL(pipe
);
3381 temp
= I915_READ(reg
);
3382 temp
&= ~FDI_LINK_TRAIN_NONE
;
3383 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3384 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3389 /* Ironlake workaround, enable clock pointer after FDI enable*/
3390 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3391 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3392 FDI_RX_PHASE_SYNC_POINTER_EN
);
3394 reg
= FDI_RX_IIR(pipe
);
3395 for (tries
= 0; tries
< 5; tries
++) {
3396 temp
= I915_READ(reg
);
3397 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3399 if ((temp
& FDI_RX_BIT_LOCK
)) {
3400 DRM_DEBUG_KMS("FDI train 1 done.\n");
3401 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3406 DRM_ERROR("FDI train 1 fail!\n");
3409 reg
= FDI_TX_CTL(pipe
);
3410 temp
= I915_READ(reg
);
3411 temp
&= ~FDI_LINK_TRAIN_NONE
;
3412 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3413 I915_WRITE(reg
, temp
);
3415 reg
= FDI_RX_CTL(pipe
);
3416 temp
= I915_READ(reg
);
3417 temp
&= ~FDI_LINK_TRAIN_NONE
;
3418 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3419 I915_WRITE(reg
, temp
);
3424 reg
= FDI_RX_IIR(pipe
);
3425 for (tries
= 0; tries
< 5; tries
++) {
3426 temp
= I915_READ(reg
);
3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3429 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3430 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3431 DRM_DEBUG_KMS("FDI train 2 done.\n");
3436 DRM_ERROR("FDI train 2 fail!\n");
3438 DRM_DEBUG_KMS("FDI train done\n");
3442 static const int snb_b_fdi_train_param
[] = {
3443 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3444 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3445 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3446 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3449 /* The FDI link training functions for SNB/Cougarpoint. */
3450 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3452 struct drm_device
*dev
= crtc
->dev
;
3453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3455 int pipe
= intel_crtc
->pipe
;
3456 u32 reg
, temp
, i
, retry
;
3458 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3460 reg
= FDI_RX_IMR(pipe
);
3461 temp
= I915_READ(reg
);
3462 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3463 temp
&= ~FDI_RX_BIT_LOCK
;
3464 I915_WRITE(reg
, temp
);
3469 /* enable CPU FDI TX and PCH FDI RX */
3470 reg
= FDI_TX_CTL(pipe
);
3471 temp
= I915_READ(reg
);
3472 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3473 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3474 temp
&= ~FDI_LINK_TRAIN_NONE
;
3475 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3476 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3478 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3479 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3481 I915_WRITE(FDI_RX_MISC(pipe
),
3482 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3484 reg
= FDI_RX_CTL(pipe
);
3485 temp
= I915_READ(reg
);
3486 if (HAS_PCH_CPT(dev
)) {
3487 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3488 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3490 temp
&= ~FDI_LINK_TRAIN_NONE
;
3491 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3493 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3498 for (i
= 0; i
< 4; i
++) {
3499 reg
= FDI_TX_CTL(pipe
);
3500 temp
= I915_READ(reg
);
3501 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3502 temp
|= snb_b_fdi_train_param
[i
];
3503 I915_WRITE(reg
, temp
);
3508 for (retry
= 0; retry
< 5; retry
++) {
3509 reg
= FDI_RX_IIR(pipe
);
3510 temp
= I915_READ(reg
);
3511 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3512 if (temp
& FDI_RX_BIT_LOCK
) {
3513 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3514 DRM_DEBUG_KMS("FDI train 1 done.\n");
3523 DRM_ERROR("FDI train 1 fail!\n");
3526 reg
= FDI_TX_CTL(pipe
);
3527 temp
= I915_READ(reg
);
3528 temp
&= ~FDI_LINK_TRAIN_NONE
;
3529 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3531 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3533 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3535 I915_WRITE(reg
, temp
);
3537 reg
= FDI_RX_CTL(pipe
);
3538 temp
= I915_READ(reg
);
3539 if (HAS_PCH_CPT(dev
)) {
3540 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3541 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3543 temp
&= ~FDI_LINK_TRAIN_NONE
;
3544 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3546 I915_WRITE(reg
, temp
);
3551 for (i
= 0; i
< 4; i
++) {
3552 reg
= FDI_TX_CTL(pipe
);
3553 temp
= I915_READ(reg
);
3554 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3555 temp
|= snb_b_fdi_train_param
[i
];
3556 I915_WRITE(reg
, temp
);
3561 for (retry
= 0; retry
< 5; retry
++) {
3562 reg
= FDI_RX_IIR(pipe
);
3563 temp
= I915_READ(reg
);
3564 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3565 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3566 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3567 DRM_DEBUG_KMS("FDI train 2 done.\n");
3576 DRM_ERROR("FDI train 2 fail!\n");
3578 DRM_DEBUG_KMS("FDI train done.\n");
3581 /* Manual link training for Ivy Bridge A0 parts */
3582 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3584 struct drm_device
*dev
= crtc
->dev
;
3585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3586 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3587 int pipe
= intel_crtc
->pipe
;
3588 u32 reg
, temp
, i
, j
;
3590 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3592 reg
= FDI_RX_IMR(pipe
);
3593 temp
= I915_READ(reg
);
3594 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3595 temp
&= ~FDI_RX_BIT_LOCK
;
3596 I915_WRITE(reg
, temp
);
3601 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3602 I915_READ(FDI_RX_IIR(pipe
)));
3604 /* Try each vswing and preemphasis setting twice before moving on */
3605 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3606 /* disable first in case we need to retry */
3607 reg
= FDI_TX_CTL(pipe
);
3608 temp
= I915_READ(reg
);
3609 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3610 temp
&= ~FDI_TX_ENABLE
;
3611 I915_WRITE(reg
, temp
);
3613 reg
= FDI_RX_CTL(pipe
);
3614 temp
= I915_READ(reg
);
3615 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3616 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3617 temp
&= ~FDI_RX_ENABLE
;
3618 I915_WRITE(reg
, temp
);
3620 /* enable CPU FDI TX and PCH FDI RX */
3621 reg
= FDI_TX_CTL(pipe
);
3622 temp
= I915_READ(reg
);
3623 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3624 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3625 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3626 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3627 temp
|= snb_b_fdi_train_param
[j
/2];
3628 temp
|= FDI_COMPOSITE_SYNC
;
3629 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3631 I915_WRITE(FDI_RX_MISC(pipe
),
3632 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3634 reg
= FDI_RX_CTL(pipe
);
3635 temp
= I915_READ(reg
);
3636 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3637 temp
|= FDI_COMPOSITE_SYNC
;
3638 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3641 udelay(1); /* should be 0.5us */
3643 for (i
= 0; i
< 4; i
++) {
3644 reg
= FDI_RX_IIR(pipe
);
3645 temp
= I915_READ(reg
);
3646 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3648 if (temp
& FDI_RX_BIT_LOCK
||
3649 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3650 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3651 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3655 udelay(1); /* should be 0.5us */
3658 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3663 reg
= FDI_TX_CTL(pipe
);
3664 temp
= I915_READ(reg
);
3665 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3666 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3667 I915_WRITE(reg
, temp
);
3669 reg
= FDI_RX_CTL(pipe
);
3670 temp
= I915_READ(reg
);
3671 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3672 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3673 I915_WRITE(reg
, temp
);
3676 udelay(2); /* should be 1.5us */
3678 for (i
= 0; i
< 4; i
++) {
3679 reg
= FDI_RX_IIR(pipe
);
3680 temp
= I915_READ(reg
);
3681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3683 if (temp
& FDI_RX_SYMBOL_LOCK
||
3684 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3685 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3686 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3690 udelay(2); /* should be 1.5us */
3693 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3697 DRM_DEBUG_KMS("FDI train done.\n");
3700 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3702 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3704 int pipe
= intel_crtc
->pipe
;
3708 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3709 reg
= FDI_RX_CTL(pipe
);
3710 temp
= I915_READ(reg
);
3711 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3712 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3713 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3714 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3719 /* Switch from Rawclk to PCDclk */
3720 temp
= I915_READ(reg
);
3721 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3726 /* Enable CPU FDI TX PLL, always on for Ironlake */
3727 reg
= FDI_TX_CTL(pipe
);
3728 temp
= I915_READ(reg
);
3729 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3730 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3737 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3739 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3741 int pipe
= intel_crtc
->pipe
;
3744 /* Switch from PCDclk to Rawclk */
3745 reg
= FDI_RX_CTL(pipe
);
3746 temp
= I915_READ(reg
);
3747 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3749 /* Disable CPU FDI TX PLL */
3750 reg
= FDI_TX_CTL(pipe
);
3751 temp
= I915_READ(reg
);
3752 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3757 reg
= FDI_RX_CTL(pipe
);
3758 temp
= I915_READ(reg
);
3759 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3761 /* Wait for the clocks to turn off. */
3766 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3768 struct drm_device
*dev
= crtc
->dev
;
3769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3770 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3771 int pipe
= intel_crtc
->pipe
;
3774 /* disable CPU FDI tx and PCH FDI rx */
3775 reg
= FDI_TX_CTL(pipe
);
3776 temp
= I915_READ(reg
);
3777 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3780 reg
= FDI_RX_CTL(pipe
);
3781 temp
= I915_READ(reg
);
3782 temp
&= ~(0x7 << 16);
3783 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3784 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3789 /* Ironlake workaround, disable clock pointer after downing FDI */
3790 if (HAS_PCH_IBX(dev
))
3791 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3793 /* still set train pattern 1 */
3794 reg
= FDI_TX_CTL(pipe
);
3795 temp
= I915_READ(reg
);
3796 temp
&= ~FDI_LINK_TRAIN_NONE
;
3797 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3798 I915_WRITE(reg
, temp
);
3800 reg
= FDI_RX_CTL(pipe
);
3801 temp
= I915_READ(reg
);
3802 if (HAS_PCH_CPT(dev
)) {
3803 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3804 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3806 temp
&= ~FDI_LINK_TRAIN_NONE
;
3807 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3809 /* BPC in FDI rx is consistent with that in PIPECONF */
3810 temp
&= ~(0x07 << 16);
3811 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3812 I915_WRITE(reg
, temp
);
3818 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3820 struct intel_crtc
*crtc
;
3822 /* Note that we don't need to be called with mode_config.lock here
3823 * as our list of CRTC objects is static for the lifetime of the
3824 * device and so cannot disappear as we iterate. Similarly, we can
3825 * happily treat the predicates as racy, atomic checks as userspace
3826 * cannot claim and pin a new fb without at least acquring the
3827 * struct_mutex and so serialising with us.
3829 for_each_intel_crtc(dev
, crtc
) {
3830 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3833 if (crtc
->unpin_work
)
3834 intel_wait_for_vblank(dev
, crtc
->pipe
);
3842 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3844 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3845 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3847 /* ensure that the unpin work is consistent wrt ->pending. */
3849 intel_crtc
->unpin_work
= NULL
;
3852 drm_send_vblank_event(intel_crtc
->base
.dev
,
3856 drm_crtc_vblank_put(&intel_crtc
->base
);
3858 wake_up_all(&dev_priv
->pending_flip_queue
);
3859 queue_work(dev_priv
->wq
, &work
->work
);
3861 trace_i915_flip_complete(intel_crtc
->plane
,
3862 work
->pending_flip_obj
);
3865 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3867 struct drm_device
*dev
= crtc
->dev
;
3868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3870 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3871 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3872 !intel_crtc_has_pending_flip(crtc
),
3874 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3876 spin_lock_irq(&dev
->event_lock
);
3877 if (intel_crtc
->unpin_work
) {
3878 WARN_ONCE(1, "Removing stuck page flip\n");
3879 page_flip_completed(intel_crtc
);
3881 spin_unlock_irq(&dev
->event_lock
);
3884 if (crtc
->primary
->fb
) {
3885 mutex_lock(&dev
->struct_mutex
);
3886 intel_finish_fb(crtc
->primary
->fb
);
3887 mutex_unlock(&dev
->struct_mutex
);
3891 /* Program iCLKIP clock to the desired frequency */
3892 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3894 struct drm_device
*dev
= crtc
->dev
;
3895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3896 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3897 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3900 mutex_lock(&dev_priv
->sb_lock
);
3902 /* It is necessary to ungate the pixclk gate prior to programming
3903 * the divisors, and gate it back when it is done.
3905 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3907 /* Disable SSCCTL */
3908 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3909 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3913 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3914 if (clock
== 20000) {
3919 /* The iCLK virtual clock root frequency is in MHz,
3920 * but the adjusted_mode->crtc_clock in in KHz. To get the
3921 * divisors, it is necessary to divide one by another, so we
3922 * convert the virtual clock precision to KHz here for higher
3925 u32 iclk_virtual_root_freq
= 172800 * 1000;
3926 u32 iclk_pi_range
= 64;
3927 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3929 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3930 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3931 pi_value
= desired_divisor
% iclk_pi_range
;
3934 divsel
= msb_divisor_value
- 2;
3935 phaseinc
= pi_value
;
3938 /* This should not happen with any sane values */
3939 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3940 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3941 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3942 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3944 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3951 /* Program SSCDIVINTPHASE6 */
3952 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3953 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3954 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3955 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3956 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3957 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3958 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3959 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3961 /* Program SSCAUXDIV */
3962 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3963 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3964 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3965 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3967 /* Enable modulator and associated divider */
3968 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3969 temp
&= ~SBI_SSCCTL_DISABLE
;
3970 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3972 /* Wait for initialization time */
3975 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3977 mutex_unlock(&dev_priv
->sb_lock
);
3980 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3981 enum pipe pch_transcoder
)
3983 struct drm_device
*dev
= crtc
->base
.dev
;
3984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3985 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3987 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3988 I915_READ(HTOTAL(cpu_transcoder
)));
3989 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3990 I915_READ(HBLANK(cpu_transcoder
)));
3991 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3992 I915_READ(HSYNC(cpu_transcoder
)));
3994 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3995 I915_READ(VTOTAL(cpu_transcoder
)));
3996 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3997 I915_READ(VBLANK(cpu_transcoder
)));
3998 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3999 I915_READ(VSYNC(cpu_transcoder
)));
4000 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4001 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4004 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4009 temp
= I915_READ(SOUTH_CHICKEN1
);
4010 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4013 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4014 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4016 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4018 temp
|= FDI_BC_BIFURCATION_SELECT
;
4020 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4021 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4022 POSTING_READ(SOUTH_CHICKEN1
);
4025 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4027 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4029 switch (intel_crtc
->pipe
) {
4033 if (intel_crtc
->config
->fdi_lanes
> 2)
4034 cpt_set_fdi_bc_bifurcation(dev
, false);
4036 cpt_set_fdi_bc_bifurcation(dev
, true);
4040 cpt_set_fdi_bc_bifurcation(dev
, true);
4049 * Enable PCH resources required for PCH ports:
4051 * - FDI training & RX/TX
4052 * - update transcoder timings
4053 * - DP transcoding bits
4056 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4058 struct drm_device
*dev
= crtc
->dev
;
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4061 int pipe
= intel_crtc
->pipe
;
4064 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4066 if (IS_IVYBRIDGE(dev
))
4067 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4069 /* Write the TU size bits before fdi link training, so that error
4070 * detection works. */
4071 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4072 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4074 /* For PCH output, training FDI link */
4075 dev_priv
->display
.fdi_link_train(crtc
);
4077 /* We need to program the right clock selection before writing the pixel
4078 * mutliplier into the DPLL. */
4079 if (HAS_PCH_CPT(dev
)) {
4082 temp
= I915_READ(PCH_DPLL_SEL
);
4083 temp
|= TRANS_DPLL_ENABLE(pipe
);
4084 sel
= TRANS_DPLLB_SEL(pipe
);
4085 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4089 I915_WRITE(PCH_DPLL_SEL
, temp
);
4092 /* XXX: pch pll's can be enabled any time before we enable the PCH
4093 * transcoder, and we actually should do this to not upset any PCH
4094 * transcoder that already use the clock when we share it.
4096 * Note that enable_shared_dpll tries to do the right thing, but
4097 * get_shared_dpll unconditionally resets the pll - we need that to have
4098 * the right LVDS enable sequence. */
4099 intel_enable_shared_dpll(intel_crtc
);
4101 /* set transcoder timing, panel must allow it */
4102 assert_panel_unlocked(dev_priv
, pipe
);
4103 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4105 intel_fdi_normal_train(crtc
);
4107 /* For PCH DP, enable TRANS_DP_CTL */
4108 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4109 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4110 reg
= TRANS_DP_CTL(pipe
);
4111 temp
= I915_READ(reg
);
4112 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4113 TRANS_DP_SYNC_MASK
|
4115 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4116 temp
|= bpc
<< 9; /* same format but at 11:9 */
4118 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4119 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4120 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4121 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4123 switch (intel_trans_dp_port_sel(crtc
)) {
4125 temp
|= TRANS_DP_PORT_SEL_B
;
4128 temp
|= TRANS_DP_PORT_SEL_C
;
4131 temp
|= TRANS_DP_PORT_SEL_D
;
4137 I915_WRITE(reg
, temp
);
4140 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4143 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4145 struct drm_device
*dev
= crtc
->dev
;
4146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4148 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4150 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4152 lpt_program_iclkip(crtc
);
4154 /* Set transcoder timing. */
4155 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4157 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4160 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4161 struct intel_crtc_state
*crtc_state
)
4163 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4164 struct intel_shared_dpll
*pll
;
4165 struct intel_shared_dpll_config
*shared_dpll
;
4166 enum intel_dpll_id i
;
4168 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
4170 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4171 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4172 i
= (enum intel_dpll_id
) crtc
->pipe
;
4173 pll
= &dev_priv
->shared_dplls
[i
];
4175 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4176 crtc
->base
.base
.id
, pll
->name
);
4178 WARN_ON(shared_dpll
[i
].crtc_mask
);
4183 if (IS_BROXTON(dev_priv
->dev
)) {
4184 /* PLL is attached to port in bxt */
4185 struct intel_encoder
*encoder
;
4186 struct intel_digital_port
*intel_dig_port
;
4188 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4189 if (WARN_ON(!encoder
))
4192 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4193 /* 1:1 mapping between ports and PLLs */
4194 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4195 pll
= &dev_priv
->shared_dplls
[i
];
4196 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4197 crtc
->base
.base
.id
, pll
->name
);
4198 WARN_ON(shared_dpll
[i
].crtc_mask
);
4203 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4204 pll
= &dev_priv
->shared_dplls
[i
];
4206 /* Only want to check enabled timings first */
4207 if (shared_dpll
[i
].crtc_mask
== 0)
4210 if (memcmp(&crtc_state
->dpll_hw_state
,
4211 &shared_dpll
[i
].hw_state
,
4212 sizeof(crtc_state
->dpll_hw_state
)) == 0) {
4213 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4214 crtc
->base
.base
.id
, pll
->name
,
4215 shared_dpll
[i
].crtc_mask
,
4221 /* Ok no matching timings, maybe there's a free one? */
4222 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4223 pll
= &dev_priv
->shared_dplls
[i
];
4224 if (shared_dpll
[i
].crtc_mask
== 0) {
4225 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4226 crtc
->base
.base
.id
, pll
->name
);
4234 if (shared_dpll
[i
].crtc_mask
== 0)
4235 shared_dpll
[i
].hw_state
=
4236 crtc_state
->dpll_hw_state
;
4238 crtc_state
->shared_dpll
= i
;
4239 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4240 pipe_name(crtc
->pipe
));
4242 shared_dpll
[i
].crtc_mask
|= 1 << crtc
->pipe
;
4247 static void intel_shared_dpll_commit(struct drm_atomic_state
*state
)
4249 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
4250 struct intel_shared_dpll_config
*shared_dpll
;
4251 struct intel_shared_dpll
*pll
;
4252 enum intel_dpll_id i
;
4254 if (!to_intel_atomic_state(state
)->dpll_set
)
4257 shared_dpll
= to_intel_atomic_state(state
)->shared_dpll
;
4258 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4259 pll
= &dev_priv
->shared_dplls
[i
];
4260 pll
->config
= shared_dpll
[i
];
4264 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4267 int dslreg
= PIPEDSL(pipe
);
4270 temp
= I915_READ(dslreg
);
4272 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4273 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4274 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4279 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4280 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4281 int src_w
, int src_h
, int dst_w
, int dst_h
)
4283 struct intel_crtc_scaler_state
*scaler_state
=
4284 &crtc_state
->scaler_state
;
4285 struct intel_crtc
*intel_crtc
=
4286 to_intel_crtc(crtc_state
->base
.crtc
);
4289 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4290 (src_h
!= dst_w
|| src_w
!= dst_h
):
4291 (src_w
!= dst_w
|| src_h
!= dst_h
);
4294 * if plane is being disabled or scaler is no more required or force detach
4295 * - free scaler binded to this plane/crtc
4296 * - in order to do this, update crtc->scaler_usage
4298 * Here scaler state in crtc_state is set free so that
4299 * scaler can be assigned to other user. Actual register
4300 * update to free the scaler is done in plane/panel-fit programming.
4301 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4303 if (force_detach
|| !need_scaling
) {
4304 if (*scaler_id
>= 0) {
4305 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4306 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4308 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4309 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4310 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4311 scaler_state
->scaler_users
);
4318 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4319 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4321 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4322 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4323 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4324 "size is out of scaler range\n",
4325 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4329 /* mark this plane as a scaler user in crtc_state */
4330 scaler_state
->scaler_users
|= (1 << scaler_user
);
4331 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4332 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4333 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4334 scaler_state
->scaler_users
);
4340 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4342 * @state: crtc's scaler state
4345 * 0 - scaler_usage updated successfully
4346 * error - requested scaling cannot be supported or other error condition
4348 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4350 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4351 struct drm_display_mode
*adjusted_mode
=
4352 &state
->base
.adjusted_mode
;
4354 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4355 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4357 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4358 &state
->scaler_state
.scaler_id
, DRM_ROTATE_0
,
4359 state
->pipe_src_w
, state
->pipe_src_h
,
4360 adjusted_mode
->hdisplay
, adjusted_mode
->vdisplay
);
4364 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4366 * @state: crtc's scaler state
4367 * @plane_state: atomic plane state to update
4370 * 0 - scaler_usage updated successfully
4371 * error - requested scaling cannot be supported or other error condition
4373 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4374 struct intel_plane_state
*plane_state
)
4377 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4378 struct intel_plane
*intel_plane
=
4379 to_intel_plane(plane_state
->base
.plane
);
4380 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4383 bool force_detach
= !fb
|| !plane_state
->visible
;
4385 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4386 intel_plane
->base
.base
.id
, intel_crtc
->pipe
,
4387 drm_plane_index(&intel_plane
->base
));
4389 ret
= skl_update_scaler(crtc_state
, force_detach
,
4390 drm_plane_index(&intel_plane
->base
),
4391 &plane_state
->scaler_id
,
4392 plane_state
->base
.rotation
,
4393 drm_rect_width(&plane_state
->src
) >> 16,
4394 drm_rect_height(&plane_state
->src
) >> 16,
4395 drm_rect_width(&plane_state
->dst
),
4396 drm_rect_height(&plane_state
->dst
));
4398 if (ret
|| plane_state
->scaler_id
< 0)
4401 /* check colorkey */
4402 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4403 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4404 intel_plane
->base
.base
.id
);
4408 /* Check src format */
4409 switch (fb
->pixel_format
) {
4410 case DRM_FORMAT_RGB565
:
4411 case DRM_FORMAT_XBGR8888
:
4412 case DRM_FORMAT_XRGB8888
:
4413 case DRM_FORMAT_ABGR8888
:
4414 case DRM_FORMAT_ARGB8888
:
4415 case DRM_FORMAT_XRGB2101010
:
4416 case DRM_FORMAT_XBGR2101010
:
4417 case DRM_FORMAT_YUYV
:
4418 case DRM_FORMAT_YVYU
:
4419 case DRM_FORMAT_UYVY
:
4420 case DRM_FORMAT_VYUY
:
4423 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4424 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4431 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4435 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4436 skl_detach_scaler(crtc
, i
);
4439 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4441 struct drm_device
*dev
= crtc
->base
.dev
;
4442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4443 int pipe
= crtc
->pipe
;
4444 struct intel_crtc_scaler_state
*scaler_state
=
4445 &crtc
->config
->scaler_state
;
4447 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4449 if (crtc
->config
->pch_pfit
.enabled
) {
4452 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4453 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4457 id
= scaler_state
->scaler_id
;
4458 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4459 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4460 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4461 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4463 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4467 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4469 struct drm_device
*dev
= crtc
->base
.dev
;
4470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4471 int pipe
= crtc
->pipe
;
4473 if (crtc
->config
->pch_pfit
.enabled
) {
4474 /* Force use of hard-coded filter coefficients
4475 * as some pre-programmed values are broken,
4478 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4479 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4480 PF_PIPE_SEL_IVB(pipe
));
4482 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4483 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4484 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4488 void hsw_enable_ips(struct intel_crtc
*crtc
)
4490 struct drm_device
*dev
= crtc
->base
.dev
;
4491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4493 if (!crtc
->config
->ips_enabled
)
4496 /* We can only enable IPS after we enable a plane and wait for a vblank */
4497 intel_wait_for_vblank(dev
, crtc
->pipe
);
4499 assert_plane_enabled(dev_priv
, crtc
->plane
);
4500 if (IS_BROADWELL(dev
)) {
4501 mutex_lock(&dev_priv
->rps
.hw_lock
);
4502 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4503 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4504 /* Quoting Art Runyan: "its not safe to expect any particular
4505 * value in IPS_CTL bit 31 after enabling IPS through the
4506 * mailbox." Moreover, the mailbox may return a bogus state,
4507 * so we need to just enable it and continue on.
4510 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4511 /* The bit only becomes 1 in the next vblank, so this wait here
4512 * is essentially intel_wait_for_vblank. If we don't have this
4513 * and don't wait for vblanks until the end of crtc_enable, then
4514 * the HW state readout code will complain that the expected
4515 * IPS_CTL value is not the one we read. */
4516 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4517 DRM_ERROR("Timed out waiting for IPS enable\n");
4521 void hsw_disable_ips(struct intel_crtc
*crtc
)
4523 struct drm_device
*dev
= crtc
->base
.dev
;
4524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4526 if (!crtc
->config
->ips_enabled
)
4529 assert_plane_enabled(dev_priv
, crtc
->plane
);
4530 if (IS_BROADWELL(dev
)) {
4531 mutex_lock(&dev_priv
->rps
.hw_lock
);
4532 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4533 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4534 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4535 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4536 DRM_ERROR("Timed out waiting for IPS disable\n");
4538 I915_WRITE(IPS_CTL
, 0);
4539 POSTING_READ(IPS_CTL
);
4542 /* We need to wait for a vblank before we can disable the plane. */
4543 intel_wait_for_vblank(dev
, crtc
->pipe
);
4546 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4547 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4549 struct drm_device
*dev
= crtc
->dev
;
4550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4551 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4552 enum pipe pipe
= intel_crtc
->pipe
;
4553 int palreg
= PALETTE(pipe
);
4555 bool reenable_ips
= false;
4557 /* The clocks have to be on to load the palette. */
4558 if (!crtc
->state
->active
)
4561 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4562 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4563 assert_dsi_pll_enabled(dev_priv
);
4565 assert_pll_enabled(dev_priv
, pipe
);
4568 /* use legacy palette for Ironlake */
4569 if (!HAS_GMCH_DISPLAY(dev
))
4570 palreg
= LGC_PALETTE(pipe
);
4572 /* Workaround : Do not read or write the pipe palette/gamma data while
4573 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4575 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4576 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4577 GAMMA_MODE_MODE_SPLIT
)) {
4578 hsw_disable_ips(intel_crtc
);
4579 reenable_ips
= true;
4582 for (i
= 0; i
< 256; i
++) {
4583 I915_WRITE(palreg
+ 4 * i
,
4584 (intel_crtc
->lut_r
[i
] << 16) |
4585 (intel_crtc
->lut_g
[i
] << 8) |
4586 intel_crtc
->lut_b
[i
]);
4590 hsw_enable_ips(intel_crtc
);
4593 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4595 if (intel_crtc
->overlay
) {
4596 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4599 mutex_lock(&dev
->struct_mutex
);
4600 dev_priv
->mm
.interruptible
= false;
4601 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4602 dev_priv
->mm
.interruptible
= true;
4603 mutex_unlock(&dev
->struct_mutex
);
4606 /* Let userspace switch the overlay on again. In most cases userspace
4607 * has to recompute where to put it anyway.
4612 * intel_post_enable_primary - Perform operations after enabling primary plane
4613 * @crtc: the CRTC whose primary plane was just enabled
4615 * Performs potentially sleeping operations that must be done after the primary
4616 * plane is enabled, such as updating FBC and IPS. Note that this may be
4617 * called due to an explicit primary plane update, or due to an implicit
4618 * re-enable that is caused when a sprite plane is updated to no longer
4619 * completely hide the primary plane.
4622 intel_post_enable_primary(struct drm_crtc
*crtc
)
4624 struct drm_device
*dev
= crtc
->dev
;
4625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4627 int pipe
= intel_crtc
->pipe
;
4630 * BDW signals flip done immediately if the plane
4631 * is disabled, even if the plane enable is already
4632 * armed to occur at the next vblank :(
4634 if (IS_BROADWELL(dev
))
4635 intel_wait_for_vblank(dev
, pipe
);
4638 * FIXME IPS should be fine as long as one plane is
4639 * enabled, but in practice it seems to have problems
4640 * when going from primary only to sprite only and vice
4643 hsw_enable_ips(intel_crtc
);
4646 * Gen2 reports pipe underruns whenever all planes are disabled.
4647 * So don't enable underrun reporting before at least some planes
4649 * FIXME: Need to fix the logic to work when we turn off all planes
4650 * but leave the pipe running.
4653 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4655 /* Underruns don't raise interrupts, so check manually. */
4656 if (HAS_GMCH_DISPLAY(dev
))
4657 i9xx_check_fifo_underruns(dev_priv
);
4661 * intel_pre_disable_primary - Perform operations before disabling primary plane
4662 * @crtc: the CRTC whose primary plane is to be disabled
4664 * Performs potentially sleeping operations that must be done before the
4665 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4666 * be called due to an explicit primary plane update, or due to an implicit
4667 * disable that is caused when a sprite plane completely hides the primary
4671 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4673 struct drm_device
*dev
= crtc
->dev
;
4674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4676 int pipe
= intel_crtc
->pipe
;
4679 * Gen2 reports pipe underruns whenever all planes are disabled.
4680 * So diasble underrun reporting before all the planes get disabled.
4681 * FIXME: Need to fix the logic to work when we turn off all planes
4682 * but leave the pipe running.
4685 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4688 * Vblank time updates from the shadow to live plane control register
4689 * are blocked if the memory self-refresh mode is active at that
4690 * moment. So to make sure the plane gets truly disabled, disable
4691 * first the self-refresh mode. The self-refresh enable bit in turn
4692 * will be checked/applied by the HW only at the next frame start
4693 * event which is after the vblank start event, so we need to have a
4694 * wait-for-vblank between disabling the plane and the pipe.
4696 if (HAS_GMCH_DISPLAY(dev
)) {
4697 intel_set_memory_cxsr(dev_priv
, false);
4698 dev_priv
->wm
.vlv
.cxsr
= false;
4699 intel_wait_for_vblank(dev
, pipe
);
4703 * FIXME IPS should be fine as long as one plane is
4704 * enabled, but in practice it seems to have problems
4705 * when going from primary only to sprite only and vice
4708 hsw_disable_ips(intel_crtc
);
4711 static void intel_post_plane_update(struct intel_crtc
*crtc
)
4713 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4714 struct drm_device
*dev
= crtc
->base
.dev
;
4715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4716 struct drm_plane
*plane
;
4718 if (atomic
->wait_vblank
)
4719 intel_wait_for_vblank(dev
, crtc
->pipe
);
4721 intel_frontbuffer_flip(dev
, atomic
->fb_bits
);
4723 if (atomic
->disable_cxsr
)
4724 crtc
->wm
.cxsr_allowed
= true;
4726 if (crtc
->atomic
.update_wm_post
)
4727 intel_update_watermarks(&crtc
->base
);
4729 if (atomic
->update_fbc
)
4730 intel_fbc_update(dev_priv
);
4732 if (atomic
->post_enable_primary
)
4733 intel_post_enable_primary(&crtc
->base
);
4735 drm_for_each_plane_mask(plane
, dev
, atomic
->update_sprite_watermarks
)
4736 intel_update_sprite_watermarks(plane
, &crtc
->base
,
4737 0, 0, 0, false, false);
4739 memset(atomic
, 0, sizeof(*atomic
));
4742 static void intel_pre_plane_update(struct intel_crtc
*crtc
)
4744 struct drm_device
*dev
= crtc
->base
.dev
;
4745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4746 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4747 struct drm_plane
*p
;
4749 /* Track fb's for any planes being disabled */
4750 drm_for_each_plane_mask(p
, dev
, atomic
->disabled_planes
) {
4751 struct intel_plane
*plane
= to_intel_plane(p
);
4753 mutex_lock(&dev
->struct_mutex
);
4754 i915_gem_track_fb(intel_fb_obj(plane
->base
.fb
), NULL
,
4755 plane
->frontbuffer_bit
);
4756 mutex_unlock(&dev
->struct_mutex
);
4759 if (atomic
->wait_for_flips
)
4760 intel_crtc_wait_for_pending_flips(&crtc
->base
);
4762 if (atomic
->disable_fbc
)
4763 intel_fbc_disable_crtc(crtc
);
4765 if (crtc
->atomic
.disable_ips
)
4766 hsw_disable_ips(crtc
);
4768 if (atomic
->pre_disable_primary
)
4769 intel_pre_disable_primary(&crtc
->base
);
4771 if (atomic
->disable_cxsr
) {
4772 crtc
->wm
.cxsr_allowed
= false;
4773 intel_set_memory_cxsr(dev_priv
, false);
4777 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4779 struct drm_device
*dev
= crtc
->dev
;
4780 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4781 struct drm_plane
*p
;
4782 int pipe
= intel_crtc
->pipe
;
4784 intel_crtc_dpms_overlay_disable(intel_crtc
);
4786 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4787 to_intel_plane(p
)->disable_plane(p
, crtc
);
4790 * FIXME: Once we grow proper nuclear flip support out of this we need
4791 * to compute the mask of flip planes precisely. For the time being
4792 * consider this a flip to a NULL plane.
4794 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4797 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4799 struct drm_device
*dev
= crtc
->dev
;
4800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4801 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4802 struct intel_encoder
*encoder
;
4803 int pipe
= intel_crtc
->pipe
;
4805 if (WARN_ON(intel_crtc
->active
))
4808 if (intel_crtc
->config
->has_pch_encoder
)
4809 intel_prepare_shared_dpll(intel_crtc
);
4811 if (intel_crtc
->config
->has_dp_encoder
)
4812 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4814 intel_set_pipe_timings(intel_crtc
);
4816 if (intel_crtc
->config
->has_pch_encoder
) {
4817 intel_cpu_transcoder_set_m_n(intel_crtc
,
4818 &intel_crtc
->config
->fdi_m_n
, NULL
);
4821 ironlake_set_pipeconf(crtc
);
4823 intel_crtc
->active
= true;
4825 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4826 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4828 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4829 if (encoder
->pre_enable
)
4830 encoder
->pre_enable(encoder
);
4832 if (intel_crtc
->config
->has_pch_encoder
) {
4833 /* Note: FDI PLL enabling _must_ be done before we enable the
4834 * cpu pipes, hence this is separate from all the other fdi/pch
4836 ironlake_fdi_pll_enable(intel_crtc
);
4838 assert_fdi_tx_disabled(dev_priv
, pipe
);
4839 assert_fdi_rx_disabled(dev_priv
, pipe
);
4842 ironlake_pfit_enable(intel_crtc
);
4845 * On ILK+ LUT must be loaded before the pipe is running but with
4848 intel_crtc_load_lut(crtc
);
4850 intel_update_watermarks(crtc
);
4851 intel_enable_pipe(intel_crtc
);
4853 if (intel_crtc
->config
->has_pch_encoder
)
4854 ironlake_pch_enable(crtc
);
4856 assert_vblank_disabled(crtc
);
4857 drm_crtc_vblank_on(crtc
);
4859 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4860 encoder
->enable(encoder
);
4862 if (HAS_PCH_CPT(dev
))
4863 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4866 /* IPS only exists on ULT machines and is tied to pipe A. */
4867 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4869 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4872 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4874 struct drm_device
*dev
= crtc
->dev
;
4875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4876 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4877 struct intel_encoder
*encoder
;
4878 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4879 struct intel_crtc_state
*pipe_config
=
4880 to_intel_crtc_state(crtc
->state
);
4882 if (WARN_ON(intel_crtc
->active
))
4885 if (intel_crtc_to_shared_dpll(intel_crtc
))
4886 intel_enable_shared_dpll(intel_crtc
);
4888 if (intel_crtc
->config
->has_dp_encoder
)
4889 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4891 intel_set_pipe_timings(intel_crtc
);
4893 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4894 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4895 intel_crtc
->config
->pixel_multiplier
- 1);
4898 if (intel_crtc
->config
->has_pch_encoder
) {
4899 intel_cpu_transcoder_set_m_n(intel_crtc
,
4900 &intel_crtc
->config
->fdi_m_n
, NULL
);
4903 haswell_set_pipeconf(crtc
);
4905 intel_set_pipe_csc(crtc
);
4907 intel_crtc
->active
= true;
4909 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4910 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4911 if (encoder
->pre_enable
)
4912 encoder
->pre_enable(encoder
);
4914 if (intel_crtc
->config
->has_pch_encoder
) {
4915 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4917 dev_priv
->display
.fdi_link_train(crtc
);
4920 intel_ddi_enable_pipe_clock(intel_crtc
);
4922 if (INTEL_INFO(dev
)->gen
>= 9)
4923 skylake_pfit_enable(intel_crtc
);
4925 ironlake_pfit_enable(intel_crtc
);
4928 * On ILK+ LUT must be loaded before the pipe is running but with
4931 intel_crtc_load_lut(crtc
);
4933 intel_ddi_set_pipe_settings(crtc
);
4934 intel_ddi_enable_transcoder_func(crtc
);
4936 intel_update_watermarks(crtc
);
4937 intel_enable_pipe(intel_crtc
);
4939 if (intel_crtc
->config
->has_pch_encoder
)
4940 lpt_pch_enable(crtc
);
4942 if (intel_crtc
->config
->dp_encoder_is_mst
)
4943 intel_ddi_set_vc_payload_alloc(crtc
, true);
4945 assert_vblank_disabled(crtc
);
4946 drm_crtc_vblank_on(crtc
);
4948 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4949 encoder
->enable(encoder
);
4950 intel_opregion_notify_encoder(encoder
, true);
4953 /* If we change the relative order between pipe/planes enabling, we need
4954 * to change the workaround. */
4955 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
4956 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
4957 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4958 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4962 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4964 struct drm_device
*dev
= crtc
->base
.dev
;
4965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4966 int pipe
= crtc
->pipe
;
4968 /* To avoid upsetting the power well on haswell only disable the pfit if
4969 * it's in use. The hw state code will make sure we get this right. */
4970 if (crtc
->config
->pch_pfit
.enabled
) {
4971 I915_WRITE(PF_CTL(pipe
), 0);
4972 I915_WRITE(PF_WIN_POS(pipe
), 0);
4973 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4977 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4979 struct drm_device
*dev
= crtc
->dev
;
4980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4982 struct intel_encoder
*encoder
;
4983 int pipe
= intel_crtc
->pipe
;
4986 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4987 encoder
->disable(encoder
);
4989 drm_crtc_vblank_off(crtc
);
4990 assert_vblank_disabled(crtc
);
4992 if (intel_crtc
->config
->has_pch_encoder
)
4993 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4995 intel_disable_pipe(intel_crtc
);
4997 ironlake_pfit_disable(intel_crtc
);
4999 if (intel_crtc
->config
->has_pch_encoder
)
5000 ironlake_fdi_disable(crtc
);
5002 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5003 if (encoder
->post_disable
)
5004 encoder
->post_disable(encoder
);
5006 if (intel_crtc
->config
->has_pch_encoder
) {
5007 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5009 if (HAS_PCH_CPT(dev
)) {
5010 /* disable TRANS_DP_CTL */
5011 reg
= TRANS_DP_CTL(pipe
);
5012 temp
= I915_READ(reg
);
5013 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5014 TRANS_DP_PORT_SEL_MASK
);
5015 temp
|= TRANS_DP_PORT_SEL_NONE
;
5016 I915_WRITE(reg
, temp
);
5018 /* disable DPLL_SEL */
5019 temp
= I915_READ(PCH_DPLL_SEL
);
5020 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5021 I915_WRITE(PCH_DPLL_SEL
, temp
);
5024 ironlake_fdi_pll_disable(intel_crtc
);
5027 intel_crtc
->active
= false;
5028 intel_update_watermarks(crtc
);
5031 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5033 struct drm_device
*dev
= crtc
->dev
;
5034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5035 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5036 struct intel_encoder
*encoder
;
5037 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5039 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5040 intel_opregion_notify_encoder(encoder
, false);
5041 encoder
->disable(encoder
);
5044 drm_crtc_vblank_off(crtc
);
5045 assert_vblank_disabled(crtc
);
5047 if (intel_crtc
->config
->has_pch_encoder
)
5048 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5050 intel_disable_pipe(intel_crtc
);
5052 if (intel_crtc
->config
->dp_encoder_is_mst
)
5053 intel_ddi_set_vc_payload_alloc(crtc
, false);
5055 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5057 if (INTEL_INFO(dev
)->gen
>= 9)
5058 skylake_scaler_disable(intel_crtc
);
5060 ironlake_pfit_disable(intel_crtc
);
5062 intel_ddi_disable_pipe_clock(intel_crtc
);
5064 if (intel_crtc
->config
->has_pch_encoder
) {
5065 lpt_disable_pch_transcoder(dev_priv
);
5066 intel_ddi_fdi_disable(crtc
);
5069 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5070 if (encoder
->post_disable
)
5071 encoder
->post_disable(encoder
);
5073 intel_crtc
->active
= false;
5074 intel_update_watermarks(crtc
);
5077 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5079 struct drm_device
*dev
= crtc
->base
.dev
;
5080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5081 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5083 if (!pipe_config
->gmch_pfit
.control
)
5087 * The panel fitter should only be adjusted whilst the pipe is disabled,
5088 * according to register description and PRM.
5090 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5091 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5093 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5094 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5096 /* Border color in case we don't scale up to the full screen. Black by
5097 * default, change to something else for debugging. */
5098 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5101 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5105 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5107 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5109 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5111 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5113 return POWER_DOMAIN_PORT_DDI_E_2_LANES
;
5116 return POWER_DOMAIN_PORT_OTHER
;
5120 #define for_each_power_domain(domain, mask) \
5121 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5122 if ((1 << (domain)) & (mask))
5124 enum intel_display_power_domain
5125 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5127 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5128 struct intel_digital_port
*intel_dig_port
;
5130 switch (intel_encoder
->type
) {
5131 case INTEL_OUTPUT_UNKNOWN
:
5132 /* Only DDI platforms should ever use this output type */
5133 WARN_ON_ONCE(!HAS_DDI(dev
));
5134 case INTEL_OUTPUT_DISPLAYPORT
:
5135 case INTEL_OUTPUT_HDMI
:
5136 case INTEL_OUTPUT_EDP
:
5137 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5138 return port_to_power_domain(intel_dig_port
->port
);
5139 case INTEL_OUTPUT_DP_MST
:
5140 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5141 return port_to_power_domain(intel_dig_port
->port
);
5142 case INTEL_OUTPUT_ANALOG
:
5143 return POWER_DOMAIN_PORT_CRT
;
5144 case INTEL_OUTPUT_DSI
:
5145 return POWER_DOMAIN_PORT_DSI
;
5147 return POWER_DOMAIN_PORT_OTHER
;
5151 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5153 struct drm_device
*dev
= crtc
->dev
;
5154 struct intel_encoder
*intel_encoder
;
5155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5156 enum pipe pipe
= intel_crtc
->pipe
;
5158 enum transcoder transcoder
;
5160 if (!crtc
->state
->active
)
5163 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5165 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5166 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5167 if (intel_crtc
->config
->pch_pfit
.enabled
||
5168 intel_crtc
->config
->pch_pfit
.force_thru
)
5169 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5171 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5172 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5177 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc
*crtc
)
5179 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5181 enum intel_display_power_domain domain
;
5182 unsigned long domains
, new_domains
, old_domains
;
5184 old_domains
= intel_crtc
->enabled_power_domains
;
5185 intel_crtc
->enabled_power_domains
= new_domains
= get_crtc_power_domains(crtc
);
5187 domains
= new_domains
& ~old_domains
;
5189 for_each_power_domain(domain
, domains
)
5190 intel_display_power_get(dev_priv
, domain
);
5192 return old_domains
& ~new_domains
;
5195 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5196 unsigned long domains
)
5198 enum intel_display_power_domain domain
;
5200 for_each_power_domain(domain
, domains
)
5201 intel_display_power_put(dev_priv
, domain
);
5204 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5206 struct drm_device
*dev
= state
->dev
;
5207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5208 unsigned long put_domains
[I915_MAX_PIPES
] = {};
5209 struct drm_crtc_state
*crtc_state
;
5210 struct drm_crtc
*crtc
;
5213 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5214 if (needs_modeset(crtc
->state
))
5215 put_domains
[to_intel_crtc(crtc
)->pipe
] =
5216 modeset_get_crtc_power_domains(crtc
);
5219 if (dev_priv
->display
.modeset_commit_cdclk
) {
5220 unsigned int cdclk
= to_intel_atomic_state(state
)->cdclk
;
5222 if (cdclk
!= dev_priv
->cdclk_freq
&&
5223 !WARN_ON(!state
->allow_modeset
))
5224 dev_priv
->display
.modeset_commit_cdclk(state
);
5227 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
5229 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
5232 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5234 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5236 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5237 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5238 return max_cdclk_freq
;
5239 else if (IS_CHERRYVIEW(dev_priv
))
5240 return max_cdclk_freq
*95/100;
5241 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5242 return 2*max_cdclk_freq
*90/100;
5244 return max_cdclk_freq
*90/100;
5247 static void intel_update_max_cdclk(struct drm_device
*dev
)
5249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5251 if (IS_SKYLAKE(dev
)) {
5252 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5254 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5255 dev_priv
->max_cdclk_freq
= 675000;
5256 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5257 dev_priv
->max_cdclk_freq
= 540000;
5258 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5259 dev_priv
->max_cdclk_freq
= 450000;
5261 dev_priv
->max_cdclk_freq
= 337500;
5262 } else if (IS_BROADWELL(dev
)) {
5264 * FIXME with extra cooling we can allow
5265 * 540 MHz for ULX and 675 Mhz for ULT.
5266 * How can we know if extra cooling is
5267 * available? PCI ID, VTB, something else?
5269 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5270 dev_priv
->max_cdclk_freq
= 450000;
5271 else if (IS_BDW_ULX(dev
))
5272 dev_priv
->max_cdclk_freq
= 450000;
5273 else if (IS_BDW_ULT(dev
))
5274 dev_priv
->max_cdclk_freq
= 540000;
5276 dev_priv
->max_cdclk_freq
= 675000;
5277 } else if (IS_CHERRYVIEW(dev
)) {
5278 dev_priv
->max_cdclk_freq
= 320000;
5279 } else if (IS_VALLEYVIEW(dev
)) {
5280 dev_priv
->max_cdclk_freq
= 400000;
5282 /* otherwise assume cdclk is fixed */
5283 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5286 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5288 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5289 dev_priv
->max_cdclk_freq
);
5291 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5292 dev_priv
->max_dotclk_freq
);
5295 static void intel_update_cdclk(struct drm_device
*dev
)
5297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5299 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5300 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5301 dev_priv
->cdclk_freq
);
5304 * Program the gmbus_freq based on the cdclk frequency.
5305 * BSpec erroneously claims we should aim for 4MHz, but
5306 * in fact 1MHz is the correct frequency.
5308 if (IS_VALLEYVIEW(dev
)) {
5310 * Program the gmbus_freq based on the cdclk frequency.
5311 * BSpec erroneously claims we should aim for 4MHz, but
5312 * in fact 1MHz is the correct frequency.
5314 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5317 if (dev_priv
->max_cdclk_freq
== 0)
5318 intel_update_max_cdclk(dev
);
5321 static void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5326 uint32_t current_freq
;
5329 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5330 switch (frequency
) {
5332 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5333 ratio
= BXT_DE_PLL_RATIO(60);
5336 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5337 ratio
= BXT_DE_PLL_RATIO(60);
5340 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5341 ratio
= BXT_DE_PLL_RATIO(60);
5344 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5345 ratio
= BXT_DE_PLL_RATIO(60);
5348 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5349 ratio
= BXT_DE_PLL_RATIO(65);
5353 * Bypass frequency with DE PLL disabled. Init ratio, divider
5354 * to suppress GCC warning.
5360 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5365 mutex_lock(&dev_priv
->rps
.hw_lock
);
5366 /* Inform power controller of upcoming frequency change */
5367 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5369 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5372 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5377 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5378 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5379 current_freq
= current_freq
* 500 + 1000;
5382 * DE PLL has to be disabled when
5383 * - setting to 19.2MHz (bypass, PLL isn't used)
5384 * - before setting to 624MHz (PLL needs toggling)
5385 * - before setting to any frequency from 624MHz (PLL needs toggling)
5387 if (frequency
== 19200 || frequency
== 624000 ||
5388 current_freq
== 624000) {
5389 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5391 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5393 DRM_ERROR("timout waiting for DE PLL unlock\n");
5396 if (frequency
!= 19200) {
5399 val
= I915_READ(BXT_DE_PLL_CTL
);
5400 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5402 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5404 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5406 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5407 DRM_ERROR("timeout waiting for DE PLL lock\n");
5409 val
= I915_READ(CDCLK_CTL
);
5410 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5413 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5416 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5417 if (frequency
>= 500000)
5418 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5420 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5421 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5422 val
|= (frequency
- 1000) / 500;
5423 I915_WRITE(CDCLK_CTL
, val
);
5426 mutex_lock(&dev_priv
->rps
.hw_lock
);
5427 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5428 DIV_ROUND_UP(frequency
, 25000));
5429 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5432 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5437 intel_update_cdclk(dev
);
5440 void broxton_init_cdclk(struct drm_device
*dev
)
5442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5446 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5447 * or else the reset will hang because there is no PCH to respond.
5448 * Move the handshake programming to initialization sequence.
5449 * Previously was left up to BIOS.
5451 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5452 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5453 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5455 /* Enable PG1 for cdclk */
5456 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5458 /* check if cd clock is enabled */
5459 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5460 DRM_DEBUG_KMS("Display already initialized\n");
5466 * - The initial CDCLK needs to be read from VBT.
5467 * Need to make this change after VBT has changes for BXT.
5468 * - check if setting the max (or any) cdclk freq is really necessary
5469 * here, it belongs to modeset time
5471 broxton_set_cdclk(dev
, 624000);
5473 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5474 POSTING_READ(DBUF_CTL
);
5478 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5479 DRM_ERROR("DBuf power enable timeout!\n");
5482 void broxton_uninit_cdclk(struct drm_device
*dev
)
5484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5486 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5487 POSTING_READ(DBUF_CTL
);
5491 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5492 DRM_ERROR("DBuf power disable timeout!\n");
5494 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5495 broxton_set_cdclk(dev
, 19200);
5497 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5500 static const struct skl_cdclk_entry
{
5503 } skl_cdclk_frequencies
[] = {
5504 { .freq
= 308570, .vco
= 8640 },
5505 { .freq
= 337500, .vco
= 8100 },
5506 { .freq
= 432000, .vco
= 8640 },
5507 { .freq
= 450000, .vco
= 8100 },
5508 { .freq
= 540000, .vco
= 8100 },
5509 { .freq
= 617140, .vco
= 8640 },
5510 { .freq
= 675000, .vco
= 8100 },
5513 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5515 return (freq
- 1000) / 500;
5518 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5522 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5523 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5525 if (e
->freq
== freq
)
5533 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5535 unsigned int min_freq
;
5538 /* select the minimum CDCLK before enabling DPLL 0 */
5539 val
= I915_READ(CDCLK_CTL
);
5540 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5541 val
|= CDCLK_FREQ_337_308
;
5543 if (required_vco
== 8640)
5548 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5550 I915_WRITE(CDCLK_CTL
, val
);
5551 POSTING_READ(CDCLK_CTL
);
5554 * We always enable DPLL0 with the lowest link rate possible, but still
5555 * taking into account the VCO required to operate the eDP panel at the
5556 * desired frequency. The usual DP link rates operate with a VCO of
5557 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5558 * The modeset code is responsible for the selection of the exact link
5559 * rate later on, with the constraint of choosing a frequency that
5560 * works with required_vco.
5562 val
= I915_READ(DPLL_CTRL1
);
5564 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5565 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5566 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5567 if (required_vco
== 8640)
5568 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5571 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5574 I915_WRITE(DPLL_CTRL1
, val
);
5575 POSTING_READ(DPLL_CTRL1
);
5577 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5579 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5580 DRM_ERROR("DPLL0 not locked\n");
5583 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5588 /* inform PCU we want to change CDCLK */
5589 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5590 mutex_lock(&dev_priv
->rps
.hw_lock
);
5591 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5592 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5594 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5597 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5601 for (i
= 0; i
< 15; i
++) {
5602 if (skl_cdclk_pcu_ready(dev_priv
))
5610 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5612 struct drm_device
*dev
= dev_priv
->dev
;
5613 u32 freq_select
, pcu_ack
;
5615 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5617 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5618 DRM_ERROR("failed to inform PCU about cdclk change\n");
5626 freq_select
= CDCLK_FREQ_450_432
;
5630 freq_select
= CDCLK_FREQ_540
;
5636 freq_select
= CDCLK_FREQ_337_308
;
5641 freq_select
= CDCLK_FREQ_675_617
;
5646 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5647 POSTING_READ(CDCLK_CTL
);
5649 /* inform PCU of the change */
5650 mutex_lock(&dev_priv
->rps
.hw_lock
);
5651 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5652 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5654 intel_update_cdclk(dev
);
5657 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5659 /* disable DBUF power */
5660 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5661 POSTING_READ(DBUF_CTL
);
5665 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5666 DRM_ERROR("DBuf power disable timeout\n");
5669 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5670 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5671 DRM_ERROR("Couldn't disable DPLL0\n");
5673 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5676 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5679 unsigned int required_vco
;
5681 /* enable PCH reset handshake */
5682 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5683 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
5685 /* enable PG1 and Misc I/O */
5686 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5688 /* DPLL0 not enabled (happens on early BIOS versions) */
5689 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
)) {
5691 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5692 skl_dpll0_enable(dev_priv
, required_vco
);
5695 /* set CDCLK to the frequency the BIOS chose */
5696 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5698 /* enable DBUF power */
5699 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5700 POSTING_READ(DBUF_CTL
);
5704 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5705 DRM_ERROR("DBuf power enable timeout\n");
5708 /* returns HPLL frequency in kHz */
5709 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5711 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5713 /* Obtain SKU information */
5714 mutex_lock(&dev_priv
->sb_lock
);
5715 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5716 CCK_FUSE_HPLL_FREQ_MASK
;
5717 mutex_unlock(&dev_priv
->sb_lock
);
5719 return vco_freq
[hpll_freq
] * 1000;
5722 /* Adjust CDclk dividers to allow high res or save power if possible */
5723 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5728 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5729 != dev_priv
->cdclk_freq
);
5731 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5733 else if (cdclk
== 266667)
5738 mutex_lock(&dev_priv
->rps
.hw_lock
);
5739 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5740 val
&= ~DSPFREQGUAR_MASK
;
5741 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5742 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5743 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5744 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5746 DRM_ERROR("timed out waiting for CDclk change\n");
5748 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5750 mutex_lock(&dev_priv
->sb_lock
);
5752 if (cdclk
== 400000) {
5755 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5757 /* adjust cdclk divider */
5758 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5759 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5761 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5763 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5764 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5766 DRM_ERROR("timed out waiting for CDclk change\n");
5769 /* adjust self-refresh exit latency value */
5770 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5774 * For high bandwidth configs, we set a higher latency in the bunit
5775 * so that the core display fetch happens in time to avoid underruns.
5777 if (cdclk
== 400000)
5778 val
|= 4500 / 250; /* 4.5 usec */
5780 val
|= 3000 / 250; /* 3.0 usec */
5781 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5783 mutex_unlock(&dev_priv
->sb_lock
);
5785 intel_update_cdclk(dev
);
5788 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5793 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5794 != dev_priv
->cdclk_freq
);
5803 MISSING_CASE(cdclk
);
5808 * Specs are full of misinformation, but testing on actual
5809 * hardware has shown that we just need to write the desired
5810 * CCK divider into the Punit register.
5812 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5814 mutex_lock(&dev_priv
->rps
.hw_lock
);
5815 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5816 val
&= ~DSPFREQGUAR_MASK_CHV
;
5817 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5818 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5819 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5820 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5822 DRM_ERROR("timed out waiting for CDclk change\n");
5824 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5826 intel_update_cdclk(dev
);
5829 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5832 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5833 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5836 * Really only a few cases to deal with, as only 4 CDclks are supported:
5839 * 320/333MHz (depends on HPLL freq)
5841 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5842 * of the lower bin and adjust if needed.
5844 * We seem to get an unstable or solid color picture at 200MHz.
5845 * Not sure what's wrong. For now use 200MHz only when all pipes
5848 if (!IS_CHERRYVIEW(dev_priv
) &&
5849 max_pixclk
> freq_320
*limit
/100)
5851 else if (max_pixclk
> 266667*limit
/100)
5853 else if (max_pixclk
> 0)
5859 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5864 * - remove the guardband, it's not needed on BXT
5865 * - set 19.2MHz bypass frequency if there are no active pipes
5867 if (max_pixclk
> 576000*9/10)
5869 else if (max_pixclk
> 384000*9/10)
5871 else if (max_pixclk
> 288000*9/10)
5873 else if (max_pixclk
> 144000*9/10)
5879 /* Compute the max pixel clock for new configuration. Uses atomic state if
5880 * that's non-NULL, look at current state otherwise. */
5881 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5882 struct drm_atomic_state
*state
)
5884 struct intel_crtc
*intel_crtc
;
5885 struct intel_crtc_state
*crtc_state
;
5888 for_each_intel_crtc(dev
, intel_crtc
) {
5889 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
5890 if (IS_ERR(crtc_state
))
5891 return PTR_ERR(crtc_state
);
5893 if (!crtc_state
->base
.enable
)
5896 max_pixclk
= max(max_pixclk
,
5897 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5903 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5905 struct drm_device
*dev
= state
->dev
;
5906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5907 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5912 to_intel_atomic_state(state
)->cdclk
=
5913 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5918 static int broxton_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5920 struct drm_device
*dev
= state
->dev
;
5921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5922 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5927 to_intel_atomic_state(state
)->cdclk
=
5928 broxton_calc_cdclk(dev_priv
, max_pixclk
);
5933 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5935 unsigned int credits
, default_credits
;
5937 if (IS_CHERRYVIEW(dev_priv
))
5938 default_credits
= PFI_CREDIT(12);
5940 default_credits
= PFI_CREDIT(8);
5942 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5943 /* CHV suggested value is 31 or 63 */
5944 if (IS_CHERRYVIEW(dev_priv
))
5945 credits
= PFI_CREDIT_63
;
5947 credits
= PFI_CREDIT(15);
5949 credits
= default_credits
;
5953 * WA - write default credits before re-programming
5954 * FIXME: should we also set the resend bit here?
5956 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5959 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5960 credits
| PFI_CREDIT_RESEND
);
5963 * FIXME is this guaranteed to clear
5964 * immediately or should we poll for it?
5966 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
5969 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
5971 struct drm_device
*dev
= old_state
->dev
;
5972 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
5973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5976 * FIXME: We can end up here with all power domains off, yet
5977 * with a CDCLK frequency other than the minimum. To account
5978 * for this take the PIPE-A power domain, which covers the HW
5979 * blocks needed for the following programming. This can be
5980 * removed once it's guaranteed that we get here either with
5981 * the minimum CDCLK set, or the required power domains
5984 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5986 if (IS_CHERRYVIEW(dev
))
5987 cherryview_set_cdclk(dev
, req_cdclk
);
5989 valleyview_set_cdclk(dev
, req_cdclk
);
5991 vlv_program_pfi_credits(dev_priv
);
5993 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5996 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5998 struct drm_device
*dev
= crtc
->dev
;
5999 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6000 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6001 struct intel_encoder
*encoder
;
6002 int pipe
= intel_crtc
->pipe
;
6005 if (WARN_ON(intel_crtc
->active
))
6008 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
6010 if (intel_crtc
->config
->has_dp_encoder
)
6011 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6013 intel_set_pipe_timings(intel_crtc
);
6015 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6018 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6019 I915_WRITE(CHV_CANVAS(pipe
), 0);
6022 i9xx_set_pipeconf(intel_crtc
);
6024 intel_crtc
->active
= true;
6026 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6028 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6029 if (encoder
->pre_pll_enable
)
6030 encoder
->pre_pll_enable(encoder
);
6033 if (IS_CHERRYVIEW(dev
)) {
6034 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6035 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6037 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6038 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6042 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6043 if (encoder
->pre_enable
)
6044 encoder
->pre_enable(encoder
);
6046 i9xx_pfit_enable(intel_crtc
);
6048 intel_crtc_load_lut(crtc
);
6050 intel_enable_pipe(intel_crtc
);
6052 assert_vblank_disabled(crtc
);
6053 drm_crtc_vblank_on(crtc
);
6055 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6056 encoder
->enable(encoder
);
6059 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6061 struct drm_device
*dev
= crtc
->base
.dev
;
6062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6064 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6065 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6068 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6070 struct drm_device
*dev
= crtc
->dev
;
6071 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6072 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6073 struct intel_encoder
*encoder
;
6074 int pipe
= intel_crtc
->pipe
;
6076 if (WARN_ON(intel_crtc
->active
))
6079 i9xx_set_pll_dividers(intel_crtc
);
6081 if (intel_crtc
->config
->has_dp_encoder
)
6082 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6084 intel_set_pipe_timings(intel_crtc
);
6086 i9xx_set_pipeconf(intel_crtc
);
6088 intel_crtc
->active
= true;
6091 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6093 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6094 if (encoder
->pre_enable
)
6095 encoder
->pre_enable(encoder
);
6097 i9xx_enable_pll(intel_crtc
);
6099 i9xx_pfit_enable(intel_crtc
);
6101 intel_crtc_load_lut(crtc
);
6103 intel_update_watermarks(crtc
);
6104 intel_enable_pipe(intel_crtc
);
6106 assert_vblank_disabled(crtc
);
6107 drm_crtc_vblank_on(crtc
);
6109 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6110 encoder
->enable(encoder
);
6113 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6115 struct drm_device
*dev
= crtc
->base
.dev
;
6116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6118 if (!crtc
->config
->gmch_pfit
.control
)
6121 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6123 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6124 I915_READ(PFIT_CONTROL
));
6125 I915_WRITE(PFIT_CONTROL
, 0);
6128 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6130 struct drm_device
*dev
= crtc
->dev
;
6131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6133 struct intel_encoder
*encoder
;
6134 int pipe
= intel_crtc
->pipe
;
6137 * On gen2 planes are double buffered but the pipe isn't, so we must
6138 * wait for planes to fully turn off before disabling the pipe.
6139 * We also need to wait on all gmch platforms because of the
6140 * self-refresh mode constraint explained above.
6142 intel_wait_for_vblank(dev
, pipe
);
6144 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6145 encoder
->disable(encoder
);
6147 drm_crtc_vblank_off(crtc
);
6148 assert_vblank_disabled(crtc
);
6150 intel_disable_pipe(intel_crtc
);
6152 i9xx_pfit_disable(intel_crtc
);
6154 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6155 if (encoder
->post_disable
)
6156 encoder
->post_disable(encoder
);
6158 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6159 if (IS_CHERRYVIEW(dev
))
6160 chv_disable_pll(dev_priv
, pipe
);
6161 else if (IS_VALLEYVIEW(dev
))
6162 vlv_disable_pll(dev_priv
, pipe
);
6164 i9xx_disable_pll(intel_crtc
);
6167 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6168 if (encoder
->post_pll_disable
)
6169 encoder
->post_pll_disable(encoder
);
6172 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6174 intel_crtc
->active
= false;
6175 intel_update_watermarks(crtc
);
6178 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6181 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6182 enum intel_display_power_domain domain
;
6183 unsigned long domains
;
6185 if (!intel_crtc
->active
)
6188 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6189 intel_crtc_wait_for_pending_flips(crtc
);
6190 intel_pre_disable_primary(crtc
);
6193 intel_crtc_disable_planes(crtc
, crtc
->state
->plane_mask
);
6194 dev_priv
->display
.crtc_disable(crtc
);
6195 intel_disable_shared_dpll(intel_crtc
);
6197 domains
= intel_crtc
->enabled_power_domains
;
6198 for_each_power_domain(domain
, domains
)
6199 intel_display_power_put(dev_priv
, domain
);
6200 intel_crtc
->enabled_power_domains
= 0;
6204 * turn all crtc's off, but do not adjust state
6205 * This has to be paired with a call to intel_modeset_setup_hw_state.
6207 int intel_display_suspend(struct drm_device
*dev
)
6209 struct drm_mode_config
*config
= &dev
->mode_config
;
6210 struct drm_modeset_acquire_ctx
*ctx
= config
->acquire_ctx
;
6211 struct drm_atomic_state
*state
;
6212 struct drm_crtc
*crtc
;
6213 unsigned crtc_mask
= 0;
6219 lockdep_assert_held(&ctx
->ww_ctx
);
6220 state
= drm_atomic_state_alloc(dev
);
6221 if (WARN_ON(!state
))
6224 state
->acquire_ctx
= ctx
;
6225 state
->allow_modeset
= true;
6227 for_each_crtc(dev
, crtc
) {
6228 struct drm_crtc_state
*crtc_state
=
6229 drm_atomic_get_crtc_state(state
, crtc
);
6231 ret
= PTR_ERR_OR_ZERO(crtc_state
);
6235 if (!crtc_state
->active
)
6238 crtc_state
->active
= false;
6239 crtc_mask
|= 1 << drm_crtc_index(crtc
);
6243 ret
= drm_atomic_commit(state
);
6246 for_each_crtc(dev
, crtc
)
6247 if (crtc_mask
& (1 << drm_crtc_index(crtc
)))
6248 crtc
->state
->active
= true;
6256 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6257 drm_atomic_state_free(state
);
6261 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6263 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6265 drm_encoder_cleanup(encoder
);
6266 kfree(intel_encoder
);
6269 /* Cross check the actual hw state with our own modeset state tracking (and it's
6270 * internal consistency). */
6271 static void intel_connector_check_state(struct intel_connector
*connector
)
6273 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6275 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6276 connector
->base
.base
.id
,
6277 connector
->base
.name
);
6279 if (connector
->get_hw_state(connector
)) {
6280 struct drm_encoder
*encoder
= &connector
->encoder
->base
;
6281 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6283 I915_STATE_WARN(!crtc
,
6284 "connector enabled without attached crtc\n");
6289 I915_STATE_WARN(!crtc
->state
->active
,
6290 "connector is active, but attached crtc isn't\n");
6295 I915_STATE_WARN(conn_state
->best_encoder
!= encoder
,
6296 "atomic encoder doesn't match attached encoder\n");
6298 I915_STATE_WARN(conn_state
->crtc
!= encoder
->crtc
,
6299 "attached encoder crtc differs from connector crtc\n");
6301 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6302 "attached crtc is active, but connector isn't\n");
6303 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6304 "best encoder set without crtc!\n");
6308 int intel_connector_init(struct intel_connector
*connector
)
6310 struct drm_connector_state
*connector_state
;
6312 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6313 if (!connector_state
)
6316 connector
->base
.state
= connector_state
;
6320 struct intel_connector
*intel_connector_alloc(void)
6322 struct intel_connector
*connector
;
6324 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6328 if (intel_connector_init(connector
) < 0) {
6336 /* Simple connector->get_hw_state implementation for encoders that support only
6337 * one connector and no cloning and hence the encoder state determines the state
6338 * of the connector. */
6339 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6342 struct intel_encoder
*encoder
= connector
->encoder
;
6344 return encoder
->get_hw_state(encoder
, &pipe
);
6347 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6349 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6350 return crtc_state
->fdi_lanes
;
6355 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6356 struct intel_crtc_state
*pipe_config
)
6358 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6359 struct intel_crtc
*other_crtc
;
6360 struct intel_crtc_state
*other_crtc_state
;
6362 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6363 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6364 if (pipe_config
->fdi_lanes
> 4) {
6365 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6366 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6370 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6371 if (pipe_config
->fdi_lanes
> 2) {
6372 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6373 pipe_config
->fdi_lanes
);
6380 if (INTEL_INFO(dev
)->num_pipes
== 2)
6383 /* Ivybridge 3 pipe is really complicated */
6388 if (pipe_config
->fdi_lanes
<= 2)
6391 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6393 intel_atomic_get_crtc_state(state
, other_crtc
);
6394 if (IS_ERR(other_crtc_state
))
6395 return PTR_ERR(other_crtc_state
);
6397 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6398 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6399 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6404 if (pipe_config
->fdi_lanes
> 2) {
6405 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6406 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6410 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6412 intel_atomic_get_crtc_state(state
, other_crtc
);
6413 if (IS_ERR(other_crtc_state
))
6414 return PTR_ERR(other_crtc_state
);
6416 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6417 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6427 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6428 struct intel_crtc_state
*pipe_config
)
6430 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6431 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6432 int lane
, link_bw
, fdi_dotclock
, ret
;
6433 bool needs_recompute
= false;
6436 /* FDI is a binary signal running at ~2.7GHz, encoding
6437 * each output octet as 10 bits. The actual frequency
6438 * is stored as a divider into a 100MHz clock, and the
6439 * mode pixel clock is stored in units of 1KHz.
6440 * Hence the bw of each lane in terms of the mode signal
6443 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6445 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6447 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6448 pipe_config
->pipe_bpp
);
6450 pipe_config
->fdi_lanes
= lane
;
6452 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6453 link_bw
, &pipe_config
->fdi_m_n
);
6455 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6456 intel_crtc
->pipe
, pipe_config
);
6457 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6458 pipe_config
->pipe_bpp
-= 2*3;
6459 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6460 pipe_config
->pipe_bpp
);
6461 needs_recompute
= true;
6462 pipe_config
->bw_constrained
= true;
6467 if (needs_recompute
)
6473 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6474 struct intel_crtc_state
*pipe_config
)
6476 if (pipe_config
->pipe_bpp
> 24)
6479 /* HSW can handle pixel rate up to cdclk? */
6480 if (IS_HASWELL(dev_priv
->dev
))
6484 * We compare against max which means we must take
6485 * the increased cdclk requirement into account when
6486 * calculating the new cdclk.
6488 * Should measure whether using a lower cdclk w/o IPS
6490 return ilk_pipe_pixel_rate(pipe_config
) <=
6491 dev_priv
->max_cdclk_freq
* 95 / 100;
6494 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6495 struct intel_crtc_state
*pipe_config
)
6497 struct drm_device
*dev
= crtc
->base
.dev
;
6498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6500 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6501 hsw_crtc_supports_ips(crtc
) &&
6502 pipe_config_supports_ips(dev_priv
, pipe_config
);
6505 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6506 struct intel_crtc_state
*pipe_config
)
6508 struct drm_device
*dev
= crtc
->base
.dev
;
6509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6510 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6512 /* FIXME should check pixel clock limits on all platforms */
6513 if (INTEL_INFO(dev
)->gen
< 4) {
6514 int clock_limit
= dev_priv
->max_cdclk_freq
;
6517 * Enable pixel doubling when the dot clock
6518 * is > 90% of the (display) core speed.
6520 * GDG double wide on either pipe,
6521 * otherwise pipe A only.
6523 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6524 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6526 pipe_config
->double_wide
= true;
6529 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6534 * Pipe horizontal size must be even in:
6536 * - LVDS dual channel mode
6537 * - Double wide pipe
6539 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6540 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6541 pipe_config
->pipe_src_w
&= ~1;
6543 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6544 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6546 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6547 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6551 hsw_compute_ips_config(crtc
, pipe_config
);
6553 if (pipe_config
->has_pch_encoder
)
6554 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6559 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6561 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6562 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6563 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6566 if (!(lcpll1
& LCPLL_PLL_ENABLE
))
6567 return 24000; /* 24MHz is the cd freq with NSSC ref */
6569 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6572 linkrate
= (I915_READ(DPLL_CTRL1
) &
6573 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6575 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6576 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6578 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6579 case CDCLK_FREQ_450_432
:
6581 case CDCLK_FREQ_337_308
:
6583 case CDCLK_FREQ_675_617
:
6586 WARN(1, "Unknown cd freq selection\n");
6590 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6591 case CDCLK_FREQ_450_432
:
6593 case CDCLK_FREQ_337_308
:
6595 case CDCLK_FREQ_675_617
:
6598 WARN(1, "Unknown cd freq selection\n");
6602 /* error case, do as if DPLL0 isn't enabled */
6606 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6608 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6609 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6610 uint32_t pll_ratio
= I915_READ(BXT_DE_PLL_CTL
) & BXT_DE_PLL_RATIO_MASK
;
6611 uint32_t pll_enab
= I915_READ(BXT_DE_PLL_ENABLE
);
6614 if (!(pll_enab
& BXT_DE_PLL_PLL_ENABLE
))
6617 cdclk
= 19200 * pll_ratio
/ 2;
6619 switch (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) {
6620 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6621 return cdclk
; /* 576MHz or 624MHz */
6622 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6623 return cdclk
* 2 / 3; /* 384MHz */
6624 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6625 return cdclk
/ 2; /* 288MHz */
6626 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6627 return cdclk
/ 4; /* 144MHz */
6630 /* error case, do as if DE PLL isn't enabled */
6634 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6637 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6638 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6640 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6642 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6644 else if (freq
== LCPLL_CLK_FREQ_450
)
6646 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6648 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6654 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6657 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6658 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6660 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6662 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6664 else if (freq
== LCPLL_CLK_FREQ_450
)
6666 else if (IS_HSW_ULT(dev
))
6672 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6678 if (dev_priv
->hpll_freq
== 0)
6679 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6681 mutex_lock(&dev_priv
->sb_lock
);
6682 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6683 mutex_unlock(&dev_priv
->sb_lock
);
6685 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6687 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6688 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6689 "cdclk change in progress\n");
6691 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6694 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6699 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6704 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6709 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6714 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6718 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6720 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6721 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6723 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6725 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6727 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6730 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6731 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6733 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6738 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6742 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6744 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6747 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6748 case GC_DISPLAY_CLOCK_333_MHZ
:
6751 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6757 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6762 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6767 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6768 * encoding is different :(
6769 * FIXME is this the right way to detect 852GM/852GMV?
6771 if (dev
->pdev
->revision
== 0x1)
6774 pci_bus_read_config_word(dev
->pdev
->bus
,
6775 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6777 /* Assume that the hardware is in the high speed state. This
6778 * should be the default.
6780 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6781 case GC_CLOCK_133_200
:
6782 case GC_CLOCK_133_200_2
:
6783 case GC_CLOCK_100_200
:
6785 case GC_CLOCK_166_250
:
6787 case GC_CLOCK_100_133
:
6789 case GC_CLOCK_133_266
:
6790 case GC_CLOCK_133_266_2
:
6791 case GC_CLOCK_166_266
:
6795 /* Shouldn't happen */
6799 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6804 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6807 static const unsigned int blb_vco
[8] = {
6814 static const unsigned int pnv_vco
[8] = {
6821 static const unsigned int cl_vco
[8] = {
6830 static const unsigned int elk_vco
[8] = {
6836 static const unsigned int ctg_vco
[8] = {
6844 const unsigned int *vco_table
;
6848 /* FIXME other chipsets? */
6850 vco_table
= ctg_vco
;
6851 else if (IS_G4X(dev
))
6852 vco_table
= elk_vco
;
6853 else if (IS_CRESTLINE(dev
))
6855 else if (IS_PINEVIEW(dev
))
6856 vco_table
= pnv_vco
;
6857 else if (IS_G33(dev
))
6858 vco_table
= blb_vco
;
6862 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6864 vco
= vco_table
[tmp
& 0x7];
6866 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6868 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6873 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
6875 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6878 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6880 cdclk_sel
= (tmp
>> 12) & 0x1;
6886 return cdclk_sel
? 333333 : 222222;
6888 return cdclk_sel
? 320000 : 228571;
6890 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
6895 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
6897 static const uint8_t div_3200
[] = { 16, 10, 8 };
6898 static const uint8_t div_4000
[] = { 20, 12, 10 };
6899 static const uint8_t div_5333
[] = { 24, 16, 14 };
6900 const uint8_t *div_table
;
6901 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6904 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6906 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
6908 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
6913 div_table
= div_3200
;
6916 div_table
= div_4000
;
6919 div_table
= div_5333
;
6925 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
6928 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
6932 static int g33_get_display_clock_speed(struct drm_device
*dev
)
6934 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
6935 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
6936 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
6937 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
6938 const uint8_t *div_table
;
6939 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6942 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6944 cdclk_sel
= (tmp
>> 4) & 0x7;
6946 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
6951 div_table
= div_3200
;
6954 div_table
= div_4000
;
6957 div_table
= div_4800
;
6960 div_table
= div_5333
;
6966 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
6969 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
6974 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6976 while (*num
> DATA_LINK_M_N_MASK
||
6977 *den
> DATA_LINK_M_N_MASK
) {
6983 static void compute_m_n(unsigned int m
, unsigned int n
,
6984 uint32_t *ret_m
, uint32_t *ret_n
)
6986 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6987 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6988 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6992 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6993 int pixel_clock
, int link_clock
,
6994 struct intel_link_m_n
*m_n
)
6998 compute_m_n(bits_per_pixel
* pixel_clock
,
6999 link_clock
* nlanes
* 8,
7000 &m_n
->gmch_m
, &m_n
->gmch_n
);
7002 compute_m_n(pixel_clock
, link_clock
,
7003 &m_n
->link_m
, &m_n
->link_n
);
7006 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7008 if (i915
.panel_use_ssc
>= 0)
7009 return i915
.panel_use_ssc
!= 0;
7010 return dev_priv
->vbt
.lvds_use_ssc
7011 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7014 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
7017 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
7018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7021 WARN_ON(!crtc_state
->base
.state
);
7023 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
7025 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7026 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7027 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7028 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7029 } else if (!IS_GEN2(dev
)) {
7038 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7040 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7043 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7045 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7048 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7049 struct intel_crtc_state
*crtc_state
,
7050 intel_clock_t
*reduced_clock
)
7052 struct drm_device
*dev
= crtc
->base
.dev
;
7055 if (IS_PINEVIEW(dev
)) {
7056 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7058 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7060 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7062 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7065 crtc_state
->dpll_hw_state
.fp0
= fp
;
7067 crtc
->lowfreq_avail
= false;
7068 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7070 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7071 crtc
->lowfreq_avail
= true;
7073 crtc_state
->dpll_hw_state
.fp1
= fp
;
7077 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7083 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7084 * and set it to a reasonable value instead.
7086 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7087 reg_val
&= 0xffffff00;
7088 reg_val
|= 0x00000030;
7089 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7091 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7092 reg_val
&= 0x8cffffff;
7093 reg_val
= 0x8c000000;
7094 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7096 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7097 reg_val
&= 0xffffff00;
7098 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7100 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7101 reg_val
&= 0x00ffffff;
7102 reg_val
|= 0xb0000000;
7103 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7106 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7107 struct intel_link_m_n
*m_n
)
7109 struct drm_device
*dev
= crtc
->base
.dev
;
7110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7111 int pipe
= crtc
->pipe
;
7113 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7114 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7115 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7116 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7119 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7120 struct intel_link_m_n
*m_n
,
7121 struct intel_link_m_n
*m2_n2
)
7123 struct drm_device
*dev
= crtc
->base
.dev
;
7124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7125 int pipe
= crtc
->pipe
;
7126 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7128 if (INTEL_INFO(dev
)->gen
>= 5) {
7129 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7130 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7131 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7132 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7133 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7134 * for gen < 8) and if DRRS is supported (to make sure the
7135 * registers are not unnecessarily accessed).
7137 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7138 crtc
->config
->has_drrs
) {
7139 I915_WRITE(PIPE_DATA_M2(transcoder
),
7140 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7141 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7142 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7143 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7146 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7147 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7148 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7149 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7153 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7155 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7158 dp_m_n
= &crtc
->config
->dp_m_n
;
7159 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7160 } else if (m_n
== M2_N2
) {
7163 * M2_N2 registers are not supported. Hence m2_n2 divider value
7164 * needs to be programmed into M1_N1.
7166 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7168 DRM_ERROR("Unsupported divider value\n");
7172 if (crtc
->config
->has_pch_encoder
)
7173 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7175 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7178 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7179 struct intel_crtc_state
*pipe_config
)
7184 * Enable DPIO clock input. We should never disable the reference
7185 * clock for pipe B, since VGA hotplug / manual detection depends
7188 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REF_CLK_ENABLE_VLV
|
7189 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_REF_CLK_VLV
;
7190 /* We should never disable this, set it here for state tracking */
7191 if (crtc
->pipe
== PIPE_B
)
7192 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7193 dpll
|= DPLL_VCO_ENABLE
;
7194 pipe_config
->dpll_hw_state
.dpll
= dpll
;
7196 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
7197 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7198 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
7201 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7202 const struct intel_crtc_state
*pipe_config
)
7204 struct drm_device
*dev
= crtc
->base
.dev
;
7205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7206 int pipe
= crtc
->pipe
;
7208 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7209 u32 coreclk
, reg_val
;
7211 mutex_lock(&dev_priv
->sb_lock
);
7213 bestn
= pipe_config
->dpll
.n
;
7214 bestm1
= pipe_config
->dpll
.m1
;
7215 bestm2
= pipe_config
->dpll
.m2
;
7216 bestp1
= pipe_config
->dpll
.p1
;
7217 bestp2
= pipe_config
->dpll
.p2
;
7219 /* See eDP HDMI DPIO driver vbios notes doc */
7221 /* PLL B needs special handling */
7223 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7225 /* Set up Tx target for periodic Rcomp update */
7226 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7228 /* Disable target IRef on PLL */
7229 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7230 reg_val
&= 0x00ffffff;
7231 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7233 /* Disable fast lock */
7234 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7236 /* Set idtafcrecal before PLL is enabled */
7237 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7238 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7239 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7240 mdiv
|= (1 << DPIO_K_SHIFT
);
7243 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7244 * but we don't support that).
7245 * Note: don't use the DAC post divider as it seems unstable.
7247 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7248 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7250 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7251 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7253 /* Set HBR and RBR LPF coefficients */
7254 if (pipe_config
->port_clock
== 162000 ||
7255 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7256 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7257 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7260 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7263 if (pipe_config
->has_dp_encoder
) {
7264 /* Use SSC source */
7266 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7269 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7271 } else { /* HDMI or VGA */
7272 /* Use bend source */
7274 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7277 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7281 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7282 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7283 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7284 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7285 coreclk
|= 0x01000000;
7286 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7288 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7289 mutex_unlock(&dev_priv
->sb_lock
);
7292 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7293 struct intel_crtc_state
*pipe_config
)
7295 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7296 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7298 if (crtc
->pipe
!= PIPE_A
)
7299 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7301 pipe_config
->dpll_hw_state
.dpll_md
=
7302 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7305 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7306 const struct intel_crtc_state
*pipe_config
)
7308 struct drm_device
*dev
= crtc
->base
.dev
;
7309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7310 int pipe
= crtc
->pipe
;
7311 int dpll_reg
= DPLL(crtc
->pipe
);
7312 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7313 u32 loopfilter
, tribuf_calcntr
;
7314 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7318 bestn
= pipe_config
->dpll
.n
;
7319 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7320 bestm1
= pipe_config
->dpll
.m1
;
7321 bestm2
= pipe_config
->dpll
.m2
>> 22;
7322 bestp1
= pipe_config
->dpll
.p1
;
7323 bestp2
= pipe_config
->dpll
.p2
;
7324 vco
= pipe_config
->dpll
.vco
;
7329 * Enable Refclk and SSC
7331 I915_WRITE(dpll_reg
,
7332 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7334 mutex_lock(&dev_priv
->sb_lock
);
7336 /* p1 and p2 divider */
7337 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7338 5 << DPIO_CHV_S1_DIV_SHIFT
|
7339 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7340 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7341 1 << DPIO_CHV_K_DIV_SHIFT
);
7343 /* Feedback post-divider - m2 */
7344 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7346 /* Feedback refclk divider - n and m1 */
7347 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7348 DPIO_CHV_M1_DIV_BY_2
|
7349 1 << DPIO_CHV_N_DIV_SHIFT
);
7351 /* M2 fraction division */
7352 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7354 /* M2 fraction division enable */
7355 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7356 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7357 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7359 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7360 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7362 /* Program digital lock detect threshold */
7363 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7364 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7365 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7366 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7368 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7369 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7372 if (vco
== 5400000) {
7373 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7374 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7375 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7376 tribuf_calcntr
= 0x9;
7377 } else if (vco
<= 6200000) {
7378 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7379 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7380 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7381 tribuf_calcntr
= 0x9;
7382 } else if (vco
<= 6480000) {
7383 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7384 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7385 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7386 tribuf_calcntr
= 0x8;
7388 /* Not supported. Apply the same limits as in the max case */
7389 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7390 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7391 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7394 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7396 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7397 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7398 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7399 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7402 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7403 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7406 mutex_unlock(&dev_priv
->sb_lock
);
7410 * vlv_force_pll_on - forcibly enable just the PLL
7411 * @dev_priv: i915 private structure
7412 * @pipe: pipe PLL to enable
7413 * @dpll: PLL configuration
7415 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7416 * in cases where we need the PLL enabled even when @pipe is not going to
7419 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7420 const struct dpll
*dpll
)
7422 struct intel_crtc
*crtc
=
7423 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7424 struct intel_crtc_state pipe_config
= {
7425 .base
.crtc
= &crtc
->base
,
7426 .pixel_multiplier
= 1,
7430 if (IS_CHERRYVIEW(dev
)) {
7431 chv_compute_dpll(crtc
, &pipe_config
);
7432 chv_prepare_pll(crtc
, &pipe_config
);
7433 chv_enable_pll(crtc
, &pipe_config
);
7435 vlv_compute_dpll(crtc
, &pipe_config
);
7436 vlv_prepare_pll(crtc
, &pipe_config
);
7437 vlv_enable_pll(crtc
, &pipe_config
);
7442 * vlv_force_pll_off - forcibly disable just the PLL
7443 * @dev_priv: i915 private structure
7444 * @pipe: pipe PLL to disable
7446 * Disable the PLL for @pipe. To be used in cases where we need
7447 * the PLL enabled even when @pipe is not going to be enabled.
7449 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7451 if (IS_CHERRYVIEW(dev
))
7452 chv_disable_pll(to_i915(dev
), pipe
);
7454 vlv_disable_pll(to_i915(dev
), pipe
);
7457 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7458 struct intel_crtc_state
*crtc_state
,
7459 intel_clock_t
*reduced_clock
,
7462 struct drm_device
*dev
= crtc
->base
.dev
;
7463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7466 struct dpll
*clock
= &crtc_state
->dpll
;
7468 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7470 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7471 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7473 dpll
= DPLL_VGA_MODE_DIS
;
7475 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7476 dpll
|= DPLLB_MODE_LVDS
;
7478 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7480 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7481 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7482 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7486 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7488 if (crtc_state
->has_dp_encoder
)
7489 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7491 /* compute bitmask from p1 value */
7492 if (IS_PINEVIEW(dev
))
7493 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7495 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7496 if (IS_G4X(dev
) && reduced_clock
)
7497 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7499 switch (clock
->p2
) {
7501 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7504 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7507 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7510 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7513 if (INTEL_INFO(dev
)->gen
>= 4)
7514 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7516 if (crtc_state
->sdvo_tv_clock
)
7517 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7518 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7519 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7520 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7522 dpll
|= PLL_REF_INPUT_DREFCLK
;
7524 dpll
|= DPLL_VCO_ENABLE
;
7525 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7527 if (INTEL_INFO(dev
)->gen
>= 4) {
7528 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7529 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7530 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7534 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7535 struct intel_crtc_state
*crtc_state
,
7536 intel_clock_t
*reduced_clock
,
7539 struct drm_device
*dev
= crtc
->base
.dev
;
7540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7542 struct dpll
*clock
= &crtc_state
->dpll
;
7544 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7546 dpll
= DPLL_VGA_MODE_DIS
;
7548 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7549 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7552 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7554 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7556 dpll
|= PLL_P2_DIVIDE_BY_4
;
7559 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7560 dpll
|= DPLL_DVO_2X_MODE
;
7562 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7563 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7564 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7566 dpll
|= PLL_REF_INPUT_DREFCLK
;
7568 dpll
|= DPLL_VCO_ENABLE
;
7569 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7572 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7574 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7576 enum pipe pipe
= intel_crtc
->pipe
;
7577 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7578 struct drm_display_mode
*adjusted_mode
=
7579 &intel_crtc
->config
->base
.adjusted_mode
;
7580 uint32_t crtc_vtotal
, crtc_vblank_end
;
7583 /* We need to be careful not to changed the adjusted mode, for otherwise
7584 * the hw state checker will get angry at the mismatch. */
7585 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7586 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7588 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7589 /* the chip adds 2 halflines automatically */
7591 crtc_vblank_end
-= 1;
7593 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7594 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7596 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7597 adjusted_mode
->crtc_htotal
/ 2;
7599 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7602 if (INTEL_INFO(dev
)->gen
> 3)
7603 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7605 I915_WRITE(HTOTAL(cpu_transcoder
),
7606 (adjusted_mode
->crtc_hdisplay
- 1) |
7607 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7608 I915_WRITE(HBLANK(cpu_transcoder
),
7609 (adjusted_mode
->crtc_hblank_start
- 1) |
7610 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7611 I915_WRITE(HSYNC(cpu_transcoder
),
7612 (adjusted_mode
->crtc_hsync_start
- 1) |
7613 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7615 I915_WRITE(VTOTAL(cpu_transcoder
),
7616 (adjusted_mode
->crtc_vdisplay
- 1) |
7617 ((crtc_vtotal
- 1) << 16));
7618 I915_WRITE(VBLANK(cpu_transcoder
),
7619 (adjusted_mode
->crtc_vblank_start
- 1) |
7620 ((crtc_vblank_end
- 1) << 16));
7621 I915_WRITE(VSYNC(cpu_transcoder
),
7622 (adjusted_mode
->crtc_vsync_start
- 1) |
7623 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7625 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7626 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7627 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7629 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7630 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7631 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7633 /* pipesrc controls the size that is scaled from, which should
7634 * always be the user's requested size.
7636 I915_WRITE(PIPESRC(pipe
),
7637 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7638 (intel_crtc
->config
->pipe_src_h
- 1));
7641 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7642 struct intel_crtc_state
*pipe_config
)
7644 struct drm_device
*dev
= crtc
->base
.dev
;
7645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7646 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7649 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7650 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7651 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7652 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7653 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7654 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7655 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7656 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7657 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7659 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7660 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7661 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7662 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7663 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7664 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7665 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7666 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7667 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7669 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7670 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7671 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7672 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7675 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7676 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7677 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7679 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7680 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7683 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7684 struct intel_crtc_state
*pipe_config
)
7686 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7687 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7688 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7689 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7691 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7692 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7693 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7694 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7696 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7697 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7699 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7700 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7702 mode
->hsync
= drm_mode_hsync(mode
);
7703 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7704 drm_mode_set_name(mode
);
7707 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7709 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7715 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7716 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7717 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7719 if (intel_crtc
->config
->double_wide
)
7720 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7722 /* only g4x and later have fancy bpc/dither controls */
7723 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7724 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7725 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7726 pipeconf
|= PIPECONF_DITHER_EN
|
7727 PIPECONF_DITHER_TYPE_SP
;
7729 switch (intel_crtc
->config
->pipe_bpp
) {
7731 pipeconf
|= PIPECONF_6BPC
;
7734 pipeconf
|= PIPECONF_8BPC
;
7737 pipeconf
|= PIPECONF_10BPC
;
7740 /* Case prevented by intel_choose_pipe_bpp_dither. */
7745 if (HAS_PIPE_CXSR(dev
)) {
7746 if (intel_crtc
->lowfreq_avail
) {
7747 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7748 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7750 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7754 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7755 if (INTEL_INFO(dev
)->gen
< 4 ||
7756 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7757 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7759 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7761 pipeconf
|= PIPECONF_PROGRESSIVE
;
7763 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7764 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7766 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7767 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7770 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7771 struct intel_crtc_state
*crtc_state
)
7773 struct drm_device
*dev
= crtc
->base
.dev
;
7774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7775 int refclk
, num_connectors
= 0;
7776 intel_clock_t clock
;
7778 bool is_dsi
= false;
7779 struct intel_encoder
*encoder
;
7780 const intel_limit_t
*limit
;
7781 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7782 struct drm_connector
*connector
;
7783 struct drm_connector_state
*connector_state
;
7786 memset(&crtc_state
->dpll_hw_state
, 0,
7787 sizeof(crtc_state
->dpll_hw_state
));
7789 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7790 if (connector_state
->crtc
!= &crtc
->base
)
7793 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7795 switch (encoder
->type
) {
7796 case INTEL_OUTPUT_DSI
:
7809 if (!crtc_state
->clock_set
) {
7810 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7813 * Returns a set of divisors for the desired target clock with
7814 * the given refclk, or FALSE. The returned values represent
7815 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7818 limit
= intel_limit(crtc_state
, refclk
);
7819 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7820 crtc_state
->port_clock
,
7821 refclk
, NULL
, &clock
);
7823 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7827 /* Compat-code for transition, will disappear. */
7828 crtc_state
->dpll
.n
= clock
.n
;
7829 crtc_state
->dpll
.m1
= clock
.m1
;
7830 crtc_state
->dpll
.m2
= clock
.m2
;
7831 crtc_state
->dpll
.p1
= clock
.p1
;
7832 crtc_state
->dpll
.p2
= clock
.p2
;
7836 i8xx_compute_dpll(crtc
, crtc_state
, NULL
,
7838 } else if (IS_CHERRYVIEW(dev
)) {
7839 chv_compute_dpll(crtc
, crtc_state
);
7840 } else if (IS_VALLEYVIEW(dev
)) {
7841 vlv_compute_dpll(crtc
, crtc_state
);
7843 i9xx_compute_dpll(crtc
, crtc_state
, NULL
,
7850 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7851 struct intel_crtc_state
*pipe_config
)
7853 struct drm_device
*dev
= crtc
->base
.dev
;
7854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7857 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7860 tmp
= I915_READ(PFIT_CONTROL
);
7861 if (!(tmp
& PFIT_ENABLE
))
7864 /* Check whether the pfit is attached to our pipe. */
7865 if (INTEL_INFO(dev
)->gen
< 4) {
7866 if (crtc
->pipe
!= PIPE_B
)
7869 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7873 pipe_config
->gmch_pfit
.control
= tmp
;
7874 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7875 if (INTEL_INFO(dev
)->gen
< 5)
7876 pipe_config
->gmch_pfit
.lvds_border_bits
=
7877 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7880 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7881 struct intel_crtc_state
*pipe_config
)
7883 struct drm_device
*dev
= crtc
->base
.dev
;
7884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7885 int pipe
= pipe_config
->cpu_transcoder
;
7886 intel_clock_t clock
;
7888 int refclk
= 100000;
7890 /* In case of MIPI DPLL will not even be used */
7891 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7894 mutex_lock(&dev_priv
->sb_lock
);
7895 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7896 mutex_unlock(&dev_priv
->sb_lock
);
7898 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7899 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7900 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7901 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7902 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7904 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
7908 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7909 struct intel_initial_plane_config
*plane_config
)
7911 struct drm_device
*dev
= crtc
->base
.dev
;
7912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7913 u32 val
, base
, offset
;
7914 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7915 int fourcc
, pixel_format
;
7916 unsigned int aligned_height
;
7917 struct drm_framebuffer
*fb
;
7918 struct intel_framebuffer
*intel_fb
;
7920 val
= I915_READ(DSPCNTR(plane
));
7921 if (!(val
& DISPLAY_PLANE_ENABLE
))
7924 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7926 DRM_DEBUG_KMS("failed to alloc fb\n");
7930 fb
= &intel_fb
->base
;
7932 if (INTEL_INFO(dev
)->gen
>= 4) {
7933 if (val
& DISPPLANE_TILED
) {
7934 plane_config
->tiling
= I915_TILING_X
;
7935 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7939 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7940 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7941 fb
->pixel_format
= fourcc
;
7942 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7944 if (INTEL_INFO(dev
)->gen
>= 4) {
7945 if (plane_config
->tiling
)
7946 offset
= I915_READ(DSPTILEOFF(plane
));
7948 offset
= I915_READ(DSPLINOFF(plane
));
7949 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7951 base
= I915_READ(DSPADDR(plane
));
7953 plane_config
->base
= base
;
7955 val
= I915_READ(PIPESRC(pipe
));
7956 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7957 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7959 val
= I915_READ(DSPSTRIDE(pipe
));
7960 fb
->pitches
[0] = val
& 0xffffffc0;
7962 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7966 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7968 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7969 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7970 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7971 plane_config
->size
);
7973 plane_config
->fb
= intel_fb
;
7976 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7977 struct intel_crtc_state
*pipe_config
)
7979 struct drm_device
*dev
= crtc
->base
.dev
;
7980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7981 int pipe
= pipe_config
->cpu_transcoder
;
7982 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7983 intel_clock_t clock
;
7984 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
7985 int refclk
= 100000;
7987 mutex_lock(&dev_priv
->sb_lock
);
7988 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7989 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7990 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7991 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7992 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7993 mutex_unlock(&dev_priv
->sb_lock
);
7995 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7996 clock
.m2
= (pll_dw0
& 0xff) << 22;
7997 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
7998 clock
.m2
|= pll_dw2
& 0x3fffff;
7999 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8000 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8001 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8003 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8006 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8007 struct intel_crtc_state
*pipe_config
)
8009 struct drm_device
*dev
= crtc
->base
.dev
;
8010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8013 if (!intel_display_power_is_enabled(dev_priv
,
8014 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8017 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8018 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8020 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8021 if (!(tmp
& PIPECONF_ENABLE
))
8024 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
8025 switch (tmp
& PIPECONF_BPC_MASK
) {
8027 pipe_config
->pipe_bpp
= 18;
8030 pipe_config
->pipe_bpp
= 24;
8032 case PIPECONF_10BPC
:
8033 pipe_config
->pipe_bpp
= 30;
8040 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8041 pipe_config
->limited_color_range
= true;
8043 if (INTEL_INFO(dev
)->gen
< 4)
8044 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8046 intel_get_pipe_timings(crtc
, pipe_config
);
8048 i9xx_get_pfit_config(crtc
, pipe_config
);
8050 if (INTEL_INFO(dev
)->gen
>= 4) {
8051 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8052 pipe_config
->pixel_multiplier
=
8053 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8054 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8055 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8056 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8057 tmp
= I915_READ(DPLL(crtc
->pipe
));
8058 pipe_config
->pixel_multiplier
=
8059 ((tmp
& SDVO_MULTIPLIER_MASK
)
8060 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8062 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8063 * port and will be fixed up in the encoder->get_config
8065 pipe_config
->pixel_multiplier
= 1;
8067 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8068 if (!IS_VALLEYVIEW(dev
)) {
8070 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8071 * on 830. Filter it out here so that we don't
8072 * report errors due to that.
8075 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8077 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8078 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8080 /* Mask out read-only status bits. */
8081 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8082 DPLL_PORTC_READY_MASK
|
8083 DPLL_PORTB_READY_MASK
);
8086 if (IS_CHERRYVIEW(dev
))
8087 chv_crtc_clock_get(crtc
, pipe_config
);
8088 else if (IS_VALLEYVIEW(dev
))
8089 vlv_crtc_clock_get(crtc
, pipe_config
);
8091 i9xx_crtc_clock_get(crtc
, pipe_config
);
8094 * Normally the dotclock is filled in by the encoder .get_config()
8095 * but in case the pipe is enabled w/o any ports we need a sane
8098 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8099 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8104 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8107 struct intel_encoder
*encoder
;
8109 bool has_lvds
= false;
8110 bool has_cpu_edp
= false;
8111 bool has_panel
= false;
8112 bool has_ck505
= false;
8113 bool can_ssc
= false;
8115 /* We need to take the global config into account */
8116 for_each_intel_encoder(dev
, encoder
) {
8117 switch (encoder
->type
) {
8118 case INTEL_OUTPUT_LVDS
:
8122 case INTEL_OUTPUT_EDP
:
8124 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8132 if (HAS_PCH_IBX(dev
)) {
8133 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8134 can_ssc
= has_ck505
;
8140 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8141 has_panel
, has_lvds
, has_ck505
);
8143 /* Ironlake: try to setup display ref clock before DPLL
8144 * enabling. This is only under driver's control after
8145 * PCH B stepping, previous chipset stepping should be
8146 * ignoring this setting.
8148 val
= I915_READ(PCH_DREF_CONTROL
);
8150 /* As we must carefully and slowly disable/enable each source in turn,
8151 * compute the final state we want first and check if we need to
8152 * make any changes at all.
8155 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8157 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8159 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8161 final
&= ~DREF_SSC_SOURCE_MASK
;
8162 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8163 final
&= ~DREF_SSC1_ENABLE
;
8166 final
|= DREF_SSC_SOURCE_ENABLE
;
8168 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8169 final
|= DREF_SSC1_ENABLE
;
8172 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8173 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8175 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8177 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8179 final
|= DREF_SSC_SOURCE_DISABLE
;
8180 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8186 /* Always enable nonspread source */
8187 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8190 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8192 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8195 val
&= ~DREF_SSC_SOURCE_MASK
;
8196 val
|= DREF_SSC_SOURCE_ENABLE
;
8198 /* SSC must be turned on before enabling the CPU output */
8199 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8200 DRM_DEBUG_KMS("Using SSC on panel\n");
8201 val
|= DREF_SSC1_ENABLE
;
8203 val
&= ~DREF_SSC1_ENABLE
;
8205 /* Get SSC going before enabling the outputs */
8206 I915_WRITE(PCH_DREF_CONTROL
, val
);
8207 POSTING_READ(PCH_DREF_CONTROL
);
8210 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8212 /* Enable CPU source on CPU attached eDP */
8214 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8215 DRM_DEBUG_KMS("Using SSC on eDP\n");
8216 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8218 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8220 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8222 I915_WRITE(PCH_DREF_CONTROL
, val
);
8223 POSTING_READ(PCH_DREF_CONTROL
);
8226 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8228 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8230 /* Turn off CPU output */
8231 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8233 I915_WRITE(PCH_DREF_CONTROL
, val
);
8234 POSTING_READ(PCH_DREF_CONTROL
);
8237 /* Turn off the SSC source */
8238 val
&= ~DREF_SSC_SOURCE_MASK
;
8239 val
|= DREF_SSC_SOURCE_DISABLE
;
8242 val
&= ~DREF_SSC1_ENABLE
;
8244 I915_WRITE(PCH_DREF_CONTROL
, val
);
8245 POSTING_READ(PCH_DREF_CONTROL
);
8249 BUG_ON(val
!= final
);
8252 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8256 tmp
= I915_READ(SOUTH_CHICKEN2
);
8257 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8258 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8260 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8261 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8262 DRM_ERROR("FDI mPHY reset assert timeout\n");
8264 tmp
= I915_READ(SOUTH_CHICKEN2
);
8265 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8266 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8268 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8269 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8270 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8273 /* WaMPhyProgramming:hsw */
8274 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8278 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8279 tmp
&= ~(0xFF << 24);
8280 tmp
|= (0x12 << 24);
8281 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8283 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8285 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8287 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8289 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8291 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8292 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8293 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8295 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8296 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8297 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8299 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8302 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8304 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8307 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8309 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8312 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8314 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8317 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8319 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8320 tmp
&= ~(0xFF << 16);
8321 tmp
|= (0x1C << 16);
8322 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8324 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8325 tmp
&= ~(0xFF << 16);
8326 tmp
|= (0x1C << 16);
8327 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8329 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8331 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8333 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8335 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8337 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8338 tmp
&= ~(0xF << 28);
8340 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8342 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8343 tmp
&= ~(0xF << 28);
8345 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8348 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8349 * Programming" based on the parameters passed:
8350 * - Sequence to enable CLKOUT_DP
8351 * - Sequence to enable CLKOUT_DP without spread
8352 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8354 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8360 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8362 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8365 mutex_lock(&dev_priv
->sb_lock
);
8367 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8368 tmp
&= ~SBI_SSCCTL_DISABLE
;
8369 tmp
|= SBI_SSCCTL_PATHALT
;
8370 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8375 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8376 tmp
&= ~SBI_SSCCTL_PATHALT
;
8377 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8380 lpt_reset_fdi_mphy(dev_priv
);
8381 lpt_program_fdi_mphy(dev_priv
);
8385 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8386 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8387 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8388 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8390 mutex_unlock(&dev_priv
->sb_lock
);
8393 /* Sequence to disable CLKOUT_DP */
8394 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8399 mutex_lock(&dev_priv
->sb_lock
);
8401 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8402 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8403 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8404 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8406 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8407 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8408 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8409 tmp
|= SBI_SSCCTL_PATHALT
;
8410 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8413 tmp
|= SBI_SSCCTL_DISABLE
;
8414 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8417 mutex_unlock(&dev_priv
->sb_lock
);
8420 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8422 struct intel_encoder
*encoder
;
8423 bool has_vga
= false;
8425 for_each_intel_encoder(dev
, encoder
) {
8426 switch (encoder
->type
) {
8427 case INTEL_OUTPUT_ANALOG
:
8436 lpt_enable_clkout_dp(dev
, true, true);
8438 lpt_disable_clkout_dp(dev
);
8442 * Initialize reference clocks when the driver loads
8444 void intel_init_pch_refclk(struct drm_device
*dev
)
8446 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8447 ironlake_init_pch_refclk(dev
);
8448 else if (HAS_PCH_LPT(dev
))
8449 lpt_init_pch_refclk(dev
);
8452 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8454 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8456 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8457 struct drm_connector
*connector
;
8458 struct drm_connector_state
*connector_state
;
8459 struct intel_encoder
*encoder
;
8460 int num_connectors
= 0, i
;
8461 bool is_lvds
= false;
8463 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8464 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8467 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8469 switch (encoder
->type
) {
8470 case INTEL_OUTPUT_LVDS
:
8479 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8480 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8481 dev_priv
->vbt
.lvds_ssc_freq
);
8482 return dev_priv
->vbt
.lvds_ssc_freq
;
8488 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8490 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8491 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8492 int pipe
= intel_crtc
->pipe
;
8497 switch (intel_crtc
->config
->pipe_bpp
) {
8499 val
|= PIPECONF_6BPC
;
8502 val
|= PIPECONF_8BPC
;
8505 val
|= PIPECONF_10BPC
;
8508 val
|= PIPECONF_12BPC
;
8511 /* Case prevented by intel_choose_pipe_bpp_dither. */
8515 if (intel_crtc
->config
->dither
)
8516 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8518 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8519 val
|= PIPECONF_INTERLACED_ILK
;
8521 val
|= PIPECONF_PROGRESSIVE
;
8523 if (intel_crtc
->config
->limited_color_range
)
8524 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8526 I915_WRITE(PIPECONF(pipe
), val
);
8527 POSTING_READ(PIPECONF(pipe
));
8531 * Set up the pipe CSC unit.
8533 * Currently only full range RGB to limited range RGB conversion
8534 * is supported, but eventually this should handle various
8535 * RGB<->YCbCr scenarios as well.
8537 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8539 struct drm_device
*dev
= crtc
->dev
;
8540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8541 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8542 int pipe
= intel_crtc
->pipe
;
8543 uint16_t coeff
= 0x7800; /* 1.0 */
8546 * TODO: Check what kind of values actually come out of the pipe
8547 * with these coeff/postoff values and adjust to get the best
8548 * accuracy. Perhaps we even need to take the bpc value into
8552 if (intel_crtc
->config
->limited_color_range
)
8553 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8556 * GY/GU and RY/RU should be the other way around according
8557 * to BSpec, but reality doesn't agree. Just set them up in
8558 * a way that results in the correct picture.
8560 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8561 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8563 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8564 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8566 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8567 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8569 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8570 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8571 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8573 if (INTEL_INFO(dev
)->gen
> 6) {
8574 uint16_t postoff
= 0;
8576 if (intel_crtc
->config
->limited_color_range
)
8577 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8579 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8580 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8581 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8583 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8585 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8587 if (intel_crtc
->config
->limited_color_range
)
8588 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8590 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8594 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8596 struct drm_device
*dev
= crtc
->dev
;
8597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8599 enum pipe pipe
= intel_crtc
->pipe
;
8600 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8605 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8606 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8608 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8609 val
|= PIPECONF_INTERLACED_ILK
;
8611 val
|= PIPECONF_PROGRESSIVE
;
8613 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8614 POSTING_READ(PIPECONF(cpu_transcoder
));
8616 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8617 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8619 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8622 switch (intel_crtc
->config
->pipe_bpp
) {
8624 val
|= PIPEMISC_DITHER_6_BPC
;
8627 val
|= PIPEMISC_DITHER_8_BPC
;
8630 val
|= PIPEMISC_DITHER_10_BPC
;
8633 val
|= PIPEMISC_DITHER_12_BPC
;
8636 /* Case prevented by pipe_config_set_bpp. */
8640 if (intel_crtc
->config
->dither
)
8641 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8643 I915_WRITE(PIPEMISC(pipe
), val
);
8647 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8648 struct intel_crtc_state
*crtc_state
,
8649 intel_clock_t
*clock
,
8650 bool *has_reduced_clock
,
8651 intel_clock_t
*reduced_clock
)
8653 struct drm_device
*dev
= crtc
->dev
;
8654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8656 const intel_limit_t
*limit
;
8659 refclk
= ironlake_get_refclk(crtc_state
);
8662 * Returns a set of divisors for the desired target clock with the given
8663 * refclk, or FALSE. The returned values represent the clock equation:
8664 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8666 limit
= intel_limit(crtc_state
, refclk
);
8667 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8668 crtc_state
->port_clock
,
8669 refclk
, NULL
, clock
);
8676 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8679 * Account for spread spectrum to avoid
8680 * oversubscribing the link. Max center spread
8681 * is 2.5%; use 5% for safety's sake.
8683 u32 bps
= target_clock
* bpp
* 21 / 20;
8684 return DIV_ROUND_UP(bps
, link_bw
* 8);
8687 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8689 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8692 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8693 struct intel_crtc_state
*crtc_state
,
8695 intel_clock_t
*reduced_clock
, u32
*fp2
)
8697 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8698 struct drm_device
*dev
= crtc
->dev
;
8699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8700 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8701 struct drm_connector
*connector
;
8702 struct drm_connector_state
*connector_state
;
8703 struct intel_encoder
*encoder
;
8705 int factor
, num_connectors
= 0, i
;
8706 bool is_lvds
= false, is_sdvo
= false;
8708 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8709 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8712 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8714 switch (encoder
->type
) {
8715 case INTEL_OUTPUT_LVDS
:
8718 case INTEL_OUTPUT_SDVO
:
8719 case INTEL_OUTPUT_HDMI
:
8729 /* Enable autotuning of the PLL clock (if permissible) */
8732 if ((intel_panel_use_ssc(dev_priv
) &&
8733 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8734 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8736 } else if (crtc_state
->sdvo_tv_clock
)
8739 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8742 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8748 dpll
|= DPLLB_MODE_LVDS
;
8750 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8752 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8753 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8756 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8757 if (crtc_state
->has_dp_encoder
)
8758 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8760 /* compute bitmask from p1 value */
8761 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8763 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8765 switch (crtc_state
->dpll
.p2
) {
8767 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8770 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8773 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8776 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8780 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8781 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8783 dpll
|= PLL_REF_INPUT_DREFCLK
;
8785 return dpll
| DPLL_VCO_ENABLE
;
8788 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8789 struct intel_crtc_state
*crtc_state
)
8791 struct drm_device
*dev
= crtc
->base
.dev
;
8792 intel_clock_t clock
, reduced_clock
;
8793 u32 dpll
= 0, fp
= 0, fp2
= 0;
8794 bool ok
, has_reduced_clock
= false;
8795 bool is_lvds
= false;
8796 struct intel_shared_dpll
*pll
;
8798 memset(&crtc_state
->dpll_hw_state
, 0,
8799 sizeof(crtc_state
->dpll_hw_state
));
8801 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8803 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8804 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8806 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8807 &has_reduced_clock
, &reduced_clock
);
8808 if (!ok
&& !crtc_state
->clock_set
) {
8809 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8812 /* Compat-code for transition, will disappear. */
8813 if (!crtc_state
->clock_set
) {
8814 crtc_state
->dpll
.n
= clock
.n
;
8815 crtc_state
->dpll
.m1
= clock
.m1
;
8816 crtc_state
->dpll
.m2
= clock
.m2
;
8817 crtc_state
->dpll
.p1
= clock
.p1
;
8818 crtc_state
->dpll
.p2
= clock
.p2
;
8821 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8822 if (crtc_state
->has_pch_encoder
) {
8823 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8824 if (has_reduced_clock
)
8825 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8827 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8828 &fp
, &reduced_clock
,
8829 has_reduced_clock
? &fp2
: NULL
);
8831 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8832 crtc_state
->dpll_hw_state
.fp0
= fp
;
8833 if (has_reduced_clock
)
8834 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8836 crtc_state
->dpll_hw_state
.fp1
= fp
;
8838 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8840 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8841 pipe_name(crtc
->pipe
));
8846 if (is_lvds
&& has_reduced_clock
)
8847 crtc
->lowfreq_avail
= true;
8849 crtc
->lowfreq_avail
= false;
8854 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8855 struct intel_link_m_n
*m_n
)
8857 struct drm_device
*dev
= crtc
->base
.dev
;
8858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8859 enum pipe pipe
= crtc
->pipe
;
8861 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8862 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8863 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8865 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8866 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8867 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8870 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8871 enum transcoder transcoder
,
8872 struct intel_link_m_n
*m_n
,
8873 struct intel_link_m_n
*m2_n2
)
8875 struct drm_device
*dev
= crtc
->base
.dev
;
8876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8877 enum pipe pipe
= crtc
->pipe
;
8879 if (INTEL_INFO(dev
)->gen
>= 5) {
8880 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8881 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8882 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8884 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8885 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8886 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8887 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8888 * gen < 8) and if DRRS is supported (to make sure the
8889 * registers are not unnecessarily read).
8891 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8892 crtc
->config
->has_drrs
) {
8893 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8894 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8895 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8897 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8898 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8899 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8902 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8903 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8904 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8906 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8907 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8908 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8912 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8913 struct intel_crtc_state
*pipe_config
)
8915 if (pipe_config
->has_pch_encoder
)
8916 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8918 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8919 &pipe_config
->dp_m_n
,
8920 &pipe_config
->dp_m2_n2
);
8923 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8924 struct intel_crtc_state
*pipe_config
)
8926 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8927 &pipe_config
->fdi_m_n
, NULL
);
8930 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8931 struct intel_crtc_state
*pipe_config
)
8933 struct drm_device
*dev
= crtc
->base
.dev
;
8934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8935 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8936 uint32_t ps_ctrl
= 0;
8940 /* find scaler attached to this pipe */
8941 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8942 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8943 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8945 pipe_config
->pch_pfit
.enabled
= true;
8946 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8947 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8952 scaler_state
->scaler_id
= id
;
8954 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8956 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8961 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8962 struct intel_initial_plane_config
*plane_config
)
8964 struct drm_device
*dev
= crtc
->base
.dev
;
8965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8966 u32 val
, base
, offset
, stride_mult
, tiling
;
8967 int pipe
= crtc
->pipe
;
8968 int fourcc
, pixel_format
;
8969 unsigned int aligned_height
;
8970 struct drm_framebuffer
*fb
;
8971 struct intel_framebuffer
*intel_fb
;
8973 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8975 DRM_DEBUG_KMS("failed to alloc fb\n");
8979 fb
= &intel_fb
->base
;
8981 val
= I915_READ(PLANE_CTL(pipe
, 0));
8982 if (!(val
& PLANE_CTL_ENABLE
))
8985 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8986 fourcc
= skl_format_to_fourcc(pixel_format
,
8987 val
& PLANE_CTL_ORDER_RGBX
,
8988 val
& PLANE_CTL_ALPHA_MASK
);
8989 fb
->pixel_format
= fourcc
;
8990 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8992 tiling
= val
& PLANE_CTL_TILED_MASK
;
8994 case PLANE_CTL_TILED_LINEAR
:
8995 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8997 case PLANE_CTL_TILED_X
:
8998 plane_config
->tiling
= I915_TILING_X
;
8999 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9001 case PLANE_CTL_TILED_Y
:
9002 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9004 case PLANE_CTL_TILED_YF
:
9005 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9008 MISSING_CASE(tiling
);
9012 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9013 plane_config
->base
= base
;
9015 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9017 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9018 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9019 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9021 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9022 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
9024 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9026 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9030 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9032 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9033 pipe_name(pipe
), fb
->width
, fb
->height
,
9034 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9035 plane_config
->size
);
9037 plane_config
->fb
= intel_fb
;
9044 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9045 struct intel_crtc_state
*pipe_config
)
9047 struct drm_device
*dev
= crtc
->base
.dev
;
9048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9051 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9053 if (tmp
& PF_ENABLE
) {
9054 pipe_config
->pch_pfit
.enabled
= true;
9055 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9056 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9058 /* We currently do not free assignements of panel fitters on
9059 * ivb/hsw (since we don't use the higher upscaling modes which
9060 * differentiates them) so just WARN about this case for now. */
9062 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9063 PF_PIPE_SEL_IVB(crtc
->pipe
));
9069 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9070 struct intel_initial_plane_config
*plane_config
)
9072 struct drm_device
*dev
= crtc
->base
.dev
;
9073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9074 u32 val
, base
, offset
;
9075 int pipe
= crtc
->pipe
;
9076 int fourcc
, pixel_format
;
9077 unsigned int aligned_height
;
9078 struct drm_framebuffer
*fb
;
9079 struct intel_framebuffer
*intel_fb
;
9081 val
= I915_READ(DSPCNTR(pipe
));
9082 if (!(val
& DISPLAY_PLANE_ENABLE
))
9085 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9087 DRM_DEBUG_KMS("failed to alloc fb\n");
9091 fb
= &intel_fb
->base
;
9093 if (INTEL_INFO(dev
)->gen
>= 4) {
9094 if (val
& DISPPLANE_TILED
) {
9095 plane_config
->tiling
= I915_TILING_X
;
9096 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9100 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9101 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9102 fb
->pixel_format
= fourcc
;
9103 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9105 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9106 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9107 offset
= I915_READ(DSPOFFSET(pipe
));
9109 if (plane_config
->tiling
)
9110 offset
= I915_READ(DSPTILEOFF(pipe
));
9112 offset
= I915_READ(DSPLINOFF(pipe
));
9114 plane_config
->base
= base
;
9116 val
= I915_READ(PIPESRC(pipe
));
9117 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9118 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9120 val
= I915_READ(DSPSTRIDE(pipe
));
9121 fb
->pitches
[0] = val
& 0xffffffc0;
9123 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9127 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9129 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9130 pipe_name(pipe
), fb
->width
, fb
->height
,
9131 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9132 plane_config
->size
);
9134 plane_config
->fb
= intel_fb
;
9137 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9138 struct intel_crtc_state
*pipe_config
)
9140 struct drm_device
*dev
= crtc
->base
.dev
;
9141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9144 if (!intel_display_power_is_enabled(dev_priv
,
9145 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9148 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9149 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9151 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9152 if (!(tmp
& PIPECONF_ENABLE
))
9155 switch (tmp
& PIPECONF_BPC_MASK
) {
9157 pipe_config
->pipe_bpp
= 18;
9160 pipe_config
->pipe_bpp
= 24;
9162 case PIPECONF_10BPC
:
9163 pipe_config
->pipe_bpp
= 30;
9165 case PIPECONF_12BPC
:
9166 pipe_config
->pipe_bpp
= 36;
9172 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9173 pipe_config
->limited_color_range
= true;
9175 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9176 struct intel_shared_dpll
*pll
;
9178 pipe_config
->has_pch_encoder
= true;
9180 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9181 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9182 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9184 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9186 if (HAS_PCH_IBX(dev_priv
->dev
)) {
9187 pipe_config
->shared_dpll
=
9188 (enum intel_dpll_id
) crtc
->pipe
;
9190 tmp
= I915_READ(PCH_DPLL_SEL
);
9191 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9192 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
9194 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
9197 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9199 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9200 &pipe_config
->dpll_hw_state
));
9202 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9203 pipe_config
->pixel_multiplier
=
9204 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9205 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9207 ironlake_pch_clock_get(crtc
, pipe_config
);
9209 pipe_config
->pixel_multiplier
= 1;
9212 intel_get_pipe_timings(crtc
, pipe_config
);
9214 ironlake_get_pfit_config(crtc
, pipe_config
);
9219 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9221 struct drm_device
*dev
= dev_priv
->dev
;
9222 struct intel_crtc
*crtc
;
9224 for_each_intel_crtc(dev
, crtc
)
9225 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9226 pipe_name(crtc
->pipe
));
9228 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9229 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9230 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9231 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9232 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9233 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9234 "CPU PWM1 enabled\n");
9235 if (IS_HASWELL(dev
))
9236 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9237 "CPU PWM2 enabled\n");
9238 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9239 "PCH PWM1 enabled\n");
9240 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9241 "Utility pin enabled\n");
9242 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9245 * In theory we can still leave IRQs enabled, as long as only the HPD
9246 * interrupts remain enabled. We used to check for that, but since it's
9247 * gen-specific and since we only disable LCPLL after we fully disable
9248 * the interrupts, the check below should be enough.
9250 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9253 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9255 struct drm_device
*dev
= dev_priv
->dev
;
9257 if (IS_HASWELL(dev
))
9258 return I915_READ(D_COMP_HSW
);
9260 return I915_READ(D_COMP_BDW
);
9263 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9265 struct drm_device
*dev
= dev_priv
->dev
;
9267 if (IS_HASWELL(dev
)) {
9268 mutex_lock(&dev_priv
->rps
.hw_lock
);
9269 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9271 DRM_ERROR("Failed to write to D_COMP\n");
9272 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9274 I915_WRITE(D_COMP_BDW
, val
);
9275 POSTING_READ(D_COMP_BDW
);
9280 * This function implements pieces of two sequences from BSpec:
9281 * - Sequence for display software to disable LCPLL
9282 * - Sequence for display software to allow package C8+
9283 * The steps implemented here are just the steps that actually touch the LCPLL
9284 * register. Callers should take care of disabling all the display engine
9285 * functions, doing the mode unset, fixing interrupts, etc.
9287 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9288 bool switch_to_fclk
, bool allow_power_down
)
9292 assert_can_disable_lcpll(dev_priv
);
9294 val
= I915_READ(LCPLL_CTL
);
9296 if (switch_to_fclk
) {
9297 val
|= LCPLL_CD_SOURCE_FCLK
;
9298 I915_WRITE(LCPLL_CTL
, val
);
9300 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9301 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9302 DRM_ERROR("Switching to FCLK failed\n");
9304 val
= I915_READ(LCPLL_CTL
);
9307 val
|= LCPLL_PLL_DISABLE
;
9308 I915_WRITE(LCPLL_CTL
, val
);
9309 POSTING_READ(LCPLL_CTL
);
9311 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9312 DRM_ERROR("LCPLL still locked\n");
9314 val
= hsw_read_dcomp(dev_priv
);
9315 val
|= D_COMP_COMP_DISABLE
;
9316 hsw_write_dcomp(dev_priv
, val
);
9319 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9321 DRM_ERROR("D_COMP RCOMP still in progress\n");
9323 if (allow_power_down
) {
9324 val
= I915_READ(LCPLL_CTL
);
9325 val
|= LCPLL_POWER_DOWN_ALLOW
;
9326 I915_WRITE(LCPLL_CTL
, val
);
9327 POSTING_READ(LCPLL_CTL
);
9332 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9335 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9339 val
= I915_READ(LCPLL_CTL
);
9341 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9342 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9346 * Make sure we're not on PC8 state before disabling PC8, otherwise
9347 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9349 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9351 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9352 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9353 I915_WRITE(LCPLL_CTL
, val
);
9354 POSTING_READ(LCPLL_CTL
);
9357 val
= hsw_read_dcomp(dev_priv
);
9358 val
|= D_COMP_COMP_FORCE
;
9359 val
&= ~D_COMP_COMP_DISABLE
;
9360 hsw_write_dcomp(dev_priv
, val
);
9362 val
= I915_READ(LCPLL_CTL
);
9363 val
&= ~LCPLL_PLL_DISABLE
;
9364 I915_WRITE(LCPLL_CTL
, val
);
9366 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9367 DRM_ERROR("LCPLL not locked yet\n");
9369 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9370 val
= I915_READ(LCPLL_CTL
);
9371 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9372 I915_WRITE(LCPLL_CTL
, val
);
9374 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9375 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9376 DRM_ERROR("Switching back to LCPLL failed\n");
9379 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9380 intel_update_cdclk(dev_priv
->dev
);
9384 * Package states C8 and deeper are really deep PC states that can only be
9385 * reached when all the devices on the system allow it, so even if the graphics
9386 * device allows PC8+, it doesn't mean the system will actually get to these
9387 * states. Our driver only allows PC8+ when going into runtime PM.
9389 * The requirements for PC8+ are that all the outputs are disabled, the power
9390 * well is disabled and most interrupts are disabled, and these are also
9391 * requirements for runtime PM. When these conditions are met, we manually do
9392 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9393 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9396 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9397 * the state of some registers, so when we come back from PC8+ we need to
9398 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9399 * need to take care of the registers kept by RC6. Notice that this happens even
9400 * if we don't put the device in PCI D3 state (which is what currently happens
9401 * because of the runtime PM support).
9403 * For more, read "Display Sequences for Package C8" on the hardware
9406 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9408 struct drm_device
*dev
= dev_priv
->dev
;
9411 DRM_DEBUG_KMS("Enabling package C8+\n");
9413 if (HAS_PCH_LPT_LP(dev
)) {
9414 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9415 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9416 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9419 lpt_disable_clkout_dp(dev
);
9420 hsw_disable_lcpll(dev_priv
, true, true);
9423 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9425 struct drm_device
*dev
= dev_priv
->dev
;
9428 DRM_DEBUG_KMS("Disabling package C8+\n");
9430 hsw_restore_lcpll(dev_priv
);
9431 lpt_init_pch_refclk(dev
);
9433 if (HAS_PCH_LPT_LP(dev
)) {
9434 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9435 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9436 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9439 intel_prepare_ddi(dev
);
9442 static void broxton_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9444 struct drm_device
*dev
= old_state
->dev
;
9445 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
9447 broxton_set_cdclk(dev
, req_cdclk
);
9450 /* compute the max rate for new configuration */
9451 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9453 struct intel_crtc
*intel_crtc
;
9454 struct intel_crtc_state
*crtc_state
;
9455 int max_pixel_rate
= 0;
9457 for_each_intel_crtc(state
->dev
, intel_crtc
) {
9460 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9461 if (IS_ERR(crtc_state
))
9462 return PTR_ERR(crtc_state
);
9464 if (!crtc_state
->base
.enable
)
9467 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9469 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9470 if (IS_BROADWELL(state
->dev
) && crtc_state
->ips_enabled
)
9471 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9473 max_pixel_rate
= max(max_pixel_rate
, pixel_rate
);
9476 return max_pixel_rate
;
9479 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9485 if (WARN((I915_READ(LCPLL_CTL
) &
9486 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9487 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9488 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9489 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9490 "trying to change cdclk frequency with cdclk not enabled\n"))
9493 mutex_lock(&dev_priv
->rps
.hw_lock
);
9494 ret
= sandybridge_pcode_write(dev_priv
,
9495 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9496 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9498 DRM_ERROR("failed to inform pcode about cdclk change\n");
9502 val
= I915_READ(LCPLL_CTL
);
9503 val
|= LCPLL_CD_SOURCE_FCLK
;
9504 I915_WRITE(LCPLL_CTL
, val
);
9506 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9507 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9508 DRM_ERROR("Switching to FCLK failed\n");
9510 val
= I915_READ(LCPLL_CTL
);
9511 val
&= ~LCPLL_CLK_FREQ_MASK
;
9515 val
|= LCPLL_CLK_FREQ_450
;
9519 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9523 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9527 val
|= LCPLL_CLK_FREQ_675_BDW
;
9531 WARN(1, "invalid cdclk frequency\n");
9535 I915_WRITE(LCPLL_CTL
, val
);
9537 val
= I915_READ(LCPLL_CTL
);
9538 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9539 I915_WRITE(LCPLL_CTL
, val
);
9541 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9542 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9543 DRM_ERROR("Switching back to LCPLL failed\n");
9545 mutex_lock(&dev_priv
->rps
.hw_lock
);
9546 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9547 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9549 intel_update_cdclk(dev
);
9551 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9552 "cdclk requested %d kHz but got %d kHz\n",
9553 cdclk
, dev_priv
->cdclk_freq
);
9556 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9558 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9559 int max_pixclk
= ilk_max_pixel_rate(state
);
9563 * FIXME should also account for plane ratio
9564 * once 64bpp pixel formats are supported.
9566 if (max_pixclk
> 540000)
9568 else if (max_pixclk
> 450000)
9570 else if (max_pixclk
> 337500)
9576 * FIXME move the cdclk caclulation to
9577 * compute_config() so we can fail gracegully.
9579 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9580 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9581 cdclk
, dev_priv
->max_cdclk_freq
);
9582 cdclk
= dev_priv
->max_cdclk_freq
;
9585 to_intel_atomic_state(state
)->cdclk
= cdclk
;
9590 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9592 struct drm_device
*dev
= old_state
->dev
;
9593 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
9595 broadwell_set_cdclk(dev
, req_cdclk
);
9598 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9599 struct intel_crtc_state
*crtc_state
)
9601 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9604 crtc
->lowfreq_avail
= false;
9609 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9611 struct intel_crtc_state
*pipe_config
)
9615 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9616 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9619 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9620 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9623 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9624 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9627 DRM_ERROR("Incorrect port type\n");
9631 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9633 struct intel_crtc_state
*pipe_config
)
9635 u32 temp
, dpll_ctl1
;
9637 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9638 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9640 switch (pipe_config
->ddi_pll_sel
) {
9643 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9644 * of the shared DPLL framework and thus needs to be read out
9647 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9648 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9651 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9654 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9657 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9662 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9664 struct intel_crtc_state
*pipe_config
)
9666 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9668 switch (pipe_config
->ddi_pll_sel
) {
9669 case PORT_CLK_SEL_WRPLL1
:
9670 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9672 case PORT_CLK_SEL_WRPLL2
:
9673 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9678 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9679 struct intel_crtc_state
*pipe_config
)
9681 struct drm_device
*dev
= crtc
->base
.dev
;
9682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9683 struct intel_shared_dpll
*pll
;
9687 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9689 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9691 if (IS_SKYLAKE(dev
))
9692 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9693 else if (IS_BROXTON(dev
))
9694 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9696 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9698 if (pipe_config
->shared_dpll
>= 0) {
9699 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9701 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9702 &pipe_config
->dpll_hw_state
));
9706 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9707 * DDI E. So just check whether this pipe is wired to DDI E and whether
9708 * the PCH transcoder is on.
9710 if (INTEL_INFO(dev
)->gen
< 9 &&
9711 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9712 pipe_config
->has_pch_encoder
= true;
9714 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9715 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9716 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9718 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9722 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9723 struct intel_crtc_state
*pipe_config
)
9725 struct drm_device
*dev
= crtc
->base
.dev
;
9726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9727 enum intel_display_power_domain pfit_domain
;
9730 if (!intel_display_power_is_enabled(dev_priv
,
9731 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9734 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9735 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9737 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9738 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9739 enum pipe trans_edp_pipe
;
9740 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9742 WARN(1, "unknown pipe linked to edp transcoder\n");
9743 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9744 case TRANS_DDI_EDP_INPUT_A_ON
:
9745 trans_edp_pipe
= PIPE_A
;
9747 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9748 trans_edp_pipe
= PIPE_B
;
9750 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9751 trans_edp_pipe
= PIPE_C
;
9755 if (trans_edp_pipe
== crtc
->pipe
)
9756 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9759 if (!intel_display_power_is_enabled(dev_priv
,
9760 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9763 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9764 if (!(tmp
& PIPECONF_ENABLE
))
9767 haswell_get_ddi_port_state(crtc
, pipe_config
);
9769 intel_get_pipe_timings(crtc
, pipe_config
);
9771 if (INTEL_INFO(dev
)->gen
>= 9) {
9772 skl_init_scalers(dev
, crtc
, pipe_config
);
9775 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9777 if (INTEL_INFO(dev
)->gen
>= 9) {
9778 pipe_config
->scaler_state
.scaler_id
= -1;
9779 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9782 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9783 if (INTEL_INFO(dev
)->gen
>= 9)
9784 skylake_get_pfit_config(crtc
, pipe_config
);
9786 ironlake_get_pfit_config(crtc
, pipe_config
);
9789 if (IS_HASWELL(dev
))
9790 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9791 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9793 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9794 pipe_config
->pixel_multiplier
=
9795 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9797 pipe_config
->pixel_multiplier
= 1;
9803 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9805 struct drm_device
*dev
= crtc
->dev
;
9806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9807 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9808 uint32_t cntl
= 0, size
= 0;
9811 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9812 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9813 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9817 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9828 cntl
|= CURSOR_ENABLE
|
9829 CURSOR_GAMMA_ENABLE
|
9830 CURSOR_FORMAT_ARGB
|
9831 CURSOR_STRIDE(stride
);
9833 size
= (height
<< 12) | width
;
9836 if (intel_crtc
->cursor_cntl
!= 0 &&
9837 (intel_crtc
->cursor_base
!= base
||
9838 intel_crtc
->cursor_size
!= size
||
9839 intel_crtc
->cursor_cntl
!= cntl
)) {
9840 /* On these chipsets we can only modify the base/size/stride
9841 * whilst the cursor is disabled.
9843 I915_WRITE(_CURACNTR
, 0);
9844 POSTING_READ(_CURACNTR
);
9845 intel_crtc
->cursor_cntl
= 0;
9848 if (intel_crtc
->cursor_base
!= base
) {
9849 I915_WRITE(_CURABASE
, base
);
9850 intel_crtc
->cursor_base
= base
;
9853 if (intel_crtc
->cursor_size
!= size
) {
9854 I915_WRITE(CURSIZE
, size
);
9855 intel_crtc
->cursor_size
= size
;
9858 if (intel_crtc
->cursor_cntl
!= cntl
) {
9859 I915_WRITE(_CURACNTR
, cntl
);
9860 POSTING_READ(_CURACNTR
);
9861 intel_crtc
->cursor_cntl
= cntl
;
9865 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9867 struct drm_device
*dev
= crtc
->dev
;
9868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9869 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9870 int pipe
= intel_crtc
->pipe
;
9875 cntl
= MCURSOR_GAMMA_ENABLE
;
9876 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9878 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9881 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9884 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9887 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
9890 cntl
|= pipe
<< 28; /* Connect to correct pipe */
9892 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
9893 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9896 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
9897 cntl
|= CURSOR_ROTATE_180
;
9899 if (intel_crtc
->cursor_cntl
!= cntl
) {
9900 I915_WRITE(CURCNTR(pipe
), cntl
);
9901 POSTING_READ(CURCNTR(pipe
));
9902 intel_crtc
->cursor_cntl
= cntl
;
9905 /* and commit changes on next vblank */
9906 I915_WRITE(CURBASE(pipe
), base
);
9907 POSTING_READ(CURBASE(pipe
));
9909 intel_crtc
->cursor_base
= base
;
9912 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9913 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
9916 struct drm_device
*dev
= crtc
->dev
;
9917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9918 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9919 int pipe
= intel_crtc
->pipe
;
9920 int x
= crtc
->cursor_x
;
9921 int y
= crtc
->cursor_y
;
9922 u32 base
= 0, pos
= 0;
9925 base
= intel_crtc
->cursor_addr
;
9927 if (x
>= intel_crtc
->config
->pipe_src_w
)
9930 if (y
>= intel_crtc
->config
->pipe_src_h
)
9934 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
9937 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9940 pos
|= x
<< CURSOR_X_SHIFT
;
9943 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
9946 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9949 pos
|= y
<< CURSOR_Y_SHIFT
;
9951 if (base
== 0 && intel_crtc
->cursor_base
== 0)
9954 I915_WRITE(CURPOS(pipe
), pos
);
9956 /* ILK+ do this automagically */
9957 if (HAS_GMCH_DISPLAY(dev
) &&
9958 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
9959 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
9960 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
9963 if (IS_845G(dev
) || IS_I865G(dev
))
9964 i845_update_cursor(crtc
, base
);
9966 i9xx_update_cursor(crtc
, base
);
9969 static bool cursor_size_ok(struct drm_device
*dev
,
9970 uint32_t width
, uint32_t height
)
9972 if (width
== 0 || height
== 0)
9976 * 845g/865g are special in that they are only limited by
9977 * the width of their cursors, the height is arbitrary up to
9978 * the precision of the register. Everything else requires
9979 * square cursors, limited to a few power-of-two sizes.
9981 if (IS_845G(dev
) || IS_I865G(dev
)) {
9982 if ((width
& 63) != 0)
9985 if (width
> (IS_845G(dev
) ? 64 : 512))
9991 switch (width
| height
) {
10006 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
10007 u16
*blue
, uint32_t start
, uint32_t size
)
10009 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
10010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10012 for (i
= start
; i
< end
; i
++) {
10013 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
10014 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
10015 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
10018 intel_crtc_load_lut(crtc
);
10021 /* VESA 640x480x72Hz mode to set on the pipe */
10022 static struct drm_display_mode load_detect_mode
= {
10023 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10024 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10027 struct drm_framebuffer
*
10028 __intel_framebuffer_create(struct drm_device
*dev
,
10029 struct drm_mode_fb_cmd2
*mode_cmd
,
10030 struct drm_i915_gem_object
*obj
)
10032 struct intel_framebuffer
*intel_fb
;
10035 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10037 drm_gem_object_unreference(&obj
->base
);
10038 return ERR_PTR(-ENOMEM
);
10041 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10045 return &intel_fb
->base
;
10047 drm_gem_object_unreference(&obj
->base
);
10050 return ERR_PTR(ret
);
10053 static struct drm_framebuffer
*
10054 intel_framebuffer_create(struct drm_device
*dev
,
10055 struct drm_mode_fb_cmd2
*mode_cmd
,
10056 struct drm_i915_gem_object
*obj
)
10058 struct drm_framebuffer
*fb
;
10061 ret
= i915_mutex_lock_interruptible(dev
);
10063 return ERR_PTR(ret
);
10064 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10065 mutex_unlock(&dev
->struct_mutex
);
10071 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10073 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10074 return ALIGN(pitch
, 64);
10078 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10080 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10081 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10084 static struct drm_framebuffer
*
10085 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10086 struct drm_display_mode
*mode
,
10087 int depth
, int bpp
)
10089 struct drm_i915_gem_object
*obj
;
10090 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10092 obj
= i915_gem_alloc_object(dev
,
10093 intel_framebuffer_size_for_mode(mode
, bpp
));
10095 return ERR_PTR(-ENOMEM
);
10097 mode_cmd
.width
= mode
->hdisplay
;
10098 mode_cmd
.height
= mode
->vdisplay
;
10099 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10101 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10103 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10106 static struct drm_framebuffer
*
10107 mode_fits_in_fbdev(struct drm_device
*dev
,
10108 struct drm_display_mode
*mode
)
10110 #ifdef CONFIG_DRM_FBDEV_EMULATION
10111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10112 struct drm_i915_gem_object
*obj
;
10113 struct drm_framebuffer
*fb
;
10115 if (!dev_priv
->fbdev
)
10118 if (!dev_priv
->fbdev
->fb
)
10121 obj
= dev_priv
->fbdev
->fb
->obj
;
10124 fb
= &dev_priv
->fbdev
->fb
->base
;
10125 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10126 fb
->bits_per_pixel
))
10129 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10138 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10139 struct drm_crtc
*crtc
,
10140 struct drm_display_mode
*mode
,
10141 struct drm_framebuffer
*fb
,
10144 struct drm_plane_state
*plane_state
;
10145 int hdisplay
, vdisplay
;
10148 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10149 if (IS_ERR(plane_state
))
10150 return PTR_ERR(plane_state
);
10153 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10155 hdisplay
= vdisplay
= 0;
10157 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10160 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10161 plane_state
->crtc_x
= 0;
10162 plane_state
->crtc_y
= 0;
10163 plane_state
->crtc_w
= hdisplay
;
10164 plane_state
->crtc_h
= vdisplay
;
10165 plane_state
->src_x
= x
<< 16;
10166 plane_state
->src_y
= y
<< 16;
10167 plane_state
->src_w
= hdisplay
<< 16;
10168 plane_state
->src_h
= vdisplay
<< 16;
10173 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10174 struct drm_display_mode
*mode
,
10175 struct intel_load_detect_pipe
*old
,
10176 struct drm_modeset_acquire_ctx
*ctx
)
10178 struct intel_crtc
*intel_crtc
;
10179 struct intel_encoder
*intel_encoder
=
10180 intel_attached_encoder(connector
);
10181 struct drm_crtc
*possible_crtc
;
10182 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10183 struct drm_crtc
*crtc
= NULL
;
10184 struct drm_device
*dev
= encoder
->dev
;
10185 struct drm_framebuffer
*fb
;
10186 struct drm_mode_config
*config
= &dev
->mode_config
;
10187 struct drm_atomic_state
*state
= NULL
;
10188 struct drm_connector_state
*connector_state
;
10189 struct intel_crtc_state
*crtc_state
;
10192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10193 connector
->base
.id
, connector
->name
,
10194 encoder
->base
.id
, encoder
->name
);
10197 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10202 * Algorithm gets a little messy:
10204 * - if the connector already has an assigned crtc, use it (but make
10205 * sure it's on first)
10207 * - try to find the first unused crtc that can drive this connector,
10208 * and use that if we find one
10211 /* See if we already have a CRTC for this connector */
10212 if (encoder
->crtc
) {
10213 crtc
= encoder
->crtc
;
10215 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10218 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10222 old
->dpms_mode
= connector
->dpms
;
10223 old
->load_detect_temp
= false;
10225 /* Make sure the crtc and connector are running */
10226 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
10227 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
10232 /* Find an unused one (if possible) */
10233 for_each_crtc(dev
, possible_crtc
) {
10235 if (!(encoder
->possible_crtcs
& (1 << i
)))
10237 if (possible_crtc
->state
->enable
)
10240 crtc
= possible_crtc
;
10245 * If we didn't find an unused CRTC, don't use any.
10248 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10252 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10255 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10259 intel_crtc
= to_intel_crtc(crtc
);
10260 old
->dpms_mode
= connector
->dpms
;
10261 old
->load_detect_temp
= true;
10262 old
->release_fb
= NULL
;
10264 state
= drm_atomic_state_alloc(dev
);
10268 state
->acquire_ctx
= ctx
;
10270 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10271 if (IS_ERR(connector_state
)) {
10272 ret
= PTR_ERR(connector_state
);
10276 connector_state
->crtc
= crtc
;
10277 connector_state
->best_encoder
= &intel_encoder
->base
;
10279 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10280 if (IS_ERR(crtc_state
)) {
10281 ret
= PTR_ERR(crtc_state
);
10285 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10288 mode
= &load_detect_mode
;
10290 /* We need a framebuffer large enough to accommodate all accesses
10291 * that the plane may generate whilst we perform load detection.
10292 * We can not rely on the fbcon either being present (we get called
10293 * during its initialisation to detect all boot displays, or it may
10294 * not even exist) or that it is large enough to satisfy the
10297 fb
= mode_fits_in_fbdev(dev
, mode
);
10299 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10300 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10301 old
->release_fb
= fb
;
10303 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10305 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10309 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10313 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
10315 if (drm_atomic_commit(state
)) {
10316 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10317 if (old
->release_fb
)
10318 old
->release_fb
->funcs
->destroy(old
->release_fb
);
10321 crtc
->primary
->crtc
= crtc
;
10323 /* let the connector get through one full cycle before testing */
10324 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10328 drm_atomic_state_free(state
);
10331 if (ret
== -EDEADLK
) {
10332 drm_modeset_backoff(ctx
);
10339 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10340 struct intel_load_detect_pipe
*old
,
10341 struct drm_modeset_acquire_ctx
*ctx
)
10343 struct drm_device
*dev
= connector
->dev
;
10344 struct intel_encoder
*intel_encoder
=
10345 intel_attached_encoder(connector
);
10346 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10347 struct drm_crtc
*crtc
= encoder
->crtc
;
10348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10349 struct drm_atomic_state
*state
;
10350 struct drm_connector_state
*connector_state
;
10351 struct intel_crtc_state
*crtc_state
;
10354 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10355 connector
->base
.id
, connector
->name
,
10356 encoder
->base
.id
, encoder
->name
);
10358 if (old
->load_detect_temp
) {
10359 state
= drm_atomic_state_alloc(dev
);
10363 state
->acquire_ctx
= ctx
;
10365 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10366 if (IS_ERR(connector_state
))
10369 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10370 if (IS_ERR(crtc_state
))
10373 connector_state
->best_encoder
= NULL
;
10374 connector_state
->crtc
= NULL
;
10376 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
10378 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
10383 ret
= drm_atomic_commit(state
);
10387 if (old
->release_fb
) {
10388 drm_framebuffer_unregister_private(old
->release_fb
);
10389 drm_framebuffer_unreference(old
->release_fb
);
10395 /* Switch crtc and encoder back off if necessary */
10396 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
10397 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
10401 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10402 drm_atomic_state_free(state
);
10405 static int i9xx_pll_refclk(struct drm_device
*dev
,
10406 const struct intel_crtc_state
*pipe_config
)
10408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10409 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10411 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10412 return dev_priv
->vbt
.lvds_ssc_freq
;
10413 else if (HAS_PCH_SPLIT(dev
))
10415 else if (!IS_GEN2(dev
))
10421 /* Returns the clock of the currently programmed mode of the given pipe. */
10422 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10423 struct intel_crtc_state
*pipe_config
)
10425 struct drm_device
*dev
= crtc
->base
.dev
;
10426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10427 int pipe
= pipe_config
->cpu_transcoder
;
10428 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10430 intel_clock_t clock
;
10432 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10434 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10435 fp
= pipe_config
->dpll_hw_state
.fp0
;
10437 fp
= pipe_config
->dpll_hw_state
.fp1
;
10439 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10440 if (IS_PINEVIEW(dev
)) {
10441 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10442 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10444 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10445 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10448 if (!IS_GEN2(dev
)) {
10449 if (IS_PINEVIEW(dev
))
10450 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10451 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10453 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10454 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10456 switch (dpll
& DPLL_MODE_MASK
) {
10457 case DPLLB_MODE_DAC_SERIAL
:
10458 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10461 case DPLLB_MODE_LVDS
:
10462 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10466 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10467 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10471 if (IS_PINEVIEW(dev
))
10472 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10474 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10476 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10477 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10480 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10481 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10483 if (lvds
& LVDS_CLKB_POWER_UP
)
10488 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10491 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10492 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10494 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10500 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10504 * This value includes pixel_multiplier. We will use
10505 * port_clock to compute adjusted_mode.crtc_clock in the
10506 * encoder's get_config() function.
10508 pipe_config
->port_clock
= port_clock
;
10511 int intel_dotclock_calculate(int link_freq
,
10512 const struct intel_link_m_n
*m_n
)
10515 * The calculation for the data clock is:
10516 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10517 * But we want to avoid losing precison if possible, so:
10518 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10520 * and the link clock is simpler:
10521 * link_clock = (m * link_clock) / n
10527 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10530 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10531 struct intel_crtc_state
*pipe_config
)
10533 struct drm_device
*dev
= crtc
->base
.dev
;
10535 /* read out port_clock from the DPLL */
10536 i9xx_crtc_clock_get(crtc
, pipe_config
);
10539 * This value does not include pixel_multiplier.
10540 * We will check that port_clock and adjusted_mode.crtc_clock
10541 * agree once we know their relationship in the encoder's
10542 * get_config() function.
10544 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10545 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10546 &pipe_config
->fdi_m_n
);
10549 /** Returns the currently programmed mode of the given pipe. */
10550 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10551 struct drm_crtc
*crtc
)
10553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10554 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10555 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10556 struct drm_display_mode
*mode
;
10557 struct intel_crtc_state pipe_config
;
10558 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10559 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10560 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10561 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10562 enum pipe pipe
= intel_crtc
->pipe
;
10564 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10569 * Construct a pipe_config sufficient for getting the clock info
10570 * back out of crtc_clock_get.
10572 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10573 * to use a real value here instead.
10575 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10576 pipe_config
.pixel_multiplier
= 1;
10577 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10578 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10579 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10580 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10582 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10583 mode
->hdisplay
= (htot
& 0xffff) + 1;
10584 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10585 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10586 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10587 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10588 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10589 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10590 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10592 drm_mode_set_name(mode
);
10597 void intel_mark_busy(struct drm_device
*dev
)
10599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10601 if (dev_priv
->mm
.busy
)
10604 intel_runtime_pm_get(dev_priv
);
10605 i915_update_gfx_val(dev_priv
);
10606 if (INTEL_INFO(dev
)->gen
>= 6)
10607 gen6_rps_busy(dev_priv
);
10608 dev_priv
->mm
.busy
= true;
10611 void intel_mark_idle(struct drm_device
*dev
)
10613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10615 if (!dev_priv
->mm
.busy
)
10618 dev_priv
->mm
.busy
= false;
10620 if (INTEL_INFO(dev
)->gen
>= 6)
10621 gen6_rps_idle(dev
->dev_private
);
10623 intel_runtime_pm_put(dev_priv
);
10626 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10629 struct drm_device
*dev
= crtc
->dev
;
10630 struct intel_unpin_work
*work
;
10632 spin_lock_irq(&dev
->event_lock
);
10633 work
= intel_crtc
->unpin_work
;
10634 intel_crtc
->unpin_work
= NULL
;
10635 spin_unlock_irq(&dev
->event_lock
);
10638 cancel_work_sync(&work
->work
);
10642 drm_crtc_cleanup(crtc
);
10647 static void intel_unpin_work_fn(struct work_struct
*__work
)
10649 struct intel_unpin_work
*work
=
10650 container_of(__work
, struct intel_unpin_work
, work
);
10651 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
10652 struct drm_device
*dev
= crtc
->base
.dev
;
10653 struct drm_plane
*primary
= crtc
->base
.primary
;
10655 mutex_lock(&dev
->struct_mutex
);
10656 intel_unpin_fb_obj(work
->old_fb
, primary
->state
);
10657 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10659 if (work
->flip_queued_req
)
10660 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10661 mutex_unlock(&dev
->struct_mutex
);
10663 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
10664 drm_framebuffer_unreference(work
->old_fb
);
10666 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
10667 atomic_dec(&crtc
->unpin_work_count
);
10672 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10673 struct drm_crtc
*crtc
)
10675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10676 struct intel_unpin_work
*work
;
10677 unsigned long flags
;
10679 /* Ignore early vblank irqs */
10680 if (intel_crtc
== NULL
)
10684 * This is called both by irq handlers and the reset code (to complete
10685 * lost pageflips) so needs the full irqsave spinlocks.
10687 spin_lock_irqsave(&dev
->event_lock
, flags
);
10688 work
= intel_crtc
->unpin_work
;
10690 /* Ensure we don't miss a work->pending update ... */
10693 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10694 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10698 page_flip_completed(intel_crtc
);
10700 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10703 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10706 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10708 do_intel_finish_page_flip(dev
, crtc
);
10711 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10714 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10716 do_intel_finish_page_flip(dev
, crtc
);
10719 /* Is 'a' after or equal to 'b'? */
10720 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10722 return !((a
- b
) & 0x80000000);
10725 static bool page_flip_finished(struct intel_crtc
*crtc
)
10727 struct drm_device
*dev
= crtc
->base
.dev
;
10728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10730 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10731 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10735 * The relevant registers doen't exist on pre-ctg.
10736 * As the flip done interrupt doesn't trigger for mmio
10737 * flips on gmch platforms, a flip count check isn't
10738 * really needed there. But since ctg has the registers,
10739 * include it in the check anyway.
10741 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10745 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10746 * used the same base address. In that case the mmio flip might
10747 * have completed, but the CS hasn't even executed the flip yet.
10749 * A flip count check isn't enough as the CS might have updated
10750 * the base address just after start of vblank, but before we
10751 * managed to process the interrupt. This means we'd complete the
10752 * CS flip too soon.
10754 * Combining both checks should get us a good enough result. It may
10755 * still happen that the CS flip has been executed, but has not
10756 * yet actually completed. But in case the base address is the same
10757 * anyway, we don't really care.
10759 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10760 crtc
->unpin_work
->gtt_offset
&&
10761 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
10762 crtc
->unpin_work
->flip_count
);
10765 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10768 struct intel_crtc
*intel_crtc
=
10769 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10770 unsigned long flags
;
10774 * This is called both by irq handlers and the reset code (to complete
10775 * lost pageflips) so needs the full irqsave spinlocks.
10777 * NB: An MMIO update of the plane base pointer will also
10778 * generate a page-flip completion irq, i.e. every modeset
10779 * is also accompanied by a spurious intel_prepare_page_flip().
10781 spin_lock_irqsave(&dev
->event_lock
, flags
);
10782 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10783 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10784 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10787 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
10789 /* Ensure that the work item is consistent when activating it ... */
10791 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
10792 /* and that it is marked active as soon as the irq could fire. */
10796 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10797 struct drm_crtc
*crtc
,
10798 struct drm_framebuffer
*fb
,
10799 struct drm_i915_gem_object
*obj
,
10800 struct drm_i915_gem_request
*req
,
10803 struct intel_engine_cs
*ring
= req
->ring
;
10804 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10808 ret
= intel_ring_begin(req
, 6);
10812 /* Can't queue multiple flips, so wait for the previous
10813 * one to finish before executing the next.
10815 if (intel_crtc
->plane
)
10816 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10818 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10819 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10820 intel_ring_emit(ring
, MI_NOOP
);
10821 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10822 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10823 intel_ring_emit(ring
, fb
->pitches
[0]);
10824 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10825 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10827 intel_mark_page_flip_active(intel_crtc
);
10831 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10832 struct drm_crtc
*crtc
,
10833 struct drm_framebuffer
*fb
,
10834 struct drm_i915_gem_object
*obj
,
10835 struct drm_i915_gem_request
*req
,
10838 struct intel_engine_cs
*ring
= req
->ring
;
10839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10843 ret
= intel_ring_begin(req
, 6);
10847 if (intel_crtc
->plane
)
10848 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10850 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10851 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10852 intel_ring_emit(ring
, MI_NOOP
);
10853 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10854 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10855 intel_ring_emit(ring
, fb
->pitches
[0]);
10856 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10857 intel_ring_emit(ring
, MI_NOOP
);
10859 intel_mark_page_flip_active(intel_crtc
);
10863 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10864 struct drm_crtc
*crtc
,
10865 struct drm_framebuffer
*fb
,
10866 struct drm_i915_gem_object
*obj
,
10867 struct drm_i915_gem_request
*req
,
10870 struct intel_engine_cs
*ring
= req
->ring
;
10871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10873 uint32_t pf
, pipesrc
;
10876 ret
= intel_ring_begin(req
, 4);
10880 /* i965+ uses the linear or tiled offsets from the
10881 * Display Registers (which do not change across a page-flip)
10882 * so we need only reprogram the base address.
10884 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10885 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10886 intel_ring_emit(ring
, fb
->pitches
[0]);
10887 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
10890 /* XXX Enabling the panel-fitter across page-flip is so far
10891 * untested on non-native modes, so ignore it for now.
10892 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10895 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10896 intel_ring_emit(ring
, pf
| pipesrc
);
10898 intel_mark_page_flip_active(intel_crtc
);
10902 static int intel_gen6_queue_flip(struct drm_device
*dev
,
10903 struct drm_crtc
*crtc
,
10904 struct drm_framebuffer
*fb
,
10905 struct drm_i915_gem_object
*obj
,
10906 struct drm_i915_gem_request
*req
,
10909 struct intel_engine_cs
*ring
= req
->ring
;
10910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10911 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10912 uint32_t pf
, pipesrc
;
10915 ret
= intel_ring_begin(req
, 4);
10919 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10920 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10921 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
10922 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10924 /* Contrary to the suggestions in the documentation,
10925 * "Enable Panel Fitter" does not seem to be required when page
10926 * flipping with a non-native mode, and worse causes a normal
10928 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10931 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10932 intel_ring_emit(ring
, pf
| pipesrc
);
10934 intel_mark_page_flip_active(intel_crtc
);
10938 static int intel_gen7_queue_flip(struct drm_device
*dev
,
10939 struct drm_crtc
*crtc
,
10940 struct drm_framebuffer
*fb
,
10941 struct drm_i915_gem_object
*obj
,
10942 struct drm_i915_gem_request
*req
,
10945 struct intel_engine_cs
*ring
= req
->ring
;
10946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10947 uint32_t plane_bit
= 0;
10950 switch (intel_crtc
->plane
) {
10952 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
10955 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
10958 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
10961 WARN_ONCE(1, "unknown plane in flip command\n");
10966 if (ring
->id
== RCS
) {
10969 * On Gen 8, SRM is now taking an extra dword to accommodate
10970 * 48bits addresses, and we need a NOOP for the batch size to
10978 * BSpec MI_DISPLAY_FLIP for IVB:
10979 * "The full packet must be contained within the same cache line."
10981 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10982 * cacheline, if we ever start emitting more commands before
10983 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10984 * then do the cacheline alignment, and finally emit the
10987 ret
= intel_ring_cacheline_align(req
);
10991 ret
= intel_ring_begin(req
, len
);
10995 /* Unmask the flip-done completion message. Note that the bspec says that
10996 * we should do this for both the BCS and RCS, and that we must not unmask
10997 * more than one flip event at any time (or ensure that one flip message
10998 * can be sent by waiting for flip-done prior to queueing new flips).
10999 * Experimentation says that BCS works despite DERRMR masking all
11000 * flip-done completion events and that unmasking all planes at once
11001 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11002 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11004 if (ring
->id
== RCS
) {
11005 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
11006 intel_ring_emit(ring
, DERRMR
);
11007 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11008 DERRMR_PIPEB_PRI_FLIP_DONE
|
11009 DERRMR_PIPEC_PRI_FLIP_DONE
));
11011 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8
|
11012 MI_SRM_LRM_GLOBAL_GTT
);
11014 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM
|
11015 MI_SRM_LRM_GLOBAL_GTT
);
11016 intel_ring_emit(ring
, DERRMR
);
11017 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
11018 if (IS_GEN8(dev
)) {
11019 intel_ring_emit(ring
, 0);
11020 intel_ring_emit(ring
, MI_NOOP
);
11024 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11025 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
11026 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11027 intel_ring_emit(ring
, (MI_NOOP
));
11029 intel_mark_page_flip_active(intel_crtc
);
11033 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
11034 struct drm_i915_gem_object
*obj
)
11037 * This is not being used for older platforms, because
11038 * non-availability of flip done interrupt forces us to use
11039 * CS flips. Older platforms derive flip done using some clever
11040 * tricks involving the flip_pending status bits and vblank irqs.
11041 * So using MMIO flips there would disrupt this mechanism.
11047 if (INTEL_INFO(ring
->dev
)->gen
< 5)
11050 if (i915
.use_mmio_flip
< 0)
11052 else if (i915
.use_mmio_flip
> 0)
11054 else if (i915
.enable_execlists
)
11057 return ring
!= i915_gem_request_get_ring(obj
->last_write_req
);
11060 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11062 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11064 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11065 const enum pipe pipe
= intel_crtc
->pipe
;
11068 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11069 ctl
&= ~PLANE_CTL_TILED_MASK
;
11070 switch (fb
->modifier
[0]) {
11071 case DRM_FORMAT_MOD_NONE
:
11073 case I915_FORMAT_MOD_X_TILED
:
11074 ctl
|= PLANE_CTL_TILED_X
;
11076 case I915_FORMAT_MOD_Y_TILED
:
11077 ctl
|= PLANE_CTL_TILED_Y
;
11079 case I915_FORMAT_MOD_Yf_TILED
:
11080 ctl
|= PLANE_CTL_TILED_YF
;
11083 MISSING_CASE(fb
->modifier
[0]);
11087 * The stride is either expressed as a multiple of 64 bytes chunks for
11088 * linear buffers or in number of tiles for tiled buffers.
11090 stride
= fb
->pitches
[0] /
11091 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
11095 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11096 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11098 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11099 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11101 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
11102 POSTING_READ(PLANE_SURF(pipe
, 0));
11105 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11107 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11109 struct intel_framebuffer
*intel_fb
=
11110 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11111 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11115 reg
= DSPCNTR(intel_crtc
->plane
);
11116 dspcntr
= I915_READ(reg
);
11118 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11119 dspcntr
|= DISPPLANE_TILED
;
11121 dspcntr
&= ~DISPPLANE_TILED
;
11123 I915_WRITE(reg
, dspcntr
);
11125 I915_WRITE(DSPSURF(intel_crtc
->plane
),
11126 intel_crtc
->unpin_work
->gtt_offset
);
11127 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11132 * XXX: This is the temporary way to update the plane registers until we get
11133 * around to using the usual plane update functions for MMIO flips
11135 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11137 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11139 intel_mark_page_flip_active(intel_crtc
);
11141 intel_pipe_update_start(intel_crtc
);
11143 if (INTEL_INFO(dev
)->gen
>= 9)
11144 skl_do_mmio_flip(intel_crtc
);
11146 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11147 ilk_do_mmio_flip(intel_crtc
);
11149 intel_pipe_update_end(intel_crtc
);
11152 static void intel_mmio_flip_work_func(struct work_struct
*work
)
11154 struct intel_mmio_flip
*mmio_flip
=
11155 container_of(work
, struct intel_mmio_flip
, work
);
11157 if (mmio_flip
->req
)
11158 WARN_ON(__i915_wait_request(mmio_flip
->req
,
11159 mmio_flip
->crtc
->reset_counter
,
11161 &mmio_flip
->i915
->rps
.mmioflips
));
11163 intel_do_mmio_flip(mmio_flip
->crtc
);
11165 i915_gem_request_unreference__unlocked(mmio_flip
->req
);
11169 static int intel_queue_mmio_flip(struct drm_device
*dev
,
11170 struct drm_crtc
*crtc
,
11171 struct drm_framebuffer
*fb
,
11172 struct drm_i915_gem_object
*obj
,
11173 struct intel_engine_cs
*ring
,
11176 struct intel_mmio_flip
*mmio_flip
;
11178 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11179 if (mmio_flip
== NULL
)
11182 mmio_flip
->i915
= to_i915(dev
);
11183 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11184 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11186 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11187 schedule_work(&mmio_flip
->work
);
11192 static int intel_default_queue_flip(struct drm_device
*dev
,
11193 struct drm_crtc
*crtc
,
11194 struct drm_framebuffer
*fb
,
11195 struct drm_i915_gem_object
*obj
,
11196 struct drm_i915_gem_request
*req
,
11202 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11203 struct drm_crtc
*crtc
)
11205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11207 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11210 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11213 if (atomic_read(&work
->pending
) < INTEL_FLIP_PENDING
)
11216 if (!work
->enable_stall_check
)
11219 if (work
->flip_ready_vblank
== 0) {
11220 if (work
->flip_queued_req
&&
11221 !i915_gem_request_completed(work
->flip_queued_req
, true))
11224 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11227 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11230 /* Potential stall - if we see that the flip has happened,
11231 * assume a missed interrupt. */
11232 if (INTEL_INFO(dev
)->gen
>= 4)
11233 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11235 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11237 /* There is a potential issue here with a false positive after a flip
11238 * to the same address. We could address this by checking for a
11239 * non-incrementing frame counter.
11241 return addr
== work
->gtt_offset
;
11244 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
11246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11247 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11249 struct intel_unpin_work
*work
;
11251 WARN_ON(!in_interrupt());
11256 spin_lock(&dev
->event_lock
);
11257 work
= intel_crtc
->unpin_work
;
11258 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11259 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11260 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11261 page_flip_completed(intel_crtc
);
11264 if (work
!= NULL
&&
11265 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11266 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
11267 spin_unlock(&dev
->event_lock
);
11270 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11271 struct drm_framebuffer
*fb
,
11272 struct drm_pending_vblank_event
*event
,
11273 uint32_t page_flip_flags
)
11275 struct drm_device
*dev
= crtc
->dev
;
11276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11277 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11278 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11279 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11280 struct drm_plane
*primary
= crtc
->primary
;
11281 enum pipe pipe
= intel_crtc
->pipe
;
11282 struct intel_unpin_work
*work
;
11283 struct intel_engine_cs
*ring
;
11285 struct drm_i915_gem_request
*request
= NULL
;
11289 * drm_mode_page_flip_ioctl() should already catch this, but double
11290 * check to be safe. In the future we may enable pageflipping from
11291 * a disabled primary plane.
11293 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11296 /* Can't change pixel format via MI display flips. */
11297 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11301 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11302 * Note that pitch changes could also affect these register.
11304 if (INTEL_INFO(dev
)->gen
> 3 &&
11305 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11306 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11309 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11312 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11316 work
->event
= event
;
11318 work
->old_fb
= old_fb
;
11319 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11321 ret
= drm_crtc_vblank_get(crtc
);
11325 /* We borrow the event spin lock for protecting unpin_work */
11326 spin_lock_irq(&dev
->event_lock
);
11327 if (intel_crtc
->unpin_work
) {
11328 /* Before declaring the flip queue wedged, check if
11329 * the hardware completed the operation behind our backs.
11331 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11332 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11333 page_flip_completed(intel_crtc
);
11335 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11336 spin_unlock_irq(&dev
->event_lock
);
11338 drm_crtc_vblank_put(crtc
);
11343 intel_crtc
->unpin_work
= work
;
11344 spin_unlock_irq(&dev
->event_lock
);
11346 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11347 flush_workqueue(dev_priv
->wq
);
11349 /* Reference the objects for the scheduled work. */
11350 drm_framebuffer_reference(work
->old_fb
);
11351 drm_gem_object_reference(&obj
->base
);
11353 crtc
->primary
->fb
= fb
;
11354 update_state_fb(crtc
->primary
);
11356 work
->pending_flip_obj
= obj
;
11358 ret
= i915_mutex_lock_interruptible(dev
);
11362 atomic_inc(&intel_crtc
->unpin_work_count
);
11363 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11365 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11366 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
11368 if (IS_VALLEYVIEW(dev
)) {
11369 ring
= &dev_priv
->ring
[BCS
];
11370 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11371 /* vlv: DISPLAY_FLIP fails to change tiling */
11373 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11374 ring
= &dev_priv
->ring
[BCS
];
11375 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11376 ring
= i915_gem_request_get_ring(obj
->last_write_req
);
11377 if (ring
== NULL
|| ring
->id
!= RCS
)
11378 ring
= &dev_priv
->ring
[BCS
];
11380 ring
= &dev_priv
->ring
[RCS
];
11383 mmio_flip
= use_mmio_flip(ring
, obj
);
11385 /* When using CS flips, we want to emit semaphores between rings.
11386 * However, when using mmio flips we will create a task to do the
11387 * synchronisation, so all we want here is to pin the framebuffer
11388 * into the display plane and skip any waits.
11390 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11391 crtc
->primary
->state
,
11392 mmio_flip
? i915_gem_request_get_ring(obj
->last_write_req
) : ring
, &request
);
11394 goto cleanup_pending
;
11396 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
11397 + intel_crtc
->dspaddr_offset
;
11400 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11403 goto cleanup_unpin
;
11405 i915_gem_request_assign(&work
->flip_queued_req
,
11406 obj
->last_write_req
);
11409 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &request
);
11411 goto cleanup_unpin
;
11414 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11417 goto cleanup_unpin
;
11419 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11423 i915_add_request_no_flush(request
);
11425 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11426 work
->enable_stall_check
= true;
11428 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11429 to_intel_plane(primary
)->frontbuffer_bit
);
11430 mutex_unlock(&dev
->struct_mutex
);
11432 intel_fbc_disable_crtc(intel_crtc
);
11433 intel_frontbuffer_flip_prepare(dev
,
11434 to_intel_plane(primary
)->frontbuffer_bit
);
11436 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11441 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11444 i915_gem_request_cancel(request
);
11445 atomic_dec(&intel_crtc
->unpin_work_count
);
11446 mutex_unlock(&dev
->struct_mutex
);
11448 crtc
->primary
->fb
= old_fb
;
11449 update_state_fb(crtc
->primary
);
11451 drm_gem_object_unreference_unlocked(&obj
->base
);
11452 drm_framebuffer_unreference(work
->old_fb
);
11454 spin_lock_irq(&dev
->event_lock
);
11455 intel_crtc
->unpin_work
= NULL
;
11456 spin_unlock_irq(&dev
->event_lock
);
11458 drm_crtc_vblank_put(crtc
);
11463 struct drm_atomic_state
*state
;
11464 struct drm_plane_state
*plane_state
;
11467 state
= drm_atomic_state_alloc(dev
);
11470 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11473 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11474 ret
= PTR_ERR_OR_ZERO(plane_state
);
11476 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11478 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11480 ret
= drm_atomic_commit(state
);
11483 if (ret
== -EDEADLK
) {
11484 drm_modeset_backoff(state
->acquire_ctx
);
11485 drm_atomic_state_clear(state
);
11490 drm_atomic_state_free(state
);
11492 if (ret
== 0 && event
) {
11493 spin_lock_irq(&dev
->event_lock
);
11494 drm_send_vblank_event(dev
, pipe
, event
);
11495 spin_unlock_irq(&dev
->event_lock
);
11503 * intel_wm_need_update - Check whether watermarks need updating
11504 * @plane: drm plane
11505 * @state: new plane state
11507 * Check current plane state versus the new one to determine whether
11508 * watermarks need to be recalculated.
11510 * Returns true or false.
11512 static bool intel_wm_need_update(struct drm_plane
*plane
,
11513 struct drm_plane_state
*state
)
11515 /* Update watermarks on tiling changes. */
11516 if (!plane
->state
->fb
|| !state
->fb
||
11517 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
11518 plane
->state
->rotation
!= state
->rotation
)
11521 if (plane
->state
->crtc_w
!= state
->crtc_w
)
11527 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11528 struct drm_plane_state
*plane_state
)
11530 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11531 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11532 struct drm_plane
*plane
= plane_state
->plane
;
11533 struct drm_device
*dev
= crtc
->dev
;
11534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11535 struct intel_plane_state
*old_plane_state
=
11536 to_intel_plane_state(plane
->state
);
11537 int idx
= intel_crtc
->base
.base
.id
, ret
;
11538 int i
= drm_plane_index(plane
);
11539 bool mode_changed
= needs_modeset(crtc_state
);
11540 bool was_crtc_enabled
= crtc
->state
->active
;
11541 bool is_crtc_enabled
= crtc_state
->active
;
11543 bool turn_off
, turn_on
, visible
, was_visible
;
11544 struct drm_framebuffer
*fb
= plane_state
->fb
;
11546 if (crtc_state
&& INTEL_INFO(dev
)->gen
>= 9 &&
11547 plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11548 ret
= skl_update_scaler_plane(
11549 to_intel_crtc_state(crtc_state
),
11550 to_intel_plane_state(plane_state
));
11556 * Disabling a plane is always okay; we just need to update
11557 * fb tracking in a special way since cleanup_fb() won't
11558 * get called by the plane helpers.
11560 if (old_plane_state
->base
.fb
&& !fb
)
11561 intel_crtc
->atomic
.disabled_planes
|= 1 << i
;
11563 was_visible
= old_plane_state
->visible
;
11564 visible
= to_intel_plane_state(plane_state
)->visible
;
11566 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11567 was_visible
= false;
11569 if (!is_crtc_enabled
&& WARN_ON(visible
))
11572 if (!was_visible
&& !visible
)
11575 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11576 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11578 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx
,
11579 plane
->base
.id
, fb
? fb
->base
.id
: -1);
11581 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11582 plane
->base
.id
, was_visible
, visible
,
11583 turn_off
, turn_on
, mode_changed
);
11586 intel_crtc
->atomic
.update_wm_pre
= true;
11587 /* must disable cxsr around plane enable/disable */
11588 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11589 intel_crtc
->atomic
.disable_cxsr
= true;
11590 /* to potentially re-enable cxsr */
11591 intel_crtc
->atomic
.wait_vblank
= true;
11592 intel_crtc
->atomic
.update_wm_post
= true;
11594 } else if (turn_off
) {
11595 intel_crtc
->atomic
.update_wm_post
= true;
11596 /* must disable cxsr around plane enable/disable */
11597 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11598 if (is_crtc_enabled
)
11599 intel_crtc
->atomic
.wait_vblank
= true;
11600 intel_crtc
->atomic
.disable_cxsr
= true;
11602 } else if (intel_wm_need_update(plane
, plane_state
)) {
11603 intel_crtc
->atomic
.update_wm_pre
= true;
11606 if (visible
|| was_visible
)
11607 intel_crtc
->atomic
.fb_bits
|=
11608 to_intel_plane(plane
)->frontbuffer_bit
;
11610 switch (plane
->type
) {
11611 case DRM_PLANE_TYPE_PRIMARY
:
11612 intel_crtc
->atomic
.wait_for_flips
= true;
11613 intel_crtc
->atomic
.pre_disable_primary
= turn_off
;
11614 intel_crtc
->atomic
.post_enable_primary
= turn_on
;
11618 * FIXME: Actually if we will still have any other
11619 * plane enabled on the pipe we could let IPS enabled
11620 * still, but for now lets consider that when we make
11621 * primary invisible by setting DSPCNTR to 0 on
11622 * update_primary_plane function IPS needs to be
11625 intel_crtc
->atomic
.disable_ips
= true;
11627 intel_crtc
->atomic
.disable_fbc
= true;
11631 * FBC does not work on some platforms for rotated
11632 * planes, so disable it when rotation is not 0 and
11633 * update it when rotation is set back to 0.
11635 * FIXME: This is redundant with the fbc update done in
11636 * the primary plane enable function except that that
11637 * one is done too late. We eventually need to unify
11642 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11643 dev_priv
->fbc
.crtc
== intel_crtc
&&
11644 plane_state
->rotation
!= BIT(DRM_ROTATE_0
))
11645 intel_crtc
->atomic
.disable_fbc
= true;
11648 * BDW signals flip done immediately if the plane
11649 * is disabled, even if the plane enable is already
11650 * armed to occur at the next vblank :(
11652 if (turn_on
&& IS_BROADWELL(dev
))
11653 intel_crtc
->atomic
.wait_vblank
= true;
11655 intel_crtc
->atomic
.update_fbc
|= visible
|| mode_changed
;
11657 case DRM_PLANE_TYPE_CURSOR
:
11659 case DRM_PLANE_TYPE_OVERLAY
:
11660 if (turn_off
&& !mode_changed
) {
11661 intel_crtc
->atomic
.wait_vblank
= true;
11662 intel_crtc
->atomic
.update_sprite_watermarks
|=
11669 static bool encoders_cloneable(const struct intel_encoder
*a
,
11670 const struct intel_encoder
*b
)
11672 /* masks could be asymmetric, so check both ways */
11673 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11674 b
->cloneable
& (1 << a
->type
));
11677 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11678 struct intel_crtc
*crtc
,
11679 struct intel_encoder
*encoder
)
11681 struct intel_encoder
*source_encoder
;
11682 struct drm_connector
*connector
;
11683 struct drm_connector_state
*connector_state
;
11686 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11687 if (connector_state
->crtc
!= &crtc
->base
)
11691 to_intel_encoder(connector_state
->best_encoder
);
11692 if (!encoders_cloneable(encoder
, source_encoder
))
11699 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11700 struct intel_crtc
*crtc
)
11702 struct intel_encoder
*encoder
;
11703 struct drm_connector
*connector
;
11704 struct drm_connector_state
*connector_state
;
11707 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11708 if (connector_state
->crtc
!= &crtc
->base
)
11711 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11712 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11719 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11720 struct drm_crtc_state
*crtc_state
)
11722 struct drm_device
*dev
= crtc
->dev
;
11723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11724 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11725 struct intel_crtc_state
*pipe_config
=
11726 to_intel_crtc_state(crtc_state
);
11727 struct drm_atomic_state
*state
= crtc_state
->state
;
11729 bool mode_changed
= needs_modeset(crtc_state
);
11731 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
11732 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11736 if (mode_changed
&& !crtc_state
->active
)
11737 intel_crtc
->atomic
.update_wm_post
= true;
11739 if (mode_changed
&& crtc_state
->enable
&&
11740 dev_priv
->display
.crtc_compute_clock
&&
11741 !WARN_ON(pipe_config
->shared_dpll
!= DPLL_ID_PRIVATE
)) {
11742 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11749 if (INTEL_INFO(dev
)->gen
>= 9) {
11751 ret
= skl_update_scaler_crtc(pipe_config
);
11754 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
11761 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11762 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11763 .load_lut
= intel_crtc_load_lut
,
11764 .atomic_begin
= intel_begin_crtc_commit
,
11765 .atomic_flush
= intel_finish_crtc_commit
,
11766 .atomic_check
= intel_crtc_atomic_check
,
11769 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11771 struct intel_connector
*connector
;
11773 for_each_intel_connector(dev
, connector
) {
11774 if (connector
->base
.encoder
) {
11775 connector
->base
.state
->best_encoder
=
11776 connector
->base
.encoder
;
11777 connector
->base
.state
->crtc
=
11778 connector
->base
.encoder
->crtc
;
11780 connector
->base
.state
->best_encoder
= NULL
;
11781 connector
->base
.state
->crtc
= NULL
;
11787 connected_sink_compute_bpp(struct intel_connector
*connector
,
11788 struct intel_crtc_state
*pipe_config
)
11790 int bpp
= pipe_config
->pipe_bpp
;
11792 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11793 connector
->base
.base
.id
,
11794 connector
->base
.name
);
11796 /* Don't use an invalid EDID bpc value */
11797 if (connector
->base
.display_info
.bpc
&&
11798 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11799 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11800 bpp
, connector
->base
.display_info
.bpc
*3);
11801 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11804 /* Clamp bpp to 8 on screens without EDID 1.4 */
11805 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11806 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11808 pipe_config
->pipe_bpp
= 24;
11813 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11814 struct intel_crtc_state
*pipe_config
)
11816 struct drm_device
*dev
= crtc
->base
.dev
;
11817 struct drm_atomic_state
*state
;
11818 struct drm_connector
*connector
;
11819 struct drm_connector_state
*connector_state
;
11822 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11824 else if (INTEL_INFO(dev
)->gen
>= 5)
11830 pipe_config
->pipe_bpp
= bpp
;
11832 state
= pipe_config
->base
.state
;
11834 /* Clamp display bpp to EDID value */
11835 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11836 if (connector_state
->crtc
!= &crtc
->base
)
11839 connected_sink_compute_bpp(to_intel_connector(connector
),
11846 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11848 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11849 "type: 0x%x flags: 0x%x\n",
11851 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11852 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11853 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11854 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11857 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11858 struct intel_crtc_state
*pipe_config
,
11859 const char *context
)
11861 struct drm_device
*dev
= crtc
->base
.dev
;
11862 struct drm_plane
*plane
;
11863 struct intel_plane
*intel_plane
;
11864 struct intel_plane_state
*state
;
11865 struct drm_framebuffer
*fb
;
11867 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11868 context
, pipe_config
, pipe_name(crtc
->pipe
));
11870 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11871 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11872 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11873 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11874 pipe_config
->has_pch_encoder
,
11875 pipe_config
->fdi_lanes
,
11876 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11877 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11878 pipe_config
->fdi_m_n
.tu
);
11879 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11880 pipe_config
->has_dp_encoder
,
11881 pipe_config
->lane_count
,
11882 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11883 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11884 pipe_config
->dp_m_n
.tu
);
11886 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11887 pipe_config
->has_dp_encoder
,
11888 pipe_config
->lane_count
,
11889 pipe_config
->dp_m2_n2
.gmch_m
,
11890 pipe_config
->dp_m2_n2
.gmch_n
,
11891 pipe_config
->dp_m2_n2
.link_m
,
11892 pipe_config
->dp_m2_n2
.link_n
,
11893 pipe_config
->dp_m2_n2
.tu
);
11895 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11896 pipe_config
->has_audio
,
11897 pipe_config
->has_infoframe
);
11899 DRM_DEBUG_KMS("requested mode:\n");
11900 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11901 DRM_DEBUG_KMS("adjusted mode:\n");
11902 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11903 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11904 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11905 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11906 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11907 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11909 pipe_config
->scaler_state
.scaler_users
,
11910 pipe_config
->scaler_state
.scaler_id
);
11911 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11912 pipe_config
->gmch_pfit
.control
,
11913 pipe_config
->gmch_pfit
.pgm_ratios
,
11914 pipe_config
->gmch_pfit
.lvds_border_bits
);
11915 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11916 pipe_config
->pch_pfit
.pos
,
11917 pipe_config
->pch_pfit
.size
,
11918 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11919 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11920 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11922 if (IS_BROXTON(dev
)) {
11923 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11924 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11925 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11926 pipe_config
->ddi_pll_sel
,
11927 pipe_config
->dpll_hw_state
.ebb0
,
11928 pipe_config
->dpll_hw_state
.ebb4
,
11929 pipe_config
->dpll_hw_state
.pll0
,
11930 pipe_config
->dpll_hw_state
.pll1
,
11931 pipe_config
->dpll_hw_state
.pll2
,
11932 pipe_config
->dpll_hw_state
.pll3
,
11933 pipe_config
->dpll_hw_state
.pll6
,
11934 pipe_config
->dpll_hw_state
.pll8
,
11935 pipe_config
->dpll_hw_state
.pll9
,
11936 pipe_config
->dpll_hw_state
.pll10
,
11937 pipe_config
->dpll_hw_state
.pcsdw12
);
11938 } else if (IS_SKYLAKE(dev
)) {
11939 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11940 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11941 pipe_config
->ddi_pll_sel
,
11942 pipe_config
->dpll_hw_state
.ctrl1
,
11943 pipe_config
->dpll_hw_state
.cfgcr1
,
11944 pipe_config
->dpll_hw_state
.cfgcr2
);
11945 } else if (HAS_DDI(dev
)) {
11946 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11947 pipe_config
->ddi_pll_sel
,
11948 pipe_config
->dpll_hw_state
.wrpll
);
11950 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11951 "fp0: 0x%x, fp1: 0x%x\n",
11952 pipe_config
->dpll_hw_state
.dpll
,
11953 pipe_config
->dpll_hw_state
.dpll_md
,
11954 pipe_config
->dpll_hw_state
.fp0
,
11955 pipe_config
->dpll_hw_state
.fp1
);
11958 DRM_DEBUG_KMS("planes on this crtc\n");
11959 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11960 intel_plane
= to_intel_plane(plane
);
11961 if (intel_plane
->pipe
!= crtc
->pipe
)
11964 state
= to_intel_plane_state(plane
->state
);
11965 fb
= state
->base
.fb
;
11967 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11968 "disabled, scaler_id = %d\n",
11969 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11970 plane
->base
.id
, intel_plane
->pipe
,
11971 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
11972 drm_plane_index(plane
), state
->scaler_id
);
11976 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11977 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11978 plane
->base
.id
, intel_plane
->pipe
,
11979 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
11980 drm_plane_index(plane
));
11981 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11982 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
11983 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11985 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
11986 drm_rect_width(&state
->src
) >> 16,
11987 drm_rect_height(&state
->src
) >> 16,
11988 state
->dst
.x1
, state
->dst
.y1
,
11989 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
11993 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11995 struct drm_device
*dev
= state
->dev
;
11996 struct intel_encoder
*encoder
;
11997 struct drm_connector
*connector
;
11998 struct drm_connector_state
*connector_state
;
11999 unsigned int used_ports
= 0;
12003 * Walk the connector list instead of the encoder
12004 * list to detect the problem on ddi platforms
12005 * where there's just one encoder per digital port.
12007 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12008 if (!connector_state
->best_encoder
)
12011 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12013 WARN_ON(!connector_state
->crtc
);
12015 switch (encoder
->type
) {
12016 unsigned int port_mask
;
12017 case INTEL_OUTPUT_UNKNOWN
:
12018 if (WARN_ON(!HAS_DDI(dev
)))
12020 case INTEL_OUTPUT_DISPLAYPORT
:
12021 case INTEL_OUTPUT_HDMI
:
12022 case INTEL_OUTPUT_EDP
:
12023 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12025 /* the same port mustn't appear more than once */
12026 if (used_ports
& port_mask
)
12029 used_ports
|= port_mask
;
12039 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12041 struct drm_crtc_state tmp_state
;
12042 struct intel_crtc_scaler_state scaler_state
;
12043 struct intel_dpll_hw_state dpll_hw_state
;
12044 enum intel_dpll_id shared_dpll
;
12045 uint32_t ddi_pll_sel
;
12048 /* FIXME: before the switch to atomic started, a new pipe_config was
12049 * kzalloc'd. Code that depends on any field being zero should be
12050 * fixed, so that the crtc_state can be safely duplicated. For now,
12051 * only fields that are know to not cause problems are preserved. */
12053 tmp_state
= crtc_state
->base
;
12054 scaler_state
= crtc_state
->scaler_state
;
12055 shared_dpll
= crtc_state
->shared_dpll
;
12056 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12057 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12058 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12060 memset(crtc_state
, 0, sizeof *crtc_state
);
12062 crtc_state
->base
= tmp_state
;
12063 crtc_state
->scaler_state
= scaler_state
;
12064 crtc_state
->shared_dpll
= shared_dpll
;
12065 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12066 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12067 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12071 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12072 struct intel_crtc_state
*pipe_config
)
12074 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12075 struct intel_encoder
*encoder
;
12076 struct drm_connector
*connector
;
12077 struct drm_connector_state
*connector_state
;
12078 int base_bpp
, ret
= -EINVAL
;
12082 clear_intel_crtc_state(pipe_config
);
12084 pipe_config
->cpu_transcoder
=
12085 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12088 * Sanitize sync polarity flags based on requested ones. If neither
12089 * positive or negative polarity is requested, treat this as meaning
12090 * negative polarity.
12092 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12093 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12094 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12096 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12097 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12098 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12100 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12106 * Determine the real pipe dimensions. Note that stereo modes can
12107 * increase the actual pipe size due to the frame doubling and
12108 * insertion of additional space for blanks between the frame. This
12109 * is stored in the crtc timings. We use the requested mode to do this
12110 * computation to clearly distinguish it from the adjusted mode, which
12111 * can be changed by the connectors in the below retry loop.
12113 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12114 &pipe_config
->pipe_src_w
,
12115 &pipe_config
->pipe_src_h
);
12118 /* Ensure the port clock defaults are reset when retrying. */
12119 pipe_config
->port_clock
= 0;
12120 pipe_config
->pixel_multiplier
= 1;
12122 /* Fill in default crtc timings, allow encoders to overwrite them. */
12123 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12124 CRTC_STEREO_DOUBLE
);
12126 /* Pass our mode to the connectors and the CRTC to give them a chance to
12127 * adjust it according to limitations or connector properties, and also
12128 * a chance to reject the mode entirely.
12130 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12131 if (connector_state
->crtc
!= crtc
)
12134 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12136 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12137 DRM_DEBUG_KMS("Encoder config failure\n");
12142 /* Set default port clock if not overwritten by the encoder. Needs to be
12143 * done afterwards in case the encoder adjusts the mode. */
12144 if (!pipe_config
->port_clock
)
12145 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12146 * pipe_config
->pixel_multiplier
;
12148 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12150 DRM_DEBUG_KMS("CRTC fixup failed\n");
12154 if (ret
== RETRY
) {
12155 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12160 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12162 goto encoder_retry
;
12165 /* Dithering seems to not pass-through bits correctly when it should, so
12166 * only enable it on 6bpc panels. */
12167 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12168 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12169 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12176 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12178 struct drm_crtc
*crtc
;
12179 struct drm_crtc_state
*crtc_state
;
12182 /* Double check state. */
12183 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12184 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12186 /* Update hwmode for vblank functions */
12187 if (crtc
->state
->active
)
12188 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12190 crtc
->hwmode
.crtc_clock
= 0;
12194 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12198 if (clock1
== clock2
)
12201 if (!clock1
|| !clock2
)
12204 diff
= abs(clock1
- clock2
);
12206 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12212 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12213 list_for_each_entry((intel_crtc), \
12214 &(dev)->mode_config.crtc_list, \
12216 if (mask & (1 <<(intel_crtc)->pipe))
12220 intel_compare_m_n(unsigned int m
, unsigned int n
,
12221 unsigned int m2
, unsigned int n2
,
12224 if (m
== m2
&& n
== n2
)
12227 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12230 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12237 } else if (m
< m2
) {
12244 return m
== m2
&& n
== n2
;
12248 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12249 struct intel_link_m_n
*m2_n2
,
12252 if (m_n
->tu
== m2_n2
->tu
&&
12253 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12254 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12255 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12256 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12267 intel_pipe_config_compare(struct drm_device
*dev
,
12268 struct intel_crtc_state
*current_config
,
12269 struct intel_crtc_state
*pipe_config
,
12274 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12277 DRM_ERROR(fmt, ##__VA_ARGS__); \
12279 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12282 #define PIPE_CONF_CHECK_X(name) \
12283 if (current_config->name != pipe_config->name) { \
12284 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12285 "(expected 0x%08x, found 0x%08x)\n", \
12286 current_config->name, \
12287 pipe_config->name); \
12291 #define PIPE_CONF_CHECK_I(name) \
12292 if (current_config->name != pipe_config->name) { \
12293 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12294 "(expected %i, found %i)\n", \
12295 current_config->name, \
12296 pipe_config->name); \
12300 #define PIPE_CONF_CHECK_M_N(name) \
12301 if (!intel_compare_link_m_n(¤t_config->name, \
12302 &pipe_config->name,\
12304 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12305 "(expected tu %i gmch %i/%i link %i/%i, " \
12306 "found tu %i, gmch %i/%i link %i/%i)\n", \
12307 current_config->name.tu, \
12308 current_config->name.gmch_m, \
12309 current_config->name.gmch_n, \
12310 current_config->name.link_m, \
12311 current_config->name.link_n, \
12312 pipe_config->name.tu, \
12313 pipe_config->name.gmch_m, \
12314 pipe_config->name.gmch_n, \
12315 pipe_config->name.link_m, \
12316 pipe_config->name.link_n); \
12320 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12321 if (!intel_compare_link_m_n(¤t_config->name, \
12322 &pipe_config->name, adjust) && \
12323 !intel_compare_link_m_n(¤t_config->alt_name, \
12324 &pipe_config->name, adjust)) { \
12325 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12326 "(expected tu %i gmch %i/%i link %i/%i, " \
12327 "or tu %i gmch %i/%i link %i/%i, " \
12328 "found tu %i, gmch %i/%i link %i/%i)\n", \
12329 current_config->name.tu, \
12330 current_config->name.gmch_m, \
12331 current_config->name.gmch_n, \
12332 current_config->name.link_m, \
12333 current_config->name.link_n, \
12334 current_config->alt_name.tu, \
12335 current_config->alt_name.gmch_m, \
12336 current_config->alt_name.gmch_n, \
12337 current_config->alt_name.link_m, \
12338 current_config->alt_name.link_n, \
12339 pipe_config->name.tu, \
12340 pipe_config->name.gmch_m, \
12341 pipe_config->name.gmch_n, \
12342 pipe_config->name.link_m, \
12343 pipe_config->name.link_n); \
12347 /* This is required for BDW+ where there is only one set of registers for
12348 * switching between high and low RR.
12349 * This macro can be used whenever a comparison has to be made between one
12350 * hw state and multiple sw state variables.
12352 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12353 if ((current_config->name != pipe_config->name) && \
12354 (current_config->alt_name != pipe_config->name)) { \
12355 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12356 "(expected %i or %i, found %i)\n", \
12357 current_config->name, \
12358 current_config->alt_name, \
12359 pipe_config->name); \
12363 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12364 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12365 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12366 "(expected %i, found %i)\n", \
12367 current_config->name & (mask), \
12368 pipe_config->name & (mask)); \
12372 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12373 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12374 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12375 "(expected %i, found %i)\n", \
12376 current_config->name, \
12377 pipe_config->name); \
12381 #define PIPE_CONF_QUIRK(quirk) \
12382 ((current_config->quirks | pipe_config->quirks) & (quirk))
12384 PIPE_CONF_CHECK_I(cpu_transcoder
);
12386 PIPE_CONF_CHECK_I(has_pch_encoder
);
12387 PIPE_CONF_CHECK_I(fdi_lanes
);
12388 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12390 PIPE_CONF_CHECK_I(has_dp_encoder
);
12391 PIPE_CONF_CHECK_I(lane_count
);
12393 if (INTEL_INFO(dev
)->gen
< 8) {
12394 PIPE_CONF_CHECK_M_N(dp_m_n
);
12396 PIPE_CONF_CHECK_I(has_drrs
);
12397 if (current_config
->has_drrs
)
12398 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12400 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12402 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12403 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12404 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12405 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12406 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12407 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12409 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12410 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12411 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12412 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12413 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12414 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12416 PIPE_CONF_CHECK_I(pixel_multiplier
);
12417 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12418 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12419 IS_VALLEYVIEW(dev
))
12420 PIPE_CONF_CHECK_I(limited_color_range
);
12421 PIPE_CONF_CHECK_I(has_infoframe
);
12423 PIPE_CONF_CHECK_I(has_audio
);
12425 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12426 DRM_MODE_FLAG_INTERLACE
);
12428 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12429 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12430 DRM_MODE_FLAG_PHSYNC
);
12431 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12432 DRM_MODE_FLAG_NHSYNC
);
12433 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12434 DRM_MODE_FLAG_PVSYNC
);
12435 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12436 DRM_MODE_FLAG_NVSYNC
);
12439 PIPE_CONF_CHECK_I(pipe_src_w
);
12440 PIPE_CONF_CHECK_I(pipe_src_h
);
12442 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12443 /* pfit ratios are autocomputed by the hw on gen4+ */
12444 if (INTEL_INFO(dev
)->gen
< 4)
12445 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
12446 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12448 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12449 if (current_config
->pch_pfit
.enabled
) {
12450 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12451 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12454 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12456 /* BDW+ don't expose a synchronous way to read the state */
12457 if (IS_HASWELL(dev
))
12458 PIPE_CONF_CHECK_I(ips_enabled
);
12460 PIPE_CONF_CHECK_I(double_wide
);
12462 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12464 PIPE_CONF_CHECK_I(shared_dpll
);
12465 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12466 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12467 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12468 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12469 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12470 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12471 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12472 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12474 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12475 PIPE_CONF_CHECK_I(pipe_bpp
);
12477 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12478 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12480 #undef PIPE_CONF_CHECK_X
12481 #undef PIPE_CONF_CHECK_I
12482 #undef PIPE_CONF_CHECK_I_ALT
12483 #undef PIPE_CONF_CHECK_FLAGS
12484 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12485 #undef PIPE_CONF_QUIRK
12486 #undef INTEL_ERR_OR_DBG_KMS
12491 static void check_wm_state(struct drm_device
*dev
)
12493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12494 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12495 struct intel_crtc
*intel_crtc
;
12498 if (INTEL_INFO(dev
)->gen
< 9)
12501 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12502 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12504 for_each_intel_crtc(dev
, intel_crtc
) {
12505 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12506 const enum pipe pipe
= intel_crtc
->pipe
;
12508 if (!intel_crtc
->active
)
12512 for_each_plane(dev_priv
, pipe
, plane
) {
12513 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12514 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12516 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12519 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12520 "(expected (%u,%u), found (%u,%u))\n",
12521 pipe_name(pipe
), plane
+ 1,
12522 sw_entry
->start
, sw_entry
->end
,
12523 hw_entry
->start
, hw_entry
->end
);
12527 hw_entry
= &hw_ddb
.cursor
[pipe
];
12528 sw_entry
= &sw_ddb
->cursor
[pipe
];
12530 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12533 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12534 "(expected (%u,%u), found (%u,%u))\n",
12536 sw_entry
->start
, sw_entry
->end
,
12537 hw_entry
->start
, hw_entry
->end
);
12542 check_connector_state(struct drm_device
*dev
,
12543 struct drm_atomic_state
*old_state
)
12545 struct drm_connector_state
*old_conn_state
;
12546 struct drm_connector
*connector
;
12549 for_each_connector_in_state(old_state
, connector
, old_conn_state
, i
) {
12550 struct drm_encoder
*encoder
= connector
->encoder
;
12551 struct drm_connector_state
*state
= connector
->state
;
12553 /* This also checks the encoder/connector hw state with the
12554 * ->get_hw_state callbacks. */
12555 intel_connector_check_state(to_intel_connector(connector
));
12557 I915_STATE_WARN(state
->best_encoder
!= encoder
,
12558 "connector's atomic encoder doesn't match legacy encoder\n");
12563 check_encoder_state(struct drm_device
*dev
)
12565 struct intel_encoder
*encoder
;
12566 struct intel_connector
*connector
;
12568 for_each_intel_encoder(dev
, encoder
) {
12569 bool enabled
= false;
12572 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12573 encoder
->base
.base
.id
,
12574 encoder
->base
.name
);
12576 for_each_intel_connector(dev
, connector
) {
12577 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
12581 I915_STATE_WARN(connector
->base
.state
->crtc
!=
12582 encoder
->base
.crtc
,
12583 "connector's crtc doesn't match encoder crtc\n");
12586 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12587 "encoder's enabled state mismatch "
12588 "(expected %i, found %i)\n",
12589 !!encoder
->base
.crtc
, enabled
);
12591 if (!encoder
->base
.crtc
) {
12594 active
= encoder
->get_hw_state(encoder
, &pipe
);
12595 I915_STATE_WARN(active
,
12596 "encoder detached but still enabled on pipe %c.\n",
12603 check_crtc_state(struct drm_device
*dev
, struct drm_atomic_state
*old_state
)
12605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12606 struct intel_encoder
*encoder
;
12607 struct drm_crtc_state
*old_crtc_state
;
12608 struct drm_crtc
*crtc
;
12611 for_each_crtc_in_state(old_state
, crtc
, old_crtc_state
, i
) {
12612 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12613 struct intel_crtc_state
*pipe_config
, *sw_config
;
12616 if (!needs_modeset(crtc
->state
))
12619 __drm_atomic_helper_crtc_destroy_state(crtc
, old_crtc_state
);
12620 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12621 memset(pipe_config
, 0, sizeof(*pipe_config
));
12622 pipe_config
->base
.crtc
= crtc
;
12623 pipe_config
->base
.state
= old_state
;
12625 DRM_DEBUG_KMS("[CRTC:%d]\n",
12628 active
= dev_priv
->display
.get_pipe_config(intel_crtc
,
12631 /* hw state is inconsistent with the pipe quirk */
12632 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12633 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12634 active
= crtc
->state
->active
;
12636 I915_STATE_WARN(crtc
->state
->active
!= active
,
12637 "crtc active state doesn't match with hw state "
12638 "(expected %i, found %i)\n", crtc
->state
->active
, active
);
12640 I915_STATE_WARN(intel_crtc
->active
!= crtc
->state
->active
,
12641 "transitional active state does not match atomic hw state "
12642 "(expected %i, found %i)\n", crtc
->state
->active
, intel_crtc
->active
);
12644 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12647 active
= encoder
->get_hw_state(encoder
, &pipe
);
12648 I915_STATE_WARN(active
!= crtc
->state
->active
,
12649 "[ENCODER:%i] active %i with crtc active %i\n",
12650 encoder
->base
.base
.id
, active
, crtc
->state
->active
);
12652 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12653 "Encoder connected to wrong pipe %c\n",
12657 encoder
->get_config(encoder
, pipe_config
);
12660 if (!crtc
->state
->active
)
12663 sw_config
= to_intel_crtc_state(crtc
->state
);
12664 if (!intel_pipe_config_compare(dev
, sw_config
,
12665 pipe_config
, false)) {
12666 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12667 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12669 intel_dump_pipe_config(intel_crtc
, sw_config
,
12676 check_shared_dpll_state(struct drm_device
*dev
)
12678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12679 struct intel_crtc
*crtc
;
12680 struct intel_dpll_hw_state dpll_hw_state
;
12683 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12684 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12685 int enabled_crtcs
= 0, active_crtcs
= 0;
12688 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12690 DRM_DEBUG_KMS("%s\n", pll
->name
);
12692 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12694 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12695 "more active pll users than references: %i vs %i\n",
12696 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12697 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12698 "pll in active use but not on in sw tracking\n");
12699 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12700 "pll in on but not on in use in sw tracking\n");
12701 I915_STATE_WARN(pll
->on
!= active
,
12702 "pll on state mismatch (expected %i, found %i)\n",
12705 for_each_intel_crtc(dev
, crtc
) {
12706 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12708 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12711 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12712 "pll active crtcs mismatch (expected %i, found %i)\n",
12713 pll
->active
, active_crtcs
);
12714 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12715 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12716 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12718 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12719 sizeof(dpll_hw_state
)),
12720 "pll hw state mismatch\n");
12725 intel_modeset_check_state(struct drm_device
*dev
,
12726 struct drm_atomic_state
*old_state
)
12728 check_wm_state(dev
);
12729 check_connector_state(dev
, old_state
);
12730 check_encoder_state(dev
);
12731 check_crtc_state(dev
, old_state
);
12732 check_shared_dpll_state(dev
);
12735 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12739 * FDI already provided one idea for the dotclock.
12740 * Yell if the encoder disagrees.
12742 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12743 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12744 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12747 static void update_scanline_offset(struct intel_crtc
*crtc
)
12749 struct drm_device
*dev
= crtc
->base
.dev
;
12752 * The scanline counter increments at the leading edge of hsync.
12754 * On most platforms it starts counting from vtotal-1 on the
12755 * first active line. That means the scanline counter value is
12756 * always one less than what we would expect. Ie. just after
12757 * start of vblank, which also occurs at start of hsync (on the
12758 * last active line), the scanline counter will read vblank_start-1.
12760 * On gen2 the scanline counter starts counting from 1 instead
12761 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12762 * to keep the value positive), instead of adding one.
12764 * On HSW+ the behaviour of the scanline counter depends on the output
12765 * type. For DP ports it behaves like most other platforms, but on HDMI
12766 * there's an extra 1 line difference. So we need to add two instead of
12767 * one to the value.
12769 if (IS_GEN2(dev
)) {
12770 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
12773 vtotal
= mode
->crtc_vtotal
;
12774 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12777 crtc
->scanline_offset
= vtotal
- 1;
12778 } else if (HAS_DDI(dev
) &&
12779 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12780 crtc
->scanline_offset
= 2;
12782 crtc
->scanline_offset
= 1;
12785 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
12787 struct drm_device
*dev
= state
->dev
;
12788 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12789 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
12790 struct intel_crtc
*intel_crtc
;
12791 struct intel_crtc_state
*intel_crtc_state
;
12792 struct drm_crtc
*crtc
;
12793 struct drm_crtc_state
*crtc_state
;
12796 if (!dev_priv
->display
.crtc_compute_clock
)
12799 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12802 intel_crtc
= to_intel_crtc(crtc
);
12803 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12804 dpll
= intel_crtc_state
->shared_dpll
;
12806 if (!needs_modeset(crtc_state
) || dpll
== DPLL_ID_PRIVATE
)
12809 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
12812 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
12814 shared_dpll
[dpll
].crtc_mask
&= ~(1 << intel_crtc
->pipe
);
12819 * This implements the workaround described in the "notes" section of the mode
12820 * set sequence documentation. When going from no pipes or single pipe to
12821 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12822 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12824 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
12826 struct drm_crtc_state
*crtc_state
;
12827 struct intel_crtc
*intel_crtc
;
12828 struct drm_crtc
*crtc
;
12829 struct intel_crtc_state
*first_crtc_state
= NULL
;
12830 struct intel_crtc_state
*other_crtc_state
= NULL
;
12831 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
12834 /* look at all crtc's that are going to be enabled in during modeset */
12835 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12836 intel_crtc
= to_intel_crtc(crtc
);
12838 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
12841 if (first_crtc_state
) {
12842 other_crtc_state
= to_intel_crtc_state(crtc_state
);
12845 first_crtc_state
= to_intel_crtc_state(crtc_state
);
12846 first_pipe
= intel_crtc
->pipe
;
12850 /* No workaround needed? */
12851 if (!first_crtc_state
)
12854 /* w/a possibly needed, check how many crtc's are already enabled. */
12855 for_each_intel_crtc(state
->dev
, intel_crtc
) {
12856 struct intel_crtc_state
*pipe_config
;
12858 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12859 if (IS_ERR(pipe_config
))
12860 return PTR_ERR(pipe_config
);
12862 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
12864 if (!pipe_config
->base
.active
||
12865 needs_modeset(&pipe_config
->base
))
12868 /* 2 or more enabled crtcs means no need for w/a */
12869 if (enabled_pipe
!= INVALID_PIPE
)
12872 enabled_pipe
= intel_crtc
->pipe
;
12875 if (enabled_pipe
!= INVALID_PIPE
)
12876 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
12877 else if (other_crtc_state
)
12878 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
12883 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
12885 struct drm_crtc
*crtc
;
12886 struct drm_crtc_state
*crtc_state
;
12889 /* add all active pipes to the state */
12890 for_each_crtc(state
->dev
, crtc
) {
12891 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
12892 if (IS_ERR(crtc_state
))
12893 return PTR_ERR(crtc_state
);
12895 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
12898 crtc_state
->mode_changed
= true;
12900 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12904 ret
= drm_atomic_add_affected_planes(state
, crtc
);
12913 static int intel_modeset_checks(struct drm_atomic_state
*state
)
12915 struct drm_device
*dev
= state
->dev
;
12916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12919 if (!check_digital_port_conflicts(state
)) {
12920 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12925 * See if the config requires any additional preparation, e.g.
12926 * to adjust global state with pipes off. We need to do this
12927 * here so we can get the modeset_pipe updated config for the new
12928 * mode set on this crtc. For other crtcs we need to use the
12929 * adjusted_mode bits in the crtc directly.
12931 if (dev_priv
->display
.modeset_calc_cdclk
) {
12932 unsigned int cdclk
;
12934 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
12936 cdclk
= to_intel_atomic_state(state
)->cdclk
;
12937 if (!ret
&& cdclk
!= dev_priv
->cdclk_freq
)
12938 ret
= intel_modeset_all_pipes(state
);
12943 to_intel_atomic_state(state
)->cdclk
= dev_priv
->cdclk_freq
;
12945 intel_modeset_clear_plls(state
);
12947 if (IS_HASWELL(dev
))
12948 return haswell_mode_set_planes_workaround(state
);
12954 * intel_atomic_check - validate state object
12956 * @state: state to validate
12958 static int intel_atomic_check(struct drm_device
*dev
,
12959 struct drm_atomic_state
*state
)
12961 struct drm_crtc
*crtc
;
12962 struct drm_crtc_state
*crtc_state
;
12964 bool any_ms
= false;
12966 ret
= drm_atomic_helper_check_modeset(dev
, state
);
12970 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12971 struct intel_crtc_state
*pipe_config
=
12972 to_intel_crtc_state(crtc_state
);
12974 /* Catch I915_MODE_FLAG_INHERITED */
12975 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
12976 crtc_state
->mode_changed
= true;
12978 if (!crtc_state
->enable
) {
12979 if (needs_modeset(crtc_state
))
12984 if (!needs_modeset(crtc_state
))
12987 /* FIXME: For only active_changed we shouldn't need to do any
12988 * state recomputation at all. */
12990 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12994 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
12998 if (i915
.fastboot
&&
12999 intel_pipe_config_compare(state
->dev
,
13000 to_intel_crtc_state(crtc
->state
),
13001 pipe_config
, true)) {
13002 crtc_state
->mode_changed
= false;
13005 if (needs_modeset(crtc_state
)) {
13008 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13013 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13014 needs_modeset(crtc_state
) ?
13015 "[modeset]" : "[fastset]");
13019 ret
= intel_modeset_checks(state
);
13024 to_intel_atomic_state(state
)->cdclk
=
13025 to_i915(state
->dev
)->cdclk_freq
;
13027 return drm_atomic_helper_check_planes(state
->dev
, state
);
13031 * intel_atomic_commit - commit validated state object
13033 * @state: the top-level driver state object
13034 * @async: asynchronous commit
13036 * This function commits a top-level state object that has been validated
13037 * with drm_atomic_helper_check().
13039 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13040 * we can only handle plane-related operations and do not yet support
13041 * asynchronous commit.
13044 * Zero for success or -errno.
13046 static int intel_atomic_commit(struct drm_device
*dev
,
13047 struct drm_atomic_state
*state
,
13050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13051 struct drm_crtc
*crtc
;
13052 struct drm_crtc_state
*crtc_state
;
13055 bool any_ms
= false;
13058 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13062 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13066 drm_atomic_helper_swap_state(dev
, state
);
13068 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13069 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13071 if (!needs_modeset(crtc
->state
))
13075 intel_pre_plane_update(intel_crtc
);
13077 if (crtc_state
->active
) {
13078 intel_crtc_disable_planes(crtc
, crtc_state
->plane_mask
);
13079 dev_priv
->display
.crtc_disable(crtc
);
13080 intel_crtc
->active
= false;
13081 intel_disable_shared_dpll(intel_crtc
);
13085 /* Only after disabling all output pipelines that will be changed can we
13086 * update the the output configuration. */
13087 intel_modeset_update_crtc_state(state
);
13090 intel_shared_dpll_commit(state
);
13092 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13093 modeset_update_crtc_power_domains(state
);
13096 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13097 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13098 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13099 bool modeset
= needs_modeset(crtc
->state
);
13101 if (modeset
&& crtc
->state
->active
) {
13102 update_scanline_offset(to_intel_crtc(crtc
));
13103 dev_priv
->display
.crtc_enable(crtc
);
13107 intel_pre_plane_update(intel_crtc
);
13109 drm_atomic_helper_commit_planes_on_crtc(crtc_state
);
13110 intel_post_plane_update(intel_crtc
);
13113 /* FIXME: add subpixel order */
13115 drm_atomic_helper_wait_for_vblanks(dev
, state
);
13116 drm_atomic_helper_cleanup_planes(dev
, state
);
13119 intel_modeset_check_state(dev
, state
);
13121 drm_atomic_state_free(state
);
13126 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13128 struct drm_device
*dev
= crtc
->dev
;
13129 struct drm_atomic_state
*state
;
13130 struct drm_crtc_state
*crtc_state
;
13133 state
= drm_atomic_state_alloc(dev
);
13135 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13140 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13143 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13144 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13146 if (!crtc_state
->active
)
13149 crtc_state
->mode_changed
= true;
13150 ret
= drm_atomic_commit(state
);
13153 if (ret
== -EDEADLK
) {
13154 drm_atomic_state_clear(state
);
13155 drm_modeset_backoff(state
->acquire_ctx
);
13161 drm_atomic_state_free(state
);
13164 #undef for_each_intel_crtc_masked
13166 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13167 .gamma_set
= intel_crtc_gamma_set
,
13168 .set_config
= drm_atomic_helper_set_config
,
13169 .destroy
= intel_crtc_destroy
,
13170 .page_flip
= intel_crtc_page_flip
,
13171 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13172 .atomic_destroy_state
= intel_crtc_destroy_state
,
13175 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
13176 struct intel_shared_dpll
*pll
,
13177 struct intel_dpll_hw_state
*hw_state
)
13181 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
13184 val
= I915_READ(PCH_DPLL(pll
->id
));
13185 hw_state
->dpll
= val
;
13186 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
13187 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
13189 return val
& DPLL_VCO_ENABLE
;
13192 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
13193 struct intel_shared_dpll
*pll
)
13195 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
13196 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13199 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13200 struct intel_shared_dpll
*pll
)
13202 /* PCH refclock must be enabled first */
13203 ibx_assert_pch_refclk_enabled(dev_priv
);
13205 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13207 /* Wait for the clocks to stabilize. */
13208 POSTING_READ(PCH_DPLL(pll
->id
));
13211 /* The pixel multiplier can only be updated once the
13212 * DPLL is enabled and the clocks are stable.
13214 * So write it again.
13216 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13217 POSTING_READ(PCH_DPLL(pll
->id
));
13221 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13222 struct intel_shared_dpll
*pll
)
13224 struct drm_device
*dev
= dev_priv
->dev
;
13225 struct intel_crtc
*crtc
;
13227 /* Make sure no transcoder isn't still depending on us. */
13228 for_each_intel_crtc(dev
, crtc
) {
13229 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13230 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13233 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13234 POSTING_READ(PCH_DPLL(pll
->id
));
13238 static char *ibx_pch_dpll_names
[] = {
13243 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13248 dev_priv
->num_shared_dpll
= 2;
13250 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13251 dev_priv
->shared_dplls
[i
].id
= i
;
13252 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13253 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13254 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13255 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13256 dev_priv
->shared_dplls
[i
].get_hw_state
=
13257 ibx_pch_dpll_get_hw_state
;
13261 static void intel_shared_dpll_init(struct drm_device
*dev
)
13263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13265 intel_update_cdclk(dev
);
13268 intel_ddi_pll_init(dev
);
13269 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13270 ibx_pch_dpll_init(dev
);
13272 dev_priv
->num_shared_dpll
= 0;
13274 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13278 * intel_prepare_plane_fb - Prepare fb for usage on plane
13279 * @plane: drm plane to prepare for
13280 * @fb: framebuffer to prepare for presentation
13282 * Prepares a framebuffer for usage on a display plane. Generally this
13283 * involves pinning the underlying object and updating the frontbuffer tracking
13284 * bits. Some older platforms need special physical address handling for
13287 * Returns 0 on success, negative error code on failure.
13290 intel_prepare_plane_fb(struct drm_plane
*plane
,
13291 struct drm_framebuffer
*fb
,
13292 const struct drm_plane_state
*new_state
)
13294 struct drm_device
*dev
= plane
->dev
;
13295 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13296 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13297 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13303 mutex_lock(&dev
->struct_mutex
);
13305 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13306 INTEL_INFO(dev
)->cursor_needs_physical
) {
13307 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13308 ret
= i915_gem_object_attach_phys(obj
, align
);
13310 DRM_DEBUG_KMS("failed to attach phys object\n");
13312 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
, NULL
);
13316 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13318 mutex_unlock(&dev
->struct_mutex
);
13324 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13325 * @plane: drm plane to clean up for
13326 * @fb: old framebuffer that was on plane
13328 * Cleans up a framebuffer that has just been removed from a plane.
13331 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13332 struct drm_framebuffer
*fb
,
13333 const struct drm_plane_state
*old_state
)
13335 struct drm_device
*dev
= plane
->dev
;
13336 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13341 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13342 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13343 mutex_lock(&dev
->struct_mutex
);
13344 intel_unpin_fb_obj(fb
, old_state
);
13345 mutex_unlock(&dev
->struct_mutex
);
13350 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13353 struct drm_device
*dev
;
13354 struct drm_i915_private
*dev_priv
;
13355 int crtc_clock
, cdclk
;
13357 if (!intel_crtc
|| !crtc_state
)
13358 return DRM_PLANE_HELPER_NO_SCALING
;
13360 dev
= intel_crtc
->base
.dev
;
13361 dev_priv
= dev
->dev_private
;
13362 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13363 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
13365 if (!crtc_clock
|| !cdclk
)
13366 return DRM_PLANE_HELPER_NO_SCALING
;
13369 * skl max scale is lower of:
13370 * close to 3 but not 3, -1 is for that purpose
13374 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13380 intel_check_primary_plane(struct drm_plane
*plane
,
13381 struct intel_crtc_state
*crtc_state
,
13382 struct intel_plane_state
*state
)
13384 struct drm_crtc
*crtc
= state
->base
.crtc
;
13385 struct drm_framebuffer
*fb
= state
->base
.fb
;
13386 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13387 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13388 bool can_position
= false;
13390 /* use scaler when colorkey is not required */
13391 if (INTEL_INFO(plane
->dev
)->gen
>= 9 &&
13392 state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13394 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
13395 can_position
= true;
13398 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13399 &state
->dst
, &state
->clip
,
13400 min_scale
, max_scale
,
13401 can_position
, true,
13406 intel_commit_primary_plane(struct drm_plane
*plane
,
13407 struct intel_plane_state
*state
)
13409 struct drm_crtc
*crtc
= state
->base
.crtc
;
13410 struct drm_framebuffer
*fb
= state
->base
.fb
;
13411 struct drm_device
*dev
= plane
->dev
;
13412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13413 struct intel_crtc
*intel_crtc
;
13414 struct drm_rect
*src
= &state
->src
;
13416 crtc
= crtc
? crtc
: plane
->crtc
;
13417 intel_crtc
= to_intel_crtc(crtc
);
13420 crtc
->x
= src
->x1
>> 16;
13421 crtc
->y
= src
->y1
>> 16;
13423 if (!crtc
->state
->active
)
13426 if (state
->visible
)
13427 /* FIXME: kill this fastboot hack */
13428 intel_update_pipe_size(intel_crtc
);
13430 dev_priv
->display
.update_primary_plane(crtc
, fb
,
13431 state
->src
.x1
>> 16,
13432 state
->src
.y1
>> 16);
13436 intel_disable_primary_plane(struct drm_plane
*plane
,
13437 struct drm_crtc
*crtc
)
13439 struct drm_device
*dev
= plane
->dev
;
13440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13442 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13445 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
13446 struct drm_crtc_state
*old_crtc_state
)
13448 struct drm_device
*dev
= crtc
->dev
;
13449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13451 if (intel_crtc
->atomic
.update_wm_pre
)
13452 intel_update_watermarks(crtc
);
13454 /* Perform vblank evasion around commit operation */
13455 if (crtc
->state
->active
)
13456 intel_pipe_update_start(intel_crtc
);
13458 if (!needs_modeset(crtc
->state
) && INTEL_INFO(dev
)->gen
>= 9)
13459 skl_detach_scalers(intel_crtc
);
13462 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
13463 struct drm_crtc_state
*old_crtc_state
)
13465 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13467 if (crtc
->state
->active
)
13468 intel_pipe_update_end(intel_crtc
);
13472 * intel_plane_destroy - destroy a plane
13473 * @plane: plane to destroy
13475 * Common destruction function for all types of planes (primary, cursor,
13478 void intel_plane_destroy(struct drm_plane
*plane
)
13480 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13481 drm_plane_cleanup(plane
);
13482 kfree(intel_plane
);
13485 const struct drm_plane_funcs intel_plane_funcs
= {
13486 .update_plane
= drm_atomic_helper_update_plane
,
13487 .disable_plane
= drm_atomic_helper_disable_plane
,
13488 .destroy
= intel_plane_destroy
,
13489 .set_property
= drm_atomic_helper_plane_set_property
,
13490 .atomic_get_property
= intel_plane_atomic_get_property
,
13491 .atomic_set_property
= intel_plane_atomic_set_property
,
13492 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13493 .atomic_destroy_state
= intel_plane_destroy_state
,
13497 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13500 struct intel_plane
*primary
;
13501 struct intel_plane_state
*state
;
13502 const uint32_t *intel_primary_formats
;
13503 unsigned int num_formats
;
13505 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13506 if (primary
== NULL
)
13509 state
= intel_create_plane_state(&primary
->base
);
13514 primary
->base
.state
= &state
->base
;
13516 primary
->can_scale
= false;
13517 primary
->max_downscale
= 1;
13518 if (INTEL_INFO(dev
)->gen
>= 9) {
13519 primary
->can_scale
= true;
13520 state
->scaler_id
= -1;
13522 primary
->pipe
= pipe
;
13523 primary
->plane
= pipe
;
13524 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13525 primary
->check_plane
= intel_check_primary_plane
;
13526 primary
->commit_plane
= intel_commit_primary_plane
;
13527 primary
->disable_plane
= intel_disable_primary_plane
;
13528 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13529 primary
->plane
= !pipe
;
13531 if (INTEL_INFO(dev
)->gen
>= 9) {
13532 intel_primary_formats
= skl_primary_formats
;
13533 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13534 } else if (INTEL_INFO(dev
)->gen
>= 4) {
13535 intel_primary_formats
= i965_primary_formats
;
13536 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13538 intel_primary_formats
= i8xx_primary_formats
;
13539 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13542 drm_universal_plane_init(dev
, &primary
->base
, 0,
13543 &intel_plane_funcs
,
13544 intel_primary_formats
, num_formats
,
13545 DRM_PLANE_TYPE_PRIMARY
);
13547 if (INTEL_INFO(dev
)->gen
>= 4)
13548 intel_create_rotation_property(dev
, primary
);
13550 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13552 return &primary
->base
;
13555 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13557 if (!dev
->mode_config
.rotation_property
) {
13558 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13559 BIT(DRM_ROTATE_180
);
13561 if (INTEL_INFO(dev
)->gen
>= 9)
13562 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13564 dev
->mode_config
.rotation_property
=
13565 drm_mode_create_rotation_property(dev
, flags
);
13567 if (dev
->mode_config
.rotation_property
)
13568 drm_object_attach_property(&plane
->base
.base
,
13569 dev
->mode_config
.rotation_property
,
13570 plane
->base
.state
->rotation
);
13574 intel_check_cursor_plane(struct drm_plane
*plane
,
13575 struct intel_crtc_state
*crtc_state
,
13576 struct intel_plane_state
*state
)
13578 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
13579 struct drm_framebuffer
*fb
= state
->base
.fb
;
13580 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13584 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13585 &state
->dst
, &state
->clip
,
13586 DRM_PLANE_HELPER_NO_SCALING
,
13587 DRM_PLANE_HELPER_NO_SCALING
,
13588 true, true, &state
->visible
);
13592 /* if we want to turn off the cursor ignore width and height */
13596 /* Check for which cursor types we support */
13597 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13598 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13599 state
->base
.crtc_w
, state
->base
.crtc_h
);
13603 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13604 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13605 DRM_DEBUG_KMS("buffer is too small\n");
13609 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13610 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13618 intel_disable_cursor_plane(struct drm_plane
*plane
,
13619 struct drm_crtc
*crtc
)
13621 intel_crtc_update_cursor(crtc
, false);
13625 intel_commit_cursor_plane(struct drm_plane
*plane
,
13626 struct intel_plane_state
*state
)
13628 struct drm_crtc
*crtc
= state
->base
.crtc
;
13629 struct drm_device
*dev
= plane
->dev
;
13630 struct intel_crtc
*intel_crtc
;
13631 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13634 crtc
= crtc
? crtc
: plane
->crtc
;
13635 intel_crtc
= to_intel_crtc(crtc
);
13637 plane
->fb
= state
->base
.fb
;
13638 crtc
->cursor_x
= state
->base
.crtc_x
;
13639 crtc
->cursor_y
= state
->base
.crtc_y
;
13641 if (intel_crtc
->cursor_bo
== obj
)
13646 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13647 addr
= i915_gem_obj_ggtt_offset(obj
);
13649 addr
= obj
->phys_handle
->busaddr
;
13651 intel_crtc
->cursor_addr
= addr
;
13652 intel_crtc
->cursor_bo
= obj
;
13655 if (crtc
->state
->active
)
13656 intel_crtc_update_cursor(crtc
, state
->visible
);
13659 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13662 struct intel_plane
*cursor
;
13663 struct intel_plane_state
*state
;
13665 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13666 if (cursor
== NULL
)
13669 state
= intel_create_plane_state(&cursor
->base
);
13674 cursor
->base
.state
= &state
->base
;
13676 cursor
->can_scale
= false;
13677 cursor
->max_downscale
= 1;
13678 cursor
->pipe
= pipe
;
13679 cursor
->plane
= pipe
;
13680 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13681 cursor
->check_plane
= intel_check_cursor_plane
;
13682 cursor
->commit_plane
= intel_commit_cursor_plane
;
13683 cursor
->disable_plane
= intel_disable_cursor_plane
;
13685 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13686 &intel_plane_funcs
,
13687 intel_cursor_formats
,
13688 ARRAY_SIZE(intel_cursor_formats
),
13689 DRM_PLANE_TYPE_CURSOR
);
13691 if (INTEL_INFO(dev
)->gen
>= 4) {
13692 if (!dev
->mode_config
.rotation_property
)
13693 dev
->mode_config
.rotation_property
=
13694 drm_mode_create_rotation_property(dev
,
13695 BIT(DRM_ROTATE_0
) |
13696 BIT(DRM_ROTATE_180
));
13697 if (dev
->mode_config
.rotation_property
)
13698 drm_object_attach_property(&cursor
->base
.base
,
13699 dev
->mode_config
.rotation_property
,
13700 state
->base
.rotation
);
13703 if (INTEL_INFO(dev
)->gen
>=9)
13704 state
->scaler_id
= -1;
13706 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13708 return &cursor
->base
;
13711 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13712 struct intel_crtc_state
*crtc_state
)
13715 struct intel_scaler
*intel_scaler
;
13716 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13718 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13719 intel_scaler
= &scaler_state
->scalers
[i
];
13720 intel_scaler
->in_use
= 0;
13721 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13724 scaler_state
->scaler_id
= -1;
13727 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13730 struct intel_crtc
*intel_crtc
;
13731 struct intel_crtc_state
*crtc_state
= NULL
;
13732 struct drm_plane
*primary
= NULL
;
13733 struct drm_plane
*cursor
= NULL
;
13736 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13737 if (intel_crtc
== NULL
)
13740 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13743 intel_crtc
->config
= crtc_state
;
13744 intel_crtc
->base
.state
= &crtc_state
->base
;
13745 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13747 /* initialize shared scalers */
13748 if (INTEL_INFO(dev
)->gen
>= 9) {
13749 if (pipe
== PIPE_C
)
13750 intel_crtc
->num_scalers
= 1;
13752 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13754 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13757 primary
= intel_primary_plane_create(dev
, pipe
);
13761 cursor
= intel_cursor_plane_create(dev
, pipe
);
13765 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13766 cursor
, &intel_crtc_funcs
);
13770 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13771 for (i
= 0; i
< 256; i
++) {
13772 intel_crtc
->lut_r
[i
] = i
;
13773 intel_crtc
->lut_g
[i
] = i
;
13774 intel_crtc
->lut_b
[i
] = i
;
13778 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13779 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13781 intel_crtc
->pipe
= pipe
;
13782 intel_crtc
->plane
= pipe
;
13783 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13784 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13785 intel_crtc
->plane
= !pipe
;
13788 intel_crtc
->cursor_base
= ~0;
13789 intel_crtc
->cursor_cntl
= ~0;
13790 intel_crtc
->cursor_size
= ~0;
13792 intel_crtc
->wm
.cxsr_allowed
= true;
13794 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13795 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13796 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13797 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13799 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13801 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13806 drm_plane_cleanup(primary
);
13808 drm_plane_cleanup(cursor
);
13813 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13815 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13816 struct drm_device
*dev
= connector
->base
.dev
;
13818 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13820 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13821 return INVALID_PIPE
;
13823 return to_intel_crtc(encoder
->crtc
)->pipe
;
13826 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13827 struct drm_file
*file
)
13829 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13830 struct drm_crtc
*drmmode_crtc
;
13831 struct intel_crtc
*crtc
;
13833 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13835 if (!drmmode_crtc
) {
13836 DRM_ERROR("no such CRTC id\n");
13840 crtc
= to_intel_crtc(drmmode_crtc
);
13841 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13846 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13848 struct drm_device
*dev
= encoder
->base
.dev
;
13849 struct intel_encoder
*source_encoder
;
13850 int index_mask
= 0;
13853 for_each_intel_encoder(dev
, source_encoder
) {
13854 if (encoders_cloneable(encoder
, source_encoder
))
13855 index_mask
|= (1 << entry
);
13863 static bool has_edp_a(struct drm_device
*dev
)
13865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13867 if (!IS_MOBILE(dev
))
13870 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13873 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13879 static bool intel_crt_present(struct drm_device
*dev
)
13881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13883 if (INTEL_INFO(dev
)->gen
>= 9)
13886 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13889 if (IS_CHERRYVIEW(dev
))
13892 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13898 static void intel_setup_outputs(struct drm_device
*dev
)
13900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13901 struct intel_encoder
*encoder
;
13902 bool dpd_is_edp
= false;
13904 intel_lvds_init(dev
);
13906 if (intel_crt_present(dev
))
13907 intel_crt_init(dev
);
13909 if (IS_BROXTON(dev
)) {
13911 * FIXME: Broxton doesn't support port detection via the
13912 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13913 * detect the ports.
13915 intel_ddi_init(dev
, PORT_A
);
13916 intel_ddi_init(dev
, PORT_B
);
13917 intel_ddi_init(dev
, PORT_C
);
13918 } else if (HAS_DDI(dev
)) {
13922 * Haswell uses DDI functions to detect digital outputs.
13923 * On SKL pre-D0 the strap isn't connected, so we assume
13926 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13927 /* WaIgnoreDDIAStrap: skl */
13928 if (found
|| IS_SKYLAKE(dev
))
13929 intel_ddi_init(dev
, PORT_A
);
13931 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13933 found
= I915_READ(SFUSE_STRAP
);
13935 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13936 intel_ddi_init(dev
, PORT_B
);
13937 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13938 intel_ddi_init(dev
, PORT_C
);
13939 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13940 intel_ddi_init(dev
, PORT_D
);
13942 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13944 if (IS_SKYLAKE(dev
) &&
13945 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
13946 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
13947 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
13948 intel_ddi_init(dev
, PORT_E
);
13950 } else if (HAS_PCH_SPLIT(dev
)) {
13952 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13954 if (has_edp_a(dev
))
13955 intel_dp_init(dev
, DP_A
, PORT_A
);
13957 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13958 /* PCH SDVOB multiplex with HDMIB */
13959 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13961 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13962 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13963 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13966 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13967 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13969 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13970 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13972 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13973 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13975 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13976 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13977 } else if (IS_VALLEYVIEW(dev
)) {
13979 * The DP_DETECTED bit is the latched state of the DDC
13980 * SDA pin at boot. However since eDP doesn't require DDC
13981 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13982 * eDP ports may have been muxed to an alternate function.
13983 * Thus we can't rely on the DP_DETECTED bit alone to detect
13984 * eDP ports. Consult the VBT as well as DP_DETECTED to
13985 * detect eDP ports.
13987 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13988 !intel_dp_is_edp(dev
, PORT_B
))
13989 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13991 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13992 intel_dp_is_edp(dev
, PORT_B
))
13993 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13995 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13996 !intel_dp_is_edp(dev
, PORT_C
))
13997 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13999 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
14000 intel_dp_is_edp(dev
, PORT_C
))
14001 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
14003 if (IS_CHERRYVIEW(dev
)) {
14004 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
14005 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
14007 /* eDP not supported on port D, so don't check VBT */
14008 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
14009 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
14012 intel_dsi_init(dev
);
14013 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14014 bool found
= false;
14016 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14017 DRM_DEBUG_KMS("probing SDVOB\n");
14018 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
14019 if (!found
&& IS_G4X(dev
)) {
14020 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14021 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14024 if (!found
&& IS_G4X(dev
))
14025 intel_dp_init(dev
, DP_B
, PORT_B
);
14028 /* Before G4X SDVOC doesn't have its own detect register */
14030 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14031 DRM_DEBUG_KMS("probing SDVOC\n");
14032 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14035 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14038 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14039 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14042 intel_dp_init(dev
, DP_C
, PORT_C
);
14046 (I915_READ(DP_D
) & DP_DETECTED
))
14047 intel_dp_init(dev
, DP_D
, PORT_D
);
14048 } else if (IS_GEN2(dev
))
14049 intel_dvo_init(dev
);
14051 if (SUPPORTS_TV(dev
))
14052 intel_tv_init(dev
);
14054 intel_psr_init(dev
);
14056 for_each_intel_encoder(dev
, encoder
) {
14057 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14058 encoder
->base
.possible_clones
=
14059 intel_encoder_clones(encoder
);
14062 intel_init_pch_refclk(dev
);
14064 drm_helper_move_panel_connectors_to_head(dev
);
14067 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14069 struct drm_device
*dev
= fb
->dev
;
14070 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14072 drm_framebuffer_cleanup(fb
);
14073 mutex_lock(&dev
->struct_mutex
);
14074 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14075 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14076 mutex_unlock(&dev
->struct_mutex
);
14080 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14081 struct drm_file
*file
,
14082 unsigned int *handle
)
14084 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14085 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14087 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14090 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14091 struct drm_file
*file
,
14092 unsigned flags
, unsigned color
,
14093 struct drm_clip_rect
*clips
,
14094 unsigned num_clips
)
14096 struct drm_device
*dev
= fb
->dev
;
14097 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14098 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14100 mutex_lock(&dev
->struct_mutex
);
14101 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14102 mutex_unlock(&dev
->struct_mutex
);
14107 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14108 .destroy
= intel_user_framebuffer_destroy
,
14109 .create_handle
= intel_user_framebuffer_create_handle
,
14110 .dirty
= intel_user_framebuffer_dirty
,
14114 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14115 uint32_t pixel_format
)
14117 u32 gen
= INTEL_INFO(dev
)->gen
;
14120 /* "The stride in bytes must not exceed the of the size of 8K
14121 * pixels and 32K bytes."
14123 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14124 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14126 } else if (gen
>= 4) {
14127 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14131 } else if (gen
>= 3) {
14132 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14137 /* XXX DSPC is limited to 4k tiled */
14142 static int intel_framebuffer_init(struct drm_device
*dev
,
14143 struct intel_framebuffer
*intel_fb
,
14144 struct drm_mode_fb_cmd2
*mode_cmd
,
14145 struct drm_i915_gem_object
*obj
)
14147 unsigned int aligned_height
;
14149 u32 pitch_limit
, stride_alignment
;
14151 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14153 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14154 /* Enforce that fb modifier and tiling mode match, but only for
14155 * X-tiled. This is needed for FBC. */
14156 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14157 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14158 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14162 if (obj
->tiling_mode
== I915_TILING_X
)
14163 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14164 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14165 DRM_DEBUG("No Y tiling for legacy addfb\n");
14170 /* Passed in modifier sanity checking. */
14171 switch (mode_cmd
->modifier
[0]) {
14172 case I915_FORMAT_MOD_Y_TILED
:
14173 case I915_FORMAT_MOD_Yf_TILED
:
14174 if (INTEL_INFO(dev
)->gen
< 9) {
14175 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14176 mode_cmd
->modifier
[0]);
14179 case DRM_FORMAT_MOD_NONE
:
14180 case I915_FORMAT_MOD_X_TILED
:
14183 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14184 mode_cmd
->modifier
[0]);
14188 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14189 mode_cmd
->pixel_format
);
14190 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14191 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14192 mode_cmd
->pitches
[0], stride_alignment
);
14196 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14197 mode_cmd
->pixel_format
);
14198 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14199 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14200 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14201 "tiled" : "linear",
14202 mode_cmd
->pitches
[0], pitch_limit
);
14206 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14207 mode_cmd
->pitches
[0] != obj
->stride
) {
14208 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14209 mode_cmd
->pitches
[0], obj
->stride
);
14213 /* Reject formats not supported by any plane early. */
14214 switch (mode_cmd
->pixel_format
) {
14215 case DRM_FORMAT_C8
:
14216 case DRM_FORMAT_RGB565
:
14217 case DRM_FORMAT_XRGB8888
:
14218 case DRM_FORMAT_ARGB8888
:
14220 case DRM_FORMAT_XRGB1555
:
14221 if (INTEL_INFO(dev
)->gen
> 3) {
14222 DRM_DEBUG("unsupported pixel format: %s\n",
14223 drm_get_format_name(mode_cmd
->pixel_format
));
14227 case DRM_FORMAT_ABGR8888
:
14228 if (!IS_VALLEYVIEW(dev
) && INTEL_INFO(dev
)->gen
< 9) {
14229 DRM_DEBUG("unsupported pixel format: %s\n",
14230 drm_get_format_name(mode_cmd
->pixel_format
));
14234 case DRM_FORMAT_XBGR8888
:
14235 case DRM_FORMAT_XRGB2101010
:
14236 case DRM_FORMAT_XBGR2101010
:
14237 if (INTEL_INFO(dev
)->gen
< 4) {
14238 DRM_DEBUG("unsupported pixel format: %s\n",
14239 drm_get_format_name(mode_cmd
->pixel_format
));
14243 case DRM_FORMAT_ABGR2101010
:
14244 if (!IS_VALLEYVIEW(dev
)) {
14245 DRM_DEBUG("unsupported pixel format: %s\n",
14246 drm_get_format_name(mode_cmd
->pixel_format
));
14250 case DRM_FORMAT_YUYV
:
14251 case DRM_FORMAT_UYVY
:
14252 case DRM_FORMAT_YVYU
:
14253 case DRM_FORMAT_VYUY
:
14254 if (INTEL_INFO(dev
)->gen
< 5) {
14255 DRM_DEBUG("unsupported pixel format: %s\n",
14256 drm_get_format_name(mode_cmd
->pixel_format
));
14261 DRM_DEBUG("unsupported pixel format: %s\n",
14262 drm_get_format_name(mode_cmd
->pixel_format
));
14266 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14267 if (mode_cmd
->offsets
[0] != 0)
14270 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14271 mode_cmd
->pixel_format
,
14272 mode_cmd
->modifier
[0]);
14273 /* FIXME drm helper for size checks (especially planar formats)? */
14274 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14277 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14278 intel_fb
->obj
= obj
;
14279 intel_fb
->obj
->framebuffer_references
++;
14281 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14283 DRM_ERROR("framebuffer init failed %d\n", ret
);
14290 static struct drm_framebuffer
*
14291 intel_user_framebuffer_create(struct drm_device
*dev
,
14292 struct drm_file
*filp
,
14293 struct drm_mode_fb_cmd2
*mode_cmd
)
14295 struct drm_i915_gem_object
*obj
;
14297 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14298 mode_cmd
->handles
[0]));
14299 if (&obj
->base
== NULL
)
14300 return ERR_PTR(-ENOENT
);
14302 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14305 #ifndef CONFIG_DRM_FBDEV_EMULATION
14306 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14311 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14312 .fb_create
= intel_user_framebuffer_create
,
14313 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14314 .atomic_check
= intel_atomic_check
,
14315 .atomic_commit
= intel_atomic_commit
,
14316 .atomic_state_alloc
= intel_atomic_state_alloc
,
14317 .atomic_state_clear
= intel_atomic_state_clear
,
14320 /* Set up chip specific display functions */
14321 static void intel_init_display(struct drm_device
*dev
)
14323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14325 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14326 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14327 else if (IS_CHERRYVIEW(dev
))
14328 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14329 else if (IS_VALLEYVIEW(dev
))
14330 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14331 else if (IS_PINEVIEW(dev
))
14332 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14334 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14336 if (INTEL_INFO(dev
)->gen
>= 9) {
14337 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14338 dev_priv
->display
.get_initial_plane_config
=
14339 skylake_get_initial_plane_config
;
14340 dev_priv
->display
.crtc_compute_clock
=
14341 haswell_crtc_compute_clock
;
14342 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14343 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14344 dev_priv
->display
.update_primary_plane
=
14345 skylake_update_primary_plane
;
14346 } else if (HAS_DDI(dev
)) {
14347 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14348 dev_priv
->display
.get_initial_plane_config
=
14349 ironlake_get_initial_plane_config
;
14350 dev_priv
->display
.crtc_compute_clock
=
14351 haswell_crtc_compute_clock
;
14352 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14353 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14354 dev_priv
->display
.update_primary_plane
=
14355 ironlake_update_primary_plane
;
14356 } else if (HAS_PCH_SPLIT(dev
)) {
14357 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14358 dev_priv
->display
.get_initial_plane_config
=
14359 ironlake_get_initial_plane_config
;
14360 dev_priv
->display
.crtc_compute_clock
=
14361 ironlake_crtc_compute_clock
;
14362 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14363 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14364 dev_priv
->display
.update_primary_plane
=
14365 ironlake_update_primary_plane
;
14366 } else if (IS_VALLEYVIEW(dev
)) {
14367 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14368 dev_priv
->display
.get_initial_plane_config
=
14369 i9xx_get_initial_plane_config
;
14370 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14371 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14372 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14373 dev_priv
->display
.update_primary_plane
=
14374 i9xx_update_primary_plane
;
14376 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14377 dev_priv
->display
.get_initial_plane_config
=
14378 i9xx_get_initial_plane_config
;
14379 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14380 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14381 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14382 dev_priv
->display
.update_primary_plane
=
14383 i9xx_update_primary_plane
;
14386 /* Returns the core display clock speed */
14387 if (IS_SKYLAKE(dev
))
14388 dev_priv
->display
.get_display_clock_speed
=
14389 skylake_get_display_clock_speed
;
14390 else if (IS_BROXTON(dev
))
14391 dev_priv
->display
.get_display_clock_speed
=
14392 broxton_get_display_clock_speed
;
14393 else if (IS_BROADWELL(dev
))
14394 dev_priv
->display
.get_display_clock_speed
=
14395 broadwell_get_display_clock_speed
;
14396 else if (IS_HASWELL(dev
))
14397 dev_priv
->display
.get_display_clock_speed
=
14398 haswell_get_display_clock_speed
;
14399 else if (IS_VALLEYVIEW(dev
))
14400 dev_priv
->display
.get_display_clock_speed
=
14401 valleyview_get_display_clock_speed
;
14402 else if (IS_GEN5(dev
))
14403 dev_priv
->display
.get_display_clock_speed
=
14404 ilk_get_display_clock_speed
;
14405 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14406 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
))
14407 dev_priv
->display
.get_display_clock_speed
=
14408 i945_get_display_clock_speed
;
14409 else if (IS_GM45(dev
))
14410 dev_priv
->display
.get_display_clock_speed
=
14411 gm45_get_display_clock_speed
;
14412 else if (IS_CRESTLINE(dev
))
14413 dev_priv
->display
.get_display_clock_speed
=
14414 i965gm_get_display_clock_speed
;
14415 else if (IS_PINEVIEW(dev
))
14416 dev_priv
->display
.get_display_clock_speed
=
14417 pnv_get_display_clock_speed
;
14418 else if (IS_G33(dev
) || IS_G4X(dev
))
14419 dev_priv
->display
.get_display_clock_speed
=
14420 g33_get_display_clock_speed
;
14421 else if (IS_I915G(dev
))
14422 dev_priv
->display
.get_display_clock_speed
=
14423 i915_get_display_clock_speed
;
14424 else if (IS_I945GM(dev
) || IS_845G(dev
))
14425 dev_priv
->display
.get_display_clock_speed
=
14426 i9xx_misc_get_display_clock_speed
;
14427 else if (IS_PINEVIEW(dev
))
14428 dev_priv
->display
.get_display_clock_speed
=
14429 pnv_get_display_clock_speed
;
14430 else if (IS_I915GM(dev
))
14431 dev_priv
->display
.get_display_clock_speed
=
14432 i915gm_get_display_clock_speed
;
14433 else if (IS_I865G(dev
))
14434 dev_priv
->display
.get_display_clock_speed
=
14435 i865_get_display_clock_speed
;
14436 else if (IS_I85X(dev
))
14437 dev_priv
->display
.get_display_clock_speed
=
14438 i85x_get_display_clock_speed
;
14440 WARN(!IS_I830(dev
), "Unknown platform. Assuming 133 MHz CDCLK\n");
14441 dev_priv
->display
.get_display_clock_speed
=
14442 i830_get_display_clock_speed
;
14445 if (IS_GEN5(dev
)) {
14446 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14447 } else if (IS_GEN6(dev
)) {
14448 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14449 } else if (IS_IVYBRIDGE(dev
)) {
14450 /* FIXME: detect B0+ stepping and use auto training */
14451 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14452 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14453 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14454 if (IS_BROADWELL(dev
)) {
14455 dev_priv
->display
.modeset_commit_cdclk
=
14456 broadwell_modeset_commit_cdclk
;
14457 dev_priv
->display
.modeset_calc_cdclk
=
14458 broadwell_modeset_calc_cdclk
;
14460 } else if (IS_VALLEYVIEW(dev
)) {
14461 dev_priv
->display
.modeset_commit_cdclk
=
14462 valleyview_modeset_commit_cdclk
;
14463 dev_priv
->display
.modeset_calc_cdclk
=
14464 valleyview_modeset_calc_cdclk
;
14465 } else if (IS_BROXTON(dev
)) {
14466 dev_priv
->display
.modeset_commit_cdclk
=
14467 broxton_modeset_commit_cdclk
;
14468 dev_priv
->display
.modeset_calc_cdclk
=
14469 broxton_modeset_calc_cdclk
;
14472 switch (INTEL_INFO(dev
)->gen
) {
14474 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14478 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14483 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14487 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14490 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14491 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14494 /* Drop through - unsupported since execlist only. */
14496 /* Default just returns -ENODEV to indicate unsupported */
14497 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14500 intel_panel_init_backlight_funcs(dev
);
14502 mutex_init(&dev_priv
->pps_mutex
);
14506 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14507 * resume, or other times. This quirk makes sure that's the case for
14508 * affected systems.
14510 static void quirk_pipea_force(struct drm_device
*dev
)
14512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14514 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14515 DRM_INFO("applying pipe a force quirk\n");
14518 static void quirk_pipeb_force(struct drm_device
*dev
)
14520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14522 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14523 DRM_INFO("applying pipe b force quirk\n");
14527 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14529 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14532 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14533 DRM_INFO("applying lvds SSC disable quirk\n");
14537 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14540 static void quirk_invert_brightness(struct drm_device
*dev
)
14542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14543 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14544 DRM_INFO("applying inverted panel brightness quirk\n");
14547 /* Some VBT's incorrectly indicate no backlight is present */
14548 static void quirk_backlight_present(struct drm_device
*dev
)
14550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14551 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14552 DRM_INFO("applying backlight present quirk\n");
14555 struct intel_quirk
{
14557 int subsystem_vendor
;
14558 int subsystem_device
;
14559 void (*hook
)(struct drm_device
*dev
);
14562 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14563 struct intel_dmi_quirk
{
14564 void (*hook
)(struct drm_device
*dev
);
14565 const struct dmi_system_id (*dmi_id_list
)[];
14568 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14570 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14574 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14576 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14578 .callback
= intel_dmi_reverse_brightness
,
14579 .ident
= "NCR Corporation",
14580 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14581 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14584 { } /* terminating entry */
14586 .hook
= quirk_invert_brightness
,
14590 static struct intel_quirk intel_quirks
[] = {
14591 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14592 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14594 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14595 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14597 /* 830 needs to leave pipe A & dpll A up */
14598 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14600 /* 830 needs to leave pipe B & dpll B up */
14601 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14603 /* Lenovo U160 cannot use SSC on LVDS */
14604 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14606 /* Sony Vaio Y cannot use SSC on LVDS */
14607 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14609 /* Acer Aspire 5734Z must invert backlight brightness */
14610 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14612 /* Acer/eMachines G725 */
14613 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14615 /* Acer/eMachines e725 */
14616 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14618 /* Acer/Packard Bell NCL20 */
14619 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14621 /* Acer Aspire 4736Z */
14622 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14624 /* Acer Aspire 5336 */
14625 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14627 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14628 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14630 /* Acer C720 Chromebook (Core i3 4005U) */
14631 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14633 /* Apple Macbook 2,1 (Core 2 T7400) */
14634 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14636 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14637 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14639 /* HP Chromebook 14 (Celeron 2955U) */
14640 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14642 /* Dell Chromebook 11 */
14643 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14646 static void intel_init_quirks(struct drm_device
*dev
)
14648 struct pci_dev
*d
= dev
->pdev
;
14651 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14652 struct intel_quirk
*q
= &intel_quirks
[i
];
14654 if (d
->device
== q
->device
&&
14655 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14656 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14657 (d
->subsystem_device
== q
->subsystem_device
||
14658 q
->subsystem_device
== PCI_ANY_ID
))
14661 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14662 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14663 intel_dmi_quirks
[i
].hook(dev
);
14667 /* Disable the VGA plane that we never use */
14668 static void i915_disable_vga(struct drm_device
*dev
)
14670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14672 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14674 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14675 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14676 outb(SR01
, VGA_SR_INDEX
);
14677 sr1
= inb(VGA_SR_DATA
);
14678 outb(sr1
| 1<<5, VGA_SR_DATA
);
14679 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14682 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14683 POSTING_READ(vga_reg
);
14686 void intel_modeset_init_hw(struct drm_device
*dev
)
14688 intel_update_cdclk(dev
);
14689 intel_prepare_ddi(dev
);
14690 intel_init_clock_gating(dev
);
14691 intel_enable_gt_powersave(dev
);
14694 void intel_modeset_init(struct drm_device
*dev
)
14696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14699 struct intel_crtc
*crtc
;
14701 drm_mode_config_init(dev
);
14703 dev
->mode_config
.min_width
= 0;
14704 dev
->mode_config
.min_height
= 0;
14706 dev
->mode_config
.preferred_depth
= 24;
14707 dev
->mode_config
.prefer_shadow
= 1;
14709 dev
->mode_config
.allow_fb_modifiers
= true;
14711 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14713 intel_init_quirks(dev
);
14715 intel_init_pm(dev
);
14717 if (INTEL_INFO(dev
)->num_pipes
== 0)
14721 * There may be no VBT; and if the BIOS enabled SSC we can
14722 * just keep using it to avoid unnecessary flicker. Whereas if the
14723 * BIOS isn't using it, don't assume it will work even if the VBT
14724 * indicates as much.
14726 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
14727 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14730 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
14731 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14732 bios_lvds_use_ssc
? "en" : "dis",
14733 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
14734 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
14738 intel_init_display(dev
);
14739 intel_init_audio(dev
);
14741 if (IS_GEN2(dev
)) {
14742 dev
->mode_config
.max_width
= 2048;
14743 dev
->mode_config
.max_height
= 2048;
14744 } else if (IS_GEN3(dev
)) {
14745 dev
->mode_config
.max_width
= 4096;
14746 dev
->mode_config
.max_height
= 4096;
14748 dev
->mode_config
.max_width
= 8192;
14749 dev
->mode_config
.max_height
= 8192;
14752 if (IS_845G(dev
) || IS_I865G(dev
)) {
14753 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14754 dev
->mode_config
.cursor_height
= 1023;
14755 } else if (IS_GEN2(dev
)) {
14756 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14757 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14759 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14760 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14763 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14765 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14766 INTEL_INFO(dev
)->num_pipes
,
14767 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14769 for_each_pipe(dev_priv
, pipe
) {
14770 intel_crtc_init(dev
, pipe
);
14771 for_each_sprite(dev_priv
, pipe
, sprite
) {
14772 ret
= intel_plane_init(dev
, pipe
, sprite
);
14774 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14775 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14779 intel_shared_dpll_init(dev
);
14781 /* Just disable it once at startup */
14782 i915_disable_vga(dev
);
14783 intel_setup_outputs(dev
);
14785 /* Just in case the BIOS is doing something questionable. */
14786 intel_fbc_disable(dev_priv
);
14788 drm_modeset_lock_all(dev
);
14789 intel_modeset_setup_hw_state(dev
);
14790 drm_modeset_unlock_all(dev
);
14792 for_each_intel_crtc(dev
, crtc
) {
14793 struct intel_initial_plane_config plane_config
= {};
14799 * Note that reserving the BIOS fb up front prevents us
14800 * from stuffing other stolen allocations like the ring
14801 * on top. This prevents some ugliness at boot time, and
14802 * can even allow for smooth boot transitions if the BIOS
14803 * fb is large enough for the active pipe configuration.
14805 dev_priv
->display
.get_initial_plane_config(crtc
,
14809 * If the fb is shared between multiple heads, we'll
14810 * just get the first one.
14812 intel_find_initial_plane_obj(crtc
, &plane_config
);
14816 static void intel_enable_pipe_a(struct drm_device
*dev
)
14818 struct intel_connector
*connector
;
14819 struct drm_connector
*crt
= NULL
;
14820 struct intel_load_detect_pipe load_detect_temp
;
14821 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14823 /* We can't just switch on the pipe A, we need to set things up with a
14824 * proper mode and output configuration. As a gross hack, enable pipe A
14825 * by enabling the load detect pipe once. */
14826 for_each_intel_connector(dev
, connector
) {
14827 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14828 crt
= &connector
->base
;
14836 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14837 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14841 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14843 struct drm_device
*dev
= crtc
->base
.dev
;
14844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14847 if (INTEL_INFO(dev
)->num_pipes
== 1)
14850 reg
= DSPCNTR(!crtc
->plane
);
14851 val
= I915_READ(reg
);
14853 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14854 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14860 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
14862 struct drm_device
*dev
= crtc
->base
.dev
;
14863 struct intel_encoder
*encoder
;
14865 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
14871 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14873 struct drm_device
*dev
= crtc
->base
.dev
;
14874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14877 /* Clear any frame start delays used for debugging left by the BIOS */
14878 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14879 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14881 /* restore vblank interrupts to correct state */
14882 drm_crtc_vblank_reset(&crtc
->base
);
14883 if (crtc
->active
) {
14884 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
14885 update_scanline_offset(crtc
);
14886 drm_crtc_vblank_on(&crtc
->base
);
14889 /* We need to sanitize the plane -> pipe mapping first because this will
14890 * disable the crtc (and hence change the state) if it is wrong. Note
14891 * that gen4+ has a fixed plane -> pipe mapping. */
14892 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14895 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14896 crtc
->base
.base
.id
);
14898 /* Pipe has the wrong plane attached and the plane is active.
14899 * Temporarily change the plane mapping and disable everything
14901 plane
= crtc
->plane
;
14902 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
14903 crtc
->plane
= !plane
;
14904 intel_crtc_disable_noatomic(&crtc
->base
);
14905 crtc
->plane
= plane
;
14908 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14909 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14910 /* BIOS forgot to enable pipe A, this mostly happens after
14911 * resume. Force-enable the pipe to fix this, the update_dpms
14912 * call below we restore the pipe to the right state, but leave
14913 * the required bits on. */
14914 intel_enable_pipe_a(dev
);
14917 /* Adjust the state of the output pipe according to whether we
14918 * have active connectors/encoders. */
14919 if (!intel_crtc_has_encoders(crtc
))
14920 intel_crtc_disable_noatomic(&crtc
->base
);
14922 if (crtc
->active
!= crtc
->base
.state
->active
) {
14923 struct intel_encoder
*encoder
;
14925 /* This can happen either due to bugs in the get_hw_state
14926 * functions or because of calls to intel_crtc_disable_noatomic,
14927 * or because the pipe is force-enabled due to the
14929 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14930 crtc
->base
.base
.id
,
14931 crtc
->base
.state
->enable
? "enabled" : "disabled",
14932 crtc
->active
? "enabled" : "disabled");
14934 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, NULL
) < 0);
14935 crtc
->base
.state
->active
= crtc
->active
;
14936 crtc
->base
.enabled
= crtc
->active
;
14938 /* Because we only establish the connector -> encoder ->
14939 * crtc links if something is active, this means the
14940 * crtc is now deactivated. Break the links. connector
14941 * -> encoder links are only establish when things are
14942 * actually up, hence no need to break them. */
14943 WARN_ON(crtc
->active
);
14945 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
14946 encoder
->base
.crtc
= NULL
;
14949 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14951 * We start out with underrun reporting disabled to avoid races.
14952 * For correct bookkeeping mark this on active crtcs.
14954 * Also on gmch platforms we dont have any hardware bits to
14955 * disable the underrun reporting. Which means we need to start
14956 * out with underrun reporting disabled also on inactive pipes,
14957 * since otherwise we'll complain about the garbage we read when
14958 * e.g. coming up after runtime pm.
14960 * No protection against concurrent access is required - at
14961 * worst a fifo underrun happens which also sets this to false.
14963 crtc
->cpu_fifo_underrun_disabled
= true;
14964 crtc
->pch_fifo_underrun_disabled
= true;
14968 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14970 struct intel_connector
*connector
;
14971 struct drm_device
*dev
= encoder
->base
.dev
;
14972 bool active
= false;
14974 /* We need to check both for a crtc link (meaning that the
14975 * encoder is active and trying to read from a pipe) and the
14976 * pipe itself being active. */
14977 bool has_active_crtc
= encoder
->base
.crtc
&&
14978 to_intel_crtc(encoder
->base
.crtc
)->active
;
14980 for_each_intel_connector(dev
, connector
) {
14981 if (connector
->base
.encoder
!= &encoder
->base
)
14988 if (active
&& !has_active_crtc
) {
14989 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14990 encoder
->base
.base
.id
,
14991 encoder
->base
.name
);
14993 /* Connector is active, but has no active pipe. This is
14994 * fallout from our resume register restoring. Disable
14995 * the encoder manually again. */
14996 if (encoder
->base
.crtc
) {
14997 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14998 encoder
->base
.base
.id
,
14999 encoder
->base
.name
);
15000 encoder
->disable(encoder
);
15001 if (encoder
->post_disable
)
15002 encoder
->post_disable(encoder
);
15004 encoder
->base
.crtc
= NULL
;
15006 /* Inconsistent output/port/pipe state happens presumably due to
15007 * a bug in one of the get_hw_state functions. Or someplace else
15008 * in our code, like the register restore mess on resume. Clamp
15009 * things to off as a safer default. */
15010 for_each_intel_connector(dev
, connector
) {
15011 if (connector
->encoder
!= encoder
)
15013 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15014 connector
->base
.encoder
= NULL
;
15017 /* Enabled encoders without active connectors will be fixed in
15018 * the crtc fixup. */
15021 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15024 u32 vga_reg
= i915_vgacntrl_reg(dev
);
15026 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15027 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15028 i915_disable_vga(dev
);
15032 void i915_redisable_vga(struct drm_device
*dev
)
15034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15036 /* This function can be called both from intel_modeset_setup_hw_state or
15037 * at a very early point in our resume sequence, where the power well
15038 * structures are not yet restored. Since this function is at a very
15039 * paranoid "someone might have enabled VGA while we were not looking"
15040 * level, just check if the power well is enabled instead of trying to
15041 * follow the "don't touch the power well if we don't need it" policy
15042 * the rest of the driver uses. */
15043 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15046 i915_redisable_vga_power_on(dev
);
15049 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
15051 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
15053 return !!(I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
);
15056 static void readout_plane_state(struct intel_crtc
*crtc
,
15057 struct intel_crtc_state
*crtc_state
)
15059 struct intel_plane
*p
;
15060 struct intel_plane_state
*plane_state
;
15061 bool active
= crtc_state
->base
.active
;
15063 for_each_intel_plane(crtc
->base
.dev
, p
) {
15064 if (crtc
->pipe
!= p
->pipe
)
15067 plane_state
= to_intel_plane_state(p
->base
.state
);
15069 if (p
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
15070 plane_state
->visible
= primary_get_hw_state(crtc
);
15073 p
->disable_plane(&p
->base
, &crtc
->base
);
15075 plane_state
->visible
= false;
15080 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15084 struct intel_crtc
*crtc
;
15085 struct intel_encoder
*encoder
;
15086 struct intel_connector
*connector
;
15089 for_each_intel_crtc(dev
, crtc
) {
15090 __drm_atomic_helper_crtc_destroy_state(&crtc
->base
, crtc
->base
.state
);
15091 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
15092 crtc
->config
->base
.crtc
= &crtc
->base
;
15094 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
15097 crtc
->base
.state
->active
= crtc
->active
;
15098 crtc
->base
.enabled
= crtc
->active
;
15100 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
15101 if (crtc
->base
.state
->active
) {
15102 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
15103 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
15104 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
15107 * The initial mode needs to be set in order to keep
15108 * the atomic core happy. It wants a valid mode if the
15109 * crtc's enabled, so we do the above call.
15111 * At this point some state updated by the connectors
15112 * in their ->detect() callback has not run yet, so
15113 * no recalculation can be done yet.
15115 * Even if we could do a recalculation and modeset
15116 * right now it would cause a double modeset if
15117 * fbdev or userspace chooses a different initial mode.
15119 * If that happens, someone indicated they wanted a
15120 * mode change, which means it's safe to do a full
15123 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
15126 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
15127 readout_plane_state(crtc
, to_intel_crtc_state(crtc
->base
.state
));
15129 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15130 crtc
->base
.base
.id
,
15131 crtc
->active
? "enabled" : "disabled");
15134 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15135 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15137 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15138 &pll
->config
.hw_state
);
15140 pll
->config
.crtc_mask
= 0;
15141 for_each_intel_crtc(dev
, crtc
) {
15142 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15144 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15148 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15149 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15151 if (pll
->config
.crtc_mask
)
15152 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15155 for_each_intel_encoder(dev
, encoder
) {
15158 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15159 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15160 encoder
->base
.crtc
= &crtc
->base
;
15161 encoder
->get_config(encoder
, crtc
->config
);
15163 encoder
->base
.crtc
= NULL
;
15166 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15167 encoder
->base
.base
.id
,
15168 encoder
->base
.name
,
15169 encoder
->base
.crtc
? "enabled" : "disabled",
15173 for_each_intel_connector(dev
, connector
) {
15174 if (connector
->get_hw_state(connector
)) {
15175 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15176 connector
->base
.encoder
= &connector
->encoder
->base
;
15178 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15179 connector
->base
.encoder
= NULL
;
15181 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15182 connector
->base
.base
.id
,
15183 connector
->base
.name
,
15184 connector
->base
.encoder
? "enabled" : "disabled");
15188 /* Scan out the current hw modeset state,
15189 * and sanitizes it to the current state
15192 intel_modeset_setup_hw_state(struct drm_device
*dev
)
15194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15196 struct intel_crtc
*crtc
;
15197 struct intel_encoder
*encoder
;
15200 intel_modeset_readout_hw_state(dev
);
15202 /* HW state is read out, now we need to sanitize this mess. */
15203 for_each_intel_encoder(dev
, encoder
) {
15204 intel_sanitize_encoder(encoder
);
15207 for_each_pipe(dev_priv
, pipe
) {
15208 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15209 intel_sanitize_crtc(crtc
);
15210 intel_dump_pipe_config(crtc
, crtc
->config
,
15211 "[setup_hw_state]");
15214 intel_modeset_update_connector_atomic_state(dev
);
15216 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15217 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15219 if (!pll
->on
|| pll
->active
)
15222 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15224 pll
->disable(dev_priv
, pll
);
15228 if (IS_VALLEYVIEW(dev
))
15229 vlv_wm_get_hw_state(dev
);
15230 else if (IS_GEN9(dev
))
15231 skl_wm_get_hw_state(dev
);
15232 else if (HAS_PCH_SPLIT(dev
))
15233 ilk_wm_get_hw_state(dev
);
15235 for_each_intel_crtc(dev
, crtc
) {
15236 unsigned long put_domains
;
15238 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
);
15239 if (WARN_ON(put_domains
))
15240 modeset_put_power_domains(dev_priv
, put_domains
);
15242 intel_display_set_init_power(dev_priv
, false);
15245 void intel_display_resume(struct drm_device
*dev
)
15247 struct drm_atomic_state
*state
= drm_atomic_state_alloc(dev
);
15248 struct intel_connector
*conn
;
15249 struct intel_plane
*plane
;
15250 struct drm_crtc
*crtc
;
15256 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
15258 /* preserve complete old state, including dpll */
15259 intel_atomic_get_shared_dpll_state(state
);
15261 for_each_crtc(dev
, crtc
) {
15262 struct drm_crtc_state
*crtc_state
=
15263 drm_atomic_get_crtc_state(state
, crtc
);
15265 ret
= PTR_ERR_OR_ZERO(crtc_state
);
15269 /* force a restore */
15270 crtc_state
->mode_changed
= true;
15273 for_each_intel_plane(dev
, plane
) {
15274 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state
, &plane
->base
));
15279 for_each_intel_connector(dev
, conn
) {
15280 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state
, &conn
->base
));
15285 intel_modeset_setup_hw_state(dev
);
15287 i915_redisable_vga(dev
);
15288 ret
= drm_atomic_commit(state
);
15293 DRM_ERROR("Restoring old state failed with %i\n", ret
);
15294 drm_atomic_state_free(state
);
15297 void intel_modeset_gem_init(struct drm_device
*dev
)
15299 struct drm_crtc
*c
;
15300 struct drm_i915_gem_object
*obj
;
15303 mutex_lock(&dev
->struct_mutex
);
15304 intel_init_gt_powersave(dev
);
15305 mutex_unlock(&dev
->struct_mutex
);
15307 intel_modeset_init_hw(dev
);
15309 intel_setup_overlay(dev
);
15312 * Make sure any fbs we allocated at startup are properly
15313 * pinned & fenced. When we do the allocation it's too early
15316 for_each_crtc(dev
, c
) {
15317 obj
= intel_fb_obj(c
->primary
->fb
);
15321 mutex_lock(&dev
->struct_mutex
);
15322 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15326 mutex_unlock(&dev
->struct_mutex
);
15328 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15329 to_intel_crtc(c
)->pipe
);
15330 drm_framebuffer_unreference(c
->primary
->fb
);
15331 c
->primary
->fb
= NULL
;
15332 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
15333 update_state_fb(c
->primary
);
15334 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
15338 intel_backlight_register(dev
);
15341 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15343 struct drm_connector
*connector
= &intel_connector
->base
;
15345 intel_panel_destroy_backlight(connector
);
15346 drm_connector_unregister(connector
);
15349 void intel_modeset_cleanup(struct drm_device
*dev
)
15351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15352 struct drm_connector
*connector
;
15354 intel_disable_gt_powersave(dev
);
15356 intel_backlight_unregister(dev
);
15359 * Interrupts and polling as the first thing to avoid creating havoc.
15360 * Too much stuff here (turning of connectors, ...) would
15361 * experience fancy races otherwise.
15363 intel_irq_uninstall(dev_priv
);
15366 * Due to the hpd irq storm handling the hotplug work can re-arm the
15367 * poll handlers. Hence disable polling after hpd handling is shut down.
15369 drm_kms_helper_poll_fini(dev
);
15371 intel_unregister_dsm_handler();
15373 intel_fbc_disable(dev_priv
);
15375 /* flush any delayed tasks or pending work */
15376 flush_scheduled_work();
15378 /* destroy the backlight and sysfs files before encoders/connectors */
15379 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15380 struct intel_connector
*intel_connector
;
15382 intel_connector
= to_intel_connector(connector
);
15383 intel_connector
->unregister(intel_connector
);
15386 drm_mode_config_cleanup(dev
);
15388 intel_cleanup_overlay(dev
);
15390 mutex_lock(&dev
->struct_mutex
);
15391 intel_cleanup_gt_powersave(dev
);
15392 mutex_unlock(&dev
->struct_mutex
);
15396 * Return which encoder is currently attached for connector.
15398 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15400 return &intel_attached_encoder(connector
)->base
;
15403 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15404 struct intel_encoder
*encoder
)
15406 connector
->encoder
= encoder
;
15407 drm_mode_connector_attach_encoder(&connector
->base
,
15412 * set vga decode state - true == enable VGA decode
15414 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15417 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15420 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15421 DRM_ERROR("failed to read control word\n");
15425 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15429 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15431 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15433 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15434 DRM_ERROR("failed to write control word\n");
15441 struct intel_display_error_state
{
15443 u32 power_well_driver
;
15445 int num_transcoders
;
15447 struct intel_cursor_error_state
{
15452 } cursor
[I915_MAX_PIPES
];
15454 struct intel_pipe_error_state
{
15455 bool power_domain_on
;
15458 } pipe
[I915_MAX_PIPES
];
15460 struct intel_plane_error_state
{
15468 } plane
[I915_MAX_PIPES
];
15470 struct intel_transcoder_error_state
{
15471 bool power_domain_on
;
15472 enum transcoder cpu_transcoder
;
15485 struct intel_display_error_state
*
15486 intel_display_capture_error_state(struct drm_device
*dev
)
15488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15489 struct intel_display_error_state
*error
;
15490 int transcoders
[] = {
15498 if (INTEL_INFO(dev
)->num_pipes
== 0)
15501 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15505 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15506 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15508 for_each_pipe(dev_priv
, i
) {
15509 error
->pipe
[i
].power_domain_on
=
15510 __intel_display_power_is_enabled(dev_priv
,
15511 POWER_DOMAIN_PIPE(i
));
15512 if (!error
->pipe
[i
].power_domain_on
)
15515 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15516 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15517 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15519 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15520 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15521 if (INTEL_INFO(dev
)->gen
<= 3) {
15522 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15523 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15525 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15526 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15527 if (INTEL_INFO(dev
)->gen
>= 4) {
15528 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15529 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15532 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15534 if (HAS_GMCH_DISPLAY(dev
))
15535 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15538 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15539 if (HAS_DDI(dev_priv
->dev
))
15540 error
->num_transcoders
++; /* Account for eDP. */
15542 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15543 enum transcoder cpu_transcoder
= transcoders
[i
];
15545 error
->transcoder
[i
].power_domain_on
=
15546 __intel_display_power_is_enabled(dev_priv
,
15547 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15548 if (!error
->transcoder
[i
].power_domain_on
)
15551 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15553 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15554 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15555 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15556 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15557 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15558 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15559 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15565 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15568 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15569 struct drm_device
*dev
,
15570 struct intel_display_error_state
*error
)
15572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15578 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15579 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15580 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15581 error
->power_well_driver
);
15582 for_each_pipe(dev_priv
, i
) {
15583 err_printf(m
, "Pipe [%d]:\n", i
);
15584 err_printf(m
, " Power: %s\n",
15585 error
->pipe
[i
].power_domain_on
? "on" : "off");
15586 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15587 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15589 err_printf(m
, "Plane [%d]:\n", i
);
15590 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15591 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15592 if (INTEL_INFO(dev
)->gen
<= 3) {
15593 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15594 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15596 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15597 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15598 if (INTEL_INFO(dev
)->gen
>= 4) {
15599 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15600 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15603 err_printf(m
, "Cursor [%d]:\n", i
);
15604 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15605 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15606 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15609 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15610 err_printf(m
, "CPU transcoder: %c\n",
15611 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15612 err_printf(m
, " Power: %s\n",
15613 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15614 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15615 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15616 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15617 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15618 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15619 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15620 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15624 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15626 struct intel_crtc
*crtc
;
15628 for_each_intel_crtc(dev
, crtc
) {
15629 struct intel_unpin_work
*work
;
15631 spin_lock_irq(&dev
->event_lock
);
15633 work
= crtc
->unpin_work
;
15635 if (work
&& work
->event
&&
15636 work
->event
->base
.file_priv
== file
) {
15637 kfree(work
->event
);
15638 work
->event
= NULL
;
15641 spin_unlock_irq(&dev
->event_lock
);