projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915/sdvo: Preserve pixel-multiplier
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
357 };
358
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
371 };
372
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
385 };
386
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
398 */
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
402 };
403
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
417 },
418 .find_pll = intel_g4x_find_best_PLL,
419 };
420
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
433 },
434 .find_pll = intel_g4x_find_best_PLL,
435 };
436
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
457 },
458 .find_pll = intel_g4x_find_best_PLL,
459 };
460
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
481 },
482 .find_pll = intel_g4x_find_best_PLL,
483 };
484
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
489 .max = G4X_VCO_MAX},
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
506 };
507
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
520 };
521
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
535 };
536
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
550 };
551
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
565 };
566
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
580 };
581
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
595 };
596
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
610 };
611
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
633 };
634
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
640 int refclk = 120;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
644 refclk = 100;
645
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
649 if (refclk == 100)
650 limit = &intel_limits_ironlake_dual_lvds_100m;
651 else
652 limit = &intel_limits_ironlake_dual_lvds;
653 } else {
654 if (refclk == 100)
655 limit = &intel_limits_ironlake_single_lvds_100m;
656 else
657 limit = &intel_limits_ironlake_single_lvds;
658 }
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
660 HAS_eDP)
661 limit = &intel_limits_ironlake_display_port;
662 else
663 limit = &intel_limits_ironlake_dac;
664
665 return limit;
666 }
667
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
676 LVDS_CLKB_POWER_UP)
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
679 else
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
691
692 return limit;
693 }
694
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
696 {
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
699
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
707 else
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
712 else
713 limit = &intel_limits_pineview_sdvo;
714 } else {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
717 else
718 limit = &intel_limits_i8xx_dvo;
719 }
720 return limit;
721 }
722
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
725 {
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
730 }
731
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
733 {
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
736 return;
737 }
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
742 }
743
744 /**
745 * Returns whether any output on the specified pipe is of the specified type
746 */
747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
748 {
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct drm_encoder *l_entry;
752
753 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
754 if (l_entry && l_entry->crtc == crtc) {
755 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
756 if (intel_encoder->type == type)
757 return true;
758 }
759 }
760 return false;
761 }
762
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
764 /**
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
767 */
768
769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
770 {
771 const intel_limit_t *limit = intel_limit (crtc);
772 struct drm_device *dev = crtc->dev;
773
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock->p < limit->p.min || limit->p.max < clock->p)
777 INTELPllInvalid ("p out of range\n");
778 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock->m < limit->m.min || limit->m.max < clock->m)
785 INTELPllInvalid ("m out of range\n");
786 if (clock->n < limit->n.min || limit->n.max < clock->n)
787 INTELPllInvalid ("n out of range\n");
788 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
789 INTELPllInvalid ("vco out of range\n");
790 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
791 * connector, etc., rather than just a single range.
792 */
793 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
794 INTELPllInvalid ("dot out of range\n");
795
796 return true;
797 }
798
799 static bool
800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
801 int target, int refclk, intel_clock_t *best_clock)
802
803 {
804 struct drm_device *dev = crtc->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 intel_clock_t clock;
807 int err = target;
808
809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
810 (I915_READ(LVDS)) != 0) {
811 /*
812 * For LVDS, if the panel is on, just rely on its current
813 * settings for dual-channel. We haven't figured out how to
814 * reliably set up different single/dual channel state, if we
815 * even can.
816 */
817 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
818 LVDS_CLKB_POWER_UP)
819 clock.p2 = limit->p2.p2_fast;
820 else
821 clock.p2 = limit->p2.p2_slow;
822 } else {
823 if (target < limit->p2.dot_limit)
824 clock.p2 = limit->p2.p2_slow;
825 else
826 clock.p2 = limit->p2.p2_fast;
827 }
828
829 memset (best_clock, 0, sizeof (*best_clock));
830
831 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
832 clock.m1++) {
833 for (clock.m2 = limit->m2.min;
834 clock.m2 <= limit->m2.max; clock.m2++) {
835 /* m1 is always 0 in Pineview */
836 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
837 break;
838 for (clock.n = limit->n.min;
839 clock.n <= limit->n.max; clock.n++) {
840 for (clock.p1 = limit->p1.min;
841 clock.p1 <= limit->p1.max; clock.p1++) {
842 int this_err;
843
844 intel_clock(dev, refclk, &clock);
845
846 if (!intel_PLL_is_valid(crtc, &clock))
847 continue;
848
849 this_err = abs(clock.dot - target);
850 if (this_err < err) {
851 *best_clock = clock;
852 err = this_err;
853 }
854 }
855 }
856 }
857 }
858
859 return (err != target);
860 }
861
862 static bool
863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
864 int target, int refclk, intel_clock_t *best_clock)
865 {
866 struct drm_device *dev = crtc->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 intel_clock_t clock;
869 int max_n;
870 bool found;
871 /* approximately equals target * 0.00585 */
872 int err_most = (target >> 8) + (target >> 9);
873 found = false;
874
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
876 int lvds_reg;
877
878 if (HAS_PCH_SPLIT(dev))
879 lvds_reg = PCH_LVDS;
880 else
881 lvds_reg = LVDS;
882 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
883 LVDS_CLKB_POWER_UP)
884 clock.p2 = limit->p2.p2_fast;
885 else
886 clock.p2 = limit->p2.p2_slow;
887 } else {
888 if (target < limit->p2.dot_limit)
889 clock.p2 = limit->p2.p2_slow;
890 else
891 clock.p2 = limit->p2.p2_fast;
892 }
893
894 memset(best_clock, 0, sizeof(*best_clock));
895 max_n = limit->n.max;
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898 /* based on hardware requirement, prefere larger m1,m2 */
899 for (clock.m1 = limit->m1.max;
900 clock.m1 >= limit->m1.min; clock.m1--) {
901 for (clock.m2 = limit->m2.max;
902 clock.m2 >= limit->m2.min; clock.m2--) {
903 for (clock.p1 = limit->p1.max;
904 clock.p1 >= limit->p1.min; clock.p1--) {
905 int this_err;
906
907 intel_clock(dev, refclk, &clock);
908 if (!intel_PLL_is_valid(crtc, &clock))
909 continue;
910 this_err = abs(clock.dot - target) ;
911 if (this_err < err_most) {
912 *best_clock = clock;
913 err_most = this_err;
914 max_n = clock.n;
915 found = true;
916 }
917 }
918 }
919 }
920 }
921 return found;
922 }
923
924 static bool
925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
926 int target, int refclk, intel_clock_t *best_clock)
927 {
928 struct drm_device *dev = crtc->dev;
929 intel_clock_t clock;
930
931 /* return directly when it is eDP */
932 if (HAS_eDP)
933 return true;
934
935 if (target < 200000) {
936 clock.n = 1;
937 clock.p1 = 2;
938 clock.p2 = 10;
939 clock.m1 = 12;
940 clock.m2 = 9;
941 } else {
942 clock.n = 2;
943 clock.p1 = 1;
944 clock.p2 = 10;
945 clock.m1 = 14;
946 clock.m2 = 8;
947 }
948 intel_clock(dev, refclk, &clock);
949 memcpy(best_clock, &clock, sizeof(intel_clock_t));
950 return true;
951 }
952
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
954 static bool
955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
956 int target, int refclk, intel_clock_t *best_clock)
957 {
958 intel_clock_t clock;
959 if (target < 200000) {
960 clock.p1 = 2;
961 clock.p2 = 10;
962 clock.n = 2;
963 clock.m1 = 23;
964 clock.m2 = 8;
965 } else {
966 clock.p1 = 1;
967 clock.p2 = 10;
968 clock.n = 1;
969 clock.m1 = 14;
970 clock.m2 = 2;
971 }
972 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
973 clock.p = (clock.p1 * clock.p2);
974 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
975 clock.vco = 0;
976 memcpy(best_clock, &clock, sizeof(intel_clock_t));
977 return true;
978 }
979
980 /**
981 * intel_wait_for_vblank - wait for vblank on a given pipe
982 * @dev: drm device
983 * @pipe: pipe to wait for
984 *
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
986 * mode setting code.
987 */
988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
989 {
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
992
993 /* Clear existing vblank status. Note this will clear any other
994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for(I915_READ(pipestat_reg) &
1011 PIPE_VBLANK_INTERRUPT_STATUS,
1012 50))
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 }
1015
1016 /**
1017 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1018 * @dev: drm device
1019 * @pipe: pipe to wait for
1020 *
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1024 *
1025 * So this function waits for the display line value to settle (it
1026 * usually ends up stopping at the start of the next frame).
1027 */
1028 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1029 {
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033 u32 last_line;
1034
1035 /* Wait for the display line to settle */
1036 do {
1037 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1038 mdelay(5);
1039 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1040 time_after(timeout, jiffies));
1041
1042 if (time_after(jiffies, timeout))
1043 DRM_DEBUG_KMS("vblank wait timed out\n");
1044 }
1045
1046 /* Parameters have changed, update FBC info */
1047 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1048 {
1049 struct drm_device *dev = crtc->dev;
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 struct drm_framebuffer *fb = crtc->fb;
1052 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1053 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1055 int plane, i;
1056 u32 fbc_ctl, fbc_ctl2;
1057
1058 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1059
1060 if (fb->pitch < dev_priv->cfb_pitch)
1061 dev_priv->cfb_pitch = fb->pitch;
1062
1063 /* FBC_CTL wants 64B units */
1064 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1065 dev_priv->cfb_fence = obj_priv->fence_reg;
1066 dev_priv->cfb_plane = intel_crtc->plane;
1067 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1068
1069 /* Clear old tags */
1070 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1071 I915_WRITE(FBC_TAG + (i * 4), 0);
1072
1073 /* Set it up... */
1074 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1075 if (obj_priv->tiling_mode != I915_TILING_NONE)
1076 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1077 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1078 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1079
1080 /* enable it... */
1081 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1082 if (IS_I945GM(dev))
1083 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1084 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1085 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1086 if (obj_priv->tiling_mode != I915_TILING_NONE)
1087 fbc_ctl |= dev_priv->cfb_fence;
1088 I915_WRITE(FBC_CONTROL, fbc_ctl);
1089
1090 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1091 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1092 }
1093
1094 void i8xx_disable_fbc(struct drm_device *dev)
1095 {
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 fbc_ctl;
1098
1099 if (!I915_HAS_FBC(dev))
1100 return;
1101
1102 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1103 return; /* Already off, just return */
1104
1105 /* Disable compression */
1106 fbc_ctl = I915_READ(FBC_CONTROL);
1107 fbc_ctl &= ~FBC_CTL_EN;
1108 I915_WRITE(FBC_CONTROL, fbc_ctl);
1109
1110 /* Wait for compressing bit to clear */
1111 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1112 DRM_DEBUG_KMS("FBC idle timed out\n");
1113 return;
1114 }
1115
1116 DRM_DEBUG_KMS("disabled FBC\n");
1117 }
1118
1119 static bool i8xx_fbc_enabled(struct drm_device *dev)
1120 {
1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122
1123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1124 }
1125
1126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127 {
1128 struct drm_device *dev = crtc->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130 struct drm_framebuffer *fb = crtc->fb;
1131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1132 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1135 DPFC_CTL_PLANEB);
1136 unsigned long stall_watermark = 200;
1137 u32 dpfc_ctl;
1138
1139 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1140 dev_priv->cfb_fence = obj_priv->fence_reg;
1141 dev_priv->cfb_plane = intel_crtc->plane;
1142
1143 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1144 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1145 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1146 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1147 } else {
1148 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1149 }
1150
1151 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1152 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1153 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1154 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1155 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1156
1157 /* enable it... */
1158 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1159
1160 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1161 }
1162
1163 void g4x_disable_fbc(struct drm_device *dev)
1164 {
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 dpfc_ctl;
1167
1168 /* Disable compression */
1169 dpfc_ctl = I915_READ(DPFC_CONTROL);
1170 dpfc_ctl &= ~DPFC_CTL_EN;
1171 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1172
1173 DRM_DEBUG_KMS("disabled FBC\n");
1174 }
1175
1176 static bool g4x_fbc_enabled(struct drm_device *dev)
1177 {
1178 struct drm_i915_private *dev_priv = dev->dev_private;
1179
1180 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1181 }
1182
1183 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1184 {
1185 struct drm_device *dev = crtc->dev;
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 struct drm_framebuffer *fb = crtc->fb;
1188 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1189 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1191 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1192 DPFC_CTL_PLANEB;
1193 unsigned long stall_watermark = 200;
1194 u32 dpfc_ctl;
1195
1196 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1197 dev_priv->cfb_fence = obj_priv->fence_reg;
1198 dev_priv->cfb_plane = intel_crtc->plane;
1199
1200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1201 dpfc_ctl &= DPFC_RESERVED;
1202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1203 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1206 } else {
1207 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1208 }
1209
1210 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1211 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1212 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1213 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1214 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1215 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1216 /* enable it... */
1217 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1218 DPFC_CTL_EN);
1219
1220 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1221 }
1222
1223 void ironlake_disable_fbc(struct drm_device *dev)
1224 {
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 u32 dpfc_ctl;
1227
1228 /* Disable compression */
1229 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1230 dpfc_ctl &= ~DPFC_CTL_EN;
1231 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1232
1233 DRM_DEBUG_KMS("disabled FBC\n");
1234 }
1235
1236 static bool ironlake_fbc_enabled(struct drm_device *dev)
1237 {
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239
1240 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1241 }
1242
1243 bool intel_fbc_enabled(struct drm_device *dev)
1244 {
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246
1247 if (!dev_priv->display.fbc_enabled)
1248 return false;
1249
1250 return dev_priv->display.fbc_enabled(dev);
1251 }
1252
1253 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1254 {
1255 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1256
1257 if (!dev_priv->display.enable_fbc)
1258 return;
1259
1260 dev_priv->display.enable_fbc(crtc, interval);
1261 }
1262
1263 void intel_disable_fbc(struct drm_device *dev)
1264 {
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266
1267 if (!dev_priv->display.disable_fbc)
1268 return;
1269
1270 dev_priv->display.disable_fbc(dev);
1271 }
1272
1273 /**
1274 * intel_update_fbc - enable/disable FBC as needed
1275 * @crtc: CRTC to point the compressor at
1276 * @mode: mode in use
1277 *
1278 * Set up the framebuffer compression hardware at mode set time. We
1279 * enable it if possible:
1280 * - plane A only (on pre-965)
1281 * - no pixel mulitply/line duplication
1282 * - no alpha buffer discard
1283 * - no dual wide
1284 * - framebuffer <= 2048 in width, 1536 in height
1285 *
1286 * We can't assume that any compression will take place (worst case),
1287 * so the compressed buffer has to be the same size as the uncompressed
1288 * one. It also must reside (along with the line length buffer) in
1289 * stolen memory.
1290 *
1291 * We need to enable/disable FBC on a global basis.
1292 */
1293 static void intel_update_fbc(struct drm_crtc *crtc,
1294 struct drm_display_mode *mode)
1295 {
1296 struct drm_device *dev = crtc->dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 struct drm_framebuffer *fb = crtc->fb;
1299 struct intel_framebuffer *intel_fb;
1300 struct drm_i915_gem_object *obj_priv;
1301 struct drm_crtc *tmp_crtc;
1302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1303 int plane = intel_crtc->plane;
1304 int crtcs_enabled = 0;
1305
1306 DRM_DEBUG_KMS("\n");
1307
1308 if (!i915_powersave)
1309 return;
1310
1311 if (!I915_HAS_FBC(dev))
1312 return;
1313
1314 if (!crtc->fb)
1315 return;
1316
1317 intel_fb = to_intel_framebuffer(fb);
1318 obj_priv = to_intel_bo(intel_fb->obj);
1319
1320 /*
1321 * If FBC is already on, we just have to verify that we can
1322 * keep it that way...
1323 * Need to disable if:
1324 * - more than one pipe is active
1325 * - changing FBC params (stride, fence, mode)
1326 * - new fb is too large to fit in compressed buffer
1327 * - going to an unsupported config (interlace, pixel multiply, etc.)
1328 */
1329 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1330 if (tmp_crtc->enabled)
1331 crtcs_enabled++;
1332 }
1333 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1334 if (crtcs_enabled > 1) {
1335 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1336 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1337 goto out_disable;
1338 }
1339 if (intel_fb->obj->size > dev_priv->cfb_size) {
1340 DRM_DEBUG_KMS("framebuffer too large, disabling "
1341 "compression\n");
1342 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1343 goto out_disable;
1344 }
1345 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1346 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1347 DRM_DEBUG_KMS("mode incompatible with compression, "
1348 "disabling\n");
1349 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1350 goto out_disable;
1351 }
1352 if ((mode->hdisplay > 2048) ||
1353 (mode->vdisplay > 1536)) {
1354 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1355 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1356 goto out_disable;
1357 }
1358 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1359 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1360 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1361 goto out_disable;
1362 }
1363 if (obj_priv->tiling_mode != I915_TILING_X) {
1364 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1365 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1366 goto out_disable;
1367 }
1368
1369 /* If the kernel debugger is active, always disable compression */
1370 if (in_dbg_master())
1371 goto out_disable;
1372
1373 if (intel_fbc_enabled(dev)) {
1374 /* We can re-enable it in this case, but need to update pitch */
1375 if ((fb->pitch > dev_priv->cfb_pitch) ||
1376 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1377 (plane != dev_priv->cfb_plane))
1378 intel_disable_fbc(dev);
1379 }
1380
1381 /* Now try to turn it back on if possible */
1382 if (!intel_fbc_enabled(dev))
1383 intel_enable_fbc(crtc, 500);
1384
1385 return;
1386
1387 out_disable:
1388 /* Multiple disables should be harmless */
1389 if (intel_fbc_enabled(dev)) {
1390 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1391 intel_disable_fbc(dev);
1392 }
1393 }
1394
1395 int
1396 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1397 {
1398 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1399 u32 alignment;
1400 int ret;
1401
1402 switch (obj_priv->tiling_mode) {
1403 case I915_TILING_NONE:
1404 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1405 alignment = 128 * 1024;
1406 else if (IS_I965G(dev))
1407 alignment = 4 * 1024;
1408 else
1409 alignment = 64 * 1024;
1410 break;
1411 case I915_TILING_X:
1412 /* pin() will align the object as required by fence */
1413 alignment = 0;
1414 break;
1415 case I915_TILING_Y:
1416 /* FIXME: Is this true? */
1417 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1418 return -EINVAL;
1419 default:
1420 BUG();
1421 }
1422
1423 ret = i915_gem_object_pin(obj, alignment);
1424 if (ret != 0)
1425 return ret;
1426
1427 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1428 * fence, whereas 965+ only requires a fence if using
1429 * framebuffer compression. For simplicity, we always install
1430 * a fence as the cost is not that onerous.
1431 */
1432 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1433 obj_priv->tiling_mode != I915_TILING_NONE) {
1434 ret = i915_gem_object_get_fence_reg(obj);
1435 if (ret != 0) {
1436 i915_gem_object_unpin(obj);
1437 return ret;
1438 }
1439 }
1440
1441 return 0;
1442 }
1443
1444 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1445 static int
1446 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1447 int x, int y)
1448 {
1449 struct drm_device *dev = crtc->dev;
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1452 struct intel_framebuffer *intel_fb;
1453 struct drm_i915_gem_object *obj_priv;
1454 struct drm_gem_object *obj;
1455 int plane = intel_crtc->plane;
1456 unsigned long Start, Offset;
1457 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1458 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1459 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1460 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1461 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1462 u32 dspcntr;
1463
1464 switch (plane) {
1465 case 0:
1466 case 1:
1467 break;
1468 default:
1469 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1470 return -EINVAL;
1471 }
1472
1473 intel_fb = to_intel_framebuffer(fb);
1474 obj = intel_fb->obj;
1475 obj_priv = to_intel_bo(obj);
1476
1477 dspcntr = I915_READ(dspcntr_reg);
1478 /* Mask out pixel format bits in case we change it */
1479 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1480 switch (fb->bits_per_pixel) {
1481 case 8:
1482 dspcntr |= DISPPLANE_8BPP;
1483 break;
1484 case 16:
1485 if (fb->depth == 15)
1486 dspcntr |= DISPPLANE_15_16BPP;
1487 else
1488 dspcntr |= DISPPLANE_16BPP;
1489 break;
1490 case 24:
1491 case 32:
1492 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1493 break;
1494 default:
1495 DRM_ERROR("Unknown color depth\n");
1496 return -EINVAL;
1497 }
1498 if (IS_I965G(dev)) {
1499 if (obj_priv->tiling_mode != I915_TILING_NONE)
1500 dspcntr |= DISPPLANE_TILED;
1501 else
1502 dspcntr &= ~DISPPLANE_TILED;
1503 }
1504
1505 if (HAS_PCH_SPLIT(dev))
1506 /* must disable */
1507 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1508
1509 I915_WRITE(dspcntr_reg, dspcntr);
1510
1511 Start = obj_priv->gtt_offset;
1512 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1513
1514 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515 Start, Offset, x, y, fb->pitch);
1516 I915_WRITE(dspstride, fb->pitch);
1517 if (IS_I965G(dev)) {
1518 I915_WRITE(dspsurf, Start);
1519 I915_WRITE(dsptileoff, (y << 16) | x);
1520 I915_WRITE(dspbase, Offset);
1521 } else {
1522 I915_WRITE(dspbase, Start + Offset);
1523 }
1524 POSTING_READ(dspbase);
1525
1526 if (IS_I965G(dev) || plane == 0)
1527 intel_update_fbc(crtc, &crtc->mode);
1528
1529 intel_wait_for_vblank(dev, intel_crtc->pipe);
1530 intel_increase_pllclock(crtc);
1531
1532 return 0;
1533 }
1534
1535 static int
1536 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1537 struct drm_framebuffer *old_fb)
1538 {
1539 struct drm_device *dev = crtc->dev;
1540 struct drm_i915_master_private *master_priv;
1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1542 struct intel_framebuffer *intel_fb;
1543 struct drm_i915_gem_object *obj_priv;
1544 struct drm_gem_object *obj;
1545 int pipe = intel_crtc->pipe;
1546 int plane = intel_crtc->plane;
1547 int ret;
1548
1549 /* no fb bound */
1550 if (!crtc->fb) {
1551 DRM_DEBUG_KMS("No FB bound\n");
1552 return 0;
1553 }
1554
1555 switch (plane) {
1556 case 0:
1557 case 1:
1558 break;
1559 default:
1560 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1561 return -EINVAL;
1562 }
1563
1564 intel_fb = to_intel_framebuffer(crtc->fb);
1565 obj = intel_fb->obj;
1566 obj_priv = to_intel_bo(obj);
1567
1568 mutex_lock(&dev->struct_mutex);
1569 ret = intel_pin_and_fence_fb_obj(dev, obj);
1570 if (ret != 0) {
1571 mutex_unlock(&dev->struct_mutex);
1572 return ret;
1573 }
1574
1575 ret = i915_gem_object_set_to_display_plane(obj);
1576 if (ret != 0) {
1577 i915_gem_object_unpin(obj);
1578 mutex_unlock(&dev->struct_mutex);
1579 return ret;
1580 }
1581
1582 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1583 if (ret) {
1584 i915_gem_object_unpin(obj);
1585 mutex_unlock(&dev->struct_mutex);
1586 return ret;
1587 }
1588
1589 if (old_fb) {
1590 intel_fb = to_intel_framebuffer(old_fb);
1591 obj_priv = to_intel_bo(intel_fb->obj);
1592 i915_gem_object_unpin(intel_fb->obj);
1593 }
1594
1595 mutex_unlock(&dev->struct_mutex);
1596
1597 if (!dev->primary->master)
1598 return 0;
1599
1600 master_priv = dev->primary->master->driver_priv;
1601 if (!master_priv->sarea_priv)
1602 return 0;
1603
1604 if (pipe) {
1605 master_priv->sarea_priv->pipeB_x = x;
1606 master_priv->sarea_priv->pipeB_y = y;
1607 } else {
1608 master_priv->sarea_priv->pipeA_x = x;
1609 master_priv->sarea_priv->pipeA_y = y;
1610 }
1611
1612 return 0;
1613 }
1614
1615 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1616 {
1617 struct drm_device *dev = crtc->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 u32 dpa_ctl;
1620
1621 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1622 dpa_ctl = I915_READ(DP_A);
1623 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1624
1625 if (clock < 200000) {
1626 u32 temp;
1627 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1628 /* workaround for 160Mhz:
1629 1) program 0x4600c bits 15:0 = 0x8124
1630 2) program 0x46010 bit 0 = 1
1631 3) program 0x46034 bit 24 = 1
1632 4) program 0x64000 bit 14 = 1
1633 */
1634 temp = I915_READ(0x4600c);
1635 temp &= 0xffff0000;
1636 I915_WRITE(0x4600c, temp | 0x8124);
1637
1638 temp = I915_READ(0x46010);
1639 I915_WRITE(0x46010, temp | 1);
1640
1641 temp = I915_READ(0x46034);
1642 I915_WRITE(0x46034, temp | (1 << 24));
1643 } else {
1644 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1645 }
1646 I915_WRITE(DP_A, dpa_ctl);
1647
1648 udelay(500);
1649 }
1650
1651 /* The FDI link training functions for ILK/Ibexpeak. */
1652 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1653 {
1654 struct drm_device *dev = crtc->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1657 int pipe = intel_crtc->pipe;
1658 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1659 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1660 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1661 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1662 u32 temp, tries = 0;
1663
1664 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1665 for train result */
1666 temp = I915_READ(fdi_rx_imr_reg);
1667 temp &= ~FDI_RX_SYMBOL_LOCK;
1668 temp &= ~FDI_RX_BIT_LOCK;
1669 I915_WRITE(fdi_rx_imr_reg, temp);
1670 I915_READ(fdi_rx_imr_reg);
1671 udelay(150);
1672
1673 /* enable CPU FDI TX and PCH FDI RX */
1674 temp = I915_READ(fdi_tx_reg);
1675 temp |= FDI_TX_ENABLE;
1676 temp &= ~(7 << 19);
1677 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1678 temp &= ~FDI_LINK_TRAIN_NONE;
1679 temp |= FDI_LINK_TRAIN_PATTERN_1;
1680 I915_WRITE(fdi_tx_reg, temp);
1681 I915_READ(fdi_tx_reg);
1682
1683 temp = I915_READ(fdi_rx_reg);
1684 temp &= ~FDI_LINK_TRAIN_NONE;
1685 temp |= FDI_LINK_TRAIN_PATTERN_1;
1686 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1687 I915_READ(fdi_rx_reg);
1688 udelay(150);
1689
1690 for (tries = 0; tries < 5; tries++) {
1691 temp = I915_READ(fdi_rx_iir_reg);
1692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1693
1694 if ((temp & FDI_RX_BIT_LOCK)) {
1695 DRM_DEBUG_KMS("FDI train 1 done.\n");
1696 I915_WRITE(fdi_rx_iir_reg,
1697 temp | FDI_RX_BIT_LOCK);
1698 break;
1699 }
1700 }
1701 if (tries == 5)
1702 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1703
1704 /* Train 2 */
1705 temp = I915_READ(fdi_tx_reg);
1706 temp &= ~FDI_LINK_TRAIN_NONE;
1707 temp |= FDI_LINK_TRAIN_PATTERN_2;
1708 I915_WRITE(fdi_tx_reg, temp);
1709
1710 temp = I915_READ(fdi_rx_reg);
1711 temp &= ~FDI_LINK_TRAIN_NONE;
1712 temp |= FDI_LINK_TRAIN_PATTERN_2;
1713 I915_WRITE(fdi_rx_reg, temp);
1714 udelay(150);
1715
1716 tries = 0;
1717
1718 for (tries = 0; tries < 5; tries++) {
1719 temp = I915_READ(fdi_rx_iir_reg);
1720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1721
1722 if (temp & FDI_RX_SYMBOL_LOCK) {
1723 I915_WRITE(fdi_rx_iir_reg,
1724 temp | FDI_RX_SYMBOL_LOCK);
1725 DRM_DEBUG_KMS("FDI train 2 done.\n");
1726 break;
1727 }
1728 }
1729 if (tries == 5)
1730 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1731
1732 DRM_DEBUG_KMS("FDI train done\n");
1733 }
1734
1735 static int snb_b_fdi_train_param [] = {
1736 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1737 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1738 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1739 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1740 };
1741
1742 /* The FDI link training functions for SNB/Cougarpoint. */
1743 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1744 {
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1748 int pipe = intel_crtc->pipe;
1749 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1750 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1751 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1752 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1753 u32 temp, i;
1754
1755 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1756 for train result */
1757 temp = I915_READ(fdi_rx_imr_reg);
1758 temp &= ~FDI_RX_SYMBOL_LOCK;
1759 temp &= ~FDI_RX_BIT_LOCK;
1760 I915_WRITE(fdi_rx_imr_reg, temp);
1761 I915_READ(fdi_rx_imr_reg);
1762 udelay(150);
1763
1764 /* enable CPU FDI TX and PCH FDI RX */
1765 temp = I915_READ(fdi_tx_reg);
1766 temp |= FDI_TX_ENABLE;
1767 temp &= ~(7 << 19);
1768 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1769 temp &= ~FDI_LINK_TRAIN_NONE;
1770 temp |= FDI_LINK_TRAIN_PATTERN_1;
1771 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1772 /* SNB-B */
1773 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1774 I915_WRITE(fdi_tx_reg, temp);
1775 I915_READ(fdi_tx_reg);
1776
1777 temp = I915_READ(fdi_rx_reg);
1778 if (HAS_PCH_CPT(dev)) {
1779 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1780 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1781 } else {
1782 temp &= ~FDI_LINK_TRAIN_NONE;
1783 temp |= FDI_LINK_TRAIN_PATTERN_1;
1784 }
1785 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1786 I915_READ(fdi_rx_reg);
1787 udelay(150);
1788
1789 for (i = 0; i < 4; i++ ) {
1790 temp = I915_READ(fdi_tx_reg);
1791 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1792 temp |= snb_b_fdi_train_param[i];
1793 I915_WRITE(fdi_tx_reg, temp);
1794 udelay(500);
1795
1796 temp = I915_READ(fdi_rx_iir_reg);
1797 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1798
1799 if (temp & FDI_RX_BIT_LOCK) {
1800 I915_WRITE(fdi_rx_iir_reg,
1801 temp | FDI_RX_BIT_LOCK);
1802 DRM_DEBUG_KMS("FDI train 1 done.\n");
1803 break;
1804 }
1805 }
1806 if (i == 4)
1807 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1808
1809 /* Train 2 */
1810 temp = I915_READ(fdi_tx_reg);
1811 temp &= ~FDI_LINK_TRAIN_NONE;
1812 temp |= FDI_LINK_TRAIN_PATTERN_2;
1813 if (IS_GEN6(dev)) {
1814 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1815 /* SNB-B */
1816 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1817 }
1818 I915_WRITE(fdi_tx_reg, temp);
1819
1820 temp = I915_READ(fdi_rx_reg);
1821 if (HAS_PCH_CPT(dev)) {
1822 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1823 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1824 } else {
1825 temp &= ~FDI_LINK_TRAIN_NONE;
1826 temp |= FDI_LINK_TRAIN_PATTERN_2;
1827 }
1828 I915_WRITE(fdi_rx_reg, temp);
1829 udelay(150);
1830
1831 for (i = 0; i < 4; i++ ) {
1832 temp = I915_READ(fdi_tx_reg);
1833 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1834 temp |= snb_b_fdi_train_param[i];
1835 I915_WRITE(fdi_tx_reg, temp);
1836 udelay(500);
1837
1838 temp = I915_READ(fdi_rx_iir_reg);
1839 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1840
1841 if (temp & FDI_RX_SYMBOL_LOCK) {
1842 I915_WRITE(fdi_rx_iir_reg,
1843 temp | FDI_RX_SYMBOL_LOCK);
1844 DRM_DEBUG_KMS("FDI train 2 done.\n");
1845 break;
1846 }
1847 }
1848 if (i == 4)
1849 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1850
1851 DRM_DEBUG_KMS("FDI train done.\n");
1852 }
1853
1854 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1855 {
1856 struct drm_device *dev = crtc->dev;
1857 struct drm_i915_private *dev_priv = dev->dev_private;
1858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1859 int pipe = intel_crtc->pipe;
1860 int plane = intel_crtc->plane;
1861 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1862 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1863 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1864 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1865 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1866 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1867 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1868 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1869 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1870 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1871 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1872 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1873 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1874 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1875 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1876 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1877 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1878 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1879 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1880 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1881 u32 temp;
1882 u32 pipe_bpc;
1883
1884 temp = I915_READ(pipeconf_reg);
1885 pipe_bpc = temp & PIPE_BPC_MASK;
1886
1887 /* XXX: When our outputs are all unaware of DPMS modes other than off
1888 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1889 */
1890 switch (mode) {
1891 case DRM_MODE_DPMS_ON:
1892 case DRM_MODE_DPMS_STANDBY:
1893 case DRM_MODE_DPMS_SUSPEND:
1894 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1895
1896 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1897 temp = I915_READ(PCH_LVDS);
1898 if ((temp & LVDS_PORT_EN) == 0) {
1899 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1900 POSTING_READ(PCH_LVDS);
1901 }
1902 }
1903
1904 if (!HAS_eDP) {
1905
1906 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1907 temp = I915_READ(fdi_rx_reg);
1908 /*
1909 * make the BPC in FDI Rx be consistent with that in
1910 * pipeconf reg.
1911 */
1912 temp &= ~(0x7 << 16);
1913 temp |= (pipe_bpc << 11);
1914 temp &= ~(7 << 19);
1915 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1916 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1917 I915_READ(fdi_rx_reg);
1918 udelay(200);
1919
1920 /* Switch from Rawclk to PCDclk */
1921 temp = I915_READ(fdi_rx_reg);
1922 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1923 I915_READ(fdi_rx_reg);
1924 udelay(200);
1925
1926 /* Enable CPU FDI TX PLL, always on for Ironlake */
1927 temp = I915_READ(fdi_tx_reg);
1928 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1929 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1930 I915_READ(fdi_tx_reg);
1931 udelay(100);
1932 }
1933 }
1934
1935 /* Enable panel fitting for LVDS */
1936 if (dev_priv->pch_pf_size &&
1937 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1938 || HAS_eDP || intel_pch_has_edp(crtc))) {
1939 /* Force use of hard-coded filter coefficients
1940 * as some pre-programmed values are broken,
1941 * e.g. x201.
1942 */
1943 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1944 PF_ENABLE | PF_FILTER_MED_3x3);
1945 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1946 dev_priv->pch_pf_pos);
1947 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1948 dev_priv->pch_pf_size);
1949 }
1950
1951 /* Enable CPU pipe */
1952 temp = I915_READ(pipeconf_reg);
1953 if ((temp & PIPEACONF_ENABLE) == 0) {
1954 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1955 I915_READ(pipeconf_reg);
1956 udelay(100);
1957 }
1958
1959 /* configure and enable CPU plane */
1960 temp = I915_READ(dspcntr_reg);
1961 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1962 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1963 /* Flush the plane changes */
1964 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1965 }
1966
1967 if (!HAS_eDP) {
1968 /* For PCH output, training FDI link */
1969 if (IS_GEN6(dev))
1970 gen6_fdi_link_train(crtc);
1971 else
1972 ironlake_fdi_link_train(crtc);
1973
1974 /* enable PCH DPLL */
1975 temp = I915_READ(pch_dpll_reg);
1976 if ((temp & DPLL_VCO_ENABLE) == 0) {
1977 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1978 I915_READ(pch_dpll_reg);
1979 }
1980 udelay(200);
1981
1982 if (HAS_PCH_CPT(dev)) {
1983 /* Be sure PCH DPLL SEL is set */
1984 temp = I915_READ(PCH_DPLL_SEL);
1985 if (trans_dpll_sel == 0 &&
1986 (temp & TRANSA_DPLL_ENABLE) == 0)
1987 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1988 else if (trans_dpll_sel == 1 &&
1989 (temp & TRANSB_DPLL_ENABLE) == 0)
1990 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1991 I915_WRITE(PCH_DPLL_SEL, temp);
1992 I915_READ(PCH_DPLL_SEL);
1993 }
1994
1995 /* set transcoder timing */
1996 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1997 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1998 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1999
2000 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2001 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2002 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2003
2004 /* enable normal train */
2005 temp = I915_READ(fdi_tx_reg);
2006 temp &= ~FDI_LINK_TRAIN_NONE;
2007 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2008 FDI_TX_ENHANCE_FRAME_ENABLE);
2009 I915_READ(fdi_tx_reg);
2010
2011 temp = I915_READ(fdi_rx_reg);
2012 if (HAS_PCH_CPT(dev)) {
2013 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2014 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2015 } else {
2016 temp &= ~FDI_LINK_TRAIN_NONE;
2017 temp |= FDI_LINK_TRAIN_NONE;
2018 }
2019 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2020 I915_READ(fdi_rx_reg);
2021
2022 /* wait one idle pattern time */
2023 udelay(100);
2024
2025 /* For PCH DP, enable TRANS_DP_CTL */
2026 if (HAS_PCH_CPT(dev) &&
2027 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2028 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2029 int reg;
2030
2031 reg = I915_READ(trans_dp_ctl);
2032 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2033 TRANS_DP_SYNC_MASK);
2034 reg |= (TRANS_DP_OUTPUT_ENABLE |
2035 TRANS_DP_ENH_FRAMING);
2036
2037 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2038 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2039 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2040 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2041
2042 switch (intel_trans_dp_port_sel(crtc)) {
2043 case PCH_DP_B:
2044 reg |= TRANS_DP_PORT_SEL_B;
2045 break;
2046 case PCH_DP_C:
2047 reg |= TRANS_DP_PORT_SEL_C;
2048 break;
2049 case PCH_DP_D:
2050 reg |= TRANS_DP_PORT_SEL_D;
2051 break;
2052 default:
2053 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2054 reg |= TRANS_DP_PORT_SEL_B;
2055 break;
2056 }
2057
2058 I915_WRITE(trans_dp_ctl, reg);
2059 POSTING_READ(trans_dp_ctl);
2060 }
2061
2062 /* enable PCH transcoder */
2063 temp = I915_READ(transconf_reg);
2064 /*
2065 * make the BPC in transcoder be consistent with
2066 * that in pipeconf reg.
2067 */
2068 temp &= ~PIPE_BPC_MASK;
2069 temp |= pipe_bpc;
2070 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2071 I915_READ(transconf_reg);
2072
2073 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
2074 DRM_ERROR("failed to enable transcoder\n");
2075 }
2076
2077 intel_crtc_load_lut(crtc);
2078
2079 intel_update_fbc(crtc, &crtc->mode);
2080 break;
2081
2082 case DRM_MODE_DPMS_OFF:
2083 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2084
2085 drm_vblank_off(dev, pipe);
2086 /* Disable display plane */
2087 temp = I915_READ(dspcntr_reg);
2088 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2089 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2090 /* Flush the plane changes */
2091 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2092 I915_READ(dspbase_reg);
2093 }
2094
2095 if (dev_priv->cfb_plane == plane &&
2096 dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
2098
2099 /* disable cpu pipe, disable after all planes disabled */
2100 temp = I915_READ(pipeconf_reg);
2101 if ((temp & PIPEACONF_ENABLE) != 0) {
2102 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2103
2104 /* wait for cpu pipe off, pipe state */
2105 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2106 DRM_ERROR("failed to turn off cpu pipe\n");
2107 } else
2108 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2109
2110 udelay(100);
2111
2112 /* Disable PF */
2113 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2114 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2115
2116 /* disable CPU FDI tx and PCH FDI rx */
2117 temp = I915_READ(fdi_tx_reg);
2118 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2119 I915_READ(fdi_tx_reg);
2120
2121 temp = I915_READ(fdi_rx_reg);
2122 /* BPC in FDI rx is consistent with that in pipeconf */
2123 temp &= ~(0x07 << 16);
2124 temp |= (pipe_bpc << 11);
2125 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2126 I915_READ(fdi_rx_reg);
2127
2128 udelay(100);
2129
2130 /* still set train pattern 1 */
2131 temp = I915_READ(fdi_tx_reg);
2132 temp &= ~FDI_LINK_TRAIN_NONE;
2133 temp |= FDI_LINK_TRAIN_PATTERN_1;
2134 I915_WRITE(fdi_tx_reg, temp);
2135 POSTING_READ(fdi_tx_reg);
2136
2137 temp = I915_READ(fdi_rx_reg);
2138 if (HAS_PCH_CPT(dev)) {
2139 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2140 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2141 } else {
2142 temp &= ~FDI_LINK_TRAIN_NONE;
2143 temp |= FDI_LINK_TRAIN_PATTERN_1;
2144 }
2145 I915_WRITE(fdi_rx_reg, temp);
2146 POSTING_READ(fdi_rx_reg);
2147
2148 udelay(100);
2149
2150 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2151 temp = I915_READ(PCH_LVDS);
2152 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2153 I915_READ(PCH_LVDS);
2154 udelay(100);
2155 }
2156
2157 /* disable PCH transcoder */
2158 temp = I915_READ(transconf_reg);
2159 if ((temp & TRANS_ENABLE) != 0) {
2160 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2161
2162 /* wait for PCH transcoder off, transcoder state */
2163 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50))
2164 DRM_ERROR("failed to disable transcoder\n");
2165 }
2166
2167 temp = I915_READ(transconf_reg);
2168 /* BPC in transcoder is consistent with that in pipeconf */
2169 temp &= ~PIPE_BPC_MASK;
2170 temp |= pipe_bpc;
2171 I915_WRITE(transconf_reg, temp);
2172 I915_READ(transconf_reg);
2173 udelay(100);
2174
2175 if (HAS_PCH_CPT(dev)) {
2176 /* disable TRANS_DP_CTL */
2177 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2178 int reg;
2179
2180 reg = I915_READ(trans_dp_ctl);
2181 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2182 I915_WRITE(trans_dp_ctl, reg);
2183 POSTING_READ(trans_dp_ctl);
2184
2185 /* disable DPLL_SEL */
2186 temp = I915_READ(PCH_DPLL_SEL);
2187 if (trans_dpll_sel == 0)
2188 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2189 else
2190 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2191 I915_WRITE(PCH_DPLL_SEL, temp);
2192 I915_READ(PCH_DPLL_SEL);
2193
2194 }
2195
2196 /* disable PCH DPLL */
2197 temp = I915_READ(pch_dpll_reg);
2198 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2199 I915_READ(pch_dpll_reg);
2200
2201 /* Switch from PCDclk to Rawclk */
2202 temp = I915_READ(fdi_rx_reg);
2203 temp &= ~FDI_SEL_PCDCLK;
2204 I915_WRITE(fdi_rx_reg, temp);
2205 I915_READ(fdi_rx_reg);
2206
2207 /* Disable CPU FDI TX PLL */
2208 temp = I915_READ(fdi_tx_reg);
2209 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2210 I915_READ(fdi_tx_reg);
2211 udelay(100);
2212
2213 temp = I915_READ(fdi_rx_reg);
2214 temp &= ~FDI_RX_PLL_ENABLE;
2215 I915_WRITE(fdi_rx_reg, temp);
2216 I915_READ(fdi_rx_reg);
2217
2218 /* Wait for the clocks to turn off. */
2219 udelay(100);
2220 break;
2221 }
2222 }
2223
2224 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2225 {
2226 struct intel_overlay *overlay;
2227 int ret;
2228
2229 if (!enable && intel_crtc->overlay) {
2230 overlay = intel_crtc->overlay;
2231 mutex_lock(&overlay->dev->struct_mutex);
2232 for (;;) {
2233 ret = intel_overlay_switch_off(overlay);
2234 if (ret == 0)
2235 break;
2236
2237 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2238 if (ret != 0) {
2239 /* overlay doesn't react anymore. Usually
2240 * results in a black screen and an unkillable
2241 * X server. */
2242 BUG();
2243 overlay->hw_wedged = HW_WEDGED;
2244 break;
2245 }
2246 }
2247 mutex_unlock(&overlay->dev->struct_mutex);
2248 }
2249 /* Let userspace switch the overlay on again. In most cases userspace
2250 * has to recompute where to put it anyway. */
2251
2252 return;
2253 }
2254
2255 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2256 {
2257 struct drm_device *dev = crtc->dev;
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260 int pipe = intel_crtc->pipe;
2261 int plane = intel_crtc->plane;
2262 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2263 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2264 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2265 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2266 u32 temp;
2267
2268 /* XXX: When our outputs are all unaware of DPMS modes other than off
2269 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2270 */
2271 switch (mode) {
2272 case DRM_MODE_DPMS_ON:
2273 case DRM_MODE_DPMS_STANDBY:
2274 case DRM_MODE_DPMS_SUSPEND:
2275 /* Enable the DPLL */
2276 temp = I915_READ(dpll_reg);
2277 if ((temp & DPLL_VCO_ENABLE) == 0) {
2278 I915_WRITE(dpll_reg, temp);
2279 I915_READ(dpll_reg);
2280 /* Wait for the clocks to stabilize. */
2281 udelay(150);
2282 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2283 I915_READ(dpll_reg);
2284 /* Wait for the clocks to stabilize. */
2285 udelay(150);
2286 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2287 I915_READ(dpll_reg);
2288 /* Wait for the clocks to stabilize. */
2289 udelay(150);
2290 }
2291
2292 /* Enable the pipe */
2293 temp = I915_READ(pipeconf_reg);
2294 if ((temp & PIPEACONF_ENABLE) == 0)
2295 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2296
2297 /* Enable the plane */
2298 temp = I915_READ(dspcntr_reg);
2299 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2300 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2301 /* Flush the plane changes */
2302 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2303 }
2304
2305 intel_crtc_load_lut(crtc);
2306
2307 if ((IS_I965G(dev) || plane == 0))
2308 intel_update_fbc(crtc, &crtc->mode);
2309
2310 /* Give the overlay scaler a chance to enable if it's on this pipe */
2311 intel_crtc_dpms_overlay(intel_crtc, true);
2312 break;
2313 case DRM_MODE_DPMS_OFF:
2314 /* Give the overlay scaler a chance to disable if it's on this pipe */
2315 intel_crtc_dpms_overlay(intel_crtc, false);
2316 drm_vblank_off(dev, pipe);
2317
2318 if (dev_priv->cfb_plane == plane &&
2319 dev_priv->display.disable_fbc)
2320 dev_priv->display.disable_fbc(dev);
2321
2322 /* Disable display plane */
2323 temp = I915_READ(dspcntr_reg);
2324 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2325 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2326 /* Flush the plane changes */
2327 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2328 I915_READ(dspbase_reg);
2329 }
2330
2331 if (!IS_I9XX(dev)) {
2332 /* Wait for vblank for the disable to take effect */
2333 intel_wait_for_vblank_off(dev, pipe);
2334 }
2335
2336 /* Don't disable pipe A or pipe A PLLs if needed */
2337 if (pipeconf_reg == PIPEACONF &&
2338 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2339 goto skip_pipe_off;
2340
2341 /* Next, disable display pipes */
2342 temp = I915_READ(pipeconf_reg);
2343 if ((temp & PIPEACONF_ENABLE) != 0) {
2344 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2345 I915_READ(pipeconf_reg);
2346 }
2347
2348 /* Wait for vblank for the disable to take effect. */
2349 intel_wait_for_vblank_off(dev, pipe);
2350
2351 temp = I915_READ(dpll_reg);
2352 if ((temp & DPLL_VCO_ENABLE) != 0) {
2353 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2354 I915_READ(dpll_reg);
2355 }
2356 skip_pipe_off:
2357 /* Wait for the clocks to turn off. */
2358 udelay(150);
2359 break;
2360 }
2361 }
2362
2363 /**
2364 * Sets the power management mode of the pipe and plane.
2365 */
2366 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2367 {
2368 struct drm_device *dev = crtc->dev;
2369 struct drm_i915_private *dev_priv = dev->dev_private;
2370 struct drm_i915_master_private *master_priv;
2371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2372 int pipe = intel_crtc->pipe;
2373 bool enabled;
2374
2375 if (intel_crtc->dpms_mode == mode)
2376 return;
2377
2378 intel_crtc->dpms_mode = mode;
2379 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2380
2381 /* When switching on the display, ensure that SR is disabled
2382 * with multiple pipes prior to enabling to new pipe.
2383 *
2384 * When switching off the display, make sure the cursor is
2385 * properly hidden prior to disabling the pipe.
2386 */
2387 if (mode == DRM_MODE_DPMS_ON)
2388 intel_update_watermarks(dev);
2389 else
2390 intel_crtc_update_cursor(crtc);
2391
2392 dev_priv->display.dpms(crtc, mode);
2393
2394 if (mode == DRM_MODE_DPMS_ON)
2395 intel_crtc_update_cursor(crtc);
2396 else
2397 intel_update_watermarks(dev);
2398
2399 if (!dev->primary->master)
2400 return;
2401
2402 master_priv = dev->primary->master->driver_priv;
2403 if (!master_priv->sarea_priv)
2404 return;
2405
2406 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2407
2408 switch (pipe) {
2409 case 0:
2410 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2411 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2412 break;
2413 case 1:
2414 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2415 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2416 break;
2417 default:
2418 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2419 break;
2420 }
2421 }
2422
2423 static void intel_crtc_prepare (struct drm_crtc *crtc)
2424 {
2425 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2426 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2427 }
2428
2429 static void intel_crtc_commit (struct drm_crtc *crtc)
2430 {
2431 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2432 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2433 }
2434
2435 void intel_encoder_prepare (struct drm_encoder *encoder)
2436 {
2437 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2438 /* lvds has its own version of prepare see intel_lvds_prepare */
2439 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2440 }
2441
2442 void intel_encoder_commit (struct drm_encoder *encoder)
2443 {
2444 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2445 /* lvds has its own version of commit see intel_lvds_commit */
2446 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2447 }
2448
2449 void intel_encoder_destroy(struct drm_encoder *encoder)
2450 {
2451 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2452
2453 if (intel_encoder->ddc_bus)
2454 intel_i2c_destroy(intel_encoder->ddc_bus);
2455
2456 if (intel_encoder->i2c_bus)
2457 intel_i2c_destroy(intel_encoder->i2c_bus);
2458
2459 drm_encoder_cleanup(encoder);
2460 kfree(intel_encoder);
2461 }
2462
2463 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2464 struct drm_display_mode *mode,
2465 struct drm_display_mode *adjusted_mode)
2466 {
2467 struct drm_device *dev = crtc->dev;
2468 if (HAS_PCH_SPLIT(dev)) {
2469 /* FDI link clock is fixed at 2.7G */
2470 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2471 return false;
2472 }
2473 return true;
2474 }
2475
2476 static int i945_get_display_clock_speed(struct drm_device *dev)
2477 {
2478 return 400000;
2479 }
2480
2481 static int i915_get_display_clock_speed(struct drm_device *dev)
2482 {
2483 return 333000;
2484 }
2485
2486 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2487 {
2488 return 200000;
2489 }
2490
2491 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2492 {
2493 u16 gcfgc = 0;
2494
2495 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2496
2497 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2498 return 133000;
2499 else {
2500 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2501 case GC_DISPLAY_CLOCK_333_MHZ:
2502 return 333000;
2503 default:
2504 case GC_DISPLAY_CLOCK_190_200_MHZ:
2505 return 190000;
2506 }
2507 }
2508 }
2509
2510 static int i865_get_display_clock_speed(struct drm_device *dev)
2511 {
2512 return 266000;
2513 }
2514
2515 static int i855_get_display_clock_speed(struct drm_device *dev)
2516 {
2517 u16 hpllcc = 0;
2518 /* Assume that the hardware is in the high speed state. This
2519 * should be the default.
2520 */
2521 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2522 case GC_CLOCK_133_200:
2523 case GC_CLOCK_100_200:
2524 return 200000;
2525 case GC_CLOCK_166_250:
2526 return 250000;
2527 case GC_CLOCK_100_133:
2528 return 133000;
2529 }
2530
2531 /* Shouldn't happen */
2532 return 0;
2533 }
2534
2535 static int i830_get_display_clock_speed(struct drm_device *dev)
2536 {
2537 return 133000;
2538 }
2539
2540 /**
2541 * Return the pipe currently connected to the panel fitter,
2542 * or -1 if the panel fitter is not present or not in use
2543 */
2544 int intel_panel_fitter_pipe (struct drm_device *dev)
2545 {
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 u32 pfit_control;
2548
2549 /* i830 doesn't have a panel fitter */
2550 if (IS_I830(dev))
2551 return -1;
2552
2553 pfit_control = I915_READ(PFIT_CONTROL);
2554
2555 /* See if the panel fitter is in use */
2556 if ((pfit_control & PFIT_ENABLE) == 0)
2557 return -1;
2558
2559 /* 965 can place panel fitter on either pipe */
2560 if (IS_I965G(dev))
2561 return (pfit_control >> 29) & 0x3;
2562
2563 /* older chips can only use pipe 1 */
2564 return 1;
2565 }
2566
2567 struct fdi_m_n {
2568 u32 tu;
2569 u32 gmch_m;
2570 u32 gmch_n;
2571 u32 link_m;
2572 u32 link_n;
2573 };
2574
2575 static void
2576 fdi_reduce_ratio(u32 *num, u32 *den)
2577 {
2578 while (*num > 0xffffff || *den > 0xffffff) {
2579 *num >>= 1;
2580 *den >>= 1;
2581 }
2582 }
2583
2584 #define DATA_N 0x800000
2585 #define LINK_N 0x80000
2586
2587 static void
2588 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2589 int link_clock, struct fdi_m_n *m_n)
2590 {
2591 u64 temp;
2592
2593 m_n->tu = 64; /* default size */
2594
2595 temp = (u64) DATA_N * pixel_clock;
2596 temp = div_u64(temp, link_clock);
2597 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2598 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2599 m_n->gmch_n = DATA_N;
2600 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2601
2602 temp = (u64) LINK_N * pixel_clock;
2603 m_n->link_m = div_u64(temp, link_clock);
2604 m_n->link_n = LINK_N;
2605 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2606 }
2607
2608
2609 struct intel_watermark_params {
2610 unsigned long fifo_size;
2611 unsigned long max_wm;
2612 unsigned long default_wm;
2613 unsigned long guard_size;
2614 unsigned long cacheline_size;
2615 };
2616
2617 /* Pineview has different values for various configs */
2618 static struct intel_watermark_params pineview_display_wm = {
2619 PINEVIEW_DISPLAY_FIFO,
2620 PINEVIEW_MAX_WM,
2621 PINEVIEW_DFT_WM,
2622 PINEVIEW_GUARD_WM,
2623 PINEVIEW_FIFO_LINE_SIZE
2624 };
2625 static struct intel_watermark_params pineview_display_hplloff_wm = {
2626 PINEVIEW_DISPLAY_FIFO,
2627 PINEVIEW_MAX_WM,
2628 PINEVIEW_DFT_HPLLOFF_WM,
2629 PINEVIEW_GUARD_WM,
2630 PINEVIEW_FIFO_LINE_SIZE
2631 };
2632 static struct intel_watermark_params pineview_cursor_wm = {
2633 PINEVIEW_CURSOR_FIFO,
2634 PINEVIEW_CURSOR_MAX_WM,
2635 PINEVIEW_CURSOR_DFT_WM,
2636 PINEVIEW_CURSOR_GUARD_WM,
2637 PINEVIEW_FIFO_LINE_SIZE,
2638 };
2639 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2640 PINEVIEW_CURSOR_FIFO,
2641 PINEVIEW_CURSOR_MAX_WM,
2642 PINEVIEW_CURSOR_DFT_WM,
2643 PINEVIEW_CURSOR_GUARD_WM,
2644 PINEVIEW_FIFO_LINE_SIZE
2645 };
2646 static struct intel_watermark_params g4x_wm_info = {
2647 G4X_FIFO_SIZE,
2648 G4X_MAX_WM,
2649 G4X_MAX_WM,
2650 2,
2651 G4X_FIFO_LINE_SIZE,
2652 };
2653 static struct intel_watermark_params g4x_cursor_wm_info = {
2654 I965_CURSOR_FIFO,
2655 I965_CURSOR_MAX_WM,
2656 I965_CURSOR_DFT_WM,
2657 2,
2658 G4X_FIFO_LINE_SIZE,
2659 };
2660 static struct intel_watermark_params i965_cursor_wm_info = {
2661 I965_CURSOR_FIFO,
2662 I965_CURSOR_MAX_WM,
2663 I965_CURSOR_DFT_WM,
2664 2,
2665 I915_FIFO_LINE_SIZE,
2666 };
2667 static struct intel_watermark_params i945_wm_info = {
2668 I945_FIFO_SIZE,
2669 I915_MAX_WM,
2670 1,
2671 2,
2672 I915_FIFO_LINE_SIZE
2673 };
2674 static struct intel_watermark_params i915_wm_info = {
2675 I915_FIFO_SIZE,
2676 I915_MAX_WM,
2677 1,
2678 2,
2679 I915_FIFO_LINE_SIZE
2680 };
2681 static struct intel_watermark_params i855_wm_info = {
2682 I855GM_FIFO_SIZE,
2683 I915_MAX_WM,
2684 1,
2685 2,
2686 I830_FIFO_LINE_SIZE
2687 };
2688 static struct intel_watermark_params i830_wm_info = {
2689 I830_FIFO_SIZE,
2690 I915_MAX_WM,
2691 1,
2692 2,
2693 I830_FIFO_LINE_SIZE
2694 };
2695
2696 static struct intel_watermark_params ironlake_display_wm_info = {
2697 ILK_DISPLAY_FIFO,
2698 ILK_DISPLAY_MAXWM,
2699 ILK_DISPLAY_DFTWM,
2700 2,
2701 ILK_FIFO_LINE_SIZE
2702 };
2703
2704 static struct intel_watermark_params ironlake_cursor_wm_info = {
2705 ILK_CURSOR_FIFO,
2706 ILK_CURSOR_MAXWM,
2707 ILK_CURSOR_DFTWM,
2708 2,
2709 ILK_FIFO_LINE_SIZE
2710 };
2711
2712 static struct intel_watermark_params ironlake_display_srwm_info = {
2713 ILK_DISPLAY_SR_FIFO,
2714 ILK_DISPLAY_MAX_SRWM,
2715 ILK_DISPLAY_DFT_SRWM,
2716 2,
2717 ILK_FIFO_LINE_SIZE
2718 };
2719
2720 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2721 ILK_CURSOR_SR_FIFO,
2722 ILK_CURSOR_MAX_SRWM,
2723 ILK_CURSOR_DFT_SRWM,
2724 2,
2725 ILK_FIFO_LINE_SIZE
2726 };
2727
2728 /**
2729 * intel_calculate_wm - calculate watermark level
2730 * @clock_in_khz: pixel clock
2731 * @wm: chip FIFO params
2732 * @pixel_size: display pixel size
2733 * @latency_ns: memory latency for the platform
2734 *
2735 * Calculate the watermark level (the level at which the display plane will
2736 * start fetching from memory again). Each chip has a different display
2737 * FIFO size and allocation, so the caller needs to figure that out and pass
2738 * in the correct intel_watermark_params structure.
2739 *
2740 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2741 * on the pixel size. When it reaches the watermark level, it'll start
2742 * fetching FIFO line sized based chunks from memory until the FIFO fills
2743 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2744 * will occur, and a display engine hang could result.
2745 */
2746 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2747 struct intel_watermark_params *wm,
2748 int pixel_size,
2749 unsigned long latency_ns)
2750 {
2751 long entries_required, wm_size;
2752
2753 /*
2754 * Note: we need to make sure we don't overflow for various clock &
2755 * latency values.
2756 * clocks go from a few thousand to several hundred thousand.
2757 * latency is usually a few thousand
2758 */
2759 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2760 1000;
2761 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2762
2763 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2764
2765 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2766
2767 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2768
2769 /* Don't promote wm_size to unsigned... */
2770 if (wm_size > (long)wm->max_wm)
2771 wm_size = wm->max_wm;
2772 if (wm_size <= 0)
2773 wm_size = wm->default_wm;
2774 return wm_size;
2775 }
2776
2777 struct cxsr_latency {
2778 int is_desktop;
2779 int is_ddr3;
2780 unsigned long fsb_freq;
2781 unsigned long mem_freq;
2782 unsigned long display_sr;
2783 unsigned long display_hpll_disable;
2784 unsigned long cursor_sr;
2785 unsigned long cursor_hpll_disable;
2786 };
2787
2788 static const struct cxsr_latency cxsr_latency_table[] = {
2789 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2790 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2791 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2792 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2793 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2794
2795 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2796 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2797 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2798 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2799 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2800
2801 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2802 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2803 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2804 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2805 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2806
2807 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2808 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2809 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2810 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2811 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2812
2813 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2814 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2815 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2816 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2817 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2818
2819 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2820 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2821 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2822 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2823 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2824 };
2825
2826 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2827 int is_ddr3,
2828 int fsb,
2829 int mem)
2830 {
2831 const struct cxsr_latency *latency;
2832 int i;
2833
2834 if (fsb == 0 || mem == 0)
2835 return NULL;
2836
2837 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2838 latency = &cxsr_latency_table[i];
2839 if (is_desktop == latency->is_desktop &&
2840 is_ddr3 == latency->is_ddr3 &&
2841 fsb == latency->fsb_freq && mem == latency->mem_freq)
2842 return latency;
2843 }
2844
2845 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2846
2847 return NULL;
2848 }
2849
2850 static void pineview_disable_cxsr(struct drm_device *dev)
2851 {
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853
2854 /* deactivate cxsr */
2855 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2856 }
2857
2858 /*
2859 * Latency for FIFO fetches is dependent on several factors:
2860 * - memory configuration (speed, channels)
2861 * - chipset
2862 * - current MCH state
2863 * It can be fairly high in some situations, so here we assume a fairly
2864 * pessimal value. It's a tradeoff between extra memory fetches (if we
2865 * set this value too high, the FIFO will fetch frequently to stay full)
2866 * and power consumption (set it too low to save power and we might see
2867 * FIFO underruns and display "flicker").
2868 *
2869 * A value of 5us seems to be a good balance; safe for very low end
2870 * platforms but not overly aggressive on lower latency configs.
2871 */
2872 static const int latency_ns = 5000;
2873
2874 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2875 {
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 uint32_t dsparb = I915_READ(DSPARB);
2878 int size;
2879
2880 size = dsparb & 0x7f;
2881 if (plane)
2882 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2883
2884 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2885 plane ? "B" : "A", size);
2886
2887 return size;
2888 }
2889
2890 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2891 {
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 uint32_t dsparb = I915_READ(DSPARB);
2894 int size;
2895
2896 size = dsparb & 0x1ff;
2897 if (plane)
2898 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2899 size >>= 1; /* Convert to cachelines */
2900
2901 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2902 plane ? "B" : "A", size);
2903
2904 return size;
2905 }
2906
2907 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2908 {
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 uint32_t dsparb = I915_READ(DSPARB);
2911 int size;
2912
2913 size = dsparb & 0x7f;
2914 size >>= 2; /* Convert to cachelines */
2915
2916 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2917 plane ? "B" : "A",
2918 size);
2919
2920 return size;
2921 }
2922
2923 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2924 {
2925 struct drm_i915_private *dev_priv = dev->dev_private;
2926 uint32_t dsparb = I915_READ(DSPARB);
2927 int size;
2928
2929 size = dsparb & 0x7f;
2930 size >>= 1; /* Convert to cachelines */
2931
2932 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2933 plane ? "B" : "A", size);
2934
2935 return size;
2936 }
2937
2938 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2939 int planeb_clock, int sr_hdisplay, int unused,
2940 int pixel_size)
2941 {
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 const struct cxsr_latency *latency;
2944 u32 reg;
2945 unsigned long wm;
2946 int sr_clock;
2947
2948 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2949 dev_priv->fsb_freq, dev_priv->mem_freq);
2950 if (!latency) {
2951 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2952 pineview_disable_cxsr(dev);
2953 return;
2954 }
2955
2956 if (!planea_clock || !planeb_clock) {
2957 sr_clock = planea_clock ? planea_clock : planeb_clock;
2958
2959 /* Display SR */
2960 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2961 pixel_size, latency->display_sr);
2962 reg = I915_READ(DSPFW1);
2963 reg &= ~DSPFW_SR_MASK;
2964 reg |= wm << DSPFW_SR_SHIFT;
2965 I915_WRITE(DSPFW1, reg);
2966 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2967
2968 /* cursor SR */
2969 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2970 pixel_size, latency->cursor_sr);
2971 reg = I915_READ(DSPFW3);
2972 reg &= ~DSPFW_CURSOR_SR_MASK;
2973 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2974 I915_WRITE(DSPFW3, reg);
2975
2976 /* Display HPLL off SR */
2977 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2978 pixel_size, latency->display_hpll_disable);
2979 reg = I915_READ(DSPFW3);
2980 reg &= ~DSPFW_HPLL_SR_MASK;
2981 reg |= wm & DSPFW_HPLL_SR_MASK;
2982 I915_WRITE(DSPFW3, reg);
2983
2984 /* cursor HPLL off SR */
2985 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2986 pixel_size, latency->cursor_hpll_disable);
2987 reg = I915_READ(DSPFW3);
2988 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2989 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2990 I915_WRITE(DSPFW3, reg);
2991 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2992
2993 /* activate cxsr */
2994 I915_WRITE(DSPFW3,
2995 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
2996 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2997 } else {
2998 pineview_disable_cxsr(dev);
2999 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3000 }
3001 }
3002
3003 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3004 int planeb_clock, int sr_hdisplay, int sr_htotal,
3005 int pixel_size)
3006 {
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 int total_size, cacheline_size;
3009 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3010 struct intel_watermark_params planea_params, planeb_params;
3011 unsigned long line_time_us;
3012 int sr_clock, sr_entries = 0, entries_required;
3013
3014 /* Create copies of the base settings for each pipe */
3015 planea_params = planeb_params = g4x_wm_info;
3016
3017 /* Grab a couple of global values before we overwrite them */
3018 total_size = planea_params.fifo_size;
3019 cacheline_size = planea_params.cacheline_size;
3020
3021 /*
3022 * Note: we need to make sure we don't overflow for various clock &
3023 * latency values.
3024 * clocks go from a few thousand to several hundred thousand.
3025 * latency is usually a few thousand
3026 */
3027 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3028 1000;
3029 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3030 planea_wm = entries_required + planea_params.guard_size;
3031
3032 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3033 1000;
3034 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3035 planeb_wm = entries_required + planeb_params.guard_size;
3036
3037 cursora_wm = cursorb_wm = 16;
3038 cursor_sr = 32;
3039
3040 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3041
3042 /* Calc sr entries for one plane configs */
3043 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3044 /* self-refresh has much higher latency */
3045 static const int sr_latency_ns = 12000;
3046
3047 sr_clock = planea_clock ? planea_clock : planeb_clock;
3048 line_time_us = ((sr_htotal * 1000) / sr_clock);
3049
3050 /* Use ns/us then divide to preserve precision */
3051 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3052 pixel_size * sr_hdisplay;
3053 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3054
3055 entries_required = (((sr_latency_ns / line_time_us) +
3056 1000) / 1000) * pixel_size * 64;
3057 entries_required = DIV_ROUND_UP(entries_required,
3058 g4x_cursor_wm_info.cacheline_size);
3059 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3060
3061 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3062 cursor_sr = g4x_cursor_wm_info.max_wm;
3063 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3064 "cursor %d\n", sr_entries, cursor_sr);
3065
3066 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3067 } else {
3068 /* Turn off self refresh if both pipes are enabled */
3069 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3070 & ~FW_BLC_SELF_EN);
3071 }
3072
3073 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3074 planea_wm, planeb_wm, sr_entries);
3075
3076 planea_wm &= 0x3f;
3077 planeb_wm &= 0x3f;
3078
3079 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3080 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3081 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3082 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3083 (cursora_wm << DSPFW_CURSORA_SHIFT));
3084 /* HPLL off in SR has some issues on G4x... disable it */
3085 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3086 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3087 }
3088
3089 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3090 int planeb_clock, int sr_hdisplay, int sr_htotal,
3091 int pixel_size)
3092 {
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 unsigned long line_time_us;
3095 int sr_clock, sr_entries, srwm = 1;
3096 int cursor_sr = 16;
3097
3098 /* Calc sr entries for one plane configs */
3099 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3100 /* self-refresh has much higher latency */
3101 static const int sr_latency_ns = 12000;
3102
3103 sr_clock = planea_clock ? planea_clock : planeb_clock;
3104 line_time_us = ((sr_htotal * 1000) / sr_clock);
3105
3106 /* Use ns/us then divide to preserve precision */
3107 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3108 pixel_size * sr_hdisplay;
3109 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3110 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3111 srwm = I965_FIFO_SIZE - sr_entries;
3112 if (srwm < 0)
3113 srwm = 1;
3114 srwm &= 0x1ff;
3115
3116 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3117 pixel_size * 64;
3118 sr_entries = DIV_ROUND_UP(sr_entries,
3119 i965_cursor_wm_info.cacheline_size);
3120 cursor_sr = i965_cursor_wm_info.fifo_size -
3121 (sr_entries + i965_cursor_wm_info.guard_size);
3122
3123 if (cursor_sr > i965_cursor_wm_info.max_wm)
3124 cursor_sr = i965_cursor_wm_info.max_wm;
3125
3126 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3127 "cursor %d\n", srwm, cursor_sr);
3128
3129 if (IS_I965GM(dev))
3130 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3131 } else {
3132 /* Turn off self refresh if both pipes are enabled */
3133 if (IS_I965GM(dev))
3134 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3135 & ~FW_BLC_SELF_EN);
3136 }
3137
3138 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3139 srwm);
3140
3141 /* 965 has limitations... */
3142 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3143 (8 << 0));
3144 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3145 /* update cursor SR watermark */
3146 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3147 }
3148
3149 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3150 int planeb_clock, int sr_hdisplay, int sr_htotal,
3151 int pixel_size)
3152 {
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 uint32_t fwater_lo;
3155 uint32_t fwater_hi;
3156 int total_size, cacheline_size, cwm, srwm = 1;
3157 int planea_wm, planeb_wm;
3158 struct intel_watermark_params planea_params, planeb_params;
3159 unsigned long line_time_us;
3160 int sr_clock, sr_entries = 0;
3161
3162 /* Create copies of the base settings for each pipe */
3163 if (IS_I965GM(dev) || IS_I945GM(dev))
3164 planea_params = planeb_params = i945_wm_info;
3165 else if (IS_I9XX(dev))
3166 planea_params = planeb_params = i915_wm_info;
3167 else
3168 planea_params = planeb_params = i855_wm_info;
3169
3170 /* Grab a couple of global values before we overwrite them */
3171 total_size = planea_params.fifo_size;
3172 cacheline_size = planea_params.cacheline_size;
3173
3174 /* Update per-plane FIFO sizes */
3175 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3176 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3177
3178 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3179 pixel_size, latency_ns);
3180 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3181 pixel_size, latency_ns);
3182 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3183
3184 /*
3185 * Overlay gets an aggressive default since video jitter is bad.
3186 */
3187 cwm = 2;
3188
3189 /* Calc sr entries for one plane configs */
3190 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3191 (!planea_clock || !planeb_clock)) {
3192 /* self-refresh has much higher latency */
3193 static const int sr_latency_ns = 6000;
3194
3195 sr_clock = planea_clock ? planea_clock : planeb_clock;
3196 line_time_us = ((sr_htotal * 1000) / sr_clock);
3197
3198 /* Use ns/us then divide to preserve precision */
3199 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3200 pixel_size * sr_hdisplay;
3201 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3202 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3203 srwm = total_size - sr_entries;
3204 if (srwm < 0)
3205 srwm = 1;
3206
3207 if (IS_I945G(dev) || IS_I945GM(dev))
3208 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3209 else if (IS_I915GM(dev)) {
3210 /* 915M has a smaller SRWM field */
3211 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3212 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3213 }
3214 } else {
3215 /* Turn off self refresh if both pipes are enabled */
3216 if (IS_I945G(dev) || IS_I945GM(dev)) {
3217 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3218 & ~FW_BLC_SELF_EN);
3219 } else if (IS_I915GM(dev)) {
3220 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3221 }
3222 }
3223
3224 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3225 planea_wm, planeb_wm, cwm, srwm);
3226
3227 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3228 fwater_hi = (cwm & 0x1f);
3229
3230 /* Set request length to 8 cachelines per fetch */
3231 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3232 fwater_hi = fwater_hi | (1 << 8);
3233
3234 I915_WRITE(FW_BLC, fwater_lo);
3235 I915_WRITE(FW_BLC2, fwater_hi);
3236 }
3237
3238 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3239 int unused2, int unused3, int pixel_size)
3240 {
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3243 int planea_wm;
3244
3245 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3246
3247 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3248 pixel_size, latency_ns);
3249 fwater_lo |= (3<<8) | planea_wm;
3250
3251 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3252
3253 I915_WRITE(FW_BLC, fwater_lo);
3254 }
3255
3256 #define ILK_LP0_PLANE_LATENCY 700
3257 #define ILK_LP0_CURSOR_LATENCY 1300
3258
3259 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3260 int planeb_clock, int sr_hdisplay, int sr_htotal,
3261 int pixel_size)
3262 {
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3265 int sr_wm, cursor_wm;
3266 unsigned long line_time_us;
3267 int sr_clock, entries_required;
3268 u32 reg_value;
3269 int line_count;
3270 int planea_htotal = 0, planeb_htotal = 0;
3271 struct drm_crtc *crtc;
3272
3273 /* Need htotal for all active display plane */
3274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3276 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3277 if (intel_crtc->plane == 0)
3278 planea_htotal = crtc->mode.htotal;
3279 else
3280 planeb_htotal = crtc->mode.htotal;
3281 }
3282 }
3283
3284 /* Calculate and update the watermark for plane A */
3285 if (planea_clock) {
3286 entries_required = ((planea_clock / 1000) * pixel_size *
3287 ILK_LP0_PLANE_LATENCY) / 1000;
3288 entries_required = DIV_ROUND_UP(entries_required,
3289 ironlake_display_wm_info.cacheline_size);
3290 planea_wm = entries_required +
3291 ironlake_display_wm_info.guard_size;
3292
3293 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3294 planea_wm = ironlake_display_wm_info.max_wm;
3295
3296 /* Use the large buffer method to calculate cursor watermark */
3297 line_time_us = (planea_htotal * 1000) / planea_clock;
3298
3299 /* Use ns/us then divide to preserve precision */
3300 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3301
3302 /* calculate the cursor watermark for cursor A */
3303 entries_required = line_count * 64 * pixel_size;
3304 entries_required = DIV_ROUND_UP(entries_required,
3305 ironlake_cursor_wm_info.cacheline_size);
3306 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3307 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3308 cursora_wm = ironlake_cursor_wm_info.max_wm;
3309
3310 reg_value = I915_READ(WM0_PIPEA_ILK);
3311 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3312 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3313 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3314 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3315 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3316 "cursor: %d\n", planea_wm, cursora_wm);
3317 }
3318 /* Calculate and update the watermark for plane B */
3319 if (planeb_clock) {
3320 entries_required = ((planeb_clock / 1000) * pixel_size *
3321 ILK_LP0_PLANE_LATENCY) / 1000;
3322 entries_required = DIV_ROUND_UP(entries_required,
3323 ironlake_display_wm_info.cacheline_size);
3324 planeb_wm = entries_required +
3325 ironlake_display_wm_info.guard_size;
3326
3327 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3328 planeb_wm = ironlake_display_wm_info.max_wm;
3329
3330 /* Use the large buffer method to calculate cursor watermark */
3331 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3332
3333 /* Use ns/us then divide to preserve precision */
3334 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3335
3336 /* calculate the cursor watermark for cursor B */
3337 entries_required = line_count * 64 * pixel_size;
3338 entries_required = DIV_ROUND_UP(entries_required,
3339 ironlake_cursor_wm_info.cacheline_size);
3340 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3341 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3342 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3343
3344 reg_value = I915_READ(WM0_PIPEB_ILK);
3345 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3346 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3347 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3348 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3349 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3350 "cursor: %d\n", planeb_wm, cursorb_wm);
3351 }
3352
3353 /*
3354 * Calculate and update the self-refresh watermark only when one
3355 * display plane is used.
3356 */
3357 if (!planea_clock || !planeb_clock) {
3358
3359 /* Read the self-refresh latency. The unit is 0.5us */
3360 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3361
3362 sr_clock = planea_clock ? planea_clock : planeb_clock;
3363 line_time_us = ((sr_htotal * 1000) / sr_clock);
3364
3365 /* Use ns/us then divide to preserve precision */
3366 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3367 / 1000;
3368
3369 /* calculate the self-refresh watermark for display plane */
3370 entries_required = line_count * sr_hdisplay * pixel_size;
3371 entries_required = DIV_ROUND_UP(entries_required,
3372 ironlake_display_srwm_info.cacheline_size);
3373 sr_wm = entries_required +
3374 ironlake_display_srwm_info.guard_size;
3375
3376 /* calculate the self-refresh watermark for display cursor */
3377 entries_required = line_count * pixel_size * 64;
3378 entries_required = DIV_ROUND_UP(entries_required,
3379 ironlake_cursor_srwm_info.cacheline_size);
3380 cursor_wm = entries_required +
3381 ironlake_cursor_srwm_info.guard_size;
3382
3383 /* configure watermark and enable self-refresh */
3384 reg_value = I915_READ(WM1_LP_ILK);
3385 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3386 WM1_LP_CURSOR_MASK);
3387 reg_value |= WM1_LP_SR_EN |
3388 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3389 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3390
3391 I915_WRITE(WM1_LP_ILK, reg_value);
3392 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3393 "cursor %d\n", sr_wm, cursor_wm);
3394
3395 } else {
3396 /* Turn off self refresh if both pipes are enabled */
3397 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3398 }
3399 }
3400 /**
3401 * intel_update_watermarks - update FIFO watermark values based on current modes
3402 *
3403 * Calculate watermark values for the various WM regs based on current mode
3404 * and plane configuration.
3405 *
3406 * There are several cases to deal with here:
3407 * - normal (i.e. non-self-refresh)
3408 * - self-refresh (SR) mode
3409 * - lines are large relative to FIFO size (buffer can hold up to 2)
3410 * - lines are small relative to FIFO size (buffer can hold more than 2
3411 * lines), so need to account for TLB latency
3412 *
3413 * The normal calculation is:
3414 * watermark = dotclock * bytes per pixel * latency
3415 * where latency is platform & configuration dependent (we assume pessimal
3416 * values here).
3417 *
3418 * The SR calculation is:
3419 * watermark = (trunc(latency/line time)+1) * surface width *
3420 * bytes per pixel
3421 * where
3422 * line time = htotal / dotclock
3423 * surface width = hdisplay for normal plane and 64 for cursor
3424 * and latency is assumed to be high, as above.
3425 *
3426 * The final value programmed to the register should always be rounded up,
3427 * and include an extra 2 entries to account for clock crossings.
3428 *
3429 * We don't use the sprite, so we can ignore that. And on Crestline we have
3430 * to set the non-SR watermarks to 8.
3431 */
3432 static void intel_update_watermarks(struct drm_device *dev)
3433 {
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435 struct drm_crtc *crtc;
3436 int sr_hdisplay = 0;
3437 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3438 int enabled = 0, pixel_size = 0;
3439 int sr_htotal = 0;
3440
3441 if (!dev_priv->display.update_wm)
3442 return;
3443
3444 /* Get the clock config from both planes */
3445 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3448 enabled++;
3449 if (intel_crtc->plane == 0) {
3450 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3451 intel_crtc->pipe, crtc->mode.clock);
3452 planea_clock = crtc->mode.clock;
3453 } else {
3454 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3455 intel_crtc->pipe, crtc->mode.clock);
3456 planeb_clock = crtc->mode.clock;
3457 }
3458 sr_hdisplay = crtc->mode.hdisplay;
3459 sr_clock = crtc->mode.clock;
3460 sr_htotal = crtc->mode.htotal;
3461 if (crtc->fb)
3462 pixel_size = crtc->fb->bits_per_pixel / 8;
3463 else
3464 pixel_size = 4; /* by default */
3465 }
3466 }
3467
3468 if (enabled <= 0)
3469 return;
3470
3471 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3472 sr_hdisplay, sr_htotal, pixel_size);
3473 }
3474
3475 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3476 struct drm_display_mode *mode,
3477 struct drm_display_mode *adjusted_mode,
3478 int x, int y,
3479 struct drm_framebuffer *old_fb)
3480 {
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484 int pipe = intel_crtc->pipe;
3485 int plane = intel_crtc->plane;
3486 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3487 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3488 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3489 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3490 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3491 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3492 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3493 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3494 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3495 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3496 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3497 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3498 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3499 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3500 int refclk, num_connectors = 0;
3501 intel_clock_t clock, reduced_clock;
3502 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3503 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3504 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3505 struct intel_encoder *has_edp_encoder = NULL;
3506 struct drm_mode_config *mode_config = &dev->mode_config;
3507 struct drm_encoder *encoder;
3508 const intel_limit_t *limit;
3509 int ret;
3510 struct fdi_m_n m_n = {0};
3511 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3512 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3513 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3514 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3515 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3516 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3517 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3518 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3519 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3520 int lvds_reg = LVDS;
3521 u32 temp;
3522 int target_clock;
3523
3524 drm_vblank_pre_modeset(dev, pipe);
3525
3526 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3527 struct intel_encoder *intel_encoder;
3528
3529 if (encoder->crtc != crtc)
3530 continue;
3531
3532 intel_encoder = enc_to_intel_encoder(encoder);
3533 switch (intel_encoder->type) {
3534 case INTEL_OUTPUT_LVDS:
3535 is_lvds = true;
3536 break;
3537 case INTEL_OUTPUT_SDVO:
3538 case INTEL_OUTPUT_HDMI:
3539 is_sdvo = true;
3540 if (intel_encoder->needs_tv_clock)
3541 is_tv = true;
3542 break;
3543 case INTEL_OUTPUT_DVO:
3544 is_dvo = true;
3545 break;
3546 case INTEL_OUTPUT_TVOUT:
3547 is_tv = true;
3548 break;
3549 case INTEL_OUTPUT_ANALOG:
3550 is_crt = true;
3551 break;
3552 case INTEL_OUTPUT_DISPLAYPORT:
3553 is_dp = true;
3554 break;
3555 case INTEL_OUTPUT_EDP:
3556 has_edp_encoder = intel_encoder;
3557 break;
3558 }
3559
3560 num_connectors++;
3561 }
3562
3563 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3564 refclk = dev_priv->lvds_ssc_freq * 1000;
3565 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3566 refclk / 1000);
3567 } else if (IS_I9XX(dev)) {
3568 refclk = 96000;
3569 if (HAS_PCH_SPLIT(dev))
3570 refclk = 120000; /* 120Mhz refclk */
3571 } else {
3572 refclk = 48000;
3573 }
3574
3575
3576 /*
3577 * Returns a set of divisors for the desired target clock with the given
3578 * refclk, or FALSE. The returned values represent the clock equation:
3579 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3580 */
3581 limit = intel_limit(crtc);
3582 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3583 if (!ok) {
3584 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3585 drm_vblank_post_modeset(dev, pipe);
3586 return -EINVAL;
3587 }
3588
3589 /* Ensure that the cursor is valid for the new mode before changing... */
3590 intel_crtc_update_cursor(crtc);
3591
3592 if (is_lvds && dev_priv->lvds_downclock_avail) {
3593 has_reduced_clock = limit->find_pll(limit, crtc,
3594 dev_priv->lvds_downclock,
3595 refclk,
3596 &reduced_clock);
3597 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3598 /*
3599 * If the different P is found, it means that we can't
3600 * switch the display clock by using the FP0/FP1.
3601 * In such case we will disable the LVDS downclock
3602 * feature.
3603 */
3604 DRM_DEBUG_KMS("Different P is found for "
3605 "LVDS clock/downclock\n");
3606 has_reduced_clock = 0;
3607 }
3608 }
3609 /* SDVO TV has fixed PLL values depend on its clock range,
3610 this mirrors vbios setting. */
3611 if (is_sdvo && is_tv) {
3612 if (adjusted_mode->clock >= 100000
3613 && adjusted_mode->clock < 140500) {
3614 clock.p1 = 2;
3615 clock.p2 = 10;
3616 clock.n = 3;
3617 clock.m1 = 16;
3618 clock.m2 = 8;
3619 } else if (adjusted_mode->clock >= 140500
3620 && adjusted_mode->clock <= 200000) {
3621 clock.p1 = 1;
3622 clock.p2 = 10;
3623 clock.n = 6;
3624 clock.m1 = 12;
3625 clock.m2 = 8;
3626 }
3627 }
3628
3629 /* FDI link */
3630 if (HAS_PCH_SPLIT(dev)) {
3631 int lane = 0, link_bw, bpp;
3632 /* eDP doesn't require FDI link, so just set DP M/N
3633 according to current link config */
3634 if (has_edp_encoder) {
3635 target_clock = mode->clock;
3636 intel_edp_link_config(has_edp_encoder,
3637 &lane, &link_bw);
3638 } else {
3639 /* DP over FDI requires target mode clock
3640 instead of link clock */
3641 if (is_dp)
3642 target_clock = mode->clock;
3643 else
3644 target_clock = adjusted_mode->clock;
3645 link_bw = 270000;
3646 }
3647
3648 /* determine panel color depth */
3649 temp = I915_READ(pipeconf_reg);
3650 temp &= ~PIPE_BPC_MASK;
3651 if (is_lvds) {
3652 int lvds_reg = I915_READ(PCH_LVDS);
3653 /* the BPC will be 6 if it is 18-bit LVDS panel */
3654 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3655 temp |= PIPE_8BPC;
3656 else
3657 temp |= PIPE_6BPC;
3658 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3659 switch (dev_priv->edp_bpp/3) {
3660 case 8:
3661 temp |= PIPE_8BPC;
3662 break;
3663 case 10:
3664 temp |= PIPE_10BPC;
3665 break;
3666 case 6:
3667 temp |= PIPE_6BPC;
3668 break;
3669 case 12:
3670 temp |= PIPE_12BPC;
3671 break;
3672 }
3673 } else
3674 temp |= PIPE_8BPC;
3675 I915_WRITE(pipeconf_reg, temp);
3676 I915_READ(pipeconf_reg);
3677
3678 switch (temp & PIPE_BPC_MASK) {
3679 case PIPE_8BPC:
3680 bpp = 24;
3681 break;
3682 case PIPE_10BPC:
3683 bpp = 30;
3684 break;
3685 case PIPE_6BPC:
3686 bpp = 18;
3687 break;
3688 case PIPE_12BPC:
3689 bpp = 36;
3690 break;
3691 default:
3692 DRM_ERROR("unknown pipe bpc value\n");
3693 bpp = 24;
3694 }
3695
3696 if (!lane) {
3697 /*
3698 * Account for spread spectrum to avoid
3699 * oversubscribing the link. Max center spread
3700 * is 2.5%; use 5% for safety's sake.
3701 */
3702 u32 bps = target_clock * bpp * 21 / 20;
3703 lane = bps / (link_bw * 8) + 1;
3704 }
3705
3706 intel_crtc->fdi_lanes = lane;
3707
3708 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3709 }
3710
3711 /* Ironlake: try to setup display ref clock before DPLL
3712 * enabling. This is only under driver's control after
3713 * PCH B stepping, previous chipset stepping should be
3714 * ignoring this setting.
3715 */
3716 if (HAS_PCH_SPLIT(dev)) {
3717 temp = I915_READ(PCH_DREF_CONTROL);
3718 /* Always enable nonspread source */
3719 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3720 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3721 I915_WRITE(PCH_DREF_CONTROL, temp);
3722 POSTING_READ(PCH_DREF_CONTROL);
3723
3724 temp &= ~DREF_SSC_SOURCE_MASK;
3725 temp |= DREF_SSC_SOURCE_ENABLE;
3726 I915_WRITE(PCH_DREF_CONTROL, temp);
3727 POSTING_READ(PCH_DREF_CONTROL);
3728
3729 udelay(200);
3730
3731 if (has_edp_encoder) {
3732 if (dev_priv->lvds_use_ssc) {
3733 temp |= DREF_SSC1_ENABLE;
3734 I915_WRITE(PCH_DREF_CONTROL, temp);
3735 POSTING_READ(PCH_DREF_CONTROL);
3736
3737 udelay(200);
3738
3739 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3740 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3741 I915_WRITE(PCH_DREF_CONTROL, temp);
3742 POSTING_READ(PCH_DREF_CONTROL);
3743 } else {
3744 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3745 I915_WRITE(PCH_DREF_CONTROL, temp);
3746 POSTING_READ(PCH_DREF_CONTROL);
3747 }
3748 }
3749 }
3750
3751 if (IS_PINEVIEW(dev)) {
3752 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3753 if (has_reduced_clock)
3754 fp2 = (1 << reduced_clock.n) << 16 |
3755 reduced_clock.m1 << 8 | reduced_clock.m2;
3756 } else {
3757 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3758 if (has_reduced_clock)
3759 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3760 reduced_clock.m2;
3761 }
3762
3763 if (!HAS_PCH_SPLIT(dev))
3764 dpll = DPLL_VGA_MODE_DIS;
3765
3766 if (IS_I9XX(dev)) {
3767 if (is_lvds)
3768 dpll |= DPLLB_MODE_LVDS;
3769 else
3770 dpll |= DPLLB_MODE_DAC_SERIAL;
3771 if (is_sdvo) {
3772 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3773 if (pixel_multiplier > 1) {
3774 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3775 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3776 else if (HAS_PCH_SPLIT(dev))
3777 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3778 }
3779 dpll |= DPLL_DVO_HIGH_SPEED;
3780 }
3781 if (is_dp)
3782 dpll |= DPLL_DVO_HIGH_SPEED;
3783
3784 /* compute bitmask from p1 value */
3785 if (IS_PINEVIEW(dev))
3786 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3787 else {
3788 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3789 /* also FPA1 */
3790 if (HAS_PCH_SPLIT(dev))
3791 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3792 if (IS_G4X(dev) && has_reduced_clock)
3793 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3794 }
3795 switch (clock.p2) {
3796 case 5:
3797 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3798 break;
3799 case 7:
3800 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3801 break;
3802 case 10:
3803 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3804 break;
3805 case 14:
3806 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3807 break;
3808 }
3809 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3810 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3811 } else {
3812 if (is_lvds) {
3813 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3814 } else {
3815 if (clock.p1 == 2)
3816 dpll |= PLL_P1_DIVIDE_BY_TWO;
3817 else
3818 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3819 if (clock.p2 == 4)
3820 dpll |= PLL_P2_DIVIDE_BY_4;
3821 }
3822 }
3823
3824 if (is_sdvo && is_tv)
3825 dpll |= PLL_REF_INPUT_TVCLKINBC;
3826 else if (is_tv)
3827 /* XXX: just matching BIOS for now */
3828 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3829 dpll |= 3;
3830 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3831 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3832 else
3833 dpll |= PLL_REF_INPUT_DREFCLK;
3834
3835 /* setup pipeconf */
3836 pipeconf = I915_READ(pipeconf_reg);
3837
3838 /* Set up the display plane register */
3839 dspcntr = DISPPLANE_GAMMA_ENABLE;
3840
3841 /* Ironlake's plane is forced to pipe, bit 24 is to
3842 enable color space conversion */
3843 if (!HAS_PCH_SPLIT(dev)) {
3844 if (pipe == 0)
3845 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3846 else
3847 dspcntr |= DISPPLANE_SEL_PIPE_B;
3848 }
3849
3850 if (pipe == 0 && !IS_I965G(dev)) {
3851 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3852 * core speed.
3853 *
3854 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3855 * pipe == 0 check?
3856 */
3857 if (mode->clock >
3858 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3859 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3860 else
3861 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3862 }
3863
3864 dspcntr |= DISPLAY_PLANE_ENABLE;
3865 pipeconf |= PIPEACONF_ENABLE;
3866 dpll |= DPLL_VCO_ENABLE;
3867
3868
3869 /* Disable the panel fitter if it was on our pipe */
3870 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3871 I915_WRITE(PFIT_CONTROL, 0);
3872
3873 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3874 drm_mode_debug_printmodeline(mode);
3875
3876 /* assign to Ironlake registers */
3877 if (HAS_PCH_SPLIT(dev)) {
3878 fp_reg = pch_fp_reg;
3879 dpll_reg = pch_dpll_reg;
3880 }
3881
3882 if (!has_edp_encoder) {
3883 I915_WRITE(fp_reg, fp);
3884 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3885 I915_READ(dpll_reg);
3886 udelay(150);
3887 }
3888
3889 /* enable transcoder DPLL */
3890 if (HAS_PCH_CPT(dev)) {
3891 temp = I915_READ(PCH_DPLL_SEL);
3892 if (trans_dpll_sel == 0)
3893 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3894 else
3895 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3896 I915_WRITE(PCH_DPLL_SEL, temp);
3897 I915_READ(PCH_DPLL_SEL);
3898 udelay(150);
3899 }
3900
3901 if (HAS_PCH_SPLIT(dev)) {
3902 pipeconf &= ~PIPE_ENABLE_DITHER;
3903 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3904 }
3905
3906 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3907 * This is an exception to the general rule that mode_set doesn't turn
3908 * things on.
3909 */
3910 if (is_lvds) {
3911 u32 lvds;
3912
3913 if (HAS_PCH_SPLIT(dev))
3914 lvds_reg = PCH_LVDS;
3915
3916 lvds = I915_READ(lvds_reg);
3917 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3918 if (pipe == 1) {
3919 if (HAS_PCH_CPT(dev))
3920 lvds |= PORT_TRANS_B_SEL_CPT;
3921 else
3922 lvds |= LVDS_PIPEB_SELECT;
3923 } else {
3924 if (HAS_PCH_CPT(dev))
3925 lvds &= ~PORT_TRANS_SEL_MASK;
3926 else
3927 lvds &= ~LVDS_PIPEB_SELECT;
3928 }
3929 /* set the corresponsding LVDS_BORDER bit */
3930 lvds |= dev_priv->lvds_border_bits;
3931 /* Set the B0-B3 data pairs corresponding to whether we're going to
3932 * set the DPLLs for dual-channel mode or not.
3933 */
3934 if (clock.p2 == 7)
3935 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3936 else
3937 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3938
3939 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3940 * appropriately here, but we need to look more thoroughly into how
3941 * panels behave in the two modes.
3942 */
3943 /* set the dithering flag */
3944 if (IS_I965G(dev)) {
3945 if (dev_priv->lvds_dither) {
3946 if (HAS_PCH_SPLIT(dev)) {
3947 pipeconf |= PIPE_ENABLE_DITHER;
3948 pipeconf |= PIPE_DITHER_TYPE_ST01;
3949 } else
3950 lvds |= LVDS_ENABLE_DITHER;
3951 } else {
3952 if (!HAS_PCH_SPLIT(dev)) {
3953 lvds &= ~LVDS_ENABLE_DITHER;
3954 }
3955 }
3956 }
3957 I915_WRITE(lvds_reg, lvds);
3958 I915_READ(lvds_reg);
3959 }
3960 if (is_dp)
3961 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3962 else if (HAS_PCH_SPLIT(dev)) {
3963 /* For non-DP output, clear any trans DP clock recovery setting.*/
3964 if (pipe == 0) {
3965 I915_WRITE(TRANSA_DATA_M1, 0);
3966 I915_WRITE(TRANSA_DATA_N1, 0);
3967 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3968 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3969 } else {
3970 I915_WRITE(TRANSB_DATA_M1, 0);
3971 I915_WRITE(TRANSB_DATA_N1, 0);
3972 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3973 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3974 }
3975 }
3976
3977 if (!has_edp_encoder) {
3978 I915_WRITE(fp_reg, fp);
3979 I915_WRITE(dpll_reg, dpll);
3980 I915_READ(dpll_reg);
3981 /* Wait for the clocks to stabilize. */
3982 udelay(150);
3983
3984 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3985 if (is_sdvo) {
3986 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3987 if (pixel_multiplier > 1)
3988 pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3989 else
3990 pixel_multiplier = 0;
3991
3992 I915_WRITE(dpll_md_reg,
3993 (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3994 pixel_multiplier);
3995 } else
3996 I915_WRITE(dpll_md_reg, 0);
3997 } else {
3998 /* write it again -- the BIOS does, after all */
3999 I915_WRITE(dpll_reg, dpll);
4000 }
4001 I915_READ(dpll_reg);
4002 /* Wait for the clocks to stabilize. */
4003 udelay(150);
4004 }
4005
4006 if (is_lvds && has_reduced_clock && i915_powersave) {
4007 I915_WRITE(fp_reg + 4, fp2);
4008 intel_crtc->lowfreq_avail = true;
4009 if (HAS_PIPE_CXSR(dev)) {
4010 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4011 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4012 }
4013 } else {
4014 I915_WRITE(fp_reg + 4, fp);
4015 intel_crtc->lowfreq_avail = false;
4016 if (HAS_PIPE_CXSR(dev)) {
4017 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4018 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4019 }
4020 }
4021
4022 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4023 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4024 /* the chip adds 2 halflines automatically */
4025 adjusted_mode->crtc_vdisplay -= 1;
4026 adjusted_mode->crtc_vtotal -= 1;
4027 adjusted_mode->crtc_vblank_start -= 1;
4028 adjusted_mode->crtc_vblank_end -= 1;
4029 adjusted_mode->crtc_vsync_end -= 1;
4030 adjusted_mode->crtc_vsync_start -= 1;
4031 } else
4032 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4033
4034 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4035 ((adjusted_mode->crtc_htotal - 1) << 16));
4036 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4037 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4038 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4039 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4040 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4041 ((adjusted_mode->crtc_vtotal - 1) << 16));
4042 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4043 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4044 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4045 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4046 /* pipesrc and dspsize control the size that is scaled from, which should
4047 * always be the user's requested size.
4048 */
4049 if (!HAS_PCH_SPLIT(dev)) {
4050 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4051 (mode->hdisplay - 1));
4052 I915_WRITE(dsppos_reg, 0);
4053 }
4054 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4055
4056 if (HAS_PCH_SPLIT(dev)) {
4057 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4058 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4059 I915_WRITE(link_m1_reg, m_n.link_m);
4060 I915_WRITE(link_n1_reg, m_n.link_n);
4061
4062 if (has_edp_encoder) {
4063 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4064 } else {
4065 /* enable FDI RX PLL too */
4066 temp = I915_READ(fdi_rx_reg);
4067 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4068 I915_READ(fdi_rx_reg);
4069 udelay(200);
4070
4071 /* enable FDI TX PLL too */
4072 temp = I915_READ(fdi_tx_reg);
4073 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4074 I915_READ(fdi_tx_reg);
4075
4076 /* enable FDI RX PCDCLK */
4077 temp = I915_READ(fdi_rx_reg);
4078 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4079 I915_READ(fdi_rx_reg);
4080 udelay(200);
4081 }
4082 }
4083
4084 I915_WRITE(pipeconf_reg, pipeconf);
4085 I915_READ(pipeconf_reg);
4086
4087 intel_wait_for_vblank(dev, pipe);
4088
4089 if (IS_IRONLAKE(dev)) {
4090 /* enable address swizzle for tiling buffer */
4091 temp = I915_READ(DISP_ARB_CTL);
4092 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4093 }
4094
4095 I915_WRITE(dspcntr_reg, dspcntr);
4096
4097 /* Flush the plane changes */
4098 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4099
4100 intel_update_watermarks(dev);
4101
4102 drm_vblank_post_modeset(dev, pipe);
4103
4104 return ret;
4105 }
4106
4107 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4108 void intel_crtc_load_lut(struct drm_crtc *crtc)
4109 {
4110 struct drm_device *dev = crtc->dev;
4111 struct drm_i915_private *dev_priv = dev->dev_private;
4112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4113 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4114 int i;
4115
4116 /* The clocks have to be on to load the palette. */
4117 if (!crtc->enabled)
4118 return;
4119
4120 /* use legacy palette for Ironlake */
4121 if (HAS_PCH_SPLIT(dev))
4122 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4123 LGC_PALETTE_B;
4124
4125 for (i = 0; i < 256; i++) {
4126 I915_WRITE(palreg + 4 * i,
4127 (intel_crtc->lut_r[i] << 16) |
4128 (intel_crtc->lut_g[i] << 8) |
4129 intel_crtc->lut_b[i]);
4130 }
4131 }
4132
4133 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4134 {
4135 struct drm_device *dev = crtc->dev;
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4138 bool visible = base != 0;
4139 u32 cntl;
4140
4141 if (intel_crtc->cursor_visible == visible)
4142 return;
4143
4144 cntl = I915_READ(CURACNTR);
4145 if (visible) {
4146 /* On these chipsets we can only modify the base whilst
4147 * the cursor is disabled.
4148 */
4149 I915_WRITE(CURABASE, base);
4150
4151 cntl &= ~(CURSOR_FORMAT_MASK);
4152 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4153 cntl |= CURSOR_ENABLE |
4154 CURSOR_GAMMA_ENABLE |
4155 CURSOR_FORMAT_ARGB;
4156 } else
4157 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4158 I915_WRITE(CURACNTR, cntl);
4159
4160 intel_crtc->cursor_visible = visible;
4161 }
4162
4163 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4164 {
4165 struct drm_device *dev = crtc->dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4168 int pipe = intel_crtc->pipe;
4169 bool visible = base != 0;
4170
4171 if (intel_crtc->cursor_visible != visible) {
4172 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4173 if (base) {
4174 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4175 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4176 cntl |= pipe << 28; /* Connect to correct pipe */
4177 } else {
4178 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4179 cntl |= CURSOR_MODE_DISABLE;
4180 }
4181 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4182
4183 intel_crtc->cursor_visible = visible;
4184 }
4185 /* and commit changes on next vblank */
4186 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4187 }
4188
4189 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4190 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4191 {
4192 struct drm_device *dev = crtc->dev;
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4195 int pipe = intel_crtc->pipe;
4196 int x = intel_crtc->cursor_x;
4197 int y = intel_crtc->cursor_y;
4198 u32 base, pos;
4199 bool visible;
4200
4201 pos = 0;
4202
4203 if (intel_crtc->cursor_on && crtc->fb) {
4204 base = intel_crtc->cursor_addr;
4205 if (x > (int) crtc->fb->width)
4206 base = 0;
4207
4208 if (y > (int) crtc->fb->height)
4209 base = 0;
4210 } else
4211 base = 0;
4212
4213 if (x < 0) {
4214 if (x + intel_crtc->cursor_width < 0)
4215 base = 0;
4216
4217 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4218 x = -x;
4219 }
4220 pos |= x << CURSOR_X_SHIFT;
4221
4222 if (y < 0) {
4223 if (y + intel_crtc->cursor_height < 0)
4224 base = 0;
4225
4226 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4227 y = -y;
4228 }
4229 pos |= y << CURSOR_Y_SHIFT;
4230
4231 visible = base != 0;
4232 if (!visible && !intel_crtc->cursor_visible)
4233 return;
4234
4235 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4236 if (IS_845G(dev) || IS_I865G(dev))
4237 i845_update_cursor(crtc, base);
4238 else
4239 i9xx_update_cursor(crtc, base);
4240
4241 if (visible)
4242 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4243 }
4244
4245 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4246 struct drm_file *file_priv,
4247 uint32_t handle,
4248 uint32_t width, uint32_t height)
4249 {
4250 struct drm_device *dev = crtc->dev;
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253 struct drm_gem_object *bo;
4254 struct drm_i915_gem_object *obj_priv;
4255 uint32_t addr;
4256 int ret;
4257
4258 DRM_DEBUG_KMS("\n");
4259
4260 /* if we want to turn off the cursor ignore width and height */
4261 if (!handle) {
4262 DRM_DEBUG_KMS("cursor off\n");
4263 addr = 0;
4264 bo = NULL;
4265 mutex_lock(&dev->struct_mutex);
4266 goto finish;
4267 }
4268
4269 /* Currently we only support 64x64 cursors */
4270 if (width != 64 || height != 64) {
4271 DRM_ERROR("we currently only support 64x64 cursors\n");
4272 return -EINVAL;
4273 }
4274
4275 bo = drm_gem_object_lookup(dev, file_priv, handle);
4276 if (!bo)
4277 return -ENOENT;
4278
4279 obj_priv = to_intel_bo(bo);
4280
4281 if (bo->size < width * height * 4) {
4282 DRM_ERROR("buffer is to small\n");
4283 ret = -ENOMEM;
4284 goto fail;
4285 }
4286
4287 /* we only need to pin inside GTT if cursor is non-phy */
4288 mutex_lock(&dev->struct_mutex);
4289 if (!dev_priv->info->cursor_needs_physical) {
4290 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4291 if (ret) {
4292 DRM_ERROR("failed to pin cursor bo\n");
4293 goto fail_locked;
4294 }
4295
4296 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4297 if (ret) {
4298 DRM_ERROR("failed to move cursor bo into the GTT\n");
4299 goto fail_unpin;
4300 }
4301
4302 addr = obj_priv->gtt_offset;
4303 } else {
4304 int align = IS_I830(dev) ? 16 * 1024 : 256;
4305 ret = i915_gem_attach_phys_object(dev, bo,
4306 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4307 align);
4308 if (ret) {
4309 DRM_ERROR("failed to attach phys object\n");
4310 goto fail_locked;
4311 }
4312 addr = obj_priv->phys_obj->handle->busaddr;
4313 }
4314
4315 if (!IS_I9XX(dev))
4316 I915_WRITE(CURSIZE, (height << 12) | width);
4317
4318 finish:
4319 if (intel_crtc->cursor_bo) {
4320 if (dev_priv->info->cursor_needs_physical) {
4321 if (intel_crtc->cursor_bo != bo)
4322 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4323 } else
4324 i915_gem_object_unpin(intel_crtc->cursor_bo);
4325 drm_gem_object_unreference(intel_crtc->cursor_bo);
4326 }
4327
4328 mutex_unlock(&dev->struct_mutex);
4329
4330 intel_crtc->cursor_addr = addr;
4331 intel_crtc->cursor_bo = bo;
4332 intel_crtc->cursor_width = width;
4333 intel_crtc->cursor_height = height;
4334
4335 intel_crtc_update_cursor(crtc);
4336
4337 return 0;
4338 fail_unpin:
4339 i915_gem_object_unpin(bo);
4340 fail_locked:
4341 mutex_unlock(&dev->struct_mutex);
4342 fail:
4343 drm_gem_object_unreference_unlocked(bo);
4344 return ret;
4345 }
4346
4347 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4348 {
4349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4350
4351 intel_crtc->cursor_x = x;
4352 intel_crtc->cursor_y = y;
4353
4354 intel_crtc_update_cursor(crtc);
4355
4356 return 0;
4357 }
4358
4359 /** Sets the color ramps on behalf of RandR */
4360 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4361 u16 blue, int regno)
4362 {
4363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4364
4365 intel_crtc->lut_r[regno] = red >> 8;
4366 intel_crtc->lut_g[regno] = green >> 8;
4367 intel_crtc->lut_b[regno] = blue >> 8;
4368 }
4369
4370 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4371 u16 *blue, int regno)
4372 {
4373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4374
4375 *red = intel_crtc->lut_r[regno] << 8;
4376 *green = intel_crtc->lut_g[regno] << 8;
4377 *blue = intel_crtc->lut_b[regno] << 8;
4378 }
4379
4380 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4381 u16 *blue, uint32_t start, uint32_t size)
4382 {
4383 int end = (start + size > 256) ? 256 : start + size, i;
4384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4385
4386 for (i = start; i < end; i++) {
4387 intel_crtc->lut_r[i] = red[i] >> 8;
4388 intel_crtc->lut_g[i] = green[i] >> 8;
4389 intel_crtc->lut_b[i] = blue[i] >> 8;
4390 }
4391
4392 intel_crtc_load_lut(crtc);
4393 }
4394
4395 /**
4396 * Get a pipe with a simple mode set on it for doing load-based monitor
4397 * detection.
4398 *
4399 * It will be up to the load-detect code to adjust the pipe as appropriate for
4400 * its requirements. The pipe will be connected to no other encoders.
4401 *
4402 * Currently this code will only succeed if there is a pipe with no encoders
4403 * configured for it. In the future, it could choose to temporarily disable
4404 * some outputs to free up a pipe for its use.
4405 *
4406 * \return crtc, or NULL if no pipes are available.
4407 */
4408
4409 /* VESA 640x480x72Hz mode to set on the pipe */
4410 static struct drm_display_mode load_detect_mode = {
4411 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4412 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4413 };
4414
4415 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4416 struct drm_connector *connector,
4417 struct drm_display_mode *mode,
4418 int *dpms_mode)
4419 {
4420 struct intel_crtc *intel_crtc;
4421 struct drm_crtc *possible_crtc;
4422 struct drm_crtc *supported_crtc =NULL;
4423 struct drm_encoder *encoder = &intel_encoder->enc;
4424 struct drm_crtc *crtc = NULL;
4425 struct drm_device *dev = encoder->dev;
4426 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4427 struct drm_crtc_helper_funcs *crtc_funcs;
4428 int i = -1;
4429
4430 /*
4431 * Algorithm gets a little messy:
4432 * - if the connector already has an assigned crtc, use it (but make
4433 * sure it's on first)
4434 * - try to find the first unused crtc that can drive this connector,
4435 * and use that if we find one
4436 * - if there are no unused crtcs available, try to use the first
4437 * one we found that supports the connector
4438 */
4439
4440 /* See if we already have a CRTC for this connector */
4441 if (encoder->crtc) {
4442 crtc = encoder->crtc;
4443 /* Make sure the crtc and connector are running */
4444 intel_crtc = to_intel_crtc(crtc);
4445 *dpms_mode = intel_crtc->dpms_mode;
4446 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4447 crtc_funcs = crtc->helper_private;
4448 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4449 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4450 }
4451 return crtc;
4452 }
4453
4454 /* Find an unused one (if possible) */
4455 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4456 i++;
4457 if (!(encoder->possible_crtcs & (1 << i)))
4458 continue;
4459 if (!possible_crtc->enabled) {
4460 crtc = possible_crtc;
4461 break;
4462 }
4463 if (!supported_crtc)
4464 supported_crtc = possible_crtc;
4465 }
4466
4467 /*
4468 * If we didn't find an unused CRTC, don't use any.
4469 */
4470 if (!crtc) {
4471 return NULL;
4472 }
4473
4474 encoder->crtc = crtc;
4475 connector->encoder = encoder;
4476 intel_encoder->load_detect_temp = true;
4477
4478 intel_crtc = to_intel_crtc(crtc);
4479 *dpms_mode = intel_crtc->dpms_mode;
4480
4481 if (!crtc->enabled) {
4482 if (!mode)
4483 mode = &load_detect_mode;
4484 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4485 } else {
4486 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4487 crtc_funcs = crtc->helper_private;
4488 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4489 }
4490
4491 /* Add this connector to the crtc */
4492 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4493 encoder_funcs->commit(encoder);
4494 }
4495 /* let the connector get through one full cycle before testing */
4496 intel_wait_for_vblank(dev, intel_crtc->pipe);
4497
4498 return crtc;
4499 }
4500
4501 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4502 struct drm_connector *connector, int dpms_mode)
4503 {
4504 struct drm_encoder *encoder = &intel_encoder->enc;
4505 struct drm_device *dev = encoder->dev;
4506 struct drm_crtc *crtc = encoder->crtc;
4507 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4508 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4509
4510 if (intel_encoder->load_detect_temp) {
4511 encoder->crtc = NULL;
4512 connector->encoder = NULL;
4513 intel_encoder->load_detect_temp = false;
4514 crtc->enabled = drm_helper_crtc_in_use(crtc);
4515 drm_helper_disable_unused_functions(dev);
4516 }
4517
4518 /* Switch crtc and encoder back off if necessary */
4519 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4520 if (encoder->crtc == crtc)
4521 encoder_funcs->dpms(encoder, dpms_mode);
4522 crtc_funcs->dpms(crtc, dpms_mode);
4523 }
4524 }
4525
4526 /* Returns the clock of the currently programmed mode of the given pipe. */
4527 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4528 {
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531 int pipe = intel_crtc->pipe;
4532 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4533 u32 fp;
4534 intel_clock_t clock;
4535
4536 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4537 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4538 else
4539 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4540
4541 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4542 if (IS_PINEVIEW(dev)) {
4543 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4544 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4545 } else {
4546 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4547 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4548 }
4549
4550 if (IS_I9XX(dev)) {
4551 if (IS_PINEVIEW(dev))
4552 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4553 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4554 else
4555 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4556 DPLL_FPA01_P1_POST_DIV_SHIFT);
4557
4558 switch (dpll & DPLL_MODE_MASK) {
4559 case DPLLB_MODE_DAC_SERIAL:
4560 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4561 5 : 10;
4562 break;
4563 case DPLLB_MODE_LVDS:
4564 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4565 7 : 14;
4566 break;
4567 default:
4568 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4569 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4570 return 0;
4571 }
4572
4573 /* XXX: Handle the 100Mhz refclk */
4574 intel_clock(dev, 96000, &clock);
4575 } else {
4576 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4577
4578 if (is_lvds) {
4579 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4580 DPLL_FPA01_P1_POST_DIV_SHIFT);
4581 clock.p2 = 14;
4582
4583 if ((dpll & PLL_REF_INPUT_MASK) ==
4584 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4585 /* XXX: might not be 66MHz */
4586 intel_clock(dev, 66000, &clock);
4587 } else
4588 intel_clock(dev, 48000, &clock);
4589 } else {
4590 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4591 clock.p1 = 2;
4592 else {
4593 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4594 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4595 }
4596 if (dpll & PLL_P2_DIVIDE_BY_4)
4597 clock.p2 = 4;
4598 else
4599 clock.p2 = 2;
4600
4601 intel_clock(dev, 48000, &clock);
4602 }
4603 }
4604
4605 /* XXX: It would be nice to validate the clocks, but we can't reuse
4606 * i830PllIsValid() because it relies on the xf86_config connector
4607 * configuration being accurate, which it isn't necessarily.
4608 */
4609
4610 return clock.dot;
4611 }
4612
4613 /** Returns the currently programmed mode of the given pipe. */
4614 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4615 struct drm_crtc *crtc)
4616 {
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4619 int pipe = intel_crtc->pipe;
4620 struct drm_display_mode *mode;
4621 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4622 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4623 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4624 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4625
4626 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4627 if (!mode)
4628 return NULL;
4629
4630 mode->clock = intel_crtc_clock_get(dev, crtc);
4631 mode->hdisplay = (htot & 0xffff) + 1;
4632 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4633 mode->hsync_start = (hsync & 0xffff) + 1;
4634 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4635 mode->vdisplay = (vtot & 0xffff) + 1;
4636 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4637 mode->vsync_start = (vsync & 0xffff) + 1;
4638 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4639
4640 drm_mode_set_name(mode);
4641 drm_mode_set_crtcinfo(mode, 0);
4642
4643 return mode;
4644 }
4645
4646 #define GPU_IDLE_TIMEOUT 500 /* ms */
4647
4648 /* When this timer fires, we've been idle for awhile */
4649 static void intel_gpu_idle_timer(unsigned long arg)
4650 {
4651 struct drm_device *dev = (struct drm_device *)arg;
4652 drm_i915_private_t *dev_priv = dev->dev_private;
4653
4654 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4655
4656 dev_priv->busy = false;
4657
4658 queue_work(dev_priv->wq, &dev_priv->idle_work);
4659 }
4660
4661 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4662
4663 static void intel_crtc_idle_timer(unsigned long arg)
4664 {
4665 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4666 struct drm_crtc *crtc = &intel_crtc->base;
4667 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4668
4669 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4670
4671 intel_crtc->busy = false;
4672
4673 queue_work(dev_priv->wq, &dev_priv->idle_work);
4674 }
4675
4676 static void intel_increase_pllclock(struct drm_crtc *crtc)
4677 {
4678 struct drm_device *dev = crtc->dev;
4679 drm_i915_private_t *dev_priv = dev->dev_private;
4680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4681 int pipe = intel_crtc->pipe;
4682 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4683 int dpll = I915_READ(dpll_reg);
4684
4685 if (HAS_PCH_SPLIT(dev))
4686 return;
4687
4688 if (!dev_priv->lvds_downclock_avail)
4689 return;
4690
4691 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4692 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4693
4694 /* Unlock panel regs */
4695 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4696 PANEL_UNLOCK_REGS);
4697
4698 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4699 I915_WRITE(dpll_reg, dpll);
4700 dpll = I915_READ(dpll_reg);
4701 intel_wait_for_vblank(dev, pipe);
4702 dpll = I915_READ(dpll_reg);
4703 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4704 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4705
4706 /* ...and lock them again */
4707 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4708 }
4709
4710 /* Schedule downclock */
4711 mod_timer(&intel_crtc->idle_timer, jiffies +
4712 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4713 }
4714
4715 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4716 {
4717 struct drm_device *dev = crtc->dev;
4718 drm_i915_private_t *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
4721 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4722 int dpll = I915_READ(dpll_reg);
4723
4724 if (HAS_PCH_SPLIT(dev))
4725 return;
4726
4727 if (!dev_priv->lvds_downclock_avail)
4728 return;
4729
4730 /*
4731 * Since this is called by a timer, we should never get here in
4732 * the manual case.
4733 */
4734 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4735 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4736
4737 /* Unlock panel regs */
4738 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4739 PANEL_UNLOCK_REGS);
4740
4741 dpll |= DISPLAY_RATE_SELECT_FPA1;
4742 I915_WRITE(dpll_reg, dpll);
4743 dpll = I915_READ(dpll_reg);
4744 intel_wait_for_vblank(dev, pipe);
4745 dpll = I915_READ(dpll_reg);
4746 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4747 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4748
4749 /* ...and lock them again */
4750 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4751 }
4752
4753 }
4754
4755 /**
4756 * intel_idle_update - adjust clocks for idleness
4757 * @work: work struct
4758 *
4759 * Either the GPU or display (or both) went idle. Check the busy status
4760 * here and adjust the CRTC and GPU clocks as necessary.
4761 */
4762 static void intel_idle_update(struct work_struct *work)
4763 {
4764 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4765 idle_work);
4766 struct drm_device *dev = dev_priv->dev;
4767 struct drm_crtc *crtc;
4768 struct intel_crtc *intel_crtc;
4769 int enabled = 0;
4770
4771 if (!i915_powersave)
4772 return;
4773
4774 mutex_lock(&dev->struct_mutex);
4775
4776 i915_update_gfx_val(dev_priv);
4777
4778 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4779 /* Skip inactive CRTCs */
4780 if (!crtc->fb)
4781 continue;
4782
4783 enabled++;
4784 intel_crtc = to_intel_crtc(crtc);
4785 if (!intel_crtc->busy)
4786 intel_decrease_pllclock(crtc);
4787 }
4788
4789 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4790 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4791 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4792 }
4793
4794 mutex_unlock(&dev->struct_mutex);
4795 }
4796
4797 /**
4798 * intel_mark_busy - mark the GPU and possibly the display busy
4799 * @dev: drm device
4800 * @obj: object we're operating on
4801 *
4802 * Callers can use this function to indicate that the GPU is busy processing
4803 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4804 * buffer), we'll also mark the display as busy, so we know to increase its
4805 * clock frequency.
4806 */
4807 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4808 {
4809 drm_i915_private_t *dev_priv = dev->dev_private;
4810 struct drm_crtc *crtc = NULL;
4811 struct intel_framebuffer *intel_fb;
4812 struct intel_crtc *intel_crtc;
4813
4814 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4815 return;
4816
4817 if (!dev_priv->busy) {
4818 if (IS_I945G(dev) || IS_I945GM(dev)) {
4819 u32 fw_blc_self;
4820
4821 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4822 fw_blc_self = I915_READ(FW_BLC_SELF);
4823 fw_blc_self &= ~FW_BLC_SELF_EN;
4824 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4825 }
4826 dev_priv->busy = true;
4827 } else
4828 mod_timer(&dev_priv->idle_timer, jiffies +
4829 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4830
4831 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4832 if (!crtc->fb)
4833 continue;
4834
4835 intel_crtc = to_intel_crtc(crtc);
4836 intel_fb = to_intel_framebuffer(crtc->fb);
4837 if (intel_fb->obj == obj) {
4838 if (!intel_crtc->busy) {
4839 if (IS_I945G(dev) || IS_I945GM(dev)) {
4840 u32 fw_blc_self;
4841
4842 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4843 fw_blc_self = I915_READ(FW_BLC_SELF);
4844 fw_blc_self &= ~FW_BLC_SELF_EN;
4845 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4846 }
4847 /* Non-busy -> busy, upclock */
4848 intel_increase_pllclock(crtc);
4849 intel_crtc->busy = true;
4850 } else {
4851 /* Busy -> busy, put off timer */
4852 mod_timer(&intel_crtc->idle_timer, jiffies +
4853 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4854 }
4855 }
4856 }
4857 }
4858
4859 static void intel_crtc_destroy(struct drm_crtc *crtc)
4860 {
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4862 struct drm_device *dev = crtc->dev;
4863 struct intel_unpin_work *work;
4864 unsigned long flags;
4865
4866 spin_lock_irqsave(&dev->event_lock, flags);
4867 work = intel_crtc->unpin_work;
4868 intel_crtc->unpin_work = NULL;
4869 spin_unlock_irqrestore(&dev->event_lock, flags);
4870
4871 if (work) {
4872 cancel_work_sync(&work->work);
4873 kfree(work);
4874 }
4875
4876 drm_crtc_cleanup(crtc);
4877
4878 kfree(intel_crtc);
4879 }
4880
4881 static void intel_unpin_work_fn(struct work_struct *__work)
4882 {
4883 struct intel_unpin_work *work =
4884 container_of(__work, struct intel_unpin_work, work);
4885
4886 mutex_lock(&work->dev->struct_mutex);
4887 i915_gem_object_unpin(work->old_fb_obj);
4888 drm_gem_object_unreference(work->pending_flip_obj);
4889 drm_gem_object_unreference(work->old_fb_obj);
4890 mutex_unlock(&work->dev->struct_mutex);
4891 kfree(work);
4892 }
4893
4894 static void do_intel_finish_page_flip(struct drm_device *dev,
4895 struct drm_crtc *crtc)
4896 {
4897 drm_i915_private_t *dev_priv = dev->dev_private;
4898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4899 struct intel_unpin_work *work;
4900 struct drm_i915_gem_object *obj_priv;
4901 struct drm_pending_vblank_event *e;
4902 struct timeval now;
4903 unsigned long flags;
4904
4905 /* Ignore early vblank irqs */
4906 if (intel_crtc == NULL)
4907 return;
4908
4909 spin_lock_irqsave(&dev->event_lock, flags);
4910 work = intel_crtc->unpin_work;
4911 if (work == NULL || !work->pending) {
4912 spin_unlock_irqrestore(&dev->event_lock, flags);
4913 return;
4914 }
4915
4916 intel_crtc->unpin_work = NULL;
4917 drm_vblank_put(dev, intel_crtc->pipe);
4918
4919 if (work->event) {
4920 e = work->event;
4921 do_gettimeofday(&now);
4922 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4923 e->event.tv_sec = now.tv_sec;
4924 e->event.tv_usec = now.tv_usec;
4925 list_add_tail(&e->base.link,
4926 &e->base.file_priv->event_list);
4927 wake_up_interruptible(&e->base.file_priv->event_wait);
4928 }
4929
4930 spin_unlock_irqrestore(&dev->event_lock, flags);
4931
4932 obj_priv = to_intel_bo(work->pending_flip_obj);
4933
4934 /* Initial scanout buffer will have a 0 pending flip count */
4935 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4936 atomic_dec_and_test(&obj_priv->pending_flip))
4937 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4938 schedule_work(&work->work);
4939
4940 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4941 }
4942
4943 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4944 {
4945 drm_i915_private_t *dev_priv = dev->dev_private;
4946 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4947
4948 do_intel_finish_page_flip(dev, crtc);
4949 }
4950
4951 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4952 {
4953 drm_i915_private_t *dev_priv = dev->dev_private;
4954 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4955
4956 do_intel_finish_page_flip(dev, crtc);
4957 }
4958
4959 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4960 {
4961 drm_i915_private_t *dev_priv = dev->dev_private;
4962 struct intel_crtc *intel_crtc =
4963 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4964 unsigned long flags;
4965
4966 spin_lock_irqsave(&dev->event_lock, flags);
4967 if (intel_crtc->unpin_work) {
4968 if ((++intel_crtc->unpin_work->pending) > 1)
4969 DRM_ERROR("Prepared flip multiple times\n");
4970 } else {
4971 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4972 }
4973 spin_unlock_irqrestore(&dev->event_lock, flags);
4974 }
4975
4976 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4977 struct drm_framebuffer *fb,
4978 struct drm_pending_vblank_event *event)
4979 {
4980 struct drm_device *dev = crtc->dev;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct intel_framebuffer *intel_fb;
4983 struct drm_i915_gem_object *obj_priv;
4984 struct drm_gem_object *obj;
4985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4986 struct intel_unpin_work *work;
4987 unsigned long flags, offset;
4988 int pipe = intel_crtc->pipe;
4989 u32 pf, pipesrc;
4990 int ret;
4991
4992 work = kzalloc(sizeof *work, GFP_KERNEL);
4993 if (work == NULL)
4994 return -ENOMEM;
4995
4996 work->event = event;
4997 work->dev = crtc->dev;
4998 intel_fb = to_intel_framebuffer(crtc->fb);
4999 work->old_fb_obj = intel_fb->obj;
5000 INIT_WORK(&work->work, intel_unpin_work_fn);
5001
5002 /* We borrow the event spin lock for protecting unpin_work */
5003 spin_lock_irqsave(&dev->event_lock, flags);
5004 if (intel_crtc->unpin_work) {
5005 spin_unlock_irqrestore(&dev->event_lock, flags);
5006 kfree(work);
5007
5008 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5009 return -EBUSY;
5010 }
5011 intel_crtc->unpin_work = work;
5012 spin_unlock_irqrestore(&dev->event_lock, flags);
5013
5014 intel_fb = to_intel_framebuffer(fb);
5015 obj = intel_fb->obj;
5016
5017 mutex_lock(&dev->struct_mutex);
5018 ret = intel_pin_and_fence_fb_obj(dev, obj);
5019 if (ret)
5020 goto cleanup_work;
5021
5022 /* Reference the objects for the scheduled work. */
5023 drm_gem_object_reference(work->old_fb_obj);
5024 drm_gem_object_reference(obj);
5025
5026 crtc->fb = fb;
5027 ret = i915_gem_object_flush_write_domain(obj);
5028 if (ret)
5029 goto cleanup_objs;
5030
5031 ret = drm_vblank_get(dev, intel_crtc->pipe);
5032 if (ret)
5033 goto cleanup_objs;
5034
5035 obj_priv = to_intel_bo(obj);
5036 atomic_inc(&obj_priv->pending_flip);
5037 work->pending_flip_obj = obj;
5038
5039 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5040 u32 flip_mask;
5041
5042 if (intel_crtc->plane)
5043 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5044 else
5045 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5046
5047 BEGIN_LP_RING(2);
5048 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5049 OUT_RING(0);
5050 ADVANCE_LP_RING();
5051 }
5052
5053 work->enable_stall_check = true;
5054
5055 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5056 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5057
5058 BEGIN_LP_RING(4);
5059 switch(INTEL_INFO(dev)->gen) {
5060 case 2:
5061 OUT_RING(MI_DISPLAY_FLIP |
5062 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5063 OUT_RING(fb->pitch);
5064 OUT_RING(obj_priv->gtt_offset + offset);
5065 OUT_RING(MI_NOOP);
5066 break;
5067
5068 case 3:
5069 OUT_RING(MI_DISPLAY_FLIP_I915 |
5070 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5071 OUT_RING(fb->pitch);
5072 OUT_RING(obj_priv->gtt_offset + offset);
5073 OUT_RING(MI_NOOP);
5074 break;
5075
5076 case 4:
5077 case 5:
5078 /* i965+ uses the linear or tiled offsets from the
5079 * Display Registers (which do not change across a page-flip)
5080 * so we need only reprogram the base address.
5081 */
5082 OUT_RING(MI_DISPLAY_FLIP |
5083 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5084 OUT_RING(fb->pitch);
5085 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5086
5087 /* XXX Enabling the panel-fitter across page-flip is so far
5088 * untested on non-native modes, so ignore it for now.
5089 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5090 */
5091 pf = 0;
5092 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5093 OUT_RING(pf | pipesrc);
5094 break;
5095
5096 case 6:
5097 OUT_RING(MI_DISPLAY_FLIP |
5098 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5099 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5100 OUT_RING(obj_priv->gtt_offset);
5101
5102 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5103 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5104 OUT_RING(pf | pipesrc);
5105 break;
5106 }
5107 ADVANCE_LP_RING();
5108
5109 mutex_unlock(&dev->struct_mutex);
5110
5111 trace_i915_flip_request(intel_crtc->plane, obj);
5112
5113 return 0;
5114
5115 cleanup_objs:
5116 drm_gem_object_unreference(work->old_fb_obj);
5117 drm_gem_object_unreference(obj);
5118 cleanup_work:
5119 mutex_unlock(&dev->struct_mutex);
5120
5121 spin_lock_irqsave(&dev->event_lock, flags);
5122 intel_crtc->unpin_work = NULL;
5123 spin_unlock_irqrestore(&dev->event_lock, flags);
5124
5125 kfree(work);
5126
5127 return ret;
5128 }
5129
5130 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5131 .dpms = intel_crtc_dpms,
5132 .mode_fixup = intel_crtc_mode_fixup,
5133 .mode_set = intel_crtc_mode_set,
5134 .mode_set_base = intel_pipe_set_base,
5135 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5136 .prepare = intel_crtc_prepare,
5137 .commit = intel_crtc_commit,
5138 .load_lut = intel_crtc_load_lut,
5139 };
5140
5141 static const struct drm_crtc_funcs intel_crtc_funcs = {
5142 .cursor_set = intel_crtc_cursor_set,
5143 .cursor_move = intel_crtc_cursor_move,
5144 .gamma_set = intel_crtc_gamma_set,
5145 .set_config = drm_crtc_helper_set_config,
5146 .destroy = intel_crtc_destroy,
5147 .page_flip = intel_crtc_page_flip,
5148 };
5149
5150
5151 static void intel_crtc_init(struct drm_device *dev, int pipe)
5152 {
5153 drm_i915_private_t *dev_priv = dev->dev_private;
5154 struct intel_crtc *intel_crtc;
5155 int i;
5156
5157 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5158 if (intel_crtc == NULL)
5159 return;
5160
5161 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5162
5163 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5164 intel_crtc->pipe = pipe;
5165 intel_crtc->plane = pipe;
5166 for (i = 0; i < 256; i++) {
5167 intel_crtc->lut_r[i] = i;
5168 intel_crtc->lut_g[i] = i;
5169 intel_crtc->lut_b[i] = i;
5170 }
5171
5172 /* Swap pipes & planes for FBC on pre-965 */
5173 intel_crtc->pipe = pipe;
5174 intel_crtc->plane = pipe;
5175 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5176 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5177 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5178 }
5179
5180 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5181 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5182 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5183 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5184
5185 intel_crtc->cursor_addr = 0;
5186 intel_crtc->dpms_mode = -1;
5187 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5188
5189 intel_crtc->busy = false;
5190
5191 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5192 (unsigned long)intel_crtc);
5193 }
5194
5195 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5196 struct drm_file *file_priv)
5197 {
5198 drm_i915_private_t *dev_priv = dev->dev_private;
5199 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5200 struct drm_mode_object *drmmode_obj;
5201 struct intel_crtc *crtc;
5202
5203 if (!dev_priv) {
5204 DRM_ERROR("called with no initialization\n");
5205 return -EINVAL;
5206 }
5207
5208 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5209 DRM_MODE_OBJECT_CRTC);
5210
5211 if (!drmmode_obj) {
5212 DRM_ERROR("no such CRTC id\n");
5213 return -EINVAL;
5214 }
5215
5216 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5217 pipe_from_crtc_id->pipe = crtc->pipe;
5218
5219 return 0;
5220 }
5221
5222 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5223 {
5224 struct drm_crtc *crtc = NULL;
5225
5226 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 if (intel_crtc->pipe == pipe)
5229 break;
5230 }
5231 return crtc;
5232 }
5233
5234 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5235 {
5236 int index_mask = 0;
5237 struct drm_encoder *encoder;
5238 int entry = 0;
5239
5240 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5241 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5242 if (type_mask & intel_encoder->clone_mask)
5243 index_mask |= (1 << entry);
5244 entry++;
5245 }
5246 return index_mask;
5247 }
5248
5249
5250 static void intel_setup_outputs(struct drm_device *dev)
5251 {
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253 struct drm_encoder *encoder;
5254 bool dpd_is_edp = false;
5255
5256 if (IS_MOBILE(dev) && !IS_I830(dev))
5257 intel_lvds_init(dev);
5258
5259 if (HAS_PCH_SPLIT(dev)) {
5260 dpd_is_edp = intel_dpd_is_edp(dev);
5261
5262 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5263 intel_dp_init(dev, DP_A);
5264
5265 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5266 intel_dp_init(dev, PCH_DP_D);
5267 }
5268
5269 intel_crt_init(dev);
5270
5271 if (HAS_PCH_SPLIT(dev)) {
5272 int found;
5273
5274 if (I915_READ(HDMIB) & PORT_DETECTED) {
5275 /* PCH SDVOB multiplex with HDMIB */
5276 found = intel_sdvo_init(dev, PCH_SDVOB);
5277 if (!found)
5278 intel_hdmi_init(dev, HDMIB);
5279 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5280 intel_dp_init(dev, PCH_DP_B);
5281 }
5282
5283 if (I915_READ(HDMIC) & PORT_DETECTED)
5284 intel_hdmi_init(dev, HDMIC);
5285
5286 if (I915_READ(HDMID) & PORT_DETECTED)
5287 intel_hdmi_init(dev, HDMID);
5288
5289 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5290 intel_dp_init(dev, PCH_DP_C);
5291
5292 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5293 intel_dp_init(dev, PCH_DP_D);
5294
5295 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5296 bool found = false;
5297
5298 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5299 DRM_DEBUG_KMS("probing SDVOB\n");
5300 found = intel_sdvo_init(dev, SDVOB);
5301 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5302 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5303 intel_hdmi_init(dev, SDVOB);
5304 }
5305
5306 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5307 DRM_DEBUG_KMS("probing DP_B\n");
5308 intel_dp_init(dev, DP_B);
5309 }
5310 }
5311
5312 /* Before G4X SDVOC doesn't have its own detect register */
5313
5314 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5315 DRM_DEBUG_KMS("probing SDVOC\n");
5316 found = intel_sdvo_init(dev, SDVOC);
5317 }
5318
5319 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5320
5321 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5322 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5323 intel_hdmi_init(dev, SDVOC);
5324 }
5325 if (SUPPORTS_INTEGRATED_DP(dev)) {
5326 DRM_DEBUG_KMS("probing DP_C\n");
5327 intel_dp_init(dev, DP_C);
5328 }
5329 }
5330
5331 if (SUPPORTS_INTEGRATED_DP(dev) &&
5332 (I915_READ(DP_D) & DP_DETECTED)) {
5333 DRM_DEBUG_KMS("probing DP_D\n");
5334 intel_dp_init(dev, DP_D);
5335 }
5336 } else if (IS_GEN2(dev))
5337 intel_dvo_init(dev);
5338
5339 if (SUPPORTS_TV(dev))
5340 intel_tv_init(dev);
5341
5342 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5343 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5344
5345 encoder->possible_crtcs = intel_encoder->crtc_mask;
5346 encoder->possible_clones = intel_encoder_clones(dev,
5347 intel_encoder->clone_mask);
5348 }
5349 }
5350
5351 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5352 {
5353 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5354
5355 drm_framebuffer_cleanup(fb);
5356 drm_gem_object_unreference_unlocked(intel_fb->obj);
5357
5358 kfree(intel_fb);
5359 }
5360
5361 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5362 struct drm_file *file_priv,
5363 unsigned int *handle)
5364 {
5365 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5366 struct drm_gem_object *object = intel_fb->obj;
5367
5368 return drm_gem_handle_create(file_priv, object, handle);
5369 }
5370
5371 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5372 .destroy = intel_user_framebuffer_destroy,
5373 .create_handle = intel_user_framebuffer_create_handle,
5374 };
5375
5376 int intel_framebuffer_init(struct drm_device *dev,
5377 struct intel_framebuffer *intel_fb,
5378 struct drm_mode_fb_cmd *mode_cmd,
5379 struct drm_gem_object *obj)
5380 {
5381 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5382 int ret;
5383
5384 if (obj_priv->tiling_mode == I915_TILING_Y)
5385 return -EINVAL;
5386
5387 if (mode_cmd->pitch & 63)
5388 return -EINVAL;
5389
5390 switch (mode_cmd->bpp) {
5391 case 8:
5392 case 16:
5393 case 24:
5394 case 32:
5395 break;
5396 default:
5397 return -EINVAL;
5398 }
5399
5400 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5401 if (ret) {
5402 DRM_ERROR("framebuffer init failed %d\n", ret);
5403 return ret;
5404 }
5405
5406 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5407 intel_fb->obj = obj;
5408 return 0;
5409 }
5410
5411 static struct drm_framebuffer *
5412 intel_user_framebuffer_create(struct drm_device *dev,
5413 struct drm_file *filp,
5414 struct drm_mode_fb_cmd *mode_cmd)
5415 {
5416 struct drm_gem_object *obj;
5417 struct intel_framebuffer *intel_fb;
5418 int ret;
5419
5420 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5421 if (!obj)
5422 return ERR_PTR(-ENOENT);
5423
5424 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5425 if (!intel_fb)
5426 return ERR_PTR(-ENOMEM);
5427
5428 ret = intel_framebuffer_init(dev, intel_fb,
5429 mode_cmd, obj);
5430 if (ret) {
5431 drm_gem_object_unreference_unlocked(obj);
5432 kfree(intel_fb);
5433 return ERR_PTR(ret);
5434 }
5435
5436 return &intel_fb->base;
5437 }
5438
5439 static const struct drm_mode_config_funcs intel_mode_funcs = {
5440 .fb_create = intel_user_framebuffer_create,
5441 .output_poll_changed = intel_fb_output_poll_changed,
5442 };
5443
5444 static struct drm_gem_object *
5445 intel_alloc_context_page(struct drm_device *dev)
5446 {
5447 struct drm_gem_object *ctx;
5448 int ret;
5449
5450 ctx = i915_gem_alloc_object(dev, 4096);
5451 if (!ctx) {
5452 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5453 return NULL;
5454 }
5455
5456 mutex_lock(&dev->struct_mutex);
5457 ret = i915_gem_object_pin(ctx, 4096);
5458 if (ret) {
5459 DRM_ERROR("failed to pin power context: %d\n", ret);
5460 goto err_unref;
5461 }
5462
5463 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5464 if (ret) {
5465 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5466 goto err_unpin;
5467 }
5468 mutex_unlock(&dev->struct_mutex);
5469
5470 return ctx;
5471
5472 err_unpin:
5473 i915_gem_object_unpin(ctx);
5474 err_unref:
5475 drm_gem_object_unreference(ctx);
5476 mutex_unlock(&dev->struct_mutex);
5477 return NULL;
5478 }
5479
5480 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5481 {
5482 struct drm_i915_private *dev_priv = dev->dev_private;
5483 u16 rgvswctl;
5484
5485 rgvswctl = I915_READ16(MEMSWCTL);
5486 if (rgvswctl & MEMCTL_CMD_STS) {
5487 DRM_DEBUG("gpu busy, RCS change rejected\n");
5488 return false; /* still busy with another command */
5489 }
5490
5491 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5492 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5493 I915_WRITE16(MEMSWCTL, rgvswctl);
5494 POSTING_READ16(MEMSWCTL);
5495
5496 rgvswctl |= MEMCTL_CMD_STS;
5497 I915_WRITE16(MEMSWCTL, rgvswctl);
5498
5499 return true;
5500 }
5501
5502 void ironlake_enable_drps(struct drm_device *dev)
5503 {
5504 struct drm_i915_private *dev_priv = dev->dev_private;
5505 u32 rgvmodectl = I915_READ(MEMMODECTL);
5506 u8 fmax, fmin, fstart, vstart;
5507
5508 /* 100ms RC evaluation intervals */
5509 I915_WRITE(RCUPEI, 100000);
5510 I915_WRITE(RCDNEI, 100000);
5511
5512 /* Set max/min thresholds to 90ms and 80ms respectively */
5513 I915_WRITE(RCBMAXAVG, 90000);
5514 I915_WRITE(RCBMINAVG, 80000);
5515
5516 I915_WRITE(MEMIHYST, 1);
5517
5518 /* Set up min, max, and cur for interrupt handling */
5519 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5520 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5521 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5522 MEMMODE_FSTART_SHIFT;
5523 fstart = fmax;
5524
5525 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5526 PXVFREQ_PX_SHIFT;
5527
5528 dev_priv->fmax = fstart; /* IPS callback will increase this */
5529 dev_priv->fstart = fstart;
5530
5531 dev_priv->max_delay = fmax;
5532 dev_priv->min_delay = fmin;
5533 dev_priv->cur_delay = fstart;
5534
5535 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5536 fstart);
5537
5538 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5539
5540 /*
5541 * Interrupts will be enabled in ironlake_irq_postinstall
5542 */
5543
5544 I915_WRITE(VIDSTART, vstart);
5545 POSTING_READ(VIDSTART);
5546
5547 rgvmodectl |= MEMMODE_SWMODE_EN;
5548 I915_WRITE(MEMMODECTL, rgvmodectl);
5549
5550 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5551 DRM_ERROR("stuck trying to change perf mode\n");
5552 msleep(1);
5553
5554 ironlake_set_drps(dev, fstart);
5555
5556 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5557 I915_READ(0x112e0);
5558 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5559 dev_priv->last_count2 = I915_READ(0x112f4);
5560 getrawmonotonic(&dev_priv->last_time2);
5561 }
5562
5563 void ironlake_disable_drps(struct drm_device *dev)
5564 {
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 u16 rgvswctl = I915_READ16(MEMSWCTL);
5567
5568 /* Ack interrupts, disable EFC interrupt */
5569 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5570 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5571 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5572 I915_WRITE(DEIIR, DE_PCU_EVENT);
5573 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5574
5575 /* Go back to the starting frequency */
5576 ironlake_set_drps(dev, dev_priv->fstart);
5577 msleep(1);
5578 rgvswctl |= MEMCTL_CMD_STS;
5579 I915_WRITE(MEMSWCTL, rgvswctl);
5580 msleep(1);
5581
5582 }
5583
5584 static unsigned long intel_pxfreq(u32 vidfreq)
5585 {
5586 unsigned long freq;
5587 int div = (vidfreq & 0x3f0000) >> 16;
5588 int post = (vidfreq & 0x3000) >> 12;
5589 int pre = (vidfreq & 0x7);
5590
5591 if (!pre)
5592 return 0;
5593
5594 freq = ((div * 133333) / ((1<<post) * pre));
5595
5596 return freq;
5597 }
5598
5599 void intel_init_emon(struct drm_device *dev)
5600 {
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5602 u32 lcfuse;
5603 u8 pxw[16];
5604 int i;
5605
5606 /* Disable to program */
5607 I915_WRITE(ECR, 0);
5608 POSTING_READ(ECR);
5609
5610 /* Program energy weights for various events */
5611 I915_WRITE(SDEW, 0x15040d00);
5612 I915_WRITE(CSIEW0, 0x007f0000);
5613 I915_WRITE(CSIEW1, 0x1e220004);
5614 I915_WRITE(CSIEW2, 0x04000004);
5615
5616 for (i = 0; i < 5; i++)
5617 I915_WRITE(PEW + (i * 4), 0);
5618 for (i = 0; i < 3; i++)
5619 I915_WRITE(DEW + (i * 4), 0);
5620
5621 /* Program P-state weights to account for frequency power adjustment */
5622 for (i = 0; i < 16; i++) {
5623 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5624 unsigned long freq = intel_pxfreq(pxvidfreq);
5625 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5626 PXVFREQ_PX_SHIFT;
5627 unsigned long val;
5628
5629 val = vid * vid;
5630 val *= (freq / 1000);
5631 val *= 255;
5632 val /= (127*127*900);
5633 if (val > 0xff)
5634 DRM_ERROR("bad pxval: %ld\n", val);
5635 pxw[i] = val;
5636 }
5637 /* Render standby states get 0 weight */
5638 pxw[14] = 0;
5639 pxw[15] = 0;
5640
5641 for (i = 0; i < 4; i++) {
5642 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5643 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5644 I915_WRITE(PXW + (i * 4), val);
5645 }
5646
5647 /* Adjust magic regs to magic values (more experimental results) */
5648 I915_WRITE(OGW0, 0);
5649 I915_WRITE(OGW1, 0);
5650 I915_WRITE(EG0, 0x00007f00);
5651 I915_WRITE(EG1, 0x0000000e);
5652 I915_WRITE(EG2, 0x000e0000);
5653 I915_WRITE(EG3, 0x68000300);
5654 I915_WRITE(EG4, 0x42000000);
5655 I915_WRITE(EG5, 0x00140031);
5656 I915_WRITE(EG6, 0);
5657 I915_WRITE(EG7, 0);
5658
5659 for (i = 0; i < 8; i++)
5660 I915_WRITE(PXWL + (i * 4), 0);
5661
5662 /* Enable PMON + select events */
5663 I915_WRITE(ECR, 0x80000019);
5664
5665 lcfuse = I915_READ(LCFUSE02);
5666
5667 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5668 }
5669
5670 void intel_init_clock_gating(struct drm_device *dev)
5671 {
5672 struct drm_i915_private *dev_priv = dev->dev_private;
5673
5674 /*
5675 * Disable clock gating reported to work incorrectly according to the
5676 * specs, but enable as much else as we can.
5677 */
5678 if (HAS_PCH_SPLIT(dev)) {
5679 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5680
5681 if (IS_IRONLAKE(dev)) {
5682 /* Required for FBC */
5683 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5684 /* Required for CxSR */
5685 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5686
5687 I915_WRITE(PCH_3DCGDIS0,
5688 MARIUNIT_CLOCK_GATE_DISABLE |
5689 SVSMUNIT_CLOCK_GATE_DISABLE);
5690 }
5691
5692 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5693
5694 /*
5695 * According to the spec the following bits should be set in
5696 * order to enable memory self-refresh
5697 * The bit 22/21 of 0x42004
5698 * The bit 5 of 0x42020
5699 * The bit 15 of 0x45000
5700 */
5701 if (IS_IRONLAKE(dev)) {
5702 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5703 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5704 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5705 I915_WRITE(ILK_DSPCLK_GATE,
5706 (I915_READ(ILK_DSPCLK_GATE) |
5707 ILK_DPARB_CLK_GATE));
5708 I915_WRITE(DISP_ARB_CTL,
5709 (I915_READ(DISP_ARB_CTL) |
5710 DISP_FBC_WM_DIS));
5711 }
5712 /*
5713 * Based on the document from hardware guys the following bits
5714 * should be set unconditionally in order to enable FBC.
5715 * The bit 22 of 0x42000
5716 * The bit 22 of 0x42004
5717 * The bit 7,8,9 of 0x42020.
5718 */
5719 if (IS_IRONLAKE_M(dev)) {
5720 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5721 I915_READ(ILK_DISPLAY_CHICKEN1) |
5722 ILK_FBCQ_DIS);
5723 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5724 I915_READ(ILK_DISPLAY_CHICKEN2) |
5725 ILK_DPARB_GATE);
5726 I915_WRITE(ILK_DSPCLK_GATE,
5727 I915_READ(ILK_DSPCLK_GATE) |
5728 ILK_DPFC_DIS1 |
5729 ILK_DPFC_DIS2 |
5730 ILK_CLK_FBC);
5731 }
5732 return;
5733 } else if (IS_G4X(dev)) {
5734 uint32_t dspclk_gate;
5735 I915_WRITE(RENCLK_GATE_D1, 0);
5736 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5737 GS_UNIT_CLOCK_GATE_DISABLE |
5738 CL_UNIT_CLOCK_GATE_DISABLE);
5739 I915_WRITE(RAMCLK_GATE_D, 0);
5740 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5741 OVRUNIT_CLOCK_GATE_DISABLE |
5742 OVCUNIT_CLOCK_GATE_DISABLE;
5743 if (IS_GM45(dev))
5744 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5745 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5746 } else if (IS_I965GM(dev)) {
5747 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5748 I915_WRITE(RENCLK_GATE_D2, 0);
5749 I915_WRITE(DSPCLK_GATE_D, 0);
5750 I915_WRITE(RAMCLK_GATE_D, 0);
5751 I915_WRITE16(DEUC, 0);
5752 } else if (IS_I965G(dev)) {
5753 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5754 I965_RCC_CLOCK_GATE_DISABLE |
5755 I965_RCPB_CLOCK_GATE_DISABLE |
5756 I965_ISC_CLOCK_GATE_DISABLE |
5757 I965_FBC_CLOCK_GATE_DISABLE);
5758 I915_WRITE(RENCLK_GATE_D2, 0);
5759 } else if (IS_I9XX(dev)) {
5760 u32 dstate = I915_READ(D_STATE);
5761
5762 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5763 DSTATE_DOT_CLOCK_GATING;
5764 I915_WRITE(D_STATE, dstate);
5765 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5766 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5767 } else if (IS_I830(dev)) {
5768 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5769 }
5770
5771 /*
5772 * GPU can automatically power down the render unit if given a page
5773 * to save state.
5774 */
5775 if (IS_IRONLAKE_M(dev)) {
5776 if (dev_priv->renderctx == NULL)
5777 dev_priv->renderctx = intel_alloc_context_page(dev);
5778 if (dev_priv->renderctx) {
5779 struct drm_i915_gem_object *obj_priv;
5780 obj_priv = to_intel_bo(dev_priv->renderctx);
5781 if (obj_priv) {
5782 BEGIN_LP_RING(4);
5783 OUT_RING(MI_SET_CONTEXT);
5784 OUT_RING(obj_priv->gtt_offset |
5785 MI_MM_SPACE_GTT |
5786 MI_SAVE_EXT_STATE_EN |
5787 MI_RESTORE_EXT_STATE_EN |
5788 MI_RESTORE_INHIBIT);
5789 OUT_RING(MI_NOOP);
5790 OUT_RING(MI_FLUSH);
5791 ADVANCE_LP_RING();
5792 }
5793 } else
5794 DRM_DEBUG_KMS("Failed to allocate render context."
5795 "Disable RC6\n");
5796 }
5797
5798 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5799 struct drm_i915_gem_object *obj_priv = NULL;
5800
5801 if (dev_priv->pwrctx) {
5802 obj_priv = to_intel_bo(dev_priv->pwrctx);
5803 } else {
5804 struct drm_gem_object *pwrctx;
5805
5806 pwrctx = intel_alloc_context_page(dev);
5807 if (pwrctx) {
5808 dev_priv->pwrctx = pwrctx;
5809 obj_priv = to_intel_bo(pwrctx);
5810 }
5811 }
5812
5813 if (obj_priv) {
5814 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5815 I915_WRITE(MCHBAR_RENDER_STANDBY,
5816 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5817 }
5818 }
5819 }
5820
5821 /* Set up chip specific display functions */
5822 static void intel_init_display(struct drm_device *dev)
5823 {
5824 struct drm_i915_private *dev_priv = dev->dev_private;
5825
5826 /* We always want a DPMS function */
5827 if (HAS_PCH_SPLIT(dev))
5828 dev_priv->display.dpms = ironlake_crtc_dpms;
5829 else
5830 dev_priv->display.dpms = i9xx_crtc_dpms;
5831
5832 if (I915_HAS_FBC(dev)) {
5833 if (IS_IRONLAKE_M(dev)) {
5834 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5835 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5836 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5837 } else if (IS_GM45(dev)) {
5838 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5839 dev_priv->display.enable_fbc = g4x_enable_fbc;
5840 dev_priv->display.disable_fbc = g4x_disable_fbc;
5841 } else if (IS_I965GM(dev)) {
5842 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5843 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5844 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5845 }
5846 /* 855GM needs testing */
5847 }
5848
5849 /* Returns the core display clock speed */
5850 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5851 dev_priv->display.get_display_clock_speed =
5852 i945_get_display_clock_speed;
5853 else if (IS_I915G(dev))
5854 dev_priv->display.get_display_clock_speed =
5855 i915_get_display_clock_speed;
5856 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5857 dev_priv->display.get_display_clock_speed =
5858 i9xx_misc_get_display_clock_speed;
5859 else if (IS_I915GM(dev))
5860 dev_priv->display.get_display_clock_speed =
5861 i915gm_get_display_clock_speed;
5862 else if (IS_I865G(dev))
5863 dev_priv->display.get_display_clock_speed =
5864 i865_get_display_clock_speed;
5865 else if (IS_I85X(dev))
5866 dev_priv->display.get_display_clock_speed =
5867 i855_get_display_clock_speed;
5868 else /* 852, 830 */
5869 dev_priv->display.get_display_clock_speed =
5870 i830_get_display_clock_speed;
5871
5872 /* For FIFO watermark updates */
5873 if (HAS_PCH_SPLIT(dev)) {
5874 if (IS_IRONLAKE(dev)) {
5875 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5876 dev_priv->display.update_wm = ironlake_update_wm;
5877 else {
5878 DRM_DEBUG_KMS("Failed to get proper latency. "
5879 "Disable CxSR\n");
5880 dev_priv->display.update_wm = NULL;
5881 }
5882 } else
5883 dev_priv->display.update_wm = NULL;
5884 } else if (IS_PINEVIEW(dev)) {
5885 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5886 dev_priv->is_ddr3,
5887 dev_priv->fsb_freq,
5888 dev_priv->mem_freq)) {
5889 DRM_INFO("failed to find known CxSR latency "
5890 "(found ddr%s fsb freq %d, mem freq %d), "
5891 "disabling CxSR\n",
5892 (dev_priv->is_ddr3 == 1) ? "3": "2",
5893 dev_priv->fsb_freq, dev_priv->mem_freq);
5894 /* Disable CxSR and never update its watermark again */
5895 pineview_disable_cxsr(dev);
5896 dev_priv->display.update_wm = NULL;
5897 } else
5898 dev_priv->display.update_wm = pineview_update_wm;
5899 } else if (IS_G4X(dev))
5900 dev_priv->display.update_wm = g4x_update_wm;
5901 else if (IS_I965G(dev))
5902 dev_priv->display.update_wm = i965_update_wm;
5903 else if (IS_I9XX(dev)) {
5904 dev_priv->display.update_wm = i9xx_update_wm;
5905 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5906 } else if (IS_I85X(dev)) {
5907 dev_priv->display.update_wm = i9xx_update_wm;
5908 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5909 } else {
5910 dev_priv->display.update_wm = i830_update_wm;
5911 if (IS_845G(dev))
5912 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5913 else
5914 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5915 }
5916 }
5917
5918 /*
5919 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5920 * resume, or other times. This quirk makes sure that's the case for
5921 * affected systems.
5922 */
5923 static void quirk_pipea_force (struct drm_device *dev)
5924 {
5925 struct drm_i915_private *dev_priv = dev->dev_private;
5926
5927 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5928 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5929 }
5930
5931 struct intel_quirk {
5932 int device;
5933 int subsystem_vendor;
5934 int subsystem_device;
5935 void (*hook)(struct drm_device *dev);
5936 };
5937
5938 struct intel_quirk intel_quirks[] = {
5939 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5940 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5941 /* HP Mini needs pipe A force quirk (LP: #322104) */
5942 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5943
5944 /* Thinkpad R31 needs pipe A force quirk */
5945 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5946 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5947 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5948
5949 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5950 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5951 /* ThinkPad X40 needs pipe A force quirk */
5952
5953 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5954 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5955
5956 /* 855 & before need to leave pipe A & dpll A up */
5957 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5958 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5959 };
5960
5961 static void intel_init_quirks(struct drm_device *dev)
5962 {
5963 struct pci_dev *d = dev->pdev;
5964 int i;
5965
5966 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5967 struct intel_quirk *q = &intel_quirks[i];
5968
5969 if (d->device == q->device &&
5970 (d->subsystem_vendor == q->subsystem_vendor ||
5971 q->subsystem_vendor == PCI_ANY_ID) &&
5972 (d->subsystem_device == q->subsystem_device ||
5973 q->subsystem_device == PCI_ANY_ID))
5974 q->hook(dev);
5975 }
5976 }
5977
5978 /* Disable the VGA plane that we never use */
5979 static void i915_disable_vga(struct drm_device *dev)
5980 {
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5982 u8 sr1;
5983 u32 vga_reg;
5984
5985 if (HAS_PCH_SPLIT(dev))
5986 vga_reg = CPU_VGACNTRL;
5987 else
5988 vga_reg = VGACNTRL;
5989
5990 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5991 outb(1, VGA_SR_INDEX);
5992 sr1 = inb(VGA_SR_DATA);
5993 outb(sr1 | 1<<5, VGA_SR_DATA);
5994 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5995 udelay(300);
5996
5997 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5998 POSTING_READ(vga_reg);
5999 }
6000
6001 void intel_modeset_init(struct drm_device *dev)
6002 {
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004 int i;
6005
6006 drm_mode_config_init(dev);
6007
6008 dev->mode_config.min_width = 0;
6009 dev->mode_config.min_height = 0;
6010
6011 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6012
6013 intel_init_quirks(dev);
6014
6015 intel_init_display(dev);
6016
6017 if (IS_I965G(dev)) {
6018 dev->mode_config.max_width = 8192;
6019 dev->mode_config.max_height = 8192;
6020 } else if (IS_I9XX(dev)) {
6021 dev->mode_config.max_width = 4096;
6022 dev->mode_config.max_height = 4096;
6023 } else {
6024 dev->mode_config.max_width = 2048;
6025 dev->mode_config.max_height = 2048;
6026 }
6027
6028 /* set memory base */
6029 if (IS_I9XX(dev))
6030 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6031 else
6032 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6033
6034 if (IS_MOBILE(dev) || IS_I9XX(dev))
6035 dev_priv->num_pipe = 2;
6036 else
6037 dev_priv->num_pipe = 1;
6038 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6039 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6040
6041 for (i = 0; i < dev_priv->num_pipe; i++) {
6042 intel_crtc_init(dev, i);
6043 }
6044
6045 intel_setup_outputs(dev);
6046
6047 intel_init_clock_gating(dev);
6048
6049 /* Just disable it once at startup */
6050 i915_disable_vga(dev);
6051
6052 if (IS_IRONLAKE_M(dev)) {
6053 ironlake_enable_drps(dev);
6054 intel_init_emon(dev);
6055 }
6056
6057 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6058 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6059 (unsigned long)dev);
6060
6061 intel_setup_overlay(dev);
6062 }
6063
6064 void intel_modeset_cleanup(struct drm_device *dev)
6065 {
6066 struct drm_i915_private *dev_priv = dev->dev_private;
6067 struct drm_crtc *crtc;
6068 struct intel_crtc *intel_crtc;
6069
6070 mutex_lock(&dev->struct_mutex);
6071
6072 drm_kms_helper_poll_fini(dev);
6073 intel_fbdev_fini(dev);
6074
6075 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6076 /* Skip inactive CRTCs */
6077 if (!crtc->fb)
6078 continue;
6079
6080 intel_crtc = to_intel_crtc(crtc);
6081 intel_increase_pllclock(crtc);
6082 }
6083
6084 if (dev_priv->display.disable_fbc)
6085 dev_priv->display.disable_fbc(dev);
6086
6087 if (dev_priv->renderctx) {
6088 struct drm_i915_gem_object *obj_priv;
6089
6090 obj_priv = to_intel_bo(dev_priv->renderctx);
6091 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6092 I915_READ(CCID);
6093 i915_gem_object_unpin(dev_priv->renderctx);
6094 drm_gem_object_unreference(dev_priv->renderctx);
6095 }
6096
6097 if (dev_priv->pwrctx) {
6098 struct drm_i915_gem_object *obj_priv;
6099
6100 obj_priv = to_intel_bo(dev_priv->pwrctx);
6101 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6102 I915_READ(PWRCTXA);
6103 i915_gem_object_unpin(dev_priv->pwrctx);
6104 drm_gem_object_unreference(dev_priv->pwrctx);
6105 }
6106
6107 if (IS_IRONLAKE_M(dev))
6108 ironlake_disable_drps(dev);
6109
6110 mutex_unlock(&dev->struct_mutex);
6111
6112 /* Disable the irq before mode object teardown, for the irq might
6113 * enqueue unpin/hotplug work. */
6114 drm_irq_uninstall(dev);
6115 cancel_work_sync(&dev_priv->hotplug_work);
6116
6117 /* Shut off idle work before the crtcs get freed. */
6118 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6119 intel_crtc = to_intel_crtc(crtc);
6120 del_timer_sync(&intel_crtc->idle_timer);
6121 }
6122 del_timer_sync(&dev_priv->idle_timer);
6123 cancel_work_sync(&dev_priv->idle_work);
6124
6125 drm_mode_config_cleanup(dev);
6126 }
6127
6128 /*
6129 * Return which encoder is currently attached for connector.
6130 */
6131 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6132 {
6133 struct drm_mode_object *obj;
6134 struct drm_encoder *encoder;
6135 int i;
6136
6137 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6138 if (connector->encoder_ids[i] == 0)
6139 break;
6140
6141 obj = drm_mode_object_find(connector->dev,
6142 connector->encoder_ids[i],
6143 DRM_MODE_OBJECT_ENCODER);
6144 if (!obj)
6145 continue;
6146
6147 encoder = obj_to_encoder(obj);
6148 return encoder;
6149 }
6150 return NULL;
6151 }
6152
6153 /*
6154 * set vga decode state - true == enable VGA decode
6155 */
6156 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6157 {
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 u16 gmch_ctrl;
6160
6161 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6162 if (state)
6163 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6164 else
6165 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6166 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6167 return 0;
6168 }
Linux kernel - Deliverables
This page took 0.313385 seconds and 5 git commands to generate.