2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll
)(const intel_limit_t
*limit
,
88 struct drm_crtc
*crtc
,
89 int target
, int refclk
,
90 intel_clock_t
*match_clock
,
91 intel_clock_t
*best_clock
);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device
*dev
)
100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
102 WARN_ON(!HAS_PCH_SPLIT(dev
));
104 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
108 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
109 int target
, int refclk
, intel_clock_t
*match_clock
,
110 intel_clock_t
*best_clock
);
112 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
113 int target
, int refclk
, intel_clock_t
*match_clock
,
114 intel_clock_t
*best_clock
);
117 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
118 int target
, int refclk
, intel_clock_t
*match_clock
,
119 intel_clock_t
*best_clock
);
121 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
122 int target
, int refclk
, intel_clock_t
*match_clock
,
123 intel_clock_t
*best_clock
);
126 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
127 int target
, int refclk
, intel_clock_t
*match_clock
,
128 intel_clock_t
*best_clock
);
130 static inline u32
/* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device
*dev
)
134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo
= {
141 .dot
= { .min
= 25000, .max
= 350000 },
142 .vco
= { .min
= 930000, .max
= 1400000 },
143 .n
= { .min
= 3, .max
= 16 },
144 .m
= { .min
= 96, .max
= 140 },
145 .m1
= { .min
= 18, .max
= 26 },
146 .m2
= { .min
= 6, .max
= 16 },
147 .p
= { .min
= 4, .max
= 128 },
148 .p1
= { .min
= 2, .max
= 33 },
149 .p2
= { .dot_limit
= 165000,
150 .p2_slow
= 4, .p2_fast
= 2 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i8xx_lvds
= {
155 .dot
= { .min
= 25000, .max
= 350000 },
156 .vco
= { .min
= 930000, .max
= 1400000 },
157 .n
= { .min
= 3, .max
= 16 },
158 .m
= { .min
= 96, .max
= 140 },
159 .m1
= { .min
= 18, .max
= 26 },
160 .m2
= { .min
= 6, .max
= 16 },
161 .p
= { .min
= 4, .max
= 128 },
162 .p1
= { .min
= 1, .max
= 6 },
163 .p2
= { .dot_limit
= 165000,
164 .p2_slow
= 14, .p2_fast
= 7 },
165 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_i9xx_sdvo
= {
169 .dot
= { .min
= 20000, .max
= 400000 },
170 .vco
= { .min
= 1400000, .max
= 2800000 },
171 .n
= { .min
= 1, .max
= 6 },
172 .m
= { .min
= 70, .max
= 120 },
173 .m1
= { .min
= 8, .max
= 18 },
174 .m2
= { .min
= 3, .max
= 7 },
175 .p
= { .min
= 5, .max
= 80 },
176 .p1
= { .min
= 1, .max
= 8 },
177 .p2
= { .dot_limit
= 200000,
178 .p2_slow
= 10, .p2_fast
= 5 },
179 .find_pll
= intel_find_best_PLL
,
182 static const intel_limit_t intel_limits_i9xx_lvds
= {
183 .dot
= { .min
= 20000, .max
= 400000 },
184 .vco
= { .min
= 1400000, .max
= 2800000 },
185 .n
= { .min
= 1, .max
= 6 },
186 .m
= { .min
= 70, .max
= 120 },
187 .m1
= { .min
= 8, .max
= 18 },
188 .m2
= { .min
= 3, .max
= 7 },
189 .p
= { .min
= 7, .max
= 98 },
190 .p1
= { .min
= 1, .max
= 8 },
191 .p2
= { .dot_limit
= 112000,
192 .p2_slow
= 14, .p2_fast
= 7 },
193 .find_pll
= intel_find_best_PLL
,
197 static const intel_limit_t intel_limits_g4x_sdvo
= {
198 .dot
= { .min
= 25000, .max
= 270000 },
199 .vco
= { .min
= 1750000, .max
= 3500000},
200 .n
= { .min
= 1, .max
= 4 },
201 .m
= { .min
= 104, .max
= 138 },
202 .m1
= { .min
= 17, .max
= 23 },
203 .m2
= { .min
= 5, .max
= 11 },
204 .p
= { .min
= 10, .max
= 30 },
205 .p1
= { .min
= 1, .max
= 3},
206 .p2
= { .dot_limit
= 270000,
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_hdmi
= {
214 .dot
= { .min
= 22000, .max
= 400000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 16, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 5, .max
= 80 },
221 .p1
= { .min
= 1, .max
= 8},
222 .p2
= { .dot_limit
= 165000,
223 .p2_slow
= 10, .p2_fast
= 5 },
224 .find_pll
= intel_g4x_find_best_PLL
,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
228 .dot
= { .min
= 20000, .max
= 115000 },
229 .vco
= { .min
= 1750000, .max
= 3500000 },
230 .n
= { .min
= 1, .max
= 3 },
231 .m
= { .min
= 104, .max
= 138 },
232 .m1
= { .min
= 17, .max
= 23 },
233 .m2
= { .min
= 5, .max
= 11 },
234 .p
= { .min
= 28, .max
= 112 },
235 .p1
= { .min
= 2, .max
= 8 },
236 .p2
= { .dot_limit
= 0,
237 .p2_slow
= 14, .p2_fast
= 14
239 .find_pll
= intel_g4x_find_best_PLL
,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
243 .dot
= { .min
= 80000, .max
= 224000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 14, .max
= 42 },
250 .p1
= { .min
= 2, .max
= 6 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 7, .p2_fast
= 7
254 .find_pll
= intel_g4x_find_best_PLL
,
257 static const intel_limit_t intel_limits_g4x_display_port
= {
258 .dot
= { .min
= 161670, .max
= 227000 },
259 .vco
= { .min
= 1750000, .max
= 3500000},
260 .n
= { .min
= 1, .max
= 2 },
261 .m
= { .min
= 97, .max
= 108 },
262 .m1
= { .min
= 0x10, .max
= 0x12 },
263 .m2
= { .min
= 0x05, .max
= 0x06 },
264 .p
= { .min
= 10, .max
= 20 },
265 .p1
= { .min
= 1, .max
= 2},
266 .p2
= { .dot_limit
= 0,
267 .p2_slow
= 10, .p2_fast
= 10 },
268 .find_pll
= intel_find_pll_g4x_dp
,
271 static const intel_limit_t intel_limits_pineview_sdvo
= {
272 .dot
= { .min
= 20000, .max
= 400000},
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n
= { .min
= 3, .max
= 6 },
276 .m
= { .min
= 2, .max
= 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 5, .max
= 80 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 200000,
283 .p2_slow
= 10, .p2_fast
= 5 },
284 .find_pll
= intel_find_best_PLL
,
287 static const intel_limit_t intel_limits_pineview_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1700000, .max
= 3500000 },
290 .n
= { .min
= 3, .max
= 6 },
291 .m
= { .min
= 2, .max
= 256 },
292 .m1
= { .min
= 0, .max
= 0 },
293 .m2
= { .min
= 0, .max
= 254 },
294 .p
= { .min
= 7, .max
= 112 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 14 },
298 .find_pll
= intel_find_best_PLL
,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 5 },
310 .m
= { .min
= 79, .max
= 127 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 5, .max
= 80 },
314 .p1
= { .min
= 1, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 10, .p2_fast
= 5 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 118 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 28, .max
= 112 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 14, .p2_fast
= 14 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
335 .dot
= { .min
= 25000, .max
= 350000 },
336 .vco
= { .min
= 1760000, .max
= 3510000 },
337 .n
= { .min
= 1, .max
= 3 },
338 .m
= { .min
= 79, .max
= 127 },
339 .m1
= { .min
= 12, .max
= 22 },
340 .m2
= { .min
= 5, .max
= 9 },
341 .p
= { .min
= 14, .max
= 56 },
342 .p1
= { .min
= 2, .max
= 8 },
343 .p2
= { .dot_limit
= 225000,
344 .p2_slow
= 7, .p2_fast
= 7 },
345 .find_pll
= intel_g4x_find_best_PLL
,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 28, .max
= 112 },
357 .p1
= { .min
= 2, .max
= 8 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 14, .p2_fast
= 14 },
360 .find_pll
= intel_g4x_find_best_PLL
,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000 },
366 .n
= { .min
= 1, .max
= 3 },
367 .m
= { .min
= 79, .max
= 126 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 14, .max
= 42 },
371 .p1
= { .min
= 2, .max
= 6 },
372 .p2
= { .dot_limit
= 225000,
373 .p2_slow
= 7, .p2_fast
= 7 },
374 .find_pll
= intel_g4x_find_best_PLL
,
377 static const intel_limit_t intel_limits_ironlake_display_port
= {
378 .dot
= { .min
= 25000, .max
= 350000 },
379 .vco
= { .min
= 1760000, .max
= 3510000},
380 .n
= { .min
= 1, .max
= 2 },
381 .m
= { .min
= 81, .max
= 90 },
382 .m1
= { .min
= 12, .max
= 22 },
383 .m2
= { .min
= 5, .max
= 9 },
384 .p
= { .min
= 10, .max
= 20 },
385 .p1
= { .min
= 1, .max
= 2},
386 .p2
= { .dot_limit
= 0,
387 .p2_slow
= 10, .p2_fast
= 10 },
388 .find_pll
= intel_find_pll_ironlake_dp
,
391 static const intel_limit_t intel_limits_vlv_dac
= {
392 .dot
= { .min
= 25000, .max
= 270000 },
393 .vco
= { .min
= 4000000, .max
= 6000000 },
394 .n
= { .min
= 1, .max
= 7 },
395 .m
= { .min
= 22, .max
= 450 }, /* guess */
396 .m1
= { .min
= 2, .max
= 3 },
397 .m2
= { .min
= 11, .max
= 156 },
398 .p
= { .min
= 10, .max
= 30 },
399 .p1
= { .min
= 2, .max
= 3 },
400 .p2
= { .dot_limit
= 270000,
401 .p2_slow
= 2, .p2_fast
= 20 },
402 .find_pll
= intel_vlv_find_best_pll
,
405 static const intel_limit_t intel_limits_vlv_hdmi
= {
406 .dot
= { .min
= 20000, .max
= 165000 },
407 .vco
= { .min
= 4000000, .max
= 5994000},
408 .n
= { .min
= 1, .max
= 7 },
409 .m
= { .min
= 60, .max
= 300 }, /* guess */
410 .m1
= { .min
= 2, .max
= 3 },
411 .m2
= { .min
= 11, .max
= 156 },
412 .p
= { .min
= 10, .max
= 30 },
413 .p1
= { .min
= 2, .max
= 3 },
414 .p2
= { .dot_limit
= 270000,
415 .p2_slow
= 2, .p2_fast
= 20 },
416 .find_pll
= intel_vlv_find_best_pll
,
419 static const intel_limit_t intel_limits_vlv_dp
= {
420 .dot
= { .min
= 25000, .max
= 270000 },
421 .vco
= { .min
= 4000000, .max
= 6000000 },
422 .n
= { .min
= 1, .max
= 7 },
423 .m
= { .min
= 22, .max
= 450 },
424 .m1
= { .min
= 2, .max
= 3 },
425 .m2
= { .min
= 11, .max
= 156 },
426 .p
= { .min
= 10, .max
= 30 },
427 .p1
= { .min
= 2, .max
= 3 },
428 .p2
= { .dot_limit
= 270000,
429 .p2_slow
= 2, .p2_fast
= 20 },
430 .find_pll
= intel_vlv_find_best_pll
,
433 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
435 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG
, reg
);
443 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA
);
453 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
456 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA
, val
);
464 I915_WRITE(DPIO_REG
, reg
);
465 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device
*dev
)
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL
, 0);
477 POSTING_READ(DPIO_CTL
);
478 I915_WRITE(DPIO_CTL
, 1);
479 POSTING_READ(DPIO_CTL
);
482 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
485 struct drm_device
*dev
= crtc
->dev
;
486 const intel_limit_t
*limit
;
488 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
489 if (intel_is_dual_link_lvds(dev
)) {
490 if (refclk
== 100000)
491 limit
= &intel_limits_ironlake_dual_lvds_100m
;
493 limit
= &intel_limits_ironlake_dual_lvds
;
495 if (refclk
== 100000)
496 limit
= &intel_limits_ironlake_single_lvds_100m
;
498 limit
= &intel_limits_ironlake_single_lvds
;
500 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
501 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
502 limit
= &intel_limits_ironlake_display_port
;
504 limit
= &intel_limits_ironlake_dac
;
509 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
511 struct drm_device
*dev
= crtc
->dev
;
512 const intel_limit_t
*limit
;
514 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
515 if (intel_is_dual_link_lvds(dev
))
516 limit
= &intel_limits_g4x_dual_channel_lvds
;
518 limit
= &intel_limits_g4x_single_channel_lvds
;
519 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
520 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
521 limit
= &intel_limits_g4x_hdmi
;
522 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
523 limit
= &intel_limits_g4x_sdvo
;
524 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
525 limit
= &intel_limits_g4x_display_port
;
526 } else /* The option is for other outputs */
527 limit
= &intel_limits_i9xx_sdvo
;
532 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
534 struct drm_device
*dev
= crtc
->dev
;
535 const intel_limit_t
*limit
;
537 if (HAS_PCH_SPLIT(dev
))
538 limit
= intel_ironlake_limit(crtc
, refclk
);
539 else if (IS_G4X(dev
)) {
540 limit
= intel_g4x_limit(crtc
);
541 } else if (IS_PINEVIEW(dev
)) {
542 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
543 limit
= &intel_limits_pineview_lvds
;
545 limit
= &intel_limits_pineview_sdvo
;
546 } else if (IS_VALLEYVIEW(dev
)) {
547 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
548 limit
= &intel_limits_vlv_dac
;
549 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
550 limit
= &intel_limits_vlv_hdmi
;
552 limit
= &intel_limits_vlv_dp
;
553 } else if (!IS_GEN2(dev
)) {
554 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
555 limit
= &intel_limits_i9xx_lvds
;
557 limit
= &intel_limits_i9xx_sdvo
;
559 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
560 limit
= &intel_limits_i8xx_lvds
;
562 limit
= &intel_limits_i8xx_dvo
;
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
570 clock
->m
= clock
->m2
+ 2;
571 clock
->p
= clock
->p1
* clock
->p2
;
572 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
573 clock
->dot
= clock
->vco
/ clock
->p
;
576 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
578 if (IS_PINEVIEW(dev
)) {
579 pineview_clock(refclk
, clock
);
582 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
583 clock
->p
= clock
->p1
* clock
->p2
;
584 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
585 clock
->dot
= clock
->vco
/ clock
->p
;
589 * Returns whether any output on the specified pipe is of the specified type
591 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
593 struct drm_device
*dev
= crtc
->dev
;
594 struct intel_encoder
*encoder
;
596 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
597 if (encoder
->type
== type
)
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_device
*dev
,
610 const intel_limit_t
*limit
,
611 const intel_clock_t
*clock
)
613 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
616 INTELPllInvalid("p out of range\n");
617 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
625 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
626 INTELPllInvalid("n out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
640 int target
, int refclk
, intel_clock_t
*match_clock
,
641 intel_clock_t
*best_clock
)
644 struct drm_device
*dev
= crtc
->dev
;
648 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev
))
655 clock
.p2
= limit
->p2
.p2_fast
;
657 clock
.p2
= limit
->p2
.p2_slow
;
659 if (target
< limit
->p2
.dot_limit
)
660 clock
.p2
= limit
->p2
.p2_slow
;
662 clock
.p2
= limit
->p2
.p2_fast
;
665 memset(best_clock
, 0, sizeof(*best_clock
));
667 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
669 for (clock
.m2
= limit
->m2
.min
;
670 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
671 /* m1 is always 0 in Pineview */
672 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
674 for (clock
.n
= limit
->n
.min
;
675 clock
.n
<= limit
->n
.max
; clock
.n
++) {
676 for (clock
.p1
= limit
->p1
.min
;
677 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
680 intel_clock(dev
, refclk
, &clock
);
681 if (!intel_PLL_is_valid(dev
, limit
,
685 clock
.p
!= match_clock
->p
)
688 this_err
= abs(clock
.dot
- target
);
689 if (this_err
< err
) {
698 return (err
!= target
);
702 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
703 int target
, int refclk
, intel_clock_t
*match_clock
,
704 intel_clock_t
*best_clock
)
706 struct drm_device
*dev
= crtc
->dev
;
710 /* approximately equals target * 0.00585 */
711 int err_most
= (target
>> 8) + (target
>> 9);
714 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (HAS_PCH_SPLIT(dev
))
721 if (intel_is_dual_link_lvds(dev
))
722 clock
.p2
= limit
->p2
.p2_fast
;
724 clock
.p2
= limit
->p2
.p2_slow
;
726 if (target
< limit
->p2
.dot_limit
)
727 clock
.p2
= limit
->p2
.p2_slow
;
729 clock
.p2
= limit
->p2
.p2_fast
;
732 memset(best_clock
, 0, sizeof(*best_clock
));
733 max_n
= limit
->n
.max
;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock
.m1
= limit
->m1
.max
;
738 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
739 for (clock
.m2
= limit
->m2
.max
;
740 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
741 for (clock
.p1
= limit
->p1
.max
;
742 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
745 intel_clock(dev
, refclk
, &clock
);
746 if (!intel_PLL_is_valid(dev
, limit
,
750 clock
.p
!= match_clock
->p
)
753 this_err
= abs(clock
.dot
- target
);
754 if (this_err
< err_most
) {
768 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
769 int target
, int refclk
, intel_clock_t
*match_clock
,
770 intel_clock_t
*best_clock
)
772 struct drm_device
*dev
= crtc
->dev
;
775 if (target
< 200000) {
788 intel_clock(dev
, refclk
, &clock
);
789 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
795 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
796 int target
, int refclk
, intel_clock_t
*match_clock
,
797 intel_clock_t
*best_clock
)
800 if (target
< 200000) {
813 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
814 clock
.p
= (clock
.p1
* clock
.p2
);
815 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
817 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
821 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
822 int target
, int refclk
, intel_clock_t
*match_clock
,
823 intel_clock_t
*best_clock
)
825 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
827 u32 updrate
, minupdate
, fracbits
, p
;
828 unsigned long bestppm
, ppm
, absppm
;
832 dotclk
= target
* 1000;
835 fastclk
= dotclk
/ (2*100);
839 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
840 bestm1
= bestm2
= bestp1
= bestp2
= 0;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
844 updrate
= refclk
/ n
;
845 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
846 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
852 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
853 refclk
) / (2*refclk
));
856 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
857 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
858 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
859 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
863 if (absppm
< bestppm
- 10) {
880 best_clock
->n
= bestn
;
881 best_clock
->m1
= bestm1
;
882 best_clock
->m2
= bestm2
;
883 best_clock
->p1
= bestp1
;
884 best_clock
->p2
= bestp2
;
889 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
892 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
893 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
895 return intel_crtc
->cpu_transcoder
;
898 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
903 frame
= I915_READ(frame_reg
);
905 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
910 * intel_wait_for_vblank - wait for vblank on a given pipe
912 * @pipe: pipe to wait for
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
917 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
920 int pipestat_reg
= PIPESTAT(pipe
);
922 if (INTEL_INFO(dev
)->gen
>= 5) {
923 ironlake_wait_for_vblank(dev
, pipe
);
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
940 I915_WRITE(pipestat_reg
,
941 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg
) &
945 PIPE_VBLANK_INTERRUPT_STATUS
,
947 DRM_DEBUG_KMS("vblank wait timed out\n");
951 * intel_wait_for_pipe_off - wait for pipe to turn off
953 * @pipe: pipe to wait for
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
960 * wait for the pipe register state bit to turn off
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
967 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
973 if (INTEL_INFO(dev
)->gen
>= 4) {
974 int reg
= PIPECONF(cpu_transcoder
);
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
979 WARN(1, "pipe_off wait timed out\n");
981 u32 last_line
, line_mask
;
982 int reg
= PIPEDSL(pipe
);
983 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
986 line_mask
= DSL_LINEMASK_GEN2
;
988 line_mask
= DSL_LINEMASK_GEN3
;
990 /* Wait for the display line to settle */
992 last_line
= I915_READ(reg
) & line_mask
;
994 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
995 time_after(timeout
, jiffies
));
996 if (time_after(jiffies
, timeout
))
997 WARN(1, "pipe_off wait timed out\n");
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1006 * Returns true if @port is connected, false otherwise.
1008 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1009 struct intel_digital_port
*port
)
1013 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1014 switch(port
->port
) {
1016 bit
= SDE_PORTB_HOTPLUG
;
1019 bit
= SDE_PORTC_HOTPLUG
;
1022 bit
= SDE_PORTD_HOTPLUG
;
1028 switch(port
->port
) {
1030 bit
= SDE_PORTB_HOTPLUG_CPT
;
1033 bit
= SDE_PORTC_HOTPLUG_CPT
;
1036 bit
= SDE_PORTD_HOTPLUG_CPT
;
1043 return I915_READ(SDEISR
) & bit
;
1046 static const char *state_string(bool enabled
)
1048 return enabled
? "on" : "off";
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private
*dev_priv
,
1053 enum pipe pipe
, bool state
)
1060 val
= I915_READ(reg
);
1061 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1062 WARN(cur_state
!= state
,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state
), state_string(cur_state
));
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1070 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1071 struct intel_pch_pll
*pll
,
1072 struct intel_crtc
*crtc
,
1078 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1087 val
= I915_READ(pll
->pll_reg
);
1088 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1089 WARN(cur_state
!= state
,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1097 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1098 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1099 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state
, crtc
->pipe
, pch_dpll
)) {
1102 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1103 WARN(cur_state
!= state
,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll
->pll_reg
== _PCH_DPLL_B
,
1106 state_string(state
),
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1115 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
->dev
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1130 reg
= FDI_TX_CTL(pipe
);
1131 val
= I915_READ(reg
);
1132 cur_state
= !!(val
& FDI_TX_ENABLE
);
1134 WARN(cur_state
!= state
,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state
), state_string(cur_state
));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv
->info
->gen
== 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
->dev
))
1172 reg
= FDI_TX_CTL(pipe
);
1173 val
= I915_READ(reg
);
1174 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1183 reg
= FDI_RX_CTL(pipe
);
1184 val
= I915_READ(reg
);
1185 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1191 int pp_reg
, lvds_reg
;
1193 enum pipe panel_pipe
= PIPE_A
;
1196 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1197 pp_reg
= PCH_PP_CONTROL
;
1198 lvds_reg
= PCH_LVDS
;
1200 pp_reg
= PP_CONTROL
;
1204 val
= I915_READ(pp_reg
);
1205 if (!(val
& PANEL_POWER_ON
) ||
1206 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1209 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1210 panel_pipe
= PIPE_B
;
1212 WARN(panel_pipe
== pipe
&& locked
,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1223 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1230 if (IS_HASWELL(dev_priv
->dev
) && cpu_transcoder
!= TRANSCODER_EDP
&&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_ENABLE
)) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv
->dev
) || IS_VALLEYVIEW(dev_priv
->dev
)) {
1271 reg
= DSPCNTR(pipe
);
1272 val
= I915_READ(reg
);
1273 WARN((val
& DISPLAY_PLANE_ENABLE
),
1274 "plane %c assertion failure, should be disabled but not\n",
1279 /* Need to check both planes against the pipe */
1280 for (i
= 0; i
< 2; i
++) {
1282 val
= I915_READ(reg
);
1283 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1284 DISPPLANE_SEL_PIPE_SHIFT
;
1285 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i
), pipe_name(pipe
));
1291 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1296 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1301 val
= I915_READ(PCH_DREF_CONTROL
);
1302 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1303 DREF_SUPERSPREAD_SOURCE_MASK
));
1304 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1307 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1314 reg
= TRANSCONF(pipe
);
1315 val
= I915_READ(reg
);
1316 enabled
= !!(val
& TRANS_ENABLE
);
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1322 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1323 enum pipe pipe
, u32 port_sel
, u32 val
)
1325 if ((val
& DP_PORT_EN
) == 0)
1328 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1329 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1330 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1331 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1334 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1340 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1341 enum pipe pipe
, u32 val
)
1343 if ((val
& SDVO_ENABLE
) == 0)
1346 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1347 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1350 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1356 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1357 enum pipe pipe
, u32 val
)
1359 if ((val
& LVDS_PORT_EN
) == 0)
1362 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1363 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1366 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1372 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1373 enum pipe pipe
, u32 val
)
1375 if ((val
& ADPA_DAC_ENABLE
) == 0)
1377 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1378 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1381 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1387 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1388 enum pipe pipe
, int reg
, u32 port_sel
)
1390 u32 val
= I915_READ(reg
);
1391 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1393 reg
, pipe_name(pipe
));
1395 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1396 && (val
& DP_PIPEB_SELECT
),
1397 "IBX PCH dp port still using transcoder B\n");
1400 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1401 enum pipe pipe
, int reg
)
1403 u32 val
= I915_READ(reg
);
1404 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg
, pipe_name(pipe
));
1408 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1409 && (val
& SDVO_PIPE_B_SELECT
),
1410 "IBX PCH hdmi port still using transcoder B\n");
1413 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1419 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1420 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1421 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1424 val
= I915_READ(reg
);
1425 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
1430 val
= I915_READ(reg
);
1431 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1435 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1436 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1437 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1449 * Note! This is for pre-ILK only.
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1453 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1458 /* No really, not for ILK+ */
1459 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1463 assert_panel_unlocked(dev_priv
, pipe
);
1466 val
= I915_READ(reg
);
1467 val
|= DPLL_VCO_ENABLE
;
1469 /* We do this three times for luck */
1470 I915_WRITE(reg
, val
);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg
, val
);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg
, val
);
1478 udelay(150); /* wait for warmup */
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1488 * Note! This is for pre-ILK only.
1490 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv
, pipe
);
1503 val
= I915_READ(reg
);
1504 val
&= ~DPLL_VCO_ENABLE
;
1505 I915_WRITE(reg
, val
);
1511 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1512 enum intel_sbi_destination destination
)
1516 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1518 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
1524 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1525 I915_WRITE(SBI_DATA
, value
);
1527 if (destination
== SBI_ICLK
)
1528 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1530 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1531 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1533 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1541 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1542 enum intel_sbi_destination destination
)
1545 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1547 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1553 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1555 if (destination
== SBI_ICLK
)
1556 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1558 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1559 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1561 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567 return I915_READ(SBI_DATA
);
1571 * ironlake_enable_pch_pll - enable PCH PLL
1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1578 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1580 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1581 struct intel_pch_pll
*pll
;
1585 /* PCH PLLs only available on ILK, SNB and IVB */
1586 BUG_ON(dev_priv
->info
->gen
< 5);
1587 pll
= intel_crtc
->pch_pll
;
1591 if (WARN_ON(pll
->refcount
== 0))
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll
->pll_reg
, pll
->active
, pll
->on
,
1596 intel_crtc
->base
.base
.id
);
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv
);
1601 if (pll
->active
++ && pll
->on
) {
1602 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1609 val
= I915_READ(reg
);
1610 val
|= DPLL_VCO_ENABLE
;
1611 I915_WRITE(reg
, val
);
1618 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1620 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1621 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv
->info
->gen
< 5);
1630 if (WARN_ON(pll
->refcount
== 0))
1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll
->pll_reg
, pll
->active
, pll
->on
,
1635 intel_crtc
->base
.base
.id
);
1637 if (WARN_ON(pll
->active
== 0)) {
1638 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1642 if (--pll
->active
) {
1643 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1653 val
= I915_READ(reg
);
1654 val
&= ~DPLL_VCO_ENABLE
;
1655 I915_WRITE(reg
, val
);
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1665 struct drm_device
*dev
= dev_priv
->dev
;
1666 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1667 uint32_t reg
, val
, pipeconf_val
;
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv
->info
->gen
< 5);
1672 /* Make sure PCH DPLL is enabled */
1673 assert_pch_pll_enabled(dev_priv
,
1674 to_intel_crtc(crtc
)->pch_pll
,
1675 to_intel_crtc(crtc
));
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv
, pipe
);
1679 assert_fdi_rx_enabled(dev_priv
, pipe
);
1681 if (HAS_PCH_CPT(dev
)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg
= TRANS_CHICKEN2(pipe
);
1685 val
= I915_READ(reg
);
1686 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1687 I915_WRITE(reg
, val
);
1690 reg
= TRANSCONF(pipe
);
1691 val
= I915_READ(reg
);
1692 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1694 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1699 val
&= ~PIPECONF_BPC_MASK
;
1700 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1703 val
&= ~TRANS_INTERLACE_MASK
;
1704 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1705 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1706 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1707 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1709 val
|= TRANS_INTERLACED
;
1711 val
|= TRANS_PROGRESSIVE
;
1713 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1714 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1719 enum transcoder cpu_transcoder
)
1721 u32 val
, pipeconf_val
;
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv
->info
->gen
< 5);
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1728 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1730 /* Workaround: set timing override bit. */
1731 val
= I915_READ(_TRANSA_CHICKEN2
);
1732 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1733 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1736 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1738 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1739 PIPECONF_INTERLACED_ILK
)
1740 val
|= TRANS_INTERLACED
;
1742 val
|= TRANS_PROGRESSIVE
;
1744 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1745 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1752 struct drm_device
*dev
= dev_priv
->dev
;
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv
, pipe
);
1757 assert_fdi_rx_disabled(dev_priv
, pipe
);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv
, pipe
);
1762 reg
= TRANSCONF(pipe
);
1763 val
= I915_READ(reg
);
1764 val
&= ~TRANS_ENABLE
;
1765 I915_WRITE(reg
, val
);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1768 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1770 if (!HAS_PCH_IBX(dev
)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg
= TRANS_CHICKEN2(pipe
);
1773 val
= I915_READ(reg
);
1774 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1775 I915_WRITE(reg
, val
);
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1783 val
= I915_READ(_TRANSACONF
);
1784 val
&= ~TRANS_ENABLE
;
1785 I915_WRITE(_TRANSACONF
, val
);
1786 /* wait for PCH transcoder off, transcoder state */
1787 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
1790 /* Workaround: clear timing override bit. */
1791 val
= I915_READ(_TRANSA_CHICKEN2
);
1792 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1793 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1797 * intel_enable_pipe - enable a pipe, asserting requirements
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1805 * @pipe should be %PIPE_A or %PIPE_B.
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1810 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1813 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1815 enum pipe pch_transcoder
;
1819 if (HAS_PCH_LPT(dev_priv
->dev
))
1820 pch_transcoder
= TRANSCODER_A
;
1822 pch_transcoder
= pipe
;
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1829 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1830 assert_pll_enabled(dev_priv
, pipe
);
1833 /* if driving the PCH, we need FDI enabled */
1834 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1835 assert_fdi_tx_pll_enabled(dev_priv
,
1836 (enum pipe
) cpu_transcoder
);
1838 /* FIXME: assert CPU port conditions for SNB+ */
1841 reg
= PIPECONF(cpu_transcoder
);
1842 val
= I915_READ(reg
);
1843 if (val
& PIPECONF_ENABLE
)
1846 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1847 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1851 * intel_disable_pipe - disable a pipe, asserting requirements
1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1858 * @pipe should be %PIPE_A or %PIPE_B.
1860 * Will wait until the pipe has shut down before returning.
1862 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1865 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1874 assert_planes_disabled(dev_priv
, pipe
);
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1880 reg
= PIPECONF(cpu_transcoder
);
1881 val
= I915_READ(reg
);
1882 if ((val
& PIPECONF_ENABLE
) == 0)
1885 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1886 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1893 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1896 if (dev_priv
->info
->gen
>= 4)
1897 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1899 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1910 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1911 enum plane plane
, enum pipe pipe
)
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv
, pipe
);
1919 reg
= DSPCNTR(plane
);
1920 val
= I915_READ(reg
);
1921 if (val
& DISPLAY_PLANE_ENABLE
)
1924 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1925 intel_flush_display_plane(dev_priv
, plane
);
1926 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1935 * Disable @plane; should be an independent operation.
1937 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1938 enum plane plane
, enum pipe pipe
)
1943 reg
= DSPCNTR(plane
);
1944 val
= I915_READ(reg
);
1945 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1948 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1949 intel_flush_display_plane(dev_priv
, plane
);
1950 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1953 static bool need_vtd_wa(struct drm_device
*dev
)
1955 #ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1963 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1964 struct drm_i915_gem_object
*obj
,
1965 struct intel_ring_buffer
*pipelined
)
1967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1971 switch (obj
->tiling_mode
) {
1972 case I915_TILING_NONE
:
1973 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1974 alignment
= 128 * 1024;
1975 else if (INTEL_INFO(dev
)->gen
>= 4)
1976 alignment
= 4 * 1024;
1978 alignment
= 64 * 1024;
1981 /* pin() will align the object as required by fence */
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1997 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1998 alignment
= 256 * 1024;
2000 dev_priv
->mm
.interruptible
= false;
2001 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2003 goto err_interruptible
;
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2010 ret
= i915_gem_object_get_fence(obj
);
2014 i915_gem_object_pin_fence(obj
);
2016 dev_priv
->mm
.interruptible
= true;
2020 i915_gem_object_unpin(obj
);
2022 dev_priv
->mm
.interruptible
= true;
2026 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2028 i915_gem_object_unpin_fence(obj
);
2029 i915_gem_object_unpin(obj
);
2032 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
2034 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2035 unsigned int tiling_mode
,
2039 if (tiling_mode
!= I915_TILING_NONE
) {
2040 unsigned int tile_rows
, tiles
;
2045 tiles
= *x
/ (512/cpp
);
2048 return tile_rows
* pitch
* 8 + tiles
* 4096;
2050 unsigned int offset
;
2052 offset
= *y
* pitch
+ *x
* cpp
;
2054 *x
= (offset
& 4095) / cpp
;
2055 return offset
& -4096;
2059 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2062 struct drm_device
*dev
= crtc
->dev
;
2063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2064 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2065 struct intel_framebuffer
*intel_fb
;
2066 struct drm_i915_gem_object
*obj
;
2067 int plane
= intel_crtc
->plane
;
2068 unsigned long linear_offset
;
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2081 intel_fb
= to_intel_framebuffer(fb
);
2082 obj
= intel_fb
->obj
;
2084 reg
= DSPCNTR(plane
);
2085 dspcntr
= I915_READ(reg
);
2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2088 switch (fb
->pixel_format
) {
2090 dspcntr
|= DISPPLANE_8BPP
;
2092 case DRM_FORMAT_XRGB1555
:
2093 case DRM_FORMAT_ARGB1555
:
2094 dspcntr
|= DISPPLANE_BGRX555
;
2096 case DRM_FORMAT_RGB565
:
2097 dspcntr
|= DISPPLANE_BGRX565
;
2099 case DRM_FORMAT_XRGB8888
:
2100 case DRM_FORMAT_ARGB8888
:
2101 dspcntr
|= DISPPLANE_BGRX888
;
2103 case DRM_FORMAT_XBGR8888
:
2104 case DRM_FORMAT_ABGR8888
:
2105 dspcntr
|= DISPPLANE_RGBX888
;
2107 case DRM_FORMAT_XRGB2101010
:
2108 case DRM_FORMAT_ARGB2101010
:
2109 dspcntr
|= DISPPLANE_BGRX101010
;
2111 case DRM_FORMAT_XBGR2101010
:
2112 case DRM_FORMAT_ABGR2101010
:
2113 dspcntr
|= DISPPLANE_RGBX101010
;
2116 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2120 if (INTEL_INFO(dev
)->gen
>= 4) {
2121 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2122 dspcntr
|= DISPPLANE_TILED
;
2124 dspcntr
&= ~DISPPLANE_TILED
;
2127 I915_WRITE(reg
, dspcntr
);
2129 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2131 if (INTEL_INFO(dev
)->gen
>= 4) {
2132 intel_crtc
->dspaddr_offset
=
2133 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2134 fb
->bits_per_pixel
/ 8,
2136 linear_offset
-= intel_crtc
->dspaddr_offset
;
2138 intel_crtc
->dspaddr_offset
= linear_offset
;
2141 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2142 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2143 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2144 if (INTEL_INFO(dev
)->gen
>= 4) {
2145 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2146 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2147 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2148 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2150 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2156 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2157 struct drm_framebuffer
*fb
, int x
, int y
)
2159 struct drm_device
*dev
= crtc
->dev
;
2160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2162 struct intel_framebuffer
*intel_fb
;
2163 struct drm_i915_gem_object
*obj
;
2164 int plane
= intel_crtc
->plane
;
2165 unsigned long linear_offset
;
2175 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2179 intel_fb
= to_intel_framebuffer(fb
);
2180 obj
= intel_fb
->obj
;
2182 reg
= DSPCNTR(plane
);
2183 dspcntr
= I915_READ(reg
);
2184 /* Mask out pixel format bits in case we change it */
2185 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2186 switch (fb
->pixel_format
) {
2188 dspcntr
|= DISPPLANE_8BPP
;
2190 case DRM_FORMAT_RGB565
:
2191 dspcntr
|= DISPPLANE_BGRX565
;
2193 case DRM_FORMAT_XRGB8888
:
2194 case DRM_FORMAT_ARGB8888
:
2195 dspcntr
|= DISPPLANE_BGRX888
;
2197 case DRM_FORMAT_XBGR8888
:
2198 case DRM_FORMAT_ABGR8888
:
2199 dspcntr
|= DISPPLANE_RGBX888
;
2201 case DRM_FORMAT_XRGB2101010
:
2202 case DRM_FORMAT_ARGB2101010
:
2203 dspcntr
|= DISPPLANE_BGRX101010
;
2205 case DRM_FORMAT_XBGR2101010
:
2206 case DRM_FORMAT_ABGR2101010
:
2207 dspcntr
|= DISPPLANE_RGBX101010
;
2210 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2214 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2215 dspcntr
|= DISPPLANE_TILED
;
2217 dspcntr
&= ~DISPPLANE_TILED
;
2220 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2222 I915_WRITE(reg
, dspcntr
);
2224 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2225 intel_crtc
->dspaddr_offset
=
2226 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2227 fb
->bits_per_pixel
/ 8,
2229 linear_offset
-= intel_crtc
->dspaddr_offset
;
2231 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2232 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2233 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2234 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2235 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2236 if (IS_HASWELL(dev
)) {
2237 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2239 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2240 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2247 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2249 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2250 int x
, int y
, enum mode_set_atomic state
)
2252 struct drm_device
*dev
= crtc
->dev
;
2253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2255 if (dev_priv
->display
.disable_fbc
)
2256 dev_priv
->display
.disable_fbc(dev
);
2257 intel_increase_pllclock(crtc
);
2259 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2262 void intel_display_handle_reset(struct drm_device
*dev
)
2264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2265 struct drm_crtc
*crtc
;
2268 * Flips in the rings have been nuked by the reset,
2269 * so complete all pending flips so that user space
2270 * will get its events and not get stuck.
2272 * Also update the base address of all primary
2273 * planes to the the last fb to make sure we're
2274 * showing the correct fb after a reset.
2276 * Need to make two loops over the crtcs so that we
2277 * don't try to grab a crtc mutex before the
2278 * pending_flip_queue really got woken up.
2281 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2282 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2283 enum plane plane
= intel_crtc
->plane
;
2285 intel_prepare_page_flip(dev
, plane
);
2286 intel_finish_page_flip_plane(dev
, plane
);
2289 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2290 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2292 mutex_lock(&crtc
->mutex
);
2293 if (intel_crtc
->active
)
2294 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2296 mutex_unlock(&crtc
->mutex
);
2301 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2303 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2304 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2305 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2308 /* Big Hammer, we also need to ensure that any pending
2309 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2310 * current scanout is retired before unpinning the old
2313 * This should only fail upon a hung GPU, in which case we
2314 * can safely continue.
2316 dev_priv
->mm
.interruptible
= false;
2317 ret
= i915_gem_object_finish_gpu(obj
);
2318 dev_priv
->mm
.interruptible
= was_interruptible
;
2323 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2325 struct drm_device
*dev
= crtc
->dev
;
2326 struct drm_i915_master_private
*master_priv
;
2327 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2329 if (!dev
->primary
->master
)
2332 master_priv
= dev
->primary
->master
->driver_priv
;
2333 if (!master_priv
->sarea_priv
)
2336 switch (intel_crtc
->pipe
) {
2338 master_priv
->sarea_priv
->pipeA_x
= x
;
2339 master_priv
->sarea_priv
->pipeA_y
= y
;
2342 master_priv
->sarea_priv
->pipeB_x
= x
;
2343 master_priv
->sarea_priv
->pipeB_y
= y
;
2351 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2352 struct drm_framebuffer
*fb
)
2354 struct drm_device
*dev
= crtc
->dev
;
2355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2356 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2357 struct drm_framebuffer
*old_fb
;
2362 DRM_ERROR("No FB bound\n");
2366 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2367 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2369 INTEL_INFO(dev
)->num_pipes
);
2373 mutex_lock(&dev
->struct_mutex
);
2374 ret
= intel_pin_and_fence_fb_obj(dev
,
2375 to_intel_framebuffer(fb
)->obj
,
2378 mutex_unlock(&dev
->struct_mutex
);
2379 DRM_ERROR("pin & fence failed\n");
2383 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2385 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2386 mutex_unlock(&dev
->struct_mutex
);
2387 DRM_ERROR("failed to update base address\n");
2397 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2398 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2401 intel_update_fbc(dev
);
2402 mutex_unlock(&dev
->struct_mutex
);
2404 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2409 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2411 struct drm_device
*dev
= crtc
->dev
;
2412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2414 int pipe
= intel_crtc
->pipe
;
2417 /* enable normal train */
2418 reg
= FDI_TX_CTL(pipe
);
2419 temp
= I915_READ(reg
);
2420 if (IS_IVYBRIDGE(dev
)) {
2421 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2422 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2424 temp
&= ~FDI_LINK_TRAIN_NONE
;
2425 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2427 I915_WRITE(reg
, temp
);
2429 reg
= FDI_RX_CTL(pipe
);
2430 temp
= I915_READ(reg
);
2431 if (HAS_PCH_CPT(dev
)) {
2432 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2433 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2435 temp
&= ~FDI_LINK_TRAIN_NONE
;
2436 temp
|= FDI_LINK_TRAIN_NONE
;
2438 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2440 /* wait one idle pattern time */
2444 /* IVB wants error correction enabled */
2445 if (IS_IVYBRIDGE(dev
))
2446 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2447 FDI_FE_ERRC_ENABLE
);
2450 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2453 struct intel_crtc
*pipe_B_crtc
=
2454 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2455 struct intel_crtc
*pipe_C_crtc
=
2456 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2459 /* When everything is off disable fdi C so that we could enable fdi B
2460 * with all lanes. XXX: This misses the case where a pipe is not using
2461 * any pch resources and so doesn't need any fdi lanes. */
2462 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2463 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2464 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2466 temp
= I915_READ(SOUTH_CHICKEN1
);
2467 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2468 DRM_DEBUG_KMS("disabling fdi C rx\n");
2469 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2473 /* The FDI link training functions for ILK/Ibexpeak. */
2474 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2476 struct drm_device
*dev
= crtc
->dev
;
2477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2479 int pipe
= intel_crtc
->pipe
;
2480 int plane
= intel_crtc
->plane
;
2481 u32 reg
, temp
, tries
;
2483 /* FDI needs bits from pipe & plane first */
2484 assert_pipe_enabled(dev_priv
, pipe
);
2485 assert_plane_enabled(dev_priv
, plane
);
2487 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2489 reg
= FDI_RX_IMR(pipe
);
2490 temp
= I915_READ(reg
);
2491 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2492 temp
&= ~FDI_RX_BIT_LOCK
;
2493 I915_WRITE(reg
, temp
);
2497 /* enable CPU FDI TX and PCH FDI RX */
2498 reg
= FDI_TX_CTL(pipe
);
2499 temp
= I915_READ(reg
);
2501 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2502 temp
&= ~FDI_LINK_TRAIN_NONE
;
2503 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2504 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2506 reg
= FDI_RX_CTL(pipe
);
2507 temp
= I915_READ(reg
);
2508 temp
&= ~FDI_LINK_TRAIN_NONE
;
2509 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2510 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2515 /* Ironlake workaround, enable clock pointer after FDI enable*/
2516 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2517 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2518 FDI_RX_PHASE_SYNC_POINTER_EN
);
2520 reg
= FDI_RX_IIR(pipe
);
2521 for (tries
= 0; tries
< 5; tries
++) {
2522 temp
= I915_READ(reg
);
2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2525 if ((temp
& FDI_RX_BIT_LOCK
)) {
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
2527 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2532 DRM_ERROR("FDI train 1 fail!\n");
2535 reg
= FDI_TX_CTL(pipe
);
2536 temp
= I915_READ(reg
);
2537 temp
&= ~FDI_LINK_TRAIN_NONE
;
2538 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2539 I915_WRITE(reg
, temp
);
2541 reg
= FDI_RX_CTL(pipe
);
2542 temp
= I915_READ(reg
);
2543 temp
&= ~FDI_LINK_TRAIN_NONE
;
2544 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2545 I915_WRITE(reg
, temp
);
2550 reg
= FDI_RX_IIR(pipe
);
2551 for (tries
= 0; tries
< 5; tries
++) {
2552 temp
= I915_READ(reg
);
2553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2555 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2556 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2562 DRM_ERROR("FDI train 2 fail!\n");
2564 DRM_DEBUG_KMS("FDI train done\n");
2568 static const int snb_b_fdi_train_param
[] = {
2569 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2570 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2571 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2572 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2575 /* The FDI link training functions for SNB/Cougarpoint. */
2576 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2578 struct drm_device
*dev
= crtc
->dev
;
2579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2580 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2581 int pipe
= intel_crtc
->pipe
;
2582 u32 reg
, temp
, i
, retry
;
2584 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2586 reg
= FDI_RX_IMR(pipe
);
2587 temp
= I915_READ(reg
);
2588 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2589 temp
&= ~FDI_RX_BIT_LOCK
;
2590 I915_WRITE(reg
, temp
);
2595 /* enable CPU FDI TX and PCH FDI RX */
2596 reg
= FDI_TX_CTL(pipe
);
2597 temp
= I915_READ(reg
);
2599 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2600 temp
&= ~FDI_LINK_TRAIN_NONE
;
2601 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2602 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2604 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2605 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2607 I915_WRITE(FDI_RX_MISC(pipe
),
2608 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2610 reg
= FDI_RX_CTL(pipe
);
2611 temp
= I915_READ(reg
);
2612 if (HAS_PCH_CPT(dev
)) {
2613 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2614 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2616 temp
&= ~FDI_LINK_TRAIN_NONE
;
2617 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2619 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2624 for (i
= 0; i
< 4; i
++) {
2625 reg
= FDI_TX_CTL(pipe
);
2626 temp
= I915_READ(reg
);
2627 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2628 temp
|= snb_b_fdi_train_param
[i
];
2629 I915_WRITE(reg
, temp
);
2634 for (retry
= 0; retry
< 5; retry
++) {
2635 reg
= FDI_RX_IIR(pipe
);
2636 temp
= I915_READ(reg
);
2637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2638 if (temp
& FDI_RX_BIT_LOCK
) {
2639 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2640 DRM_DEBUG_KMS("FDI train 1 done.\n");
2649 DRM_ERROR("FDI train 1 fail!\n");
2652 reg
= FDI_TX_CTL(pipe
);
2653 temp
= I915_READ(reg
);
2654 temp
&= ~FDI_LINK_TRAIN_NONE
;
2655 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2657 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2659 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2661 I915_WRITE(reg
, temp
);
2663 reg
= FDI_RX_CTL(pipe
);
2664 temp
= I915_READ(reg
);
2665 if (HAS_PCH_CPT(dev
)) {
2666 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2667 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2669 temp
&= ~FDI_LINK_TRAIN_NONE
;
2670 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2672 I915_WRITE(reg
, temp
);
2677 for (i
= 0; i
< 4; i
++) {
2678 reg
= FDI_TX_CTL(pipe
);
2679 temp
= I915_READ(reg
);
2680 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2681 temp
|= snb_b_fdi_train_param
[i
];
2682 I915_WRITE(reg
, temp
);
2687 for (retry
= 0; retry
< 5; retry
++) {
2688 reg
= FDI_RX_IIR(pipe
);
2689 temp
= I915_READ(reg
);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2691 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2692 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2693 DRM_DEBUG_KMS("FDI train 2 done.\n");
2702 DRM_ERROR("FDI train 2 fail!\n");
2704 DRM_DEBUG_KMS("FDI train done.\n");
2707 /* Manual link training for Ivy Bridge A0 parts */
2708 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2710 struct drm_device
*dev
= crtc
->dev
;
2711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2712 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2713 int pipe
= intel_crtc
->pipe
;
2716 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2718 reg
= FDI_RX_IMR(pipe
);
2719 temp
= I915_READ(reg
);
2720 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2721 temp
&= ~FDI_RX_BIT_LOCK
;
2722 I915_WRITE(reg
, temp
);
2727 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2728 I915_READ(FDI_RX_IIR(pipe
)));
2730 /* enable CPU FDI TX and PCH FDI RX */
2731 reg
= FDI_TX_CTL(pipe
);
2732 temp
= I915_READ(reg
);
2734 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2735 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2736 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2737 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2738 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2739 temp
|= FDI_COMPOSITE_SYNC
;
2740 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2742 I915_WRITE(FDI_RX_MISC(pipe
),
2743 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2745 reg
= FDI_RX_CTL(pipe
);
2746 temp
= I915_READ(reg
);
2747 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2748 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2749 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2750 temp
|= FDI_COMPOSITE_SYNC
;
2751 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2756 for (i
= 0; i
< 4; i
++) {
2757 reg
= FDI_TX_CTL(pipe
);
2758 temp
= I915_READ(reg
);
2759 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2760 temp
|= snb_b_fdi_train_param
[i
];
2761 I915_WRITE(reg
, temp
);
2766 reg
= FDI_RX_IIR(pipe
);
2767 temp
= I915_READ(reg
);
2768 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2770 if (temp
& FDI_RX_BIT_LOCK
||
2771 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2772 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2773 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2778 DRM_ERROR("FDI train 1 fail!\n");
2781 reg
= FDI_TX_CTL(pipe
);
2782 temp
= I915_READ(reg
);
2783 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2784 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2785 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2786 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2787 I915_WRITE(reg
, temp
);
2789 reg
= FDI_RX_CTL(pipe
);
2790 temp
= I915_READ(reg
);
2791 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2792 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2793 I915_WRITE(reg
, temp
);
2798 for (i
= 0; i
< 4; i
++) {
2799 reg
= FDI_TX_CTL(pipe
);
2800 temp
= I915_READ(reg
);
2801 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2802 temp
|= snb_b_fdi_train_param
[i
];
2803 I915_WRITE(reg
, temp
);
2808 reg
= FDI_RX_IIR(pipe
);
2809 temp
= I915_READ(reg
);
2810 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2812 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2813 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2814 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2819 DRM_ERROR("FDI train 2 fail!\n");
2821 DRM_DEBUG_KMS("FDI train done.\n");
2824 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2826 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2828 int pipe
= intel_crtc
->pipe
;
2832 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2833 reg
= FDI_RX_CTL(pipe
);
2834 temp
= I915_READ(reg
);
2835 temp
&= ~((0x7 << 19) | (0x7 << 16));
2836 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2837 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2838 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2843 /* Switch from Rawclk to PCDclk */
2844 temp
= I915_READ(reg
);
2845 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2850 /* Enable CPU FDI TX PLL, always on for Ironlake */
2851 reg
= FDI_TX_CTL(pipe
);
2852 temp
= I915_READ(reg
);
2853 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2854 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2861 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2863 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2865 int pipe
= intel_crtc
->pipe
;
2868 /* Switch from PCDclk to Rawclk */
2869 reg
= FDI_RX_CTL(pipe
);
2870 temp
= I915_READ(reg
);
2871 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2873 /* Disable CPU FDI TX PLL */
2874 reg
= FDI_TX_CTL(pipe
);
2875 temp
= I915_READ(reg
);
2876 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2881 reg
= FDI_RX_CTL(pipe
);
2882 temp
= I915_READ(reg
);
2883 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2885 /* Wait for the clocks to turn off. */
2890 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2892 struct drm_device
*dev
= crtc
->dev
;
2893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2894 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2895 int pipe
= intel_crtc
->pipe
;
2898 /* disable CPU FDI tx and PCH FDI rx */
2899 reg
= FDI_TX_CTL(pipe
);
2900 temp
= I915_READ(reg
);
2901 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2904 reg
= FDI_RX_CTL(pipe
);
2905 temp
= I915_READ(reg
);
2906 temp
&= ~(0x7 << 16);
2907 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2908 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2913 /* Ironlake workaround, disable clock pointer after downing FDI */
2914 if (HAS_PCH_IBX(dev
)) {
2915 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2918 /* still set train pattern 1 */
2919 reg
= FDI_TX_CTL(pipe
);
2920 temp
= I915_READ(reg
);
2921 temp
&= ~FDI_LINK_TRAIN_NONE
;
2922 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2923 I915_WRITE(reg
, temp
);
2925 reg
= FDI_RX_CTL(pipe
);
2926 temp
= I915_READ(reg
);
2927 if (HAS_PCH_CPT(dev
)) {
2928 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2929 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2931 temp
&= ~FDI_LINK_TRAIN_NONE
;
2932 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2934 /* BPC in FDI rx is consistent with that in PIPECONF */
2935 temp
&= ~(0x07 << 16);
2936 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2937 I915_WRITE(reg
, temp
);
2943 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2945 struct drm_device
*dev
= crtc
->dev
;
2946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2948 unsigned long flags
;
2951 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2952 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2955 spin_lock_irqsave(&dev
->event_lock
, flags
);
2956 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2957 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2962 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2964 struct drm_device
*dev
= crtc
->dev
;
2965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2967 if (crtc
->fb
== NULL
)
2970 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2972 wait_event(dev_priv
->pending_flip_queue
,
2973 !intel_crtc_has_pending_flip(crtc
));
2975 mutex_lock(&dev
->struct_mutex
);
2976 intel_finish_fb(crtc
->fb
);
2977 mutex_unlock(&dev
->struct_mutex
);
2980 static bool haswell_crtc_driving_pch(struct drm_crtc
*crtc
)
2982 return intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
);
2985 /* Program iCLKIP clock to the desired frequency */
2986 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2988 struct drm_device
*dev
= crtc
->dev
;
2989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2990 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2993 mutex_lock(&dev_priv
->dpio_lock
);
2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2998 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3002 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (crtc
->mode
.clock
== 20000) {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the crtc->mode.clock in in KHz. To get the divisors,
3014 * it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3018 u32 iclk_virtual_root_freq
= 172800 * 1000;
3019 u32 iclk_pi_range
= 64;
3020 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3022 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
3023 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3024 pi_value
= desired_divisor
% iclk_pi_range
;
3027 divsel
= msb_divisor_value
- 2;
3028 phaseinc
= pi_value
;
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3044 /* Program SSCDIVINTPHASE6 */
3045 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3046 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3047 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3048 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3049 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3050 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3051 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3052 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3054 /* Program SSCAUXDIV */
3055 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3056 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3058 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3060 /* Enable modulator and associated divider */
3061 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3062 temp
&= ~SBI_SSCCTL_DISABLE
;
3063 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3065 /* Wait for initialization time */
3068 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3070 mutex_unlock(&dev_priv
->dpio_lock
);
3074 * Enable PCH resources required for PCH ports:
3076 * - FDI training & RX/TX
3077 * - update transcoder timings
3078 * - DP transcoding bits
3081 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3083 struct drm_device
*dev
= crtc
->dev
;
3084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3085 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3086 int pipe
= intel_crtc
->pipe
;
3089 assert_transcoder_disabled(dev_priv
, pipe
);
3091 /* Write the TU size bits before fdi link training, so that error
3092 * detection works. */
3093 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3094 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3096 /* For PCH output, training FDI link */
3097 dev_priv
->display
.fdi_link_train(crtc
);
3099 /* XXX: pch pll's can be enabled any time before we enable the PCH
3100 * transcoder, and we actually should do this to not upset any PCH
3101 * transcoder that already use the clock when we share it.
3103 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3104 * unconditionally resets the pll - we need that to have the right LVDS
3105 * enable sequence. */
3106 ironlake_enable_pch_pll(intel_crtc
);
3108 if (HAS_PCH_CPT(dev
)) {
3111 temp
= I915_READ(PCH_DPLL_SEL
);
3115 temp
|= TRANSA_DPLL_ENABLE
;
3116 sel
= TRANSA_DPLLB_SEL
;
3119 temp
|= TRANSB_DPLL_ENABLE
;
3120 sel
= TRANSB_DPLLB_SEL
;
3123 temp
|= TRANSC_DPLL_ENABLE
;
3124 sel
= TRANSC_DPLLB_SEL
;
3127 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3131 I915_WRITE(PCH_DPLL_SEL
, temp
);
3134 /* set transcoder timing, panel must allow it */
3135 assert_panel_unlocked(dev_priv
, pipe
);
3136 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3137 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3138 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3140 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3141 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3142 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3143 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3145 intel_fdi_normal_train(crtc
);
3147 /* For PCH DP, enable TRANS_DP_CTL */
3148 if (HAS_PCH_CPT(dev
) &&
3149 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3150 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3151 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3152 reg
= TRANS_DP_CTL(pipe
);
3153 temp
= I915_READ(reg
);
3154 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3155 TRANS_DP_SYNC_MASK
|
3157 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3158 TRANS_DP_ENH_FRAMING
);
3159 temp
|= bpc
<< 9; /* same format but at 11:9 */
3161 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3162 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3163 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3164 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3166 switch (intel_trans_dp_port_sel(crtc
)) {
3168 temp
|= TRANS_DP_PORT_SEL_B
;
3171 temp
|= TRANS_DP_PORT_SEL_C
;
3174 temp
|= TRANS_DP_PORT_SEL_D
;
3180 I915_WRITE(reg
, temp
);
3183 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3186 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3188 struct drm_device
*dev
= crtc
->dev
;
3189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3190 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3191 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3193 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3195 lpt_program_iclkip(crtc
);
3197 /* Set transcoder timing. */
3198 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3199 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3200 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3202 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3203 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3204 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3205 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3207 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3210 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3212 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3217 if (pll
->refcount
== 0) {
3218 WARN(1, "bad PCH PLL refcount\n");
3223 intel_crtc
->pch_pll
= NULL
;
3226 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3228 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3229 struct intel_pch_pll
*pll
;
3232 pll
= intel_crtc
->pch_pll
;
3234 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3235 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3239 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3240 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3241 i
= intel_crtc
->pipe
;
3242 pll
= &dev_priv
->pch_plls
[i
];
3244 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3245 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3250 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3251 pll
= &dev_priv
->pch_plls
[i
];
3253 /* Only want to check enabled timings first */
3254 if (pll
->refcount
== 0)
3257 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3258 fp
== I915_READ(pll
->fp0_reg
)) {
3259 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3260 intel_crtc
->base
.base
.id
,
3261 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3267 /* Ok no matching timings, maybe there's a free one? */
3268 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3269 pll
= &dev_priv
->pch_plls
[i
];
3270 if (pll
->refcount
== 0) {
3271 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3272 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3280 intel_crtc
->pch_pll
= pll
;
3282 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3283 prepare
: /* separate function? */
3284 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3286 /* Wait for the clocks to stabilize before rewriting the regs */
3287 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3288 POSTING_READ(pll
->pll_reg
);
3291 I915_WRITE(pll
->fp0_reg
, fp
);
3292 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3297 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3300 int dslreg
= PIPEDSL(pipe
);
3303 temp
= I915_READ(dslreg
);
3305 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3306 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3307 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3311 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3313 struct drm_device
*dev
= crtc
->dev
;
3314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3315 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3316 struct intel_encoder
*encoder
;
3317 int pipe
= intel_crtc
->pipe
;
3318 int plane
= intel_crtc
->plane
;
3321 WARN_ON(!crtc
->enabled
);
3323 if (intel_crtc
->active
)
3326 intel_crtc
->active
= true;
3327 intel_update_watermarks(dev
);
3329 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3330 temp
= I915_READ(PCH_LVDS
);
3331 if ((temp
& LVDS_PORT_EN
) == 0)
3332 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3336 if (intel_crtc
->config
.has_pch_encoder
) {
3337 /* Note: FDI PLL enabling _must_ be done before we enable the
3338 * cpu pipes, hence this is separate from all the other fdi/pch
3340 ironlake_fdi_pll_enable(intel_crtc
);
3342 assert_fdi_tx_disabled(dev_priv
, pipe
);
3343 assert_fdi_rx_disabled(dev_priv
, pipe
);
3346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3347 if (encoder
->pre_enable
)
3348 encoder
->pre_enable(encoder
);
3350 /* Enable panel fitting for LVDS */
3351 if (dev_priv
->pch_pf_size
&&
3352 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3353 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3354 /* Force use of hard-coded filter coefficients
3355 * as some pre-programmed values are broken,
3358 if (IS_IVYBRIDGE(dev
))
3359 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3360 PF_PIPE_SEL_IVB(pipe
));
3362 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3363 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3364 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3371 intel_crtc_load_lut(crtc
);
3373 intel_enable_pipe(dev_priv
, pipe
,
3374 intel_crtc
->config
.has_pch_encoder
);
3375 intel_enable_plane(dev_priv
, plane
, pipe
);
3377 if (intel_crtc
->config
.has_pch_encoder
)
3378 ironlake_pch_enable(crtc
);
3380 mutex_lock(&dev
->struct_mutex
);
3381 intel_update_fbc(dev
);
3382 mutex_unlock(&dev
->struct_mutex
);
3384 intel_crtc_update_cursor(crtc
, true);
3386 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3387 encoder
->enable(encoder
);
3389 if (HAS_PCH_CPT(dev
))
3390 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3393 * There seems to be a race in PCH platform hw (at least on some
3394 * outputs) where an enabled pipe still completes any pageflip right
3395 * away (as if the pipe is off) instead of waiting for vblank. As soon
3396 * as the first vblank happend, everything works as expected. Hence just
3397 * wait for one vblank before returning to avoid strange things
3400 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3403 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3405 struct drm_device
*dev
= crtc
->dev
;
3406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3407 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3408 struct intel_encoder
*encoder
;
3409 int pipe
= intel_crtc
->pipe
;
3410 int plane
= intel_crtc
->plane
;
3412 WARN_ON(!crtc
->enabled
);
3414 if (intel_crtc
->active
)
3417 intel_crtc
->active
= true;
3418 intel_update_watermarks(dev
);
3420 if (intel_crtc
->config
.has_pch_encoder
)
3421 dev_priv
->display
.fdi_link_train(crtc
);
3423 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3424 if (encoder
->pre_enable
)
3425 encoder
->pre_enable(encoder
);
3427 intel_ddi_enable_pipe_clock(intel_crtc
);
3429 /* Enable panel fitting for eDP */
3430 if (dev_priv
->pch_pf_size
&&
3431 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3432 /* Force use of hard-coded filter coefficients
3433 * as some pre-programmed values are broken,
3436 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3437 PF_PIPE_SEL_IVB(pipe
));
3438 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3439 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3443 * On ILK+ LUT must be loaded before the pipe is running but with
3446 intel_crtc_load_lut(crtc
);
3448 intel_ddi_set_pipe_settings(crtc
);
3449 intel_ddi_enable_transcoder_func(crtc
);
3451 intel_enable_pipe(dev_priv
, pipe
,
3452 intel_crtc
->config
.has_pch_encoder
);
3453 intel_enable_plane(dev_priv
, plane
, pipe
);
3455 if (intel_crtc
->config
.has_pch_encoder
)
3456 lpt_pch_enable(crtc
);
3458 mutex_lock(&dev
->struct_mutex
);
3459 intel_update_fbc(dev
);
3460 mutex_unlock(&dev
->struct_mutex
);
3462 intel_crtc_update_cursor(crtc
, true);
3464 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3465 encoder
->enable(encoder
);
3468 * There seems to be a race in PCH platform hw (at least on some
3469 * outputs) where an enabled pipe still completes any pageflip right
3470 * away (as if the pipe is off) instead of waiting for vblank. As soon
3471 * as the first vblank happend, everything works as expected. Hence just
3472 * wait for one vblank before returning to avoid strange things
3475 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3478 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3480 struct drm_device
*dev
= crtc
->dev
;
3481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3482 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3483 struct intel_encoder
*encoder
;
3484 int pipe
= intel_crtc
->pipe
;
3485 int plane
= intel_crtc
->plane
;
3489 if (!intel_crtc
->active
)
3492 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3493 encoder
->disable(encoder
);
3495 intel_crtc_wait_for_pending_flips(crtc
);
3496 drm_vblank_off(dev
, pipe
);
3497 intel_crtc_update_cursor(crtc
, false);
3499 intel_disable_plane(dev_priv
, plane
, pipe
);
3501 if (dev_priv
->cfb_plane
== plane
)
3502 intel_disable_fbc(dev
);
3504 intel_disable_pipe(dev_priv
, pipe
);
3507 I915_WRITE(PF_CTL(pipe
), 0);
3508 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3510 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3511 if (encoder
->post_disable
)
3512 encoder
->post_disable(encoder
);
3514 ironlake_fdi_disable(crtc
);
3516 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3518 if (HAS_PCH_CPT(dev
)) {
3519 /* disable TRANS_DP_CTL */
3520 reg
= TRANS_DP_CTL(pipe
);
3521 temp
= I915_READ(reg
);
3522 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3523 temp
|= TRANS_DP_PORT_SEL_NONE
;
3524 I915_WRITE(reg
, temp
);
3526 /* disable DPLL_SEL */
3527 temp
= I915_READ(PCH_DPLL_SEL
);
3530 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3533 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3536 /* C shares PLL A or B */
3537 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3542 I915_WRITE(PCH_DPLL_SEL
, temp
);
3545 /* disable PCH DPLL */
3546 intel_disable_pch_pll(intel_crtc
);
3548 ironlake_fdi_pll_disable(intel_crtc
);
3550 intel_crtc
->active
= false;
3551 intel_update_watermarks(dev
);
3553 mutex_lock(&dev
->struct_mutex
);
3554 intel_update_fbc(dev
);
3555 mutex_unlock(&dev
->struct_mutex
);
3558 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3560 struct drm_device
*dev
= crtc
->dev
;
3561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3562 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3563 struct intel_encoder
*encoder
;
3564 int pipe
= intel_crtc
->pipe
;
3565 int plane
= intel_crtc
->plane
;
3566 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3569 if (!intel_crtc
->active
)
3572 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3574 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3575 encoder
->disable(encoder
);
3577 intel_crtc_wait_for_pending_flips(crtc
);
3578 drm_vblank_off(dev
, pipe
);
3579 intel_crtc_update_cursor(crtc
, false);
3581 intel_disable_plane(dev_priv
, plane
, pipe
);
3583 if (dev_priv
->cfb_plane
== plane
)
3584 intel_disable_fbc(dev
);
3586 intel_disable_pipe(dev_priv
, pipe
);
3588 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3591 I915_WRITE(PF_CTL(pipe
), 0);
3592 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3594 intel_ddi_disable_pipe_clock(intel_crtc
);
3596 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3597 if (encoder
->post_disable
)
3598 encoder
->post_disable(encoder
);
3601 lpt_disable_pch_transcoder(dev_priv
);
3602 intel_ddi_fdi_disable(crtc
);
3605 intel_crtc
->active
= false;
3606 intel_update_watermarks(dev
);
3608 mutex_lock(&dev
->struct_mutex
);
3609 intel_update_fbc(dev
);
3610 mutex_unlock(&dev
->struct_mutex
);
3613 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3615 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3616 intel_put_pch_pll(intel_crtc
);
3619 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3621 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3623 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3624 * start using it. */
3625 intel_crtc
->cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3627 intel_ddi_put_crtc_pll(crtc
);
3630 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3632 if (!enable
&& intel_crtc
->overlay
) {
3633 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3636 mutex_lock(&dev
->struct_mutex
);
3637 dev_priv
->mm
.interruptible
= false;
3638 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3639 dev_priv
->mm
.interruptible
= true;
3640 mutex_unlock(&dev
->struct_mutex
);
3643 /* Let userspace switch the overlay on again. In most cases userspace
3644 * has to recompute where to put it anyway.
3649 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3650 * cursor plane briefly if not already running after enabling the display
3652 * This workaround avoids occasional blank screens when self refresh is
3656 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3658 u32 cntl
= I915_READ(CURCNTR(pipe
));
3660 if ((cntl
& CURSOR_MODE
) == 0) {
3661 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3663 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3664 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3665 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3666 I915_WRITE(CURCNTR(pipe
), cntl
);
3667 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3668 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3672 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3674 struct drm_device
*dev
= crtc
->dev
;
3675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3676 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3677 struct intel_encoder
*encoder
;
3678 int pipe
= intel_crtc
->pipe
;
3679 int plane
= intel_crtc
->plane
;
3681 WARN_ON(!crtc
->enabled
);
3683 if (intel_crtc
->active
)
3686 intel_crtc
->active
= true;
3687 intel_update_watermarks(dev
);
3689 intel_enable_pll(dev_priv
, pipe
);
3691 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3692 if (encoder
->pre_enable
)
3693 encoder
->pre_enable(encoder
);
3695 intel_enable_pipe(dev_priv
, pipe
, false);
3696 intel_enable_plane(dev_priv
, plane
, pipe
);
3698 g4x_fixup_plane(dev_priv
, pipe
);
3700 intel_crtc_load_lut(crtc
);
3701 intel_update_fbc(dev
);
3703 /* Give the overlay scaler a chance to enable if it's on this pipe */
3704 intel_crtc_dpms_overlay(intel_crtc
, true);
3705 intel_crtc_update_cursor(crtc
, true);
3707 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3708 encoder
->enable(encoder
);
3711 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3713 struct drm_device
*dev
= crtc
->dev
;
3714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3715 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3716 struct intel_encoder
*encoder
;
3717 int pipe
= intel_crtc
->pipe
;
3718 int plane
= intel_crtc
->plane
;
3722 if (!intel_crtc
->active
)
3725 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3726 encoder
->disable(encoder
);
3728 /* Give the overlay scaler a chance to disable if it's on this pipe */
3729 intel_crtc_wait_for_pending_flips(crtc
);
3730 drm_vblank_off(dev
, pipe
);
3731 intel_crtc_dpms_overlay(intel_crtc
, false);
3732 intel_crtc_update_cursor(crtc
, false);
3734 if (dev_priv
->cfb_plane
== plane
)
3735 intel_disable_fbc(dev
);
3737 intel_disable_plane(dev_priv
, plane
, pipe
);
3738 intel_disable_pipe(dev_priv
, pipe
);
3740 /* Disable pannel fitter if it is on this pipe. */
3741 pctl
= I915_READ(PFIT_CONTROL
);
3742 if ((pctl
& PFIT_ENABLE
) &&
3743 ((pctl
& PFIT_PIPE_MASK
) >> PFIT_PIPE_SHIFT
) == pipe
)
3744 I915_WRITE(PFIT_CONTROL
, 0);
3746 intel_disable_pll(dev_priv
, pipe
);
3748 intel_crtc
->active
= false;
3749 intel_update_fbc(dev
);
3750 intel_update_watermarks(dev
);
3753 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3757 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3760 struct drm_device
*dev
= crtc
->dev
;
3761 struct drm_i915_master_private
*master_priv
;
3762 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3763 int pipe
= intel_crtc
->pipe
;
3765 if (!dev
->primary
->master
)
3768 master_priv
= dev
->primary
->master
->driver_priv
;
3769 if (!master_priv
->sarea_priv
)
3774 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3775 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3778 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3779 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3782 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3788 * Sets the power management mode of the pipe and plane.
3790 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3792 struct drm_device
*dev
= crtc
->dev
;
3793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3794 struct intel_encoder
*intel_encoder
;
3795 bool enable
= false;
3797 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3798 enable
|= intel_encoder
->connectors_active
;
3801 dev_priv
->display
.crtc_enable(crtc
);
3803 dev_priv
->display
.crtc_disable(crtc
);
3805 intel_crtc_update_sarea(crtc
, enable
);
3808 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3810 struct drm_device
*dev
= crtc
->dev
;
3811 struct drm_connector
*connector
;
3812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3813 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3815 /* crtc should still be enabled when we disable it. */
3816 WARN_ON(!crtc
->enabled
);
3818 intel_crtc
->eld_vld
= false;
3819 dev_priv
->display
.crtc_disable(crtc
);
3820 intel_crtc_update_sarea(crtc
, false);
3821 dev_priv
->display
.off(crtc
);
3823 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3824 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3827 mutex_lock(&dev
->struct_mutex
);
3828 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3829 mutex_unlock(&dev
->struct_mutex
);
3833 /* Update computed state. */
3834 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3835 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3838 if (connector
->encoder
->crtc
!= crtc
)
3841 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3842 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3846 void intel_modeset_disable(struct drm_device
*dev
)
3848 struct drm_crtc
*crtc
;
3850 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3852 intel_crtc_disable(crtc
);
3856 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3858 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3860 drm_encoder_cleanup(encoder
);
3861 kfree(intel_encoder
);
3864 /* Simple dpms helper for encodres with just one connector, no cloning and only
3865 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866 * state of the entire output pipe. */
3867 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3869 if (mode
== DRM_MODE_DPMS_ON
) {
3870 encoder
->connectors_active
= true;
3872 intel_crtc_update_dpms(encoder
->base
.crtc
);
3874 encoder
->connectors_active
= false;
3876 intel_crtc_update_dpms(encoder
->base
.crtc
);
3880 /* Cross check the actual hw state with our own modeset state tracking (and it's
3881 * internal consistency). */
3882 static void intel_connector_check_state(struct intel_connector
*connector
)
3884 if (connector
->get_hw_state(connector
)) {
3885 struct intel_encoder
*encoder
= connector
->encoder
;
3886 struct drm_crtc
*crtc
;
3887 bool encoder_enabled
;
3890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891 connector
->base
.base
.id
,
3892 drm_get_connector_name(&connector
->base
));
3894 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3895 "wrong connector dpms state\n");
3896 WARN(connector
->base
.encoder
!= &encoder
->base
,
3897 "active connector not linked to encoder\n");
3898 WARN(!encoder
->connectors_active
,
3899 "encoder->connectors_active not set\n");
3901 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3902 WARN(!encoder_enabled
, "encoder not enabled\n");
3903 if (WARN_ON(!encoder
->base
.crtc
))
3906 crtc
= encoder
->base
.crtc
;
3908 WARN(!crtc
->enabled
, "crtc not enabled\n");
3909 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3910 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3911 "encoder active on the wrong pipe\n");
3915 /* Even simpler default implementation, if there's really no special case to
3917 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3919 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3921 /* All the simple cases only support two dpms states. */
3922 if (mode
!= DRM_MODE_DPMS_ON
)
3923 mode
= DRM_MODE_DPMS_OFF
;
3925 if (mode
== connector
->dpms
)
3928 connector
->dpms
= mode
;
3930 /* Only need to change hw state when actually enabled */
3931 if (encoder
->base
.crtc
)
3932 intel_encoder_dpms(encoder
, mode
);
3934 WARN_ON(encoder
->connectors_active
!= false);
3936 intel_modeset_check_state(connector
->dev
);
3939 /* Simple connector->get_hw_state implementation for encoders that support only
3940 * one connector and no cloning and hence the encoder state determines the state
3941 * of the connector. */
3942 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3945 struct intel_encoder
*encoder
= connector
->encoder
;
3947 return encoder
->get_hw_state(encoder
, &pipe
);
3950 static bool intel_crtc_compute_config(struct drm_crtc
*crtc
,
3951 struct intel_crtc_config
*pipe_config
)
3953 struct drm_device
*dev
= crtc
->dev
;
3954 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
3956 if (HAS_PCH_SPLIT(dev
)) {
3957 /* FDI link clock is fixed at 2.7G */
3958 if (pipe_config
->requested_mode
.clock
* 3
3959 > IRONLAKE_FDI_FREQ
* 4)
3963 /* All interlaced capable intel hw wants timings in frames. Note though
3964 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3965 * timings, so we need to be careful not to clobber these.*/
3966 if (!pipe_config
->timings_set
)
3967 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3969 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3970 * with a hsync front porch of 0.
3972 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3973 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3979 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3981 return 400000; /* FIXME */
3984 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3989 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3994 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3999 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4003 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4005 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4008 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4009 case GC_DISPLAY_CLOCK_333_MHZ
:
4012 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4018 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4023 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4026 /* Assume that the hardware is in the high speed state. This
4027 * should be the default.
4029 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4030 case GC_CLOCK_133_200
:
4031 case GC_CLOCK_100_200
:
4033 case GC_CLOCK_166_250
:
4035 case GC_CLOCK_100_133
:
4039 /* Shouldn't happen */
4043 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4049 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
4051 while (*num
> 0xffffff || *den
> 0xffffff) {
4058 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4059 int pixel_clock
, int link_clock
,
4060 struct intel_link_m_n
*m_n
)
4063 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
4064 m_n
->gmch_n
= link_clock
* nlanes
* 8;
4065 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
4066 m_n
->link_m
= pixel_clock
;
4067 m_n
->link_n
= link_clock
;
4068 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
4071 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4073 if (i915_panel_use_ssc
>= 0)
4074 return i915_panel_use_ssc
!= 0;
4075 return dev_priv
->lvds_use_ssc
4076 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4079 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4081 struct drm_device
*dev
= crtc
->dev
;
4082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4083 int refclk
= 27000; /* for DP & HDMI */
4085 return 100000; /* only one validated so far */
4087 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4089 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4090 if (intel_panel_use_ssc(dev_priv
))
4094 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4101 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4103 struct drm_device
*dev
= crtc
->dev
;
4104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4107 if (IS_VALLEYVIEW(dev
)) {
4108 refclk
= vlv_get_refclk(crtc
);
4109 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4110 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4111 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4112 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4114 } else if (!IS_GEN2(dev
)) {
4123 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
4124 intel_clock_t
*clock
)
4126 /* SDVO TV has fixed PLL values depend on its clock range,
4127 this mirrors vbios setting. */
4128 if (adjusted_mode
->clock
>= 100000
4129 && adjusted_mode
->clock
< 140500) {
4135 } else if (adjusted_mode
->clock
>= 140500
4136 && adjusted_mode
->clock
<= 200000) {
4145 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
4146 intel_clock_t
*clock
,
4147 intel_clock_t
*reduced_clock
)
4149 struct drm_device
*dev
= crtc
->dev
;
4150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4151 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4152 int pipe
= intel_crtc
->pipe
;
4155 if (IS_PINEVIEW(dev
)) {
4156 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4158 fp2
= (1 << reduced_clock
->n
) << 16 |
4159 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4161 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4163 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4167 I915_WRITE(FP0(pipe
), fp
);
4169 intel_crtc
->lowfreq_avail
= false;
4170 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4171 reduced_clock
&& i915_powersave
) {
4172 I915_WRITE(FP1(pipe
), fp2
);
4173 intel_crtc
->lowfreq_avail
= true;
4175 I915_WRITE(FP1(pipe
), fp
);
4179 static void vlv_update_pll(struct drm_crtc
*crtc
,
4180 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4183 struct drm_device
*dev
= crtc
->dev
;
4184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4185 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4186 struct drm_display_mode
*adjusted_mode
=
4187 &intel_crtc
->config
.adjusted_mode
;
4188 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4189 int pipe
= intel_crtc
->pipe
;
4190 u32 dpll
, mdiv
, pdiv
;
4191 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4195 mutex_lock(&dev_priv
->dpio_lock
);
4197 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4198 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4200 dpll
= DPLL_VGA_MODE_DIS
;
4201 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4202 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4203 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4205 I915_WRITE(DPLL(pipe
), dpll
);
4206 POSTING_READ(DPLL(pipe
));
4215 * In Valleyview PLL and program lane counter registers are exposed
4216 * through DPIO interface
4218 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4219 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4220 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4221 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4222 mdiv
|= (1 << DPIO_K_SHIFT
);
4223 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4224 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4226 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4228 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4229 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4230 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4231 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4232 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4234 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4236 dpll
|= DPLL_VCO_ENABLE
;
4237 I915_WRITE(DPLL(pipe
), dpll
);
4238 POSTING_READ(DPLL(pipe
));
4239 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4240 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4242 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4244 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4245 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4247 I915_WRITE(DPLL(pipe
), dpll
);
4249 /* Wait for the clocks to stabilize. */
4250 POSTING_READ(DPLL(pipe
));
4256 if (intel_crtc
->config
.pixel_multiplier
> 1) {
4257 temp
= (intel_crtc
->config
.pixel_multiplier
- 1)
4258 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4261 I915_WRITE(DPLL_MD(pipe
), temp
);
4262 POSTING_READ(DPLL_MD(pipe
));
4264 /* Now program lane control registers */
4265 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4266 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4271 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4273 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4278 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4281 mutex_unlock(&dev_priv
->dpio_lock
);
4284 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4285 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4288 struct drm_device
*dev
= crtc
->dev
;
4289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4290 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4291 struct drm_display_mode
*adjusted_mode
=
4292 &intel_crtc
->config
.adjusted_mode
;
4293 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4294 struct intel_encoder
*encoder
;
4295 int pipe
= intel_crtc
->pipe
;
4299 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4301 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4302 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4304 dpll
= DPLL_VGA_MODE_DIS
;
4306 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4307 dpll
|= DPLLB_MODE_LVDS
;
4309 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4312 if ((intel_crtc
->config
.pixel_multiplier
> 1) &&
4313 (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))) {
4314 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
4315 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4317 dpll
|= DPLL_DVO_HIGH_SPEED
;
4319 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4320 dpll
|= DPLL_DVO_HIGH_SPEED
;
4322 /* compute bitmask from p1 value */
4323 if (IS_PINEVIEW(dev
))
4324 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4326 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4327 if (IS_G4X(dev
) && reduced_clock
)
4328 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4330 switch (clock
->p2
) {
4332 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4335 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4338 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4341 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4344 if (INTEL_INFO(dev
)->gen
>= 4)
4345 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4347 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4348 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4349 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4350 /* XXX: just matching BIOS for now */
4351 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4353 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4354 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4355 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4357 dpll
|= PLL_REF_INPUT_DREFCLK
;
4359 dpll
|= DPLL_VCO_ENABLE
;
4360 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4361 POSTING_READ(DPLL(pipe
));
4364 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4365 if (encoder
->pre_pll_enable
)
4366 encoder
->pre_pll_enable(encoder
);
4368 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4369 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4371 I915_WRITE(DPLL(pipe
), dpll
);
4373 /* Wait for the clocks to stabilize. */
4374 POSTING_READ(DPLL(pipe
));
4377 if (INTEL_INFO(dev
)->gen
>= 4) {
4381 if (intel_crtc
->config
.pixel_multiplier
> 1) {
4382 temp
= (intel_crtc
->config
.pixel_multiplier
- 1)
4383 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4386 I915_WRITE(DPLL_MD(pipe
), temp
);
4388 /* The pixel multiplier can only be updated once the
4389 * DPLL is enabled and the clocks are stable.
4391 * So write it again.
4393 I915_WRITE(DPLL(pipe
), dpll
);
4397 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4398 struct drm_display_mode
*adjusted_mode
,
4399 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4402 struct drm_device
*dev
= crtc
->dev
;
4403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4404 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4405 struct intel_encoder
*encoder
;
4406 int pipe
= intel_crtc
->pipe
;
4409 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4411 dpll
= DPLL_VGA_MODE_DIS
;
4413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4414 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4417 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4419 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4421 dpll
|= PLL_P2_DIVIDE_BY_4
;
4424 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4425 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4426 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4428 dpll
|= PLL_REF_INPUT_DREFCLK
;
4430 dpll
|= DPLL_VCO_ENABLE
;
4431 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4432 POSTING_READ(DPLL(pipe
));
4435 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4436 if (encoder
->pre_pll_enable
)
4437 encoder
->pre_pll_enable(encoder
);
4439 I915_WRITE(DPLL(pipe
), dpll
);
4441 /* Wait for the clocks to stabilize. */
4442 POSTING_READ(DPLL(pipe
));
4445 /* The pixel multiplier can only be updated once the
4446 * DPLL is enabled and the clocks are stable.
4448 * So write it again.
4450 I915_WRITE(DPLL(pipe
), dpll
);
4453 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4454 struct drm_display_mode
*mode
,
4455 struct drm_display_mode
*adjusted_mode
)
4457 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4459 enum pipe pipe
= intel_crtc
->pipe
;
4460 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4461 uint32_t vsyncshift
;
4463 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4464 /* the chip adds 2 halflines automatically */
4465 adjusted_mode
->crtc_vtotal
-= 1;
4466 adjusted_mode
->crtc_vblank_end
-= 1;
4467 vsyncshift
= adjusted_mode
->crtc_hsync_start
4468 - adjusted_mode
->crtc_htotal
/ 2;
4473 if (INTEL_INFO(dev
)->gen
> 3)
4474 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4476 I915_WRITE(HTOTAL(cpu_transcoder
),
4477 (adjusted_mode
->crtc_hdisplay
- 1) |
4478 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4479 I915_WRITE(HBLANK(cpu_transcoder
),
4480 (adjusted_mode
->crtc_hblank_start
- 1) |
4481 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4482 I915_WRITE(HSYNC(cpu_transcoder
),
4483 (adjusted_mode
->crtc_hsync_start
- 1) |
4484 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4486 I915_WRITE(VTOTAL(cpu_transcoder
),
4487 (adjusted_mode
->crtc_vdisplay
- 1) |
4488 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4489 I915_WRITE(VBLANK(cpu_transcoder
),
4490 (adjusted_mode
->crtc_vblank_start
- 1) |
4491 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4492 I915_WRITE(VSYNC(cpu_transcoder
),
4493 (adjusted_mode
->crtc_vsync_start
- 1) |
4494 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4496 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4497 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4498 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4500 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4501 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4502 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4504 /* pipesrc controls the size that is scaled from, which should
4505 * always be the user's requested size.
4507 I915_WRITE(PIPESRC(pipe
),
4508 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4511 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4513 struct drm_framebuffer
*fb
)
4515 struct drm_device
*dev
= crtc
->dev
;
4516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4517 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4518 struct drm_display_mode
*adjusted_mode
=
4519 &intel_crtc
->config
.adjusted_mode
;
4520 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4521 int pipe
= intel_crtc
->pipe
;
4522 int plane
= intel_crtc
->plane
;
4523 int refclk
, num_connectors
= 0;
4524 intel_clock_t clock
, reduced_clock
;
4525 u32 dspcntr
, pipeconf
;
4526 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4527 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4528 struct intel_encoder
*encoder
;
4529 const intel_limit_t
*limit
;
4532 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4533 switch (encoder
->type
) {
4534 case INTEL_OUTPUT_LVDS
:
4537 case INTEL_OUTPUT_SDVO
:
4538 case INTEL_OUTPUT_HDMI
:
4540 if (encoder
->needs_tv_clock
)
4543 case INTEL_OUTPUT_TVOUT
:
4546 case INTEL_OUTPUT_DISPLAYPORT
:
4554 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4557 * Returns a set of divisors for the desired target clock with the given
4558 * refclk, or FALSE. The returned values represent the clock equation:
4559 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4561 limit
= intel_limit(crtc
, refclk
);
4562 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4565 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4569 /* Ensure that the cursor is valid for the new mode before changing... */
4570 intel_crtc_update_cursor(crtc
, true);
4572 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4574 * Ensure we match the reduced clock's P to the target clock.
4575 * If the clocks don't match, we can't switch the display clock
4576 * by using the FP0/FP1. In such case we will disable the LVDS
4577 * downclock feature.
4579 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4580 dev_priv
->lvds_downclock
,
4586 if (is_sdvo
&& is_tv
)
4587 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4590 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4591 has_reduced_clock
? &reduced_clock
: NULL
,
4593 else if (IS_VALLEYVIEW(dev
))
4594 vlv_update_pll(crtc
, &clock
,
4595 has_reduced_clock
? &reduced_clock
: NULL
,
4598 i9xx_update_pll(crtc
, &clock
,
4599 has_reduced_clock
? &reduced_clock
: NULL
,
4602 /* setup pipeconf */
4603 pipeconf
= I915_READ(PIPECONF(pipe
));
4605 /* Set up the display plane register */
4606 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4608 if (!IS_VALLEYVIEW(dev
)) {
4610 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4612 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4615 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4616 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4619 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4623 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4624 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4626 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4629 /* default to 8bpc */
4630 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4632 if (intel_crtc
->config
.dither
) {
4633 pipeconf
|= PIPECONF_6BPC
|
4634 PIPECONF_DITHER_EN
|
4635 PIPECONF_DITHER_TYPE_SP
;
4639 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4640 if (intel_crtc
->config
.dither
) {
4641 pipeconf
|= PIPECONF_6BPC
|
4643 I965_PIPECONF_ACTIVE
;
4647 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4648 drm_mode_debug_printmodeline(mode
);
4650 if (HAS_PIPE_CXSR(dev
)) {
4651 if (intel_crtc
->lowfreq_avail
) {
4652 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4653 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4655 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4656 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4660 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4661 if (!IS_GEN2(dev
) &&
4662 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4663 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4665 pipeconf
|= PIPECONF_PROGRESSIVE
;
4667 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4669 /* pipesrc and dspsize control the size that is scaled from,
4670 * which should always be the user's requested size.
4672 I915_WRITE(DSPSIZE(plane
),
4673 ((mode
->vdisplay
- 1) << 16) |
4674 (mode
->hdisplay
- 1));
4675 I915_WRITE(DSPPOS(plane
), 0);
4677 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4678 POSTING_READ(PIPECONF(pipe
));
4679 intel_enable_pipe(dev_priv
, pipe
, false);
4681 intel_wait_for_vblank(dev
, pipe
);
4683 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4684 POSTING_READ(DSPCNTR(plane
));
4686 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4688 intel_update_watermarks(dev
);
4693 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4696 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4697 struct intel_encoder
*encoder
;
4699 bool has_lvds
= false;
4700 bool has_cpu_edp
= false;
4701 bool has_pch_edp
= false;
4702 bool has_panel
= false;
4703 bool has_ck505
= false;
4704 bool can_ssc
= false;
4706 /* We need to take the global config into account */
4707 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4709 switch (encoder
->type
) {
4710 case INTEL_OUTPUT_LVDS
:
4714 case INTEL_OUTPUT_EDP
:
4716 if (intel_encoder_is_pch_edp(&encoder
->base
))
4724 if (HAS_PCH_IBX(dev
)) {
4725 has_ck505
= dev_priv
->display_clock_mode
;
4726 can_ssc
= has_ck505
;
4732 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4733 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4736 /* Ironlake: try to setup display ref clock before DPLL
4737 * enabling. This is only under driver's control after
4738 * PCH B stepping, previous chipset stepping should be
4739 * ignoring this setting.
4741 temp
= I915_READ(PCH_DREF_CONTROL
);
4742 /* Always enable nonspread source */
4743 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4746 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4748 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4751 temp
&= ~DREF_SSC_SOURCE_MASK
;
4752 temp
|= DREF_SSC_SOURCE_ENABLE
;
4754 /* SSC must be turned on before enabling the CPU output */
4755 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4756 DRM_DEBUG_KMS("Using SSC on panel\n");
4757 temp
|= DREF_SSC1_ENABLE
;
4759 temp
&= ~DREF_SSC1_ENABLE
;
4761 /* Get SSC going before enabling the outputs */
4762 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4763 POSTING_READ(PCH_DREF_CONTROL
);
4766 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4768 /* Enable CPU source on CPU attached eDP */
4770 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4771 DRM_DEBUG_KMS("Using SSC on eDP\n");
4772 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4775 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4777 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4779 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4780 POSTING_READ(PCH_DREF_CONTROL
);
4783 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4785 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4787 /* Turn off CPU output */
4788 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4790 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4791 POSTING_READ(PCH_DREF_CONTROL
);
4794 /* Turn off the SSC source */
4795 temp
&= ~DREF_SSC_SOURCE_MASK
;
4796 temp
|= DREF_SSC_SOURCE_DISABLE
;
4799 temp
&= ~ DREF_SSC1_ENABLE
;
4801 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4802 POSTING_READ(PCH_DREF_CONTROL
);
4807 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4808 static void lpt_init_pch_refclk(struct drm_device
*dev
)
4810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4811 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4812 struct intel_encoder
*encoder
;
4813 bool has_vga
= false;
4814 bool is_sdv
= false;
4817 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4818 switch (encoder
->type
) {
4819 case INTEL_OUTPUT_ANALOG
:
4828 mutex_lock(&dev_priv
->dpio_lock
);
4830 /* XXX: Rip out SDV support once Haswell ships for real. */
4831 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
4834 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4835 tmp
&= ~SBI_SSCCTL_DISABLE
;
4836 tmp
|= SBI_SSCCTL_PATHALT
;
4837 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4841 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4842 tmp
&= ~SBI_SSCCTL_PATHALT
;
4843 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4846 tmp
= I915_READ(SOUTH_CHICKEN2
);
4847 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
4848 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4850 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
4851 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
4852 DRM_ERROR("FDI mPHY reset assert timeout\n");
4854 tmp
= I915_READ(SOUTH_CHICKEN2
);
4855 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
4856 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4858 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
4859 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
4861 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4864 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
4865 tmp
&= ~(0xFF << 24);
4866 tmp
|= (0x12 << 24);
4867 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
4870 tmp
= intel_sbi_read(dev_priv
, 0x808C, SBI_MPHY
);
4872 tmp
|= (1 << 6) | (1 << 0);
4873 intel_sbi_write(dev_priv
, 0x808C, tmp
, SBI_MPHY
);
4877 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
4879 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
4882 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
4884 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
4886 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
4888 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
4891 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
4892 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4893 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
4895 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
4896 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4897 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
4899 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
4901 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
4903 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
4905 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
4908 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
4909 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
4910 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
4912 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
4913 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
4914 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
4917 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
4920 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
4922 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
4925 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
4928 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
4931 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
4933 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
4936 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
4938 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
4939 tmp
&= ~(0xFF << 16);
4940 tmp
|= (0x1C << 16);
4941 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
4943 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
4944 tmp
&= ~(0xFF << 16);
4945 tmp
|= (0x1C << 16);
4946 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
4949 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
4951 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
4953 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
4955 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
4957 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
4958 tmp
&= ~(0xF << 28);
4960 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
4962 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
4963 tmp
&= ~(0xF << 28);
4965 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
4968 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
4969 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
4970 tmp
|= SBI_DBUFF0_ENABLE
;
4971 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
4973 mutex_unlock(&dev_priv
->dpio_lock
);
4977 * Initialize reference clocks when the driver loads
4979 void intel_init_pch_refclk(struct drm_device
*dev
)
4981 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4982 ironlake_init_pch_refclk(dev
);
4983 else if (HAS_PCH_LPT(dev
))
4984 lpt_init_pch_refclk(dev
);
4987 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4989 struct drm_device
*dev
= crtc
->dev
;
4990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4991 struct intel_encoder
*encoder
;
4992 struct intel_encoder
*edp_encoder
= NULL
;
4993 int num_connectors
= 0;
4994 bool is_lvds
= false;
4996 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4997 switch (encoder
->type
) {
4998 case INTEL_OUTPUT_LVDS
:
5001 case INTEL_OUTPUT_EDP
:
5002 edp_encoder
= encoder
;
5008 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5009 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5010 dev_priv
->lvds_ssc_freq
);
5011 return dev_priv
->lvds_ssc_freq
* 1000;
5017 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5018 struct drm_display_mode
*adjusted_mode
,
5021 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5022 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5023 int pipe
= intel_crtc
->pipe
;
5026 val
= I915_READ(PIPECONF(pipe
));
5028 val
&= ~PIPECONF_BPC_MASK
;
5029 switch (intel_crtc
->config
.pipe_bpp
) {
5031 val
|= PIPECONF_6BPC
;
5034 val
|= PIPECONF_8BPC
;
5037 val
|= PIPECONF_10BPC
;
5040 val
|= PIPECONF_12BPC
;
5043 /* Case prevented by intel_choose_pipe_bpp_dither. */
5047 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5049 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5051 val
&= ~PIPECONF_INTERLACE_MASK
;
5052 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5053 val
|= PIPECONF_INTERLACED_ILK
;
5055 val
|= PIPECONF_PROGRESSIVE
;
5057 if (intel_crtc
->config
.limited_color_range
)
5058 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5060 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5062 I915_WRITE(PIPECONF(pipe
), val
);
5063 POSTING_READ(PIPECONF(pipe
));
5067 * Set up the pipe CSC unit.
5069 * Currently only full range RGB to limited range RGB conversion
5070 * is supported, but eventually this should handle various
5071 * RGB<->YCbCr scenarios as well.
5073 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5075 struct drm_device
*dev
= crtc
->dev
;
5076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5077 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5078 int pipe
= intel_crtc
->pipe
;
5079 uint16_t coeff
= 0x7800; /* 1.0 */
5082 * TODO: Check what kind of values actually come out of the pipe
5083 * with these coeff/postoff values and adjust to get the best
5084 * accuracy. Perhaps we even need to take the bpc value into
5088 if (intel_crtc
->config
.limited_color_range
)
5089 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5092 * GY/GU and RY/RU should be the other way around according
5093 * to BSpec, but reality doesn't agree. Just set them up in
5094 * a way that results in the correct picture.
5096 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5097 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5099 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5100 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5102 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5103 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5105 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5106 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5107 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5109 if (INTEL_INFO(dev
)->gen
> 6) {
5110 uint16_t postoff
= 0;
5112 if (intel_crtc
->config
.limited_color_range
)
5113 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5115 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5116 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5117 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5119 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5121 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5123 if (intel_crtc
->config
.limited_color_range
)
5124 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5126 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5130 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5131 struct drm_display_mode
*adjusted_mode
,
5134 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5136 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5139 val
= I915_READ(PIPECONF(cpu_transcoder
));
5141 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5143 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5145 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5146 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5147 val
|= PIPECONF_INTERLACED_ILK
;
5149 val
|= PIPECONF_PROGRESSIVE
;
5151 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5152 POSTING_READ(PIPECONF(cpu_transcoder
));
5155 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5156 struct drm_display_mode
*adjusted_mode
,
5157 intel_clock_t
*clock
,
5158 bool *has_reduced_clock
,
5159 intel_clock_t
*reduced_clock
)
5161 struct drm_device
*dev
= crtc
->dev
;
5162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5163 struct intel_encoder
*intel_encoder
;
5165 const intel_limit_t
*limit
;
5166 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5168 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5169 switch (intel_encoder
->type
) {
5170 case INTEL_OUTPUT_LVDS
:
5173 case INTEL_OUTPUT_SDVO
:
5174 case INTEL_OUTPUT_HDMI
:
5176 if (intel_encoder
->needs_tv_clock
)
5179 case INTEL_OUTPUT_TVOUT
:
5185 refclk
= ironlake_get_refclk(crtc
);
5188 * Returns a set of divisors for the desired target clock with the given
5189 * refclk, or FALSE. The returned values represent the clock equation:
5190 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5192 limit
= intel_limit(crtc
, refclk
);
5193 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5198 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5200 * Ensure we match the reduced clock's P to the target clock.
5201 * If the clocks don't match, we can't switch the display clock
5202 * by using the FP0/FP1. In such case we will disable the LVDS
5203 * downclock feature.
5205 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5206 dev_priv
->lvds_downclock
,
5212 if (is_sdvo
&& is_tv
)
5213 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
5218 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5223 temp
= I915_READ(SOUTH_CHICKEN1
);
5224 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5227 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5228 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5230 temp
|= FDI_BC_BIFURCATION_SELECT
;
5231 DRM_DEBUG_KMS("enabling fdi C rx\n");
5232 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5233 POSTING_READ(SOUTH_CHICKEN1
);
5236 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5238 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5240 struct intel_crtc
*pipe_B_crtc
=
5241 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5243 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5244 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5245 if (intel_crtc
->fdi_lanes
> 4) {
5246 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5247 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5248 /* Clamp lanes to avoid programming the hw with bogus values. */
5249 intel_crtc
->fdi_lanes
= 4;
5254 if (INTEL_INFO(dev
)->num_pipes
== 2)
5257 switch (intel_crtc
->pipe
) {
5261 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5262 intel_crtc
->fdi_lanes
> 2) {
5263 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5264 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5265 /* Clamp lanes to avoid programming the hw with bogus values. */
5266 intel_crtc
->fdi_lanes
= 2;
5271 if (intel_crtc
->fdi_lanes
> 2)
5272 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5274 cpt_enable_fdi_bc_bifurcation(dev
);
5278 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5279 if (intel_crtc
->fdi_lanes
> 2) {
5280 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5281 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5282 /* Clamp lanes to avoid programming the hw with bogus values. */
5283 intel_crtc
->fdi_lanes
= 2;
5288 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5292 cpt_enable_fdi_bc_bifurcation(dev
);
5300 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5303 * Account for spread spectrum to avoid
5304 * oversubscribing the link. Max center spread
5305 * is 2.5%; use 5% for safety's sake.
5307 u32 bps
= target_clock
* bpp
* 21 / 20;
5308 return bps
/ (link_bw
* 8) + 1;
5311 static void ironlake_set_m_n(struct drm_crtc
*crtc
)
5313 struct drm_device
*dev
= crtc
->dev
;
5314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5315 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5316 struct drm_display_mode
*adjusted_mode
=
5317 &intel_crtc
->config
.adjusted_mode
;
5318 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5319 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5320 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
5321 struct intel_link_m_n m_n
= {0};
5322 int target_clock
, lane
, link_bw
;
5323 bool is_dp
= false, is_cpu_edp
= false;
5325 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5326 switch (intel_encoder
->type
) {
5327 case INTEL_OUTPUT_DISPLAYPORT
:
5330 case INTEL_OUTPUT_EDP
:
5332 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5334 edp_encoder
= intel_encoder
;
5341 /* CPU eDP doesn't require FDI link, so just set DP M/N
5342 according to current link config */
5344 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
5346 /* FDI is a binary signal running at ~2.7GHz, encoding
5347 * each output octet as 10 bits. The actual frequency
5348 * is stored as a divider into a 100MHz clock, and the
5349 * mode pixel clock is stored in units of 1KHz.
5350 * Hence the bw of each lane in terms of the mode signal
5353 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5356 /* [e]DP over FDI requires target mode clock instead of link clock. */
5358 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
5360 target_clock
= mode
->clock
;
5362 target_clock
= adjusted_mode
->clock
;
5365 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5366 intel_crtc
->config
.pipe_bpp
);
5368 intel_crtc
->fdi_lanes
= lane
;
5370 if (intel_crtc
->config
.pixel_multiplier
> 1)
5371 link_bw
*= intel_crtc
->config
.pixel_multiplier
;
5372 intel_link_compute_m_n(intel_crtc
->config
.pipe_bpp
, lane
, target_clock
,
5375 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5376 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
5377 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
5378 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
5381 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5382 intel_clock_t
*clock
, u32 fp
)
5384 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5385 struct drm_device
*dev
= crtc
->dev
;
5386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5387 struct intel_encoder
*intel_encoder
;
5389 int factor
, num_connectors
= 0;
5390 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5391 bool is_dp
= false, is_cpu_edp
= false;
5393 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5394 switch (intel_encoder
->type
) {
5395 case INTEL_OUTPUT_LVDS
:
5398 case INTEL_OUTPUT_SDVO
:
5399 case INTEL_OUTPUT_HDMI
:
5401 if (intel_encoder
->needs_tv_clock
)
5404 case INTEL_OUTPUT_TVOUT
:
5407 case INTEL_OUTPUT_DISPLAYPORT
:
5410 case INTEL_OUTPUT_EDP
:
5412 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5420 /* Enable autotuning of the PLL clock (if permissible) */
5423 if ((intel_panel_use_ssc(dev_priv
) &&
5424 dev_priv
->lvds_ssc_freq
== 100) ||
5425 intel_is_dual_link_lvds(dev
))
5427 } else if (is_sdvo
&& is_tv
)
5430 if (clock
->m
< factor
* clock
->n
)
5436 dpll
|= DPLLB_MODE_LVDS
;
5438 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5440 if (intel_crtc
->config
.pixel_multiplier
> 1) {
5441 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5442 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5444 dpll
|= DPLL_DVO_HIGH_SPEED
;
5446 if (is_dp
&& !is_cpu_edp
)
5447 dpll
|= DPLL_DVO_HIGH_SPEED
;
5449 /* compute bitmask from p1 value */
5450 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5452 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5454 switch (clock
->p2
) {
5456 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5459 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5462 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5465 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5469 if (is_sdvo
&& is_tv
)
5470 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5472 /* XXX: just matching BIOS for now */
5473 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5475 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5476 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5478 dpll
|= PLL_REF_INPUT_DREFCLK
;
5483 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5485 struct drm_framebuffer
*fb
)
5487 struct drm_device
*dev
= crtc
->dev
;
5488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5489 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5490 struct drm_display_mode
*adjusted_mode
=
5491 &intel_crtc
->config
.adjusted_mode
;
5492 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5493 int pipe
= intel_crtc
->pipe
;
5494 int plane
= intel_crtc
->plane
;
5495 int num_connectors
= 0;
5496 intel_clock_t clock
, reduced_clock
;
5497 u32 dpll
, fp
= 0, fp2
= 0;
5498 bool ok
, has_reduced_clock
= false;
5499 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5500 struct intel_encoder
*encoder
;
5502 bool dither
, fdi_config_ok
;
5504 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5505 switch (encoder
->type
) {
5506 case INTEL_OUTPUT_LVDS
:
5509 case INTEL_OUTPUT_DISPLAYPORT
:
5512 case INTEL_OUTPUT_EDP
:
5514 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5522 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5523 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5525 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5526 &has_reduced_clock
, &reduced_clock
);
5528 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5532 /* Ensure that the cursor is valid for the new mode before changing... */
5533 intel_crtc_update_cursor(crtc
, true);
5535 /* determine panel color depth */
5536 dither
= intel_crtc
->config
.dither
;
5537 if (is_lvds
&& dev_priv
->lvds_dither
)
5540 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5541 if (has_reduced_clock
)
5542 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5545 dpll
= ironlake_compute_dpll(intel_crtc
, &clock
, fp
);
5547 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5548 drm_mode_debug_printmodeline(mode
);
5550 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5552 struct intel_pch_pll
*pll
;
5554 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5556 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5561 intel_put_pch_pll(intel_crtc
);
5563 if (is_dp
&& !is_cpu_edp
)
5564 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5566 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5567 if (encoder
->pre_pll_enable
)
5568 encoder
->pre_pll_enable(encoder
);
5570 if (intel_crtc
->pch_pll
) {
5571 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5573 /* Wait for the clocks to stabilize. */
5574 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5577 /* The pixel multiplier can only be updated once the
5578 * DPLL is enabled and the clocks are stable.
5580 * So write it again.
5582 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5585 intel_crtc
->lowfreq_avail
= false;
5586 if (intel_crtc
->pch_pll
) {
5587 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5588 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5589 intel_crtc
->lowfreq_avail
= true;
5591 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5595 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5597 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5598 * ironlake_check_fdi_lanes. */
5599 ironlake_set_m_n(crtc
);
5601 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5603 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5605 intel_wait_for_vblank(dev
, pipe
);
5607 /* Set up the display plane register */
5608 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5609 POSTING_READ(DSPCNTR(plane
));
5611 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5613 intel_update_watermarks(dev
);
5615 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5617 return fdi_config_ok
? ret
: -EINVAL
;
5620 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5623 bool enable
= false;
5624 struct intel_crtc
*crtc
;
5625 struct intel_encoder
*encoder
;
5627 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5628 if (crtc
->pipe
!= PIPE_A
&& crtc
->base
.enabled
)
5630 /* XXX: Should check for edp transcoder here, but thanks to init
5631 * sequence that's not yet available. Just in case desktop eDP
5632 * on PORT D is possible on haswell, too. */
5635 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
5637 if (encoder
->type
!= INTEL_OUTPUT_EDP
&&
5638 encoder
->connectors_active
)
5642 /* Even the eDP panel fitter is outside the always-on well. */
5643 if (dev_priv
->pch_pf_size
)
5646 intel_set_power_well(dev
, enable
);
5649 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5651 struct drm_framebuffer
*fb
)
5653 struct drm_device
*dev
= crtc
->dev
;
5654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5656 struct drm_display_mode
*adjusted_mode
=
5657 &intel_crtc
->config
.adjusted_mode
;
5658 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5659 int pipe
= intel_crtc
->pipe
;
5660 int plane
= intel_crtc
->plane
;
5661 int num_connectors
= 0;
5662 bool is_dp
= false, is_cpu_edp
= false;
5663 struct intel_encoder
*encoder
;
5667 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5668 switch (encoder
->type
) {
5669 case INTEL_OUTPUT_DISPLAYPORT
:
5672 case INTEL_OUTPUT_EDP
:
5674 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5682 /* We are not sure yet this won't happen. */
5683 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5684 INTEL_PCH_TYPE(dev
));
5686 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5687 num_connectors
, pipe_name(pipe
));
5689 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5690 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5692 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5694 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5697 /* Ensure that the cursor is valid for the new mode before changing... */
5698 intel_crtc_update_cursor(crtc
, true);
5700 /* determine panel color depth */
5701 dither
= intel_crtc
->config
.dither
;
5703 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5704 drm_mode_debug_printmodeline(mode
);
5706 if (is_dp
&& !is_cpu_edp
)
5707 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5709 intel_crtc
->lowfreq_avail
= false;
5711 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5713 if (!is_dp
|| is_cpu_edp
)
5714 ironlake_set_m_n(crtc
);
5716 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5718 intel_set_pipe_csc(crtc
);
5720 /* Set up the display plane register */
5721 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5722 POSTING_READ(DSPCNTR(plane
));
5724 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5726 intel_update_watermarks(dev
);
5728 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5733 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5735 struct drm_framebuffer
*fb
)
5737 struct drm_device
*dev
= crtc
->dev
;
5738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5739 struct drm_encoder_helper_funcs
*encoder_funcs
;
5740 struct intel_encoder
*encoder
;
5741 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5742 struct drm_display_mode
*adjusted_mode
=
5743 &intel_crtc
->config
.adjusted_mode
;
5744 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5745 int pipe
= intel_crtc
->pipe
;
5748 if (IS_HASWELL(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
5749 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5751 intel_crtc
->cpu_transcoder
= pipe
;
5753 drm_vblank_pre_modeset(dev
, pipe
);
5755 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
5757 drm_vblank_post_modeset(dev
, pipe
);
5762 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5763 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5764 encoder
->base
.base
.id
,
5765 drm_get_encoder_name(&encoder
->base
),
5766 mode
->base
.id
, mode
->name
);
5767 if (encoder
->mode_set
) {
5768 encoder
->mode_set(encoder
);
5770 encoder_funcs
= encoder
->base
.helper_private
;
5771 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5778 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5779 int reg_eldv
, uint32_t bits_eldv
,
5780 int reg_elda
, uint32_t bits_elda
,
5783 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5784 uint8_t *eld
= connector
->eld
;
5787 i
= I915_READ(reg_eldv
);
5796 i
= I915_READ(reg_elda
);
5798 I915_WRITE(reg_elda
, i
);
5800 for (i
= 0; i
< eld
[2]; i
++)
5801 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5807 static void g4x_write_eld(struct drm_connector
*connector
,
5808 struct drm_crtc
*crtc
)
5810 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5811 uint8_t *eld
= connector
->eld
;
5816 i
= I915_READ(G4X_AUD_VID_DID
);
5818 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5819 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5821 eldv
= G4X_ELDV_DEVCTG
;
5823 if (intel_eld_uptodate(connector
,
5824 G4X_AUD_CNTL_ST
, eldv
,
5825 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5826 G4X_HDMIW_HDMIEDID
))
5829 i
= I915_READ(G4X_AUD_CNTL_ST
);
5830 i
&= ~(eldv
| G4X_ELD_ADDR
);
5831 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5832 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5837 len
= min_t(uint8_t, eld
[2], len
);
5838 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5839 for (i
= 0; i
< len
; i
++)
5840 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5842 i
= I915_READ(G4X_AUD_CNTL_ST
);
5844 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5847 static void haswell_write_eld(struct drm_connector
*connector
,
5848 struct drm_crtc
*crtc
)
5850 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5851 uint8_t *eld
= connector
->eld
;
5852 struct drm_device
*dev
= crtc
->dev
;
5853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5857 int pipe
= to_intel_crtc(crtc
)->pipe
;
5860 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5861 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5862 int aud_config
= HSW_AUD_CFG(pipe
);
5863 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5866 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5868 /* Audio output enable */
5869 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5870 tmp
= I915_READ(aud_cntrl_st2
);
5871 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5872 I915_WRITE(aud_cntrl_st2
, tmp
);
5874 /* Wait for 1 vertical blank */
5875 intel_wait_for_vblank(dev
, pipe
);
5877 /* Set ELD valid state */
5878 tmp
= I915_READ(aud_cntrl_st2
);
5879 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5880 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5881 I915_WRITE(aud_cntrl_st2
, tmp
);
5882 tmp
= I915_READ(aud_cntrl_st2
);
5883 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5885 /* Enable HDMI mode */
5886 tmp
= I915_READ(aud_config
);
5887 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5888 /* clear N_programing_enable and N_value_index */
5889 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5890 I915_WRITE(aud_config
, tmp
);
5892 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5894 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5895 intel_crtc
->eld_vld
= true;
5897 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5898 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5899 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5900 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5902 I915_WRITE(aud_config
, 0);
5904 if (intel_eld_uptodate(connector
,
5905 aud_cntrl_st2
, eldv
,
5906 aud_cntl_st
, IBX_ELD_ADDRESS
,
5910 i
= I915_READ(aud_cntrl_st2
);
5912 I915_WRITE(aud_cntrl_st2
, i
);
5917 i
= I915_READ(aud_cntl_st
);
5918 i
&= ~IBX_ELD_ADDRESS
;
5919 I915_WRITE(aud_cntl_st
, i
);
5920 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5921 DRM_DEBUG_DRIVER("port num:%d\n", i
);
5923 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5924 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5925 for (i
= 0; i
< len
; i
++)
5926 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5928 i
= I915_READ(aud_cntrl_st2
);
5930 I915_WRITE(aud_cntrl_st2
, i
);
5934 static void ironlake_write_eld(struct drm_connector
*connector
,
5935 struct drm_crtc
*crtc
)
5937 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5938 uint8_t *eld
= connector
->eld
;
5946 int pipe
= to_intel_crtc(crtc
)->pipe
;
5948 if (HAS_PCH_IBX(connector
->dev
)) {
5949 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
5950 aud_config
= IBX_AUD_CFG(pipe
);
5951 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
5952 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5954 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
5955 aud_config
= CPT_AUD_CFG(pipe
);
5956 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
5957 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5960 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5962 i
= I915_READ(aud_cntl_st
);
5963 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5965 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5966 /* operate blindly on all ports */
5967 eldv
= IBX_ELD_VALIDB
;
5968 eldv
|= IBX_ELD_VALIDB
<< 4;
5969 eldv
|= IBX_ELD_VALIDB
<< 8;
5971 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5972 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5975 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5976 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5977 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5978 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5980 I915_WRITE(aud_config
, 0);
5982 if (intel_eld_uptodate(connector
,
5983 aud_cntrl_st2
, eldv
,
5984 aud_cntl_st
, IBX_ELD_ADDRESS
,
5988 i
= I915_READ(aud_cntrl_st2
);
5990 I915_WRITE(aud_cntrl_st2
, i
);
5995 i
= I915_READ(aud_cntl_st
);
5996 i
&= ~IBX_ELD_ADDRESS
;
5997 I915_WRITE(aud_cntl_st
, i
);
5999 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6000 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6001 for (i
= 0; i
< len
; i
++)
6002 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6004 i
= I915_READ(aud_cntrl_st2
);
6006 I915_WRITE(aud_cntrl_st2
, i
);
6009 void intel_write_eld(struct drm_encoder
*encoder
,
6010 struct drm_display_mode
*mode
)
6012 struct drm_crtc
*crtc
= encoder
->crtc
;
6013 struct drm_connector
*connector
;
6014 struct drm_device
*dev
= encoder
->dev
;
6015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6017 connector
= drm_select_eld(encoder
, mode
);
6021 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6023 drm_get_connector_name(connector
),
6024 connector
->encoder
->base
.id
,
6025 drm_get_encoder_name(connector
->encoder
));
6027 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6029 if (dev_priv
->display
.write_eld
)
6030 dev_priv
->display
.write_eld(connector
, crtc
);
6033 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6034 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6036 struct drm_device
*dev
= crtc
->dev
;
6037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6038 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6039 int palreg
= PALETTE(intel_crtc
->pipe
);
6042 /* The clocks have to be on to load the palette. */
6043 if (!crtc
->enabled
|| !intel_crtc
->active
)
6046 /* use legacy palette for Ironlake */
6047 if (HAS_PCH_SPLIT(dev
))
6048 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6050 for (i
= 0; i
< 256; i
++) {
6051 I915_WRITE(palreg
+ 4 * i
,
6052 (intel_crtc
->lut_r
[i
] << 16) |
6053 (intel_crtc
->lut_g
[i
] << 8) |
6054 intel_crtc
->lut_b
[i
]);
6058 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6060 struct drm_device
*dev
= crtc
->dev
;
6061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6062 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6063 bool visible
= base
!= 0;
6066 if (intel_crtc
->cursor_visible
== visible
)
6069 cntl
= I915_READ(_CURACNTR
);
6071 /* On these chipsets we can only modify the base whilst
6072 * the cursor is disabled.
6074 I915_WRITE(_CURABASE
, base
);
6076 cntl
&= ~(CURSOR_FORMAT_MASK
);
6077 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6078 cntl
|= CURSOR_ENABLE
|
6079 CURSOR_GAMMA_ENABLE
|
6082 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6083 I915_WRITE(_CURACNTR
, cntl
);
6085 intel_crtc
->cursor_visible
= visible
;
6088 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6090 struct drm_device
*dev
= crtc
->dev
;
6091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6092 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6093 int pipe
= intel_crtc
->pipe
;
6094 bool visible
= base
!= 0;
6096 if (intel_crtc
->cursor_visible
!= visible
) {
6097 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6099 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6100 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6101 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6103 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6104 cntl
|= CURSOR_MODE_DISABLE
;
6106 I915_WRITE(CURCNTR(pipe
), cntl
);
6108 intel_crtc
->cursor_visible
= visible
;
6110 /* and commit changes on next vblank */
6111 I915_WRITE(CURBASE(pipe
), base
);
6114 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6116 struct drm_device
*dev
= crtc
->dev
;
6117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6118 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6119 int pipe
= intel_crtc
->pipe
;
6120 bool visible
= base
!= 0;
6122 if (intel_crtc
->cursor_visible
!= visible
) {
6123 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6125 cntl
&= ~CURSOR_MODE
;
6126 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6128 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6129 cntl
|= CURSOR_MODE_DISABLE
;
6131 if (IS_HASWELL(dev
))
6132 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6133 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6135 intel_crtc
->cursor_visible
= visible
;
6137 /* and commit changes on next vblank */
6138 I915_WRITE(CURBASE_IVB(pipe
), base
);
6141 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6142 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6145 struct drm_device
*dev
= crtc
->dev
;
6146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6148 int pipe
= intel_crtc
->pipe
;
6149 int x
= intel_crtc
->cursor_x
;
6150 int y
= intel_crtc
->cursor_y
;
6156 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6157 base
= intel_crtc
->cursor_addr
;
6158 if (x
> (int) crtc
->fb
->width
)
6161 if (y
> (int) crtc
->fb
->height
)
6167 if (x
+ intel_crtc
->cursor_width
< 0)
6170 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6173 pos
|= x
<< CURSOR_X_SHIFT
;
6176 if (y
+ intel_crtc
->cursor_height
< 0)
6179 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6182 pos
|= y
<< CURSOR_Y_SHIFT
;
6184 visible
= base
!= 0;
6185 if (!visible
&& !intel_crtc
->cursor_visible
)
6188 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6189 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6190 ivb_update_cursor(crtc
, base
);
6192 I915_WRITE(CURPOS(pipe
), pos
);
6193 if (IS_845G(dev
) || IS_I865G(dev
))
6194 i845_update_cursor(crtc
, base
);
6196 i9xx_update_cursor(crtc
, base
);
6200 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6201 struct drm_file
*file
,
6203 uint32_t width
, uint32_t height
)
6205 struct drm_device
*dev
= crtc
->dev
;
6206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6208 struct drm_i915_gem_object
*obj
;
6212 /* if we want to turn off the cursor ignore width and height */
6214 DRM_DEBUG_KMS("cursor off\n");
6217 mutex_lock(&dev
->struct_mutex
);
6221 /* Currently we only support 64x64 cursors */
6222 if (width
!= 64 || height
!= 64) {
6223 DRM_ERROR("we currently only support 64x64 cursors\n");
6227 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6228 if (&obj
->base
== NULL
)
6231 if (obj
->base
.size
< width
* height
* 4) {
6232 DRM_ERROR("buffer is to small\n");
6237 /* we only need to pin inside GTT if cursor is non-phy */
6238 mutex_lock(&dev
->struct_mutex
);
6239 if (!dev_priv
->info
->cursor_needs_physical
) {
6242 if (obj
->tiling_mode
) {
6243 DRM_ERROR("cursor cannot be tiled\n");
6248 /* Note that the w/a also requires 2 PTE of padding following
6249 * the bo. We currently fill all unused PTE with the shadow
6250 * page and so we should always have valid PTE following the
6251 * cursor preventing the VT-d warning.
6254 if (need_vtd_wa(dev
))
6255 alignment
= 64*1024;
6257 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6259 DRM_ERROR("failed to move cursor bo into the GTT\n");
6263 ret
= i915_gem_object_put_fence(obj
);
6265 DRM_ERROR("failed to release fence for cursor");
6269 addr
= obj
->gtt_offset
;
6271 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6272 ret
= i915_gem_attach_phys_object(dev
, obj
,
6273 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6276 DRM_ERROR("failed to attach phys object\n");
6279 addr
= obj
->phys_obj
->handle
->busaddr
;
6283 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6286 if (intel_crtc
->cursor_bo
) {
6287 if (dev_priv
->info
->cursor_needs_physical
) {
6288 if (intel_crtc
->cursor_bo
!= obj
)
6289 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6291 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6292 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6295 mutex_unlock(&dev
->struct_mutex
);
6297 intel_crtc
->cursor_addr
= addr
;
6298 intel_crtc
->cursor_bo
= obj
;
6299 intel_crtc
->cursor_width
= width
;
6300 intel_crtc
->cursor_height
= height
;
6302 intel_crtc_update_cursor(crtc
, true);
6306 i915_gem_object_unpin(obj
);
6308 mutex_unlock(&dev
->struct_mutex
);
6310 drm_gem_object_unreference_unlocked(&obj
->base
);
6314 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6316 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6318 intel_crtc
->cursor_x
= x
;
6319 intel_crtc
->cursor_y
= y
;
6321 intel_crtc_update_cursor(crtc
, true);
6326 /** Sets the color ramps on behalf of RandR */
6327 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6328 u16 blue
, int regno
)
6330 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6332 intel_crtc
->lut_r
[regno
] = red
>> 8;
6333 intel_crtc
->lut_g
[regno
] = green
>> 8;
6334 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6337 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6338 u16
*blue
, int regno
)
6340 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6342 *red
= intel_crtc
->lut_r
[regno
] << 8;
6343 *green
= intel_crtc
->lut_g
[regno
] << 8;
6344 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6347 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6348 u16
*blue
, uint32_t start
, uint32_t size
)
6350 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6351 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6353 for (i
= start
; i
< end
; i
++) {
6354 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6355 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6356 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6359 intel_crtc_load_lut(crtc
);
6362 /* VESA 640x480x72Hz mode to set on the pipe */
6363 static struct drm_display_mode load_detect_mode
= {
6364 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6365 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6368 static struct drm_framebuffer
*
6369 intel_framebuffer_create(struct drm_device
*dev
,
6370 struct drm_mode_fb_cmd2
*mode_cmd
,
6371 struct drm_i915_gem_object
*obj
)
6373 struct intel_framebuffer
*intel_fb
;
6376 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6378 drm_gem_object_unreference_unlocked(&obj
->base
);
6379 return ERR_PTR(-ENOMEM
);
6382 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6384 drm_gem_object_unreference_unlocked(&obj
->base
);
6386 return ERR_PTR(ret
);
6389 return &intel_fb
->base
;
6393 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6395 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6396 return ALIGN(pitch
, 64);
6400 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6402 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6403 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6406 static struct drm_framebuffer
*
6407 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6408 struct drm_display_mode
*mode
,
6411 struct drm_i915_gem_object
*obj
;
6412 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6414 obj
= i915_gem_alloc_object(dev
,
6415 intel_framebuffer_size_for_mode(mode
, bpp
));
6417 return ERR_PTR(-ENOMEM
);
6419 mode_cmd
.width
= mode
->hdisplay
;
6420 mode_cmd
.height
= mode
->vdisplay
;
6421 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6423 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6425 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6428 static struct drm_framebuffer
*
6429 mode_fits_in_fbdev(struct drm_device
*dev
,
6430 struct drm_display_mode
*mode
)
6432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6433 struct drm_i915_gem_object
*obj
;
6434 struct drm_framebuffer
*fb
;
6436 if (dev_priv
->fbdev
== NULL
)
6439 obj
= dev_priv
->fbdev
->ifb
.obj
;
6443 fb
= &dev_priv
->fbdev
->ifb
.base
;
6444 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6445 fb
->bits_per_pixel
))
6448 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6454 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6455 struct drm_display_mode
*mode
,
6456 struct intel_load_detect_pipe
*old
)
6458 struct intel_crtc
*intel_crtc
;
6459 struct intel_encoder
*intel_encoder
=
6460 intel_attached_encoder(connector
);
6461 struct drm_crtc
*possible_crtc
;
6462 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6463 struct drm_crtc
*crtc
= NULL
;
6464 struct drm_device
*dev
= encoder
->dev
;
6465 struct drm_framebuffer
*fb
;
6468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6469 connector
->base
.id
, drm_get_connector_name(connector
),
6470 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6473 * Algorithm gets a little messy:
6475 * - if the connector already has an assigned crtc, use it (but make
6476 * sure it's on first)
6478 * - try to find the first unused crtc that can drive this connector,
6479 * and use that if we find one
6482 /* See if we already have a CRTC for this connector */
6483 if (encoder
->crtc
) {
6484 crtc
= encoder
->crtc
;
6486 mutex_lock(&crtc
->mutex
);
6488 old
->dpms_mode
= connector
->dpms
;
6489 old
->load_detect_temp
= false;
6491 /* Make sure the crtc and connector are running */
6492 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6493 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6498 /* Find an unused one (if possible) */
6499 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6501 if (!(encoder
->possible_crtcs
& (1 << i
)))
6503 if (!possible_crtc
->enabled
) {
6504 crtc
= possible_crtc
;
6510 * If we didn't find an unused CRTC, don't use any.
6513 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6517 mutex_lock(&crtc
->mutex
);
6518 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6519 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6521 intel_crtc
= to_intel_crtc(crtc
);
6522 old
->dpms_mode
= connector
->dpms
;
6523 old
->load_detect_temp
= true;
6524 old
->release_fb
= NULL
;
6527 mode
= &load_detect_mode
;
6529 /* We need a framebuffer large enough to accommodate all accesses
6530 * that the plane may generate whilst we perform load detection.
6531 * We can not rely on the fbcon either being present (we get called
6532 * during its initialisation to detect all boot displays, or it may
6533 * not even exist) or that it is large enough to satisfy the
6536 fb
= mode_fits_in_fbdev(dev
, mode
);
6538 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6539 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6540 old
->release_fb
= fb
;
6542 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6544 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6545 mutex_unlock(&crtc
->mutex
);
6549 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6550 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6551 if (old
->release_fb
)
6552 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6553 mutex_unlock(&crtc
->mutex
);
6557 /* let the connector get through one full cycle before testing */
6558 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6562 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6563 struct intel_load_detect_pipe
*old
)
6565 struct intel_encoder
*intel_encoder
=
6566 intel_attached_encoder(connector
);
6567 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6568 struct drm_crtc
*crtc
= encoder
->crtc
;
6570 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6571 connector
->base
.id
, drm_get_connector_name(connector
),
6572 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6574 if (old
->load_detect_temp
) {
6575 to_intel_connector(connector
)->new_encoder
= NULL
;
6576 intel_encoder
->new_crtc
= NULL
;
6577 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6579 if (old
->release_fb
) {
6580 drm_framebuffer_unregister_private(old
->release_fb
);
6581 drm_framebuffer_unreference(old
->release_fb
);
6584 mutex_unlock(&crtc
->mutex
);
6588 /* Switch crtc and encoder back off if necessary */
6589 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6590 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6592 mutex_unlock(&crtc
->mutex
);
6595 /* Returns the clock of the currently programmed mode of the given pipe. */
6596 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6599 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6600 int pipe
= intel_crtc
->pipe
;
6601 u32 dpll
= I915_READ(DPLL(pipe
));
6603 intel_clock_t clock
;
6605 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6606 fp
= I915_READ(FP0(pipe
));
6608 fp
= I915_READ(FP1(pipe
));
6610 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6611 if (IS_PINEVIEW(dev
)) {
6612 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6613 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6615 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6616 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6619 if (!IS_GEN2(dev
)) {
6620 if (IS_PINEVIEW(dev
))
6621 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6622 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6624 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6625 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6627 switch (dpll
& DPLL_MODE_MASK
) {
6628 case DPLLB_MODE_DAC_SERIAL
:
6629 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6632 case DPLLB_MODE_LVDS
:
6633 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6637 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6638 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6642 /* XXX: Handle the 100Mhz refclk */
6643 intel_clock(dev
, 96000, &clock
);
6645 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6648 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6649 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6652 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6653 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6654 /* XXX: might not be 66MHz */
6655 intel_clock(dev
, 66000, &clock
);
6657 intel_clock(dev
, 48000, &clock
);
6659 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6662 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6663 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6665 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6670 intel_clock(dev
, 48000, &clock
);
6674 /* XXX: It would be nice to validate the clocks, but we can't reuse
6675 * i830PllIsValid() because it relies on the xf86_config connector
6676 * configuration being accurate, which it isn't necessarily.
6682 /** Returns the currently programmed mode of the given pipe. */
6683 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6684 struct drm_crtc
*crtc
)
6686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6687 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6688 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6689 struct drm_display_mode
*mode
;
6690 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6691 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6692 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6693 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6695 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6699 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6700 mode
->hdisplay
= (htot
& 0xffff) + 1;
6701 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6702 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6703 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6704 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6705 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6706 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6707 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6709 drm_mode_set_name(mode
);
6714 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6716 struct drm_device
*dev
= crtc
->dev
;
6717 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6718 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6719 int pipe
= intel_crtc
->pipe
;
6720 int dpll_reg
= DPLL(pipe
);
6723 if (HAS_PCH_SPLIT(dev
))
6726 if (!dev_priv
->lvds_downclock_avail
)
6729 dpll
= I915_READ(dpll_reg
);
6730 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6731 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6733 assert_panel_unlocked(dev_priv
, pipe
);
6735 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6736 I915_WRITE(dpll_reg
, dpll
);
6737 intel_wait_for_vblank(dev
, pipe
);
6739 dpll
= I915_READ(dpll_reg
);
6740 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6741 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6745 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6747 struct drm_device
*dev
= crtc
->dev
;
6748 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6749 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6751 if (HAS_PCH_SPLIT(dev
))
6754 if (!dev_priv
->lvds_downclock_avail
)
6758 * Since this is called by a timer, we should never get here in
6761 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6762 int pipe
= intel_crtc
->pipe
;
6763 int dpll_reg
= DPLL(pipe
);
6766 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6768 assert_panel_unlocked(dev_priv
, pipe
);
6770 dpll
= I915_READ(dpll_reg
);
6771 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6772 I915_WRITE(dpll_reg
, dpll
);
6773 intel_wait_for_vblank(dev
, pipe
);
6774 dpll
= I915_READ(dpll_reg
);
6775 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6776 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6781 void intel_mark_busy(struct drm_device
*dev
)
6783 i915_update_gfx_val(dev
->dev_private
);
6786 void intel_mark_idle(struct drm_device
*dev
)
6788 struct drm_crtc
*crtc
;
6790 if (!i915_powersave
)
6793 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6797 intel_decrease_pllclock(crtc
);
6801 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6803 struct drm_device
*dev
= obj
->base
.dev
;
6804 struct drm_crtc
*crtc
;
6806 if (!i915_powersave
)
6809 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6813 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6814 intel_increase_pllclock(crtc
);
6818 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6821 struct drm_device
*dev
= crtc
->dev
;
6822 struct intel_unpin_work
*work
;
6823 unsigned long flags
;
6825 spin_lock_irqsave(&dev
->event_lock
, flags
);
6826 work
= intel_crtc
->unpin_work
;
6827 intel_crtc
->unpin_work
= NULL
;
6828 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6831 cancel_work_sync(&work
->work
);
6835 drm_crtc_cleanup(crtc
);
6840 static void intel_unpin_work_fn(struct work_struct
*__work
)
6842 struct intel_unpin_work
*work
=
6843 container_of(__work
, struct intel_unpin_work
, work
);
6844 struct drm_device
*dev
= work
->crtc
->dev
;
6846 mutex_lock(&dev
->struct_mutex
);
6847 intel_unpin_fb_obj(work
->old_fb_obj
);
6848 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6849 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6851 intel_update_fbc(dev
);
6852 mutex_unlock(&dev
->struct_mutex
);
6854 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
6855 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
6860 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6861 struct drm_crtc
*crtc
)
6863 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6864 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6865 struct intel_unpin_work
*work
;
6866 unsigned long flags
;
6868 /* Ignore early vblank irqs */
6869 if (intel_crtc
== NULL
)
6872 spin_lock_irqsave(&dev
->event_lock
, flags
);
6873 work
= intel_crtc
->unpin_work
;
6875 /* Ensure we don't miss a work->pending update ... */
6878 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
6879 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6883 /* and that the unpin work is consistent wrt ->pending. */
6886 intel_crtc
->unpin_work
= NULL
;
6889 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
6891 drm_vblank_put(dev
, intel_crtc
->pipe
);
6893 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6895 wake_up_all(&dev_priv
->pending_flip_queue
);
6897 queue_work(dev_priv
->wq
, &work
->work
);
6899 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6902 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6904 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6905 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6907 do_intel_finish_page_flip(dev
, crtc
);
6910 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6913 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6915 do_intel_finish_page_flip(dev
, crtc
);
6918 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6920 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6921 struct intel_crtc
*intel_crtc
=
6922 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6923 unsigned long flags
;
6925 /* NB: An MMIO update of the plane base pointer will also
6926 * generate a page-flip completion irq, i.e. every modeset
6927 * is also accompanied by a spurious intel_prepare_page_flip().
6929 spin_lock_irqsave(&dev
->event_lock
, flags
);
6930 if (intel_crtc
->unpin_work
)
6931 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
6932 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6935 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
6937 /* Ensure that the work item is consistent when activating it ... */
6939 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
6940 /* and that it is marked active as soon as the irq could fire. */
6944 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6945 struct drm_crtc
*crtc
,
6946 struct drm_framebuffer
*fb
,
6947 struct drm_i915_gem_object
*obj
)
6949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6950 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6952 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6955 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6959 ret
= intel_ring_begin(ring
, 6);
6963 /* Can't queue multiple flips, so wait for the previous
6964 * one to finish before executing the next.
6966 if (intel_crtc
->plane
)
6967 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6969 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6970 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6971 intel_ring_emit(ring
, MI_NOOP
);
6972 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6973 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6974 intel_ring_emit(ring
, fb
->pitches
[0]);
6975 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6976 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6978 intel_mark_page_flip_active(intel_crtc
);
6979 intel_ring_advance(ring
);
6983 intel_unpin_fb_obj(obj
);
6988 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6989 struct drm_crtc
*crtc
,
6990 struct drm_framebuffer
*fb
,
6991 struct drm_i915_gem_object
*obj
)
6993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6994 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6996 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6999 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7003 ret
= intel_ring_begin(ring
, 6);
7007 if (intel_crtc
->plane
)
7008 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7010 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7011 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7012 intel_ring_emit(ring
, MI_NOOP
);
7013 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7014 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7015 intel_ring_emit(ring
, fb
->pitches
[0]);
7016 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7017 intel_ring_emit(ring
, MI_NOOP
);
7019 intel_mark_page_flip_active(intel_crtc
);
7020 intel_ring_advance(ring
);
7024 intel_unpin_fb_obj(obj
);
7029 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7030 struct drm_crtc
*crtc
,
7031 struct drm_framebuffer
*fb
,
7032 struct drm_i915_gem_object
*obj
)
7034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7035 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7036 uint32_t pf
, pipesrc
;
7037 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7040 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7044 ret
= intel_ring_begin(ring
, 4);
7048 /* i965+ uses the linear or tiled offsets from the
7049 * Display Registers (which do not change across a page-flip)
7050 * so we need only reprogram the base address.
7052 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7053 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7054 intel_ring_emit(ring
, fb
->pitches
[0]);
7055 intel_ring_emit(ring
,
7056 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7059 /* XXX Enabling the panel-fitter across page-flip is so far
7060 * untested on non-native modes, so ignore it for now.
7061 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7064 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7065 intel_ring_emit(ring
, pf
| pipesrc
);
7067 intel_mark_page_flip_active(intel_crtc
);
7068 intel_ring_advance(ring
);
7072 intel_unpin_fb_obj(obj
);
7077 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7078 struct drm_crtc
*crtc
,
7079 struct drm_framebuffer
*fb
,
7080 struct drm_i915_gem_object
*obj
)
7082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7083 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7084 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7085 uint32_t pf
, pipesrc
;
7088 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7092 ret
= intel_ring_begin(ring
, 4);
7096 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7097 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7098 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7099 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7101 /* Contrary to the suggestions in the documentation,
7102 * "Enable Panel Fitter" does not seem to be required when page
7103 * flipping with a non-native mode, and worse causes a normal
7105 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7108 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7109 intel_ring_emit(ring
, pf
| pipesrc
);
7111 intel_mark_page_flip_active(intel_crtc
);
7112 intel_ring_advance(ring
);
7116 intel_unpin_fb_obj(obj
);
7122 * On gen7 we currently use the blit ring because (in early silicon at least)
7123 * the render ring doesn't give us interrpts for page flip completion, which
7124 * means clients will hang after the first flip is queued. Fortunately the
7125 * blit ring generates interrupts properly, so use it instead.
7127 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7128 struct drm_crtc
*crtc
,
7129 struct drm_framebuffer
*fb
,
7130 struct drm_i915_gem_object
*obj
)
7132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7134 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7135 uint32_t plane_bit
= 0;
7138 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7142 switch(intel_crtc
->plane
) {
7144 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7147 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7150 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7153 WARN_ONCE(1, "unknown plane in flip command\n");
7158 ret
= intel_ring_begin(ring
, 4);
7162 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7163 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7164 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7165 intel_ring_emit(ring
, (MI_NOOP
));
7167 intel_mark_page_flip_active(intel_crtc
);
7168 intel_ring_advance(ring
);
7172 intel_unpin_fb_obj(obj
);
7177 static int intel_default_queue_flip(struct drm_device
*dev
,
7178 struct drm_crtc
*crtc
,
7179 struct drm_framebuffer
*fb
,
7180 struct drm_i915_gem_object
*obj
)
7185 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7186 struct drm_framebuffer
*fb
,
7187 struct drm_pending_vblank_event
*event
)
7189 struct drm_device
*dev
= crtc
->dev
;
7190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7191 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7192 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7194 struct intel_unpin_work
*work
;
7195 unsigned long flags
;
7198 /* Can't change pixel format via MI display flips. */
7199 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7203 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7204 * Note that pitch changes could also affect these register.
7206 if (INTEL_INFO(dev
)->gen
> 3 &&
7207 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7208 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7211 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7215 work
->event
= event
;
7217 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7218 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7220 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7224 /* We borrow the event spin lock for protecting unpin_work */
7225 spin_lock_irqsave(&dev
->event_lock
, flags
);
7226 if (intel_crtc
->unpin_work
) {
7227 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7229 drm_vblank_put(dev
, intel_crtc
->pipe
);
7231 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7234 intel_crtc
->unpin_work
= work
;
7235 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7237 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7238 flush_workqueue(dev_priv
->wq
);
7240 ret
= i915_mutex_lock_interruptible(dev
);
7244 /* Reference the objects for the scheduled work. */
7245 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7246 drm_gem_object_reference(&obj
->base
);
7250 work
->pending_flip_obj
= obj
;
7252 work
->enable_stall_check
= true;
7254 atomic_inc(&intel_crtc
->unpin_work_count
);
7255 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7257 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7259 goto cleanup_pending
;
7261 intel_disable_fbc(dev
);
7262 intel_mark_fb_busy(obj
);
7263 mutex_unlock(&dev
->struct_mutex
);
7265 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7270 atomic_dec(&intel_crtc
->unpin_work_count
);
7272 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7273 drm_gem_object_unreference(&obj
->base
);
7274 mutex_unlock(&dev
->struct_mutex
);
7277 spin_lock_irqsave(&dev
->event_lock
, flags
);
7278 intel_crtc
->unpin_work
= NULL
;
7279 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7281 drm_vblank_put(dev
, intel_crtc
->pipe
);
7288 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7289 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7290 .load_lut
= intel_crtc_load_lut
,
7293 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7295 struct intel_encoder
*other_encoder
;
7296 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7301 list_for_each_entry(other_encoder
,
7302 &crtc
->dev
->mode_config
.encoder_list
,
7305 if (&other_encoder
->new_crtc
->base
!= crtc
||
7306 encoder
== other_encoder
)
7315 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7316 struct drm_crtc
*crtc
)
7318 struct drm_device
*dev
;
7319 struct drm_crtc
*tmp
;
7322 WARN(!crtc
, "checking null crtc?\n");
7326 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7332 if (encoder
->possible_crtcs
& crtc_mask
)
7338 * intel_modeset_update_staged_output_state
7340 * Updates the staged output configuration state, e.g. after we've read out the
7343 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7345 struct intel_encoder
*encoder
;
7346 struct intel_connector
*connector
;
7348 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7350 connector
->new_encoder
=
7351 to_intel_encoder(connector
->base
.encoder
);
7354 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7357 to_intel_crtc(encoder
->base
.crtc
);
7362 * intel_modeset_commit_output_state
7364 * This function copies the stage display pipe configuration to the real one.
7366 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7368 struct intel_encoder
*encoder
;
7369 struct intel_connector
*connector
;
7371 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7373 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7376 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7378 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7383 pipe_config_set_bpp(struct drm_crtc
*crtc
,
7384 struct drm_framebuffer
*fb
,
7385 struct intel_crtc_config
*pipe_config
)
7387 struct drm_device
*dev
= crtc
->dev
;
7388 struct drm_connector
*connector
;
7391 switch (fb
->depth
) {
7393 bpp
= 8*3; /* since we go through a colormap */
7397 bpp
= 6*3; /* min is 18bpp */
7409 DRM_DEBUG_KMS("unsupported depth\n");
7413 if (fb
->depth
> 24 && !HAS_PCH_SPLIT(dev
)) {
7414 DRM_DEBUG_KMS("high depth not supported on gmch platforms\n");
7418 pipe_config
->pipe_bpp
= bpp
;
7420 /* Clamp display bpp to EDID value */
7421 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7423 if (connector
->encoder
&& connector
->encoder
->crtc
!= crtc
)
7426 /* Don't use an invalid EDID bpc value */
7427 if (connector
->display_info
.bpc
&&
7428 connector
->display_info
.bpc
* 3 < bpp
) {
7429 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7430 bpp
, connector
->display_info
.bpc
*3);
7431 pipe_config
->pipe_bpp
= connector
->display_info
.bpc
*3;
7438 static struct intel_crtc_config
*
7439 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7440 struct drm_framebuffer
*fb
,
7441 struct drm_display_mode
*mode
)
7443 struct drm_device
*dev
= crtc
->dev
;
7444 struct drm_encoder_helper_funcs
*encoder_funcs
;
7445 struct intel_encoder
*encoder
;
7446 struct intel_crtc_config
*pipe_config
;
7449 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7451 return ERR_PTR(-ENOMEM
);
7453 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7454 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7456 plane_bpp
= pipe_config_set_bpp(crtc
, fb
, pipe_config
);
7460 /* Pass our mode to the connectors and the CRTC to give them a chance to
7461 * adjust it according to limitations or connector properties, and also
7462 * a chance to reject the mode entirely.
7464 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7467 if (&encoder
->new_crtc
->base
!= crtc
)
7470 if (encoder
->compute_config
) {
7471 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7472 DRM_DEBUG_KMS("Encoder config failure\n");
7479 encoder_funcs
= encoder
->base
.helper_private
;
7480 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7481 &pipe_config
->requested_mode
,
7482 &pipe_config
->adjusted_mode
))) {
7483 DRM_DEBUG_KMS("Encoder fixup failed\n");
7488 /* temporary hack until the DP code doesn't use the 6BPC flag any more */
7489 if (pipe_config
->adjusted_mode
.private_flags
& INTEL_MODE_DP_FORCE_6BPC
)
7490 pipe_config
->pipe_bpp
= 6*8;
7492 if (!(intel_crtc_compute_config(crtc
, pipe_config
))) {
7493 DRM_DEBUG_KMS("CRTC fixup failed\n");
7496 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7498 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7499 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7500 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7505 return ERR_PTR(-EINVAL
);
7508 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7509 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7511 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7512 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7514 struct intel_crtc
*intel_crtc
;
7515 struct drm_device
*dev
= crtc
->dev
;
7516 struct intel_encoder
*encoder
;
7517 struct intel_connector
*connector
;
7518 struct drm_crtc
*tmp_crtc
;
7520 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7522 /* Check which crtcs have changed outputs connected to them, these need
7523 * to be part of the prepare_pipes mask. We don't (yet) support global
7524 * modeset across multiple crtcs, so modeset_pipes will only have one
7525 * bit set at most. */
7526 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7528 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7531 if (connector
->base
.encoder
) {
7532 tmp_crtc
= connector
->base
.encoder
->crtc
;
7534 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7537 if (connector
->new_encoder
)
7539 1 << connector
->new_encoder
->new_crtc
->pipe
;
7542 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7544 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7547 if (encoder
->base
.crtc
) {
7548 tmp_crtc
= encoder
->base
.crtc
;
7550 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7553 if (encoder
->new_crtc
)
7554 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7557 /* Check for any pipes that will be fully disabled ... */
7558 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7562 /* Don't try to disable disabled crtcs. */
7563 if (!intel_crtc
->base
.enabled
)
7566 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7568 if (encoder
->new_crtc
== intel_crtc
)
7573 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7577 /* set_mode is also used to update properties on life display pipes. */
7578 intel_crtc
= to_intel_crtc(crtc
);
7580 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7582 /* We only support modeset on one single crtc, hence we need to do that
7583 * only for the passed in crtc iff we change anything else than just
7586 * This is actually not true, to be fully compatible with the old crtc
7587 * helper we automatically disable _any_ output (i.e. doesn't need to be
7588 * connected to the crtc we're modesetting on) if it's disconnected.
7589 * Which is a rather nutty api (since changed the output configuration
7590 * without userspace's explicit request can lead to confusion), but
7591 * alas. Hence we currently need to modeset on all pipes we prepare. */
7593 *modeset_pipes
= *prepare_pipes
;
7595 /* ... and mask these out. */
7596 *modeset_pipes
&= ~(*disable_pipes
);
7597 *prepare_pipes
&= ~(*disable_pipes
);
7600 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7602 struct drm_encoder
*encoder
;
7603 struct drm_device
*dev
= crtc
->dev
;
7605 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7606 if (encoder
->crtc
== crtc
)
7613 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7615 struct intel_encoder
*intel_encoder
;
7616 struct intel_crtc
*intel_crtc
;
7617 struct drm_connector
*connector
;
7619 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7621 if (!intel_encoder
->base
.crtc
)
7624 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7626 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7627 intel_encoder
->connectors_active
= false;
7630 intel_modeset_commit_output_state(dev
);
7632 /* Update computed state. */
7633 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7635 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7638 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7639 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7642 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7644 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7645 struct drm_property
*dpms_property
=
7646 dev
->mode_config
.dpms_property
;
7648 connector
->dpms
= DRM_MODE_DPMS_ON
;
7649 drm_object_property_set_value(&connector
->base
,
7653 intel_encoder
= to_intel_encoder(connector
->encoder
);
7654 intel_encoder
->connectors_active
= true;
7660 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7661 list_for_each_entry((intel_crtc), \
7662 &(dev)->mode_config.crtc_list, \
7664 if (mask & (1 <<(intel_crtc)->pipe)) \
7667 intel_modeset_check_state(struct drm_device
*dev
)
7669 struct intel_crtc
*crtc
;
7670 struct intel_encoder
*encoder
;
7671 struct intel_connector
*connector
;
7673 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7675 /* This also checks the encoder/connector hw state with the
7676 * ->get_hw_state callbacks. */
7677 intel_connector_check_state(connector
);
7679 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7680 "connector's staged encoder doesn't match current encoder\n");
7683 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7685 bool enabled
= false;
7686 bool active
= false;
7687 enum pipe pipe
, tracked_pipe
;
7689 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7690 encoder
->base
.base
.id
,
7691 drm_get_encoder_name(&encoder
->base
));
7693 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7694 "encoder's stage crtc doesn't match current crtc\n");
7695 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7696 "encoder's active_connectors set, but no crtc\n");
7698 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7700 if (connector
->base
.encoder
!= &encoder
->base
)
7703 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7706 WARN(!!encoder
->base
.crtc
!= enabled
,
7707 "encoder's enabled state mismatch "
7708 "(expected %i, found %i)\n",
7709 !!encoder
->base
.crtc
, enabled
);
7710 WARN(active
&& !encoder
->base
.crtc
,
7711 "active encoder with no crtc\n");
7713 WARN(encoder
->connectors_active
!= active
,
7714 "encoder's computed active state doesn't match tracked active state "
7715 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7717 active
= encoder
->get_hw_state(encoder
, &pipe
);
7718 WARN(active
!= encoder
->connectors_active
,
7719 "encoder's hw state doesn't match sw tracking "
7720 "(expected %i, found %i)\n",
7721 encoder
->connectors_active
, active
);
7723 if (!encoder
->base
.crtc
)
7726 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7727 WARN(active
&& pipe
!= tracked_pipe
,
7728 "active encoder's pipe doesn't match"
7729 "(expected %i, found %i)\n",
7730 tracked_pipe
, pipe
);
7734 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7736 bool enabled
= false;
7737 bool active
= false;
7739 DRM_DEBUG_KMS("[CRTC:%d]\n",
7740 crtc
->base
.base
.id
);
7742 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7743 "active crtc, but not enabled in sw tracking\n");
7745 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7747 if (encoder
->base
.crtc
!= &crtc
->base
)
7750 if (encoder
->connectors_active
)
7753 WARN(active
!= crtc
->active
,
7754 "crtc's computed active state doesn't match tracked active state "
7755 "(expected %i, found %i)\n", active
, crtc
->active
);
7756 WARN(enabled
!= crtc
->base
.enabled
,
7757 "crtc's computed enabled state doesn't match tracked enabled state "
7758 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7760 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7764 int intel_set_mode(struct drm_crtc
*crtc
,
7765 struct drm_display_mode
*mode
,
7766 int x
, int y
, struct drm_framebuffer
*fb
)
7768 struct drm_device
*dev
= crtc
->dev
;
7769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7770 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
7771 struct intel_crtc_config
*pipe_config
= NULL
;
7772 struct intel_crtc
*intel_crtc
;
7773 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7776 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
7779 saved_hwmode
= saved_mode
+ 1;
7781 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7782 &prepare_pipes
, &disable_pipes
);
7784 *saved_hwmode
= crtc
->hwmode
;
7785 *saved_mode
= crtc
->mode
;
7787 /* Hack: Because we don't (yet) support global modeset on multiple
7788 * crtcs, we don't keep track of the new mode for more than one crtc.
7789 * Hence simply check whether any bit is set in modeset_pipes in all the
7790 * pieces of code that are not yet converted to deal with mutliple crtcs
7791 * changing their mode at the same time. */
7792 if (modeset_pipes
) {
7793 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
7794 if (IS_ERR(pipe_config
)) {
7795 ret
= PTR_ERR(pipe_config
);
7802 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7803 modeset_pipes
, prepare_pipes
, disable_pipes
);
7805 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7806 intel_crtc_disable(&intel_crtc
->base
);
7808 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7809 if (intel_crtc
->base
.enabled
)
7810 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7813 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7814 * to set it here already despite that we pass it down the callchain.
7816 if (modeset_pipes
) {
7818 /* mode_set/enable/disable functions rely on a correct pipe
7820 to_intel_crtc(crtc
)->config
= *pipe_config
;
7823 /* Only after disabling all output pipelines that will be changed can we
7824 * update the the output configuration. */
7825 intel_modeset_update_state(dev
, prepare_pipes
);
7827 if (dev_priv
->display
.modeset_global_resources
)
7828 dev_priv
->display
.modeset_global_resources(dev
);
7830 /* Set up the DPLL and any encoders state that needs to adjust or depend
7833 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7834 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
7840 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7841 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7842 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7844 if (modeset_pipes
) {
7845 /* Store real post-adjustment hardware mode. */
7846 crtc
->hwmode
= pipe_config
->adjusted_mode
;
7848 /* Calculate and store various constants which
7849 * are later needed by vblank and swap-completion
7850 * timestamping. They are derived from true hwmode.
7852 drm_calc_timestamping_constants(crtc
);
7855 /* FIXME: add subpixel order */
7857 if (ret
&& crtc
->enabled
) {
7858 crtc
->hwmode
= *saved_hwmode
;
7859 crtc
->mode
= *saved_mode
;
7861 intel_modeset_check_state(dev
);
7870 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
7872 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
7875 #undef for_each_intel_crtc_masked
7877 static void intel_set_config_free(struct intel_set_config
*config
)
7882 kfree(config
->save_connector_encoders
);
7883 kfree(config
->save_encoder_crtcs
);
7887 static int intel_set_config_save_state(struct drm_device
*dev
,
7888 struct intel_set_config
*config
)
7890 struct drm_encoder
*encoder
;
7891 struct drm_connector
*connector
;
7894 config
->save_encoder_crtcs
=
7895 kcalloc(dev
->mode_config
.num_encoder
,
7896 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7897 if (!config
->save_encoder_crtcs
)
7900 config
->save_connector_encoders
=
7901 kcalloc(dev
->mode_config
.num_connector
,
7902 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7903 if (!config
->save_connector_encoders
)
7906 /* Copy data. Note that driver private data is not affected.
7907 * Should anything bad happen only the expected state is
7908 * restored, not the drivers personal bookkeeping.
7911 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7912 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7916 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7917 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7923 static void intel_set_config_restore_state(struct drm_device
*dev
,
7924 struct intel_set_config
*config
)
7926 struct intel_encoder
*encoder
;
7927 struct intel_connector
*connector
;
7931 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7933 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7937 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7938 connector
->new_encoder
=
7939 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7944 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7945 struct intel_set_config
*config
)
7948 /* We should be able to check here if the fb has the same properties
7949 * and then just flip_or_move it */
7950 if (set
->crtc
->fb
!= set
->fb
) {
7951 /* If we have no fb then treat it as a full mode set */
7952 if (set
->crtc
->fb
== NULL
) {
7953 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7954 config
->mode_changed
= true;
7955 } else if (set
->fb
== NULL
) {
7956 config
->mode_changed
= true;
7957 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7958 config
->mode_changed
= true;
7959 } else if (set
->fb
->bits_per_pixel
!=
7960 set
->crtc
->fb
->bits_per_pixel
) {
7961 config
->mode_changed
= true;
7963 config
->fb_changed
= true;
7966 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7967 config
->fb_changed
= true;
7969 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7970 DRM_DEBUG_KMS("modes are different, full mode set\n");
7971 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7972 drm_mode_debug_printmodeline(set
->mode
);
7973 config
->mode_changed
= true;
7978 intel_modeset_stage_output_state(struct drm_device
*dev
,
7979 struct drm_mode_set
*set
,
7980 struct intel_set_config
*config
)
7982 struct drm_crtc
*new_crtc
;
7983 struct intel_connector
*connector
;
7984 struct intel_encoder
*encoder
;
7987 /* The upper layers ensure that we either disable a crtc or have a list
7988 * of connectors. For paranoia, double-check this. */
7989 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7990 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
7993 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7995 /* Otherwise traverse passed in connector list and get encoders
7997 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7998 if (set
->connectors
[ro
] == &connector
->base
) {
7999 connector
->new_encoder
= connector
->encoder
;
8004 /* If we disable the crtc, disable all its connectors. Also, if
8005 * the connector is on the changing crtc but not on the new
8006 * connector list, disable it. */
8007 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8008 connector
->base
.encoder
&&
8009 connector
->base
.encoder
->crtc
== set
->crtc
) {
8010 connector
->new_encoder
= NULL
;
8012 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8013 connector
->base
.base
.id
,
8014 drm_get_connector_name(&connector
->base
));
8018 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8019 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8020 config
->mode_changed
= true;
8023 /* connector->new_encoder is now updated for all connectors. */
8025 /* Update crtc of enabled connectors. */
8027 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8029 if (!connector
->new_encoder
)
8032 new_crtc
= connector
->new_encoder
->base
.crtc
;
8034 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8035 if (set
->connectors
[ro
] == &connector
->base
)
8036 new_crtc
= set
->crtc
;
8039 /* Make sure the new CRTC will work with the encoder */
8040 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8044 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8047 connector
->base
.base
.id
,
8048 drm_get_connector_name(&connector
->base
),
8052 /* Check for any encoders that needs to be disabled. */
8053 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8055 list_for_each_entry(connector
,
8056 &dev
->mode_config
.connector_list
,
8058 if (connector
->new_encoder
== encoder
) {
8059 WARN_ON(!connector
->new_encoder
->new_crtc
);
8064 encoder
->new_crtc
= NULL
;
8066 /* Only now check for crtc changes so we don't miss encoders
8067 * that will be disabled. */
8068 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8069 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8070 config
->mode_changed
= true;
8073 /* Now we've also updated encoder->new_crtc for all encoders. */
8078 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8080 struct drm_device
*dev
;
8081 struct drm_mode_set save_set
;
8082 struct intel_set_config
*config
;
8087 BUG_ON(!set
->crtc
->helper_private
);
8089 /* Enforce sane interface api - has been abused by the fb helper. */
8090 BUG_ON(!set
->mode
&& set
->fb
);
8091 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8094 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8095 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8096 (int)set
->num_connectors
, set
->x
, set
->y
);
8098 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8101 dev
= set
->crtc
->dev
;
8104 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8108 ret
= intel_set_config_save_state(dev
, config
);
8112 save_set
.crtc
= set
->crtc
;
8113 save_set
.mode
= &set
->crtc
->mode
;
8114 save_set
.x
= set
->crtc
->x
;
8115 save_set
.y
= set
->crtc
->y
;
8116 save_set
.fb
= set
->crtc
->fb
;
8118 /* Compute whether we need a full modeset, only an fb base update or no
8119 * change at all. In the future we might also check whether only the
8120 * mode changed, e.g. for LVDS where we only change the panel fitter in
8122 intel_set_config_compute_mode_changes(set
, config
);
8124 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8128 if (config
->mode_changed
) {
8130 DRM_DEBUG_KMS("attempting to set mode from"
8132 drm_mode_debug_printmodeline(set
->mode
);
8135 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8136 set
->x
, set
->y
, set
->fb
);
8138 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8139 set
->crtc
->base
.id
, ret
);
8142 } else if (config
->fb_changed
) {
8143 intel_crtc_wait_for_pending_flips(set
->crtc
);
8145 ret
= intel_pipe_set_base(set
->crtc
,
8146 set
->x
, set
->y
, set
->fb
);
8149 intel_set_config_free(config
);
8154 intel_set_config_restore_state(dev
, config
);
8156 /* Try to restore the config */
8157 if (config
->mode_changed
&&
8158 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8159 save_set
.x
, save_set
.y
, save_set
.fb
))
8160 DRM_ERROR("failed to restore config after modeset failure\n");
8163 intel_set_config_free(config
);
8167 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8168 .cursor_set
= intel_crtc_cursor_set
,
8169 .cursor_move
= intel_crtc_cursor_move
,
8170 .gamma_set
= intel_crtc_gamma_set
,
8171 .set_config
= intel_crtc_set_config
,
8172 .destroy
= intel_crtc_destroy
,
8173 .page_flip
= intel_crtc_page_flip
,
8176 static void intel_cpu_pll_init(struct drm_device
*dev
)
8179 intel_ddi_pll_init(dev
);
8182 static void intel_pch_pll_init(struct drm_device
*dev
)
8184 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8187 if (dev_priv
->num_pch_pll
== 0) {
8188 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8192 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8193 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8194 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8195 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8199 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8201 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8202 struct intel_crtc
*intel_crtc
;
8205 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8206 if (intel_crtc
== NULL
)
8209 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8211 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8212 for (i
= 0; i
< 256; i
++) {
8213 intel_crtc
->lut_r
[i
] = i
;
8214 intel_crtc
->lut_g
[i
] = i
;
8215 intel_crtc
->lut_b
[i
] = i
;
8218 /* Swap pipes & planes for FBC on pre-965 */
8219 intel_crtc
->pipe
= pipe
;
8220 intel_crtc
->plane
= pipe
;
8221 intel_crtc
->cpu_transcoder
= pipe
;
8222 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8223 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8224 intel_crtc
->plane
= !pipe
;
8227 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8228 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8229 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8230 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8232 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8235 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8236 struct drm_file
*file
)
8238 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8239 struct drm_mode_object
*drmmode_obj
;
8240 struct intel_crtc
*crtc
;
8242 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8245 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8246 DRM_MODE_OBJECT_CRTC
);
8249 DRM_ERROR("no such CRTC id\n");
8253 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8254 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8259 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8261 struct drm_device
*dev
= encoder
->base
.dev
;
8262 struct intel_encoder
*source_encoder
;
8266 list_for_each_entry(source_encoder
,
8267 &dev
->mode_config
.encoder_list
, base
.head
) {
8269 if (encoder
== source_encoder
)
8270 index_mask
|= (1 << entry
);
8272 /* Intel hw has only one MUX where enocoders could be cloned. */
8273 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8274 index_mask
|= (1 << entry
);
8282 static bool has_edp_a(struct drm_device
*dev
)
8284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8286 if (!IS_MOBILE(dev
))
8289 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8293 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8299 static void intel_setup_outputs(struct drm_device
*dev
)
8301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8302 struct intel_encoder
*encoder
;
8303 bool dpd_is_edp
= false;
8306 has_lvds
= intel_lvds_init(dev
);
8307 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8308 /* disable the panel fitter on everything but LVDS */
8309 I915_WRITE(PFIT_CONTROL
, 0);
8312 if (!(HAS_DDI(dev
) && (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)))
8313 intel_crt_init(dev
);
8318 /* Haswell uses DDI functions to detect digital outputs */
8319 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8320 /* DDI A only supports eDP */
8322 intel_ddi_init(dev
, PORT_A
);
8324 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8326 found
= I915_READ(SFUSE_STRAP
);
8328 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8329 intel_ddi_init(dev
, PORT_B
);
8330 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8331 intel_ddi_init(dev
, PORT_C
);
8332 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8333 intel_ddi_init(dev
, PORT_D
);
8334 } else if (HAS_PCH_SPLIT(dev
)) {
8336 dpd_is_edp
= intel_dpd_is_edp(dev
);
8339 intel_dp_init(dev
, DP_A
, PORT_A
);
8341 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
8342 /* PCH SDVOB multiplex with HDMIB */
8343 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8345 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8346 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8347 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8350 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
8351 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8353 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
8354 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8356 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8357 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8359 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8360 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8361 } else if (IS_VALLEYVIEW(dev
)) {
8362 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8363 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8364 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8366 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
8367 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8369 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8370 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8372 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8375 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8376 DRM_DEBUG_KMS("probing SDVOB\n");
8377 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8378 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8379 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8380 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8383 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8384 DRM_DEBUG_KMS("probing DP_B\n");
8385 intel_dp_init(dev
, DP_B
, PORT_B
);
8389 /* Before G4X SDVOC doesn't have its own detect register */
8391 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8392 DRM_DEBUG_KMS("probing SDVOC\n");
8393 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8396 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8398 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8399 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8400 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8402 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8403 DRM_DEBUG_KMS("probing DP_C\n");
8404 intel_dp_init(dev
, DP_C
, PORT_C
);
8408 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8409 (I915_READ(DP_D
) & DP_DETECTED
)) {
8410 DRM_DEBUG_KMS("probing DP_D\n");
8411 intel_dp_init(dev
, DP_D
, PORT_D
);
8413 } else if (IS_GEN2(dev
))
8414 intel_dvo_init(dev
);
8416 if (SUPPORTS_TV(dev
))
8419 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8420 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8421 encoder
->base
.possible_clones
=
8422 intel_encoder_clones(encoder
);
8425 intel_init_pch_refclk(dev
);
8427 drm_helper_move_panel_connectors_to_head(dev
);
8430 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8432 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8434 drm_framebuffer_cleanup(fb
);
8435 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8440 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8441 struct drm_file
*file
,
8442 unsigned int *handle
)
8444 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8445 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8447 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8450 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8451 .destroy
= intel_user_framebuffer_destroy
,
8452 .create_handle
= intel_user_framebuffer_create_handle
,
8455 int intel_framebuffer_init(struct drm_device
*dev
,
8456 struct intel_framebuffer
*intel_fb
,
8457 struct drm_mode_fb_cmd2
*mode_cmd
,
8458 struct drm_i915_gem_object
*obj
)
8462 if (obj
->tiling_mode
== I915_TILING_Y
) {
8463 DRM_DEBUG("hardware does not support tiling Y\n");
8467 if (mode_cmd
->pitches
[0] & 63) {
8468 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8469 mode_cmd
->pitches
[0]);
8473 /* FIXME <= Gen4 stride limits are bit unclear */
8474 if (mode_cmd
->pitches
[0] > 32768) {
8475 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8476 mode_cmd
->pitches
[0]);
8480 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8481 mode_cmd
->pitches
[0] != obj
->stride
) {
8482 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8483 mode_cmd
->pitches
[0], obj
->stride
);
8487 /* Reject formats not supported by any plane early. */
8488 switch (mode_cmd
->pixel_format
) {
8490 case DRM_FORMAT_RGB565
:
8491 case DRM_FORMAT_XRGB8888
:
8492 case DRM_FORMAT_ARGB8888
:
8494 case DRM_FORMAT_XRGB1555
:
8495 case DRM_FORMAT_ARGB1555
:
8496 if (INTEL_INFO(dev
)->gen
> 3) {
8497 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8501 case DRM_FORMAT_XBGR8888
:
8502 case DRM_FORMAT_ABGR8888
:
8503 case DRM_FORMAT_XRGB2101010
:
8504 case DRM_FORMAT_ARGB2101010
:
8505 case DRM_FORMAT_XBGR2101010
:
8506 case DRM_FORMAT_ABGR2101010
:
8507 if (INTEL_INFO(dev
)->gen
< 4) {
8508 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8512 case DRM_FORMAT_YUYV
:
8513 case DRM_FORMAT_UYVY
:
8514 case DRM_FORMAT_YVYU
:
8515 case DRM_FORMAT_VYUY
:
8516 if (INTEL_INFO(dev
)->gen
< 5) {
8517 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8522 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8526 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8527 if (mode_cmd
->offsets
[0] != 0)
8530 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8531 intel_fb
->obj
= obj
;
8533 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8535 DRM_ERROR("framebuffer init failed %d\n", ret
);
8542 static struct drm_framebuffer
*
8543 intel_user_framebuffer_create(struct drm_device
*dev
,
8544 struct drm_file
*filp
,
8545 struct drm_mode_fb_cmd2
*mode_cmd
)
8547 struct drm_i915_gem_object
*obj
;
8549 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8550 mode_cmd
->handles
[0]));
8551 if (&obj
->base
== NULL
)
8552 return ERR_PTR(-ENOENT
);
8554 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8557 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8558 .fb_create
= intel_user_framebuffer_create
,
8559 .output_poll_changed
= intel_fb_output_poll_changed
,
8562 /* Set up chip specific display functions */
8563 static void intel_init_display(struct drm_device
*dev
)
8565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8568 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8569 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8570 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8571 dev_priv
->display
.off
= haswell_crtc_off
;
8572 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8573 } else if (HAS_PCH_SPLIT(dev
)) {
8574 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8575 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8576 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8577 dev_priv
->display
.off
= ironlake_crtc_off
;
8578 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8580 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8581 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8582 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8583 dev_priv
->display
.off
= i9xx_crtc_off
;
8584 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8587 /* Returns the core display clock speed */
8588 if (IS_VALLEYVIEW(dev
))
8589 dev_priv
->display
.get_display_clock_speed
=
8590 valleyview_get_display_clock_speed
;
8591 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8592 dev_priv
->display
.get_display_clock_speed
=
8593 i945_get_display_clock_speed
;
8594 else if (IS_I915G(dev
))
8595 dev_priv
->display
.get_display_clock_speed
=
8596 i915_get_display_clock_speed
;
8597 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8598 dev_priv
->display
.get_display_clock_speed
=
8599 i9xx_misc_get_display_clock_speed
;
8600 else if (IS_I915GM(dev
))
8601 dev_priv
->display
.get_display_clock_speed
=
8602 i915gm_get_display_clock_speed
;
8603 else if (IS_I865G(dev
))
8604 dev_priv
->display
.get_display_clock_speed
=
8605 i865_get_display_clock_speed
;
8606 else if (IS_I85X(dev
))
8607 dev_priv
->display
.get_display_clock_speed
=
8608 i855_get_display_clock_speed
;
8610 dev_priv
->display
.get_display_clock_speed
=
8611 i830_get_display_clock_speed
;
8613 if (HAS_PCH_SPLIT(dev
)) {
8615 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8616 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8617 } else if (IS_GEN6(dev
)) {
8618 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8619 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8620 } else if (IS_IVYBRIDGE(dev
)) {
8621 /* FIXME: detect B0+ stepping and use auto training */
8622 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8623 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8624 dev_priv
->display
.modeset_global_resources
=
8625 ivb_modeset_global_resources
;
8626 } else if (IS_HASWELL(dev
)) {
8627 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8628 dev_priv
->display
.write_eld
= haswell_write_eld
;
8629 dev_priv
->display
.modeset_global_resources
=
8630 haswell_modeset_global_resources
;
8632 } else if (IS_G4X(dev
)) {
8633 dev_priv
->display
.write_eld
= g4x_write_eld
;
8636 /* Default just returns -ENODEV to indicate unsupported */
8637 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8639 switch (INTEL_INFO(dev
)->gen
) {
8641 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8645 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8650 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8654 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8657 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8663 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8664 * resume, or other times. This quirk makes sure that's the case for
8667 static void quirk_pipea_force(struct drm_device
*dev
)
8669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8671 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8672 DRM_INFO("applying pipe a force quirk\n");
8676 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8678 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8681 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8682 DRM_INFO("applying lvds SSC disable quirk\n");
8686 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8689 static void quirk_invert_brightness(struct drm_device
*dev
)
8691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8692 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8693 DRM_INFO("applying inverted panel brightness quirk\n");
8696 struct intel_quirk
{
8698 int subsystem_vendor
;
8699 int subsystem_device
;
8700 void (*hook
)(struct drm_device
*dev
);
8703 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8704 struct intel_dmi_quirk
{
8705 void (*hook
)(struct drm_device
*dev
);
8706 const struct dmi_system_id (*dmi_id_list
)[];
8709 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8711 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8715 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8717 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8719 .callback
= intel_dmi_reverse_brightness
,
8720 .ident
= "NCR Corporation",
8721 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8722 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8725 { } /* terminating entry */
8727 .hook
= quirk_invert_brightness
,
8731 static struct intel_quirk intel_quirks
[] = {
8732 /* HP Mini needs pipe A force quirk (LP: #322104) */
8733 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8735 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8736 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8738 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8739 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8741 /* 830/845 need to leave pipe A & dpll A up */
8742 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8743 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8745 /* Lenovo U160 cannot use SSC on LVDS */
8746 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8748 /* Sony Vaio Y cannot use SSC on LVDS */
8749 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8751 /* Acer Aspire 5734Z must invert backlight brightness */
8752 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8754 /* Acer/eMachines G725 */
8755 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
8757 /* Acer/eMachines e725 */
8758 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
8760 /* Acer/Packard Bell NCL20 */
8761 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
8763 /* Acer Aspire 4736Z */
8764 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
8767 static void intel_init_quirks(struct drm_device
*dev
)
8769 struct pci_dev
*d
= dev
->pdev
;
8772 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8773 struct intel_quirk
*q
= &intel_quirks
[i
];
8775 if (d
->device
== q
->device
&&
8776 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8777 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8778 (d
->subsystem_device
== q
->subsystem_device
||
8779 q
->subsystem_device
== PCI_ANY_ID
))
8782 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
8783 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
8784 intel_dmi_quirks
[i
].hook(dev
);
8788 /* Disable the VGA plane that we never use */
8789 static void i915_disable_vga(struct drm_device
*dev
)
8791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8793 u32 vga_reg
= i915_vgacntrl_reg(dev
);
8795 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8796 outb(SR01
, VGA_SR_INDEX
);
8797 sr1
= inb(VGA_SR_DATA
);
8798 outb(sr1
| 1<<5, VGA_SR_DATA
);
8799 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8802 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8803 POSTING_READ(vga_reg
);
8806 void intel_modeset_init_hw(struct drm_device
*dev
)
8808 intel_init_power_well(dev
);
8810 intel_prepare_ddi(dev
);
8812 intel_init_clock_gating(dev
);
8814 mutex_lock(&dev
->struct_mutex
);
8815 intel_enable_gt_powersave(dev
);
8816 mutex_unlock(&dev
->struct_mutex
);
8819 void intel_modeset_init(struct drm_device
*dev
)
8821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8824 drm_mode_config_init(dev
);
8826 dev
->mode_config
.min_width
= 0;
8827 dev
->mode_config
.min_height
= 0;
8829 dev
->mode_config
.preferred_depth
= 24;
8830 dev
->mode_config
.prefer_shadow
= 1;
8832 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8834 intel_init_quirks(dev
);
8838 intel_init_display(dev
);
8841 dev
->mode_config
.max_width
= 2048;
8842 dev
->mode_config
.max_height
= 2048;
8843 } else if (IS_GEN3(dev
)) {
8844 dev
->mode_config
.max_width
= 4096;
8845 dev
->mode_config
.max_height
= 4096;
8847 dev
->mode_config
.max_width
= 8192;
8848 dev
->mode_config
.max_height
= 8192;
8850 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
8852 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8853 INTEL_INFO(dev
)->num_pipes
,
8854 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
8856 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
8857 intel_crtc_init(dev
, i
);
8858 ret
= intel_plane_init(dev
, i
);
8860 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8863 intel_cpu_pll_init(dev
);
8864 intel_pch_pll_init(dev
);
8866 /* Just disable it once at startup */
8867 i915_disable_vga(dev
);
8868 intel_setup_outputs(dev
);
8870 /* Just in case the BIOS is doing something questionable. */
8871 intel_disable_fbc(dev
);
8875 intel_connector_break_all_links(struct intel_connector
*connector
)
8877 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8878 connector
->base
.encoder
= NULL
;
8879 connector
->encoder
->connectors_active
= false;
8880 connector
->encoder
->base
.crtc
= NULL
;
8883 static void intel_enable_pipe_a(struct drm_device
*dev
)
8885 struct intel_connector
*connector
;
8886 struct drm_connector
*crt
= NULL
;
8887 struct intel_load_detect_pipe load_detect_temp
;
8889 /* We can't just switch on the pipe A, we need to set things up with a
8890 * proper mode and output configuration. As a gross hack, enable pipe A
8891 * by enabling the load detect pipe once. */
8892 list_for_each_entry(connector
,
8893 &dev
->mode_config
.connector_list
,
8895 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8896 crt
= &connector
->base
;
8904 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8905 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8911 intel_check_plane_mapping(struct intel_crtc
*crtc
)
8913 struct drm_device
*dev
= crtc
->base
.dev
;
8914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8917 if (INTEL_INFO(dev
)->num_pipes
== 1)
8920 reg
= DSPCNTR(!crtc
->plane
);
8921 val
= I915_READ(reg
);
8923 if ((val
& DISPLAY_PLANE_ENABLE
) &&
8924 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8930 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8932 struct drm_device
*dev
= crtc
->base
.dev
;
8933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8936 /* Clear any frame start delays used for debugging left by the BIOS */
8937 reg
= PIPECONF(crtc
->cpu_transcoder
);
8938 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8940 /* We need to sanitize the plane -> pipe mapping first because this will
8941 * disable the crtc (and hence change the state) if it is wrong. Note
8942 * that gen4+ has a fixed plane -> pipe mapping. */
8943 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
8944 struct intel_connector
*connector
;
8947 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8948 crtc
->base
.base
.id
);
8950 /* Pipe has the wrong plane attached and the plane is active.
8951 * Temporarily change the plane mapping and disable everything
8953 plane
= crtc
->plane
;
8954 crtc
->plane
= !plane
;
8955 dev_priv
->display
.crtc_disable(&crtc
->base
);
8956 crtc
->plane
= plane
;
8958 /* ... and break all links. */
8959 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8961 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8964 intel_connector_break_all_links(connector
);
8967 WARN_ON(crtc
->active
);
8968 crtc
->base
.enabled
= false;
8971 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8972 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8973 /* BIOS forgot to enable pipe A, this mostly happens after
8974 * resume. Force-enable the pipe to fix this, the update_dpms
8975 * call below we restore the pipe to the right state, but leave
8976 * the required bits on. */
8977 intel_enable_pipe_a(dev
);
8980 /* Adjust the state of the output pipe according to whether we
8981 * have active connectors/encoders. */
8982 intel_crtc_update_dpms(&crtc
->base
);
8984 if (crtc
->active
!= crtc
->base
.enabled
) {
8985 struct intel_encoder
*encoder
;
8987 /* This can happen either due to bugs in the get_hw_state
8988 * functions or because the pipe is force-enabled due to the
8990 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8992 crtc
->base
.enabled
? "enabled" : "disabled",
8993 crtc
->active
? "enabled" : "disabled");
8995 crtc
->base
.enabled
= crtc
->active
;
8997 /* Because we only establish the connector -> encoder ->
8998 * crtc links if something is active, this means the
8999 * crtc is now deactivated. Break the links. connector
9000 * -> encoder links are only establish when things are
9001 * actually up, hence no need to break them. */
9002 WARN_ON(crtc
->active
);
9004 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9005 WARN_ON(encoder
->connectors_active
);
9006 encoder
->base
.crtc
= NULL
;
9011 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9013 struct intel_connector
*connector
;
9014 struct drm_device
*dev
= encoder
->base
.dev
;
9016 /* We need to check both for a crtc link (meaning that the
9017 * encoder is active and trying to read from a pipe) and the
9018 * pipe itself being active. */
9019 bool has_active_crtc
= encoder
->base
.crtc
&&
9020 to_intel_crtc(encoder
->base
.crtc
)->active
;
9022 if (encoder
->connectors_active
&& !has_active_crtc
) {
9023 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9024 encoder
->base
.base
.id
,
9025 drm_get_encoder_name(&encoder
->base
));
9027 /* Connector is active, but has no active pipe. This is
9028 * fallout from our resume register restoring. Disable
9029 * the encoder manually again. */
9030 if (encoder
->base
.crtc
) {
9031 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9032 encoder
->base
.base
.id
,
9033 drm_get_encoder_name(&encoder
->base
));
9034 encoder
->disable(encoder
);
9037 /* Inconsistent output/port/pipe state happens presumably due to
9038 * a bug in one of the get_hw_state functions. Or someplace else
9039 * in our code, like the register restore mess on resume. Clamp
9040 * things to off as a safer default. */
9041 list_for_each_entry(connector
,
9042 &dev
->mode_config
.connector_list
,
9044 if (connector
->encoder
!= encoder
)
9047 intel_connector_break_all_links(connector
);
9050 /* Enabled encoders without active connectors will be fixed in
9051 * the crtc fixup. */
9054 void i915_redisable_vga(struct drm_device
*dev
)
9056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9057 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9059 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9060 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9061 i915_disable_vga(dev
);
9065 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9066 * and i915 state tracking structures. */
9067 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9073 struct drm_plane
*plane
;
9074 struct intel_crtc
*crtc
;
9075 struct intel_encoder
*encoder
;
9076 struct intel_connector
*connector
;
9079 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9081 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9082 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9083 case TRANS_DDI_EDP_INPUT_A_ON
:
9084 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9087 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9090 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9094 /* A bogus value has been programmed, disable
9096 WARN(1, "Bogus eDP source %08x\n", tmp
);
9097 intel_ddi_disable_transcoder_func(dev_priv
,
9102 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9103 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
9105 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9111 for_each_pipe(pipe
) {
9112 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9114 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
9115 if (tmp
& PIPECONF_ENABLE
)
9116 crtc
->active
= true;
9118 crtc
->active
= false;
9120 crtc
->base
.enabled
= crtc
->active
;
9122 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9124 crtc
->active
? "enabled" : "disabled");
9128 intel_ddi_setup_hw_pll_state(dev
);
9130 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9134 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9135 encoder
->base
.crtc
=
9136 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9138 encoder
->base
.crtc
= NULL
;
9141 encoder
->connectors_active
= false;
9142 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9143 encoder
->base
.base
.id
,
9144 drm_get_encoder_name(&encoder
->base
),
9145 encoder
->base
.crtc
? "enabled" : "disabled",
9149 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9151 if (connector
->get_hw_state(connector
)) {
9152 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9153 connector
->encoder
->connectors_active
= true;
9154 connector
->base
.encoder
= &connector
->encoder
->base
;
9156 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9157 connector
->base
.encoder
= NULL
;
9159 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9160 connector
->base
.base
.id
,
9161 drm_get_connector_name(&connector
->base
),
9162 connector
->base
.encoder
? "enabled" : "disabled");
9165 /* HW state is read out, now we need to sanitize this mess. */
9166 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9168 intel_sanitize_encoder(encoder
);
9171 for_each_pipe(pipe
) {
9172 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9173 intel_sanitize_crtc(crtc
);
9176 if (force_restore
) {
9177 for_each_pipe(pipe
) {
9178 struct drm_crtc
*crtc
=
9179 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9180 intel_crtc_restore_mode(crtc
);
9182 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
9183 intel_plane_restore(plane
);
9185 i915_redisable_vga(dev
);
9187 intel_modeset_update_staged_output_state(dev
);
9190 intel_modeset_check_state(dev
);
9192 drm_mode_config_reset(dev
);
9195 void intel_modeset_gem_init(struct drm_device
*dev
)
9197 intel_modeset_init_hw(dev
);
9199 intel_setup_overlay(dev
);
9201 intel_modeset_setup_hw_state(dev
, false);
9204 void intel_modeset_cleanup(struct drm_device
*dev
)
9206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9207 struct drm_crtc
*crtc
;
9208 struct intel_crtc
*intel_crtc
;
9210 drm_kms_helper_poll_fini(dev
);
9211 mutex_lock(&dev
->struct_mutex
);
9213 intel_unregister_dsm_handler();
9216 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9217 /* Skip inactive CRTCs */
9221 intel_crtc
= to_intel_crtc(crtc
);
9222 intel_increase_pllclock(crtc
);
9225 intel_disable_fbc(dev
);
9227 intel_disable_gt_powersave(dev
);
9229 ironlake_teardown_rc6(dev
);
9231 if (IS_VALLEYVIEW(dev
))
9234 mutex_unlock(&dev
->struct_mutex
);
9236 /* Disable the irq before mode object teardown, for the irq might
9237 * enqueue unpin/hotplug work. */
9238 drm_irq_uninstall(dev
);
9239 cancel_work_sync(&dev_priv
->hotplug_work
);
9240 cancel_work_sync(&dev_priv
->rps
.work
);
9242 /* flush any delayed tasks or pending work */
9243 flush_scheduled_work();
9245 drm_mode_config_cleanup(dev
);
9247 intel_cleanup_overlay(dev
);
9251 * Return which encoder is currently attached for connector.
9253 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9255 return &intel_attached_encoder(connector
)->base
;
9258 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9259 struct intel_encoder
*encoder
)
9261 connector
->encoder
= encoder
;
9262 drm_mode_connector_attach_encoder(&connector
->base
,
9267 * set vga decode state - true == enable VGA decode
9269 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9274 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9276 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9278 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9279 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9283 #ifdef CONFIG_DEBUG_FS
9284 #include <linux/seq_file.h>
9286 struct intel_display_error_state
{
9287 struct intel_cursor_error_state
{
9292 } cursor
[I915_MAX_PIPES
];
9294 struct intel_pipe_error_state
{
9304 } pipe
[I915_MAX_PIPES
];
9306 struct intel_plane_error_state
{
9314 } plane
[I915_MAX_PIPES
];
9317 struct intel_display_error_state
*
9318 intel_display_capture_error_state(struct drm_device
*dev
)
9320 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9321 struct intel_display_error_state
*error
;
9322 enum transcoder cpu_transcoder
;
9325 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9330 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9332 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
9333 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9334 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9335 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9337 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
9338 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
9339 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
9342 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9343 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9344 if (INTEL_INFO(dev
)->gen
<= 3) {
9345 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9346 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9348 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9349 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9350 if (INTEL_INFO(dev
)->gen
>= 4) {
9351 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9352 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9355 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9356 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9357 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9358 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9359 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9360 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9361 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9362 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9369 intel_display_print_error_state(struct seq_file
*m
,
9370 struct drm_device
*dev
,
9371 struct intel_display_error_state
*error
)
9375 seq_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
9377 seq_printf(m
, "Pipe [%d]:\n", i
);
9378 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9379 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9380 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9381 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9382 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9383 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9384 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9385 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9387 seq_printf(m
, "Plane [%d]:\n", i
);
9388 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9389 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9390 if (INTEL_INFO(dev
)->gen
<= 3) {
9391 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9392 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9394 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9395 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9396 if (INTEL_INFO(dev
)->gen
>= 4) {
9397 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9398 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9401 seq_printf(m
, "Cursor [%d]:\n", i
);
9402 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9403 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9404 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);