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Merge branch 'for-linus' into for-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151 {
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
313 },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
340 },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
354 },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503 return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
513
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
516 return true;
517
518 return false;
519 }
520
521 /**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
529 {
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
535
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
541
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
544 return true;
545 }
546
547 WARN_ON(num_connectors == 0);
548
549 return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
570 } else
571 limit = &intel_limits_ironlake_dac;
572
573 return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
581
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
585 else
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
594
595 return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
603
604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
613 else
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
624 } else {
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
629 else
630 limit = &intel_limits_i8xx_dac;
631 }
632 return limit;
633 }
634
635 /*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
649 return 0;
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653 return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666 return 0;
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670 return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
678 return 0;
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682 return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
690 return 0;
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
707 {
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
716
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
735
736 return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
743 {
744 struct drm_device *dev = crtc_state->base.crtc->dev;
745
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747 /*
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
751 */
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
754 else
755 return limit->p2.p2_slow;
756 } else {
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
759 else
760 return limit->p2.p2_fast;
761 }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
816 {
817 struct drm_device *dev = crtc_state->base.crtc->dev;
818 intel_clock_t clock;
819 int err = target;
820
821 memset(best_clock, 0, sizeof(*best_clock));
822
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
833 int this_err;
834
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
838 continue;
839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct drm_device *dev = crtc_state->base.crtc->dev;
863 intel_clock_t clock;
864 int max_n;
865 bool found = false;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
868
869 memset(best_clock, 0, sizeof(*best_clock));
870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
888 continue;
889
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
901 return found;
902 }
903
904 /*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913 {
914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949 {
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
952 intel_clock_t clock;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
956 bool found = false;
957
958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
961
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970 unsigned int ppm;
971
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
975 vlv_calc_dpll_params(refclk, &clock);
976
977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
979 continue;
980
981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
986
987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
990 }
991 }
992 }
993 }
994
995 return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
1038 chv_calc_dpll_params(refclk, &clock);
1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
1050 }
1051 }
1052
1053 return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058 {
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1074 *
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
1081 */
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088 {
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092 return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 i915_reg_t reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
1108 msleep(5);
1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112 }
1113
1114 /*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1128 *
1129 */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 i915_reg_t reg = PIPECONF(cpu_transcoder);
1139
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
1143 WARN(1, "pipe_off wait timed out\n");
1144 } else {
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153 return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159 {
1160 u32 val;
1161 bool cur_state;
1162
1163 val = I915_READ(DPLL(pipe));
1164 cur_state = !!(val & DPLL_VCO_ENABLE);
1165 I915_STATE_WARN(cur_state != state,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173 u32 val;
1174 bool cur_state;
1175
1176 mutex_lock(&dev_priv->sb_lock);
1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178 mutex_unlock(&dev_priv->sb_lock);
1179
1180 cur_state = val & DSI_PLL_VCO_EN;
1181 I915_STATE_WARN(cur_state != state,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193 if (crtc->config->shared_dpll < 0)
1194 return NULL;
1195
1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
1203 {
1204 bool cur_state;
1205 struct intel_dpll_hw_state hw_state;
1206
1207 if (WARN (!pll,
1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
1209 return;
1210
1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212 I915_STATE_WARN(cur_state != state,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 bool cur_state;
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
1223
1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228 } else {
1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
1232 I915_STATE_WARN(cur_state != state,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(FDI_RX_CTL(pipe));
1246 cur_state = !!(val & FDI_RX_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261 return;
1262
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv->dev))
1265 return;
1266
1267 val = I915_READ(FDI_TX_CTL(pipe));
1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 u32 val;
1275 bool cur_state;
1276
1277 val = I915_READ(FDI_RX_CTL(pipe));
1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279 I915_STATE_WARN(cur_state != state,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286 {
1287 struct drm_device *dev = dev_priv->dev;
1288 i915_reg_t pp_reg;
1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
1291 bool locked = true;
1292
1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
1299 pp_reg = PCH_PP_CONTROL;
1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
1310 } else {
1311 pp_reg = PP_CONTROL;
1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319 locked = false;
1320
1321 I915_STATE_WARN(panel_pipe == pipe && locked,
1322 "panel assertion failure, pipe %c regs locked\n",
1323 pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
1332 if (IS_845G(dev) || IS_I865G(dev))
1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334 else
1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
1346 {
1347 bool cur_state;
1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
1350
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354 state = true;
1355
1356 if (!intel_display_power_is_enabled(dev_priv,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358 cur_state = false;
1359 } else {
1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
1364 I915_STATE_WARN(cur_state != state,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
1371 {
1372 u32 val;
1373 bool cur_state;
1374
1375 val = I915_READ(DSPCNTR(plane));
1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377 I915_STATE_WARN(cur_state != state,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 struct drm_device *dev = dev_priv->dev;
1389 int i;
1390
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
1393 u32 val = I915_READ(DSPCNTR(pipe));
1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
1397 return;
1398 }
1399
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv, i) {
1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404 DISPPLANE_SEL_PIPE_SHIFT;
1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
1408 }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 struct drm_device *dev = dev_priv->dev;
1415 int sprite;
1416
1417 if (INTEL_INFO(dev)->gen >= 9) {
1418 for_each_sprite(dev_priv, pipe, sprite) {
1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
1425 for_each_sprite(dev_priv, pipe, sprite) {
1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
1427 I915_STATE_WARN(val & SP_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe, sprite), pipe_name(pipe));
1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
1432 u32 val = I915_READ(SPRCTL(pipe));
1433 I915_STATE_WARN(val & SPRITE_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
1437 u32 val = I915_READ(DVSCNTR(pipe));
1438 I915_STATE_WARN(val & DVS_ENABLE,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe), pipe_name(pipe));
1441 }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452 u32 val;
1453 bool enabled;
1454
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 u32 val;
1467 bool enabled;
1468
1469 val = I915_READ(PCH_TRANSCONF(pipe));
1470 enabled = !!(val & TRANS_ENABLE);
1471 I915_STATE_WARN(enabled,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1484 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1485 return false;
1486 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1488 return false;
1489 } else {
1490 if ((val & DP_PIPE_MASK) != (pipe << 30))
1491 return false;
1492 }
1493 return true;
1494 }
1495
1496 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, u32 val)
1498 {
1499 if ((val & SDVO_ENABLE) == 0)
1500 return false;
1501
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1504 return false;
1505 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1506 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1507 return false;
1508 } else {
1509 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1510 return false;
1511 }
1512 return true;
1513 }
1514
1515 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1516 enum pipe pipe, u32 val)
1517 {
1518 if ((val & LVDS_PORT_EN) == 0)
1519 return false;
1520
1521 if (HAS_PCH_CPT(dev_priv->dev)) {
1522 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1523 return false;
1524 } else {
1525 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1526 return false;
1527 }
1528 return true;
1529 }
1530
1531 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1532 enum pipe pipe, u32 val)
1533 {
1534 if ((val & ADPA_DAC_ENABLE) == 0)
1535 return false;
1536 if (HAS_PCH_CPT(dev_priv->dev)) {
1537 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1538 return false;
1539 } else {
1540 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1541 return false;
1542 }
1543 return true;
1544 }
1545
1546 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1547 enum pipe pipe, i915_reg_t reg,
1548 u32 port_sel)
1549 {
1550 u32 val = I915_READ(reg);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 i915_mmio_reg_offset(reg), pipe_name(pipe));
1554
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556 && (val & DP_PIPEB_SELECT),
1557 "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, i915_reg_t reg)
1562 {
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 i915_mmio_reg_offset(reg), pipe_name(pipe));
1567
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569 && (val & SDVO_PIPE_B_SELECT),
1570 "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575 {
1576 u32 val;
1577
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582 val = I915_READ(PCH_ADPA);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 val = I915_READ(PCH_LVDS);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 i915_reg_t reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 i915_reg_t reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /*
1717 * Apparently we need to have VGA mode enabled prior to changing
1718 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719 * dividers, even though the register value does change.
1720 */
1721 I915_WRITE(reg, 0);
1722
1723 I915_WRITE(reg, dpll);
1724
1725 /* Wait for the clocks to stabilize. */
1726 POSTING_READ(reg);
1727 udelay(150);
1728
1729 if (INTEL_INFO(dev)->gen >= 4) {
1730 I915_WRITE(DPLL_MD(crtc->pipe),
1731 crtc->config->dpll_hw_state.dpll_md);
1732 } else {
1733 /* The pixel multiplier can only be updated once the
1734 * DPLL is enabled and the clocks are stable.
1735 *
1736 * So write it again.
1737 */
1738 I915_WRITE(reg, dpll);
1739 }
1740
1741 /* We do this three times for luck */
1742 I915_WRITE(reg, dpll);
1743 POSTING_READ(reg);
1744 udelay(150); /* wait for warmup */
1745 I915_WRITE(reg, dpll);
1746 POSTING_READ(reg);
1747 udelay(150); /* wait for warmup */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754 * i9xx_disable_pll - disable a PLL
1755 * @dev_priv: i915 private structure
1756 * @pipe: pipe PLL to disable
1757 *
1758 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 *
1760 * Note! This is for pre-ILK only.
1761 */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764 struct drm_device *dev = crtc->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 enum pipe pipe = crtc->pipe;
1767
1768 /* Disable DVO 2x clock on both PLLs if necessary */
1769 if (IS_I830(dev) &&
1770 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771 !intel_num_dvo_pipes(dev)) {
1772 I915_WRITE(DPLL(PIPE_B),
1773 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774 I915_WRITE(DPLL(PIPE_A),
1775 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776 }
1777
1778 /* Don't disable pipe or pipe PLLs if needed */
1779 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781 return;
1782
1783 /* Make sure the pipe isn't still relying on us */
1784 assert_pipe_disabled(dev_priv, pipe);
1785
1786 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787 POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792 u32 val;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 /*
1798 * Leave integrated clock source and reference clock enabled for pipe B.
1799 * The latter is needed for VGA hotplug / manual detection.
1800 */
1801 val = DPLL_VGA_MODE_DIS;
1802 if (pipe == PIPE_B)
1803 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804 I915_WRITE(DPLL(pipe), val);
1805 POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812 u32 val;
1813
1814 /* Make sure the pipe isn't still relying on us */
1815 assert_pipe_disabled(dev_priv, pipe);
1816
1817 /* Set PLL en = 0 */
1818 val = DPLL_SSC_REF_CLK_CHV |
1819 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->sb_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
1838 {
1839 u32 port_mask;
1840 i915_reg_t dpll_reg;
1841
1842 switch (dport->port) {
1843 case PORT_B:
1844 port_mask = DPLL_PORTB_READY_MASK;
1845 dpll_reg = DPLL(0);
1846 break;
1847 case PORT_C:
1848 port_mask = DPLL_PORTC_READY_MASK;
1849 dpll_reg = DPLL(0);
1850 expected_mask <<= 4;
1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
1855 break;
1856 default:
1857 BUG();
1858 }
1859
1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871 if (WARN_ON(pll == NULL))
1872 return;
1873
1874 WARN_ON(!pll->config.crtc_mask);
1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882 }
1883
1884 /**
1885 * intel_enable_shared_dpll - enable PCH PLL
1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898 if (WARN_ON(pll == NULL))
1899 return;
1900
1901 if (WARN_ON(pll->config.crtc_mask == 0))
1902 return;
1903
1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905 pll->name, pll->active, pll->on,
1906 crtc->base.base.id);
1907
1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
1910 assert_shared_dpll_enabled(dev_priv, pll);
1911 return;
1912 }
1913 WARN_ON(pll->on);
1914
1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918 pll->enable(dev_priv, pll);
1919 pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928 /* PCH only available on ILK+ */
1929 if (INTEL_INFO(dev)->gen < 5)
1930 return;
1931
1932 if (pll == NULL)
1933 return;
1934
1935 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936 return;
1937
1938 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939 pll->name, pll->active, pll->on,
1940 crtc->base.base.id);
1941
1942 if (WARN_ON(pll->active == 0)) {
1943 assert_shared_dpll_disabled(dev_priv, pll);
1944 return;
1945 }
1946
1947 assert_shared_dpll_enabled(dev_priv, pll);
1948 WARN_ON(!pll->on);
1949 if (--pll->active)
1950 return;
1951
1952 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953 pll->disable(dev_priv, pll);
1954 pll->on = false;
1955
1956 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965 i915_reg_t reg;
1966 uint32_t val, pipeconf_val;
1967
1968 /* PCH only available on ILK+ */
1969 BUG_ON(!HAS_PCH_SPLIT(dev));
1970
1971 /* Make sure PCH DPLL is enabled */
1972 assert_shared_dpll_enabled(dev_priv,
1973 intel_crtc_to_shared_dpll(intel_crtc));
1974
1975 /* FDI must be feeding us bits for PCH ports */
1976 assert_fdi_tx_enabled(dev_priv, pipe);
1977 assert_fdi_rx_enabled(dev_priv, pipe);
1978
1979 if (HAS_PCH_CPT(dev)) {
1980 /* Workaround: Set the timing override bit before enabling the
1981 * pch transcoder. */
1982 reg = TRANS_CHICKEN2(pipe);
1983 val = I915_READ(reg);
1984 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(reg, val);
1986 }
1987
1988 reg = PCH_TRANSCONF(pipe);
1989 val = I915_READ(reg);
1990 pipeconf_val = I915_READ(PIPECONF(pipe));
1991
1992 if (HAS_PCH_IBX(dev_priv->dev)) {
1993 /*
1994 * Make the BPC in transcoder be consistent with
1995 * that in pipeconf reg. For HDMI we must use 8bpc
1996 * here for both 8bpc and 12bpc.
1997 */
1998 val &= ~PIPECONF_BPC_MASK;
1999 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2000 val |= PIPECONF_8BPC;
2001 else
2002 val |= pipeconf_val & PIPECONF_BPC_MASK;
2003 }
2004
2005 val &= ~TRANS_INTERLACE_MASK;
2006 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2007 if (HAS_PCH_IBX(dev_priv->dev) &&
2008 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2009 val |= TRANS_LEGACY_INTERLACED_ILK;
2010 else
2011 val |= TRANS_INTERLACED;
2012 else
2013 val |= TRANS_PROGRESSIVE;
2014
2015 I915_WRITE(reg, val | TRANS_ENABLE);
2016 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2017 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2018 }
2019
2020 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2021 enum transcoder cpu_transcoder)
2022 {
2023 u32 val, pipeconf_val;
2024
2025 /* PCH only available on ILK+ */
2026 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2027
2028 /* FDI must be feeding us bits for PCH ports */
2029 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2030 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2031
2032 /* Workaround: set timing override bit. */
2033 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2034 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2035 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2036
2037 val = TRANS_ENABLE;
2038 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2039
2040 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2041 PIPECONF_INTERLACED_ILK)
2042 val |= TRANS_INTERLACED;
2043 else
2044 val |= TRANS_PROGRESSIVE;
2045
2046 I915_WRITE(LPT_TRANSCONF, val);
2047 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2048 DRM_ERROR("Failed to enable PCH transcoder\n");
2049 }
2050
2051 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2052 enum pipe pipe)
2053 {
2054 struct drm_device *dev = dev_priv->dev;
2055 i915_reg_t reg;
2056 uint32_t val;
2057
2058 /* FDI relies on the transcoder */
2059 assert_fdi_tx_disabled(dev_priv, pipe);
2060 assert_fdi_rx_disabled(dev_priv, pipe);
2061
2062 /* Ports must be off as well */
2063 assert_pch_ports_disabled(dev_priv, pipe);
2064
2065 reg = PCH_TRANSCONF(pipe);
2066 val = I915_READ(reg);
2067 val &= ~TRANS_ENABLE;
2068 I915_WRITE(reg, val);
2069 /* wait for PCH transcoder off, transcoder state */
2070 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2071 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2072
2073 if (HAS_PCH_CPT(dev)) {
2074 /* Workaround: Clear the timing override chicken bit again. */
2075 reg = TRANS_CHICKEN2(pipe);
2076 val = I915_READ(reg);
2077 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2078 I915_WRITE(reg, val);
2079 }
2080 }
2081
2082 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2083 {
2084 u32 val;
2085
2086 val = I915_READ(LPT_TRANSCONF);
2087 val &= ~TRANS_ENABLE;
2088 I915_WRITE(LPT_TRANSCONF, val);
2089 /* wait for PCH transcoder off, transcoder state */
2090 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2091 DRM_ERROR("Failed to disable PCH transcoder\n");
2092
2093 /* Workaround: clear timing override bit. */
2094 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2095 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2096 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2097 }
2098
2099 /**
2100 * intel_enable_pipe - enable a pipe, asserting requirements
2101 * @crtc: crtc responsible for the pipe
2102 *
2103 * Enable @crtc's pipe, making sure that various hardware specific requirements
2104 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2105 */
2106 static void intel_enable_pipe(struct intel_crtc *crtc)
2107 {
2108 struct drm_device *dev = crtc->base.dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 enum pipe pipe = crtc->pipe;
2111 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2112 enum pipe pch_transcoder;
2113 i915_reg_t reg;
2114 u32 val;
2115
2116 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2117
2118 assert_planes_disabled(dev_priv, pipe);
2119 assert_cursor_disabled(dev_priv, pipe);
2120 assert_sprites_disabled(dev_priv, pipe);
2121
2122 if (HAS_PCH_LPT(dev_priv->dev))
2123 pch_transcoder = TRANSCODER_A;
2124 else
2125 pch_transcoder = pipe;
2126
2127 /*
2128 * A pipe without a PLL won't actually be able to drive bits from
2129 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2130 * need the check.
2131 */
2132 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2134 assert_dsi_pll_enabled(dev_priv);
2135 else
2136 assert_pll_enabled(dev_priv, pipe);
2137 else {
2138 if (crtc->config->has_pch_encoder) {
2139 /* if driving the PCH, we need FDI enabled */
2140 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2141 assert_fdi_tx_pll_enabled(dev_priv,
2142 (enum pipe) cpu_transcoder);
2143 }
2144 /* FIXME: assert CPU port conditions for SNB+ */
2145 }
2146
2147 reg = PIPECONF(cpu_transcoder);
2148 val = I915_READ(reg);
2149 if (val & PIPECONF_ENABLE) {
2150 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2151 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2152 return;
2153 }
2154
2155 I915_WRITE(reg, val | PIPECONF_ENABLE);
2156 POSTING_READ(reg);
2157 }
2158
2159 /**
2160 * intel_disable_pipe - disable a pipe, asserting requirements
2161 * @crtc: crtc whose pipes is to be disabled
2162 *
2163 * Disable the pipe of @crtc, making sure that various hardware
2164 * specific requirements are met, if applicable, e.g. plane
2165 * disabled, panel fitter off, etc.
2166 *
2167 * Will wait until the pipe has shut down before returning.
2168 */
2169 static void intel_disable_pipe(struct intel_crtc *crtc)
2170 {
2171 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2172 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2173 enum pipe pipe = crtc->pipe;
2174 i915_reg_t reg;
2175 u32 val;
2176
2177 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
2184 assert_cursor_disabled(dev_priv, pipe);
2185 assert_sprites_disabled(dev_priv, pipe);
2186
2187 reg = PIPECONF(cpu_transcoder);
2188 val = I915_READ(reg);
2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
2196 if (crtc->config->double_wide)
2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 static bool need_vtd_wa(struct drm_device *dev)
2210 {
2211 #ifdef CONFIG_INTEL_IOMMU
2212 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2213 return true;
2214 #endif
2215 return false;
2216 }
2217
2218 unsigned int
2219 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2220 uint64_t fb_format_modifier, unsigned int plane)
2221 {
2222 unsigned int tile_height;
2223 uint32_t pixel_bytes;
2224
2225 switch (fb_format_modifier) {
2226 case DRM_FORMAT_MOD_NONE:
2227 tile_height = 1;
2228 break;
2229 case I915_FORMAT_MOD_X_TILED:
2230 tile_height = IS_GEN2(dev) ? 16 : 8;
2231 break;
2232 case I915_FORMAT_MOD_Y_TILED:
2233 tile_height = 32;
2234 break;
2235 case I915_FORMAT_MOD_Yf_TILED:
2236 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2237 switch (pixel_bytes) {
2238 default:
2239 case 1:
2240 tile_height = 64;
2241 break;
2242 case 2:
2243 case 4:
2244 tile_height = 32;
2245 break;
2246 case 8:
2247 tile_height = 16;
2248 break;
2249 case 16:
2250 WARN_ONCE(1,
2251 "128-bit pixels are not supported for display!");
2252 tile_height = 16;
2253 break;
2254 }
2255 break;
2256 default:
2257 MISSING_CASE(fb_format_modifier);
2258 tile_height = 1;
2259 break;
2260 }
2261
2262 return tile_height;
2263 }
2264
2265 unsigned int
2266 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2267 uint32_t pixel_format, uint64_t fb_format_modifier)
2268 {
2269 return ALIGN(height, intel_tile_height(dev, pixel_format,
2270 fb_format_modifier, 0));
2271 }
2272
2273 static void
2274 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2275 const struct drm_plane_state *plane_state)
2276 {
2277 struct intel_rotation_info *info = &view->params.rotation_info;
2278 unsigned int tile_height, tile_pitch;
2279
2280 *view = i915_ggtt_view_normal;
2281
2282 if (!plane_state)
2283 return;
2284
2285 if (!intel_rotation_90_or_270(plane_state->rotation))
2286 return;
2287
2288 *view = i915_ggtt_view_rotated;
2289
2290 info->height = fb->height;
2291 info->pixel_format = fb->pixel_format;
2292 info->pitch = fb->pitches[0];
2293 info->uv_offset = fb->offsets[1];
2294 info->fb_modifier = fb->modifier[0];
2295
2296 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2297 fb->modifier[0], 0);
2298 tile_pitch = PAGE_SIZE / tile_height;
2299 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2300 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2301 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2302
2303 if (info->pixel_format == DRM_FORMAT_NV12) {
2304 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305 fb->modifier[0], 1);
2306 tile_pitch = PAGE_SIZE / tile_height;
2307 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2309 tile_height);
2310 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2311 PAGE_SIZE;
2312 }
2313 }
2314
2315 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2316 {
2317 if (INTEL_INFO(dev_priv)->gen >= 9)
2318 return 256 * 1024;
2319 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2320 IS_VALLEYVIEW(dev_priv))
2321 return 128 * 1024;
2322 else if (INTEL_INFO(dev_priv)->gen >= 4)
2323 return 4 * 1024;
2324 else
2325 return 0;
2326 }
2327
2328 int
2329 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2330 struct drm_framebuffer *fb,
2331 const struct drm_plane_state *plane_state)
2332 {
2333 struct drm_device *dev = fb->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2336 struct i915_ggtt_view view;
2337 u32 alignment;
2338 int ret;
2339
2340 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341
2342 switch (fb->modifier[0]) {
2343 case DRM_FORMAT_MOD_NONE:
2344 alignment = intel_linear_alignment(dev_priv);
2345 break;
2346 case I915_FORMAT_MOD_X_TILED:
2347 if (INTEL_INFO(dev)->gen >= 9)
2348 alignment = 256 * 1024;
2349 else {
2350 /* pin() will align the object as required by fence */
2351 alignment = 0;
2352 }
2353 break;
2354 case I915_FORMAT_MOD_Y_TILED:
2355 case I915_FORMAT_MOD_Yf_TILED:
2356 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2357 "Y tiling bo slipped through, driver bug!\n"))
2358 return -EINVAL;
2359 alignment = 1 * 1024 * 1024;
2360 break;
2361 default:
2362 MISSING_CASE(fb->modifier[0]);
2363 return -EINVAL;
2364 }
2365
2366 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2367
2368 /* Note that the w/a also requires 64 PTE of padding following the
2369 * bo. We currently fill all unused PTE with the shadow page and so
2370 * we should always have valid PTE following the scanout preventing
2371 * the VT-d warning.
2372 */
2373 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2374 alignment = 256 * 1024;
2375
2376 /*
2377 * Global gtt pte registers are special registers which actually forward
2378 * writes to a chunk of system memory. Which means that there is no risk
2379 * that the register values disappear as soon as we call
2380 * intel_runtime_pm_put(), so it is correct to wrap only the
2381 * pin/unpin/fence and not more.
2382 */
2383 intel_runtime_pm_get(dev_priv);
2384
2385 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2386 &view);
2387 if (ret)
2388 goto err_pm;
2389
2390 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2391 * fence, whereas 965+ only requires a fence if using
2392 * framebuffer compression. For simplicity, we always install
2393 * a fence as the cost is not that onerous.
2394 */
2395 if (view.type == I915_GGTT_VIEW_NORMAL) {
2396 ret = i915_gem_object_get_fence(obj);
2397 if (ret == -EDEADLK) {
2398 /*
2399 * -EDEADLK means there are no free fences
2400 * no pending flips.
2401 *
2402 * This is propagated to atomic, but it uses
2403 * -EDEADLK to force a locking recovery, so
2404 * change the returned error to -EBUSY.
2405 */
2406 ret = -EBUSY;
2407 goto err_unpin;
2408 } else if (ret)
2409 goto err_unpin;
2410
2411 i915_gem_object_pin_fence(obj);
2412 }
2413
2414 intel_runtime_pm_put(dev_priv);
2415 return 0;
2416
2417 err_unpin:
2418 i915_gem_object_unpin_from_display_plane(obj, &view);
2419 err_pm:
2420 intel_runtime_pm_put(dev_priv);
2421 return ret;
2422 }
2423
2424 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425 const struct drm_plane_state *plane_state)
2426 {
2427 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428 struct i915_ggtt_view view;
2429
2430 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
2432 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433
2434 if (view.type == I915_GGTT_VIEW_NORMAL)
2435 i915_gem_object_unpin_fence(obj);
2436
2437 i915_gem_object_unpin_from_display_plane(obj, &view);
2438 }
2439
2440 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441 * is assumed to be a power-of-two. */
2442 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2443 int *x, int *y,
2444 unsigned int tiling_mode,
2445 unsigned int cpp,
2446 unsigned int pitch)
2447 {
2448 if (tiling_mode != I915_TILING_NONE) {
2449 unsigned int tile_rows, tiles;
2450
2451 tile_rows = *y / 8;
2452 *y %= 8;
2453
2454 tiles = *x / (512/cpp);
2455 *x %= 512/cpp;
2456
2457 return tile_rows * pitch * 8 + tiles * 4096;
2458 } else {
2459 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2460 unsigned int offset;
2461
2462 offset = *y * pitch + *x * cpp;
2463 *y = (offset & alignment) / pitch;
2464 *x = ((offset & alignment) - *y * pitch) / cpp;
2465 return offset & ~alignment;
2466 }
2467 }
2468
2469 static int i9xx_format_to_fourcc(int format)
2470 {
2471 switch (format) {
2472 case DISPPLANE_8BPP:
2473 return DRM_FORMAT_C8;
2474 case DISPPLANE_BGRX555:
2475 return DRM_FORMAT_XRGB1555;
2476 case DISPPLANE_BGRX565:
2477 return DRM_FORMAT_RGB565;
2478 default:
2479 case DISPPLANE_BGRX888:
2480 return DRM_FORMAT_XRGB8888;
2481 case DISPPLANE_RGBX888:
2482 return DRM_FORMAT_XBGR8888;
2483 case DISPPLANE_BGRX101010:
2484 return DRM_FORMAT_XRGB2101010;
2485 case DISPPLANE_RGBX101010:
2486 return DRM_FORMAT_XBGR2101010;
2487 }
2488 }
2489
2490 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2491 {
2492 switch (format) {
2493 case PLANE_CTL_FORMAT_RGB_565:
2494 return DRM_FORMAT_RGB565;
2495 default:
2496 case PLANE_CTL_FORMAT_XRGB_8888:
2497 if (rgb_order) {
2498 if (alpha)
2499 return DRM_FORMAT_ABGR8888;
2500 else
2501 return DRM_FORMAT_XBGR8888;
2502 } else {
2503 if (alpha)
2504 return DRM_FORMAT_ARGB8888;
2505 else
2506 return DRM_FORMAT_XRGB8888;
2507 }
2508 case PLANE_CTL_FORMAT_XRGB_2101010:
2509 if (rgb_order)
2510 return DRM_FORMAT_XBGR2101010;
2511 else
2512 return DRM_FORMAT_XRGB2101010;
2513 }
2514 }
2515
2516 static bool
2517 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2518 struct intel_initial_plane_config *plane_config)
2519 {
2520 struct drm_device *dev = crtc->base.dev;
2521 struct drm_i915_private *dev_priv = to_i915(dev);
2522 struct drm_i915_gem_object *obj = NULL;
2523 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2524 struct drm_framebuffer *fb = &plane_config->fb->base;
2525 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2526 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2527 PAGE_SIZE);
2528
2529 size_aligned -= base_aligned;
2530
2531 if (plane_config->size == 0)
2532 return false;
2533
2534 /* If the FB is too big, just don't use it since fbdev is not very
2535 * important and we should probably use that space with FBC or other
2536 * features. */
2537 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2538 return false;
2539
2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
2544 if (!obj)
2545 return false;
2546
2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
2549 obj->stride = fb->pitches[0];
2550
2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558 mutex_lock(&dev->struct_mutex);
2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560 &mode_cmd, obj)) {
2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
2564 mutex_unlock(&dev->struct_mutex);
2565
2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567 return true;
2568
2569 out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
2572 return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
2592 {
2593 struct drm_device *dev = intel_crtc->base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2597 struct drm_i915_gem_object *obj;
2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_plane_state *plane_state = primary->state;
2600 struct drm_framebuffer *fb;
2601
2602 if (!plane_config->fb)
2603 return;
2604
2605 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2606 fb = &plane_config->fb->base;
2607 goto valid_fb;
2608 }
2609
2610 kfree(plane_config->fb);
2611
2612 /*
2613 * Failed to alloc the obj, check to see if we should share
2614 * an fb with another CRTC instead
2615 */
2616 for_each_crtc(dev, c) {
2617 i = to_intel_crtc(c);
2618
2619 if (c == &intel_crtc->base)
2620 continue;
2621
2622 if (!i->active)
2623 continue;
2624
2625 fb = c->primary->fb;
2626 if (!fb)
2627 continue;
2628
2629 obj = intel_fb_obj(fb);
2630 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2631 drm_framebuffer_reference(fb);
2632 goto valid_fb;
2633 }
2634 }
2635
2636 return;
2637
2638 valid_fb:
2639 plane_state->src_x = 0;
2640 plane_state->src_y = 0;
2641 plane_state->src_w = fb->width << 16;
2642 plane_state->src_h = fb->height << 16;
2643
2644 plane_state->crtc_x = 0;
2645 plane_state->crtc_y = 0;
2646 plane_state->crtc_w = fb->width;
2647 plane_state->crtc_h = fb->height;
2648
2649 obj = intel_fb_obj(fb);
2650 if (obj->tiling_mode != I915_TILING_NONE)
2651 dev_priv->preserve_bios_swizzle = true;
2652
2653 drm_framebuffer_reference(fb);
2654 primary->fb = primary->state->fb = fb;
2655 primary->crtc = primary->state->crtc = &intel_crtc->base;
2656 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2657 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658 }
2659
2660 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2661 struct drm_framebuffer *fb,
2662 int x, int y)
2663 {
2664 struct drm_device *dev = crtc->dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667 struct drm_plane *primary = crtc->primary;
2668 bool visible = to_intel_plane_state(primary->state)->visible;
2669 struct drm_i915_gem_object *obj;
2670 int plane = intel_crtc->plane;
2671 unsigned long linear_offset;
2672 u32 dspcntr;
2673 i915_reg_t reg = DSPCNTR(plane);
2674 int pixel_size;
2675
2676 if (!visible || !fb) {
2677 I915_WRITE(reg, 0);
2678 if (INTEL_INFO(dev)->gen >= 4)
2679 I915_WRITE(DSPSURF(plane), 0);
2680 else
2681 I915_WRITE(DSPADDR(plane), 0);
2682 POSTING_READ(reg);
2683 return;
2684 }
2685
2686 obj = intel_fb_obj(fb);
2687 if (WARN_ON(obj == NULL))
2688 return;
2689
2690 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2691
2692 dspcntr = DISPPLANE_GAMMA_ENABLE;
2693
2694 dspcntr |= DISPLAY_PLANE_ENABLE;
2695
2696 if (INTEL_INFO(dev)->gen < 4) {
2697 if (intel_crtc->pipe == PIPE_B)
2698 dspcntr |= DISPPLANE_SEL_PIPE_B;
2699
2700 /* pipesrc and dspsize control the size that is scaled from,
2701 * which should always be the user's requested size.
2702 */
2703 I915_WRITE(DSPSIZE(plane),
2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
2706 I915_WRITE(DSPPOS(plane), 0);
2707 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2708 I915_WRITE(PRIMSIZE(plane),
2709 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2710 (intel_crtc->config->pipe_src_w - 1));
2711 I915_WRITE(PRIMPOS(plane), 0);
2712 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2713 }
2714
2715 switch (fb->pixel_format) {
2716 case DRM_FORMAT_C8:
2717 dspcntr |= DISPPLANE_8BPP;
2718 break;
2719 case DRM_FORMAT_XRGB1555:
2720 dspcntr |= DISPPLANE_BGRX555;
2721 break;
2722 case DRM_FORMAT_RGB565:
2723 dspcntr |= DISPPLANE_BGRX565;
2724 break;
2725 case DRM_FORMAT_XRGB8888:
2726 dspcntr |= DISPPLANE_BGRX888;
2727 break;
2728 case DRM_FORMAT_XBGR8888:
2729 dspcntr |= DISPPLANE_RGBX888;
2730 break;
2731 case DRM_FORMAT_XRGB2101010:
2732 dspcntr |= DISPPLANE_BGRX101010;
2733 break;
2734 case DRM_FORMAT_XBGR2101010:
2735 dspcntr |= DISPPLANE_RGBX101010;
2736 break;
2737 default:
2738 BUG();
2739 }
2740
2741 if (INTEL_INFO(dev)->gen >= 4 &&
2742 obj->tiling_mode != I915_TILING_NONE)
2743 dspcntr |= DISPPLANE_TILED;
2744
2745 if (IS_G4X(dev))
2746 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2747
2748 linear_offset = y * fb->pitches[0] + x * pixel_size;
2749
2750 if (INTEL_INFO(dev)->gen >= 4) {
2751 intel_crtc->dspaddr_offset =
2752 intel_gen4_compute_page_offset(dev_priv,
2753 &x, &y, obj->tiling_mode,
2754 pixel_size,
2755 fb->pitches[0]);
2756 linear_offset -= intel_crtc->dspaddr_offset;
2757 } else {
2758 intel_crtc->dspaddr_offset = linear_offset;
2759 }
2760
2761 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2762 dspcntr |= DISPPLANE_ROTATE_180;
2763
2764 x += (intel_crtc->config->pipe_src_w - 1);
2765 y += (intel_crtc->config->pipe_src_h - 1);
2766
2767 /* Finding the last pixel of the last line of the display
2768 data and adding to linear_offset*/
2769 linear_offset +=
2770 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2772 }
2773
2774 intel_crtc->adjusted_x = x;
2775 intel_crtc->adjusted_y = y;
2776
2777 I915_WRITE(reg, dspcntr);
2778
2779 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2780 if (INTEL_INFO(dev)->gen >= 4) {
2781 I915_WRITE(DSPSURF(plane),
2782 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2783 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2784 I915_WRITE(DSPLINOFF(plane), linear_offset);
2785 } else
2786 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2787 POSTING_READ(reg);
2788 }
2789
2790 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2791 struct drm_framebuffer *fb,
2792 int x, int y)
2793 {
2794 struct drm_device *dev = crtc->dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797 struct drm_plane *primary = crtc->primary;
2798 bool visible = to_intel_plane_state(primary->state)->visible;
2799 struct drm_i915_gem_object *obj;
2800 int plane = intel_crtc->plane;
2801 unsigned long linear_offset;
2802 u32 dspcntr;
2803 i915_reg_t reg = DSPCNTR(plane);
2804 int pixel_size;
2805
2806 if (!visible || !fb) {
2807 I915_WRITE(reg, 0);
2808 I915_WRITE(DSPSURF(plane), 0);
2809 POSTING_READ(reg);
2810 return;
2811 }
2812
2813 obj = intel_fb_obj(fb);
2814 if (WARN_ON(obj == NULL))
2815 return;
2816
2817 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
2819 dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
2821 dspcntr |= DISPLAY_PLANE_ENABLE;
2822
2823 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2825
2826 switch (fb->pixel_format) {
2827 case DRM_FORMAT_C8:
2828 dspcntr |= DISPPLANE_8BPP;
2829 break;
2830 case DRM_FORMAT_RGB565:
2831 dspcntr |= DISPPLANE_BGRX565;
2832 break;
2833 case DRM_FORMAT_XRGB8888:
2834 dspcntr |= DISPPLANE_BGRX888;
2835 break;
2836 case DRM_FORMAT_XBGR8888:
2837 dspcntr |= DISPPLANE_RGBX888;
2838 break;
2839 case DRM_FORMAT_XRGB2101010:
2840 dspcntr |= DISPPLANE_BGRX101010;
2841 break;
2842 case DRM_FORMAT_XBGR2101010:
2843 dspcntr |= DISPPLANE_RGBX101010;
2844 break;
2845 default:
2846 BUG();
2847 }
2848
2849 if (obj->tiling_mode != I915_TILING_NONE)
2850 dspcntr |= DISPPLANE_TILED;
2851
2852 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2853 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2854
2855 linear_offset = y * fb->pitches[0] + x * pixel_size;
2856 intel_crtc->dspaddr_offset =
2857 intel_gen4_compute_page_offset(dev_priv,
2858 &x, &y, obj->tiling_mode,
2859 pixel_size,
2860 fb->pitches[0]);
2861 linear_offset -= intel_crtc->dspaddr_offset;
2862 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2863 dspcntr |= DISPPLANE_ROTATE_180;
2864
2865 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2866 x += (intel_crtc->config->pipe_src_w - 1);
2867 y += (intel_crtc->config->pipe_src_h - 1);
2868
2869 /* Finding the last pixel of the last line of the display
2870 data and adding to linear_offset*/
2871 linear_offset +=
2872 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2873 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2874 }
2875 }
2876
2877 intel_crtc->adjusted_x = x;
2878 intel_crtc->adjusted_y = y;
2879
2880 I915_WRITE(reg, dspcntr);
2881
2882 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2883 I915_WRITE(DSPSURF(plane),
2884 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2885 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2886 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887 } else {
2888 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890 }
2891 POSTING_READ(reg);
2892 }
2893
2894 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895 uint32_t pixel_format)
2896 {
2897 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899 /*
2900 * The stride is either expressed as a multiple of 64 bytes
2901 * chunks for linear buffers or in number of tiles for tiled
2902 * buffers.
2903 */
2904 switch (fb_modifier) {
2905 case DRM_FORMAT_MOD_NONE:
2906 return 64;
2907 case I915_FORMAT_MOD_X_TILED:
2908 if (INTEL_INFO(dev)->gen == 2)
2909 return 128;
2910 return 512;
2911 case I915_FORMAT_MOD_Y_TILED:
2912 /* No need to check for old gens and Y tiling since this is
2913 * about the display engine and those will be blocked before
2914 * we get here.
2915 */
2916 return 128;
2917 case I915_FORMAT_MOD_Yf_TILED:
2918 if (bits_per_pixel == 8)
2919 return 64;
2920 else
2921 return 128;
2922 default:
2923 MISSING_CASE(fb_modifier);
2924 return 64;
2925 }
2926 }
2927
2928 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2929 struct drm_i915_gem_object *obj,
2930 unsigned int plane)
2931 {
2932 struct i915_ggtt_view view;
2933 struct i915_vma *vma;
2934 u64 offset;
2935
2936 intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2937 intel_plane->base.state);
2938
2939 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2940 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2941 view.type))
2942 return -1;
2943
2944 offset = vma->node.start;
2945
2946 if (plane == 1) {
2947 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2948 PAGE_SIZE;
2949 }
2950
2951 WARN_ON(upper_32_bits(offset));
2952
2953 return lower_32_bits(offset);
2954 }
2955
2956 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2957 {
2958 struct drm_device *dev = intel_crtc->base.dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960
2961 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2962 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2963 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2964 }
2965
2966 /*
2967 * This function detaches (aka. unbinds) unused scalers in hardware
2968 */
2969 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2970 {
2971 struct intel_crtc_scaler_state *scaler_state;
2972 int i;
2973
2974 scaler_state = &intel_crtc->config->scaler_state;
2975
2976 /* loop through and disable scalers that aren't in use */
2977 for (i = 0; i < intel_crtc->num_scalers; i++) {
2978 if (!scaler_state->scalers[i].in_use)
2979 skl_detach_scaler(intel_crtc, i);
2980 }
2981 }
2982
2983 u32 skl_plane_ctl_format(uint32_t pixel_format)
2984 {
2985 switch (pixel_format) {
2986 case DRM_FORMAT_C8:
2987 return PLANE_CTL_FORMAT_INDEXED;
2988 case DRM_FORMAT_RGB565:
2989 return PLANE_CTL_FORMAT_RGB_565;
2990 case DRM_FORMAT_XBGR8888:
2991 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2992 case DRM_FORMAT_XRGB8888:
2993 return PLANE_CTL_FORMAT_XRGB_8888;
2994 /*
2995 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2996 * to be already pre-multiplied. We need to add a knob (or a different
2997 * DRM_FORMAT) for user-space to configure that.
2998 */
2999 case DRM_FORMAT_ABGR8888:
3000 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3001 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3002 case DRM_FORMAT_ARGB8888:
3003 return PLANE_CTL_FORMAT_XRGB_8888 |
3004 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3005 case DRM_FORMAT_XRGB2101010:
3006 return PLANE_CTL_FORMAT_XRGB_2101010;
3007 case DRM_FORMAT_XBGR2101010:
3008 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3009 case DRM_FORMAT_YUYV:
3010 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3011 case DRM_FORMAT_YVYU:
3012 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3013 case DRM_FORMAT_UYVY:
3014 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3015 case DRM_FORMAT_VYUY:
3016 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3017 default:
3018 MISSING_CASE(pixel_format);
3019 }
3020
3021 return 0;
3022 }
3023
3024 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3025 {
3026 switch (fb_modifier) {
3027 case DRM_FORMAT_MOD_NONE:
3028 break;
3029 case I915_FORMAT_MOD_X_TILED:
3030 return PLANE_CTL_TILED_X;
3031 case I915_FORMAT_MOD_Y_TILED:
3032 return PLANE_CTL_TILED_Y;
3033 case I915_FORMAT_MOD_Yf_TILED:
3034 return PLANE_CTL_TILED_YF;
3035 default:
3036 MISSING_CASE(fb_modifier);
3037 }
3038
3039 return 0;
3040 }
3041
3042 u32 skl_plane_ctl_rotation(unsigned int rotation)
3043 {
3044 switch (rotation) {
3045 case BIT(DRM_ROTATE_0):
3046 break;
3047 /*
3048 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3049 * while i915 HW rotation is clockwise, thats why this swapping.
3050 */
3051 case BIT(DRM_ROTATE_90):
3052 return PLANE_CTL_ROTATE_270;
3053 case BIT(DRM_ROTATE_180):
3054 return PLANE_CTL_ROTATE_180;
3055 case BIT(DRM_ROTATE_270):
3056 return PLANE_CTL_ROTATE_90;
3057 default:
3058 MISSING_CASE(rotation);
3059 }
3060
3061 return 0;
3062 }
3063
3064 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3065 struct drm_framebuffer *fb,
3066 int x, int y)
3067 {
3068 struct drm_device *dev = crtc->dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071 struct drm_plane *plane = crtc->primary;
3072 bool visible = to_intel_plane_state(plane->state)->visible;
3073 struct drm_i915_gem_object *obj;
3074 int pipe = intel_crtc->pipe;
3075 u32 plane_ctl, stride_div, stride;
3076 u32 tile_height, plane_offset, plane_size;
3077 unsigned int rotation;
3078 int x_offset, y_offset;
3079 u32 surf_addr;
3080 struct intel_crtc_state *crtc_state = intel_crtc->config;
3081 struct intel_plane_state *plane_state;
3082 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3083 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3084 int scaler_id = -1;
3085
3086 plane_state = to_intel_plane_state(plane->state);
3087
3088 if (!visible || !fb) {
3089 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3090 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3091 POSTING_READ(PLANE_CTL(pipe, 0));
3092 return;
3093 }
3094
3095 plane_ctl = PLANE_CTL_ENABLE |
3096 PLANE_CTL_PIPE_GAMMA_ENABLE |
3097 PLANE_CTL_PIPE_CSC_ENABLE;
3098
3099 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3100 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3101 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3102
3103 rotation = plane->state->rotation;
3104 plane_ctl |= skl_plane_ctl_rotation(rotation);
3105
3106 obj = intel_fb_obj(fb);
3107 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3108 fb->pixel_format);
3109 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3110
3111 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3112
3113 scaler_id = plane_state->scaler_id;
3114 src_x = plane_state->src.x1 >> 16;
3115 src_y = plane_state->src.y1 >> 16;
3116 src_w = drm_rect_width(&plane_state->src) >> 16;
3117 src_h = drm_rect_height(&plane_state->src) >> 16;
3118 dst_x = plane_state->dst.x1;
3119 dst_y = plane_state->dst.y1;
3120 dst_w = drm_rect_width(&plane_state->dst);
3121 dst_h = drm_rect_height(&plane_state->dst);
3122
3123 WARN_ON(x != src_x || y != src_y);
3124
3125 if (intel_rotation_90_or_270(rotation)) {
3126 /* stride = Surface height in tiles */
3127 tile_height = intel_tile_height(dev, fb->pixel_format,
3128 fb->modifier[0], 0);
3129 stride = DIV_ROUND_UP(fb->height, tile_height);
3130 x_offset = stride * tile_height - y - src_h;
3131 y_offset = x;
3132 plane_size = (src_w - 1) << 16 | (src_h - 1);
3133 } else {
3134 stride = fb->pitches[0] / stride_div;
3135 x_offset = x;
3136 y_offset = y;
3137 plane_size = (src_h - 1) << 16 | (src_w - 1);
3138 }
3139 plane_offset = y_offset << 16 | x_offset;
3140
3141 intel_crtc->adjusted_x = x_offset;
3142 intel_crtc->adjusted_y = y_offset;
3143
3144 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3145 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3146 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3147 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3148
3149 if (scaler_id >= 0) {
3150 uint32_t ps_ctrl = 0;
3151
3152 WARN_ON(!dst_w || !dst_h);
3153 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3154 crtc_state->scaler_state.scalers[scaler_id].mode;
3155 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3156 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3157 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3158 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3159 I915_WRITE(PLANE_POS(pipe, 0), 0);
3160 } else {
3161 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3162 }
3163
3164 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3165
3166 POSTING_READ(PLANE_SURF(pipe, 0));
3167 }
3168
3169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3170 static int
3171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3172 int x, int y, enum mode_set_atomic state)
3173 {
3174 struct drm_device *dev = crtc->dev;
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176
3177 if (dev_priv->fbc.disable_fbc)
3178 dev_priv->fbc.disable_fbc(dev_priv);
3179
3180 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3181
3182 return 0;
3183 }
3184
3185 static void intel_complete_page_flips(struct drm_device *dev)
3186 {
3187 struct drm_crtc *crtc;
3188
3189 for_each_crtc(dev, crtc) {
3190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3191 enum plane plane = intel_crtc->plane;
3192
3193 intel_prepare_page_flip(dev, plane);
3194 intel_finish_page_flip_plane(dev, plane);
3195 }
3196 }
3197
3198 static void intel_update_primary_planes(struct drm_device *dev)
3199 {
3200 struct drm_crtc *crtc;
3201
3202 for_each_crtc(dev, crtc) {
3203 struct intel_plane *plane = to_intel_plane(crtc->primary);
3204 struct intel_plane_state *plane_state;
3205
3206 drm_modeset_lock_crtc(crtc, &plane->base);
3207 plane_state = to_intel_plane_state(plane->base.state);
3208
3209 if (crtc->state->active && plane_state->base.fb)
3210 plane->commit_plane(&plane->base, plane_state);
3211
3212 drm_modeset_unlock_crtc(crtc);
3213 }
3214 }
3215
3216 void intel_prepare_reset(struct drm_device *dev)
3217 {
3218 /* no reset support for gen2 */
3219 if (IS_GEN2(dev))
3220 return;
3221
3222 /* reset doesn't touch the display */
3223 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3224 return;
3225
3226 drm_modeset_lock_all(dev);
3227 /*
3228 * Disabling the crtcs gracefully seems nicer. Also the
3229 * g33 docs say we should at least disable all the planes.
3230 */
3231 intel_display_suspend(dev);
3232 }
3233
3234 void intel_finish_reset(struct drm_device *dev)
3235 {
3236 struct drm_i915_private *dev_priv = to_i915(dev);
3237
3238 /*
3239 * Flips in the rings will be nuked by the reset,
3240 * so complete all pending flips so that user space
3241 * will get its events and not get stuck.
3242 */
3243 intel_complete_page_flips(dev);
3244
3245 /* no reset support for gen2 */
3246 if (IS_GEN2(dev))
3247 return;
3248
3249 /* reset doesn't touch the display */
3250 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3251 /*
3252 * Flips in the rings have been nuked by the reset,
3253 * so update the base address of all primary
3254 * planes to the the last fb to make sure we're
3255 * showing the correct fb after a reset.
3256 *
3257 * FIXME: Atomic will make this obsolete since we won't schedule
3258 * CS-based flips (which might get lost in gpu resets) any more.
3259 */
3260 intel_update_primary_planes(dev);
3261 return;
3262 }
3263
3264 /*
3265 * The display has been reset as well,
3266 * so need a full re-initialization.
3267 */
3268 intel_runtime_pm_disable_interrupts(dev_priv);
3269 intel_runtime_pm_enable_interrupts(dev_priv);
3270
3271 intel_modeset_init_hw(dev);
3272
3273 spin_lock_irq(&dev_priv->irq_lock);
3274 if (dev_priv->display.hpd_irq_setup)
3275 dev_priv->display.hpd_irq_setup(dev);
3276 spin_unlock_irq(&dev_priv->irq_lock);
3277
3278 intel_display_resume(dev);
3279
3280 intel_hpd_init(dev_priv);
3281
3282 drm_modeset_unlock_all(dev);
3283 }
3284
3285 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3286 {
3287 struct drm_device *dev = crtc->dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290 bool pending;
3291
3292 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3293 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3294 return false;
3295
3296 spin_lock_irq(&dev->event_lock);
3297 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3298 spin_unlock_irq(&dev->event_lock);
3299
3300 return pending;
3301 }
3302
3303 static void intel_update_pipe_config(struct intel_crtc *crtc,
3304 struct intel_crtc_state *old_crtc_state)
3305 {
3306 struct drm_device *dev = crtc->base.dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 struct intel_crtc_state *pipe_config =
3309 to_intel_crtc_state(crtc->base.state);
3310
3311 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3312 crtc->base.mode = crtc->base.state->mode;
3313
3314 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3315 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3316 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3317
3318 if (HAS_DDI(dev))
3319 intel_set_pipe_csc(&crtc->base);
3320
3321 /*
3322 * Update pipe size and adjust fitter if needed: the reason for this is
3323 * that in compute_mode_changes we check the native mode (not the pfit
3324 * mode) to see if we can flip rather than do a full mode set. In the
3325 * fastboot case, we'll flip, but if we don't update the pipesrc and
3326 * pfit state, we'll end up with a big fb scanned out into the wrong
3327 * sized surface.
3328 */
3329
3330 I915_WRITE(PIPESRC(crtc->pipe),
3331 ((pipe_config->pipe_src_w - 1) << 16) |
3332 (pipe_config->pipe_src_h - 1));
3333
3334 /* on skylake this is done by detaching scalers */
3335 if (INTEL_INFO(dev)->gen >= 9) {
3336 skl_detach_scalers(crtc);
3337
3338 if (pipe_config->pch_pfit.enabled)
3339 skylake_pfit_enable(crtc);
3340 } else if (HAS_PCH_SPLIT(dev)) {
3341 if (pipe_config->pch_pfit.enabled)
3342 ironlake_pfit_enable(crtc);
3343 else if (old_crtc_state->pch_pfit.enabled)
3344 ironlake_pfit_disable(crtc, true);
3345 }
3346 }
3347
3348 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3349 {
3350 struct drm_device *dev = crtc->dev;
3351 struct drm_i915_private *dev_priv = dev->dev_private;
3352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353 int pipe = intel_crtc->pipe;
3354 i915_reg_t reg;
3355 u32 temp;
3356
3357 /* enable normal train */
3358 reg = FDI_TX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 if (IS_IVYBRIDGE(dev)) {
3361 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3362 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3363 } else {
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3366 }
3367 I915_WRITE(reg, temp);
3368
3369 reg = FDI_RX_CTL(pipe);
3370 temp = I915_READ(reg);
3371 if (HAS_PCH_CPT(dev)) {
3372 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3373 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3374 } else {
3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_NONE;
3377 }
3378 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3379
3380 /* wait one idle pattern time */
3381 POSTING_READ(reg);
3382 udelay(1000);
3383
3384 /* IVB wants error correction enabled */
3385 if (IS_IVYBRIDGE(dev))
3386 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3387 FDI_FE_ERRC_ENABLE);
3388 }
3389
3390 /* The FDI link training functions for ILK/Ibexpeak. */
3391 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3392 {
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 int pipe = intel_crtc->pipe;
3397 i915_reg_t reg;
3398 u32 temp, tries;
3399
3400 /* FDI needs bits from pipe first */
3401 assert_pipe_enabled(dev_priv, pipe);
3402
3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
3411 udelay(150);
3412
3413 /* enable CPU FDI TX and PCH FDI RX */
3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3421
3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
3429 udelay(150);
3430
3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
3435
3436 reg = FDI_RX_IIR(pipe);
3437 for (tries = 0; tries < 5; tries++) {
3438 temp = I915_READ(reg);
3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3444 break;
3445 }
3446 }
3447 if (tries == 5)
3448 DRM_ERROR("FDI train 1 fail!\n");
3449
3450 /* Train 2 */
3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
3455 I915_WRITE(reg, temp);
3456
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
3461 I915_WRITE(reg, temp);
3462
3463 POSTING_READ(reg);
3464 udelay(150);
3465
3466 reg = FDI_RX_IIR(pipe);
3467 for (tries = 0; tries < 5; tries++) {
3468 temp = I915_READ(reg);
3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
3476 }
3477 if (tries == 5)
3478 DRM_ERROR("FDI train 2 fail!\n");
3479
3480 DRM_DEBUG_KMS("FDI train done\n");
3481
3482 }
3483
3484 static const int snb_b_fdi_train_param[] = {
3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489 };
3490
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493 {
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
3498 i915_reg_t reg;
3499 u32 temp, i, retry;
3500
3501 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502 for train result */
3503 reg = FDI_RX_IMR(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_RX_SYMBOL_LOCK;
3506 temp &= ~FDI_RX_BIT_LOCK;
3507 I915_WRITE(reg, temp);
3508
3509 POSTING_READ(reg);
3510 udelay(150);
3511
3512 /* enable CPU FDI TX and PCH FDI RX */
3513 reg = FDI_TX_CTL(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3516 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3517 temp &= ~FDI_LINK_TRAIN_NONE;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1;
3519 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3520 /* SNB-B */
3521 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3523
3524 I915_WRITE(FDI_RX_MISC(pipe),
3525 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3526
3527 reg = FDI_RX_CTL(pipe);
3528 temp = I915_READ(reg);
3529 if (HAS_PCH_CPT(dev)) {
3530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3532 } else {
3533 temp &= ~FDI_LINK_TRAIN_NONE;
3534 temp |= FDI_LINK_TRAIN_PATTERN_1;
3535 }
3536 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3537
3538 POSTING_READ(reg);
3539 udelay(150);
3540
3541 for (i = 0; i < 4; i++) {
3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545 temp |= snb_b_fdi_train_param[i];
3546 I915_WRITE(reg, temp);
3547
3548 POSTING_READ(reg);
3549 udelay(500);
3550
3551 for (retry = 0; retry < 5; retry++) {
3552 reg = FDI_RX_IIR(pipe);
3553 temp = I915_READ(reg);
3554 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3555 if (temp & FDI_RX_BIT_LOCK) {
3556 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3557 DRM_DEBUG_KMS("FDI train 1 done.\n");
3558 break;
3559 }
3560 udelay(50);
3561 }
3562 if (retry < 5)
3563 break;
3564 }
3565 if (i == 4)
3566 DRM_ERROR("FDI train 1 fail!\n");
3567
3568 /* Train 2 */
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573 if (IS_GEN6(dev)) {
3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575 /* SNB-B */
3576 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3577 }
3578 I915_WRITE(reg, temp);
3579
3580 reg = FDI_RX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 if (HAS_PCH_CPT(dev)) {
3583 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3585 } else {
3586 temp &= ~FDI_LINK_TRAIN_NONE;
3587 temp |= FDI_LINK_TRAIN_PATTERN_2;
3588 }
3589 I915_WRITE(reg, temp);
3590
3591 POSTING_READ(reg);
3592 udelay(150);
3593
3594 for (i = 0; i < 4; i++) {
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598 temp |= snb_b_fdi_train_param[i];
3599 I915_WRITE(reg, temp);
3600
3601 POSTING_READ(reg);
3602 udelay(500);
3603
3604 for (retry = 0; retry < 5; retry++) {
3605 reg = FDI_RX_IIR(pipe);
3606 temp = I915_READ(reg);
3607 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3608 if (temp & FDI_RX_SYMBOL_LOCK) {
3609 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3610 DRM_DEBUG_KMS("FDI train 2 done.\n");
3611 break;
3612 }
3613 udelay(50);
3614 }
3615 if (retry < 5)
3616 break;
3617 }
3618 if (i == 4)
3619 DRM_ERROR("FDI train 2 fail!\n");
3620
3621 DRM_DEBUG_KMS("FDI train done.\n");
3622 }
3623
3624 /* Manual link training for Ivy Bridge A0 parts */
3625 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3626 {
3627 struct drm_device *dev = crtc->dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630 int pipe = intel_crtc->pipe;
3631 i915_reg_t reg;
3632 u32 temp, i, j;
3633
3634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635 for train result */
3636 reg = FDI_RX_IMR(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_RX_SYMBOL_LOCK;
3639 temp &= ~FDI_RX_BIT_LOCK;
3640 I915_WRITE(reg, temp);
3641
3642 POSTING_READ(reg);
3643 udelay(150);
3644
3645 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646 I915_READ(FDI_RX_IIR(pipe)));
3647
3648 /* Try each vswing and preemphasis setting twice before moving on */
3649 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650 /* disable first in case we need to retry */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654 temp &= ~FDI_TX_ENABLE;
3655 I915_WRITE(reg, temp);
3656
3657 reg = FDI_RX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_AUTO;
3660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661 temp &= ~FDI_RX_ENABLE;
3662 I915_WRITE(reg, temp);
3663
3664 /* enable CPU FDI TX and PCH FDI RX */
3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671 temp |= snb_b_fdi_train_param[j/2];
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675 I915_WRITE(FDI_RX_MISC(pipe),
3676 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678 reg = FDI_RX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681 temp |= FDI_COMPOSITE_SYNC;
3682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684 POSTING_READ(reg);
3685 udelay(1); /* should be 0.5us */
3686
3687 for (i = 0; i < 4; i++) {
3688 reg = FDI_RX_IIR(pipe);
3689 temp = I915_READ(reg);
3690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692 if (temp & FDI_RX_BIT_LOCK ||
3693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696 i);
3697 break;
3698 }
3699 udelay(1); /* should be 0.5us */
3700 }
3701 if (i == 4) {
3702 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703 continue;
3704 }
3705
3706 /* Train 2 */
3707 reg = FDI_TX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711 I915_WRITE(reg, temp);
3712
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717 I915_WRITE(reg, temp);
3718
3719 POSTING_READ(reg);
3720 udelay(2); /* should be 1.5us */
3721
3722 for (i = 0; i < 4; i++) {
3723 reg = FDI_RX_IIR(pipe);
3724 temp = I915_READ(reg);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727 if (temp & FDI_RX_SYMBOL_LOCK ||
3728 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731 i);
3732 goto train_done;
3733 }
3734 udelay(2); /* should be 1.5us */
3735 }
3736 if (i == 4)
3737 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738 }
3739
3740 train_done:
3741 DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746 struct drm_device *dev = intel_crtc->base.dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 int pipe = intel_crtc->pipe;
3749 i915_reg_t reg;
3750 u32 temp;
3751
3752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760 POSTING_READ(reg);
3761 udelay(200);
3762
3763 /* Switch from Rawclk to PCDclk */
3764 temp = I915_READ(reg);
3765 I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767 POSTING_READ(reg);
3768 udelay(200);
3769
3770 /* Enable CPU FDI TX PLL, always on for Ironlake */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776 POSTING_READ(reg);
3777 udelay(100);
3778 }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783 struct drm_device *dev = intel_crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 int pipe = intel_crtc->pipe;
3786 i915_reg_t reg;
3787 u32 temp;
3788
3789 /* Switch from PCDclk to Rawclk */
3790 reg = FDI_RX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3793
3794 /* Disable CPU FDI TX PLL */
3795 reg = FDI_TX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3798
3799 POSTING_READ(reg);
3800 udelay(100);
3801
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3805
3806 /* Wait for the clocks to turn off. */
3807 POSTING_READ(reg);
3808 udelay(100);
3809 }
3810
3811 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3812 {
3813 struct drm_device *dev = crtc->dev;
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3816 int pipe = intel_crtc->pipe;
3817 i915_reg_t reg;
3818 u32 temp;
3819
3820 /* disable CPU FDI tx and PCH FDI rx */
3821 reg = FDI_TX_CTL(pipe);
3822 temp = I915_READ(reg);
3823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3824 POSTING_READ(reg);
3825
3826 reg = FDI_RX_CTL(pipe);
3827 temp = I915_READ(reg);
3828 temp &= ~(0x7 << 16);
3829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3831
3832 POSTING_READ(reg);
3833 udelay(100);
3834
3835 /* Ironlake workaround, disable clock pointer after downing FDI */
3836 if (HAS_PCH_IBX(dev))
3837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3838
3839 /* still set train pattern 1 */
3840 reg = FDI_TX_CTL(pipe);
3841 temp = I915_READ(reg);
3842 temp &= ~FDI_LINK_TRAIN_NONE;
3843 temp |= FDI_LINK_TRAIN_PATTERN_1;
3844 I915_WRITE(reg, temp);
3845
3846 reg = FDI_RX_CTL(pipe);
3847 temp = I915_READ(reg);
3848 if (HAS_PCH_CPT(dev)) {
3849 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3850 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3851 } else {
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 }
3855 /* BPC in FDI rx is consistent with that in PIPECONF */
3856 temp &= ~(0x07 << 16);
3857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3858 I915_WRITE(reg, temp);
3859
3860 POSTING_READ(reg);
3861 udelay(100);
3862 }
3863
3864 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3865 {
3866 struct intel_crtc *crtc;
3867
3868 /* Note that we don't need to be called with mode_config.lock here
3869 * as our list of CRTC objects is static for the lifetime of the
3870 * device and so cannot disappear as we iterate. Similarly, we can
3871 * happily treat the predicates as racy, atomic checks as userspace
3872 * cannot claim and pin a new fb without at least acquring the
3873 * struct_mutex and so serialising with us.
3874 */
3875 for_each_intel_crtc(dev, crtc) {
3876 if (atomic_read(&crtc->unpin_work_count) == 0)
3877 continue;
3878
3879 if (crtc->unpin_work)
3880 intel_wait_for_vblank(dev, crtc->pipe);
3881
3882 return true;
3883 }
3884
3885 return false;
3886 }
3887
3888 static void page_flip_completed(struct intel_crtc *intel_crtc)
3889 {
3890 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3891 struct intel_unpin_work *work = intel_crtc->unpin_work;
3892
3893 /* ensure that the unpin work is consistent wrt ->pending. */
3894 smp_rmb();
3895 intel_crtc->unpin_work = NULL;
3896
3897 if (work->event)
3898 drm_send_vblank_event(intel_crtc->base.dev,
3899 intel_crtc->pipe,
3900 work->event);
3901
3902 drm_crtc_vblank_put(&intel_crtc->base);
3903
3904 wake_up_all(&dev_priv->pending_flip_queue);
3905 queue_work(dev_priv->wq, &work->work);
3906
3907 trace_i915_flip_complete(intel_crtc->plane,
3908 work->pending_flip_obj);
3909 }
3910
3911 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3912 {
3913 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 long ret;
3916
3917 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3918
3919 ret = wait_event_interruptible_timeout(
3920 dev_priv->pending_flip_queue,
3921 !intel_crtc_has_pending_flip(crtc),
3922 60*HZ);
3923
3924 if (ret < 0)
3925 return ret;
3926
3927 if (ret == 0) {
3928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929
3930 spin_lock_irq(&dev->event_lock);
3931 if (intel_crtc->unpin_work) {
3932 WARN_ONCE(1, "Removing stuck page flip\n");
3933 page_flip_completed(intel_crtc);
3934 }
3935 spin_unlock_irq(&dev->event_lock);
3936 }
3937
3938 return 0;
3939 }
3940
3941 /* Program iCLKIP clock to the desired frequency */
3942 static void lpt_program_iclkip(struct drm_crtc *crtc)
3943 {
3944 struct drm_device *dev = crtc->dev;
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3947 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3948 u32 temp;
3949
3950 mutex_lock(&dev_priv->sb_lock);
3951
3952 /* It is necessary to ungate the pixclk gate prior to programming
3953 * the divisors, and gate it back when it is done.
3954 */
3955 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3956
3957 /* Disable SSCCTL */
3958 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3959 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3960 SBI_SSCCTL_DISABLE,
3961 SBI_ICLK);
3962
3963 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3964 if (clock == 20000) {
3965 auxdiv = 1;
3966 divsel = 0x41;
3967 phaseinc = 0x20;
3968 } else {
3969 /* The iCLK virtual clock root frequency is in MHz,
3970 * but the adjusted_mode->crtc_clock in in KHz. To get the
3971 * divisors, it is necessary to divide one by another, so we
3972 * convert the virtual clock precision to KHz here for higher
3973 * precision.
3974 */
3975 u32 iclk_virtual_root_freq = 172800 * 1000;
3976 u32 iclk_pi_range = 64;
3977 u32 desired_divisor, msb_divisor_value, pi_value;
3978
3979 desired_divisor = (iclk_virtual_root_freq / clock);
3980 msb_divisor_value = desired_divisor / iclk_pi_range;
3981 pi_value = desired_divisor % iclk_pi_range;
3982
3983 auxdiv = 0;
3984 divsel = msb_divisor_value - 2;
3985 phaseinc = pi_value;
3986 }
3987
3988 /* This should not happen with any sane values */
3989 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3990 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3991 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3992 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3993
3994 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3995 clock,
3996 auxdiv,
3997 divsel,
3998 phasedir,
3999 phaseinc);
4000
4001 /* Program SSCDIVINTPHASE6 */
4002 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4003 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4004 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4005 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4006 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4007 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4008 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4009 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4010
4011 /* Program SSCAUXDIV */
4012 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4013 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4014 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4015 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4016
4017 /* Enable modulator and associated divider */
4018 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4019 temp &= ~SBI_SSCCTL_DISABLE;
4020 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4021
4022 /* Wait for initialization time */
4023 udelay(24);
4024
4025 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4026
4027 mutex_unlock(&dev_priv->sb_lock);
4028 }
4029
4030 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4031 enum pipe pch_transcoder)
4032 {
4033 struct drm_device *dev = crtc->base.dev;
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4036
4037 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4038 I915_READ(HTOTAL(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4040 I915_READ(HBLANK(cpu_transcoder)));
4041 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4042 I915_READ(HSYNC(cpu_transcoder)));
4043
4044 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4045 I915_READ(VTOTAL(cpu_transcoder)));
4046 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4047 I915_READ(VBLANK(cpu_transcoder)));
4048 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4049 I915_READ(VSYNC(cpu_transcoder)));
4050 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4051 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4052 }
4053
4054 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4055 {
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057 uint32_t temp;
4058
4059 temp = I915_READ(SOUTH_CHICKEN1);
4060 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4061 return;
4062
4063 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4064 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4065
4066 temp &= ~FDI_BC_BIFURCATION_SELECT;
4067 if (enable)
4068 temp |= FDI_BC_BIFURCATION_SELECT;
4069
4070 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4071 I915_WRITE(SOUTH_CHICKEN1, temp);
4072 POSTING_READ(SOUTH_CHICKEN1);
4073 }
4074
4075 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4076 {
4077 struct drm_device *dev = intel_crtc->base.dev;
4078
4079 switch (intel_crtc->pipe) {
4080 case PIPE_A:
4081 break;
4082 case PIPE_B:
4083 if (intel_crtc->config->fdi_lanes > 2)
4084 cpt_set_fdi_bc_bifurcation(dev, false);
4085 else
4086 cpt_set_fdi_bc_bifurcation(dev, true);
4087
4088 break;
4089 case PIPE_C:
4090 cpt_set_fdi_bc_bifurcation(dev, true);
4091
4092 break;
4093 default:
4094 BUG();
4095 }
4096 }
4097
4098 /* Return which DP Port should be selected for Transcoder DP control */
4099 static enum port
4100 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4101 {
4102 struct drm_device *dev = crtc->dev;
4103 struct intel_encoder *encoder;
4104
4105 for_each_encoder_on_crtc(dev, crtc, encoder) {
4106 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4107 encoder->type == INTEL_OUTPUT_EDP)
4108 return enc_to_dig_port(&encoder->base)->port;
4109 }
4110
4111 return -1;
4112 }
4113
4114 /*
4115 * Enable PCH resources required for PCH ports:
4116 * - PCH PLLs
4117 * - FDI training & RX/TX
4118 * - update transcoder timings
4119 * - DP transcoding bits
4120 * - transcoder
4121 */
4122 static void ironlake_pch_enable(struct drm_crtc *crtc)
4123 {
4124 struct drm_device *dev = crtc->dev;
4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4127 int pipe = intel_crtc->pipe;
4128 u32 temp;
4129
4130 assert_pch_transcoder_disabled(dev_priv, pipe);
4131
4132 if (IS_IVYBRIDGE(dev))
4133 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4134
4135 /* Write the TU size bits before fdi link training, so that error
4136 * detection works. */
4137 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4138 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4139
4140 /* For PCH output, training FDI link */
4141 dev_priv->display.fdi_link_train(crtc);
4142
4143 /* We need to program the right clock selection before writing the pixel
4144 * mutliplier into the DPLL. */
4145 if (HAS_PCH_CPT(dev)) {
4146 u32 sel;
4147
4148 temp = I915_READ(PCH_DPLL_SEL);
4149 temp |= TRANS_DPLL_ENABLE(pipe);
4150 sel = TRANS_DPLLB_SEL(pipe);
4151 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4152 temp |= sel;
4153 else
4154 temp &= ~sel;
4155 I915_WRITE(PCH_DPLL_SEL, temp);
4156 }
4157
4158 /* XXX: pch pll's can be enabled any time before we enable the PCH
4159 * transcoder, and we actually should do this to not upset any PCH
4160 * transcoder that already use the clock when we share it.
4161 *
4162 * Note that enable_shared_dpll tries to do the right thing, but
4163 * get_shared_dpll unconditionally resets the pll - we need that to have
4164 * the right LVDS enable sequence. */
4165 intel_enable_shared_dpll(intel_crtc);
4166
4167 /* set transcoder timing, panel must allow it */
4168 assert_panel_unlocked(dev_priv, pipe);
4169 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4170
4171 intel_fdi_normal_train(crtc);
4172
4173 /* For PCH DP, enable TRANS_DP_CTL */
4174 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4175 const struct drm_display_mode *adjusted_mode =
4176 &intel_crtc->config->base.adjusted_mode;
4177 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4178 i915_reg_t reg = TRANS_DP_CTL(pipe);
4179 temp = I915_READ(reg);
4180 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4181 TRANS_DP_SYNC_MASK |
4182 TRANS_DP_BPC_MASK);
4183 temp |= TRANS_DP_OUTPUT_ENABLE;
4184 temp |= bpc << 9; /* same format but at 11:9 */
4185
4186 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4187 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4188 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4189 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4190
4191 switch (intel_trans_dp_port_sel(crtc)) {
4192 case PORT_B:
4193 temp |= TRANS_DP_PORT_SEL_B;
4194 break;
4195 case PORT_C:
4196 temp |= TRANS_DP_PORT_SEL_C;
4197 break;
4198 case PORT_D:
4199 temp |= TRANS_DP_PORT_SEL_D;
4200 break;
4201 default:
4202 BUG();
4203 }
4204
4205 I915_WRITE(reg, temp);
4206 }
4207
4208 ironlake_enable_pch_transcoder(dev_priv, pipe);
4209 }
4210
4211 static void lpt_pch_enable(struct drm_crtc *crtc)
4212 {
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4217
4218 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4219
4220 lpt_program_iclkip(crtc);
4221
4222 /* Set transcoder timing. */
4223 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4224
4225 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4226 }
4227
4228 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4229 struct intel_crtc_state *crtc_state)
4230 {
4231 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4232 struct intel_shared_dpll *pll;
4233 struct intel_shared_dpll_config *shared_dpll;
4234 enum intel_dpll_id i;
4235 int max = dev_priv->num_shared_dpll;
4236
4237 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4238
4239 if (HAS_PCH_IBX(dev_priv->dev)) {
4240 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4241 i = (enum intel_dpll_id) crtc->pipe;
4242 pll = &dev_priv->shared_dplls[i];
4243
4244 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4245 crtc->base.base.id, pll->name);
4246
4247 WARN_ON(shared_dpll[i].crtc_mask);
4248
4249 goto found;
4250 }
4251
4252 if (IS_BROXTON(dev_priv->dev)) {
4253 /* PLL is attached to port in bxt */
4254 struct intel_encoder *encoder;
4255 struct intel_digital_port *intel_dig_port;
4256
4257 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4258 if (WARN_ON(!encoder))
4259 return NULL;
4260
4261 intel_dig_port = enc_to_dig_port(&encoder->base);
4262 /* 1:1 mapping between ports and PLLs */
4263 i = (enum intel_dpll_id)intel_dig_port->port;
4264 pll = &dev_priv->shared_dplls[i];
4265 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4266 crtc->base.base.id, pll->name);
4267 WARN_ON(shared_dpll[i].crtc_mask);
4268
4269 goto found;
4270 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4271 /* Do not consider SPLL */
4272 max = 2;
4273
4274 for (i = 0; i < max; i++) {
4275 pll = &dev_priv->shared_dplls[i];
4276
4277 /* Only want to check enabled timings first */
4278 if (shared_dpll[i].crtc_mask == 0)
4279 continue;
4280
4281 if (memcmp(&crtc_state->dpll_hw_state,
4282 &shared_dpll[i].hw_state,
4283 sizeof(crtc_state->dpll_hw_state)) == 0) {
4284 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4285 crtc->base.base.id, pll->name,
4286 shared_dpll[i].crtc_mask,
4287 pll->active);
4288 goto found;
4289 }
4290 }
4291
4292 /* Ok no matching timings, maybe there's a free one? */
4293 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4294 pll = &dev_priv->shared_dplls[i];
4295 if (shared_dpll[i].crtc_mask == 0) {
4296 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4297 crtc->base.base.id, pll->name);
4298 goto found;
4299 }
4300 }
4301
4302 return NULL;
4303
4304 found:
4305 if (shared_dpll[i].crtc_mask == 0)
4306 shared_dpll[i].hw_state =
4307 crtc_state->dpll_hw_state;
4308
4309 crtc_state->shared_dpll = i;
4310 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4311 pipe_name(crtc->pipe));
4312
4313 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4314
4315 return pll;
4316 }
4317
4318 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4319 {
4320 struct drm_i915_private *dev_priv = to_i915(state->dev);
4321 struct intel_shared_dpll_config *shared_dpll;
4322 struct intel_shared_dpll *pll;
4323 enum intel_dpll_id i;
4324
4325 if (!to_intel_atomic_state(state)->dpll_set)
4326 return;
4327
4328 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4329 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4330 pll = &dev_priv->shared_dplls[i];
4331 pll->config = shared_dpll[i];
4332 }
4333 }
4334
4335 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4336 {
4337 struct drm_i915_private *dev_priv = dev->dev_private;
4338 i915_reg_t dslreg = PIPEDSL(pipe);
4339 u32 temp;
4340
4341 temp = I915_READ(dslreg);
4342 udelay(500);
4343 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4344 if (wait_for(I915_READ(dslreg) != temp, 5))
4345 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4346 }
4347 }
4348
4349 static int
4350 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4351 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4352 int src_w, int src_h, int dst_w, int dst_h)
4353 {
4354 struct intel_crtc_scaler_state *scaler_state =
4355 &crtc_state->scaler_state;
4356 struct intel_crtc *intel_crtc =
4357 to_intel_crtc(crtc_state->base.crtc);
4358 int need_scaling;
4359
4360 need_scaling = intel_rotation_90_or_270(rotation) ?
4361 (src_h != dst_w || src_w != dst_h):
4362 (src_w != dst_w || src_h != dst_h);
4363
4364 /*
4365 * if plane is being disabled or scaler is no more required or force detach
4366 * - free scaler binded to this plane/crtc
4367 * - in order to do this, update crtc->scaler_usage
4368 *
4369 * Here scaler state in crtc_state is set free so that
4370 * scaler can be assigned to other user. Actual register
4371 * update to free the scaler is done in plane/panel-fit programming.
4372 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4373 */
4374 if (force_detach || !need_scaling) {
4375 if (*scaler_id >= 0) {
4376 scaler_state->scaler_users &= ~(1 << scaler_user);
4377 scaler_state->scalers[*scaler_id].in_use = 0;
4378
4379 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4380 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4381 intel_crtc->pipe, scaler_user, *scaler_id,
4382 scaler_state->scaler_users);
4383 *scaler_id = -1;
4384 }
4385 return 0;
4386 }
4387
4388 /* range checks */
4389 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4390 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4391
4392 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4393 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4394 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4395 "size is out of scaler range\n",
4396 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4397 return -EINVAL;
4398 }
4399
4400 /* mark this plane as a scaler user in crtc_state */
4401 scaler_state->scaler_users |= (1 << scaler_user);
4402 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4403 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4404 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4405 scaler_state->scaler_users);
4406
4407 return 0;
4408 }
4409
4410 /**
4411 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4412 *
4413 * @state: crtc's scaler state
4414 *
4415 * Return
4416 * 0 - scaler_usage updated successfully
4417 * error - requested scaling cannot be supported or other error condition
4418 */
4419 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4420 {
4421 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4422 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4423
4424 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4425 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4426
4427 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4428 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4429 state->pipe_src_w, state->pipe_src_h,
4430 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4431 }
4432
4433 /**
4434 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4435 *
4436 * @state: crtc's scaler state
4437 * @plane_state: atomic plane state to update
4438 *
4439 * Return
4440 * 0 - scaler_usage updated successfully
4441 * error - requested scaling cannot be supported or other error condition
4442 */
4443 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4444 struct intel_plane_state *plane_state)
4445 {
4446
4447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4448 struct intel_plane *intel_plane =
4449 to_intel_plane(plane_state->base.plane);
4450 struct drm_framebuffer *fb = plane_state->base.fb;
4451 int ret;
4452
4453 bool force_detach = !fb || !plane_state->visible;
4454
4455 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4456 intel_plane->base.base.id, intel_crtc->pipe,
4457 drm_plane_index(&intel_plane->base));
4458
4459 ret = skl_update_scaler(crtc_state, force_detach,
4460 drm_plane_index(&intel_plane->base),
4461 &plane_state->scaler_id,
4462 plane_state->base.rotation,
4463 drm_rect_width(&plane_state->src) >> 16,
4464 drm_rect_height(&plane_state->src) >> 16,
4465 drm_rect_width(&plane_state->dst),
4466 drm_rect_height(&plane_state->dst));
4467
4468 if (ret || plane_state->scaler_id < 0)
4469 return ret;
4470
4471 /* check colorkey */
4472 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4473 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4474 intel_plane->base.base.id);
4475 return -EINVAL;
4476 }
4477
4478 /* Check src format */
4479 switch (fb->pixel_format) {
4480 case DRM_FORMAT_RGB565:
4481 case DRM_FORMAT_XBGR8888:
4482 case DRM_FORMAT_XRGB8888:
4483 case DRM_FORMAT_ABGR8888:
4484 case DRM_FORMAT_ARGB8888:
4485 case DRM_FORMAT_XRGB2101010:
4486 case DRM_FORMAT_XBGR2101010:
4487 case DRM_FORMAT_YUYV:
4488 case DRM_FORMAT_YVYU:
4489 case DRM_FORMAT_UYVY:
4490 case DRM_FORMAT_VYUY:
4491 break;
4492 default:
4493 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4494 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4495 return -EINVAL;
4496 }
4497
4498 return 0;
4499 }
4500
4501 static void skylake_scaler_disable(struct intel_crtc *crtc)
4502 {
4503 int i;
4504
4505 for (i = 0; i < crtc->num_scalers; i++)
4506 skl_detach_scaler(crtc, i);
4507 }
4508
4509 static void skylake_pfit_enable(struct intel_crtc *crtc)
4510 {
4511 struct drm_device *dev = crtc->base.dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 int pipe = crtc->pipe;
4514 struct intel_crtc_scaler_state *scaler_state =
4515 &crtc->config->scaler_state;
4516
4517 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4518
4519 if (crtc->config->pch_pfit.enabled) {
4520 int id;
4521
4522 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4523 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4524 return;
4525 }
4526
4527 id = scaler_state->scaler_id;
4528 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4529 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4530 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4531 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4532
4533 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4534 }
4535 }
4536
4537 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->base.dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 int pipe = crtc->pipe;
4542
4543 if (crtc->config->pch_pfit.enabled) {
4544 /* Force use of hard-coded filter coefficients
4545 * as some pre-programmed values are broken,
4546 * e.g. x201.
4547 */
4548 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4549 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4550 PF_PIPE_SEL_IVB(pipe));
4551 else
4552 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4553 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4554 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4555 }
4556 }
4557
4558 void hsw_enable_ips(struct intel_crtc *crtc)
4559 {
4560 struct drm_device *dev = crtc->base.dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562
4563 if (!crtc->config->ips_enabled)
4564 return;
4565
4566 /* We can only enable IPS after we enable a plane and wait for a vblank */
4567 intel_wait_for_vblank(dev, crtc->pipe);
4568
4569 assert_plane_enabled(dev_priv, crtc->plane);
4570 if (IS_BROADWELL(dev)) {
4571 mutex_lock(&dev_priv->rps.hw_lock);
4572 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4573 mutex_unlock(&dev_priv->rps.hw_lock);
4574 /* Quoting Art Runyan: "its not safe to expect any particular
4575 * value in IPS_CTL bit 31 after enabling IPS through the
4576 * mailbox." Moreover, the mailbox may return a bogus state,
4577 * so we need to just enable it and continue on.
4578 */
4579 } else {
4580 I915_WRITE(IPS_CTL, IPS_ENABLE);
4581 /* The bit only becomes 1 in the next vblank, so this wait here
4582 * is essentially intel_wait_for_vblank. If we don't have this
4583 * and don't wait for vblanks until the end of crtc_enable, then
4584 * the HW state readout code will complain that the expected
4585 * IPS_CTL value is not the one we read. */
4586 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4587 DRM_ERROR("Timed out waiting for IPS enable\n");
4588 }
4589 }
4590
4591 void hsw_disable_ips(struct intel_crtc *crtc)
4592 {
4593 struct drm_device *dev = crtc->base.dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595
4596 if (!crtc->config->ips_enabled)
4597 return;
4598
4599 assert_plane_enabled(dev_priv, crtc->plane);
4600 if (IS_BROADWELL(dev)) {
4601 mutex_lock(&dev_priv->rps.hw_lock);
4602 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4603 mutex_unlock(&dev_priv->rps.hw_lock);
4604 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4605 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4606 DRM_ERROR("Timed out waiting for IPS disable\n");
4607 } else {
4608 I915_WRITE(IPS_CTL, 0);
4609 POSTING_READ(IPS_CTL);
4610 }
4611
4612 /* We need to wait for a vblank before we can disable the plane. */
4613 intel_wait_for_vblank(dev, crtc->pipe);
4614 }
4615
4616 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4617 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4618 {
4619 struct drm_device *dev = crtc->dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622 enum pipe pipe = intel_crtc->pipe;
4623 int i;
4624 bool reenable_ips = false;
4625
4626 /* The clocks have to be on to load the palette. */
4627 if (!crtc->state->active)
4628 return;
4629
4630 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4631 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4632 assert_dsi_pll_enabled(dev_priv);
4633 else
4634 assert_pll_enabled(dev_priv, pipe);
4635 }
4636
4637 /* Workaround : Do not read or write the pipe palette/gamma data while
4638 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4639 */
4640 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4641 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4642 GAMMA_MODE_MODE_SPLIT)) {
4643 hsw_disable_ips(intel_crtc);
4644 reenable_ips = true;
4645 }
4646
4647 for (i = 0; i < 256; i++) {
4648 i915_reg_t palreg;
4649
4650 if (HAS_GMCH_DISPLAY(dev))
4651 palreg = PALETTE(pipe, i);
4652 else
4653 palreg = LGC_PALETTE(pipe, i);
4654
4655 I915_WRITE(palreg,
4656 (intel_crtc->lut_r[i] << 16) |
4657 (intel_crtc->lut_g[i] << 8) |
4658 intel_crtc->lut_b[i]);
4659 }
4660
4661 if (reenable_ips)
4662 hsw_enable_ips(intel_crtc);
4663 }
4664
4665 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4666 {
4667 if (intel_crtc->overlay) {
4668 struct drm_device *dev = intel_crtc->base.dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 mutex_lock(&dev->struct_mutex);
4672 dev_priv->mm.interruptible = false;
4673 (void) intel_overlay_switch_off(intel_crtc->overlay);
4674 dev_priv->mm.interruptible = true;
4675 mutex_unlock(&dev->struct_mutex);
4676 }
4677
4678 /* Let userspace switch the overlay on again. In most cases userspace
4679 * has to recompute where to put it anyway.
4680 */
4681 }
4682
4683 /**
4684 * intel_post_enable_primary - Perform operations after enabling primary plane
4685 * @crtc: the CRTC whose primary plane was just enabled
4686 *
4687 * Performs potentially sleeping operations that must be done after the primary
4688 * plane is enabled, such as updating FBC and IPS. Note that this may be
4689 * called due to an explicit primary plane update, or due to an implicit
4690 * re-enable that is caused when a sprite plane is updated to no longer
4691 * completely hide the primary plane.
4692 */
4693 static void
4694 intel_post_enable_primary(struct drm_crtc *crtc)
4695 {
4696 struct drm_device *dev = crtc->dev;
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699 int pipe = intel_crtc->pipe;
4700
4701 /*
4702 * BDW signals flip done immediately if the plane
4703 * is disabled, even if the plane enable is already
4704 * armed to occur at the next vblank :(
4705 */
4706 if (IS_BROADWELL(dev))
4707 intel_wait_for_vblank(dev, pipe);
4708
4709 /*
4710 * FIXME IPS should be fine as long as one plane is
4711 * enabled, but in practice it seems to have problems
4712 * when going from primary only to sprite only and vice
4713 * versa.
4714 */
4715 hsw_enable_ips(intel_crtc);
4716
4717 /*
4718 * Gen2 reports pipe underruns whenever all planes are disabled.
4719 * So don't enable underrun reporting before at least some planes
4720 * are enabled.
4721 * FIXME: Need to fix the logic to work when we turn off all planes
4722 * but leave the pipe running.
4723 */
4724 if (IS_GEN2(dev))
4725 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4726
4727 /* Underruns don't always raise interrupts, so check manually. */
4728 intel_check_cpu_fifo_underruns(dev_priv);
4729 intel_check_pch_fifo_underruns(dev_priv);
4730 }
4731
4732 /**
4733 * intel_pre_disable_primary - Perform operations before disabling primary plane
4734 * @crtc: the CRTC whose primary plane is to be disabled
4735 *
4736 * Performs potentially sleeping operations that must be done before the
4737 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4738 * be called due to an explicit primary plane update, or due to an implicit
4739 * disable that is caused when a sprite plane completely hides the primary
4740 * plane.
4741 */
4742 static void
4743 intel_pre_disable_primary(struct drm_crtc *crtc)
4744 {
4745 struct drm_device *dev = crtc->dev;
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4748 int pipe = intel_crtc->pipe;
4749
4750 /*
4751 * Gen2 reports pipe underruns whenever all planes are disabled.
4752 * So diasble underrun reporting before all the planes get disabled.
4753 * FIXME: Need to fix the logic to work when we turn off all planes
4754 * but leave the pipe running.
4755 */
4756 if (IS_GEN2(dev))
4757 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4758
4759 /*
4760 * Vblank time updates from the shadow to live plane control register
4761 * are blocked if the memory self-refresh mode is active at that
4762 * moment. So to make sure the plane gets truly disabled, disable
4763 * first the self-refresh mode. The self-refresh enable bit in turn
4764 * will be checked/applied by the HW only at the next frame start
4765 * event which is after the vblank start event, so we need to have a
4766 * wait-for-vblank between disabling the plane and the pipe.
4767 */
4768 if (HAS_GMCH_DISPLAY(dev)) {
4769 intel_set_memory_cxsr(dev_priv, false);
4770 dev_priv->wm.vlv.cxsr = false;
4771 intel_wait_for_vblank(dev, pipe);
4772 }
4773
4774 /*
4775 * FIXME IPS should be fine as long as one plane is
4776 * enabled, but in practice it seems to have problems
4777 * when going from primary only to sprite only and vice
4778 * versa.
4779 */
4780 hsw_disable_ips(intel_crtc);
4781 }
4782
4783 static void intel_post_plane_update(struct intel_crtc *crtc)
4784 {
4785 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4786 struct drm_device *dev = crtc->base.dev;
4787 struct drm_i915_private *dev_priv = dev->dev_private;
4788
4789 if (atomic->wait_vblank)
4790 intel_wait_for_vblank(dev, crtc->pipe);
4791
4792 intel_frontbuffer_flip(dev, atomic->fb_bits);
4793
4794 if (atomic->disable_cxsr)
4795 crtc->wm.cxsr_allowed = true;
4796
4797 if (crtc->atomic.update_wm_post)
4798 intel_update_watermarks(&crtc->base);
4799
4800 if (atomic->update_fbc)
4801 intel_fbc_update(dev_priv);
4802
4803 if (atomic->post_enable_primary)
4804 intel_post_enable_primary(&crtc->base);
4805
4806 memset(atomic, 0, sizeof(*atomic));
4807 }
4808
4809 static void intel_pre_plane_update(struct intel_crtc *crtc)
4810 {
4811 struct drm_device *dev = crtc->base.dev;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4814
4815 if (atomic->disable_fbc)
4816 intel_fbc_disable_crtc(crtc);
4817
4818 if (crtc->atomic.disable_ips)
4819 hsw_disable_ips(crtc);
4820
4821 if (atomic->pre_disable_primary)
4822 intel_pre_disable_primary(&crtc->base);
4823
4824 if (atomic->disable_cxsr) {
4825 crtc->wm.cxsr_allowed = false;
4826 intel_set_memory_cxsr(dev_priv, false);
4827 }
4828 }
4829
4830 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4831 {
4832 struct drm_device *dev = crtc->dev;
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 struct drm_plane *p;
4835 int pipe = intel_crtc->pipe;
4836
4837 intel_crtc_dpms_overlay_disable(intel_crtc);
4838
4839 drm_for_each_plane_mask(p, dev, plane_mask)
4840 to_intel_plane(p)->disable_plane(p, crtc);
4841
4842 /*
4843 * FIXME: Once we grow proper nuclear flip support out of this we need
4844 * to compute the mask of flip planes precisely. For the time being
4845 * consider this a flip to a NULL plane.
4846 */
4847 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4848 }
4849
4850 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4851 {
4852 struct drm_device *dev = crtc->dev;
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855 struct intel_encoder *encoder;
4856 int pipe = intel_crtc->pipe;
4857
4858 if (WARN_ON(intel_crtc->active))
4859 return;
4860
4861 if (intel_crtc->config->has_pch_encoder)
4862 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4863
4864 if (intel_crtc->config->has_pch_encoder)
4865 intel_prepare_shared_dpll(intel_crtc);
4866
4867 if (intel_crtc->config->has_dp_encoder)
4868 intel_dp_set_m_n(intel_crtc, M1_N1);
4869
4870 intel_set_pipe_timings(intel_crtc);
4871
4872 if (intel_crtc->config->has_pch_encoder) {
4873 intel_cpu_transcoder_set_m_n(intel_crtc,
4874 &intel_crtc->config->fdi_m_n, NULL);
4875 }
4876
4877 ironlake_set_pipeconf(crtc);
4878
4879 intel_crtc->active = true;
4880
4881 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4882
4883 for_each_encoder_on_crtc(dev, crtc, encoder)
4884 if (encoder->pre_enable)
4885 encoder->pre_enable(encoder);
4886
4887 if (intel_crtc->config->has_pch_encoder) {
4888 /* Note: FDI PLL enabling _must_ be done before we enable the
4889 * cpu pipes, hence this is separate from all the other fdi/pch
4890 * enabling. */
4891 ironlake_fdi_pll_enable(intel_crtc);
4892 } else {
4893 assert_fdi_tx_disabled(dev_priv, pipe);
4894 assert_fdi_rx_disabled(dev_priv, pipe);
4895 }
4896
4897 ironlake_pfit_enable(intel_crtc);
4898
4899 /*
4900 * On ILK+ LUT must be loaded before the pipe is running but with
4901 * clocks enabled
4902 */
4903 intel_crtc_load_lut(crtc);
4904
4905 intel_update_watermarks(crtc);
4906 intel_enable_pipe(intel_crtc);
4907
4908 if (intel_crtc->config->has_pch_encoder)
4909 ironlake_pch_enable(crtc);
4910
4911 assert_vblank_disabled(crtc);
4912 drm_crtc_vblank_on(crtc);
4913
4914 for_each_encoder_on_crtc(dev, crtc, encoder)
4915 encoder->enable(encoder);
4916
4917 if (HAS_PCH_CPT(dev))
4918 cpt_verify_modeset(dev, intel_crtc->pipe);
4919
4920 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4921 if (intel_crtc->config->has_pch_encoder)
4922 intel_wait_for_vblank(dev, pipe);
4923 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4924 }
4925
4926 /* IPS only exists on ULT machines and is tied to pipe A. */
4927 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4928 {
4929 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4930 }
4931
4932 static void haswell_crtc_enable(struct drm_crtc *crtc)
4933 {
4934 struct drm_device *dev = crtc->dev;
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937 struct intel_encoder *encoder;
4938 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4939 struct intel_crtc_state *pipe_config =
4940 to_intel_crtc_state(crtc->state);
4941 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4942
4943 if (WARN_ON(intel_crtc->active))
4944 return;
4945
4946 if (intel_crtc->config->has_pch_encoder)
4947 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4948 false);
4949
4950 if (intel_crtc_to_shared_dpll(intel_crtc))
4951 intel_enable_shared_dpll(intel_crtc);
4952
4953 if (intel_crtc->config->has_dp_encoder)
4954 intel_dp_set_m_n(intel_crtc, M1_N1);
4955
4956 intel_set_pipe_timings(intel_crtc);
4957
4958 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4959 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4960 intel_crtc->config->pixel_multiplier - 1);
4961 }
4962
4963 if (intel_crtc->config->has_pch_encoder) {
4964 intel_cpu_transcoder_set_m_n(intel_crtc,
4965 &intel_crtc->config->fdi_m_n, NULL);
4966 }
4967
4968 haswell_set_pipeconf(crtc);
4969
4970 intel_set_pipe_csc(crtc);
4971
4972 intel_crtc->active = true;
4973
4974 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4975 for_each_encoder_on_crtc(dev, crtc, encoder) {
4976 if (encoder->pre_pll_enable)
4977 encoder->pre_pll_enable(encoder);
4978 if (encoder->pre_enable)
4979 encoder->pre_enable(encoder);
4980 }
4981
4982 if (intel_crtc->config->has_pch_encoder)
4983 dev_priv->display.fdi_link_train(crtc);
4984
4985 if (!is_dsi)
4986 intel_ddi_enable_pipe_clock(intel_crtc);
4987
4988 if (INTEL_INFO(dev)->gen >= 9)
4989 skylake_pfit_enable(intel_crtc);
4990 else
4991 ironlake_pfit_enable(intel_crtc);
4992
4993 /*
4994 * On ILK+ LUT must be loaded before the pipe is running but with
4995 * clocks enabled
4996 */
4997 intel_crtc_load_lut(crtc);
4998
4999 intel_ddi_set_pipe_settings(crtc);
5000 if (!is_dsi)
5001 intel_ddi_enable_transcoder_func(crtc);
5002
5003 intel_update_watermarks(crtc);
5004 intel_enable_pipe(intel_crtc);
5005
5006 if (intel_crtc->config->has_pch_encoder)
5007 lpt_pch_enable(crtc);
5008
5009 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5010 intel_ddi_set_vc_payload_alloc(crtc, true);
5011
5012 assert_vblank_disabled(crtc);
5013 drm_crtc_vblank_on(crtc);
5014
5015 for_each_encoder_on_crtc(dev, crtc, encoder) {
5016 encoder->enable(encoder);
5017 intel_opregion_notify_encoder(encoder, true);
5018 }
5019
5020 if (intel_crtc->config->has_pch_encoder)
5021 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5022 true);
5023
5024 /* If we change the relative order between pipe/planes enabling, we need
5025 * to change the workaround. */
5026 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5027 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5028 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5029 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5030 }
5031 }
5032
5033 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5034 {
5035 struct drm_device *dev = crtc->base.dev;
5036 struct drm_i915_private *dev_priv = dev->dev_private;
5037 int pipe = crtc->pipe;
5038
5039 /* To avoid upsetting the power well on haswell only disable the pfit if
5040 * it's in use. The hw state code will make sure we get this right. */
5041 if (force || crtc->config->pch_pfit.enabled) {
5042 I915_WRITE(PF_CTL(pipe), 0);
5043 I915_WRITE(PF_WIN_POS(pipe), 0);
5044 I915_WRITE(PF_WIN_SZ(pipe), 0);
5045 }
5046 }
5047
5048 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5049 {
5050 struct drm_device *dev = crtc->dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5053 struct intel_encoder *encoder;
5054 int pipe = intel_crtc->pipe;
5055
5056 if (intel_crtc->config->has_pch_encoder)
5057 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5058
5059 for_each_encoder_on_crtc(dev, crtc, encoder)
5060 encoder->disable(encoder);
5061
5062 drm_crtc_vblank_off(crtc);
5063 assert_vblank_disabled(crtc);
5064
5065 intel_disable_pipe(intel_crtc);
5066
5067 ironlake_pfit_disable(intel_crtc, false);
5068
5069 if (intel_crtc->config->has_pch_encoder)
5070 ironlake_fdi_disable(crtc);
5071
5072 for_each_encoder_on_crtc(dev, crtc, encoder)
5073 if (encoder->post_disable)
5074 encoder->post_disable(encoder);
5075
5076 if (intel_crtc->config->has_pch_encoder) {
5077 ironlake_disable_pch_transcoder(dev_priv, pipe);
5078
5079 if (HAS_PCH_CPT(dev)) {
5080 i915_reg_t reg;
5081 u32 temp;
5082
5083 /* disable TRANS_DP_CTL */
5084 reg = TRANS_DP_CTL(pipe);
5085 temp = I915_READ(reg);
5086 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5087 TRANS_DP_PORT_SEL_MASK);
5088 temp |= TRANS_DP_PORT_SEL_NONE;
5089 I915_WRITE(reg, temp);
5090
5091 /* disable DPLL_SEL */
5092 temp = I915_READ(PCH_DPLL_SEL);
5093 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5094 I915_WRITE(PCH_DPLL_SEL, temp);
5095 }
5096
5097 ironlake_fdi_pll_disable(intel_crtc);
5098 }
5099
5100 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5101 }
5102
5103 static void haswell_crtc_disable(struct drm_crtc *crtc)
5104 {
5105 struct drm_device *dev = crtc->dev;
5106 struct drm_i915_private *dev_priv = dev->dev_private;
5107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5108 struct intel_encoder *encoder;
5109 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5110 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5111
5112 if (intel_crtc->config->has_pch_encoder)
5113 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5114 false);
5115
5116 for_each_encoder_on_crtc(dev, crtc, encoder) {
5117 intel_opregion_notify_encoder(encoder, false);
5118 encoder->disable(encoder);
5119 }
5120
5121 drm_crtc_vblank_off(crtc);
5122 assert_vblank_disabled(crtc);
5123
5124 intel_disable_pipe(intel_crtc);
5125
5126 if (intel_crtc->config->dp_encoder_is_mst)
5127 intel_ddi_set_vc_payload_alloc(crtc, false);
5128
5129 if (!is_dsi)
5130 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5131
5132 if (INTEL_INFO(dev)->gen >= 9)
5133 skylake_scaler_disable(intel_crtc);
5134 else
5135 ironlake_pfit_disable(intel_crtc, false);
5136
5137 if (!is_dsi)
5138 intel_ddi_disable_pipe_clock(intel_crtc);
5139
5140 if (intel_crtc->config->has_pch_encoder) {
5141 lpt_disable_pch_transcoder(dev_priv);
5142 intel_ddi_fdi_disable(crtc);
5143 }
5144
5145 for_each_encoder_on_crtc(dev, crtc, encoder)
5146 if (encoder->post_disable)
5147 encoder->post_disable(encoder);
5148
5149 if (intel_crtc->config->has_pch_encoder)
5150 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5151 true);
5152 }
5153
5154 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5155 {
5156 struct drm_device *dev = crtc->base.dev;
5157 struct drm_i915_private *dev_priv = dev->dev_private;
5158 struct intel_crtc_state *pipe_config = crtc->config;
5159
5160 if (!pipe_config->gmch_pfit.control)
5161 return;
5162
5163 /*
5164 * The panel fitter should only be adjusted whilst the pipe is disabled,
5165 * according to register description and PRM.
5166 */
5167 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5168 assert_pipe_disabled(dev_priv, crtc->pipe);
5169
5170 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5171 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5172
5173 /* Border color in case we don't scale up to the full screen. Black by
5174 * default, change to something else for debugging. */
5175 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5176 }
5177
5178 static enum intel_display_power_domain port_to_power_domain(enum port port)
5179 {
5180 switch (port) {
5181 case PORT_A:
5182 return POWER_DOMAIN_PORT_DDI_A_LANES;
5183 case PORT_B:
5184 return POWER_DOMAIN_PORT_DDI_B_LANES;
5185 case PORT_C:
5186 return POWER_DOMAIN_PORT_DDI_C_LANES;
5187 case PORT_D:
5188 return POWER_DOMAIN_PORT_DDI_D_LANES;
5189 case PORT_E:
5190 return POWER_DOMAIN_PORT_DDI_E_LANES;
5191 default:
5192 MISSING_CASE(port);
5193 return POWER_DOMAIN_PORT_OTHER;
5194 }
5195 }
5196
5197 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5198 {
5199 switch (port) {
5200 case PORT_A:
5201 return POWER_DOMAIN_AUX_A;
5202 case PORT_B:
5203 return POWER_DOMAIN_AUX_B;
5204 case PORT_C:
5205 return POWER_DOMAIN_AUX_C;
5206 case PORT_D:
5207 return POWER_DOMAIN_AUX_D;
5208 case PORT_E:
5209 /* FIXME: Check VBT for actual wiring of PORT E */
5210 return POWER_DOMAIN_AUX_D;
5211 default:
5212 MISSING_CASE(port);
5213 return POWER_DOMAIN_AUX_A;
5214 }
5215 }
5216
5217 #define for_each_power_domain(domain, mask) \
5218 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5219 if ((1 << (domain)) & (mask))
5220
5221 enum intel_display_power_domain
5222 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5223 {
5224 struct drm_device *dev = intel_encoder->base.dev;
5225 struct intel_digital_port *intel_dig_port;
5226
5227 switch (intel_encoder->type) {
5228 case INTEL_OUTPUT_UNKNOWN:
5229 /* Only DDI platforms should ever use this output type */
5230 WARN_ON_ONCE(!HAS_DDI(dev));
5231 case INTEL_OUTPUT_DISPLAYPORT:
5232 case INTEL_OUTPUT_HDMI:
5233 case INTEL_OUTPUT_EDP:
5234 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5235 return port_to_power_domain(intel_dig_port->port);
5236 case INTEL_OUTPUT_DP_MST:
5237 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5238 return port_to_power_domain(intel_dig_port->port);
5239 case INTEL_OUTPUT_ANALOG:
5240 return POWER_DOMAIN_PORT_CRT;
5241 case INTEL_OUTPUT_DSI:
5242 return POWER_DOMAIN_PORT_DSI;
5243 default:
5244 return POWER_DOMAIN_PORT_OTHER;
5245 }
5246 }
5247
5248 enum intel_display_power_domain
5249 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5250 {
5251 struct drm_device *dev = intel_encoder->base.dev;
5252 struct intel_digital_port *intel_dig_port;
5253
5254 switch (intel_encoder->type) {
5255 case INTEL_OUTPUT_UNKNOWN:
5256 case INTEL_OUTPUT_HDMI:
5257 /*
5258 * Only DDI platforms should ever use these output types.
5259 * We can get here after the HDMI detect code has already set
5260 * the type of the shared encoder. Since we can't be sure
5261 * what's the status of the given connectors, play safe and
5262 * run the DP detection too.
5263 */
5264 WARN_ON_ONCE(!HAS_DDI(dev));
5265 case INTEL_OUTPUT_DISPLAYPORT:
5266 case INTEL_OUTPUT_EDP:
5267 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5268 return port_to_aux_power_domain(intel_dig_port->port);
5269 case INTEL_OUTPUT_DP_MST:
5270 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5271 return port_to_aux_power_domain(intel_dig_port->port);
5272 default:
5273 MISSING_CASE(intel_encoder->type);
5274 return POWER_DOMAIN_AUX_A;
5275 }
5276 }
5277
5278 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5279 {
5280 struct drm_device *dev = crtc->dev;
5281 struct intel_encoder *intel_encoder;
5282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5283 enum pipe pipe = intel_crtc->pipe;
5284 unsigned long mask;
5285 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5286
5287 if (!crtc->state->active)
5288 return 0;
5289
5290 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5291 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5292 if (intel_crtc->config->pch_pfit.enabled ||
5293 intel_crtc->config->pch_pfit.force_thru)
5294 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5295
5296 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5297 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5298
5299 return mask;
5300 }
5301
5302 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5303 {
5304 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5306 enum intel_display_power_domain domain;
5307 unsigned long domains, new_domains, old_domains;
5308
5309 old_domains = intel_crtc->enabled_power_domains;
5310 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5311
5312 domains = new_domains & ~old_domains;
5313
5314 for_each_power_domain(domain, domains)
5315 intel_display_power_get(dev_priv, domain);
5316
5317 return old_domains & ~new_domains;
5318 }
5319
5320 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5321 unsigned long domains)
5322 {
5323 enum intel_display_power_domain domain;
5324
5325 for_each_power_domain(domain, domains)
5326 intel_display_power_put(dev_priv, domain);
5327 }
5328
5329 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5330 {
5331 struct drm_device *dev = state->dev;
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 unsigned long put_domains[I915_MAX_PIPES] = {};
5334 struct drm_crtc_state *crtc_state;
5335 struct drm_crtc *crtc;
5336 int i;
5337
5338 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5339 if (needs_modeset(crtc->state))
5340 put_domains[to_intel_crtc(crtc)->pipe] =
5341 modeset_get_crtc_power_domains(crtc);
5342 }
5343
5344 if (dev_priv->display.modeset_commit_cdclk) {
5345 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5346
5347 if (cdclk != dev_priv->cdclk_freq &&
5348 !WARN_ON(!state->allow_modeset))
5349 dev_priv->display.modeset_commit_cdclk(state);
5350 }
5351
5352 for (i = 0; i < I915_MAX_PIPES; i++)
5353 if (put_domains[i])
5354 modeset_put_power_domains(dev_priv, put_domains[i]);
5355 }
5356
5357 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5358 {
5359 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5360
5361 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5362 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5363 return max_cdclk_freq;
5364 else if (IS_CHERRYVIEW(dev_priv))
5365 return max_cdclk_freq*95/100;
5366 else if (INTEL_INFO(dev_priv)->gen < 4)
5367 return 2*max_cdclk_freq*90/100;
5368 else
5369 return max_cdclk_freq*90/100;
5370 }
5371
5372 static void intel_update_max_cdclk(struct drm_device *dev)
5373 {
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375
5376 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5377 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5378
5379 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5380 dev_priv->max_cdclk_freq = 675000;
5381 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5382 dev_priv->max_cdclk_freq = 540000;
5383 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5384 dev_priv->max_cdclk_freq = 450000;
5385 else
5386 dev_priv->max_cdclk_freq = 337500;
5387 } else if (IS_BROADWELL(dev)) {
5388 /*
5389 * FIXME with extra cooling we can allow
5390 * 540 MHz for ULX and 675 Mhz for ULT.
5391 * How can we know if extra cooling is
5392 * available? PCI ID, VTB, something else?
5393 */
5394 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5395 dev_priv->max_cdclk_freq = 450000;
5396 else if (IS_BDW_ULX(dev))
5397 dev_priv->max_cdclk_freq = 450000;
5398 else if (IS_BDW_ULT(dev))
5399 dev_priv->max_cdclk_freq = 540000;
5400 else
5401 dev_priv->max_cdclk_freq = 675000;
5402 } else if (IS_CHERRYVIEW(dev)) {
5403 dev_priv->max_cdclk_freq = 320000;
5404 } else if (IS_VALLEYVIEW(dev)) {
5405 dev_priv->max_cdclk_freq = 400000;
5406 } else {
5407 /* otherwise assume cdclk is fixed */
5408 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5409 }
5410
5411 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5412
5413 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5414 dev_priv->max_cdclk_freq);
5415
5416 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5417 dev_priv->max_dotclk_freq);
5418 }
5419
5420 static void intel_update_cdclk(struct drm_device *dev)
5421 {
5422 struct drm_i915_private *dev_priv = dev->dev_private;
5423
5424 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5425 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5426 dev_priv->cdclk_freq);
5427
5428 /*
5429 * Program the gmbus_freq based on the cdclk frequency.
5430 * BSpec erroneously claims we should aim for 4MHz, but
5431 * in fact 1MHz is the correct frequency.
5432 */
5433 if (IS_VALLEYVIEW(dev)) {
5434 /*
5435 * Program the gmbus_freq based on the cdclk frequency.
5436 * BSpec erroneously claims we should aim for 4MHz, but
5437 * in fact 1MHz is the correct frequency.
5438 */
5439 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5440 }
5441
5442 if (dev_priv->max_cdclk_freq == 0)
5443 intel_update_max_cdclk(dev);
5444 }
5445
5446 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5447 {
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 uint32_t divider;
5450 uint32_t ratio;
5451 uint32_t current_freq;
5452 int ret;
5453
5454 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5455 switch (frequency) {
5456 case 144000:
5457 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5458 ratio = BXT_DE_PLL_RATIO(60);
5459 break;
5460 case 288000:
5461 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5462 ratio = BXT_DE_PLL_RATIO(60);
5463 break;
5464 case 384000:
5465 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5466 ratio = BXT_DE_PLL_RATIO(60);
5467 break;
5468 case 576000:
5469 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5470 ratio = BXT_DE_PLL_RATIO(60);
5471 break;
5472 case 624000:
5473 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5474 ratio = BXT_DE_PLL_RATIO(65);
5475 break;
5476 case 19200:
5477 /*
5478 * Bypass frequency with DE PLL disabled. Init ratio, divider
5479 * to suppress GCC warning.
5480 */
5481 ratio = 0;
5482 divider = 0;
5483 break;
5484 default:
5485 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5486
5487 return;
5488 }
5489
5490 mutex_lock(&dev_priv->rps.hw_lock);
5491 /* Inform power controller of upcoming frequency change */
5492 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5493 0x80000000);
5494 mutex_unlock(&dev_priv->rps.hw_lock);
5495
5496 if (ret) {
5497 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5498 ret, frequency);
5499 return;
5500 }
5501
5502 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5503 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5504 current_freq = current_freq * 500 + 1000;
5505
5506 /*
5507 * DE PLL has to be disabled when
5508 * - setting to 19.2MHz (bypass, PLL isn't used)
5509 * - before setting to 624MHz (PLL needs toggling)
5510 * - before setting to any frequency from 624MHz (PLL needs toggling)
5511 */
5512 if (frequency == 19200 || frequency == 624000 ||
5513 current_freq == 624000) {
5514 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5515 /* Timeout 200us */
5516 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5517 1))
5518 DRM_ERROR("timout waiting for DE PLL unlock\n");
5519 }
5520
5521 if (frequency != 19200) {
5522 uint32_t val;
5523
5524 val = I915_READ(BXT_DE_PLL_CTL);
5525 val &= ~BXT_DE_PLL_RATIO_MASK;
5526 val |= ratio;
5527 I915_WRITE(BXT_DE_PLL_CTL, val);
5528
5529 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5530 /* Timeout 200us */
5531 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5532 DRM_ERROR("timeout waiting for DE PLL lock\n");
5533
5534 val = I915_READ(CDCLK_CTL);
5535 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5536 val |= divider;
5537 /*
5538 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5539 * enable otherwise.
5540 */
5541 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5542 if (frequency >= 500000)
5543 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5544
5545 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5546 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5547 val |= (frequency - 1000) / 500;
5548 I915_WRITE(CDCLK_CTL, val);
5549 }
5550
5551 mutex_lock(&dev_priv->rps.hw_lock);
5552 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5553 DIV_ROUND_UP(frequency, 25000));
5554 mutex_unlock(&dev_priv->rps.hw_lock);
5555
5556 if (ret) {
5557 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5558 ret, frequency);
5559 return;
5560 }
5561
5562 intel_update_cdclk(dev);
5563 }
5564
5565 void broxton_init_cdclk(struct drm_device *dev)
5566 {
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568 uint32_t val;
5569
5570 /*
5571 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5572 * or else the reset will hang because there is no PCH to respond.
5573 * Move the handshake programming to initialization sequence.
5574 * Previously was left up to BIOS.
5575 */
5576 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5577 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5578 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5579
5580 /* Enable PG1 for cdclk */
5581 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5582
5583 /* check if cd clock is enabled */
5584 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5585 DRM_DEBUG_KMS("Display already initialized\n");
5586 return;
5587 }
5588
5589 /*
5590 * FIXME:
5591 * - The initial CDCLK needs to be read from VBT.
5592 * Need to make this change after VBT has changes for BXT.
5593 * - check if setting the max (or any) cdclk freq is really necessary
5594 * here, it belongs to modeset time
5595 */
5596 broxton_set_cdclk(dev, 624000);
5597
5598 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5599 POSTING_READ(DBUF_CTL);
5600
5601 udelay(10);
5602
5603 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5604 DRM_ERROR("DBuf power enable timeout!\n");
5605 }
5606
5607 void broxton_uninit_cdclk(struct drm_device *dev)
5608 {
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610
5611 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5612 POSTING_READ(DBUF_CTL);
5613
5614 udelay(10);
5615
5616 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5617 DRM_ERROR("DBuf power disable timeout!\n");
5618
5619 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5620 broxton_set_cdclk(dev, 19200);
5621
5622 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5623 }
5624
5625 static const struct skl_cdclk_entry {
5626 unsigned int freq;
5627 unsigned int vco;
5628 } skl_cdclk_frequencies[] = {
5629 { .freq = 308570, .vco = 8640 },
5630 { .freq = 337500, .vco = 8100 },
5631 { .freq = 432000, .vco = 8640 },
5632 { .freq = 450000, .vco = 8100 },
5633 { .freq = 540000, .vco = 8100 },
5634 { .freq = 617140, .vco = 8640 },
5635 { .freq = 675000, .vco = 8100 },
5636 };
5637
5638 static unsigned int skl_cdclk_decimal(unsigned int freq)
5639 {
5640 return (freq - 1000) / 500;
5641 }
5642
5643 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5644 {
5645 unsigned int i;
5646
5647 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5648 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5649
5650 if (e->freq == freq)
5651 return e->vco;
5652 }
5653
5654 return 8100;
5655 }
5656
5657 static void
5658 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5659 {
5660 unsigned int min_freq;
5661 u32 val;
5662
5663 /* select the minimum CDCLK before enabling DPLL 0 */
5664 val = I915_READ(CDCLK_CTL);
5665 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5666 val |= CDCLK_FREQ_337_308;
5667
5668 if (required_vco == 8640)
5669 min_freq = 308570;
5670 else
5671 min_freq = 337500;
5672
5673 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5674
5675 I915_WRITE(CDCLK_CTL, val);
5676 POSTING_READ(CDCLK_CTL);
5677
5678 /*
5679 * We always enable DPLL0 with the lowest link rate possible, but still
5680 * taking into account the VCO required to operate the eDP panel at the
5681 * desired frequency. The usual DP link rates operate with a VCO of
5682 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5683 * The modeset code is responsible for the selection of the exact link
5684 * rate later on, with the constraint of choosing a frequency that
5685 * works with required_vco.
5686 */
5687 val = I915_READ(DPLL_CTRL1);
5688
5689 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5690 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5691 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5692 if (required_vco == 8640)
5693 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5694 SKL_DPLL0);
5695 else
5696 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5697 SKL_DPLL0);
5698
5699 I915_WRITE(DPLL_CTRL1, val);
5700 POSTING_READ(DPLL_CTRL1);
5701
5702 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5703
5704 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5705 DRM_ERROR("DPLL0 not locked\n");
5706 }
5707
5708 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5709 {
5710 int ret;
5711 u32 val;
5712
5713 /* inform PCU we want to change CDCLK */
5714 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5715 mutex_lock(&dev_priv->rps.hw_lock);
5716 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5717 mutex_unlock(&dev_priv->rps.hw_lock);
5718
5719 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5720 }
5721
5722 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5723 {
5724 unsigned int i;
5725
5726 for (i = 0; i < 15; i++) {
5727 if (skl_cdclk_pcu_ready(dev_priv))
5728 return true;
5729 udelay(10);
5730 }
5731
5732 return false;
5733 }
5734
5735 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5736 {
5737 struct drm_device *dev = dev_priv->dev;
5738 u32 freq_select, pcu_ack;
5739
5740 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5741
5742 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5743 DRM_ERROR("failed to inform PCU about cdclk change\n");
5744 return;
5745 }
5746
5747 /* set CDCLK_CTL */
5748 switch(freq) {
5749 case 450000:
5750 case 432000:
5751 freq_select = CDCLK_FREQ_450_432;
5752 pcu_ack = 1;
5753 break;
5754 case 540000:
5755 freq_select = CDCLK_FREQ_540;
5756 pcu_ack = 2;
5757 break;
5758 case 308570:
5759 case 337500:
5760 default:
5761 freq_select = CDCLK_FREQ_337_308;
5762 pcu_ack = 0;
5763 break;
5764 case 617140:
5765 case 675000:
5766 freq_select = CDCLK_FREQ_675_617;
5767 pcu_ack = 3;
5768 break;
5769 }
5770
5771 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5772 POSTING_READ(CDCLK_CTL);
5773
5774 /* inform PCU of the change */
5775 mutex_lock(&dev_priv->rps.hw_lock);
5776 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5777 mutex_unlock(&dev_priv->rps.hw_lock);
5778
5779 intel_update_cdclk(dev);
5780 }
5781
5782 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5783 {
5784 /* disable DBUF power */
5785 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5786 POSTING_READ(DBUF_CTL);
5787
5788 udelay(10);
5789
5790 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5791 DRM_ERROR("DBuf power disable timeout\n");
5792
5793 /* disable DPLL0 */
5794 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5795 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5796 DRM_ERROR("Couldn't disable DPLL0\n");
5797 }
5798
5799 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5800 {
5801 unsigned int required_vco;
5802
5803 /* DPLL0 not enabled (happens on early BIOS versions) */
5804 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5805 /* enable DPLL0 */
5806 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5807 skl_dpll0_enable(dev_priv, required_vco);
5808 }
5809
5810 /* set CDCLK to the frequency the BIOS chose */
5811 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5812
5813 /* enable DBUF power */
5814 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5815 POSTING_READ(DBUF_CTL);
5816
5817 udelay(10);
5818
5819 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5820 DRM_ERROR("DBuf power enable timeout\n");
5821 }
5822
5823 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5824 {
5825 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5826 uint32_t cdctl = I915_READ(CDCLK_CTL);
5827 int freq = dev_priv->skl_boot_cdclk;
5828
5829 /*
5830 * check if the pre-os intialized the display
5831 * There is SWF18 scratchpad register defined which is set by the
5832 * pre-os which can be used by the OS drivers to check the status
5833 */
5834 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5835 goto sanitize;
5836
5837 /* Is PLL enabled and locked ? */
5838 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5839 goto sanitize;
5840
5841 /* DPLL okay; verify the cdclock
5842 *
5843 * Noticed in some instances that the freq selection is correct but
5844 * decimal part is programmed wrong from BIOS where pre-os does not
5845 * enable display. Verify the same as well.
5846 */
5847 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5848 /* All well; nothing to sanitize */
5849 return false;
5850 sanitize:
5851 /*
5852 * As of now initialize with max cdclk till
5853 * we get dynamic cdclk support
5854 * */
5855 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5856 skl_init_cdclk(dev_priv);
5857
5858 /* we did have to sanitize */
5859 return true;
5860 }
5861
5862 /* Adjust CDclk dividers to allow high res or save power if possible */
5863 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5864 {
5865 struct drm_i915_private *dev_priv = dev->dev_private;
5866 u32 val, cmd;
5867
5868 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5869 != dev_priv->cdclk_freq);
5870
5871 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5872 cmd = 2;
5873 else if (cdclk == 266667)
5874 cmd = 1;
5875 else
5876 cmd = 0;
5877
5878 mutex_lock(&dev_priv->rps.hw_lock);
5879 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5880 val &= ~DSPFREQGUAR_MASK;
5881 val |= (cmd << DSPFREQGUAR_SHIFT);
5882 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5883 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5884 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5885 50)) {
5886 DRM_ERROR("timed out waiting for CDclk change\n");
5887 }
5888 mutex_unlock(&dev_priv->rps.hw_lock);
5889
5890 mutex_lock(&dev_priv->sb_lock);
5891
5892 if (cdclk == 400000) {
5893 u32 divider;
5894
5895 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5896
5897 /* adjust cdclk divider */
5898 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5899 val &= ~CCK_FREQUENCY_VALUES;
5900 val |= divider;
5901 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5902
5903 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5904 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5905 50))
5906 DRM_ERROR("timed out waiting for CDclk change\n");
5907 }
5908
5909 /* adjust self-refresh exit latency value */
5910 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5911 val &= ~0x7f;
5912
5913 /*
5914 * For high bandwidth configs, we set a higher latency in the bunit
5915 * so that the core display fetch happens in time to avoid underruns.
5916 */
5917 if (cdclk == 400000)
5918 val |= 4500 / 250; /* 4.5 usec */
5919 else
5920 val |= 3000 / 250; /* 3.0 usec */
5921 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5922
5923 mutex_unlock(&dev_priv->sb_lock);
5924
5925 intel_update_cdclk(dev);
5926 }
5927
5928 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5929 {
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931 u32 val, cmd;
5932
5933 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5934 != dev_priv->cdclk_freq);
5935
5936 switch (cdclk) {
5937 case 333333:
5938 case 320000:
5939 case 266667:
5940 case 200000:
5941 break;
5942 default:
5943 MISSING_CASE(cdclk);
5944 return;
5945 }
5946
5947 /*
5948 * Specs are full of misinformation, but testing on actual
5949 * hardware has shown that we just need to write the desired
5950 * CCK divider into the Punit register.
5951 */
5952 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5953
5954 mutex_lock(&dev_priv->rps.hw_lock);
5955 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5956 val &= ~DSPFREQGUAR_MASK_CHV;
5957 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5958 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5959 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5960 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5961 50)) {
5962 DRM_ERROR("timed out waiting for CDclk change\n");
5963 }
5964 mutex_unlock(&dev_priv->rps.hw_lock);
5965
5966 intel_update_cdclk(dev);
5967 }
5968
5969 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5970 int max_pixclk)
5971 {
5972 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5973 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5974
5975 /*
5976 * Really only a few cases to deal with, as only 4 CDclks are supported:
5977 * 200MHz
5978 * 267MHz
5979 * 320/333MHz (depends on HPLL freq)
5980 * 400MHz (VLV only)
5981 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5982 * of the lower bin and adjust if needed.
5983 *
5984 * We seem to get an unstable or solid color picture at 200MHz.
5985 * Not sure what's wrong. For now use 200MHz only when all pipes
5986 * are off.
5987 */
5988 if (!IS_CHERRYVIEW(dev_priv) &&
5989 max_pixclk > freq_320*limit/100)
5990 return 400000;
5991 else if (max_pixclk > 266667*limit/100)
5992 return freq_320;
5993 else if (max_pixclk > 0)
5994 return 266667;
5995 else
5996 return 200000;
5997 }
5998
5999 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6000 int max_pixclk)
6001 {
6002 /*
6003 * FIXME:
6004 * - remove the guardband, it's not needed on BXT
6005 * - set 19.2MHz bypass frequency if there are no active pipes
6006 */
6007 if (max_pixclk > 576000*9/10)
6008 return 624000;
6009 else if (max_pixclk > 384000*9/10)
6010 return 576000;
6011 else if (max_pixclk > 288000*9/10)
6012 return 384000;
6013 else if (max_pixclk > 144000*9/10)
6014 return 288000;
6015 else
6016 return 144000;
6017 }
6018
6019 /* Compute the max pixel clock for new configuration. Uses atomic state if
6020 * that's non-NULL, look at current state otherwise. */
6021 static int intel_mode_max_pixclk(struct drm_device *dev,
6022 struct drm_atomic_state *state)
6023 {
6024 struct intel_crtc *intel_crtc;
6025 struct intel_crtc_state *crtc_state;
6026 int max_pixclk = 0;
6027
6028 for_each_intel_crtc(dev, intel_crtc) {
6029 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6030 if (IS_ERR(crtc_state))
6031 return PTR_ERR(crtc_state);
6032
6033 if (!crtc_state->base.enable)
6034 continue;
6035
6036 max_pixclk = max(max_pixclk,
6037 crtc_state->base.adjusted_mode.crtc_clock);
6038 }
6039
6040 return max_pixclk;
6041 }
6042
6043 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6044 {
6045 struct drm_device *dev = state->dev;
6046 struct drm_i915_private *dev_priv = dev->dev_private;
6047 int max_pixclk = intel_mode_max_pixclk(dev, state);
6048
6049 if (max_pixclk < 0)
6050 return max_pixclk;
6051
6052 to_intel_atomic_state(state)->cdclk =
6053 valleyview_calc_cdclk(dev_priv, max_pixclk);
6054
6055 return 0;
6056 }
6057
6058 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6059 {
6060 struct drm_device *dev = state->dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 int max_pixclk = intel_mode_max_pixclk(dev, state);
6063
6064 if (max_pixclk < 0)
6065 return max_pixclk;
6066
6067 to_intel_atomic_state(state)->cdclk =
6068 broxton_calc_cdclk(dev_priv, max_pixclk);
6069
6070 return 0;
6071 }
6072
6073 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6074 {
6075 unsigned int credits, default_credits;
6076
6077 if (IS_CHERRYVIEW(dev_priv))
6078 default_credits = PFI_CREDIT(12);
6079 else
6080 default_credits = PFI_CREDIT(8);
6081
6082 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6083 /* CHV suggested value is 31 or 63 */
6084 if (IS_CHERRYVIEW(dev_priv))
6085 credits = PFI_CREDIT_63;
6086 else
6087 credits = PFI_CREDIT(15);
6088 } else {
6089 credits = default_credits;
6090 }
6091
6092 /*
6093 * WA - write default credits before re-programming
6094 * FIXME: should we also set the resend bit here?
6095 */
6096 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6097 default_credits);
6098
6099 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6100 credits | PFI_CREDIT_RESEND);
6101
6102 /*
6103 * FIXME is this guaranteed to clear
6104 * immediately or should we poll for it?
6105 */
6106 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6107 }
6108
6109 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6110 {
6111 struct drm_device *dev = old_state->dev;
6112 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6113 struct drm_i915_private *dev_priv = dev->dev_private;
6114
6115 /*
6116 * FIXME: We can end up here with all power domains off, yet
6117 * with a CDCLK frequency other than the minimum. To account
6118 * for this take the PIPE-A power domain, which covers the HW
6119 * blocks needed for the following programming. This can be
6120 * removed once it's guaranteed that we get here either with
6121 * the minimum CDCLK set, or the required power domains
6122 * enabled.
6123 */
6124 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6125
6126 if (IS_CHERRYVIEW(dev))
6127 cherryview_set_cdclk(dev, req_cdclk);
6128 else
6129 valleyview_set_cdclk(dev, req_cdclk);
6130
6131 vlv_program_pfi_credits(dev_priv);
6132
6133 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6134 }
6135
6136 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6137 {
6138 struct drm_device *dev = crtc->dev;
6139 struct drm_i915_private *dev_priv = to_i915(dev);
6140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6141 struct intel_encoder *encoder;
6142 int pipe = intel_crtc->pipe;
6143 bool is_dsi;
6144
6145 if (WARN_ON(intel_crtc->active))
6146 return;
6147
6148 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6149
6150 if (intel_crtc->config->has_dp_encoder)
6151 intel_dp_set_m_n(intel_crtc, M1_N1);
6152
6153 intel_set_pipe_timings(intel_crtc);
6154
6155 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157
6158 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6159 I915_WRITE(CHV_CANVAS(pipe), 0);
6160 }
6161
6162 i9xx_set_pipeconf(intel_crtc);
6163
6164 intel_crtc->active = true;
6165
6166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6167
6168 for_each_encoder_on_crtc(dev, crtc, encoder)
6169 if (encoder->pre_pll_enable)
6170 encoder->pre_pll_enable(encoder);
6171
6172 if (!is_dsi) {
6173 if (IS_CHERRYVIEW(dev)) {
6174 chv_prepare_pll(intel_crtc, intel_crtc->config);
6175 chv_enable_pll(intel_crtc, intel_crtc->config);
6176 } else {
6177 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6178 vlv_enable_pll(intel_crtc, intel_crtc->config);
6179 }
6180 }
6181
6182 for_each_encoder_on_crtc(dev, crtc, encoder)
6183 if (encoder->pre_enable)
6184 encoder->pre_enable(encoder);
6185
6186 i9xx_pfit_enable(intel_crtc);
6187
6188 intel_crtc_load_lut(crtc);
6189
6190 intel_enable_pipe(intel_crtc);
6191
6192 assert_vblank_disabled(crtc);
6193 drm_crtc_vblank_on(crtc);
6194
6195 for_each_encoder_on_crtc(dev, crtc, encoder)
6196 encoder->enable(encoder);
6197 }
6198
6199 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6200 {
6201 struct drm_device *dev = crtc->base.dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203
6204 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6205 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6206 }
6207
6208 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6209 {
6210 struct drm_device *dev = crtc->dev;
6211 struct drm_i915_private *dev_priv = to_i915(dev);
6212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6213 struct intel_encoder *encoder;
6214 int pipe = intel_crtc->pipe;
6215
6216 if (WARN_ON(intel_crtc->active))
6217 return;
6218
6219 i9xx_set_pll_dividers(intel_crtc);
6220
6221 if (intel_crtc->config->has_dp_encoder)
6222 intel_dp_set_m_n(intel_crtc, M1_N1);
6223
6224 intel_set_pipe_timings(intel_crtc);
6225
6226 i9xx_set_pipeconf(intel_crtc);
6227
6228 intel_crtc->active = true;
6229
6230 if (!IS_GEN2(dev))
6231 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6232
6233 for_each_encoder_on_crtc(dev, crtc, encoder)
6234 if (encoder->pre_enable)
6235 encoder->pre_enable(encoder);
6236
6237 i9xx_enable_pll(intel_crtc);
6238
6239 i9xx_pfit_enable(intel_crtc);
6240
6241 intel_crtc_load_lut(crtc);
6242
6243 intel_update_watermarks(crtc);
6244 intel_enable_pipe(intel_crtc);
6245
6246 assert_vblank_disabled(crtc);
6247 drm_crtc_vblank_on(crtc);
6248
6249 for_each_encoder_on_crtc(dev, crtc, encoder)
6250 encoder->enable(encoder);
6251 }
6252
6253 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6254 {
6255 struct drm_device *dev = crtc->base.dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257
6258 if (!crtc->config->gmch_pfit.control)
6259 return;
6260
6261 assert_pipe_disabled(dev_priv, crtc->pipe);
6262
6263 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6264 I915_READ(PFIT_CONTROL));
6265 I915_WRITE(PFIT_CONTROL, 0);
6266 }
6267
6268 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6269 {
6270 struct drm_device *dev = crtc->dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273 struct intel_encoder *encoder;
6274 int pipe = intel_crtc->pipe;
6275
6276 /*
6277 * On gen2 planes are double buffered but the pipe isn't, so we must
6278 * wait for planes to fully turn off before disabling the pipe.
6279 * We also need to wait on all gmch platforms because of the
6280 * self-refresh mode constraint explained above.
6281 */
6282 intel_wait_for_vblank(dev, pipe);
6283
6284 for_each_encoder_on_crtc(dev, crtc, encoder)
6285 encoder->disable(encoder);
6286
6287 drm_crtc_vblank_off(crtc);
6288 assert_vblank_disabled(crtc);
6289
6290 intel_disable_pipe(intel_crtc);
6291
6292 i9xx_pfit_disable(intel_crtc);
6293
6294 for_each_encoder_on_crtc(dev, crtc, encoder)
6295 if (encoder->post_disable)
6296 encoder->post_disable(encoder);
6297
6298 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6299 if (IS_CHERRYVIEW(dev))
6300 chv_disable_pll(dev_priv, pipe);
6301 else if (IS_VALLEYVIEW(dev))
6302 vlv_disable_pll(dev_priv, pipe);
6303 else
6304 i9xx_disable_pll(intel_crtc);
6305 }
6306
6307 for_each_encoder_on_crtc(dev, crtc, encoder)
6308 if (encoder->post_pll_disable)
6309 encoder->post_pll_disable(encoder);
6310
6311 if (!IS_GEN2(dev))
6312 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6313 }
6314
6315 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6316 {
6317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6318 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6319 enum intel_display_power_domain domain;
6320 unsigned long domains;
6321
6322 if (!intel_crtc->active)
6323 return;
6324
6325 if (to_intel_plane_state(crtc->primary->state)->visible) {
6326 WARN_ON(intel_crtc->unpin_work);
6327
6328 intel_pre_disable_primary(crtc);
6329
6330 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6331 to_intel_plane_state(crtc->primary->state)->visible = false;
6332 }
6333
6334 dev_priv->display.crtc_disable(crtc);
6335 intel_crtc->active = false;
6336 intel_update_watermarks(crtc);
6337 intel_disable_shared_dpll(intel_crtc);
6338
6339 domains = intel_crtc->enabled_power_domains;
6340 for_each_power_domain(domain, domains)
6341 intel_display_power_put(dev_priv, domain);
6342 intel_crtc->enabled_power_domains = 0;
6343 }
6344
6345 /*
6346 * turn all crtc's off, but do not adjust state
6347 * This has to be paired with a call to intel_modeset_setup_hw_state.
6348 */
6349 int intel_display_suspend(struct drm_device *dev)
6350 {
6351 struct drm_mode_config *config = &dev->mode_config;
6352 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6353 struct drm_atomic_state *state;
6354 struct drm_crtc *crtc;
6355 unsigned crtc_mask = 0;
6356 int ret = 0;
6357
6358 if (WARN_ON(!ctx))
6359 return 0;
6360
6361 lockdep_assert_held(&ctx->ww_ctx);
6362 state = drm_atomic_state_alloc(dev);
6363 if (WARN_ON(!state))
6364 return -ENOMEM;
6365
6366 state->acquire_ctx = ctx;
6367 state->allow_modeset = true;
6368
6369 for_each_crtc(dev, crtc) {
6370 struct drm_crtc_state *crtc_state =
6371 drm_atomic_get_crtc_state(state, crtc);
6372
6373 ret = PTR_ERR_OR_ZERO(crtc_state);
6374 if (ret)
6375 goto free;
6376
6377 if (!crtc_state->active)
6378 continue;
6379
6380 crtc_state->active = false;
6381 crtc_mask |= 1 << drm_crtc_index(crtc);
6382 }
6383
6384 if (crtc_mask) {
6385 ret = drm_atomic_commit(state);
6386
6387 if (!ret) {
6388 for_each_crtc(dev, crtc)
6389 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6390 crtc->state->active = true;
6391
6392 return ret;
6393 }
6394 }
6395
6396 free:
6397 if (ret)
6398 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6399 drm_atomic_state_free(state);
6400 return ret;
6401 }
6402
6403 void intel_encoder_destroy(struct drm_encoder *encoder)
6404 {
6405 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6406
6407 drm_encoder_cleanup(encoder);
6408 kfree(intel_encoder);
6409 }
6410
6411 /* Cross check the actual hw state with our own modeset state tracking (and it's
6412 * internal consistency). */
6413 static void intel_connector_check_state(struct intel_connector *connector)
6414 {
6415 struct drm_crtc *crtc = connector->base.state->crtc;
6416
6417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6418 connector->base.base.id,
6419 connector->base.name);
6420
6421 if (connector->get_hw_state(connector)) {
6422 struct intel_encoder *encoder = connector->encoder;
6423 struct drm_connector_state *conn_state = connector->base.state;
6424
6425 I915_STATE_WARN(!crtc,
6426 "connector enabled without attached crtc\n");
6427
6428 if (!crtc)
6429 return;
6430
6431 I915_STATE_WARN(!crtc->state->active,
6432 "connector is active, but attached crtc isn't\n");
6433
6434 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6435 return;
6436
6437 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6438 "atomic encoder doesn't match attached encoder\n");
6439
6440 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6441 "attached encoder crtc differs from connector crtc\n");
6442 } else {
6443 I915_STATE_WARN(crtc && crtc->state->active,
6444 "attached crtc is active, but connector isn't\n");
6445 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6446 "best encoder set without crtc!\n");
6447 }
6448 }
6449
6450 int intel_connector_init(struct intel_connector *connector)
6451 {
6452 struct drm_connector_state *connector_state;
6453
6454 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6455 if (!connector_state)
6456 return -ENOMEM;
6457
6458 connector->base.state = connector_state;
6459 return 0;
6460 }
6461
6462 struct intel_connector *intel_connector_alloc(void)
6463 {
6464 struct intel_connector *connector;
6465
6466 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6467 if (!connector)
6468 return NULL;
6469
6470 if (intel_connector_init(connector) < 0) {
6471 kfree(connector);
6472 return NULL;
6473 }
6474
6475 return connector;
6476 }
6477
6478 /* Simple connector->get_hw_state implementation for encoders that support only
6479 * one connector and no cloning and hence the encoder state determines the state
6480 * of the connector. */
6481 bool intel_connector_get_hw_state(struct intel_connector *connector)
6482 {
6483 enum pipe pipe = 0;
6484 struct intel_encoder *encoder = connector->encoder;
6485
6486 return encoder->get_hw_state(encoder, &pipe);
6487 }
6488
6489 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6490 {
6491 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6492 return crtc_state->fdi_lanes;
6493
6494 return 0;
6495 }
6496
6497 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6498 struct intel_crtc_state *pipe_config)
6499 {
6500 struct drm_atomic_state *state = pipe_config->base.state;
6501 struct intel_crtc *other_crtc;
6502 struct intel_crtc_state *other_crtc_state;
6503
6504 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6505 pipe_name(pipe), pipe_config->fdi_lanes);
6506 if (pipe_config->fdi_lanes > 4) {
6507 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6508 pipe_name(pipe), pipe_config->fdi_lanes);
6509 return -EINVAL;
6510 }
6511
6512 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6513 if (pipe_config->fdi_lanes > 2) {
6514 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6515 pipe_config->fdi_lanes);
6516 return -EINVAL;
6517 } else {
6518 return 0;
6519 }
6520 }
6521
6522 if (INTEL_INFO(dev)->num_pipes == 2)
6523 return 0;
6524
6525 /* Ivybridge 3 pipe is really complicated */
6526 switch (pipe) {
6527 case PIPE_A:
6528 return 0;
6529 case PIPE_B:
6530 if (pipe_config->fdi_lanes <= 2)
6531 return 0;
6532
6533 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6534 other_crtc_state =
6535 intel_atomic_get_crtc_state(state, other_crtc);
6536 if (IS_ERR(other_crtc_state))
6537 return PTR_ERR(other_crtc_state);
6538
6539 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6540 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6541 pipe_name(pipe), pipe_config->fdi_lanes);
6542 return -EINVAL;
6543 }
6544 return 0;
6545 case PIPE_C:
6546 if (pipe_config->fdi_lanes > 2) {
6547 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6548 pipe_name(pipe), pipe_config->fdi_lanes);
6549 return -EINVAL;
6550 }
6551
6552 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6553 other_crtc_state =
6554 intel_atomic_get_crtc_state(state, other_crtc);
6555 if (IS_ERR(other_crtc_state))
6556 return PTR_ERR(other_crtc_state);
6557
6558 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6559 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6560 return -EINVAL;
6561 }
6562 return 0;
6563 default:
6564 BUG();
6565 }
6566 }
6567
6568 #define RETRY 1
6569 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6570 struct intel_crtc_state *pipe_config)
6571 {
6572 struct drm_device *dev = intel_crtc->base.dev;
6573 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6574 int lane, link_bw, fdi_dotclock, ret;
6575 bool needs_recompute = false;
6576
6577 retry:
6578 /* FDI is a binary signal running at ~2.7GHz, encoding
6579 * each output octet as 10 bits. The actual frequency
6580 * is stored as a divider into a 100MHz clock, and the
6581 * mode pixel clock is stored in units of 1KHz.
6582 * Hence the bw of each lane in terms of the mode signal
6583 * is:
6584 */
6585 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6586
6587 fdi_dotclock = adjusted_mode->crtc_clock;
6588
6589 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6590 pipe_config->pipe_bpp);
6591
6592 pipe_config->fdi_lanes = lane;
6593
6594 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6595 link_bw, &pipe_config->fdi_m_n);
6596
6597 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6598 intel_crtc->pipe, pipe_config);
6599 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6600 pipe_config->pipe_bpp -= 2*3;
6601 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6602 pipe_config->pipe_bpp);
6603 needs_recompute = true;
6604 pipe_config->bw_constrained = true;
6605
6606 goto retry;
6607 }
6608
6609 if (needs_recompute)
6610 return RETRY;
6611
6612 return ret;
6613 }
6614
6615 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6616 struct intel_crtc_state *pipe_config)
6617 {
6618 if (pipe_config->pipe_bpp > 24)
6619 return false;
6620
6621 /* HSW can handle pixel rate up to cdclk? */
6622 if (IS_HASWELL(dev_priv->dev))
6623 return true;
6624
6625 /*
6626 * We compare against max which means we must take
6627 * the increased cdclk requirement into account when
6628 * calculating the new cdclk.
6629 *
6630 * Should measure whether using a lower cdclk w/o IPS
6631 */
6632 return ilk_pipe_pixel_rate(pipe_config) <=
6633 dev_priv->max_cdclk_freq * 95 / 100;
6634 }
6635
6636 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6637 struct intel_crtc_state *pipe_config)
6638 {
6639 struct drm_device *dev = crtc->base.dev;
6640 struct drm_i915_private *dev_priv = dev->dev_private;
6641
6642 pipe_config->ips_enabled = i915.enable_ips &&
6643 hsw_crtc_supports_ips(crtc) &&
6644 pipe_config_supports_ips(dev_priv, pipe_config);
6645 }
6646
6647 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6648 {
6649 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6650
6651 /* GDG double wide on either pipe, otherwise pipe A only */
6652 return INTEL_INFO(dev_priv)->gen < 4 &&
6653 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6654 }
6655
6656 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6657 struct intel_crtc_state *pipe_config)
6658 {
6659 struct drm_device *dev = crtc->base.dev;
6660 struct drm_i915_private *dev_priv = dev->dev_private;
6661 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6662
6663 /* FIXME should check pixel clock limits on all platforms */
6664 if (INTEL_INFO(dev)->gen < 4) {
6665 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6666
6667 /*
6668 * Enable double wide mode when the dot clock
6669 * is > 90% of the (display) core speed.
6670 */
6671 if (intel_crtc_supports_double_wide(crtc) &&
6672 adjusted_mode->crtc_clock > clock_limit) {
6673 clock_limit *= 2;
6674 pipe_config->double_wide = true;
6675 }
6676
6677 if (adjusted_mode->crtc_clock > clock_limit) {
6678 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6679 adjusted_mode->crtc_clock, clock_limit,
6680 yesno(pipe_config->double_wide));
6681 return -EINVAL;
6682 }
6683 }
6684
6685 /*
6686 * Pipe horizontal size must be even in:
6687 * - DVO ganged mode
6688 * - LVDS dual channel mode
6689 * - Double wide pipe
6690 */
6691 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6692 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6693 pipe_config->pipe_src_w &= ~1;
6694
6695 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6696 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6697 */
6698 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6699 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6700 return -EINVAL;
6701
6702 if (HAS_IPS(dev))
6703 hsw_compute_ips_config(crtc, pipe_config);
6704
6705 if (pipe_config->has_pch_encoder)
6706 return ironlake_fdi_compute_config(crtc, pipe_config);
6707
6708 return 0;
6709 }
6710
6711 static int skylake_get_display_clock_speed(struct drm_device *dev)
6712 {
6713 struct drm_i915_private *dev_priv = to_i915(dev);
6714 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6715 uint32_t cdctl = I915_READ(CDCLK_CTL);
6716 uint32_t linkrate;
6717
6718 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6719 return 24000; /* 24MHz is the cd freq with NSSC ref */
6720
6721 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6722 return 540000;
6723
6724 linkrate = (I915_READ(DPLL_CTRL1) &
6725 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6726
6727 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6728 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6729 /* vco 8640 */
6730 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6731 case CDCLK_FREQ_450_432:
6732 return 432000;
6733 case CDCLK_FREQ_337_308:
6734 return 308570;
6735 case CDCLK_FREQ_675_617:
6736 return 617140;
6737 default:
6738 WARN(1, "Unknown cd freq selection\n");
6739 }
6740 } else {
6741 /* vco 8100 */
6742 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6743 case CDCLK_FREQ_450_432:
6744 return 450000;
6745 case CDCLK_FREQ_337_308:
6746 return 337500;
6747 case CDCLK_FREQ_675_617:
6748 return 675000;
6749 default:
6750 WARN(1, "Unknown cd freq selection\n");
6751 }
6752 }
6753
6754 /* error case, do as if DPLL0 isn't enabled */
6755 return 24000;
6756 }
6757
6758 static int broxton_get_display_clock_speed(struct drm_device *dev)
6759 {
6760 struct drm_i915_private *dev_priv = to_i915(dev);
6761 uint32_t cdctl = I915_READ(CDCLK_CTL);
6762 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6763 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6764 int cdclk;
6765
6766 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6767 return 19200;
6768
6769 cdclk = 19200 * pll_ratio / 2;
6770
6771 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6772 case BXT_CDCLK_CD2X_DIV_SEL_1:
6773 return cdclk; /* 576MHz or 624MHz */
6774 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6775 return cdclk * 2 / 3; /* 384MHz */
6776 case BXT_CDCLK_CD2X_DIV_SEL_2:
6777 return cdclk / 2; /* 288MHz */
6778 case BXT_CDCLK_CD2X_DIV_SEL_4:
6779 return cdclk / 4; /* 144MHz */
6780 }
6781
6782 /* error case, do as if DE PLL isn't enabled */
6783 return 19200;
6784 }
6785
6786 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6787 {
6788 struct drm_i915_private *dev_priv = dev->dev_private;
6789 uint32_t lcpll = I915_READ(LCPLL_CTL);
6790 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6791
6792 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6793 return 800000;
6794 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6795 return 450000;
6796 else if (freq == LCPLL_CLK_FREQ_450)
6797 return 450000;
6798 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6799 return 540000;
6800 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6801 return 337500;
6802 else
6803 return 675000;
6804 }
6805
6806 static int haswell_get_display_clock_speed(struct drm_device *dev)
6807 {
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 uint32_t lcpll = I915_READ(LCPLL_CTL);
6810 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6811
6812 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6813 return 800000;
6814 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6815 return 450000;
6816 else if (freq == LCPLL_CLK_FREQ_450)
6817 return 450000;
6818 else if (IS_HSW_ULT(dev))
6819 return 337500;
6820 else
6821 return 540000;
6822 }
6823
6824 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6825 {
6826 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6827 CCK_DISPLAY_CLOCK_CONTROL);
6828 }
6829
6830 static int ilk_get_display_clock_speed(struct drm_device *dev)
6831 {
6832 return 450000;
6833 }
6834
6835 static int i945_get_display_clock_speed(struct drm_device *dev)
6836 {
6837 return 400000;
6838 }
6839
6840 static int i915_get_display_clock_speed(struct drm_device *dev)
6841 {
6842 return 333333;
6843 }
6844
6845 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6846 {
6847 return 200000;
6848 }
6849
6850 static int pnv_get_display_clock_speed(struct drm_device *dev)
6851 {
6852 u16 gcfgc = 0;
6853
6854 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6855
6856 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6857 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6858 return 266667;
6859 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6860 return 333333;
6861 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6862 return 444444;
6863 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6864 return 200000;
6865 default:
6866 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6867 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6868 return 133333;
6869 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6870 return 166667;
6871 }
6872 }
6873
6874 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6875 {
6876 u16 gcfgc = 0;
6877
6878 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6879
6880 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6881 return 133333;
6882 else {
6883 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6884 case GC_DISPLAY_CLOCK_333_MHZ:
6885 return 333333;
6886 default:
6887 case GC_DISPLAY_CLOCK_190_200_MHZ:
6888 return 190000;
6889 }
6890 }
6891 }
6892
6893 static int i865_get_display_clock_speed(struct drm_device *dev)
6894 {
6895 return 266667;
6896 }
6897
6898 static int i85x_get_display_clock_speed(struct drm_device *dev)
6899 {
6900 u16 hpllcc = 0;
6901
6902 /*
6903 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6904 * encoding is different :(
6905 * FIXME is this the right way to detect 852GM/852GMV?
6906 */
6907 if (dev->pdev->revision == 0x1)
6908 return 133333;
6909
6910 pci_bus_read_config_word(dev->pdev->bus,
6911 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6912
6913 /* Assume that the hardware is in the high speed state. This
6914 * should be the default.
6915 */
6916 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6917 case GC_CLOCK_133_200:
6918 case GC_CLOCK_133_200_2:
6919 case GC_CLOCK_100_200:
6920 return 200000;
6921 case GC_CLOCK_166_250:
6922 return 250000;
6923 case GC_CLOCK_100_133:
6924 return 133333;
6925 case GC_CLOCK_133_266:
6926 case GC_CLOCK_133_266_2:
6927 case GC_CLOCK_166_266:
6928 return 266667;
6929 }
6930
6931 /* Shouldn't happen */
6932 return 0;
6933 }
6934
6935 static int i830_get_display_clock_speed(struct drm_device *dev)
6936 {
6937 return 133333;
6938 }
6939
6940 static unsigned int intel_hpll_vco(struct drm_device *dev)
6941 {
6942 struct drm_i915_private *dev_priv = dev->dev_private;
6943 static const unsigned int blb_vco[8] = {
6944 [0] = 3200000,
6945 [1] = 4000000,
6946 [2] = 5333333,
6947 [3] = 4800000,
6948 [4] = 6400000,
6949 };
6950 static const unsigned int pnv_vco[8] = {
6951 [0] = 3200000,
6952 [1] = 4000000,
6953 [2] = 5333333,
6954 [3] = 4800000,
6955 [4] = 2666667,
6956 };
6957 static const unsigned int cl_vco[8] = {
6958 [0] = 3200000,
6959 [1] = 4000000,
6960 [2] = 5333333,
6961 [3] = 6400000,
6962 [4] = 3333333,
6963 [5] = 3566667,
6964 [6] = 4266667,
6965 };
6966 static const unsigned int elk_vco[8] = {
6967 [0] = 3200000,
6968 [1] = 4000000,
6969 [2] = 5333333,
6970 [3] = 4800000,
6971 };
6972 static const unsigned int ctg_vco[8] = {
6973 [0] = 3200000,
6974 [1] = 4000000,
6975 [2] = 5333333,
6976 [3] = 6400000,
6977 [4] = 2666667,
6978 [5] = 4266667,
6979 };
6980 const unsigned int *vco_table;
6981 unsigned int vco;
6982 uint8_t tmp = 0;
6983
6984 /* FIXME other chipsets? */
6985 if (IS_GM45(dev))
6986 vco_table = ctg_vco;
6987 else if (IS_G4X(dev))
6988 vco_table = elk_vco;
6989 else if (IS_CRESTLINE(dev))
6990 vco_table = cl_vco;
6991 else if (IS_PINEVIEW(dev))
6992 vco_table = pnv_vco;
6993 else if (IS_G33(dev))
6994 vco_table = blb_vco;
6995 else
6996 return 0;
6997
6998 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6999
7000 vco = vco_table[tmp & 0x7];
7001 if (vco == 0)
7002 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7003 else
7004 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7005
7006 return vco;
7007 }
7008
7009 static int gm45_get_display_clock_speed(struct drm_device *dev)
7010 {
7011 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7012 uint16_t tmp = 0;
7013
7014 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7015
7016 cdclk_sel = (tmp >> 12) & 0x1;
7017
7018 switch (vco) {
7019 case 2666667:
7020 case 4000000:
7021 case 5333333:
7022 return cdclk_sel ? 333333 : 222222;
7023 case 3200000:
7024 return cdclk_sel ? 320000 : 228571;
7025 default:
7026 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7027 return 222222;
7028 }
7029 }
7030
7031 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7032 {
7033 static const uint8_t div_3200[] = { 16, 10, 8 };
7034 static const uint8_t div_4000[] = { 20, 12, 10 };
7035 static const uint8_t div_5333[] = { 24, 16, 14 };
7036 const uint8_t *div_table;
7037 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7038 uint16_t tmp = 0;
7039
7040 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7041
7042 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7043
7044 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7045 goto fail;
7046
7047 switch (vco) {
7048 case 3200000:
7049 div_table = div_3200;
7050 break;
7051 case 4000000:
7052 div_table = div_4000;
7053 break;
7054 case 5333333:
7055 div_table = div_5333;
7056 break;
7057 default:
7058 goto fail;
7059 }
7060
7061 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7062
7063 fail:
7064 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7065 return 200000;
7066 }
7067
7068 static int g33_get_display_clock_speed(struct drm_device *dev)
7069 {
7070 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7071 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7072 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7073 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7074 const uint8_t *div_table;
7075 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7076 uint16_t tmp = 0;
7077
7078 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7079
7080 cdclk_sel = (tmp >> 4) & 0x7;
7081
7082 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7083 goto fail;
7084
7085 switch (vco) {
7086 case 3200000:
7087 div_table = div_3200;
7088 break;
7089 case 4000000:
7090 div_table = div_4000;
7091 break;
7092 case 4800000:
7093 div_table = div_4800;
7094 break;
7095 case 5333333:
7096 div_table = div_5333;
7097 break;
7098 default:
7099 goto fail;
7100 }
7101
7102 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7103
7104 fail:
7105 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7106 return 190476;
7107 }
7108
7109 static void
7110 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7111 {
7112 while (*num > DATA_LINK_M_N_MASK ||
7113 *den > DATA_LINK_M_N_MASK) {
7114 *num >>= 1;
7115 *den >>= 1;
7116 }
7117 }
7118
7119 static void compute_m_n(unsigned int m, unsigned int n,
7120 uint32_t *ret_m, uint32_t *ret_n)
7121 {
7122 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7123 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7124 intel_reduce_m_n_ratio(ret_m, ret_n);
7125 }
7126
7127 void
7128 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7129 int pixel_clock, int link_clock,
7130 struct intel_link_m_n *m_n)
7131 {
7132 m_n->tu = 64;
7133
7134 compute_m_n(bits_per_pixel * pixel_clock,
7135 link_clock * nlanes * 8,
7136 &m_n->gmch_m, &m_n->gmch_n);
7137
7138 compute_m_n(pixel_clock, link_clock,
7139 &m_n->link_m, &m_n->link_n);
7140 }
7141
7142 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7143 {
7144 if (i915.panel_use_ssc >= 0)
7145 return i915.panel_use_ssc != 0;
7146 return dev_priv->vbt.lvds_use_ssc
7147 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7148 }
7149
7150 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7151 int num_connectors)
7152 {
7153 struct drm_device *dev = crtc_state->base.crtc->dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 int refclk;
7156
7157 WARN_ON(!crtc_state->base.state);
7158
7159 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7160 refclk = 100000;
7161 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7162 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7163 refclk = dev_priv->vbt.lvds_ssc_freq;
7164 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7165 } else if (!IS_GEN2(dev)) {
7166 refclk = 96000;
7167 } else {
7168 refclk = 48000;
7169 }
7170
7171 return refclk;
7172 }
7173
7174 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7175 {
7176 return (1 << dpll->n) << 16 | dpll->m2;
7177 }
7178
7179 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7180 {
7181 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7182 }
7183
7184 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7185 struct intel_crtc_state *crtc_state,
7186 intel_clock_t *reduced_clock)
7187 {
7188 struct drm_device *dev = crtc->base.dev;
7189 u32 fp, fp2 = 0;
7190
7191 if (IS_PINEVIEW(dev)) {
7192 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7193 if (reduced_clock)
7194 fp2 = pnv_dpll_compute_fp(reduced_clock);
7195 } else {
7196 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7197 if (reduced_clock)
7198 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7199 }
7200
7201 crtc_state->dpll_hw_state.fp0 = fp;
7202
7203 crtc->lowfreq_avail = false;
7204 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7205 reduced_clock) {
7206 crtc_state->dpll_hw_state.fp1 = fp2;
7207 crtc->lowfreq_avail = true;
7208 } else {
7209 crtc_state->dpll_hw_state.fp1 = fp;
7210 }
7211 }
7212
7213 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7214 pipe)
7215 {
7216 u32 reg_val;
7217
7218 /*
7219 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7220 * and set it to a reasonable value instead.
7221 */
7222 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7223 reg_val &= 0xffffff00;
7224 reg_val |= 0x00000030;
7225 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7226
7227 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7228 reg_val &= 0x8cffffff;
7229 reg_val = 0x8c000000;
7230 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7231
7232 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7233 reg_val &= 0xffffff00;
7234 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7235
7236 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7237 reg_val &= 0x00ffffff;
7238 reg_val |= 0xb0000000;
7239 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7240 }
7241
7242 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7243 struct intel_link_m_n *m_n)
7244 {
7245 struct drm_device *dev = crtc->base.dev;
7246 struct drm_i915_private *dev_priv = dev->dev_private;
7247 int pipe = crtc->pipe;
7248
7249 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7250 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7251 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7252 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7253 }
7254
7255 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7256 struct intel_link_m_n *m_n,
7257 struct intel_link_m_n *m2_n2)
7258 {
7259 struct drm_device *dev = crtc->base.dev;
7260 struct drm_i915_private *dev_priv = dev->dev_private;
7261 int pipe = crtc->pipe;
7262 enum transcoder transcoder = crtc->config->cpu_transcoder;
7263
7264 if (INTEL_INFO(dev)->gen >= 5) {
7265 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7266 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7267 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7268 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7269 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7270 * for gen < 8) and if DRRS is supported (to make sure the
7271 * registers are not unnecessarily accessed).
7272 */
7273 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7274 crtc->config->has_drrs) {
7275 I915_WRITE(PIPE_DATA_M2(transcoder),
7276 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7277 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7278 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7279 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7280 }
7281 } else {
7282 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7283 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7284 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7285 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7286 }
7287 }
7288
7289 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7290 {
7291 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7292
7293 if (m_n == M1_N1) {
7294 dp_m_n = &crtc->config->dp_m_n;
7295 dp_m2_n2 = &crtc->config->dp_m2_n2;
7296 } else if (m_n == M2_N2) {
7297
7298 /*
7299 * M2_N2 registers are not supported. Hence m2_n2 divider value
7300 * needs to be programmed into M1_N1.
7301 */
7302 dp_m_n = &crtc->config->dp_m2_n2;
7303 } else {
7304 DRM_ERROR("Unsupported divider value\n");
7305 return;
7306 }
7307
7308 if (crtc->config->has_pch_encoder)
7309 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7310 else
7311 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7312 }
7313
7314 static void vlv_compute_dpll(struct intel_crtc *crtc,
7315 struct intel_crtc_state *pipe_config)
7316 {
7317 u32 dpll, dpll_md;
7318
7319 /*
7320 * Enable DPIO clock input. We should never disable the reference
7321 * clock for pipe B, since VGA hotplug / manual detection depends
7322 * on it.
7323 */
7324 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7325 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7326 /* We should never disable this, set it here for state tracking */
7327 if (crtc->pipe == PIPE_B)
7328 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7329 dpll |= DPLL_VCO_ENABLE;
7330 pipe_config->dpll_hw_state.dpll = dpll;
7331
7332 dpll_md = (pipe_config->pixel_multiplier - 1)
7333 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7334 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7335 }
7336
7337 static void vlv_prepare_pll(struct intel_crtc *crtc,
7338 const struct intel_crtc_state *pipe_config)
7339 {
7340 struct drm_device *dev = crtc->base.dev;
7341 struct drm_i915_private *dev_priv = dev->dev_private;
7342 int pipe = crtc->pipe;
7343 u32 mdiv;
7344 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7345 u32 coreclk, reg_val;
7346
7347 mutex_lock(&dev_priv->sb_lock);
7348
7349 bestn = pipe_config->dpll.n;
7350 bestm1 = pipe_config->dpll.m1;
7351 bestm2 = pipe_config->dpll.m2;
7352 bestp1 = pipe_config->dpll.p1;
7353 bestp2 = pipe_config->dpll.p2;
7354
7355 /* See eDP HDMI DPIO driver vbios notes doc */
7356
7357 /* PLL B needs special handling */
7358 if (pipe == PIPE_B)
7359 vlv_pllb_recal_opamp(dev_priv, pipe);
7360
7361 /* Set up Tx target for periodic Rcomp update */
7362 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7363
7364 /* Disable target IRef on PLL */
7365 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7366 reg_val &= 0x00ffffff;
7367 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7368
7369 /* Disable fast lock */
7370 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7371
7372 /* Set idtafcrecal before PLL is enabled */
7373 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7374 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7375 mdiv |= ((bestn << DPIO_N_SHIFT));
7376 mdiv |= (1 << DPIO_K_SHIFT);
7377
7378 /*
7379 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7380 * but we don't support that).
7381 * Note: don't use the DAC post divider as it seems unstable.
7382 */
7383 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7385
7386 mdiv |= DPIO_ENABLE_CALIBRATION;
7387 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7388
7389 /* Set HBR and RBR LPF coefficients */
7390 if (pipe_config->port_clock == 162000 ||
7391 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7392 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7393 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7394 0x009f0003);
7395 else
7396 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7397 0x00d0000f);
7398
7399 if (pipe_config->has_dp_encoder) {
7400 /* Use SSC source */
7401 if (pipe == PIPE_A)
7402 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7403 0x0df40000);
7404 else
7405 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7406 0x0df70000);
7407 } else { /* HDMI or VGA */
7408 /* Use bend source */
7409 if (pipe == PIPE_A)
7410 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7411 0x0df70000);
7412 else
7413 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7414 0x0df40000);
7415 }
7416
7417 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7418 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7420 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7421 coreclk |= 0x01000000;
7422 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7423
7424 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7425 mutex_unlock(&dev_priv->sb_lock);
7426 }
7427
7428 static void chv_compute_dpll(struct intel_crtc *crtc,
7429 struct intel_crtc_state *pipe_config)
7430 {
7431 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7432 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7433 DPLL_VCO_ENABLE;
7434 if (crtc->pipe != PIPE_A)
7435 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7436
7437 pipe_config->dpll_hw_state.dpll_md =
7438 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7439 }
7440
7441 static void chv_prepare_pll(struct intel_crtc *crtc,
7442 const struct intel_crtc_state *pipe_config)
7443 {
7444 struct drm_device *dev = crtc->base.dev;
7445 struct drm_i915_private *dev_priv = dev->dev_private;
7446 int pipe = crtc->pipe;
7447 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7448 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7449 u32 loopfilter, tribuf_calcntr;
7450 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7451 u32 dpio_val;
7452 int vco;
7453
7454 bestn = pipe_config->dpll.n;
7455 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7456 bestm1 = pipe_config->dpll.m1;
7457 bestm2 = pipe_config->dpll.m2 >> 22;
7458 bestp1 = pipe_config->dpll.p1;
7459 bestp2 = pipe_config->dpll.p2;
7460 vco = pipe_config->dpll.vco;
7461 dpio_val = 0;
7462 loopfilter = 0;
7463
7464 /*
7465 * Enable Refclk and SSC
7466 */
7467 I915_WRITE(dpll_reg,
7468 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7469
7470 mutex_lock(&dev_priv->sb_lock);
7471
7472 /* p1 and p2 divider */
7473 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7474 5 << DPIO_CHV_S1_DIV_SHIFT |
7475 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7476 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7477 1 << DPIO_CHV_K_DIV_SHIFT);
7478
7479 /* Feedback post-divider - m2 */
7480 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7481
7482 /* Feedback refclk divider - n and m1 */
7483 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7484 DPIO_CHV_M1_DIV_BY_2 |
7485 1 << DPIO_CHV_N_DIV_SHIFT);
7486
7487 /* M2 fraction division */
7488 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7489
7490 /* M2 fraction division enable */
7491 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7492 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7493 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7494 if (bestm2_frac)
7495 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7496 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7497
7498 /* Program digital lock detect threshold */
7499 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7500 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7501 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7502 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7503 if (!bestm2_frac)
7504 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7505 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7506
7507 /* Loop filter */
7508 if (vco == 5400000) {
7509 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7510 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7511 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7512 tribuf_calcntr = 0x9;
7513 } else if (vco <= 6200000) {
7514 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7515 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7516 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7517 tribuf_calcntr = 0x9;
7518 } else if (vco <= 6480000) {
7519 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7520 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7521 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7522 tribuf_calcntr = 0x8;
7523 } else {
7524 /* Not supported. Apply the same limits as in the max case */
7525 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7526 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7527 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7528 tribuf_calcntr = 0;
7529 }
7530 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7531
7532 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7533 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7534 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7535 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7536
7537 /* AFC Recal */
7538 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7539 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7540 DPIO_AFC_RECAL);
7541
7542 mutex_unlock(&dev_priv->sb_lock);
7543 }
7544
7545 /**
7546 * vlv_force_pll_on - forcibly enable just the PLL
7547 * @dev_priv: i915 private structure
7548 * @pipe: pipe PLL to enable
7549 * @dpll: PLL configuration
7550 *
7551 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7552 * in cases where we need the PLL enabled even when @pipe is not going to
7553 * be enabled.
7554 */
7555 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7556 const struct dpll *dpll)
7557 {
7558 struct intel_crtc *crtc =
7559 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7560 struct intel_crtc_state pipe_config = {
7561 .base.crtc = &crtc->base,
7562 .pixel_multiplier = 1,
7563 .dpll = *dpll,
7564 };
7565
7566 if (IS_CHERRYVIEW(dev)) {
7567 chv_compute_dpll(crtc, &pipe_config);
7568 chv_prepare_pll(crtc, &pipe_config);
7569 chv_enable_pll(crtc, &pipe_config);
7570 } else {
7571 vlv_compute_dpll(crtc, &pipe_config);
7572 vlv_prepare_pll(crtc, &pipe_config);
7573 vlv_enable_pll(crtc, &pipe_config);
7574 }
7575 }
7576
7577 /**
7578 * vlv_force_pll_off - forcibly disable just the PLL
7579 * @dev_priv: i915 private structure
7580 * @pipe: pipe PLL to disable
7581 *
7582 * Disable the PLL for @pipe. To be used in cases where we need
7583 * the PLL enabled even when @pipe is not going to be enabled.
7584 */
7585 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7586 {
7587 if (IS_CHERRYVIEW(dev))
7588 chv_disable_pll(to_i915(dev), pipe);
7589 else
7590 vlv_disable_pll(to_i915(dev), pipe);
7591 }
7592
7593 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7594 struct intel_crtc_state *crtc_state,
7595 intel_clock_t *reduced_clock,
7596 int num_connectors)
7597 {
7598 struct drm_device *dev = crtc->base.dev;
7599 struct drm_i915_private *dev_priv = dev->dev_private;
7600 u32 dpll;
7601 bool is_sdvo;
7602 struct dpll *clock = &crtc_state->dpll;
7603
7604 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7605
7606 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7607 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7608
7609 dpll = DPLL_VGA_MODE_DIS;
7610
7611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7612 dpll |= DPLLB_MODE_LVDS;
7613 else
7614 dpll |= DPLLB_MODE_DAC_SERIAL;
7615
7616 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7617 dpll |= (crtc_state->pixel_multiplier - 1)
7618 << SDVO_MULTIPLIER_SHIFT_HIRES;
7619 }
7620
7621 if (is_sdvo)
7622 dpll |= DPLL_SDVO_HIGH_SPEED;
7623
7624 if (crtc_state->has_dp_encoder)
7625 dpll |= DPLL_SDVO_HIGH_SPEED;
7626
7627 /* compute bitmask from p1 value */
7628 if (IS_PINEVIEW(dev))
7629 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7630 else {
7631 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7632 if (IS_G4X(dev) && reduced_clock)
7633 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7634 }
7635 switch (clock->p2) {
7636 case 5:
7637 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7638 break;
7639 case 7:
7640 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7641 break;
7642 case 10:
7643 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7644 break;
7645 case 14:
7646 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7647 break;
7648 }
7649 if (INTEL_INFO(dev)->gen >= 4)
7650 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7651
7652 if (crtc_state->sdvo_tv_clock)
7653 dpll |= PLL_REF_INPUT_TVCLKINBC;
7654 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7655 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7656 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7657 else
7658 dpll |= PLL_REF_INPUT_DREFCLK;
7659
7660 dpll |= DPLL_VCO_ENABLE;
7661 crtc_state->dpll_hw_state.dpll = dpll;
7662
7663 if (INTEL_INFO(dev)->gen >= 4) {
7664 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7665 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7666 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7667 }
7668 }
7669
7670 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7671 struct intel_crtc_state *crtc_state,
7672 intel_clock_t *reduced_clock,
7673 int num_connectors)
7674 {
7675 struct drm_device *dev = crtc->base.dev;
7676 struct drm_i915_private *dev_priv = dev->dev_private;
7677 u32 dpll;
7678 struct dpll *clock = &crtc_state->dpll;
7679
7680 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7681
7682 dpll = DPLL_VGA_MODE_DIS;
7683
7684 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7685 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7686 } else {
7687 if (clock->p1 == 2)
7688 dpll |= PLL_P1_DIVIDE_BY_TWO;
7689 else
7690 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7691 if (clock->p2 == 4)
7692 dpll |= PLL_P2_DIVIDE_BY_4;
7693 }
7694
7695 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7696 dpll |= DPLL_DVO_2X_MODE;
7697
7698 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7699 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7700 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7701 else
7702 dpll |= PLL_REF_INPUT_DREFCLK;
7703
7704 dpll |= DPLL_VCO_ENABLE;
7705 crtc_state->dpll_hw_state.dpll = dpll;
7706 }
7707
7708 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7709 {
7710 struct drm_device *dev = intel_crtc->base.dev;
7711 struct drm_i915_private *dev_priv = dev->dev_private;
7712 enum pipe pipe = intel_crtc->pipe;
7713 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7714 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7715 uint32_t crtc_vtotal, crtc_vblank_end;
7716 int vsyncshift = 0;
7717
7718 /* We need to be careful not to changed the adjusted mode, for otherwise
7719 * the hw state checker will get angry at the mismatch. */
7720 crtc_vtotal = adjusted_mode->crtc_vtotal;
7721 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7722
7723 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7724 /* the chip adds 2 halflines automatically */
7725 crtc_vtotal -= 1;
7726 crtc_vblank_end -= 1;
7727
7728 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7729 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7730 else
7731 vsyncshift = adjusted_mode->crtc_hsync_start -
7732 adjusted_mode->crtc_htotal / 2;
7733 if (vsyncshift < 0)
7734 vsyncshift += adjusted_mode->crtc_htotal;
7735 }
7736
7737 if (INTEL_INFO(dev)->gen > 3)
7738 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7739
7740 I915_WRITE(HTOTAL(cpu_transcoder),
7741 (adjusted_mode->crtc_hdisplay - 1) |
7742 ((adjusted_mode->crtc_htotal - 1) << 16));
7743 I915_WRITE(HBLANK(cpu_transcoder),
7744 (adjusted_mode->crtc_hblank_start - 1) |
7745 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7746 I915_WRITE(HSYNC(cpu_transcoder),
7747 (adjusted_mode->crtc_hsync_start - 1) |
7748 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7749
7750 I915_WRITE(VTOTAL(cpu_transcoder),
7751 (adjusted_mode->crtc_vdisplay - 1) |
7752 ((crtc_vtotal - 1) << 16));
7753 I915_WRITE(VBLANK(cpu_transcoder),
7754 (adjusted_mode->crtc_vblank_start - 1) |
7755 ((crtc_vblank_end - 1) << 16));
7756 I915_WRITE(VSYNC(cpu_transcoder),
7757 (adjusted_mode->crtc_vsync_start - 1) |
7758 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7759
7760 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7761 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7762 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7763 * bits. */
7764 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7765 (pipe == PIPE_B || pipe == PIPE_C))
7766 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7767
7768 /* pipesrc controls the size that is scaled from, which should
7769 * always be the user's requested size.
7770 */
7771 I915_WRITE(PIPESRC(pipe),
7772 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7773 (intel_crtc->config->pipe_src_h - 1));
7774 }
7775
7776 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7777 struct intel_crtc_state *pipe_config)
7778 {
7779 struct drm_device *dev = crtc->base.dev;
7780 struct drm_i915_private *dev_priv = dev->dev_private;
7781 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7782 uint32_t tmp;
7783
7784 tmp = I915_READ(HTOTAL(cpu_transcoder));
7785 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7786 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7787 tmp = I915_READ(HBLANK(cpu_transcoder));
7788 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7789 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7790 tmp = I915_READ(HSYNC(cpu_transcoder));
7791 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7792 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7793
7794 tmp = I915_READ(VTOTAL(cpu_transcoder));
7795 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7796 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7797 tmp = I915_READ(VBLANK(cpu_transcoder));
7798 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7799 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7800 tmp = I915_READ(VSYNC(cpu_transcoder));
7801 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7802 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7803
7804 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7805 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7806 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7807 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7808 }
7809
7810 tmp = I915_READ(PIPESRC(crtc->pipe));
7811 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7812 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7813
7814 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7815 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7816 }
7817
7818 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7819 struct intel_crtc_state *pipe_config)
7820 {
7821 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7822 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7823 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7824 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7825
7826 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7827 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7828 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7829 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7830
7831 mode->flags = pipe_config->base.adjusted_mode.flags;
7832 mode->type = DRM_MODE_TYPE_DRIVER;
7833
7834 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7835 mode->flags |= pipe_config->base.adjusted_mode.flags;
7836
7837 mode->hsync = drm_mode_hsync(mode);
7838 mode->vrefresh = drm_mode_vrefresh(mode);
7839 drm_mode_set_name(mode);
7840 }
7841
7842 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7843 {
7844 struct drm_device *dev = intel_crtc->base.dev;
7845 struct drm_i915_private *dev_priv = dev->dev_private;
7846 uint32_t pipeconf;
7847
7848 pipeconf = 0;
7849
7850 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7851 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7852 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7853
7854 if (intel_crtc->config->double_wide)
7855 pipeconf |= PIPECONF_DOUBLE_WIDE;
7856
7857 /* only g4x and later have fancy bpc/dither controls */
7858 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7859 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7860 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7861 pipeconf |= PIPECONF_DITHER_EN |
7862 PIPECONF_DITHER_TYPE_SP;
7863
7864 switch (intel_crtc->config->pipe_bpp) {
7865 case 18:
7866 pipeconf |= PIPECONF_6BPC;
7867 break;
7868 case 24:
7869 pipeconf |= PIPECONF_8BPC;
7870 break;
7871 case 30:
7872 pipeconf |= PIPECONF_10BPC;
7873 break;
7874 default:
7875 /* Case prevented by intel_choose_pipe_bpp_dither. */
7876 BUG();
7877 }
7878 }
7879
7880 if (HAS_PIPE_CXSR(dev)) {
7881 if (intel_crtc->lowfreq_avail) {
7882 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7883 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7884 } else {
7885 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7886 }
7887 }
7888
7889 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7890 if (INTEL_INFO(dev)->gen < 4 ||
7891 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7892 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7893 else
7894 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7895 } else
7896 pipeconf |= PIPECONF_PROGRESSIVE;
7897
7898 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7899 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7900
7901 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7902 POSTING_READ(PIPECONF(intel_crtc->pipe));
7903 }
7904
7905 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7906 struct intel_crtc_state *crtc_state)
7907 {
7908 struct drm_device *dev = crtc->base.dev;
7909 struct drm_i915_private *dev_priv = dev->dev_private;
7910 int refclk, num_connectors = 0;
7911 intel_clock_t clock;
7912 bool ok;
7913 bool is_dsi = false;
7914 struct intel_encoder *encoder;
7915 const intel_limit_t *limit;
7916 struct drm_atomic_state *state = crtc_state->base.state;
7917 struct drm_connector *connector;
7918 struct drm_connector_state *connector_state;
7919 int i;
7920
7921 memset(&crtc_state->dpll_hw_state, 0,
7922 sizeof(crtc_state->dpll_hw_state));
7923
7924 for_each_connector_in_state(state, connector, connector_state, i) {
7925 if (connector_state->crtc != &crtc->base)
7926 continue;
7927
7928 encoder = to_intel_encoder(connector_state->best_encoder);
7929
7930 switch (encoder->type) {
7931 case INTEL_OUTPUT_DSI:
7932 is_dsi = true;
7933 break;
7934 default:
7935 break;
7936 }
7937
7938 num_connectors++;
7939 }
7940
7941 if (is_dsi)
7942 return 0;
7943
7944 if (!crtc_state->clock_set) {
7945 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7946
7947 /*
7948 * Returns a set of divisors for the desired target clock with
7949 * the given refclk, or FALSE. The returned values represent
7950 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7951 * 2) / p1 / p2.
7952 */
7953 limit = intel_limit(crtc_state, refclk);
7954 ok = dev_priv->display.find_dpll(limit, crtc_state,
7955 crtc_state->port_clock,
7956 refclk, NULL, &clock);
7957 if (!ok) {
7958 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7959 return -EINVAL;
7960 }
7961
7962 /* Compat-code for transition, will disappear. */
7963 crtc_state->dpll.n = clock.n;
7964 crtc_state->dpll.m1 = clock.m1;
7965 crtc_state->dpll.m2 = clock.m2;
7966 crtc_state->dpll.p1 = clock.p1;
7967 crtc_state->dpll.p2 = clock.p2;
7968 }
7969
7970 if (IS_GEN2(dev)) {
7971 i8xx_compute_dpll(crtc, crtc_state, NULL,
7972 num_connectors);
7973 } else if (IS_CHERRYVIEW(dev)) {
7974 chv_compute_dpll(crtc, crtc_state);
7975 } else if (IS_VALLEYVIEW(dev)) {
7976 vlv_compute_dpll(crtc, crtc_state);
7977 } else {
7978 i9xx_compute_dpll(crtc, crtc_state, NULL,
7979 num_connectors);
7980 }
7981
7982 return 0;
7983 }
7984
7985 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7986 struct intel_crtc_state *pipe_config)
7987 {
7988 struct drm_device *dev = crtc->base.dev;
7989 struct drm_i915_private *dev_priv = dev->dev_private;
7990 uint32_t tmp;
7991
7992 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7993 return;
7994
7995 tmp = I915_READ(PFIT_CONTROL);
7996 if (!(tmp & PFIT_ENABLE))
7997 return;
7998
7999 /* Check whether the pfit is attached to our pipe. */
8000 if (INTEL_INFO(dev)->gen < 4) {
8001 if (crtc->pipe != PIPE_B)
8002 return;
8003 } else {
8004 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8005 return;
8006 }
8007
8008 pipe_config->gmch_pfit.control = tmp;
8009 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8010 if (INTEL_INFO(dev)->gen < 5)
8011 pipe_config->gmch_pfit.lvds_border_bits =
8012 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8013 }
8014
8015 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8016 struct intel_crtc_state *pipe_config)
8017 {
8018 struct drm_device *dev = crtc->base.dev;
8019 struct drm_i915_private *dev_priv = dev->dev_private;
8020 int pipe = pipe_config->cpu_transcoder;
8021 intel_clock_t clock;
8022 u32 mdiv;
8023 int refclk = 100000;
8024
8025 /* In case of MIPI DPLL will not even be used */
8026 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8027 return;
8028
8029 mutex_lock(&dev_priv->sb_lock);
8030 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8031 mutex_unlock(&dev_priv->sb_lock);
8032
8033 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8034 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8035 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8036 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8037 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8038
8039 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8040 }
8041
8042 static void
8043 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8044 struct intel_initial_plane_config *plane_config)
8045 {
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 u32 val, base, offset;
8049 int pipe = crtc->pipe, plane = crtc->plane;
8050 int fourcc, pixel_format;
8051 unsigned int aligned_height;
8052 struct drm_framebuffer *fb;
8053 struct intel_framebuffer *intel_fb;
8054
8055 val = I915_READ(DSPCNTR(plane));
8056 if (!(val & DISPLAY_PLANE_ENABLE))
8057 return;
8058
8059 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8060 if (!intel_fb) {
8061 DRM_DEBUG_KMS("failed to alloc fb\n");
8062 return;
8063 }
8064
8065 fb = &intel_fb->base;
8066
8067 if (INTEL_INFO(dev)->gen >= 4) {
8068 if (val & DISPPLANE_TILED) {
8069 plane_config->tiling = I915_TILING_X;
8070 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8071 }
8072 }
8073
8074 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8075 fourcc = i9xx_format_to_fourcc(pixel_format);
8076 fb->pixel_format = fourcc;
8077 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8078
8079 if (INTEL_INFO(dev)->gen >= 4) {
8080 if (plane_config->tiling)
8081 offset = I915_READ(DSPTILEOFF(plane));
8082 else
8083 offset = I915_READ(DSPLINOFF(plane));
8084 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8085 } else {
8086 base = I915_READ(DSPADDR(plane));
8087 }
8088 plane_config->base = base;
8089
8090 val = I915_READ(PIPESRC(pipe));
8091 fb->width = ((val >> 16) & 0xfff) + 1;
8092 fb->height = ((val >> 0) & 0xfff) + 1;
8093
8094 val = I915_READ(DSPSTRIDE(pipe));
8095 fb->pitches[0] = val & 0xffffffc0;
8096
8097 aligned_height = intel_fb_align_height(dev, fb->height,
8098 fb->pixel_format,
8099 fb->modifier[0]);
8100
8101 plane_config->size = fb->pitches[0] * aligned_height;
8102
8103 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8104 pipe_name(pipe), plane, fb->width, fb->height,
8105 fb->bits_per_pixel, base, fb->pitches[0],
8106 plane_config->size);
8107
8108 plane_config->fb = intel_fb;
8109 }
8110
8111 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8112 struct intel_crtc_state *pipe_config)
8113 {
8114 struct drm_device *dev = crtc->base.dev;
8115 struct drm_i915_private *dev_priv = dev->dev_private;
8116 int pipe = pipe_config->cpu_transcoder;
8117 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8118 intel_clock_t clock;
8119 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8120 int refclk = 100000;
8121
8122 mutex_lock(&dev_priv->sb_lock);
8123 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8124 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8125 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8126 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8127 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8128 mutex_unlock(&dev_priv->sb_lock);
8129
8130 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8131 clock.m2 = (pll_dw0 & 0xff) << 22;
8132 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8133 clock.m2 |= pll_dw2 & 0x3fffff;
8134 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8135 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8136 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8137
8138 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8139 }
8140
8141 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8142 struct intel_crtc_state *pipe_config)
8143 {
8144 struct drm_device *dev = crtc->base.dev;
8145 struct drm_i915_private *dev_priv = dev->dev_private;
8146 uint32_t tmp;
8147
8148 if (!intel_display_power_is_enabled(dev_priv,
8149 POWER_DOMAIN_PIPE(crtc->pipe)))
8150 return false;
8151
8152 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8153 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8154
8155 tmp = I915_READ(PIPECONF(crtc->pipe));
8156 if (!(tmp & PIPECONF_ENABLE))
8157 return false;
8158
8159 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8160 switch (tmp & PIPECONF_BPC_MASK) {
8161 case PIPECONF_6BPC:
8162 pipe_config->pipe_bpp = 18;
8163 break;
8164 case PIPECONF_8BPC:
8165 pipe_config->pipe_bpp = 24;
8166 break;
8167 case PIPECONF_10BPC:
8168 pipe_config->pipe_bpp = 30;
8169 break;
8170 default:
8171 break;
8172 }
8173 }
8174
8175 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8176 pipe_config->limited_color_range = true;
8177
8178 if (INTEL_INFO(dev)->gen < 4)
8179 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8180
8181 intel_get_pipe_timings(crtc, pipe_config);
8182
8183 i9xx_get_pfit_config(crtc, pipe_config);
8184
8185 if (INTEL_INFO(dev)->gen >= 4) {
8186 tmp = I915_READ(DPLL_MD(crtc->pipe));
8187 pipe_config->pixel_multiplier =
8188 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8189 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8190 pipe_config->dpll_hw_state.dpll_md = tmp;
8191 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8192 tmp = I915_READ(DPLL(crtc->pipe));
8193 pipe_config->pixel_multiplier =
8194 ((tmp & SDVO_MULTIPLIER_MASK)
8195 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8196 } else {
8197 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8198 * port and will be fixed up in the encoder->get_config
8199 * function. */
8200 pipe_config->pixel_multiplier = 1;
8201 }
8202 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8203 if (!IS_VALLEYVIEW(dev)) {
8204 /*
8205 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8206 * on 830. Filter it out here so that we don't
8207 * report errors due to that.
8208 */
8209 if (IS_I830(dev))
8210 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8211
8212 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8213 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8214 } else {
8215 /* Mask out read-only status bits. */
8216 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8217 DPLL_PORTC_READY_MASK |
8218 DPLL_PORTB_READY_MASK);
8219 }
8220
8221 if (IS_CHERRYVIEW(dev))
8222 chv_crtc_clock_get(crtc, pipe_config);
8223 else if (IS_VALLEYVIEW(dev))
8224 vlv_crtc_clock_get(crtc, pipe_config);
8225 else
8226 i9xx_crtc_clock_get(crtc, pipe_config);
8227
8228 /*
8229 * Normally the dotclock is filled in by the encoder .get_config()
8230 * but in case the pipe is enabled w/o any ports we need a sane
8231 * default.
8232 */
8233 pipe_config->base.adjusted_mode.crtc_clock =
8234 pipe_config->port_clock / pipe_config->pixel_multiplier;
8235
8236 return true;
8237 }
8238
8239 static void ironlake_init_pch_refclk(struct drm_device *dev)
8240 {
8241 struct drm_i915_private *dev_priv = dev->dev_private;
8242 struct intel_encoder *encoder;
8243 u32 val, final;
8244 bool has_lvds = false;
8245 bool has_cpu_edp = false;
8246 bool has_panel = false;
8247 bool has_ck505 = false;
8248 bool can_ssc = false;
8249
8250 /* We need to take the global config into account */
8251 for_each_intel_encoder(dev, encoder) {
8252 switch (encoder->type) {
8253 case INTEL_OUTPUT_LVDS:
8254 has_panel = true;
8255 has_lvds = true;
8256 break;
8257 case INTEL_OUTPUT_EDP:
8258 has_panel = true;
8259 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8260 has_cpu_edp = true;
8261 break;
8262 default:
8263 break;
8264 }
8265 }
8266
8267 if (HAS_PCH_IBX(dev)) {
8268 has_ck505 = dev_priv->vbt.display_clock_mode;
8269 can_ssc = has_ck505;
8270 } else {
8271 has_ck505 = false;
8272 can_ssc = true;
8273 }
8274
8275 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8276 has_panel, has_lvds, has_ck505);
8277
8278 /* Ironlake: try to setup display ref clock before DPLL
8279 * enabling. This is only under driver's control after
8280 * PCH B stepping, previous chipset stepping should be
8281 * ignoring this setting.
8282 */
8283 val = I915_READ(PCH_DREF_CONTROL);
8284
8285 /* As we must carefully and slowly disable/enable each source in turn,
8286 * compute the final state we want first and check if we need to
8287 * make any changes at all.
8288 */
8289 final = val;
8290 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8291 if (has_ck505)
8292 final |= DREF_NONSPREAD_CK505_ENABLE;
8293 else
8294 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8295
8296 final &= ~DREF_SSC_SOURCE_MASK;
8297 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8298 final &= ~DREF_SSC1_ENABLE;
8299
8300 if (has_panel) {
8301 final |= DREF_SSC_SOURCE_ENABLE;
8302
8303 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8304 final |= DREF_SSC1_ENABLE;
8305
8306 if (has_cpu_edp) {
8307 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8308 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8309 else
8310 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8311 } else
8312 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8313 } else {
8314 final |= DREF_SSC_SOURCE_DISABLE;
8315 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8316 }
8317
8318 if (final == val)
8319 return;
8320
8321 /* Always enable nonspread source */
8322 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8323
8324 if (has_ck505)
8325 val |= DREF_NONSPREAD_CK505_ENABLE;
8326 else
8327 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8328
8329 if (has_panel) {
8330 val &= ~DREF_SSC_SOURCE_MASK;
8331 val |= DREF_SSC_SOURCE_ENABLE;
8332
8333 /* SSC must be turned on before enabling the CPU output */
8334 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8335 DRM_DEBUG_KMS("Using SSC on panel\n");
8336 val |= DREF_SSC1_ENABLE;
8337 } else
8338 val &= ~DREF_SSC1_ENABLE;
8339
8340 /* Get SSC going before enabling the outputs */
8341 I915_WRITE(PCH_DREF_CONTROL, val);
8342 POSTING_READ(PCH_DREF_CONTROL);
8343 udelay(200);
8344
8345 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8346
8347 /* Enable CPU source on CPU attached eDP */
8348 if (has_cpu_edp) {
8349 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8350 DRM_DEBUG_KMS("Using SSC on eDP\n");
8351 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8352 } else
8353 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8354 } else
8355 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8356
8357 I915_WRITE(PCH_DREF_CONTROL, val);
8358 POSTING_READ(PCH_DREF_CONTROL);
8359 udelay(200);
8360 } else {
8361 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8362
8363 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8364
8365 /* Turn off CPU output */
8366 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8367
8368 I915_WRITE(PCH_DREF_CONTROL, val);
8369 POSTING_READ(PCH_DREF_CONTROL);
8370 udelay(200);
8371
8372 /* Turn off the SSC source */
8373 val &= ~DREF_SSC_SOURCE_MASK;
8374 val |= DREF_SSC_SOURCE_DISABLE;
8375
8376 /* Turn off SSC1 */
8377 val &= ~DREF_SSC1_ENABLE;
8378
8379 I915_WRITE(PCH_DREF_CONTROL, val);
8380 POSTING_READ(PCH_DREF_CONTROL);
8381 udelay(200);
8382 }
8383
8384 BUG_ON(val != final);
8385 }
8386
8387 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8388 {
8389 uint32_t tmp;
8390
8391 tmp = I915_READ(SOUTH_CHICKEN2);
8392 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8393 I915_WRITE(SOUTH_CHICKEN2, tmp);
8394
8395 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8396 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8397 DRM_ERROR("FDI mPHY reset assert timeout\n");
8398
8399 tmp = I915_READ(SOUTH_CHICKEN2);
8400 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8401 I915_WRITE(SOUTH_CHICKEN2, tmp);
8402
8403 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8404 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8405 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8406 }
8407
8408 /* WaMPhyProgramming:hsw */
8409 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8410 {
8411 uint32_t tmp;
8412
8413 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8414 tmp &= ~(0xFF << 24);
8415 tmp |= (0x12 << 24);
8416 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8417
8418 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8419 tmp |= (1 << 11);
8420 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8421
8422 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8423 tmp |= (1 << 11);
8424 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8425
8426 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8427 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8428 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8429
8430 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8431 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8432 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8433
8434 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8435 tmp &= ~(7 << 13);
8436 tmp |= (5 << 13);
8437 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8438
8439 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8440 tmp &= ~(7 << 13);
8441 tmp |= (5 << 13);
8442 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8443
8444 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8445 tmp &= ~0xFF;
8446 tmp |= 0x1C;
8447 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8448
8449 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8450 tmp &= ~0xFF;
8451 tmp |= 0x1C;
8452 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8453
8454 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8455 tmp &= ~(0xFF << 16);
8456 tmp |= (0x1C << 16);
8457 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8458
8459 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8460 tmp &= ~(0xFF << 16);
8461 tmp |= (0x1C << 16);
8462 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8463
8464 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8465 tmp |= (1 << 27);
8466 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8467
8468 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8469 tmp |= (1 << 27);
8470 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8471
8472 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8473 tmp &= ~(0xF << 28);
8474 tmp |= (4 << 28);
8475 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8476
8477 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8478 tmp &= ~(0xF << 28);
8479 tmp |= (4 << 28);
8480 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8481 }
8482
8483 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8484 * Programming" based on the parameters passed:
8485 * - Sequence to enable CLKOUT_DP
8486 * - Sequence to enable CLKOUT_DP without spread
8487 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8488 */
8489 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8490 bool with_fdi)
8491 {
8492 struct drm_i915_private *dev_priv = dev->dev_private;
8493 uint32_t reg, tmp;
8494
8495 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8496 with_spread = true;
8497 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8498 with_fdi = false;
8499
8500 mutex_lock(&dev_priv->sb_lock);
8501
8502 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8503 tmp &= ~SBI_SSCCTL_DISABLE;
8504 tmp |= SBI_SSCCTL_PATHALT;
8505 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8506
8507 udelay(24);
8508
8509 if (with_spread) {
8510 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8511 tmp &= ~SBI_SSCCTL_PATHALT;
8512 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8513
8514 if (with_fdi) {
8515 lpt_reset_fdi_mphy(dev_priv);
8516 lpt_program_fdi_mphy(dev_priv);
8517 }
8518 }
8519
8520 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8521 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8522 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8523 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8524
8525 mutex_unlock(&dev_priv->sb_lock);
8526 }
8527
8528 /* Sequence to disable CLKOUT_DP */
8529 static void lpt_disable_clkout_dp(struct drm_device *dev)
8530 {
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532 uint32_t reg, tmp;
8533
8534 mutex_lock(&dev_priv->sb_lock);
8535
8536 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8537 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8538 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8539 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8540
8541 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8542 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8543 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8544 tmp |= SBI_SSCCTL_PATHALT;
8545 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8546 udelay(32);
8547 }
8548 tmp |= SBI_SSCCTL_DISABLE;
8549 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8550 }
8551
8552 mutex_unlock(&dev_priv->sb_lock);
8553 }
8554
8555 static void lpt_init_pch_refclk(struct drm_device *dev)
8556 {
8557 struct intel_encoder *encoder;
8558 bool has_vga = false;
8559
8560 for_each_intel_encoder(dev, encoder) {
8561 switch (encoder->type) {
8562 case INTEL_OUTPUT_ANALOG:
8563 has_vga = true;
8564 break;
8565 default:
8566 break;
8567 }
8568 }
8569
8570 if (has_vga)
8571 lpt_enable_clkout_dp(dev, true, true);
8572 else
8573 lpt_disable_clkout_dp(dev);
8574 }
8575
8576 /*
8577 * Initialize reference clocks when the driver loads
8578 */
8579 void intel_init_pch_refclk(struct drm_device *dev)
8580 {
8581 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8582 ironlake_init_pch_refclk(dev);
8583 else if (HAS_PCH_LPT(dev))
8584 lpt_init_pch_refclk(dev);
8585 }
8586
8587 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8588 {
8589 struct drm_device *dev = crtc_state->base.crtc->dev;
8590 struct drm_i915_private *dev_priv = dev->dev_private;
8591 struct drm_atomic_state *state = crtc_state->base.state;
8592 struct drm_connector *connector;
8593 struct drm_connector_state *connector_state;
8594 struct intel_encoder *encoder;
8595 int num_connectors = 0, i;
8596 bool is_lvds = false;
8597
8598 for_each_connector_in_state(state, connector, connector_state, i) {
8599 if (connector_state->crtc != crtc_state->base.crtc)
8600 continue;
8601
8602 encoder = to_intel_encoder(connector_state->best_encoder);
8603
8604 switch (encoder->type) {
8605 case INTEL_OUTPUT_LVDS:
8606 is_lvds = true;
8607 break;
8608 default:
8609 break;
8610 }
8611 num_connectors++;
8612 }
8613
8614 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8615 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8616 dev_priv->vbt.lvds_ssc_freq);
8617 return dev_priv->vbt.lvds_ssc_freq;
8618 }
8619
8620 return 120000;
8621 }
8622
8623 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8624 {
8625 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8627 int pipe = intel_crtc->pipe;
8628 uint32_t val;
8629
8630 val = 0;
8631
8632 switch (intel_crtc->config->pipe_bpp) {
8633 case 18:
8634 val |= PIPECONF_6BPC;
8635 break;
8636 case 24:
8637 val |= PIPECONF_8BPC;
8638 break;
8639 case 30:
8640 val |= PIPECONF_10BPC;
8641 break;
8642 case 36:
8643 val |= PIPECONF_12BPC;
8644 break;
8645 default:
8646 /* Case prevented by intel_choose_pipe_bpp_dither. */
8647 BUG();
8648 }
8649
8650 if (intel_crtc->config->dither)
8651 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8652
8653 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8654 val |= PIPECONF_INTERLACED_ILK;
8655 else
8656 val |= PIPECONF_PROGRESSIVE;
8657
8658 if (intel_crtc->config->limited_color_range)
8659 val |= PIPECONF_COLOR_RANGE_SELECT;
8660
8661 I915_WRITE(PIPECONF(pipe), val);
8662 POSTING_READ(PIPECONF(pipe));
8663 }
8664
8665 /*
8666 * Set up the pipe CSC unit.
8667 *
8668 * Currently only full range RGB to limited range RGB conversion
8669 * is supported, but eventually this should handle various
8670 * RGB<->YCbCr scenarios as well.
8671 */
8672 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8673 {
8674 struct drm_device *dev = crtc->dev;
8675 struct drm_i915_private *dev_priv = dev->dev_private;
8676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8677 int pipe = intel_crtc->pipe;
8678 uint16_t coeff = 0x7800; /* 1.0 */
8679
8680 /*
8681 * TODO: Check what kind of values actually come out of the pipe
8682 * with these coeff/postoff values and adjust to get the best
8683 * accuracy. Perhaps we even need to take the bpc value into
8684 * consideration.
8685 */
8686
8687 if (intel_crtc->config->limited_color_range)
8688 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8689
8690 /*
8691 * GY/GU and RY/RU should be the other way around according
8692 * to BSpec, but reality doesn't agree. Just set them up in
8693 * a way that results in the correct picture.
8694 */
8695 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8696 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8697
8698 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8699 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8700
8701 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8702 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8703
8704 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8705 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8706 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8707
8708 if (INTEL_INFO(dev)->gen > 6) {
8709 uint16_t postoff = 0;
8710
8711 if (intel_crtc->config->limited_color_range)
8712 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8713
8714 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8715 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8716 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8717
8718 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8719 } else {
8720 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8721
8722 if (intel_crtc->config->limited_color_range)
8723 mode |= CSC_BLACK_SCREEN_OFFSET;
8724
8725 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8726 }
8727 }
8728
8729 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8730 {
8731 struct drm_device *dev = crtc->dev;
8732 struct drm_i915_private *dev_priv = dev->dev_private;
8733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8734 enum pipe pipe = intel_crtc->pipe;
8735 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8736 uint32_t val;
8737
8738 val = 0;
8739
8740 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8741 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8742
8743 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8744 val |= PIPECONF_INTERLACED_ILK;
8745 else
8746 val |= PIPECONF_PROGRESSIVE;
8747
8748 I915_WRITE(PIPECONF(cpu_transcoder), val);
8749 POSTING_READ(PIPECONF(cpu_transcoder));
8750
8751 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8752 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8753
8754 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8755 val = 0;
8756
8757 switch (intel_crtc->config->pipe_bpp) {
8758 case 18:
8759 val |= PIPEMISC_DITHER_6_BPC;
8760 break;
8761 case 24:
8762 val |= PIPEMISC_DITHER_8_BPC;
8763 break;
8764 case 30:
8765 val |= PIPEMISC_DITHER_10_BPC;
8766 break;
8767 case 36:
8768 val |= PIPEMISC_DITHER_12_BPC;
8769 break;
8770 default:
8771 /* Case prevented by pipe_config_set_bpp. */
8772 BUG();
8773 }
8774
8775 if (intel_crtc->config->dither)
8776 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8777
8778 I915_WRITE(PIPEMISC(pipe), val);
8779 }
8780 }
8781
8782 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8783 struct intel_crtc_state *crtc_state,
8784 intel_clock_t *clock,
8785 bool *has_reduced_clock,
8786 intel_clock_t *reduced_clock)
8787 {
8788 struct drm_device *dev = crtc->dev;
8789 struct drm_i915_private *dev_priv = dev->dev_private;
8790 int refclk;
8791 const intel_limit_t *limit;
8792 bool ret;
8793
8794 refclk = ironlake_get_refclk(crtc_state);
8795
8796 /*
8797 * Returns a set of divisors for the desired target clock with the given
8798 * refclk, or FALSE. The returned values represent the clock equation:
8799 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8800 */
8801 limit = intel_limit(crtc_state, refclk);
8802 ret = dev_priv->display.find_dpll(limit, crtc_state,
8803 crtc_state->port_clock,
8804 refclk, NULL, clock);
8805 if (!ret)
8806 return false;
8807
8808 return true;
8809 }
8810
8811 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8812 {
8813 /*
8814 * Account for spread spectrum to avoid
8815 * oversubscribing the link. Max center spread
8816 * is 2.5%; use 5% for safety's sake.
8817 */
8818 u32 bps = target_clock * bpp * 21 / 20;
8819 return DIV_ROUND_UP(bps, link_bw * 8);
8820 }
8821
8822 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8823 {
8824 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8825 }
8826
8827 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8828 struct intel_crtc_state *crtc_state,
8829 u32 *fp,
8830 intel_clock_t *reduced_clock, u32 *fp2)
8831 {
8832 struct drm_crtc *crtc = &intel_crtc->base;
8833 struct drm_device *dev = crtc->dev;
8834 struct drm_i915_private *dev_priv = dev->dev_private;
8835 struct drm_atomic_state *state = crtc_state->base.state;
8836 struct drm_connector *connector;
8837 struct drm_connector_state *connector_state;
8838 struct intel_encoder *encoder;
8839 uint32_t dpll;
8840 int factor, num_connectors = 0, i;
8841 bool is_lvds = false, is_sdvo = false;
8842
8843 for_each_connector_in_state(state, connector, connector_state, i) {
8844 if (connector_state->crtc != crtc_state->base.crtc)
8845 continue;
8846
8847 encoder = to_intel_encoder(connector_state->best_encoder);
8848
8849 switch (encoder->type) {
8850 case INTEL_OUTPUT_LVDS:
8851 is_lvds = true;
8852 break;
8853 case INTEL_OUTPUT_SDVO:
8854 case INTEL_OUTPUT_HDMI:
8855 is_sdvo = true;
8856 break;
8857 default:
8858 break;
8859 }
8860
8861 num_connectors++;
8862 }
8863
8864 /* Enable autotuning of the PLL clock (if permissible) */
8865 factor = 21;
8866 if (is_lvds) {
8867 if ((intel_panel_use_ssc(dev_priv) &&
8868 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8869 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8870 factor = 25;
8871 } else if (crtc_state->sdvo_tv_clock)
8872 factor = 20;
8873
8874 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8875 *fp |= FP_CB_TUNE;
8876
8877 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8878 *fp2 |= FP_CB_TUNE;
8879
8880 dpll = 0;
8881
8882 if (is_lvds)
8883 dpll |= DPLLB_MODE_LVDS;
8884 else
8885 dpll |= DPLLB_MODE_DAC_SERIAL;
8886
8887 dpll |= (crtc_state->pixel_multiplier - 1)
8888 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8889
8890 if (is_sdvo)
8891 dpll |= DPLL_SDVO_HIGH_SPEED;
8892 if (crtc_state->has_dp_encoder)
8893 dpll |= DPLL_SDVO_HIGH_SPEED;
8894
8895 /* compute bitmask from p1 value */
8896 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8897 /* also FPA1 */
8898 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8899
8900 switch (crtc_state->dpll.p2) {
8901 case 5:
8902 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8903 break;
8904 case 7:
8905 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8906 break;
8907 case 10:
8908 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8909 break;
8910 case 14:
8911 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8912 break;
8913 }
8914
8915 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8916 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8917 else
8918 dpll |= PLL_REF_INPUT_DREFCLK;
8919
8920 return dpll | DPLL_VCO_ENABLE;
8921 }
8922
8923 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8924 struct intel_crtc_state *crtc_state)
8925 {
8926 struct drm_device *dev = crtc->base.dev;
8927 intel_clock_t clock, reduced_clock;
8928 u32 dpll = 0, fp = 0, fp2 = 0;
8929 bool ok, has_reduced_clock = false;
8930 bool is_lvds = false;
8931 struct intel_shared_dpll *pll;
8932
8933 memset(&crtc_state->dpll_hw_state, 0,
8934 sizeof(crtc_state->dpll_hw_state));
8935
8936 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8937
8938 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8939 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8940
8941 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8942 &has_reduced_clock, &reduced_clock);
8943 if (!ok && !crtc_state->clock_set) {
8944 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8945 return -EINVAL;
8946 }
8947 /* Compat-code for transition, will disappear. */
8948 if (!crtc_state->clock_set) {
8949 crtc_state->dpll.n = clock.n;
8950 crtc_state->dpll.m1 = clock.m1;
8951 crtc_state->dpll.m2 = clock.m2;
8952 crtc_state->dpll.p1 = clock.p1;
8953 crtc_state->dpll.p2 = clock.p2;
8954 }
8955
8956 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8957 if (crtc_state->has_pch_encoder) {
8958 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8959 if (has_reduced_clock)
8960 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8961
8962 dpll = ironlake_compute_dpll(crtc, crtc_state,
8963 &fp, &reduced_clock,
8964 has_reduced_clock ? &fp2 : NULL);
8965
8966 crtc_state->dpll_hw_state.dpll = dpll;
8967 crtc_state->dpll_hw_state.fp0 = fp;
8968 if (has_reduced_clock)
8969 crtc_state->dpll_hw_state.fp1 = fp2;
8970 else
8971 crtc_state->dpll_hw_state.fp1 = fp;
8972
8973 pll = intel_get_shared_dpll(crtc, crtc_state);
8974 if (pll == NULL) {
8975 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8976 pipe_name(crtc->pipe));
8977 return -EINVAL;
8978 }
8979 }
8980
8981 if (is_lvds && has_reduced_clock)
8982 crtc->lowfreq_avail = true;
8983 else
8984 crtc->lowfreq_avail = false;
8985
8986 return 0;
8987 }
8988
8989 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8990 struct intel_link_m_n *m_n)
8991 {
8992 struct drm_device *dev = crtc->base.dev;
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994 enum pipe pipe = crtc->pipe;
8995
8996 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8997 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8998 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8999 & ~TU_SIZE_MASK;
9000 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9001 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9002 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9003 }
9004
9005 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9006 enum transcoder transcoder,
9007 struct intel_link_m_n *m_n,
9008 struct intel_link_m_n *m2_n2)
9009 {
9010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 enum pipe pipe = crtc->pipe;
9013
9014 if (INTEL_INFO(dev)->gen >= 5) {
9015 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9016 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9017 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9018 & ~TU_SIZE_MASK;
9019 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9020 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9021 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9022 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9023 * gen < 8) and if DRRS is supported (to make sure the
9024 * registers are not unnecessarily read).
9025 */
9026 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9027 crtc->config->has_drrs) {
9028 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9029 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9030 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9031 & ~TU_SIZE_MASK;
9032 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9033 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9034 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9035 }
9036 } else {
9037 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9038 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9039 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9040 & ~TU_SIZE_MASK;
9041 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9042 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9043 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9044 }
9045 }
9046
9047 void intel_dp_get_m_n(struct intel_crtc *crtc,
9048 struct intel_crtc_state *pipe_config)
9049 {
9050 if (pipe_config->has_pch_encoder)
9051 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9052 else
9053 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9054 &pipe_config->dp_m_n,
9055 &pipe_config->dp_m2_n2);
9056 }
9057
9058 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9059 struct intel_crtc_state *pipe_config)
9060 {
9061 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9062 &pipe_config->fdi_m_n, NULL);
9063 }
9064
9065 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9066 struct intel_crtc_state *pipe_config)
9067 {
9068 struct drm_device *dev = crtc->base.dev;
9069 struct drm_i915_private *dev_priv = dev->dev_private;
9070 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9071 uint32_t ps_ctrl = 0;
9072 int id = -1;
9073 int i;
9074
9075 /* find scaler attached to this pipe */
9076 for (i = 0; i < crtc->num_scalers; i++) {
9077 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9078 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9079 id = i;
9080 pipe_config->pch_pfit.enabled = true;
9081 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9082 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9083 break;
9084 }
9085 }
9086
9087 scaler_state->scaler_id = id;
9088 if (id >= 0) {
9089 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9090 } else {
9091 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9092 }
9093 }
9094
9095 static void
9096 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9097 struct intel_initial_plane_config *plane_config)
9098 {
9099 struct drm_device *dev = crtc->base.dev;
9100 struct drm_i915_private *dev_priv = dev->dev_private;
9101 u32 val, base, offset, stride_mult, tiling;
9102 int pipe = crtc->pipe;
9103 int fourcc, pixel_format;
9104 unsigned int aligned_height;
9105 struct drm_framebuffer *fb;
9106 struct intel_framebuffer *intel_fb;
9107
9108 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9109 if (!intel_fb) {
9110 DRM_DEBUG_KMS("failed to alloc fb\n");
9111 return;
9112 }
9113
9114 fb = &intel_fb->base;
9115
9116 val = I915_READ(PLANE_CTL(pipe, 0));
9117 if (!(val & PLANE_CTL_ENABLE))
9118 goto error;
9119
9120 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9121 fourcc = skl_format_to_fourcc(pixel_format,
9122 val & PLANE_CTL_ORDER_RGBX,
9123 val & PLANE_CTL_ALPHA_MASK);
9124 fb->pixel_format = fourcc;
9125 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9126
9127 tiling = val & PLANE_CTL_TILED_MASK;
9128 switch (tiling) {
9129 case PLANE_CTL_TILED_LINEAR:
9130 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9131 break;
9132 case PLANE_CTL_TILED_X:
9133 plane_config->tiling = I915_TILING_X;
9134 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9135 break;
9136 case PLANE_CTL_TILED_Y:
9137 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9138 break;
9139 case PLANE_CTL_TILED_YF:
9140 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9141 break;
9142 default:
9143 MISSING_CASE(tiling);
9144 goto error;
9145 }
9146
9147 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9148 plane_config->base = base;
9149
9150 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9151
9152 val = I915_READ(PLANE_SIZE(pipe, 0));
9153 fb->height = ((val >> 16) & 0xfff) + 1;
9154 fb->width = ((val >> 0) & 0x1fff) + 1;
9155
9156 val = I915_READ(PLANE_STRIDE(pipe, 0));
9157 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9158 fb->pixel_format);
9159 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9160
9161 aligned_height = intel_fb_align_height(dev, fb->height,
9162 fb->pixel_format,
9163 fb->modifier[0]);
9164
9165 plane_config->size = fb->pitches[0] * aligned_height;
9166
9167 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9168 pipe_name(pipe), fb->width, fb->height,
9169 fb->bits_per_pixel, base, fb->pitches[0],
9170 plane_config->size);
9171
9172 plane_config->fb = intel_fb;
9173 return;
9174
9175 error:
9176 kfree(fb);
9177 }
9178
9179 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9180 struct intel_crtc_state *pipe_config)
9181 {
9182 struct drm_device *dev = crtc->base.dev;
9183 struct drm_i915_private *dev_priv = dev->dev_private;
9184 uint32_t tmp;
9185
9186 tmp = I915_READ(PF_CTL(crtc->pipe));
9187
9188 if (tmp & PF_ENABLE) {
9189 pipe_config->pch_pfit.enabled = true;
9190 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9191 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9192
9193 /* We currently do not free assignements of panel fitters on
9194 * ivb/hsw (since we don't use the higher upscaling modes which
9195 * differentiates them) so just WARN about this case for now. */
9196 if (IS_GEN7(dev)) {
9197 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9198 PF_PIPE_SEL_IVB(crtc->pipe));
9199 }
9200 }
9201 }
9202
9203 static void
9204 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9205 struct intel_initial_plane_config *plane_config)
9206 {
9207 struct drm_device *dev = crtc->base.dev;
9208 struct drm_i915_private *dev_priv = dev->dev_private;
9209 u32 val, base, offset;
9210 int pipe = crtc->pipe;
9211 int fourcc, pixel_format;
9212 unsigned int aligned_height;
9213 struct drm_framebuffer *fb;
9214 struct intel_framebuffer *intel_fb;
9215
9216 val = I915_READ(DSPCNTR(pipe));
9217 if (!(val & DISPLAY_PLANE_ENABLE))
9218 return;
9219
9220 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9221 if (!intel_fb) {
9222 DRM_DEBUG_KMS("failed to alloc fb\n");
9223 return;
9224 }
9225
9226 fb = &intel_fb->base;
9227
9228 if (INTEL_INFO(dev)->gen >= 4) {
9229 if (val & DISPPLANE_TILED) {
9230 plane_config->tiling = I915_TILING_X;
9231 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9232 }
9233 }
9234
9235 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9236 fourcc = i9xx_format_to_fourcc(pixel_format);
9237 fb->pixel_format = fourcc;
9238 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9239
9240 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9241 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9242 offset = I915_READ(DSPOFFSET(pipe));
9243 } else {
9244 if (plane_config->tiling)
9245 offset = I915_READ(DSPTILEOFF(pipe));
9246 else
9247 offset = I915_READ(DSPLINOFF(pipe));
9248 }
9249 plane_config->base = base;
9250
9251 val = I915_READ(PIPESRC(pipe));
9252 fb->width = ((val >> 16) & 0xfff) + 1;
9253 fb->height = ((val >> 0) & 0xfff) + 1;
9254
9255 val = I915_READ(DSPSTRIDE(pipe));
9256 fb->pitches[0] = val & 0xffffffc0;
9257
9258 aligned_height = intel_fb_align_height(dev, fb->height,
9259 fb->pixel_format,
9260 fb->modifier[0]);
9261
9262 plane_config->size = fb->pitches[0] * aligned_height;
9263
9264 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9265 pipe_name(pipe), fb->width, fb->height,
9266 fb->bits_per_pixel, base, fb->pitches[0],
9267 plane_config->size);
9268
9269 plane_config->fb = intel_fb;
9270 }
9271
9272 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9273 struct intel_crtc_state *pipe_config)
9274 {
9275 struct drm_device *dev = crtc->base.dev;
9276 struct drm_i915_private *dev_priv = dev->dev_private;
9277 uint32_t tmp;
9278
9279 if (!intel_display_power_is_enabled(dev_priv,
9280 POWER_DOMAIN_PIPE(crtc->pipe)))
9281 return false;
9282
9283 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9284 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9285
9286 tmp = I915_READ(PIPECONF(crtc->pipe));
9287 if (!(tmp & PIPECONF_ENABLE))
9288 return false;
9289
9290 switch (tmp & PIPECONF_BPC_MASK) {
9291 case PIPECONF_6BPC:
9292 pipe_config->pipe_bpp = 18;
9293 break;
9294 case PIPECONF_8BPC:
9295 pipe_config->pipe_bpp = 24;
9296 break;
9297 case PIPECONF_10BPC:
9298 pipe_config->pipe_bpp = 30;
9299 break;
9300 case PIPECONF_12BPC:
9301 pipe_config->pipe_bpp = 36;
9302 break;
9303 default:
9304 break;
9305 }
9306
9307 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9308 pipe_config->limited_color_range = true;
9309
9310 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9311 struct intel_shared_dpll *pll;
9312
9313 pipe_config->has_pch_encoder = true;
9314
9315 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9316 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9317 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9318
9319 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9320
9321 if (HAS_PCH_IBX(dev_priv->dev)) {
9322 pipe_config->shared_dpll =
9323 (enum intel_dpll_id) crtc->pipe;
9324 } else {
9325 tmp = I915_READ(PCH_DPLL_SEL);
9326 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9327 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9328 else
9329 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9330 }
9331
9332 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9333
9334 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9335 &pipe_config->dpll_hw_state));
9336
9337 tmp = pipe_config->dpll_hw_state.dpll;
9338 pipe_config->pixel_multiplier =
9339 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9340 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9341
9342 ironlake_pch_clock_get(crtc, pipe_config);
9343 } else {
9344 pipe_config->pixel_multiplier = 1;
9345 }
9346
9347 intel_get_pipe_timings(crtc, pipe_config);
9348
9349 ironlake_get_pfit_config(crtc, pipe_config);
9350
9351 return true;
9352 }
9353
9354 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9355 {
9356 struct drm_device *dev = dev_priv->dev;
9357 struct intel_crtc *crtc;
9358
9359 for_each_intel_crtc(dev, crtc)
9360 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9361 pipe_name(crtc->pipe));
9362
9363 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9364 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9365 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9366 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9367 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9368 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9369 "CPU PWM1 enabled\n");
9370 if (IS_HASWELL(dev))
9371 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9372 "CPU PWM2 enabled\n");
9373 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9374 "PCH PWM1 enabled\n");
9375 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9376 "Utility pin enabled\n");
9377 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9378
9379 /*
9380 * In theory we can still leave IRQs enabled, as long as only the HPD
9381 * interrupts remain enabled. We used to check for that, but since it's
9382 * gen-specific and since we only disable LCPLL after we fully disable
9383 * the interrupts, the check below should be enough.
9384 */
9385 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9386 }
9387
9388 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9389 {
9390 struct drm_device *dev = dev_priv->dev;
9391
9392 if (IS_HASWELL(dev))
9393 return I915_READ(D_COMP_HSW);
9394 else
9395 return I915_READ(D_COMP_BDW);
9396 }
9397
9398 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9399 {
9400 struct drm_device *dev = dev_priv->dev;
9401
9402 if (IS_HASWELL(dev)) {
9403 mutex_lock(&dev_priv->rps.hw_lock);
9404 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9405 val))
9406 DRM_ERROR("Failed to write to D_COMP\n");
9407 mutex_unlock(&dev_priv->rps.hw_lock);
9408 } else {
9409 I915_WRITE(D_COMP_BDW, val);
9410 POSTING_READ(D_COMP_BDW);
9411 }
9412 }
9413
9414 /*
9415 * This function implements pieces of two sequences from BSpec:
9416 * - Sequence for display software to disable LCPLL
9417 * - Sequence for display software to allow package C8+
9418 * The steps implemented here are just the steps that actually touch the LCPLL
9419 * register. Callers should take care of disabling all the display engine
9420 * functions, doing the mode unset, fixing interrupts, etc.
9421 */
9422 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9423 bool switch_to_fclk, bool allow_power_down)
9424 {
9425 uint32_t val;
9426
9427 assert_can_disable_lcpll(dev_priv);
9428
9429 val = I915_READ(LCPLL_CTL);
9430
9431 if (switch_to_fclk) {
9432 val |= LCPLL_CD_SOURCE_FCLK;
9433 I915_WRITE(LCPLL_CTL, val);
9434
9435 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9436 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9437 DRM_ERROR("Switching to FCLK failed\n");
9438
9439 val = I915_READ(LCPLL_CTL);
9440 }
9441
9442 val |= LCPLL_PLL_DISABLE;
9443 I915_WRITE(LCPLL_CTL, val);
9444 POSTING_READ(LCPLL_CTL);
9445
9446 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9447 DRM_ERROR("LCPLL still locked\n");
9448
9449 val = hsw_read_dcomp(dev_priv);
9450 val |= D_COMP_COMP_DISABLE;
9451 hsw_write_dcomp(dev_priv, val);
9452 ndelay(100);
9453
9454 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9455 1))
9456 DRM_ERROR("D_COMP RCOMP still in progress\n");
9457
9458 if (allow_power_down) {
9459 val = I915_READ(LCPLL_CTL);
9460 val |= LCPLL_POWER_DOWN_ALLOW;
9461 I915_WRITE(LCPLL_CTL, val);
9462 POSTING_READ(LCPLL_CTL);
9463 }
9464 }
9465
9466 /*
9467 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9468 * source.
9469 */
9470 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9471 {
9472 uint32_t val;
9473
9474 val = I915_READ(LCPLL_CTL);
9475
9476 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9477 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9478 return;
9479
9480 /*
9481 * Make sure we're not on PC8 state before disabling PC8, otherwise
9482 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9483 */
9484 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9485
9486 if (val & LCPLL_POWER_DOWN_ALLOW) {
9487 val &= ~LCPLL_POWER_DOWN_ALLOW;
9488 I915_WRITE(LCPLL_CTL, val);
9489 POSTING_READ(LCPLL_CTL);
9490 }
9491
9492 val = hsw_read_dcomp(dev_priv);
9493 val |= D_COMP_COMP_FORCE;
9494 val &= ~D_COMP_COMP_DISABLE;
9495 hsw_write_dcomp(dev_priv, val);
9496
9497 val = I915_READ(LCPLL_CTL);
9498 val &= ~LCPLL_PLL_DISABLE;
9499 I915_WRITE(LCPLL_CTL, val);
9500
9501 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9502 DRM_ERROR("LCPLL not locked yet\n");
9503
9504 if (val & LCPLL_CD_SOURCE_FCLK) {
9505 val = I915_READ(LCPLL_CTL);
9506 val &= ~LCPLL_CD_SOURCE_FCLK;
9507 I915_WRITE(LCPLL_CTL, val);
9508
9509 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9510 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9511 DRM_ERROR("Switching back to LCPLL failed\n");
9512 }
9513
9514 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9515 intel_update_cdclk(dev_priv->dev);
9516 }
9517
9518 /*
9519 * Package states C8 and deeper are really deep PC states that can only be
9520 * reached when all the devices on the system allow it, so even if the graphics
9521 * device allows PC8+, it doesn't mean the system will actually get to these
9522 * states. Our driver only allows PC8+ when going into runtime PM.
9523 *
9524 * The requirements for PC8+ are that all the outputs are disabled, the power
9525 * well is disabled and most interrupts are disabled, and these are also
9526 * requirements for runtime PM. When these conditions are met, we manually do
9527 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9528 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9529 * hang the machine.
9530 *
9531 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9532 * the state of some registers, so when we come back from PC8+ we need to
9533 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9534 * need to take care of the registers kept by RC6. Notice that this happens even
9535 * if we don't put the device in PCI D3 state (which is what currently happens
9536 * because of the runtime PM support).
9537 *
9538 * For more, read "Display Sequences for Package C8" on the hardware
9539 * documentation.
9540 */
9541 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9542 {
9543 struct drm_device *dev = dev_priv->dev;
9544 uint32_t val;
9545
9546 DRM_DEBUG_KMS("Enabling package C8+\n");
9547
9548 if (HAS_PCH_LPT_LP(dev)) {
9549 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9550 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9551 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9552 }
9553
9554 lpt_disable_clkout_dp(dev);
9555 hsw_disable_lcpll(dev_priv, true, true);
9556 }
9557
9558 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9559 {
9560 struct drm_device *dev = dev_priv->dev;
9561 uint32_t val;
9562
9563 DRM_DEBUG_KMS("Disabling package C8+\n");
9564
9565 hsw_restore_lcpll(dev_priv);
9566 lpt_init_pch_refclk(dev);
9567
9568 if (HAS_PCH_LPT_LP(dev)) {
9569 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9570 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9571 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9572 }
9573
9574 intel_prepare_ddi(dev);
9575 }
9576
9577 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9578 {
9579 struct drm_device *dev = old_state->dev;
9580 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9581
9582 broxton_set_cdclk(dev, req_cdclk);
9583 }
9584
9585 /* compute the max rate for new configuration */
9586 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9587 {
9588 struct intel_crtc *intel_crtc;
9589 struct intel_crtc_state *crtc_state;
9590 int max_pixel_rate = 0;
9591
9592 for_each_intel_crtc(state->dev, intel_crtc) {
9593 int pixel_rate;
9594
9595 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9596 if (IS_ERR(crtc_state))
9597 return PTR_ERR(crtc_state);
9598
9599 if (!crtc_state->base.enable)
9600 continue;
9601
9602 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9603
9604 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9605 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9606 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9607
9608 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9609 }
9610
9611 return max_pixel_rate;
9612 }
9613
9614 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9615 {
9616 struct drm_i915_private *dev_priv = dev->dev_private;
9617 uint32_t val, data;
9618 int ret;
9619
9620 if (WARN((I915_READ(LCPLL_CTL) &
9621 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9622 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9623 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9624 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9625 "trying to change cdclk frequency with cdclk not enabled\n"))
9626 return;
9627
9628 mutex_lock(&dev_priv->rps.hw_lock);
9629 ret = sandybridge_pcode_write(dev_priv,
9630 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9631 mutex_unlock(&dev_priv->rps.hw_lock);
9632 if (ret) {
9633 DRM_ERROR("failed to inform pcode about cdclk change\n");
9634 return;
9635 }
9636
9637 val = I915_READ(LCPLL_CTL);
9638 val |= LCPLL_CD_SOURCE_FCLK;
9639 I915_WRITE(LCPLL_CTL, val);
9640
9641 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9642 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9643 DRM_ERROR("Switching to FCLK failed\n");
9644
9645 val = I915_READ(LCPLL_CTL);
9646 val &= ~LCPLL_CLK_FREQ_MASK;
9647
9648 switch (cdclk) {
9649 case 450000:
9650 val |= LCPLL_CLK_FREQ_450;
9651 data = 0;
9652 break;
9653 case 540000:
9654 val |= LCPLL_CLK_FREQ_54O_BDW;
9655 data = 1;
9656 break;
9657 case 337500:
9658 val |= LCPLL_CLK_FREQ_337_5_BDW;
9659 data = 2;
9660 break;
9661 case 675000:
9662 val |= LCPLL_CLK_FREQ_675_BDW;
9663 data = 3;
9664 break;
9665 default:
9666 WARN(1, "invalid cdclk frequency\n");
9667 return;
9668 }
9669
9670 I915_WRITE(LCPLL_CTL, val);
9671
9672 val = I915_READ(LCPLL_CTL);
9673 val &= ~LCPLL_CD_SOURCE_FCLK;
9674 I915_WRITE(LCPLL_CTL, val);
9675
9676 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9677 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9678 DRM_ERROR("Switching back to LCPLL failed\n");
9679
9680 mutex_lock(&dev_priv->rps.hw_lock);
9681 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9682 mutex_unlock(&dev_priv->rps.hw_lock);
9683
9684 intel_update_cdclk(dev);
9685
9686 WARN(cdclk != dev_priv->cdclk_freq,
9687 "cdclk requested %d kHz but got %d kHz\n",
9688 cdclk, dev_priv->cdclk_freq);
9689 }
9690
9691 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9692 {
9693 struct drm_i915_private *dev_priv = to_i915(state->dev);
9694 int max_pixclk = ilk_max_pixel_rate(state);
9695 int cdclk;
9696
9697 /*
9698 * FIXME should also account for plane ratio
9699 * once 64bpp pixel formats are supported.
9700 */
9701 if (max_pixclk > 540000)
9702 cdclk = 675000;
9703 else if (max_pixclk > 450000)
9704 cdclk = 540000;
9705 else if (max_pixclk > 337500)
9706 cdclk = 450000;
9707 else
9708 cdclk = 337500;
9709
9710 /*
9711 * FIXME move the cdclk caclulation to
9712 * compute_config() so we can fail gracegully.
9713 */
9714 if (cdclk > dev_priv->max_cdclk_freq) {
9715 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9716 cdclk, dev_priv->max_cdclk_freq);
9717 cdclk = dev_priv->max_cdclk_freq;
9718 }
9719
9720 to_intel_atomic_state(state)->cdclk = cdclk;
9721
9722 return 0;
9723 }
9724
9725 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9726 {
9727 struct drm_device *dev = old_state->dev;
9728 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9729
9730 broadwell_set_cdclk(dev, req_cdclk);
9731 }
9732
9733 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9734 struct intel_crtc_state *crtc_state)
9735 {
9736 if (!intel_ddi_pll_select(crtc, crtc_state))
9737 return -EINVAL;
9738
9739 crtc->lowfreq_avail = false;
9740
9741 return 0;
9742 }
9743
9744 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9745 enum port port,
9746 struct intel_crtc_state *pipe_config)
9747 {
9748 switch (port) {
9749 case PORT_A:
9750 pipe_config->ddi_pll_sel = SKL_DPLL0;
9751 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9752 break;
9753 case PORT_B:
9754 pipe_config->ddi_pll_sel = SKL_DPLL1;
9755 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9756 break;
9757 case PORT_C:
9758 pipe_config->ddi_pll_sel = SKL_DPLL2;
9759 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9760 break;
9761 default:
9762 DRM_ERROR("Incorrect port type\n");
9763 }
9764 }
9765
9766 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9767 enum port port,
9768 struct intel_crtc_state *pipe_config)
9769 {
9770 u32 temp, dpll_ctl1;
9771
9772 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9773 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9774
9775 switch (pipe_config->ddi_pll_sel) {
9776 case SKL_DPLL0:
9777 /*
9778 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9779 * of the shared DPLL framework and thus needs to be read out
9780 * separately
9781 */
9782 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9783 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9784 break;
9785 case SKL_DPLL1:
9786 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9787 break;
9788 case SKL_DPLL2:
9789 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9790 break;
9791 case SKL_DPLL3:
9792 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9793 break;
9794 }
9795 }
9796
9797 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9798 enum port port,
9799 struct intel_crtc_state *pipe_config)
9800 {
9801 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9802
9803 switch (pipe_config->ddi_pll_sel) {
9804 case PORT_CLK_SEL_WRPLL1:
9805 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9806 break;
9807 case PORT_CLK_SEL_WRPLL2:
9808 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9809 break;
9810 case PORT_CLK_SEL_SPLL:
9811 pipe_config->shared_dpll = DPLL_ID_SPLL;
9812 }
9813 }
9814
9815 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9816 struct intel_crtc_state *pipe_config)
9817 {
9818 struct drm_device *dev = crtc->base.dev;
9819 struct drm_i915_private *dev_priv = dev->dev_private;
9820 struct intel_shared_dpll *pll;
9821 enum port port;
9822 uint32_t tmp;
9823
9824 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9825
9826 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9827
9828 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9829 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9830 else if (IS_BROXTON(dev))
9831 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9832 else
9833 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9834
9835 if (pipe_config->shared_dpll >= 0) {
9836 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9837
9838 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9839 &pipe_config->dpll_hw_state));
9840 }
9841
9842 /*
9843 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9844 * DDI E. So just check whether this pipe is wired to DDI E and whether
9845 * the PCH transcoder is on.
9846 */
9847 if (INTEL_INFO(dev)->gen < 9 &&
9848 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9849 pipe_config->has_pch_encoder = true;
9850
9851 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9852 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9853 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9854
9855 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9856 }
9857 }
9858
9859 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9860 struct intel_crtc_state *pipe_config)
9861 {
9862 struct drm_device *dev = crtc->base.dev;
9863 struct drm_i915_private *dev_priv = dev->dev_private;
9864 enum intel_display_power_domain pfit_domain;
9865 uint32_t tmp;
9866
9867 if (!intel_display_power_is_enabled(dev_priv,
9868 POWER_DOMAIN_PIPE(crtc->pipe)))
9869 return false;
9870
9871 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9872 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9873
9874 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9875 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9876 enum pipe trans_edp_pipe;
9877 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9878 default:
9879 WARN(1, "unknown pipe linked to edp transcoder\n");
9880 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9881 case TRANS_DDI_EDP_INPUT_A_ON:
9882 trans_edp_pipe = PIPE_A;
9883 break;
9884 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9885 trans_edp_pipe = PIPE_B;
9886 break;
9887 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9888 trans_edp_pipe = PIPE_C;
9889 break;
9890 }
9891
9892 if (trans_edp_pipe == crtc->pipe)
9893 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9894 }
9895
9896 if (!intel_display_power_is_enabled(dev_priv,
9897 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9898 return false;
9899
9900 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9901 if (!(tmp & PIPECONF_ENABLE))
9902 return false;
9903
9904 haswell_get_ddi_port_state(crtc, pipe_config);
9905
9906 intel_get_pipe_timings(crtc, pipe_config);
9907
9908 if (INTEL_INFO(dev)->gen >= 9) {
9909 skl_init_scalers(dev, crtc, pipe_config);
9910 }
9911
9912 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9913
9914 if (INTEL_INFO(dev)->gen >= 9) {
9915 pipe_config->scaler_state.scaler_id = -1;
9916 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9917 }
9918
9919 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9920 if (INTEL_INFO(dev)->gen >= 9)
9921 skylake_get_pfit_config(crtc, pipe_config);
9922 else
9923 ironlake_get_pfit_config(crtc, pipe_config);
9924 }
9925
9926 if (IS_HASWELL(dev))
9927 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9928 (I915_READ(IPS_CTL) & IPS_ENABLE);
9929
9930 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9931 pipe_config->pixel_multiplier =
9932 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9933 } else {
9934 pipe_config->pixel_multiplier = 1;
9935 }
9936
9937 return true;
9938 }
9939
9940 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9941 {
9942 struct drm_device *dev = crtc->dev;
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9945 uint32_t cntl = 0, size = 0;
9946
9947 if (base) {
9948 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9949 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9950 unsigned int stride = roundup_pow_of_two(width) * 4;
9951
9952 switch (stride) {
9953 default:
9954 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9955 width, stride);
9956 stride = 256;
9957 /* fallthrough */
9958 case 256:
9959 case 512:
9960 case 1024:
9961 case 2048:
9962 break;
9963 }
9964
9965 cntl |= CURSOR_ENABLE |
9966 CURSOR_GAMMA_ENABLE |
9967 CURSOR_FORMAT_ARGB |
9968 CURSOR_STRIDE(stride);
9969
9970 size = (height << 12) | width;
9971 }
9972
9973 if (intel_crtc->cursor_cntl != 0 &&
9974 (intel_crtc->cursor_base != base ||
9975 intel_crtc->cursor_size != size ||
9976 intel_crtc->cursor_cntl != cntl)) {
9977 /* On these chipsets we can only modify the base/size/stride
9978 * whilst the cursor is disabled.
9979 */
9980 I915_WRITE(CURCNTR(PIPE_A), 0);
9981 POSTING_READ(CURCNTR(PIPE_A));
9982 intel_crtc->cursor_cntl = 0;
9983 }
9984
9985 if (intel_crtc->cursor_base != base) {
9986 I915_WRITE(CURBASE(PIPE_A), base);
9987 intel_crtc->cursor_base = base;
9988 }
9989
9990 if (intel_crtc->cursor_size != size) {
9991 I915_WRITE(CURSIZE, size);
9992 intel_crtc->cursor_size = size;
9993 }
9994
9995 if (intel_crtc->cursor_cntl != cntl) {
9996 I915_WRITE(CURCNTR(PIPE_A), cntl);
9997 POSTING_READ(CURCNTR(PIPE_A));
9998 intel_crtc->cursor_cntl = cntl;
9999 }
10000 }
10001
10002 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10003 {
10004 struct drm_device *dev = crtc->dev;
10005 struct drm_i915_private *dev_priv = dev->dev_private;
10006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10007 int pipe = intel_crtc->pipe;
10008 uint32_t cntl;
10009
10010 cntl = 0;
10011 if (base) {
10012 cntl = MCURSOR_GAMMA_ENABLE;
10013 switch (intel_crtc->base.cursor->state->crtc_w) {
10014 case 64:
10015 cntl |= CURSOR_MODE_64_ARGB_AX;
10016 break;
10017 case 128:
10018 cntl |= CURSOR_MODE_128_ARGB_AX;
10019 break;
10020 case 256:
10021 cntl |= CURSOR_MODE_256_ARGB_AX;
10022 break;
10023 default:
10024 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10025 return;
10026 }
10027 cntl |= pipe << 28; /* Connect to correct pipe */
10028
10029 if (HAS_DDI(dev))
10030 cntl |= CURSOR_PIPE_CSC_ENABLE;
10031 }
10032
10033 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10034 cntl |= CURSOR_ROTATE_180;
10035
10036 if (intel_crtc->cursor_cntl != cntl) {
10037 I915_WRITE(CURCNTR(pipe), cntl);
10038 POSTING_READ(CURCNTR(pipe));
10039 intel_crtc->cursor_cntl = cntl;
10040 }
10041
10042 /* and commit changes on next vblank */
10043 I915_WRITE(CURBASE(pipe), base);
10044 POSTING_READ(CURBASE(pipe));
10045
10046 intel_crtc->cursor_base = base;
10047 }
10048
10049 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10050 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10051 bool on)
10052 {
10053 struct drm_device *dev = crtc->dev;
10054 struct drm_i915_private *dev_priv = dev->dev_private;
10055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10056 int pipe = intel_crtc->pipe;
10057 struct drm_plane_state *cursor_state = crtc->cursor->state;
10058 int x = cursor_state->crtc_x;
10059 int y = cursor_state->crtc_y;
10060 u32 base = 0, pos = 0;
10061
10062 if (on)
10063 base = intel_crtc->cursor_addr;
10064
10065 if (x >= intel_crtc->config->pipe_src_w)
10066 base = 0;
10067
10068 if (y >= intel_crtc->config->pipe_src_h)
10069 base = 0;
10070
10071 if (x < 0) {
10072 if (x + cursor_state->crtc_w <= 0)
10073 base = 0;
10074
10075 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10076 x = -x;
10077 }
10078 pos |= x << CURSOR_X_SHIFT;
10079
10080 if (y < 0) {
10081 if (y + cursor_state->crtc_h <= 0)
10082 base = 0;
10083
10084 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10085 y = -y;
10086 }
10087 pos |= y << CURSOR_Y_SHIFT;
10088
10089 if (base == 0 && intel_crtc->cursor_base == 0)
10090 return;
10091
10092 I915_WRITE(CURPOS(pipe), pos);
10093
10094 /* ILK+ do this automagically */
10095 if (HAS_GMCH_DISPLAY(dev) &&
10096 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10097 base += (cursor_state->crtc_h *
10098 cursor_state->crtc_w - 1) * 4;
10099 }
10100
10101 if (IS_845G(dev) || IS_I865G(dev))
10102 i845_update_cursor(crtc, base);
10103 else
10104 i9xx_update_cursor(crtc, base);
10105 }
10106
10107 static bool cursor_size_ok(struct drm_device *dev,
10108 uint32_t width, uint32_t height)
10109 {
10110 if (width == 0 || height == 0)
10111 return false;
10112
10113 /*
10114 * 845g/865g are special in that they are only limited by
10115 * the width of their cursors, the height is arbitrary up to
10116 * the precision of the register. Everything else requires
10117 * square cursors, limited to a few power-of-two sizes.
10118 */
10119 if (IS_845G(dev) || IS_I865G(dev)) {
10120 if ((width & 63) != 0)
10121 return false;
10122
10123 if (width > (IS_845G(dev) ? 64 : 512))
10124 return false;
10125
10126 if (height > 1023)
10127 return false;
10128 } else {
10129 switch (width | height) {
10130 case 256:
10131 case 128:
10132 if (IS_GEN2(dev))
10133 return false;
10134 case 64:
10135 break;
10136 default:
10137 return false;
10138 }
10139 }
10140
10141 return true;
10142 }
10143
10144 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10145 u16 *blue, uint32_t start, uint32_t size)
10146 {
10147 int end = (start + size > 256) ? 256 : start + size, i;
10148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10149
10150 for (i = start; i < end; i++) {
10151 intel_crtc->lut_r[i] = red[i] >> 8;
10152 intel_crtc->lut_g[i] = green[i] >> 8;
10153 intel_crtc->lut_b[i] = blue[i] >> 8;
10154 }
10155
10156 intel_crtc_load_lut(crtc);
10157 }
10158
10159 /* VESA 640x480x72Hz mode to set on the pipe */
10160 static struct drm_display_mode load_detect_mode = {
10161 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10162 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10163 };
10164
10165 struct drm_framebuffer *
10166 __intel_framebuffer_create(struct drm_device *dev,
10167 struct drm_mode_fb_cmd2 *mode_cmd,
10168 struct drm_i915_gem_object *obj)
10169 {
10170 struct intel_framebuffer *intel_fb;
10171 int ret;
10172
10173 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10174 if (!intel_fb)
10175 return ERR_PTR(-ENOMEM);
10176
10177 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10178 if (ret)
10179 goto err;
10180
10181 return &intel_fb->base;
10182
10183 err:
10184 kfree(intel_fb);
10185 return ERR_PTR(ret);
10186 }
10187
10188 static struct drm_framebuffer *
10189 intel_framebuffer_create(struct drm_device *dev,
10190 struct drm_mode_fb_cmd2 *mode_cmd,
10191 struct drm_i915_gem_object *obj)
10192 {
10193 struct drm_framebuffer *fb;
10194 int ret;
10195
10196 ret = i915_mutex_lock_interruptible(dev);
10197 if (ret)
10198 return ERR_PTR(ret);
10199 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10200 mutex_unlock(&dev->struct_mutex);
10201
10202 return fb;
10203 }
10204
10205 static u32
10206 intel_framebuffer_pitch_for_width(int width, int bpp)
10207 {
10208 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10209 return ALIGN(pitch, 64);
10210 }
10211
10212 static u32
10213 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10214 {
10215 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10216 return PAGE_ALIGN(pitch * mode->vdisplay);
10217 }
10218
10219 static struct drm_framebuffer *
10220 intel_framebuffer_create_for_mode(struct drm_device *dev,
10221 struct drm_display_mode *mode,
10222 int depth, int bpp)
10223 {
10224 struct drm_framebuffer *fb;
10225 struct drm_i915_gem_object *obj;
10226 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10227
10228 obj = i915_gem_alloc_object(dev,
10229 intel_framebuffer_size_for_mode(mode, bpp));
10230 if (obj == NULL)
10231 return ERR_PTR(-ENOMEM);
10232
10233 mode_cmd.width = mode->hdisplay;
10234 mode_cmd.height = mode->vdisplay;
10235 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10236 bpp);
10237 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10238
10239 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10240 if (IS_ERR(fb))
10241 drm_gem_object_unreference_unlocked(&obj->base);
10242
10243 return fb;
10244 }
10245
10246 static struct drm_framebuffer *
10247 mode_fits_in_fbdev(struct drm_device *dev,
10248 struct drm_display_mode *mode)
10249 {
10250 #ifdef CONFIG_DRM_FBDEV_EMULATION
10251 struct drm_i915_private *dev_priv = dev->dev_private;
10252 struct drm_i915_gem_object *obj;
10253 struct drm_framebuffer *fb;
10254
10255 if (!dev_priv->fbdev)
10256 return NULL;
10257
10258 if (!dev_priv->fbdev->fb)
10259 return NULL;
10260
10261 obj = dev_priv->fbdev->fb->obj;
10262 BUG_ON(!obj);
10263
10264 fb = &dev_priv->fbdev->fb->base;
10265 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10266 fb->bits_per_pixel))
10267 return NULL;
10268
10269 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10270 return NULL;
10271
10272 return fb;
10273 #else
10274 return NULL;
10275 #endif
10276 }
10277
10278 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10279 struct drm_crtc *crtc,
10280 struct drm_display_mode *mode,
10281 struct drm_framebuffer *fb,
10282 int x, int y)
10283 {
10284 struct drm_plane_state *plane_state;
10285 int hdisplay, vdisplay;
10286 int ret;
10287
10288 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10289 if (IS_ERR(plane_state))
10290 return PTR_ERR(plane_state);
10291
10292 if (mode)
10293 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10294 else
10295 hdisplay = vdisplay = 0;
10296
10297 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10298 if (ret)
10299 return ret;
10300 drm_atomic_set_fb_for_plane(plane_state, fb);
10301 plane_state->crtc_x = 0;
10302 plane_state->crtc_y = 0;
10303 plane_state->crtc_w = hdisplay;
10304 plane_state->crtc_h = vdisplay;
10305 plane_state->src_x = x << 16;
10306 plane_state->src_y = y << 16;
10307 plane_state->src_w = hdisplay << 16;
10308 plane_state->src_h = vdisplay << 16;
10309
10310 return 0;
10311 }
10312
10313 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10314 struct drm_display_mode *mode,
10315 struct intel_load_detect_pipe *old,
10316 struct drm_modeset_acquire_ctx *ctx)
10317 {
10318 struct intel_crtc *intel_crtc;
10319 struct intel_encoder *intel_encoder =
10320 intel_attached_encoder(connector);
10321 struct drm_crtc *possible_crtc;
10322 struct drm_encoder *encoder = &intel_encoder->base;
10323 struct drm_crtc *crtc = NULL;
10324 struct drm_device *dev = encoder->dev;
10325 struct drm_framebuffer *fb;
10326 struct drm_mode_config *config = &dev->mode_config;
10327 struct drm_atomic_state *state = NULL;
10328 struct drm_connector_state *connector_state;
10329 struct intel_crtc_state *crtc_state;
10330 int ret, i = -1;
10331
10332 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10333 connector->base.id, connector->name,
10334 encoder->base.id, encoder->name);
10335
10336 retry:
10337 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10338 if (ret)
10339 goto fail;
10340
10341 /*
10342 * Algorithm gets a little messy:
10343 *
10344 * - if the connector already has an assigned crtc, use it (but make
10345 * sure it's on first)
10346 *
10347 * - try to find the first unused crtc that can drive this connector,
10348 * and use that if we find one
10349 */
10350
10351 /* See if we already have a CRTC for this connector */
10352 if (encoder->crtc) {
10353 crtc = encoder->crtc;
10354
10355 ret = drm_modeset_lock(&crtc->mutex, ctx);
10356 if (ret)
10357 goto fail;
10358 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10359 if (ret)
10360 goto fail;
10361
10362 old->dpms_mode = connector->dpms;
10363 old->load_detect_temp = false;
10364
10365 /* Make sure the crtc and connector are running */
10366 if (connector->dpms != DRM_MODE_DPMS_ON)
10367 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10368
10369 return true;
10370 }
10371
10372 /* Find an unused one (if possible) */
10373 for_each_crtc(dev, possible_crtc) {
10374 i++;
10375 if (!(encoder->possible_crtcs & (1 << i)))
10376 continue;
10377 if (possible_crtc->state->enable)
10378 continue;
10379
10380 crtc = possible_crtc;
10381 break;
10382 }
10383
10384 /*
10385 * If we didn't find an unused CRTC, don't use any.
10386 */
10387 if (!crtc) {
10388 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10389 goto fail;
10390 }
10391
10392 ret = drm_modeset_lock(&crtc->mutex, ctx);
10393 if (ret)
10394 goto fail;
10395 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10396 if (ret)
10397 goto fail;
10398
10399 intel_crtc = to_intel_crtc(crtc);
10400 old->dpms_mode = connector->dpms;
10401 old->load_detect_temp = true;
10402 old->release_fb = NULL;
10403
10404 state = drm_atomic_state_alloc(dev);
10405 if (!state)
10406 return false;
10407
10408 state->acquire_ctx = ctx;
10409
10410 connector_state = drm_atomic_get_connector_state(state, connector);
10411 if (IS_ERR(connector_state)) {
10412 ret = PTR_ERR(connector_state);
10413 goto fail;
10414 }
10415
10416 connector_state->crtc = crtc;
10417 connector_state->best_encoder = &intel_encoder->base;
10418
10419 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10420 if (IS_ERR(crtc_state)) {
10421 ret = PTR_ERR(crtc_state);
10422 goto fail;
10423 }
10424
10425 crtc_state->base.active = crtc_state->base.enable = true;
10426
10427 if (!mode)
10428 mode = &load_detect_mode;
10429
10430 /* We need a framebuffer large enough to accommodate all accesses
10431 * that the plane may generate whilst we perform load detection.
10432 * We can not rely on the fbcon either being present (we get called
10433 * during its initialisation to detect all boot displays, or it may
10434 * not even exist) or that it is large enough to satisfy the
10435 * requested mode.
10436 */
10437 fb = mode_fits_in_fbdev(dev, mode);
10438 if (fb == NULL) {
10439 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10440 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10441 old->release_fb = fb;
10442 } else
10443 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10444 if (IS_ERR(fb)) {
10445 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10446 goto fail;
10447 }
10448
10449 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10450 if (ret)
10451 goto fail;
10452
10453 drm_mode_copy(&crtc_state->base.mode, mode);
10454
10455 if (drm_atomic_commit(state)) {
10456 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10457 if (old->release_fb)
10458 old->release_fb->funcs->destroy(old->release_fb);
10459 goto fail;
10460 }
10461 crtc->primary->crtc = crtc;
10462
10463 /* let the connector get through one full cycle before testing */
10464 intel_wait_for_vblank(dev, intel_crtc->pipe);
10465 return true;
10466
10467 fail:
10468 drm_atomic_state_free(state);
10469 state = NULL;
10470
10471 if (ret == -EDEADLK) {
10472 drm_modeset_backoff(ctx);
10473 goto retry;
10474 }
10475
10476 return false;
10477 }
10478
10479 void intel_release_load_detect_pipe(struct drm_connector *connector,
10480 struct intel_load_detect_pipe *old,
10481 struct drm_modeset_acquire_ctx *ctx)
10482 {
10483 struct drm_device *dev = connector->dev;
10484 struct intel_encoder *intel_encoder =
10485 intel_attached_encoder(connector);
10486 struct drm_encoder *encoder = &intel_encoder->base;
10487 struct drm_crtc *crtc = encoder->crtc;
10488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10489 struct drm_atomic_state *state;
10490 struct drm_connector_state *connector_state;
10491 struct intel_crtc_state *crtc_state;
10492 int ret;
10493
10494 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10495 connector->base.id, connector->name,
10496 encoder->base.id, encoder->name);
10497
10498 if (old->load_detect_temp) {
10499 state = drm_atomic_state_alloc(dev);
10500 if (!state)
10501 goto fail;
10502
10503 state->acquire_ctx = ctx;
10504
10505 connector_state = drm_atomic_get_connector_state(state, connector);
10506 if (IS_ERR(connector_state))
10507 goto fail;
10508
10509 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10510 if (IS_ERR(crtc_state))
10511 goto fail;
10512
10513 connector_state->best_encoder = NULL;
10514 connector_state->crtc = NULL;
10515
10516 crtc_state->base.enable = crtc_state->base.active = false;
10517
10518 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10519 0, 0);
10520 if (ret)
10521 goto fail;
10522
10523 ret = drm_atomic_commit(state);
10524 if (ret)
10525 goto fail;
10526
10527 if (old->release_fb) {
10528 drm_framebuffer_unregister_private(old->release_fb);
10529 drm_framebuffer_unreference(old->release_fb);
10530 }
10531
10532 return;
10533 }
10534
10535 /* Switch crtc and encoder back off if necessary */
10536 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10537 connector->funcs->dpms(connector, old->dpms_mode);
10538
10539 return;
10540 fail:
10541 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10542 drm_atomic_state_free(state);
10543 }
10544
10545 static int i9xx_pll_refclk(struct drm_device *dev,
10546 const struct intel_crtc_state *pipe_config)
10547 {
10548 struct drm_i915_private *dev_priv = dev->dev_private;
10549 u32 dpll = pipe_config->dpll_hw_state.dpll;
10550
10551 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10552 return dev_priv->vbt.lvds_ssc_freq;
10553 else if (HAS_PCH_SPLIT(dev))
10554 return 120000;
10555 else if (!IS_GEN2(dev))
10556 return 96000;
10557 else
10558 return 48000;
10559 }
10560
10561 /* Returns the clock of the currently programmed mode of the given pipe. */
10562 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10563 struct intel_crtc_state *pipe_config)
10564 {
10565 struct drm_device *dev = crtc->base.dev;
10566 struct drm_i915_private *dev_priv = dev->dev_private;
10567 int pipe = pipe_config->cpu_transcoder;
10568 u32 dpll = pipe_config->dpll_hw_state.dpll;
10569 u32 fp;
10570 intel_clock_t clock;
10571 int port_clock;
10572 int refclk = i9xx_pll_refclk(dev, pipe_config);
10573
10574 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10575 fp = pipe_config->dpll_hw_state.fp0;
10576 else
10577 fp = pipe_config->dpll_hw_state.fp1;
10578
10579 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10580 if (IS_PINEVIEW(dev)) {
10581 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10582 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10583 } else {
10584 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10585 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10586 }
10587
10588 if (!IS_GEN2(dev)) {
10589 if (IS_PINEVIEW(dev))
10590 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10591 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10592 else
10593 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10594 DPLL_FPA01_P1_POST_DIV_SHIFT);
10595
10596 switch (dpll & DPLL_MODE_MASK) {
10597 case DPLLB_MODE_DAC_SERIAL:
10598 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10599 5 : 10;
10600 break;
10601 case DPLLB_MODE_LVDS:
10602 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10603 7 : 14;
10604 break;
10605 default:
10606 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10607 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10608 return;
10609 }
10610
10611 if (IS_PINEVIEW(dev))
10612 port_clock = pnv_calc_dpll_params(refclk, &clock);
10613 else
10614 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10615 } else {
10616 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10617 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10618
10619 if (is_lvds) {
10620 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10621 DPLL_FPA01_P1_POST_DIV_SHIFT);
10622
10623 if (lvds & LVDS_CLKB_POWER_UP)
10624 clock.p2 = 7;
10625 else
10626 clock.p2 = 14;
10627 } else {
10628 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10629 clock.p1 = 2;
10630 else {
10631 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10632 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10633 }
10634 if (dpll & PLL_P2_DIVIDE_BY_4)
10635 clock.p2 = 4;
10636 else
10637 clock.p2 = 2;
10638 }
10639
10640 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10641 }
10642
10643 /*
10644 * This value includes pixel_multiplier. We will use
10645 * port_clock to compute adjusted_mode.crtc_clock in the
10646 * encoder's get_config() function.
10647 */
10648 pipe_config->port_clock = port_clock;
10649 }
10650
10651 int intel_dotclock_calculate(int link_freq,
10652 const struct intel_link_m_n *m_n)
10653 {
10654 /*
10655 * The calculation for the data clock is:
10656 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10657 * But we want to avoid losing precison if possible, so:
10658 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10659 *
10660 * and the link clock is simpler:
10661 * link_clock = (m * link_clock) / n
10662 */
10663
10664 if (!m_n->link_n)
10665 return 0;
10666
10667 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10668 }
10669
10670 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10671 struct intel_crtc_state *pipe_config)
10672 {
10673 struct drm_device *dev = crtc->base.dev;
10674
10675 /* read out port_clock from the DPLL */
10676 i9xx_crtc_clock_get(crtc, pipe_config);
10677
10678 /*
10679 * This value does not include pixel_multiplier.
10680 * We will check that port_clock and adjusted_mode.crtc_clock
10681 * agree once we know their relationship in the encoder's
10682 * get_config() function.
10683 */
10684 pipe_config->base.adjusted_mode.crtc_clock =
10685 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10686 &pipe_config->fdi_m_n);
10687 }
10688
10689 /** Returns the currently programmed mode of the given pipe. */
10690 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10691 struct drm_crtc *crtc)
10692 {
10693 struct drm_i915_private *dev_priv = dev->dev_private;
10694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10695 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10696 struct drm_display_mode *mode;
10697 struct intel_crtc_state pipe_config;
10698 int htot = I915_READ(HTOTAL(cpu_transcoder));
10699 int hsync = I915_READ(HSYNC(cpu_transcoder));
10700 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10701 int vsync = I915_READ(VSYNC(cpu_transcoder));
10702 enum pipe pipe = intel_crtc->pipe;
10703
10704 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10705 if (!mode)
10706 return NULL;
10707
10708 /*
10709 * Construct a pipe_config sufficient for getting the clock info
10710 * back out of crtc_clock_get.
10711 *
10712 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10713 * to use a real value here instead.
10714 */
10715 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10716 pipe_config.pixel_multiplier = 1;
10717 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10718 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10719 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10720 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10721
10722 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10723 mode->hdisplay = (htot & 0xffff) + 1;
10724 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10725 mode->hsync_start = (hsync & 0xffff) + 1;
10726 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10727 mode->vdisplay = (vtot & 0xffff) + 1;
10728 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10729 mode->vsync_start = (vsync & 0xffff) + 1;
10730 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10731
10732 drm_mode_set_name(mode);
10733
10734 return mode;
10735 }
10736
10737 void intel_mark_busy(struct drm_device *dev)
10738 {
10739 struct drm_i915_private *dev_priv = dev->dev_private;
10740
10741 if (dev_priv->mm.busy)
10742 return;
10743
10744 intel_runtime_pm_get(dev_priv);
10745 i915_update_gfx_val(dev_priv);
10746 if (INTEL_INFO(dev)->gen >= 6)
10747 gen6_rps_busy(dev_priv);
10748 dev_priv->mm.busy = true;
10749 }
10750
10751 void intel_mark_idle(struct drm_device *dev)
10752 {
10753 struct drm_i915_private *dev_priv = dev->dev_private;
10754
10755 if (!dev_priv->mm.busy)
10756 return;
10757
10758 dev_priv->mm.busy = false;
10759
10760 if (INTEL_INFO(dev)->gen >= 6)
10761 gen6_rps_idle(dev->dev_private);
10762
10763 intel_runtime_pm_put(dev_priv);
10764 }
10765
10766 static void intel_crtc_destroy(struct drm_crtc *crtc)
10767 {
10768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10769 struct drm_device *dev = crtc->dev;
10770 struct intel_unpin_work *work;
10771
10772 spin_lock_irq(&dev->event_lock);
10773 work = intel_crtc->unpin_work;
10774 intel_crtc->unpin_work = NULL;
10775 spin_unlock_irq(&dev->event_lock);
10776
10777 if (work) {
10778 cancel_work_sync(&work->work);
10779 kfree(work);
10780 }
10781
10782 drm_crtc_cleanup(crtc);
10783
10784 kfree(intel_crtc);
10785 }
10786
10787 static void intel_unpin_work_fn(struct work_struct *__work)
10788 {
10789 struct intel_unpin_work *work =
10790 container_of(__work, struct intel_unpin_work, work);
10791 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10792 struct drm_device *dev = crtc->base.dev;
10793 struct drm_plane *primary = crtc->base.primary;
10794
10795 mutex_lock(&dev->struct_mutex);
10796 intel_unpin_fb_obj(work->old_fb, primary->state);
10797 drm_gem_object_unreference(&work->pending_flip_obj->base);
10798
10799 if (work->flip_queued_req)
10800 i915_gem_request_assign(&work->flip_queued_req, NULL);
10801 mutex_unlock(&dev->struct_mutex);
10802
10803 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10804 drm_framebuffer_unreference(work->old_fb);
10805
10806 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10807 atomic_dec(&crtc->unpin_work_count);
10808
10809 kfree(work);
10810 }
10811
10812 static void do_intel_finish_page_flip(struct drm_device *dev,
10813 struct drm_crtc *crtc)
10814 {
10815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10816 struct intel_unpin_work *work;
10817 unsigned long flags;
10818
10819 /* Ignore early vblank irqs */
10820 if (intel_crtc == NULL)
10821 return;
10822
10823 /*
10824 * This is called both by irq handlers and the reset code (to complete
10825 * lost pageflips) so needs the full irqsave spinlocks.
10826 */
10827 spin_lock_irqsave(&dev->event_lock, flags);
10828 work = intel_crtc->unpin_work;
10829
10830 /* Ensure we don't miss a work->pending update ... */
10831 smp_rmb();
10832
10833 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10834 spin_unlock_irqrestore(&dev->event_lock, flags);
10835 return;
10836 }
10837
10838 page_flip_completed(intel_crtc);
10839
10840 spin_unlock_irqrestore(&dev->event_lock, flags);
10841 }
10842
10843 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10844 {
10845 struct drm_i915_private *dev_priv = dev->dev_private;
10846 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10847
10848 do_intel_finish_page_flip(dev, crtc);
10849 }
10850
10851 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10852 {
10853 struct drm_i915_private *dev_priv = dev->dev_private;
10854 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10855
10856 do_intel_finish_page_flip(dev, crtc);
10857 }
10858
10859 /* Is 'a' after or equal to 'b'? */
10860 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10861 {
10862 return !((a - b) & 0x80000000);
10863 }
10864
10865 static bool page_flip_finished(struct intel_crtc *crtc)
10866 {
10867 struct drm_device *dev = crtc->base.dev;
10868 struct drm_i915_private *dev_priv = dev->dev_private;
10869
10870 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10871 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10872 return true;
10873
10874 /*
10875 * The relevant registers doen't exist on pre-ctg.
10876 * As the flip done interrupt doesn't trigger for mmio
10877 * flips on gmch platforms, a flip count check isn't
10878 * really needed there. But since ctg has the registers,
10879 * include it in the check anyway.
10880 */
10881 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10882 return true;
10883
10884 /*
10885 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10886 * used the same base address. In that case the mmio flip might
10887 * have completed, but the CS hasn't even executed the flip yet.
10888 *
10889 * A flip count check isn't enough as the CS might have updated
10890 * the base address just after start of vblank, but before we
10891 * managed to process the interrupt. This means we'd complete the
10892 * CS flip too soon.
10893 *
10894 * Combining both checks should get us a good enough result. It may
10895 * still happen that the CS flip has been executed, but has not
10896 * yet actually completed. But in case the base address is the same
10897 * anyway, we don't really care.
10898 */
10899 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10900 crtc->unpin_work->gtt_offset &&
10901 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10902 crtc->unpin_work->flip_count);
10903 }
10904
10905 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10906 {
10907 struct drm_i915_private *dev_priv = dev->dev_private;
10908 struct intel_crtc *intel_crtc =
10909 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10910 unsigned long flags;
10911
10912
10913 /*
10914 * This is called both by irq handlers and the reset code (to complete
10915 * lost pageflips) so needs the full irqsave spinlocks.
10916 *
10917 * NB: An MMIO update of the plane base pointer will also
10918 * generate a page-flip completion irq, i.e. every modeset
10919 * is also accompanied by a spurious intel_prepare_page_flip().
10920 */
10921 spin_lock_irqsave(&dev->event_lock, flags);
10922 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10923 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10924 spin_unlock_irqrestore(&dev->event_lock, flags);
10925 }
10926
10927 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10928 {
10929 /* Ensure that the work item is consistent when activating it ... */
10930 smp_wmb();
10931 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10932 /* and that it is marked active as soon as the irq could fire. */
10933 smp_wmb();
10934 }
10935
10936 static int intel_gen2_queue_flip(struct drm_device *dev,
10937 struct drm_crtc *crtc,
10938 struct drm_framebuffer *fb,
10939 struct drm_i915_gem_object *obj,
10940 struct drm_i915_gem_request *req,
10941 uint32_t flags)
10942 {
10943 struct intel_engine_cs *ring = req->ring;
10944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10945 u32 flip_mask;
10946 int ret;
10947
10948 ret = intel_ring_begin(req, 6);
10949 if (ret)
10950 return ret;
10951
10952 /* Can't queue multiple flips, so wait for the previous
10953 * one to finish before executing the next.
10954 */
10955 if (intel_crtc->plane)
10956 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10957 else
10958 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10959 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10960 intel_ring_emit(ring, MI_NOOP);
10961 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10962 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10963 intel_ring_emit(ring, fb->pitches[0]);
10964 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10965 intel_ring_emit(ring, 0); /* aux display base address, unused */
10966
10967 intel_mark_page_flip_active(intel_crtc->unpin_work);
10968 return 0;
10969 }
10970
10971 static int intel_gen3_queue_flip(struct drm_device *dev,
10972 struct drm_crtc *crtc,
10973 struct drm_framebuffer *fb,
10974 struct drm_i915_gem_object *obj,
10975 struct drm_i915_gem_request *req,
10976 uint32_t flags)
10977 {
10978 struct intel_engine_cs *ring = req->ring;
10979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10980 u32 flip_mask;
10981 int ret;
10982
10983 ret = intel_ring_begin(req, 6);
10984 if (ret)
10985 return ret;
10986
10987 if (intel_crtc->plane)
10988 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10989 else
10990 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10991 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10992 intel_ring_emit(ring, MI_NOOP);
10993 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10994 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10995 intel_ring_emit(ring, fb->pitches[0]);
10996 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10997 intel_ring_emit(ring, MI_NOOP);
10998
10999 intel_mark_page_flip_active(intel_crtc->unpin_work);
11000 return 0;
11001 }
11002
11003 static int intel_gen4_queue_flip(struct drm_device *dev,
11004 struct drm_crtc *crtc,
11005 struct drm_framebuffer *fb,
11006 struct drm_i915_gem_object *obj,
11007 struct drm_i915_gem_request *req,
11008 uint32_t flags)
11009 {
11010 struct intel_engine_cs *ring = req->ring;
11011 struct drm_i915_private *dev_priv = dev->dev_private;
11012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11013 uint32_t pf, pipesrc;
11014 int ret;
11015
11016 ret = intel_ring_begin(req, 4);
11017 if (ret)
11018 return ret;
11019
11020 /* i965+ uses the linear or tiled offsets from the
11021 * Display Registers (which do not change across a page-flip)
11022 * so we need only reprogram the base address.
11023 */
11024 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11025 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11026 intel_ring_emit(ring, fb->pitches[0]);
11027 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11028 obj->tiling_mode);
11029
11030 /* XXX Enabling the panel-fitter across page-flip is so far
11031 * untested on non-native modes, so ignore it for now.
11032 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11033 */
11034 pf = 0;
11035 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11036 intel_ring_emit(ring, pf | pipesrc);
11037
11038 intel_mark_page_flip_active(intel_crtc->unpin_work);
11039 return 0;
11040 }
11041
11042 static int intel_gen6_queue_flip(struct drm_device *dev,
11043 struct drm_crtc *crtc,
11044 struct drm_framebuffer *fb,
11045 struct drm_i915_gem_object *obj,
11046 struct drm_i915_gem_request *req,
11047 uint32_t flags)
11048 {
11049 struct intel_engine_cs *ring = req->ring;
11050 struct drm_i915_private *dev_priv = dev->dev_private;
11051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11052 uint32_t pf, pipesrc;
11053 int ret;
11054
11055 ret = intel_ring_begin(req, 4);
11056 if (ret)
11057 return ret;
11058
11059 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11060 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11061 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11062 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11063
11064 /* Contrary to the suggestions in the documentation,
11065 * "Enable Panel Fitter" does not seem to be required when page
11066 * flipping with a non-native mode, and worse causes a normal
11067 * modeset to fail.
11068 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11069 */
11070 pf = 0;
11071 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11072 intel_ring_emit(ring, pf | pipesrc);
11073
11074 intel_mark_page_flip_active(intel_crtc->unpin_work);
11075 return 0;
11076 }
11077
11078 static int intel_gen7_queue_flip(struct drm_device *dev,
11079 struct drm_crtc *crtc,
11080 struct drm_framebuffer *fb,
11081 struct drm_i915_gem_object *obj,
11082 struct drm_i915_gem_request *req,
11083 uint32_t flags)
11084 {
11085 struct intel_engine_cs *ring = req->ring;
11086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11087 uint32_t plane_bit = 0;
11088 int len, ret;
11089
11090 switch (intel_crtc->plane) {
11091 case PLANE_A:
11092 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11093 break;
11094 case PLANE_B:
11095 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11096 break;
11097 case PLANE_C:
11098 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11099 break;
11100 default:
11101 WARN_ONCE(1, "unknown plane in flip command\n");
11102 return -ENODEV;
11103 }
11104
11105 len = 4;
11106 if (ring->id == RCS) {
11107 len += 6;
11108 /*
11109 * On Gen 8, SRM is now taking an extra dword to accommodate
11110 * 48bits addresses, and we need a NOOP for the batch size to
11111 * stay even.
11112 */
11113 if (IS_GEN8(dev))
11114 len += 2;
11115 }
11116
11117 /*
11118 * BSpec MI_DISPLAY_FLIP for IVB:
11119 * "The full packet must be contained within the same cache line."
11120 *
11121 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11122 * cacheline, if we ever start emitting more commands before
11123 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11124 * then do the cacheline alignment, and finally emit the
11125 * MI_DISPLAY_FLIP.
11126 */
11127 ret = intel_ring_cacheline_align(req);
11128 if (ret)
11129 return ret;
11130
11131 ret = intel_ring_begin(req, len);
11132 if (ret)
11133 return ret;
11134
11135 /* Unmask the flip-done completion message. Note that the bspec says that
11136 * we should do this for both the BCS and RCS, and that we must not unmask
11137 * more than one flip event at any time (or ensure that one flip message
11138 * can be sent by waiting for flip-done prior to queueing new flips).
11139 * Experimentation says that BCS works despite DERRMR masking all
11140 * flip-done completion events and that unmasking all planes at once
11141 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11142 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11143 */
11144 if (ring->id == RCS) {
11145 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11146 intel_ring_emit_reg(ring, DERRMR);
11147 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11148 DERRMR_PIPEB_PRI_FLIP_DONE |
11149 DERRMR_PIPEC_PRI_FLIP_DONE));
11150 if (IS_GEN8(dev))
11151 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11152 MI_SRM_LRM_GLOBAL_GTT);
11153 else
11154 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11155 MI_SRM_LRM_GLOBAL_GTT);
11156 intel_ring_emit_reg(ring, DERRMR);
11157 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11158 if (IS_GEN8(dev)) {
11159 intel_ring_emit(ring, 0);
11160 intel_ring_emit(ring, MI_NOOP);
11161 }
11162 }
11163
11164 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11165 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11166 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11167 intel_ring_emit(ring, (MI_NOOP));
11168
11169 intel_mark_page_flip_active(intel_crtc->unpin_work);
11170 return 0;
11171 }
11172
11173 static bool use_mmio_flip(struct intel_engine_cs *ring,
11174 struct drm_i915_gem_object *obj)
11175 {
11176 /*
11177 * This is not being used for older platforms, because
11178 * non-availability of flip done interrupt forces us to use
11179 * CS flips. Older platforms derive flip done using some clever
11180 * tricks involving the flip_pending status bits and vblank irqs.
11181 * So using MMIO flips there would disrupt this mechanism.
11182 */
11183
11184 if (ring == NULL)
11185 return true;
11186
11187 if (INTEL_INFO(ring->dev)->gen < 5)
11188 return false;
11189
11190 if (i915.use_mmio_flip < 0)
11191 return false;
11192 else if (i915.use_mmio_flip > 0)
11193 return true;
11194 else if (i915.enable_execlists)
11195 return true;
11196 else
11197 return ring != i915_gem_request_get_ring(obj->last_write_req);
11198 }
11199
11200 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11201 unsigned int rotation,
11202 struct intel_unpin_work *work)
11203 {
11204 struct drm_device *dev = intel_crtc->base.dev;
11205 struct drm_i915_private *dev_priv = dev->dev_private;
11206 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11207 const enum pipe pipe = intel_crtc->pipe;
11208 u32 ctl, stride, tile_height;
11209
11210 ctl = I915_READ(PLANE_CTL(pipe, 0));
11211 ctl &= ~PLANE_CTL_TILED_MASK;
11212 switch (fb->modifier[0]) {
11213 case DRM_FORMAT_MOD_NONE:
11214 break;
11215 case I915_FORMAT_MOD_X_TILED:
11216 ctl |= PLANE_CTL_TILED_X;
11217 break;
11218 case I915_FORMAT_MOD_Y_TILED:
11219 ctl |= PLANE_CTL_TILED_Y;
11220 break;
11221 case I915_FORMAT_MOD_Yf_TILED:
11222 ctl |= PLANE_CTL_TILED_YF;
11223 break;
11224 default:
11225 MISSING_CASE(fb->modifier[0]);
11226 }
11227
11228 /*
11229 * The stride is either expressed as a multiple of 64 bytes chunks for
11230 * linear buffers or in number of tiles for tiled buffers.
11231 */
11232 if (intel_rotation_90_or_270(rotation)) {
11233 /* stride = Surface height in tiles */
11234 tile_height = intel_tile_height(dev, fb->pixel_format,
11235 fb->modifier[0], 0);
11236 stride = DIV_ROUND_UP(fb->height, tile_height);
11237 } else {
11238 stride = fb->pitches[0] /
11239 intel_fb_stride_alignment(dev, fb->modifier[0],
11240 fb->pixel_format);
11241 }
11242
11243 /*
11244 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11245 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11246 */
11247 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11248 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11249
11250 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11251 POSTING_READ(PLANE_SURF(pipe, 0));
11252 }
11253
11254 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11255 struct intel_unpin_work *work)
11256 {
11257 struct drm_device *dev = intel_crtc->base.dev;
11258 struct drm_i915_private *dev_priv = dev->dev_private;
11259 struct intel_framebuffer *intel_fb =
11260 to_intel_framebuffer(intel_crtc->base.primary->fb);
11261 struct drm_i915_gem_object *obj = intel_fb->obj;
11262 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11263 u32 dspcntr;
11264
11265 dspcntr = I915_READ(reg);
11266
11267 if (obj->tiling_mode != I915_TILING_NONE)
11268 dspcntr |= DISPPLANE_TILED;
11269 else
11270 dspcntr &= ~DISPPLANE_TILED;
11271
11272 I915_WRITE(reg, dspcntr);
11273
11274 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11275 POSTING_READ(DSPSURF(intel_crtc->plane));
11276 }
11277
11278 /*
11279 * XXX: This is the temporary way to update the plane registers until we get
11280 * around to using the usual plane update functions for MMIO flips
11281 */
11282 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11283 {
11284 struct intel_crtc *crtc = mmio_flip->crtc;
11285 struct intel_unpin_work *work;
11286
11287 spin_lock_irq(&crtc->base.dev->event_lock);
11288 work = crtc->unpin_work;
11289 spin_unlock_irq(&crtc->base.dev->event_lock);
11290 if (work == NULL)
11291 return;
11292
11293 intel_mark_page_flip_active(work);
11294
11295 intel_pipe_update_start(crtc);
11296
11297 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11298 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11299 else
11300 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11301 ilk_do_mmio_flip(crtc, work);
11302
11303 intel_pipe_update_end(crtc);
11304 }
11305
11306 static void intel_mmio_flip_work_func(struct work_struct *work)
11307 {
11308 struct intel_mmio_flip *mmio_flip =
11309 container_of(work, struct intel_mmio_flip, work);
11310
11311 if (mmio_flip->req) {
11312 WARN_ON(__i915_wait_request(mmio_flip->req,
11313 mmio_flip->crtc->reset_counter,
11314 false, NULL,
11315 &mmio_flip->i915->rps.mmioflips));
11316 i915_gem_request_unreference__unlocked(mmio_flip->req);
11317 }
11318
11319 intel_do_mmio_flip(mmio_flip);
11320 kfree(mmio_flip);
11321 }
11322
11323 static int intel_queue_mmio_flip(struct drm_device *dev,
11324 struct drm_crtc *crtc,
11325 struct drm_i915_gem_object *obj)
11326 {
11327 struct intel_mmio_flip *mmio_flip;
11328
11329 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11330 if (mmio_flip == NULL)
11331 return -ENOMEM;
11332
11333 mmio_flip->i915 = to_i915(dev);
11334 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11335 mmio_flip->crtc = to_intel_crtc(crtc);
11336 mmio_flip->rotation = crtc->primary->state->rotation;
11337
11338 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11339 schedule_work(&mmio_flip->work);
11340
11341 return 0;
11342 }
11343
11344 static int intel_default_queue_flip(struct drm_device *dev,
11345 struct drm_crtc *crtc,
11346 struct drm_framebuffer *fb,
11347 struct drm_i915_gem_object *obj,
11348 struct drm_i915_gem_request *req,
11349 uint32_t flags)
11350 {
11351 return -ENODEV;
11352 }
11353
11354 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11355 struct drm_crtc *crtc)
11356 {
11357 struct drm_i915_private *dev_priv = dev->dev_private;
11358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11359 struct intel_unpin_work *work = intel_crtc->unpin_work;
11360 u32 addr;
11361
11362 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11363 return true;
11364
11365 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11366 return false;
11367
11368 if (!work->enable_stall_check)
11369 return false;
11370
11371 if (work->flip_ready_vblank == 0) {
11372 if (work->flip_queued_req &&
11373 !i915_gem_request_completed(work->flip_queued_req, true))
11374 return false;
11375
11376 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11377 }
11378
11379 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11380 return false;
11381
11382 /* Potential stall - if we see that the flip has happened,
11383 * assume a missed interrupt. */
11384 if (INTEL_INFO(dev)->gen >= 4)
11385 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11386 else
11387 addr = I915_READ(DSPADDR(intel_crtc->plane));
11388
11389 /* There is a potential issue here with a false positive after a flip
11390 * to the same address. We could address this by checking for a
11391 * non-incrementing frame counter.
11392 */
11393 return addr == work->gtt_offset;
11394 }
11395
11396 void intel_check_page_flip(struct drm_device *dev, int pipe)
11397 {
11398 struct drm_i915_private *dev_priv = dev->dev_private;
11399 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11401 struct intel_unpin_work *work;
11402
11403 WARN_ON(!in_interrupt());
11404
11405 if (crtc == NULL)
11406 return;
11407
11408 spin_lock(&dev->event_lock);
11409 work = intel_crtc->unpin_work;
11410 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11411 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11412 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11413 page_flip_completed(intel_crtc);
11414 work = NULL;
11415 }
11416 if (work != NULL &&
11417 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11418 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11419 spin_unlock(&dev->event_lock);
11420 }
11421
11422 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11423 struct drm_framebuffer *fb,
11424 struct drm_pending_vblank_event *event,
11425 uint32_t page_flip_flags)
11426 {
11427 struct drm_device *dev = crtc->dev;
11428 struct drm_i915_private *dev_priv = dev->dev_private;
11429 struct drm_framebuffer *old_fb = crtc->primary->fb;
11430 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11432 struct drm_plane *primary = crtc->primary;
11433 enum pipe pipe = intel_crtc->pipe;
11434 struct intel_unpin_work *work;
11435 struct intel_engine_cs *ring;
11436 bool mmio_flip;
11437 struct drm_i915_gem_request *request = NULL;
11438 int ret;
11439
11440 /*
11441 * drm_mode_page_flip_ioctl() should already catch this, but double
11442 * check to be safe. In the future we may enable pageflipping from
11443 * a disabled primary plane.
11444 */
11445 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11446 return -EBUSY;
11447
11448 /* Can't change pixel format via MI display flips. */
11449 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11450 return -EINVAL;
11451
11452 /*
11453 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11454 * Note that pitch changes could also affect these register.
11455 */
11456 if (INTEL_INFO(dev)->gen > 3 &&
11457 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11458 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11459 return -EINVAL;
11460
11461 if (i915_terminally_wedged(&dev_priv->gpu_error))
11462 goto out_hang;
11463
11464 work = kzalloc(sizeof(*work), GFP_KERNEL);
11465 if (work == NULL)
11466 return -ENOMEM;
11467
11468 work->event = event;
11469 work->crtc = crtc;
11470 work->old_fb = old_fb;
11471 INIT_WORK(&work->work, intel_unpin_work_fn);
11472
11473 ret = drm_crtc_vblank_get(crtc);
11474 if (ret)
11475 goto free_work;
11476
11477 /* We borrow the event spin lock for protecting unpin_work */
11478 spin_lock_irq(&dev->event_lock);
11479 if (intel_crtc->unpin_work) {
11480 /* Before declaring the flip queue wedged, check if
11481 * the hardware completed the operation behind our backs.
11482 */
11483 if (__intel_pageflip_stall_check(dev, crtc)) {
11484 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11485 page_flip_completed(intel_crtc);
11486 } else {
11487 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11488 spin_unlock_irq(&dev->event_lock);
11489
11490 drm_crtc_vblank_put(crtc);
11491 kfree(work);
11492 return -EBUSY;
11493 }
11494 }
11495 intel_crtc->unpin_work = work;
11496 spin_unlock_irq(&dev->event_lock);
11497
11498 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11499 flush_workqueue(dev_priv->wq);
11500
11501 /* Reference the objects for the scheduled work. */
11502 drm_framebuffer_reference(work->old_fb);
11503 drm_gem_object_reference(&obj->base);
11504
11505 crtc->primary->fb = fb;
11506 update_state_fb(crtc->primary);
11507
11508 work->pending_flip_obj = obj;
11509
11510 ret = i915_mutex_lock_interruptible(dev);
11511 if (ret)
11512 goto cleanup;
11513
11514 atomic_inc(&intel_crtc->unpin_work_count);
11515 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11516
11517 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11518 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11519
11520 if (IS_VALLEYVIEW(dev)) {
11521 ring = &dev_priv->ring[BCS];
11522 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11523 /* vlv: DISPLAY_FLIP fails to change tiling */
11524 ring = NULL;
11525 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11526 ring = &dev_priv->ring[BCS];
11527 } else if (INTEL_INFO(dev)->gen >= 7) {
11528 ring = i915_gem_request_get_ring(obj->last_write_req);
11529 if (ring == NULL || ring->id != RCS)
11530 ring = &dev_priv->ring[BCS];
11531 } else {
11532 ring = &dev_priv->ring[RCS];
11533 }
11534
11535 mmio_flip = use_mmio_flip(ring, obj);
11536
11537 /* When using CS flips, we want to emit semaphores between rings.
11538 * However, when using mmio flips we will create a task to do the
11539 * synchronisation, so all we want here is to pin the framebuffer
11540 * into the display plane and skip any waits.
11541 */
11542 if (!mmio_flip) {
11543 ret = i915_gem_object_sync(obj, ring, &request);
11544 if (ret)
11545 goto cleanup_pending;
11546 }
11547
11548 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11549 crtc->primary->state);
11550 if (ret)
11551 goto cleanup_pending;
11552
11553 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11554 obj, 0);
11555 work->gtt_offset += intel_crtc->dspaddr_offset;
11556
11557 if (mmio_flip) {
11558 ret = intel_queue_mmio_flip(dev, crtc, obj);
11559 if (ret)
11560 goto cleanup_unpin;
11561
11562 i915_gem_request_assign(&work->flip_queued_req,
11563 obj->last_write_req);
11564 } else {
11565 if (!request) {
11566 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11567 if (ret)
11568 goto cleanup_unpin;
11569 }
11570
11571 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11572 page_flip_flags);
11573 if (ret)
11574 goto cleanup_unpin;
11575
11576 i915_gem_request_assign(&work->flip_queued_req, request);
11577 }
11578
11579 if (request)
11580 i915_add_request_no_flush(request);
11581
11582 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11583 work->enable_stall_check = true;
11584
11585 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11586 to_intel_plane(primary)->frontbuffer_bit);
11587 mutex_unlock(&dev->struct_mutex);
11588
11589 intel_fbc_disable_crtc(intel_crtc);
11590 intel_frontbuffer_flip_prepare(dev,
11591 to_intel_plane(primary)->frontbuffer_bit);
11592
11593 trace_i915_flip_request(intel_crtc->plane, obj);
11594
11595 return 0;
11596
11597 cleanup_unpin:
11598 intel_unpin_fb_obj(fb, crtc->primary->state);
11599 cleanup_pending:
11600 if (request)
11601 i915_gem_request_cancel(request);
11602 atomic_dec(&intel_crtc->unpin_work_count);
11603 mutex_unlock(&dev->struct_mutex);
11604 cleanup:
11605 crtc->primary->fb = old_fb;
11606 update_state_fb(crtc->primary);
11607
11608 drm_gem_object_unreference_unlocked(&obj->base);
11609 drm_framebuffer_unreference(work->old_fb);
11610
11611 spin_lock_irq(&dev->event_lock);
11612 intel_crtc->unpin_work = NULL;
11613 spin_unlock_irq(&dev->event_lock);
11614
11615 drm_crtc_vblank_put(crtc);
11616 free_work:
11617 kfree(work);
11618
11619 if (ret == -EIO) {
11620 struct drm_atomic_state *state;
11621 struct drm_plane_state *plane_state;
11622
11623 out_hang:
11624 state = drm_atomic_state_alloc(dev);
11625 if (!state)
11626 return -ENOMEM;
11627 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11628
11629 retry:
11630 plane_state = drm_atomic_get_plane_state(state, primary);
11631 ret = PTR_ERR_OR_ZERO(plane_state);
11632 if (!ret) {
11633 drm_atomic_set_fb_for_plane(plane_state, fb);
11634
11635 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11636 if (!ret)
11637 ret = drm_atomic_commit(state);
11638 }
11639
11640 if (ret == -EDEADLK) {
11641 drm_modeset_backoff(state->acquire_ctx);
11642 drm_atomic_state_clear(state);
11643 goto retry;
11644 }
11645
11646 if (ret)
11647 drm_atomic_state_free(state);
11648
11649 if (ret == 0 && event) {
11650 spin_lock_irq(&dev->event_lock);
11651 drm_send_vblank_event(dev, pipe, event);
11652 spin_unlock_irq(&dev->event_lock);
11653 }
11654 }
11655 return ret;
11656 }
11657
11658
11659 /**
11660 * intel_wm_need_update - Check whether watermarks need updating
11661 * @plane: drm plane
11662 * @state: new plane state
11663 *
11664 * Check current plane state versus the new one to determine whether
11665 * watermarks need to be recalculated.
11666 *
11667 * Returns true or false.
11668 */
11669 static bool intel_wm_need_update(struct drm_plane *plane,
11670 struct drm_plane_state *state)
11671 {
11672 struct intel_plane_state *new = to_intel_plane_state(state);
11673 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11674
11675 /* Update watermarks on tiling or size changes. */
11676 if (!plane->state->fb || !state->fb ||
11677 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11678 plane->state->rotation != state->rotation ||
11679 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11680 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11681 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11682 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11683 return true;
11684
11685 return false;
11686 }
11687
11688 static bool needs_scaling(struct intel_plane_state *state)
11689 {
11690 int src_w = drm_rect_width(&state->src) >> 16;
11691 int src_h = drm_rect_height(&state->src) >> 16;
11692 int dst_w = drm_rect_width(&state->dst);
11693 int dst_h = drm_rect_height(&state->dst);
11694
11695 return (src_w != dst_w || src_h != dst_h);
11696 }
11697
11698 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11699 struct drm_plane_state *plane_state)
11700 {
11701 struct drm_crtc *crtc = crtc_state->crtc;
11702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11703 struct drm_plane *plane = plane_state->plane;
11704 struct drm_device *dev = crtc->dev;
11705 struct drm_i915_private *dev_priv = dev->dev_private;
11706 struct intel_plane_state *old_plane_state =
11707 to_intel_plane_state(plane->state);
11708 int idx = intel_crtc->base.base.id, ret;
11709 int i = drm_plane_index(plane);
11710 bool mode_changed = needs_modeset(crtc_state);
11711 bool was_crtc_enabled = crtc->state->active;
11712 bool is_crtc_enabled = crtc_state->active;
11713 bool turn_off, turn_on, visible, was_visible;
11714 struct drm_framebuffer *fb = plane_state->fb;
11715
11716 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11717 plane->type != DRM_PLANE_TYPE_CURSOR) {
11718 ret = skl_update_scaler_plane(
11719 to_intel_crtc_state(crtc_state),
11720 to_intel_plane_state(plane_state));
11721 if (ret)
11722 return ret;
11723 }
11724
11725 was_visible = old_plane_state->visible;
11726 visible = to_intel_plane_state(plane_state)->visible;
11727
11728 if (!was_crtc_enabled && WARN_ON(was_visible))
11729 was_visible = false;
11730
11731 if (!is_crtc_enabled && WARN_ON(visible))
11732 visible = false;
11733
11734 if (!was_visible && !visible)
11735 return 0;
11736
11737 turn_off = was_visible && (!visible || mode_changed);
11738 turn_on = visible && (!was_visible || mode_changed);
11739
11740 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11741 plane->base.id, fb ? fb->base.id : -1);
11742
11743 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11744 plane->base.id, was_visible, visible,
11745 turn_off, turn_on, mode_changed);
11746
11747 if (turn_on) {
11748 intel_crtc->atomic.update_wm_pre = true;
11749 /* must disable cxsr around plane enable/disable */
11750 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11751 intel_crtc->atomic.disable_cxsr = true;
11752 /* to potentially re-enable cxsr */
11753 intel_crtc->atomic.wait_vblank = true;
11754 intel_crtc->atomic.update_wm_post = true;
11755 }
11756 } else if (turn_off) {
11757 intel_crtc->atomic.update_wm_post = true;
11758 /* must disable cxsr around plane enable/disable */
11759 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11760 if (is_crtc_enabled)
11761 intel_crtc->atomic.wait_vblank = true;
11762 intel_crtc->atomic.disable_cxsr = true;
11763 }
11764 } else if (intel_wm_need_update(plane, plane_state)) {
11765 intel_crtc->atomic.update_wm_pre = true;
11766 }
11767
11768 if (visible || was_visible)
11769 intel_crtc->atomic.fb_bits |=
11770 to_intel_plane(plane)->frontbuffer_bit;
11771
11772 switch (plane->type) {
11773 case DRM_PLANE_TYPE_PRIMARY:
11774 intel_crtc->atomic.pre_disable_primary = turn_off;
11775 intel_crtc->atomic.post_enable_primary = turn_on;
11776
11777 if (turn_off) {
11778 /*
11779 * FIXME: Actually if we will still have any other
11780 * plane enabled on the pipe we could let IPS enabled
11781 * still, but for now lets consider that when we make
11782 * primary invisible by setting DSPCNTR to 0 on
11783 * update_primary_plane function IPS needs to be
11784 * disable.
11785 */
11786 intel_crtc->atomic.disable_ips = true;
11787
11788 intel_crtc->atomic.disable_fbc = true;
11789 }
11790
11791 /*
11792 * FBC does not work on some platforms for rotated
11793 * planes, so disable it when rotation is not 0 and
11794 * update it when rotation is set back to 0.
11795 *
11796 * FIXME: This is redundant with the fbc update done in
11797 * the primary plane enable function except that that
11798 * one is done too late. We eventually need to unify
11799 * this.
11800 */
11801
11802 if (visible &&
11803 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11804 dev_priv->fbc.crtc == intel_crtc &&
11805 plane_state->rotation != BIT(DRM_ROTATE_0))
11806 intel_crtc->atomic.disable_fbc = true;
11807
11808 /*
11809 * BDW signals flip done immediately if the plane
11810 * is disabled, even if the plane enable is already
11811 * armed to occur at the next vblank :(
11812 */
11813 if (turn_on && IS_BROADWELL(dev))
11814 intel_crtc->atomic.wait_vblank = true;
11815
11816 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11817 break;
11818 case DRM_PLANE_TYPE_CURSOR:
11819 break;
11820 case DRM_PLANE_TYPE_OVERLAY:
11821 /*
11822 * WaCxSRDisabledForSpriteScaling:ivb
11823 *
11824 * cstate->update_wm was already set above, so this flag will
11825 * take effect when we commit and program watermarks.
11826 */
11827 if (IS_IVYBRIDGE(dev) &&
11828 needs_scaling(to_intel_plane_state(plane_state)) &&
11829 !needs_scaling(old_plane_state)) {
11830 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11831 } else if (turn_off && !mode_changed) {
11832 intel_crtc->atomic.wait_vblank = true;
11833 intel_crtc->atomic.update_sprite_watermarks |=
11834 1 << i;
11835 }
11836
11837 break;
11838 }
11839 return 0;
11840 }
11841
11842 static bool encoders_cloneable(const struct intel_encoder *a,
11843 const struct intel_encoder *b)
11844 {
11845 /* masks could be asymmetric, so check both ways */
11846 return a == b || (a->cloneable & (1 << b->type) &&
11847 b->cloneable & (1 << a->type));
11848 }
11849
11850 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11851 struct intel_crtc *crtc,
11852 struct intel_encoder *encoder)
11853 {
11854 struct intel_encoder *source_encoder;
11855 struct drm_connector *connector;
11856 struct drm_connector_state *connector_state;
11857 int i;
11858
11859 for_each_connector_in_state(state, connector, connector_state, i) {
11860 if (connector_state->crtc != &crtc->base)
11861 continue;
11862
11863 source_encoder =
11864 to_intel_encoder(connector_state->best_encoder);
11865 if (!encoders_cloneable(encoder, source_encoder))
11866 return false;
11867 }
11868
11869 return true;
11870 }
11871
11872 static bool check_encoder_cloning(struct drm_atomic_state *state,
11873 struct intel_crtc *crtc)
11874 {
11875 struct intel_encoder *encoder;
11876 struct drm_connector *connector;
11877 struct drm_connector_state *connector_state;
11878 int i;
11879
11880 for_each_connector_in_state(state, connector, connector_state, i) {
11881 if (connector_state->crtc != &crtc->base)
11882 continue;
11883
11884 encoder = to_intel_encoder(connector_state->best_encoder);
11885 if (!check_single_encoder_cloning(state, crtc, encoder))
11886 return false;
11887 }
11888
11889 return true;
11890 }
11891
11892 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11893 struct drm_crtc_state *crtc_state)
11894 {
11895 struct drm_device *dev = crtc->dev;
11896 struct drm_i915_private *dev_priv = dev->dev_private;
11897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11898 struct intel_crtc_state *pipe_config =
11899 to_intel_crtc_state(crtc_state);
11900 struct drm_atomic_state *state = crtc_state->state;
11901 int ret;
11902 bool mode_changed = needs_modeset(crtc_state);
11903
11904 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11905 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11906 return -EINVAL;
11907 }
11908
11909 if (mode_changed && !crtc_state->active)
11910 intel_crtc->atomic.update_wm_post = true;
11911
11912 if (mode_changed && crtc_state->enable &&
11913 dev_priv->display.crtc_compute_clock &&
11914 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11915 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11916 pipe_config);
11917 if (ret)
11918 return ret;
11919 }
11920
11921 ret = 0;
11922 if (dev_priv->display.compute_pipe_wm) {
11923 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11924 if (ret)
11925 return ret;
11926 }
11927
11928 if (INTEL_INFO(dev)->gen >= 9) {
11929 if (mode_changed)
11930 ret = skl_update_scaler_crtc(pipe_config);
11931
11932 if (!ret)
11933 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11934 pipe_config);
11935 }
11936
11937 return ret;
11938 }
11939
11940 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11941 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11942 .load_lut = intel_crtc_load_lut,
11943 .atomic_begin = intel_begin_crtc_commit,
11944 .atomic_flush = intel_finish_crtc_commit,
11945 .atomic_check = intel_crtc_atomic_check,
11946 };
11947
11948 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11949 {
11950 struct intel_connector *connector;
11951
11952 for_each_intel_connector(dev, connector) {
11953 if (connector->base.encoder) {
11954 connector->base.state->best_encoder =
11955 connector->base.encoder;
11956 connector->base.state->crtc =
11957 connector->base.encoder->crtc;
11958 } else {
11959 connector->base.state->best_encoder = NULL;
11960 connector->base.state->crtc = NULL;
11961 }
11962 }
11963 }
11964
11965 static void
11966 connected_sink_compute_bpp(struct intel_connector *connector,
11967 struct intel_crtc_state *pipe_config)
11968 {
11969 int bpp = pipe_config->pipe_bpp;
11970
11971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11972 connector->base.base.id,
11973 connector->base.name);
11974
11975 /* Don't use an invalid EDID bpc value */
11976 if (connector->base.display_info.bpc &&
11977 connector->base.display_info.bpc * 3 < bpp) {
11978 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11979 bpp, connector->base.display_info.bpc*3);
11980 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11981 }
11982
11983 /* Clamp bpp to 8 on screens without EDID 1.4 */
11984 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11985 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11986 bpp);
11987 pipe_config->pipe_bpp = 24;
11988 }
11989 }
11990
11991 static int
11992 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11993 struct intel_crtc_state *pipe_config)
11994 {
11995 struct drm_device *dev = crtc->base.dev;
11996 struct drm_atomic_state *state;
11997 struct drm_connector *connector;
11998 struct drm_connector_state *connector_state;
11999 int bpp, i;
12000
12001 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12002 bpp = 10*3;
12003 else if (INTEL_INFO(dev)->gen >= 5)
12004 bpp = 12*3;
12005 else
12006 bpp = 8*3;
12007
12008
12009 pipe_config->pipe_bpp = bpp;
12010
12011 state = pipe_config->base.state;
12012
12013 /* Clamp display bpp to EDID value */
12014 for_each_connector_in_state(state, connector, connector_state, i) {
12015 if (connector_state->crtc != &crtc->base)
12016 continue;
12017
12018 connected_sink_compute_bpp(to_intel_connector(connector),
12019 pipe_config);
12020 }
12021
12022 return bpp;
12023 }
12024
12025 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12026 {
12027 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12028 "type: 0x%x flags: 0x%x\n",
12029 mode->crtc_clock,
12030 mode->crtc_hdisplay, mode->crtc_hsync_start,
12031 mode->crtc_hsync_end, mode->crtc_htotal,
12032 mode->crtc_vdisplay, mode->crtc_vsync_start,
12033 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12034 }
12035
12036 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12037 struct intel_crtc_state *pipe_config,
12038 const char *context)
12039 {
12040 struct drm_device *dev = crtc->base.dev;
12041 struct drm_plane *plane;
12042 struct intel_plane *intel_plane;
12043 struct intel_plane_state *state;
12044 struct drm_framebuffer *fb;
12045
12046 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12047 context, pipe_config, pipe_name(crtc->pipe));
12048
12049 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12050 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12051 pipe_config->pipe_bpp, pipe_config->dither);
12052 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12053 pipe_config->has_pch_encoder,
12054 pipe_config->fdi_lanes,
12055 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12056 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12057 pipe_config->fdi_m_n.tu);
12058 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12059 pipe_config->has_dp_encoder,
12060 pipe_config->lane_count,
12061 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12062 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12063 pipe_config->dp_m_n.tu);
12064
12065 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12066 pipe_config->has_dp_encoder,
12067 pipe_config->lane_count,
12068 pipe_config->dp_m2_n2.gmch_m,
12069 pipe_config->dp_m2_n2.gmch_n,
12070 pipe_config->dp_m2_n2.link_m,
12071 pipe_config->dp_m2_n2.link_n,
12072 pipe_config->dp_m2_n2.tu);
12073
12074 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12075 pipe_config->has_audio,
12076 pipe_config->has_infoframe);
12077
12078 DRM_DEBUG_KMS("requested mode:\n");
12079 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12080 DRM_DEBUG_KMS("adjusted mode:\n");
12081 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12082 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12083 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12084 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12085 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12086 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12087 crtc->num_scalers,
12088 pipe_config->scaler_state.scaler_users,
12089 pipe_config->scaler_state.scaler_id);
12090 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12091 pipe_config->gmch_pfit.control,
12092 pipe_config->gmch_pfit.pgm_ratios,
12093 pipe_config->gmch_pfit.lvds_border_bits);
12094 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12095 pipe_config->pch_pfit.pos,
12096 pipe_config->pch_pfit.size,
12097 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12098 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12099 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12100
12101 if (IS_BROXTON(dev)) {
12102 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12103 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12104 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12105 pipe_config->ddi_pll_sel,
12106 pipe_config->dpll_hw_state.ebb0,
12107 pipe_config->dpll_hw_state.ebb4,
12108 pipe_config->dpll_hw_state.pll0,
12109 pipe_config->dpll_hw_state.pll1,
12110 pipe_config->dpll_hw_state.pll2,
12111 pipe_config->dpll_hw_state.pll3,
12112 pipe_config->dpll_hw_state.pll6,
12113 pipe_config->dpll_hw_state.pll8,
12114 pipe_config->dpll_hw_state.pll9,
12115 pipe_config->dpll_hw_state.pll10,
12116 pipe_config->dpll_hw_state.pcsdw12);
12117 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12118 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12119 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12120 pipe_config->ddi_pll_sel,
12121 pipe_config->dpll_hw_state.ctrl1,
12122 pipe_config->dpll_hw_state.cfgcr1,
12123 pipe_config->dpll_hw_state.cfgcr2);
12124 } else if (HAS_DDI(dev)) {
12125 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12126 pipe_config->ddi_pll_sel,
12127 pipe_config->dpll_hw_state.wrpll,
12128 pipe_config->dpll_hw_state.spll);
12129 } else {
12130 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12131 "fp0: 0x%x, fp1: 0x%x\n",
12132 pipe_config->dpll_hw_state.dpll,
12133 pipe_config->dpll_hw_state.dpll_md,
12134 pipe_config->dpll_hw_state.fp0,
12135 pipe_config->dpll_hw_state.fp1);
12136 }
12137
12138 DRM_DEBUG_KMS("planes on this crtc\n");
12139 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12140 intel_plane = to_intel_plane(plane);
12141 if (intel_plane->pipe != crtc->pipe)
12142 continue;
12143
12144 state = to_intel_plane_state(plane->state);
12145 fb = state->base.fb;
12146 if (!fb) {
12147 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12148 "disabled, scaler_id = %d\n",
12149 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12150 plane->base.id, intel_plane->pipe,
12151 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12152 drm_plane_index(plane), state->scaler_id);
12153 continue;
12154 }
12155
12156 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12157 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12158 plane->base.id, intel_plane->pipe,
12159 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12160 drm_plane_index(plane));
12161 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12162 fb->base.id, fb->width, fb->height, fb->pixel_format);
12163 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12164 state->scaler_id,
12165 state->src.x1 >> 16, state->src.y1 >> 16,
12166 drm_rect_width(&state->src) >> 16,
12167 drm_rect_height(&state->src) >> 16,
12168 state->dst.x1, state->dst.y1,
12169 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12170 }
12171 }
12172
12173 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12174 {
12175 struct drm_device *dev = state->dev;
12176 struct intel_encoder *encoder;
12177 struct drm_connector *connector;
12178 struct drm_connector_state *connector_state;
12179 unsigned int used_ports = 0;
12180 int i;
12181
12182 /*
12183 * Walk the connector list instead of the encoder
12184 * list to detect the problem on ddi platforms
12185 * where there's just one encoder per digital port.
12186 */
12187 for_each_connector_in_state(state, connector, connector_state, i) {
12188 if (!connector_state->best_encoder)
12189 continue;
12190
12191 encoder = to_intel_encoder(connector_state->best_encoder);
12192
12193 WARN_ON(!connector_state->crtc);
12194
12195 switch (encoder->type) {
12196 unsigned int port_mask;
12197 case INTEL_OUTPUT_UNKNOWN:
12198 if (WARN_ON(!HAS_DDI(dev)))
12199 break;
12200 case INTEL_OUTPUT_DISPLAYPORT:
12201 case INTEL_OUTPUT_HDMI:
12202 case INTEL_OUTPUT_EDP:
12203 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12204
12205 /* the same port mustn't appear more than once */
12206 if (used_ports & port_mask)
12207 return false;
12208
12209 used_ports |= port_mask;
12210 default:
12211 break;
12212 }
12213 }
12214
12215 return true;
12216 }
12217
12218 static void
12219 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12220 {
12221 struct drm_crtc_state tmp_state;
12222 struct intel_crtc_scaler_state scaler_state;
12223 struct intel_dpll_hw_state dpll_hw_state;
12224 enum intel_dpll_id shared_dpll;
12225 uint32_t ddi_pll_sel;
12226 bool force_thru;
12227
12228 /* FIXME: before the switch to atomic started, a new pipe_config was
12229 * kzalloc'd. Code that depends on any field being zero should be
12230 * fixed, so that the crtc_state can be safely duplicated. For now,
12231 * only fields that are know to not cause problems are preserved. */
12232
12233 tmp_state = crtc_state->base;
12234 scaler_state = crtc_state->scaler_state;
12235 shared_dpll = crtc_state->shared_dpll;
12236 dpll_hw_state = crtc_state->dpll_hw_state;
12237 ddi_pll_sel = crtc_state->ddi_pll_sel;
12238 force_thru = crtc_state->pch_pfit.force_thru;
12239
12240 memset(crtc_state, 0, sizeof *crtc_state);
12241
12242 crtc_state->base = tmp_state;
12243 crtc_state->scaler_state = scaler_state;
12244 crtc_state->shared_dpll = shared_dpll;
12245 crtc_state->dpll_hw_state = dpll_hw_state;
12246 crtc_state->ddi_pll_sel = ddi_pll_sel;
12247 crtc_state->pch_pfit.force_thru = force_thru;
12248 }
12249
12250 static int
12251 intel_modeset_pipe_config(struct drm_crtc *crtc,
12252 struct intel_crtc_state *pipe_config)
12253 {
12254 struct drm_atomic_state *state = pipe_config->base.state;
12255 struct intel_encoder *encoder;
12256 struct drm_connector *connector;
12257 struct drm_connector_state *connector_state;
12258 int base_bpp, ret = -EINVAL;
12259 int i;
12260 bool retry = true;
12261
12262 clear_intel_crtc_state(pipe_config);
12263
12264 pipe_config->cpu_transcoder =
12265 (enum transcoder) to_intel_crtc(crtc)->pipe;
12266
12267 /*
12268 * Sanitize sync polarity flags based on requested ones. If neither
12269 * positive or negative polarity is requested, treat this as meaning
12270 * negative polarity.
12271 */
12272 if (!(pipe_config->base.adjusted_mode.flags &
12273 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12274 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12275
12276 if (!(pipe_config->base.adjusted_mode.flags &
12277 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12278 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12279
12280 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12281 pipe_config);
12282 if (base_bpp < 0)
12283 goto fail;
12284
12285 /*
12286 * Determine the real pipe dimensions. Note that stereo modes can
12287 * increase the actual pipe size due to the frame doubling and
12288 * insertion of additional space for blanks between the frame. This
12289 * is stored in the crtc timings. We use the requested mode to do this
12290 * computation to clearly distinguish it from the adjusted mode, which
12291 * can be changed by the connectors in the below retry loop.
12292 */
12293 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12294 &pipe_config->pipe_src_w,
12295 &pipe_config->pipe_src_h);
12296
12297 encoder_retry:
12298 /* Ensure the port clock defaults are reset when retrying. */
12299 pipe_config->port_clock = 0;
12300 pipe_config->pixel_multiplier = 1;
12301
12302 /* Fill in default crtc timings, allow encoders to overwrite them. */
12303 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12304 CRTC_STEREO_DOUBLE);
12305
12306 /* Pass our mode to the connectors and the CRTC to give them a chance to
12307 * adjust it according to limitations or connector properties, and also
12308 * a chance to reject the mode entirely.
12309 */
12310 for_each_connector_in_state(state, connector, connector_state, i) {
12311 if (connector_state->crtc != crtc)
12312 continue;
12313
12314 encoder = to_intel_encoder(connector_state->best_encoder);
12315
12316 if (!(encoder->compute_config(encoder, pipe_config))) {
12317 DRM_DEBUG_KMS("Encoder config failure\n");
12318 goto fail;
12319 }
12320 }
12321
12322 /* Set default port clock if not overwritten by the encoder. Needs to be
12323 * done afterwards in case the encoder adjusts the mode. */
12324 if (!pipe_config->port_clock)
12325 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12326 * pipe_config->pixel_multiplier;
12327
12328 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12329 if (ret < 0) {
12330 DRM_DEBUG_KMS("CRTC fixup failed\n");
12331 goto fail;
12332 }
12333
12334 if (ret == RETRY) {
12335 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12336 ret = -EINVAL;
12337 goto fail;
12338 }
12339
12340 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12341 retry = false;
12342 goto encoder_retry;
12343 }
12344
12345 /* Dithering seems to not pass-through bits correctly when it should, so
12346 * only enable it on 6bpc panels. */
12347 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12348 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12349 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12350
12351 fail:
12352 return ret;
12353 }
12354
12355 static void
12356 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12357 {
12358 struct drm_crtc *crtc;
12359 struct drm_crtc_state *crtc_state;
12360 int i;
12361
12362 /* Double check state. */
12363 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12364 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12365
12366 /* Update hwmode for vblank functions */
12367 if (crtc->state->active)
12368 crtc->hwmode = crtc->state->adjusted_mode;
12369 else
12370 crtc->hwmode.crtc_clock = 0;
12371
12372 /*
12373 * Update legacy state to satisfy fbc code. This can
12374 * be removed when fbc uses the atomic state.
12375 */
12376 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12377 struct drm_plane_state *plane_state = crtc->primary->state;
12378
12379 crtc->primary->fb = plane_state->fb;
12380 crtc->x = plane_state->src_x >> 16;
12381 crtc->y = plane_state->src_y >> 16;
12382 }
12383 }
12384 }
12385
12386 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12387 {
12388 int diff;
12389
12390 if (clock1 == clock2)
12391 return true;
12392
12393 if (!clock1 || !clock2)
12394 return false;
12395
12396 diff = abs(clock1 - clock2);
12397
12398 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12399 return true;
12400
12401 return false;
12402 }
12403
12404 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12405 list_for_each_entry((intel_crtc), \
12406 &(dev)->mode_config.crtc_list, \
12407 base.head) \
12408 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12409
12410 static bool
12411 intel_compare_m_n(unsigned int m, unsigned int n,
12412 unsigned int m2, unsigned int n2,
12413 bool exact)
12414 {
12415 if (m == m2 && n == n2)
12416 return true;
12417
12418 if (exact || !m || !n || !m2 || !n2)
12419 return false;
12420
12421 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12422
12423 if (m > m2) {
12424 while (m > m2) {
12425 m2 <<= 1;
12426 n2 <<= 1;
12427 }
12428 } else if (m < m2) {
12429 while (m < m2) {
12430 m <<= 1;
12431 n <<= 1;
12432 }
12433 }
12434
12435 return m == m2 && n == n2;
12436 }
12437
12438 static bool
12439 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12440 struct intel_link_m_n *m2_n2,
12441 bool adjust)
12442 {
12443 if (m_n->tu == m2_n2->tu &&
12444 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12445 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12446 intel_compare_m_n(m_n->link_m, m_n->link_n,
12447 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12448 if (adjust)
12449 *m2_n2 = *m_n;
12450
12451 return true;
12452 }
12453
12454 return false;
12455 }
12456
12457 static bool
12458 intel_pipe_config_compare(struct drm_device *dev,
12459 struct intel_crtc_state *current_config,
12460 struct intel_crtc_state *pipe_config,
12461 bool adjust)
12462 {
12463 bool ret = true;
12464
12465 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12466 do { \
12467 if (!adjust) \
12468 DRM_ERROR(fmt, ##__VA_ARGS__); \
12469 else \
12470 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12471 } while (0)
12472
12473 #define PIPE_CONF_CHECK_X(name) \
12474 if (current_config->name != pipe_config->name) { \
12475 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12476 "(expected 0x%08x, found 0x%08x)\n", \
12477 current_config->name, \
12478 pipe_config->name); \
12479 ret = false; \
12480 }
12481
12482 #define PIPE_CONF_CHECK_I(name) \
12483 if (current_config->name != pipe_config->name) { \
12484 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12485 "(expected %i, found %i)\n", \
12486 current_config->name, \
12487 pipe_config->name); \
12488 ret = false; \
12489 }
12490
12491 #define PIPE_CONF_CHECK_M_N(name) \
12492 if (!intel_compare_link_m_n(&current_config->name, \
12493 &pipe_config->name,\
12494 adjust)) { \
12495 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12496 "(expected tu %i gmch %i/%i link %i/%i, " \
12497 "found tu %i, gmch %i/%i link %i/%i)\n", \
12498 current_config->name.tu, \
12499 current_config->name.gmch_m, \
12500 current_config->name.gmch_n, \
12501 current_config->name.link_m, \
12502 current_config->name.link_n, \
12503 pipe_config->name.tu, \
12504 pipe_config->name.gmch_m, \
12505 pipe_config->name.gmch_n, \
12506 pipe_config->name.link_m, \
12507 pipe_config->name.link_n); \
12508 ret = false; \
12509 }
12510
12511 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12512 if (!intel_compare_link_m_n(&current_config->name, \
12513 &pipe_config->name, adjust) && \
12514 !intel_compare_link_m_n(&current_config->alt_name, \
12515 &pipe_config->name, adjust)) { \
12516 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12517 "(expected tu %i gmch %i/%i link %i/%i, " \
12518 "or tu %i gmch %i/%i link %i/%i, " \
12519 "found tu %i, gmch %i/%i link %i/%i)\n", \
12520 current_config->name.tu, \
12521 current_config->name.gmch_m, \
12522 current_config->name.gmch_n, \
12523 current_config->name.link_m, \
12524 current_config->name.link_n, \
12525 current_config->alt_name.tu, \
12526 current_config->alt_name.gmch_m, \
12527 current_config->alt_name.gmch_n, \
12528 current_config->alt_name.link_m, \
12529 current_config->alt_name.link_n, \
12530 pipe_config->name.tu, \
12531 pipe_config->name.gmch_m, \
12532 pipe_config->name.gmch_n, \
12533 pipe_config->name.link_m, \
12534 pipe_config->name.link_n); \
12535 ret = false; \
12536 }
12537
12538 /* This is required for BDW+ where there is only one set of registers for
12539 * switching between high and low RR.
12540 * This macro can be used whenever a comparison has to be made between one
12541 * hw state and multiple sw state variables.
12542 */
12543 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12544 if ((current_config->name != pipe_config->name) && \
12545 (current_config->alt_name != pipe_config->name)) { \
12546 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12547 "(expected %i or %i, found %i)\n", \
12548 current_config->name, \
12549 current_config->alt_name, \
12550 pipe_config->name); \
12551 ret = false; \
12552 }
12553
12554 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12555 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12556 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12557 "(expected %i, found %i)\n", \
12558 current_config->name & (mask), \
12559 pipe_config->name & (mask)); \
12560 ret = false; \
12561 }
12562
12563 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12564 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12565 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12566 "(expected %i, found %i)\n", \
12567 current_config->name, \
12568 pipe_config->name); \
12569 ret = false; \
12570 }
12571
12572 #define PIPE_CONF_QUIRK(quirk) \
12573 ((current_config->quirks | pipe_config->quirks) & (quirk))
12574
12575 PIPE_CONF_CHECK_I(cpu_transcoder);
12576
12577 PIPE_CONF_CHECK_I(has_pch_encoder);
12578 PIPE_CONF_CHECK_I(fdi_lanes);
12579 PIPE_CONF_CHECK_M_N(fdi_m_n);
12580
12581 PIPE_CONF_CHECK_I(has_dp_encoder);
12582 PIPE_CONF_CHECK_I(lane_count);
12583
12584 if (INTEL_INFO(dev)->gen < 8) {
12585 PIPE_CONF_CHECK_M_N(dp_m_n);
12586
12587 if (current_config->has_drrs)
12588 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12589 } else
12590 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12591
12592 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12593 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12594 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12595 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12596 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12597 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12598
12599 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12600 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12601 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12602 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12603 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12604 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12605
12606 PIPE_CONF_CHECK_I(pixel_multiplier);
12607 PIPE_CONF_CHECK_I(has_hdmi_sink);
12608 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12609 IS_VALLEYVIEW(dev))
12610 PIPE_CONF_CHECK_I(limited_color_range);
12611 PIPE_CONF_CHECK_I(has_infoframe);
12612
12613 PIPE_CONF_CHECK_I(has_audio);
12614
12615 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12616 DRM_MODE_FLAG_INTERLACE);
12617
12618 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12619 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12620 DRM_MODE_FLAG_PHSYNC);
12621 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12622 DRM_MODE_FLAG_NHSYNC);
12623 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12624 DRM_MODE_FLAG_PVSYNC);
12625 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12626 DRM_MODE_FLAG_NVSYNC);
12627 }
12628
12629 PIPE_CONF_CHECK_X(gmch_pfit.control);
12630 /* pfit ratios are autocomputed by the hw on gen4+ */
12631 if (INTEL_INFO(dev)->gen < 4)
12632 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12633 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12634
12635 if (!adjust) {
12636 PIPE_CONF_CHECK_I(pipe_src_w);
12637 PIPE_CONF_CHECK_I(pipe_src_h);
12638
12639 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12640 if (current_config->pch_pfit.enabled) {
12641 PIPE_CONF_CHECK_X(pch_pfit.pos);
12642 PIPE_CONF_CHECK_X(pch_pfit.size);
12643 }
12644
12645 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12646 }
12647
12648 /* BDW+ don't expose a synchronous way to read the state */
12649 if (IS_HASWELL(dev))
12650 PIPE_CONF_CHECK_I(ips_enabled);
12651
12652 PIPE_CONF_CHECK_I(double_wide);
12653
12654 PIPE_CONF_CHECK_X(ddi_pll_sel);
12655
12656 PIPE_CONF_CHECK_I(shared_dpll);
12657 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12658 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12659 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12660 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12661 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12662 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12663 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12664 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12665 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12666
12667 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12668 PIPE_CONF_CHECK_I(pipe_bpp);
12669
12670 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12671 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12672
12673 #undef PIPE_CONF_CHECK_X
12674 #undef PIPE_CONF_CHECK_I
12675 #undef PIPE_CONF_CHECK_I_ALT
12676 #undef PIPE_CONF_CHECK_FLAGS
12677 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12678 #undef PIPE_CONF_QUIRK
12679 #undef INTEL_ERR_OR_DBG_KMS
12680
12681 return ret;
12682 }
12683
12684 static void check_wm_state(struct drm_device *dev)
12685 {
12686 struct drm_i915_private *dev_priv = dev->dev_private;
12687 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12688 struct intel_crtc *intel_crtc;
12689 int plane;
12690
12691 if (INTEL_INFO(dev)->gen < 9)
12692 return;
12693
12694 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12695 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12696
12697 for_each_intel_crtc(dev, intel_crtc) {
12698 struct skl_ddb_entry *hw_entry, *sw_entry;
12699 const enum pipe pipe = intel_crtc->pipe;
12700
12701 if (!intel_crtc->active)
12702 continue;
12703
12704 /* planes */
12705 for_each_plane(dev_priv, pipe, plane) {
12706 hw_entry = &hw_ddb.plane[pipe][plane];
12707 sw_entry = &sw_ddb->plane[pipe][plane];
12708
12709 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12710 continue;
12711
12712 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12713 "(expected (%u,%u), found (%u,%u))\n",
12714 pipe_name(pipe), plane + 1,
12715 sw_entry->start, sw_entry->end,
12716 hw_entry->start, hw_entry->end);
12717 }
12718
12719 /* cursor */
12720 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12721 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12722
12723 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12724 continue;
12725
12726 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12727 "(expected (%u,%u), found (%u,%u))\n",
12728 pipe_name(pipe),
12729 sw_entry->start, sw_entry->end,
12730 hw_entry->start, hw_entry->end);
12731 }
12732 }
12733
12734 static void
12735 check_connector_state(struct drm_device *dev,
12736 struct drm_atomic_state *old_state)
12737 {
12738 struct drm_connector_state *old_conn_state;
12739 struct drm_connector *connector;
12740 int i;
12741
12742 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12743 struct drm_encoder *encoder = connector->encoder;
12744 struct drm_connector_state *state = connector->state;
12745
12746 /* This also checks the encoder/connector hw state with the
12747 * ->get_hw_state callbacks. */
12748 intel_connector_check_state(to_intel_connector(connector));
12749
12750 I915_STATE_WARN(state->best_encoder != encoder,
12751 "connector's atomic encoder doesn't match legacy encoder\n");
12752 }
12753 }
12754
12755 static void
12756 check_encoder_state(struct drm_device *dev)
12757 {
12758 struct intel_encoder *encoder;
12759 struct intel_connector *connector;
12760
12761 for_each_intel_encoder(dev, encoder) {
12762 bool enabled = false;
12763 enum pipe pipe;
12764
12765 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12766 encoder->base.base.id,
12767 encoder->base.name);
12768
12769 for_each_intel_connector(dev, connector) {
12770 if (connector->base.state->best_encoder != &encoder->base)
12771 continue;
12772 enabled = true;
12773
12774 I915_STATE_WARN(connector->base.state->crtc !=
12775 encoder->base.crtc,
12776 "connector's crtc doesn't match encoder crtc\n");
12777 }
12778
12779 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12780 "encoder's enabled state mismatch "
12781 "(expected %i, found %i)\n",
12782 !!encoder->base.crtc, enabled);
12783
12784 if (!encoder->base.crtc) {
12785 bool active;
12786
12787 active = encoder->get_hw_state(encoder, &pipe);
12788 I915_STATE_WARN(active,
12789 "encoder detached but still enabled on pipe %c.\n",
12790 pipe_name(pipe));
12791 }
12792 }
12793 }
12794
12795 static void
12796 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12797 {
12798 struct drm_i915_private *dev_priv = dev->dev_private;
12799 struct intel_encoder *encoder;
12800 struct drm_crtc_state *old_crtc_state;
12801 struct drm_crtc *crtc;
12802 int i;
12803
12804 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12806 struct intel_crtc_state *pipe_config, *sw_config;
12807 bool active;
12808
12809 if (!needs_modeset(crtc->state) &&
12810 !to_intel_crtc_state(crtc->state)->update_pipe)
12811 continue;
12812
12813 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12814 pipe_config = to_intel_crtc_state(old_crtc_state);
12815 memset(pipe_config, 0, sizeof(*pipe_config));
12816 pipe_config->base.crtc = crtc;
12817 pipe_config->base.state = old_state;
12818
12819 DRM_DEBUG_KMS("[CRTC:%d]\n",
12820 crtc->base.id);
12821
12822 active = dev_priv->display.get_pipe_config(intel_crtc,
12823 pipe_config);
12824
12825 /* hw state is inconsistent with the pipe quirk */
12826 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12827 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12828 active = crtc->state->active;
12829
12830 I915_STATE_WARN(crtc->state->active != active,
12831 "crtc active state doesn't match with hw state "
12832 "(expected %i, found %i)\n", crtc->state->active, active);
12833
12834 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12835 "transitional active state does not match atomic hw state "
12836 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12837
12838 for_each_encoder_on_crtc(dev, crtc, encoder) {
12839 enum pipe pipe;
12840
12841 active = encoder->get_hw_state(encoder, &pipe);
12842 I915_STATE_WARN(active != crtc->state->active,
12843 "[ENCODER:%i] active %i with crtc active %i\n",
12844 encoder->base.base.id, active, crtc->state->active);
12845
12846 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12847 "Encoder connected to wrong pipe %c\n",
12848 pipe_name(pipe));
12849
12850 if (active)
12851 encoder->get_config(encoder, pipe_config);
12852 }
12853
12854 if (!crtc->state->active)
12855 continue;
12856
12857 sw_config = to_intel_crtc_state(crtc->state);
12858 if (!intel_pipe_config_compare(dev, sw_config,
12859 pipe_config, false)) {
12860 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12861 intel_dump_pipe_config(intel_crtc, pipe_config,
12862 "[hw state]");
12863 intel_dump_pipe_config(intel_crtc, sw_config,
12864 "[sw state]");
12865 }
12866 }
12867 }
12868
12869 static void
12870 check_shared_dpll_state(struct drm_device *dev)
12871 {
12872 struct drm_i915_private *dev_priv = dev->dev_private;
12873 struct intel_crtc *crtc;
12874 struct intel_dpll_hw_state dpll_hw_state;
12875 int i;
12876
12877 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12878 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12879 int enabled_crtcs = 0, active_crtcs = 0;
12880 bool active;
12881
12882 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12883
12884 DRM_DEBUG_KMS("%s\n", pll->name);
12885
12886 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12887
12888 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12889 "more active pll users than references: %i vs %i\n",
12890 pll->active, hweight32(pll->config.crtc_mask));
12891 I915_STATE_WARN(pll->active && !pll->on,
12892 "pll in active use but not on in sw tracking\n");
12893 I915_STATE_WARN(pll->on && !pll->active,
12894 "pll in on but not on in use in sw tracking\n");
12895 I915_STATE_WARN(pll->on != active,
12896 "pll on state mismatch (expected %i, found %i)\n",
12897 pll->on, active);
12898
12899 for_each_intel_crtc(dev, crtc) {
12900 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12901 enabled_crtcs++;
12902 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12903 active_crtcs++;
12904 }
12905 I915_STATE_WARN(pll->active != active_crtcs,
12906 "pll active crtcs mismatch (expected %i, found %i)\n",
12907 pll->active, active_crtcs);
12908 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12909 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12910 hweight32(pll->config.crtc_mask), enabled_crtcs);
12911
12912 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12913 sizeof(dpll_hw_state)),
12914 "pll hw state mismatch\n");
12915 }
12916 }
12917
12918 static void
12919 intel_modeset_check_state(struct drm_device *dev,
12920 struct drm_atomic_state *old_state)
12921 {
12922 check_wm_state(dev);
12923 check_connector_state(dev, old_state);
12924 check_encoder_state(dev);
12925 check_crtc_state(dev, old_state);
12926 check_shared_dpll_state(dev);
12927 }
12928
12929 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12930 int dotclock)
12931 {
12932 /*
12933 * FDI already provided one idea for the dotclock.
12934 * Yell if the encoder disagrees.
12935 */
12936 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12937 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12938 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12939 }
12940
12941 static void update_scanline_offset(struct intel_crtc *crtc)
12942 {
12943 struct drm_device *dev = crtc->base.dev;
12944
12945 /*
12946 * The scanline counter increments at the leading edge of hsync.
12947 *
12948 * On most platforms it starts counting from vtotal-1 on the
12949 * first active line. That means the scanline counter value is
12950 * always one less than what we would expect. Ie. just after
12951 * start of vblank, which also occurs at start of hsync (on the
12952 * last active line), the scanline counter will read vblank_start-1.
12953 *
12954 * On gen2 the scanline counter starts counting from 1 instead
12955 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12956 * to keep the value positive), instead of adding one.
12957 *
12958 * On HSW+ the behaviour of the scanline counter depends on the output
12959 * type. For DP ports it behaves like most other platforms, but on HDMI
12960 * there's an extra 1 line difference. So we need to add two instead of
12961 * one to the value.
12962 */
12963 if (IS_GEN2(dev)) {
12964 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12965 int vtotal;
12966
12967 vtotal = adjusted_mode->crtc_vtotal;
12968 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12969 vtotal /= 2;
12970
12971 crtc->scanline_offset = vtotal - 1;
12972 } else if (HAS_DDI(dev) &&
12973 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12974 crtc->scanline_offset = 2;
12975 } else
12976 crtc->scanline_offset = 1;
12977 }
12978
12979 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12980 {
12981 struct drm_device *dev = state->dev;
12982 struct drm_i915_private *dev_priv = to_i915(dev);
12983 struct intel_shared_dpll_config *shared_dpll = NULL;
12984 struct intel_crtc *intel_crtc;
12985 struct intel_crtc_state *intel_crtc_state;
12986 struct drm_crtc *crtc;
12987 struct drm_crtc_state *crtc_state;
12988 int i;
12989
12990 if (!dev_priv->display.crtc_compute_clock)
12991 return;
12992
12993 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12994 int dpll;
12995
12996 intel_crtc = to_intel_crtc(crtc);
12997 intel_crtc_state = to_intel_crtc_state(crtc_state);
12998 dpll = intel_crtc_state->shared_dpll;
12999
13000 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13001 continue;
13002
13003 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13004
13005 if (!shared_dpll)
13006 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13007
13008 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13009 }
13010 }
13011
13012 /*
13013 * This implements the workaround described in the "notes" section of the mode
13014 * set sequence documentation. When going from no pipes or single pipe to
13015 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13016 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13017 */
13018 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13019 {
13020 struct drm_crtc_state *crtc_state;
13021 struct intel_crtc *intel_crtc;
13022 struct drm_crtc *crtc;
13023 struct intel_crtc_state *first_crtc_state = NULL;
13024 struct intel_crtc_state *other_crtc_state = NULL;
13025 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13026 int i;
13027
13028 /* look at all crtc's that are going to be enabled in during modeset */
13029 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13030 intel_crtc = to_intel_crtc(crtc);
13031
13032 if (!crtc_state->active || !needs_modeset(crtc_state))
13033 continue;
13034
13035 if (first_crtc_state) {
13036 other_crtc_state = to_intel_crtc_state(crtc_state);
13037 break;
13038 } else {
13039 first_crtc_state = to_intel_crtc_state(crtc_state);
13040 first_pipe = intel_crtc->pipe;
13041 }
13042 }
13043
13044 /* No workaround needed? */
13045 if (!first_crtc_state)
13046 return 0;
13047
13048 /* w/a possibly needed, check how many crtc's are already enabled. */
13049 for_each_intel_crtc(state->dev, intel_crtc) {
13050 struct intel_crtc_state *pipe_config;
13051
13052 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13053 if (IS_ERR(pipe_config))
13054 return PTR_ERR(pipe_config);
13055
13056 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13057
13058 if (!pipe_config->base.active ||
13059 needs_modeset(&pipe_config->base))
13060 continue;
13061
13062 /* 2 or more enabled crtcs means no need for w/a */
13063 if (enabled_pipe != INVALID_PIPE)
13064 return 0;
13065
13066 enabled_pipe = intel_crtc->pipe;
13067 }
13068
13069 if (enabled_pipe != INVALID_PIPE)
13070 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13071 else if (other_crtc_state)
13072 other_crtc_state->hsw_workaround_pipe = first_pipe;
13073
13074 return 0;
13075 }
13076
13077 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13078 {
13079 struct drm_crtc *crtc;
13080 struct drm_crtc_state *crtc_state;
13081 int ret = 0;
13082
13083 /* add all active pipes to the state */
13084 for_each_crtc(state->dev, crtc) {
13085 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13086 if (IS_ERR(crtc_state))
13087 return PTR_ERR(crtc_state);
13088
13089 if (!crtc_state->active || needs_modeset(crtc_state))
13090 continue;
13091
13092 crtc_state->mode_changed = true;
13093
13094 ret = drm_atomic_add_affected_connectors(state, crtc);
13095 if (ret)
13096 break;
13097
13098 ret = drm_atomic_add_affected_planes(state, crtc);
13099 if (ret)
13100 break;
13101 }
13102
13103 return ret;
13104 }
13105
13106 static int intel_modeset_checks(struct drm_atomic_state *state)
13107 {
13108 struct drm_device *dev = state->dev;
13109 struct drm_i915_private *dev_priv = dev->dev_private;
13110 int ret;
13111
13112 if (!check_digital_port_conflicts(state)) {
13113 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13114 return -EINVAL;
13115 }
13116
13117 /*
13118 * See if the config requires any additional preparation, e.g.
13119 * to adjust global state with pipes off. We need to do this
13120 * here so we can get the modeset_pipe updated config for the new
13121 * mode set on this crtc. For other crtcs we need to use the
13122 * adjusted_mode bits in the crtc directly.
13123 */
13124 if (dev_priv->display.modeset_calc_cdclk) {
13125 unsigned int cdclk;
13126
13127 ret = dev_priv->display.modeset_calc_cdclk(state);
13128
13129 cdclk = to_intel_atomic_state(state)->cdclk;
13130 if (!ret && cdclk != dev_priv->cdclk_freq)
13131 ret = intel_modeset_all_pipes(state);
13132
13133 if (ret < 0)
13134 return ret;
13135 } else
13136 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13137
13138 intel_modeset_clear_plls(state);
13139
13140 if (IS_HASWELL(dev))
13141 return haswell_mode_set_planes_workaround(state);
13142
13143 return 0;
13144 }
13145
13146 /*
13147 * Handle calculation of various watermark data at the end of the atomic check
13148 * phase. The code here should be run after the per-crtc and per-plane 'check'
13149 * handlers to ensure that all derived state has been updated.
13150 */
13151 static void calc_watermark_data(struct drm_atomic_state *state)
13152 {
13153 struct drm_device *dev = state->dev;
13154 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13155 struct drm_crtc *crtc;
13156 struct drm_crtc_state *cstate;
13157 struct drm_plane *plane;
13158 struct drm_plane_state *pstate;
13159
13160 /*
13161 * Calculate watermark configuration details now that derived
13162 * plane/crtc state is all properly updated.
13163 */
13164 drm_for_each_crtc(crtc, dev) {
13165 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13166 crtc->state;
13167
13168 if (cstate->active)
13169 intel_state->wm_config.num_pipes_active++;
13170 }
13171 drm_for_each_legacy_plane(plane, dev) {
13172 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13173 plane->state;
13174
13175 if (!to_intel_plane_state(pstate)->visible)
13176 continue;
13177
13178 intel_state->wm_config.sprites_enabled = true;
13179 if (pstate->crtc_w != pstate->src_w >> 16 ||
13180 pstate->crtc_h != pstate->src_h >> 16)
13181 intel_state->wm_config.sprites_scaled = true;
13182 }
13183 }
13184
13185 /**
13186 * intel_atomic_check - validate state object
13187 * @dev: drm device
13188 * @state: state to validate
13189 */
13190 static int intel_atomic_check(struct drm_device *dev,
13191 struct drm_atomic_state *state)
13192 {
13193 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13194 struct drm_crtc *crtc;
13195 struct drm_crtc_state *crtc_state;
13196 int ret, i;
13197 bool any_ms = false;
13198
13199 ret = drm_atomic_helper_check_modeset(dev, state);
13200 if (ret)
13201 return ret;
13202
13203 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13204 struct intel_crtc_state *pipe_config =
13205 to_intel_crtc_state(crtc_state);
13206
13207 memset(&to_intel_crtc(crtc)->atomic, 0,
13208 sizeof(struct intel_crtc_atomic_commit));
13209
13210 /* Catch I915_MODE_FLAG_INHERITED */
13211 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13212 crtc_state->mode_changed = true;
13213
13214 if (!crtc_state->enable) {
13215 if (needs_modeset(crtc_state))
13216 any_ms = true;
13217 continue;
13218 }
13219
13220 if (!needs_modeset(crtc_state))
13221 continue;
13222
13223 /* FIXME: For only active_changed we shouldn't need to do any
13224 * state recomputation at all. */
13225
13226 ret = drm_atomic_add_affected_connectors(state, crtc);
13227 if (ret)
13228 return ret;
13229
13230 ret = intel_modeset_pipe_config(crtc, pipe_config);
13231 if (ret)
13232 return ret;
13233
13234 if (i915.fastboot &&
13235 intel_pipe_config_compare(state->dev,
13236 to_intel_crtc_state(crtc->state),
13237 pipe_config, true)) {
13238 crtc_state->mode_changed = false;
13239 to_intel_crtc_state(crtc_state)->update_pipe = true;
13240 }
13241
13242 if (needs_modeset(crtc_state)) {
13243 any_ms = true;
13244
13245 ret = drm_atomic_add_affected_planes(state, crtc);
13246 if (ret)
13247 return ret;
13248 }
13249
13250 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13251 needs_modeset(crtc_state) ?
13252 "[modeset]" : "[fastset]");
13253 }
13254
13255 if (any_ms) {
13256 ret = intel_modeset_checks(state);
13257
13258 if (ret)
13259 return ret;
13260 } else
13261 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13262
13263 ret = drm_atomic_helper_check_planes(state->dev, state);
13264 if (ret)
13265 return ret;
13266
13267 calc_watermark_data(state);
13268
13269 return 0;
13270 }
13271
13272 static int intel_atomic_prepare_commit(struct drm_device *dev,
13273 struct drm_atomic_state *state,
13274 bool async)
13275 {
13276 struct drm_i915_private *dev_priv = dev->dev_private;
13277 struct drm_plane_state *plane_state;
13278 struct drm_crtc_state *crtc_state;
13279 struct drm_plane *plane;
13280 struct drm_crtc *crtc;
13281 int i, ret;
13282
13283 if (async) {
13284 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13285 return -EINVAL;
13286 }
13287
13288 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13289 ret = intel_crtc_wait_for_pending_flips(crtc);
13290 if (ret)
13291 return ret;
13292
13293 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13294 flush_workqueue(dev_priv->wq);
13295 }
13296
13297 ret = mutex_lock_interruptible(&dev->struct_mutex);
13298 if (ret)
13299 return ret;
13300
13301 ret = drm_atomic_helper_prepare_planes(dev, state);
13302 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13303 u32 reset_counter;
13304
13305 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13306 mutex_unlock(&dev->struct_mutex);
13307
13308 for_each_plane_in_state(state, plane, plane_state, i) {
13309 struct intel_plane_state *intel_plane_state =
13310 to_intel_plane_state(plane_state);
13311
13312 if (!intel_plane_state->wait_req)
13313 continue;
13314
13315 ret = __i915_wait_request(intel_plane_state->wait_req,
13316 reset_counter, true,
13317 NULL, NULL);
13318
13319 /* Swallow -EIO errors to allow updates during hw lockup. */
13320 if (ret == -EIO)
13321 ret = 0;
13322
13323 if (ret)
13324 break;
13325 }
13326
13327 if (!ret)
13328 return 0;
13329
13330 mutex_lock(&dev->struct_mutex);
13331 drm_atomic_helper_cleanup_planes(dev, state);
13332 }
13333
13334 mutex_unlock(&dev->struct_mutex);
13335 return ret;
13336 }
13337
13338 /**
13339 * intel_atomic_commit - commit validated state object
13340 * @dev: DRM device
13341 * @state: the top-level driver state object
13342 * @async: asynchronous commit
13343 *
13344 * This function commits a top-level state object that has been validated
13345 * with drm_atomic_helper_check().
13346 *
13347 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13348 * we can only handle plane-related operations and do not yet support
13349 * asynchronous commit.
13350 *
13351 * RETURNS
13352 * Zero for success or -errno.
13353 */
13354 static int intel_atomic_commit(struct drm_device *dev,
13355 struct drm_atomic_state *state,
13356 bool async)
13357 {
13358 struct drm_i915_private *dev_priv = dev->dev_private;
13359 struct drm_crtc_state *crtc_state;
13360 struct drm_crtc *crtc;
13361 int ret = 0;
13362 int i;
13363 bool any_ms = false;
13364
13365 ret = intel_atomic_prepare_commit(dev, state, async);
13366 if (ret) {
13367 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13368 return ret;
13369 }
13370
13371 drm_atomic_helper_swap_state(dev, state);
13372 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13373
13374 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13376
13377 if (!needs_modeset(crtc->state))
13378 continue;
13379
13380 any_ms = true;
13381 intel_pre_plane_update(intel_crtc);
13382
13383 if (crtc_state->active) {
13384 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13385 dev_priv->display.crtc_disable(crtc);
13386 intel_crtc->active = false;
13387 intel_disable_shared_dpll(intel_crtc);
13388 }
13389 }
13390
13391 /* Only after disabling all output pipelines that will be changed can we
13392 * update the the output configuration. */
13393 intel_modeset_update_crtc_state(state);
13394
13395 if (any_ms) {
13396 intel_shared_dpll_commit(state);
13397
13398 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13399 modeset_update_crtc_power_domains(state);
13400 }
13401
13402 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13403 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13405 bool modeset = needs_modeset(crtc->state);
13406 bool update_pipe = !modeset &&
13407 to_intel_crtc_state(crtc->state)->update_pipe;
13408 unsigned long put_domains = 0;
13409
13410 if (modeset)
13411 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13412
13413 if (modeset && crtc->state->active) {
13414 update_scanline_offset(to_intel_crtc(crtc));
13415 dev_priv->display.crtc_enable(crtc);
13416 }
13417
13418 if (update_pipe) {
13419 put_domains = modeset_get_crtc_power_domains(crtc);
13420
13421 /* make sure intel_modeset_check_state runs */
13422 any_ms = true;
13423 }
13424
13425 if (!modeset)
13426 intel_pre_plane_update(intel_crtc);
13427
13428 if (crtc->state->active &&
13429 (crtc->state->planes_changed || update_pipe))
13430 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13431
13432 if (put_domains)
13433 modeset_put_power_domains(dev_priv, put_domains);
13434
13435 intel_post_plane_update(intel_crtc);
13436
13437 if (modeset)
13438 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13439 }
13440
13441 /* FIXME: add subpixel order */
13442
13443 drm_atomic_helper_wait_for_vblanks(dev, state);
13444
13445 mutex_lock(&dev->struct_mutex);
13446 drm_atomic_helper_cleanup_planes(dev, state);
13447 mutex_unlock(&dev->struct_mutex);
13448
13449 if (any_ms)
13450 intel_modeset_check_state(dev, state);
13451
13452 drm_atomic_state_free(state);
13453
13454 return 0;
13455 }
13456
13457 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13458 {
13459 struct drm_device *dev = crtc->dev;
13460 struct drm_atomic_state *state;
13461 struct drm_crtc_state *crtc_state;
13462 int ret;
13463
13464 state = drm_atomic_state_alloc(dev);
13465 if (!state) {
13466 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13467 crtc->base.id);
13468 return;
13469 }
13470
13471 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13472
13473 retry:
13474 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13475 ret = PTR_ERR_OR_ZERO(crtc_state);
13476 if (!ret) {
13477 if (!crtc_state->active)
13478 goto out;
13479
13480 crtc_state->mode_changed = true;
13481 ret = drm_atomic_commit(state);
13482 }
13483
13484 if (ret == -EDEADLK) {
13485 drm_atomic_state_clear(state);
13486 drm_modeset_backoff(state->acquire_ctx);
13487 goto retry;
13488 }
13489
13490 if (ret)
13491 out:
13492 drm_atomic_state_free(state);
13493 }
13494
13495 #undef for_each_intel_crtc_masked
13496
13497 static const struct drm_crtc_funcs intel_crtc_funcs = {
13498 .gamma_set = intel_crtc_gamma_set,
13499 .set_config = drm_atomic_helper_set_config,
13500 .destroy = intel_crtc_destroy,
13501 .page_flip = intel_crtc_page_flip,
13502 .atomic_duplicate_state = intel_crtc_duplicate_state,
13503 .atomic_destroy_state = intel_crtc_destroy_state,
13504 };
13505
13506 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13507 struct intel_shared_dpll *pll,
13508 struct intel_dpll_hw_state *hw_state)
13509 {
13510 uint32_t val;
13511
13512 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13513 return false;
13514
13515 val = I915_READ(PCH_DPLL(pll->id));
13516 hw_state->dpll = val;
13517 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13518 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13519
13520 return val & DPLL_VCO_ENABLE;
13521 }
13522
13523 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13524 struct intel_shared_dpll *pll)
13525 {
13526 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13527 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13528 }
13529
13530 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13531 struct intel_shared_dpll *pll)
13532 {
13533 /* PCH refclock must be enabled first */
13534 ibx_assert_pch_refclk_enabled(dev_priv);
13535
13536 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13537
13538 /* Wait for the clocks to stabilize. */
13539 POSTING_READ(PCH_DPLL(pll->id));
13540 udelay(150);
13541
13542 /* The pixel multiplier can only be updated once the
13543 * DPLL is enabled and the clocks are stable.
13544 *
13545 * So write it again.
13546 */
13547 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13548 POSTING_READ(PCH_DPLL(pll->id));
13549 udelay(200);
13550 }
13551
13552 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13553 struct intel_shared_dpll *pll)
13554 {
13555 struct drm_device *dev = dev_priv->dev;
13556 struct intel_crtc *crtc;
13557
13558 /* Make sure no transcoder isn't still depending on us. */
13559 for_each_intel_crtc(dev, crtc) {
13560 if (intel_crtc_to_shared_dpll(crtc) == pll)
13561 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13562 }
13563
13564 I915_WRITE(PCH_DPLL(pll->id), 0);
13565 POSTING_READ(PCH_DPLL(pll->id));
13566 udelay(200);
13567 }
13568
13569 static char *ibx_pch_dpll_names[] = {
13570 "PCH DPLL A",
13571 "PCH DPLL B",
13572 };
13573
13574 static void ibx_pch_dpll_init(struct drm_device *dev)
13575 {
13576 struct drm_i915_private *dev_priv = dev->dev_private;
13577 int i;
13578
13579 dev_priv->num_shared_dpll = 2;
13580
13581 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13582 dev_priv->shared_dplls[i].id = i;
13583 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13584 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13585 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13586 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13587 dev_priv->shared_dplls[i].get_hw_state =
13588 ibx_pch_dpll_get_hw_state;
13589 }
13590 }
13591
13592 static void intel_shared_dpll_init(struct drm_device *dev)
13593 {
13594 struct drm_i915_private *dev_priv = dev->dev_private;
13595
13596 if (HAS_DDI(dev))
13597 intel_ddi_pll_init(dev);
13598 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13599 ibx_pch_dpll_init(dev);
13600 else
13601 dev_priv->num_shared_dpll = 0;
13602
13603 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13604 }
13605
13606 /**
13607 * intel_prepare_plane_fb - Prepare fb for usage on plane
13608 * @plane: drm plane to prepare for
13609 * @fb: framebuffer to prepare for presentation
13610 *
13611 * Prepares a framebuffer for usage on a display plane. Generally this
13612 * involves pinning the underlying object and updating the frontbuffer tracking
13613 * bits. Some older platforms need special physical address handling for
13614 * cursor planes.
13615 *
13616 * Must be called with struct_mutex held.
13617 *
13618 * Returns 0 on success, negative error code on failure.
13619 */
13620 int
13621 intel_prepare_plane_fb(struct drm_plane *plane,
13622 const struct drm_plane_state *new_state)
13623 {
13624 struct drm_device *dev = plane->dev;
13625 struct drm_framebuffer *fb = new_state->fb;
13626 struct intel_plane *intel_plane = to_intel_plane(plane);
13627 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13628 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13629 int ret = 0;
13630
13631 if (!obj && !old_obj)
13632 return 0;
13633
13634 if (old_obj) {
13635 struct drm_crtc_state *crtc_state =
13636 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13637
13638 /* Big Hammer, we also need to ensure that any pending
13639 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13640 * current scanout is retired before unpinning the old
13641 * framebuffer. Note that we rely on userspace rendering
13642 * into the buffer attached to the pipe they are waiting
13643 * on. If not, userspace generates a GPU hang with IPEHR
13644 * point to the MI_WAIT_FOR_EVENT.
13645 *
13646 * This should only fail upon a hung GPU, in which case we
13647 * can safely continue.
13648 */
13649 if (needs_modeset(crtc_state))
13650 ret = i915_gem_object_wait_rendering(old_obj, true);
13651
13652 /* Swallow -EIO errors to allow updates during hw lockup. */
13653 if (ret && ret != -EIO)
13654 return ret;
13655 }
13656
13657 if (!obj) {
13658 ret = 0;
13659 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13660 INTEL_INFO(dev)->cursor_needs_physical) {
13661 int align = IS_I830(dev) ? 16 * 1024 : 256;
13662 ret = i915_gem_object_attach_phys(obj, align);
13663 if (ret)
13664 DRM_DEBUG_KMS("failed to attach phys object\n");
13665 } else {
13666 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13667 }
13668
13669 if (ret == 0) {
13670 if (obj) {
13671 struct intel_plane_state *plane_state =
13672 to_intel_plane_state(new_state);
13673
13674 i915_gem_request_assign(&plane_state->wait_req,
13675 obj->last_write_req);
13676 }
13677
13678 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13679 }
13680
13681 return ret;
13682 }
13683
13684 /**
13685 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13686 * @plane: drm plane to clean up for
13687 * @fb: old framebuffer that was on plane
13688 *
13689 * Cleans up a framebuffer that has just been removed from a plane.
13690 *
13691 * Must be called with struct_mutex held.
13692 */
13693 void
13694 intel_cleanup_plane_fb(struct drm_plane *plane,
13695 const struct drm_plane_state *old_state)
13696 {
13697 struct drm_device *dev = plane->dev;
13698 struct intel_plane *intel_plane = to_intel_plane(plane);
13699 struct intel_plane_state *old_intel_state;
13700 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13701 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13702
13703 old_intel_state = to_intel_plane_state(old_state);
13704
13705 if (!obj && !old_obj)
13706 return;
13707
13708 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13709 !INTEL_INFO(dev)->cursor_needs_physical))
13710 intel_unpin_fb_obj(old_state->fb, old_state);
13711
13712 /* prepare_fb aborted? */
13713 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13714 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13715 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13716
13717 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13718
13719 }
13720
13721 int
13722 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13723 {
13724 int max_scale;
13725 struct drm_device *dev;
13726 struct drm_i915_private *dev_priv;
13727 int crtc_clock, cdclk;
13728
13729 if (!intel_crtc || !crtc_state)
13730 return DRM_PLANE_HELPER_NO_SCALING;
13731
13732 dev = intel_crtc->base.dev;
13733 dev_priv = dev->dev_private;
13734 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13735 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13736
13737 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13738 return DRM_PLANE_HELPER_NO_SCALING;
13739
13740 /*
13741 * skl max scale is lower of:
13742 * close to 3 but not 3, -1 is for that purpose
13743 * or
13744 * cdclk/crtc_clock
13745 */
13746 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13747
13748 return max_scale;
13749 }
13750
13751 static int
13752 intel_check_primary_plane(struct drm_plane *plane,
13753 struct intel_crtc_state *crtc_state,
13754 struct intel_plane_state *state)
13755 {
13756 struct drm_crtc *crtc = state->base.crtc;
13757 struct drm_framebuffer *fb = state->base.fb;
13758 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13759 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13760 bool can_position = false;
13761
13762 /* use scaler when colorkey is not required */
13763 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13764 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13765 min_scale = 1;
13766 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13767 can_position = true;
13768 }
13769
13770 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13771 &state->dst, &state->clip,
13772 min_scale, max_scale,
13773 can_position, true,
13774 &state->visible);
13775 }
13776
13777 static void
13778 intel_commit_primary_plane(struct drm_plane *plane,
13779 struct intel_plane_state *state)
13780 {
13781 struct drm_crtc *crtc = state->base.crtc;
13782 struct drm_framebuffer *fb = state->base.fb;
13783 struct drm_device *dev = plane->dev;
13784 struct drm_i915_private *dev_priv = dev->dev_private;
13785
13786 crtc = crtc ? crtc : plane->crtc;
13787
13788 dev_priv->display.update_primary_plane(crtc, fb,
13789 state->src.x1 >> 16,
13790 state->src.y1 >> 16);
13791 }
13792
13793 static void
13794 intel_disable_primary_plane(struct drm_plane *plane,
13795 struct drm_crtc *crtc)
13796 {
13797 struct drm_device *dev = plane->dev;
13798 struct drm_i915_private *dev_priv = dev->dev_private;
13799
13800 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13801 }
13802
13803 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13804 struct drm_crtc_state *old_crtc_state)
13805 {
13806 struct drm_device *dev = crtc->dev;
13807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13808 struct intel_crtc_state *old_intel_state =
13809 to_intel_crtc_state(old_crtc_state);
13810 bool modeset = needs_modeset(crtc->state);
13811
13812 if (intel_crtc->atomic.update_wm_pre)
13813 intel_update_watermarks(crtc);
13814
13815 /* Perform vblank evasion around commit operation */
13816 intel_pipe_update_start(intel_crtc);
13817
13818 if (modeset)
13819 return;
13820
13821 if (to_intel_crtc_state(crtc->state)->update_pipe)
13822 intel_update_pipe_config(intel_crtc, old_intel_state);
13823 else if (INTEL_INFO(dev)->gen >= 9)
13824 skl_detach_scalers(intel_crtc);
13825 }
13826
13827 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13828 struct drm_crtc_state *old_crtc_state)
13829 {
13830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13831
13832 intel_pipe_update_end(intel_crtc);
13833 }
13834
13835 /**
13836 * intel_plane_destroy - destroy a plane
13837 * @plane: plane to destroy
13838 *
13839 * Common destruction function for all types of planes (primary, cursor,
13840 * sprite).
13841 */
13842 void intel_plane_destroy(struct drm_plane *plane)
13843 {
13844 struct intel_plane *intel_plane = to_intel_plane(plane);
13845 drm_plane_cleanup(plane);
13846 kfree(intel_plane);
13847 }
13848
13849 const struct drm_plane_funcs intel_plane_funcs = {
13850 .update_plane = drm_atomic_helper_update_plane,
13851 .disable_plane = drm_atomic_helper_disable_plane,
13852 .destroy = intel_plane_destroy,
13853 .set_property = drm_atomic_helper_plane_set_property,
13854 .atomic_get_property = intel_plane_atomic_get_property,
13855 .atomic_set_property = intel_plane_atomic_set_property,
13856 .atomic_duplicate_state = intel_plane_duplicate_state,
13857 .atomic_destroy_state = intel_plane_destroy_state,
13858
13859 };
13860
13861 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13862 int pipe)
13863 {
13864 struct intel_plane *primary;
13865 struct intel_plane_state *state;
13866 const uint32_t *intel_primary_formats;
13867 unsigned int num_formats;
13868
13869 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13870 if (primary == NULL)
13871 return NULL;
13872
13873 state = intel_create_plane_state(&primary->base);
13874 if (!state) {
13875 kfree(primary);
13876 return NULL;
13877 }
13878 primary->base.state = &state->base;
13879
13880 primary->can_scale = false;
13881 primary->max_downscale = 1;
13882 if (INTEL_INFO(dev)->gen >= 9) {
13883 primary->can_scale = true;
13884 state->scaler_id = -1;
13885 }
13886 primary->pipe = pipe;
13887 primary->plane = pipe;
13888 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13889 primary->check_plane = intel_check_primary_plane;
13890 primary->commit_plane = intel_commit_primary_plane;
13891 primary->disable_plane = intel_disable_primary_plane;
13892 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13893 primary->plane = !pipe;
13894
13895 if (INTEL_INFO(dev)->gen >= 9) {
13896 intel_primary_formats = skl_primary_formats;
13897 num_formats = ARRAY_SIZE(skl_primary_formats);
13898 } else if (INTEL_INFO(dev)->gen >= 4) {
13899 intel_primary_formats = i965_primary_formats;
13900 num_formats = ARRAY_SIZE(i965_primary_formats);
13901 } else {
13902 intel_primary_formats = i8xx_primary_formats;
13903 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13904 }
13905
13906 drm_universal_plane_init(dev, &primary->base, 0,
13907 &intel_plane_funcs,
13908 intel_primary_formats, num_formats,
13909 DRM_PLANE_TYPE_PRIMARY);
13910
13911 if (INTEL_INFO(dev)->gen >= 4)
13912 intel_create_rotation_property(dev, primary);
13913
13914 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13915
13916 return &primary->base;
13917 }
13918
13919 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13920 {
13921 if (!dev->mode_config.rotation_property) {
13922 unsigned long flags = BIT(DRM_ROTATE_0) |
13923 BIT(DRM_ROTATE_180);
13924
13925 if (INTEL_INFO(dev)->gen >= 9)
13926 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13927
13928 dev->mode_config.rotation_property =
13929 drm_mode_create_rotation_property(dev, flags);
13930 }
13931 if (dev->mode_config.rotation_property)
13932 drm_object_attach_property(&plane->base.base,
13933 dev->mode_config.rotation_property,
13934 plane->base.state->rotation);
13935 }
13936
13937 static int
13938 intel_check_cursor_plane(struct drm_plane *plane,
13939 struct intel_crtc_state *crtc_state,
13940 struct intel_plane_state *state)
13941 {
13942 struct drm_crtc *crtc = crtc_state->base.crtc;
13943 struct drm_framebuffer *fb = state->base.fb;
13944 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13945 unsigned stride;
13946 int ret;
13947
13948 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13949 &state->dst, &state->clip,
13950 DRM_PLANE_HELPER_NO_SCALING,
13951 DRM_PLANE_HELPER_NO_SCALING,
13952 true, true, &state->visible);
13953 if (ret)
13954 return ret;
13955
13956 /* if we want to turn off the cursor ignore width and height */
13957 if (!obj)
13958 return 0;
13959
13960 /* Check for which cursor types we support */
13961 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13962 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13963 state->base.crtc_w, state->base.crtc_h);
13964 return -EINVAL;
13965 }
13966
13967 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13968 if (obj->base.size < stride * state->base.crtc_h) {
13969 DRM_DEBUG_KMS("buffer is too small\n");
13970 return -ENOMEM;
13971 }
13972
13973 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13974 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13975 return -EINVAL;
13976 }
13977
13978 return 0;
13979 }
13980
13981 static void
13982 intel_disable_cursor_plane(struct drm_plane *plane,
13983 struct drm_crtc *crtc)
13984 {
13985 intel_crtc_update_cursor(crtc, false);
13986 }
13987
13988 static void
13989 intel_commit_cursor_plane(struct drm_plane *plane,
13990 struct intel_plane_state *state)
13991 {
13992 struct drm_crtc *crtc = state->base.crtc;
13993 struct drm_device *dev = plane->dev;
13994 struct intel_crtc *intel_crtc;
13995 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13996 uint32_t addr;
13997
13998 crtc = crtc ? crtc : plane->crtc;
13999 intel_crtc = to_intel_crtc(crtc);
14000
14001 if (intel_crtc->cursor_bo == obj)
14002 goto update;
14003
14004 if (!obj)
14005 addr = 0;
14006 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14007 addr = i915_gem_obj_ggtt_offset(obj);
14008 else
14009 addr = obj->phys_handle->busaddr;
14010
14011 intel_crtc->cursor_addr = addr;
14012 intel_crtc->cursor_bo = obj;
14013
14014 update:
14015 intel_crtc_update_cursor(crtc, state->visible);
14016 }
14017
14018 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14019 int pipe)
14020 {
14021 struct intel_plane *cursor;
14022 struct intel_plane_state *state;
14023
14024 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14025 if (cursor == NULL)
14026 return NULL;
14027
14028 state = intel_create_plane_state(&cursor->base);
14029 if (!state) {
14030 kfree(cursor);
14031 return NULL;
14032 }
14033 cursor->base.state = &state->base;
14034
14035 cursor->can_scale = false;
14036 cursor->max_downscale = 1;
14037 cursor->pipe = pipe;
14038 cursor->plane = pipe;
14039 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14040 cursor->check_plane = intel_check_cursor_plane;
14041 cursor->commit_plane = intel_commit_cursor_plane;
14042 cursor->disable_plane = intel_disable_cursor_plane;
14043
14044 drm_universal_plane_init(dev, &cursor->base, 0,
14045 &intel_plane_funcs,
14046 intel_cursor_formats,
14047 ARRAY_SIZE(intel_cursor_formats),
14048 DRM_PLANE_TYPE_CURSOR);
14049
14050 if (INTEL_INFO(dev)->gen >= 4) {
14051 if (!dev->mode_config.rotation_property)
14052 dev->mode_config.rotation_property =
14053 drm_mode_create_rotation_property(dev,
14054 BIT(DRM_ROTATE_0) |
14055 BIT(DRM_ROTATE_180));
14056 if (dev->mode_config.rotation_property)
14057 drm_object_attach_property(&cursor->base.base,
14058 dev->mode_config.rotation_property,
14059 state->base.rotation);
14060 }
14061
14062 if (INTEL_INFO(dev)->gen >=9)
14063 state->scaler_id = -1;
14064
14065 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14066
14067 return &cursor->base;
14068 }
14069
14070 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14071 struct intel_crtc_state *crtc_state)
14072 {
14073 int i;
14074 struct intel_scaler *intel_scaler;
14075 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14076
14077 for (i = 0; i < intel_crtc->num_scalers; i++) {
14078 intel_scaler = &scaler_state->scalers[i];
14079 intel_scaler->in_use = 0;
14080 intel_scaler->mode = PS_SCALER_MODE_DYN;
14081 }
14082
14083 scaler_state->scaler_id = -1;
14084 }
14085
14086 static void intel_crtc_init(struct drm_device *dev, int pipe)
14087 {
14088 struct drm_i915_private *dev_priv = dev->dev_private;
14089 struct intel_crtc *intel_crtc;
14090 struct intel_crtc_state *crtc_state = NULL;
14091 struct drm_plane *primary = NULL;
14092 struct drm_plane *cursor = NULL;
14093 int i, ret;
14094
14095 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14096 if (intel_crtc == NULL)
14097 return;
14098
14099 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14100 if (!crtc_state)
14101 goto fail;
14102 intel_crtc->config = crtc_state;
14103 intel_crtc->base.state = &crtc_state->base;
14104 crtc_state->base.crtc = &intel_crtc->base;
14105
14106 /* initialize shared scalers */
14107 if (INTEL_INFO(dev)->gen >= 9) {
14108 if (pipe == PIPE_C)
14109 intel_crtc->num_scalers = 1;
14110 else
14111 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14112
14113 skl_init_scalers(dev, intel_crtc, crtc_state);
14114 }
14115
14116 primary = intel_primary_plane_create(dev, pipe);
14117 if (!primary)
14118 goto fail;
14119
14120 cursor = intel_cursor_plane_create(dev, pipe);
14121 if (!cursor)
14122 goto fail;
14123
14124 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14125 cursor, &intel_crtc_funcs);
14126 if (ret)
14127 goto fail;
14128
14129 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14130 for (i = 0; i < 256; i++) {
14131 intel_crtc->lut_r[i] = i;
14132 intel_crtc->lut_g[i] = i;
14133 intel_crtc->lut_b[i] = i;
14134 }
14135
14136 /*
14137 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14138 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14139 */
14140 intel_crtc->pipe = pipe;
14141 intel_crtc->plane = pipe;
14142 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14143 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14144 intel_crtc->plane = !pipe;
14145 }
14146
14147 intel_crtc->cursor_base = ~0;
14148 intel_crtc->cursor_cntl = ~0;
14149 intel_crtc->cursor_size = ~0;
14150
14151 intel_crtc->wm.cxsr_allowed = true;
14152
14153 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14154 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14155 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14156 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14157
14158 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14159
14160 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14161 return;
14162
14163 fail:
14164 if (primary)
14165 drm_plane_cleanup(primary);
14166 if (cursor)
14167 drm_plane_cleanup(cursor);
14168 kfree(crtc_state);
14169 kfree(intel_crtc);
14170 }
14171
14172 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14173 {
14174 struct drm_encoder *encoder = connector->base.encoder;
14175 struct drm_device *dev = connector->base.dev;
14176
14177 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14178
14179 if (!encoder || WARN_ON(!encoder->crtc))
14180 return INVALID_PIPE;
14181
14182 return to_intel_crtc(encoder->crtc)->pipe;
14183 }
14184
14185 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14186 struct drm_file *file)
14187 {
14188 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14189 struct drm_crtc *drmmode_crtc;
14190 struct intel_crtc *crtc;
14191
14192 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14193
14194 if (!drmmode_crtc) {
14195 DRM_ERROR("no such CRTC id\n");
14196 return -ENOENT;
14197 }
14198
14199 crtc = to_intel_crtc(drmmode_crtc);
14200 pipe_from_crtc_id->pipe = crtc->pipe;
14201
14202 return 0;
14203 }
14204
14205 static int intel_encoder_clones(struct intel_encoder *encoder)
14206 {
14207 struct drm_device *dev = encoder->base.dev;
14208 struct intel_encoder *source_encoder;
14209 int index_mask = 0;
14210 int entry = 0;
14211
14212 for_each_intel_encoder(dev, source_encoder) {
14213 if (encoders_cloneable(encoder, source_encoder))
14214 index_mask |= (1 << entry);
14215
14216 entry++;
14217 }
14218
14219 return index_mask;
14220 }
14221
14222 static bool has_edp_a(struct drm_device *dev)
14223 {
14224 struct drm_i915_private *dev_priv = dev->dev_private;
14225
14226 if (!IS_MOBILE(dev))
14227 return false;
14228
14229 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14230 return false;
14231
14232 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14233 return false;
14234
14235 return true;
14236 }
14237
14238 static bool intel_crt_present(struct drm_device *dev)
14239 {
14240 struct drm_i915_private *dev_priv = dev->dev_private;
14241
14242 if (INTEL_INFO(dev)->gen >= 9)
14243 return false;
14244
14245 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14246 return false;
14247
14248 if (IS_CHERRYVIEW(dev))
14249 return false;
14250
14251 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14252 return false;
14253
14254 return true;
14255 }
14256
14257 static void intel_setup_outputs(struct drm_device *dev)
14258 {
14259 struct drm_i915_private *dev_priv = dev->dev_private;
14260 struct intel_encoder *encoder;
14261 bool dpd_is_edp = false;
14262
14263 intel_lvds_init(dev);
14264
14265 if (intel_crt_present(dev))
14266 intel_crt_init(dev);
14267
14268 if (IS_BROXTON(dev)) {
14269 /*
14270 * FIXME: Broxton doesn't support port detection via the
14271 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14272 * detect the ports.
14273 */
14274 intel_ddi_init(dev, PORT_A);
14275 intel_ddi_init(dev, PORT_B);
14276 intel_ddi_init(dev, PORT_C);
14277 } else if (HAS_DDI(dev)) {
14278 int found;
14279
14280 /*
14281 * Haswell uses DDI functions to detect digital outputs.
14282 * On SKL pre-D0 the strap isn't connected, so we assume
14283 * it's there.
14284 */
14285 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14286 /* WaIgnoreDDIAStrap: skl */
14287 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14288 intel_ddi_init(dev, PORT_A);
14289
14290 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14291 * register */
14292 found = I915_READ(SFUSE_STRAP);
14293
14294 if (found & SFUSE_STRAP_DDIB_DETECTED)
14295 intel_ddi_init(dev, PORT_B);
14296 if (found & SFUSE_STRAP_DDIC_DETECTED)
14297 intel_ddi_init(dev, PORT_C);
14298 if (found & SFUSE_STRAP_DDID_DETECTED)
14299 intel_ddi_init(dev, PORT_D);
14300 /*
14301 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14302 */
14303 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14304 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14305 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14306 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14307 intel_ddi_init(dev, PORT_E);
14308
14309 } else if (HAS_PCH_SPLIT(dev)) {
14310 int found;
14311 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14312
14313 if (has_edp_a(dev))
14314 intel_dp_init(dev, DP_A, PORT_A);
14315
14316 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14317 /* PCH SDVOB multiplex with HDMIB */
14318 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14319 if (!found)
14320 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14321 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14322 intel_dp_init(dev, PCH_DP_B, PORT_B);
14323 }
14324
14325 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14326 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14327
14328 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14329 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14330
14331 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14332 intel_dp_init(dev, PCH_DP_C, PORT_C);
14333
14334 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14335 intel_dp_init(dev, PCH_DP_D, PORT_D);
14336 } else if (IS_VALLEYVIEW(dev)) {
14337 /*
14338 * The DP_DETECTED bit is the latched state of the DDC
14339 * SDA pin at boot. However since eDP doesn't require DDC
14340 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14341 * eDP ports may have been muxed to an alternate function.
14342 * Thus we can't rely on the DP_DETECTED bit alone to detect
14343 * eDP ports. Consult the VBT as well as DP_DETECTED to
14344 * detect eDP ports.
14345 */
14346 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14347 !intel_dp_is_edp(dev, PORT_B))
14348 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14349 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14350 intel_dp_is_edp(dev, PORT_B))
14351 intel_dp_init(dev, VLV_DP_B, PORT_B);
14352
14353 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14354 !intel_dp_is_edp(dev, PORT_C))
14355 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14356 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14357 intel_dp_is_edp(dev, PORT_C))
14358 intel_dp_init(dev, VLV_DP_C, PORT_C);
14359
14360 if (IS_CHERRYVIEW(dev)) {
14361 /* eDP not supported on port D, so don't check VBT */
14362 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14363 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14364 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14365 intel_dp_init(dev, CHV_DP_D, PORT_D);
14366 }
14367
14368 intel_dsi_init(dev);
14369 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14370 bool found = false;
14371
14372 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14373 DRM_DEBUG_KMS("probing SDVOB\n");
14374 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14375 if (!found && IS_G4X(dev)) {
14376 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14377 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14378 }
14379
14380 if (!found && IS_G4X(dev))
14381 intel_dp_init(dev, DP_B, PORT_B);
14382 }
14383
14384 /* Before G4X SDVOC doesn't have its own detect register */
14385
14386 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14387 DRM_DEBUG_KMS("probing SDVOC\n");
14388 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14389 }
14390
14391 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14392
14393 if (IS_G4X(dev)) {
14394 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14395 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14396 }
14397 if (IS_G4X(dev))
14398 intel_dp_init(dev, DP_C, PORT_C);
14399 }
14400
14401 if (IS_G4X(dev) &&
14402 (I915_READ(DP_D) & DP_DETECTED))
14403 intel_dp_init(dev, DP_D, PORT_D);
14404 } else if (IS_GEN2(dev))
14405 intel_dvo_init(dev);
14406
14407 if (SUPPORTS_TV(dev))
14408 intel_tv_init(dev);
14409
14410 intel_psr_init(dev);
14411
14412 for_each_intel_encoder(dev, encoder) {
14413 encoder->base.possible_crtcs = encoder->crtc_mask;
14414 encoder->base.possible_clones =
14415 intel_encoder_clones(encoder);
14416 }
14417
14418 intel_init_pch_refclk(dev);
14419
14420 drm_helper_move_panel_connectors_to_head(dev);
14421 }
14422
14423 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14424 {
14425 struct drm_device *dev = fb->dev;
14426 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14427
14428 drm_framebuffer_cleanup(fb);
14429 mutex_lock(&dev->struct_mutex);
14430 WARN_ON(!intel_fb->obj->framebuffer_references--);
14431 drm_gem_object_unreference(&intel_fb->obj->base);
14432 mutex_unlock(&dev->struct_mutex);
14433 kfree(intel_fb);
14434 }
14435
14436 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14437 struct drm_file *file,
14438 unsigned int *handle)
14439 {
14440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14441 struct drm_i915_gem_object *obj = intel_fb->obj;
14442
14443 if (obj->userptr.mm) {
14444 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14445 return -EINVAL;
14446 }
14447
14448 return drm_gem_handle_create(file, &obj->base, handle);
14449 }
14450
14451 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14452 struct drm_file *file,
14453 unsigned flags, unsigned color,
14454 struct drm_clip_rect *clips,
14455 unsigned num_clips)
14456 {
14457 struct drm_device *dev = fb->dev;
14458 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14459 struct drm_i915_gem_object *obj = intel_fb->obj;
14460
14461 mutex_lock(&dev->struct_mutex);
14462 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14463 mutex_unlock(&dev->struct_mutex);
14464
14465 return 0;
14466 }
14467
14468 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14469 .destroy = intel_user_framebuffer_destroy,
14470 .create_handle = intel_user_framebuffer_create_handle,
14471 .dirty = intel_user_framebuffer_dirty,
14472 };
14473
14474 static
14475 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14476 uint32_t pixel_format)
14477 {
14478 u32 gen = INTEL_INFO(dev)->gen;
14479
14480 if (gen >= 9) {
14481 /* "The stride in bytes must not exceed the of the size of 8K
14482 * pixels and 32K bytes."
14483 */
14484 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14485 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14486 return 32*1024;
14487 } else if (gen >= 4) {
14488 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14489 return 16*1024;
14490 else
14491 return 32*1024;
14492 } else if (gen >= 3) {
14493 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14494 return 8*1024;
14495 else
14496 return 16*1024;
14497 } else {
14498 /* XXX DSPC is limited to 4k tiled */
14499 return 8*1024;
14500 }
14501 }
14502
14503 static int intel_framebuffer_init(struct drm_device *dev,
14504 struct intel_framebuffer *intel_fb,
14505 struct drm_mode_fb_cmd2 *mode_cmd,
14506 struct drm_i915_gem_object *obj)
14507 {
14508 unsigned int aligned_height;
14509 int ret;
14510 u32 pitch_limit, stride_alignment;
14511
14512 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14513
14514 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14515 /* Enforce that fb modifier and tiling mode match, but only for
14516 * X-tiled. This is needed for FBC. */
14517 if (!!(obj->tiling_mode == I915_TILING_X) !=
14518 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14519 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14520 return -EINVAL;
14521 }
14522 } else {
14523 if (obj->tiling_mode == I915_TILING_X)
14524 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14525 else if (obj->tiling_mode == I915_TILING_Y) {
14526 DRM_DEBUG("No Y tiling for legacy addfb\n");
14527 return -EINVAL;
14528 }
14529 }
14530
14531 /* Passed in modifier sanity checking. */
14532 switch (mode_cmd->modifier[0]) {
14533 case I915_FORMAT_MOD_Y_TILED:
14534 case I915_FORMAT_MOD_Yf_TILED:
14535 if (INTEL_INFO(dev)->gen < 9) {
14536 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14537 mode_cmd->modifier[0]);
14538 return -EINVAL;
14539 }
14540 case DRM_FORMAT_MOD_NONE:
14541 case I915_FORMAT_MOD_X_TILED:
14542 break;
14543 default:
14544 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14545 mode_cmd->modifier[0]);
14546 return -EINVAL;
14547 }
14548
14549 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14550 mode_cmd->pixel_format);
14551 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14552 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14553 mode_cmd->pitches[0], stride_alignment);
14554 return -EINVAL;
14555 }
14556
14557 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14558 mode_cmd->pixel_format);
14559 if (mode_cmd->pitches[0] > pitch_limit) {
14560 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14561 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14562 "tiled" : "linear",
14563 mode_cmd->pitches[0], pitch_limit);
14564 return -EINVAL;
14565 }
14566
14567 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14568 mode_cmd->pitches[0] != obj->stride) {
14569 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14570 mode_cmd->pitches[0], obj->stride);
14571 return -EINVAL;
14572 }
14573
14574 /* Reject formats not supported by any plane early. */
14575 switch (mode_cmd->pixel_format) {
14576 case DRM_FORMAT_C8:
14577 case DRM_FORMAT_RGB565:
14578 case DRM_FORMAT_XRGB8888:
14579 case DRM_FORMAT_ARGB8888:
14580 break;
14581 case DRM_FORMAT_XRGB1555:
14582 if (INTEL_INFO(dev)->gen > 3) {
14583 DRM_DEBUG("unsupported pixel format: %s\n",
14584 drm_get_format_name(mode_cmd->pixel_format));
14585 return -EINVAL;
14586 }
14587 break;
14588 case DRM_FORMAT_ABGR8888:
14589 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14590 DRM_DEBUG("unsupported pixel format: %s\n",
14591 drm_get_format_name(mode_cmd->pixel_format));
14592 return -EINVAL;
14593 }
14594 break;
14595 case DRM_FORMAT_XBGR8888:
14596 case DRM_FORMAT_XRGB2101010:
14597 case DRM_FORMAT_XBGR2101010:
14598 if (INTEL_INFO(dev)->gen < 4) {
14599 DRM_DEBUG("unsupported pixel format: %s\n",
14600 drm_get_format_name(mode_cmd->pixel_format));
14601 return -EINVAL;
14602 }
14603 break;
14604 case DRM_FORMAT_ABGR2101010:
14605 if (!IS_VALLEYVIEW(dev)) {
14606 DRM_DEBUG("unsupported pixel format: %s\n",
14607 drm_get_format_name(mode_cmd->pixel_format));
14608 return -EINVAL;
14609 }
14610 break;
14611 case DRM_FORMAT_YUYV:
14612 case DRM_FORMAT_UYVY:
14613 case DRM_FORMAT_YVYU:
14614 case DRM_FORMAT_VYUY:
14615 if (INTEL_INFO(dev)->gen < 5) {
14616 DRM_DEBUG("unsupported pixel format: %s\n",
14617 drm_get_format_name(mode_cmd->pixel_format));
14618 return -EINVAL;
14619 }
14620 break;
14621 default:
14622 DRM_DEBUG("unsupported pixel format: %s\n",
14623 drm_get_format_name(mode_cmd->pixel_format));
14624 return -EINVAL;
14625 }
14626
14627 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14628 if (mode_cmd->offsets[0] != 0)
14629 return -EINVAL;
14630
14631 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14632 mode_cmd->pixel_format,
14633 mode_cmd->modifier[0]);
14634 /* FIXME drm helper for size checks (especially planar formats)? */
14635 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14636 return -EINVAL;
14637
14638 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14639 intel_fb->obj = obj;
14640 intel_fb->obj->framebuffer_references++;
14641
14642 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14643 if (ret) {
14644 DRM_ERROR("framebuffer init failed %d\n", ret);
14645 return ret;
14646 }
14647
14648 return 0;
14649 }
14650
14651 static struct drm_framebuffer *
14652 intel_user_framebuffer_create(struct drm_device *dev,
14653 struct drm_file *filp,
14654 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14655 {
14656 struct drm_framebuffer *fb;
14657 struct drm_i915_gem_object *obj;
14658 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14659
14660 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14661 mode_cmd.handles[0]));
14662 if (&obj->base == NULL)
14663 return ERR_PTR(-ENOENT);
14664
14665 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14666 if (IS_ERR(fb))
14667 drm_gem_object_unreference_unlocked(&obj->base);
14668
14669 return fb;
14670 }
14671
14672 #ifndef CONFIG_DRM_FBDEV_EMULATION
14673 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14674 {
14675 }
14676 #endif
14677
14678 static const struct drm_mode_config_funcs intel_mode_funcs = {
14679 .fb_create = intel_user_framebuffer_create,
14680 .output_poll_changed = intel_fbdev_output_poll_changed,
14681 .atomic_check = intel_atomic_check,
14682 .atomic_commit = intel_atomic_commit,
14683 .atomic_state_alloc = intel_atomic_state_alloc,
14684 .atomic_state_clear = intel_atomic_state_clear,
14685 };
14686
14687 /* Set up chip specific display functions */
14688 static void intel_init_display(struct drm_device *dev)
14689 {
14690 struct drm_i915_private *dev_priv = dev->dev_private;
14691
14692 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14693 dev_priv->display.find_dpll = g4x_find_best_dpll;
14694 else if (IS_CHERRYVIEW(dev))
14695 dev_priv->display.find_dpll = chv_find_best_dpll;
14696 else if (IS_VALLEYVIEW(dev))
14697 dev_priv->display.find_dpll = vlv_find_best_dpll;
14698 else if (IS_PINEVIEW(dev))
14699 dev_priv->display.find_dpll = pnv_find_best_dpll;
14700 else
14701 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14702
14703 if (INTEL_INFO(dev)->gen >= 9) {
14704 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14705 dev_priv->display.get_initial_plane_config =
14706 skylake_get_initial_plane_config;
14707 dev_priv->display.crtc_compute_clock =
14708 haswell_crtc_compute_clock;
14709 dev_priv->display.crtc_enable = haswell_crtc_enable;
14710 dev_priv->display.crtc_disable = haswell_crtc_disable;
14711 dev_priv->display.update_primary_plane =
14712 skylake_update_primary_plane;
14713 } else if (HAS_DDI(dev)) {
14714 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14715 dev_priv->display.get_initial_plane_config =
14716 ironlake_get_initial_plane_config;
14717 dev_priv->display.crtc_compute_clock =
14718 haswell_crtc_compute_clock;
14719 dev_priv->display.crtc_enable = haswell_crtc_enable;
14720 dev_priv->display.crtc_disable = haswell_crtc_disable;
14721 dev_priv->display.update_primary_plane =
14722 ironlake_update_primary_plane;
14723 } else if (HAS_PCH_SPLIT(dev)) {
14724 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14725 dev_priv->display.get_initial_plane_config =
14726 ironlake_get_initial_plane_config;
14727 dev_priv->display.crtc_compute_clock =
14728 ironlake_crtc_compute_clock;
14729 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14730 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14731 dev_priv->display.update_primary_plane =
14732 ironlake_update_primary_plane;
14733 } else if (IS_VALLEYVIEW(dev)) {
14734 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14735 dev_priv->display.get_initial_plane_config =
14736 i9xx_get_initial_plane_config;
14737 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14738 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14739 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14740 dev_priv->display.update_primary_plane =
14741 i9xx_update_primary_plane;
14742 } else {
14743 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14744 dev_priv->display.get_initial_plane_config =
14745 i9xx_get_initial_plane_config;
14746 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14747 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14748 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14749 dev_priv->display.update_primary_plane =
14750 i9xx_update_primary_plane;
14751 }
14752
14753 /* Returns the core display clock speed */
14754 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14755 dev_priv->display.get_display_clock_speed =
14756 skylake_get_display_clock_speed;
14757 else if (IS_BROXTON(dev))
14758 dev_priv->display.get_display_clock_speed =
14759 broxton_get_display_clock_speed;
14760 else if (IS_BROADWELL(dev))
14761 dev_priv->display.get_display_clock_speed =
14762 broadwell_get_display_clock_speed;
14763 else if (IS_HASWELL(dev))
14764 dev_priv->display.get_display_clock_speed =
14765 haswell_get_display_clock_speed;
14766 else if (IS_VALLEYVIEW(dev))
14767 dev_priv->display.get_display_clock_speed =
14768 valleyview_get_display_clock_speed;
14769 else if (IS_GEN5(dev))
14770 dev_priv->display.get_display_clock_speed =
14771 ilk_get_display_clock_speed;
14772 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14773 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14774 dev_priv->display.get_display_clock_speed =
14775 i945_get_display_clock_speed;
14776 else if (IS_GM45(dev))
14777 dev_priv->display.get_display_clock_speed =
14778 gm45_get_display_clock_speed;
14779 else if (IS_CRESTLINE(dev))
14780 dev_priv->display.get_display_clock_speed =
14781 i965gm_get_display_clock_speed;
14782 else if (IS_PINEVIEW(dev))
14783 dev_priv->display.get_display_clock_speed =
14784 pnv_get_display_clock_speed;
14785 else if (IS_G33(dev) || IS_G4X(dev))
14786 dev_priv->display.get_display_clock_speed =
14787 g33_get_display_clock_speed;
14788 else if (IS_I915G(dev))
14789 dev_priv->display.get_display_clock_speed =
14790 i915_get_display_clock_speed;
14791 else if (IS_I945GM(dev) || IS_845G(dev))
14792 dev_priv->display.get_display_clock_speed =
14793 i9xx_misc_get_display_clock_speed;
14794 else if (IS_PINEVIEW(dev))
14795 dev_priv->display.get_display_clock_speed =
14796 pnv_get_display_clock_speed;
14797 else if (IS_I915GM(dev))
14798 dev_priv->display.get_display_clock_speed =
14799 i915gm_get_display_clock_speed;
14800 else if (IS_I865G(dev))
14801 dev_priv->display.get_display_clock_speed =
14802 i865_get_display_clock_speed;
14803 else if (IS_I85X(dev))
14804 dev_priv->display.get_display_clock_speed =
14805 i85x_get_display_clock_speed;
14806 else { /* 830 */
14807 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14808 dev_priv->display.get_display_clock_speed =
14809 i830_get_display_clock_speed;
14810 }
14811
14812 if (IS_GEN5(dev)) {
14813 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14814 } else if (IS_GEN6(dev)) {
14815 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14816 } else if (IS_IVYBRIDGE(dev)) {
14817 /* FIXME: detect B0+ stepping and use auto training */
14818 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14819 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14820 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14821 if (IS_BROADWELL(dev)) {
14822 dev_priv->display.modeset_commit_cdclk =
14823 broadwell_modeset_commit_cdclk;
14824 dev_priv->display.modeset_calc_cdclk =
14825 broadwell_modeset_calc_cdclk;
14826 }
14827 } else if (IS_VALLEYVIEW(dev)) {
14828 dev_priv->display.modeset_commit_cdclk =
14829 valleyview_modeset_commit_cdclk;
14830 dev_priv->display.modeset_calc_cdclk =
14831 valleyview_modeset_calc_cdclk;
14832 } else if (IS_BROXTON(dev)) {
14833 dev_priv->display.modeset_commit_cdclk =
14834 broxton_modeset_commit_cdclk;
14835 dev_priv->display.modeset_calc_cdclk =
14836 broxton_modeset_calc_cdclk;
14837 }
14838
14839 switch (INTEL_INFO(dev)->gen) {
14840 case 2:
14841 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14842 break;
14843
14844 case 3:
14845 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14846 break;
14847
14848 case 4:
14849 case 5:
14850 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14851 break;
14852
14853 case 6:
14854 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14855 break;
14856 case 7:
14857 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14858 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14859 break;
14860 case 9:
14861 /* Drop through - unsupported since execlist only. */
14862 default:
14863 /* Default just returns -ENODEV to indicate unsupported */
14864 dev_priv->display.queue_flip = intel_default_queue_flip;
14865 }
14866
14867 mutex_init(&dev_priv->pps_mutex);
14868 }
14869
14870 /*
14871 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14872 * resume, or other times. This quirk makes sure that's the case for
14873 * affected systems.
14874 */
14875 static void quirk_pipea_force(struct drm_device *dev)
14876 {
14877 struct drm_i915_private *dev_priv = dev->dev_private;
14878
14879 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14880 DRM_INFO("applying pipe a force quirk\n");
14881 }
14882
14883 static void quirk_pipeb_force(struct drm_device *dev)
14884 {
14885 struct drm_i915_private *dev_priv = dev->dev_private;
14886
14887 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14888 DRM_INFO("applying pipe b force quirk\n");
14889 }
14890
14891 /*
14892 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14893 */
14894 static void quirk_ssc_force_disable(struct drm_device *dev)
14895 {
14896 struct drm_i915_private *dev_priv = dev->dev_private;
14897 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14898 DRM_INFO("applying lvds SSC disable quirk\n");
14899 }
14900
14901 /*
14902 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14903 * brightness value
14904 */
14905 static void quirk_invert_brightness(struct drm_device *dev)
14906 {
14907 struct drm_i915_private *dev_priv = dev->dev_private;
14908 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14909 DRM_INFO("applying inverted panel brightness quirk\n");
14910 }
14911
14912 /* Some VBT's incorrectly indicate no backlight is present */
14913 static void quirk_backlight_present(struct drm_device *dev)
14914 {
14915 struct drm_i915_private *dev_priv = dev->dev_private;
14916 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14917 DRM_INFO("applying backlight present quirk\n");
14918 }
14919
14920 struct intel_quirk {
14921 int device;
14922 int subsystem_vendor;
14923 int subsystem_device;
14924 void (*hook)(struct drm_device *dev);
14925 };
14926
14927 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14928 struct intel_dmi_quirk {
14929 void (*hook)(struct drm_device *dev);
14930 const struct dmi_system_id (*dmi_id_list)[];
14931 };
14932
14933 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14934 {
14935 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14936 return 1;
14937 }
14938
14939 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14940 {
14941 .dmi_id_list = &(const struct dmi_system_id[]) {
14942 {
14943 .callback = intel_dmi_reverse_brightness,
14944 .ident = "NCR Corporation",
14945 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14946 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14947 },
14948 },
14949 { } /* terminating entry */
14950 },
14951 .hook = quirk_invert_brightness,
14952 },
14953 };
14954
14955 static struct intel_quirk intel_quirks[] = {
14956 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14957 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14958
14959 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14960 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14961
14962 /* 830 needs to leave pipe A & dpll A up */
14963 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14964
14965 /* 830 needs to leave pipe B & dpll B up */
14966 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14967
14968 /* Lenovo U160 cannot use SSC on LVDS */
14969 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14970
14971 /* Sony Vaio Y cannot use SSC on LVDS */
14972 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14973
14974 /* Acer Aspire 5734Z must invert backlight brightness */
14975 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14976
14977 /* Acer/eMachines G725 */
14978 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14979
14980 /* Acer/eMachines e725 */
14981 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14982
14983 /* Acer/Packard Bell NCL20 */
14984 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14985
14986 /* Acer Aspire 4736Z */
14987 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14988
14989 /* Acer Aspire 5336 */
14990 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14991
14992 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14993 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14994
14995 /* Acer C720 Chromebook (Core i3 4005U) */
14996 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14997
14998 /* Apple Macbook 2,1 (Core 2 T7400) */
14999 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15000
15001 /* Apple Macbook 4,1 */
15002 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15003
15004 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15005 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15006
15007 /* HP Chromebook 14 (Celeron 2955U) */
15008 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15009
15010 /* Dell Chromebook 11 */
15011 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15012
15013 /* Dell Chromebook 11 (2015 version) */
15014 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15015 };
15016
15017 static void intel_init_quirks(struct drm_device *dev)
15018 {
15019 struct pci_dev *d = dev->pdev;
15020 int i;
15021
15022 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15023 struct intel_quirk *q = &intel_quirks[i];
15024
15025 if (d->device == q->device &&
15026 (d->subsystem_vendor == q->subsystem_vendor ||
15027 q->subsystem_vendor == PCI_ANY_ID) &&
15028 (d->subsystem_device == q->subsystem_device ||
15029 q->subsystem_device == PCI_ANY_ID))
15030 q->hook(dev);
15031 }
15032 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15033 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15034 intel_dmi_quirks[i].hook(dev);
15035 }
15036 }
15037
15038 /* Disable the VGA plane that we never use */
15039 static void i915_disable_vga(struct drm_device *dev)
15040 {
15041 struct drm_i915_private *dev_priv = dev->dev_private;
15042 u8 sr1;
15043 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15044
15045 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15046 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15047 outb(SR01, VGA_SR_INDEX);
15048 sr1 = inb(VGA_SR_DATA);
15049 outb(sr1 | 1<<5, VGA_SR_DATA);
15050 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15051 udelay(300);
15052
15053 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15054 POSTING_READ(vga_reg);
15055 }
15056
15057 void intel_modeset_init_hw(struct drm_device *dev)
15058 {
15059 intel_update_cdclk(dev);
15060 intel_prepare_ddi(dev);
15061 intel_init_clock_gating(dev);
15062 intel_enable_gt_powersave(dev);
15063 }
15064
15065 void intel_modeset_init(struct drm_device *dev)
15066 {
15067 struct drm_i915_private *dev_priv = dev->dev_private;
15068 int sprite, ret;
15069 enum pipe pipe;
15070 struct intel_crtc *crtc;
15071
15072 drm_mode_config_init(dev);
15073
15074 dev->mode_config.min_width = 0;
15075 dev->mode_config.min_height = 0;
15076
15077 dev->mode_config.preferred_depth = 24;
15078 dev->mode_config.prefer_shadow = 1;
15079
15080 dev->mode_config.allow_fb_modifiers = true;
15081
15082 dev->mode_config.funcs = &intel_mode_funcs;
15083
15084 intel_init_quirks(dev);
15085
15086 intel_init_pm(dev);
15087
15088 if (INTEL_INFO(dev)->num_pipes == 0)
15089 return;
15090
15091 /*
15092 * There may be no VBT; and if the BIOS enabled SSC we can
15093 * just keep using it to avoid unnecessary flicker. Whereas if the
15094 * BIOS isn't using it, don't assume it will work even if the VBT
15095 * indicates as much.
15096 */
15097 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15098 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15099 DREF_SSC1_ENABLE);
15100
15101 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15102 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15103 bios_lvds_use_ssc ? "en" : "dis",
15104 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15105 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15106 }
15107 }
15108
15109 intel_init_display(dev);
15110 intel_init_audio(dev);
15111
15112 if (IS_GEN2(dev)) {
15113 dev->mode_config.max_width = 2048;
15114 dev->mode_config.max_height = 2048;
15115 } else if (IS_GEN3(dev)) {
15116 dev->mode_config.max_width = 4096;
15117 dev->mode_config.max_height = 4096;
15118 } else {
15119 dev->mode_config.max_width = 8192;
15120 dev->mode_config.max_height = 8192;
15121 }
15122
15123 if (IS_845G(dev) || IS_I865G(dev)) {
15124 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15125 dev->mode_config.cursor_height = 1023;
15126 } else if (IS_GEN2(dev)) {
15127 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15128 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15129 } else {
15130 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15131 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15132 }
15133
15134 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15135
15136 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15137 INTEL_INFO(dev)->num_pipes,
15138 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15139
15140 for_each_pipe(dev_priv, pipe) {
15141 intel_crtc_init(dev, pipe);
15142 for_each_sprite(dev_priv, pipe, sprite) {
15143 ret = intel_plane_init(dev, pipe, sprite);
15144 if (ret)
15145 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15146 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15147 }
15148 }
15149
15150 intel_update_czclk(dev_priv);
15151 intel_update_cdclk(dev);
15152
15153 intel_shared_dpll_init(dev);
15154
15155 /* Just disable it once at startup */
15156 i915_disable_vga(dev);
15157 intel_setup_outputs(dev);
15158
15159 drm_modeset_lock_all(dev);
15160 intel_modeset_setup_hw_state(dev);
15161 drm_modeset_unlock_all(dev);
15162
15163 for_each_intel_crtc(dev, crtc) {
15164 struct intel_initial_plane_config plane_config = {};
15165
15166 if (!crtc->active)
15167 continue;
15168
15169 /*
15170 * Note that reserving the BIOS fb up front prevents us
15171 * from stuffing other stolen allocations like the ring
15172 * on top. This prevents some ugliness at boot time, and
15173 * can even allow for smooth boot transitions if the BIOS
15174 * fb is large enough for the active pipe configuration.
15175 */
15176 dev_priv->display.get_initial_plane_config(crtc,
15177 &plane_config);
15178
15179 /*
15180 * If the fb is shared between multiple heads, we'll
15181 * just get the first one.
15182 */
15183 intel_find_initial_plane_obj(crtc, &plane_config);
15184 }
15185 }
15186
15187 static void intel_enable_pipe_a(struct drm_device *dev)
15188 {
15189 struct intel_connector *connector;
15190 struct drm_connector *crt = NULL;
15191 struct intel_load_detect_pipe load_detect_temp;
15192 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15193
15194 /* We can't just switch on the pipe A, we need to set things up with a
15195 * proper mode and output configuration. As a gross hack, enable pipe A
15196 * by enabling the load detect pipe once. */
15197 for_each_intel_connector(dev, connector) {
15198 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15199 crt = &connector->base;
15200 break;
15201 }
15202 }
15203
15204 if (!crt)
15205 return;
15206
15207 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15208 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15209 }
15210
15211 static bool
15212 intel_check_plane_mapping(struct intel_crtc *crtc)
15213 {
15214 struct drm_device *dev = crtc->base.dev;
15215 struct drm_i915_private *dev_priv = dev->dev_private;
15216 u32 val;
15217
15218 if (INTEL_INFO(dev)->num_pipes == 1)
15219 return true;
15220
15221 val = I915_READ(DSPCNTR(!crtc->plane));
15222
15223 if ((val & DISPLAY_PLANE_ENABLE) &&
15224 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15225 return false;
15226
15227 return true;
15228 }
15229
15230 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15231 {
15232 struct drm_device *dev = crtc->base.dev;
15233 struct intel_encoder *encoder;
15234
15235 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15236 return true;
15237
15238 return false;
15239 }
15240
15241 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15242 {
15243 struct drm_device *dev = crtc->base.dev;
15244 struct drm_i915_private *dev_priv = dev->dev_private;
15245 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15246
15247 /* Clear any frame start delays used for debugging left by the BIOS */
15248 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15249
15250 /* restore vblank interrupts to correct state */
15251 drm_crtc_vblank_reset(&crtc->base);
15252 if (crtc->active) {
15253 struct intel_plane *plane;
15254
15255 drm_crtc_vblank_on(&crtc->base);
15256
15257 /* Disable everything but the primary plane */
15258 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15259 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15260 continue;
15261
15262 plane->disable_plane(&plane->base, &crtc->base);
15263 }
15264 }
15265
15266 /* We need to sanitize the plane -> pipe mapping first because this will
15267 * disable the crtc (and hence change the state) if it is wrong. Note
15268 * that gen4+ has a fixed plane -> pipe mapping. */
15269 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15270 bool plane;
15271
15272 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15273 crtc->base.base.id);
15274
15275 /* Pipe has the wrong plane attached and the plane is active.
15276 * Temporarily change the plane mapping and disable everything
15277 * ... */
15278 plane = crtc->plane;
15279 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15280 crtc->plane = !plane;
15281 intel_crtc_disable_noatomic(&crtc->base);
15282 crtc->plane = plane;
15283 }
15284
15285 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15286 crtc->pipe == PIPE_A && !crtc->active) {
15287 /* BIOS forgot to enable pipe A, this mostly happens after
15288 * resume. Force-enable the pipe to fix this, the update_dpms
15289 * call below we restore the pipe to the right state, but leave
15290 * the required bits on. */
15291 intel_enable_pipe_a(dev);
15292 }
15293
15294 /* Adjust the state of the output pipe according to whether we
15295 * have active connectors/encoders. */
15296 if (!intel_crtc_has_encoders(crtc))
15297 intel_crtc_disable_noatomic(&crtc->base);
15298
15299 if (crtc->active != crtc->base.state->active) {
15300 struct intel_encoder *encoder;
15301
15302 /* This can happen either due to bugs in the get_hw_state
15303 * functions or because of calls to intel_crtc_disable_noatomic,
15304 * or because the pipe is force-enabled due to the
15305 * pipe A quirk. */
15306 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15307 crtc->base.base.id,
15308 crtc->base.state->enable ? "enabled" : "disabled",
15309 crtc->active ? "enabled" : "disabled");
15310
15311 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15312 crtc->base.state->active = crtc->active;
15313 crtc->base.enabled = crtc->active;
15314
15315 /* Because we only establish the connector -> encoder ->
15316 * crtc links if something is active, this means the
15317 * crtc is now deactivated. Break the links. connector
15318 * -> encoder links are only establish when things are
15319 * actually up, hence no need to break them. */
15320 WARN_ON(crtc->active);
15321
15322 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15323 encoder->base.crtc = NULL;
15324 }
15325
15326 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15327 /*
15328 * We start out with underrun reporting disabled to avoid races.
15329 * For correct bookkeeping mark this on active crtcs.
15330 *
15331 * Also on gmch platforms we dont have any hardware bits to
15332 * disable the underrun reporting. Which means we need to start
15333 * out with underrun reporting disabled also on inactive pipes,
15334 * since otherwise we'll complain about the garbage we read when
15335 * e.g. coming up after runtime pm.
15336 *
15337 * No protection against concurrent access is required - at
15338 * worst a fifo underrun happens which also sets this to false.
15339 */
15340 crtc->cpu_fifo_underrun_disabled = true;
15341 crtc->pch_fifo_underrun_disabled = true;
15342 }
15343 }
15344
15345 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15346 {
15347 struct intel_connector *connector;
15348 struct drm_device *dev = encoder->base.dev;
15349 bool active = false;
15350
15351 /* We need to check both for a crtc link (meaning that the
15352 * encoder is active and trying to read from a pipe) and the
15353 * pipe itself being active. */
15354 bool has_active_crtc = encoder->base.crtc &&
15355 to_intel_crtc(encoder->base.crtc)->active;
15356
15357 for_each_intel_connector(dev, connector) {
15358 if (connector->base.encoder != &encoder->base)
15359 continue;
15360
15361 active = true;
15362 break;
15363 }
15364
15365 if (active && !has_active_crtc) {
15366 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15367 encoder->base.base.id,
15368 encoder->base.name);
15369
15370 /* Connector is active, but has no active pipe. This is
15371 * fallout from our resume register restoring. Disable
15372 * the encoder manually again. */
15373 if (encoder->base.crtc) {
15374 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15375 encoder->base.base.id,
15376 encoder->base.name);
15377 encoder->disable(encoder);
15378 if (encoder->post_disable)
15379 encoder->post_disable(encoder);
15380 }
15381 encoder->base.crtc = NULL;
15382
15383 /* Inconsistent output/port/pipe state happens presumably due to
15384 * a bug in one of the get_hw_state functions. Or someplace else
15385 * in our code, like the register restore mess on resume. Clamp
15386 * things to off as a safer default. */
15387 for_each_intel_connector(dev, connector) {
15388 if (connector->encoder != encoder)
15389 continue;
15390 connector->base.dpms = DRM_MODE_DPMS_OFF;
15391 connector->base.encoder = NULL;
15392 }
15393 }
15394 /* Enabled encoders without active connectors will be fixed in
15395 * the crtc fixup. */
15396 }
15397
15398 void i915_redisable_vga_power_on(struct drm_device *dev)
15399 {
15400 struct drm_i915_private *dev_priv = dev->dev_private;
15401 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15402
15403 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15404 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15405 i915_disable_vga(dev);
15406 }
15407 }
15408
15409 void i915_redisable_vga(struct drm_device *dev)
15410 {
15411 struct drm_i915_private *dev_priv = dev->dev_private;
15412
15413 /* This function can be called both from intel_modeset_setup_hw_state or
15414 * at a very early point in our resume sequence, where the power well
15415 * structures are not yet restored. Since this function is at a very
15416 * paranoid "someone might have enabled VGA while we were not looking"
15417 * level, just check if the power well is enabled instead of trying to
15418 * follow the "don't touch the power well if we don't need it" policy
15419 * the rest of the driver uses. */
15420 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15421 return;
15422
15423 i915_redisable_vga_power_on(dev);
15424 }
15425
15426 static bool primary_get_hw_state(struct intel_plane *plane)
15427 {
15428 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15429
15430 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15431 }
15432
15433 /* FIXME read out full plane state for all planes */
15434 static void readout_plane_state(struct intel_crtc *crtc)
15435 {
15436 struct drm_plane *primary = crtc->base.primary;
15437 struct intel_plane_state *plane_state =
15438 to_intel_plane_state(primary->state);
15439
15440 plane_state->visible = crtc->active &&
15441 primary_get_hw_state(to_intel_plane(primary));
15442
15443 if (plane_state->visible)
15444 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15445 }
15446
15447 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15448 {
15449 struct drm_i915_private *dev_priv = dev->dev_private;
15450 enum pipe pipe;
15451 struct intel_crtc *crtc;
15452 struct intel_encoder *encoder;
15453 struct intel_connector *connector;
15454 int i;
15455
15456 for_each_intel_crtc(dev, crtc) {
15457 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15458 memset(crtc->config, 0, sizeof(*crtc->config));
15459 crtc->config->base.crtc = &crtc->base;
15460
15461 crtc->active = dev_priv->display.get_pipe_config(crtc,
15462 crtc->config);
15463
15464 crtc->base.state->active = crtc->active;
15465 crtc->base.enabled = crtc->active;
15466
15467 readout_plane_state(crtc);
15468
15469 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15470 crtc->base.base.id,
15471 crtc->active ? "enabled" : "disabled");
15472 }
15473
15474 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15475 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15476
15477 pll->on = pll->get_hw_state(dev_priv, pll,
15478 &pll->config.hw_state);
15479 pll->active = 0;
15480 pll->config.crtc_mask = 0;
15481 for_each_intel_crtc(dev, crtc) {
15482 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15483 pll->active++;
15484 pll->config.crtc_mask |= 1 << crtc->pipe;
15485 }
15486 }
15487
15488 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15489 pll->name, pll->config.crtc_mask, pll->on);
15490
15491 if (pll->config.crtc_mask)
15492 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15493 }
15494
15495 for_each_intel_encoder(dev, encoder) {
15496 pipe = 0;
15497
15498 if (encoder->get_hw_state(encoder, &pipe)) {
15499 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15500 encoder->base.crtc = &crtc->base;
15501 encoder->get_config(encoder, crtc->config);
15502 } else {
15503 encoder->base.crtc = NULL;
15504 }
15505
15506 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15507 encoder->base.base.id,
15508 encoder->base.name,
15509 encoder->base.crtc ? "enabled" : "disabled",
15510 pipe_name(pipe));
15511 }
15512
15513 for_each_intel_connector(dev, connector) {
15514 if (connector->get_hw_state(connector)) {
15515 connector->base.dpms = DRM_MODE_DPMS_ON;
15516 connector->base.encoder = &connector->encoder->base;
15517 } else {
15518 connector->base.dpms = DRM_MODE_DPMS_OFF;
15519 connector->base.encoder = NULL;
15520 }
15521 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15522 connector->base.base.id,
15523 connector->base.name,
15524 connector->base.encoder ? "enabled" : "disabled");
15525 }
15526
15527 for_each_intel_crtc(dev, crtc) {
15528 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15529
15530 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15531 if (crtc->base.state->active) {
15532 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15533 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15534 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15535
15536 /*
15537 * The initial mode needs to be set in order to keep
15538 * the atomic core happy. It wants a valid mode if the
15539 * crtc's enabled, so we do the above call.
15540 *
15541 * At this point some state updated by the connectors
15542 * in their ->detect() callback has not run yet, so
15543 * no recalculation can be done yet.
15544 *
15545 * Even if we could do a recalculation and modeset
15546 * right now it would cause a double modeset if
15547 * fbdev or userspace chooses a different initial mode.
15548 *
15549 * If that happens, someone indicated they wanted a
15550 * mode change, which means it's safe to do a full
15551 * recalculation.
15552 */
15553 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15554
15555 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15556 update_scanline_offset(crtc);
15557 }
15558 }
15559 }
15560
15561 /* Scan out the current hw modeset state,
15562 * and sanitizes it to the current state
15563 */
15564 static void
15565 intel_modeset_setup_hw_state(struct drm_device *dev)
15566 {
15567 struct drm_i915_private *dev_priv = dev->dev_private;
15568 enum pipe pipe;
15569 struct intel_crtc *crtc;
15570 struct intel_encoder *encoder;
15571 int i;
15572
15573 intel_modeset_readout_hw_state(dev);
15574
15575 /* HW state is read out, now we need to sanitize this mess. */
15576 for_each_intel_encoder(dev, encoder) {
15577 intel_sanitize_encoder(encoder);
15578 }
15579
15580 for_each_pipe(dev_priv, pipe) {
15581 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15582 intel_sanitize_crtc(crtc);
15583 intel_dump_pipe_config(crtc, crtc->config,
15584 "[setup_hw_state]");
15585 }
15586
15587 intel_modeset_update_connector_atomic_state(dev);
15588
15589 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15590 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15591
15592 if (!pll->on || pll->active)
15593 continue;
15594
15595 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15596
15597 pll->disable(dev_priv, pll);
15598 pll->on = false;
15599 }
15600
15601 if (IS_VALLEYVIEW(dev))
15602 vlv_wm_get_hw_state(dev);
15603 else if (IS_GEN9(dev))
15604 skl_wm_get_hw_state(dev);
15605 else if (HAS_PCH_SPLIT(dev))
15606 ilk_wm_get_hw_state(dev);
15607
15608 for_each_intel_crtc(dev, crtc) {
15609 unsigned long put_domains;
15610
15611 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15612 if (WARN_ON(put_domains))
15613 modeset_put_power_domains(dev_priv, put_domains);
15614 }
15615 intel_display_set_init_power(dev_priv, false);
15616 }
15617
15618 void intel_display_resume(struct drm_device *dev)
15619 {
15620 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15621 struct intel_connector *conn;
15622 struct intel_plane *plane;
15623 struct drm_crtc *crtc;
15624 int ret;
15625
15626 if (!state)
15627 return;
15628
15629 state->acquire_ctx = dev->mode_config.acquire_ctx;
15630
15631 /* preserve complete old state, including dpll */
15632 intel_atomic_get_shared_dpll_state(state);
15633
15634 for_each_crtc(dev, crtc) {
15635 struct drm_crtc_state *crtc_state =
15636 drm_atomic_get_crtc_state(state, crtc);
15637
15638 ret = PTR_ERR_OR_ZERO(crtc_state);
15639 if (ret)
15640 goto err;
15641
15642 /* force a restore */
15643 crtc_state->mode_changed = true;
15644 }
15645
15646 for_each_intel_plane(dev, plane) {
15647 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15648 if (ret)
15649 goto err;
15650 }
15651
15652 for_each_intel_connector(dev, conn) {
15653 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15654 if (ret)
15655 goto err;
15656 }
15657
15658 intel_modeset_setup_hw_state(dev);
15659
15660 i915_redisable_vga(dev);
15661 ret = drm_atomic_commit(state);
15662 if (!ret)
15663 return;
15664
15665 err:
15666 DRM_ERROR("Restoring old state failed with %i\n", ret);
15667 drm_atomic_state_free(state);
15668 }
15669
15670 void intel_modeset_gem_init(struct drm_device *dev)
15671 {
15672 struct drm_crtc *c;
15673 struct drm_i915_gem_object *obj;
15674 int ret;
15675
15676 mutex_lock(&dev->struct_mutex);
15677 intel_init_gt_powersave(dev);
15678 mutex_unlock(&dev->struct_mutex);
15679
15680 intel_modeset_init_hw(dev);
15681
15682 intel_setup_overlay(dev);
15683
15684 /*
15685 * Make sure any fbs we allocated at startup are properly
15686 * pinned & fenced. When we do the allocation it's too early
15687 * for this.
15688 */
15689 for_each_crtc(dev, c) {
15690 obj = intel_fb_obj(c->primary->fb);
15691 if (obj == NULL)
15692 continue;
15693
15694 mutex_lock(&dev->struct_mutex);
15695 ret = intel_pin_and_fence_fb_obj(c->primary,
15696 c->primary->fb,
15697 c->primary->state);
15698 mutex_unlock(&dev->struct_mutex);
15699 if (ret) {
15700 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15701 to_intel_crtc(c)->pipe);
15702 drm_framebuffer_unreference(c->primary->fb);
15703 c->primary->fb = NULL;
15704 c->primary->crtc = c->primary->state->crtc = NULL;
15705 update_state_fb(c->primary);
15706 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15707 }
15708 }
15709
15710 intel_backlight_register(dev);
15711 }
15712
15713 void intel_connector_unregister(struct intel_connector *intel_connector)
15714 {
15715 struct drm_connector *connector = &intel_connector->base;
15716
15717 intel_panel_destroy_backlight(connector);
15718 drm_connector_unregister(connector);
15719 }
15720
15721 void intel_modeset_cleanup(struct drm_device *dev)
15722 {
15723 struct drm_i915_private *dev_priv = dev->dev_private;
15724 struct drm_connector *connector;
15725
15726 intel_disable_gt_powersave(dev);
15727
15728 intel_backlight_unregister(dev);
15729
15730 /*
15731 * Interrupts and polling as the first thing to avoid creating havoc.
15732 * Too much stuff here (turning of connectors, ...) would
15733 * experience fancy races otherwise.
15734 */
15735 intel_irq_uninstall(dev_priv);
15736
15737 /*
15738 * Due to the hpd irq storm handling the hotplug work can re-arm the
15739 * poll handlers. Hence disable polling after hpd handling is shut down.
15740 */
15741 drm_kms_helper_poll_fini(dev);
15742
15743 intel_unregister_dsm_handler();
15744
15745 intel_fbc_disable(dev_priv);
15746
15747 /* flush any delayed tasks or pending work */
15748 flush_scheduled_work();
15749
15750 /* destroy the backlight and sysfs files before encoders/connectors */
15751 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15752 struct intel_connector *intel_connector;
15753
15754 intel_connector = to_intel_connector(connector);
15755 intel_connector->unregister(intel_connector);
15756 }
15757
15758 drm_mode_config_cleanup(dev);
15759
15760 intel_cleanup_overlay(dev);
15761
15762 mutex_lock(&dev->struct_mutex);
15763 intel_cleanup_gt_powersave(dev);
15764 mutex_unlock(&dev->struct_mutex);
15765 }
15766
15767 /*
15768 * Return which encoder is currently attached for connector.
15769 */
15770 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15771 {
15772 return &intel_attached_encoder(connector)->base;
15773 }
15774
15775 void intel_connector_attach_encoder(struct intel_connector *connector,
15776 struct intel_encoder *encoder)
15777 {
15778 connector->encoder = encoder;
15779 drm_mode_connector_attach_encoder(&connector->base,
15780 &encoder->base);
15781 }
15782
15783 /*
15784 * set vga decode state - true == enable VGA decode
15785 */
15786 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15787 {
15788 struct drm_i915_private *dev_priv = dev->dev_private;
15789 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15790 u16 gmch_ctrl;
15791
15792 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15793 DRM_ERROR("failed to read control word\n");
15794 return -EIO;
15795 }
15796
15797 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15798 return 0;
15799
15800 if (state)
15801 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15802 else
15803 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15804
15805 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15806 DRM_ERROR("failed to write control word\n");
15807 return -EIO;
15808 }
15809
15810 return 0;
15811 }
15812
15813 struct intel_display_error_state {
15814
15815 u32 power_well_driver;
15816
15817 int num_transcoders;
15818
15819 struct intel_cursor_error_state {
15820 u32 control;
15821 u32 position;
15822 u32 base;
15823 u32 size;
15824 } cursor[I915_MAX_PIPES];
15825
15826 struct intel_pipe_error_state {
15827 bool power_domain_on;
15828 u32 source;
15829 u32 stat;
15830 } pipe[I915_MAX_PIPES];
15831
15832 struct intel_plane_error_state {
15833 u32 control;
15834 u32 stride;
15835 u32 size;
15836 u32 pos;
15837 u32 addr;
15838 u32 surface;
15839 u32 tile_offset;
15840 } plane[I915_MAX_PIPES];
15841
15842 struct intel_transcoder_error_state {
15843 bool power_domain_on;
15844 enum transcoder cpu_transcoder;
15845
15846 u32 conf;
15847
15848 u32 htotal;
15849 u32 hblank;
15850 u32 hsync;
15851 u32 vtotal;
15852 u32 vblank;
15853 u32 vsync;
15854 } transcoder[4];
15855 };
15856
15857 struct intel_display_error_state *
15858 intel_display_capture_error_state(struct drm_device *dev)
15859 {
15860 struct drm_i915_private *dev_priv = dev->dev_private;
15861 struct intel_display_error_state *error;
15862 int transcoders[] = {
15863 TRANSCODER_A,
15864 TRANSCODER_B,
15865 TRANSCODER_C,
15866 TRANSCODER_EDP,
15867 };
15868 int i;
15869
15870 if (INTEL_INFO(dev)->num_pipes == 0)
15871 return NULL;
15872
15873 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15874 if (error == NULL)
15875 return NULL;
15876
15877 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15878 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15879
15880 for_each_pipe(dev_priv, i) {
15881 error->pipe[i].power_domain_on =
15882 __intel_display_power_is_enabled(dev_priv,
15883 POWER_DOMAIN_PIPE(i));
15884 if (!error->pipe[i].power_domain_on)
15885 continue;
15886
15887 error->cursor[i].control = I915_READ(CURCNTR(i));
15888 error->cursor[i].position = I915_READ(CURPOS(i));
15889 error->cursor[i].base = I915_READ(CURBASE(i));
15890
15891 error->plane[i].control = I915_READ(DSPCNTR(i));
15892 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15893 if (INTEL_INFO(dev)->gen <= 3) {
15894 error->plane[i].size = I915_READ(DSPSIZE(i));
15895 error->plane[i].pos = I915_READ(DSPPOS(i));
15896 }
15897 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15898 error->plane[i].addr = I915_READ(DSPADDR(i));
15899 if (INTEL_INFO(dev)->gen >= 4) {
15900 error->plane[i].surface = I915_READ(DSPSURF(i));
15901 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15902 }
15903
15904 error->pipe[i].source = I915_READ(PIPESRC(i));
15905
15906 if (HAS_GMCH_DISPLAY(dev))
15907 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15908 }
15909
15910 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15911 if (HAS_DDI(dev_priv->dev))
15912 error->num_transcoders++; /* Account for eDP. */
15913
15914 for (i = 0; i < error->num_transcoders; i++) {
15915 enum transcoder cpu_transcoder = transcoders[i];
15916
15917 error->transcoder[i].power_domain_on =
15918 __intel_display_power_is_enabled(dev_priv,
15919 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15920 if (!error->transcoder[i].power_domain_on)
15921 continue;
15922
15923 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15924
15925 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15926 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15927 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15928 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15929 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15930 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15931 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15932 }
15933
15934 return error;
15935 }
15936
15937 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15938
15939 void
15940 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15941 struct drm_device *dev,
15942 struct intel_display_error_state *error)
15943 {
15944 struct drm_i915_private *dev_priv = dev->dev_private;
15945 int i;
15946
15947 if (!error)
15948 return;
15949
15950 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15951 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15952 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15953 error->power_well_driver);
15954 for_each_pipe(dev_priv, i) {
15955 err_printf(m, "Pipe [%d]:\n", i);
15956 err_printf(m, " Power: %s\n",
15957 error->pipe[i].power_domain_on ? "on" : "off");
15958 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15959 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15960
15961 err_printf(m, "Plane [%d]:\n", i);
15962 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15963 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15964 if (INTEL_INFO(dev)->gen <= 3) {
15965 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15966 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15967 }
15968 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15969 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15970 if (INTEL_INFO(dev)->gen >= 4) {
15971 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15972 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15973 }
15974
15975 err_printf(m, "Cursor [%d]:\n", i);
15976 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15977 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15978 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15979 }
15980
15981 for (i = 0; i < error->num_transcoders; i++) {
15982 err_printf(m, "CPU transcoder: %c\n",
15983 transcoder_name(error->transcoder[i].cpu_transcoder));
15984 err_printf(m, " Power: %s\n",
15985 error->transcoder[i].power_domain_on ? "on" : "off");
15986 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15987 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15988 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15989 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15990 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15991 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15992 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15993 }
15994 }
15995
15996 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15997 {
15998 struct intel_crtc *crtc;
15999
16000 for_each_intel_crtc(dev, crtc) {
16001 struct intel_unpin_work *work;
16002
16003 spin_lock_irq(&dev->event_lock);
16004
16005 work = crtc->unpin_work;
16006
16007 if (work && work->event &&
16008 work->event->base.file_priv == file) {
16009 kfree(work->event);
16010 work->event = NULL;
16011 }
16012
16013 spin_unlock_irq(&dev->event_lock);
16014 }
16015 }
Linux kernel - Deliverables
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