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184ba09842f588ef9fef29ca6633a66dd2802e79
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151 {
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
313 },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
340 },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
354 },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503 return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
513
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
516 return true;
517
518 return false;
519 }
520
521 /**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
529 {
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
535
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
541
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
544 return true;
545 }
546
547 WARN_ON(num_connectors == 0);
548
549 return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
570 } else
571 limit = &intel_limits_ironlake_dac;
572
573 return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
581
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
585 else
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
594
595 return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
603
604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
613 else
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
624 } else {
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
629 else
630 limit = &intel_limits_i8xx_dac;
631 }
632 return limit;
633 }
634
635 /*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
649 return 0;
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653 return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666 return 0;
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670 return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
678 return 0;
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682 return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
690 return 0;
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
707 {
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
716
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
735
736 return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
743 {
744 struct drm_device *dev = crtc_state->base.crtc->dev;
745
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747 /*
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
751 */
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
754 else
755 return limit->p2.p2_slow;
756 } else {
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
759 else
760 return limit->p2.p2_fast;
761 }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
816 {
817 struct drm_device *dev = crtc_state->base.crtc->dev;
818 intel_clock_t clock;
819 int err = target;
820
821 memset(best_clock, 0, sizeof(*best_clock));
822
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
833 int this_err;
834
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
838 continue;
839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct drm_device *dev = crtc_state->base.crtc->dev;
863 intel_clock_t clock;
864 int max_n;
865 bool found = false;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
868
869 memset(best_clock, 0, sizeof(*best_clock));
870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
888 continue;
889
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
901 return found;
902 }
903
904 /*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913 {
914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949 {
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
952 intel_clock_t clock;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
956 bool found = false;
957
958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
961
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970 unsigned int ppm;
971
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
975 vlv_calc_dpll_params(refclk, &clock);
976
977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
979 continue;
980
981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
986
987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
990 }
991 }
992 }
993 }
994
995 return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
1038 chv_calc_dpll_params(refclk, &clock);
1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
1050 }
1051 }
1052
1053 return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058 {
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1074 *
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
1081 */
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088 {
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092 return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
1108 msleep(5);
1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112 }
1113
1114 /*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1128 *
1129 */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 int reg = PIPECONF(cpu_transcoder);
1139
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
1143 WARN(1, "pipe_off wait timed out\n");
1144 } else {
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153 return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159 {
1160 int reg;
1161 u32 val;
1162 bool cur_state;
1163
1164 reg = DPLL(pipe);
1165 val = I915_READ(reg);
1166 cur_state = !!(val & DPLL_VCO_ENABLE);
1167 I915_STATE_WARN(cur_state != state,
1168 "PLL state assertion failure (expected %s, current %s)\n",
1169 state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175 u32 val;
1176 bool cur_state;
1177
1178 mutex_lock(&dev_priv->sb_lock);
1179 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180 mutex_unlock(&dev_priv->sb_lock);
1181
1182 cur_state = val & DSI_PLL_VCO_EN;
1183 I915_STATE_WARN(cur_state != state,
1184 "DSI PLL state assertion failure (expected %s, current %s)\n",
1185 state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195 if (crtc->config->shared_dpll < 0)
1196 return NULL;
1197
1198 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203 struct intel_shared_dpll *pll,
1204 bool state)
1205 {
1206 bool cur_state;
1207 struct intel_dpll_hw_state hw_state;
1208
1209 if (WARN (!pll,
1210 "asserting DPLL %s with no DPLL\n", state_string(state)))
1211 return;
1212
1213 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214 I915_STATE_WARN(cur_state != state,
1215 "%s assertion failure (expected %s, current %s)\n",
1216 pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 if (HAS_DDI(dev_priv->dev)) {
1229 /* DDI does not have a specific FDI_TX register */
1230 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1231 val = I915_READ(reg);
1232 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1233 } else {
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & FDI_TX_ENABLE);
1237 }
1238 I915_STATE_WARN(cur_state != state,
1239 "FDI TX state assertion failure (expected %s, current %s)\n",
1240 state_string(state), state_string(cur_state));
1241 }
1242 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1243 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1244
1245 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247 {
1248 int reg;
1249 u32 val;
1250 bool cur_state;
1251
1252 reg = FDI_RX_CTL(pipe);
1253 val = I915_READ(reg);
1254 cur_state = !!(val & FDI_RX_ENABLE);
1255 I915_STATE_WARN(cur_state != state,
1256 "FDI RX state assertion failure (expected %s, current %s)\n",
1257 state_string(state), state_string(cur_state));
1258 }
1259 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1260 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1261
1262 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 int reg;
1266 u32 val;
1267
1268 /* ILK FDI PLL is always enabled */
1269 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1270 return;
1271
1272 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1273 if (HAS_DDI(dev_priv->dev))
1274 return;
1275
1276 reg = FDI_TX_CTL(pipe);
1277 val = I915_READ(reg);
1278 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1279 }
1280
1281 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1282 enum pipe pipe, bool state)
1283 {
1284 int reg;
1285 u32 val;
1286 bool cur_state;
1287
1288 reg = FDI_RX_CTL(pipe);
1289 val = I915_READ(reg);
1290 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1291 I915_STATE_WARN(cur_state != state,
1292 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1293 state_string(state), state_string(cur_state));
1294 }
1295
1296 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1297 enum pipe pipe)
1298 {
1299 struct drm_device *dev = dev_priv->dev;
1300 int pp_reg;
1301 u32 val;
1302 enum pipe panel_pipe = PIPE_A;
1303 bool locked = true;
1304
1305 if (WARN_ON(HAS_DDI(dev)))
1306 return;
1307
1308 if (HAS_PCH_SPLIT(dev)) {
1309 u32 port_sel;
1310
1311 pp_reg = PCH_PP_CONTROL;
1312 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1313
1314 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1315 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1316 panel_pipe = PIPE_B;
1317 /* XXX: else fix for eDP */
1318 } else if (IS_VALLEYVIEW(dev)) {
1319 /* presumably write lock depends on pipe, not port select */
1320 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1321 panel_pipe = pipe;
1322 } else {
1323 pp_reg = PP_CONTROL;
1324 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1325 panel_pipe = PIPE_B;
1326 }
1327
1328 val = I915_READ(pp_reg);
1329 if (!(val & PANEL_POWER_ON) ||
1330 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1331 locked = false;
1332
1333 I915_STATE_WARN(panel_pipe == pipe && locked,
1334 "panel assertion failure, pipe %c regs locked\n",
1335 pipe_name(pipe));
1336 }
1337
1338 static void assert_cursor(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, bool state)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 bool cur_state;
1343
1344 if (IS_845G(dev) || IS_I865G(dev))
1345 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1346 else
1347 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1348
1349 I915_STATE_WARN(cur_state != state,
1350 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1354 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1355
1356 void assert_pipe(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, bool state)
1358 {
1359 int reg;
1360 u32 val;
1361 bool cur_state;
1362 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1363 pipe);
1364
1365 /* if we need the pipe quirk it must be always on */
1366 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1367 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1368 state = true;
1369
1370 if (!intel_display_power_is_enabled(dev_priv,
1371 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1372 cur_state = false;
1373 } else {
1374 reg = PIPECONF(cpu_transcoder);
1375 val = I915_READ(reg);
1376 cur_state = !!(val & PIPECONF_ENABLE);
1377 }
1378
1379 I915_STATE_WARN(cur_state != state,
1380 "pipe %c assertion failure (expected %s, current %s)\n",
1381 pipe_name(pipe), state_string(state), state_string(cur_state));
1382 }
1383
1384 static void assert_plane(struct drm_i915_private *dev_priv,
1385 enum plane plane, bool state)
1386 {
1387 int reg;
1388 u32 val;
1389 bool cur_state;
1390
1391 reg = DSPCNTR(plane);
1392 val = I915_READ(reg);
1393 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1394 I915_STATE_WARN(cur_state != state,
1395 "plane %c assertion failure (expected %s, current %s)\n",
1396 plane_name(plane), state_string(state), state_string(cur_state));
1397 }
1398
1399 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1400 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1401
1402 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404 {
1405 struct drm_device *dev = dev_priv->dev;
1406 int reg, i;
1407 u32 val;
1408 int cur_pipe;
1409
1410 /* Primary planes are fixed to pipes on gen4+ */
1411 if (INTEL_INFO(dev)->gen >= 4) {
1412 reg = DSPCNTR(pipe);
1413 val = I915_READ(reg);
1414 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1415 "plane %c assertion failure, should be disabled but not\n",
1416 plane_name(pipe));
1417 return;
1418 }
1419
1420 /* Need to check both planes against the pipe */
1421 for_each_pipe(dev_priv, i) {
1422 reg = DSPCNTR(i);
1423 val = I915_READ(reg);
1424 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1425 DISPPLANE_SEL_PIPE_SHIFT;
1426 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1427 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1428 plane_name(i), pipe_name(pipe));
1429 }
1430 }
1431
1432 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434 {
1435 struct drm_device *dev = dev_priv->dev;
1436 int reg, sprite;
1437 u32 val;
1438
1439 if (INTEL_INFO(dev)->gen >= 9) {
1440 for_each_sprite(dev_priv, pipe, sprite) {
1441 val = I915_READ(PLANE_CTL(pipe, sprite));
1442 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1443 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1444 sprite, pipe_name(pipe));
1445 }
1446 } else if (IS_VALLEYVIEW(dev)) {
1447 for_each_sprite(dev_priv, pipe, sprite) {
1448 reg = SPCNTR(pipe, sprite);
1449 val = I915_READ(reg);
1450 I915_STATE_WARN(val & SP_ENABLE,
1451 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1452 sprite_name(pipe, sprite), pipe_name(pipe));
1453 }
1454 } else if (INTEL_INFO(dev)->gen >= 7) {
1455 reg = SPRCTL(pipe);
1456 val = I915_READ(reg);
1457 I915_STATE_WARN(val & SPRITE_ENABLE,
1458 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1459 plane_name(pipe), pipe_name(pipe));
1460 } else if (INTEL_INFO(dev)->gen >= 5) {
1461 reg = DVSCNTR(pipe);
1462 val = I915_READ(reg);
1463 I915_STATE_WARN(val & DVS_ENABLE,
1464 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1465 plane_name(pipe), pipe_name(pipe));
1466 }
1467 }
1468
1469 static void assert_vblank_disabled(struct drm_crtc *crtc)
1470 {
1471 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1472 drm_crtc_vblank_put(crtc);
1473 }
1474
1475 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1476 {
1477 u32 val;
1478 bool enabled;
1479
1480 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1481
1482 val = I915_READ(PCH_DREF_CONTROL);
1483 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1484 DREF_SUPERSPREAD_SOURCE_MASK));
1485 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1486 }
1487
1488 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1489 enum pipe pipe)
1490 {
1491 int reg;
1492 u32 val;
1493 bool enabled;
1494
1495 reg = PCH_TRANSCONF(pipe);
1496 val = I915_READ(reg);
1497 enabled = !!(val & TRANS_ENABLE);
1498 I915_STATE_WARN(enabled,
1499 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1500 pipe_name(pipe));
1501 }
1502
1503 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1504 enum pipe pipe, u32 port_sel, u32 val)
1505 {
1506 if ((val & DP_PORT_EN) == 0)
1507 return false;
1508
1509 if (HAS_PCH_CPT(dev_priv->dev)) {
1510 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1511 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1512 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1513 return false;
1514 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1515 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1516 return false;
1517 } else {
1518 if ((val & DP_PIPE_MASK) != (pipe << 30))
1519 return false;
1520 }
1521 return true;
1522 }
1523
1524 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526 {
1527 if ((val & SDVO_ENABLE) == 0)
1528 return false;
1529
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1532 return false;
1533 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1534 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1535 return false;
1536 } else {
1537 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1538 return false;
1539 }
1540 return true;
1541 }
1542
1543 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1544 enum pipe pipe, u32 val)
1545 {
1546 if ((val & LVDS_PORT_EN) == 0)
1547 return false;
1548
1549 if (HAS_PCH_CPT(dev_priv->dev)) {
1550 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1551 return false;
1552 } else {
1553 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1554 return false;
1555 }
1556 return true;
1557 }
1558
1559 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1560 enum pipe pipe, u32 val)
1561 {
1562 if ((val & ADPA_DAC_ENABLE) == 0)
1563 return false;
1564 if (HAS_PCH_CPT(dev_priv->dev)) {
1565 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1566 return false;
1567 } else {
1568 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1569 return false;
1570 }
1571 return true;
1572 }
1573
1574 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1575 enum pipe pipe, int reg, u32 port_sel)
1576 {
1577 u32 val = I915_READ(reg);
1578 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1579 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1580 reg, pipe_name(pipe));
1581
1582 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1583 && (val & DP_PIPEB_SELECT),
1584 "IBX PCH dp port still using transcoder B\n");
1585 }
1586
1587 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1588 enum pipe pipe, int reg)
1589 {
1590 u32 val = I915_READ(reg);
1591 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1592 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1593 reg, pipe_name(pipe));
1594
1595 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1596 && (val & SDVO_PIPE_B_SELECT),
1597 "IBX PCH hdmi port still using transcoder B\n");
1598 }
1599
1600 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1601 enum pipe pipe)
1602 {
1603 int reg;
1604 u32 val;
1605
1606 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1609
1610 reg = PCH_ADPA;
1611 val = I915_READ(reg);
1612 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1613 "PCH VGA enabled on transcoder %c, should be disabled\n",
1614 pipe_name(pipe));
1615
1616 reg = PCH_LVDS;
1617 val = I915_READ(reg);
1618 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1619 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1620 pipe_name(pipe));
1621
1622 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1623 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1624 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1625 }
1626
1627 static void vlv_enable_pll(struct intel_crtc *crtc,
1628 const struct intel_crtc_state *pipe_config)
1629 {
1630 struct drm_device *dev = crtc->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 int reg = DPLL(crtc->pipe);
1633 u32 dpll = pipe_config->dpll_hw_state.dpll;
1634
1635 assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637 /* No really, not for ILK+ */
1638 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1639
1640 /* PLL is protected by panel, make sure we can write it */
1641 if (IS_MOBILE(dev_priv->dev))
1642 assert_panel_unlocked(dev_priv, crtc->pipe);
1643
1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150);
1647
1648 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1649 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1650
1651 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1652 POSTING_READ(DPLL_MD(crtc->pipe));
1653
1654 /* We do this three times for luck */
1655 I915_WRITE(reg, dpll);
1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664 }
1665
1666 static void chv_enable_pll(struct intel_crtc *crtc,
1667 const struct intel_crtc_state *pipe_config)
1668 {
1669 struct drm_device *dev = crtc->base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int pipe = crtc->pipe;
1672 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1673 u32 tmp;
1674
1675 assert_pipe_disabled(dev_priv, crtc->pipe);
1676
1677 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1678
1679 mutex_lock(&dev_priv->sb_lock);
1680
1681 /* Enable back the 10bit clock to display controller */
1682 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1683 tmp |= DPIO_DCLKP_EN;
1684 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1685
1686 mutex_unlock(&dev_priv->sb_lock);
1687
1688 /*
1689 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1690 */
1691 udelay(1);
1692
1693 /* Enable PLL */
1694 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1695
1696 /* Check PLL is locked */
1697 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1698 DRM_ERROR("PLL %d failed to lock\n", pipe);
1699
1700 /* not sure when this should be written */
1701 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1702 POSTING_READ(DPLL_MD(pipe));
1703 }
1704
1705 static int intel_num_dvo_pipes(struct drm_device *dev)
1706 {
1707 struct intel_crtc *crtc;
1708 int count = 0;
1709
1710 for_each_intel_crtc(dev, crtc)
1711 count += crtc->base.state->active &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1713
1714 return count;
1715 }
1716
1717 static void i9xx_enable_pll(struct intel_crtc *crtc)
1718 {
1719 struct drm_device *dev = crtc->base.dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 int reg = DPLL(crtc->pipe);
1722 u32 dpll = crtc->config->dpll_hw_state.dpll;
1723
1724 assert_pipe_disabled(dev_priv, crtc->pipe);
1725
1726 /* No really, not for ILK+ */
1727 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1728
1729 /* PLL is protected by panel, make sure we can write it */
1730 if (IS_MOBILE(dev) && !IS_I830(dev))
1731 assert_panel_unlocked(dev_priv, crtc->pipe);
1732
1733 /* Enable DVO 2x clock on both PLLs if necessary */
1734 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1735 /*
1736 * It appears to be important that we don't enable this
1737 * for the current pipe before otherwise configuring the
1738 * PLL. No idea how this should be handled if multiple
1739 * DVO outputs are enabled simultaneosly.
1740 */
1741 dpll |= DPLL_DVO_2X_MODE;
1742 I915_WRITE(DPLL(!crtc->pipe),
1743 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1744 }
1745
1746 /* Wait for the clocks to stabilize. */
1747 POSTING_READ(reg);
1748 udelay(150);
1749
1750 if (INTEL_INFO(dev)->gen >= 4) {
1751 I915_WRITE(DPLL_MD(crtc->pipe),
1752 crtc->config->dpll_hw_state.dpll_md);
1753 } else {
1754 /* The pixel multiplier can only be updated once the
1755 * DPLL is enabled and the clocks are stable.
1756 *
1757 * So write it again.
1758 */
1759 I915_WRITE(reg, dpll);
1760 }
1761
1762 /* We do this three times for luck */
1763 I915_WRITE(reg, dpll);
1764 POSTING_READ(reg);
1765 udelay(150); /* wait for warmup */
1766 I915_WRITE(reg, dpll);
1767 POSTING_READ(reg);
1768 udelay(150); /* wait for warmup */
1769 I915_WRITE(reg, dpll);
1770 POSTING_READ(reg);
1771 udelay(150); /* wait for warmup */
1772 }
1773
1774 /**
1775 * i9xx_disable_pll - disable a PLL
1776 * @dev_priv: i915 private structure
1777 * @pipe: pipe PLL to disable
1778 *
1779 * Disable the PLL for @pipe, making sure the pipe is off first.
1780 *
1781 * Note! This is for pre-ILK only.
1782 */
1783 static void i9xx_disable_pll(struct intel_crtc *crtc)
1784 {
1785 struct drm_device *dev = crtc->base.dev;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787 enum pipe pipe = crtc->pipe;
1788
1789 /* Disable DVO 2x clock on both PLLs if necessary */
1790 if (IS_I830(dev) &&
1791 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1792 !intel_num_dvo_pipes(dev)) {
1793 I915_WRITE(DPLL(PIPE_B),
1794 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1795 I915_WRITE(DPLL(PIPE_A),
1796 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1797 }
1798
1799 /* Don't disable pipe or pipe PLLs if needed */
1800 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1801 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1802 return;
1803
1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
1806
1807 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1808 POSTING_READ(DPLL(pipe));
1809 }
1810
1811 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813 u32 val;
1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
1818 /*
1819 * Leave integrated clock source and reference clock enabled for pipe B.
1820 * The latter is needed for VGA hotplug / manual detection.
1821 */
1822 val = DPLL_VGA_MODE_DIS;
1823 if (pipe == PIPE_B)
1824 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1825 I915_WRITE(DPLL(pipe), val);
1826 POSTING_READ(DPLL(pipe));
1827
1828 }
1829
1830 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1831 {
1832 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1833 u32 val;
1834
1835 /* Make sure the pipe isn't still relying on us */
1836 assert_pipe_disabled(dev_priv, pipe);
1837
1838 /* Set PLL en = 0 */
1839 val = DPLL_SSC_REF_CLK_CHV |
1840 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1841 if (pipe != PIPE_A)
1842 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1843 I915_WRITE(DPLL(pipe), val);
1844 POSTING_READ(DPLL(pipe));
1845
1846 mutex_lock(&dev_priv->sb_lock);
1847
1848 /* Disable 10bit clock to display controller */
1849 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1850 val &= ~DPIO_DCLKP_EN;
1851 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1852
1853 mutex_unlock(&dev_priv->sb_lock);
1854 }
1855
1856 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1857 struct intel_digital_port *dport,
1858 unsigned int expected_mask)
1859 {
1860 u32 port_mask;
1861 int dpll_reg;
1862
1863 switch (dport->port) {
1864 case PORT_B:
1865 port_mask = DPLL_PORTB_READY_MASK;
1866 dpll_reg = DPLL(0);
1867 break;
1868 case PORT_C:
1869 port_mask = DPLL_PORTC_READY_MASK;
1870 dpll_reg = DPLL(0);
1871 expected_mask <<= 4;
1872 break;
1873 case PORT_D:
1874 port_mask = DPLL_PORTD_READY_MASK;
1875 dpll_reg = DPIO_PHY_STATUS;
1876 break;
1877 default:
1878 BUG();
1879 }
1880
1881 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1884 }
1885
1886 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887 {
1888 struct drm_device *dev = crtc->base.dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
1892 if (WARN_ON(pll == NULL))
1893 return;
1894
1895 WARN_ON(!pll->config.crtc_mask);
1896 if (pll->active == 0) {
1897 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898 WARN_ON(pll->on);
1899 assert_shared_dpll_disabled(dev_priv, pll);
1900
1901 pll->mode_set(dev_priv, pll);
1902 }
1903 }
1904
1905 /**
1906 * intel_enable_shared_dpll - enable PCH PLL
1907 * @dev_priv: i915 private structure
1908 * @pipe: pipe PLL to enable
1909 *
1910 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911 * drives the transcoder clock.
1912 */
1913 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919 if (WARN_ON(pll == NULL))
1920 return;
1921
1922 if (WARN_ON(pll->config.crtc_mask == 0))
1923 return;
1924
1925 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1926 pll->name, pll->active, pll->on,
1927 crtc->base.base.id);
1928
1929 if (pll->active++) {
1930 WARN_ON(!pll->on);
1931 assert_shared_dpll_enabled(dev_priv, pll);
1932 return;
1933 }
1934 WARN_ON(pll->on);
1935
1936 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937
1938 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1939 pll->enable(dev_priv, pll);
1940 pll->on = true;
1941 }
1942
1943 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1944 {
1945 struct drm_device *dev = crtc->base.dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
1947 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1948
1949 /* PCH only available on ILK+ */
1950 if (INTEL_INFO(dev)->gen < 5)
1951 return;
1952
1953 if (pll == NULL)
1954 return;
1955
1956 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1957 return;
1958
1959 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1960 pll->name, pll->active, pll->on,
1961 crtc->base.base.id);
1962
1963 if (WARN_ON(pll->active == 0)) {
1964 assert_shared_dpll_disabled(dev_priv, pll);
1965 return;
1966 }
1967
1968 assert_shared_dpll_enabled(dev_priv, pll);
1969 WARN_ON(!pll->on);
1970 if (--pll->active)
1971 return;
1972
1973 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1974 pll->disable(dev_priv, pll);
1975 pll->on = false;
1976
1977 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1978 }
1979
1980 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1981 enum pipe pipe)
1982 {
1983 struct drm_device *dev = dev_priv->dev;
1984 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1986 uint32_t reg, val, pipeconf_val;
1987
1988 /* PCH only available on ILK+ */
1989 BUG_ON(!HAS_PCH_SPLIT(dev));
1990
1991 /* Make sure PCH DPLL is enabled */
1992 assert_shared_dpll_enabled(dev_priv,
1993 intel_crtc_to_shared_dpll(intel_crtc));
1994
1995 /* FDI must be feeding us bits for PCH ports */
1996 assert_fdi_tx_enabled(dev_priv, pipe);
1997 assert_fdi_rx_enabled(dev_priv, pipe);
1998
1999 if (HAS_PCH_CPT(dev)) {
2000 /* Workaround: Set the timing override bit before enabling the
2001 * pch transcoder. */
2002 reg = TRANS_CHICKEN2(pipe);
2003 val = I915_READ(reg);
2004 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2005 I915_WRITE(reg, val);
2006 }
2007
2008 reg = PCH_TRANSCONF(pipe);
2009 val = I915_READ(reg);
2010 pipeconf_val = I915_READ(PIPECONF(pipe));
2011
2012 if (HAS_PCH_IBX(dev_priv->dev)) {
2013 /*
2014 * Make the BPC in transcoder be consistent with
2015 * that in pipeconf reg. For HDMI we must use 8bpc
2016 * here for both 8bpc and 12bpc.
2017 */
2018 val &= ~PIPECONF_BPC_MASK;
2019 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2020 val |= PIPECONF_8BPC;
2021 else
2022 val |= pipeconf_val & PIPECONF_BPC_MASK;
2023 }
2024
2025 val &= ~TRANS_INTERLACE_MASK;
2026 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2027 if (HAS_PCH_IBX(dev_priv->dev) &&
2028 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2029 val |= TRANS_LEGACY_INTERLACED_ILK;
2030 else
2031 val |= TRANS_INTERLACED;
2032 else
2033 val |= TRANS_PROGRESSIVE;
2034
2035 I915_WRITE(reg, val | TRANS_ENABLE);
2036 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2037 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2038 }
2039
2040 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2041 enum transcoder cpu_transcoder)
2042 {
2043 u32 val, pipeconf_val;
2044
2045 /* PCH only available on ILK+ */
2046 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2047
2048 /* FDI must be feeding us bits for PCH ports */
2049 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2050 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2051
2052 /* Workaround: set timing override bit. */
2053 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2054 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2055 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2056
2057 val = TRANS_ENABLE;
2058 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2059
2060 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2061 PIPECONF_INTERLACED_ILK)
2062 val |= TRANS_INTERLACED;
2063 else
2064 val |= TRANS_PROGRESSIVE;
2065
2066 I915_WRITE(LPT_TRANSCONF, val);
2067 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2068 DRM_ERROR("Failed to enable PCH transcoder\n");
2069 }
2070
2071 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2072 enum pipe pipe)
2073 {
2074 struct drm_device *dev = dev_priv->dev;
2075 uint32_t reg, val;
2076
2077 /* FDI relies on the transcoder */
2078 assert_fdi_tx_disabled(dev_priv, pipe);
2079 assert_fdi_rx_disabled(dev_priv, pipe);
2080
2081 /* Ports must be off as well */
2082 assert_pch_ports_disabled(dev_priv, pipe);
2083
2084 reg = PCH_TRANSCONF(pipe);
2085 val = I915_READ(reg);
2086 val &= ~TRANS_ENABLE;
2087 I915_WRITE(reg, val);
2088 /* wait for PCH transcoder off, transcoder state */
2089 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2090 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2091
2092 if (!HAS_PCH_IBX(dev)) {
2093 /* Workaround: Clear the timing override chicken bit again. */
2094 reg = TRANS_CHICKEN2(pipe);
2095 val = I915_READ(reg);
2096 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097 I915_WRITE(reg, val);
2098 }
2099 }
2100
2101 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2102 {
2103 u32 val;
2104
2105 val = I915_READ(LPT_TRANSCONF);
2106 val &= ~TRANS_ENABLE;
2107 I915_WRITE(LPT_TRANSCONF, val);
2108 /* wait for PCH transcoder off, transcoder state */
2109 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2110 DRM_ERROR("Failed to disable PCH transcoder\n");
2111
2112 /* Workaround: clear timing override bit. */
2113 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2114 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2115 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2116 }
2117
2118 /**
2119 * intel_enable_pipe - enable a pipe, asserting requirements
2120 * @crtc: crtc responsible for the pipe
2121 *
2122 * Enable @crtc's pipe, making sure that various hardware specific requirements
2123 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2124 */
2125 static void intel_enable_pipe(struct intel_crtc *crtc)
2126 {
2127 struct drm_device *dev = crtc->base.dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 enum pipe pipe = crtc->pipe;
2130 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2131 pipe);
2132 enum pipe pch_transcoder;
2133 int reg;
2134 u32 val;
2135
2136 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2137
2138 assert_planes_disabled(dev_priv, pipe);
2139 assert_cursor_disabled(dev_priv, pipe);
2140 assert_sprites_disabled(dev_priv, pipe);
2141
2142 if (HAS_PCH_LPT(dev_priv->dev))
2143 pch_transcoder = TRANSCODER_A;
2144 else
2145 pch_transcoder = pipe;
2146
2147 /*
2148 * A pipe without a PLL won't actually be able to drive bits from
2149 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2150 * need the check.
2151 */
2152 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2154 assert_dsi_pll_enabled(dev_priv);
2155 else
2156 assert_pll_enabled(dev_priv, pipe);
2157 else {
2158 if (crtc->config->has_pch_encoder) {
2159 /* if driving the PCH, we need FDI enabled */
2160 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2161 assert_fdi_tx_pll_enabled(dev_priv,
2162 (enum pipe) cpu_transcoder);
2163 }
2164 /* FIXME: assert CPU port conditions for SNB+ */
2165 }
2166
2167 reg = PIPECONF(cpu_transcoder);
2168 val = I915_READ(reg);
2169 if (val & PIPECONF_ENABLE) {
2170 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2171 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2172 return;
2173 }
2174
2175 I915_WRITE(reg, val | PIPECONF_ENABLE);
2176 POSTING_READ(reg);
2177 }
2178
2179 /**
2180 * intel_disable_pipe - disable a pipe, asserting requirements
2181 * @crtc: crtc whose pipes is to be disabled
2182 *
2183 * Disable the pipe of @crtc, making sure that various hardware
2184 * specific requirements are met, if applicable, e.g. plane
2185 * disabled, panel fitter off, etc.
2186 *
2187 * Will wait until the pipe has shut down before returning.
2188 */
2189 static void intel_disable_pipe(struct intel_crtc *crtc)
2190 {
2191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2192 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2193 enum pipe pipe = crtc->pipe;
2194 int reg;
2195 u32 val;
2196
2197 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2198
2199 /*
2200 * Make sure planes won't keep trying to pump pixels to us,
2201 * or we might hang the display.
2202 */
2203 assert_planes_disabled(dev_priv, pipe);
2204 assert_cursor_disabled(dev_priv, pipe);
2205 assert_sprites_disabled(dev_priv, pipe);
2206
2207 reg = PIPECONF(cpu_transcoder);
2208 val = I915_READ(reg);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 return;
2211
2212 /*
2213 * Double wide has implications for planes
2214 * so best keep it disabled when not needed.
2215 */
2216 if (crtc->config->double_wide)
2217 val &= ~PIPECONF_DOUBLE_WIDE;
2218
2219 /* Don't disable pipe or pipe PLLs if needed */
2220 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2221 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2222 val &= ~PIPECONF_ENABLE;
2223
2224 I915_WRITE(reg, val);
2225 if ((val & PIPECONF_ENABLE) == 0)
2226 intel_wait_for_pipe_off(crtc);
2227 }
2228
2229 static bool need_vtd_wa(struct drm_device *dev)
2230 {
2231 #ifdef CONFIG_INTEL_IOMMU
2232 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2233 return true;
2234 #endif
2235 return false;
2236 }
2237
2238 unsigned int
2239 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2240 uint64_t fb_format_modifier, unsigned int plane)
2241 {
2242 unsigned int tile_height;
2243 uint32_t pixel_bytes;
2244
2245 switch (fb_format_modifier) {
2246 case DRM_FORMAT_MOD_NONE:
2247 tile_height = 1;
2248 break;
2249 case I915_FORMAT_MOD_X_TILED:
2250 tile_height = IS_GEN2(dev) ? 16 : 8;
2251 break;
2252 case I915_FORMAT_MOD_Y_TILED:
2253 tile_height = 32;
2254 break;
2255 case I915_FORMAT_MOD_Yf_TILED:
2256 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2257 switch (pixel_bytes) {
2258 default:
2259 case 1:
2260 tile_height = 64;
2261 break;
2262 case 2:
2263 case 4:
2264 tile_height = 32;
2265 break;
2266 case 8:
2267 tile_height = 16;
2268 break;
2269 case 16:
2270 WARN_ONCE(1,
2271 "128-bit pixels are not supported for display!");
2272 tile_height = 16;
2273 break;
2274 }
2275 break;
2276 default:
2277 MISSING_CASE(fb_format_modifier);
2278 tile_height = 1;
2279 break;
2280 }
2281
2282 return tile_height;
2283 }
2284
2285 unsigned int
2286 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2287 uint32_t pixel_format, uint64_t fb_format_modifier)
2288 {
2289 return ALIGN(height, intel_tile_height(dev, pixel_format,
2290 fb_format_modifier, 0));
2291 }
2292
2293 static int
2294 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2295 const struct drm_plane_state *plane_state)
2296 {
2297 struct intel_rotation_info *info = &view->rotation_info;
2298 unsigned int tile_height, tile_pitch;
2299
2300 *view = i915_ggtt_view_normal;
2301
2302 if (!plane_state)
2303 return 0;
2304
2305 if (!intel_rotation_90_or_270(plane_state->rotation))
2306 return 0;
2307
2308 *view = i915_ggtt_view_rotated;
2309
2310 info->height = fb->height;
2311 info->pixel_format = fb->pixel_format;
2312 info->pitch = fb->pitches[0];
2313 info->uv_offset = fb->offsets[1];
2314 info->fb_modifier = fb->modifier[0];
2315
2316 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2317 fb->modifier[0], 0);
2318 tile_pitch = PAGE_SIZE / tile_height;
2319 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2320 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2321 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2322
2323 if (info->pixel_format == DRM_FORMAT_NV12) {
2324 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2325 fb->modifier[0], 1);
2326 tile_pitch = PAGE_SIZE / tile_height;
2327 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2328 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2329 tile_height);
2330 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2331 PAGE_SIZE;
2332 }
2333
2334 return 0;
2335 }
2336
2337 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2338 {
2339 if (INTEL_INFO(dev_priv)->gen >= 9)
2340 return 256 * 1024;
2341 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2342 IS_VALLEYVIEW(dev_priv))
2343 return 128 * 1024;
2344 else if (INTEL_INFO(dev_priv)->gen >= 4)
2345 return 4 * 1024;
2346 else
2347 return 0;
2348 }
2349
2350 int
2351 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2352 struct drm_framebuffer *fb,
2353 const struct drm_plane_state *plane_state,
2354 struct intel_engine_cs *pipelined,
2355 struct drm_i915_gem_request **pipelined_request)
2356 {
2357 struct drm_device *dev = fb->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2360 struct i915_ggtt_view view;
2361 u32 alignment;
2362 int ret;
2363
2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
2368 alignment = intel_linear_alignment(dev_priv);
2369 break;
2370 case I915_FORMAT_MOD_X_TILED:
2371 if (INTEL_INFO(dev)->gen >= 9)
2372 alignment = 256 * 1024;
2373 else {
2374 /* pin() will align the object as required by fence */
2375 alignment = 0;
2376 }
2377 break;
2378 case I915_FORMAT_MOD_Y_TILED:
2379 case I915_FORMAT_MOD_Yf_TILED:
2380 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2381 "Y tiling bo slipped through, driver bug!\n"))
2382 return -EINVAL;
2383 alignment = 1 * 1024 * 1024;
2384 break;
2385 default:
2386 MISSING_CASE(fb->modifier[0]);
2387 return -EINVAL;
2388 }
2389
2390 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2391 if (ret)
2392 return ret;
2393
2394 /* Note that the w/a also requires 64 PTE of padding following the
2395 * bo. We currently fill all unused PTE with the shadow page and so
2396 * we should always have valid PTE following the scanout preventing
2397 * the VT-d warning.
2398 */
2399 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2400 alignment = 256 * 1024;
2401
2402 /*
2403 * Global gtt pte registers are special registers which actually forward
2404 * writes to a chunk of system memory. Which means that there is no risk
2405 * that the register values disappear as soon as we call
2406 * intel_runtime_pm_put(), so it is correct to wrap only the
2407 * pin/unpin/fence and not more.
2408 */
2409 intel_runtime_pm_get(dev_priv);
2410
2411 dev_priv->mm.interruptible = false;
2412 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2413 pipelined_request, &view);
2414 if (ret)
2415 goto err_interruptible;
2416
2417 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2418 * fence, whereas 965+ only requires a fence if using
2419 * framebuffer compression. For simplicity, we always install
2420 * a fence as the cost is not that onerous.
2421 */
2422 ret = i915_gem_object_get_fence(obj);
2423 if (ret == -EDEADLK) {
2424 /*
2425 * -EDEADLK means there are no free fences
2426 * no pending flips.
2427 *
2428 * This is propagated to atomic, but it uses
2429 * -EDEADLK to force a locking recovery, so
2430 * change the returned error to -EBUSY.
2431 */
2432 ret = -EBUSY;
2433 goto err_unpin;
2434 } else if (ret)
2435 goto err_unpin;
2436
2437 i915_gem_object_pin_fence(obj);
2438
2439 dev_priv->mm.interruptible = true;
2440 intel_runtime_pm_put(dev_priv);
2441 return 0;
2442
2443 err_unpin:
2444 i915_gem_object_unpin_from_display_plane(obj, &view);
2445 err_interruptible:
2446 dev_priv->mm.interruptible = true;
2447 intel_runtime_pm_put(dev_priv);
2448 return ret;
2449 }
2450
2451 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2452 const struct drm_plane_state *plane_state)
2453 {
2454 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2455 struct i915_ggtt_view view;
2456 int ret;
2457
2458 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2459
2460 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2461 WARN_ONCE(ret, "Couldn't get view from plane state!");
2462
2463 i915_gem_object_unpin_fence(obj);
2464 i915_gem_object_unpin_from_display_plane(obj, &view);
2465 }
2466
2467 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2468 * is assumed to be a power-of-two. */
2469 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2470 int *x, int *y,
2471 unsigned int tiling_mode,
2472 unsigned int cpp,
2473 unsigned int pitch)
2474 {
2475 if (tiling_mode != I915_TILING_NONE) {
2476 unsigned int tile_rows, tiles;
2477
2478 tile_rows = *y / 8;
2479 *y %= 8;
2480
2481 tiles = *x / (512/cpp);
2482 *x %= 512/cpp;
2483
2484 return tile_rows * pitch * 8 + tiles * 4096;
2485 } else {
2486 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2487 unsigned int offset;
2488
2489 offset = *y * pitch + *x * cpp;
2490 *y = (offset & alignment) / pitch;
2491 *x = ((offset & alignment) - *y * pitch) / cpp;
2492 return offset & ~alignment;
2493 }
2494 }
2495
2496 static int i9xx_format_to_fourcc(int format)
2497 {
2498 switch (format) {
2499 case DISPPLANE_8BPP:
2500 return DRM_FORMAT_C8;
2501 case DISPPLANE_BGRX555:
2502 return DRM_FORMAT_XRGB1555;
2503 case DISPPLANE_BGRX565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case DISPPLANE_BGRX888:
2507 return DRM_FORMAT_XRGB8888;
2508 case DISPPLANE_RGBX888:
2509 return DRM_FORMAT_XBGR8888;
2510 case DISPPLANE_BGRX101010:
2511 return DRM_FORMAT_XRGB2101010;
2512 case DISPPLANE_RGBX101010:
2513 return DRM_FORMAT_XBGR2101010;
2514 }
2515 }
2516
2517 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2518 {
2519 switch (format) {
2520 case PLANE_CTL_FORMAT_RGB_565:
2521 return DRM_FORMAT_RGB565;
2522 default:
2523 case PLANE_CTL_FORMAT_XRGB_8888:
2524 if (rgb_order) {
2525 if (alpha)
2526 return DRM_FORMAT_ABGR8888;
2527 else
2528 return DRM_FORMAT_XBGR8888;
2529 } else {
2530 if (alpha)
2531 return DRM_FORMAT_ARGB8888;
2532 else
2533 return DRM_FORMAT_XRGB8888;
2534 }
2535 case PLANE_CTL_FORMAT_XRGB_2101010:
2536 if (rgb_order)
2537 return DRM_FORMAT_XBGR2101010;
2538 else
2539 return DRM_FORMAT_XRGB2101010;
2540 }
2541 }
2542
2543 static bool
2544 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2545 struct intel_initial_plane_config *plane_config)
2546 {
2547 struct drm_device *dev = crtc->base.dev;
2548 struct drm_i915_private *dev_priv = to_i915(dev);
2549 struct drm_i915_gem_object *obj = NULL;
2550 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2551 struct drm_framebuffer *fb = &plane_config->fb->base;
2552 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2553 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2554 PAGE_SIZE);
2555
2556 size_aligned -= base_aligned;
2557
2558 if (plane_config->size == 0)
2559 return false;
2560
2561 /* If the FB is too big, just don't use it since fbdev is not very
2562 * important and we should probably use that space with FBC or other
2563 * features. */
2564 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2565 return false;
2566
2567 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2568 base_aligned,
2569 base_aligned,
2570 size_aligned);
2571 if (!obj)
2572 return false;
2573
2574 obj->tiling_mode = plane_config->tiling;
2575 if (obj->tiling_mode == I915_TILING_X)
2576 obj->stride = fb->pitches[0];
2577
2578 mode_cmd.pixel_format = fb->pixel_format;
2579 mode_cmd.width = fb->width;
2580 mode_cmd.height = fb->height;
2581 mode_cmd.pitches[0] = fb->pitches[0];
2582 mode_cmd.modifier[0] = fb->modifier[0];
2583 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2584
2585 mutex_lock(&dev->struct_mutex);
2586 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2587 &mode_cmd, obj)) {
2588 DRM_DEBUG_KMS("intel fb init failed\n");
2589 goto out_unref_obj;
2590 }
2591 mutex_unlock(&dev->struct_mutex);
2592
2593 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2594 return true;
2595
2596 out_unref_obj:
2597 drm_gem_object_unreference(&obj->base);
2598 mutex_unlock(&dev->struct_mutex);
2599 return false;
2600 }
2601
2602 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2603 static void
2604 update_state_fb(struct drm_plane *plane)
2605 {
2606 if (plane->fb == plane->state->fb)
2607 return;
2608
2609 if (plane->state->fb)
2610 drm_framebuffer_unreference(plane->state->fb);
2611 plane->state->fb = plane->fb;
2612 if (plane->state->fb)
2613 drm_framebuffer_reference(plane->state->fb);
2614 }
2615
2616 static void
2617 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2618 struct intel_initial_plane_config *plane_config)
2619 {
2620 struct drm_device *dev = intel_crtc->base.dev;
2621 struct drm_i915_private *dev_priv = dev->dev_private;
2622 struct drm_crtc *c;
2623 struct intel_crtc *i;
2624 struct drm_i915_gem_object *obj;
2625 struct drm_plane *primary = intel_crtc->base.primary;
2626 struct drm_plane_state *plane_state = primary->state;
2627 struct drm_framebuffer *fb;
2628
2629 if (!plane_config->fb)
2630 return;
2631
2632 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2633 fb = &plane_config->fb->base;
2634 goto valid_fb;
2635 }
2636
2637 kfree(plane_config->fb);
2638
2639 /*
2640 * Failed to alloc the obj, check to see if we should share
2641 * an fb with another CRTC instead
2642 */
2643 for_each_crtc(dev, c) {
2644 i = to_intel_crtc(c);
2645
2646 if (c == &intel_crtc->base)
2647 continue;
2648
2649 if (!i->active)
2650 continue;
2651
2652 fb = c->primary->fb;
2653 if (!fb)
2654 continue;
2655
2656 obj = intel_fb_obj(fb);
2657 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2658 drm_framebuffer_reference(fb);
2659 goto valid_fb;
2660 }
2661 }
2662
2663 return;
2664
2665 valid_fb:
2666 plane_state->src_x = plane_state->src_y = 0;
2667 plane_state->src_w = fb->width << 16;
2668 plane_state->src_h = fb->height << 16;
2669
2670 plane_state->crtc_x = plane_state->src_y = 0;
2671 plane_state->crtc_w = fb->width;
2672 plane_state->crtc_h = fb->height;
2673
2674 obj = intel_fb_obj(fb);
2675 if (obj->tiling_mode != I915_TILING_NONE)
2676 dev_priv->preserve_bios_swizzle = true;
2677
2678 drm_framebuffer_reference(fb);
2679 primary->fb = primary->state->fb = fb;
2680 primary->crtc = primary->state->crtc = &intel_crtc->base;
2681 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2682 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2683 }
2684
2685 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2686 struct drm_framebuffer *fb,
2687 int x, int y)
2688 {
2689 struct drm_device *dev = crtc->dev;
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692 struct drm_plane *primary = crtc->primary;
2693 bool visible = to_intel_plane_state(primary->state)->visible;
2694 struct drm_i915_gem_object *obj;
2695 int plane = intel_crtc->plane;
2696 unsigned long linear_offset;
2697 u32 dspcntr;
2698 u32 reg = DSPCNTR(plane);
2699 int pixel_size;
2700
2701 if (!visible || !fb) {
2702 I915_WRITE(reg, 0);
2703 if (INTEL_INFO(dev)->gen >= 4)
2704 I915_WRITE(DSPSURF(plane), 0);
2705 else
2706 I915_WRITE(DSPADDR(plane), 0);
2707 POSTING_READ(reg);
2708 return;
2709 }
2710
2711 obj = intel_fb_obj(fb);
2712 if (WARN_ON(obj == NULL))
2713 return;
2714
2715 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2716
2717 dspcntr = DISPPLANE_GAMMA_ENABLE;
2718
2719 dspcntr |= DISPLAY_PLANE_ENABLE;
2720
2721 if (INTEL_INFO(dev)->gen < 4) {
2722 if (intel_crtc->pipe == PIPE_B)
2723 dspcntr |= DISPPLANE_SEL_PIPE_B;
2724
2725 /* pipesrc and dspsize control the size that is scaled from,
2726 * which should always be the user's requested size.
2727 */
2728 I915_WRITE(DSPSIZE(plane),
2729 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2730 (intel_crtc->config->pipe_src_w - 1));
2731 I915_WRITE(DSPPOS(plane), 0);
2732 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2733 I915_WRITE(PRIMSIZE(plane),
2734 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2735 (intel_crtc->config->pipe_src_w - 1));
2736 I915_WRITE(PRIMPOS(plane), 0);
2737 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2738 }
2739
2740 switch (fb->pixel_format) {
2741 case DRM_FORMAT_C8:
2742 dspcntr |= DISPPLANE_8BPP;
2743 break;
2744 case DRM_FORMAT_XRGB1555:
2745 dspcntr |= DISPPLANE_BGRX555;
2746 break;
2747 case DRM_FORMAT_RGB565:
2748 dspcntr |= DISPPLANE_BGRX565;
2749 break;
2750 case DRM_FORMAT_XRGB8888:
2751 dspcntr |= DISPPLANE_BGRX888;
2752 break;
2753 case DRM_FORMAT_XBGR8888:
2754 dspcntr |= DISPPLANE_RGBX888;
2755 break;
2756 case DRM_FORMAT_XRGB2101010:
2757 dspcntr |= DISPPLANE_BGRX101010;
2758 break;
2759 case DRM_FORMAT_XBGR2101010:
2760 dspcntr |= DISPPLANE_RGBX101010;
2761 break;
2762 default:
2763 BUG();
2764 }
2765
2766 if (INTEL_INFO(dev)->gen >= 4 &&
2767 obj->tiling_mode != I915_TILING_NONE)
2768 dspcntr |= DISPPLANE_TILED;
2769
2770 if (IS_G4X(dev))
2771 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2772
2773 linear_offset = y * fb->pitches[0] + x * pixel_size;
2774
2775 if (INTEL_INFO(dev)->gen >= 4) {
2776 intel_crtc->dspaddr_offset =
2777 intel_gen4_compute_page_offset(dev_priv,
2778 &x, &y, obj->tiling_mode,
2779 pixel_size,
2780 fb->pitches[0]);
2781 linear_offset -= intel_crtc->dspaddr_offset;
2782 } else {
2783 intel_crtc->dspaddr_offset = linear_offset;
2784 }
2785
2786 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2787 dspcntr |= DISPPLANE_ROTATE_180;
2788
2789 x += (intel_crtc->config->pipe_src_w - 1);
2790 y += (intel_crtc->config->pipe_src_h - 1);
2791
2792 /* Finding the last pixel of the last line of the display
2793 data and adding to linear_offset*/
2794 linear_offset +=
2795 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2796 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2797 }
2798
2799 intel_crtc->adjusted_x = x;
2800 intel_crtc->adjusted_y = y;
2801
2802 I915_WRITE(reg, dspcntr);
2803
2804 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2805 if (INTEL_INFO(dev)->gen >= 4) {
2806 I915_WRITE(DSPSURF(plane),
2807 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2808 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2809 I915_WRITE(DSPLINOFF(plane), linear_offset);
2810 } else
2811 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2812 POSTING_READ(reg);
2813 }
2814
2815 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2816 struct drm_framebuffer *fb,
2817 int x, int y)
2818 {
2819 struct drm_device *dev = crtc->dev;
2820 struct drm_i915_private *dev_priv = dev->dev_private;
2821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2822 struct drm_plane *primary = crtc->primary;
2823 bool visible = to_intel_plane_state(primary->state)->visible;
2824 struct drm_i915_gem_object *obj;
2825 int plane = intel_crtc->plane;
2826 unsigned long linear_offset;
2827 u32 dspcntr;
2828 u32 reg = DSPCNTR(plane);
2829 int pixel_size;
2830
2831 if (!visible || !fb) {
2832 I915_WRITE(reg, 0);
2833 I915_WRITE(DSPSURF(plane), 0);
2834 POSTING_READ(reg);
2835 return;
2836 }
2837
2838 obj = intel_fb_obj(fb);
2839 if (WARN_ON(obj == NULL))
2840 return;
2841
2842 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2843
2844 dspcntr = DISPPLANE_GAMMA_ENABLE;
2845
2846 dspcntr |= DISPLAY_PLANE_ENABLE;
2847
2848 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2849 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2850
2851 switch (fb->pixel_format) {
2852 case DRM_FORMAT_C8:
2853 dspcntr |= DISPPLANE_8BPP;
2854 break;
2855 case DRM_FORMAT_RGB565:
2856 dspcntr |= DISPPLANE_BGRX565;
2857 break;
2858 case DRM_FORMAT_XRGB8888:
2859 dspcntr |= DISPPLANE_BGRX888;
2860 break;
2861 case DRM_FORMAT_XBGR8888:
2862 dspcntr |= DISPPLANE_RGBX888;
2863 break;
2864 case DRM_FORMAT_XRGB2101010:
2865 dspcntr |= DISPPLANE_BGRX101010;
2866 break;
2867 case DRM_FORMAT_XBGR2101010:
2868 dspcntr |= DISPPLANE_RGBX101010;
2869 break;
2870 default:
2871 BUG();
2872 }
2873
2874 if (obj->tiling_mode != I915_TILING_NONE)
2875 dspcntr |= DISPPLANE_TILED;
2876
2877 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2878 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2879
2880 linear_offset = y * fb->pitches[0] + x * pixel_size;
2881 intel_crtc->dspaddr_offset =
2882 intel_gen4_compute_page_offset(dev_priv,
2883 &x, &y, obj->tiling_mode,
2884 pixel_size,
2885 fb->pitches[0]);
2886 linear_offset -= intel_crtc->dspaddr_offset;
2887 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2888 dspcntr |= DISPPLANE_ROTATE_180;
2889
2890 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2891 x += (intel_crtc->config->pipe_src_w - 1);
2892 y += (intel_crtc->config->pipe_src_h - 1);
2893
2894 /* Finding the last pixel of the last line of the display
2895 data and adding to linear_offset*/
2896 linear_offset +=
2897 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2898 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2899 }
2900 }
2901
2902 intel_crtc->adjusted_x = x;
2903 intel_crtc->adjusted_y = y;
2904
2905 I915_WRITE(reg, dspcntr);
2906
2907 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2908 I915_WRITE(DSPSURF(plane),
2909 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2910 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2911 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2912 } else {
2913 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2914 I915_WRITE(DSPLINOFF(plane), linear_offset);
2915 }
2916 POSTING_READ(reg);
2917 }
2918
2919 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2920 uint32_t pixel_format)
2921 {
2922 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2923
2924 /*
2925 * The stride is either expressed as a multiple of 64 bytes
2926 * chunks for linear buffers or in number of tiles for tiled
2927 * buffers.
2928 */
2929 switch (fb_modifier) {
2930 case DRM_FORMAT_MOD_NONE:
2931 return 64;
2932 case I915_FORMAT_MOD_X_TILED:
2933 if (INTEL_INFO(dev)->gen == 2)
2934 return 128;
2935 return 512;
2936 case I915_FORMAT_MOD_Y_TILED:
2937 /* No need to check for old gens and Y tiling since this is
2938 * about the display engine and those will be blocked before
2939 * we get here.
2940 */
2941 return 128;
2942 case I915_FORMAT_MOD_Yf_TILED:
2943 if (bits_per_pixel == 8)
2944 return 64;
2945 else
2946 return 128;
2947 default:
2948 MISSING_CASE(fb_modifier);
2949 return 64;
2950 }
2951 }
2952
2953 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2954 struct drm_i915_gem_object *obj,
2955 unsigned int plane)
2956 {
2957 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2958 struct i915_vma *vma;
2959 unsigned char *offset;
2960
2961 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2962 view = &i915_ggtt_view_rotated;
2963
2964 vma = i915_gem_obj_to_ggtt_view(obj, view);
2965 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2966 view->type))
2967 return -1;
2968
2969 offset = (unsigned char *)vma->node.start;
2970
2971 if (plane == 1) {
2972 offset += vma->ggtt_view.rotation_info.uv_start_page *
2973 PAGE_SIZE;
2974 }
2975
2976 return (unsigned long)offset;
2977 }
2978
2979 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2980 {
2981 struct drm_device *dev = intel_crtc->base.dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983
2984 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2985 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2986 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2987 }
2988
2989 /*
2990 * This function detaches (aka. unbinds) unused scalers in hardware
2991 */
2992 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2993 {
2994 struct intel_crtc_scaler_state *scaler_state;
2995 int i;
2996
2997 scaler_state = &intel_crtc->config->scaler_state;
2998
2999 /* loop through and disable scalers that aren't in use */
3000 for (i = 0; i < intel_crtc->num_scalers; i++) {
3001 if (!scaler_state->scalers[i].in_use)
3002 skl_detach_scaler(intel_crtc, i);
3003 }
3004 }
3005
3006 u32 skl_plane_ctl_format(uint32_t pixel_format)
3007 {
3008 switch (pixel_format) {
3009 case DRM_FORMAT_C8:
3010 return PLANE_CTL_FORMAT_INDEXED;
3011 case DRM_FORMAT_RGB565:
3012 return PLANE_CTL_FORMAT_RGB_565;
3013 case DRM_FORMAT_XBGR8888:
3014 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3015 case DRM_FORMAT_XRGB8888:
3016 return PLANE_CTL_FORMAT_XRGB_8888;
3017 /*
3018 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3019 * to be already pre-multiplied. We need to add a knob (or a different
3020 * DRM_FORMAT) for user-space to configure that.
3021 */
3022 case DRM_FORMAT_ABGR8888:
3023 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3024 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3025 case DRM_FORMAT_ARGB8888:
3026 return PLANE_CTL_FORMAT_XRGB_8888 |
3027 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3028 case DRM_FORMAT_XRGB2101010:
3029 return PLANE_CTL_FORMAT_XRGB_2101010;
3030 case DRM_FORMAT_XBGR2101010:
3031 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3032 case DRM_FORMAT_YUYV:
3033 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3034 case DRM_FORMAT_YVYU:
3035 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3036 case DRM_FORMAT_UYVY:
3037 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3038 case DRM_FORMAT_VYUY:
3039 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3040 default:
3041 MISSING_CASE(pixel_format);
3042 }
3043
3044 return 0;
3045 }
3046
3047 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3048 {
3049 switch (fb_modifier) {
3050 case DRM_FORMAT_MOD_NONE:
3051 break;
3052 case I915_FORMAT_MOD_X_TILED:
3053 return PLANE_CTL_TILED_X;
3054 case I915_FORMAT_MOD_Y_TILED:
3055 return PLANE_CTL_TILED_Y;
3056 case I915_FORMAT_MOD_Yf_TILED:
3057 return PLANE_CTL_TILED_YF;
3058 default:
3059 MISSING_CASE(fb_modifier);
3060 }
3061
3062 return 0;
3063 }
3064
3065 u32 skl_plane_ctl_rotation(unsigned int rotation)
3066 {
3067 switch (rotation) {
3068 case BIT(DRM_ROTATE_0):
3069 break;
3070 /*
3071 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3072 * while i915 HW rotation is clockwise, thats why this swapping.
3073 */
3074 case BIT(DRM_ROTATE_90):
3075 return PLANE_CTL_ROTATE_270;
3076 case BIT(DRM_ROTATE_180):
3077 return PLANE_CTL_ROTATE_180;
3078 case BIT(DRM_ROTATE_270):
3079 return PLANE_CTL_ROTATE_90;
3080 default:
3081 MISSING_CASE(rotation);
3082 }
3083
3084 return 0;
3085 }
3086
3087 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3088 struct drm_framebuffer *fb,
3089 int x, int y)
3090 {
3091 struct drm_device *dev = crtc->dev;
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3094 struct drm_plane *plane = crtc->primary;
3095 bool visible = to_intel_plane_state(plane->state)->visible;
3096 struct drm_i915_gem_object *obj;
3097 int pipe = intel_crtc->pipe;
3098 u32 plane_ctl, stride_div, stride;
3099 u32 tile_height, plane_offset, plane_size;
3100 unsigned int rotation;
3101 int x_offset, y_offset;
3102 unsigned long surf_addr;
3103 struct intel_crtc_state *crtc_state = intel_crtc->config;
3104 struct intel_plane_state *plane_state;
3105 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3106 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3107 int scaler_id = -1;
3108
3109 plane_state = to_intel_plane_state(plane->state);
3110
3111 if (!visible || !fb) {
3112 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3113 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3114 POSTING_READ(PLANE_CTL(pipe, 0));
3115 return;
3116 }
3117
3118 plane_ctl = PLANE_CTL_ENABLE |
3119 PLANE_CTL_PIPE_GAMMA_ENABLE |
3120 PLANE_CTL_PIPE_CSC_ENABLE;
3121
3122 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3123 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3124 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3125
3126 rotation = plane->state->rotation;
3127 plane_ctl |= skl_plane_ctl_rotation(rotation);
3128
3129 obj = intel_fb_obj(fb);
3130 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3131 fb->pixel_format);
3132 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3133
3134 /*
3135 * FIXME: intel_plane_state->src, dst aren't set when transitional
3136 * update_plane helpers are called from legacy paths.
3137 * Once full atomic crtc is available, below check can be avoided.
3138 */
3139 if (drm_rect_width(&plane_state->src)) {
3140 scaler_id = plane_state->scaler_id;
3141 src_x = plane_state->src.x1 >> 16;
3142 src_y = plane_state->src.y1 >> 16;
3143 src_w = drm_rect_width(&plane_state->src) >> 16;
3144 src_h = drm_rect_height(&plane_state->src) >> 16;
3145 dst_x = plane_state->dst.x1;
3146 dst_y = plane_state->dst.y1;
3147 dst_w = drm_rect_width(&plane_state->dst);
3148 dst_h = drm_rect_height(&plane_state->dst);
3149
3150 WARN_ON(x != src_x || y != src_y);
3151 } else {
3152 src_w = intel_crtc->config->pipe_src_w;
3153 src_h = intel_crtc->config->pipe_src_h;
3154 }
3155
3156 if (intel_rotation_90_or_270(rotation)) {
3157 /* stride = Surface height in tiles */
3158 tile_height = intel_tile_height(dev, fb->pixel_format,
3159 fb->modifier[0], 0);
3160 stride = DIV_ROUND_UP(fb->height, tile_height);
3161 x_offset = stride * tile_height - y - src_h;
3162 y_offset = x;
3163 plane_size = (src_w - 1) << 16 | (src_h - 1);
3164 } else {
3165 stride = fb->pitches[0] / stride_div;
3166 x_offset = x;
3167 y_offset = y;
3168 plane_size = (src_h - 1) << 16 | (src_w - 1);
3169 }
3170 plane_offset = y_offset << 16 | x_offset;
3171
3172 intel_crtc->adjusted_x = x_offset;
3173 intel_crtc->adjusted_y = y_offset;
3174
3175 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3176 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3177 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3178 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3179
3180 if (scaler_id >= 0) {
3181 uint32_t ps_ctrl = 0;
3182
3183 WARN_ON(!dst_w || !dst_h);
3184 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3185 crtc_state->scaler_state.scalers[scaler_id].mode;
3186 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3187 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3188 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3189 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3190 I915_WRITE(PLANE_POS(pipe, 0), 0);
3191 } else {
3192 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3193 }
3194
3195 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3196
3197 POSTING_READ(PLANE_SURF(pipe, 0));
3198 }
3199
3200 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3201 static int
3202 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3203 int x, int y, enum mode_set_atomic state)
3204 {
3205 struct drm_device *dev = crtc->dev;
3206 struct drm_i915_private *dev_priv = dev->dev_private;
3207
3208 if (dev_priv->fbc.disable_fbc)
3209 dev_priv->fbc.disable_fbc(dev_priv);
3210
3211 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3212
3213 return 0;
3214 }
3215
3216 static void intel_complete_page_flips(struct drm_device *dev)
3217 {
3218 struct drm_crtc *crtc;
3219
3220 for_each_crtc(dev, crtc) {
3221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3222 enum plane plane = intel_crtc->plane;
3223
3224 intel_prepare_page_flip(dev, plane);
3225 intel_finish_page_flip_plane(dev, plane);
3226 }
3227 }
3228
3229 static void intel_update_primary_planes(struct drm_device *dev)
3230 {
3231 struct drm_crtc *crtc;
3232
3233 for_each_crtc(dev, crtc) {
3234 struct intel_plane *plane = to_intel_plane(crtc->primary);
3235 struct intel_plane_state *plane_state;
3236
3237 drm_modeset_lock_crtc(crtc, &plane->base);
3238
3239 plane_state = to_intel_plane_state(plane->base.state);
3240
3241 if (plane_state->base.fb)
3242 plane->commit_plane(&plane->base, plane_state);
3243
3244 drm_modeset_unlock_crtc(crtc);
3245 }
3246 }
3247
3248 void intel_prepare_reset(struct drm_device *dev)
3249 {
3250 /* no reset support for gen2 */
3251 if (IS_GEN2(dev))
3252 return;
3253
3254 /* reset doesn't touch the display */
3255 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3256 return;
3257
3258 drm_modeset_lock_all(dev);
3259 /*
3260 * Disabling the crtcs gracefully seems nicer. Also the
3261 * g33 docs say we should at least disable all the planes.
3262 */
3263 intel_display_suspend(dev);
3264 }
3265
3266 void intel_finish_reset(struct drm_device *dev)
3267 {
3268 struct drm_i915_private *dev_priv = to_i915(dev);
3269
3270 /*
3271 * Flips in the rings will be nuked by the reset,
3272 * so complete all pending flips so that user space
3273 * will get its events and not get stuck.
3274 */
3275 intel_complete_page_flips(dev);
3276
3277 /* no reset support for gen2 */
3278 if (IS_GEN2(dev))
3279 return;
3280
3281 /* reset doesn't touch the display */
3282 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3283 /*
3284 * Flips in the rings have been nuked by the reset,
3285 * so update the base address of all primary
3286 * planes to the the last fb to make sure we're
3287 * showing the correct fb after a reset.
3288 *
3289 * FIXME: Atomic will make this obsolete since we won't schedule
3290 * CS-based flips (which might get lost in gpu resets) any more.
3291 */
3292 intel_update_primary_planes(dev);
3293 return;
3294 }
3295
3296 /*
3297 * The display has been reset as well,
3298 * so need a full re-initialization.
3299 */
3300 intel_runtime_pm_disable_interrupts(dev_priv);
3301 intel_runtime_pm_enable_interrupts(dev_priv);
3302
3303 intel_modeset_init_hw(dev);
3304
3305 spin_lock_irq(&dev_priv->irq_lock);
3306 if (dev_priv->display.hpd_irq_setup)
3307 dev_priv->display.hpd_irq_setup(dev);
3308 spin_unlock_irq(&dev_priv->irq_lock);
3309
3310 intel_display_resume(dev);
3311
3312 intel_hpd_init(dev_priv);
3313
3314 drm_modeset_unlock_all(dev);
3315 }
3316
3317 static void
3318 intel_finish_fb(struct drm_framebuffer *old_fb)
3319 {
3320 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3321 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3322 bool was_interruptible = dev_priv->mm.interruptible;
3323 int ret;
3324
3325 /* Big Hammer, we also need to ensure that any pending
3326 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3327 * current scanout is retired before unpinning the old
3328 * framebuffer. Note that we rely on userspace rendering
3329 * into the buffer attached to the pipe they are waiting
3330 * on. If not, userspace generates a GPU hang with IPEHR
3331 * point to the MI_WAIT_FOR_EVENT.
3332 *
3333 * This should only fail upon a hung GPU, in which case we
3334 * can safely continue.
3335 */
3336 dev_priv->mm.interruptible = false;
3337 ret = i915_gem_object_wait_rendering(obj, true);
3338 dev_priv->mm.interruptible = was_interruptible;
3339
3340 WARN_ON(ret);
3341 }
3342
3343 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3344 {
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 bool pending;
3349
3350 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3351 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3352 return false;
3353
3354 spin_lock_irq(&dev->event_lock);
3355 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3356 spin_unlock_irq(&dev->event_lock);
3357
3358 return pending;
3359 }
3360
3361 static void intel_update_pipe_config(struct intel_crtc *crtc,
3362 struct intel_crtc_state *old_crtc_state)
3363 {
3364 struct drm_device *dev = crtc->base.dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct intel_crtc_state *pipe_config =
3367 to_intel_crtc_state(crtc->base.state);
3368
3369 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3370 crtc->base.mode = crtc->base.state->mode;
3371
3372 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3373 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3374 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3375
3376 if (HAS_DDI(dev))
3377 intel_set_pipe_csc(&crtc->base);
3378
3379 /*
3380 * Update pipe size and adjust fitter if needed: the reason for this is
3381 * that in compute_mode_changes we check the native mode (not the pfit
3382 * mode) to see if we can flip rather than do a full mode set. In the
3383 * fastboot case, we'll flip, but if we don't update the pipesrc and
3384 * pfit state, we'll end up with a big fb scanned out into the wrong
3385 * sized surface.
3386 */
3387
3388 I915_WRITE(PIPESRC(crtc->pipe),
3389 ((pipe_config->pipe_src_w - 1) << 16) |
3390 (pipe_config->pipe_src_h - 1));
3391
3392 /* on skylake this is done by detaching scalers */
3393 if (INTEL_INFO(dev)->gen >= 9) {
3394 skl_detach_scalers(crtc);
3395
3396 if (pipe_config->pch_pfit.enabled)
3397 skylake_pfit_enable(crtc);
3398 } else if (HAS_PCH_SPLIT(dev)) {
3399 if (pipe_config->pch_pfit.enabled)
3400 ironlake_pfit_enable(crtc);
3401 else if (old_crtc_state->pch_pfit.enabled)
3402 ironlake_pfit_disable(crtc, true);
3403 }
3404 }
3405
3406 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3407 {
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
3412 u32 reg, temp;
3413
3414 /* enable normal train */
3415 reg = FDI_TX_CTL(pipe);
3416 temp = I915_READ(reg);
3417 if (IS_IVYBRIDGE(dev)) {
3418 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3419 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3420 } else {
3421 temp &= ~FDI_LINK_TRAIN_NONE;
3422 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3423 }
3424 I915_WRITE(reg, temp);
3425
3426 reg = FDI_RX_CTL(pipe);
3427 temp = I915_READ(reg);
3428 if (HAS_PCH_CPT(dev)) {
3429 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3430 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3431 } else {
3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_NONE;
3434 }
3435 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3436
3437 /* wait one idle pattern time */
3438 POSTING_READ(reg);
3439 udelay(1000);
3440
3441 /* IVB wants error correction enabled */
3442 if (IS_IVYBRIDGE(dev))
3443 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3444 FDI_FE_ERRC_ENABLE);
3445 }
3446
3447 /* The FDI link training functions for ILK/Ibexpeak. */
3448 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3449 {
3450 struct drm_device *dev = crtc->dev;
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453 int pipe = intel_crtc->pipe;
3454 u32 reg, temp, tries;
3455
3456 /* FDI needs bits from pipe first */
3457 assert_pipe_enabled(dev_priv, pipe);
3458
3459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3460 for train result */
3461 reg = FDI_RX_IMR(pipe);
3462 temp = I915_READ(reg);
3463 temp &= ~FDI_RX_SYMBOL_LOCK;
3464 temp &= ~FDI_RX_BIT_LOCK;
3465 I915_WRITE(reg, temp);
3466 I915_READ(reg);
3467 udelay(150);
3468
3469 /* enable CPU FDI TX and PCH FDI RX */
3470 reg = FDI_TX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3473 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3474 temp &= ~FDI_LINK_TRAIN_NONE;
3475 temp |= FDI_LINK_TRAIN_PATTERN_1;
3476 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3477
3478 reg = FDI_RX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1;
3482 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3483
3484 POSTING_READ(reg);
3485 udelay(150);
3486
3487 /* Ironlake workaround, enable clock pointer after FDI enable*/
3488 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3489 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3490 FDI_RX_PHASE_SYNC_POINTER_EN);
3491
3492 reg = FDI_RX_IIR(pipe);
3493 for (tries = 0; tries < 5; tries++) {
3494 temp = I915_READ(reg);
3495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3496
3497 if ((temp & FDI_RX_BIT_LOCK)) {
3498 DRM_DEBUG_KMS("FDI train 1 done.\n");
3499 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3500 break;
3501 }
3502 }
3503 if (tries == 5)
3504 DRM_ERROR("FDI train 1 fail!\n");
3505
3506 /* Train 2 */
3507 reg = FDI_TX_CTL(pipe);
3508 temp = I915_READ(reg);
3509 temp &= ~FDI_LINK_TRAIN_NONE;
3510 temp |= FDI_LINK_TRAIN_PATTERN_2;
3511 I915_WRITE(reg, temp);
3512
3513 reg = FDI_RX_CTL(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_LINK_TRAIN_NONE;
3516 temp |= FDI_LINK_TRAIN_PATTERN_2;
3517 I915_WRITE(reg, temp);
3518
3519 POSTING_READ(reg);
3520 udelay(150);
3521
3522 reg = FDI_RX_IIR(pipe);
3523 for (tries = 0; tries < 5; tries++) {
3524 temp = I915_READ(reg);
3525 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3526
3527 if (temp & FDI_RX_SYMBOL_LOCK) {
3528 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3529 DRM_DEBUG_KMS("FDI train 2 done.\n");
3530 break;
3531 }
3532 }
3533 if (tries == 5)
3534 DRM_ERROR("FDI train 2 fail!\n");
3535
3536 DRM_DEBUG_KMS("FDI train done\n");
3537
3538 }
3539
3540 static const int snb_b_fdi_train_param[] = {
3541 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3542 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3543 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3544 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3545 };
3546
3547 /* The FDI link training functions for SNB/Cougarpoint. */
3548 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3549 {
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 int pipe = intel_crtc->pipe;
3554 u32 reg, temp, i, retry;
3555
3556 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3557 for train result */
3558 reg = FDI_RX_IMR(pipe);
3559 temp = I915_READ(reg);
3560 temp &= ~FDI_RX_SYMBOL_LOCK;
3561 temp &= ~FDI_RX_BIT_LOCK;
3562 I915_WRITE(reg, temp);
3563
3564 POSTING_READ(reg);
3565 udelay(150);
3566
3567 /* enable CPU FDI TX and PCH FDI RX */
3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3571 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3572 temp &= ~FDI_LINK_TRAIN_NONE;
3573 temp |= FDI_LINK_TRAIN_PATTERN_1;
3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575 /* SNB-B */
3576 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3577 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3578
3579 I915_WRITE(FDI_RX_MISC(pipe),
3580 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3581
3582 reg = FDI_RX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 if (HAS_PCH_CPT(dev)) {
3585 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3586 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3587 } else {
3588 temp &= ~FDI_LINK_TRAIN_NONE;
3589 temp |= FDI_LINK_TRAIN_PATTERN_1;
3590 }
3591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3592
3593 POSTING_READ(reg);
3594 udelay(150);
3595
3596 for (i = 0; i < 4; i++) {
3597 reg = FDI_TX_CTL(pipe);
3598 temp = I915_READ(reg);
3599 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3600 temp |= snb_b_fdi_train_param[i];
3601 I915_WRITE(reg, temp);
3602
3603 POSTING_READ(reg);
3604 udelay(500);
3605
3606 for (retry = 0; retry < 5; retry++) {
3607 reg = FDI_RX_IIR(pipe);
3608 temp = I915_READ(reg);
3609 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3610 if (temp & FDI_RX_BIT_LOCK) {
3611 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3612 DRM_DEBUG_KMS("FDI train 1 done.\n");
3613 break;
3614 }
3615 udelay(50);
3616 }
3617 if (retry < 5)
3618 break;
3619 }
3620 if (i == 4)
3621 DRM_ERROR("FDI train 1 fail!\n");
3622
3623 /* Train 2 */
3624 reg = FDI_TX_CTL(pipe);
3625 temp = I915_READ(reg);
3626 temp &= ~FDI_LINK_TRAIN_NONE;
3627 temp |= FDI_LINK_TRAIN_PATTERN_2;
3628 if (IS_GEN6(dev)) {
3629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3630 /* SNB-B */
3631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3632 }
3633 I915_WRITE(reg, temp);
3634
3635 reg = FDI_RX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 if (HAS_PCH_CPT(dev)) {
3638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3639 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3640 } else {
3641 temp &= ~FDI_LINK_TRAIN_NONE;
3642 temp |= FDI_LINK_TRAIN_PATTERN_2;
3643 }
3644 I915_WRITE(reg, temp);
3645
3646 POSTING_READ(reg);
3647 udelay(150);
3648
3649 for (i = 0; i < 4; i++) {
3650 reg = FDI_TX_CTL(pipe);
3651 temp = I915_READ(reg);
3652 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3653 temp |= snb_b_fdi_train_param[i];
3654 I915_WRITE(reg, temp);
3655
3656 POSTING_READ(reg);
3657 udelay(500);
3658
3659 for (retry = 0; retry < 5; retry++) {
3660 reg = FDI_RX_IIR(pipe);
3661 temp = I915_READ(reg);
3662 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3663 if (temp & FDI_RX_SYMBOL_LOCK) {
3664 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3665 DRM_DEBUG_KMS("FDI train 2 done.\n");
3666 break;
3667 }
3668 udelay(50);
3669 }
3670 if (retry < 5)
3671 break;
3672 }
3673 if (i == 4)
3674 DRM_ERROR("FDI train 2 fail!\n");
3675
3676 DRM_DEBUG_KMS("FDI train done.\n");
3677 }
3678
3679 /* Manual link training for Ivy Bridge A0 parts */
3680 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3681 {
3682 struct drm_device *dev = crtc->dev;
3683 struct drm_i915_private *dev_priv = dev->dev_private;
3684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685 int pipe = intel_crtc->pipe;
3686 u32 reg, temp, i, j;
3687
3688 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3689 for train result */
3690 reg = FDI_RX_IMR(pipe);
3691 temp = I915_READ(reg);
3692 temp &= ~FDI_RX_SYMBOL_LOCK;
3693 temp &= ~FDI_RX_BIT_LOCK;
3694 I915_WRITE(reg, temp);
3695
3696 POSTING_READ(reg);
3697 udelay(150);
3698
3699 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3700 I915_READ(FDI_RX_IIR(pipe)));
3701
3702 /* Try each vswing and preemphasis setting twice before moving on */
3703 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3704 /* disable first in case we need to retry */
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3708 temp &= ~FDI_TX_ENABLE;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_AUTO;
3714 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3715 temp &= ~FDI_RX_ENABLE;
3716 I915_WRITE(reg, temp);
3717
3718 /* enable CPU FDI TX and PCH FDI RX */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3722 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3723 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3724 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3725 temp |= snb_b_fdi_train_param[j/2];
3726 temp |= FDI_COMPOSITE_SYNC;
3727 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3728
3729 I915_WRITE(FDI_RX_MISC(pipe),
3730 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3731
3732 reg = FDI_RX_CTL(pipe);
3733 temp = I915_READ(reg);
3734 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3735 temp |= FDI_COMPOSITE_SYNC;
3736 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3737
3738 POSTING_READ(reg);
3739 udelay(1); /* should be 0.5us */
3740
3741 for (i = 0; i < 4; i++) {
3742 reg = FDI_RX_IIR(pipe);
3743 temp = I915_READ(reg);
3744 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3745
3746 if (temp & FDI_RX_BIT_LOCK ||
3747 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3748 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3749 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3750 i);
3751 break;
3752 }
3753 udelay(1); /* should be 0.5us */
3754 }
3755 if (i == 4) {
3756 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3757 continue;
3758 }
3759
3760 /* Train 2 */
3761 reg = FDI_TX_CTL(pipe);
3762 temp = I915_READ(reg);
3763 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3764 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3765 I915_WRITE(reg, temp);
3766
3767 reg = FDI_RX_CTL(pipe);
3768 temp = I915_READ(reg);
3769 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3770 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3771 I915_WRITE(reg, temp);
3772
3773 POSTING_READ(reg);
3774 udelay(2); /* should be 1.5us */
3775
3776 for (i = 0; i < 4; i++) {
3777 reg = FDI_RX_IIR(pipe);
3778 temp = I915_READ(reg);
3779 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3780
3781 if (temp & FDI_RX_SYMBOL_LOCK ||
3782 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3783 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3784 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3785 i);
3786 goto train_done;
3787 }
3788 udelay(2); /* should be 1.5us */
3789 }
3790 if (i == 4)
3791 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3792 }
3793
3794 train_done:
3795 DRM_DEBUG_KMS("FDI train done.\n");
3796 }
3797
3798 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3799 {
3800 struct drm_device *dev = intel_crtc->base.dev;
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 int pipe = intel_crtc->pipe;
3803 u32 reg, temp;
3804
3805
3806 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3807 reg = FDI_RX_CTL(pipe);
3808 temp = I915_READ(reg);
3809 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3810 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3811 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3812 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3813
3814 POSTING_READ(reg);
3815 udelay(200);
3816
3817 /* Switch from Rawclk to PCDclk */
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp | FDI_PCDCLK);
3820
3821 POSTING_READ(reg);
3822 udelay(200);
3823
3824 /* Enable CPU FDI TX PLL, always on for Ironlake */
3825 reg = FDI_TX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3828 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3829
3830 POSTING_READ(reg);
3831 udelay(100);
3832 }
3833 }
3834
3835 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3836 {
3837 struct drm_device *dev = intel_crtc->base.dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 int pipe = intel_crtc->pipe;
3840 u32 reg, temp;
3841
3842 /* Switch from PCDclk to Rawclk */
3843 reg = FDI_RX_CTL(pipe);
3844 temp = I915_READ(reg);
3845 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3846
3847 /* Disable CPU FDI TX PLL */
3848 reg = FDI_TX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3851
3852 POSTING_READ(reg);
3853 udelay(100);
3854
3855 reg = FDI_RX_CTL(pipe);
3856 temp = I915_READ(reg);
3857 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3858
3859 /* Wait for the clocks to turn off. */
3860 POSTING_READ(reg);
3861 udelay(100);
3862 }
3863
3864 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3865 {
3866 struct drm_device *dev = crtc->dev;
3867 struct drm_i915_private *dev_priv = dev->dev_private;
3868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3869 int pipe = intel_crtc->pipe;
3870 u32 reg, temp;
3871
3872 /* disable CPU FDI tx and PCH FDI rx */
3873 reg = FDI_TX_CTL(pipe);
3874 temp = I915_READ(reg);
3875 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3876 POSTING_READ(reg);
3877
3878 reg = FDI_RX_CTL(pipe);
3879 temp = I915_READ(reg);
3880 temp &= ~(0x7 << 16);
3881 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3882 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3883
3884 POSTING_READ(reg);
3885 udelay(100);
3886
3887 /* Ironlake workaround, disable clock pointer after downing FDI */
3888 if (HAS_PCH_IBX(dev))
3889 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3890
3891 /* still set train pattern 1 */
3892 reg = FDI_TX_CTL(pipe);
3893 temp = I915_READ(reg);
3894 temp &= ~FDI_LINK_TRAIN_NONE;
3895 temp |= FDI_LINK_TRAIN_PATTERN_1;
3896 I915_WRITE(reg, temp);
3897
3898 reg = FDI_RX_CTL(pipe);
3899 temp = I915_READ(reg);
3900 if (HAS_PCH_CPT(dev)) {
3901 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3902 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3903 } else {
3904 temp &= ~FDI_LINK_TRAIN_NONE;
3905 temp |= FDI_LINK_TRAIN_PATTERN_1;
3906 }
3907 /* BPC in FDI rx is consistent with that in PIPECONF */
3908 temp &= ~(0x07 << 16);
3909 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3910 I915_WRITE(reg, temp);
3911
3912 POSTING_READ(reg);
3913 udelay(100);
3914 }
3915
3916 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3917 {
3918 struct intel_crtc *crtc;
3919
3920 /* Note that we don't need to be called with mode_config.lock here
3921 * as our list of CRTC objects is static for the lifetime of the
3922 * device and so cannot disappear as we iterate. Similarly, we can
3923 * happily treat the predicates as racy, atomic checks as userspace
3924 * cannot claim and pin a new fb without at least acquring the
3925 * struct_mutex and so serialising with us.
3926 */
3927 for_each_intel_crtc(dev, crtc) {
3928 if (atomic_read(&crtc->unpin_work_count) == 0)
3929 continue;
3930
3931 if (crtc->unpin_work)
3932 intel_wait_for_vblank(dev, crtc->pipe);
3933
3934 return true;
3935 }
3936
3937 return false;
3938 }
3939
3940 static void page_flip_completed(struct intel_crtc *intel_crtc)
3941 {
3942 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3943 struct intel_unpin_work *work = intel_crtc->unpin_work;
3944
3945 /* ensure that the unpin work is consistent wrt ->pending. */
3946 smp_rmb();
3947 intel_crtc->unpin_work = NULL;
3948
3949 if (work->event)
3950 drm_send_vblank_event(intel_crtc->base.dev,
3951 intel_crtc->pipe,
3952 work->event);
3953
3954 drm_crtc_vblank_put(&intel_crtc->base);
3955
3956 wake_up_all(&dev_priv->pending_flip_queue);
3957 queue_work(dev_priv->wq, &work->work);
3958
3959 trace_i915_flip_complete(intel_crtc->plane,
3960 work->pending_flip_obj);
3961 }
3962
3963 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3964 {
3965 struct drm_device *dev = crtc->dev;
3966 struct drm_i915_private *dev_priv = dev->dev_private;
3967
3968 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3969 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3970 !intel_crtc_has_pending_flip(crtc),
3971 60*HZ) == 0)) {
3972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3973
3974 spin_lock_irq(&dev->event_lock);
3975 if (intel_crtc->unpin_work) {
3976 WARN_ONCE(1, "Removing stuck page flip\n");
3977 page_flip_completed(intel_crtc);
3978 }
3979 spin_unlock_irq(&dev->event_lock);
3980 }
3981
3982 if (crtc->primary->fb) {
3983 mutex_lock(&dev->struct_mutex);
3984 intel_finish_fb(crtc->primary->fb);
3985 mutex_unlock(&dev->struct_mutex);
3986 }
3987 }
3988
3989 /* Program iCLKIP clock to the desired frequency */
3990 static void lpt_program_iclkip(struct drm_crtc *crtc)
3991 {
3992 struct drm_device *dev = crtc->dev;
3993 struct drm_i915_private *dev_priv = dev->dev_private;
3994 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3995 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3996 u32 temp;
3997
3998 mutex_lock(&dev_priv->sb_lock);
3999
4000 /* It is necessary to ungate the pixclk gate prior to programming
4001 * the divisors, and gate it back when it is done.
4002 */
4003 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4004
4005 /* Disable SSCCTL */
4006 intel_sbi_write(dev_priv, SBI_SSCCTL6,
4007 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4008 SBI_SSCCTL_DISABLE,
4009 SBI_ICLK);
4010
4011 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
4012 if (clock == 20000) {
4013 auxdiv = 1;
4014 divsel = 0x41;
4015 phaseinc = 0x20;
4016 } else {
4017 /* The iCLK virtual clock root frequency is in MHz,
4018 * but the adjusted_mode->crtc_clock in in KHz. To get the
4019 * divisors, it is necessary to divide one by another, so we
4020 * convert the virtual clock precision to KHz here for higher
4021 * precision.
4022 */
4023 u32 iclk_virtual_root_freq = 172800 * 1000;
4024 u32 iclk_pi_range = 64;
4025 u32 desired_divisor, msb_divisor_value, pi_value;
4026
4027 desired_divisor = (iclk_virtual_root_freq / clock);
4028 msb_divisor_value = desired_divisor / iclk_pi_range;
4029 pi_value = desired_divisor % iclk_pi_range;
4030
4031 auxdiv = 0;
4032 divsel = msb_divisor_value - 2;
4033 phaseinc = pi_value;
4034 }
4035
4036 /* This should not happen with any sane values */
4037 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4038 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4039 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4040 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4041
4042 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4043 clock,
4044 auxdiv,
4045 divsel,
4046 phasedir,
4047 phaseinc);
4048
4049 /* Program SSCDIVINTPHASE6 */
4050 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4051 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4052 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4053 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4054 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4055 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4056 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4057 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4058
4059 /* Program SSCAUXDIV */
4060 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4061 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4062 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4063 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4064
4065 /* Enable modulator and associated divider */
4066 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4067 temp &= ~SBI_SSCCTL_DISABLE;
4068 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4069
4070 /* Wait for initialization time */
4071 udelay(24);
4072
4073 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4074
4075 mutex_unlock(&dev_priv->sb_lock);
4076 }
4077
4078 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4079 enum pipe pch_transcoder)
4080 {
4081 struct drm_device *dev = crtc->base.dev;
4082 struct drm_i915_private *dev_priv = dev->dev_private;
4083 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4084
4085 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4086 I915_READ(HTOTAL(cpu_transcoder)));
4087 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4088 I915_READ(HBLANK(cpu_transcoder)));
4089 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4090 I915_READ(HSYNC(cpu_transcoder)));
4091
4092 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4093 I915_READ(VTOTAL(cpu_transcoder)));
4094 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4095 I915_READ(VBLANK(cpu_transcoder)));
4096 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4097 I915_READ(VSYNC(cpu_transcoder)));
4098 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4099 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4100 }
4101
4102 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4103 {
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 uint32_t temp;
4106
4107 temp = I915_READ(SOUTH_CHICKEN1);
4108 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4109 return;
4110
4111 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4112 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4113
4114 temp &= ~FDI_BC_BIFURCATION_SELECT;
4115 if (enable)
4116 temp |= FDI_BC_BIFURCATION_SELECT;
4117
4118 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4119 I915_WRITE(SOUTH_CHICKEN1, temp);
4120 POSTING_READ(SOUTH_CHICKEN1);
4121 }
4122
4123 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4124 {
4125 struct drm_device *dev = intel_crtc->base.dev;
4126
4127 switch (intel_crtc->pipe) {
4128 case PIPE_A:
4129 break;
4130 case PIPE_B:
4131 if (intel_crtc->config->fdi_lanes > 2)
4132 cpt_set_fdi_bc_bifurcation(dev, false);
4133 else
4134 cpt_set_fdi_bc_bifurcation(dev, true);
4135
4136 break;
4137 case PIPE_C:
4138 cpt_set_fdi_bc_bifurcation(dev, true);
4139
4140 break;
4141 default:
4142 BUG();
4143 }
4144 }
4145
4146 /*
4147 * Enable PCH resources required for PCH ports:
4148 * - PCH PLLs
4149 * - FDI training & RX/TX
4150 * - update transcoder timings
4151 * - DP transcoding bits
4152 * - transcoder
4153 */
4154 static void ironlake_pch_enable(struct drm_crtc *crtc)
4155 {
4156 struct drm_device *dev = crtc->dev;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159 int pipe = intel_crtc->pipe;
4160 u32 reg, temp;
4161
4162 assert_pch_transcoder_disabled(dev_priv, pipe);
4163
4164 if (IS_IVYBRIDGE(dev))
4165 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4166
4167 /* Write the TU size bits before fdi link training, so that error
4168 * detection works. */
4169 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4170 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4171
4172 /* For PCH output, training FDI link */
4173 dev_priv->display.fdi_link_train(crtc);
4174
4175 /* We need to program the right clock selection before writing the pixel
4176 * mutliplier into the DPLL. */
4177 if (HAS_PCH_CPT(dev)) {
4178 u32 sel;
4179
4180 temp = I915_READ(PCH_DPLL_SEL);
4181 temp |= TRANS_DPLL_ENABLE(pipe);
4182 sel = TRANS_DPLLB_SEL(pipe);
4183 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4184 temp |= sel;
4185 else
4186 temp &= ~sel;
4187 I915_WRITE(PCH_DPLL_SEL, temp);
4188 }
4189
4190 /* XXX: pch pll's can be enabled any time before we enable the PCH
4191 * transcoder, and we actually should do this to not upset any PCH
4192 * transcoder that already use the clock when we share it.
4193 *
4194 * Note that enable_shared_dpll tries to do the right thing, but
4195 * get_shared_dpll unconditionally resets the pll - we need that to have
4196 * the right LVDS enable sequence. */
4197 intel_enable_shared_dpll(intel_crtc);
4198
4199 /* set transcoder timing, panel must allow it */
4200 assert_panel_unlocked(dev_priv, pipe);
4201 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4202
4203 intel_fdi_normal_train(crtc);
4204
4205 /* For PCH DP, enable TRANS_DP_CTL */
4206 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4207 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4208 reg = TRANS_DP_CTL(pipe);
4209 temp = I915_READ(reg);
4210 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4211 TRANS_DP_SYNC_MASK |
4212 TRANS_DP_BPC_MASK);
4213 temp |= TRANS_DP_OUTPUT_ENABLE;
4214 temp |= bpc << 9; /* same format but at 11:9 */
4215
4216 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4217 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4218 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4219 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4220
4221 switch (intel_trans_dp_port_sel(crtc)) {
4222 case PCH_DP_B:
4223 temp |= TRANS_DP_PORT_SEL_B;
4224 break;
4225 case PCH_DP_C:
4226 temp |= TRANS_DP_PORT_SEL_C;
4227 break;
4228 case PCH_DP_D:
4229 temp |= TRANS_DP_PORT_SEL_D;
4230 break;
4231 default:
4232 BUG();
4233 }
4234
4235 I915_WRITE(reg, temp);
4236 }
4237
4238 ironlake_enable_pch_transcoder(dev_priv, pipe);
4239 }
4240
4241 static void lpt_pch_enable(struct drm_crtc *crtc)
4242 {
4243 struct drm_device *dev = crtc->dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4246 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4247
4248 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4249
4250 lpt_program_iclkip(crtc);
4251
4252 /* Set transcoder timing. */
4253 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4254
4255 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4256 }
4257
4258 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4259 struct intel_crtc_state *crtc_state)
4260 {
4261 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4262 struct intel_shared_dpll *pll;
4263 struct intel_shared_dpll_config *shared_dpll;
4264 enum intel_dpll_id i;
4265
4266 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4267
4268 if (HAS_PCH_IBX(dev_priv->dev)) {
4269 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4270 i = (enum intel_dpll_id) crtc->pipe;
4271 pll = &dev_priv->shared_dplls[i];
4272
4273 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4274 crtc->base.base.id, pll->name);
4275
4276 WARN_ON(shared_dpll[i].crtc_mask);
4277
4278 goto found;
4279 }
4280
4281 if (IS_BROXTON(dev_priv->dev)) {
4282 /* PLL is attached to port in bxt */
4283 struct intel_encoder *encoder;
4284 struct intel_digital_port *intel_dig_port;
4285
4286 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4287 if (WARN_ON(!encoder))
4288 return NULL;
4289
4290 intel_dig_port = enc_to_dig_port(&encoder->base);
4291 /* 1:1 mapping between ports and PLLs */
4292 i = (enum intel_dpll_id)intel_dig_port->port;
4293 pll = &dev_priv->shared_dplls[i];
4294 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4295 crtc->base.base.id, pll->name);
4296 WARN_ON(shared_dpll[i].crtc_mask);
4297
4298 goto found;
4299 }
4300
4301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4302 pll = &dev_priv->shared_dplls[i];
4303
4304 /* Only want to check enabled timings first */
4305 if (shared_dpll[i].crtc_mask == 0)
4306 continue;
4307
4308 if (memcmp(&crtc_state->dpll_hw_state,
4309 &shared_dpll[i].hw_state,
4310 sizeof(crtc_state->dpll_hw_state)) == 0) {
4311 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4312 crtc->base.base.id, pll->name,
4313 shared_dpll[i].crtc_mask,
4314 pll->active);
4315 goto found;
4316 }
4317 }
4318
4319 /* Ok no matching timings, maybe there's a free one? */
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322 if (shared_dpll[i].crtc_mask == 0) {
4323 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4324 crtc->base.base.id, pll->name);
4325 goto found;
4326 }
4327 }
4328
4329 return NULL;
4330
4331 found:
4332 if (shared_dpll[i].crtc_mask == 0)
4333 shared_dpll[i].hw_state =
4334 crtc_state->dpll_hw_state;
4335
4336 crtc_state->shared_dpll = i;
4337 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4338 pipe_name(crtc->pipe));
4339
4340 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4341
4342 return pll;
4343 }
4344
4345 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4346 {
4347 struct drm_i915_private *dev_priv = to_i915(state->dev);
4348 struct intel_shared_dpll_config *shared_dpll;
4349 struct intel_shared_dpll *pll;
4350 enum intel_dpll_id i;
4351
4352 if (!to_intel_atomic_state(state)->dpll_set)
4353 return;
4354
4355 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4356 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4357 pll = &dev_priv->shared_dplls[i];
4358 pll->config = shared_dpll[i];
4359 }
4360 }
4361
4362 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4363 {
4364 struct drm_i915_private *dev_priv = dev->dev_private;
4365 int dslreg = PIPEDSL(pipe);
4366 u32 temp;
4367
4368 temp = I915_READ(dslreg);
4369 udelay(500);
4370 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4371 if (wait_for(I915_READ(dslreg) != temp, 5))
4372 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4373 }
4374 }
4375
4376 static int
4377 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4378 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4379 int src_w, int src_h, int dst_w, int dst_h)
4380 {
4381 struct intel_crtc_scaler_state *scaler_state =
4382 &crtc_state->scaler_state;
4383 struct intel_crtc *intel_crtc =
4384 to_intel_crtc(crtc_state->base.crtc);
4385 int need_scaling;
4386
4387 need_scaling = intel_rotation_90_or_270(rotation) ?
4388 (src_h != dst_w || src_w != dst_h):
4389 (src_w != dst_w || src_h != dst_h);
4390
4391 /*
4392 * if plane is being disabled or scaler is no more required or force detach
4393 * - free scaler binded to this plane/crtc
4394 * - in order to do this, update crtc->scaler_usage
4395 *
4396 * Here scaler state in crtc_state is set free so that
4397 * scaler can be assigned to other user. Actual register
4398 * update to free the scaler is done in plane/panel-fit programming.
4399 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4400 */
4401 if (force_detach || !need_scaling) {
4402 if (*scaler_id >= 0) {
4403 scaler_state->scaler_users &= ~(1 << scaler_user);
4404 scaler_state->scalers[*scaler_id].in_use = 0;
4405
4406 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4407 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4408 intel_crtc->pipe, scaler_user, *scaler_id,
4409 scaler_state->scaler_users);
4410 *scaler_id = -1;
4411 }
4412 return 0;
4413 }
4414
4415 /* range checks */
4416 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4417 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4418
4419 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4420 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4421 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4422 "size is out of scaler range\n",
4423 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4424 return -EINVAL;
4425 }
4426
4427 /* mark this plane as a scaler user in crtc_state */
4428 scaler_state->scaler_users |= (1 << scaler_user);
4429 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4430 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4431 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4432 scaler_state->scaler_users);
4433
4434 return 0;
4435 }
4436
4437 /**
4438 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4439 *
4440 * @state: crtc's scaler state
4441 *
4442 * Return
4443 * 0 - scaler_usage updated successfully
4444 * error - requested scaling cannot be supported or other error condition
4445 */
4446 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4447 {
4448 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4449 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4450
4451 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4452 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4453
4454 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4455 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4456 state->pipe_src_w, state->pipe_src_h,
4457 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4458 }
4459
4460 /**
4461 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4462 *
4463 * @state: crtc's scaler state
4464 * @plane_state: atomic plane state to update
4465 *
4466 * Return
4467 * 0 - scaler_usage updated successfully
4468 * error - requested scaling cannot be supported or other error condition
4469 */
4470 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4471 struct intel_plane_state *plane_state)
4472 {
4473
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4475 struct intel_plane *intel_plane =
4476 to_intel_plane(plane_state->base.plane);
4477 struct drm_framebuffer *fb = plane_state->base.fb;
4478 int ret;
4479
4480 bool force_detach = !fb || !plane_state->visible;
4481
4482 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4483 intel_plane->base.base.id, intel_crtc->pipe,
4484 drm_plane_index(&intel_plane->base));
4485
4486 ret = skl_update_scaler(crtc_state, force_detach,
4487 drm_plane_index(&intel_plane->base),
4488 &plane_state->scaler_id,
4489 plane_state->base.rotation,
4490 drm_rect_width(&plane_state->src) >> 16,
4491 drm_rect_height(&plane_state->src) >> 16,
4492 drm_rect_width(&plane_state->dst),
4493 drm_rect_height(&plane_state->dst));
4494
4495 if (ret || plane_state->scaler_id < 0)
4496 return ret;
4497
4498 /* check colorkey */
4499 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4500 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4501 intel_plane->base.base.id);
4502 return -EINVAL;
4503 }
4504
4505 /* Check src format */
4506 switch (fb->pixel_format) {
4507 case DRM_FORMAT_RGB565:
4508 case DRM_FORMAT_XBGR8888:
4509 case DRM_FORMAT_XRGB8888:
4510 case DRM_FORMAT_ABGR8888:
4511 case DRM_FORMAT_ARGB8888:
4512 case DRM_FORMAT_XRGB2101010:
4513 case DRM_FORMAT_XBGR2101010:
4514 case DRM_FORMAT_YUYV:
4515 case DRM_FORMAT_YVYU:
4516 case DRM_FORMAT_UYVY:
4517 case DRM_FORMAT_VYUY:
4518 break;
4519 default:
4520 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4521 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4522 return -EINVAL;
4523 }
4524
4525 return 0;
4526 }
4527
4528 static void skylake_scaler_disable(struct intel_crtc *crtc)
4529 {
4530 int i;
4531
4532 for (i = 0; i < crtc->num_scalers; i++)
4533 skl_detach_scaler(crtc, i);
4534 }
4535
4536 static void skylake_pfit_enable(struct intel_crtc *crtc)
4537 {
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 int pipe = crtc->pipe;
4541 struct intel_crtc_scaler_state *scaler_state =
4542 &crtc->config->scaler_state;
4543
4544 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4545
4546 if (crtc->config->pch_pfit.enabled) {
4547 int id;
4548
4549 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4550 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4551 return;
4552 }
4553
4554 id = scaler_state->scaler_id;
4555 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4556 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4557 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4558 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4559
4560 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4561 }
4562 }
4563
4564 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4565 {
4566 struct drm_device *dev = crtc->base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 int pipe = crtc->pipe;
4569
4570 if (crtc->config->pch_pfit.enabled) {
4571 /* Force use of hard-coded filter coefficients
4572 * as some pre-programmed values are broken,
4573 * e.g. x201.
4574 */
4575 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4576 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4577 PF_PIPE_SEL_IVB(pipe));
4578 else
4579 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4580 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4581 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4582 }
4583 }
4584
4585 void hsw_enable_ips(struct intel_crtc *crtc)
4586 {
4587 struct drm_device *dev = crtc->base.dev;
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4589
4590 if (!crtc->config->ips_enabled)
4591 return;
4592
4593 /* We can only enable IPS after we enable a plane and wait for a vblank */
4594 intel_wait_for_vblank(dev, crtc->pipe);
4595
4596 assert_plane_enabled(dev_priv, crtc->plane);
4597 if (IS_BROADWELL(dev)) {
4598 mutex_lock(&dev_priv->rps.hw_lock);
4599 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4600 mutex_unlock(&dev_priv->rps.hw_lock);
4601 /* Quoting Art Runyan: "its not safe to expect any particular
4602 * value in IPS_CTL bit 31 after enabling IPS through the
4603 * mailbox." Moreover, the mailbox may return a bogus state,
4604 * so we need to just enable it and continue on.
4605 */
4606 } else {
4607 I915_WRITE(IPS_CTL, IPS_ENABLE);
4608 /* The bit only becomes 1 in the next vblank, so this wait here
4609 * is essentially intel_wait_for_vblank. If we don't have this
4610 * and don't wait for vblanks until the end of crtc_enable, then
4611 * the HW state readout code will complain that the expected
4612 * IPS_CTL value is not the one we read. */
4613 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4614 DRM_ERROR("Timed out waiting for IPS enable\n");
4615 }
4616 }
4617
4618 void hsw_disable_ips(struct intel_crtc *crtc)
4619 {
4620 struct drm_device *dev = crtc->base.dev;
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622
4623 if (!crtc->config->ips_enabled)
4624 return;
4625
4626 assert_plane_enabled(dev_priv, crtc->plane);
4627 if (IS_BROADWELL(dev)) {
4628 mutex_lock(&dev_priv->rps.hw_lock);
4629 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4630 mutex_unlock(&dev_priv->rps.hw_lock);
4631 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4632 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4633 DRM_ERROR("Timed out waiting for IPS disable\n");
4634 } else {
4635 I915_WRITE(IPS_CTL, 0);
4636 POSTING_READ(IPS_CTL);
4637 }
4638
4639 /* We need to wait for a vblank before we can disable the plane. */
4640 intel_wait_for_vblank(dev, crtc->pipe);
4641 }
4642
4643 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4644 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4645 {
4646 struct drm_device *dev = crtc->dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 enum pipe pipe = intel_crtc->pipe;
4650 int i;
4651 bool reenable_ips = false;
4652
4653 /* The clocks have to be on to load the palette. */
4654 if (!crtc->state->active)
4655 return;
4656
4657 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4658 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4659 assert_dsi_pll_enabled(dev_priv);
4660 else
4661 assert_pll_enabled(dev_priv, pipe);
4662 }
4663
4664 /* Workaround : Do not read or write the pipe palette/gamma data while
4665 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4666 */
4667 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4668 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4669 GAMMA_MODE_MODE_SPLIT)) {
4670 hsw_disable_ips(intel_crtc);
4671 reenable_ips = true;
4672 }
4673
4674 for (i = 0; i < 256; i++) {
4675 u32 palreg;
4676
4677 if (HAS_GMCH_DISPLAY(dev))
4678 palreg = PALETTE(pipe, i);
4679 else
4680 palreg = LGC_PALETTE(pipe, i);
4681
4682 I915_WRITE(palreg,
4683 (intel_crtc->lut_r[i] << 16) |
4684 (intel_crtc->lut_g[i] << 8) |
4685 intel_crtc->lut_b[i]);
4686 }
4687
4688 if (reenable_ips)
4689 hsw_enable_ips(intel_crtc);
4690 }
4691
4692 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4693 {
4694 if (intel_crtc->overlay) {
4695 struct drm_device *dev = intel_crtc->base.dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697
4698 mutex_lock(&dev->struct_mutex);
4699 dev_priv->mm.interruptible = false;
4700 (void) intel_overlay_switch_off(intel_crtc->overlay);
4701 dev_priv->mm.interruptible = true;
4702 mutex_unlock(&dev->struct_mutex);
4703 }
4704
4705 /* Let userspace switch the overlay on again. In most cases userspace
4706 * has to recompute where to put it anyway.
4707 */
4708 }
4709
4710 /**
4711 * intel_post_enable_primary - Perform operations after enabling primary plane
4712 * @crtc: the CRTC whose primary plane was just enabled
4713 *
4714 * Performs potentially sleeping operations that must be done after the primary
4715 * plane is enabled, such as updating FBC and IPS. Note that this may be
4716 * called due to an explicit primary plane update, or due to an implicit
4717 * re-enable that is caused when a sprite plane is updated to no longer
4718 * completely hide the primary plane.
4719 */
4720 static void
4721 intel_post_enable_primary(struct drm_crtc *crtc)
4722 {
4723 struct drm_device *dev = crtc->dev;
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4726 int pipe = intel_crtc->pipe;
4727
4728 /*
4729 * BDW signals flip done immediately if the plane
4730 * is disabled, even if the plane enable is already
4731 * armed to occur at the next vblank :(
4732 */
4733 if (IS_BROADWELL(dev))
4734 intel_wait_for_vblank(dev, pipe);
4735
4736 /*
4737 * FIXME IPS should be fine as long as one plane is
4738 * enabled, but in practice it seems to have problems
4739 * when going from primary only to sprite only and vice
4740 * versa.
4741 */
4742 hsw_enable_ips(intel_crtc);
4743
4744 /*
4745 * Gen2 reports pipe underruns whenever all planes are disabled.
4746 * So don't enable underrun reporting before at least some planes
4747 * are enabled.
4748 * FIXME: Need to fix the logic to work when we turn off all planes
4749 * but leave the pipe running.
4750 */
4751 if (IS_GEN2(dev))
4752 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4753
4754 /* Underruns don't raise interrupts, so check manually. */
4755 if (HAS_GMCH_DISPLAY(dev))
4756 i9xx_check_fifo_underruns(dev_priv);
4757 }
4758
4759 /**
4760 * intel_pre_disable_primary - Perform operations before disabling primary plane
4761 * @crtc: the CRTC whose primary plane is to be disabled
4762 *
4763 * Performs potentially sleeping operations that must be done before the
4764 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4765 * be called due to an explicit primary plane update, or due to an implicit
4766 * disable that is caused when a sprite plane completely hides the primary
4767 * plane.
4768 */
4769 static void
4770 intel_pre_disable_primary(struct drm_crtc *crtc)
4771 {
4772 struct drm_device *dev = crtc->dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4775 int pipe = intel_crtc->pipe;
4776
4777 /*
4778 * Gen2 reports pipe underruns whenever all planes are disabled.
4779 * So diasble underrun reporting before all the planes get disabled.
4780 * FIXME: Need to fix the logic to work when we turn off all planes
4781 * but leave the pipe running.
4782 */
4783 if (IS_GEN2(dev))
4784 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4785
4786 /*
4787 * Vblank time updates from the shadow to live plane control register
4788 * are blocked if the memory self-refresh mode is active at that
4789 * moment. So to make sure the plane gets truly disabled, disable
4790 * first the self-refresh mode. The self-refresh enable bit in turn
4791 * will be checked/applied by the HW only at the next frame start
4792 * event which is after the vblank start event, so we need to have a
4793 * wait-for-vblank between disabling the plane and the pipe.
4794 */
4795 if (HAS_GMCH_DISPLAY(dev)) {
4796 intel_set_memory_cxsr(dev_priv, false);
4797 dev_priv->wm.vlv.cxsr = false;
4798 intel_wait_for_vblank(dev, pipe);
4799 }
4800
4801 /*
4802 * FIXME IPS should be fine as long as one plane is
4803 * enabled, but in practice it seems to have problems
4804 * when going from primary only to sprite only and vice
4805 * versa.
4806 */
4807 hsw_disable_ips(intel_crtc);
4808 }
4809
4810 static void intel_post_plane_update(struct intel_crtc *crtc)
4811 {
4812 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4813 struct drm_device *dev = crtc->base.dev;
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815
4816 if (atomic->wait_vblank)
4817 intel_wait_for_vblank(dev, crtc->pipe);
4818
4819 intel_frontbuffer_flip(dev, atomic->fb_bits);
4820
4821 if (atomic->disable_cxsr)
4822 crtc->wm.cxsr_allowed = true;
4823
4824 if (crtc->atomic.update_wm_post)
4825 intel_update_watermarks(&crtc->base);
4826
4827 if (atomic->update_fbc)
4828 intel_fbc_update(dev_priv);
4829
4830 if (atomic->post_enable_primary)
4831 intel_post_enable_primary(&crtc->base);
4832
4833 memset(atomic, 0, sizeof(*atomic));
4834 }
4835
4836 static void intel_pre_plane_update(struct intel_crtc *crtc)
4837 {
4838 struct drm_device *dev = crtc->base.dev;
4839 struct drm_i915_private *dev_priv = dev->dev_private;
4840 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4841 struct drm_plane *p;
4842
4843 /* Track fb's for any planes being disabled */
4844 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4845 struct intel_plane *plane = to_intel_plane(p);
4846
4847 mutex_lock(&dev->struct_mutex);
4848 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4849 plane->frontbuffer_bit);
4850 mutex_unlock(&dev->struct_mutex);
4851 }
4852
4853 if (atomic->wait_for_flips)
4854 intel_crtc_wait_for_pending_flips(&crtc->base);
4855
4856 if (atomic->disable_fbc)
4857 intel_fbc_disable_crtc(crtc);
4858
4859 if (crtc->atomic.disable_ips)
4860 hsw_disable_ips(crtc);
4861
4862 if (atomic->pre_disable_primary)
4863 intel_pre_disable_primary(&crtc->base);
4864
4865 if (atomic->disable_cxsr) {
4866 crtc->wm.cxsr_allowed = false;
4867 intel_set_memory_cxsr(dev_priv, false);
4868 }
4869 }
4870
4871 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4872 {
4873 struct drm_device *dev = crtc->dev;
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875 struct drm_plane *p;
4876 int pipe = intel_crtc->pipe;
4877
4878 intel_crtc_dpms_overlay_disable(intel_crtc);
4879
4880 drm_for_each_plane_mask(p, dev, plane_mask)
4881 to_intel_plane(p)->disable_plane(p, crtc);
4882
4883 /*
4884 * FIXME: Once we grow proper nuclear flip support out of this we need
4885 * to compute the mask of flip planes precisely. For the time being
4886 * consider this a flip to a NULL plane.
4887 */
4888 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4889 }
4890
4891 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4892 {
4893 struct drm_device *dev = crtc->dev;
4894 struct drm_i915_private *dev_priv = dev->dev_private;
4895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4896 struct intel_encoder *encoder;
4897 int pipe = intel_crtc->pipe;
4898
4899 if (WARN_ON(intel_crtc->active))
4900 return;
4901
4902 if (intel_crtc->config->has_pch_encoder)
4903 intel_prepare_shared_dpll(intel_crtc);
4904
4905 if (intel_crtc->config->has_dp_encoder)
4906 intel_dp_set_m_n(intel_crtc, M1_N1);
4907
4908 intel_set_pipe_timings(intel_crtc);
4909
4910 if (intel_crtc->config->has_pch_encoder) {
4911 intel_cpu_transcoder_set_m_n(intel_crtc,
4912 &intel_crtc->config->fdi_m_n, NULL);
4913 }
4914
4915 ironlake_set_pipeconf(crtc);
4916
4917 intel_crtc->active = true;
4918
4919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4920 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4921
4922 for_each_encoder_on_crtc(dev, crtc, encoder)
4923 if (encoder->pre_enable)
4924 encoder->pre_enable(encoder);
4925
4926 if (intel_crtc->config->has_pch_encoder) {
4927 /* Note: FDI PLL enabling _must_ be done before we enable the
4928 * cpu pipes, hence this is separate from all the other fdi/pch
4929 * enabling. */
4930 ironlake_fdi_pll_enable(intel_crtc);
4931 } else {
4932 assert_fdi_tx_disabled(dev_priv, pipe);
4933 assert_fdi_rx_disabled(dev_priv, pipe);
4934 }
4935
4936 ironlake_pfit_enable(intel_crtc);
4937
4938 /*
4939 * On ILK+ LUT must be loaded before the pipe is running but with
4940 * clocks enabled
4941 */
4942 intel_crtc_load_lut(crtc);
4943
4944 intel_update_watermarks(crtc);
4945 intel_enable_pipe(intel_crtc);
4946
4947 if (intel_crtc->config->has_pch_encoder)
4948 ironlake_pch_enable(crtc);
4949
4950 assert_vblank_disabled(crtc);
4951 drm_crtc_vblank_on(crtc);
4952
4953 for_each_encoder_on_crtc(dev, crtc, encoder)
4954 encoder->enable(encoder);
4955
4956 if (HAS_PCH_CPT(dev))
4957 cpt_verify_modeset(dev, intel_crtc->pipe);
4958 }
4959
4960 /* IPS only exists on ULT machines and is tied to pipe A. */
4961 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4962 {
4963 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4964 }
4965
4966 static void haswell_crtc_enable(struct drm_crtc *crtc)
4967 {
4968 struct drm_device *dev = crtc->dev;
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4971 struct intel_encoder *encoder;
4972 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4973 struct intel_crtc_state *pipe_config =
4974 to_intel_crtc_state(crtc->state);
4975 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4976
4977 if (WARN_ON(intel_crtc->active))
4978 return;
4979
4980 if (intel_crtc_to_shared_dpll(intel_crtc))
4981 intel_enable_shared_dpll(intel_crtc);
4982
4983 if (intel_crtc->config->has_dp_encoder)
4984 intel_dp_set_m_n(intel_crtc, M1_N1);
4985
4986 intel_set_pipe_timings(intel_crtc);
4987
4988 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4989 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4990 intel_crtc->config->pixel_multiplier - 1);
4991 }
4992
4993 if (intel_crtc->config->has_pch_encoder) {
4994 intel_cpu_transcoder_set_m_n(intel_crtc,
4995 &intel_crtc->config->fdi_m_n, NULL);
4996 }
4997
4998 haswell_set_pipeconf(crtc);
4999
5000 intel_set_pipe_csc(crtc);
5001
5002 intel_crtc->active = true;
5003
5004 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5005 for_each_encoder_on_crtc(dev, crtc, encoder) {
5006 if (encoder->pre_pll_enable)
5007 encoder->pre_pll_enable(encoder);
5008 if (encoder->pre_enable)
5009 encoder->pre_enable(encoder);
5010 }
5011
5012 if (intel_crtc->config->has_pch_encoder) {
5013 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5014 true);
5015 dev_priv->display.fdi_link_train(crtc);
5016 }
5017
5018 if (!is_dsi)
5019 intel_ddi_enable_pipe_clock(intel_crtc);
5020
5021 if (INTEL_INFO(dev)->gen >= 9)
5022 skylake_pfit_enable(intel_crtc);
5023 else
5024 ironlake_pfit_enable(intel_crtc);
5025
5026 /*
5027 * On ILK+ LUT must be loaded before the pipe is running but with
5028 * clocks enabled
5029 */
5030 intel_crtc_load_lut(crtc);
5031
5032 intel_ddi_set_pipe_settings(crtc);
5033 if (!is_dsi)
5034 intel_ddi_enable_transcoder_func(crtc);
5035
5036 intel_update_watermarks(crtc);
5037 intel_enable_pipe(intel_crtc);
5038
5039 if (intel_crtc->config->has_pch_encoder)
5040 lpt_pch_enable(crtc);
5041
5042 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5043 intel_ddi_set_vc_payload_alloc(crtc, true);
5044
5045 assert_vblank_disabled(crtc);
5046 drm_crtc_vblank_on(crtc);
5047
5048 for_each_encoder_on_crtc(dev, crtc, encoder) {
5049 encoder->enable(encoder);
5050 intel_opregion_notify_encoder(encoder, true);
5051 }
5052
5053 /* If we change the relative order between pipe/planes enabling, we need
5054 * to change the workaround. */
5055 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5056 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5057 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5058 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5059 }
5060 }
5061
5062 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5063 {
5064 struct drm_device *dev = crtc->base.dev;
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5066 int pipe = crtc->pipe;
5067
5068 /* To avoid upsetting the power well on haswell only disable the pfit if
5069 * it's in use. The hw state code will make sure we get this right. */
5070 if (force || crtc->config->pch_pfit.enabled) {
5071 I915_WRITE(PF_CTL(pipe), 0);
5072 I915_WRITE(PF_WIN_POS(pipe), 0);
5073 I915_WRITE(PF_WIN_SZ(pipe), 0);
5074 }
5075 }
5076
5077 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5078 {
5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082 struct intel_encoder *encoder;
5083 int pipe = intel_crtc->pipe;
5084 u32 reg, temp;
5085
5086 for_each_encoder_on_crtc(dev, crtc, encoder)
5087 encoder->disable(encoder);
5088
5089 drm_crtc_vblank_off(crtc);
5090 assert_vblank_disabled(crtc);
5091
5092 if (intel_crtc->config->has_pch_encoder)
5093 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5094
5095 intel_disable_pipe(intel_crtc);
5096
5097 ironlake_pfit_disable(intel_crtc, false);
5098
5099 if (intel_crtc->config->has_pch_encoder)
5100 ironlake_fdi_disable(crtc);
5101
5102 for_each_encoder_on_crtc(dev, crtc, encoder)
5103 if (encoder->post_disable)
5104 encoder->post_disable(encoder);
5105
5106 if (intel_crtc->config->has_pch_encoder) {
5107 ironlake_disable_pch_transcoder(dev_priv, pipe);
5108
5109 if (HAS_PCH_CPT(dev)) {
5110 /* disable TRANS_DP_CTL */
5111 reg = TRANS_DP_CTL(pipe);
5112 temp = I915_READ(reg);
5113 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5114 TRANS_DP_PORT_SEL_MASK);
5115 temp |= TRANS_DP_PORT_SEL_NONE;
5116 I915_WRITE(reg, temp);
5117
5118 /* disable DPLL_SEL */
5119 temp = I915_READ(PCH_DPLL_SEL);
5120 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5121 I915_WRITE(PCH_DPLL_SEL, temp);
5122 }
5123
5124 ironlake_fdi_pll_disable(intel_crtc);
5125 }
5126 }
5127
5128 static void haswell_crtc_disable(struct drm_crtc *crtc)
5129 {
5130 struct drm_device *dev = crtc->dev;
5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133 struct intel_encoder *encoder;
5134 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5135 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5136
5137 for_each_encoder_on_crtc(dev, crtc, encoder) {
5138 intel_opregion_notify_encoder(encoder, false);
5139 encoder->disable(encoder);
5140 }
5141
5142 drm_crtc_vblank_off(crtc);
5143 assert_vblank_disabled(crtc);
5144
5145 if (intel_crtc->config->has_pch_encoder)
5146 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5147 false);
5148 intel_disable_pipe(intel_crtc);
5149
5150 if (intel_crtc->config->dp_encoder_is_mst)
5151 intel_ddi_set_vc_payload_alloc(crtc, false);
5152
5153 if (!is_dsi)
5154 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5155
5156 if (INTEL_INFO(dev)->gen >= 9)
5157 skylake_scaler_disable(intel_crtc);
5158 else
5159 ironlake_pfit_disable(intel_crtc, false);
5160
5161 if (!is_dsi)
5162 intel_ddi_disable_pipe_clock(intel_crtc);
5163
5164 if (intel_crtc->config->has_pch_encoder) {
5165 lpt_disable_pch_transcoder(dev_priv);
5166 intel_ddi_fdi_disable(crtc);
5167 }
5168
5169 for_each_encoder_on_crtc(dev, crtc, encoder)
5170 if (encoder->post_disable)
5171 encoder->post_disable(encoder);
5172 }
5173
5174 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5175 {
5176 struct drm_device *dev = crtc->base.dev;
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 struct intel_crtc_state *pipe_config = crtc->config;
5179
5180 if (!pipe_config->gmch_pfit.control)
5181 return;
5182
5183 /*
5184 * The panel fitter should only be adjusted whilst the pipe is disabled,
5185 * according to register description and PRM.
5186 */
5187 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5188 assert_pipe_disabled(dev_priv, crtc->pipe);
5189
5190 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5191 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5192
5193 /* Border color in case we don't scale up to the full screen. Black by
5194 * default, change to something else for debugging. */
5195 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5196 }
5197
5198 static enum intel_display_power_domain port_to_power_domain(enum port port)
5199 {
5200 switch (port) {
5201 case PORT_A:
5202 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5203 case PORT_B:
5204 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5205 case PORT_C:
5206 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5207 case PORT_D:
5208 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5209 case PORT_E:
5210 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5211 default:
5212 WARN_ON_ONCE(1);
5213 return POWER_DOMAIN_PORT_OTHER;
5214 }
5215 }
5216
5217 #define for_each_power_domain(domain, mask) \
5218 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5219 if ((1 << (domain)) & (mask))
5220
5221 enum intel_display_power_domain
5222 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5223 {
5224 struct drm_device *dev = intel_encoder->base.dev;
5225 struct intel_digital_port *intel_dig_port;
5226
5227 switch (intel_encoder->type) {
5228 case INTEL_OUTPUT_UNKNOWN:
5229 /* Only DDI platforms should ever use this output type */
5230 WARN_ON_ONCE(!HAS_DDI(dev));
5231 case INTEL_OUTPUT_DISPLAYPORT:
5232 case INTEL_OUTPUT_HDMI:
5233 case INTEL_OUTPUT_EDP:
5234 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5235 return port_to_power_domain(intel_dig_port->port);
5236 case INTEL_OUTPUT_DP_MST:
5237 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5238 return port_to_power_domain(intel_dig_port->port);
5239 case INTEL_OUTPUT_ANALOG:
5240 return POWER_DOMAIN_PORT_CRT;
5241 case INTEL_OUTPUT_DSI:
5242 return POWER_DOMAIN_PORT_DSI;
5243 default:
5244 return POWER_DOMAIN_PORT_OTHER;
5245 }
5246 }
5247
5248 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5249 {
5250 struct drm_device *dev = crtc->dev;
5251 struct intel_encoder *intel_encoder;
5252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5253 enum pipe pipe = intel_crtc->pipe;
5254 unsigned long mask;
5255 enum transcoder transcoder;
5256
5257 if (!crtc->state->active)
5258 return 0;
5259
5260 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5261
5262 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5263 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5264 if (intel_crtc->config->pch_pfit.enabled ||
5265 intel_crtc->config->pch_pfit.force_thru)
5266 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5267
5268 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5269 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5270
5271 return mask;
5272 }
5273
5274 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5275 {
5276 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5278 enum intel_display_power_domain domain;
5279 unsigned long domains, new_domains, old_domains;
5280
5281 old_domains = intel_crtc->enabled_power_domains;
5282 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5283
5284 domains = new_domains & ~old_domains;
5285
5286 for_each_power_domain(domain, domains)
5287 intel_display_power_get(dev_priv, domain);
5288
5289 return old_domains & ~new_domains;
5290 }
5291
5292 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5293 unsigned long domains)
5294 {
5295 enum intel_display_power_domain domain;
5296
5297 for_each_power_domain(domain, domains)
5298 intel_display_power_put(dev_priv, domain);
5299 }
5300
5301 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5302 {
5303 struct drm_device *dev = state->dev;
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305 unsigned long put_domains[I915_MAX_PIPES] = {};
5306 struct drm_crtc_state *crtc_state;
5307 struct drm_crtc *crtc;
5308 int i;
5309
5310 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5311 if (needs_modeset(crtc->state))
5312 put_domains[to_intel_crtc(crtc)->pipe] =
5313 modeset_get_crtc_power_domains(crtc);
5314 }
5315
5316 if (dev_priv->display.modeset_commit_cdclk) {
5317 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5318
5319 if (cdclk != dev_priv->cdclk_freq &&
5320 !WARN_ON(!state->allow_modeset))
5321 dev_priv->display.modeset_commit_cdclk(state);
5322 }
5323
5324 for (i = 0; i < I915_MAX_PIPES; i++)
5325 if (put_domains[i])
5326 modeset_put_power_domains(dev_priv, put_domains[i]);
5327 }
5328
5329 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5330 {
5331 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5332
5333 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5334 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5335 return max_cdclk_freq;
5336 else if (IS_CHERRYVIEW(dev_priv))
5337 return max_cdclk_freq*95/100;
5338 else if (INTEL_INFO(dev_priv)->gen < 4)
5339 return 2*max_cdclk_freq*90/100;
5340 else
5341 return max_cdclk_freq*90/100;
5342 }
5343
5344 static void intel_update_max_cdclk(struct drm_device *dev)
5345 {
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347
5348 if (IS_SKYLAKE(dev)) {
5349 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5350
5351 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5352 dev_priv->max_cdclk_freq = 675000;
5353 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5354 dev_priv->max_cdclk_freq = 540000;
5355 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5356 dev_priv->max_cdclk_freq = 450000;
5357 else
5358 dev_priv->max_cdclk_freq = 337500;
5359 } else if (IS_BROADWELL(dev)) {
5360 /*
5361 * FIXME with extra cooling we can allow
5362 * 540 MHz for ULX and 675 Mhz for ULT.
5363 * How can we know if extra cooling is
5364 * available? PCI ID, VTB, something else?
5365 */
5366 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5367 dev_priv->max_cdclk_freq = 450000;
5368 else if (IS_BDW_ULX(dev))
5369 dev_priv->max_cdclk_freq = 450000;
5370 else if (IS_BDW_ULT(dev))
5371 dev_priv->max_cdclk_freq = 540000;
5372 else
5373 dev_priv->max_cdclk_freq = 675000;
5374 } else if (IS_CHERRYVIEW(dev)) {
5375 dev_priv->max_cdclk_freq = 320000;
5376 } else if (IS_VALLEYVIEW(dev)) {
5377 dev_priv->max_cdclk_freq = 400000;
5378 } else {
5379 /* otherwise assume cdclk is fixed */
5380 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5381 }
5382
5383 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5384
5385 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5386 dev_priv->max_cdclk_freq);
5387
5388 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5389 dev_priv->max_dotclk_freq);
5390 }
5391
5392 static void intel_update_cdclk(struct drm_device *dev)
5393 {
5394 struct drm_i915_private *dev_priv = dev->dev_private;
5395
5396 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5397 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5398 dev_priv->cdclk_freq);
5399
5400 /*
5401 * Program the gmbus_freq based on the cdclk frequency.
5402 * BSpec erroneously claims we should aim for 4MHz, but
5403 * in fact 1MHz is the correct frequency.
5404 */
5405 if (IS_VALLEYVIEW(dev)) {
5406 /*
5407 * Program the gmbus_freq based on the cdclk frequency.
5408 * BSpec erroneously claims we should aim for 4MHz, but
5409 * in fact 1MHz is the correct frequency.
5410 */
5411 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5412 }
5413
5414 if (dev_priv->max_cdclk_freq == 0)
5415 intel_update_max_cdclk(dev);
5416 }
5417
5418 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5419 {
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 uint32_t divider;
5422 uint32_t ratio;
5423 uint32_t current_freq;
5424 int ret;
5425
5426 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5427 switch (frequency) {
5428 case 144000:
5429 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5430 ratio = BXT_DE_PLL_RATIO(60);
5431 break;
5432 case 288000:
5433 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5434 ratio = BXT_DE_PLL_RATIO(60);
5435 break;
5436 case 384000:
5437 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5438 ratio = BXT_DE_PLL_RATIO(60);
5439 break;
5440 case 576000:
5441 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5442 ratio = BXT_DE_PLL_RATIO(60);
5443 break;
5444 case 624000:
5445 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5446 ratio = BXT_DE_PLL_RATIO(65);
5447 break;
5448 case 19200:
5449 /*
5450 * Bypass frequency with DE PLL disabled. Init ratio, divider
5451 * to suppress GCC warning.
5452 */
5453 ratio = 0;
5454 divider = 0;
5455 break;
5456 default:
5457 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5458
5459 return;
5460 }
5461
5462 mutex_lock(&dev_priv->rps.hw_lock);
5463 /* Inform power controller of upcoming frequency change */
5464 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5465 0x80000000);
5466 mutex_unlock(&dev_priv->rps.hw_lock);
5467
5468 if (ret) {
5469 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5470 ret, frequency);
5471 return;
5472 }
5473
5474 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5475 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5476 current_freq = current_freq * 500 + 1000;
5477
5478 /*
5479 * DE PLL has to be disabled when
5480 * - setting to 19.2MHz (bypass, PLL isn't used)
5481 * - before setting to 624MHz (PLL needs toggling)
5482 * - before setting to any frequency from 624MHz (PLL needs toggling)
5483 */
5484 if (frequency == 19200 || frequency == 624000 ||
5485 current_freq == 624000) {
5486 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5487 /* Timeout 200us */
5488 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5489 1))
5490 DRM_ERROR("timout waiting for DE PLL unlock\n");
5491 }
5492
5493 if (frequency != 19200) {
5494 uint32_t val;
5495
5496 val = I915_READ(BXT_DE_PLL_CTL);
5497 val &= ~BXT_DE_PLL_RATIO_MASK;
5498 val |= ratio;
5499 I915_WRITE(BXT_DE_PLL_CTL, val);
5500
5501 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5502 /* Timeout 200us */
5503 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5504 DRM_ERROR("timeout waiting for DE PLL lock\n");
5505
5506 val = I915_READ(CDCLK_CTL);
5507 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5508 val |= divider;
5509 /*
5510 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5511 * enable otherwise.
5512 */
5513 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5514 if (frequency >= 500000)
5515 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5516
5517 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5518 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5519 val |= (frequency - 1000) / 500;
5520 I915_WRITE(CDCLK_CTL, val);
5521 }
5522
5523 mutex_lock(&dev_priv->rps.hw_lock);
5524 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5525 DIV_ROUND_UP(frequency, 25000));
5526 mutex_unlock(&dev_priv->rps.hw_lock);
5527
5528 if (ret) {
5529 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5530 ret, frequency);
5531 return;
5532 }
5533
5534 intel_update_cdclk(dev);
5535 }
5536
5537 void broxton_init_cdclk(struct drm_device *dev)
5538 {
5539 struct drm_i915_private *dev_priv = dev->dev_private;
5540 uint32_t val;
5541
5542 /*
5543 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5544 * or else the reset will hang because there is no PCH to respond.
5545 * Move the handshake programming to initialization sequence.
5546 * Previously was left up to BIOS.
5547 */
5548 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5549 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5550 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5551
5552 /* Enable PG1 for cdclk */
5553 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5554
5555 /* check if cd clock is enabled */
5556 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5557 DRM_DEBUG_KMS("Display already initialized\n");
5558 return;
5559 }
5560
5561 /*
5562 * FIXME:
5563 * - The initial CDCLK needs to be read from VBT.
5564 * Need to make this change after VBT has changes for BXT.
5565 * - check if setting the max (or any) cdclk freq is really necessary
5566 * here, it belongs to modeset time
5567 */
5568 broxton_set_cdclk(dev, 624000);
5569
5570 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5571 POSTING_READ(DBUF_CTL);
5572
5573 udelay(10);
5574
5575 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5576 DRM_ERROR("DBuf power enable timeout!\n");
5577 }
5578
5579 void broxton_uninit_cdclk(struct drm_device *dev)
5580 {
5581 struct drm_i915_private *dev_priv = dev->dev_private;
5582
5583 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5584 POSTING_READ(DBUF_CTL);
5585
5586 udelay(10);
5587
5588 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5589 DRM_ERROR("DBuf power disable timeout!\n");
5590
5591 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5592 broxton_set_cdclk(dev, 19200);
5593
5594 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5595 }
5596
5597 static const struct skl_cdclk_entry {
5598 unsigned int freq;
5599 unsigned int vco;
5600 } skl_cdclk_frequencies[] = {
5601 { .freq = 308570, .vco = 8640 },
5602 { .freq = 337500, .vco = 8100 },
5603 { .freq = 432000, .vco = 8640 },
5604 { .freq = 450000, .vco = 8100 },
5605 { .freq = 540000, .vco = 8100 },
5606 { .freq = 617140, .vco = 8640 },
5607 { .freq = 675000, .vco = 8100 },
5608 };
5609
5610 static unsigned int skl_cdclk_decimal(unsigned int freq)
5611 {
5612 return (freq - 1000) / 500;
5613 }
5614
5615 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5616 {
5617 unsigned int i;
5618
5619 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5620 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5621
5622 if (e->freq == freq)
5623 return e->vco;
5624 }
5625
5626 return 8100;
5627 }
5628
5629 static void
5630 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5631 {
5632 unsigned int min_freq;
5633 u32 val;
5634
5635 /* select the minimum CDCLK before enabling DPLL 0 */
5636 val = I915_READ(CDCLK_CTL);
5637 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5638 val |= CDCLK_FREQ_337_308;
5639
5640 if (required_vco == 8640)
5641 min_freq = 308570;
5642 else
5643 min_freq = 337500;
5644
5645 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5646
5647 I915_WRITE(CDCLK_CTL, val);
5648 POSTING_READ(CDCLK_CTL);
5649
5650 /*
5651 * We always enable DPLL0 with the lowest link rate possible, but still
5652 * taking into account the VCO required to operate the eDP panel at the
5653 * desired frequency. The usual DP link rates operate with a VCO of
5654 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5655 * The modeset code is responsible for the selection of the exact link
5656 * rate later on, with the constraint of choosing a frequency that
5657 * works with required_vco.
5658 */
5659 val = I915_READ(DPLL_CTRL1);
5660
5661 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5662 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5663 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5664 if (required_vco == 8640)
5665 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5666 SKL_DPLL0);
5667 else
5668 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5669 SKL_DPLL0);
5670
5671 I915_WRITE(DPLL_CTRL1, val);
5672 POSTING_READ(DPLL_CTRL1);
5673
5674 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5675
5676 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5677 DRM_ERROR("DPLL0 not locked\n");
5678 }
5679
5680 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5681 {
5682 int ret;
5683 u32 val;
5684
5685 /* inform PCU we want to change CDCLK */
5686 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5687 mutex_lock(&dev_priv->rps.hw_lock);
5688 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5689 mutex_unlock(&dev_priv->rps.hw_lock);
5690
5691 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5692 }
5693
5694 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5695 {
5696 unsigned int i;
5697
5698 for (i = 0; i < 15; i++) {
5699 if (skl_cdclk_pcu_ready(dev_priv))
5700 return true;
5701 udelay(10);
5702 }
5703
5704 return false;
5705 }
5706
5707 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5708 {
5709 struct drm_device *dev = dev_priv->dev;
5710 u32 freq_select, pcu_ack;
5711
5712 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5713
5714 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5715 DRM_ERROR("failed to inform PCU about cdclk change\n");
5716 return;
5717 }
5718
5719 /* set CDCLK_CTL */
5720 switch(freq) {
5721 case 450000:
5722 case 432000:
5723 freq_select = CDCLK_FREQ_450_432;
5724 pcu_ack = 1;
5725 break;
5726 case 540000:
5727 freq_select = CDCLK_FREQ_540;
5728 pcu_ack = 2;
5729 break;
5730 case 308570:
5731 case 337500:
5732 default:
5733 freq_select = CDCLK_FREQ_337_308;
5734 pcu_ack = 0;
5735 break;
5736 case 617140:
5737 case 675000:
5738 freq_select = CDCLK_FREQ_675_617;
5739 pcu_ack = 3;
5740 break;
5741 }
5742
5743 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5744 POSTING_READ(CDCLK_CTL);
5745
5746 /* inform PCU of the change */
5747 mutex_lock(&dev_priv->rps.hw_lock);
5748 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5749 mutex_unlock(&dev_priv->rps.hw_lock);
5750
5751 intel_update_cdclk(dev);
5752 }
5753
5754 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5755 {
5756 /* disable DBUF power */
5757 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5758 POSTING_READ(DBUF_CTL);
5759
5760 udelay(10);
5761
5762 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5763 DRM_ERROR("DBuf power disable timeout\n");
5764
5765 /*
5766 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5767 */
5768 if (dev_priv->csr.dmc_payload) {
5769 /* disable DPLL0 */
5770 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5771 ~LCPLL_PLL_ENABLE);
5772 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5773 DRM_ERROR("Couldn't disable DPLL0\n");
5774 }
5775
5776 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5777 }
5778
5779 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5780 {
5781 u32 val;
5782 unsigned int required_vco;
5783
5784 /* enable PCH reset handshake */
5785 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5786 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5787
5788 /* enable PG1 and Misc I/O */
5789 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5790
5791 /* DPLL0 not enabled (happens on early BIOS versions) */
5792 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5793 /* enable DPLL0 */
5794 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5795 skl_dpll0_enable(dev_priv, required_vco);
5796 }
5797
5798 /* set CDCLK to the frequency the BIOS chose */
5799 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5800
5801 /* enable DBUF power */
5802 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5803 POSTING_READ(DBUF_CTL);
5804
5805 udelay(10);
5806
5807 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5808 DRM_ERROR("DBuf power enable timeout\n");
5809 }
5810
5811 /* Adjust CDclk dividers to allow high res or save power if possible */
5812 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5813 {
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5815 u32 val, cmd;
5816
5817 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5818 != dev_priv->cdclk_freq);
5819
5820 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5821 cmd = 2;
5822 else if (cdclk == 266667)
5823 cmd = 1;
5824 else
5825 cmd = 0;
5826
5827 mutex_lock(&dev_priv->rps.hw_lock);
5828 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5829 val &= ~DSPFREQGUAR_MASK;
5830 val |= (cmd << DSPFREQGUAR_SHIFT);
5831 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5832 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5833 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5834 50)) {
5835 DRM_ERROR("timed out waiting for CDclk change\n");
5836 }
5837 mutex_unlock(&dev_priv->rps.hw_lock);
5838
5839 mutex_lock(&dev_priv->sb_lock);
5840
5841 if (cdclk == 400000) {
5842 u32 divider;
5843
5844 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5845
5846 /* adjust cdclk divider */
5847 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5848 val &= ~CCK_FREQUENCY_VALUES;
5849 val |= divider;
5850 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5851
5852 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5853 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5854 50))
5855 DRM_ERROR("timed out waiting for CDclk change\n");
5856 }
5857
5858 /* adjust self-refresh exit latency value */
5859 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5860 val &= ~0x7f;
5861
5862 /*
5863 * For high bandwidth configs, we set a higher latency in the bunit
5864 * so that the core display fetch happens in time to avoid underruns.
5865 */
5866 if (cdclk == 400000)
5867 val |= 4500 / 250; /* 4.5 usec */
5868 else
5869 val |= 3000 / 250; /* 3.0 usec */
5870 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5871
5872 mutex_unlock(&dev_priv->sb_lock);
5873
5874 intel_update_cdclk(dev);
5875 }
5876
5877 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5878 {
5879 struct drm_i915_private *dev_priv = dev->dev_private;
5880 u32 val, cmd;
5881
5882 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5883 != dev_priv->cdclk_freq);
5884
5885 switch (cdclk) {
5886 case 333333:
5887 case 320000:
5888 case 266667:
5889 case 200000:
5890 break;
5891 default:
5892 MISSING_CASE(cdclk);
5893 return;
5894 }
5895
5896 /*
5897 * Specs are full of misinformation, but testing on actual
5898 * hardware has shown that we just need to write the desired
5899 * CCK divider into the Punit register.
5900 */
5901 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5902
5903 mutex_lock(&dev_priv->rps.hw_lock);
5904 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5905 val &= ~DSPFREQGUAR_MASK_CHV;
5906 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5907 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5908 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5909 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5910 50)) {
5911 DRM_ERROR("timed out waiting for CDclk change\n");
5912 }
5913 mutex_unlock(&dev_priv->rps.hw_lock);
5914
5915 intel_update_cdclk(dev);
5916 }
5917
5918 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5919 int max_pixclk)
5920 {
5921 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5922 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5923
5924 /*
5925 * Really only a few cases to deal with, as only 4 CDclks are supported:
5926 * 200MHz
5927 * 267MHz
5928 * 320/333MHz (depends on HPLL freq)
5929 * 400MHz (VLV only)
5930 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5931 * of the lower bin and adjust if needed.
5932 *
5933 * We seem to get an unstable or solid color picture at 200MHz.
5934 * Not sure what's wrong. For now use 200MHz only when all pipes
5935 * are off.
5936 */
5937 if (!IS_CHERRYVIEW(dev_priv) &&
5938 max_pixclk > freq_320*limit/100)
5939 return 400000;
5940 else if (max_pixclk > 266667*limit/100)
5941 return freq_320;
5942 else if (max_pixclk > 0)
5943 return 266667;
5944 else
5945 return 200000;
5946 }
5947
5948 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5949 int max_pixclk)
5950 {
5951 /*
5952 * FIXME:
5953 * - remove the guardband, it's not needed on BXT
5954 * - set 19.2MHz bypass frequency if there are no active pipes
5955 */
5956 if (max_pixclk > 576000*9/10)
5957 return 624000;
5958 else if (max_pixclk > 384000*9/10)
5959 return 576000;
5960 else if (max_pixclk > 288000*9/10)
5961 return 384000;
5962 else if (max_pixclk > 144000*9/10)
5963 return 288000;
5964 else
5965 return 144000;
5966 }
5967
5968 /* Compute the max pixel clock for new configuration. Uses atomic state if
5969 * that's non-NULL, look at current state otherwise. */
5970 static int intel_mode_max_pixclk(struct drm_device *dev,
5971 struct drm_atomic_state *state)
5972 {
5973 struct intel_crtc *intel_crtc;
5974 struct intel_crtc_state *crtc_state;
5975 int max_pixclk = 0;
5976
5977 for_each_intel_crtc(dev, intel_crtc) {
5978 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5979 if (IS_ERR(crtc_state))
5980 return PTR_ERR(crtc_state);
5981
5982 if (!crtc_state->base.enable)
5983 continue;
5984
5985 max_pixclk = max(max_pixclk,
5986 crtc_state->base.adjusted_mode.crtc_clock);
5987 }
5988
5989 return max_pixclk;
5990 }
5991
5992 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5993 {
5994 struct drm_device *dev = state->dev;
5995 struct drm_i915_private *dev_priv = dev->dev_private;
5996 int max_pixclk = intel_mode_max_pixclk(dev, state);
5997
5998 if (max_pixclk < 0)
5999 return max_pixclk;
6000
6001 to_intel_atomic_state(state)->cdclk =
6002 valleyview_calc_cdclk(dev_priv, max_pixclk);
6003
6004 return 0;
6005 }
6006
6007 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6008 {
6009 struct drm_device *dev = state->dev;
6010 struct drm_i915_private *dev_priv = dev->dev_private;
6011 int max_pixclk = intel_mode_max_pixclk(dev, state);
6012
6013 if (max_pixclk < 0)
6014 return max_pixclk;
6015
6016 to_intel_atomic_state(state)->cdclk =
6017 broxton_calc_cdclk(dev_priv, max_pixclk);
6018
6019 return 0;
6020 }
6021
6022 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6023 {
6024 unsigned int credits, default_credits;
6025
6026 if (IS_CHERRYVIEW(dev_priv))
6027 default_credits = PFI_CREDIT(12);
6028 else
6029 default_credits = PFI_CREDIT(8);
6030
6031 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6032 /* CHV suggested value is 31 or 63 */
6033 if (IS_CHERRYVIEW(dev_priv))
6034 credits = PFI_CREDIT_63;
6035 else
6036 credits = PFI_CREDIT(15);
6037 } else {
6038 credits = default_credits;
6039 }
6040
6041 /*
6042 * WA - write default credits before re-programming
6043 * FIXME: should we also set the resend bit here?
6044 */
6045 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6046 default_credits);
6047
6048 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6049 credits | PFI_CREDIT_RESEND);
6050
6051 /*
6052 * FIXME is this guaranteed to clear
6053 * immediately or should we poll for it?
6054 */
6055 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6056 }
6057
6058 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6059 {
6060 struct drm_device *dev = old_state->dev;
6061 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6062 struct drm_i915_private *dev_priv = dev->dev_private;
6063
6064 /*
6065 * FIXME: We can end up here with all power domains off, yet
6066 * with a CDCLK frequency other than the minimum. To account
6067 * for this take the PIPE-A power domain, which covers the HW
6068 * blocks needed for the following programming. This can be
6069 * removed once it's guaranteed that we get here either with
6070 * the minimum CDCLK set, or the required power domains
6071 * enabled.
6072 */
6073 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6074
6075 if (IS_CHERRYVIEW(dev))
6076 cherryview_set_cdclk(dev, req_cdclk);
6077 else
6078 valleyview_set_cdclk(dev, req_cdclk);
6079
6080 vlv_program_pfi_credits(dev_priv);
6081
6082 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6083 }
6084
6085 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6086 {
6087 struct drm_device *dev = crtc->dev;
6088 struct drm_i915_private *dev_priv = to_i915(dev);
6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 struct intel_encoder *encoder;
6091 int pipe = intel_crtc->pipe;
6092 bool is_dsi;
6093
6094 if (WARN_ON(intel_crtc->active))
6095 return;
6096
6097 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6098
6099 if (intel_crtc->config->has_dp_encoder)
6100 intel_dp_set_m_n(intel_crtc, M1_N1);
6101
6102 intel_set_pipe_timings(intel_crtc);
6103
6104 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106
6107 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6108 I915_WRITE(CHV_CANVAS(pipe), 0);
6109 }
6110
6111 i9xx_set_pipeconf(intel_crtc);
6112
6113 intel_crtc->active = true;
6114
6115 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6116
6117 for_each_encoder_on_crtc(dev, crtc, encoder)
6118 if (encoder->pre_pll_enable)
6119 encoder->pre_pll_enable(encoder);
6120
6121 if (!is_dsi) {
6122 if (IS_CHERRYVIEW(dev)) {
6123 chv_prepare_pll(intel_crtc, intel_crtc->config);
6124 chv_enable_pll(intel_crtc, intel_crtc->config);
6125 } else {
6126 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6127 vlv_enable_pll(intel_crtc, intel_crtc->config);
6128 }
6129 }
6130
6131 for_each_encoder_on_crtc(dev, crtc, encoder)
6132 if (encoder->pre_enable)
6133 encoder->pre_enable(encoder);
6134
6135 i9xx_pfit_enable(intel_crtc);
6136
6137 intel_crtc_load_lut(crtc);
6138
6139 intel_enable_pipe(intel_crtc);
6140
6141 assert_vblank_disabled(crtc);
6142 drm_crtc_vblank_on(crtc);
6143
6144 for_each_encoder_on_crtc(dev, crtc, encoder)
6145 encoder->enable(encoder);
6146 }
6147
6148 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6149 {
6150 struct drm_device *dev = crtc->base.dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152
6153 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6154 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6155 }
6156
6157 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6158 {
6159 struct drm_device *dev = crtc->dev;
6160 struct drm_i915_private *dev_priv = to_i915(dev);
6161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6162 struct intel_encoder *encoder;
6163 int pipe = intel_crtc->pipe;
6164
6165 if (WARN_ON(intel_crtc->active))
6166 return;
6167
6168 i9xx_set_pll_dividers(intel_crtc);
6169
6170 if (intel_crtc->config->has_dp_encoder)
6171 intel_dp_set_m_n(intel_crtc, M1_N1);
6172
6173 intel_set_pipe_timings(intel_crtc);
6174
6175 i9xx_set_pipeconf(intel_crtc);
6176
6177 intel_crtc->active = true;
6178
6179 if (!IS_GEN2(dev))
6180 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6181
6182 for_each_encoder_on_crtc(dev, crtc, encoder)
6183 if (encoder->pre_enable)
6184 encoder->pre_enable(encoder);
6185
6186 i9xx_enable_pll(intel_crtc);
6187
6188 i9xx_pfit_enable(intel_crtc);
6189
6190 intel_crtc_load_lut(crtc);
6191
6192 intel_update_watermarks(crtc);
6193 intel_enable_pipe(intel_crtc);
6194
6195 assert_vblank_disabled(crtc);
6196 drm_crtc_vblank_on(crtc);
6197
6198 for_each_encoder_on_crtc(dev, crtc, encoder)
6199 encoder->enable(encoder);
6200 }
6201
6202 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6203 {
6204 struct drm_device *dev = crtc->base.dev;
6205 struct drm_i915_private *dev_priv = dev->dev_private;
6206
6207 if (!crtc->config->gmch_pfit.control)
6208 return;
6209
6210 assert_pipe_disabled(dev_priv, crtc->pipe);
6211
6212 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6213 I915_READ(PFIT_CONTROL));
6214 I915_WRITE(PFIT_CONTROL, 0);
6215 }
6216
6217 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6218 {
6219 struct drm_device *dev = crtc->dev;
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6222 struct intel_encoder *encoder;
6223 int pipe = intel_crtc->pipe;
6224
6225 /*
6226 * On gen2 planes are double buffered but the pipe isn't, so we must
6227 * wait for planes to fully turn off before disabling the pipe.
6228 * We also need to wait on all gmch platforms because of the
6229 * self-refresh mode constraint explained above.
6230 */
6231 intel_wait_for_vblank(dev, pipe);
6232
6233 for_each_encoder_on_crtc(dev, crtc, encoder)
6234 encoder->disable(encoder);
6235
6236 drm_crtc_vblank_off(crtc);
6237 assert_vblank_disabled(crtc);
6238
6239 intel_disable_pipe(intel_crtc);
6240
6241 i9xx_pfit_disable(intel_crtc);
6242
6243 for_each_encoder_on_crtc(dev, crtc, encoder)
6244 if (encoder->post_disable)
6245 encoder->post_disable(encoder);
6246
6247 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6248 if (IS_CHERRYVIEW(dev))
6249 chv_disable_pll(dev_priv, pipe);
6250 else if (IS_VALLEYVIEW(dev))
6251 vlv_disable_pll(dev_priv, pipe);
6252 else
6253 i9xx_disable_pll(intel_crtc);
6254 }
6255
6256 for_each_encoder_on_crtc(dev, crtc, encoder)
6257 if (encoder->post_pll_disable)
6258 encoder->post_pll_disable(encoder);
6259
6260 if (!IS_GEN2(dev))
6261 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6262 }
6263
6264 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6265 {
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6268 enum intel_display_power_domain domain;
6269 unsigned long domains;
6270
6271 if (!intel_crtc->active)
6272 return;
6273
6274 if (to_intel_plane_state(crtc->primary->state)->visible) {
6275 intel_crtc_wait_for_pending_flips(crtc);
6276 intel_pre_disable_primary(crtc);
6277 }
6278
6279 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6280 dev_priv->display.crtc_disable(crtc);
6281 intel_crtc->active = false;
6282 intel_update_watermarks(crtc);
6283 intel_disable_shared_dpll(intel_crtc);
6284
6285 domains = intel_crtc->enabled_power_domains;
6286 for_each_power_domain(domain, domains)
6287 intel_display_power_put(dev_priv, domain);
6288 intel_crtc->enabled_power_domains = 0;
6289 }
6290
6291 /*
6292 * turn all crtc's off, but do not adjust state
6293 * This has to be paired with a call to intel_modeset_setup_hw_state.
6294 */
6295 int intel_display_suspend(struct drm_device *dev)
6296 {
6297 struct drm_mode_config *config = &dev->mode_config;
6298 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6299 struct drm_atomic_state *state;
6300 struct drm_crtc *crtc;
6301 unsigned crtc_mask = 0;
6302 int ret = 0;
6303
6304 if (WARN_ON(!ctx))
6305 return 0;
6306
6307 lockdep_assert_held(&ctx->ww_ctx);
6308 state = drm_atomic_state_alloc(dev);
6309 if (WARN_ON(!state))
6310 return -ENOMEM;
6311
6312 state->acquire_ctx = ctx;
6313 state->allow_modeset = true;
6314
6315 for_each_crtc(dev, crtc) {
6316 struct drm_crtc_state *crtc_state =
6317 drm_atomic_get_crtc_state(state, crtc);
6318
6319 ret = PTR_ERR_OR_ZERO(crtc_state);
6320 if (ret)
6321 goto free;
6322
6323 if (!crtc_state->active)
6324 continue;
6325
6326 crtc_state->active = false;
6327 crtc_mask |= 1 << drm_crtc_index(crtc);
6328 }
6329
6330 if (crtc_mask) {
6331 ret = drm_atomic_commit(state);
6332
6333 if (!ret) {
6334 for_each_crtc(dev, crtc)
6335 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6336 crtc->state->active = true;
6337
6338 return ret;
6339 }
6340 }
6341
6342 free:
6343 if (ret)
6344 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6345 drm_atomic_state_free(state);
6346 return ret;
6347 }
6348
6349 void intel_encoder_destroy(struct drm_encoder *encoder)
6350 {
6351 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6352
6353 drm_encoder_cleanup(encoder);
6354 kfree(intel_encoder);
6355 }
6356
6357 /* Cross check the actual hw state with our own modeset state tracking (and it's
6358 * internal consistency). */
6359 static void intel_connector_check_state(struct intel_connector *connector)
6360 {
6361 struct drm_crtc *crtc = connector->base.state->crtc;
6362
6363 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6364 connector->base.base.id,
6365 connector->base.name);
6366
6367 if (connector->get_hw_state(connector)) {
6368 struct intel_encoder *encoder = connector->encoder;
6369 struct drm_connector_state *conn_state = connector->base.state;
6370
6371 I915_STATE_WARN(!crtc,
6372 "connector enabled without attached crtc\n");
6373
6374 if (!crtc)
6375 return;
6376
6377 I915_STATE_WARN(!crtc->state->active,
6378 "connector is active, but attached crtc isn't\n");
6379
6380 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6381 return;
6382
6383 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6384 "atomic encoder doesn't match attached encoder\n");
6385
6386 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6387 "attached encoder crtc differs from connector crtc\n");
6388 } else {
6389 I915_STATE_WARN(crtc && crtc->state->active,
6390 "attached crtc is active, but connector isn't\n");
6391 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6392 "best encoder set without crtc!\n");
6393 }
6394 }
6395
6396 int intel_connector_init(struct intel_connector *connector)
6397 {
6398 struct drm_connector_state *connector_state;
6399
6400 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6401 if (!connector_state)
6402 return -ENOMEM;
6403
6404 connector->base.state = connector_state;
6405 return 0;
6406 }
6407
6408 struct intel_connector *intel_connector_alloc(void)
6409 {
6410 struct intel_connector *connector;
6411
6412 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6413 if (!connector)
6414 return NULL;
6415
6416 if (intel_connector_init(connector) < 0) {
6417 kfree(connector);
6418 return NULL;
6419 }
6420
6421 return connector;
6422 }
6423
6424 /* Simple connector->get_hw_state implementation for encoders that support only
6425 * one connector and no cloning and hence the encoder state determines the state
6426 * of the connector. */
6427 bool intel_connector_get_hw_state(struct intel_connector *connector)
6428 {
6429 enum pipe pipe = 0;
6430 struct intel_encoder *encoder = connector->encoder;
6431
6432 return encoder->get_hw_state(encoder, &pipe);
6433 }
6434
6435 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6436 {
6437 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6438 return crtc_state->fdi_lanes;
6439
6440 return 0;
6441 }
6442
6443 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6444 struct intel_crtc_state *pipe_config)
6445 {
6446 struct drm_atomic_state *state = pipe_config->base.state;
6447 struct intel_crtc *other_crtc;
6448 struct intel_crtc_state *other_crtc_state;
6449
6450 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6451 pipe_name(pipe), pipe_config->fdi_lanes);
6452 if (pipe_config->fdi_lanes > 4) {
6453 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6454 pipe_name(pipe), pipe_config->fdi_lanes);
6455 return -EINVAL;
6456 }
6457
6458 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6459 if (pipe_config->fdi_lanes > 2) {
6460 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6461 pipe_config->fdi_lanes);
6462 return -EINVAL;
6463 } else {
6464 return 0;
6465 }
6466 }
6467
6468 if (INTEL_INFO(dev)->num_pipes == 2)
6469 return 0;
6470
6471 /* Ivybridge 3 pipe is really complicated */
6472 switch (pipe) {
6473 case PIPE_A:
6474 return 0;
6475 case PIPE_B:
6476 if (pipe_config->fdi_lanes <= 2)
6477 return 0;
6478
6479 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6480 other_crtc_state =
6481 intel_atomic_get_crtc_state(state, other_crtc);
6482 if (IS_ERR(other_crtc_state))
6483 return PTR_ERR(other_crtc_state);
6484
6485 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6486 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6487 pipe_name(pipe), pipe_config->fdi_lanes);
6488 return -EINVAL;
6489 }
6490 return 0;
6491 case PIPE_C:
6492 if (pipe_config->fdi_lanes > 2) {
6493 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6494 pipe_name(pipe), pipe_config->fdi_lanes);
6495 return -EINVAL;
6496 }
6497
6498 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6499 other_crtc_state =
6500 intel_atomic_get_crtc_state(state, other_crtc);
6501 if (IS_ERR(other_crtc_state))
6502 return PTR_ERR(other_crtc_state);
6503
6504 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6505 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6506 return -EINVAL;
6507 }
6508 return 0;
6509 default:
6510 BUG();
6511 }
6512 }
6513
6514 #define RETRY 1
6515 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6516 struct intel_crtc_state *pipe_config)
6517 {
6518 struct drm_device *dev = intel_crtc->base.dev;
6519 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6520 int lane, link_bw, fdi_dotclock, ret;
6521 bool needs_recompute = false;
6522
6523 retry:
6524 /* FDI is a binary signal running at ~2.7GHz, encoding
6525 * each output octet as 10 bits. The actual frequency
6526 * is stored as a divider into a 100MHz clock, and the
6527 * mode pixel clock is stored in units of 1KHz.
6528 * Hence the bw of each lane in terms of the mode signal
6529 * is:
6530 */
6531 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6532
6533 fdi_dotclock = adjusted_mode->crtc_clock;
6534
6535 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6536 pipe_config->pipe_bpp);
6537
6538 pipe_config->fdi_lanes = lane;
6539
6540 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6541 link_bw, &pipe_config->fdi_m_n);
6542
6543 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6544 intel_crtc->pipe, pipe_config);
6545 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6546 pipe_config->pipe_bpp -= 2*3;
6547 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6548 pipe_config->pipe_bpp);
6549 needs_recompute = true;
6550 pipe_config->bw_constrained = true;
6551
6552 goto retry;
6553 }
6554
6555 if (needs_recompute)
6556 return RETRY;
6557
6558 return ret;
6559 }
6560
6561 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6562 struct intel_crtc_state *pipe_config)
6563 {
6564 if (pipe_config->pipe_bpp > 24)
6565 return false;
6566
6567 /* HSW can handle pixel rate up to cdclk? */
6568 if (IS_HASWELL(dev_priv->dev))
6569 return true;
6570
6571 /*
6572 * We compare against max which means we must take
6573 * the increased cdclk requirement into account when
6574 * calculating the new cdclk.
6575 *
6576 * Should measure whether using a lower cdclk w/o IPS
6577 */
6578 return ilk_pipe_pixel_rate(pipe_config) <=
6579 dev_priv->max_cdclk_freq * 95 / 100;
6580 }
6581
6582 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6583 struct intel_crtc_state *pipe_config)
6584 {
6585 struct drm_device *dev = crtc->base.dev;
6586 struct drm_i915_private *dev_priv = dev->dev_private;
6587
6588 pipe_config->ips_enabled = i915.enable_ips &&
6589 hsw_crtc_supports_ips(crtc) &&
6590 pipe_config_supports_ips(dev_priv, pipe_config);
6591 }
6592
6593 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6594 struct intel_crtc_state *pipe_config)
6595 {
6596 struct drm_device *dev = crtc->base.dev;
6597 struct drm_i915_private *dev_priv = dev->dev_private;
6598 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6599
6600 /* FIXME should check pixel clock limits on all platforms */
6601 if (INTEL_INFO(dev)->gen < 4) {
6602 int clock_limit = dev_priv->max_cdclk_freq;
6603
6604 /*
6605 * Enable pixel doubling when the dot clock
6606 * is > 90% of the (display) core speed.
6607 *
6608 * GDG double wide on either pipe,
6609 * otherwise pipe A only.
6610 */
6611 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6612 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6613 clock_limit *= 2;
6614 pipe_config->double_wide = true;
6615 }
6616
6617 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6618 return -EINVAL;
6619 }
6620
6621 /*
6622 * Pipe horizontal size must be even in:
6623 * - DVO ganged mode
6624 * - LVDS dual channel mode
6625 * - Double wide pipe
6626 */
6627 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6628 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6629 pipe_config->pipe_src_w &= ~1;
6630
6631 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6632 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6633 */
6634 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6635 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6636 return -EINVAL;
6637
6638 if (HAS_IPS(dev))
6639 hsw_compute_ips_config(crtc, pipe_config);
6640
6641 if (pipe_config->has_pch_encoder)
6642 return ironlake_fdi_compute_config(crtc, pipe_config);
6643
6644 return 0;
6645 }
6646
6647 static int skylake_get_display_clock_speed(struct drm_device *dev)
6648 {
6649 struct drm_i915_private *dev_priv = to_i915(dev);
6650 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6651 uint32_t cdctl = I915_READ(CDCLK_CTL);
6652 uint32_t linkrate;
6653
6654 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6655 return 24000; /* 24MHz is the cd freq with NSSC ref */
6656
6657 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6658 return 540000;
6659
6660 linkrate = (I915_READ(DPLL_CTRL1) &
6661 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6662
6663 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6664 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6665 /* vco 8640 */
6666 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6667 case CDCLK_FREQ_450_432:
6668 return 432000;
6669 case CDCLK_FREQ_337_308:
6670 return 308570;
6671 case CDCLK_FREQ_675_617:
6672 return 617140;
6673 default:
6674 WARN(1, "Unknown cd freq selection\n");
6675 }
6676 } else {
6677 /* vco 8100 */
6678 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6679 case CDCLK_FREQ_450_432:
6680 return 450000;
6681 case CDCLK_FREQ_337_308:
6682 return 337500;
6683 case CDCLK_FREQ_675_617:
6684 return 675000;
6685 default:
6686 WARN(1, "Unknown cd freq selection\n");
6687 }
6688 }
6689
6690 /* error case, do as if DPLL0 isn't enabled */
6691 return 24000;
6692 }
6693
6694 static int broxton_get_display_clock_speed(struct drm_device *dev)
6695 {
6696 struct drm_i915_private *dev_priv = to_i915(dev);
6697 uint32_t cdctl = I915_READ(CDCLK_CTL);
6698 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6699 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6700 int cdclk;
6701
6702 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6703 return 19200;
6704
6705 cdclk = 19200 * pll_ratio / 2;
6706
6707 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6708 case BXT_CDCLK_CD2X_DIV_SEL_1:
6709 return cdclk; /* 576MHz or 624MHz */
6710 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6711 return cdclk * 2 / 3; /* 384MHz */
6712 case BXT_CDCLK_CD2X_DIV_SEL_2:
6713 return cdclk / 2; /* 288MHz */
6714 case BXT_CDCLK_CD2X_DIV_SEL_4:
6715 return cdclk / 4; /* 144MHz */
6716 }
6717
6718 /* error case, do as if DE PLL isn't enabled */
6719 return 19200;
6720 }
6721
6722 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6723 {
6724 struct drm_i915_private *dev_priv = dev->dev_private;
6725 uint32_t lcpll = I915_READ(LCPLL_CTL);
6726 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6727
6728 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6729 return 800000;
6730 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6731 return 450000;
6732 else if (freq == LCPLL_CLK_FREQ_450)
6733 return 450000;
6734 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6735 return 540000;
6736 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6737 return 337500;
6738 else
6739 return 675000;
6740 }
6741
6742 static int haswell_get_display_clock_speed(struct drm_device *dev)
6743 {
6744 struct drm_i915_private *dev_priv = dev->dev_private;
6745 uint32_t lcpll = I915_READ(LCPLL_CTL);
6746 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6747
6748 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6749 return 800000;
6750 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6751 return 450000;
6752 else if (freq == LCPLL_CLK_FREQ_450)
6753 return 450000;
6754 else if (IS_HSW_ULT(dev))
6755 return 337500;
6756 else
6757 return 540000;
6758 }
6759
6760 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6761 {
6762 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6763 CCK_DISPLAY_CLOCK_CONTROL);
6764 }
6765
6766 static int ilk_get_display_clock_speed(struct drm_device *dev)
6767 {
6768 return 450000;
6769 }
6770
6771 static int i945_get_display_clock_speed(struct drm_device *dev)
6772 {
6773 return 400000;
6774 }
6775
6776 static int i915_get_display_clock_speed(struct drm_device *dev)
6777 {
6778 return 333333;
6779 }
6780
6781 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6782 {
6783 return 200000;
6784 }
6785
6786 static int pnv_get_display_clock_speed(struct drm_device *dev)
6787 {
6788 u16 gcfgc = 0;
6789
6790 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6791
6792 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6793 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6794 return 266667;
6795 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6796 return 333333;
6797 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6798 return 444444;
6799 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6800 return 200000;
6801 default:
6802 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6803 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6804 return 133333;
6805 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6806 return 166667;
6807 }
6808 }
6809
6810 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6811 {
6812 u16 gcfgc = 0;
6813
6814 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6815
6816 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6817 return 133333;
6818 else {
6819 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6820 case GC_DISPLAY_CLOCK_333_MHZ:
6821 return 333333;
6822 default:
6823 case GC_DISPLAY_CLOCK_190_200_MHZ:
6824 return 190000;
6825 }
6826 }
6827 }
6828
6829 static int i865_get_display_clock_speed(struct drm_device *dev)
6830 {
6831 return 266667;
6832 }
6833
6834 static int i85x_get_display_clock_speed(struct drm_device *dev)
6835 {
6836 u16 hpllcc = 0;
6837
6838 /*
6839 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6840 * encoding is different :(
6841 * FIXME is this the right way to detect 852GM/852GMV?
6842 */
6843 if (dev->pdev->revision == 0x1)
6844 return 133333;
6845
6846 pci_bus_read_config_word(dev->pdev->bus,
6847 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6848
6849 /* Assume that the hardware is in the high speed state. This
6850 * should be the default.
6851 */
6852 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6853 case GC_CLOCK_133_200:
6854 case GC_CLOCK_133_200_2:
6855 case GC_CLOCK_100_200:
6856 return 200000;
6857 case GC_CLOCK_166_250:
6858 return 250000;
6859 case GC_CLOCK_100_133:
6860 return 133333;
6861 case GC_CLOCK_133_266:
6862 case GC_CLOCK_133_266_2:
6863 case GC_CLOCK_166_266:
6864 return 266667;
6865 }
6866
6867 /* Shouldn't happen */
6868 return 0;
6869 }
6870
6871 static int i830_get_display_clock_speed(struct drm_device *dev)
6872 {
6873 return 133333;
6874 }
6875
6876 static unsigned int intel_hpll_vco(struct drm_device *dev)
6877 {
6878 struct drm_i915_private *dev_priv = dev->dev_private;
6879 static const unsigned int blb_vco[8] = {
6880 [0] = 3200000,
6881 [1] = 4000000,
6882 [2] = 5333333,
6883 [3] = 4800000,
6884 [4] = 6400000,
6885 };
6886 static const unsigned int pnv_vco[8] = {
6887 [0] = 3200000,
6888 [1] = 4000000,
6889 [2] = 5333333,
6890 [3] = 4800000,
6891 [4] = 2666667,
6892 };
6893 static const unsigned int cl_vco[8] = {
6894 [0] = 3200000,
6895 [1] = 4000000,
6896 [2] = 5333333,
6897 [3] = 6400000,
6898 [4] = 3333333,
6899 [5] = 3566667,
6900 [6] = 4266667,
6901 };
6902 static const unsigned int elk_vco[8] = {
6903 [0] = 3200000,
6904 [1] = 4000000,
6905 [2] = 5333333,
6906 [3] = 4800000,
6907 };
6908 static const unsigned int ctg_vco[8] = {
6909 [0] = 3200000,
6910 [1] = 4000000,
6911 [2] = 5333333,
6912 [3] = 6400000,
6913 [4] = 2666667,
6914 [5] = 4266667,
6915 };
6916 const unsigned int *vco_table;
6917 unsigned int vco;
6918 uint8_t tmp = 0;
6919
6920 /* FIXME other chipsets? */
6921 if (IS_GM45(dev))
6922 vco_table = ctg_vco;
6923 else if (IS_G4X(dev))
6924 vco_table = elk_vco;
6925 else if (IS_CRESTLINE(dev))
6926 vco_table = cl_vco;
6927 else if (IS_PINEVIEW(dev))
6928 vco_table = pnv_vco;
6929 else if (IS_G33(dev))
6930 vco_table = blb_vco;
6931 else
6932 return 0;
6933
6934 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6935
6936 vco = vco_table[tmp & 0x7];
6937 if (vco == 0)
6938 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6939 else
6940 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6941
6942 return vco;
6943 }
6944
6945 static int gm45_get_display_clock_speed(struct drm_device *dev)
6946 {
6947 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6948 uint16_t tmp = 0;
6949
6950 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6951
6952 cdclk_sel = (tmp >> 12) & 0x1;
6953
6954 switch (vco) {
6955 case 2666667:
6956 case 4000000:
6957 case 5333333:
6958 return cdclk_sel ? 333333 : 222222;
6959 case 3200000:
6960 return cdclk_sel ? 320000 : 228571;
6961 default:
6962 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6963 return 222222;
6964 }
6965 }
6966
6967 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6968 {
6969 static const uint8_t div_3200[] = { 16, 10, 8 };
6970 static const uint8_t div_4000[] = { 20, 12, 10 };
6971 static const uint8_t div_5333[] = { 24, 16, 14 };
6972 const uint8_t *div_table;
6973 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6974 uint16_t tmp = 0;
6975
6976 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6977
6978 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6979
6980 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6981 goto fail;
6982
6983 switch (vco) {
6984 case 3200000:
6985 div_table = div_3200;
6986 break;
6987 case 4000000:
6988 div_table = div_4000;
6989 break;
6990 case 5333333:
6991 div_table = div_5333;
6992 break;
6993 default:
6994 goto fail;
6995 }
6996
6997 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6998
6999 fail:
7000 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7001 return 200000;
7002 }
7003
7004 static int g33_get_display_clock_speed(struct drm_device *dev)
7005 {
7006 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7007 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7008 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7009 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7010 const uint8_t *div_table;
7011 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7012 uint16_t tmp = 0;
7013
7014 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7015
7016 cdclk_sel = (tmp >> 4) & 0x7;
7017
7018 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7019 goto fail;
7020
7021 switch (vco) {
7022 case 3200000:
7023 div_table = div_3200;
7024 break;
7025 case 4000000:
7026 div_table = div_4000;
7027 break;
7028 case 4800000:
7029 div_table = div_4800;
7030 break;
7031 case 5333333:
7032 div_table = div_5333;
7033 break;
7034 default:
7035 goto fail;
7036 }
7037
7038 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7039
7040 fail:
7041 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7042 return 190476;
7043 }
7044
7045 static void
7046 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7047 {
7048 while (*num > DATA_LINK_M_N_MASK ||
7049 *den > DATA_LINK_M_N_MASK) {
7050 *num >>= 1;
7051 *den >>= 1;
7052 }
7053 }
7054
7055 static void compute_m_n(unsigned int m, unsigned int n,
7056 uint32_t *ret_m, uint32_t *ret_n)
7057 {
7058 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7059 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7060 intel_reduce_m_n_ratio(ret_m, ret_n);
7061 }
7062
7063 void
7064 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7065 int pixel_clock, int link_clock,
7066 struct intel_link_m_n *m_n)
7067 {
7068 m_n->tu = 64;
7069
7070 compute_m_n(bits_per_pixel * pixel_clock,
7071 link_clock * nlanes * 8,
7072 &m_n->gmch_m, &m_n->gmch_n);
7073
7074 compute_m_n(pixel_clock, link_clock,
7075 &m_n->link_m, &m_n->link_n);
7076 }
7077
7078 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7079 {
7080 if (i915.panel_use_ssc >= 0)
7081 return i915.panel_use_ssc != 0;
7082 return dev_priv->vbt.lvds_use_ssc
7083 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7084 }
7085
7086 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7087 int num_connectors)
7088 {
7089 struct drm_device *dev = crtc_state->base.crtc->dev;
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091 int refclk;
7092
7093 WARN_ON(!crtc_state->base.state);
7094
7095 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7096 refclk = 100000;
7097 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7098 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7099 refclk = dev_priv->vbt.lvds_ssc_freq;
7100 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7101 } else if (!IS_GEN2(dev)) {
7102 refclk = 96000;
7103 } else {
7104 refclk = 48000;
7105 }
7106
7107 return refclk;
7108 }
7109
7110 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7111 {
7112 return (1 << dpll->n) << 16 | dpll->m2;
7113 }
7114
7115 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7116 {
7117 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7118 }
7119
7120 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7121 struct intel_crtc_state *crtc_state,
7122 intel_clock_t *reduced_clock)
7123 {
7124 struct drm_device *dev = crtc->base.dev;
7125 u32 fp, fp2 = 0;
7126
7127 if (IS_PINEVIEW(dev)) {
7128 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7129 if (reduced_clock)
7130 fp2 = pnv_dpll_compute_fp(reduced_clock);
7131 } else {
7132 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7133 if (reduced_clock)
7134 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7135 }
7136
7137 crtc_state->dpll_hw_state.fp0 = fp;
7138
7139 crtc->lowfreq_avail = false;
7140 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7141 reduced_clock) {
7142 crtc_state->dpll_hw_state.fp1 = fp2;
7143 crtc->lowfreq_avail = true;
7144 } else {
7145 crtc_state->dpll_hw_state.fp1 = fp;
7146 }
7147 }
7148
7149 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7150 pipe)
7151 {
7152 u32 reg_val;
7153
7154 /*
7155 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7156 * and set it to a reasonable value instead.
7157 */
7158 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7159 reg_val &= 0xffffff00;
7160 reg_val |= 0x00000030;
7161 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7162
7163 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7164 reg_val &= 0x8cffffff;
7165 reg_val = 0x8c000000;
7166 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7167
7168 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7169 reg_val &= 0xffffff00;
7170 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7171
7172 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7173 reg_val &= 0x00ffffff;
7174 reg_val |= 0xb0000000;
7175 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7176 }
7177
7178 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7179 struct intel_link_m_n *m_n)
7180 {
7181 struct drm_device *dev = crtc->base.dev;
7182 struct drm_i915_private *dev_priv = dev->dev_private;
7183 int pipe = crtc->pipe;
7184
7185 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7186 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7187 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7188 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7189 }
7190
7191 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7192 struct intel_link_m_n *m_n,
7193 struct intel_link_m_n *m2_n2)
7194 {
7195 struct drm_device *dev = crtc->base.dev;
7196 struct drm_i915_private *dev_priv = dev->dev_private;
7197 int pipe = crtc->pipe;
7198 enum transcoder transcoder = crtc->config->cpu_transcoder;
7199
7200 if (INTEL_INFO(dev)->gen >= 5) {
7201 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7202 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7203 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7204 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7205 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7206 * for gen < 8) and if DRRS is supported (to make sure the
7207 * registers are not unnecessarily accessed).
7208 */
7209 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7210 crtc->config->has_drrs) {
7211 I915_WRITE(PIPE_DATA_M2(transcoder),
7212 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7213 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7214 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7215 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7216 }
7217 } else {
7218 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7219 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7220 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7221 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7222 }
7223 }
7224
7225 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7226 {
7227 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7228
7229 if (m_n == M1_N1) {
7230 dp_m_n = &crtc->config->dp_m_n;
7231 dp_m2_n2 = &crtc->config->dp_m2_n2;
7232 } else if (m_n == M2_N2) {
7233
7234 /*
7235 * M2_N2 registers are not supported. Hence m2_n2 divider value
7236 * needs to be programmed into M1_N1.
7237 */
7238 dp_m_n = &crtc->config->dp_m2_n2;
7239 } else {
7240 DRM_ERROR("Unsupported divider value\n");
7241 return;
7242 }
7243
7244 if (crtc->config->has_pch_encoder)
7245 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7246 else
7247 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7248 }
7249
7250 static void vlv_compute_dpll(struct intel_crtc *crtc,
7251 struct intel_crtc_state *pipe_config)
7252 {
7253 u32 dpll, dpll_md;
7254
7255 /*
7256 * Enable DPIO clock input. We should never disable the reference
7257 * clock for pipe B, since VGA hotplug / manual detection depends
7258 * on it.
7259 */
7260 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7261 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7262 /* We should never disable this, set it here for state tracking */
7263 if (crtc->pipe == PIPE_B)
7264 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7265 dpll |= DPLL_VCO_ENABLE;
7266 pipe_config->dpll_hw_state.dpll = dpll;
7267
7268 dpll_md = (pipe_config->pixel_multiplier - 1)
7269 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7270 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7271 }
7272
7273 static void vlv_prepare_pll(struct intel_crtc *crtc,
7274 const struct intel_crtc_state *pipe_config)
7275 {
7276 struct drm_device *dev = crtc->base.dev;
7277 struct drm_i915_private *dev_priv = dev->dev_private;
7278 int pipe = crtc->pipe;
7279 u32 mdiv;
7280 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7281 u32 coreclk, reg_val;
7282
7283 mutex_lock(&dev_priv->sb_lock);
7284
7285 bestn = pipe_config->dpll.n;
7286 bestm1 = pipe_config->dpll.m1;
7287 bestm2 = pipe_config->dpll.m2;
7288 bestp1 = pipe_config->dpll.p1;
7289 bestp2 = pipe_config->dpll.p2;
7290
7291 /* See eDP HDMI DPIO driver vbios notes doc */
7292
7293 /* PLL B needs special handling */
7294 if (pipe == PIPE_B)
7295 vlv_pllb_recal_opamp(dev_priv, pipe);
7296
7297 /* Set up Tx target for periodic Rcomp update */
7298 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7299
7300 /* Disable target IRef on PLL */
7301 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7302 reg_val &= 0x00ffffff;
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7304
7305 /* Disable fast lock */
7306 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7307
7308 /* Set idtafcrecal before PLL is enabled */
7309 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7310 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7311 mdiv |= ((bestn << DPIO_N_SHIFT));
7312 mdiv |= (1 << DPIO_K_SHIFT);
7313
7314 /*
7315 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7316 * but we don't support that).
7317 * Note: don't use the DAC post divider as it seems unstable.
7318 */
7319 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7321
7322 mdiv |= DPIO_ENABLE_CALIBRATION;
7323 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7324
7325 /* Set HBR and RBR LPF coefficients */
7326 if (pipe_config->port_clock == 162000 ||
7327 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7328 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7330 0x009f0003);
7331 else
7332 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7333 0x00d0000f);
7334
7335 if (pipe_config->has_dp_encoder) {
7336 /* Use SSC source */
7337 if (pipe == PIPE_A)
7338 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7339 0x0df40000);
7340 else
7341 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7342 0x0df70000);
7343 } else { /* HDMI or VGA */
7344 /* Use bend source */
7345 if (pipe == PIPE_A)
7346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7347 0x0df70000);
7348 else
7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7350 0x0df40000);
7351 }
7352
7353 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7354 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7355 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7356 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7357 coreclk |= 0x01000000;
7358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7359
7360 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7361 mutex_unlock(&dev_priv->sb_lock);
7362 }
7363
7364 static void chv_compute_dpll(struct intel_crtc *crtc,
7365 struct intel_crtc_state *pipe_config)
7366 {
7367 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7368 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7369 DPLL_VCO_ENABLE;
7370 if (crtc->pipe != PIPE_A)
7371 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7372
7373 pipe_config->dpll_hw_state.dpll_md =
7374 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7375 }
7376
7377 static void chv_prepare_pll(struct intel_crtc *crtc,
7378 const struct intel_crtc_state *pipe_config)
7379 {
7380 struct drm_device *dev = crtc->base.dev;
7381 struct drm_i915_private *dev_priv = dev->dev_private;
7382 int pipe = crtc->pipe;
7383 int dpll_reg = DPLL(crtc->pipe);
7384 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7385 u32 loopfilter, tribuf_calcntr;
7386 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7387 u32 dpio_val;
7388 int vco;
7389
7390 bestn = pipe_config->dpll.n;
7391 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7392 bestm1 = pipe_config->dpll.m1;
7393 bestm2 = pipe_config->dpll.m2 >> 22;
7394 bestp1 = pipe_config->dpll.p1;
7395 bestp2 = pipe_config->dpll.p2;
7396 vco = pipe_config->dpll.vco;
7397 dpio_val = 0;
7398 loopfilter = 0;
7399
7400 /*
7401 * Enable Refclk and SSC
7402 */
7403 I915_WRITE(dpll_reg,
7404 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7405
7406 mutex_lock(&dev_priv->sb_lock);
7407
7408 /* p1 and p2 divider */
7409 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7410 5 << DPIO_CHV_S1_DIV_SHIFT |
7411 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7412 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7413 1 << DPIO_CHV_K_DIV_SHIFT);
7414
7415 /* Feedback post-divider - m2 */
7416 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7417
7418 /* Feedback refclk divider - n and m1 */
7419 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7420 DPIO_CHV_M1_DIV_BY_2 |
7421 1 << DPIO_CHV_N_DIV_SHIFT);
7422
7423 /* M2 fraction division */
7424 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7425
7426 /* M2 fraction division enable */
7427 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7428 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7429 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7430 if (bestm2_frac)
7431 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7432 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7433
7434 /* Program digital lock detect threshold */
7435 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7436 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7437 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7438 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7439 if (!bestm2_frac)
7440 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7441 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7442
7443 /* Loop filter */
7444 if (vco == 5400000) {
7445 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7446 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7447 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7448 tribuf_calcntr = 0x9;
7449 } else if (vco <= 6200000) {
7450 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7451 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7452 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7453 tribuf_calcntr = 0x9;
7454 } else if (vco <= 6480000) {
7455 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7456 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7457 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7458 tribuf_calcntr = 0x8;
7459 } else {
7460 /* Not supported. Apply the same limits as in the max case */
7461 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7462 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7463 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7464 tribuf_calcntr = 0;
7465 }
7466 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7467
7468 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7469 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7470 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7471 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7472
7473 /* AFC Recal */
7474 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7475 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7476 DPIO_AFC_RECAL);
7477
7478 mutex_unlock(&dev_priv->sb_lock);
7479 }
7480
7481 /**
7482 * vlv_force_pll_on - forcibly enable just the PLL
7483 * @dev_priv: i915 private structure
7484 * @pipe: pipe PLL to enable
7485 * @dpll: PLL configuration
7486 *
7487 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7488 * in cases where we need the PLL enabled even when @pipe is not going to
7489 * be enabled.
7490 */
7491 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7492 const struct dpll *dpll)
7493 {
7494 struct intel_crtc *crtc =
7495 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7496 struct intel_crtc_state pipe_config = {
7497 .base.crtc = &crtc->base,
7498 .pixel_multiplier = 1,
7499 .dpll = *dpll,
7500 };
7501
7502 if (IS_CHERRYVIEW(dev)) {
7503 chv_compute_dpll(crtc, &pipe_config);
7504 chv_prepare_pll(crtc, &pipe_config);
7505 chv_enable_pll(crtc, &pipe_config);
7506 } else {
7507 vlv_compute_dpll(crtc, &pipe_config);
7508 vlv_prepare_pll(crtc, &pipe_config);
7509 vlv_enable_pll(crtc, &pipe_config);
7510 }
7511 }
7512
7513 /**
7514 * vlv_force_pll_off - forcibly disable just the PLL
7515 * @dev_priv: i915 private structure
7516 * @pipe: pipe PLL to disable
7517 *
7518 * Disable the PLL for @pipe. To be used in cases where we need
7519 * the PLL enabled even when @pipe is not going to be enabled.
7520 */
7521 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7522 {
7523 if (IS_CHERRYVIEW(dev))
7524 chv_disable_pll(to_i915(dev), pipe);
7525 else
7526 vlv_disable_pll(to_i915(dev), pipe);
7527 }
7528
7529 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7530 struct intel_crtc_state *crtc_state,
7531 intel_clock_t *reduced_clock,
7532 int num_connectors)
7533 {
7534 struct drm_device *dev = crtc->base.dev;
7535 struct drm_i915_private *dev_priv = dev->dev_private;
7536 u32 dpll;
7537 bool is_sdvo;
7538 struct dpll *clock = &crtc_state->dpll;
7539
7540 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7541
7542 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7543 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7544
7545 dpll = DPLL_VGA_MODE_DIS;
7546
7547 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7548 dpll |= DPLLB_MODE_LVDS;
7549 else
7550 dpll |= DPLLB_MODE_DAC_SERIAL;
7551
7552 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7553 dpll |= (crtc_state->pixel_multiplier - 1)
7554 << SDVO_MULTIPLIER_SHIFT_HIRES;
7555 }
7556
7557 if (is_sdvo)
7558 dpll |= DPLL_SDVO_HIGH_SPEED;
7559
7560 if (crtc_state->has_dp_encoder)
7561 dpll |= DPLL_SDVO_HIGH_SPEED;
7562
7563 /* compute bitmask from p1 value */
7564 if (IS_PINEVIEW(dev))
7565 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7566 else {
7567 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7568 if (IS_G4X(dev) && reduced_clock)
7569 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7570 }
7571 switch (clock->p2) {
7572 case 5:
7573 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7574 break;
7575 case 7:
7576 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7577 break;
7578 case 10:
7579 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7580 break;
7581 case 14:
7582 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7583 break;
7584 }
7585 if (INTEL_INFO(dev)->gen >= 4)
7586 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7587
7588 if (crtc_state->sdvo_tv_clock)
7589 dpll |= PLL_REF_INPUT_TVCLKINBC;
7590 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7591 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7592 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7593 else
7594 dpll |= PLL_REF_INPUT_DREFCLK;
7595
7596 dpll |= DPLL_VCO_ENABLE;
7597 crtc_state->dpll_hw_state.dpll = dpll;
7598
7599 if (INTEL_INFO(dev)->gen >= 4) {
7600 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7601 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7602 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7603 }
7604 }
7605
7606 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7607 struct intel_crtc_state *crtc_state,
7608 intel_clock_t *reduced_clock,
7609 int num_connectors)
7610 {
7611 struct drm_device *dev = crtc->base.dev;
7612 struct drm_i915_private *dev_priv = dev->dev_private;
7613 u32 dpll;
7614 struct dpll *clock = &crtc_state->dpll;
7615
7616 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7617
7618 dpll = DPLL_VGA_MODE_DIS;
7619
7620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7621 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7622 } else {
7623 if (clock->p1 == 2)
7624 dpll |= PLL_P1_DIVIDE_BY_TWO;
7625 else
7626 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7627 if (clock->p2 == 4)
7628 dpll |= PLL_P2_DIVIDE_BY_4;
7629 }
7630
7631 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7632 dpll |= DPLL_DVO_2X_MODE;
7633
7634 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7635 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7636 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7637 else
7638 dpll |= PLL_REF_INPUT_DREFCLK;
7639
7640 dpll |= DPLL_VCO_ENABLE;
7641 crtc_state->dpll_hw_state.dpll = dpll;
7642 }
7643
7644 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7645 {
7646 struct drm_device *dev = intel_crtc->base.dev;
7647 struct drm_i915_private *dev_priv = dev->dev_private;
7648 enum pipe pipe = intel_crtc->pipe;
7649 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7650 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7651 uint32_t crtc_vtotal, crtc_vblank_end;
7652 int vsyncshift = 0;
7653
7654 /* We need to be careful not to changed the adjusted mode, for otherwise
7655 * the hw state checker will get angry at the mismatch. */
7656 crtc_vtotal = adjusted_mode->crtc_vtotal;
7657 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7658
7659 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7660 /* the chip adds 2 halflines automatically */
7661 crtc_vtotal -= 1;
7662 crtc_vblank_end -= 1;
7663
7664 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7665 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7666 else
7667 vsyncshift = adjusted_mode->crtc_hsync_start -
7668 adjusted_mode->crtc_htotal / 2;
7669 if (vsyncshift < 0)
7670 vsyncshift += adjusted_mode->crtc_htotal;
7671 }
7672
7673 if (INTEL_INFO(dev)->gen > 3)
7674 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7675
7676 I915_WRITE(HTOTAL(cpu_transcoder),
7677 (adjusted_mode->crtc_hdisplay - 1) |
7678 ((adjusted_mode->crtc_htotal - 1) << 16));
7679 I915_WRITE(HBLANK(cpu_transcoder),
7680 (adjusted_mode->crtc_hblank_start - 1) |
7681 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7682 I915_WRITE(HSYNC(cpu_transcoder),
7683 (adjusted_mode->crtc_hsync_start - 1) |
7684 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7685
7686 I915_WRITE(VTOTAL(cpu_transcoder),
7687 (adjusted_mode->crtc_vdisplay - 1) |
7688 ((crtc_vtotal - 1) << 16));
7689 I915_WRITE(VBLANK(cpu_transcoder),
7690 (adjusted_mode->crtc_vblank_start - 1) |
7691 ((crtc_vblank_end - 1) << 16));
7692 I915_WRITE(VSYNC(cpu_transcoder),
7693 (adjusted_mode->crtc_vsync_start - 1) |
7694 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7695
7696 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7697 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7698 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7699 * bits. */
7700 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7701 (pipe == PIPE_B || pipe == PIPE_C))
7702 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7703
7704 /* pipesrc controls the size that is scaled from, which should
7705 * always be the user's requested size.
7706 */
7707 I915_WRITE(PIPESRC(pipe),
7708 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7709 (intel_crtc->config->pipe_src_h - 1));
7710 }
7711
7712 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7713 struct intel_crtc_state *pipe_config)
7714 {
7715 struct drm_device *dev = crtc->base.dev;
7716 struct drm_i915_private *dev_priv = dev->dev_private;
7717 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7718 uint32_t tmp;
7719
7720 tmp = I915_READ(HTOTAL(cpu_transcoder));
7721 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7722 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7723 tmp = I915_READ(HBLANK(cpu_transcoder));
7724 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7725 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7726 tmp = I915_READ(HSYNC(cpu_transcoder));
7727 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7728 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7729
7730 tmp = I915_READ(VTOTAL(cpu_transcoder));
7731 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7732 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7733 tmp = I915_READ(VBLANK(cpu_transcoder));
7734 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7735 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7736 tmp = I915_READ(VSYNC(cpu_transcoder));
7737 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7738 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7739
7740 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7741 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7742 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7743 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7744 }
7745
7746 tmp = I915_READ(PIPESRC(crtc->pipe));
7747 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7748 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7749
7750 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7751 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7752 }
7753
7754 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7755 struct intel_crtc_state *pipe_config)
7756 {
7757 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7758 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7759 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7760 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7761
7762 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7763 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7764 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7765 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7766
7767 mode->flags = pipe_config->base.adjusted_mode.flags;
7768 mode->type = DRM_MODE_TYPE_DRIVER;
7769
7770 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7771 mode->flags |= pipe_config->base.adjusted_mode.flags;
7772
7773 mode->hsync = drm_mode_hsync(mode);
7774 mode->vrefresh = drm_mode_vrefresh(mode);
7775 drm_mode_set_name(mode);
7776 }
7777
7778 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7779 {
7780 struct drm_device *dev = intel_crtc->base.dev;
7781 struct drm_i915_private *dev_priv = dev->dev_private;
7782 uint32_t pipeconf;
7783
7784 pipeconf = 0;
7785
7786 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7787 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7788 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7789
7790 if (intel_crtc->config->double_wide)
7791 pipeconf |= PIPECONF_DOUBLE_WIDE;
7792
7793 /* only g4x and later have fancy bpc/dither controls */
7794 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7795 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7796 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7797 pipeconf |= PIPECONF_DITHER_EN |
7798 PIPECONF_DITHER_TYPE_SP;
7799
7800 switch (intel_crtc->config->pipe_bpp) {
7801 case 18:
7802 pipeconf |= PIPECONF_6BPC;
7803 break;
7804 case 24:
7805 pipeconf |= PIPECONF_8BPC;
7806 break;
7807 case 30:
7808 pipeconf |= PIPECONF_10BPC;
7809 break;
7810 default:
7811 /* Case prevented by intel_choose_pipe_bpp_dither. */
7812 BUG();
7813 }
7814 }
7815
7816 if (HAS_PIPE_CXSR(dev)) {
7817 if (intel_crtc->lowfreq_avail) {
7818 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7819 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7820 } else {
7821 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7822 }
7823 }
7824
7825 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7826 if (INTEL_INFO(dev)->gen < 4 ||
7827 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7828 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7829 else
7830 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7831 } else
7832 pipeconf |= PIPECONF_PROGRESSIVE;
7833
7834 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7835 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7836
7837 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7838 POSTING_READ(PIPECONF(intel_crtc->pipe));
7839 }
7840
7841 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7842 struct intel_crtc_state *crtc_state)
7843 {
7844 struct drm_device *dev = crtc->base.dev;
7845 struct drm_i915_private *dev_priv = dev->dev_private;
7846 int refclk, num_connectors = 0;
7847 intel_clock_t clock;
7848 bool ok;
7849 bool is_dsi = false;
7850 struct intel_encoder *encoder;
7851 const intel_limit_t *limit;
7852 struct drm_atomic_state *state = crtc_state->base.state;
7853 struct drm_connector *connector;
7854 struct drm_connector_state *connector_state;
7855 int i;
7856
7857 memset(&crtc_state->dpll_hw_state, 0,
7858 sizeof(crtc_state->dpll_hw_state));
7859
7860 for_each_connector_in_state(state, connector, connector_state, i) {
7861 if (connector_state->crtc != &crtc->base)
7862 continue;
7863
7864 encoder = to_intel_encoder(connector_state->best_encoder);
7865
7866 switch (encoder->type) {
7867 case INTEL_OUTPUT_DSI:
7868 is_dsi = true;
7869 break;
7870 default:
7871 break;
7872 }
7873
7874 num_connectors++;
7875 }
7876
7877 if (is_dsi)
7878 return 0;
7879
7880 if (!crtc_state->clock_set) {
7881 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7882
7883 /*
7884 * Returns a set of divisors for the desired target clock with
7885 * the given refclk, or FALSE. The returned values represent
7886 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7887 * 2) / p1 / p2.
7888 */
7889 limit = intel_limit(crtc_state, refclk);
7890 ok = dev_priv->display.find_dpll(limit, crtc_state,
7891 crtc_state->port_clock,
7892 refclk, NULL, &clock);
7893 if (!ok) {
7894 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7895 return -EINVAL;
7896 }
7897
7898 /* Compat-code for transition, will disappear. */
7899 crtc_state->dpll.n = clock.n;
7900 crtc_state->dpll.m1 = clock.m1;
7901 crtc_state->dpll.m2 = clock.m2;
7902 crtc_state->dpll.p1 = clock.p1;
7903 crtc_state->dpll.p2 = clock.p2;
7904 }
7905
7906 if (IS_GEN2(dev)) {
7907 i8xx_compute_dpll(crtc, crtc_state, NULL,
7908 num_connectors);
7909 } else if (IS_CHERRYVIEW(dev)) {
7910 chv_compute_dpll(crtc, crtc_state);
7911 } else if (IS_VALLEYVIEW(dev)) {
7912 vlv_compute_dpll(crtc, crtc_state);
7913 } else {
7914 i9xx_compute_dpll(crtc, crtc_state, NULL,
7915 num_connectors);
7916 }
7917
7918 return 0;
7919 }
7920
7921 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7922 struct intel_crtc_state *pipe_config)
7923 {
7924 struct drm_device *dev = crtc->base.dev;
7925 struct drm_i915_private *dev_priv = dev->dev_private;
7926 uint32_t tmp;
7927
7928 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7929 return;
7930
7931 tmp = I915_READ(PFIT_CONTROL);
7932 if (!(tmp & PFIT_ENABLE))
7933 return;
7934
7935 /* Check whether the pfit is attached to our pipe. */
7936 if (INTEL_INFO(dev)->gen < 4) {
7937 if (crtc->pipe != PIPE_B)
7938 return;
7939 } else {
7940 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7941 return;
7942 }
7943
7944 pipe_config->gmch_pfit.control = tmp;
7945 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7946 if (INTEL_INFO(dev)->gen < 5)
7947 pipe_config->gmch_pfit.lvds_border_bits =
7948 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7949 }
7950
7951 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7952 struct intel_crtc_state *pipe_config)
7953 {
7954 struct drm_device *dev = crtc->base.dev;
7955 struct drm_i915_private *dev_priv = dev->dev_private;
7956 int pipe = pipe_config->cpu_transcoder;
7957 intel_clock_t clock;
7958 u32 mdiv;
7959 int refclk = 100000;
7960
7961 /* In case of MIPI DPLL will not even be used */
7962 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7963 return;
7964
7965 mutex_lock(&dev_priv->sb_lock);
7966 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7967 mutex_unlock(&dev_priv->sb_lock);
7968
7969 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7970 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7971 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7972 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7973 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7974
7975 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7976 }
7977
7978 static void
7979 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7980 struct intel_initial_plane_config *plane_config)
7981 {
7982 struct drm_device *dev = crtc->base.dev;
7983 struct drm_i915_private *dev_priv = dev->dev_private;
7984 u32 val, base, offset;
7985 int pipe = crtc->pipe, plane = crtc->plane;
7986 int fourcc, pixel_format;
7987 unsigned int aligned_height;
7988 struct drm_framebuffer *fb;
7989 struct intel_framebuffer *intel_fb;
7990
7991 val = I915_READ(DSPCNTR(plane));
7992 if (!(val & DISPLAY_PLANE_ENABLE))
7993 return;
7994
7995 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7996 if (!intel_fb) {
7997 DRM_DEBUG_KMS("failed to alloc fb\n");
7998 return;
7999 }
8000
8001 fb = &intel_fb->base;
8002
8003 if (INTEL_INFO(dev)->gen >= 4) {
8004 if (val & DISPPLANE_TILED) {
8005 plane_config->tiling = I915_TILING_X;
8006 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8007 }
8008 }
8009
8010 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8011 fourcc = i9xx_format_to_fourcc(pixel_format);
8012 fb->pixel_format = fourcc;
8013 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8014
8015 if (INTEL_INFO(dev)->gen >= 4) {
8016 if (plane_config->tiling)
8017 offset = I915_READ(DSPTILEOFF(plane));
8018 else
8019 offset = I915_READ(DSPLINOFF(plane));
8020 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8021 } else {
8022 base = I915_READ(DSPADDR(plane));
8023 }
8024 plane_config->base = base;
8025
8026 val = I915_READ(PIPESRC(pipe));
8027 fb->width = ((val >> 16) & 0xfff) + 1;
8028 fb->height = ((val >> 0) & 0xfff) + 1;
8029
8030 val = I915_READ(DSPSTRIDE(pipe));
8031 fb->pitches[0] = val & 0xffffffc0;
8032
8033 aligned_height = intel_fb_align_height(dev, fb->height,
8034 fb->pixel_format,
8035 fb->modifier[0]);
8036
8037 plane_config->size = fb->pitches[0] * aligned_height;
8038
8039 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8040 pipe_name(pipe), plane, fb->width, fb->height,
8041 fb->bits_per_pixel, base, fb->pitches[0],
8042 plane_config->size);
8043
8044 plane_config->fb = intel_fb;
8045 }
8046
8047 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8048 struct intel_crtc_state *pipe_config)
8049 {
8050 struct drm_device *dev = crtc->base.dev;
8051 struct drm_i915_private *dev_priv = dev->dev_private;
8052 int pipe = pipe_config->cpu_transcoder;
8053 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8054 intel_clock_t clock;
8055 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8056 int refclk = 100000;
8057
8058 mutex_lock(&dev_priv->sb_lock);
8059 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8060 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8061 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8062 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8063 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8064 mutex_unlock(&dev_priv->sb_lock);
8065
8066 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8067 clock.m2 = (pll_dw0 & 0xff) << 22;
8068 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8069 clock.m2 |= pll_dw2 & 0x3fffff;
8070 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8071 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8072 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8073
8074 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8075 }
8076
8077 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8078 struct intel_crtc_state *pipe_config)
8079 {
8080 struct drm_device *dev = crtc->base.dev;
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082 uint32_t tmp;
8083
8084 if (!intel_display_power_is_enabled(dev_priv,
8085 POWER_DOMAIN_PIPE(crtc->pipe)))
8086 return false;
8087
8088 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8089 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8090
8091 tmp = I915_READ(PIPECONF(crtc->pipe));
8092 if (!(tmp & PIPECONF_ENABLE))
8093 return false;
8094
8095 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8096 switch (tmp & PIPECONF_BPC_MASK) {
8097 case PIPECONF_6BPC:
8098 pipe_config->pipe_bpp = 18;
8099 break;
8100 case PIPECONF_8BPC:
8101 pipe_config->pipe_bpp = 24;
8102 break;
8103 case PIPECONF_10BPC:
8104 pipe_config->pipe_bpp = 30;
8105 break;
8106 default:
8107 break;
8108 }
8109 }
8110
8111 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8112 pipe_config->limited_color_range = true;
8113
8114 if (INTEL_INFO(dev)->gen < 4)
8115 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8116
8117 intel_get_pipe_timings(crtc, pipe_config);
8118
8119 i9xx_get_pfit_config(crtc, pipe_config);
8120
8121 if (INTEL_INFO(dev)->gen >= 4) {
8122 tmp = I915_READ(DPLL_MD(crtc->pipe));
8123 pipe_config->pixel_multiplier =
8124 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8125 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8126 pipe_config->dpll_hw_state.dpll_md = tmp;
8127 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8128 tmp = I915_READ(DPLL(crtc->pipe));
8129 pipe_config->pixel_multiplier =
8130 ((tmp & SDVO_MULTIPLIER_MASK)
8131 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8132 } else {
8133 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8134 * port and will be fixed up in the encoder->get_config
8135 * function. */
8136 pipe_config->pixel_multiplier = 1;
8137 }
8138 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8139 if (!IS_VALLEYVIEW(dev)) {
8140 /*
8141 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8142 * on 830. Filter it out here so that we don't
8143 * report errors due to that.
8144 */
8145 if (IS_I830(dev))
8146 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8147
8148 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8149 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8150 } else {
8151 /* Mask out read-only status bits. */
8152 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8153 DPLL_PORTC_READY_MASK |
8154 DPLL_PORTB_READY_MASK);
8155 }
8156
8157 if (IS_CHERRYVIEW(dev))
8158 chv_crtc_clock_get(crtc, pipe_config);
8159 else if (IS_VALLEYVIEW(dev))
8160 vlv_crtc_clock_get(crtc, pipe_config);
8161 else
8162 i9xx_crtc_clock_get(crtc, pipe_config);
8163
8164 /*
8165 * Normally the dotclock is filled in by the encoder .get_config()
8166 * but in case the pipe is enabled w/o any ports we need a sane
8167 * default.
8168 */
8169 pipe_config->base.adjusted_mode.crtc_clock =
8170 pipe_config->port_clock / pipe_config->pixel_multiplier;
8171
8172 return true;
8173 }
8174
8175 static void ironlake_init_pch_refclk(struct drm_device *dev)
8176 {
8177 struct drm_i915_private *dev_priv = dev->dev_private;
8178 struct intel_encoder *encoder;
8179 u32 val, final;
8180 bool has_lvds = false;
8181 bool has_cpu_edp = false;
8182 bool has_panel = false;
8183 bool has_ck505 = false;
8184 bool can_ssc = false;
8185
8186 /* We need to take the global config into account */
8187 for_each_intel_encoder(dev, encoder) {
8188 switch (encoder->type) {
8189 case INTEL_OUTPUT_LVDS:
8190 has_panel = true;
8191 has_lvds = true;
8192 break;
8193 case INTEL_OUTPUT_EDP:
8194 has_panel = true;
8195 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8196 has_cpu_edp = true;
8197 break;
8198 default:
8199 break;
8200 }
8201 }
8202
8203 if (HAS_PCH_IBX(dev)) {
8204 has_ck505 = dev_priv->vbt.display_clock_mode;
8205 can_ssc = has_ck505;
8206 } else {
8207 has_ck505 = false;
8208 can_ssc = true;
8209 }
8210
8211 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8212 has_panel, has_lvds, has_ck505);
8213
8214 /* Ironlake: try to setup display ref clock before DPLL
8215 * enabling. This is only under driver's control after
8216 * PCH B stepping, previous chipset stepping should be
8217 * ignoring this setting.
8218 */
8219 val = I915_READ(PCH_DREF_CONTROL);
8220
8221 /* As we must carefully and slowly disable/enable each source in turn,
8222 * compute the final state we want first and check if we need to
8223 * make any changes at all.
8224 */
8225 final = val;
8226 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8227 if (has_ck505)
8228 final |= DREF_NONSPREAD_CK505_ENABLE;
8229 else
8230 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8231
8232 final &= ~DREF_SSC_SOURCE_MASK;
8233 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8234 final &= ~DREF_SSC1_ENABLE;
8235
8236 if (has_panel) {
8237 final |= DREF_SSC_SOURCE_ENABLE;
8238
8239 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8240 final |= DREF_SSC1_ENABLE;
8241
8242 if (has_cpu_edp) {
8243 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8244 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8245 else
8246 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8247 } else
8248 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8249 } else {
8250 final |= DREF_SSC_SOURCE_DISABLE;
8251 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8252 }
8253
8254 if (final == val)
8255 return;
8256
8257 /* Always enable nonspread source */
8258 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8259
8260 if (has_ck505)
8261 val |= DREF_NONSPREAD_CK505_ENABLE;
8262 else
8263 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8264
8265 if (has_panel) {
8266 val &= ~DREF_SSC_SOURCE_MASK;
8267 val |= DREF_SSC_SOURCE_ENABLE;
8268
8269 /* SSC must be turned on before enabling the CPU output */
8270 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8271 DRM_DEBUG_KMS("Using SSC on panel\n");
8272 val |= DREF_SSC1_ENABLE;
8273 } else
8274 val &= ~DREF_SSC1_ENABLE;
8275
8276 /* Get SSC going before enabling the outputs */
8277 I915_WRITE(PCH_DREF_CONTROL, val);
8278 POSTING_READ(PCH_DREF_CONTROL);
8279 udelay(200);
8280
8281 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8282
8283 /* Enable CPU source on CPU attached eDP */
8284 if (has_cpu_edp) {
8285 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8286 DRM_DEBUG_KMS("Using SSC on eDP\n");
8287 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8288 } else
8289 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8290 } else
8291 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8292
8293 I915_WRITE(PCH_DREF_CONTROL, val);
8294 POSTING_READ(PCH_DREF_CONTROL);
8295 udelay(200);
8296 } else {
8297 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8298
8299 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8300
8301 /* Turn off CPU output */
8302 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8303
8304 I915_WRITE(PCH_DREF_CONTROL, val);
8305 POSTING_READ(PCH_DREF_CONTROL);
8306 udelay(200);
8307
8308 /* Turn off the SSC source */
8309 val &= ~DREF_SSC_SOURCE_MASK;
8310 val |= DREF_SSC_SOURCE_DISABLE;
8311
8312 /* Turn off SSC1 */
8313 val &= ~DREF_SSC1_ENABLE;
8314
8315 I915_WRITE(PCH_DREF_CONTROL, val);
8316 POSTING_READ(PCH_DREF_CONTROL);
8317 udelay(200);
8318 }
8319
8320 BUG_ON(val != final);
8321 }
8322
8323 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8324 {
8325 uint32_t tmp;
8326
8327 tmp = I915_READ(SOUTH_CHICKEN2);
8328 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8329 I915_WRITE(SOUTH_CHICKEN2, tmp);
8330
8331 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8332 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8333 DRM_ERROR("FDI mPHY reset assert timeout\n");
8334
8335 tmp = I915_READ(SOUTH_CHICKEN2);
8336 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8337 I915_WRITE(SOUTH_CHICKEN2, tmp);
8338
8339 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8340 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8341 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8342 }
8343
8344 /* WaMPhyProgramming:hsw */
8345 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8346 {
8347 uint32_t tmp;
8348
8349 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8350 tmp &= ~(0xFF << 24);
8351 tmp |= (0x12 << 24);
8352 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8353
8354 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8355 tmp |= (1 << 11);
8356 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8357
8358 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8359 tmp |= (1 << 11);
8360 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8361
8362 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8363 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8364 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8365
8366 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8367 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8368 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8369
8370 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8371 tmp &= ~(7 << 13);
8372 tmp |= (5 << 13);
8373 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8374
8375 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8376 tmp &= ~(7 << 13);
8377 tmp |= (5 << 13);
8378 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8379
8380 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8381 tmp &= ~0xFF;
8382 tmp |= 0x1C;
8383 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8384
8385 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8386 tmp &= ~0xFF;
8387 tmp |= 0x1C;
8388 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8389
8390 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8391 tmp &= ~(0xFF << 16);
8392 tmp |= (0x1C << 16);
8393 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8394
8395 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8396 tmp &= ~(0xFF << 16);
8397 tmp |= (0x1C << 16);
8398 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8399
8400 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8401 tmp |= (1 << 27);
8402 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8403
8404 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8405 tmp |= (1 << 27);
8406 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8407
8408 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8409 tmp &= ~(0xF << 28);
8410 tmp |= (4 << 28);
8411 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8412
8413 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8414 tmp &= ~(0xF << 28);
8415 tmp |= (4 << 28);
8416 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8417 }
8418
8419 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8420 * Programming" based on the parameters passed:
8421 * - Sequence to enable CLKOUT_DP
8422 * - Sequence to enable CLKOUT_DP without spread
8423 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8424 */
8425 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8426 bool with_fdi)
8427 {
8428 struct drm_i915_private *dev_priv = dev->dev_private;
8429 uint32_t reg, tmp;
8430
8431 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8432 with_spread = true;
8433 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8434 with_fdi = false;
8435
8436 mutex_lock(&dev_priv->sb_lock);
8437
8438 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8439 tmp &= ~SBI_SSCCTL_DISABLE;
8440 tmp |= SBI_SSCCTL_PATHALT;
8441 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8442
8443 udelay(24);
8444
8445 if (with_spread) {
8446 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8447 tmp &= ~SBI_SSCCTL_PATHALT;
8448 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8449
8450 if (with_fdi) {
8451 lpt_reset_fdi_mphy(dev_priv);
8452 lpt_program_fdi_mphy(dev_priv);
8453 }
8454 }
8455
8456 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8457 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8458 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8459 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8460
8461 mutex_unlock(&dev_priv->sb_lock);
8462 }
8463
8464 /* Sequence to disable CLKOUT_DP */
8465 static void lpt_disable_clkout_dp(struct drm_device *dev)
8466 {
8467 struct drm_i915_private *dev_priv = dev->dev_private;
8468 uint32_t reg, tmp;
8469
8470 mutex_lock(&dev_priv->sb_lock);
8471
8472 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8473 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8474 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8475 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8476
8477 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8478 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8479 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8480 tmp |= SBI_SSCCTL_PATHALT;
8481 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8482 udelay(32);
8483 }
8484 tmp |= SBI_SSCCTL_DISABLE;
8485 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8486 }
8487
8488 mutex_unlock(&dev_priv->sb_lock);
8489 }
8490
8491 static void lpt_init_pch_refclk(struct drm_device *dev)
8492 {
8493 struct intel_encoder *encoder;
8494 bool has_vga = false;
8495
8496 for_each_intel_encoder(dev, encoder) {
8497 switch (encoder->type) {
8498 case INTEL_OUTPUT_ANALOG:
8499 has_vga = true;
8500 break;
8501 default:
8502 break;
8503 }
8504 }
8505
8506 if (has_vga)
8507 lpt_enable_clkout_dp(dev, true, true);
8508 else
8509 lpt_disable_clkout_dp(dev);
8510 }
8511
8512 /*
8513 * Initialize reference clocks when the driver loads
8514 */
8515 void intel_init_pch_refclk(struct drm_device *dev)
8516 {
8517 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8518 ironlake_init_pch_refclk(dev);
8519 else if (HAS_PCH_LPT(dev))
8520 lpt_init_pch_refclk(dev);
8521 }
8522
8523 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8524 {
8525 struct drm_device *dev = crtc_state->base.crtc->dev;
8526 struct drm_i915_private *dev_priv = dev->dev_private;
8527 struct drm_atomic_state *state = crtc_state->base.state;
8528 struct drm_connector *connector;
8529 struct drm_connector_state *connector_state;
8530 struct intel_encoder *encoder;
8531 int num_connectors = 0, i;
8532 bool is_lvds = false;
8533
8534 for_each_connector_in_state(state, connector, connector_state, i) {
8535 if (connector_state->crtc != crtc_state->base.crtc)
8536 continue;
8537
8538 encoder = to_intel_encoder(connector_state->best_encoder);
8539
8540 switch (encoder->type) {
8541 case INTEL_OUTPUT_LVDS:
8542 is_lvds = true;
8543 break;
8544 default:
8545 break;
8546 }
8547 num_connectors++;
8548 }
8549
8550 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8551 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8552 dev_priv->vbt.lvds_ssc_freq);
8553 return dev_priv->vbt.lvds_ssc_freq;
8554 }
8555
8556 return 120000;
8557 }
8558
8559 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8560 {
8561 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8563 int pipe = intel_crtc->pipe;
8564 uint32_t val;
8565
8566 val = 0;
8567
8568 switch (intel_crtc->config->pipe_bpp) {
8569 case 18:
8570 val |= PIPECONF_6BPC;
8571 break;
8572 case 24:
8573 val |= PIPECONF_8BPC;
8574 break;
8575 case 30:
8576 val |= PIPECONF_10BPC;
8577 break;
8578 case 36:
8579 val |= PIPECONF_12BPC;
8580 break;
8581 default:
8582 /* Case prevented by intel_choose_pipe_bpp_dither. */
8583 BUG();
8584 }
8585
8586 if (intel_crtc->config->dither)
8587 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8588
8589 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8590 val |= PIPECONF_INTERLACED_ILK;
8591 else
8592 val |= PIPECONF_PROGRESSIVE;
8593
8594 if (intel_crtc->config->limited_color_range)
8595 val |= PIPECONF_COLOR_RANGE_SELECT;
8596
8597 I915_WRITE(PIPECONF(pipe), val);
8598 POSTING_READ(PIPECONF(pipe));
8599 }
8600
8601 /*
8602 * Set up the pipe CSC unit.
8603 *
8604 * Currently only full range RGB to limited range RGB conversion
8605 * is supported, but eventually this should handle various
8606 * RGB<->YCbCr scenarios as well.
8607 */
8608 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8609 {
8610 struct drm_device *dev = crtc->dev;
8611 struct drm_i915_private *dev_priv = dev->dev_private;
8612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8613 int pipe = intel_crtc->pipe;
8614 uint16_t coeff = 0x7800; /* 1.0 */
8615
8616 /*
8617 * TODO: Check what kind of values actually come out of the pipe
8618 * with these coeff/postoff values and adjust to get the best
8619 * accuracy. Perhaps we even need to take the bpc value into
8620 * consideration.
8621 */
8622
8623 if (intel_crtc->config->limited_color_range)
8624 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8625
8626 /*
8627 * GY/GU and RY/RU should be the other way around according
8628 * to BSpec, but reality doesn't agree. Just set them up in
8629 * a way that results in the correct picture.
8630 */
8631 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8632 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8633
8634 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8635 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8636
8637 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8638 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8639
8640 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8641 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8642 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8643
8644 if (INTEL_INFO(dev)->gen > 6) {
8645 uint16_t postoff = 0;
8646
8647 if (intel_crtc->config->limited_color_range)
8648 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8649
8650 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8651 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8652 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8653
8654 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8655 } else {
8656 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8657
8658 if (intel_crtc->config->limited_color_range)
8659 mode |= CSC_BLACK_SCREEN_OFFSET;
8660
8661 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8662 }
8663 }
8664
8665 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8666 {
8667 struct drm_device *dev = crtc->dev;
8668 struct drm_i915_private *dev_priv = dev->dev_private;
8669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8670 enum pipe pipe = intel_crtc->pipe;
8671 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8672 uint32_t val;
8673
8674 val = 0;
8675
8676 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8677 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8678
8679 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8680 val |= PIPECONF_INTERLACED_ILK;
8681 else
8682 val |= PIPECONF_PROGRESSIVE;
8683
8684 I915_WRITE(PIPECONF(cpu_transcoder), val);
8685 POSTING_READ(PIPECONF(cpu_transcoder));
8686
8687 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8688 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8689
8690 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8691 val = 0;
8692
8693 switch (intel_crtc->config->pipe_bpp) {
8694 case 18:
8695 val |= PIPEMISC_DITHER_6_BPC;
8696 break;
8697 case 24:
8698 val |= PIPEMISC_DITHER_8_BPC;
8699 break;
8700 case 30:
8701 val |= PIPEMISC_DITHER_10_BPC;
8702 break;
8703 case 36:
8704 val |= PIPEMISC_DITHER_12_BPC;
8705 break;
8706 default:
8707 /* Case prevented by pipe_config_set_bpp. */
8708 BUG();
8709 }
8710
8711 if (intel_crtc->config->dither)
8712 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8713
8714 I915_WRITE(PIPEMISC(pipe), val);
8715 }
8716 }
8717
8718 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8719 struct intel_crtc_state *crtc_state,
8720 intel_clock_t *clock,
8721 bool *has_reduced_clock,
8722 intel_clock_t *reduced_clock)
8723 {
8724 struct drm_device *dev = crtc->dev;
8725 struct drm_i915_private *dev_priv = dev->dev_private;
8726 int refclk;
8727 const intel_limit_t *limit;
8728 bool ret;
8729
8730 refclk = ironlake_get_refclk(crtc_state);
8731
8732 /*
8733 * Returns a set of divisors for the desired target clock with the given
8734 * refclk, or FALSE. The returned values represent the clock equation:
8735 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8736 */
8737 limit = intel_limit(crtc_state, refclk);
8738 ret = dev_priv->display.find_dpll(limit, crtc_state,
8739 crtc_state->port_clock,
8740 refclk, NULL, clock);
8741 if (!ret)
8742 return false;
8743
8744 return true;
8745 }
8746
8747 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8748 {
8749 /*
8750 * Account for spread spectrum to avoid
8751 * oversubscribing the link. Max center spread
8752 * is 2.5%; use 5% for safety's sake.
8753 */
8754 u32 bps = target_clock * bpp * 21 / 20;
8755 return DIV_ROUND_UP(bps, link_bw * 8);
8756 }
8757
8758 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8759 {
8760 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8761 }
8762
8763 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8764 struct intel_crtc_state *crtc_state,
8765 u32 *fp,
8766 intel_clock_t *reduced_clock, u32 *fp2)
8767 {
8768 struct drm_crtc *crtc = &intel_crtc->base;
8769 struct drm_device *dev = crtc->dev;
8770 struct drm_i915_private *dev_priv = dev->dev_private;
8771 struct drm_atomic_state *state = crtc_state->base.state;
8772 struct drm_connector *connector;
8773 struct drm_connector_state *connector_state;
8774 struct intel_encoder *encoder;
8775 uint32_t dpll;
8776 int factor, num_connectors = 0, i;
8777 bool is_lvds = false, is_sdvo = false;
8778
8779 for_each_connector_in_state(state, connector, connector_state, i) {
8780 if (connector_state->crtc != crtc_state->base.crtc)
8781 continue;
8782
8783 encoder = to_intel_encoder(connector_state->best_encoder);
8784
8785 switch (encoder->type) {
8786 case INTEL_OUTPUT_LVDS:
8787 is_lvds = true;
8788 break;
8789 case INTEL_OUTPUT_SDVO:
8790 case INTEL_OUTPUT_HDMI:
8791 is_sdvo = true;
8792 break;
8793 default:
8794 break;
8795 }
8796
8797 num_connectors++;
8798 }
8799
8800 /* Enable autotuning of the PLL clock (if permissible) */
8801 factor = 21;
8802 if (is_lvds) {
8803 if ((intel_panel_use_ssc(dev_priv) &&
8804 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8805 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8806 factor = 25;
8807 } else if (crtc_state->sdvo_tv_clock)
8808 factor = 20;
8809
8810 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8811 *fp |= FP_CB_TUNE;
8812
8813 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8814 *fp2 |= FP_CB_TUNE;
8815
8816 dpll = 0;
8817
8818 if (is_lvds)
8819 dpll |= DPLLB_MODE_LVDS;
8820 else
8821 dpll |= DPLLB_MODE_DAC_SERIAL;
8822
8823 dpll |= (crtc_state->pixel_multiplier - 1)
8824 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8825
8826 if (is_sdvo)
8827 dpll |= DPLL_SDVO_HIGH_SPEED;
8828 if (crtc_state->has_dp_encoder)
8829 dpll |= DPLL_SDVO_HIGH_SPEED;
8830
8831 /* compute bitmask from p1 value */
8832 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8833 /* also FPA1 */
8834 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8835
8836 switch (crtc_state->dpll.p2) {
8837 case 5:
8838 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8839 break;
8840 case 7:
8841 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8842 break;
8843 case 10:
8844 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8845 break;
8846 case 14:
8847 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8848 break;
8849 }
8850
8851 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8852 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8853 else
8854 dpll |= PLL_REF_INPUT_DREFCLK;
8855
8856 return dpll | DPLL_VCO_ENABLE;
8857 }
8858
8859 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8860 struct intel_crtc_state *crtc_state)
8861 {
8862 struct drm_device *dev = crtc->base.dev;
8863 intel_clock_t clock, reduced_clock;
8864 u32 dpll = 0, fp = 0, fp2 = 0;
8865 bool ok, has_reduced_clock = false;
8866 bool is_lvds = false;
8867 struct intel_shared_dpll *pll;
8868
8869 memset(&crtc_state->dpll_hw_state, 0,
8870 sizeof(crtc_state->dpll_hw_state));
8871
8872 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8873
8874 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8875 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8876
8877 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8878 &has_reduced_clock, &reduced_clock);
8879 if (!ok && !crtc_state->clock_set) {
8880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8881 return -EINVAL;
8882 }
8883 /* Compat-code for transition, will disappear. */
8884 if (!crtc_state->clock_set) {
8885 crtc_state->dpll.n = clock.n;
8886 crtc_state->dpll.m1 = clock.m1;
8887 crtc_state->dpll.m2 = clock.m2;
8888 crtc_state->dpll.p1 = clock.p1;
8889 crtc_state->dpll.p2 = clock.p2;
8890 }
8891
8892 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8893 if (crtc_state->has_pch_encoder) {
8894 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8895 if (has_reduced_clock)
8896 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8897
8898 dpll = ironlake_compute_dpll(crtc, crtc_state,
8899 &fp, &reduced_clock,
8900 has_reduced_clock ? &fp2 : NULL);
8901
8902 crtc_state->dpll_hw_state.dpll = dpll;
8903 crtc_state->dpll_hw_state.fp0 = fp;
8904 if (has_reduced_clock)
8905 crtc_state->dpll_hw_state.fp1 = fp2;
8906 else
8907 crtc_state->dpll_hw_state.fp1 = fp;
8908
8909 pll = intel_get_shared_dpll(crtc, crtc_state);
8910 if (pll == NULL) {
8911 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8912 pipe_name(crtc->pipe));
8913 return -EINVAL;
8914 }
8915 }
8916
8917 if (is_lvds && has_reduced_clock)
8918 crtc->lowfreq_avail = true;
8919 else
8920 crtc->lowfreq_avail = false;
8921
8922 return 0;
8923 }
8924
8925 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8926 struct intel_link_m_n *m_n)
8927 {
8928 struct drm_device *dev = crtc->base.dev;
8929 struct drm_i915_private *dev_priv = dev->dev_private;
8930 enum pipe pipe = crtc->pipe;
8931
8932 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8933 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8934 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8935 & ~TU_SIZE_MASK;
8936 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8937 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8938 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8939 }
8940
8941 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8942 enum transcoder transcoder,
8943 struct intel_link_m_n *m_n,
8944 struct intel_link_m_n *m2_n2)
8945 {
8946 struct drm_device *dev = crtc->base.dev;
8947 struct drm_i915_private *dev_priv = dev->dev_private;
8948 enum pipe pipe = crtc->pipe;
8949
8950 if (INTEL_INFO(dev)->gen >= 5) {
8951 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8952 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8953 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8954 & ~TU_SIZE_MASK;
8955 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8956 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8957 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8958 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8959 * gen < 8) and if DRRS is supported (to make sure the
8960 * registers are not unnecessarily read).
8961 */
8962 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8963 crtc->config->has_drrs) {
8964 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8965 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8966 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8967 & ~TU_SIZE_MASK;
8968 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8969 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8970 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8971 }
8972 } else {
8973 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8974 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8975 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8976 & ~TU_SIZE_MASK;
8977 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8978 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8979 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8980 }
8981 }
8982
8983 void intel_dp_get_m_n(struct intel_crtc *crtc,
8984 struct intel_crtc_state *pipe_config)
8985 {
8986 if (pipe_config->has_pch_encoder)
8987 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8988 else
8989 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8990 &pipe_config->dp_m_n,
8991 &pipe_config->dp_m2_n2);
8992 }
8993
8994 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8995 struct intel_crtc_state *pipe_config)
8996 {
8997 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8998 &pipe_config->fdi_m_n, NULL);
8999 }
9000
9001 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9002 struct intel_crtc_state *pipe_config)
9003 {
9004 struct drm_device *dev = crtc->base.dev;
9005 struct drm_i915_private *dev_priv = dev->dev_private;
9006 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9007 uint32_t ps_ctrl = 0;
9008 int id = -1;
9009 int i;
9010
9011 /* find scaler attached to this pipe */
9012 for (i = 0; i < crtc->num_scalers; i++) {
9013 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9014 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9015 id = i;
9016 pipe_config->pch_pfit.enabled = true;
9017 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9018 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9019 break;
9020 }
9021 }
9022
9023 scaler_state->scaler_id = id;
9024 if (id >= 0) {
9025 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9026 } else {
9027 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9028 }
9029 }
9030
9031 static void
9032 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9033 struct intel_initial_plane_config *plane_config)
9034 {
9035 struct drm_device *dev = crtc->base.dev;
9036 struct drm_i915_private *dev_priv = dev->dev_private;
9037 u32 val, base, offset, stride_mult, tiling;
9038 int pipe = crtc->pipe;
9039 int fourcc, pixel_format;
9040 unsigned int aligned_height;
9041 struct drm_framebuffer *fb;
9042 struct intel_framebuffer *intel_fb;
9043
9044 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9045 if (!intel_fb) {
9046 DRM_DEBUG_KMS("failed to alloc fb\n");
9047 return;
9048 }
9049
9050 fb = &intel_fb->base;
9051
9052 val = I915_READ(PLANE_CTL(pipe, 0));
9053 if (!(val & PLANE_CTL_ENABLE))
9054 goto error;
9055
9056 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9057 fourcc = skl_format_to_fourcc(pixel_format,
9058 val & PLANE_CTL_ORDER_RGBX,
9059 val & PLANE_CTL_ALPHA_MASK);
9060 fb->pixel_format = fourcc;
9061 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9062
9063 tiling = val & PLANE_CTL_TILED_MASK;
9064 switch (tiling) {
9065 case PLANE_CTL_TILED_LINEAR:
9066 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9067 break;
9068 case PLANE_CTL_TILED_X:
9069 plane_config->tiling = I915_TILING_X;
9070 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9071 break;
9072 case PLANE_CTL_TILED_Y:
9073 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9074 break;
9075 case PLANE_CTL_TILED_YF:
9076 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9077 break;
9078 default:
9079 MISSING_CASE(tiling);
9080 goto error;
9081 }
9082
9083 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9084 plane_config->base = base;
9085
9086 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9087
9088 val = I915_READ(PLANE_SIZE(pipe, 0));
9089 fb->height = ((val >> 16) & 0xfff) + 1;
9090 fb->width = ((val >> 0) & 0x1fff) + 1;
9091
9092 val = I915_READ(PLANE_STRIDE(pipe, 0));
9093 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9094 fb->pixel_format);
9095 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9096
9097 aligned_height = intel_fb_align_height(dev, fb->height,
9098 fb->pixel_format,
9099 fb->modifier[0]);
9100
9101 plane_config->size = fb->pitches[0] * aligned_height;
9102
9103 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9104 pipe_name(pipe), fb->width, fb->height,
9105 fb->bits_per_pixel, base, fb->pitches[0],
9106 plane_config->size);
9107
9108 plane_config->fb = intel_fb;
9109 return;
9110
9111 error:
9112 kfree(fb);
9113 }
9114
9115 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9116 struct intel_crtc_state *pipe_config)
9117 {
9118 struct drm_device *dev = crtc->base.dev;
9119 struct drm_i915_private *dev_priv = dev->dev_private;
9120 uint32_t tmp;
9121
9122 tmp = I915_READ(PF_CTL(crtc->pipe));
9123
9124 if (tmp & PF_ENABLE) {
9125 pipe_config->pch_pfit.enabled = true;
9126 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9127 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9128
9129 /* We currently do not free assignements of panel fitters on
9130 * ivb/hsw (since we don't use the higher upscaling modes which
9131 * differentiates them) so just WARN about this case for now. */
9132 if (IS_GEN7(dev)) {
9133 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9134 PF_PIPE_SEL_IVB(crtc->pipe));
9135 }
9136 }
9137 }
9138
9139 static void
9140 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9141 struct intel_initial_plane_config *plane_config)
9142 {
9143 struct drm_device *dev = crtc->base.dev;
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9145 u32 val, base, offset;
9146 int pipe = crtc->pipe;
9147 int fourcc, pixel_format;
9148 unsigned int aligned_height;
9149 struct drm_framebuffer *fb;
9150 struct intel_framebuffer *intel_fb;
9151
9152 val = I915_READ(DSPCNTR(pipe));
9153 if (!(val & DISPLAY_PLANE_ENABLE))
9154 return;
9155
9156 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9157 if (!intel_fb) {
9158 DRM_DEBUG_KMS("failed to alloc fb\n");
9159 return;
9160 }
9161
9162 fb = &intel_fb->base;
9163
9164 if (INTEL_INFO(dev)->gen >= 4) {
9165 if (val & DISPPLANE_TILED) {
9166 plane_config->tiling = I915_TILING_X;
9167 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9168 }
9169 }
9170
9171 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9172 fourcc = i9xx_format_to_fourcc(pixel_format);
9173 fb->pixel_format = fourcc;
9174 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9175
9176 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9177 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9178 offset = I915_READ(DSPOFFSET(pipe));
9179 } else {
9180 if (plane_config->tiling)
9181 offset = I915_READ(DSPTILEOFF(pipe));
9182 else
9183 offset = I915_READ(DSPLINOFF(pipe));
9184 }
9185 plane_config->base = base;
9186
9187 val = I915_READ(PIPESRC(pipe));
9188 fb->width = ((val >> 16) & 0xfff) + 1;
9189 fb->height = ((val >> 0) & 0xfff) + 1;
9190
9191 val = I915_READ(DSPSTRIDE(pipe));
9192 fb->pitches[0] = val & 0xffffffc0;
9193
9194 aligned_height = intel_fb_align_height(dev, fb->height,
9195 fb->pixel_format,
9196 fb->modifier[0]);
9197
9198 plane_config->size = fb->pitches[0] * aligned_height;
9199
9200 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9201 pipe_name(pipe), fb->width, fb->height,
9202 fb->bits_per_pixel, base, fb->pitches[0],
9203 plane_config->size);
9204
9205 plane_config->fb = intel_fb;
9206 }
9207
9208 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9209 struct intel_crtc_state *pipe_config)
9210 {
9211 struct drm_device *dev = crtc->base.dev;
9212 struct drm_i915_private *dev_priv = dev->dev_private;
9213 uint32_t tmp;
9214
9215 if (!intel_display_power_is_enabled(dev_priv,
9216 POWER_DOMAIN_PIPE(crtc->pipe)))
9217 return false;
9218
9219 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9220 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9221
9222 tmp = I915_READ(PIPECONF(crtc->pipe));
9223 if (!(tmp & PIPECONF_ENABLE))
9224 return false;
9225
9226 switch (tmp & PIPECONF_BPC_MASK) {
9227 case PIPECONF_6BPC:
9228 pipe_config->pipe_bpp = 18;
9229 break;
9230 case PIPECONF_8BPC:
9231 pipe_config->pipe_bpp = 24;
9232 break;
9233 case PIPECONF_10BPC:
9234 pipe_config->pipe_bpp = 30;
9235 break;
9236 case PIPECONF_12BPC:
9237 pipe_config->pipe_bpp = 36;
9238 break;
9239 default:
9240 break;
9241 }
9242
9243 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9244 pipe_config->limited_color_range = true;
9245
9246 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9247 struct intel_shared_dpll *pll;
9248
9249 pipe_config->has_pch_encoder = true;
9250
9251 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9252 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9253 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9254
9255 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9256
9257 if (HAS_PCH_IBX(dev_priv->dev)) {
9258 pipe_config->shared_dpll =
9259 (enum intel_dpll_id) crtc->pipe;
9260 } else {
9261 tmp = I915_READ(PCH_DPLL_SEL);
9262 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9263 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9264 else
9265 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9266 }
9267
9268 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9269
9270 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9271 &pipe_config->dpll_hw_state));
9272
9273 tmp = pipe_config->dpll_hw_state.dpll;
9274 pipe_config->pixel_multiplier =
9275 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9276 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9277
9278 ironlake_pch_clock_get(crtc, pipe_config);
9279 } else {
9280 pipe_config->pixel_multiplier = 1;
9281 }
9282
9283 intel_get_pipe_timings(crtc, pipe_config);
9284
9285 ironlake_get_pfit_config(crtc, pipe_config);
9286
9287 return true;
9288 }
9289
9290 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9291 {
9292 struct drm_device *dev = dev_priv->dev;
9293 struct intel_crtc *crtc;
9294
9295 for_each_intel_crtc(dev, crtc)
9296 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9297 pipe_name(crtc->pipe));
9298
9299 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9300 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9301 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9302 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9303 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9304 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9305 "CPU PWM1 enabled\n");
9306 if (IS_HASWELL(dev))
9307 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9308 "CPU PWM2 enabled\n");
9309 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9310 "PCH PWM1 enabled\n");
9311 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9312 "Utility pin enabled\n");
9313 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9314
9315 /*
9316 * In theory we can still leave IRQs enabled, as long as only the HPD
9317 * interrupts remain enabled. We used to check for that, but since it's
9318 * gen-specific and since we only disable LCPLL after we fully disable
9319 * the interrupts, the check below should be enough.
9320 */
9321 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9322 }
9323
9324 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9325 {
9326 struct drm_device *dev = dev_priv->dev;
9327
9328 if (IS_HASWELL(dev))
9329 return I915_READ(D_COMP_HSW);
9330 else
9331 return I915_READ(D_COMP_BDW);
9332 }
9333
9334 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9335 {
9336 struct drm_device *dev = dev_priv->dev;
9337
9338 if (IS_HASWELL(dev)) {
9339 mutex_lock(&dev_priv->rps.hw_lock);
9340 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9341 val))
9342 DRM_ERROR("Failed to write to D_COMP\n");
9343 mutex_unlock(&dev_priv->rps.hw_lock);
9344 } else {
9345 I915_WRITE(D_COMP_BDW, val);
9346 POSTING_READ(D_COMP_BDW);
9347 }
9348 }
9349
9350 /*
9351 * This function implements pieces of two sequences from BSpec:
9352 * - Sequence for display software to disable LCPLL
9353 * - Sequence for display software to allow package C8+
9354 * The steps implemented here are just the steps that actually touch the LCPLL
9355 * register. Callers should take care of disabling all the display engine
9356 * functions, doing the mode unset, fixing interrupts, etc.
9357 */
9358 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9359 bool switch_to_fclk, bool allow_power_down)
9360 {
9361 uint32_t val;
9362
9363 assert_can_disable_lcpll(dev_priv);
9364
9365 val = I915_READ(LCPLL_CTL);
9366
9367 if (switch_to_fclk) {
9368 val |= LCPLL_CD_SOURCE_FCLK;
9369 I915_WRITE(LCPLL_CTL, val);
9370
9371 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9372 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9373 DRM_ERROR("Switching to FCLK failed\n");
9374
9375 val = I915_READ(LCPLL_CTL);
9376 }
9377
9378 val |= LCPLL_PLL_DISABLE;
9379 I915_WRITE(LCPLL_CTL, val);
9380 POSTING_READ(LCPLL_CTL);
9381
9382 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9383 DRM_ERROR("LCPLL still locked\n");
9384
9385 val = hsw_read_dcomp(dev_priv);
9386 val |= D_COMP_COMP_DISABLE;
9387 hsw_write_dcomp(dev_priv, val);
9388 ndelay(100);
9389
9390 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9391 1))
9392 DRM_ERROR("D_COMP RCOMP still in progress\n");
9393
9394 if (allow_power_down) {
9395 val = I915_READ(LCPLL_CTL);
9396 val |= LCPLL_POWER_DOWN_ALLOW;
9397 I915_WRITE(LCPLL_CTL, val);
9398 POSTING_READ(LCPLL_CTL);
9399 }
9400 }
9401
9402 /*
9403 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9404 * source.
9405 */
9406 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9407 {
9408 uint32_t val;
9409
9410 val = I915_READ(LCPLL_CTL);
9411
9412 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9413 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9414 return;
9415
9416 /*
9417 * Make sure we're not on PC8 state before disabling PC8, otherwise
9418 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9419 */
9420 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9421
9422 if (val & LCPLL_POWER_DOWN_ALLOW) {
9423 val &= ~LCPLL_POWER_DOWN_ALLOW;
9424 I915_WRITE(LCPLL_CTL, val);
9425 POSTING_READ(LCPLL_CTL);
9426 }
9427
9428 val = hsw_read_dcomp(dev_priv);
9429 val |= D_COMP_COMP_FORCE;
9430 val &= ~D_COMP_COMP_DISABLE;
9431 hsw_write_dcomp(dev_priv, val);
9432
9433 val = I915_READ(LCPLL_CTL);
9434 val &= ~LCPLL_PLL_DISABLE;
9435 I915_WRITE(LCPLL_CTL, val);
9436
9437 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9438 DRM_ERROR("LCPLL not locked yet\n");
9439
9440 if (val & LCPLL_CD_SOURCE_FCLK) {
9441 val = I915_READ(LCPLL_CTL);
9442 val &= ~LCPLL_CD_SOURCE_FCLK;
9443 I915_WRITE(LCPLL_CTL, val);
9444
9445 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9446 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9447 DRM_ERROR("Switching back to LCPLL failed\n");
9448 }
9449
9450 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9451 intel_update_cdclk(dev_priv->dev);
9452 }
9453
9454 /*
9455 * Package states C8 and deeper are really deep PC states that can only be
9456 * reached when all the devices on the system allow it, so even if the graphics
9457 * device allows PC8+, it doesn't mean the system will actually get to these
9458 * states. Our driver only allows PC8+ when going into runtime PM.
9459 *
9460 * The requirements for PC8+ are that all the outputs are disabled, the power
9461 * well is disabled and most interrupts are disabled, and these are also
9462 * requirements for runtime PM. When these conditions are met, we manually do
9463 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9464 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9465 * hang the machine.
9466 *
9467 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9468 * the state of some registers, so when we come back from PC8+ we need to
9469 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9470 * need to take care of the registers kept by RC6. Notice that this happens even
9471 * if we don't put the device in PCI D3 state (which is what currently happens
9472 * because of the runtime PM support).
9473 *
9474 * For more, read "Display Sequences for Package C8" on the hardware
9475 * documentation.
9476 */
9477 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9478 {
9479 struct drm_device *dev = dev_priv->dev;
9480 uint32_t val;
9481
9482 DRM_DEBUG_KMS("Enabling package C8+\n");
9483
9484 if (HAS_PCH_LPT_LP(dev)) {
9485 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9486 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9487 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9488 }
9489
9490 lpt_disable_clkout_dp(dev);
9491 hsw_disable_lcpll(dev_priv, true, true);
9492 }
9493
9494 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9495 {
9496 struct drm_device *dev = dev_priv->dev;
9497 uint32_t val;
9498
9499 DRM_DEBUG_KMS("Disabling package C8+\n");
9500
9501 hsw_restore_lcpll(dev_priv);
9502 lpt_init_pch_refclk(dev);
9503
9504 if (HAS_PCH_LPT_LP(dev)) {
9505 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9506 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9507 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9508 }
9509
9510 intel_prepare_ddi(dev);
9511 }
9512
9513 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9514 {
9515 struct drm_device *dev = old_state->dev;
9516 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9517
9518 broxton_set_cdclk(dev, req_cdclk);
9519 }
9520
9521 /* compute the max rate for new configuration */
9522 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9523 {
9524 struct intel_crtc *intel_crtc;
9525 struct intel_crtc_state *crtc_state;
9526 int max_pixel_rate = 0;
9527
9528 for_each_intel_crtc(state->dev, intel_crtc) {
9529 int pixel_rate;
9530
9531 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9532 if (IS_ERR(crtc_state))
9533 return PTR_ERR(crtc_state);
9534
9535 if (!crtc_state->base.enable)
9536 continue;
9537
9538 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9539
9540 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9541 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9542 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9543
9544 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9545 }
9546
9547 return max_pixel_rate;
9548 }
9549
9550 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9551 {
9552 struct drm_i915_private *dev_priv = dev->dev_private;
9553 uint32_t val, data;
9554 int ret;
9555
9556 if (WARN((I915_READ(LCPLL_CTL) &
9557 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9558 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9559 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9560 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9561 "trying to change cdclk frequency with cdclk not enabled\n"))
9562 return;
9563
9564 mutex_lock(&dev_priv->rps.hw_lock);
9565 ret = sandybridge_pcode_write(dev_priv,
9566 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9567 mutex_unlock(&dev_priv->rps.hw_lock);
9568 if (ret) {
9569 DRM_ERROR("failed to inform pcode about cdclk change\n");
9570 return;
9571 }
9572
9573 val = I915_READ(LCPLL_CTL);
9574 val |= LCPLL_CD_SOURCE_FCLK;
9575 I915_WRITE(LCPLL_CTL, val);
9576
9577 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9578 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9579 DRM_ERROR("Switching to FCLK failed\n");
9580
9581 val = I915_READ(LCPLL_CTL);
9582 val &= ~LCPLL_CLK_FREQ_MASK;
9583
9584 switch (cdclk) {
9585 case 450000:
9586 val |= LCPLL_CLK_FREQ_450;
9587 data = 0;
9588 break;
9589 case 540000:
9590 val |= LCPLL_CLK_FREQ_54O_BDW;
9591 data = 1;
9592 break;
9593 case 337500:
9594 val |= LCPLL_CLK_FREQ_337_5_BDW;
9595 data = 2;
9596 break;
9597 case 675000:
9598 val |= LCPLL_CLK_FREQ_675_BDW;
9599 data = 3;
9600 break;
9601 default:
9602 WARN(1, "invalid cdclk frequency\n");
9603 return;
9604 }
9605
9606 I915_WRITE(LCPLL_CTL, val);
9607
9608 val = I915_READ(LCPLL_CTL);
9609 val &= ~LCPLL_CD_SOURCE_FCLK;
9610 I915_WRITE(LCPLL_CTL, val);
9611
9612 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9613 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9614 DRM_ERROR("Switching back to LCPLL failed\n");
9615
9616 mutex_lock(&dev_priv->rps.hw_lock);
9617 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9618 mutex_unlock(&dev_priv->rps.hw_lock);
9619
9620 intel_update_cdclk(dev);
9621
9622 WARN(cdclk != dev_priv->cdclk_freq,
9623 "cdclk requested %d kHz but got %d kHz\n",
9624 cdclk, dev_priv->cdclk_freq);
9625 }
9626
9627 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9628 {
9629 struct drm_i915_private *dev_priv = to_i915(state->dev);
9630 int max_pixclk = ilk_max_pixel_rate(state);
9631 int cdclk;
9632
9633 /*
9634 * FIXME should also account for plane ratio
9635 * once 64bpp pixel formats are supported.
9636 */
9637 if (max_pixclk > 540000)
9638 cdclk = 675000;
9639 else if (max_pixclk > 450000)
9640 cdclk = 540000;
9641 else if (max_pixclk > 337500)
9642 cdclk = 450000;
9643 else
9644 cdclk = 337500;
9645
9646 /*
9647 * FIXME move the cdclk caclulation to
9648 * compute_config() so we can fail gracegully.
9649 */
9650 if (cdclk > dev_priv->max_cdclk_freq) {
9651 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9652 cdclk, dev_priv->max_cdclk_freq);
9653 cdclk = dev_priv->max_cdclk_freq;
9654 }
9655
9656 to_intel_atomic_state(state)->cdclk = cdclk;
9657
9658 return 0;
9659 }
9660
9661 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9662 {
9663 struct drm_device *dev = old_state->dev;
9664 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9665
9666 broadwell_set_cdclk(dev, req_cdclk);
9667 }
9668
9669 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9670 struct intel_crtc_state *crtc_state)
9671 {
9672 if (!intel_ddi_pll_select(crtc, crtc_state))
9673 return -EINVAL;
9674
9675 crtc->lowfreq_avail = false;
9676
9677 return 0;
9678 }
9679
9680 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9681 enum port port,
9682 struct intel_crtc_state *pipe_config)
9683 {
9684 switch (port) {
9685 case PORT_A:
9686 pipe_config->ddi_pll_sel = SKL_DPLL0;
9687 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9688 break;
9689 case PORT_B:
9690 pipe_config->ddi_pll_sel = SKL_DPLL1;
9691 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9692 break;
9693 case PORT_C:
9694 pipe_config->ddi_pll_sel = SKL_DPLL2;
9695 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9696 break;
9697 default:
9698 DRM_ERROR("Incorrect port type\n");
9699 }
9700 }
9701
9702 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9703 enum port port,
9704 struct intel_crtc_state *pipe_config)
9705 {
9706 u32 temp, dpll_ctl1;
9707
9708 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9709 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9710
9711 switch (pipe_config->ddi_pll_sel) {
9712 case SKL_DPLL0:
9713 /*
9714 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9715 * of the shared DPLL framework and thus needs to be read out
9716 * separately
9717 */
9718 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9719 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9720 break;
9721 case SKL_DPLL1:
9722 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9723 break;
9724 case SKL_DPLL2:
9725 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9726 break;
9727 case SKL_DPLL3:
9728 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9729 break;
9730 }
9731 }
9732
9733 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9734 enum port port,
9735 struct intel_crtc_state *pipe_config)
9736 {
9737 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9738
9739 switch (pipe_config->ddi_pll_sel) {
9740 case PORT_CLK_SEL_WRPLL1:
9741 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9742 break;
9743 case PORT_CLK_SEL_WRPLL2:
9744 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9745 break;
9746 }
9747 }
9748
9749 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9750 struct intel_crtc_state *pipe_config)
9751 {
9752 struct drm_device *dev = crtc->base.dev;
9753 struct drm_i915_private *dev_priv = dev->dev_private;
9754 struct intel_shared_dpll *pll;
9755 enum port port;
9756 uint32_t tmp;
9757
9758 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9759
9760 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9761
9762 if (IS_SKYLAKE(dev))
9763 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9764 else if (IS_BROXTON(dev))
9765 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9766 else
9767 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9768
9769 if (pipe_config->shared_dpll >= 0) {
9770 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9771
9772 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9773 &pipe_config->dpll_hw_state));
9774 }
9775
9776 /*
9777 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9778 * DDI E. So just check whether this pipe is wired to DDI E and whether
9779 * the PCH transcoder is on.
9780 */
9781 if (INTEL_INFO(dev)->gen < 9 &&
9782 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9783 pipe_config->has_pch_encoder = true;
9784
9785 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9786 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9787 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9788
9789 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9790 }
9791 }
9792
9793 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9794 struct intel_crtc_state *pipe_config)
9795 {
9796 struct drm_device *dev = crtc->base.dev;
9797 struct drm_i915_private *dev_priv = dev->dev_private;
9798 enum intel_display_power_domain pfit_domain;
9799 uint32_t tmp;
9800
9801 if (!intel_display_power_is_enabled(dev_priv,
9802 POWER_DOMAIN_PIPE(crtc->pipe)))
9803 return false;
9804
9805 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9806 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9807
9808 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9809 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9810 enum pipe trans_edp_pipe;
9811 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9812 default:
9813 WARN(1, "unknown pipe linked to edp transcoder\n");
9814 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9815 case TRANS_DDI_EDP_INPUT_A_ON:
9816 trans_edp_pipe = PIPE_A;
9817 break;
9818 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9819 trans_edp_pipe = PIPE_B;
9820 break;
9821 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9822 trans_edp_pipe = PIPE_C;
9823 break;
9824 }
9825
9826 if (trans_edp_pipe == crtc->pipe)
9827 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9828 }
9829
9830 if (!intel_display_power_is_enabled(dev_priv,
9831 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9832 return false;
9833
9834 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9835 if (!(tmp & PIPECONF_ENABLE))
9836 return false;
9837
9838 haswell_get_ddi_port_state(crtc, pipe_config);
9839
9840 intel_get_pipe_timings(crtc, pipe_config);
9841
9842 if (INTEL_INFO(dev)->gen >= 9) {
9843 skl_init_scalers(dev, crtc, pipe_config);
9844 }
9845
9846 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9847
9848 if (INTEL_INFO(dev)->gen >= 9) {
9849 pipe_config->scaler_state.scaler_id = -1;
9850 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9851 }
9852
9853 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9854 if (INTEL_INFO(dev)->gen >= 9)
9855 skylake_get_pfit_config(crtc, pipe_config);
9856 else
9857 ironlake_get_pfit_config(crtc, pipe_config);
9858 }
9859
9860 if (IS_HASWELL(dev))
9861 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9862 (I915_READ(IPS_CTL) & IPS_ENABLE);
9863
9864 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9865 pipe_config->pixel_multiplier =
9866 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9867 } else {
9868 pipe_config->pixel_multiplier = 1;
9869 }
9870
9871 return true;
9872 }
9873
9874 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9875 {
9876 struct drm_device *dev = crtc->dev;
9877 struct drm_i915_private *dev_priv = dev->dev_private;
9878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9879 uint32_t cntl = 0, size = 0;
9880
9881 if (base) {
9882 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9883 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9884 unsigned int stride = roundup_pow_of_two(width) * 4;
9885
9886 switch (stride) {
9887 default:
9888 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9889 width, stride);
9890 stride = 256;
9891 /* fallthrough */
9892 case 256:
9893 case 512:
9894 case 1024:
9895 case 2048:
9896 break;
9897 }
9898
9899 cntl |= CURSOR_ENABLE |
9900 CURSOR_GAMMA_ENABLE |
9901 CURSOR_FORMAT_ARGB |
9902 CURSOR_STRIDE(stride);
9903
9904 size = (height << 12) | width;
9905 }
9906
9907 if (intel_crtc->cursor_cntl != 0 &&
9908 (intel_crtc->cursor_base != base ||
9909 intel_crtc->cursor_size != size ||
9910 intel_crtc->cursor_cntl != cntl)) {
9911 /* On these chipsets we can only modify the base/size/stride
9912 * whilst the cursor is disabled.
9913 */
9914 I915_WRITE(CURCNTR(PIPE_A), 0);
9915 POSTING_READ(CURCNTR(PIPE_A));
9916 intel_crtc->cursor_cntl = 0;
9917 }
9918
9919 if (intel_crtc->cursor_base != base) {
9920 I915_WRITE(CURBASE(PIPE_A), base);
9921 intel_crtc->cursor_base = base;
9922 }
9923
9924 if (intel_crtc->cursor_size != size) {
9925 I915_WRITE(CURSIZE, size);
9926 intel_crtc->cursor_size = size;
9927 }
9928
9929 if (intel_crtc->cursor_cntl != cntl) {
9930 I915_WRITE(CURCNTR(PIPE_A), cntl);
9931 POSTING_READ(CURCNTR(PIPE_A));
9932 intel_crtc->cursor_cntl = cntl;
9933 }
9934 }
9935
9936 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9937 {
9938 struct drm_device *dev = crtc->dev;
9939 struct drm_i915_private *dev_priv = dev->dev_private;
9940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9941 int pipe = intel_crtc->pipe;
9942 uint32_t cntl;
9943
9944 cntl = 0;
9945 if (base) {
9946 cntl = MCURSOR_GAMMA_ENABLE;
9947 switch (intel_crtc->base.cursor->state->crtc_w) {
9948 case 64:
9949 cntl |= CURSOR_MODE_64_ARGB_AX;
9950 break;
9951 case 128:
9952 cntl |= CURSOR_MODE_128_ARGB_AX;
9953 break;
9954 case 256:
9955 cntl |= CURSOR_MODE_256_ARGB_AX;
9956 break;
9957 default:
9958 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9959 return;
9960 }
9961 cntl |= pipe << 28; /* Connect to correct pipe */
9962
9963 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9964 cntl |= CURSOR_PIPE_CSC_ENABLE;
9965 }
9966
9967 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9968 cntl |= CURSOR_ROTATE_180;
9969
9970 if (intel_crtc->cursor_cntl != cntl) {
9971 I915_WRITE(CURCNTR(pipe), cntl);
9972 POSTING_READ(CURCNTR(pipe));
9973 intel_crtc->cursor_cntl = cntl;
9974 }
9975
9976 /* and commit changes on next vblank */
9977 I915_WRITE(CURBASE(pipe), base);
9978 POSTING_READ(CURBASE(pipe));
9979
9980 intel_crtc->cursor_base = base;
9981 }
9982
9983 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9984 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9985 bool on)
9986 {
9987 struct drm_device *dev = crtc->dev;
9988 struct drm_i915_private *dev_priv = dev->dev_private;
9989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9990 int pipe = intel_crtc->pipe;
9991 struct drm_plane_state *cursor_state = crtc->cursor->state;
9992 int x = cursor_state->crtc_x;
9993 int y = cursor_state->crtc_y;
9994 u32 base = 0, pos = 0;
9995
9996 if (on)
9997 base = intel_crtc->cursor_addr;
9998
9999 if (x >= intel_crtc->config->pipe_src_w)
10000 base = 0;
10001
10002 if (y >= intel_crtc->config->pipe_src_h)
10003 base = 0;
10004
10005 if (x < 0) {
10006 if (x + cursor_state->crtc_w <= 0)
10007 base = 0;
10008
10009 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10010 x = -x;
10011 }
10012 pos |= x << CURSOR_X_SHIFT;
10013
10014 if (y < 0) {
10015 if (y + cursor_state->crtc_h <= 0)
10016 base = 0;
10017
10018 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10019 y = -y;
10020 }
10021 pos |= y << CURSOR_Y_SHIFT;
10022
10023 if (base == 0 && intel_crtc->cursor_base == 0)
10024 return;
10025
10026 I915_WRITE(CURPOS(pipe), pos);
10027
10028 /* ILK+ do this automagically */
10029 if (HAS_GMCH_DISPLAY(dev) &&
10030 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10031 base += (cursor_state->crtc_h *
10032 cursor_state->crtc_w - 1) * 4;
10033 }
10034
10035 if (IS_845G(dev) || IS_I865G(dev))
10036 i845_update_cursor(crtc, base);
10037 else
10038 i9xx_update_cursor(crtc, base);
10039 }
10040
10041 static bool cursor_size_ok(struct drm_device *dev,
10042 uint32_t width, uint32_t height)
10043 {
10044 if (width == 0 || height == 0)
10045 return false;
10046
10047 /*
10048 * 845g/865g are special in that they are only limited by
10049 * the width of their cursors, the height is arbitrary up to
10050 * the precision of the register. Everything else requires
10051 * square cursors, limited to a few power-of-two sizes.
10052 */
10053 if (IS_845G(dev) || IS_I865G(dev)) {
10054 if ((width & 63) != 0)
10055 return false;
10056
10057 if (width > (IS_845G(dev) ? 64 : 512))
10058 return false;
10059
10060 if (height > 1023)
10061 return false;
10062 } else {
10063 switch (width | height) {
10064 case 256:
10065 case 128:
10066 if (IS_GEN2(dev))
10067 return false;
10068 case 64:
10069 break;
10070 default:
10071 return false;
10072 }
10073 }
10074
10075 return true;
10076 }
10077
10078 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10079 u16 *blue, uint32_t start, uint32_t size)
10080 {
10081 int end = (start + size > 256) ? 256 : start + size, i;
10082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10083
10084 for (i = start; i < end; i++) {
10085 intel_crtc->lut_r[i] = red[i] >> 8;
10086 intel_crtc->lut_g[i] = green[i] >> 8;
10087 intel_crtc->lut_b[i] = blue[i] >> 8;
10088 }
10089
10090 intel_crtc_load_lut(crtc);
10091 }
10092
10093 /* VESA 640x480x72Hz mode to set on the pipe */
10094 static struct drm_display_mode load_detect_mode = {
10095 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10096 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10097 };
10098
10099 struct drm_framebuffer *
10100 __intel_framebuffer_create(struct drm_device *dev,
10101 struct drm_mode_fb_cmd2 *mode_cmd,
10102 struct drm_i915_gem_object *obj)
10103 {
10104 struct intel_framebuffer *intel_fb;
10105 int ret;
10106
10107 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10108 if (!intel_fb) {
10109 drm_gem_object_unreference(&obj->base);
10110 return ERR_PTR(-ENOMEM);
10111 }
10112
10113 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10114 if (ret)
10115 goto err;
10116
10117 return &intel_fb->base;
10118 err:
10119 drm_gem_object_unreference(&obj->base);
10120 kfree(intel_fb);
10121
10122 return ERR_PTR(ret);
10123 }
10124
10125 static struct drm_framebuffer *
10126 intel_framebuffer_create(struct drm_device *dev,
10127 struct drm_mode_fb_cmd2 *mode_cmd,
10128 struct drm_i915_gem_object *obj)
10129 {
10130 struct drm_framebuffer *fb;
10131 int ret;
10132
10133 ret = i915_mutex_lock_interruptible(dev);
10134 if (ret)
10135 return ERR_PTR(ret);
10136 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10137 mutex_unlock(&dev->struct_mutex);
10138
10139 return fb;
10140 }
10141
10142 static u32
10143 intel_framebuffer_pitch_for_width(int width, int bpp)
10144 {
10145 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10146 return ALIGN(pitch, 64);
10147 }
10148
10149 static u32
10150 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10151 {
10152 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10153 return PAGE_ALIGN(pitch * mode->vdisplay);
10154 }
10155
10156 static struct drm_framebuffer *
10157 intel_framebuffer_create_for_mode(struct drm_device *dev,
10158 struct drm_display_mode *mode,
10159 int depth, int bpp)
10160 {
10161 struct drm_i915_gem_object *obj;
10162 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10163
10164 obj = i915_gem_alloc_object(dev,
10165 intel_framebuffer_size_for_mode(mode, bpp));
10166 if (obj == NULL)
10167 return ERR_PTR(-ENOMEM);
10168
10169 mode_cmd.width = mode->hdisplay;
10170 mode_cmd.height = mode->vdisplay;
10171 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10172 bpp);
10173 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10174
10175 return intel_framebuffer_create(dev, &mode_cmd, obj);
10176 }
10177
10178 static struct drm_framebuffer *
10179 mode_fits_in_fbdev(struct drm_device *dev,
10180 struct drm_display_mode *mode)
10181 {
10182 #ifdef CONFIG_DRM_FBDEV_EMULATION
10183 struct drm_i915_private *dev_priv = dev->dev_private;
10184 struct drm_i915_gem_object *obj;
10185 struct drm_framebuffer *fb;
10186
10187 if (!dev_priv->fbdev)
10188 return NULL;
10189
10190 if (!dev_priv->fbdev->fb)
10191 return NULL;
10192
10193 obj = dev_priv->fbdev->fb->obj;
10194 BUG_ON(!obj);
10195
10196 fb = &dev_priv->fbdev->fb->base;
10197 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10198 fb->bits_per_pixel))
10199 return NULL;
10200
10201 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10202 return NULL;
10203
10204 return fb;
10205 #else
10206 return NULL;
10207 #endif
10208 }
10209
10210 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10211 struct drm_crtc *crtc,
10212 struct drm_display_mode *mode,
10213 struct drm_framebuffer *fb,
10214 int x, int y)
10215 {
10216 struct drm_plane_state *plane_state;
10217 int hdisplay, vdisplay;
10218 int ret;
10219
10220 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10221 if (IS_ERR(plane_state))
10222 return PTR_ERR(plane_state);
10223
10224 if (mode)
10225 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10226 else
10227 hdisplay = vdisplay = 0;
10228
10229 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10230 if (ret)
10231 return ret;
10232 drm_atomic_set_fb_for_plane(plane_state, fb);
10233 plane_state->crtc_x = 0;
10234 plane_state->crtc_y = 0;
10235 plane_state->crtc_w = hdisplay;
10236 plane_state->crtc_h = vdisplay;
10237 plane_state->src_x = x << 16;
10238 plane_state->src_y = y << 16;
10239 plane_state->src_w = hdisplay << 16;
10240 plane_state->src_h = vdisplay << 16;
10241
10242 return 0;
10243 }
10244
10245 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10246 struct drm_display_mode *mode,
10247 struct intel_load_detect_pipe *old,
10248 struct drm_modeset_acquire_ctx *ctx)
10249 {
10250 struct intel_crtc *intel_crtc;
10251 struct intel_encoder *intel_encoder =
10252 intel_attached_encoder(connector);
10253 struct drm_crtc *possible_crtc;
10254 struct drm_encoder *encoder = &intel_encoder->base;
10255 struct drm_crtc *crtc = NULL;
10256 struct drm_device *dev = encoder->dev;
10257 struct drm_framebuffer *fb;
10258 struct drm_mode_config *config = &dev->mode_config;
10259 struct drm_atomic_state *state = NULL;
10260 struct drm_connector_state *connector_state;
10261 struct intel_crtc_state *crtc_state;
10262 int ret, i = -1;
10263
10264 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10265 connector->base.id, connector->name,
10266 encoder->base.id, encoder->name);
10267
10268 retry:
10269 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10270 if (ret)
10271 goto fail;
10272
10273 /*
10274 * Algorithm gets a little messy:
10275 *
10276 * - if the connector already has an assigned crtc, use it (but make
10277 * sure it's on first)
10278 *
10279 * - try to find the first unused crtc that can drive this connector,
10280 * and use that if we find one
10281 */
10282
10283 /* See if we already have a CRTC for this connector */
10284 if (encoder->crtc) {
10285 crtc = encoder->crtc;
10286
10287 ret = drm_modeset_lock(&crtc->mutex, ctx);
10288 if (ret)
10289 goto fail;
10290 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10291 if (ret)
10292 goto fail;
10293
10294 old->dpms_mode = connector->dpms;
10295 old->load_detect_temp = false;
10296
10297 /* Make sure the crtc and connector are running */
10298 if (connector->dpms != DRM_MODE_DPMS_ON)
10299 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10300
10301 return true;
10302 }
10303
10304 /* Find an unused one (if possible) */
10305 for_each_crtc(dev, possible_crtc) {
10306 i++;
10307 if (!(encoder->possible_crtcs & (1 << i)))
10308 continue;
10309 if (possible_crtc->state->enable)
10310 continue;
10311
10312 crtc = possible_crtc;
10313 break;
10314 }
10315
10316 /*
10317 * If we didn't find an unused CRTC, don't use any.
10318 */
10319 if (!crtc) {
10320 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10321 goto fail;
10322 }
10323
10324 ret = drm_modeset_lock(&crtc->mutex, ctx);
10325 if (ret)
10326 goto fail;
10327 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10328 if (ret)
10329 goto fail;
10330
10331 intel_crtc = to_intel_crtc(crtc);
10332 old->dpms_mode = connector->dpms;
10333 old->load_detect_temp = true;
10334 old->release_fb = NULL;
10335
10336 state = drm_atomic_state_alloc(dev);
10337 if (!state)
10338 return false;
10339
10340 state->acquire_ctx = ctx;
10341
10342 connector_state = drm_atomic_get_connector_state(state, connector);
10343 if (IS_ERR(connector_state)) {
10344 ret = PTR_ERR(connector_state);
10345 goto fail;
10346 }
10347
10348 connector_state->crtc = crtc;
10349 connector_state->best_encoder = &intel_encoder->base;
10350
10351 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10352 if (IS_ERR(crtc_state)) {
10353 ret = PTR_ERR(crtc_state);
10354 goto fail;
10355 }
10356
10357 crtc_state->base.active = crtc_state->base.enable = true;
10358
10359 if (!mode)
10360 mode = &load_detect_mode;
10361
10362 /* We need a framebuffer large enough to accommodate all accesses
10363 * that the plane may generate whilst we perform load detection.
10364 * We can not rely on the fbcon either being present (we get called
10365 * during its initialisation to detect all boot displays, or it may
10366 * not even exist) or that it is large enough to satisfy the
10367 * requested mode.
10368 */
10369 fb = mode_fits_in_fbdev(dev, mode);
10370 if (fb == NULL) {
10371 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10372 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10373 old->release_fb = fb;
10374 } else
10375 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10376 if (IS_ERR(fb)) {
10377 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10378 goto fail;
10379 }
10380
10381 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10382 if (ret)
10383 goto fail;
10384
10385 drm_mode_copy(&crtc_state->base.mode, mode);
10386
10387 if (drm_atomic_commit(state)) {
10388 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10389 if (old->release_fb)
10390 old->release_fb->funcs->destroy(old->release_fb);
10391 goto fail;
10392 }
10393 crtc->primary->crtc = crtc;
10394
10395 /* let the connector get through one full cycle before testing */
10396 intel_wait_for_vblank(dev, intel_crtc->pipe);
10397 return true;
10398
10399 fail:
10400 drm_atomic_state_free(state);
10401 state = NULL;
10402
10403 if (ret == -EDEADLK) {
10404 drm_modeset_backoff(ctx);
10405 goto retry;
10406 }
10407
10408 return false;
10409 }
10410
10411 void intel_release_load_detect_pipe(struct drm_connector *connector,
10412 struct intel_load_detect_pipe *old,
10413 struct drm_modeset_acquire_ctx *ctx)
10414 {
10415 struct drm_device *dev = connector->dev;
10416 struct intel_encoder *intel_encoder =
10417 intel_attached_encoder(connector);
10418 struct drm_encoder *encoder = &intel_encoder->base;
10419 struct drm_crtc *crtc = encoder->crtc;
10420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10421 struct drm_atomic_state *state;
10422 struct drm_connector_state *connector_state;
10423 struct intel_crtc_state *crtc_state;
10424 int ret;
10425
10426 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10427 connector->base.id, connector->name,
10428 encoder->base.id, encoder->name);
10429
10430 if (old->load_detect_temp) {
10431 state = drm_atomic_state_alloc(dev);
10432 if (!state)
10433 goto fail;
10434
10435 state->acquire_ctx = ctx;
10436
10437 connector_state = drm_atomic_get_connector_state(state, connector);
10438 if (IS_ERR(connector_state))
10439 goto fail;
10440
10441 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10442 if (IS_ERR(crtc_state))
10443 goto fail;
10444
10445 connector_state->best_encoder = NULL;
10446 connector_state->crtc = NULL;
10447
10448 crtc_state->base.enable = crtc_state->base.active = false;
10449
10450 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10451 0, 0);
10452 if (ret)
10453 goto fail;
10454
10455 ret = drm_atomic_commit(state);
10456 if (ret)
10457 goto fail;
10458
10459 if (old->release_fb) {
10460 drm_framebuffer_unregister_private(old->release_fb);
10461 drm_framebuffer_unreference(old->release_fb);
10462 }
10463
10464 return;
10465 }
10466
10467 /* Switch crtc and encoder back off if necessary */
10468 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10469 connector->funcs->dpms(connector, old->dpms_mode);
10470
10471 return;
10472 fail:
10473 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10474 drm_atomic_state_free(state);
10475 }
10476
10477 static int i9xx_pll_refclk(struct drm_device *dev,
10478 const struct intel_crtc_state *pipe_config)
10479 {
10480 struct drm_i915_private *dev_priv = dev->dev_private;
10481 u32 dpll = pipe_config->dpll_hw_state.dpll;
10482
10483 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10484 return dev_priv->vbt.lvds_ssc_freq;
10485 else if (HAS_PCH_SPLIT(dev))
10486 return 120000;
10487 else if (!IS_GEN2(dev))
10488 return 96000;
10489 else
10490 return 48000;
10491 }
10492
10493 /* Returns the clock of the currently programmed mode of the given pipe. */
10494 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10495 struct intel_crtc_state *pipe_config)
10496 {
10497 struct drm_device *dev = crtc->base.dev;
10498 struct drm_i915_private *dev_priv = dev->dev_private;
10499 int pipe = pipe_config->cpu_transcoder;
10500 u32 dpll = pipe_config->dpll_hw_state.dpll;
10501 u32 fp;
10502 intel_clock_t clock;
10503 int port_clock;
10504 int refclk = i9xx_pll_refclk(dev, pipe_config);
10505
10506 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10507 fp = pipe_config->dpll_hw_state.fp0;
10508 else
10509 fp = pipe_config->dpll_hw_state.fp1;
10510
10511 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10512 if (IS_PINEVIEW(dev)) {
10513 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10514 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10515 } else {
10516 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10517 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10518 }
10519
10520 if (!IS_GEN2(dev)) {
10521 if (IS_PINEVIEW(dev))
10522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10523 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10524 else
10525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10526 DPLL_FPA01_P1_POST_DIV_SHIFT);
10527
10528 switch (dpll & DPLL_MODE_MASK) {
10529 case DPLLB_MODE_DAC_SERIAL:
10530 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10531 5 : 10;
10532 break;
10533 case DPLLB_MODE_LVDS:
10534 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10535 7 : 14;
10536 break;
10537 default:
10538 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10539 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10540 return;
10541 }
10542
10543 if (IS_PINEVIEW(dev))
10544 port_clock = pnv_calc_dpll_params(refclk, &clock);
10545 else
10546 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10547 } else {
10548 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10549 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10550
10551 if (is_lvds) {
10552 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10553 DPLL_FPA01_P1_POST_DIV_SHIFT);
10554
10555 if (lvds & LVDS_CLKB_POWER_UP)
10556 clock.p2 = 7;
10557 else
10558 clock.p2 = 14;
10559 } else {
10560 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10561 clock.p1 = 2;
10562 else {
10563 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10564 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10565 }
10566 if (dpll & PLL_P2_DIVIDE_BY_4)
10567 clock.p2 = 4;
10568 else
10569 clock.p2 = 2;
10570 }
10571
10572 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10573 }
10574
10575 /*
10576 * This value includes pixel_multiplier. We will use
10577 * port_clock to compute adjusted_mode.crtc_clock in the
10578 * encoder's get_config() function.
10579 */
10580 pipe_config->port_clock = port_clock;
10581 }
10582
10583 int intel_dotclock_calculate(int link_freq,
10584 const struct intel_link_m_n *m_n)
10585 {
10586 /*
10587 * The calculation for the data clock is:
10588 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10589 * But we want to avoid losing precison if possible, so:
10590 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10591 *
10592 * and the link clock is simpler:
10593 * link_clock = (m * link_clock) / n
10594 */
10595
10596 if (!m_n->link_n)
10597 return 0;
10598
10599 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10600 }
10601
10602 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10603 struct intel_crtc_state *pipe_config)
10604 {
10605 struct drm_device *dev = crtc->base.dev;
10606
10607 /* read out port_clock from the DPLL */
10608 i9xx_crtc_clock_get(crtc, pipe_config);
10609
10610 /*
10611 * This value does not include pixel_multiplier.
10612 * We will check that port_clock and adjusted_mode.crtc_clock
10613 * agree once we know their relationship in the encoder's
10614 * get_config() function.
10615 */
10616 pipe_config->base.adjusted_mode.crtc_clock =
10617 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10618 &pipe_config->fdi_m_n);
10619 }
10620
10621 /** Returns the currently programmed mode of the given pipe. */
10622 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10623 struct drm_crtc *crtc)
10624 {
10625 struct drm_i915_private *dev_priv = dev->dev_private;
10626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10627 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10628 struct drm_display_mode *mode;
10629 struct intel_crtc_state pipe_config;
10630 int htot = I915_READ(HTOTAL(cpu_transcoder));
10631 int hsync = I915_READ(HSYNC(cpu_transcoder));
10632 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10633 int vsync = I915_READ(VSYNC(cpu_transcoder));
10634 enum pipe pipe = intel_crtc->pipe;
10635
10636 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10637 if (!mode)
10638 return NULL;
10639
10640 /*
10641 * Construct a pipe_config sufficient for getting the clock info
10642 * back out of crtc_clock_get.
10643 *
10644 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10645 * to use a real value here instead.
10646 */
10647 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10648 pipe_config.pixel_multiplier = 1;
10649 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10650 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10651 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10652 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10653
10654 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10655 mode->hdisplay = (htot & 0xffff) + 1;
10656 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10657 mode->hsync_start = (hsync & 0xffff) + 1;
10658 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10659 mode->vdisplay = (vtot & 0xffff) + 1;
10660 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10661 mode->vsync_start = (vsync & 0xffff) + 1;
10662 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10663
10664 drm_mode_set_name(mode);
10665
10666 return mode;
10667 }
10668
10669 void intel_mark_busy(struct drm_device *dev)
10670 {
10671 struct drm_i915_private *dev_priv = dev->dev_private;
10672
10673 if (dev_priv->mm.busy)
10674 return;
10675
10676 intel_runtime_pm_get(dev_priv);
10677 i915_update_gfx_val(dev_priv);
10678 if (INTEL_INFO(dev)->gen >= 6)
10679 gen6_rps_busy(dev_priv);
10680 dev_priv->mm.busy = true;
10681 }
10682
10683 void intel_mark_idle(struct drm_device *dev)
10684 {
10685 struct drm_i915_private *dev_priv = dev->dev_private;
10686
10687 if (!dev_priv->mm.busy)
10688 return;
10689
10690 dev_priv->mm.busy = false;
10691
10692 if (INTEL_INFO(dev)->gen >= 6)
10693 gen6_rps_idle(dev->dev_private);
10694
10695 intel_runtime_pm_put(dev_priv);
10696 }
10697
10698 static void intel_crtc_destroy(struct drm_crtc *crtc)
10699 {
10700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10701 struct drm_device *dev = crtc->dev;
10702 struct intel_unpin_work *work;
10703
10704 spin_lock_irq(&dev->event_lock);
10705 work = intel_crtc->unpin_work;
10706 intel_crtc->unpin_work = NULL;
10707 spin_unlock_irq(&dev->event_lock);
10708
10709 if (work) {
10710 cancel_work_sync(&work->work);
10711 kfree(work);
10712 }
10713
10714 drm_crtc_cleanup(crtc);
10715
10716 kfree(intel_crtc);
10717 }
10718
10719 static void intel_unpin_work_fn(struct work_struct *__work)
10720 {
10721 struct intel_unpin_work *work =
10722 container_of(__work, struct intel_unpin_work, work);
10723 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10724 struct drm_device *dev = crtc->base.dev;
10725 struct drm_plane *primary = crtc->base.primary;
10726
10727 mutex_lock(&dev->struct_mutex);
10728 intel_unpin_fb_obj(work->old_fb, primary->state);
10729 drm_gem_object_unreference(&work->pending_flip_obj->base);
10730
10731 if (work->flip_queued_req)
10732 i915_gem_request_assign(&work->flip_queued_req, NULL);
10733 mutex_unlock(&dev->struct_mutex);
10734
10735 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10736 drm_framebuffer_unreference(work->old_fb);
10737
10738 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10739 atomic_dec(&crtc->unpin_work_count);
10740
10741 kfree(work);
10742 }
10743
10744 static void do_intel_finish_page_flip(struct drm_device *dev,
10745 struct drm_crtc *crtc)
10746 {
10747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10748 struct intel_unpin_work *work;
10749 unsigned long flags;
10750
10751 /* Ignore early vblank irqs */
10752 if (intel_crtc == NULL)
10753 return;
10754
10755 /*
10756 * This is called both by irq handlers and the reset code (to complete
10757 * lost pageflips) so needs the full irqsave spinlocks.
10758 */
10759 spin_lock_irqsave(&dev->event_lock, flags);
10760 work = intel_crtc->unpin_work;
10761
10762 /* Ensure we don't miss a work->pending update ... */
10763 smp_rmb();
10764
10765 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10766 spin_unlock_irqrestore(&dev->event_lock, flags);
10767 return;
10768 }
10769
10770 page_flip_completed(intel_crtc);
10771
10772 spin_unlock_irqrestore(&dev->event_lock, flags);
10773 }
10774
10775 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10776 {
10777 struct drm_i915_private *dev_priv = dev->dev_private;
10778 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10779
10780 do_intel_finish_page_flip(dev, crtc);
10781 }
10782
10783 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10784 {
10785 struct drm_i915_private *dev_priv = dev->dev_private;
10786 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10787
10788 do_intel_finish_page_flip(dev, crtc);
10789 }
10790
10791 /* Is 'a' after or equal to 'b'? */
10792 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10793 {
10794 return !((a - b) & 0x80000000);
10795 }
10796
10797 static bool page_flip_finished(struct intel_crtc *crtc)
10798 {
10799 struct drm_device *dev = crtc->base.dev;
10800 struct drm_i915_private *dev_priv = dev->dev_private;
10801
10802 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10803 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10804 return true;
10805
10806 /*
10807 * The relevant registers doen't exist on pre-ctg.
10808 * As the flip done interrupt doesn't trigger for mmio
10809 * flips on gmch platforms, a flip count check isn't
10810 * really needed there. But since ctg has the registers,
10811 * include it in the check anyway.
10812 */
10813 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10814 return true;
10815
10816 /*
10817 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10818 * used the same base address. In that case the mmio flip might
10819 * have completed, but the CS hasn't even executed the flip yet.
10820 *
10821 * A flip count check isn't enough as the CS might have updated
10822 * the base address just after start of vblank, but before we
10823 * managed to process the interrupt. This means we'd complete the
10824 * CS flip too soon.
10825 *
10826 * Combining both checks should get us a good enough result. It may
10827 * still happen that the CS flip has been executed, but has not
10828 * yet actually completed. But in case the base address is the same
10829 * anyway, we don't really care.
10830 */
10831 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10832 crtc->unpin_work->gtt_offset &&
10833 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10834 crtc->unpin_work->flip_count);
10835 }
10836
10837 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10838 {
10839 struct drm_i915_private *dev_priv = dev->dev_private;
10840 struct intel_crtc *intel_crtc =
10841 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10842 unsigned long flags;
10843
10844
10845 /*
10846 * This is called both by irq handlers and the reset code (to complete
10847 * lost pageflips) so needs the full irqsave spinlocks.
10848 *
10849 * NB: An MMIO update of the plane base pointer will also
10850 * generate a page-flip completion irq, i.e. every modeset
10851 * is also accompanied by a spurious intel_prepare_page_flip().
10852 */
10853 spin_lock_irqsave(&dev->event_lock, flags);
10854 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10855 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10856 spin_unlock_irqrestore(&dev->event_lock, flags);
10857 }
10858
10859 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10860 {
10861 /* Ensure that the work item is consistent when activating it ... */
10862 smp_wmb();
10863 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10864 /* and that it is marked active as soon as the irq could fire. */
10865 smp_wmb();
10866 }
10867
10868 static int intel_gen2_queue_flip(struct drm_device *dev,
10869 struct drm_crtc *crtc,
10870 struct drm_framebuffer *fb,
10871 struct drm_i915_gem_object *obj,
10872 struct drm_i915_gem_request *req,
10873 uint32_t flags)
10874 {
10875 struct intel_engine_cs *ring = req->ring;
10876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10877 u32 flip_mask;
10878 int ret;
10879
10880 ret = intel_ring_begin(req, 6);
10881 if (ret)
10882 return ret;
10883
10884 /* Can't queue multiple flips, so wait for the previous
10885 * one to finish before executing the next.
10886 */
10887 if (intel_crtc->plane)
10888 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10889 else
10890 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10891 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10892 intel_ring_emit(ring, MI_NOOP);
10893 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10894 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10895 intel_ring_emit(ring, fb->pitches[0]);
10896 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10897 intel_ring_emit(ring, 0); /* aux display base address, unused */
10898
10899 intel_mark_page_flip_active(intel_crtc);
10900 return 0;
10901 }
10902
10903 static int intel_gen3_queue_flip(struct drm_device *dev,
10904 struct drm_crtc *crtc,
10905 struct drm_framebuffer *fb,
10906 struct drm_i915_gem_object *obj,
10907 struct drm_i915_gem_request *req,
10908 uint32_t flags)
10909 {
10910 struct intel_engine_cs *ring = req->ring;
10911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10912 u32 flip_mask;
10913 int ret;
10914
10915 ret = intel_ring_begin(req, 6);
10916 if (ret)
10917 return ret;
10918
10919 if (intel_crtc->plane)
10920 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10921 else
10922 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10923 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10924 intel_ring_emit(ring, MI_NOOP);
10925 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10926 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10927 intel_ring_emit(ring, fb->pitches[0]);
10928 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10929 intel_ring_emit(ring, MI_NOOP);
10930
10931 intel_mark_page_flip_active(intel_crtc);
10932 return 0;
10933 }
10934
10935 static int intel_gen4_queue_flip(struct drm_device *dev,
10936 struct drm_crtc *crtc,
10937 struct drm_framebuffer *fb,
10938 struct drm_i915_gem_object *obj,
10939 struct drm_i915_gem_request *req,
10940 uint32_t flags)
10941 {
10942 struct intel_engine_cs *ring = req->ring;
10943 struct drm_i915_private *dev_priv = dev->dev_private;
10944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10945 uint32_t pf, pipesrc;
10946 int ret;
10947
10948 ret = intel_ring_begin(req, 4);
10949 if (ret)
10950 return ret;
10951
10952 /* i965+ uses the linear or tiled offsets from the
10953 * Display Registers (which do not change across a page-flip)
10954 * so we need only reprogram the base address.
10955 */
10956 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10957 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10958 intel_ring_emit(ring, fb->pitches[0]);
10959 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10960 obj->tiling_mode);
10961
10962 /* XXX Enabling the panel-fitter across page-flip is so far
10963 * untested on non-native modes, so ignore it for now.
10964 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10965 */
10966 pf = 0;
10967 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10968 intel_ring_emit(ring, pf | pipesrc);
10969
10970 intel_mark_page_flip_active(intel_crtc);
10971 return 0;
10972 }
10973
10974 static int intel_gen6_queue_flip(struct drm_device *dev,
10975 struct drm_crtc *crtc,
10976 struct drm_framebuffer *fb,
10977 struct drm_i915_gem_object *obj,
10978 struct drm_i915_gem_request *req,
10979 uint32_t flags)
10980 {
10981 struct intel_engine_cs *ring = req->ring;
10982 struct drm_i915_private *dev_priv = dev->dev_private;
10983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10984 uint32_t pf, pipesrc;
10985 int ret;
10986
10987 ret = intel_ring_begin(req, 4);
10988 if (ret)
10989 return ret;
10990
10991 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10992 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10993 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10994 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10995
10996 /* Contrary to the suggestions in the documentation,
10997 * "Enable Panel Fitter" does not seem to be required when page
10998 * flipping with a non-native mode, and worse causes a normal
10999 * modeset to fail.
11000 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11001 */
11002 pf = 0;
11003 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11004 intel_ring_emit(ring, pf | pipesrc);
11005
11006 intel_mark_page_flip_active(intel_crtc);
11007 return 0;
11008 }
11009
11010 static int intel_gen7_queue_flip(struct drm_device *dev,
11011 struct drm_crtc *crtc,
11012 struct drm_framebuffer *fb,
11013 struct drm_i915_gem_object *obj,
11014 struct drm_i915_gem_request *req,
11015 uint32_t flags)
11016 {
11017 struct intel_engine_cs *ring = req->ring;
11018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11019 uint32_t plane_bit = 0;
11020 int len, ret;
11021
11022 switch (intel_crtc->plane) {
11023 case PLANE_A:
11024 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11025 break;
11026 case PLANE_B:
11027 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11028 break;
11029 case PLANE_C:
11030 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11031 break;
11032 default:
11033 WARN_ONCE(1, "unknown plane in flip command\n");
11034 return -ENODEV;
11035 }
11036
11037 len = 4;
11038 if (ring->id == RCS) {
11039 len += 6;
11040 /*
11041 * On Gen 8, SRM is now taking an extra dword to accommodate
11042 * 48bits addresses, and we need a NOOP for the batch size to
11043 * stay even.
11044 */
11045 if (IS_GEN8(dev))
11046 len += 2;
11047 }
11048
11049 /*
11050 * BSpec MI_DISPLAY_FLIP for IVB:
11051 * "The full packet must be contained within the same cache line."
11052 *
11053 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11054 * cacheline, if we ever start emitting more commands before
11055 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11056 * then do the cacheline alignment, and finally emit the
11057 * MI_DISPLAY_FLIP.
11058 */
11059 ret = intel_ring_cacheline_align(req);
11060 if (ret)
11061 return ret;
11062
11063 ret = intel_ring_begin(req, len);
11064 if (ret)
11065 return ret;
11066
11067 /* Unmask the flip-done completion message. Note that the bspec says that
11068 * we should do this for both the BCS and RCS, and that we must not unmask
11069 * more than one flip event at any time (or ensure that one flip message
11070 * can be sent by waiting for flip-done prior to queueing new flips).
11071 * Experimentation says that BCS works despite DERRMR masking all
11072 * flip-done completion events and that unmasking all planes at once
11073 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11074 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11075 */
11076 if (ring->id == RCS) {
11077 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11078 intel_ring_emit(ring, DERRMR);
11079 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11080 DERRMR_PIPEB_PRI_FLIP_DONE |
11081 DERRMR_PIPEC_PRI_FLIP_DONE));
11082 if (IS_GEN8(dev))
11083 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11084 MI_SRM_LRM_GLOBAL_GTT);
11085 else
11086 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11087 MI_SRM_LRM_GLOBAL_GTT);
11088 intel_ring_emit(ring, DERRMR);
11089 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11090 if (IS_GEN8(dev)) {
11091 intel_ring_emit(ring, 0);
11092 intel_ring_emit(ring, MI_NOOP);
11093 }
11094 }
11095
11096 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11097 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11098 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11099 intel_ring_emit(ring, (MI_NOOP));
11100
11101 intel_mark_page_flip_active(intel_crtc);
11102 return 0;
11103 }
11104
11105 static bool use_mmio_flip(struct intel_engine_cs *ring,
11106 struct drm_i915_gem_object *obj)
11107 {
11108 /*
11109 * This is not being used for older platforms, because
11110 * non-availability of flip done interrupt forces us to use
11111 * CS flips. Older platforms derive flip done using some clever
11112 * tricks involving the flip_pending status bits and vblank irqs.
11113 * So using MMIO flips there would disrupt this mechanism.
11114 */
11115
11116 if (ring == NULL)
11117 return true;
11118
11119 if (INTEL_INFO(ring->dev)->gen < 5)
11120 return false;
11121
11122 if (i915.use_mmio_flip < 0)
11123 return false;
11124 else if (i915.use_mmio_flip > 0)
11125 return true;
11126 else if (i915.enable_execlists)
11127 return true;
11128 else
11129 return ring != i915_gem_request_get_ring(obj->last_write_req);
11130 }
11131
11132 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11133 {
11134 struct drm_device *dev = intel_crtc->base.dev;
11135 struct drm_i915_private *dev_priv = dev->dev_private;
11136 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11137 const enum pipe pipe = intel_crtc->pipe;
11138 u32 ctl, stride;
11139
11140 ctl = I915_READ(PLANE_CTL(pipe, 0));
11141 ctl &= ~PLANE_CTL_TILED_MASK;
11142 switch (fb->modifier[0]) {
11143 case DRM_FORMAT_MOD_NONE:
11144 break;
11145 case I915_FORMAT_MOD_X_TILED:
11146 ctl |= PLANE_CTL_TILED_X;
11147 break;
11148 case I915_FORMAT_MOD_Y_TILED:
11149 ctl |= PLANE_CTL_TILED_Y;
11150 break;
11151 case I915_FORMAT_MOD_Yf_TILED:
11152 ctl |= PLANE_CTL_TILED_YF;
11153 break;
11154 default:
11155 MISSING_CASE(fb->modifier[0]);
11156 }
11157
11158 /*
11159 * The stride is either expressed as a multiple of 64 bytes chunks for
11160 * linear buffers or in number of tiles for tiled buffers.
11161 */
11162 stride = fb->pitches[0] /
11163 intel_fb_stride_alignment(dev, fb->modifier[0],
11164 fb->pixel_format);
11165
11166 /*
11167 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11168 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11169 */
11170 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11171 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11172
11173 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11174 POSTING_READ(PLANE_SURF(pipe, 0));
11175 }
11176
11177 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11178 {
11179 struct drm_device *dev = intel_crtc->base.dev;
11180 struct drm_i915_private *dev_priv = dev->dev_private;
11181 struct intel_framebuffer *intel_fb =
11182 to_intel_framebuffer(intel_crtc->base.primary->fb);
11183 struct drm_i915_gem_object *obj = intel_fb->obj;
11184 u32 dspcntr;
11185 u32 reg;
11186
11187 reg = DSPCNTR(intel_crtc->plane);
11188 dspcntr = I915_READ(reg);
11189
11190 if (obj->tiling_mode != I915_TILING_NONE)
11191 dspcntr |= DISPPLANE_TILED;
11192 else
11193 dspcntr &= ~DISPPLANE_TILED;
11194
11195 I915_WRITE(reg, dspcntr);
11196
11197 I915_WRITE(DSPSURF(intel_crtc->plane),
11198 intel_crtc->unpin_work->gtt_offset);
11199 POSTING_READ(DSPSURF(intel_crtc->plane));
11200
11201 }
11202
11203 /*
11204 * XXX: This is the temporary way to update the plane registers until we get
11205 * around to using the usual plane update functions for MMIO flips
11206 */
11207 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11208 {
11209 struct drm_device *dev = intel_crtc->base.dev;
11210
11211 intel_mark_page_flip_active(intel_crtc);
11212
11213 intel_pipe_update_start(intel_crtc);
11214
11215 if (INTEL_INFO(dev)->gen >= 9)
11216 skl_do_mmio_flip(intel_crtc);
11217 else
11218 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11219 ilk_do_mmio_flip(intel_crtc);
11220
11221 intel_pipe_update_end(intel_crtc);
11222 }
11223
11224 static void intel_mmio_flip_work_func(struct work_struct *work)
11225 {
11226 struct intel_mmio_flip *mmio_flip =
11227 container_of(work, struct intel_mmio_flip, work);
11228
11229 if (mmio_flip->req)
11230 WARN_ON(__i915_wait_request(mmio_flip->req,
11231 mmio_flip->crtc->reset_counter,
11232 false, NULL,
11233 &mmio_flip->i915->rps.mmioflips));
11234
11235 intel_do_mmio_flip(mmio_flip->crtc);
11236
11237 i915_gem_request_unreference__unlocked(mmio_flip->req);
11238 kfree(mmio_flip);
11239 }
11240
11241 static int intel_queue_mmio_flip(struct drm_device *dev,
11242 struct drm_crtc *crtc,
11243 struct drm_framebuffer *fb,
11244 struct drm_i915_gem_object *obj,
11245 struct intel_engine_cs *ring,
11246 uint32_t flags)
11247 {
11248 struct intel_mmio_flip *mmio_flip;
11249
11250 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11251 if (mmio_flip == NULL)
11252 return -ENOMEM;
11253
11254 mmio_flip->i915 = to_i915(dev);
11255 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11256 mmio_flip->crtc = to_intel_crtc(crtc);
11257
11258 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11259 schedule_work(&mmio_flip->work);
11260
11261 return 0;
11262 }
11263
11264 static int intel_default_queue_flip(struct drm_device *dev,
11265 struct drm_crtc *crtc,
11266 struct drm_framebuffer *fb,
11267 struct drm_i915_gem_object *obj,
11268 struct drm_i915_gem_request *req,
11269 uint32_t flags)
11270 {
11271 return -ENODEV;
11272 }
11273
11274 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11275 struct drm_crtc *crtc)
11276 {
11277 struct drm_i915_private *dev_priv = dev->dev_private;
11278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11279 struct intel_unpin_work *work = intel_crtc->unpin_work;
11280 u32 addr;
11281
11282 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11283 return true;
11284
11285 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11286 return false;
11287
11288 if (!work->enable_stall_check)
11289 return false;
11290
11291 if (work->flip_ready_vblank == 0) {
11292 if (work->flip_queued_req &&
11293 !i915_gem_request_completed(work->flip_queued_req, true))
11294 return false;
11295
11296 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11297 }
11298
11299 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11300 return false;
11301
11302 /* Potential stall - if we see that the flip has happened,
11303 * assume a missed interrupt. */
11304 if (INTEL_INFO(dev)->gen >= 4)
11305 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11306 else
11307 addr = I915_READ(DSPADDR(intel_crtc->plane));
11308
11309 /* There is a potential issue here with a false positive after a flip
11310 * to the same address. We could address this by checking for a
11311 * non-incrementing frame counter.
11312 */
11313 return addr == work->gtt_offset;
11314 }
11315
11316 void intel_check_page_flip(struct drm_device *dev, int pipe)
11317 {
11318 struct drm_i915_private *dev_priv = dev->dev_private;
11319 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11321 struct intel_unpin_work *work;
11322
11323 WARN_ON(!in_interrupt());
11324
11325 if (crtc == NULL)
11326 return;
11327
11328 spin_lock(&dev->event_lock);
11329 work = intel_crtc->unpin_work;
11330 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11331 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11332 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11333 page_flip_completed(intel_crtc);
11334 work = NULL;
11335 }
11336 if (work != NULL &&
11337 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11338 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11339 spin_unlock(&dev->event_lock);
11340 }
11341
11342 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11343 struct drm_framebuffer *fb,
11344 struct drm_pending_vblank_event *event,
11345 uint32_t page_flip_flags)
11346 {
11347 struct drm_device *dev = crtc->dev;
11348 struct drm_i915_private *dev_priv = dev->dev_private;
11349 struct drm_framebuffer *old_fb = crtc->primary->fb;
11350 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11352 struct drm_plane *primary = crtc->primary;
11353 enum pipe pipe = intel_crtc->pipe;
11354 struct intel_unpin_work *work;
11355 struct intel_engine_cs *ring;
11356 bool mmio_flip;
11357 struct drm_i915_gem_request *request = NULL;
11358 int ret;
11359
11360 /*
11361 * drm_mode_page_flip_ioctl() should already catch this, but double
11362 * check to be safe. In the future we may enable pageflipping from
11363 * a disabled primary plane.
11364 */
11365 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11366 return -EBUSY;
11367
11368 /* Can't change pixel format via MI display flips. */
11369 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11370 return -EINVAL;
11371
11372 /*
11373 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11374 * Note that pitch changes could also affect these register.
11375 */
11376 if (INTEL_INFO(dev)->gen > 3 &&
11377 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11378 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11379 return -EINVAL;
11380
11381 if (i915_terminally_wedged(&dev_priv->gpu_error))
11382 goto out_hang;
11383
11384 work = kzalloc(sizeof(*work), GFP_KERNEL);
11385 if (work == NULL)
11386 return -ENOMEM;
11387
11388 work->event = event;
11389 work->crtc = crtc;
11390 work->old_fb = old_fb;
11391 INIT_WORK(&work->work, intel_unpin_work_fn);
11392
11393 ret = drm_crtc_vblank_get(crtc);
11394 if (ret)
11395 goto free_work;
11396
11397 /* We borrow the event spin lock for protecting unpin_work */
11398 spin_lock_irq(&dev->event_lock);
11399 if (intel_crtc->unpin_work) {
11400 /* Before declaring the flip queue wedged, check if
11401 * the hardware completed the operation behind our backs.
11402 */
11403 if (__intel_pageflip_stall_check(dev, crtc)) {
11404 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11405 page_flip_completed(intel_crtc);
11406 } else {
11407 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11408 spin_unlock_irq(&dev->event_lock);
11409
11410 drm_crtc_vblank_put(crtc);
11411 kfree(work);
11412 return -EBUSY;
11413 }
11414 }
11415 intel_crtc->unpin_work = work;
11416 spin_unlock_irq(&dev->event_lock);
11417
11418 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11419 flush_workqueue(dev_priv->wq);
11420
11421 /* Reference the objects for the scheduled work. */
11422 drm_framebuffer_reference(work->old_fb);
11423 drm_gem_object_reference(&obj->base);
11424
11425 crtc->primary->fb = fb;
11426 update_state_fb(crtc->primary);
11427
11428 work->pending_flip_obj = obj;
11429
11430 ret = i915_mutex_lock_interruptible(dev);
11431 if (ret)
11432 goto cleanup;
11433
11434 atomic_inc(&intel_crtc->unpin_work_count);
11435 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11436
11437 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11438 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11439
11440 if (IS_VALLEYVIEW(dev)) {
11441 ring = &dev_priv->ring[BCS];
11442 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11443 /* vlv: DISPLAY_FLIP fails to change tiling */
11444 ring = NULL;
11445 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11446 ring = &dev_priv->ring[BCS];
11447 } else if (INTEL_INFO(dev)->gen >= 7) {
11448 ring = i915_gem_request_get_ring(obj->last_write_req);
11449 if (ring == NULL || ring->id != RCS)
11450 ring = &dev_priv->ring[BCS];
11451 } else {
11452 ring = &dev_priv->ring[RCS];
11453 }
11454
11455 mmio_flip = use_mmio_flip(ring, obj);
11456
11457 /* When using CS flips, we want to emit semaphores between rings.
11458 * However, when using mmio flips we will create a task to do the
11459 * synchronisation, so all we want here is to pin the framebuffer
11460 * into the display plane and skip any waits.
11461 */
11462 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11463 crtc->primary->state,
11464 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11465 if (ret)
11466 goto cleanup_pending;
11467
11468 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11469 obj, 0);
11470 work->gtt_offset += intel_crtc->dspaddr_offset;
11471
11472 if (mmio_flip) {
11473 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11474 page_flip_flags);
11475 if (ret)
11476 goto cleanup_unpin;
11477
11478 i915_gem_request_assign(&work->flip_queued_req,
11479 obj->last_write_req);
11480 } else {
11481 if (!request) {
11482 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11483 if (ret)
11484 goto cleanup_unpin;
11485 }
11486
11487 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11488 page_flip_flags);
11489 if (ret)
11490 goto cleanup_unpin;
11491
11492 i915_gem_request_assign(&work->flip_queued_req, request);
11493 }
11494
11495 if (request)
11496 i915_add_request_no_flush(request);
11497
11498 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11499 work->enable_stall_check = true;
11500
11501 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11502 to_intel_plane(primary)->frontbuffer_bit);
11503 mutex_unlock(&dev->struct_mutex);
11504
11505 intel_fbc_disable_crtc(intel_crtc);
11506 intel_frontbuffer_flip_prepare(dev,
11507 to_intel_plane(primary)->frontbuffer_bit);
11508
11509 trace_i915_flip_request(intel_crtc->plane, obj);
11510
11511 return 0;
11512
11513 cleanup_unpin:
11514 intel_unpin_fb_obj(fb, crtc->primary->state);
11515 cleanup_pending:
11516 if (request)
11517 i915_gem_request_cancel(request);
11518 atomic_dec(&intel_crtc->unpin_work_count);
11519 mutex_unlock(&dev->struct_mutex);
11520 cleanup:
11521 crtc->primary->fb = old_fb;
11522 update_state_fb(crtc->primary);
11523
11524 drm_gem_object_unreference_unlocked(&obj->base);
11525 drm_framebuffer_unreference(work->old_fb);
11526
11527 spin_lock_irq(&dev->event_lock);
11528 intel_crtc->unpin_work = NULL;
11529 spin_unlock_irq(&dev->event_lock);
11530
11531 drm_crtc_vblank_put(crtc);
11532 free_work:
11533 kfree(work);
11534
11535 if (ret == -EIO) {
11536 struct drm_atomic_state *state;
11537 struct drm_plane_state *plane_state;
11538
11539 out_hang:
11540 state = drm_atomic_state_alloc(dev);
11541 if (!state)
11542 return -ENOMEM;
11543 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11544
11545 retry:
11546 plane_state = drm_atomic_get_plane_state(state, primary);
11547 ret = PTR_ERR_OR_ZERO(plane_state);
11548 if (!ret) {
11549 drm_atomic_set_fb_for_plane(plane_state, fb);
11550
11551 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11552 if (!ret)
11553 ret = drm_atomic_commit(state);
11554 }
11555
11556 if (ret == -EDEADLK) {
11557 drm_modeset_backoff(state->acquire_ctx);
11558 drm_atomic_state_clear(state);
11559 goto retry;
11560 }
11561
11562 if (ret)
11563 drm_atomic_state_free(state);
11564
11565 if (ret == 0 && event) {
11566 spin_lock_irq(&dev->event_lock);
11567 drm_send_vblank_event(dev, pipe, event);
11568 spin_unlock_irq(&dev->event_lock);
11569 }
11570 }
11571 return ret;
11572 }
11573
11574
11575 /**
11576 * intel_wm_need_update - Check whether watermarks need updating
11577 * @plane: drm plane
11578 * @state: new plane state
11579 *
11580 * Check current plane state versus the new one to determine whether
11581 * watermarks need to be recalculated.
11582 *
11583 * Returns true or false.
11584 */
11585 static bool intel_wm_need_update(struct drm_plane *plane,
11586 struct drm_plane_state *state)
11587 {
11588 struct intel_plane_state *new = to_intel_plane_state(state);
11589 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11590
11591 /* Update watermarks on tiling or size changes. */
11592 if (!plane->state->fb || !state->fb ||
11593 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11594 plane->state->rotation != state->rotation ||
11595 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11596 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11597 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11598 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11599 return true;
11600
11601 return false;
11602 }
11603
11604 static bool needs_scaling(struct intel_plane_state *state)
11605 {
11606 int src_w = drm_rect_width(&state->src) >> 16;
11607 int src_h = drm_rect_height(&state->src) >> 16;
11608 int dst_w = drm_rect_width(&state->dst);
11609 int dst_h = drm_rect_height(&state->dst);
11610
11611 return (src_w != dst_w || src_h != dst_h);
11612 }
11613
11614 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11615 struct drm_plane_state *plane_state)
11616 {
11617 struct drm_crtc *crtc = crtc_state->crtc;
11618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11619 struct drm_plane *plane = plane_state->plane;
11620 struct drm_device *dev = crtc->dev;
11621 struct drm_i915_private *dev_priv = dev->dev_private;
11622 struct intel_plane_state *old_plane_state =
11623 to_intel_plane_state(plane->state);
11624 int idx = intel_crtc->base.base.id, ret;
11625 int i = drm_plane_index(plane);
11626 bool mode_changed = needs_modeset(crtc_state);
11627 bool was_crtc_enabled = crtc->state->active;
11628 bool is_crtc_enabled = crtc_state->active;
11629 bool turn_off, turn_on, visible, was_visible;
11630 struct drm_framebuffer *fb = plane_state->fb;
11631
11632 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11633 plane->type != DRM_PLANE_TYPE_CURSOR) {
11634 ret = skl_update_scaler_plane(
11635 to_intel_crtc_state(crtc_state),
11636 to_intel_plane_state(plane_state));
11637 if (ret)
11638 return ret;
11639 }
11640
11641 /*
11642 * Disabling a plane is always okay; we just need to update
11643 * fb tracking in a special way since cleanup_fb() won't
11644 * get called by the plane helpers.
11645 */
11646 if (old_plane_state->base.fb && !fb)
11647 intel_crtc->atomic.disabled_planes |= 1 << i;
11648
11649 was_visible = old_plane_state->visible;
11650 visible = to_intel_plane_state(plane_state)->visible;
11651
11652 if (!was_crtc_enabled && WARN_ON(was_visible))
11653 was_visible = false;
11654
11655 if (!is_crtc_enabled && WARN_ON(visible))
11656 visible = false;
11657
11658 if (!was_visible && !visible)
11659 return 0;
11660
11661 turn_off = was_visible && (!visible || mode_changed);
11662 turn_on = visible && (!was_visible || mode_changed);
11663
11664 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11665 plane->base.id, fb ? fb->base.id : -1);
11666
11667 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11668 plane->base.id, was_visible, visible,
11669 turn_off, turn_on, mode_changed);
11670
11671 if (turn_on) {
11672 intel_crtc->atomic.update_wm_pre = true;
11673 /* must disable cxsr around plane enable/disable */
11674 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11675 intel_crtc->atomic.disable_cxsr = true;
11676 /* to potentially re-enable cxsr */
11677 intel_crtc->atomic.wait_vblank = true;
11678 intel_crtc->atomic.update_wm_post = true;
11679 }
11680 } else if (turn_off) {
11681 intel_crtc->atomic.update_wm_post = true;
11682 /* must disable cxsr around plane enable/disable */
11683 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11684 if (is_crtc_enabled)
11685 intel_crtc->atomic.wait_vblank = true;
11686 intel_crtc->atomic.disable_cxsr = true;
11687 }
11688 } else if (intel_wm_need_update(plane, plane_state)) {
11689 intel_crtc->atomic.update_wm_pre = true;
11690 }
11691
11692 if (visible || was_visible)
11693 intel_crtc->atomic.fb_bits |=
11694 to_intel_plane(plane)->frontbuffer_bit;
11695
11696 switch (plane->type) {
11697 case DRM_PLANE_TYPE_PRIMARY:
11698 intel_crtc->atomic.wait_for_flips = true;
11699 intel_crtc->atomic.pre_disable_primary = turn_off;
11700 intel_crtc->atomic.post_enable_primary = turn_on;
11701
11702 if (turn_off) {
11703 /*
11704 * FIXME: Actually if we will still have any other
11705 * plane enabled on the pipe we could let IPS enabled
11706 * still, but for now lets consider that when we make
11707 * primary invisible by setting DSPCNTR to 0 on
11708 * update_primary_plane function IPS needs to be
11709 * disable.
11710 */
11711 intel_crtc->atomic.disable_ips = true;
11712
11713 intel_crtc->atomic.disable_fbc = true;
11714 }
11715
11716 /*
11717 * FBC does not work on some platforms for rotated
11718 * planes, so disable it when rotation is not 0 and
11719 * update it when rotation is set back to 0.
11720 *
11721 * FIXME: This is redundant with the fbc update done in
11722 * the primary plane enable function except that that
11723 * one is done too late. We eventually need to unify
11724 * this.
11725 */
11726
11727 if (visible &&
11728 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11729 dev_priv->fbc.crtc == intel_crtc &&
11730 plane_state->rotation != BIT(DRM_ROTATE_0))
11731 intel_crtc->atomic.disable_fbc = true;
11732
11733 /*
11734 * BDW signals flip done immediately if the plane
11735 * is disabled, even if the plane enable is already
11736 * armed to occur at the next vblank :(
11737 */
11738 if (turn_on && IS_BROADWELL(dev))
11739 intel_crtc->atomic.wait_vblank = true;
11740
11741 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11742 break;
11743 case DRM_PLANE_TYPE_CURSOR:
11744 break;
11745 case DRM_PLANE_TYPE_OVERLAY:
11746 /*
11747 * WaCxSRDisabledForSpriteScaling:ivb
11748 *
11749 * cstate->update_wm was already set above, so this flag will
11750 * take effect when we commit and program watermarks.
11751 */
11752 if (IS_IVYBRIDGE(dev) &&
11753 needs_scaling(to_intel_plane_state(plane_state)) &&
11754 !needs_scaling(old_plane_state)) {
11755 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11756 } else if (turn_off && !mode_changed) {
11757 intel_crtc->atomic.wait_vblank = true;
11758 intel_crtc->atomic.update_sprite_watermarks |=
11759 1 << i;
11760 }
11761
11762 break;
11763 }
11764 return 0;
11765 }
11766
11767 static bool encoders_cloneable(const struct intel_encoder *a,
11768 const struct intel_encoder *b)
11769 {
11770 /* masks could be asymmetric, so check both ways */
11771 return a == b || (a->cloneable & (1 << b->type) &&
11772 b->cloneable & (1 << a->type));
11773 }
11774
11775 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11776 struct intel_crtc *crtc,
11777 struct intel_encoder *encoder)
11778 {
11779 struct intel_encoder *source_encoder;
11780 struct drm_connector *connector;
11781 struct drm_connector_state *connector_state;
11782 int i;
11783
11784 for_each_connector_in_state(state, connector, connector_state, i) {
11785 if (connector_state->crtc != &crtc->base)
11786 continue;
11787
11788 source_encoder =
11789 to_intel_encoder(connector_state->best_encoder);
11790 if (!encoders_cloneable(encoder, source_encoder))
11791 return false;
11792 }
11793
11794 return true;
11795 }
11796
11797 static bool check_encoder_cloning(struct drm_atomic_state *state,
11798 struct intel_crtc *crtc)
11799 {
11800 struct intel_encoder *encoder;
11801 struct drm_connector *connector;
11802 struct drm_connector_state *connector_state;
11803 int i;
11804
11805 for_each_connector_in_state(state, connector, connector_state, i) {
11806 if (connector_state->crtc != &crtc->base)
11807 continue;
11808
11809 encoder = to_intel_encoder(connector_state->best_encoder);
11810 if (!check_single_encoder_cloning(state, crtc, encoder))
11811 return false;
11812 }
11813
11814 return true;
11815 }
11816
11817 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11818 struct drm_crtc_state *crtc_state)
11819 {
11820 struct drm_device *dev = crtc->dev;
11821 struct drm_i915_private *dev_priv = dev->dev_private;
11822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11823 struct intel_crtc_state *pipe_config =
11824 to_intel_crtc_state(crtc_state);
11825 struct drm_atomic_state *state = crtc_state->state;
11826 int ret;
11827 bool mode_changed = needs_modeset(crtc_state);
11828
11829 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11830 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11831 return -EINVAL;
11832 }
11833
11834 if (mode_changed && !crtc_state->active)
11835 intel_crtc->atomic.update_wm_post = true;
11836
11837 if (mode_changed && crtc_state->enable &&
11838 dev_priv->display.crtc_compute_clock &&
11839 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11840 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11841 pipe_config);
11842 if (ret)
11843 return ret;
11844 }
11845
11846 ret = 0;
11847 if (dev_priv->display.compute_pipe_wm) {
11848 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11849 if (ret)
11850 return ret;
11851 }
11852
11853 if (INTEL_INFO(dev)->gen >= 9) {
11854 if (mode_changed)
11855 ret = skl_update_scaler_crtc(pipe_config);
11856
11857 if (!ret)
11858 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11859 pipe_config);
11860 }
11861
11862 return ret;
11863 }
11864
11865 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11866 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11867 .load_lut = intel_crtc_load_lut,
11868 .atomic_begin = intel_begin_crtc_commit,
11869 .atomic_flush = intel_finish_crtc_commit,
11870 .atomic_check = intel_crtc_atomic_check,
11871 };
11872
11873 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11874 {
11875 struct intel_connector *connector;
11876
11877 for_each_intel_connector(dev, connector) {
11878 if (connector->base.encoder) {
11879 connector->base.state->best_encoder =
11880 connector->base.encoder;
11881 connector->base.state->crtc =
11882 connector->base.encoder->crtc;
11883 } else {
11884 connector->base.state->best_encoder = NULL;
11885 connector->base.state->crtc = NULL;
11886 }
11887 }
11888 }
11889
11890 static void
11891 connected_sink_compute_bpp(struct intel_connector *connector,
11892 struct intel_crtc_state *pipe_config)
11893 {
11894 int bpp = pipe_config->pipe_bpp;
11895
11896 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11897 connector->base.base.id,
11898 connector->base.name);
11899
11900 /* Don't use an invalid EDID bpc value */
11901 if (connector->base.display_info.bpc &&
11902 connector->base.display_info.bpc * 3 < bpp) {
11903 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11904 bpp, connector->base.display_info.bpc*3);
11905 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11906 }
11907
11908 /* Clamp bpp to 8 on screens without EDID 1.4 */
11909 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11910 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11911 bpp);
11912 pipe_config->pipe_bpp = 24;
11913 }
11914 }
11915
11916 static int
11917 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11918 struct intel_crtc_state *pipe_config)
11919 {
11920 struct drm_device *dev = crtc->base.dev;
11921 struct drm_atomic_state *state;
11922 struct drm_connector *connector;
11923 struct drm_connector_state *connector_state;
11924 int bpp, i;
11925
11926 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11927 bpp = 10*3;
11928 else if (INTEL_INFO(dev)->gen >= 5)
11929 bpp = 12*3;
11930 else
11931 bpp = 8*3;
11932
11933
11934 pipe_config->pipe_bpp = bpp;
11935
11936 state = pipe_config->base.state;
11937
11938 /* Clamp display bpp to EDID value */
11939 for_each_connector_in_state(state, connector, connector_state, i) {
11940 if (connector_state->crtc != &crtc->base)
11941 continue;
11942
11943 connected_sink_compute_bpp(to_intel_connector(connector),
11944 pipe_config);
11945 }
11946
11947 return bpp;
11948 }
11949
11950 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11951 {
11952 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11953 "type: 0x%x flags: 0x%x\n",
11954 mode->crtc_clock,
11955 mode->crtc_hdisplay, mode->crtc_hsync_start,
11956 mode->crtc_hsync_end, mode->crtc_htotal,
11957 mode->crtc_vdisplay, mode->crtc_vsync_start,
11958 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11959 }
11960
11961 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11962 struct intel_crtc_state *pipe_config,
11963 const char *context)
11964 {
11965 struct drm_device *dev = crtc->base.dev;
11966 struct drm_plane *plane;
11967 struct intel_plane *intel_plane;
11968 struct intel_plane_state *state;
11969 struct drm_framebuffer *fb;
11970
11971 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11972 context, pipe_config, pipe_name(crtc->pipe));
11973
11974 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11975 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11976 pipe_config->pipe_bpp, pipe_config->dither);
11977 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11978 pipe_config->has_pch_encoder,
11979 pipe_config->fdi_lanes,
11980 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11981 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11982 pipe_config->fdi_m_n.tu);
11983 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11984 pipe_config->has_dp_encoder,
11985 pipe_config->lane_count,
11986 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11987 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11988 pipe_config->dp_m_n.tu);
11989
11990 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11991 pipe_config->has_dp_encoder,
11992 pipe_config->lane_count,
11993 pipe_config->dp_m2_n2.gmch_m,
11994 pipe_config->dp_m2_n2.gmch_n,
11995 pipe_config->dp_m2_n2.link_m,
11996 pipe_config->dp_m2_n2.link_n,
11997 pipe_config->dp_m2_n2.tu);
11998
11999 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12000 pipe_config->has_audio,
12001 pipe_config->has_infoframe);
12002
12003 DRM_DEBUG_KMS("requested mode:\n");
12004 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12005 DRM_DEBUG_KMS("adjusted mode:\n");
12006 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12007 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12008 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12009 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12010 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12011 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12012 crtc->num_scalers,
12013 pipe_config->scaler_state.scaler_users,
12014 pipe_config->scaler_state.scaler_id);
12015 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12016 pipe_config->gmch_pfit.control,
12017 pipe_config->gmch_pfit.pgm_ratios,
12018 pipe_config->gmch_pfit.lvds_border_bits);
12019 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12020 pipe_config->pch_pfit.pos,
12021 pipe_config->pch_pfit.size,
12022 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12023 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12024 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12025
12026 if (IS_BROXTON(dev)) {
12027 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12028 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12029 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12030 pipe_config->ddi_pll_sel,
12031 pipe_config->dpll_hw_state.ebb0,
12032 pipe_config->dpll_hw_state.ebb4,
12033 pipe_config->dpll_hw_state.pll0,
12034 pipe_config->dpll_hw_state.pll1,
12035 pipe_config->dpll_hw_state.pll2,
12036 pipe_config->dpll_hw_state.pll3,
12037 pipe_config->dpll_hw_state.pll6,
12038 pipe_config->dpll_hw_state.pll8,
12039 pipe_config->dpll_hw_state.pll9,
12040 pipe_config->dpll_hw_state.pll10,
12041 pipe_config->dpll_hw_state.pcsdw12);
12042 } else if (IS_SKYLAKE(dev)) {
12043 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12044 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12045 pipe_config->ddi_pll_sel,
12046 pipe_config->dpll_hw_state.ctrl1,
12047 pipe_config->dpll_hw_state.cfgcr1,
12048 pipe_config->dpll_hw_state.cfgcr2);
12049 } else if (HAS_DDI(dev)) {
12050 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12051 pipe_config->ddi_pll_sel,
12052 pipe_config->dpll_hw_state.wrpll);
12053 } else {
12054 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12055 "fp0: 0x%x, fp1: 0x%x\n",
12056 pipe_config->dpll_hw_state.dpll,
12057 pipe_config->dpll_hw_state.dpll_md,
12058 pipe_config->dpll_hw_state.fp0,
12059 pipe_config->dpll_hw_state.fp1);
12060 }
12061
12062 DRM_DEBUG_KMS("planes on this crtc\n");
12063 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12064 intel_plane = to_intel_plane(plane);
12065 if (intel_plane->pipe != crtc->pipe)
12066 continue;
12067
12068 state = to_intel_plane_state(plane->state);
12069 fb = state->base.fb;
12070 if (!fb) {
12071 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12072 "disabled, scaler_id = %d\n",
12073 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12074 plane->base.id, intel_plane->pipe,
12075 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12076 drm_plane_index(plane), state->scaler_id);
12077 continue;
12078 }
12079
12080 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12081 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12082 plane->base.id, intel_plane->pipe,
12083 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12084 drm_plane_index(plane));
12085 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12086 fb->base.id, fb->width, fb->height, fb->pixel_format);
12087 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12088 state->scaler_id,
12089 state->src.x1 >> 16, state->src.y1 >> 16,
12090 drm_rect_width(&state->src) >> 16,
12091 drm_rect_height(&state->src) >> 16,
12092 state->dst.x1, state->dst.y1,
12093 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12094 }
12095 }
12096
12097 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12098 {
12099 struct drm_device *dev = state->dev;
12100 struct intel_encoder *encoder;
12101 struct drm_connector *connector;
12102 struct drm_connector_state *connector_state;
12103 unsigned int used_ports = 0;
12104 int i;
12105
12106 /*
12107 * Walk the connector list instead of the encoder
12108 * list to detect the problem on ddi platforms
12109 * where there's just one encoder per digital port.
12110 */
12111 for_each_connector_in_state(state, connector, connector_state, i) {
12112 if (!connector_state->best_encoder)
12113 continue;
12114
12115 encoder = to_intel_encoder(connector_state->best_encoder);
12116
12117 WARN_ON(!connector_state->crtc);
12118
12119 switch (encoder->type) {
12120 unsigned int port_mask;
12121 case INTEL_OUTPUT_UNKNOWN:
12122 if (WARN_ON(!HAS_DDI(dev)))
12123 break;
12124 case INTEL_OUTPUT_DISPLAYPORT:
12125 case INTEL_OUTPUT_HDMI:
12126 case INTEL_OUTPUT_EDP:
12127 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12128
12129 /* the same port mustn't appear more than once */
12130 if (used_ports & port_mask)
12131 return false;
12132
12133 used_ports |= port_mask;
12134 default:
12135 break;
12136 }
12137 }
12138
12139 return true;
12140 }
12141
12142 static void
12143 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12144 {
12145 struct drm_crtc_state tmp_state;
12146 struct intel_crtc_scaler_state scaler_state;
12147 struct intel_dpll_hw_state dpll_hw_state;
12148 enum intel_dpll_id shared_dpll;
12149 uint32_t ddi_pll_sel;
12150 bool force_thru;
12151
12152 /* FIXME: before the switch to atomic started, a new pipe_config was
12153 * kzalloc'd. Code that depends on any field being zero should be
12154 * fixed, so that the crtc_state can be safely duplicated. For now,
12155 * only fields that are know to not cause problems are preserved. */
12156
12157 tmp_state = crtc_state->base;
12158 scaler_state = crtc_state->scaler_state;
12159 shared_dpll = crtc_state->shared_dpll;
12160 dpll_hw_state = crtc_state->dpll_hw_state;
12161 ddi_pll_sel = crtc_state->ddi_pll_sel;
12162 force_thru = crtc_state->pch_pfit.force_thru;
12163
12164 memset(crtc_state, 0, sizeof *crtc_state);
12165
12166 crtc_state->base = tmp_state;
12167 crtc_state->scaler_state = scaler_state;
12168 crtc_state->shared_dpll = shared_dpll;
12169 crtc_state->dpll_hw_state = dpll_hw_state;
12170 crtc_state->ddi_pll_sel = ddi_pll_sel;
12171 crtc_state->pch_pfit.force_thru = force_thru;
12172 }
12173
12174 static int
12175 intel_modeset_pipe_config(struct drm_crtc *crtc,
12176 struct intel_crtc_state *pipe_config)
12177 {
12178 struct drm_atomic_state *state = pipe_config->base.state;
12179 struct intel_encoder *encoder;
12180 struct drm_connector *connector;
12181 struct drm_connector_state *connector_state;
12182 int base_bpp, ret = -EINVAL;
12183 int i;
12184 bool retry = true;
12185
12186 clear_intel_crtc_state(pipe_config);
12187
12188 pipe_config->cpu_transcoder =
12189 (enum transcoder) to_intel_crtc(crtc)->pipe;
12190
12191 /*
12192 * Sanitize sync polarity flags based on requested ones. If neither
12193 * positive or negative polarity is requested, treat this as meaning
12194 * negative polarity.
12195 */
12196 if (!(pipe_config->base.adjusted_mode.flags &
12197 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12198 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12199
12200 if (!(pipe_config->base.adjusted_mode.flags &
12201 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12202 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12203
12204 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12205 pipe_config);
12206 if (base_bpp < 0)
12207 goto fail;
12208
12209 /*
12210 * Determine the real pipe dimensions. Note that stereo modes can
12211 * increase the actual pipe size due to the frame doubling and
12212 * insertion of additional space for blanks between the frame. This
12213 * is stored in the crtc timings. We use the requested mode to do this
12214 * computation to clearly distinguish it from the adjusted mode, which
12215 * can be changed by the connectors in the below retry loop.
12216 */
12217 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12218 &pipe_config->pipe_src_w,
12219 &pipe_config->pipe_src_h);
12220
12221 encoder_retry:
12222 /* Ensure the port clock defaults are reset when retrying. */
12223 pipe_config->port_clock = 0;
12224 pipe_config->pixel_multiplier = 1;
12225
12226 /* Fill in default crtc timings, allow encoders to overwrite them. */
12227 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12228 CRTC_STEREO_DOUBLE);
12229
12230 /* Pass our mode to the connectors and the CRTC to give them a chance to
12231 * adjust it according to limitations or connector properties, and also
12232 * a chance to reject the mode entirely.
12233 */
12234 for_each_connector_in_state(state, connector, connector_state, i) {
12235 if (connector_state->crtc != crtc)
12236 continue;
12237
12238 encoder = to_intel_encoder(connector_state->best_encoder);
12239
12240 if (!(encoder->compute_config(encoder, pipe_config))) {
12241 DRM_DEBUG_KMS("Encoder config failure\n");
12242 goto fail;
12243 }
12244 }
12245
12246 /* Set default port clock if not overwritten by the encoder. Needs to be
12247 * done afterwards in case the encoder adjusts the mode. */
12248 if (!pipe_config->port_clock)
12249 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12250 * pipe_config->pixel_multiplier;
12251
12252 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12253 if (ret < 0) {
12254 DRM_DEBUG_KMS("CRTC fixup failed\n");
12255 goto fail;
12256 }
12257
12258 if (ret == RETRY) {
12259 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12260 ret = -EINVAL;
12261 goto fail;
12262 }
12263
12264 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12265 retry = false;
12266 goto encoder_retry;
12267 }
12268
12269 /* Dithering seems to not pass-through bits correctly when it should, so
12270 * only enable it on 6bpc panels. */
12271 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12272 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12273 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12274
12275 fail:
12276 return ret;
12277 }
12278
12279 static void
12280 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12281 {
12282 struct drm_crtc *crtc;
12283 struct drm_crtc_state *crtc_state;
12284 int i;
12285
12286 /* Double check state. */
12287 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12288 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12289
12290 /* Update hwmode for vblank functions */
12291 if (crtc->state->active)
12292 crtc->hwmode = crtc->state->adjusted_mode;
12293 else
12294 crtc->hwmode.crtc_clock = 0;
12295 }
12296 }
12297
12298 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12299 {
12300 int diff;
12301
12302 if (clock1 == clock2)
12303 return true;
12304
12305 if (!clock1 || !clock2)
12306 return false;
12307
12308 diff = abs(clock1 - clock2);
12309
12310 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12311 return true;
12312
12313 return false;
12314 }
12315
12316 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12317 list_for_each_entry((intel_crtc), \
12318 &(dev)->mode_config.crtc_list, \
12319 base.head) \
12320 if (mask & (1 <<(intel_crtc)->pipe))
12321
12322 static bool
12323 intel_compare_m_n(unsigned int m, unsigned int n,
12324 unsigned int m2, unsigned int n2,
12325 bool exact)
12326 {
12327 if (m == m2 && n == n2)
12328 return true;
12329
12330 if (exact || !m || !n || !m2 || !n2)
12331 return false;
12332
12333 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12334
12335 if (m > m2) {
12336 while (m > m2) {
12337 m2 <<= 1;
12338 n2 <<= 1;
12339 }
12340 } else if (m < m2) {
12341 while (m < m2) {
12342 m <<= 1;
12343 n <<= 1;
12344 }
12345 }
12346
12347 return m == m2 && n == n2;
12348 }
12349
12350 static bool
12351 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12352 struct intel_link_m_n *m2_n2,
12353 bool adjust)
12354 {
12355 if (m_n->tu == m2_n2->tu &&
12356 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12357 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12358 intel_compare_m_n(m_n->link_m, m_n->link_n,
12359 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12360 if (adjust)
12361 *m2_n2 = *m_n;
12362
12363 return true;
12364 }
12365
12366 return false;
12367 }
12368
12369 static bool
12370 intel_pipe_config_compare(struct drm_device *dev,
12371 struct intel_crtc_state *current_config,
12372 struct intel_crtc_state *pipe_config,
12373 bool adjust)
12374 {
12375 bool ret = true;
12376
12377 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12378 do { \
12379 if (!adjust) \
12380 DRM_ERROR(fmt, ##__VA_ARGS__); \
12381 else \
12382 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12383 } while (0)
12384
12385 #define PIPE_CONF_CHECK_X(name) \
12386 if (current_config->name != pipe_config->name) { \
12387 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12388 "(expected 0x%08x, found 0x%08x)\n", \
12389 current_config->name, \
12390 pipe_config->name); \
12391 ret = false; \
12392 }
12393
12394 #define PIPE_CONF_CHECK_I(name) \
12395 if (current_config->name != pipe_config->name) { \
12396 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12397 "(expected %i, found %i)\n", \
12398 current_config->name, \
12399 pipe_config->name); \
12400 ret = false; \
12401 }
12402
12403 #define PIPE_CONF_CHECK_M_N(name) \
12404 if (!intel_compare_link_m_n(&current_config->name, \
12405 &pipe_config->name,\
12406 adjust)) { \
12407 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12408 "(expected tu %i gmch %i/%i link %i/%i, " \
12409 "found tu %i, gmch %i/%i link %i/%i)\n", \
12410 current_config->name.tu, \
12411 current_config->name.gmch_m, \
12412 current_config->name.gmch_n, \
12413 current_config->name.link_m, \
12414 current_config->name.link_n, \
12415 pipe_config->name.tu, \
12416 pipe_config->name.gmch_m, \
12417 pipe_config->name.gmch_n, \
12418 pipe_config->name.link_m, \
12419 pipe_config->name.link_n); \
12420 ret = false; \
12421 }
12422
12423 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12424 if (!intel_compare_link_m_n(&current_config->name, \
12425 &pipe_config->name, adjust) && \
12426 !intel_compare_link_m_n(&current_config->alt_name, \
12427 &pipe_config->name, adjust)) { \
12428 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12429 "(expected tu %i gmch %i/%i link %i/%i, " \
12430 "or tu %i gmch %i/%i link %i/%i, " \
12431 "found tu %i, gmch %i/%i link %i/%i)\n", \
12432 current_config->name.tu, \
12433 current_config->name.gmch_m, \
12434 current_config->name.gmch_n, \
12435 current_config->name.link_m, \
12436 current_config->name.link_n, \
12437 current_config->alt_name.tu, \
12438 current_config->alt_name.gmch_m, \
12439 current_config->alt_name.gmch_n, \
12440 current_config->alt_name.link_m, \
12441 current_config->alt_name.link_n, \
12442 pipe_config->name.tu, \
12443 pipe_config->name.gmch_m, \
12444 pipe_config->name.gmch_n, \
12445 pipe_config->name.link_m, \
12446 pipe_config->name.link_n); \
12447 ret = false; \
12448 }
12449
12450 /* This is required for BDW+ where there is only one set of registers for
12451 * switching between high and low RR.
12452 * This macro can be used whenever a comparison has to be made between one
12453 * hw state and multiple sw state variables.
12454 */
12455 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12456 if ((current_config->name != pipe_config->name) && \
12457 (current_config->alt_name != pipe_config->name)) { \
12458 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12459 "(expected %i or %i, found %i)\n", \
12460 current_config->name, \
12461 current_config->alt_name, \
12462 pipe_config->name); \
12463 ret = false; \
12464 }
12465
12466 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12467 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12468 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12469 "(expected %i, found %i)\n", \
12470 current_config->name & (mask), \
12471 pipe_config->name & (mask)); \
12472 ret = false; \
12473 }
12474
12475 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12476 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12477 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12478 "(expected %i, found %i)\n", \
12479 current_config->name, \
12480 pipe_config->name); \
12481 ret = false; \
12482 }
12483
12484 #define PIPE_CONF_QUIRK(quirk) \
12485 ((current_config->quirks | pipe_config->quirks) & (quirk))
12486
12487 PIPE_CONF_CHECK_I(cpu_transcoder);
12488
12489 PIPE_CONF_CHECK_I(has_pch_encoder);
12490 PIPE_CONF_CHECK_I(fdi_lanes);
12491 PIPE_CONF_CHECK_M_N(fdi_m_n);
12492
12493 PIPE_CONF_CHECK_I(has_dp_encoder);
12494 PIPE_CONF_CHECK_I(lane_count);
12495
12496 if (INTEL_INFO(dev)->gen < 8) {
12497 PIPE_CONF_CHECK_M_N(dp_m_n);
12498
12499 PIPE_CONF_CHECK_I(has_drrs);
12500 if (current_config->has_drrs)
12501 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12502 } else
12503 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12504
12505 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12506 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12507 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12508 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12509 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12510 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12511
12512 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12513 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12514 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12515 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12516 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12517 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12518
12519 PIPE_CONF_CHECK_I(pixel_multiplier);
12520 PIPE_CONF_CHECK_I(has_hdmi_sink);
12521 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12522 IS_VALLEYVIEW(dev))
12523 PIPE_CONF_CHECK_I(limited_color_range);
12524 PIPE_CONF_CHECK_I(has_infoframe);
12525
12526 PIPE_CONF_CHECK_I(has_audio);
12527
12528 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12529 DRM_MODE_FLAG_INTERLACE);
12530
12531 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12532 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12533 DRM_MODE_FLAG_PHSYNC);
12534 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12535 DRM_MODE_FLAG_NHSYNC);
12536 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12537 DRM_MODE_FLAG_PVSYNC);
12538 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12539 DRM_MODE_FLAG_NVSYNC);
12540 }
12541
12542 PIPE_CONF_CHECK_X(gmch_pfit.control);
12543 /* pfit ratios are autocomputed by the hw on gen4+ */
12544 if (INTEL_INFO(dev)->gen < 4)
12545 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12546 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12547
12548 if (!adjust) {
12549 PIPE_CONF_CHECK_I(pipe_src_w);
12550 PIPE_CONF_CHECK_I(pipe_src_h);
12551
12552 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12553 if (current_config->pch_pfit.enabled) {
12554 PIPE_CONF_CHECK_X(pch_pfit.pos);
12555 PIPE_CONF_CHECK_X(pch_pfit.size);
12556 }
12557
12558 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12559 }
12560
12561 /* BDW+ don't expose a synchronous way to read the state */
12562 if (IS_HASWELL(dev))
12563 PIPE_CONF_CHECK_I(ips_enabled);
12564
12565 PIPE_CONF_CHECK_I(double_wide);
12566
12567 PIPE_CONF_CHECK_X(ddi_pll_sel);
12568
12569 PIPE_CONF_CHECK_I(shared_dpll);
12570 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12571 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12572 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12573 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12574 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12575 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12576 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12577 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12578
12579 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12580 PIPE_CONF_CHECK_I(pipe_bpp);
12581
12582 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12583 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12584
12585 #undef PIPE_CONF_CHECK_X
12586 #undef PIPE_CONF_CHECK_I
12587 #undef PIPE_CONF_CHECK_I_ALT
12588 #undef PIPE_CONF_CHECK_FLAGS
12589 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12590 #undef PIPE_CONF_QUIRK
12591 #undef INTEL_ERR_OR_DBG_KMS
12592
12593 return ret;
12594 }
12595
12596 static void check_wm_state(struct drm_device *dev)
12597 {
12598 struct drm_i915_private *dev_priv = dev->dev_private;
12599 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12600 struct intel_crtc *intel_crtc;
12601 int plane;
12602
12603 if (INTEL_INFO(dev)->gen < 9)
12604 return;
12605
12606 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12607 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12608
12609 for_each_intel_crtc(dev, intel_crtc) {
12610 struct skl_ddb_entry *hw_entry, *sw_entry;
12611 const enum pipe pipe = intel_crtc->pipe;
12612
12613 if (!intel_crtc->active)
12614 continue;
12615
12616 /* planes */
12617 for_each_plane(dev_priv, pipe, plane) {
12618 hw_entry = &hw_ddb.plane[pipe][plane];
12619 sw_entry = &sw_ddb->plane[pipe][plane];
12620
12621 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12622 continue;
12623
12624 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12625 "(expected (%u,%u), found (%u,%u))\n",
12626 pipe_name(pipe), plane + 1,
12627 sw_entry->start, sw_entry->end,
12628 hw_entry->start, hw_entry->end);
12629 }
12630
12631 /* cursor */
12632 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12633 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12634
12635 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12636 continue;
12637
12638 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12639 "(expected (%u,%u), found (%u,%u))\n",
12640 pipe_name(pipe),
12641 sw_entry->start, sw_entry->end,
12642 hw_entry->start, hw_entry->end);
12643 }
12644 }
12645
12646 static void
12647 check_connector_state(struct drm_device *dev,
12648 struct drm_atomic_state *old_state)
12649 {
12650 struct drm_connector_state *old_conn_state;
12651 struct drm_connector *connector;
12652 int i;
12653
12654 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12655 struct drm_encoder *encoder = connector->encoder;
12656 struct drm_connector_state *state = connector->state;
12657
12658 /* This also checks the encoder/connector hw state with the
12659 * ->get_hw_state callbacks. */
12660 intel_connector_check_state(to_intel_connector(connector));
12661
12662 I915_STATE_WARN(state->best_encoder != encoder,
12663 "connector's atomic encoder doesn't match legacy encoder\n");
12664 }
12665 }
12666
12667 static void
12668 check_encoder_state(struct drm_device *dev)
12669 {
12670 struct intel_encoder *encoder;
12671 struct intel_connector *connector;
12672
12673 for_each_intel_encoder(dev, encoder) {
12674 bool enabled = false;
12675 enum pipe pipe;
12676
12677 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12678 encoder->base.base.id,
12679 encoder->base.name);
12680
12681 for_each_intel_connector(dev, connector) {
12682 if (connector->base.state->best_encoder != &encoder->base)
12683 continue;
12684 enabled = true;
12685
12686 I915_STATE_WARN(connector->base.state->crtc !=
12687 encoder->base.crtc,
12688 "connector's crtc doesn't match encoder crtc\n");
12689 }
12690
12691 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12692 "encoder's enabled state mismatch "
12693 "(expected %i, found %i)\n",
12694 !!encoder->base.crtc, enabled);
12695
12696 if (!encoder->base.crtc) {
12697 bool active;
12698
12699 active = encoder->get_hw_state(encoder, &pipe);
12700 I915_STATE_WARN(active,
12701 "encoder detached but still enabled on pipe %c.\n",
12702 pipe_name(pipe));
12703 }
12704 }
12705 }
12706
12707 static void
12708 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12709 {
12710 struct drm_i915_private *dev_priv = dev->dev_private;
12711 struct intel_encoder *encoder;
12712 struct drm_crtc_state *old_crtc_state;
12713 struct drm_crtc *crtc;
12714 int i;
12715
12716 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12718 struct intel_crtc_state *pipe_config, *sw_config;
12719 bool active;
12720
12721 if (!needs_modeset(crtc->state) &&
12722 !to_intel_crtc_state(crtc->state)->update_pipe)
12723 continue;
12724
12725 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12726 pipe_config = to_intel_crtc_state(old_crtc_state);
12727 memset(pipe_config, 0, sizeof(*pipe_config));
12728 pipe_config->base.crtc = crtc;
12729 pipe_config->base.state = old_state;
12730
12731 DRM_DEBUG_KMS("[CRTC:%d]\n",
12732 crtc->base.id);
12733
12734 active = dev_priv->display.get_pipe_config(intel_crtc,
12735 pipe_config);
12736
12737 /* hw state is inconsistent with the pipe quirk */
12738 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12739 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12740 active = crtc->state->active;
12741
12742 I915_STATE_WARN(crtc->state->active != active,
12743 "crtc active state doesn't match with hw state "
12744 "(expected %i, found %i)\n", crtc->state->active, active);
12745
12746 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12747 "transitional active state does not match atomic hw state "
12748 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12749
12750 for_each_encoder_on_crtc(dev, crtc, encoder) {
12751 enum pipe pipe;
12752
12753 active = encoder->get_hw_state(encoder, &pipe);
12754 I915_STATE_WARN(active != crtc->state->active,
12755 "[ENCODER:%i] active %i with crtc active %i\n",
12756 encoder->base.base.id, active, crtc->state->active);
12757
12758 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12759 "Encoder connected to wrong pipe %c\n",
12760 pipe_name(pipe));
12761
12762 if (active)
12763 encoder->get_config(encoder, pipe_config);
12764 }
12765
12766 if (!crtc->state->active)
12767 continue;
12768
12769 sw_config = to_intel_crtc_state(crtc->state);
12770 if (!intel_pipe_config_compare(dev, sw_config,
12771 pipe_config, false)) {
12772 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12773 intel_dump_pipe_config(intel_crtc, pipe_config,
12774 "[hw state]");
12775 intel_dump_pipe_config(intel_crtc, sw_config,
12776 "[sw state]");
12777 }
12778 }
12779 }
12780
12781 static void
12782 check_shared_dpll_state(struct drm_device *dev)
12783 {
12784 struct drm_i915_private *dev_priv = dev->dev_private;
12785 struct intel_crtc *crtc;
12786 struct intel_dpll_hw_state dpll_hw_state;
12787 int i;
12788
12789 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12790 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12791 int enabled_crtcs = 0, active_crtcs = 0;
12792 bool active;
12793
12794 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12795
12796 DRM_DEBUG_KMS("%s\n", pll->name);
12797
12798 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12799
12800 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12801 "more active pll users than references: %i vs %i\n",
12802 pll->active, hweight32(pll->config.crtc_mask));
12803 I915_STATE_WARN(pll->active && !pll->on,
12804 "pll in active use but not on in sw tracking\n");
12805 I915_STATE_WARN(pll->on && !pll->active,
12806 "pll in on but not on in use in sw tracking\n");
12807 I915_STATE_WARN(pll->on != active,
12808 "pll on state mismatch (expected %i, found %i)\n",
12809 pll->on, active);
12810
12811 for_each_intel_crtc(dev, crtc) {
12812 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12813 enabled_crtcs++;
12814 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12815 active_crtcs++;
12816 }
12817 I915_STATE_WARN(pll->active != active_crtcs,
12818 "pll active crtcs mismatch (expected %i, found %i)\n",
12819 pll->active, active_crtcs);
12820 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12821 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12822 hweight32(pll->config.crtc_mask), enabled_crtcs);
12823
12824 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12825 sizeof(dpll_hw_state)),
12826 "pll hw state mismatch\n");
12827 }
12828 }
12829
12830 static void
12831 intel_modeset_check_state(struct drm_device *dev,
12832 struct drm_atomic_state *old_state)
12833 {
12834 check_wm_state(dev);
12835 check_connector_state(dev, old_state);
12836 check_encoder_state(dev);
12837 check_crtc_state(dev, old_state);
12838 check_shared_dpll_state(dev);
12839 }
12840
12841 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12842 int dotclock)
12843 {
12844 /*
12845 * FDI already provided one idea for the dotclock.
12846 * Yell if the encoder disagrees.
12847 */
12848 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12849 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12850 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12851 }
12852
12853 static void update_scanline_offset(struct intel_crtc *crtc)
12854 {
12855 struct drm_device *dev = crtc->base.dev;
12856
12857 /*
12858 * The scanline counter increments at the leading edge of hsync.
12859 *
12860 * On most platforms it starts counting from vtotal-1 on the
12861 * first active line. That means the scanline counter value is
12862 * always one less than what we would expect. Ie. just after
12863 * start of vblank, which also occurs at start of hsync (on the
12864 * last active line), the scanline counter will read vblank_start-1.
12865 *
12866 * On gen2 the scanline counter starts counting from 1 instead
12867 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12868 * to keep the value positive), instead of adding one.
12869 *
12870 * On HSW+ the behaviour of the scanline counter depends on the output
12871 * type. For DP ports it behaves like most other platforms, but on HDMI
12872 * there's an extra 1 line difference. So we need to add two instead of
12873 * one to the value.
12874 */
12875 if (IS_GEN2(dev)) {
12876 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12877 int vtotal;
12878
12879 vtotal = adjusted_mode->crtc_vtotal;
12880 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12881 vtotal /= 2;
12882
12883 crtc->scanline_offset = vtotal - 1;
12884 } else if (HAS_DDI(dev) &&
12885 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12886 crtc->scanline_offset = 2;
12887 } else
12888 crtc->scanline_offset = 1;
12889 }
12890
12891 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12892 {
12893 struct drm_device *dev = state->dev;
12894 struct drm_i915_private *dev_priv = to_i915(dev);
12895 struct intel_shared_dpll_config *shared_dpll = NULL;
12896 struct intel_crtc *intel_crtc;
12897 struct intel_crtc_state *intel_crtc_state;
12898 struct drm_crtc *crtc;
12899 struct drm_crtc_state *crtc_state;
12900 int i;
12901
12902 if (!dev_priv->display.crtc_compute_clock)
12903 return;
12904
12905 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12906 int dpll;
12907
12908 intel_crtc = to_intel_crtc(crtc);
12909 intel_crtc_state = to_intel_crtc_state(crtc_state);
12910 dpll = intel_crtc_state->shared_dpll;
12911
12912 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12913 continue;
12914
12915 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12916
12917 if (!shared_dpll)
12918 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12919
12920 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12921 }
12922 }
12923
12924 /*
12925 * This implements the workaround described in the "notes" section of the mode
12926 * set sequence documentation. When going from no pipes or single pipe to
12927 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12928 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12929 */
12930 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12931 {
12932 struct drm_crtc_state *crtc_state;
12933 struct intel_crtc *intel_crtc;
12934 struct drm_crtc *crtc;
12935 struct intel_crtc_state *first_crtc_state = NULL;
12936 struct intel_crtc_state *other_crtc_state = NULL;
12937 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12938 int i;
12939
12940 /* look at all crtc's that are going to be enabled in during modeset */
12941 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12942 intel_crtc = to_intel_crtc(crtc);
12943
12944 if (!crtc_state->active || !needs_modeset(crtc_state))
12945 continue;
12946
12947 if (first_crtc_state) {
12948 other_crtc_state = to_intel_crtc_state(crtc_state);
12949 break;
12950 } else {
12951 first_crtc_state = to_intel_crtc_state(crtc_state);
12952 first_pipe = intel_crtc->pipe;
12953 }
12954 }
12955
12956 /* No workaround needed? */
12957 if (!first_crtc_state)
12958 return 0;
12959
12960 /* w/a possibly needed, check how many crtc's are already enabled. */
12961 for_each_intel_crtc(state->dev, intel_crtc) {
12962 struct intel_crtc_state *pipe_config;
12963
12964 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12965 if (IS_ERR(pipe_config))
12966 return PTR_ERR(pipe_config);
12967
12968 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12969
12970 if (!pipe_config->base.active ||
12971 needs_modeset(&pipe_config->base))
12972 continue;
12973
12974 /* 2 or more enabled crtcs means no need for w/a */
12975 if (enabled_pipe != INVALID_PIPE)
12976 return 0;
12977
12978 enabled_pipe = intel_crtc->pipe;
12979 }
12980
12981 if (enabled_pipe != INVALID_PIPE)
12982 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12983 else if (other_crtc_state)
12984 other_crtc_state->hsw_workaround_pipe = first_pipe;
12985
12986 return 0;
12987 }
12988
12989 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12990 {
12991 struct drm_crtc *crtc;
12992 struct drm_crtc_state *crtc_state;
12993 int ret = 0;
12994
12995 /* add all active pipes to the state */
12996 for_each_crtc(state->dev, crtc) {
12997 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12998 if (IS_ERR(crtc_state))
12999 return PTR_ERR(crtc_state);
13000
13001 if (!crtc_state->active || needs_modeset(crtc_state))
13002 continue;
13003
13004 crtc_state->mode_changed = true;
13005
13006 ret = drm_atomic_add_affected_connectors(state, crtc);
13007 if (ret)
13008 break;
13009
13010 ret = drm_atomic_add_affected_planes(state, crtc);
13011 if (ret)
13012 break;
13013 }
13014
13015 return ret;
13016 }
13017
13018 static int intel_modeset_checks(struct drm_atomic_state *state)
13019 {
13020 struct drm_device *dev = state->dev;
13021 struct drm_i915_private *dev_priv = dev->dev_private;
13022 int ret;
13023
13024 if (!check_digital_port_conflicts(state)) {
13025 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13026 return -EINVAL;
13027 }
13028
13029 /*
13030 * See if the config requires any additional preparation, e.g.
13031 * to adjust global state with pipes off. We need to do this
13032 * here so we can get the modeset_pipe updated config for the new
13033 * mode set on this crtc. For other crtcs we need to use the
13034 * adjusted_mode bits in the crtc directly.
13035 */
13036 if (dev_priv->display.modeset_calc_cdclk) {
13037 unsigned int cdclk;
13038
13039 ret = dev_priv->display.modeset_calc_cdclk(state);
13040
13041 cdclk = to_intel_atomic_state(state)->cdclk;
13042 if (!ret && cdclk != dev_priv->cdclk_freq)
13043 ret = intel_modeset_all_pipes(state);
13044
13045 if (ret < 0)
13046 return ret;
13047 } else
13048 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13049
13050 intel_modeset_clear_plls(state);
13051
13052 if (IS_HASWELL(dev))
13053 return haswell_mode_set_planes_workaround(state);
13054
13055 return 0;
13056 }
13057
13058 /*
13059 * Handle calculation of various watermark data at the end of the atomic check
13060 * phase. The code here should be run after the per-crtc and per-plane 'check'
13061 * handlers to ensure that all derived state has been updated.
13062 */
13063 static void calc_watermark_data(struct drm_atomic_state *state)
13064 {
13065 struct drm_device *dev = state->dev;
13066 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13067 struct drm_crtc *crtc;
13068 struct drm_crtc_state *cstate;
13069 struct drm_plane *plane;
13070 struct drm_plane_state *pstate;
13071
13072 /*
13073 * Calculate watermark configuration details now that derived
13074 * plane/crtc state is all properly updated.
13075 */
13076 drm_for_each_crtc(crtc, dev) {
13077 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13078 crtc->state;
13079
13080 if (cstate->active)
13081 intel_state->wm_config.num_pipes_active++;
13082 }
13083 drm_for_each_legacy_plane(plane, dev) {
13084 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13085 plane->state;
13086
13087 if (!to_intel_plane_state(pstate)->visible)
13088 continue;
13089
13090 intel_state->wm_config.sprites_enabled = true;
13091 if (pstate->crtc_w != pstate->src_w >> 16 ||
13092 pstate->crtc_h != pstate->src_h >> 16)
13093 intel_state->wm_config.sprites_scaled = true;
13094 }
13095 }
13096
13097 /**
13098 * intel_atomic_check - validate state object
13099 * @dev: drm device
13100 * @state: state to validate
13101 */
13102 static int intel_atomic_check(struct drm_device *dev,
13103 struct drm_atomic_state *state)
13104 {
13105 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13106 struct drm_crtc *crtc;
13107 struct drm_crtc_state *crtc_state;
13108 int ret, i;
13109 bool any_ms = false;
13110
13111 ret = drm_atomic_helper_check_modeset(dev, state);
13112 if (ret)
13113 return ret;
13114
13115 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13116 struct intel_crtc_state *pipe_config =
13117 to_intel_crtc_state(crtc_state);
13118
13119 /* Catch I915_MODE_FLAG_INHERITED */
13120 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13121 crtc_state->mode_changed = true;
13122
13123 if (!crtc_state->enable) {
13124 if (needs_modeset(crtc_state))
13125 any_ms = true;
13126 continue;
13127 }
13128
13129 if (!needs_modeset(crtc_state))
13130 continue;
13131
13132 /* FIXME: For only active_changed we shouldn't need to do any
13133 * state recomputation at all. */
13134
13135 ret = drm_atomic_add_affected_connectors(state, crtc);
13136 if (ret)
13137 return ret;
13138
13139 ret = intel_modeset_pipe_config(crtc, pipe_config);
13140 if (ret)
13141 return ret;
13142
13143 if (intel_pipe_config_compare(state->dev,
13144 to_intel_crtc_state(crtc->state),
13145 pipe_config, true)) {
13146 crtc_state->mode_changed = false;
13147 to_intel_crtc_state(crtc_state)->update_pipe = true;
13148 }
13149
13150 if (needs_modeset(crtc_state)) {
13151 any_ms = true;
13152
13153 ret = drm_atomic_add_affected_planes(state, crtc);
13154 if (ret)
13155 return ret;
13156 }
13157
13158 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13159 needs_modeset(crtc_state) ?
13160 "[modeset]" : "[fastset]");
13161 }
13162
13163 if (any_ms) {
13164 ret = intel_modeset_checks(state);
13165
13166 if (ret)
13167 return ret;
13168 } else
13169 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13170
13171 ret = drm_atomic_helper_check_planes(state->dev, state);
13172 if (ret)
13173 return ret;
13174
13175 calc_watermark_data(state);
13176
13177 return 0;
13178 }
13179
13180 /**
13181 * intel_atomic_commit - commit validated state object
13182 * @dev: DRM device
13183 * @state: the top-level driver state object
13184 * @async: asynchronous commit
13185 *
13186 * This function commits a top-level state object that has been validated
13187 * with drm_atomic_helper_check().
13188 *
13189 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13190 * we can only handle plane-related operations and do not yet support
13191 * asynchronous commit.
13192 *
13193 * RETURNS
13194 * Zero for success or -errno.
13195 */
13196 static int intel_atomic_commit(struct drm_device *dev,
13197 struct drm_atomic_state *state,
13198 bool async)
13199 {
13200 struct drm_i915_private *dev_priv = dev->dev_private;
13201 struct drm_crtc *crtc;
13202 struct drm_crtc_state *crtc_state;
13203 int ret = 0;
13204 int i;
13205 bool any_ms = false;
13206
13207 if (async) {
13208 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13209 return -EINVAL;
13210 }
13211
13212 ret = drm_atomic_helper_prepare_planes(dev, state);
13213 if (ret)
13214 return ret;
13215
13216 drm_atomic_helper_swap_state(dev, state);
13217 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13218
13219 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13221
13222 if (!needs_modeset(crtc->state))
13223 continue;
13224
13225 any_ms = true;
13226 intel_pre_plane_update(intel_crtc);
13227
13228 if (crtc_state->active) {
13229 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13230 dev_priv->display.crtc_disable(crtc);
13231 intel_crtc->active = false;
13232 intel_disable_shared_dpll(intel_crtc);
13233 }
13234 }
13235
13236 /* Only after disabling all output pipelines that will be changed can we
13237 * update the the output configuration. */
13238 intel_modeset_update_crtc_state(state);
13239
13240 if (any_ms) {
13241 intel_shared_dpll_commit(state);
13242
13243 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13244 modeset_update_crtc_power_domains(state);
13245 }
13246
13247 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13248 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13250 bool modeset = needs_modeset(crtc->state);
13251 bool update_pipe = !modeset &&
13252 to_intel_crtc_state(crtc->state)->update_pipe;
13253 unsigned long put_domains = 0;
13254
13255 if (modeset && crtc->state->active) {
13256 update_scanline_offset(to_intel_crtc(crtc));
13257 dev_priv->display.crtc_enable(crtc);
13258 }
13259
13260 if (update_pipe) {
13261 put_domains = modeset_get_crtc_power_domains(crtc);
13262
13263 /* make sure intel_modeset_check_state runs */
13264 any_ms = true;
13265 }
13266
13267 if (!modeset)
13268 intel_pre_plane_update(intel_crtc);
13269
13270 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13271
13272 if (put_domains)
13273 modeset_put_power_domains(dev_priv, put_domains);
13274
13275 intel_post_plane_update(intel_crtc);
13276 }
13277
13278 /* FIXME: add subpixel order */
13279
13280 drm_atomic_helper_wait_for_vblanks(dev, state);
13281 drm_atomic_helper_cleanup_planes(dev, state);
13282
13283 if (any_ms)
13284 intel_modeset_check_state(dev, state);
13285
13286 drm_atomic_state_free(state);
13287
13288 return 0;
13289 }
13290
13291 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13292 {
13293 struct drm_device *dev = crtc->dev;
13294 struct drm_atomic_state *state;
13295 struct drm_crtc_state *crtc_state;
13296 int ret;
13297
13298 state = drm_atomic_state_alloc(dev);
13299 if (!state) {
13300 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13301 crtc->base.id);
13302 return;
13303 }
13304
13305 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13306
13307 retry:
13308 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13309 ret = PTR_ERR_OR_ZERO(crtc_state);
13310 if (!ret) {
13311 if (!crtc_state->active)
13312 goto out;
13313
13314 crtc_state->mode_changed = true;
13315 ret = drm_atomic_commit(state);
13316 }
13317
13318 if (ret == -EDEADLK) {
13319 drm_atomic_state_clear(state);
13320 drm_modeset_backoff(state->acquire_ctx);
13321 goto retry;
13322 }
13323
13324 if (ret)
13325 out:
13326 drm_atomic_state_free(state);
13327 }
13328
13329 #undef for_each_intel_crtc_masked
13330
13331 static const struct drm_crtc_funcs intel_crtc_funcs = {
13332 .gamma_set = intel_crtc_gamma_set,
13333 .set_config = drm_atomic_helper_set_config,
13334 .destroy = intel_crtc_destroy,
13335 .page_flip = intel_crtc_page_flip,
13336 .atomic_duplicate_state = intel_crtc_duplicate_state,
13337 .atomic_destroy_state = intel_crtc_destroy_state,
13338 };
13339
13340 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13341 struct intel_shared_dpll *pll,
13342 struct intel_dpll_hw_state *hw_state)
13343 {
13344 uint32_t val;
13345
13346 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13347 return false;
13348
13349 val = I915_READ(PCH_DPLL(pll->id));
13350 hw_state->dpll = val;
13351 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13352 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13353
13354 return val & DPLL_VCO_ENABLE;
13355 }
13356
13357 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13358 struct intel_shared_dpll *pll)
13359 {
13360 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13361 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13362 }
13363
13364 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13365 struct intel_shared_dpll *pll)
13366 {
13367 /* PCH refclock must be enabled first */
13368 ibx_assert_pch_refclk_enabled(dev_priv);
13369
13370 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13371
13372 /* Wait for the clocks to stabilize. */
13373 POSTING_READ(PCH_DPLL(pll->id));
13374 udelay(150);
13375
13376 /* The pixel multiplier can only be updated once the
13377 * DPLL is enabled and the clocks are stable.
13378 *
13379 * So write it again.
13380 */
13381 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13382 POSTING_READ(PCH_DPLL(pll->id));
13383 udelay(200);
13384 }
13385
13386 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13387 struct intel_shared_dpll *pll)
13388 {
13389 struct drm_device *dev = dev_priv->dev;
13390 struct intel_crtc *crtc;
13391
13392 /* Make sure no transcoder isn't still depending on us. */
13393 for_each_intel_crtc(dev, crtc) {
13394 if (intel_crtc_to_shared_dpll(crtc) == pll)
13395 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13396 }
13397
13398 I915_WRITE(PCH_DPLL(pll->id), 0);
13399 POSTING_READ(PCH_DPLL(pll->id));
13400 udelay(200);
13401 }
13402
13403 static char *ibx_pch_dpll_names[] = {
13404 "PCH DPLL A",
13405 "PCH DPLL B",
13406 };
13407
13408 static void ibx_pch_dpll_init(struct drm_device *dev)
13409 {
13410 struct drm_i915_private *dev_priv = dev->dev_private;
13411 int i;
13412
13413 dev_priv->num_shared_dpll = 2;
13414
13415 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13416 dev_priv->shared_dplls[i].id = i;
13417 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13418 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13419 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13420 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13421 dev_priv->shared_dplls[i].get_hw_state =
13422 ibx_pch_dpll_get_hw_state;
13423 }
13424 }
13425
13426 static void intel_shared_dpll_init(struct drm_device *dev)
13427 {
13428 struct drm_i915_private *dev_priv = dev->dev_private;
13429
13430 if (HAS_DDI(dev))
13431 intel_ddi_pll_init(dev);
13432 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13433 ibx_pch_dpll_init(dev);
13434 else
13435 dev_priv->num_shared_dpll = 0;
13436
13437 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13438 }
13439
13440 /**
13441 * intel_prepare_plane_fb - Prepare fb for usage on plane
13442 * @plane: drm plane to prepare for
13443 * @fb: framebuffer to prepare for presentation
13444 *
13445 * Prepares a framebuffer for usage on a display plane. Generally this
13446 * involves pinning the underlying object and updating the frontbuffer tracking
13447 * bits. Some older platforms need special physical address handling for
13448 * cursor planes.
13449 *
13450 * Returns 0 on success, negative error code on failure.
13451 */
13452 int
13453 intel_prepare_plane_fb(struct drm_plane *plane,
13454 const struct drm_plane_state *new_state)
13455 {
13456 struct drm_device *dev = plane->dev;
13457 struct drm_framebuffer *fb = new_state->fb;
13458 struct intel_plane *intel_plane = to_intel_plane(plane);
13459 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13460 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13461 int ret = 0;
13462
13463 if (!obj)
13464 return 0;
13465
13466 mutex_lock(&dev->struct_mutex);
13467
13468 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13469 INTEL_INFO(dev)->cursor_needs_physical) {
13470 int align = IS_I830(dev) ? 16 * 1024 : 256;
13471 ret = i915_gem_object_attach_phys(obj, align);
13472 if (ret)
13473 DRM_DEBUG_KMS("failed to attach phys object\n");
13474 } else {
13475 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13476 }
13477
13478 if (ret == 0)
13479 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13480
13481 mutex_unlock(&dev->struct_mutex);
13482
13483 return ret;
13484 }
13485
13486 /**
13487 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13488 * @plane: drm plane to clean up for
13489 * @fb: old framebuffer that was on plane
13490 *
13491 * Cleans up a framebuffer that has just been removed from a plane.
13492 */
13493 void
13494 intel_cleanup_plane_fb(struct drm_plane *plane,
13495 const struct drm_plane_state *old_state)
13496 {
13497 struct drm_device *dev = plane->dev;
13498 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13499
13500 if (!obj)
13501 return;
13502
13503 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13504 !INTEL_INFO(dev)->cursor_needs_physical) {
13505 mutex_lock(&dev->struct_mutex);
13506 intel_unpin_fb_obj(old_state->fb, old_state);
13507 mutex_unlock(&dev->struct_mutex);
13508 }
13509 }
13510
13511 int
13512 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13513 {
13514 int max_scale;
13515 struct drm_device *dev;
13516 struct drm_i915_private *dev_priv;
13517 int crtc_clock, cdclk;
13518
13519 if (!intel_crtc || !crtc_state)
13520 return DRM_PLANE_HELPER_NO_SCALING;
13521
13522 dev = intel_crtc->base.dev;
13523 dev_priv = dev->dev_private;
13524 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13525 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13526
13527 if (!crtc_clock || !cdclk)
13528 return DRM_PLANE_HELPER_NO_SCALING;
13529
13530 /*
13531 * skl max scale is lower of:
13532 * close to 3 but not 3, -1 is for that purpose
13533 * or
13534 * cdclk/crtc_clock
13535 */
13536 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13537
13538 return max_scale;
13539 }
13540
13541 static int
13542 intel_check_primary_plane(struct drm_plane *plane,
13543 struct intel_crtc_state *crtc_state,
13544 struct intel_plane_state *state)
13545 {
13546 struct drm_crtc *crtc = state->base.crtc;
13547 struct drm_framebuffer *fb = state->base.fb;
13548 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13549 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13550 bool can_position = false;
13551
13552 /* use scaler when colorkey is not required */
13553 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13554 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13555 min_scale = 1;
13556 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13557 can_position = true;
13558 }
13559
13560 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13561 &state->dst, &state->clip,
13562 min_scale, max_scale,
13563 can_position, true,
13564 &state->visible);
13565 }
13566
13567 static void
13568 intel_commit_primary_plane(struct drm_plane *plane,
13569 struct intel_plane_state *state)
13570 {
13571 struct drm_crtc *crtc = state->base.crtc;
13572 struct drm_framebuffer *fb = state->base.fb;
13573 struct drm_device *dev = plane->dev;
13574 struct drm_i915_private *dev_priv = dev->dev_private;
13575 struct intel_crtc *intel_crtc;
13576 struct drm_rect *src = &state->src;
13577
13578 crtc = crtc ? crtc : plane->crtc;
13579 intel_crtc = to_intel_crtc(crtc);
13580
13581 plane->fb = fb;
13582 crtc->x = src->x1 >> 16;
13583 crtc->y = src->y1 >> 16;
13584
13585 if (!crtc->state->active)
13586 return;
13587
13588 dev_priv->display.update_primary_plane(crtc, fb,
13589 state->src.x1 >> 16,
13590 state->src.y1 >> 16);
13591 }
13592
13593 static void
13594 intel_disable_primary_plane(struct drm_plane *plane,
13595 struct drm_crtc *crtc)
13596 {
13597 struct drm_device *dev = plane->dev;
13598 struct drm_i915_private *dev_priv = dev->dev_private;
13599
13600 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13601 }
13602
13603 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13604 struct drm_crtc_state *old_crtc_state)
13605 {
13606 struct drm_device *dev = crtc->dev;
13607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13608 struct intel_crtc_state *old_intel_state =
13609 to_intel_crtc_state(old_crtc_state);
13610 bool modeset = needs_modeset(crtc->state);
13611
13612 if (intel_crtc->atomic.update_wm_pre)
13613 intel_update_watermarks(crtc);
13614
13615 /* Perform vblank evasion around commit operation */
13616 if (crtc->state->active)
13617 intel_pipe_update_start(intel_crtc);
13618
13619 if (modeset)
13620 return;
13621
13622 if (to_intel_crtc_state(crtc->state)->update_pipe)
13623 intel_update_pipe_config(intel_crtc, old_intel_state);
13624 else if (INTEL_INFO(dev)->gen >= 9)
13625 skl_detach_scalers(intel_crtc);
13626 }
13627
13628 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13629 struct drm_crtc_state *old_crtc_state)
13630 {
13631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13632
13633 if (crtc->state->active)
13634 intel_pipe_update_end(intel_crtc);
13635 }
13636
13637 /**
13638 * intel_plane_destroy - destroy a plane
13639 * @plane: plane to destroy
13640 *
13641 * Common destruction function for all types of planes (primary, cursor,
13642 * sprite).
13643 */
13644 void intel_plane_destroy(struct drm_plane *plane)
13645 {
13646 struct intel_plane *intel_plane = to_intel_plane(plane);
13647 drm_plane_cleanup(plane);
13648 kfree(intel_plane);
13649 }
13650
13651 const struct drm_plane_funcs intel_plane_funcs = {
13652 .update_plane = drm_atomic_helper_update_plane,
13653 .disable_plane = drm_atomic_helper_disable_plane,
13654 .destroy = intel_plane_destroy,
13655 .set_property = drm_atomic_helper_plane_set_property,
13656 .atomic_get_property = intel_plane_atomic_get_property,
13657 .atomic_set_property = intel_plane_atomic_set_property,
13658 .atomic_duplicate_state = intel_plane_duplicate_state,
13659 .atomic_destroy_state = intel_plane_destroy_state,
13660
13661 };
13662
13663 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13664 int pipe)
13665 {
13666 struct intel_plane *primary;
13667 struct intel_plane_state *state;
13668 const uint32_t *intel_primary_formats;
13669 unsigned int num_formats;
13670
13671 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13672 if (primary == NULL)
13673 return NULL;
13674
13675 state = intel_create_plane_state(&primary->base);
13676 if (!state) {
13677 kfree(primary);
13678 return NULL;
13679 }
13680 primary->base.state = &state->base;
13681
13682 primary->can_scale = false;
13683 primary->max_downscale = 1;
13684 if (INTEL_INFO(dev)->gen >= 9) {
13685 primary->can_scale = true;
13686 state->scaler_id = -1;
13687 }
13688 primary->pipe = pipe;
13689 primary->plane = pipe;
13690 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13691 primary->check_plane = intel_check_primary_plane;
13692 primary->commit_plane = intel_commit_primary_plane;
13693 primary->disable_plane = intel_disable_primary_plane;
13694 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13695 primary->plane = !pipe;
13696
13697 if (INTEL_INFO(dev)->gen >= 9) {
13698 intel_primary_formats = skl_primary_formats;
13699 num_formats = ARRAY_SIZE(skl_primary_formats);
13700 } else if (INTEL_INFO(dev)->gen >= 4) {
13701 intel_primary_formats = i965_primary_formats;
13702 num_formats = ARRAY_SIZE(i965_primary_formats);
13703 } else {
13704 intel_primary_formats = i8xx_primary_formats;
13705 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13706 }
13707
13708 drm_universal_plane_init(dev, &primary->base, 0,
13709 &intel_plane_funcs,
13710 intel_primary_formats, num_formats,
13711 DRM_PLANE_TYPE_PRIMARY);
13712
13713 if (INTEL_INFO(dev)->gen >= 4)
13714 intel_create_rotation_property(dev, primary);
13715
13716 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13717
13718 return &primary->base;
13719 }
13720
13721 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13722 {
13723 if (!dev->mode_config.rotation_property) {
13724 unsigned long flags = BIT(DRM_ROTATE_0) |
13725 BIT(DRM_ROTATE_180);
13726
13727 if (INTEL_INFO(dev)->gen >= 9)
13728 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13729
13730 dev->mode_config.rotation_property =
13731 drm_mode_create_rotation_property(dev, flags);
13732 }
13733 if (dev->mode_config.rotation_property)
13734 drm_object_attach_property(&plane->base.base,
13735 dev->mode_config.rotation_property,
13736 plane->base.state->rotation);
13737 }
13738
13739 static int
13740 intel_check_cursor_plane(struct drm_plane *plane,
13741 struct intel_crtc_state *crtc_state,
13742 struct intel_plane_state *state)
13743 {
13744 struct drm_crtc *crtc = crtc_state->base.crtc;
13745 struct drm_framebuffer *fb = state->base.fb;
13746 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13747 unsigned stride;
13748 int ret;
13749
13750 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13751 &state->dst, &state->clip,
13752 DRM_PLANE_HELPER_NO_SCALING,
13753 DRM_PLANE_HELPER_NO_SCALING,
13754 true, true, &state->visible);
13755 if (ret)
13756 return ret;
13757
13758 /* if we want to turn off the cursor ignore width and height */
13759 if (!obj)
13760 return 0;
13761
13762 /* Check for which cursor types we support */
13763 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13764 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13765 state->base.crtc_w, state->base.crtc_h);
13766 return -EINVAL;
13767 }
13768
13769 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13770 if (obj->base.size < stride * state->base.crtc_h) {
13771 DRM_DEBUG_KMS("buffer is too small\n");
13772 return -ENOMEM;
13773 }
13774
13775 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13776 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13777 return -EINVAL;
13778 }
13779
13780 return 0;
13781 }
13782
13783 static void
13784 intel_disable_cursor_plane(struct drm_plane *plane,
13785 struct drm_crtc *crtc)
13786 {
13787 intel_crtc_update_cursor(crtc, false);
13788 }
13789
13790 static void
13791 intel_commit_cursor_plane(struct drm_plane *plane,
13792 struct intel_plane_state *state)
13793 {
13794 struct drm_crtc *crtc = state->base.crtc;
13795 struct drm_device *dev = plane->dev;
13796 struct intel_crtc *intel_crtc;
13797 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13798 uint32_t addr;
13799
13800 crtc = crtc ? crtc : plane->crtc;
13801 intel_crtc = to_intel_crtc(crtc);
13802
13803 if (intel_crtc->cursor_bo == obj)
13804 goto update;
13805
13806 if (!obj)
13807 addr = 0;
13808 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13809 addr = i915_gem_obj_ggtt_offset(obj);
13810 else
13811 addr = obj->phys_handle->busaddr;
13812
13813 intel_crtc->cursor_addr = addr;
13814 intel_crtc->cursor_bo = obj;
13815
13816 update:
13817 if (crtc->state->active)
13818 intel_crtc_update_cursor(crtc, state->visible);
13819 }
13820
13821 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13822 int pipe)
13823 {
13824 struct intel_plane *cursor;
13825 struct intel_plane_state *state;
13826
13827 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13828 if (cursor == NULL)
13829 return NULL;
13830
13831 state = intel_create_plane_state(&cursor->base);
13832 if (!state) {
13833 kfree(cursor);
13834 return NULL;
13835 }
13836 cursor->base.state = &state->base;
13837
13838 cursor->can_scale = false;
13839 cursor->max_downscale = 1;
13840 cursor->pipe = pipe;
13841 cursor->plane = pipe;
13842 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13843 cursor->check_plane = intel_check_cursor_plane;
13844 cursor->commit_plane = intel_commit_cursor_plane;
13845 cursor->disable_plane = intel_disable_cursor_plane;
13846
13847 drm_universal_plane_init(dev, &cursor->base, 0,
13848 &intel_plane_funcs,
13849 intel_cursor_formats,
13850 ARRAY_SIZE(intel_cursor_formats),
13851 DRM_PLANE_TYPE_CURSOR);
13852
13853 if (INTEL_INFO(dev)->gen >= 4) {
13854 if (!dev->mode_config.rotation_property)
13855 dev->mode_config.rotation_property =
13856 drm_mode_create_rotation_property(dev,
13857 BIT(DRM_ROTATE_0) |
13858 BIT(DRM_ROTATE_180));
13859 if (dev->mode_config.rotation_property)
13860 drm_object_attach_property(&cursor->base.base,
13861 dev->mode_config.rotation_property,
13862 state->base.rotation);
13863 }
13864
13865 if (INTEL_INFO(dev)->gen >=9)
13866 state->scaler_id = -1;
13867
13868 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13869
13870 return &cursor->base;
13871 }
13872
13873 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13874 struct intel_crtc_state *crtc_state)
13875 {
13876 int i;
13877 struct intel_scaler *intel_scaler;
13878 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13879
13880 for (i = 0; i < intel_crtc->num_scalers; i++) {
13881 intel_scaler = &scaler_state->scalers[i];
13882 intel_scaler->in_use = 0;
13883 intel_scaler->mode = PS_SCALER_MODE_DYN;
13884 }
13885
13886 scaler_state->scaler_id = -1;
13887 }
13888
13889 static void intel_crtc_init(struct drm_device *dev, int pipe)
13890 {
13891 struct drm_i915_private *dev_priv = dev->dev_private;
13892 struct intel_crtc *intel_crtc;
13893 struct intel_crtc_state *crtc_state = NULL;
13894 struct drm_plane *primary = NULL;
13895 struct drm_plane *cursor = NULL;
13896 int i, ret;
13897
13898 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13899 if (intel_crtc == NULL)
13900 return;
13901
13902 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13903 if (!crtc_state)
13904 goto fail;
13905 intel_crtc->config = crtc_state;
13906 intel_crtc->base.state = &crtc_state->base;
13907 crtc_state->base.crtc = &intel_crtc->base;
13908
13909 /* initialize shared scalers */
13910 if (INTEL_INFO(dev)->gen >= 9) {
13911 if (pipe == PIPE_C)
13912 intel_crtc->num_scalers = 1;
13913 else
13914 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13915
13916 skl_init_scalers(dev, intel_crtc, crtc_state);
13917 }
13918
13919 primary = intel_primary_plane_create(dev, pipe);
13920 if (!primary)
13921 goto fail;
13922
13923 cursor = intel_cursor_plane_create(dev, pipe);
13924 if (!cursor)
13925 goto fail;
13926
13927 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13928 cursor, &intel_crtc_funcs);
13929 if (ret)
13930 goto fail;
13931
13932 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13933 for (i = 0; i < 256; i++) {
13934 intel_crtc->lut_r[i] = i;
13935 intel_crtc->lut_g[i] = i;
13936 intel_crtc->lut_b[i] = i;
13937 }
13938
13939 /*
13940 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13941 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13942 */
13943 intel_crtc->pipe = pipe;
13944 intel_crtc->plane = pipe;
13945 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13946 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13947 intel_crtc->plane = !pipe;
13948 }
13949
13950 intel_crtc->cursor_base = ~0;
13951 intel_crtc->cursor_cntl = ~0;
13952 intel_crtc->cursor_size = ~0;
13953
13954 intel_crtc->wm.cxsr_allowed = true;
13955
13956 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13957 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13958 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13959 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13960
13961 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13962
13963 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13964 return;
13965
13966 fail:
13967 if (primary)
13968 drm_plane_cleanup(primary);
13969 if (cursor)
13970 drm_plane_cleanup(cursor);
13971 kfree(crtc_state);
13972 kfree(intel_crtc);
13973 }
13974
13975 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13976 {
13977 struct drm_encoder *encoder = connector->base.encoder;
13978 struct drm_device *dev = connector->base.dev;
13979
13980 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13981
13982 if (!encoder || WARN_ON(!encoder->crtc))
13983 return INVALID_PIPE;
13984
13985 return to_intel_crtc(encoder->crtc)->pipe;
13986 }
13987
13988 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13989 struct drm_file *file)
13990 {
13991 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13992 struct drm_crtc *drmmode_crtc;
13993 struct intel_crtc *crtc;
13994
13995 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13996
13997 if (!drmmode_crtc) {
13998 DRM_ERROR("no such CRTC id\n");
13999 return -ENOENT;
14000 }
14001
14002 crtc = to_intel_crtc(drmmode_crtc);
14003 pipe_from_crtc_id->pipe = crtc->pipe;
14004
14005 return 0;
14006 }
14007
14008 static int intel_encoder_clones(struct intel_encoder *encoder)
14009 {
14010 struct drm_device *dev = encoder->base.dev;
14011 struct intel_encoder *source_encoder;
14012 int index_mask = 0;
14013 int entry = 0;
14014
14015 for_each_intel_encoder(dev, source_encoder) {
14016 if (encoders_cloneable(encoder, source_encoder))
14017 index_mask |= (1 << entry);
14018
14019 entry++;
14020 }
14021
14022 return index_mask;
14023 }
14024
14025 static bool has_edp_a(struct drm_device *dev)
14026 {
14027 struct drm_i915_private *dev_priv = dev->dev_private;
14028
14029 if (!IS_MOBILE(dev))
14030 return false;
14031
14032 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14033 return false;
14034
14035 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14036 return false;
14037
14038 return true;
14039 }
14040
14041 static bool intel_crt_present(struct drm_device *dev)
14042 {
14043 struct drm_i915_private *dev_priv = dev->dev_private;
14044
14045 if (INTEL_INFO(dev)->gen >= 9)
14046 return false;
14047
14048 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14049 return false;
14050
14051 if (IS_CHERRYVIEW(dev))
14052 return false;
14053
14054 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14055 return false;
14056
14057 return true;
14058 }
14059
14060 static void intel_setup_outputs(struct drm_device *dev)
14061 {
14062 struct drm_i915_private *dev_priv = dev->dev_private;
14063 struct intel_encoder *encoder;
14064 bool dpd_is_edp = false;
14065
14066 intel_lvds_init(dev);
14067
14068 if (intel_crt_present(dev))
14069 intel_crt_init(dev);
14070
14071 if (IS_BROXTON(dev)) {
14072 /*
14073 * FIXME: Broxton doesn't support port detection via the
14074 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14075 * detect the ports.
14076 */
14077 intel_ddi_init(dev, PORT_A);
14078 intel_ddi_init(dev, PORT_B);
14079 intel_ddi_init(dev, PORT_C);
14080 } else if (HAS_DDI(dev)) {
14081 int found;
14082
14083 /*
14084 * Haswell uses DDI functions to detect digital outputs.
14085 * On SKL pre-D0 the strap isn't connected, so we assume
14086 * it's there.
14087 */
14088 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14089 /* WaIgnoreDDIAStrap: skl */
14090 if (found || IS_SKYLAKE(dev))
14091 intel_ddi_init(dev, PORT_A);
14092
14093 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14094 * register */
14095 found = I915_READ(SFUSE_STRAP);
14096
14097 if (found & SFUSE_STRAP_DDIB_DETECTED)
14098 intel_ddi_init(dev, PORT_B);
14099 if (found & SFUSE_STRAP_DDIC_DETECTED)
14100 intel_ddi_init(dev, PORT_C);
14101 if (found & SFUSE_STRAP_DDID_DETECTED)
14102 intel_ddi_init(dev, PORT_D);
14103 /*
14104 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14105 */
14106 if (IS_SKYLAKE(dev) &&
14107 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14108 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14109 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14110 intel_ddi_init(dev, PORT_E);
14111
14112 } else if (HAS_PCH_SPLIT(dev)) {
14113 int found;
14114 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14115
14116 if (has_edp_a(dev))
14117 intel_dp_init(dev, DP_A, PORT_A);
14118
14119 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14120 /* PCH SDVOB multiplex with HDMIB */
14121 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14122 if (!found)
14123 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14124 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14125 intel_dp_init(dev, PCH_DP_B, PORT_B);
14126 }
14127
14128 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14129 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14130
14131 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14132 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14133
14134 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14135 intel_dp_init(dev, PCH_DP_C, PORT_C);
14136
14137 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14138 intel_dp_init(dev, PCH_DP_D, PORT_D);
14139 } else if (IS_VALLEYVIEW(dev)) {
14140 /*
14141 * The DP_DETECTED bit is the latched state of the DDC
14142 * SDA pin at boot. However since eDP doesn't require DDC
14143 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14144 * eDP ports may have been muxed to an alternate function.
14145 * Thus we can't rely on the DP_DETECTED bit alone to detect
14146 * eDP ports. Consult the VBT as well as DP_DETECTED to
14147 * detect eDP ports.
14148 */
14149 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14150 !intel_dp_is_edp(dev, PORT_B))
14151 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14152 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14153 intel_dp_is_edp(dev, PORT_B))
14154 intel_dp_init(dev, VLV_DP_B, PORT_B);
14155
14156 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14157 !intel_dp_is_edp(dev, PORT_C))
14158 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14159 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14160 intel_dp_is_edp(dev, PORT_C))
14161 intel_dp_init(dev, VLV_DP_C, PORT_C);
14162
14163 if (IS_CHERRYVIEW(dev)) {
14164 /* eDP not supported on port D, so don't check VBT */
14165 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14166 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14167 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14168 intel_dp_init(dev, CHV_DP_D, PORT_D);
14169 }
14170
14171 intel_dsi_init(dev);
14172 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14173 bool found = false;
14174
14175 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14176 DRM_DEBUG_KMS("probing SDVOB\n");
14177 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14178 if (!found && IS_G4X(dev)) {
14179 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14180 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14181 }
14182
14183 if (!found && IS_G4X(dev))
14184 intel_dp_init(dev, DP_B, PORT_B);
14185 }
14186
14187 /* Before G4X SDVOC doesn't have its own detect register */
14188
14189 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14190 DRM_DEBUG_KMS("probing SDVOC\n");
14191 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14192 }
14193
14194 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14195
14196 if (IS_G4X(dev)) {
14197 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14198 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14199 }
14200 if (IS_G4X(dev))
14201 intel_dp_init(dev, DP_C, PORT_C);
14202 }
14203
14204 if (IS_G4X(dev) &&
14205 (I915_READ(DP_D) & DP_DETECTED))
14206 intel_dp_init(dev, DP_D, PORT_D);
14207 } else if (IS_GEN2(dev))
14208 intel_dvo_init(dev);
14209
14210 if (SUPPORTS_TV(dev))
14211 intel_tv_init(dev);
14212
14213 intel_psr_init(dev);
14214
14215 for_each_intel_encoder(dev, encoder) {
14216 encoder->base.possible_crtcs = encoder->crtc_mask;
14217 encoder->base.possible_clones =
14218 intel_encoder_clones(encoder);
14219 }
14220
14221 intel_init_pch_refclk(dev);
14222
14223 drm_helper_move_panel_connectors_to_head(dev);
14224 }
14225
14226 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14227 {
14228 struct drm_device *dev = fb->dev;
14229 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14230
14231 drm_framebuffer_cleanup(fb);
14232 mutex_lock(&dev->struct_mutex);
14233 WARN_ON(!intel_fb->obj->framebuffer_references--);
14234 drm_gem_object_unreference(&intel_fb->obj->base);
14235 mutex_unlock(&dev->struct_mutex);
14236 kfree(intel_fb);
14237 }
14238
14239 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14240 struct drm_file *file,
14241 unsigned int *handle)
14242 {
14243 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14244 struct drm_i915_gem_object *obj = intel_fb->obj;
14245
14246 return drm_gem_handle_create(file, &obj->base, handle);
14247 }
14248
14249 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14250 struct drm_file *file,
14251 unsigned flags, unsigned color,
14252 struct drm_clip_rect *clips,
14253 unsigned num_clips)
14254 {
14255 struct drm_device *dev = fb->dev;
14256 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14257 struct drm_i915_gem_object *obj = intel_fb->obj;
14258
14259 mutex_lock(&dev->struct_mutex);
14260 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14261 mutex_unlock(&dev->struct_mutex);
14262
14263 return 0;
14264 }
14265
14266 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14267 .destroy = intel_user_framebuffer_destroy,
14268 .create_handle = intel_user_framebuffer_create_handle,
14269 .dirty = intel_user_framebuffer_dirty,
14270 };
14271
14272 static
14273 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14274 uint32_t pixel_format)
14275 {
14276 u32 gen = INTEL_INFO(dev)->gen;
14277
14278 if (gen >= 9) {
14279 /* "The stride in bytes must not exceed the of the size of 8K
14280 * pixels and 32K bytes."
14281 */
14282 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14283 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14284 return 32*1024;
14285 } else if (gen >= 4) {
14286 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14287 return 16*1024;
14288 else
14289 return 32*1024;
14290 } else if (gen >= 3) {
14291 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14292 return 8*1024;
14293 else
14294 return 16*1024;
14295 } else {
14296 /* XXX DSPC is limited to 4k tiled */
14297 return 8*1024;
14298 }
14299 }
14300
14301 static int intel_framebuffer_init(struct drm_device *dev,
14302 struct intel_framebuffer *intel_fb,
14303 struct drm_mode_fb_cmd2 *mode_cmd,
14304 struct drm_i915_gem_object *obj)
14305 {
14306 unsigned int aligned_height;
14307 int ret;
14308 u32 pitch_limit, stride_alignment;
14309
14310 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14311
14312 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14313 /* Enforce that fb modifier and tiling mode match, but only for
14314 * X-tiled. This is needed for FBC. */
14315 if (!!(obj->tiling_mode == I915_TILING_X) !=
14316 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14317 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14318 return -EINVAL;
14319 }
14320 } else {
14321 if (obj->tiling_mode == I915_TILING_X)
14322 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14323 else if (obj->tiling_mode == I915_TILING_Y) {
14324 DRM_DEBUG("No Y tiling for legacy addfb\n");
14325 return -EINVAL;
14326 }
14327 }
14328
14329 /* Passed in modifier sanity checking. */
14330 switch (mode_cmd->modifier[0]) {
14331 case I915_FORMAT_MOD_Y_TILED:
14332 case I915_FORMAT_MOD_Yf_TILED:
14333 if (INTEL_INFO(dev)->gen < 9) {
14334 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14335 mode_cmd->modifier[0]);
14336 return -EINVAL;
14337 }
14338 case DRM_FORMAT_MOD_NONE:
14339 case I915_FORMAT_MOD_X_TILED:
14340 break;
14341 default:
14342 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14343 mode_cmd->modifier[0]);
14344 return -EINVAL;
14345 }
14346
14347 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14348 mode_cmd->pixel_format);
14349 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14350 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14351 mode_cmd->pitches[0], stride_alignment);
14352 return -EINVAL;
14353 }
14354
14355 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14356 mode_cmd->pixel_format);
14357 if (mode_cmd->pitches[0] > pitch_limit) {
14358 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14359 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14360 "tiled" : "linear",
14361 mode_cmd->pitches[0], pitch_limit);
14362 return -EINVAL;
14363 }
14364
14365 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14366 mode_cmd->pitches[0] != obj->stride) {
14367 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14368 mode_cmd->pitches[0], obj->stride);
14369 return -EINVAL;
14370 }
14371
14372 /* Reject formats not supported by any plane early. */
14373 switch (mode_cmd->pixel_format) {
14374 case DRM_FORMAT_C8:
14375 case DRM_FORMAT_RGB565:
14376 case DRM_FORMAT_XRGB8888:
14377 case DRM_FORMAT_ARGB8888:
14378 break;
14379 case DRM_FORMAT_XRGB1555:
14380 if (INTEL_INFO(dev)->gen > 3) {
14381 DRM_DEBUG("unsupported pixel format: %s\n",
14382 drm_get_format_name(mode_cmd->pixel_format));
14383 return -EINVAL;
14384 }
14385 break;
14386 case DRM_FORMAT_ABGR8888:
14387 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14388 DRM_DEBUG("unsupported pixel format: %s\n",
14389 drm_get_format_name(mode_cmd->pixel_format));
14390 return -EINVAL;
14391 }
14392 break;
14393 case DRM_FORMAT_XBGR8888:
14394 case DRM_FORMAT_XRGB2101010:
14395 case DRM_FORMAT_XBGR2101010:
14396 if (INTEL_INFO(dev)->gen < 4) {
14397 DRM_DEBUG("unsupported pixel format: %s\n",
14398 drm_get_format_name(mode_cmd->pixel_format));
14399 return -EINVAL;
14400 }
14401 break;
14402 case DRM_FORMAT_ABGR2101010:
14403 if (!IS_VALLEYVIEW(dev)) {
14404 DRM_DEBUG("unsupported pixel format: %s\n",
14405 drm_get_format_name(mode_cmd->pixel_format));
14406 return -EINVAL;
14407 }
14408 break;
14409 case DRM_FORMAT_YUYV:
14410 case DRM_FORMAT_UYVY:
14411 case DRM_FORMAT_YVYU:
14412 case DRM_FORMAT_VYUY:
14413 if (INTEL_INFO(dev)->gen < 5) {
14414 DRM_DEBUG("unsupported pixel format: %s\n",
14415 drm_get_format_name(mode_cmd->pixel_format));
14416 return -EINVAL;
14417 }
14418 break;
14419 default:
14420 DRM_DEBUG("unsupported pixel format: %s\n",
14421 drm_get_format_name(mode_cmd->pixel_format));
14422 return -EINVAL;
14423 }
14424
14425 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14426 if (mode_cmd->offsets[0] != 0)
14427 return -EINVAL;
14428
14429 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14430 mode_cmd->pixel_format,
14431 mode_cmd->modifier[0]);
14432 /* FIXME drm helper for size checks (especially planar formats)? */
14433 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14434 return -EINVAL;
14435
14436 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14437 intel_fb->obj = obj;
14438 intel_fb->obj->framebuffer_references++;
14439
14440 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14441 if (ret) {
14442 DRM_ERROR("framebuffer init failed %d\n", ret);
14443 return ret;
14444 }
14445
14446 return 0;
14447 }
14448
14449 static struct drm_framebuffer *
14450 intel_user_framebuffer_create(struct drm_device *dev,
14451 struct drm_file *filp,
14452 struct drm_mode_fb_cmd2 *mode_cmd)
14453 {
14454 struct drm_i915_gem_object *obj;
14455
14456 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14457 mode_cmd->handles[0]));
14458 if (&obj->base == NULL)
14459 return ERR_PTR(-ENOENT);
14460
14461 return intel_framebuffer_create(dev, mode_cmd, obj);
14462 }
14463
14464 #ifndef CONFIG_DRM_FBDEV_EMULATION
14465 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14466 {
14467 }
14468 #endif
14469
14470 static const struct drm_mode_config_funcs intel_mode_funcs = {
14471 .fb_create = intel_user_framebuffer_create,
14472 .output_poll_changed = intel_fbdev_output_poll_changed,
14473 .atomic_check = intel_atomic_check,
14474 .atomic_commit = intel_atomic_commit,
14475 .atomic_state_alloc = intel_atomic_state_alloc,
14476 .atomic_state_clear = intel_atomic_state_clear,
14477 };
14478
14479 /* Set up chip specific display functions */
14480 static void intel_init_display(struct drm_device *dev)
14481 {
14482 struct drm_i915_private *dev_priv = dev->dev_private;
14483
14484 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14485 dev_priv->display.find_dpll = g4x_find_best_dpll;
14486 else if (IS_CHERRYVIEW(dev))
14487 dev_priv->display.find_dpll = chv_find_best_dpll;
14488 else if (IS_VALLEYVIEW(dev))
14489 dev_priv->display.find_dpll = vlv_find_best_dpll;
14490 else if (IS_PINEVIEW(dev))
14491 dev_priv->display.find_dpll = pnv_find_best_dpll;
14492 else
14493 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14494
14495 if (INTEL_INFO(dev)->gen >= 9) {
14496 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14497 dev_priv->display.get_initial_plane_config =
14498 skylake_get_initial_plane_config;
14499 dev_priv->display.crtc_compute_clock =
14500 haswell_crtc_compute_clock;
14501 dev_priv->display.crtc_enable = haswell_crtc_enable;
14502 dev_priv->display.crtc_disable = haswell_crtc_disable;
14503 dev_priv->display.update_primary_plane =
14504 skylake_update_primary_plane;
14505 } else if (HAS_DDI(dev)) {
14506 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14507 dev_priv->display.get_initial_plane_config =
14508 ironlake_get_initial_plane_config;
14509 dev_priv->display.crtc_compute_clock =
14510 haswell_crtc_compute_clock;
14511 dev_priv->display.crtc_enable = haswell_crtc_enable;
14512 dev_priv->display.crtc_disable = haswell_crtc_disable;
14513 dev_priv->display.update_primary_plane =
14514 ironlake_update_primary_plane;
14515 } else if (HAS_PCH_SPLIT(dev)) {
14516 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14517 dev_priv->display.get_initial_plane_config =
14518 ironlake_get_initial_plane_config;
14519 dev_priv->display.crtc_compute_clock =
14520 ironlake_crtc_compute_clock;
14521 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14522 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14523 dev_priv->display.update_primary_plane =
14524 ironlake_update_primary_plane;
14525 } else if (IS_VALLEYVIEW(dev)) {
14526 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14527 dev_priv->display.get_initial_plane_config =
14528 i9xx_get_initial_plane_config;
14529 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14530 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14531 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14532 dev_priv->display.update_primary_plane =
14533 i9xx_update_primary_plane;
14534 } else {
14535 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14536 dev_priv->display.get_initial_plane_config =
14537 i9xx_get_initial_plane_config;
14538 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14539 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14540 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14541 dev_priv->display.update_primary_plane =
14542 i9xx_update_primary_plane;
14543 }
14544
14545 /* Returns the core display clock speed */
14546 if (IS_SKYLAKE(dev))
14547 dev_priv->display.get_display_clock_speed =
14548 skylake_get_display_clock_speed;
14549 else if (IS_BROXTON(dev))
14550 dev_priv->display.get_display_clock_speed =
14551 broxton_get_display_clock_speed;
14552 else if (IS_BROADWELL(dev))
14553 dev_priv->display.get_display_clock_speed =
14554 broadwell_get_display_clock_speed;
14555 else if (IS_HASWELL(dev))
14556 dev_priv->display.get_display_clock_speed =
14557 haswell_get_display_clock_speed;
14558 else if (IS_VALLEYVIEW(dev))
14559 dev_priv->display.get_display_clock_speed =
14560 valleyview_get_display_clock_speed;
14561 else if (IS_GEN5(dev))
14562 dev_priv->display.get_display_clock_speed =
14563 ilk_get_display_clock_speed;
14564 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14565 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14566 dev_priv->display.get_display_clock_speed =
14567 i945_get_display_clock_speed;
14568 else if (IS_GM45(dev))
14569 dev_priv->display.get_display_clock_speed =
14570 gm45_get_display_clock_speed;
14571 else if (IS_CRESTLINE(dev))
14572 dev_priv->display.get_display_clock_speed =
14573 i965gm_get_display_clock_speed;
14574 else if (IS_PINEVIEW(dev))
14575 dev_priv->display.get_display_clock_speed =
14576 pnv_get_display_clock_speed;
14577 else if (IS_G33(dev) || IS_G4X(dev))
14578 dev_priv->display.get_display_clock_speed =
14579 g33_get_display_clock_speed;
14580 else if (IS_I915G(dev))
14581 dev_priv->display.get_display_clock_speed =
14582 i915_get_display_clock_speed;
14583 else if (IS_I945GM(dev) || IS_845G(dev))
14584 dev_priv->display.get_display_clock_speed =
14585 i9xx_misc_get_display_clock_speed;
14586 else if (IS_PINEVIEW(dev))
14587 dev_priv->display.get_display_clock_speed =
14588 pnv_get_display_clock_speed;
14589 else if (IS_I915GM(dev))
14590 dev_priv->display.get_display_clock_speed =
14591 i915gm_get_display_clock_speed;
14592 else if (IS_I865G(dev))
14593 dev_priv->display.get_display_clock_speed =
14594 i865_get_display_clock_speed;
14595 else if (IS_I85X(dev))
14596 dev_priv->display.get_display_clock_speed =
14597 i85x_get_display_clock_speed;
14598 else { /* 830 */
14599 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14600 dev_priv->display.get_display_clock_speed =
14601 i830_get_display_clock_speed;
14602 }
14603
14604 if (IS_GEN5(dev)) {
14605 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14606 } else if (IS_GEN6(dev)) {
14607 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14608 } else if (IS_IVYBRIDGE(dev)) {
14609 /* FIXME: detect B0+ stepping and use auto training */
14610 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14611 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14612 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14613 if (IS_BROADWELL(dev)) {
14614 dev_priv->display.modeset_commit_cdclk =
14615 broadwell_modeset_commit_cdclk;
14616 dev_priv->display.modeset_calc_cdclk =
14617 broadwell_modeset_calc_cdclk;
14618 }
14619 } else if (IS_VALLEYVIEW(dev)) {
14620 dev_priv->display.modeset_commit_cdclk =
14621 valleyview_modeset_commit_cdclk;
14622 dev_priv->display.modeset_calc_cdclk =
14623 valleyview_modeset_calc_cdclk;
14624 } else if (IS_BROXTON(dev)) {
14625 dev_priv->display.modeset_commit_cdclk =
14626 broxton_modeset_commit_cdclk;
14627 dev_priv->display.modeset_calc_cdclk =
14628 broxton_modeset_calc_cdclk;
14629 }
14630
14631 switch (INTEL_INFO(dev)->gen) {
14632 case 2:
14633 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14634 break;
14635
14636 case 3:
14637 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14638 break;
14639
14640 case 4:
14641 case 5:
14642 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14643 break;
14644
14645 case 6:
14646 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14647 break;
14648 case 7:
14649 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14650 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14651 break;
14652 case 9:
14653 /* Drop through - unsupported since execlist only. */
14654 default:
14655 /* Default just returns -ENODEV to indicate unsupported */
14656 dev_priv->display.queue_flip = intel_default_queue_flip;
14657 }
14658
14659 mutex_init(&dev_priv->pps_mutex);
14660 }
14661
14662 /*
14663 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14664 * resume, or other times. This quirk makes sure that's the case for
14665 * affected systems.
14666 */
14667 static void quirk_pipea_force(struct drm_device *dev)
14668 {
14669 struct drm_i915_private *dev_priv = dev->dev_private;
14670
14671 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14672 DRM_INFO("applying pipe a force quirk\n");
14673 }
14674
14675 static void quirk_pipeb_force(struct drm_device *dev)
14676 {
14677 struct drm_i915_private *dev_priv = dev->dev_private;
14678
14679 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14680 DRM_INFO("applying pipe b force quirk\n");
14681 }
14682
14683 /*
14684 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14685 */
14686 static void quirk_ssc_force_disable(struct drm_device *dev)
14687 {
14688 struct drm_i915_private *dev_priv = dev->dev_private;
14689 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14690 DRM_INFO("applying lvds SSC disable quirk\n");
14691 }
14692
14693 /*
14694 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14695 * brightness value
14696 */
14697 static void quirk_invert_brightness(struct drm_device *dev)
14698 {
14699 struct drm_i915_private *dev_priv = dev->dev_private;
14700 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14701 DRM_INFO("applying inverted panel brightness quirk\n");
14702 }
14703
14704 /* Some VBT's incorrectly indicate no backlight is present */
14705 static void quirk_backlight_present(struct drm_device *dev)
14706 {
14707 struct drm_i915_private *dev_priv = dev->dev_private;
14708 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14709 DRM_INFO("applying backlight present quirk\n");
14710 }
14711
14712 struct intel_quirk {
14713 int device;
14714 int subsystem_vendor;
14715 int subsystem_device;
14716 void (*hook)(struct drm_device *dev);
14717 };
14718
14719 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14720 struct intel_dmi_quirk {
14721 void (*hook)(struct drm_device *dev);
14722 const struct dmi_system_id (*dmi_id_list)[];
14723 };
14724
14725 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14726 {
14727 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14728 return 1;
14729 }
14730
14731 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14732 {
14733 .dmi_id_list = &(const struct dmi_system_id[]) {
14734 {
14735 .callback = intel_dmi_reverse_brightness,
14736 .ident = "NCR Corporation",
14737 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14738 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14739 },
14740 },
14741 { } /* terminating entry */
14742 },
14743 .hook = quirk_invert_brightness,
14744 },
14745 };
14746
14747 static struct intel_quirk intel_quirks[] = {
14748 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14749 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14750
14751 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14752 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14753
14754 /* 830 needs to leave pipe A & dpll A up */
14755 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14756
14757 /* 830 needs to leave pipe B & dpll B up */
14758 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14759
14760 /* Lenovo U160 cannot use SSC on LVDS */
14761 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14762
14763 /* Sony Vaio Y cannot use SSC on LVDS */
14764 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14765
14766 /* Acer Aspire 5734Z must invert backlight brightness */
14767 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14768
14769 /* Acer/eMachines G725 */
14770 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14771
14772 /* Acer/eMachines e725 */
14773 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14774
14775 /* Acer/Packard Bell NCL20 */
14776 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14777
14778 /* Acer Aspire 4736Z */
14779 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14780
14781 /* Acer Aspire 5336 */
14782 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14783
14784 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14785 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14786
14787 /* Acer C720 Chromebook (Core i3 4005U) */
14788 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14789
14790 /* Apple Macbook 2,1 (Core 2 T7400) */
14791 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14792
14793 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14794 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14795
14796 /* HP Chromebook 14 (Celeron 2955U) */
14797 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14798
14799 /* Dell Chromebook 11 */
14800 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14801 };
14802
14803 static void intel_init_quirks(struct drm_device *dev)
14804 {
14805 struct pci_dev *d = dev->pdev;
14806 int i;
14807
14808 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14809 struct intel_quirk *q = &intel_quirks[i];
14810
14811 if (d->device == q->device &&
14812 (d->subsystem_vendor == q->subsystem_vendor ||
14813 q->subsystem_vendor == PCI_ANY_ID) &&
14814 (d->subsystem_device == q->subsystem_device ||
14815 q->subsystem_device == PCI_ANY_ID))
14816 q->hook(dev);
14817 }
14818 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14819 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14820 intel_dmi_quirks[i].hook(dev);
14821 }
14822 }
14823
14824 /* Disable the VGA plane that we never use */
14825 static void i915_disable_vga(struct drm_device *dev)
14826 {
14827 struct drm_i915_private *dev_priv = dev->dev_private;
14828 u8 sr1;
14829 u32 vga_reg = i915_vgacntrl_reg(dev);
14830
14831 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14832 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14833 outb(SR01, VGA_SR_INDEX);
14834 sr1 = inb(VGA_SR_DATA);
14835 outb(sr1 | 1<<5, VGA_SR_DATA);
14836 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14837 udelay(300);
14838
14839 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14840 POSTING_READ(vga_reg);
14841 }
14842
14843 void intel_modeset_init_hw(struct drm_device *dev)
14844 {
14845 intel_update_cdclk(dev);
14846 intel_prepare_ddi(dev);
14847 intel_init_clock_gating(dev);
14848 intel_enable_gt_powersave(dev);
14849 }
14850
14851 void intel_modeset_init(struct drm_device *dev)
14852 {
14853 struct drm_i915_private *dev_priv = dev->dev_private;
14854 int sprite, ret;
14855 enum pipe pipe;
14856 struct intel_crtc *crtc;
14857
14858 drm_mode_config_init(dev);
14859
14860 dev->mode_config.min_width = 0;
14861 dev->mode_config.min_height = 0;
14862
14863 dev->mode_config.preferred_depth = 24;
14864 dev->mode_config.prefer_shadow = 1;
14865
14866 dev->mode_config.allow_fb_modifiers = true;
14867
14868 dev->mode_config.funcs = &intel_mode_funcs;
14869
14870 intel_init_quirks(dev);
14871
14872 intel_init_pm(dev);
14873
14874 if (INTEL_INFO(dev)->num_pipes == 0)
14875 return;
14876
14877 /*
14878 * There may be no VBT; and if the BIOS enabled SSC we can
14879 * just keep using it to avoid unnecessary flicker. Whereas if the
14880 * BIOS isn't using it, don't assume it will work even if the VBT
14881 * indicates as much.
14882 */
14883 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14884 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14885 DREF_SSC1_ENABLE);
14886
14887 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14888 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14889 bios_lvds_use_ssc ? "en" : "dis",
14890 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14891 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14892 }
14893 }
14894
14895 intel_init_display(dev);
14896 intel_init_audio(dev);
14897
14898 if (IS_GEN2(dev)) {
14899 dev->mode_config.max_width = 2048;
14900 dev->mode_config.max_height = 2048;
14901 } else if (IS_GEN3(dev)) {
14902 dev->mode_config.max_width = 4096;
14903 dev->mode_config.max_height = 4096;
14904 } else {
14905 dev->mode_config.max_width = 8192;
14906 dev->mode_config.max_height = 8192;
14907 }
14908
14909 if (IS_845G(dev) || IS_I865G(dev)) {
14910 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14911 dev->mode_config.cursor_height = 1023;
14912 } else if (IS_GEN2(dev)) {
14913 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14914 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14915 } else {
14916 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14917 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14918 }
14919
14920 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14921
14922 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14923 INTEL_INFO(dev)->num_pipes,
14924 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14925
14926 for_each_pipe(dev_priv, pipe) {
14927 intel_crtc_init(dev, pipe);
14928 for_each_sprite(dev_priv, pipe, sprite) {
14929 ret = intel_plane_init(dev, pipe, sprite);
14930 if (ret)
14931 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14932 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14933 }
14934 }
14935
14936 intel_update_czclk(dev_priv);
14937 intel_update_cdclk(dev);
14938
14939 intel_shared_dpll_init(dev);
14940
14941 /* Just disable it once at startup */
14942 i915_disable_vga(dev);
14943 intel_setup_outputs(dev);
14944
14945 /* Just in case the BIOS is doing something questionable. */
14946 intel_fbc_disable(dev_priv);
14947
14948 drm_modeset_lock_all(dev);
14949 intel_modeset_setup_hw_state(dev);
14950 drm_modeset_unlock_all(dev);
14951
14952 for_each_intel_crtc(dev, crtc) {
14953 struct intel_initial_plane_config plane_config = {};
14954
14955 if (!crtc->active)
14956 continue;
14957
14958 /*
14959 * Note that reserving the BIOS fb up front prevents us
14960 * from stuffing other stolen allocations like the ring
14961 * on top. This prevents some ugliness at boot time, and
14962 * can even allow for smooth boot transitions if the BIOS
14963 * fb is large enough for the active pipe configuration.
14964 */
14965 dev_priv->display.get_initial_plane_config(crtc,
14966 &plane_config);
14967
14968 /*
14969 * If the fb is shared between multiple heads, we'll
14970 * just get the first one.
14971 */
14972 intel_find_initial_plane_obj(crtc, &plane_config);
14973 }
14974 }
14975
14976 static void intel_enable_pipe_a(struct drm_device *dev)
14977 {
14978 struct intel_connector *connector;
14979 struct drm_connector *crt = NULL;
14980 struct intel_load_detect_pipe load_detect_temp;
14981 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14982
14983 /* We can't just switch on the pipe A, we need to set things up with a
14984 * proper mode and output configuration. As a gross hack, enable pipe A
14985 * by enabling the load detect pipe once. */
14986 for_each_intel_connector(dev, connector) {
14987 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14988 crt = &connector->base;
14989 break;
14990 }
14991 }
14992
14993 if (!crt)
14994 return;
14995
14996 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14997 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14998 }
14999
15000 static bool
15001 intel_check_plane_mapping(struct intel_crtc *crtc)
15002 {
15003 struct drm_device *dev = crtc->base.dev;
15004 struct drm_i915_private *dev_priv = dev->dev_private;
15005 u32 reg, val;
15006
15007 if (INTEL_INFO(dev)->num_pipes == 1)
15008 return true;
15009
15010 reg = DSPCNTR(!crtc->plane);
15011 val = I915_READ(reg);
15012
15013 if ((val & DISPLAY_PLANE_ENABLE) &&
15014 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15015 return false;
15016
15017 return true;
15018 }
15019
15020 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15021 {
15022 struct drm_device *dev = crtc->base.dev;
15023 struct intel_encoder *encoder;
15024
15025 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15026 return true;
15027
15028 return false;
15029 }
15030
15031 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15032 {
15033 struct drm_device *dev = crtc->base.dev;
15034 struct drm_i915_private *dev_priv = dev->dev_private;
15035 u32 reg;
15036
15037 /* Clear any frame start delays used for debugging left by the BIOS */
15038 reg = PIPECONF(crtc->config->cpu_transcoder);
15039 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15040
15041 /* restore vblank interrupts to correct state */
15042 drm_crtc_vblank_reset(&crtc->base);
15043 if (crtc->active) {
15044 struct intel_plane *plane;
15045
15046 drm_crtc_vblank_on(&crtc->base);
15047
15048 /* Disable everything but the primary plane */
15049 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15050 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15051 continue;
15052
15053 plane->disable_plane(&plane->base, &crtc->base);
15054 }
15055 }
15056
15057 /* We need to sanitize the plane -> pipe mapping first because this will
15058 * disable the crtc (and hence change the state) if it is wrong. Note
15059 * that gen4+ has a fixed plane -> pipe mapping. */
15060 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15061 bool plane;
15062
15063 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15064 crtc->base.base.id);
15065
15066 /* Pipe has the wrong plane attached and the plane is active.
15067 * Temporarily change the plane mapping and disable everything
15068 * ... */
15069 plane = crtc->plane;
15070 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15071 crtc->plane = !plane;
15072 intel_crtc_disable_noatomic(&crtc->base);
15073 crtc->plane = plane;
15074 }
15075
15076 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15077 crtc->pipe == PIPE_A && !crtc->active) {
15078 /* BIOS forgot to enable pipe A, this mostly happens after
15079 * resume. Force-enable the pipe to fix this, the update_dpms
15080 * call below we restore the pipe to the right state, but leave
15081 * the required bits on. */
15082 intel_enable_pipe_a(dev);
15083 }
15084
15085 /* Adjust the state of the output pipe according to whether we
15086 * have active connectors/encoders. */
15087 if (!intel_crtc_has_encoders(crtc))
15088 intel_crtc_disable_noatomic(&crtc->base);
15089
15090 if (crtc->active != crtc->base.state->active) {
15091 struct intel_encoder *encoder;
15092
15093 /* This can happen either due to bugs in the get_hw_state
15094 * functions or because of calls to intel_crtc_disable_noatomic,
15095 * or because the pipe is force-enabled due to the
15096 * pipe A quirk. */
15097 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15098 crtc->base.base.id,
15099 crtc->base.state->enable ? "enabled" : "disabled",
15100 crtc->active ? "enabled" : "disabled");
15101
15102 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15103 crtc->base.state->active = crtc->active;
15104 crtc->base.enabled = crtc->active;
15105
15106 /* Because we only establish the connector -> encoder ->
15107 * crtc links if something is active, this means the
15108 * crtc is now deactivated. Break the links. connector
15109 * -> encoder links are only establish when things are
15110 * actually up, hence no need to break them. */
15111 WARN_ON(crtc->active);
15112
15113 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15114 encoder->base.crtc = NULL;
15115 }
15116
15117 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15118 /*
15119 * We start out with underrun reporting disabled to avoid races.
15120 * For correct bookkeeping mark this on active crtcs.
15121 *
15122 * Also on gmch platforms we dont have any hardware bits to
15123 * disable the underrun reporting. Which means we need to start
15124 * out with underrun reporting disabled also on inactive pipes,
15125 * since otherwise we'll complain about the garbage we read when
15126 * e.g. coming up after runtime pm.
15127 *
15128 * No protection against concurrent access is required - at
15129 * worst a fifo underrun happens which also sets this to false.
15130 */
15131 crtc->cpu_fifo_underrun_disabled = true;
15132 crtc->pch_fifo_underrun_disabled = true;
15133 }
15134 }
15135
15136 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15137 {
15138 struct intel_connector *connector;
15139 struct drm_device *dev = encoder->base.dev;
15140 bool active = false;
15141
15142 /* We need to check both for a crtc link (meaning that the
15143 * encoder is active and trying to read from a pipe) and the
15144 * pipe itself being active. */
15145 bool has_active_crtc = encoder->base.crtc &&
15146 to_intel_crtc(encoder->base.crtc)->active;
15147
15148 for_each_intel_connector(dev, connector) {
15149 if (connector->base.encoder != &encoder->base)
15150 continue;
15151
15152 active = true;
15153 break;
15154 }
15155
15156 if (active && !has_active_crtc) {
15157 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15158 encoder->base.base.id,
15159 encoder->base.name);
15160
15161 /* Connector is active, but has no active pipe. This is
15162 * fallout from our resume register restoring. Disable
15163 * the encoder manually again. */
15164 if (encoder->base.crtc) {
15165 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15166 encoder->base.base.id,
15167 encoder->base.name);
15168 encoder->disable(encoder);
15169 if (encoder->post_disable)
15170 encoder->post_disable(encoder);
15171 }
15172 encoder->base.crtc = NULL;
15173
15174 /* Inconsistent output/port/pipe state happens presumably due to
15175 * a bug in one of the get_hw_state functions. Or someplace else
15176 * in our code, like the register restore mess on resume. Clamp
15177 * things to off as a safer default. */
15178 for_each_intel_connector(dev, connector) {
15179 if (connector->encoder != encoder)
15180 continue;
15181 connector->base.dpms = DRM_MODE_DPMS_OFF;
15182 connector->base.encoder = NULL;
15183 }
15184 }
15185 /* Enabled encoders without active connectors will be fixed in
15186 * the crtc fixup. */
15187 }
15188
15189 void i915_redisable_vga_power_on(struct drm_device *dev)
15190 {
15191 struct drm_i915_private *dev_priv = dev->dev_private;
15192 u32 vga_reg = i915_vgacntrl_reg(dev);
15193
15194 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15195 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15196 i915_disable_vga(dev);
15197 }
15198 }
15199
15200 void i915_redisable_vga(struct drm_device *dev)
15201 {
15202 struct drm_i915_private *dev_priv = dev->dev_private;
15203
15204 /* This function can be called both from intel_modeset_setup_hw_state or
15205 * at a very early point in our resume sequence, where the power well
15206 * structures are not yet restored. Since this function is at a very
15207 * paranoid "someone might have enabled VGA while we were not looking"
15208 * level, just check if the power well is enabled instead of trying to
15209 * follow the "don't touch the power well if we don't need it" policy
15210 * the rest of the driver uses. */
15211 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15212 return;
15213
15214 i915_redisable_vga_power_on(dev);
15215 }
15216
15217 static bool primary_get_hw_state(struct intel_plane *plane)
15218 {
15219 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15220
15221 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15222 }
15223
15224 /* FIXME read out full plane state for all planes */
15225 static void readout_plane_state(struct intel_crtc *crtc)
15226 {
15227 struct drm_plane *primary = crtc->base.primary;
15228 struct intel_plane_state *plane_state =
15229 to_intel_plane_state(primary->state);
15230
15231 plane_state->visible = crtc->active &&
15232 primary_get_hw_state(to_intel_plane(primary));
15233
15234 if (plane_state->visible)
15235 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15236 }
15237
15238 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15239 {
15240 struct drm_i915_private *dev_priv = dev->dev_private;
15241 enum pipe pipe;
15242 struct intel_crtc *crtc;
15243 struct intel_encoder *encoder;
15244 struct intel_connector *connector;
15245 int i;
15246
15247 for_each_intel_crtc(dev, crtc) {
15248 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15249 memset(crtc->config, 0, sizeof(*crtc->config));
15250 crtc->config->base.crtc = &crtc->base;
15251
15252 crtc->active = dev_priv->display.get_pipe_config(crtc,
15253 crtc->config);
15254
15255 crtc->base.state->active = crtc->active;
15256 crtc->base.enabled = crtc->active;
15257
15258 readout_plane_state(crtc);
15259
15260 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15261 crtc->base.base.id,
15262 crtc->active ? "enabled" : "disabled");
15263 }
15264
15265 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15266 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15267
15268 pll->on = pll->get_hw_state(dev_priv, pll,
15269 &pll->config.hw_state);
15270 pll->active = 0;
15271 pll->config.crtc_mask = 0;
15272 for_each_intel_crtc(dev, crtc) {
15273 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15274 pll->active++;
15275 pll->config.crtc_mask |= 1 << crtc->pipe;
15276 }
15277 }
15278
15279 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15280 pll->name, pll->config.crtc_mask, pll->on);
15281
15282 if (pll->config.crtc_mask)
15283 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15284 }
15285
15286 for_each_intel_encoder(dev, encoder) {
15287 pipe = 0;
15288
15289 if (encoder->get_hw_state(encoder, &pipe)) {
15290 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15291 encoder->base.crtc = &crtc->base;
15292 encoder->get_config(encoder, crtc->config);
15293 } else {
15294 encoder->base.crtc = NULL;
15295 }
15296
15297 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15298 encoder->base.base.id,
15299 encoder->base.name,
15300 encoder->base.crtc ? "enabled" : "disabled",
15301 pipe_name(pipe));
15302 }
15303
15304 for_each_intel_connector(dev, connector) {
15305 if (connector->get_hw_state(connector)) {
15306 connector->base.dpms = DRM_MODE_DPMS_ON;
15307 connector->base.encoder = &connector->encoder->base;
15308 } else {
15309 connector->base.dpms = DRM_MODE_DPMS_OFF;
15310 connector->base.encoder = NULL;
15311 }
15312 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15313 connector->base.base.id,
15314 connector->base.name,
15315 connector->base.encoder ? "enabled" : "disabled");
15316 }
15317
15318 for_each_intel_crtc(dev, crtc) {
15319 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15320
15321 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15322 if (crtc->base.state->active) {
15323 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15324 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15325 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15326
15327 /*
15328 * The initial mode needs to be set in order to keep
15329 * the atomic core happy. It wants a valid mode if the
15330 * crtc's enabled, so we do the above call.
15331 *
15332 * At this point some state updated by the connectors
15333 * in their ->detect() callback has not run yet, so
15334 * no recalculation can be done yet.
15335 *
15336 * Even if we could do a recalculation and modeset
15337 * right now it would cause a double modeset if
15338 * fbdev or userspace chooses a different initial mode.
15339 *
15340 * If that happens, someone indicated they wanted a
15341 * mode change, which means it's safe to do a full
15342 * recalculation.
15343 */
15344 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15345
15346 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15347 update_scanline_offset(crtc);
15348 }
15349 }
15350 }
15351
15352 /* Scan out the current hw modeset state,
15353 * and sanitizes it to the current state
15354 */
15355 static void
15356 intel_modeset_setup_hw_state(struct drm_device *dev)
15357 {
15358 struct drm_i915_private *dev_priv = dev->dev_private;
15359 enum pipe pipe;
15360 struct intel_crtc *crtc;
15361 struct intel_encoder *encoder;
15362 int i;
15363
15364 intel_modeset_readout_hw_state(dev);
15365
15366 /* HW state is read out, now we need to sanitize this mess. */
15367 for_each_intel_encoder(dev, encoder) {
15368 intel_sanitize_encoder(encoder);
15369 }
15370
15371 for_each_pipe(dev_priv, pipe) {
15372 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15373 intel_sanitize_crtc(crtc);
15374 intel_dump_pipe_config(crtc, crtc->config,
15375 "[setup_hw_state]");
15376 }
15377
15378 intel_modeset_update_connector_atomic_state(dev);
15379
15380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15381 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15382
15383 if (!pll->on || pll->active)
15384 continue;
15385
15386 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15387
15388 pll->disable(dev_priv, pll);
15389 pll->on = false;
15390 }
15391
15392 if (IS_VALLEYVIEW(dev))
15393 vlv_wm_get_hw_state(dev);
15394 else if (IS_GEN9(dev))
15395 skl_wm_get_hw_state(dev);
15396 else if (HAS_PCH_SPLIT(dev))
15397 ilk_wm_get_hw_state(dev);
15398
15399 for_each_intel_crtc(dev, crtc) {
15400 unsigned long put_domains;
15401
15402 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15403 if (WARN_ON(put_domains))
15404 modeset_put_power_domains(dev_priv, put_domains);
15405 }
15406 intel_display_set_init_power(dev_priv, false);
15407 }
15408
15409 void intel_display_resume(struct drm_device *dev)
15410 {
15411 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15412 struct intel_connector *conn;
15413 struct intel_plane *plane;
15414 struct drm_crtc *crtc;
15415 int ret;
15416
15417 if (!state)
15418 return;
15419
15420 state->acquire_ctx = dev->mode_config.acquire_ctx;
15421
15422 /* preserve complete old state, including dpll */
15423 intel_atomic_get_shared_dpll_state(state);
15424
15425 for_each_crtc(dev, crtc) {
15426 struct drm_crtc_state *crtc_state =
15427 drm_atomic_get_crtc_state(state, crtc);
15428
15429 ret = PTR_ERR_OR_ZERO(crtc_state);
15430 if (ret)
15431 goto err;
15432
15433 /* force a restore */
15434 crtc_state->mode_changed = true;
15435 }
15436
15437 for_each_intel_plane(dev, plane) {
15438 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15439 if (ret)
15440 goto err;
15441 }
15442
15443 for_each_intel_connector(dev, conn) {
15444 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15445 if (ret)
15446 goto err;
15447 }
15448
15449 intel_modeset_setup_hw_state(dev);
15450
15451 i915_redisable_vga(dev);
15452 ret = drm_atomic_commit(state);
15453 if (!ret)
15454 return;
15455
15456 err:
15457 DRM_ERROR("Restoring old state failed with %i\n", ret);
15458 drm_atomic_state_free(state);
15459 }
15460
15461 void intel_modeset_gem_init(struct drm_device *dev)
15462 {
15463 struct drm_crtc *c;
15464 struct drm_i915_gem_object *obj;
15465 int ret;
15466
15467 mutex_lock(&dev->struct_mutex);
15468 intel_init_gt_powersave(dev);
15469 mutex_unlock(&dev->struct_mutex);
15470
15471 intel_modeset_init_hw(dev);
15472
15473 intel_setup_overlay(dev);
15474
15475 /*
15476 * Make sure any fbs we allocated at startup are properly
15477 * pinned & fenced. When we do the allocation it's too early
15478 * for this.
15479 */
15480 for_each_crtc(dev, c) {
15481 obj = intel_fb_obj(c->primary->fb);
15482 if (obj == NULL)
15483 continue;
15484
15485 mutex_lock(&dev->struct_mutex);
15486 ret = intel_pin_and_fence_fb_obj(c->primary,
15487 c->primary->fb,
15488 c->primary->state,
15489 NULL, NULL);
15490 mutex_unlock(&dev->struct_mutex);
15491 if (ret) {
15492 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15493 to_intel_crtc(c)->pipe);
15494 drm_framebuffer_unreference(c->primary->fb);
15495 c->primary->fb = NULL;
15496 c->primary->crtc = c->primary->state->crtc = NULL;
15497 update_state_fb(c->primary);
15498 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15499 }
15500 }
15501
15502 intel_backlight_register(dev);
15503 }
15504
15505 void intel_connector_unregister(struct intel_connector *intel_connector)
15506 {
15507 struct drm_connector *connector = &intel_connector->base;
15508
15509 intel_panel_destroy_backlight(connector);
15510 drm_connector_unregister(connector);
15511 }
15512
15513 void intel_modeset_cleanup(struct drm_device *dev)
15514 {
15515 struct drm_i915_private *dev_priv = dev->dev_private;
15516 struct drm_connector *connector;
15517
15518 intel_disable_gt_powersave(dev);
15519
15520 intel_backlight_unregister(dev);
15521
15522 /*
15523 * Interrupts and polling as the first thing to avoid creating havoc.
15524 * Too much stuff here (turning of connectors, ...) would
15525 * experience fancy races otherwise.
15526 */
15527 intel_irq_uninstall(dev_priv);
15528
15529 /*
15530 * Due to the hpd irq storm handling the hotplug work can re-arm the
15531 * poll handlers. Hence disable polling after hpd handling is shut down.
15532 */
15533 drm_kms_helper_poll_fini(dev);
15534
15535 intel_unregister_dsm_handler();
15536
15537 intel_fbc_disable(dev_priv);
15538
15539 /* flush any delayed tasks or pending work */
15540 flush_scheduled_work();
15541
15542 /* destroy the backlight and sysfs files before encoders/connectors */
15543 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15544 struct intel_connector *intel_connector;
15545
15546 intel_connector = to_intel_connector(connector);
15547 intel_connector->unregister(intel_connector);
15548 }
15549
15550 drm_mode_config_cleanup(dev);
15551
15552 intel_cleanup_overlay(dev);
15553
15554 mutex_lock(&dev->struct_mutex);
15555 intel_cleanup_gt_powersave(dev);
15556 mutex_unlock(&dev->struct_mutex);
15557 }
15558
15559 /*
15560 * Return which encoder is currently attached for connector.
15561 */
15562 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15563 {
15564 return &intel_attached_encoder(connector)->base;
15565 }
15566
15567 void intel_connector_attach_encoder(struct intel_connector *connector,
15568 struct intel_encoder *encoder)
15569 {
15570 connector->encoder = encoder;
15571 drm_mode_connector_attach_encoder(&connector->base,
15572 &encoder->base);
15573 }
15574
15575 /*
15576 * set vga decode state - true == enable VGA decode
15577 */
15578 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15579 {
15580 struct drm_i915_private *dev_priv = dev->dev_private;
15581 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15582 u16 gmch_ctrl;
15583
15584 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15585 DRM_ERROR("failed to read control word\n");
15586 return -EIO;
15587 }
15588
15589 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15590 return 0;
15591
15592 if (state)
15593 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15594 else
15595 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15596
15597 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15598 DRM_ERROR("failed to write control word\n");
15599 return -EIO;
15600 }
15601
15602 return 0;
15603 }
15604
15605 struct intel_display_error_state {
15606
15607 u32 power_well_driver;
15608
15609 int num_transcoders;
15610
15611 struct intel_cursor_error_state {
15612 u32 control;
15613 u32 position;
15614 u32 base;
15615 u32 size;
15616 } cursor[I915_MAX_PIPES];
15617
15618 struct intel_pipe_error_state {
15619 bool power_domain_on;
15620 u32 source;
15621 u32 stat;
15622 } pipe[I915_MAX_PIPES];
15623
15624 struct intel_plane_error_state {
15625 u32 control;
15626 u32 stride;
15627 u32 size;
15628 u32 pos;
15629 u32 addr;
15630 u32 surface;
15631 u32 tile_offset;
15632 } plane[I915_MAX_PIPES];
15633
15634 struct intel_transcoder_error_state {
15635 bool power_domain_on;
15636 enum transcoder cpu_transcoder;
15637
15638 u32 conf;
15639
15640 u32 htotal;
15641 u32 hblank;
15642 u32 hsync;
15643 u32 vtotal;
15644 u32 vblank;
15645 u32 vsync;
15646 } transcoder[4];
15647 };
15648
15649 struct intel_display_error_state *
15650 intel_display_capture_error_state(struct drm_device *dev)
15651 {
15652 struct drm_i915_private *dev_priv = dev->dev_private;
15653 struct intel_display_error_state *error;
15654 int transcoders[] = {
15655 TRANSCODER_A,
15656 TRANSCODER_B,
15657 TRANSCODER_C,
15658 TRANSCODER_EDP,
15659 };
15660 int i;
15661
15662 if (INTEL_INFO(dev)->num_pipes == 0)
15663 return NULL;
15664
15665 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15666 if (error == NULL)
15667 return NULL;
15668
15669 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15670 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15671
15672 for_each_pipe(dev_priv, i) {
15673 error->pipe[i].power_domain_on =
15674 __intel_display_power_is_enabled(dev_priv,
15675 POWER_DOMAIN_PIPE(i));
15676 if (!error->pipe[i].power_domain_on)
15677 continue;
15678
15679 error->cursor[i].control = I915_READ(CURCNTR(i));
15680 error->cursor[i].position = I915_READ(CURPOS(i));
15681 error->cursor[i].base = I915_READ(CURBASE(i));
15682
15683 error->plane[i].control = I915_READ(DSPCNTR(i));
15684 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15685 if (INTEL_INFO(dev)->gen <= 3) {
15686 error->plane[i].size = I915_READ(DSPSIZE(i));
15687 error->plane[i].pos = I915_READ(DSPPOS(i));
15688 }
15689 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15690 error->plane[i].addr = I915_READ(DSPADDR(i));
15691 if (INTEL_INFO(dev)->gen >= 4) {
15692 error->plane[i].surface = I915_READ(DSPSURF(i));
15693 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15694 }
15695
15696 error->pipe[i].source = I915_READ(PIPESRC(i));
15697
15698 if (HAS_GMCH_DISPLAY(dev))
15699 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15700 }
15701
15702 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15703 if (HAS_DDI(dev_priv->dev))
15704 error->num_transcoders++; /* Account for eDP. */
15705
15706 for (i = 0; i < error->num_transcoders; i++) {
15707 enum transcoder cpu_transcoder = transcoders[i];
15708
15709 error->transcoder[i].power_domain_on =
15710 __intel_display_power_is_enabled(dev_priv,
15711 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15712 if (!error->transcoder[i].power_domain_on)
15713 continue;
15714
15715 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15716
15717 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15718 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15719 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15720 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15721 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15722 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15723 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15724 }
15725
15726 return error;
15727 }
15728
15729 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15730
15731 void
15732 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15733 struct drm_device *dev,
15734 struct intel_display_error_state *error)
15735 {
15736 struct drm_i915_private *dev_priv = dev->dev_private;
15737 int i;
15738
15739 if (!error)
15740 return;
15741
15742 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15743 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15744 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15745 error->power_well_driver);
15746 for_each_pipe(dev_priv, i) {
15747 err_printf(m, "Pipe [%d]:\n", i);
15748 err_printf(m, " Power: %s\n",
15749 error->pipe[i].power_domain_on ? "on" : "off");
15750 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15751 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15752
15753 err_printf(m, "Plane [%d]:\n", i);
15754 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15755 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15756 if (INTEL_INFO(dev)->gen <= 3) {
15757 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15758 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15759 }
15760 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15761 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15762 if (INTEL_INFO(dev)->gen >= 4) {
15763 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15764 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15765 }
15766
15767 err_printf(m, "Cursor [%d]:\n", i);
15768 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15769 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15770 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15771 }
15772
15773 for (i = 0; i < error->num_transcoders; i++) {
15774 err_printf(m, "CPU transcoder: %c\n",
15775 transcoder_name(error->transcoder[i].cpu_transcoder));
15776 err_printf(m, " Power: %s\n",
15777 error->transcoder[i].power_domain_on ? "on" : "off");
15778 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15779 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15780 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15781 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15782 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15783 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15784 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15785 }
15786 }
15787
15788 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15789 {
15790 struct intel_crtc *crtc;
15791
15792 for_each_intel_crtc(dev, crtc) {
15793 struct intel_unpin_work *work;
15794
15795 spin_lock_irq(&dev->event_lock);
15796
15797 work = crtc->unpin_work;
15798
15799 if (work && work->event &&
15800 work->event->base.file_priv == file) {
15801 kfree(work->event);
15802 work->event = NULL;
15803 }
15804
15805 spin_unlock_irq(&dev->event_lock);
15806 }
15807 }
Linux kernel - Deliverables
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