2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
45 static void intel_update_watermarks(struct drm_device
*dev
);
46 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
47 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t
;
73 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
76 int, int, intel_clock_t
*);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
333 int target
, int refclk
, intel_clock_t
*best_clock
);
335 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
336 int target
, int refclk
, intel_clock_t
*best_clock
);
339 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
340 int target
, int refclk
, intel_clock_t
*best_clock
);
342 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
343 int target
, int refclk
, intel_clock_t
*best_clock
);
345 static inline u32
/* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device
*dev
)
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
350 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
355 static const intel_limit_t intel_limits_i8xx_dvo
= {
356 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
357 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
358 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
359 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
360 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
361 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
362 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
363 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
364 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
365 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
366 .find_pll
= intel_find_best_PLL
,
369 static const intel_limit_t intel_limits_i8xx_lvds
= {
370 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
371 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
372 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
373 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
374 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
375 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
376 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
377 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
378 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
379 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
380 .find_pll
= intel_find_best_PLL
,
383 static const intel_limit_t intel_limits_i9xx_sdvo
= {
384 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
385 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
386 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
387 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
388 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
389 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
390 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
391 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
392 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
393 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
394 .find_pll
= intel_find_best_PLL
,
397 static const intel_limit_t intel_limits_i9xx_lvds
= {
398 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
399 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
400 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
401 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
402 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
403 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
404 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
405 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
409 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
410 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
411 .find_pll
= intel_find_best_PLL
,
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo
= {
416 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
417 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
418 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
419 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
420 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
421 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
422 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
423 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
424 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
425 .p2_slow
= G4X_P2_SDVO_SLOW
,
426 .p2_fast
= G4X_P2_SDVO_FAST
428 .find_pll
= intel_g4x_find_best_PLL
,
431 static const intel_limit_t intel_limits_g4x_hdmi
= {
432 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
433 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
434 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
435 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
436 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
437 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
438 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
439 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
440 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
441 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
442 .p2_fast
= G4X_P2_HDMI_DAC_FAST
444 .find_pll
= intel_g4x_find_best_PLL
,
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
448 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
449 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
450 .vco
= { .min
= G4X_VCO_MIN
,
451 .max
= G4X_VCO_MAX
},
452 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
453 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
454 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
455 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
456 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
457 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
458 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
459 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
460 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
461 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
462 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
463 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
464 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
465 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
466 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
468 .find_pll
= intel_g4x_find_best_PLL
,
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
472 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
473 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
474 .vco
= { .min
= G4X_VCO_MIN
,
475 .max
= G4X_VCO_MAX
},
476 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
477 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
478 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
479 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
480 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
481 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
482 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
483 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
484 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
485 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
486 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
487 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
488 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
489 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
490 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
492 .find_pll
= intel_g4x_find_best_PLL
,
495 static const intel_limit_t intel_limits_g4x_display_port
= {
496 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
497 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
498 .vco
= { .min
= G4X_VCO_MIN
,
500 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
501 .max
= G4X_N_DISPLAY_PORT_MAX
},
502 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
503 .max
= G4X_M_DISPLAY_PORT_MAX
},
504 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
505 .max
= G4X_M1_DISPLAY_PORT_MAX
},
506 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
507 .max
= G4X_M2_DISPLAY_PORT_MAX
},
508 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
509 .max
= G4X_P_DISPLAY_PORT_MAX
},
510 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
511 .max
= G4X_P1_DISPLAY_PORT_MAX
},
512 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
513 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
514 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
515 .find_pll
= intel_find_pll_g4x_dp
,
518 static const intel_limit_t intel_limits_pineview_sdvo
= {
519 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
520 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
521 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
522 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
523 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
524 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
525 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
526 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
527 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
528 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
529 .find_pll
= intel_find_best_PLL
,
532 static const intel_limit_t intel_limits_pineview_lvds
= {
533 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
534 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
535 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
536 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
537 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
538 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
539 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
540 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
541 /* Pineview only supports single-channel mode. */
542 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
543 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
544 .find_pll
= intel_find_best_PLL
,
547 static const intel_limit_t intel_limits_ironlake_dac
= {
548 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
549 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
550 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
551 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
552 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
553 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
554 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
555 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
556 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
557 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
558 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
559 .find_pll
= intel_g4x_find_best_PLL
,
562 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
563 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
564 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
565 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
566 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
567 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
568 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
569 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
570 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
571 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
572 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
573 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
574 .find_pll
= intel_g4x_find_best_PLL
,
577 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
578 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
579 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
580 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
581 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
582 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
583 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
584 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
585 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
586 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
587 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
588 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
589 .find_pll
= intel_g4x_find_best_PLL
,
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
593 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
594 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
595 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
596 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
597 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
598 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
599 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
600 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
601 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
602 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
603 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
604 .find_pll
= intel_g4x_find_best_PLL
,
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
608 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
609 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
610 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
611 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
612 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
613 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
614 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
615 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
616 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
617 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
618 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
619 .find_pll
= intel_g4x_find_best_PLL
,
622 static const intel_limit_t intel_limits_ironlake_display_port
= {
623 .dot
= { .min
= IRONLAKE_DOT_MIN
,
624 .max
= IRONLAKE_DOT_MAX
},
625 .vco
= { .min
= IRONLAKE_VCO_MIN
,
626 .max
= IRONLAKE_VCO_MAX
},
627 .n
= { .min
= IRONLAKE_DP_N_MIN
,
628 .max
= IRONLAKE_DP_N_MAX
},
629 .m
= { .min
= IRONLAKE_DP_M_MIN
,
630 .max
= IRONLAKE_DP_M_MAX
},
631 .m1
= { .min
= IRONLAKE_M1_MIN
,
632 .max
= IRONLAKE_M1_MAX
},
633 .m2
= { .min
= IRONLAKE_M2_MIN
,
634 .max
= IRONLAKE_M2_MAX
},
635 .p
= { .min
= IRONLAKE_DP_P_MIN
,
636 .max
= IRONLAKE_DP_P_MAX
},
637 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
638 .max
= IRONLAKE_DP_P1_MAX
},
639 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
640 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
641 .p2_fast
= IRONLAKE_DP_P2_FAST
},
642 .find_pll
= intel_find_pll_ironlake_dp
,
645 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
648 struct drm_device
*dev
= crtc
->dev
;
649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
650 const intel_limit_t
*limit
;
652 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
653 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
654 LVDS_CLKB_POWER_UP
) {
655 /* LVDS dual channel */
656 if (refclk
== 100000)
657 limit
= &intel_limits_ironlake_dual_lvds_100m
;
659 limit
= &intel_limits_ironlake_dual_lvds
;
661 if (refclk
== 100000)
662 limit
= &intel_limits_ironlake_single_lvds_100m
;
664 limit
= &intel_limits_ironlake_single_lvds
;
666 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
668 limit
= &intel_limits_ironlake_display_port
;
670 limit
= &intel_limits_ironlake_dac
;
675 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
677 struct drm_device
*dev
= crtc
->dev
;
678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
679 const intel_limit_t
*limit
;
681 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
682 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
684 /* LVDS with dual channel */
685 limit
= &intel_limits_g4x_dual_channel_lvds
;
687 /* LVDS with dual channel */
688 limit
= &intel_limits_g4x_single_channel_lvds
;
689 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
690 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
691 limit
= &intel_limits_g4x_hdmi
;
692 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
693 limit
= &intel_limits_g4x_sdvo
;
694 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
695 limit
= &intel_limits_g4x_display_port
;
696 } else /* The option is for other outputs */
697 limit
= &intel_limits_i9xx_sdvo
;
702 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
704 struct drm_device
*dev
= crtc
->dev
;
705 const intel_limit_t
*limit
;
707 if (HAS_PCH_SPLIT(dev
))
708 limit
= intel_ironlake_limit(crtc
, refclk
);
709 else if (IS_G4X(dev
)) {
710 limit
= intel_g4x_limit(crtc
);
711 } else if (IS_PINEVIEW(dev
)) {
712 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
713 limit
= &intel_limits_pineview_lvds
;
715 limit
= &intel_limits_pineview_sdvo
;
716 } else if (!IS_GEN2(dev
)) {
717 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
718 limit
= &intel_limits_i9xx_lvds
;
720 limit
= &intel_limits_i9xx_sdvo
;
722 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
723 limit
= &intel_limits_i8xx_lvds
;
725 limit
= &intel_limits_i8xx_dvo
;
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
733 clock
->m
= clock
->m2
+ 2;
734 clock
->p
= clock
->p1
* clock
->p2
;
735 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
736 clock
->dot
= clock
->vco
/ clock
->p
;
739 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
741 if (IS_PINEVIEW(dev
)) {
742 pineview_clock(refclk
, clock
);
745 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
746 clock
->p
= clock
->p1
* clock
->p2
;
747 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
748 clock
->dot
= clock
->vco
/ clock
->p
;
752 * Returns whether any output on the specified pipe is of the specified type
754 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
756 struct drm_device
*dev
= crtc
->dev
;
757 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
758 struct intel_encoder
*encoder
;
760 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
761 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
773 static bool intel_PLL_is_valid(struct drm_device
*dev
,
774 const intel_limit_t
*limit
,
775 const intel_clock_t
*clock
)
777 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
780 INTELPllInvalid ("p out of range\n");
781 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
788 INTELPllInvalid ("m out of range\n");
789 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
790 INTELPllInvalid ("n out of range\n");
791 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
796 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
797 INTELPllInvalid ("dot out of range\n");
803 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
804 int target
, int refclk
, intel_clock_t
*best_clock
)
807 struct drm_device
*dev
= crtc
->dev
;
808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
812 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
813 (I915_READ(LVDS
)) != 0) {
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
820 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
822 clock
.p2
= limit
->p2
.p2_fast
;
824 clock
.p2
= limit
->p2
.p2_slow
;
826 if (target
< limit
->p2
.dot_limit
)
827 clock
.p2
= limit
->p2
.p2_slow
;
829 clock
.p2
= limit
->p2
.p2_fast
;
832 memset (best_clock
, 0, sizeof (*best_clock
));
834 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
836 for (clock
.m2
= limit
->m2
.min
;
837 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
838 /* m1 is always 0 in Pineview */
839 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
841 for (clock
.n
= limit
->n
.min
;
842 clock
.n
<= limit
->n
.max
; clock
.n
++) {
843 for (clock
.p1
= limit
->p1
.min
;
844 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
847 intel_clock(dev
, refclk
, &clock
);
848 if (!intel_PLL_is_valid(dev
, limit
,
852 this_err
= abs(clock
.dot
- target
);
853 if (this_err
< err
) {
862 return (err
!= target
);
866 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
867 int target
, int refclk
, intel_clock_t
*best_clock
)
869 struct drm_device
*dev
= crtc
->dev
;
870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
874 /* approximately equals target * 0.00585 */
875 int err_most
= (target
>> 8) + (target
>> 9);
878 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
881 if (HAS_PCH_SPLIT(dev
))
885 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
887 clock
.p2
= limit
->p2
.p2_fast
;
889 clock
.p2
= limit
->p2
.p2_slow
;
891 if (target
< limit
->p2
.dot_limit
)
892 clock
.p2
= limit
->p2
.p2_slow
;
894 clock
.p2
= limit
->p2
.p2_fast
;
897 memset(best_clock
, 0, sizeof(*best_clock
));
898 max_n
= limit
->n
.max
;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock
.m1
= limit
->m1
.max
;
903 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
904 for (clock
.m2
= limit
->m2
.max
;
905 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
906 for (clock
.p1
= limit
->p1
.max
;
907 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
910 intel_clock(dev
, refclk
, &clock
);
911 if (!intel_PLL_is_valid(dev
, limit
,
915 this_err
= abs(clock
.dot
- target
);
916 if (this_err
< err_most
) {
930 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
931 int target
, int refclk
, intel_clock_t
*best_clock
)
933 struct drm_device
*dev
= crtc
->dev
;
936 if (target
< 200000) {
949 intel_clock(dev
, refclk
, &clock
);
950 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
956 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
957 int target
, int refclk
, intel_clock_t
*best_clock
)
960 if (target
< 200000) {
973 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
974 clock
.p
= (clock
.p1
* clock
.p2
);
975 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
977 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
982 * intel_wait_for_vblank - wait for vblank on a given pipe
984 * @pipe: pipe to wait for
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
989 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
992 int pipestat_reg
= PIPESTAT(pipe
);
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1007 I915_WRITE(pipestat_reg
,
1008 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg
) &
1012 PIPE_VBLANK_INTERRUPT_STATUS
,
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1020 * @pipe: pipe to wait for
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1034 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1038 if (INTEL_INFO(dev
)->gen
>= 4) {
1039 int reg
= PIPECONF(pipe
);
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047 int reg
= PIPEDSL(pipe
);
1048 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1050 /* Wait for the display line to settle */
1052 last_line
= I915_READ(reg
) & DSL_LINEMASK
;
1054 } while (((I915_READ(reg
) & DSL_LINEMASK
) != last_line
) &&
1055 time_after(timeout
, jiffies
));
1056 if (time_after(jiffies
, timeout
))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1061 static const char *state_string(bool enabled
)
1063 return enabled
? "on" : "off";
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private
*dev_priv
,
1068 enum pipe pipe
, bool state
)
1075 val
= I915_READ(reg
);
1076 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1077 WARN(cur_state
!= state
,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state
), state_string(cur_state
));
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1085 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1086 enum pipe pipe
, bool state
)
1092 reg
= PCH_DPLL(pipe
);
1093 val
= I915_READ(reg
);
1094 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1095 WARN(cur_state
!= state
,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state
), state_string(cur_state
));
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1102 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1103 enum pipe pipe
, bool state
)
1109 reg
= FDI_TX_CTL(pipe
);
1110 val
= I915_READ(reg
);
1111 cur_state
= !!(val
& FDI_TX_ENABLE
);
1112 WARN(cur_state
!= state
,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state
), state_string(cur_state
));
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1119 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1120 enum pipe pipe
, bool state
)
1126 reg
= FDI_RX_CTL(pipe
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& FDI_RX_ENABLE
);
1129 WARN(cur_state
!= state
,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state
), state_string(cur_state
));
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv
->info
->gen
== 5)
1146 reg
= FDI_TX_CTL(pipe
);
1147 val
= I915_READ(reg
);
1148 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1157 reg
= FDI_RX_CTL(pipe
);
1158 val
= I915_READ(reg
);
1159 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1162 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1165 int pp_reg
, lvds_reg
;
1167 enum pipe panel_pipe
= PIPE_A
;
1168 bool locked
= locked
;
1170 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1171 pp_reg
= PCH_PP_CONTROL
;
1172 lvds_reg
= PCH_LVDS
;
1174 pp_reg
= PP_CONTROL
;
1178 val
= I915_READ(pp_reg
);
1179 if (!(val
& PANEL_POWER_ON
) ||
1180 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1183 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1184 panel_pipe
= PIPE_B
;
1186 WARN(panel_pipe
== pipe
&& locked
,
1187 "panel assertion failure, pipe %c regs locked\n",
1191 static void assert_pipe(struct drm_i915_private
*dev_priv
,
1192 enum pipe pipe
, bool state
)
1198 reg
= PIPECONF(pipe
);
1199 val
= I915_READ(reg
);
1200 cur_state
= !!(val
& PIPECONF_ENABLE
);
1201 WARN(cur_state
!= state
,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1208 static void assert_plane_enabled(struct drm_i915_private
*dev_priv
,
1214 reg
= DSPCNTR(plane
);
1215 val
= I915_READ(reg
);
1216 WARN(!(val
& DISPLAY_PLANE_ENABLE
),
1217 "plane %c assertion failure, should be active but is disabled\n",
1221 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1228 /* Planes are fixed to pipes on ILK+ */
1229 if (HAS_PCH_SPLIT(dev_priv
->dev
))
1232 /* Need to check both planes against the pipe */
1233 for (i
= 0; i
< 2; i
++) {
1235 val
= I915_READ(reg
);
1236 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1237 DISPPLANE_SEL_PIPE_SHIFT
;
1238 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1239 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240 plane_name(i
), pipe_name(pipe
));
1244 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1249 val
= I915_READ(PCH_DREF_CONTROL
);
1250 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1251 DREF_SUPERSPREAD_SOURCE_MASK
));
1252 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1255 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1262 reg
= TRANSCONF(pipe
);
1263 val
= I915_READ(reg
);
1264 enabled
= !!(val
& TRANS_ENABLE
);
1266 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1270 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1271 enum pipe pipe
, int reg
)
1273 u32 val
= I915_READ(reg
);
1274 WARN(DP_PIPE_ENABLED(val
, pipe
),
1275 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276 reg
, pipe_name(pipe
));
1279 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1280 enum pipe pipe
, int reg
)
1282 u32 val
= I915_READ(reg
);
1283 WARN(HDMI_PIPE_ENABLED(val
, pipe
),
1284 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1285 reg
, pipe_name(pipe
));
1288 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1294 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
);
1295 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
);
1296 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
);
1299 val
= I915_READ(reg
);
1300 WARN(ADPA_PIPE_ENABLED(val
, pipe
),
1301 "PCH VGA enabled on transcoder %c, should be disabled\n",
1305 val
= I915_READ(reg
);
1306 WARN(LVDS_PIPE_ENABLED(val
, pipe
),
1307 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1310 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1311 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1312 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1316 * intel_enable_pll - enable a PLL
1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe PLL to enable
1320 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1321 * make sure the PLL reg is writable first though, since the panel write
1322 * protect mechanism may be enabled.
1324 * Note! This is for pre-ILK only.
1326 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1331 /* No really, not for ILK+ */
1332 BUG_ON(dev_priv
->info
->gen
>= 5);
1334 /* PLL is protected by panel, make sure we can write it */
1335 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1336 assert_panel_unlocked(dev_priv
, pipe
);
1339 val
= I915_READ(reg
);
1340 val
|= DPLL_VCO_ENABLE
;
1342 /* We do this three times for luck */
1343 I915_WRITE(reg
, val
);
1345 udelay(150); /* wait for warmup */
1346 I915_WRITE(reg
, val
);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg
, val
);
1351 udelay(150); /* wait for warmup */
1355 * intel_disable_pll - disable a PLL
1356 * @dev_priv: i915 private structure
1357 * @pipe: pipe PLL to disable
1359 * Disable the PLL for @pipe, making sure the pipe is off first.
1361 * Note! This is for pre-ILK only.
1363 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1368 /* Don't disable pipe A or pipe A PLLs if needed */
1369 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1372 /* Make sure the pipe isn't still relying on us */
1373 assert_pipe_disabled(dev_priv
, pipe
);
1376 val
= I915_READ(reg
);
1377 val
&= ~DPLL_VCO_ENABLE
;
1378 I915_WRITE(reg
, val
);
1383 * intel_enable_pch_pll - enable PCH PLL
1384 * @dev_priv: i915 private structure
1385 * @pipe: pipe PLL to enable
1387 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1388 * drives the transcoder clock.
1390 static void intel_enable_pch_pll(struct drm_i915_private
*dev_priv
,
1396 /* PCH only available on ILK+ */
1397 BUG_ON(dev_priv
->info
->gen
< 5);
1399 /* PCH refclock must be enabled first */
1400 assert_pch_refclk_enabled(dev_priv
);
1402 reg
= PCH_DPLL(pipe
);
1403 val
= I915_READ(reg
);
1404 val
|= DPLL_VCO_ENABLE
;
1405 I915_WRITE(reg
, val
);
1410 static void intel_disable_pch_pll(struct drm_i915_private
*dev_priv
,
1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv
->info
->gen
< 5);
1419 /* Make sure transcoder isn't still depending on us */
1420 assert_transcoder_disabled(dev_priv
, pipe
);
1422 reg
= PCH_DPLL(pipe
);
1423 val
= I915_READ(reg
);
1424 val
&= ~DPLL_VCO_ENABLE
;
1425 I915_WRITE(reg
, val
);
1430 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1436 /* PCH only available on ILK+ */
1437 BUG_ON(dev_priv
->info
->gen
< 5);
1439 /* Make sure PCH DPLL is enabled */
1440 assert_pch_pll_enabled(dev_priv
, pipe
);
1442 /* FDI must be feeding us bits for PCH ports */
1443 assert_fdi_tx_enabled(dev_priv
, pipe
);
1444 assert_fdi_rx_enabled(dev_priv
, pipe
);
1446 reg
= TRANSCONF(pipe
);
1447 val
= I915_READ(reg
);
1449 * make the BPC in transcoder be consistent with
1450 * that in pipeconf reg.
1452 val
&= ~PIPE_BPC_MASK
;
1453 val
|= I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
;
1454 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1455 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1456 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1459 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1465 /* FDI relies on the transcoder */
1466 assert_fdi_tx_disabled(dev_priv
, pipe
);
1467 assert_fdi_rx_disabled(dev_priv
, pipe
);
1469 /* Ports must be off as well */
1470 assert_pch_ports_disabled(dev_priv
, pipe
);
1472 reg
= TRANSCONF(pipe
);
1473 val
= I915_READ(reg
);
1474 val
&= ~TRANS_ENABLE
;
1475 I915_WRITE(reg
, val
);
1476 /* wait for PCH transcoder off, transcoder state */
1477 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1478 DRM_ERROR("failed to disable transcoder\n");
1482 * intel_enable_pipe - enable a pipe, asserting requirements
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe to enable
1485 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1487 * Enable @pipe, making sure that various hardware specific requirements
1488 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1490 * @pipe should be %PIPE_A or %PIPE_B.
1492 * Will wait until the pipe is actually running (i.e. first vblank) before
1495 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1502 * A pipe without a PLL won't actually be able to drive bits from
1503 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1506 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1507 assert_pll_enabled(dev_priv
, pipe
);
1510 /* if driving the PCH, we need FDI enabled */
1511 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1512 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1514 /* FIXME: assert CPU port conditions for SNB+ */
1517 reg
= PIPECONF(pipe
);
1518 val
= I915_READ(reg
);
1519 if (val
& PIPECONF_ENABLE
)
1522 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1523 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1527 * intel_disable_pipe - disable a pipe, asserting requirements
1528 * @dev_priv: i915 private structure
1529 * @pipe: pipe to disable
1531 * Disable @pipe, making sure that various hardware specific requirements
1532 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1534 * @pipe should be %PIPE_A or %PIPE_B.
1536 * Will wait until the pipe has shut down before returning.
1538 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1545 * Make sure planes won't keep trying to pump pixels to us,
1546 * or we might hang the display.
1548 assert_planes_disabled(dev_priv
, pipe
);
1550 /* Don't disable pipe A or pipe A PLLs if needed */
1551 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1554 reg
= PIPECONF(pipe
);
1555 val
= I915_READ(reg
);
1556 if ((val
& PIPECONF_ENABLE
) == 0)
1559 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1560 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1564 * intel_enable_plane - enable a display plane on a given pipe
1565 * @dev_priv: i915 private structure
1566 * @plane: plane to enable
1567 * @pipe: pipe being fed
1569 * Enable @plane on @pipe, making sure that @pipe is running first.
1571 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1572 enum plane plane
, enum pipe pipe
)
1577 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1578 assert_pipe_enabled(dev_priv
, pipe
);
1580 reg
= DSPCNTR(plane
);
1581 val
= I915_READ(reg
);
1582 if (val
& DISPLAY_PLANE_ENABLE
)
1585 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1586 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1590 * Plane regs are double buffered, going from enabled->disabled needs a
1591 * trigger in order to latch. The display address reg provides this.
1593 static void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1596 u32 reg
= DSPADDR(plane
);
1597 I915_WRITE(reg
, I915_READ(reg
));
1601 * intel_disable_plane - disable a display plane
1602 * @dev_priv: i915 private structure
1603 * @plane: plane to disable
1604 * @pipe: pipe consuming the data
1606 * Disable @plane; should be an independent operation.
1608 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1609 enum plane plane
, enum pipe pipe
)
1614 reg
= DSPCNTR(plane
);
1615 val
= I915_READ(reg
);
1616 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1619 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1620 intel_flush_display_plane(dev_priv
, plane
);
1621 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1624 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1625 enum pipe pipe
, int reg
)
1627 u32 val
= I915_READ(reg
);
1628 if (DP_PIPE_ENABLED(val
, pipe
))
1629 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1632 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1633 enum pipe pipe
, int reg
)
1635 u32 val
= I915_READ(reg
);
1636 if (HDMI_PIPE_ENABLED(val
, pipe
))
1637 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1640 /* Disable any ports connected to this transcoder */
1641 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1646 val
= I915_READ(PCH_PP_CONTROL
);
1647 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1649 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
);
1650 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
);
1651 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
);
1654 val
= I915_READ(reg
);
1655 if (ADPA_PIPE_ENABLED(val
, pipe
))
1656 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1659 val
= I915_READ(reg
);
1660 if (LVDS_PIPE_ENABLED(val
, pipe
)) {
1661 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1666 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1667 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1668 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1671 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1673 struct drm_device
*dev
= crtc
->dev
;
1674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1675 struct drm_framebuffer
*fb
= crtc
->fb
;
1676 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1677 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1678 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1680 u32 fbc_ctl
, fbc_ctl2
;
1682 if (fb
->pitch
== dev_priv
->cfb_pitch
&&
1683 obj
->fence_reg
== dev_priv
->cfb_fence
&&
1684 intel_crtc
->plane
== dev_priv
->cfb_plane
&&
1685 I915_READ(FBC_CONTROL
) & FBC_CTL_EN
)
1688 i8xx_disable_fbc(dev
);
1690 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1692 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1693 dev_priv
->cfb_pitch
= fb
->pitch
;
1695 /* FBC_CTL wants 64B units */
1696 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1697 dev_priv
->cfb_fence
= obj
->fence_reg
;
1698 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1699 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1701 /* Clear old tags */
1702 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1703 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1706 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1707 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1708 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1709 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1710 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1713 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1715 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1716 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1717 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1718 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1719 fbc_ctl
|= dev_priv
->cfb_fence
;
1720 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1722 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1723 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1726 void i8xx_disable_fbc(struct drm_device
*dev
)
1728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1731 /* Disable compression */
1732 fbc_ctl
= I915_READ(FBC_CONTROL
);
1733 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
1736 fbc_ctl
&= ~FBC_CTL_EN
;
1737 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1739 /* Wait for compressing bit to clear */
1740 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1741 DRM_DEBUG_KMS("FBC idle timed out\n");
1745 DRM_DEBUG_KMS("disabled FBC\n");
1748 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1752 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1755 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1757 struct drm_device
*dev
= crtc
->dev
;
1758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1759 struct drm_framebuffer
*fb
= crtc
->fb
;
1760 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1761 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1762 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1763 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1764 unsigned long stall_watermark
= 200;
1767 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1768 if (dpfc_ctl
& DPFC_CTL_EN
) {
1769 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1770 dev_priv
->cfb_fence
== obj
->fence_reg
&&
1771 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1772 dev_priv
->cfb_y
== crtc
->y
)
1775 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1776 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1779 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1780 dev_priv
->cfb_fence
= obj
->fence_reg
;
1781 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1782 dev_priv
->cfb_y
= crtc
->y
;
1784 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1785 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1786 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1787 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1789 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1792 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1793 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1794 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1795 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1798 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1800 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1803 void g4x_disable_fbc(struct drm_device
*dev
)
1805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1808 /* Disable compression */
1809 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1810 if (dpfc_ctl
& DPFC_CTL_EN
) {
1811 dpfc_ctl
&= ~DPFC_CTL_EN
;
1812 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1814 DRM_DEBUG_KMS("disabled FBC\n");
1818 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1822 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1825 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
1827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1830 /* Make sure blitter notifies FBC of writes */
1831 __gen6_gt_force_wake_get(dev_priv
);
1832 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
1833 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
1834 GEN6_BLITTER_LOCK_SHIFT
;
1835 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1836 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
1837 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1838 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
1839 GEN6_BLITTER_LOCK_SHIFT
);
1840 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1841 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
1842 __gen6_gt_force_wake_put(dev_priv
);
1845 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1847 struct drm_device
*dev
= crtc
->dev
;
1848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1849 struct drm_framebuffer
*fb
= crtc
->fb
;
1850 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1851 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1853 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1854 unsigned long stall_watermark
= 200;
1857 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1858 if (dpfc_ctl
& DPFC_CTL_EN
) {
1859 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1860 dev_priv
->cfb_fence
== obj
->fence_reg
&&
1861 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1862 dev_priv
->cfb_offset
== obj
->gtt_offset
&&
1863 dev_priv
->cfb_y
== crtc
->y
)
1866 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1867 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1870 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1871 dev_priv
->cfb_fence
= obj
->fence_reg
;
1872 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1873 dev_priv
->cfb_offset
= obj
->gtt_offset
;
1874 dev_priv
->cfb_y
= crtc
->y
;
1876 dpfc_ctl
&= DPFC_RESERVED
;
1877 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1878 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1879 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1880 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1882 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1885 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1886 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1887 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1888 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1889 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
1891 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
1894 I915_WRITE(SNB_DPFC_CTL_SA
,
1895 SNB_CPU_FENCE_ENABLE
| dev_priv
->cfb_fence
);
1896 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
1897 sandybridge_blit_fbc_update(dev
);
1900 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1903 void ironlake_disable_fbc(struct drm_device
*dev
)
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1908 /* Disable compression */
1909 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1910 if (dpfc_ctl
& DPFC_CTL_EN
) {
1911 dpfc_ctl
&= ~DPFC_CTL_EN
;
1912 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1914 DRM_DEBUG_KMS("disabled FBC\n");
1918 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1922 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1925 bool intel_fbc_enabled(struct drm_device
*dev
)
1927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1929 if (!dev_priv
->display
.fbc_enabled
)
1932 return dev_priv
->display
.fbc_enabled(dev
);
1935 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1937 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1939 if (!dev_priv
->display
.enable_fbc
)
1942 dev_priv
->display
.enable_fbc(crtc
, interval
);
1945 void intel_disable_fbc(struct drm_device
*dev
)
1947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1949 if (!dev_priv
->display
.disable_fbc
)
1952 dev_priv
->display
.disable_fbc(dev
);
1956 * intel_update_fbc - enable/disable FBC as needed
1957 * @dev: the drm_device
1959 * Set up the framebuffer compression hardware at mode set time. We
1960 * enable it if possible:
1961 * - plane A only (on pre-965)
1962 * - no pixel mulitply/line duplication
1963 * - no alpha buffer discard
1965 * - framebuffer <= 2048 in width, 1536 in height
1967 * We can't assume that any compression will take place (worst case),
1968 * so the compressed buffer has to be the same size as the uncompressed
1969 * one. It also must reside (along with the line length buffer) in
1972 * We need to enable/disable FBC on a global basis.
1974 static void intel_update_fbc(struct drm_device
*dev
)
1976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1977 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
1978 struct intel_crtc
*intel_crtc
;
1979 struct drm_framebuffer
*fb
;
1980 struct intel_framebuffer
*intel_fb
;
1981 struct drm_i915_gem_object
*obj
;
1983 DRM_DEBUG_KMS("\n");
1985 if (!i915_powersave
)
1988 if (!I915_HAS_FBC(dev
))
1992 * If FBC is already on, we just have to verify that we can
1993 * keep it that way...
1994 * Need to disable if:
1995 * - more than one pipe is active
1996 * - changing FBC params (stride, fence, mode)
1997 * - new fb is too large to fit in compressed buffer
1998 * - going to an unsupported config (interlace, pixel multiply, etc.)
2000 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
2001 if (tmp_crtc
->enabled
&& tmp_crtc
->fb
) {
2003 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
2004 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
2011 if (!crtc
|| crtc
->fb
== NULL
) {
2012 DRM_DEBUG_KMS("no output, disabling\n");
2013 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
2017 intel_crtc
= to_intel_crtc(crtc
);
2019 intel_fb
= to_intel_framebuffer(fb
);
2020 obj
= intel_fb
->obj
;
2022 if (intel_fb
->obj
->base
.size
> dev_priv
->cfb_size
) {
2023 DRM_DEBUG_KMS("framebuffer too large, disabling "
2025 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
2028 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
2029 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
2030 DRM_DEBUG_KMS("mode incompatible with compression, "
2032 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
2035 if ((crtc
->mode
.hdisplay
> 2048) ||
2036 (crtc
->mode
.vdisplay
> 1536)) {
2037 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2038 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
2041 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
2042 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2043 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
2046 if (obj
->tiling_mode
!= I915_TILING_X
) {
2047 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
2048 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
2052 /* If the kernel debugger is active, always disable compression */
2053 if (in_dbg_master())
2056 intel_enable_fbc(crtc
, 500);
2060 /* Multiple disables should be harmless */
2061 if (intel_fbc_enabled(dev
)) {
2062 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2063 intel_disable_fbc(dev
);
2068 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2069 struct drm_i915_gem_object
*obj
,
2070 struct intel_ring_buffer
*pipelined
)
2072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2076 switch (obj
->tiling_mode
) {
2077 case I915_TILING_NONE
:
2078 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2079 alignment
= 128 * 1024;
2080 else if (INTEL_INFO(dev
)->gen
>= 4)
2081 alignment
= 4 * 1024;
2083 alignment
= 64 * 1024;
2086 /* pin() will align the object as required by fence */
2090 /* FIXME: Is this true? */
2091 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2097 dev_priv
->mm
.interruptible
= false;
2098 ret
= i915_gem_object_pin(obj
, alignment
, true);
2100 goto err_interruptible
;
2102 ret
= i915_gem_object_set_to_display_plane(obj
, pipelined
);
2106 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2107 * fence, whereas 965+ only requires a fence if using
2108 * framebuffer compression. For simplicity, we always install
2109 * a fence as the cost is not that onerous.
2111 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
2112 ret
= i915_gem_object_get_fence(obj
, pipelined
);
2117 dev_priv
->mm
.interruptible
= true;
2121 i915_gem_object_unpin(obj
);
2123 dev_priv
->mm
.interruptible
= true;
2127 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2129 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2130 int x
, int y
, enum mode_set_atomic state
)
2132 struct drm_device
*dev
= crtc
->dev
;
2133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2135 struct intel_framebuffer
*intel_fb
;
2136 struct drm_i915_gem_object
*obj
;
2137 int plane
= intel_crtc
->plane
;
2138 unsigned long Start
, Offset
;
2147 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2151 intel_fb
= to_intel_framebuffer(fb
);
2152 obj
= intel_fb
->obj
;
2154 reg
= DSPCNTR(plane
);
2155 dspcntr
= I915_READ(reg
);
2156 /* Mask out pixel format bits in case we change it */
2157 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2158 switch (fb
->bits_per_pixel
) {
2160 dspcntr
|= DISPPLANE_8BPP
;
2163 if (fb
->depth
== 15)
2164 dspcntr
|= DISPPLANE_15_16BPP
;
2166 dspcntr
|= DISPPLANE_16BPP
;
2170 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2173 DRM_ERROR("Unknown color depth\n");
2176 if (INTEL_INFO(dev
)->gen
>= 4) {
2177 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2178 dspcntr
|= DISPPLANE_TILED
;
2180 dspcntr
&= ~DISPPLANE_TILED
;
2183 if (HAS_PCH_SPLIT(dev
))
2185 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2187 I915_WRITE(reg
, dspcntr
);
2189 Start
= obj
->gtt_offset
;
2190 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
2192 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2193 Start
, Offset
, x
, y
, fb
->pitch
);
2194 I915_WRITE(DSPSTRIDE(plane
), fb
->pitch
);
2195 if (INTEL_INFO(dev
)->gen
>= 4) {
2196 I915_WRITE(DSPSURF(plane
), Start
);
2197 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2198 I915_WRITE(DSPADDR(plane
), Offset
);
2200 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
2203 intel_update_fbc(dev
);
2204 intel_increase_pllclock(crtc
);
2210 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2211 struct drm_framebuffer
*old_fb
)
2213 struct drm_device
*dev
= crtc
->dev
;
2214 struct drm_i915_master_private
*master_priv
;
2215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2220 DRM_DEBUG_KMS("No FB bound\n");
2224 switch (intel_crtc
->plane
) {
2232 mutex_lock(&dev
->struct_mutex
);
2233 ret
= intel_pin_and_fence_fb_obj(dev
,
2234 to_intel_framebuffer(crtc
->fb
)->obj
,
2237 mutex_unlock(&dev
->struct_mutex
);
2242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2243 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2245 wait_event(dev_priv
->pending_flip_queue
,
2246 atomic_read(&dev_priv
->mm
.wedged
) ||
2247 atomic_read(&obj
->pending_flip
) == 0);
2249 /* Big Hammer, we also need to ensure that any pending
2250 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251 * current scanout is retired before unpinning the old
2254 * This should only fail upon a hung GPU, in which case we
2255 * can safely continue.
2257 ret
= i915_gem_object_flush_gpu(obj
);
2261 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
,
2262 LEAVE_ATOMIC_MODE_SET
);
2264 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
2265 mutex_unlock(&dev
->struct_mutex
);
2270 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2271 i915_gem_object_unpin(to_intel_framebuffer(old_fb
)->obj
);
2274 mutex_unlock(&dev
->struct_mutex
);
2276 if (!dev
->primary
->master
)
2279 master_priv
= dev
->primary
->master
->driver_priv
;
2280 if (!master_priv
->sarea_priv
)
2283 if (intel_crtc
->pipe
) {
2284 master_priv
->sarea_priv
->pipeB_x
= x
;
2285 master_priv
->sarea_priv
->pipeB_y
= y
;
2287 master_priv
->sarea_priv
->pipeA_x
= x
;
2288 master_priv
->sarea_priv
->pipeA_y
= y
;
2294 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2296 struct drm_device
*dev
= crtc
->dev
;
2297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2300 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2301 dpa_ctl
= I915_READ(DP_A
);
2302 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2304 if (clock
< 200000) {
2306 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2307 /* workaround for 160Mhz:
2308 1) program 0x4600c bits 15:0 = 0x8124
2309 2) program 0x46010 bit 0 = 1
2310 3) program 0x46034 bit 24 = 1
2311 4) program 0x64000 bit 14 = 1
2313 temp
= I915_READ(0x4600c);
2315 I915_WRITE(0x4600c, temp
| 0x8124);
2317 temp
= I915_READ(0x46010);
2318 I915_WRITE(0x46010, temp
| 1);
2320 temp
= I915_READ(0x46034);
2321 I915_WRITE(0x46034, temp
| (1 << 24));
2323 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2325 I915_WRITE(DP_A
, dpa_ctl
);
2331 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2336 int pipe
= intel_crtc
->pipe
;
2339 /* enable normal train */
2340 reg
= FDI_TX_CTL(pipe
);
2341 temp
= I915_READ(reg
);
2342 temp
&= ~FDI_LINK_TRAIN_NONE
;
2343 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2344 I915_WRITE(reg
, temp
);
2346 reg
= FDI_RX_CTL(pipe
);
2347 temp
= I915_READ(reg
);
2348 if (HAS_PCH_CPT(dev
)) {
2349 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2350 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2352 temp
&= ~FDI_LINK_TRAIN_NONE
;
2353 temp
|= FDI_LINK_TRAIN_NONE
;
2355 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2357 /* wait one idle pattern time */
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2365 struct drm_device
*dev
= crtc
->dev
;
2366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2368 int pipe
= intel_crtc
->pipe
;
2369 int plane
= intel_crtc
->plane
;
2370 u32 reg
, temp
, tries
;
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv
, pipe
);
2374 assert_plane_enabled(dev_priv
, plane
);
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2378 reg
= FDI_RX_IMR(pipe
);
2379 temp
= I915_READ(reg
);
2380 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2381 temp
&= ~FDI_RX_BIT_LOCK
;
2382 I915_WRITE(reg
, temp
);
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg
= FDI_TX_CTL(pipe
);
2388 temp
= I915_READ(reg
);
2390 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2391 temp
&= ~FDI_LINK_TRAIN_NONE
;
2392 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2393 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2395 reg
= FDI_RX_CTL(pipe
);
2396 temp
= I915_READ(reg
);
2397 temp
&= ~FDI_LINK_TRAIN_NONE
;
2398 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2399 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 if (HAS_PCH_IBX(dev
)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2408 FDI_RX_PHASE_SYNC_POINTER_EN
);
2411 reg
= FDI_RX_IIR(pipe
);
2412 for (tries
= 0; tries
< 5; tries
++) {
2413 temp
= I915_READ(reg
);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2416 if ((temp
& FDI_RX_BIT_LOCK
)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2423 DRM_ERROR("FDI train 1 fail!\n");
2426 reg
= FDI_TX_CTL(pipe
);
2427 temp
= I915_READ(reg
);
2428 temp
&= ~FDI_LINK_TRAIN_NONE
;
2429 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2430 I915_WRITE(reg
, temp
);
2432 reg
= FDI_RX_CTL(pipe
);
2433 temp
= I915_READ(reg
);
2434 temp
&= ~FDI_LINK_TRAIN_NONE
;
2435 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2436 I915_WRITE(reg
, temp
);
2441 reg
= FDI_RX_IIR(pipe
);
2442 for (tries
= 0; tries
< 5; tries
++) {
2443 temp
= I915_READ(reg
);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2446 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2447 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2453 DRM_ERROR("FDI train 2 fail!\n");
2455 DRM_DEBUG_KMS("FDI train done\n");
2459 static const int snb_b_fdi_train_param
[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2469 struct drm_device
*dev
= crtc
->dev
;
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2472 int pipe
= intel_crtc
->pipe
;
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477 reg
= FDI_RX_IMR(pipe
);
2478 temp
= I915_READ(reg
);
2479 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2480 temp
&= ~FDI_RX_BIT_LOCK
;
2481 I915_WRITE(reg
, temp
);
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg
= FDI_TX_CTL(pipe
);
2488 temp
= I915_READ(reg
);
2490 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2491 temp
&= ~FDI_LINK_TRAIN_NONE
;
2492 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2493 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2495 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2496 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2498 reg
= FDI_RX_CTL(pipe
);
2499 temp
= I915_READ(reg
);
2500 if (HAS_PCH_CPT(dev
)) {
2501 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2502 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2504 temp
&= ~FDI_LINK_TRAIN_NONE
;
2505 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2507 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2512 for (i
= 0; i
< 4; i
++ ) {
2513 reg
= FDI_TX_CTL(pipe
);
2514 temp
= I915_READ(reg
);
2515 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2516 temp
|= snb_b_fdi_train_param
[i
];
2517 I915_WRITE(reg
, temp
);
2522 reg
= FDI_RX_IIR(pipe
);
2523 temp
= I915_READ(reg
);
2524 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2526 if (temp
& FDI_RX_BIT_LOCK
) {
2527 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2528 DRM_DEBUG_KMS("FDI train 1 done.\n");
2533 DRM_ERROR("FDI train 1 fail!\n");
2536 reg
= FDI_TX_CTL(pipe
);
2537 temp
= I915_READ(reg
);
2538 temp
&= ~FDI_LINK_TRAIN_NONE
;
2539 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2541 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2543 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2545 I915_WRITE(reg
, temp
);
2547 reg
= FDI_RX_CTL(pipe
);
2548 temp
= I915_READ(reg
);
2549 if (HAS_PCH_CPT(dev
)) {
2550 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2551 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2553 temp
&= ~FDI_LINK_TRAIN_NONE
;
2554 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2556 I915_WRITE(reg
, temp
);
2561 for (i
= 0; i
< 4; i
++ ) {
2562 reg
= FDI_TX_CTL(pipe
);
2563 temp
= I915_READ(reg
);
2564 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2565 temp
|= snb_b_fdi_train_param
[i
];
2566 I915_WRITE(reg
, temp
);
2571 reg
= FDI_RX_IIR(pipe
);
2572 temp
= I915_READ(reg
);
2573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2575 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2576 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2582 DRM_ERROR("FDI train 2 fail!\n");
2584 DRM_DEBUG_KMS("FDI train done.\n");
2587 static void ironlake_fdi_enable(struct drm_crtc
*crtc
)
2589 struct drm_device
*dev
= crtc
->dev
;
2590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2592 int pipe
= intel_crtc
->pipe
;
2595 /* Write the TU size bits so error detection works */
2596 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2597 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2599 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2600 reg
= FDI_RX_CTL(pipe
);
2601 temp
= I915_READ(reg
);
2602 temp
&= ~((0x7 << 19) | (0x7 << 16));
2603 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2604 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2605 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2610 /* Switch from Rawclk to PCDclk */
2611 temp
= I915_READ(reg
);
2612 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2617 /* Enable CPU FDI TX PLL, always on for Ironlake */
2618 reg
= FDI_TX_CTL(pipe
);
2619 temp
= I915_READ(reg
);
2620 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2621 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2628 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2630 struct drm_device
*dev
= crtc
->dev
;
2631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2632 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2633 int pipe
= intel_crtc
->pipe
;
2636 /* disable CPU FDI tx and PCH FDI rx */
2637 reg
= FDI_TX_CTL(pipe
);
2638 temp
= I915_READ(reg
);
2639 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2642 reg
= FDI_RX_CTL(pipe
);
2643 temp
= I915_READ(reg
);
2644 temp
&= ~(0x7 << 16);
2645 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2646 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2651 /* Ironlake workaround, disable clock pointer after downing FDI */
2652 if (HAS_PCH_IBX(dev
)) {
2653 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2654 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2655 I915_READ(FDI_RX_CHICKEN(pipe
) &
2656 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2659 /* still set train pattern 1 */
2660 reg
= FDI_TX_CTL(pipe
);
2661 temp
= I915_READ(reg
);
2662 temp
&= ~FDI_LINK_TRAIN_NONE
;
2663 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2664 I915_WRITE(reg
, temp
);
2666 reg
= FDI_RX_CTL(pipe
);
2667 temp
= I915_READ(reg
);
2668 if (HAS_PCH_CPT(dev
)) {
2669 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2670 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2672 temp
&= ~FDI_LINK_TRAIN_NONE
;
2673 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2675 /* BPC in FDI rx is consistent with that in PIPECONF */
2676 temp
&= ~(0x07 << 16);
2677 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2678 I915_WRITE(reg
, temp
);
2685 * When we disable a pipe, we need to clear any pending scanline wait events
2686 * to avoid hanging the ring, which we assume we are waiting on.
2688 static void intel_clear_scanline_wait(struct drm_device
*dev
)
2690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2691 struct intel_ring_buffer
*ring
;
2695 /* Can't break the hang on i8xx */
2698 ring
= LP_RING(dev_priv
);
2699 tmp
= I915_READ_CTL(ring
);
2700 if (tmp
& RING_WAIT
)
2701 I915_WRITE_CTL(ring
, tmp
);
2704 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2706 struct drm_i915_gem_object
*obj
;
2707 struct drm_i915_private
*dev_priv
;
2709 if (crtc
->fb
== NULL
)
2712 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
2713 dev_priv
= crtc
->dev
->dev_private
;
2714 wait_event(dev_priv
->pending_flip_queue
,
2715 atomic_read(&obj
->pending_flip
) == 0);
2718 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2720 struct drm_device
*dev
= crtc
->dev
;
2721 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2722 struct intel_encoder
*encoder
;
2725 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2726 * must be driven by its own crtc; no sharing is possible.
2728 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
2729 if (encoder
->base
.crtc
!= crtc
)
2732 switch (encoder
->type
) {
2733 case INTEL_OUTPUT_EDP
:
2734 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2744 * Enable PCH resources required for PCH ports:
2746 * - FDI training & RX/TX
2747 * - update transcoder timings
2748 * - DP transcoding bits
2751 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2753 struct drm_device
*dev
= crtc
->dev
;
2754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2755 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2756 int pipe
= intel_crtc
->pipe
;
2759 /* For PCH output, training FDI link */
2761 gen6_fdi_link_train(crtc
);
2763 ironlake_fdi_link_train(crtc
);
2765 intel_enable_pch_pll(dev_priv
, pipe
);
2767 if (HAS_PCH_CPT(dev
)) {
2768 /* Be sure PCH DPLL SEL is set */
2769 temp
= I915_READ(PCH_DPLL_SEL
);
2770 if (pipe
== 0 && (temp
& TRANSA_DPLL_ENABLE
) == 0)
2771 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2772 else if (pipe
== 1 && (temp
& TRANSB_DPLL_ENABLE
) == 0)
2773 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2774 I915_WRITE(PCH_DPLL_SEL
, temp
);
2777 /* set transcoder timing, panel must allow it */
2778 assert_panel_unlocked(dev_priv
, pipe
);
2779 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2780 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2781 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2783 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2784 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2785 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2787 intel_fdi_normal_train(crtc
);
2789 /* For PCH DP, enable TRANS_DP_CTL */
2790 if (HAS_PCH_CPT(dev
) &&
2791 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2792 reg
= TRANS_DP_CTL(pipe
);
2793 temp
= I915_READ(reg
);
2794 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2795 TRANS_DP_SYNC_MASK
|
2797 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
2798 TRANS_DP_ENH_FRAMING
);
2799 temp
|= TRANS_DP_8BPC
;
2801 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2802 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2803 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2804 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2806 switch (intel_trans_dp_port_sel(crtc
)) {
2808 temp
|= TRANS_DP_PORT_SEL_B
;
2811 temp
|= TRANS_DP_PORT_SEL_C
;
2814 temp
|= TRANS_DP_PORT_SEL_D
;
2817 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2818 temp
|= TRANS_DP_PORT_SEL_B
;
2822 I915_WRITE(reg
, temp
);
2825 intel_enable_transcoder(dev_priv
, pipe
);
2828 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
2830 struct drm_device
*dev
= crtc
->dev
;
2831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2833 int pipe
= intel_crtc
->pipe
;
2834 int plane
= intel_crtc
->plane
;
2838 if (intel_crtc
->active
)
2841 intel_crtc
->active
= true;
2842 intel_update_watermarks(dev
);
2844 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2845 temp
= I915_READ(PCH_LVDS
);
2846 if ((temp
& LVDS_PORT_EN
) == 0)
2847 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
2850 is_pch_port
= intel_crtc_driving_pch(crtc
);
2853 ironlake_fdi_enable(crtc
);
2855 ironlake_fdi_disable(crtc
);
2857 /* Enable panel fitting for LVDS */
2858 if (dev_priv
->pch_pf_size
&&
2859 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
2860 /* Force use of hard-coded filter coefficients
2861 * as some pre-programmed values are broken,
2864 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
2865 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
2866 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
2869 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
2870 intel_enable_plane(dev_priv
, plane
, pipe
);
2873 ironlake_pch_enable(crtc
);
2875 intel_crtc_load_lut(crtc
);
2876 intel_update_fbc(dev
);
2877 intel_crtc_update_cursor(crtc
, true);
2880 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
2882 struct drm_device
*dev
= crtc
->dev
;
2883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2884 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2885 int pipe
= intel_crtc
->pipe
;
2886 int plane
= intel_crtc
->plane
;
2889 if (!intel_crtc
->active
)
2892 intel_crtc_wait_for_pending_flips(crtc
);
2893 drm_vblank_off(dev
, pipe
);
2894 intel_crtc_update_cursor(crtc
, false);
2896 intel_disable_plane(dev_priv
, plane
, pipe
);
2898 if (dev_priv
->cfb_plane
== plane
&&
2899 dev_priv
->display
.disable_fbc
)
2900 dev_priv
->display
.disable_fbc(dev
);
2902 intel_disable_pipe(dev_priv
, pipe
);
2905 I915_WRITE(PF_CTL(pipe
), 0);
2906 I915_WRITE(PF_WIN_SZ(pipe
), 0);
2908 ironlake_fdi_disable(crtc
);
2910 /* This is a horrible layering violation; we should be doing this in
2911 * the connector/encoder ->prepare instead, but we don't always have
2912 * enough information there about the config to know whether it will
2913 * actually be necessary or just cause undesired flicker.
2915 intel_disable_pch_ports(dev_priv
, pipe
);
2917 intel_disable_transcoder(dev_priv
, pipe
);
2919 if (HAS_PCH_CPT(dev
)) {
2920 /* disable TRANS_DP_CTL */
2921 reg
= TRANS_DP_CTL(pipe
);
2922 temp
= I915_READ(reg
);
2923 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2924 temp
|= TRANS_DP_PORT_SEL_NONE
;
2925 I915_WRITE(reg
, temp
);
2927 /* disable DPLL_SEL */
2928 temp
= I915_READ(PCH_DPLL_SEL
);
2931 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2934 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2937 /* FIXME: manage transcoder PLLs? */
2938 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
2943 I915_WRITE(PCH_DPLL_SEL
, temp
);
2946 /* disable PCH DPLL */
2947 intel_disable_pch_pll(dev_priv
, pipe
);
2949 /* Switch from PCDclk to Rawclk */
2950 reg
= FDI_RX_CTL(pipe
);
2951 temp
= I915_READ(reg
);
2952 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2954 /* Disable CPU FDI TX PLL */
2955 reg
= FDI_TX_CTL(pipe
);
2956 temp
= I915_READ(reg
);
2957 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2962 reg
= FDI_RX_CTL(pipe
);
2963 temp
= I915_READ(reg
);
2964 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2966 /* Wait for the clocks to turn off. */
2970 intel_crtc
->active
= false;
2971 intel_update_watermarks(dev
);
2972 intel_update_fbc(dev
);
2973 intel_clear_scanline_wait(dev
);
2976 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2978 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2979 int pipe
= intel_crtc
->pipe
;
2980 int plane
= intel_crtc
->plane
;
2982 /* XXX: When our outputs are all unaware of DPMS modes other than off
2983 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2986 case DRM_MODE_DPMS_ON
:
2987 case DRM_MODE_DPMS_STANDBY
:
2988 case DRM_MODE_DPMS_SUSPEND
:
2989 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
2990 ironlake_crtc_enable(crtc
);
2993 case DRM_MODE_DPMS_OFF
:
2994 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
2995 ironlake_crtc_disable(crtc
);
3000 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3002 if (!enable
&& intel_crtc
->overlay
) {
3003 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3006 mutex_lock(&dev
->struct_mutex
);
3007 dev_priv
->mm
.interruptible
= false;
3008 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3009 dev_priv
->mm
.interruptible
= true;
3010 mutex_unlock(&dev
->struct_mutex
);
3013 /* Let userspace switch the overlay on again. In most cases userspace
3014 * has to recompute where to put it anyway.
3018 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3020 struct drm_device
*dev
= crtc
->dev
;
3021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3022 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3023 int pipe
= intel_crtc
->pipe
;
3024 int plane
= intel_crtc
->plane
;
3026 if (intel_crtc
->active
)
3029 intel_crtc
->active
= true;
3030 intel_update_watermarks(dev
);
3032 intel_enable_pll(dev_priv
, pipe
);
3033 intel_enable_pipe(dev_priv
, pipe
, false);
3034 intel_enable_plane(dev_priv
, plane
, pipe
);
3036 intel_crtc_load_lut(crtc
);
3037 intel_update_fbc(dev
);
3039 /* Give the overlay scaler a chance to enable if it's on this pipe */
3040 intel_crtc_dpms_overlay(intel_crtc
, true);
3041 intel_crtc_update_cursor(crtc
, true);
3044 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3046 struct drm_device
*dev
= crtc
->dev
;
3047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3048 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3049 int pipe
= intel_crtc
->pipe
;
3050 int plane
= intel_crtc
->plane
;
3052 if (!intel_crtc
->active
)
3055 /* Give the overlay scaler a chance to disable if it's on this pipe */
3056 intel_crtc_wait_for_pending_flips(crtc
);
3057 drm_vblank_off(dev
, pipe
);
3058 intel_crtc_dpms_overlay(intel_crtc
, false);
3059 intel_crtc_update_cursor(crtc
, false);
3061 if (dev_priv
->cfb_plane
== plane
&&
3062 dev_priv
->display
.disable_fbc
)
3063 dev_priv
->display
.disable_fbc(dev
);
3065 intel_disable_plane(dev_priv
, plane
, pipe
);
3066 intel_disable_pipe(dev_priv
, pipe
);
3067 intel_disable_pll(dev_priv
, pipe
);
3069 intel_crtc
->active
= false;
3070 intel_update_fbc(dev
);
3071 intel_update_watermarks(dev
);
3072 intel_clear_scanline_wait(dev
);
3075 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3077 /* XXX: When our outputs are all unaware of DPMS modes other than off
3078 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3081 case DRM_MODE_DPMS_ON
:
3082 case DRM_MODE_DPMS_STANDBY
:
3083 case DRM_MODE_DPMS_SUSPEND
:
3084 i9xx_crtc_enable(crtc
);
3086 case DRM_MODE_DPMS_OFF
:
3087 i9xx_crtc_disable(crtc
);
3093 * Sets the power management mode of the pipe and plane.
3095 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3097 struct drm_device
*dev
= crtc
->dev
;
3098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3099 struct drm_i915_master_private
*master_priv
;
3100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3101 int pipe
= intel_crtc
->pipe
;
3104 if (intel_crtc
->dpms_mode
== mode
)
3107 intel_crtc
->dpms_mode
= mode
;
3109 dev_priv
->display
.dpms(crtc
, mode
);
3111 if (!dev
->primary
->master
)
3114 master_priv
= dev
->primary
->master
->driver_priv
;
3115 if (!master_priv
->sarea_priv
)
3118 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
3122 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3123 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3126 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3127 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3130 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3135 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3137 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3138 struct drm_device
*dev
= crtc
->dev
;
3140 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3143 mutex_lock(&dev
->struct_mutex
);
3144 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
3145 mutex_unlock(&dev
->struct_mutex
);
3149 /* Prepare for a mode set.
3151 * Note we could be a lot smarter here. We need to figure out which outputs
3152 * will be enabled, which disabled (in short, how the config will changes)
3153 * and perform the minimum necessary steps to accomplish that, e.g. updating
3154 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3155 * panel fitting is in the proper state, etc.
3157 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3159 i9xx_crtc_disable(crtc
);
3162 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3164 i9xx_crtc_enable(crtc
);
3167 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3169 ironlake_crtc_disable(crtc
);
3172 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3174 ironlake_crtc_enable(crtc
);
3177 void intel_encoder_prepare (struct drm_encoder
*encoder
)
3179 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3180 /* lvds has its own version of prepare see intel_lvds_prepare */
3181 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3184 void intel_encoder_commit (struct drm_encoder
*encoder
)
3186 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3187 /* lvds has its own version of commit see intel_lvds_commit */
3188 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3191 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3193 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3195 drm_encoder_cleanup(encoder
);
3196 kfree(intel_encoder
);
3199 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3200 struct drm_display_mode
*mode
,
3201 struct drm_display_mode
*adjusted_mode
)
3203 struct drm_device
*dev
= crtc
->dev
;
3205 if (HAS_PCH_SPLIT(dev
)) {
3206 /* FDI link clock is fixed at 2.7G */
3207 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3211 /* XXX some encoders set the crtcinfo, others don't.
3212 * Obviously we need some form of conflict resolution here...
3214 if (adjusted_mode
->crtc_htotal
== 0)
3215 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3220 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3225 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3230 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3235 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3239 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3241 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3244 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3245 case GC_DISPLAY_CLOCK_333_MHZ
:
3248 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3254 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3259 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3262 /* Assume that the hardware is in the high speed state. This
3263 * should be the default.
3265 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3266 case GC_CLOCK_133_200
:
3267 case GC_CLOCK_100_200
:
3269 case GC_CLOCK_166_250
:
3271 case GC_CLOCK_100_133
:
3275 /* Shouldn't happen */
3279 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3293 fdi_reduce_ratio(u32
*num
, u32
*den
)
3295 while (*num
> 0xffffff || *den
> 0xffffff) {
3302 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3303 int link_clock
, struct fdi_m_n
*m_n
)
3305 m_n
->tu
= 64; /* default size */
3307 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3308 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3309 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3310 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3312 m_n
->link_m
= pixel_clock
;
3313 m_n
->link_n
= link_clock
;
3314 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3318 struct intel_watermark_params
{
3319 unsigned long fifo_size
;
3320 unsigned long max_wm
;
3321 unsigned long default_wm
;
3322 unsigned long guard_size
;
3323 unsigned long cacheline_size
;
3326 /* Pineview has different values for various configs */
3327 static const struct intel_watermark_params pineview_display_wm
= {
3328 PINEVIEW_DISPLAY_FIFO
,
3332 PINEVIEW_FIFO_LINE_SIZE
3334 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
3335 PINEVIEW_DISPLAY_FIFO
,
3337 PINEVIEW_DFT_HPLLOFF_WM
,
3339 PINEVIEW_FIFO_LINE_SIZE
3341 static const struct intel_watermark_params pineview_cursor_wm
= {
3342 PINEVIEW_CURSOR_FIFO
,
3343 PINEVIEW_CURSOR_MAX_WM
,
3344 PINEVIEW_CURSOR_DFT_WM
,
3345 PINEVIEW_CURSOR_GUARD_WM
,
3346 PINEVIEW_FIFO_LINE_SIZE
,
3348 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
3349 PINEVIEW_CURSOR_FIFO
,
3350 PINEVIEW_CURSOR_MAX_WM
,
3351 PINEVIEW_CURSOR_DFT_WM
,
3352 PINEVIEW_CURSOR_GUARD_WM
,
3353 PINEVIEW_FIFO_LINE_SIZE
3355 static const struct intel_watermark_params g4x_wm_info
= {
3362 static const struct intel_watermark_params g4x_cursor_wm_info
= {
3369 static const struct intel_watermark_params i965_cursor_wm_info
= {
3374 I915_FIFO_LINE_SIZE
,
3376 static const struct intel_watermark_params i945_wm_info
= {
3383 static const struct intel_watermark_params i915_wm_info
= {
3390 static const struct intel_watermark_params i855_wm_info
= {
3397 static const struct intel_watermark_params i830_wm_info
= {
3405 static const struct intel_watermark_params ironlake_display_wm_info
= {
3412 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
3419 static const struct intel_watermark_params ironlake_display_srwm_info
= {
3420 ILK_DISPLAY_SR_FIFO
,
3421 ILK_DISPLAY_MAX_SRWM
,
3422 ILK_DISPLAY_DFT_SRWM
,
3426 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
3428 ILK_CURSOR_MAX_SRWM
,
3429 ILK_CURSOR_DFT_SRWM
,
3434 static const struct intel_watermark_params sandybridge_display_wm_info
= {
3441 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
3448 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
3449 SNB_DISPLAY_SR_FIFO
,
3450 SNB_DISPLAY_MAX_SRWM
,
3451 SNB_DISPLAY_DFT_SRWM
,
3455 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
3457 SNB_CURSOR_MAX_SRWM
,
3458 SNB_CURSOR_DFT_SRWM
,
3465 * intel_calculate_wm - calculate watermark level
3466 * @clock_in_khz: pixel clock
3467 * @wm: chip FIFO params
3468 * @pixel_size: display pixel size
3469 * @latency_ns: memory latency for the platform
3471 * Calculate the watermark level (the level at which the display plane will
3472 * start fetching from memory again). Each chip has a different display
3473 * FIFO size and allocation, so the caller needs to figure that out and pass
3474 * in the correct intel_watermark_params structure.
3476 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3477 * on the pixel size. When it reaches the watermark level, it'll start
3478 * fetching FIFO line sized based chunks from memory until the FIFO fills
3479 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3480 * will occur, and a display engine hang could result.
3482 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
3483 const struct intel_watermark_params
*wm
,
3486 unsigned long latency_ns
)
3488 long entries_required
, wm_size
;
3491 * Note: we need to make sure we don't overflow for various clock &
3493 * clocks go from a few thousand to several hundred thousand.
3494 * latency is usually a few thousand
3496 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
3498 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
3500 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
3502 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
3504 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
3506 /* Don't promote wm_size to unsigned... */
3507 if (wm_size
> (long)wm
->max_wm
)
3508 wm_size
= wm
->max_wm
;
3510 wm_size
= wm
->default_wm
;
3514 struct cxsr_latency
{
3517 unsigned long fsb_freq
;
3518 unsigned long mem_freq
;
3519 unsigned long display_sr
;
3520 unsigned long display_hpll_disable
;
3521 unsigned long cursor_sr
;
3522 unsigned long cursor_hpll_disable
;
3525 static const struct cxsr_latency cxsr_latency_table
[] = {
3526 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3527 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3528 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3529 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3530 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3532 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3533 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3534 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3535 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3536 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3538 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3539 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3540 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3541 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3542 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3544 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3545 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3546 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3547 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3548 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3550 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3551 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3552 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3553 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3554 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3556 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3557 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3558 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3559 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3560 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3563 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
3568 const struct cxsr_latency
*latency
;
3571 if (fsb
== 0 || mem
== 0)
3574 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
3575 latency
= &cxsr_latency_table
[i
];
3576 if (is_desktop
== latency
->is_desktop
&&
3577 is_ddr3
== latency
->is_ddr3
&&
3578 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
3582 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3587 static void pineview_disable_cxsr(struct drm_device
*dev
)
3589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3591 /* deactivate cxsr */
3592 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
3596 * Latency for FIFO fetches is dependent on several factors:
3597 * - memory configuration (speed, channels)
3599 * - current MCH state
3600 * It can be fairly high in some situations, so here we assume a fairly
3601 * pessimal value. It's a tradeoff between extra memory fetches (if we
3602 * set this value too high, the FIFO will fetch frequently to stay full)
3603 * and power consumption (set it too low to save power and we might see
3604 * FIFO underruns and display "flicker").
3606 * A value of 5us seems to be a good balance; safe for very low end
3607 * platforms but not overly aggressive on lower latency configs.
3609 static const int latency_ns
= 5000;
3611 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
3613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3614 uint32_t dsparb
= I915_READ(DSPARB
);
3617 size
= dsparb
& 0x7f;
3619 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
3621 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3622 plane
? "B" : "A", size
);
3627 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
3629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3630 uint32_t dsparb
= I915_READ(DSPARB
);
3633 size
= dsparb
& 0x1ff;
3635 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
3636 size
>>= 1; /* Convert to cachelines */
3638 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3639 plane
? "B" : "A", size
);
3644 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
3646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3647 uint32_t dsparb
= I915_READ(DSPARB
);
3650 size
= dsparb
& 0x7f;
3651 size
>>= 2; /* Convert to cachelines */
3653 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3660 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3663 uint32_t dsparb
= I915_READ(DSPARB
);
3666 size
= dsparb
& 0x7f;
3667 size
>>= 1; /* Convert to cachelines */
3669 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3670 plane
? "B" : "A", size
);
3675 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
3677 struct drm_crtc
*crtc
, *enabled
= NULL
;
3679 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3680 if (crtc
->enabled
&& crtc
->fb
) {
3690 static void pineview_update_wm(struct drm_device
*dev
)
3692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3693 struct drm_crtc
*crtc
;
3694 const struct cxsr_latency
*latency
;
3698 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3699 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3701 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3702 pineview_disable_cxsr(dev
);
3706 crtc
= single_enabled_crtc(dev
);
3708 int clock
= crtc
->mode
.clock
;
3709 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3712 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
3713 pineview_display_wm
.fifo_size
,
3714 pixel_size
, latency
->display_sr
);
3715 reg
= I915_READ(DSPFW1
);
3716 reg
&= ~DSPFW_SR_MASK
;
3717 reg
|= wm
<< DSPFW_SR_SHIFT
;
3718 I915_WRITE(DSPFW1
, reg
);
3719 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3722 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
3723 pineview_display_wm
.fifo_size
,
3724 pixel_size
, latency
->cursor_sr
);
3725 reg
= I915_READ(DSPFW3
);
3726 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3727 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3728 I915_WRITE(DSPFW3
, reg
);
3730 /* Display HPLL off SR */
3731 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
3732 pineview_display_hplloff_wm
.fifo_size
,
3733 pixel_size
, latency
->display_hpll_disable
);
3734 reg
= I915_READ(DSPFW3
);
3735 reg
&= ~DSPFW_HPLL_SR_MASK
;
3736 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3737 I915_WRITE(DSPFW3
, reg
);
3739 /* cursor HPLL off SR */
3740 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
3741 pineview_display_hplloff_wm
.fifo_size
,
3742 pixel_size
, latency
->cursor_hpll_disable
);
3743 reg
= I915_READ(DSPFW3
);
3744 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3745 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3746 I915_WRITE(DSPFW3
, reg
);
3747 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3751 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3752 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3754 pineview_disable_cxsr(dev
);
3755 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3759 static bool g4x_compute_wm0(struct drm_device
*dev
,
3761 const struct intel_watermark_params
*display
,
3762 int display_latency_ns
,
3763 const struct intel_watermark_params
*cursor
,
3764 int cursor_latency_ns
,
3768 struct drm_crtc
*crtc
;
3769 int htotal
, hdisplay
, clock
, pixel_size
;
3770 int line_time_us
, line_count
;
3771 int entries
, tlb_miss
;
3773 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3774 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
3775 *cursor_wm
= cursor
->guard_size
;
3776 *plane_wm
= display
->guard_size
;
3780 htotal
= crtc
->mode
.htotal
;
3781 hdisplay
= crtc
->mode
.hdisplay
;
3782 clock
= crtc
->mode
.clock
;
3783 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3785 /* Use the small buffer method to calculate plane watermark */
3786 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
3787 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
3789 entries
+= tlb_miss
;
3790 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
3791 *plane_wm
= entries
+ display
->guard_size
;
3792 if (*plane_wm
> (int)display
->max_wm
)
3793 *plane_wm
= display
->max_wm
;
3795 /* Use the large buffer method to calculate cursor watermark */
3796 line_time_us
= ((htotal
* 1000) / clock
);
3797 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
3798 entries
= line_count
* 64 * pixel_size
;
3799 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
3801 entries
+= tlb_miss
;
3802 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
3803 *cursor_wm
= entries
+ cursor
->guard_size
;
3804 if (*cursor_wm
> (int)cursor
->max_wm
)
3805 *cursor_wm
= (int)cursor
->max_wm
;
3811 * Check the wm result.
3813 * If any calculated watermark values is larger than the maximum value that
3814 * can be programmed into the associated watermark register, that watermark
3817 static bool g4x_check_srwm(struct drm_device
*dev
,
3818 int display_wm
, int cursor_wm
,
3819 const struct intel_watermark_params
*display
,
3820 const struct intel_watermark_params
*cursor
)
3822 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3823 display_wm
, cursor_wm
);
3825 if (display_wm
> display
->max_wm
) {
3826 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3827 display_wm
, display
->max_wm
);
3831 if (cursor_wm
> cursor
->max_wm
) {
3832 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3833 cursor_wm
, cursor
->max_wm
);
3837 if (!(display_wm
|| cursor_wm
)) {
3838 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3845 static bool g4x_compute_srwm(struct drm_device
*dev
,
3848 const struct intel_watermark_params
*display
,
3849 const struct intel_watermark_params
*cursor
,
3850 int *display_wm
, int *cursor_wm
)
3852 struct drm_crtc
*crtc
;
3853 int hdisplay
, htotal
, pixel_size
, clock
;
3854 unsigned long line_time_us
;
3855 int line_count
, line_size
;
3860 *display_wm
= *cursor_wm
= 0;
3864 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3865 hdisplay
= crtc
->mode
.hdisplay
;
3866 htotal
= crtc
->mode
.htotal
;
3867 clock
= crtc
->mode
.clock
;
3868 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3870 line_time_us
= (htotal
* 1000) / clock
;
3871 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
3872 line_size
= hdisplay
* pixel_size
;
3874 /* Use the minimum of the small and large buffer method for primary */
3875 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
3876 large
= line_count
* line_size
;
3878 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
3879 *display_wm
= entries
+ display
->guard_size
;
3881 /* calculate the self-refresh watermark for display cursor */
3882 entries
= line_count
* pixel_size
* 64;
3883 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
3884 *cursor_wm
= entries
+ cursor
->guard_size
;
3886 return g4x_check_srwm(dev
,
3887 *display_wm
, *cursor_wm
,
3891 #define single_plane_enabled(mask) is_power_of_2(mask)
3893 static void g4x_update_wm(struct drm_device
*dev
)
3895 static const int sr_latency_ns
= 12000;
3896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3897 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3898 int plane_sr
, cursor_sr
;
3899 unsigned int enabled
= 0;
3901 if (g4x_compute_wm0(dev
, 0,
3902 &g4x_wm_info
, latency_ns
,
3903 &g4x_cursor_wm_info
, latency_ns
,
3904 &planea_wm
, &cursora_wm
))
3907 if (g4x_compute_wm0(dev
, 1,
3908 &g4x_wm_info
, latency_ns
,
3909 &g4x_cursor_wm_info
, latency_ns
,
3910 &planeb_wm
, &cursorb_wm
))
3913 plane_sr
= cursor_sr
= 0;
3914 if (single_plane_enabled(enabled
) &&
3915 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
3918 &g4x_cursor_wm_info
,
3919 &plane_sr
, &cursor_sr
))
3920 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3922 I915_WRITE(FW_BLC_SELF
,
3923 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
3925 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3926 planea_wm
, cursora_wm
,
3927 planeb_wm
, cursorb_wm
,
3928 plane_sr
, cursor_sr
);
3931 (plane_sr
<< DSPFW_SR_SHIFT
) |
3932 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3933 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
3936 (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3937 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3938 /* HPLL off in SR has some issues on G4x... disable it */
3940 (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3941 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3944 static void i965_update_wm(struct drm_device
*dev
)
3946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3947 struct drm_crtc
*crtc
;
3951 /* Calc sr entries for one plane configs */
3952 crtc
= single_enabled_crtc(dev
);
3954 /* self-refresh has much higher latency */
3955 static const int sr_latency_ns
= 12000;
3956 int clock
= crtc
->mode
.clock
;
3957 int htotal
= crtc
->mode
.htotal
;
3958 int hdisplay
= crtc
->mode
.hdisplay
;
3959 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3960 unsigned long line_time_us
;
3963 line_time_us
= ((htotal
* 1000) / clock
);
3965 /* Use ns/us then divide to preserve precision */
3966 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3967 pixel_size
* hdisplay
;
3968 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
3969 srwm
= I965_FIFO_SIZE
- entries
;
3973 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3976 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3978 entries
= DIV_ROUND_UP(entries
,
3979 i965_cursor_wm_info
.cacheline_size
);
3980 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3981 (entries
+ i965_cursor_wm_info
.guard_size
);
3983 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3984 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3986 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3987 "cursor %d\n", srwm
, cursor_sr
);
3989 if (IS_CRESTLINE(dev
))
3990 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3992 /* Turn off self refresh if both pipes are enabled */
3993 if (IS_CRESTLINE(dev
))
3994 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3998 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4001 /* 965 has limitations... */
4002 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
4003 (8 << 16) | (8 << 8) | (8 << 0));
4004 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
4005 /* update cursor SR watermark */
4006 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
4009 static void i9xx_update_wm(struct drm_device
*dev
)
4011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4012 const struct intel_watermark_params
*wm_info
;
4017 int planea_wm
, planeb_wm
;
4018 struct drm_crtc
*crtc
, *enabled
= NULL
;
4021 wm_info
= &i945_wm_info
;
4022 else if (!IS_GEN2(dev
))
4023 wm_info
= &i915_wm_info
;
4025 wm_info
= &i855_wm_info
;
4027 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
4028 crtc
= intel_get_crtc_for_plane(dev
, 0);
4029 if (crtc
->enabled
&& crtc
->fb
) {
4030 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
4032 crtc
->fb
->bits_per_pixel
/ 8,
4036 planea_wm
= fifo_size
- wm_info
->guard_size
;
4038 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
4039 crtc
= intel_get_crtc_for_plane(dev
, 1);
4040 if (crtc
->enabled
&& crtc
->fb
) {
4041 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
4043 crtc
->fb
->bits_per_pixel
/ 8,
4045 if (enabled
== NULL
)
4050 planeb_wm
= fifo_size
- wm_info
->guard_size
;
4052 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
4055 * Overlay gets an aggressive default since video jitter is bad.
4059 /* Play safe and disable self-refresh before adjusting watermarks. */
4060 if (IS_I945G(dev
) || IS_I945GM(dev
))
4061 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
4062 else if (IS_I915GM(dev
))
4063 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
4065 /* Calc sr entries for one plane configs */
4066 if (HAS_FW_BLC(dev
) && enabled
) {
4067 /* self-refresh has much higher latency */
4068 static const int sr_latency_ns
= 6000;
4069 int clock
= enabled
->mode
.clock
;
4070 int htotal
= enabled
->mode
.htotal
;
4071 int hdisplay
= enabled
->mode
.hdisplay
;
4072 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
4073 unsigned long line_time_us
;
4076 line_time_us
= (htotal
* 1000) / clock
;
4078 /* Use ns/us then divide to preserve precision */
4079 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
4080 pixel_size
* hdisplay
;
4081 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
4082 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
4083 srwm
= wm_info
->fifo_size
- entries
;
4087 if (IS_I945G(dev
) || IS_I945GM(dev
))
4088 I915_WRITE(FW_BLC_SELF
,
4089 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
4090 else if (IS_I915GM(dev
))
4091 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
4094 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4095 planea_wm
, planeb_wm
, cwm
, srwm
);
4097 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
4098 fwater_hi
= (cwm
& 0x1f);
4100 /* Set request length to 8 cachelines per fetch */
4101 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
4102 fwater_hi
= fwater_hi
| (1 << 8);
4104 I915_WRITE(FW_BLC
, fwater_lo
);
4105 I915_WRITE(FW_BLC2
, fwater_hi
);
4107 if (HAS_FW_BLC(dev
)) {
4109 if (IS_I945G(dev
) || IS_I945GM(dev
))
4110 I915_WRITE(FW_BLC_SELF
,
4111 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4112 else if (IS_I915GM(dev
))
4113 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
4114 DRM_DEBUG_KMS("memory self refresh enabled\n");
4116 DRM_DEBUG_KMS("memory self refresh disabled\n");
4120 static void i830_update_wm(struct drm_device
*dev
)
4122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4123 struct drm_crtc
*crtc
;
4127 crtc
= single_enabled_crtc(dev
);
4131 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
4132 dev_priv
->display
.get_fifo_size(dev
, 0),
4133 crtc
->fb
->bits_per_pixel
/ 8,
4135 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
4136 fwater_lo
|= (3<<8) | planea_wm
;
4138 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
4140 I915_WRITE(FW_BLC
, fwater_lo
);
4143 #define ILK_LP0_PLANE_LATENCY 700
4144 #define ILK_LP0_CURSOR_LATENCY 1300
4146 static bool ironlake_compute_wm0(struct drm_device
*dev
,
4148 const struct intel_watermark_params
*display
,
4149 int display_latency_ns
,
4150 const struct intel_watermark_params
*cursor
,
4151 int cursor_latency_ns
,
4155 struct drm_crtc
*crtc
;
4156 int htotal
, hdisplay
, clock
, pixel_size
;
4157 int line_time_us
, line_count
;
4158 int entries
, tlb_miss
;
4160 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
4161 if (crtc
->fb
== NULL
|| !crtc
->enabled
)
4164 htotal
= crtc
->mode
.htotal
;
4165 hdisplay
= crtc
->mode
.hdisplay
;
4166 clock
= crtc
->mode
.clock
;
4167 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4169 /* Use the small buffer method to calculate plane watermark */
4170 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
4171 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
4173 entries
+= tlb_miss
;
4174 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
4175 *plane_wm
= entries
+ display
->guard_size
;
4176 if (*plane_wm
> (int)display
->max_wm
)
4177 *plane_wm
= display
->max_wm
;
4179 /* Use the large buffer method to calculate cursor watermark */
4180 line_time_us
= ((htotal
* 1000) / clock
);
4181 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
4182 entries
= line_count
* 64 * pixel_size
;
4183 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
4185 entries
+= tlb_miss
;
4186 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4187 *cursor_wm
= entries
+ cursor
->guard_size
;
4188 if (*cursor_wm
> (int)cursor
->max_wm
)
4189 *cursor_wm
= (int)cursor
->max_wm
;
4195 * Check the wm result.
4197 * If any calculated watermark values is larger than the maximum value that
4198 * can be programmed into the associated watermark register, that watermark
4201 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
4202 int fbc_wm
, int display_wm
, int cursor_wm
,
4203 const struct intel_watermark_params
*display
,
4204 const struct intel_watermark_params
*cursor
)
4206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4208 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4209 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
4211 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
4212 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4213 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
4215 /* fbc has it's own way to disable FBC WM */
4216 I915_WRITE(DISP_ARB_CTL
,
4217 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
4221 if (display_wm
> display
->max_wm
) {
4222 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4223 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
4227 if (cursor_wm
> cursor
->max_wm
) {
4228 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4229 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
4233 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
4234 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
4242 * Compute watermark values of WM[1-3],
4244 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
4246 const struct intel_watermark_params
*display
,
4247 const struct intel_watermark_params
*cursor
,
4248 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
4250 struct drm_crtc
*crtc
;
4251 unsigned long line_time_us
;
4252 int hdisplay
, htotal
, pixel_size
, clock
;
4253 int line_count
, line_size
;
4258 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
4262 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4263 hdisplay
= crtc
->mode
.hdisplay
;
4264 htotal
= crtc
->mode
.htotal
;
4265 clock
= crtc
->mode
.clock
;
4266 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4268 line_time_us
= (htotal
* 1000) / clock
;
4269 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
4270 line_size
= hdisplay
* pixel_size
;
4272 /* Use the minimum of the small and large buffer method for primary */
4273 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
4274 large
= line_count
* line_size
;
4276 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
4277 *display_wm
= entries
+ display
->guard_size
;
4281 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4283 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
4285 /* calculate the self-refresh watermark for display cursor */
4286 entries
= line_count
* pixel_size
* 64;
4287 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4288 *cursor_wm
= entries
+ cursor
->guard_size
;
4290 return ironlake_check_srwm(dev
, level
,
4291 *fbc_wm
, *display_wm
, *cursor_wm
,
4295 static void ironlake_update_wm(struct drm_device
*dev
)
4297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4298 int fbc_wm
, plane_wm
, cursor_wm
;
4299 unsigned int enabled
;
4302 if (ironlake_compute_wm0(dev
, 0,
4303 &ironlake_display_wm_info
,
4304 ILK_LP0_PLANE_LATENCY
,
4305 &ironlake_cursor_wm_info
,
4306 ILK_LP0_CURSOR_LATENCY
,
4307 &plane_wm
, &cursor_wm
)) {
4308 I915_WRITE(WM0_PIPEA_ILK
,
4309 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4310 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4311 " plane %d, " "cursor: %d\n",
4312 plane_wm
, cursor_wm
);
4316 if (ironlake_compute_wm0(dev
, 1,
4317 &ironlake_display_wm_info
,
4318 ILK_LP0_PLANE_LATENCY
,
4319 &ironlake_cursor_wm_info
,
4320 ILK_LP0_CURSOR_LATENCY
,
4321 &plane_wm
, &cursor_wm
)) {
4322 I915_WRITE(WM0_PIPEB_ILK
,
4323 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4324 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4325 " plane %d, cursor: %d\n",
4326 plane_wm
, cursor_wm
);
4331 * Calculate and update the self-refresh watermark only when one
4332 * display plane is used.
4334 I915_WRITE(WM3_LP_ILK
, 0);
4335 I915_WRITE(WM2_LP_ILK
, 0);
4336 I915_WRITE(WM1_LP_ILK
, 0);
4338 if (!single_plane_enabled(enabled
))
4340 enabled
= ffs(enabled
) - 1;
4343 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4344 ILK_READ_WM1_LATENCY() * 500,
4345 &ironlake_display_srwm_info
,
4346 &ironlake_cursor_srwm_info
,
4347 &fbc_wm
, &plane_wm
, &cursor_wm
))
4350 I915_WRITE(WM1_LP_ILK
,
4352 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4353 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4354 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4358 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4359 ILK_READ_WM2_LATENCY() * 500,
4360 &ironlake_display_srwm_info
,
4361 &ironlake_cursor_srwm_info
,
4362 &fbc_wm
, &plane_wm
, &cursor_wm
))
4365 I915_WRITE(WM2_LP_ILK
,
4367 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4368 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4369 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4373 * WM3 is unsupported on ILK, probably because we don't have latency
4374 * data for that power state
4378 static void sandybridge_update_wm(struct drm_device
*dev
)
4380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4381 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4382 int fbc_wm
, plane_wm
, cursor_wm
;
4383 unsigned int enabled
;
4386 if (ironlake_compute_wm0(dev
, 0,
4387 &sandybridge_display_wm_info
, latency
,
4388 &sandybridge_cursor_wm_info
, latency
,
4389 &plane_wm
, &cursor_wm
)) {
4390 I915_WRITE(WM0_PIPEA_ILK
,
4391 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4392 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4393 " plane %d, " "cursor: %d\n",
4394 plane_wm
, cursor_wm
);
4398 if (ironlake_compute_wm0(dev
, 1,
4399 &sandybridge_display_wm_info
, latency
,
4400 &sandybridge_cursor_wm_info
, latency
,
4401 &plane_wm
, &cursor_wm
)) {
4402 I915_WRITE(WM0_PIPEB_ILK
,
4403 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4404 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4405 " plane %d, cursor: %d\n",
4406 plane_wm
, cursor_wm
);
4411 * Calculate and update the self-refresh watermark only when one
4412 * display plane is used.
4414 * SNB support 3 levels of watermark.
4416 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4417 * and disabled in the descending order
4420 I915_WRITE(WM3_LP_ILK
, 0);
4421 I915_WRITE(WM2_LP_ILK
, 0);
4422 I915_WRITE(WM1_LP_ILK
, 0);
4424 if (!single_plane_enabled(enabled
))
4426 enabled
= ffs(enabled
) - 1;
4429 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4430 SNB_READ_WM1_LATENCY() * 500,
4431 &sandybridge_display_srwm_info
,
4432 &sandybridge_cursor_srwm_info
,
4433 &fbc_wm
, &plane_wm
, &cursor_wm
))
4436 I915_WRITE(WM1_LP_ILK
,
4438 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4439 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4440 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4444 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4445 SNB_READ_WM2_LATENCY() * 500,
4446 &sandybridge_display_srwm_info
,
4447 &sandybridge_cursor_srwm_info
,
4448 &fbc_wm
, &plane_wm
, &cursor_wm
))
4451 I915_WRITE(WM2_LP_ILK
,
4453 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4454 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4455 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4459 if (!ironlake_compute_srwm(dev
, 3, enabled
,
4460 SNB_READ_WM3_LATENCY() * 500,
4461 &sandybridge_display_srwm_info
,
4462 &sandybridge_cursor_srwm_info
,
4463 &fbc_wm
, &plane_wm
, &cursor_wm
))
4466 I915_WRITE(WM3_LP_ILK
,
4468 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4469 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4470 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4475 * intel_update_watermarks - update FIFO watermark values based on current modes
4477 * Calculate watermark values for the various WM regs based on current mode
4478 * and plane configuration.
4480 * There are several cases to deal with here:
4481 * - normal (i.e. non-self-refresh)
4482 * - self-refresh (SR) mode
4483 * - lines are large relative to FIFO size (buffer can hold up to 2)
4484 * - lines are small relative to FIFO size (buffer can hold more than 2
4485 * lines), so need to account for TLB latency
4487 * The normal calculation is:
4488 * watermark = dotclock * bytes per pixel * latency
4489 * where latency is platform & configuration dependent (we assume pessimal
4492 * The SR calculation is:
4493 * watermark = (trunc(latency/line time)+1) * surface width *
4496 * line time = htotal / dotclock
4497 * surface width = hdisplay for normal plane and 64 for cursor
4498 * and latency is assumed to be high, as above.
4500 * The final value programmed to the register should always be rounded up,
4501 * and include an extra 2 entries to account for clock crossings.
4503 * We don't use the sprite, so we can ignore that. And on Crestline we have
4504 * to set the non-SR watermarks to 8.
4506 static void intel_update_watermarks(struct drm_device
*dev
)
4508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4510 if (dev_priv
->display
.update_wm
)
4511 dev_priv
->display
.update_wm(dev
);
4514 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4516 return dev_priv
->lvds_use_ssc
&& i915_panel_use_ssc
;
4519 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
4520 struct drm_display_mode
*mode
,
4521 struct drm_display_mode
*adjusted_mode
,
4523 struct drm_framebuffer
*old_fb
)
4525 struct drm_device
*dev
= crtc
->dev
;
4526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4527 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4528 int pipe
= intel_crtc
->pipe
;
4529 int plane
= intel_crtc
->plane
;
4530 u32 fp_reg
, dpll_reg
;
4531 int refclk
, num_connectors
= 0;
4532 intel_clock_t clock
, reduced_clock
;
4533 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4534 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
4535 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4536 struct intel_encoder
*has_edp_encoder
= NULL
;
4537 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4538 struct intel_encoder
*encoder
;
4539 const intel_limit_t
*limit
;
4541 struct fdi_m_n m_n
= {0};
4546 drm_vblank_pre_modeset(dev
, pipe
);
4548 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4549 if (encoder
->base
.crtc
!= crtc
)
4552 switch (encoder
->type
) {
4553 case INTEL_OUTPUT_LVDS
:
4556 case INTEL_OUTPUT_SDVO
:
4557 case INTEL_OUTPUT_HDMI
:
4559 if (encoder
->needs_tv_clock
)
4562 case INTEL_OUTPUT_DVO
:
4565 case INTEL_OUTPUT_TVOUT
:
4568 case INTEL_OUTPUT_ANALOG
:
4571 case INTEL_OUTPUT_DISPLAYPORT
:
4574 case INTEL_OUTPUT_EDP
:
4575 has_edp_encoder
= encoder
;
4582 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4583 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4584 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4586 } else if (!IS_GEN2(dev
)) {
4588 if (HAS_PCH_SPLIT(dev
) &&
4589 (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)))
4590 refclk
= 120000; /* 120Mhz refclk */
4596 * Returns a set of divisors for the desired target clock with the given
4597 * refclk, or FALSE. The returned values represent the clock equation:
4598 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4600 limit
= intel_limit(crtc
, refclk
);
4601 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
4603 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4604 drm_vblank_post_modeset(dev
, pipe
);
4608 /* Ensure that the cursor is valid for the new mode before changing... */
4609 intel_crtc_update_cursor(crtc
, true);
4611 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4612 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4613 dev_priv
->lvds_downclock
,
4616 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
4618 * If the different P is found, it means that we can't
4619 * switch the display clock by using the FP0/FP1.
4620 * In such case we will disable the LVDS downclock
4623 DRM_DEBUG_KMS("Different P is found for "
4624 "LVDS clock/downclock\n");
4625 has_reduced_clock
= 0;
4628 /* SDVO TV has fixed PLL values depend on its clock range,
4629 this mirrors vbios setting. */
4630 if (is_sdvo
&& is_tv
) {
4631 if (adjusted_mode
->clock
>= 100000
4632 && adjusted_mode
->clock
< 140500) {
4638 } else if (adjusted_mode
->clock
>= 140500
4639 && adjusted_mode
->clock
<= 200000) {
4649 if (HAS_PCH_SPLIT(dev
)) {
4650 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4651 int lane
= 0, link_bw
, bpp
;
4652 /* CPU eDP doesn't require FDI link, so just set DP M/N
4653 according to current link config */
4654 if (has_edp_encoder
&& !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4655 target_clock
= mode
->clock
;
4656 intel_edp_link_config(has_edp_encoder
,
4659 /* [e]DP over FDI requires target mode clock
4660 instead of link clock */
4661 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
4662 target_clock
= mode
->clock
;
4664 target_clock
= adjusted_mode
->clock
;
4666 /* FDI is a binary signal running at ~2.7GHz, encoding
4667 * each output octet as 10 bits. The actual frequency
4668 * is stored as a divider into a 100MHz clock, and the
4669 * mode pixel clock is stored in units of 1KHz.
4670 * Hence the bw of each lane in terms of the mode signal
4673 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4676 /* determine panel color depth */
4677 temp
= I915_READ(PIPECONF(pipe
));
4678 temp
&= ~PIPE_BPC_MASK
;
4680 /* the BPC will be 6 if it is 18-bit LVDS panel */
4681 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
4685 } else if (has_edp_encoder
) {
4686 switch (dev_priv
->edp
.bpp
/3) {
4702 I915_WRITE(PIPECONF(pipe
), temp
);
4704 switch (temp
& PIPE_BPC_MASK
) {
4718 DRM_ERROR("unknown pipe bpc value\n");
4724 * Account for spread spectrum to avoid
4725 * oversubscribing the link. Max center spread
4726 * is 2.5%; use 5% for safety's sake.
4728 u32 bps
= target_clock
* bpp
* 21 / 20;
4729 lane
= bps
/ (link_bw
* 8) + 1;
4732 intel_crtc
->fdi_lanes
= lane
;
4734 if (pixel_multiplier
> 1)
4735 link_bw
*= pixel_multiplier
;
4736 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
4739 /* Ironlake: try to setup display ref clock before DPLL
4740 * enabling. This is only under driver's control after
4741 * PCH B stepping, previous chipset stepping should be
4742 * ignoring this setting.
4744 if (HAS_PCH_SPLIT(dev
)) {
4745 temp
= I915_READ(PCH_DREF_CONTROL
);
4746 /* Always enable nonspread source */
4747 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4748 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4749 temp
&= ~DREF_SSC_SOURCE_MASK
;
4750 temp
|= DREF_SSC_SOURCE_ENABLE
;
4751 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4753 POSTING_READ(PCH_DREF_CONTROL
);
4756 if (has_edp_encoder
) {
4757 if (intel_panel_use_ssc(dev_priv
)) {
4758 temp
|= DREF_SSC1_ENABLE
;
4759 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4761 POSTING_READ(PCH_DREF_CONTROL
);
4764 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4766 /* Enable CPU source on CPU attached eDP */
4767 if (!intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4768 if (intel_panel_use_ssc(dev_priv
))
4769 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4771 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4773 /* Enable SSC on PCH eDP if needed */
4774 if (intel_panel_use_ssc(dev_priv
)) {
4775 DRM_ERROR("enabling SSC on PCH\n");
4776 temp
|= DREF_SUPERSPREAD_SOURCE_ENABLE
;
4779 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4780 POSTING_READ(PCH_DREF_CONTROL
);
4785 if (IS_PINEVIEW(dev
)) {
4786 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
4787 if (has_reduced_clock
)
4788 fp2
= (1 << reduced_clock
.n
) << 16 |
4789 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
4791 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4792 if (has_reduced_clock
)
4793 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4797 /* Enable autotuning of the PLL clock (if permissible) */
4798 if (HAS_PCH_SPLIT(dev
)) {
4802 if ((intel_panel_use_ssc(dev_priv
) &&
4803 dev_priv
->lvds_ssc_freq
== 100) ||
4804 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4806 } else if (is_sdvo
&& is_tv
)
4809 if (clock
.m1
< factor
* clock
.n
)
4814 if (!HAS_PCH_SPLIT(dev
))
4815 dpll
= DPLL_VGA_MODE_DIS
;
4817 if (!IS_GEN2(dev
)) {
4819 dpll
|= DPLLB_MODE_LVDS
;
4821 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4823 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4824 if (pixel_multiplier
> 1) {
4825 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4826 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4827 else if (HAS_PCH_SPLIT(dev
))
4828 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4830 dpll
|= DPLL_DVO_HIGH_SPEED
;
4832 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
4833 dpll
|= DPLL_DVO_HIGH_SPEED
;
4835 /* compute bitmask from p1 value */
4836 if (IS_PINEVIEW(dev
))
4837 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4839 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4841 if (HAS_PCH_SPLIT(dev
))
4842 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4843 if (IS_G4X(dev
) && has_reduced_clock
)
4844 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4848 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4851 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4854 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4857 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4860 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
))
4861 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4864 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4867 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4869 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4871 dpll
|= PLL_P2_DIVIDE_BY_4
;
4875 if (is_sdvo
&& is_tv
)
4876 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4878 /* XXX: just matching BIOS for now */
4879 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4881 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4882 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4884 dpll
|= PLL_REF_INPUT_DREFCLK
;
4886 /* setup pipeconf */
4887 pipeconf
= I915_READ(PIPECONF(pipe
));
4889 /* Set up the display plane register */
4890 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4892 /* Ironlake's plane is forced to pipe, bit 24 is to
4893 enable color space conversion */
4894 if (!HAS_PCH_SPLIT(dev
)) {
4896 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4898 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4901 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4902 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4905 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4909 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4910 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4912 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4915 if (!HAS_PCH_SPLIT(dev
))
4916 dpll
|= DPLL_VCO_ENABLE
;
4918 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4919 drm_mode_debug_printmodeline(mode
);
4921 /* assign to Ironlake registers */
4922 if (HAS_PCH_SPLIT(dev
)) {
4923 fp_reg
= PCH_FP0(pipe
);
4924 dpll_reg
= PCH_DPLL(pipe
);
4927 dpll_reg
= DPLL(pipe
);
4930 /* PCH eDP needs FDI, but CPU eDP does not */
4931 if (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4932 I915_WRITE(fp_reg
, fp
);
4933 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
4935 POSTING_READ(dpll_reg
);
4939 /* enable transcoder DPLL */
4940 if (HAS_PCH_CPT(dev
)) {
4941 temp
= I915_READ(PCH_DPLL_SEL
);
4944 temp
|= TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
;
4947 temp
|= TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
;
4950 /* FIXME: manage transcoder PLLs? */
4951 temp
|= TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
;
4956 I915_WRITE(PCH_DPLL_SEL
, temp
);
4958 POSTING_READ(PCH_DPLL_SEL
);
4962 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4963 * This is an exception to the general rule that mode_set doesn't turn
4968 if (HAS_PCH_SPLIT(dev
))
4971 temp
= I915_READ(reg
);
4972 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4974 if (HAS_PCH_CPT(dev
))
4975 temp
|= PORT_TRANS_B_SEL_CPT
;
4977 temp
|= LVDS_PIPEB_SELECT
;
4979 if (HAS_PCH_CPT(dev
))
4980 temp
&= ~PORT_TRANS_SEL_MASK
;
4982 temp
&= ~LVDS_PIPEB_SELECT
;
4984 /* set the corresponsding LVDS_BORDER bit */
4985 temp
|= dev_priv
->lvds_border_bits
;
4986 /* Set the B0-B3 data pairs corresponding to whether we're going to
4987 * set the DPLLs for dual-channel mode or not.
4990 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4992 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4994 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4995 * appropriately here, but we need to look more thoroughly into how
4996 * panels behave in the two modes.
4998 /* set the dithering flag on non-PCH LVDS as needed */
4999 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
5000 if (dev_priv
->lvds_dither
)
5001 temp
|= LVDS_ENABLE_DITHER
;
5003 temp
&= ~LVDS_ENABLE_DITHER
;
5005 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5006 lvds_sync
|= LVDS_HSYNC_POLARITY
;
5007 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5008 lvds_sync
|= LVDS_VSYNC_POLARITY
;
5009 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
5011 char flags
[2] = "-+";
5012 DRM_INFO("Changing LVDS panel from "
5013 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5014 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
5015 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
5016 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
5017 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
5018 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5021 I915_WRITE(reg
, temp
);
5024 /* set the dithering flag and clear for anything other than a panel. */
5025 if (HAS_PCH_SPLIT(dev
)) {
5026 pipeconf
&= ~PIPECONF_DITHER_EN
;
5027 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
5028 if (dev_priv
->lvds_dither
&& (is_lvds
|| has_edp_encoder
)) {
5029 pipeconf
|= PIPECONF_DITHER_EN
;
5030 pipeconf
|= PIPECONF_DITHER_TYPE_ST1
;
5034 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5035 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5036 } else if (HAS_PCH_SPLIT(dev
)) {
5037 /* For non-DP output, clear any trans DP clock recovery setting.*/
5038 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5039 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5040 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5041 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5044 if (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5045 I915_WRITE(dpll_reg
, dpll
);
5047 /* Wait for the clocks to stabilize. */
5048 POSTING_READ(dpll_reg
);
5051 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
5054 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5056 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5060 I915_WRITE(DPLL_MD(pipe
), temp
);
5062 /* The pixel multiplier can only be updated once the
5063 * DPLL is enabled and the clocks are stable.
5065 * So write it again.
5067 I915_WRITE(dpll_reg
, dpll
);
5071 intel_crtc
->lowfreq_avail
= false;
5072 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5073 I915_WRITE(fp_reg
+ 4, fp2
);
5074 intel_crtc
->lowfreq_avail
= true;
5075 if (HAS_PIPE_CXSR(dev
)) {
5076 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5077 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5080 I915_WRITE(fp_reg
+ 4, fp
);
5081 if (HAS_PIPE_CXSR(dev
)) {
5082 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5083 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
5087 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5088 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5089 /* the chip adds 2 halflines automatically */
5090 adjusted_mode
->crtc_vdisplay
-= 1;
5091 adjusted_mode
->crtc_vtotal
-= 1;
5092 adjusted_mode
->crtc_vblank_start
-= 1;
5093 adjusted_mode
->crtc_vblank_end
-= 1;
5094 adjusted_mode
->crtc_vsync_end
-= 1;
5095 adjusted_mode
->crtc_vsync_start
-= 1;
5097 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
5099 I915_WRITE(HTOTAL(pipe
),
5100 (adjusted_mode
->crtc_hdisplay
- 1) |
5101 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5102 I915_WRITE(HBLANK(pipe
),
5103 (adjusted_mode
->crtc_hblank_start
- 1) |
5104 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5105 I915_WRITE(HSYNC(pipe
),
5106 (adjusted_mode
->crtc_hsync_start
- 1) |
5107 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5109 I915_WRITE(VTOTAL(pipe
),
5110 (adjusted_mode
->crtc_vdisplay
- 1) |
5111 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
5112 I915_WRITE(VBLANK(pipe
),
5113 (adjusted_mode
->crtc_vblank_start
- 1) |
5114 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
5115 I915_WRITE(VSYNC(pipe
),
5116 (adjusted_mode
->crtc_vsync_start
- 1) |
5117 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5119 /* pipesrc and dspsize control the size that is scaled from,
5120 * which should always be the user's requested size.
5122 if (!HAS_PCH_SPLIT(dev
)) {
5123 I915_WRITE(DSPSIZE(plane
),
5124 ((mode
->vdisplay
- 1) << 16) |
5125 (mode
->hdisplay
- 1));
5126 I915_WRITE(DSPPOS(plane
), 0);
5128 I915_WRITE(PIPESRC(pipe
),
5129 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
5131 if (HAS_PCH_SPLIT(dev
)) {
5132 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5133 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
5134 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
5135 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
5137 if (has_edp_encoder
&& !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5138 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5142 I915_WRITE(PIPECONF(pipe
), pipeconf
);
5143 POSTING_READ(PIPECONF(pipe
));
5144 if (!HAS_PCH_SPLIT(dev
))
5145 intel_enable_pipe(dev_priv
, pipe
, false);
5147 intel_wait_for_vblank(dev
, pipe
);
5150 /* enable address swizzle for tiling buffer */
5151 temp
= I915_READ(DISP_ARB_CTL
);
5152 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
5155 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5156 POSTING_READ(DSPCNTR(plane
));
5157 if (!HAS_PCH_SPLIT(dev
))
5158 intel_enable_plane(dev_priv
, plane
, pipe
);
5160 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
5162 intel_update_watermarks(dev
);
5164 drm_vblank_post_modeset(dev
, pipe
);
5169 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5170 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5172 struct drm_device
*dev
= crtc
->dev
;
5173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5174 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5175 int palreg
= PALETTE(intel_crtc
->pipe
);
5178 /* The clocks have to be on to load the palette. */
5182 /* use legacy palette for Ironlake */
5183 if (HAS_PCH_SPLIT(dev
))
5184 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5186 for (i
= 0; i
< 256; i
++) {
5187 I915_WRITE(palreg
+ 4 * i
,
5188 (intel_crtc
->lut_r
[i
] << 16) |
5189 (intel_crtc
->lut_g
[i
] << 8) |
5190 intel_crtc
->lut_b
[i
]);
5194 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5196 struct drm_device
*dev
= crtc
->dev
;
5197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5199 bool visible
= base
!= 0;
5202 if (intel_crtc
->cursor_visible
== visible
)
5205 cntl
= I915_READ(_CURACNTR
);
5207 /* On these chipsets we can only modify the base whilst
5208 * the cursor is disabled.
5210 I915_WRITE(_CURABASE
, base
);
5212 cntl
&= ~(CURSOR_FORMAT_MASK
);
5213 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5214 cntl
|= CURSOR_ENABLE
|
5215 CURSOR_GAMMA_ENABLE
|
5218 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5219 I915_WRITE(_CURACNTR
, cntl
);
5221 intel_crtc
->cursor_visible
= visible
;
5224 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5226 struct drm_device
*dev
= crtc
->dev
;
5227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5229 int pipe
= intel_crtc
->pipe
;
5230 bool visible
= base
!= 0;
5232 if (intel_crtc
->cursor_visible
!= visible
) {
5233 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5235 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5236 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5237 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5239 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5240 cntl
|= CURSOR_MODE_DISABLE
;
5242 I915_WRITE(CURCNTR(pipe
), cntl
);
5244 intel_crtc
->cursor_visible
= visible
;
5246 /* and commit changes on next vblank */
5247 I915_WRITE(CURBASE(pipe
), base
);
5250 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5251 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5254 struct drm_device
*dev
= crtc
->dev
;
5255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5257 int pipe
= intel_crtc
->pipe
;
5258 int x
= intel_crtc
->cursor_x
;
5259 int y
= intel_crtc
->cursor_y
;
5265 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5266 base
= intel_crtc
->cursor_addr
;
5267 if (x
> (int) crtc
->fb
->width
)
5270 if (y
> (int) crtc
->fb
->height
)
5276 if (x
+ intel_crtc
->cursor_width
< 0)
5279 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5282 pos
|= x
<< CURSOR_X_SHIFT
;
5285 if (y
+ intel_crtc
->cursor_height
< 0)
5288 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5291 pos
|= y
<< CURSOR_Y_SHIFT
;
5293 visible
= base
!= 0;
5294 if (!visible
&& !intel_crtc
->cursor_visible
)
5297 I915_WRITE(CURPOS(pipe
), pos
);
5298 if (IS_845G(dev
) || IS_I865G(dev
))
5299 i845_update_cursor(crtc
, base
);
5301 i9xx_update_cursor(crtc
, base
);
5304 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
5307 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5308 struct drm_file
*file
,
5310 uint32_t width
, uint32_t height
)
5312 struct drm_device
*dev
= crtc
->dev
;
5313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5314 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5315 struct drm_i915_gem_object
*obj
;
5319 DRM_DEBUG_KMS("\n");
5321 /* if we want to turn off the cursor ignore width and height */
5323 DRM_DEBUG_KMS("cursor off\n");
5326 mutex_lock(&dev
->struct_mutex
);
5330 /* Currently we only support 64x64 cursors */
5331 if (width
!= 64 || height
!= 64) {
5332 DRM_ERROR("we currently only support 64x64 cursors\n");
5336 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5337 if (&obj
->base
== NULL
)
5340 if (obj
->base
.size
< width
* height
* 4) {
5341 DRM_ERROR("buffer is to small\n");
5346 /* we only need to pin inside GTT if cursor is non-phy */
5347 mutex_lock(&dev
->struct_mutex
);
5348 if (!dev_priv
->info
->cursor_needs_physical
) {
5349 if (obj
->tiling_mode
) {
5350 DRM_ERROR("cursor cannot be tiled\n");
5355 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
5357 DRM_ERROR("failed to pin cursor bo\n");
5361 ret
= i915_gem_object_set_to_gtt_domain(obj
, 0);
5363 DRM_ERROR("failed to move cursor bo into the GTT\n");
5367 ret
= i915_gem_object_put_fence(obj
);
5369 DRM_ERROR("failed to move cursor bo into the GTT\n");
5373 addr
= obj
->gtt_offset
;
5375 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5376 ret
= i915_gem_attach_phys_object(dev
, obj
,
5377 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5380 DRM_ERROR("failed to attach phys object\n");
5383 addr
= obj
->phys_obj
->handle
->busaddr
;
5387 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5390 if (intel_crtc
->cursor_bo
) {
5391 if (dev_priv
->info
->cursor_needs_physical
) {
5392 if (intel_crtc
->cursor_bo
!= obj
)
5393 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5395 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5396 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5399 mutex_unlock(&dev
->struct_mutex
);
5401 intel_crtc
->cursor_addr
= addr
;
5402 intel_crtc
->cursor_bo
= obj
;
5403 intel_crtc
->cursor_width
= width
;
5404 intel_crtc
->cursor_height
= height
;
5406 intel_crtc_update_cursor(crtc
, true);
5410 i915_gem_object_unpin(obj
);
5412 mutex_unlock(&dev
->struct_mutex
);
5414 drm_gem_object_unreference_unlocked(&obj
->base
);
5418 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5422 intel_crtc
->cursor_x
= x
;
5423 intel_crtc
->cursor_y
= y
;
5425 intel_crtc_update_cursor(crtc
, true);
5430 /** Sets the color ramps on behalf of RandR */
5431 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5432 u16 blue
, int regno
)
5434 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5436 intel_crtc
->lut_r
[regno
] = red
>> 8;
5437 intel_crtc
->lut_g
[regno
] = green
>> 8;
5438 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5441 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5442 u16
*blue
, int regno
)
5444 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5446 *red
= intel_crtc
->lut_r
[regno
] << 8;
5447 *green
= intel_crtc
->lut_g
[regno
] << 8;
5448 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5451 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5452 u16
*blue
, uint32_t start
, uint32_t size
)
5454 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5455 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5457 for (i
= start
; i
< end
; i
++) {
5458 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5459 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5460 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5463 intel_crtc_load_lut(crtc
);
5467 * Get a pipe with a simple mode set on it for doing load-based monitor
5470 * It will be up to the load-detect code to adjust the pipe as appropriate for
5471 * its requirements. The pipe will be connected to no other encoders.
5473 * Currently this code will only succeed if there is a pipe with no encoders
5474 * configured for it. In the future, it could choose to temporarily disable
5475 * some outputs to free up a pipe for its use.
5477 * \return crtc, or NULL if no pipes are available.
5480 /* VESA 640x480x72Hz mode to set on the pipe */
5481 static struct drm_display_mode load_detect_mode
= {
5482 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5483 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5486 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5487 struct drm_connector
*connector
,
5488 struct drm_display_mode
*mode
,
5491 struct intel_crtc
*intel_crtc
;
5492 struct drm_crtc
*possible_crtc
;
5493 struct drm_crtc
*supported_crtc
=NULL
;
5494 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5495 struct drm_crtc
*crtc
= NULL
;
5496 struct drm_device
*dev
= encoder
->dev
;
5497 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5498 struct drm_crtc_helper_funcs
*crtc_funcs
;
5502 * Algorithm gets a little messy:
5503 * - if the connector already has an assigned crtc, use it (but make
5504 * sure it's on first)
5505 * - try to find the first unused crtc that can drive this connector,
5506 * and use that if we find one
5507 * - if there are no unused crtcs available, try to use the first
5508 * one we found that supports the connector
5511 /* See if we already have a CRTC for this connector */
5512 if (encoder
->crtc
) {
5513 crtc
= encoder
->crtc
;
5514 /* Make sure the crtc and connector are running */
5515 intel_crtc
= to_intel_crtc(crtc
);
5516 *dpms_mode
= intel_crtc
->dpms_mode
;
5517 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5518 crtc_funcs
= crtc
->helper_private
;
5519 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5520 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
5525 /* Find an unused one (if possible) */
5526 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5528 if (!(encoder
->possible_crtcs
& (1 << i
)))
5530 if (!possible_crtc
->enabled
) {
5531 crtc
= possible_crtc
;
5534 if (!supported_crtc
)
5535 supported_crtc
= possible_crtc
;
5539 * If we didn't find an unused CRTC, don't use any.
5545 encoder
->crtc
= crtc
;
5546 connector
->encoder
= encoder
;
5547 intel_encoder
->load_detect_temp
= true;
5549 intel_crtc
= to_intel_crtc(crtc
);
5550 *dpms_mode
= intel_crtc
->dpms_mode
;
5552 if (!crtc
->enabled
) {
5554 mode
= &load_detect_mode
;
5555 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
5557 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5558 crtc_funcs
= crtc
->helper_private
;
5559 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5562 /* Add this connector to the crtc */
5563 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
5564 encoder_funcs
->commit(encoder
);
5566 /* let the connector get through one full cycle before testing */
5567 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5572 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5573 struct drm_connector
*connector
, int dpms_mode
)
5575 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5576 struct drm_device
*dev
= encoder
->dev
;
5577 struct drm_crtc
*crtc
= encoder
->crtc
;
5578 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5579 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
5581 if (intel_encoder
->load_detect_temp
) {
5582 encoder
->crtc
= NULL
;
5583 connector
->encoder
= NULL
;
5584 intel_encoder
->load_detect_temp
= false;
5585 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
5586 drm_helper_disable_unused_functions(dev
);
5589 /* Switch crtc and encoder back off if necessary */
5590 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
5591 if (encoder
->crtc
== crtc
)
5592 encoder_funcs
->dpms(encoder
, dpms_mode
);
5593 crtc_funcs
->dpms(crtc
, dpms_mode
);
5597 /* Returns the clock of the currently programmed mode of the given pipe. */
5598 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5602 int pipe
= intel_crtc
->pipe
;
5603 u32 dpll
= I915_READ(DPLL(pipe
));
5605 intel_clock_t clock
;
5607 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5608 fp
= I915_READ(FP0(pipe
));
5610 fp
= I915_READ(FP1(pipe
));
5612 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5613 if (IS_PINEVIEW(dev
)) {
5614 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5615 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5617 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5618 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5621 if (!IS_GEN2(dev
)) {
5622 if (IS_PINEVIEW(dev
))
5623 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5624 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5626 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5627 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5629 switch (dpll
& DPLL_MODE_MASK
) {
5630 case DPLLB_MODE_DAC_SERIAL
:
5631 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5634 case DPLLB_MODE_LVDS
:
5635 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5639 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5640 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5644 /* XXX: Handle the 100Mhz refclk */
5645 intel_clock(dev
, 96000, &clock
);
5647 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5650 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5651 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5654 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5655 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5656 /* XXX: might not be 66MHz */
5657 intel_clock(dev
, 66000, &clock
);
5659 intel_clock(dev
, 48000, &clock
);
5661 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5664 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5665 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5667 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5672 intel_clock(dev
, 48000, &clock
);
5676 /* XXX: It would be nice to validate the clocks, but we can't reuse
5677 * i830PllIsValid() because it relies on the xf86_config connector
5678 * configuration being accurate, which it isn't necessarily.
5684 /** Returns the currently programmed mode of the given pipe. */
5685 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5686 struct drm_crtc
*crtc
)
5688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5689 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5690 int pipe
= intel_crtc
->pipe
;
5691 struct drm_display_mode
*mode
;
5692 int htot
= I915_READ(HTOTAL(pipe
));
5693 int hsync
= I915_READ(HSYNC(pipe
));
5694 int vtot
= I915_READ(VTOTAL(pipe
));
5695 int vsync
= I915_READ(VSYNC(pipe
));
5697 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5701 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5702 mode
->hdisplay
= (htot
& 0xffff) + 1;
5703 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5704 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5705 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5706 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5707 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5708 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5709 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
5711 drm_mode_set_name(mode
);
5712 drm_mode_set_crtcinfo(mode
, 0);
5717 #define GPU_IDLE_TIMEOUT 500 /* ms */
5719 /* When this timer fires, we've been idle for awhile */
5720 static void intel_gpu_idle_timer(unsigned long arg
)
5722 struct drm_device
*dev
= (struct drm_device
*)arg
;
5723 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5725 if (!list_empty(&dev_priv
->mm
.active_list
)) {
5726 /* Still processing requests, so just re-arm the timer. */
5727 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5728 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5732 dev_priv
->busy
= false;
5733 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5736 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5738 static void intel_crtc_idle_timer(unsigned long arg
)
5740 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
5741 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5742 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
5743 struct intel_framebuffer
*intel_fb
;
5745 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5746 if (intel_fb
&& intel_fb
->obj
->active
) {
5747 /* The framebuffer is still being accessed by the GPU. */
5748 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5749 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5753 intel_crtc
->busy
= false;
5754 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5757 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
5759 struct drm_device
*dev
= crtc
->dev
;
5760 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5761 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5762 int pipe
= intel_crtc
->pipe
;
5763 int dpll_reg
= DPLL(pipe
);
5766 if (HAS_PCH_SPLIT(dev
))
5769 if (!dev_priv
->lvds_downclock_avail
)
5772 dpll
= I915_READ(dpll_reg
);
5773 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
5774 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5776 /* Unlock panel regs */
5777 I915_WRITE(PP_CONTROL
,
5778 I915_READ(PP_CONTROL
) | PANEL_UNLOCK_REGS
);
5780 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
5781 I915_WRITE(dpll_reg
, dpll
);
5782 intel_wait_for_vblank(dev
, pipe
);
5784 dpll
= I915_READ(dpll_reg
);
5785 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
5786 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5788 /* ...and lock them again */
5789 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
5792 /* Schedule downclock */
5793 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5794 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5797 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
5799 struct drm_device
*dev
= crtc
->dev
;
5800 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5801 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5802 int pipe
= intel_crtc
->pipe
;
5803 int dpll_reg
= DPLL(pipe
);
5804 int dpll
= I915_READ(dpll_reg
);
5806 if (HAS_PCH_SPLIT(dev
))
5809 if (!dev_priv
->lvds_downclock_avail
)
5813 * Since this is called by a timer, we should never get here in
5816 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
5817 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5819 /* Unlock panel regs */
5820 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
5823 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
5824 I915_WRITE(dpll_reg
, dpll
);
5825 intel_wait_for_vblank(dev
, pipe
);
5826 dpll
= I915_READ(dpll_reg
);
5827 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
5828 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5830 /* ...and lock them again */
5831 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
5837 * intel_idle_update - adjust clocks for idleness
5838 * @work: work struct
5840 * Either the GPU or display (or both) went idle. Check the busy status
5841 * here and adjust the CRTC and GPU clocks as necessary.
5843 static void intel_idle_update(struct work_struct
*work
)
5845 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
5847 struct drm_device
*dev
= dev_priv
->dev
;
5848 struct drm_crtc
*crtc
;
5849 struct intel_crtc
*intel_crtc
;
5851 if (!i915_powersave
)
5854 mutex_lock(&dev
->struct_mutex
);
5856 i915_update_gfx_val(dev_priv
);
5858 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5859 /* Skip inactive CRTCs */
5863 intel_crtc
= to_intel_crtc(crtc
);
5864 if (!intel_crtc
->busy
)
5865 intel_decrease_pllclock(crtc
);
5869 mutex_unlock(&dev
->struct_mutex
);
5873 * intel_mark_busy - mark the GPU and possibly the display busy
5875 * @obj: object we're operating on
5877 * Callers can use this function to indicate that the GPU is busy processing
5878 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5879 * buffer), we'll also mark the display as busy, so we know to increase its
5882 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
5884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5885 struct drm_crtc
*crtc
= NULL
;
5886 struct intel_framebuffer
*intel_fb
;
5887 struct intel_crtc
*intel_crtc
;
5889 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
5892 if (!dev_priv
->busy
)
5893 dev_priv
->busy
= true;
5895 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5896 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5898 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5902 intel_crtc
= to_intel_crtc(crtc
);
5903 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5904 if (intel_fb
->obj
== obj
) {
5905 if (!intel_crtc
->busy
) {
5906 /* Non-busy -> busy, upclock */
5907 intel_increase_pllclock(crtc
);
5908 intel_crtc
->busy
= true;
5910 /* Busy -> busy, put off timer */
5911 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5912 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5918 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
5920 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5921 struct drm_device
*dev
= crtc
->dev
;
5922 struct intel_unpin_work
*work
;
5923 unsigned long flags
;
5925 spin_lock_irqsave(&dev
->event_lock
, flags
);
5926 work
= intel_crtc
->unpin_work
;
5927 intel_crtc
->unpin_work
= NULL
;
5928 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5931 cancel_work_sync(&work
->work
);
5935 drm_crtc_cleanup(crtc
);
5940 static void intel_unpin_work_fn(struct work_struct
*__work
)
5942 struct intel_unpin_work
*work
=
5943 container_of(__work
, struct intel_unpin_work
, work
);
5945 mutex_lock(&work
->dev
->struct_mutex
);
5946 i915_gem_object_unpin(work
->old_fb_obj
);
5947 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
5948 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
5950 mutex_unlock(&work
->dev
->struct_mutex
);
5954 static void do_intel_finish_page_flip(struct drm_device
*dev
,
5955 struct drm_crtc
*crtc
)
5957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5958 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5959 struct intel_unpin_work
*work
;
5960 struct drm_i915_gem_object
*obj
;
5961 struct drm_pending_vblank_event
*e
;
5962 struct timeval tnow
, tvbl
;
5963 unsigned long flags
;
5965 /* Ignore early vblank irqs */
5966 if (intel_crtc
== NULL
)
5969 do_gettimeofday(&tnow
);
5971 spin_lock_irqsave(&dev
->event_lock
, flags
);
5972 work
= intel_crtc
->unpin_work
;
5973 if (work
== NULL
|| !work
->pending
) {
5974 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5978 intel_crtc
->unpin_work
= NULL
;
5982 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
5984 /* Called before vblank count and timestamps have
5985 * been updated for the vblank interval of flip
5986 * completion? Need to increment vblank count and
5987 * add one videorefresh duration to returned timestamp
5988 * to account for this. We assume this happened if we
5989 * get called over 0.9 frame durations after the last
5990 * timestamped vblank.
5992 * This calculation can not be used with vrefresh rates
5993 * below 5Hz (10Hz to be on the safe side) without
5994 * promoting to 64 integers.
5996 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
5997 9 * crtc
->framedur_ns
) {
5998 e
->event
.sequence
++;
5999 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
6003 e
->event
.tv_sec
= tvbl
.tv_sec
;
6004 e
->event
.tv_usec
= tvbl
.tv_usec
;
6006 list_add_tail(&e
->base
.link
,
6007 &e
->base
.file_priv
->event_list
);
6008 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6011 drm_vblank_put(dev
, intel_crtc
->pipe
);
6013 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6015 obj
= work
->old_fb_obj
;
6017 atomic_clear_mask(1 << intel_crtc
->plane
,
6018 &obj
->pending_flip
.counter
);
6019 if (atomic_read(&obj
->pending_flip
) == 0)
6020 wake_up(&dev_priv
->pending_flip_queue
);
6022 schedule_work(&work
->work
);
6024 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6027 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6029 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6030 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6032 do_intel_finish_page_flip(dev
, crtc
);
6035 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6037 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6038 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6040 do_intel_finish_page_flip(dev
, crtc
);
6043 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6045 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6046 struct intel_crtc
*intel_crtc
=
6047 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6048 unsigned long flags
;
6050 spin_lock_irqsave(&dev
->event_lock
, flags
);
6051 if (intel_crtc
->unpin_work
) {
6052 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6053 DRM_ERROR("Prepared flip multiple times\n");
6055 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6057 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6060 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6061 struct drm_framebuffer
*fb
,
6062 struct drm_pending_vblank_event
*event
)
6064 struct drm_device
*dev
= crtc
->dev
;
6065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6066 struct intel_framebuffer
*intel_fb
;
6067 struct drm_i915_gem_object
*obj
;
6068 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6069 struct intel_unpin_work
*work
;
6070 unsigned long flags
, offset
;
6071 int pipe
= intel_crtc
->pipe
;
6075 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6079 work
->event
= event
;
6080 work
->dev
= crtc
->dev
;
6081 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6082 work
->old_fb_obj
= intel_fb
->obj
;
6083 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6085 /* We borrow the event spin lock for protecting unpin_work */
6086 spin_lock_irqsave(&dev
->event_lock
, flags
);
6087 if (intel_crtc
->unpin_work
) {
6088 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6091 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6094 intel_crtc
->unpin_work
= work
;
6095 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6097 intel_fb
= to_intel_framebuffer(fb
);
6098 obj
= intel_fb
->obj
;
6100 mutex_lock(&dev
->struct_mutex
);
6101 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
6105 /* Reference the objects for the scheduled work. */
6106 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6107 drm_gem_object_reference(&obj
->base
);
6111 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6115 if (IS_GEN3(dev
) || IS_GEN2(dev
)) {
6118 /* Can't queue multiple flips, so wait for the previous
6119 * one to finish before executing the next.
6121 ret
= BEGIN_LP_RING(2);
6125 if (intel_crtc
->plane
)
6126 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6128 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6129 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
6134 work
->pending_flip_obj
= obj
;
6136 work
->enable_stall_check
= true;
6138 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6139 offset
= crtc
->y
* fb
->pitch
+ crtc
->x
* fb
->bits_per_pixel
/8;
6141 ret
= BEGIN_LP_RING(4);
6145 /* Block clients from rendering to the new back buffer until
6146 * the flip occurs and the object is no longer visible.
6148 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6150 switch (INTEL_INFO(dev
)->gen
) {
6152 OUT_RING(MI_DISPLAY_FLIP
|
6153 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6154 OUT_RING(fb
->pitch
);
6155 OUT_RING(obj
->gtt_offset
+ offset
);
6160 OUT_RING(MI_DISPLAY_FLIP_I915
|
6161 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6162 OUT_RING(fb
->pitch
);
6163 OUT_RING(obj
->gtt_offset
+ offset
);
6169 /* i965+ uses the linear or tiled offsets from the
6170 * Display Registers (which do not change across a page-flip)
6171 * so we need only reprogram the base address.
6173 OUT_RING(MI_DISPLAY_FLIP
|
6174 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6175 OUT_RING(fb
->pitch
);
6176 OUT_RING(obj
->gtt_offset
| obj
->tiling_mode
);
6178 /* XXX Enabling the panel-fitter across page-flip is so far
6179 * untested on non-native modes, so ignore it for now.
6180 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6183 pipesrc
= I915_READ(PIPESRC(pipe
)) & 0x0fff0fff;
6184 OUT_RING(pf
| pipesrc
);
6188 OUT_RING(MI_DISPLAY_FLIP
|
6189 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6190 OUT_RING(fb
->pitch
| obj
->tiling_mode
);
6191 OUT_RING(obj
->gtt_offset
);
6193 pf
= I915_READ(PF_CTL(pipe
)) & PF_ENABLE
;
6194 pipesrc
= I915_READ(PIPESRC(pipe
)) & 0x0fff0fff;
6195 OUT_RING(pf
| pipesrc
);
6200 mutex_unlock(&dev
->struct_mutex
);
6202 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6207 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6208 drm_gem_object_unreference(&obj
->base
);
6210 mutex_unlock(&dev
->struct_mutex
);
6212 spin_lock_irqsave(&dev
->event_lock
, flags
);
6213 intel_crtc
->unpin_work
= NULL
;
6214 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6221 static void intel_sanitize_modesetting(struct drm_device
*dev
,
6222 int pipe
, int plane
)
6224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6227 if (HAS_PCH_SPLIT(dev
))
6230 /* Who knows what state these registers were left in by the BIOS or
6233 * If we leave the registers in a conflicting state (e.g. with the
6234 * display plane reading from the other pipe than the one we intend
6235 * to use) then when we attempt to teardown the active mode, we will
6236 * not disable the pipes and planes in the correct order -- leaving
6237 * a plane reading from a disabled pipe and possibly leading to
6238 * undefined behaviour.
6241 reg
= DSPCNTR(plane
);
6242 val
= I915_READ(reg
);
6244 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
6246 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
6249 /* This display plane is active and attached to the other CPU pipe. */
6252 /* Disable the plane and wait for it to stop reading from the pipe. */
6253 intel_disable_plane(dev_priv
, plane
, pipe
);
6254 intel_disable_pipe(dev_priv
, pipe
);
6257 static void intel_crtc_reset(struct drm_crtc
*crtc
)
6259 struct drm_device
*dev
= crtc
->dev
;
6260 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6262 /* Reset flags back to the 'unknown' status so that they
6263 * will be correctly set on the initial modeset.
6265 intel_crtc
->dpms_mode
= -1;
6267 /* We need to fix up any BIOS configuration that conflicts with
6270 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
6273 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6274 .dpms
= intel_crtc_dpms
,
6275 .mode_fixup
= intel_crtc_mode_fixup
,
6276 .mode_set
= intel_crtc_mode_set
,
6277 .mode_set_base
= intel_pipe_set_base
,
6278 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6279 .load_lut
= intel_crtc_load_lut
,
6280 .disable
= intel_crtc_disable
,
6283 static const struct drm_crtc_funcs intel_crtc_funcs
= {
6284 .reset
= intel_crtc_reset
,
6285 .cursor_set
= intel_crtc_cursor_set
,
6286 .cursor_move
= intel_crtc_cursor_move
,
6287 .gamma_set
= intel_crtc_gamma_set
,
6288 .set_config
= drm_crtc_helper_set_config
,
6289 .destroy
= intel_crtc_destroy
,
6290 .page_flip
= intel_crtc_page_flip
,
6293 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
6295 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6296 struct intel_crtc
*intel_crtc
;
6299 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
6300 if (intel_crtc
== NULL
)
6303 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
6305 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
6306 for (i
= 0; i
< 256; i
++) {
6307 intel_crtc
->lut_r
[i
] = i
;
6308 intel_crtc
->lut_g
[i
] = i
;
6309 intel_crtc
->lut_b
[i
] = i
;
6312 /* Swap pipes & planes for FBC on pre-965 */
6313 intel_crtc
->pipe
= pipe
;
6314 intel_crtc
->plane
= pipe
;
6315 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
6316 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6317 intel_crtc
->plane
= !pipe
;
6320 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
6321 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
6322 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
6323 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
6325 intel_crtc_reset(&intel_crtc
->base
);
6326 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
6328 if (HAS_PCH_SPLIT(dev
)) {
6329 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
6330 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
6332 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
6333 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
6336 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
6338 intel_crtc
->busy
= false;
6340 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
6341 (unsigned long)intel_crtc
);
6344 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
6345 struct drm_file
*file
)
6347 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6348 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
6349 struct drm_mode_object
*drmmode_obj
;
6350 struct intel_crtc
*crtc
;
6353 DRM_ERROR("called with no initialization\n");
6357 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
6358 DRM_MODE_OBJECT_CRTC
);
6361 DRM_ERROR("no such CRTC id\n");
6365 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
6366 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
6371 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
6373 struct intel_encoder
*encoder
;
6377 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6378 if (type_mask
& encoder
->clone_mask
)
6379 index_mask
|= (1 << entry
);
6386 static bool has_edp_a(struct drm_device
*dev
)
6388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6390 if (!IS_MOBILE(dev
))
6393 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
6397 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
6403 static void intel_setup_outputs(struct drm_device
*dev
)
6405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6406 struct intel_encoder
*encoder
;
6407 bool dpd_is_edp
= false;
6408 bool has_lvds
= false;
6410 if (IS_MOBILE(dev
) && !IS_I830(dev
))
6411 has_lvds
= intel_lvds_init(dev
);
6412 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
6413 /* disable the panel fitter on everything but LVDS */
6414 I915_WRITE(PFIT_CONTROL
, 0);
6417 if (HAS_PCH_SPLIT(dev
)) {
6418 dpd_is_edp
= intel_dpd_is_edp(dev
);
6421 intel_dp_init(dev
, DP_A
);
6423 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6424 intel_dp_init(dev
, PCH_DP_D
);
6427 intel_crt_init(dev
);
6429 if (HAS_PCH_SPLIT(dev
)) {
6432 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
6433 /* PCH SDVOB multiplex with HDMIB */
6434 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
6436 intel_hdmi_init(dev
, HDMIB
);
6437 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
6438 intel_dp_init(dev
, PCH_DP_B
);
6441 if (I915_READ(HDMIC
) & PORT_DETECTED
)
6442 intel_hdmi_init(dev
, HDMIC
);
6444 if (I915_READ(HDMID
) & PORT_DETECTED
)
6445 intel_hdmi_init(dev
, HDMID
);
6447 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
6448 intel_dp_init(dev
, PCH_DP_C
);
6450 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6451 intel_dp_init(dev
, PCH_DP_D
);
6453 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
6456 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6457 DRM_DEBUG_KMS("probing SDVOB\n");
6458 found
= intel_sdvo_init(dev
, SDVOB
);
6459 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
6460 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6461 intel_hdmi_init(dev
, SDVOB
);
6464 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
6465 DRM_DEBUG_KMS("probing DP_B\n");
6466 intel_dp_init(dev
, DP_B
);
6470 /* Before G4X SDVOC doesn't have its own detect register */
6472 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6473 DRM_DEBUG_KMS("probing SDVOC\n");
6474 found
= intel_sdvo_init(dev
, SDVOC
);
6477 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
6479 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
6480 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6481 intel_hdmi_init(dev
, SDVOC
);
6483 if (SUPPORTS_INTEGRATED_DP(dev
)) {
6484 DRM_DEBUG_KMS("probing DP_C\n");
6485 intel_dp_init(dev
, DP_C
);
6489 if (SUPPORTS_INTEGRATED_DP(dev
) &&
6490 (I915_READ(DP_D
) & DP_DETECTED
)) {
6491 DRM_DEBUG_KMS("probing DP_D\n");
6492 intel_dp_init(dev
, DP_D
);
6494 } else if (IS_GEN2(dev
))
6495 intel_dvo_init(dev
);
6497 if (SUPPORTS_TV(dev
))
6500 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6501 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
6502 encoder
->base
.possible_clones
=
6503 intel_encoder_clones(dev
, encoder
->clone_mask
);
6506 intel_panel_setup_backlight(dev
);
6509 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
6511 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6513 drm_framebuffer_cleanup(fb
);
6514 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
6519 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
6520 struct drm_file
*file
,
6521 unsigned int *handle
)
6523 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6524 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
6526 return drm_gem_handle_create(file
, &obj
->base
, handle
);
6529 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
6530 .destroy
= intel_user_framebuffer_destroy
,
6531 .create_handle
= intel_user_framebuffer_create_handle
,
6534 int intel_framebuffer_init(struct drm_device
*dev
,
6535 struct intel_framebuffer
*intel_fb
,
6536 struct drm_mode_fb_cmd
*mode_cmd
,
6537 struct drm_i915_gem_object
*obj
)
6541 if (obj
->tiling_mode
== I915_TILING_Y
)
6544 if (mode_cmd
->pitch
& 63)
6547 switch (mode_cmd
->bpp
) {
6557 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
6559 DRM_ERROR("framebuffer init failed %d\n", ret
);
6563 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
6564 intel_fb
->obj
= obj
;
6568 static struct drm_framebuffer
*
6569 intel_user_framebuffer_create(struct drm_device
*dev
,
6570 struct drm_file
*filp
,
6571 struct drm_mode_fb_cmd
*mode_cmd
)
6573 struct drm_i915_gem_object
*obj
;
6574 struct intel_framebuffer
*intel_fb
;
6577 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
));
6578 if (&obj
->base
== NULL
)
6579 return ERR_PTR(-ENOENT
);
6581 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6583 drm_gem_object_unreference_unlocked(&obj
->base
);
6584 return ERR_PTR(-ENOMEM
);
6587 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6589 drm_gem_object_unreference_unlocked(&obj
->base
);
6591 return ERR_PTR(ret
);
6594 return &intel_fb
->base
;
6597 static const struct drm_mode_config_funcs intel_mode_funcs
= {
6598 .fb_create
= intel_user_framebuffer_create
,
6599 .output_poll_changed
= intel_fb_output_poll_changed
,
6602 static struct drm_i915_gem_object
*
6603 intel_alloc_context_page(struct drm_device
*dev
)
6605 struct drm_i915_gem_object
*ctx
;
6608 ctx
= i915_gem_alloc_object(dev
, 4096);
6610 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6614 mutex_lock(&dev
->struct_mutex
);
6615 ret
= i915_gem_object_pin(ctx
, 4096, true);
6617 DRM_ERROR("failed to pin power context: %d\n", ret
);
6621 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
6623 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
6626 mutex_unlock(&dev
->struct_mutex
);
6631 i915_gem_object_unpin(ctx
);
6633 drm_gem_object_unreference(&ctx
->base
);
6634 mutex_unlock(&dev
->struct_mutex
);
6638 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
6640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6643 rgvswctl
= I915_READ16(MEMSWCTL
);
6644 if (rgvswctl
& MEMCTL_CMD_STS
) {
6645 DRM_DEBUG("gpu busy, RCS change rejected\n");
6646 return false; /* still busy with another command */
6649 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
6650 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
6651 I915_WRITE16(MEMSWCTL
, rgvswctl
);
6652 POSTING_READ16(MEMSWCTL
);
6654 rgvswctl
|= MEMCTL_CMD_STS
;
6655 I915_WRITE16(MEMSWCTL
, rgvswctl
);
6660 void ironlake_enable_drps(struct drm_device
*dev
)
6662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6663 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
6664 u8 fmax
, fmin
, fstart
, vstart
;
6666 /* Enable temp reporting */
6667 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
6668 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
6670 /* 100ms RC evaluation intervals */
6671 I915_WRITE(RCUPEI
, 100000);
6672 I915_WRITE(RCDNEI
, 100000);
6674 /* Set max/min thresholds to 90ms and 80ms respectively */
6675 I915_WRITE(RCBMAXAVG
, 90000);
6676 I915_WRITE(RCBMINAVG
, 80000);
6678 I915_WRITE(MEMIHYST
, 1);
6680 /* Set up min, max, and cur for interrupt handling */
6681 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
6682 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
6683 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
6684 MEMMODE_FSTART_SHIFT
;
6686 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
6689 dev_priv
->fmax
= fmax
; /* IPS callback will increase this */
6690 dev_priv
->fstart
= fstart
;
6692 dev_priv
->max_delay
= fstart
;
6693 dev_priv
->min_delay
= fmin
;
6694 dev_priv
->cur_delay
= fstart
;
6696 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6697 fmax
, fmin
, fstart
);
6699 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
6702 * Interrupts will be enabled in ironlake_irq_postinstall
6705 I915_WRITE(VIDSTART
, vstart
);
6706 POSTING_READ(VIDSTART
);
6708 rgvmodectl
|= MEMMODE_SWMODE_EN
;
6709 I915_WRITE(MEMMODECTL
, rgvmodectl
);
6711 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
6712 DRM_ERROR("stuck trying to change perf mode\n");
6715 ironlake_set_drps(dev
, fstart
);
6717 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
6719 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
6720 dev_priv
->last_count2
= I915_READ(0x112f4);
6721 getrawmonotonic(&dev_priv
->last_time2
);
6724 void ironlake_disable_drps(struct drm_device
*dev
)
6726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6727 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
6729 /* Ack interrupts, disable EFC interrupt */
6730 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
6731 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
6732 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
6733 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
6734 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
6736 /* Go back to the starting frequency */
6737 ironlake_set_drps(dev
, dev_priv
->fstart
);
6739 rgvswctl
|= MEMCTL_CMD_STS
;
6740 I915_WRITE(MEMSWCTL
, rgvswctl
);
6745 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
6747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6750 swreq
= (val
& 0x3ff) << 25;
6751 I915_WRITE(GEN6_RPNSWREQ
, swreq
);
6754 void gen6_disable_rps(struct drm_device
*dev
)
6756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6758 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
6759 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
6760 I915_WRITE(GEN6_PMIER
, 0);
6761 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
6764 static unsigned long intel_pxfreq(u32 vidfreq
)
6767 int div
= (vidfreq
& 0x3f0000) >> 16;
6768 int post
= (vidfreq
& 0x3000) >> 12;
6769 int pre
= (vidfreq
& 0x7);
6774 freq
= ((div
* 133333) / ((1<<post
) * pre
));
6779 void intel_init_emon(struct drm_device
*dev
)
6781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6786 /* Disable to program */
6790 /* Program energy weights for various events */
6791 I915_WRITE(SDEW
, 0x15040d00);
6792 I915_WRITE(CSIEW0
, 0x007f0000);
6793 I915_WRITE(CSIEW1
, 0x1e220004);
6794 I915_WRITE(CSIEW2
, 0x04000004);
6796 for (i
= 0; i
< 5; i
++)
6797 I915_WRITE(PEW
+ (i
* 4), 0);
6798 for (i
= 0; i
< 3; i
++)
6799 I915_WRITE(DEW
+ (i
* 4), 0);
6801 /* Program P-state weights to account for frequency power adjustment */
6802 for (i
= 0; i
< 16; i
++) {
6803 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
6804 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6805 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6810 val
*= (freq
/ 1000);
6812 val
/= (127*127*900);
6814 DRM_ERROR("bad pxval: %ld\n", val
);
6817 /* Render standby states get 0 weight */
6821 for (i
= 0; i
< 4; i
++) {
6822 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6823 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6824 I915_WRITE(PXW
+ (i
* 4), val
);
6827 /* Adjust magic regs to magic values (more experimental results) */
6828 I915_WRITE(OGW0
, 0);
6829 I915_WRITE(OGW1
, 0);
6830 I915_WRITE(EG0
, 0x00007f00);
6831 I915_WRITE(EG1
, 0x0000000e);
6832 I915_WRITE(EG2
, 0x000e0000);
6833 I915_WRITE(EG3
, 0x68000300);
6834 I915_WRITE(EG4
, 0x42000000);
6835 I915_WRITE(EG5
, 0x00140031);
6839 for (i
= 0; i
< 8; i
++)
6840 I915_WRITE(PXWL
+ (i
* 4), 0);
6842 /* Enable PMON + select events */
6843 I915_WRITE(ECR
, 0x80000019);
6845 lcfuse
= I915_READ(LCFUSE02
);
6847 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6850 void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
6852 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
6853 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
6855 int cur_freq
, min_freq
, max_freq
;
6858 /* Here begins a magic sequence of register writes to enable
6859 * auto-downclocking.
6861 * Perhaps there might be some value in exposing these to
6864 I915_WRITE(GEN6_RC_STATE
, 0);
6865 __gen6_gt_force_wake_get(dev_priv
);
6867 /* disable the counters and set deterministic thresholds */
6868 I915_WRITE(GEN6_RC_CONTROL
, 0);
6870 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
6871 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
6872 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
6873 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6874 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6876 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
6877 I915_WRITE(RING_MAX_IDLE(dev_priv
->ring
[i
].mmio_base
), 10);
6879 I915_WRITE(GEN6_RC_SLEEP
, 0);
6880 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
6881 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
6882 I915_WRITE(GEN6_RC6p_THRESHOLD
, 100000);
6883 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
6885 I915_WRITE(GEN6_RC_CONTROL
,
6886 GEN6_RC_CTL_RC6p_ENABLE
|
6887 GEN6_RC_CTL_RC6_ENABLE
|
6888 GEN6_RC_CTL_EI_MODE(1) |
6889 GEN6_RC_CTL_HW_ENABLE
);
6891 I915_WRITE(GEN6_RPNSWREQ
,
6892 GEN6_FREQUENCY(10) |
6894 GEN6_AGGRESSIVE_TURBO
);
6895 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6896 GEN6_FREQUENCY(12));
6898 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6899 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
6902 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 10000);
6903 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 1000000);
6904 I915_WRITE(GEN6_RP_UP_EI
, 100000);
6905 I915_WRITE(GEN6_RP_DOWN_EI
, 5000000);
6906 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6907 I915_WRITE(GEN6_RP_CONTROL
,
6908 GEN6_RP_MEDIA_TURBO
|
6909 GEN6_RP_USE_NORMAL_FREQ
|
6910 GEN6_RP_MEDIA_IS_GFX
|
6912 GEN6_RP_UP_BUSY_AVG
|
6913 GEN6_RP_DOWN_IDLE_CONT
);
6915 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6917 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6919 I915_WRITE(GEN6_PCODE_DATA
, 0);
6920 I915_WRITE(GEN6_PCODE_MAILBOX
,
6922 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
6923 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6925 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6927 min_freq
= (rp_state_cap
& 0xff0000) >> 16;
6928 max_freq
= rp_state_cap
& 0xff;
6929 cur_freq
= (gt_perf_status
& 0xff00) >> 8;
6931 /* Check for overclock support */
6932 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6934 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6935 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_READ_OC_PARAMS
);
6936 pcu_mbox
= I915_READ(GEN6_PCODE_DATA
);
6937 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6939 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6940 if (pcu_mbox
& (1<<31)) { /* OC supported */
6941 max_freq
= pcu_mbox
& 0xff;
6942 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox
* 50);
6945 /* In units of 100MHz */
6946 dev_priv
->max_delay
= max_freq
;
6947 dev_priv
->min_delay
= min_freq
;
6948 dev_priv
->cur_delay
= cur_freq
;
6950 /* requires MSI enabled */
6951 I915_WRITE(GEN6_PMIER
,
6952 GEN6_PM_MBOX_EVENT
|
6953 GEN6_PM_THERMAL_EVENT
|
6954 GEN6_PM_RP_DOWN_TIMEOUT
|
6955 GEN6_PM_RP_UP_THRESHOLD
|
6956 GEN6_PM_RP_DOWN_THRESHOLD
|
6957 GEN6_PM_RP_UP_EI_EXPIRED
|
6958 GEN6_PM_RP_DOWN_EI_EXPIRED
);
6959 I915_WRITE(GEN6_PMIMR
, 0);
6960 /* enable all PM interrupts */
6961 I915_WRITE(GEN6_PMINTRMSK
, 0);
6963 __gen6_gt_force_wake_put(dev_priv
);
6966 void intel_enable_clock_gating(struct drm_device
*dev
)
6968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6972 * Disable clock gating reported to work incorrectly according to the
6973 * specs, but enable as much else as we can.
6975 if (HAS_PCH_SPLIT(dev
)) {
6976 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
6979 /* Required for FBC */
6980 dspclk_gate
|= DPFCUNIT_CLOCK_GATE_DISABLE
|
6981 DPFCRUNIT_CLOCK_GATE_DISABLE
|
6982 DPFDUNIT_CLOCK_GATE_DISABLE
;
6983 /* Required for CxSR */
6984 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
6986 I915_WRITE(PCH_3DCGDIS0
,
6987 MARIUNIT_CLOCK_GATE_DISABLE
|
6988 SVSMUNIT_CLOCK_GATE_DISABLE
);
6989 I915_WRITE(PCH_3DCGDIS1
,
6990 VFMUNIT_CLOCK_GATE_DISABLE
);
6993 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
6996 * On Ibex Peak and Cougar Point, we need to disable clock
6997 * gating for the panel power sequencer or it will fail to
6998 * start up when no ports are active.
7000 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
7003 * According to the spec the following bits should be set in
7004 * order to enable memory self-refresh
7005 * The bit 22/21 of 0x42004
7006 * The bit 5 of 0x42020
7007 * The bit 15 of 0x45000
7010 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7011 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
7012 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
7013 I915_WRITE(ILK_DSPCLK_GATE
,
7014 (I915_READ(ILK_DSPCLK_GATE
) |
7015 ILK_DPARB_CLK_GATE
));
7016 I915_WRITE(DISP_ARB_CTL
,
7017 (I915_READ(DISP_ARB_CTL
) |
7019 I915_WRITE(WM3_LP_ILK
, 0);
7020 I915_WRITE(WM2_LP_ILK
, 0);
7021 I915_WRITE(WM1_LP_ILK
, 0);
7024 * Based on the document from hardware guys the following bits
7025 * should be set unconditionally in order to enable FBC.
7026 * The bit 22 of 0x42000
7027 * The bit 22 of 0x42004
7028 * The bit 7,8,9 of 0x42020.
7030 if (IS_IRONLAKE_M(dev
)) {
7031 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7032 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7034 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7035 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7037 I915_WRITE(ILK_DSPCLK_GATE
,
7038 I915_READ(ILK_DSPCLK_GATE
) |
7044 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7045 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7046 ILK_ELPIN_409_SELECT
);
7049 I915_WRITE(_3D_CHICKEN2
,
7050 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
7051 _3D_CHICKEN2_WM_READ_PIPELINED
);
7055 I915_WRITE(WM3_LP_ILK
, 0);
7056 I915_WRITE(WM2_LP_ILK
, 0);
7057 I915_WRITE(WM1_LP_ILK
, 0);
7060 * According to the spec the following bits should be
7061 * set in order to enable memory self-refresh and fbc:
7062 * The bit21 and bit22 of 0x42000
7063 * The bit21 and bit22 of 0x42004
7064 * The bit5 and bit7 of 0x42020
7065 * The bit14 of 0x70180
7066 * The bit14 of 0x71180
7068 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7069 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7070 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
7071 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7072 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7073 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
7074 I915_WRITE(ILK_DSPCLK_GATE
,
7075 I915_READ(ILK_DSPCLK_GATE
) |
7076 ILK_DPARB_CLK_GATE
|
7080 I915_WRITE(DSPCNTR(pipe
),
7081 I915_READ(DSPCNTR(pipe
)) |
7082 DISPPLANE_TRICKLE_FEED_DISABLE
);
7084 } else if (IS_G4X(dev
)) {
7085 uint32_t dspclk_gate
;
7086 I915_WRITE(RENCLK_GATE_D1
, 0);
7087 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7088 GS_UNIT_CLOCK_GATE_DISABLE
|
7089 CL_UNIT_CLOCK_GATE_DISABLE
);
7090 I915_WRITE(RAMCLK_GATE_D
, 0);
7091 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7092 OVRUNIT_CLOCK_GATE_DISABLE
|
7093 OVCUNIT_CLOCK_GATE_DISABLE
;
7095 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7096 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7097 } else if (IS_CRESTLINE(dev
)) {
7098 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7099 I915_WRITE(RENCLK_GATE_D2
, 0);
7100 I915_WRITE(DSPCLK_GATE_D
, 0);
7101 I915_WRITE(RAMCLK_GATE_D
, 0);
7102 I915_WRITE16(DEUC
, 0);
7103 } else if (IS_BROADWATER(dev
)) {
7104 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7105 I965_RCC_CLOCK_GATE_DISABLE
|
7106 I965_RCPB_CLOCK_GATE_DISABLE
|
7107 I965_ISC_CLOCK_GATE_DISABLE
|
7108 I965_FBC_CLOCK_GATE_DISABLE
);
7109 I915_WRITE(RENCLK_GATE_D2
, 0);
7110 } else if (IS_GEN3(dev
)) {
7111 u32 dstate
= I915_READ(D_STATE
);
7113 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7114 DSTATE_DOT_CLOCK_GATING
;
7115 I915_WRITE(D_STATE
, dstate
);
7116 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
7117 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7118 } else if (IS_I830(dev
)) {
7119 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
7123 static void ironlake_teardown_rc6(struct drm_device
*dev
)
7125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7127 if (dev_priv
->renderctx
) {
7128 i915_gem_object_unpin(dev_priv
->renderctx
);
7129 drm_gem_object_unreference(&dev_priv
->renderctx
->base
);
7130 dev_priv
->renderctx
= NULL
;
7133 if (dev_priv
->pwrctx
) {
7134 i915_gem_object_unpin(dev_priv
->pwrctx
);
7135 drm_gem_object_unreference(&dev_priv
->pwrctx
->base
);
7136 dev_priv
->pwrctx
= NULL
;
7140 static void ironlake_disable_rc6(struct drm_device
*dev
)
7142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7144 if (I915_READ(PWRCTXA
)) {
7145 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7146 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
7147 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
7150 I915_WRITE(PWRCTXA
, 0);
7151 POSTING_READ(PWRCTXA
);
7153 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
7154 POSTING_READ(RSTDBYCTL
);
7157 ironlake_teardown_rc6(dev
);
7160 static int ironlake_setup_rc6(struct drm_device
*dev
)
7162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7164 if (dev_priv
->renderctx
== NULL
)
7165 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
7166 if (!dev_priv
->renderctx
)
7169 if (dev_priv
->pwrctx
== NULL
)
7170 dev_priv
->pwrctx
= intel_alloc_context_page(dev
);
7171 if (!dev_priv
->pwrctx
) {
7172 ironlake_teardown_rc6(dev
);
7179 void ironlake_enable_rc6(struct drm_device
*dev
)
7181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7184 /* rc6 disabled by default due to repeated reports of hanging during
7187 if (!i915_enable_rc6
)
7190 ret
= ironlake_setup_rc6(dev
);
7195 * GPU can automatically power down the render unit if given a page
7198 ret
= BEGIN_LP_RING(6);
7200 ironlake_teardown_rc6(dev
);
7204 OUT_RING(MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
7205 OUT_RING(MI_SET_CONTEXT
);
7206 OUT_RING(dev_priv
->renderctx
->gtt_offset
|
7208 MI_SAVE_EXT_STATE_EN
|
7209 MI_RESTORE_EXT_STATE_EN
|
7210 MI_RESTORE_INHIBIT
);
7211 OUT_RING(MI_SUSPEND_FLUSH
);
7216 I915_WRITE(PWRCTXA
, dev_priv
->pwrctx
->gtt_offset
| PWRCTX_EN
);
7217 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
7221 /* Set up chip specific display functions */
7222 static void intel_init_display(struct drm_device
*dev
)
7224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7226 /* We always want a DPMS function */
7227 if (HAS_PCH_SPLIT(dev
))
7228 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
7230 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
7232 if (I915_HAS_FBC(dev
)) {
7233 if (HAS_PCH_SPLIT(dev
)) {
7234 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
7235 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
7236 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
7237 } else if (IS_GM45(dev
)) {
7238 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
7239 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
7240 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
7241 } else if (IS_CRESTLINE(dev
)) {
7242 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
7243 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
7244 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
7246 /* 855GM needs testing */
7249 /* Returns the core display clock speed */
7250 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
7251 dev_priv
->display
.get_display_clock_speed
=
7252 i945_get_display_clock_speed
;
7253 else if (IS_I915G(dev
))
7254 dev_priv
->display
.get_display_clock_speed
=
7255 i915_get_display_clock_speed
;
7256 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
7257 dev_priv
->display
.get_display_clock_speed
=
7258 i9xx_misc_get_display_clock_speed
;
7259 else if (IS_I915GM(dev
))
7260 dev_priv
->display
.get_display_clock_speed
=
7261 i915gm_get_display_clock_speed
;
7262 else if (IS_I865G(dev
))
7263 dev_priv
->display
.get_display_clock_speed
=
7264 i865_get_display_clock_speed
;
7265 else if (IS_I85X(dev
))
7266 dev_priv
->display
.get_display_clock_speed
=
7267 i855_get_display_clock_speed
;
7269 dev_priv
->display
.get_display_clock_speed
=
7270 i830_get_display_clock_speed
;
7272 /* For FIFO watermark updates */
7273 if (HAS_PCH_SPLIT(dev
)) {
7275 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
7276 dev_priv
->display
.update_wm
= ironlake_update_wm
;
7278 DRM_DEBUG_KMS("Failed to get proper latency. "
7280 dev_priv
->display
.update_wm
= NULL
;
7282 } else if (IS_GEN6(dev
)) {
7283 if (SNB_READ_WM0_LATENCY()) {
7284 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
7286 DRM_DEBUG_KMS("Failed to read display plane latency. "
7288 dev_priv
->display
.update_wm
= NULL
;
7291 dev_priv
->display
.update_wm
= NULL
;
7292 } else if (IS_PINEVIEW(dev
)) {
7293 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7296 dev_priv
->mem_freq
)) {
7297 DRM_INFO("failed to find known CxSR latency "
7298 "(found ddr%s fsb freq %d, mem freq %d), "
7300 (dev_priv
->is_ddr3
== 1) ? "3": "2",
7301 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7302 /* Disable CxSR and never update its watermark again */
7303 pineview_disable_cxsr(dev
);
7304 dev_priv
->display
.update_wm
= NULL
;
7306 dev_priv
->display
.update_wm
= pineview_update_wm
;
7307 } else if (IS_G4X(dev
))
7308 dev_priv
->display
.update_wm
= g4x_update_wm
;
7309 else if (IS_GEN4(dev
))
7310 dev_priv
->display
.update_wm
= i965_update_wm
;
7311 else if (IS_GEN3(dev
)) {
7312 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7313 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7314 } else if (IS_I85X(dev
)) {
7315 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7316 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
7318 dev_priv
->display
.update_wm
= i830_update_wm
;
7320 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7322 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7327 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7328 * resume, or other times. This quirk makes sure that's the case for
7331 static void quirk_pipea_force (struct drm_device
*dev
)
7333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7335 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7336 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7339 struct intel_quirk
{
7341 int subsystem_vendor
;
7342 int subsystem_device
;
7343 void (*hook
)(struct drm_device
*dev
);
7346 struct intel_quirk intel_quirks
[] = {
7347 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7348 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
7349 /* HP Mini needs pipe A force quirk (LP: #322104) */
7350 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
7352 /* Thinkpad R31 needs pipe A force quirk */
7353 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
7354 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7355 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7357 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7358 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
7359 /* ThinkPad X40 needs pipe A force quirk */
7361 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7362 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7364 /* 855 & before need to leave pipe A & dpll A up */
7365 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7366 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7369 static void intel_init_quirks(struct drm_device
*dev
)
7371 struct pci_dev
*d
= dev
->pdev
;
7374 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
7375 struct intel_quirk
*q
= &intel_quirks
[i
];
7377 if (d
->device
== q
->device
&&
7378 (d
->subsystem_vendor
== q
->subsystem_vendor
||
7379 q
->subsystem_vendor
== PCI_ANY_ID
) &&
7380 (d
->subsystem_device
== q
->subsystem_device
||
7381 q
->subsystem_device
== PCI_ANY_ID
))
7386 /* Disable the VGA plane that we never use */
7387 static void i915_disable_vga(struct drm_device
*dev
)
7389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7393 if (HAS_PCH_SPLIT(dev
))
7394 vga_reg
= CPU_VGACNTRL
;
7398 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7399 outb(1, VGA_SR_INDEX
);
7400 sr1
= inb(VGA_SR_DATA
);
7401 outb(sr1
| 1<<5, VGA_SR_DATA
);
7402 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7405 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
7406 POSTING_READ(vga_reg
);
7409 void intel_modeset_init(struct drm_device
*dev
)
7411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7414 drm_mode_config_init(dev
);
7416 dev
->mode_config
.min_width
= 0;
7417 dev
->mode_config
.min_height
= 0;
7419 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
7421 intel_init_quirks(dev
);
7423 intel_init_display(dev
);
7426 dev
->mode_config
.max_width
= 2048;
7427 dev
->mode_config
.max_height
= 2048;
7428 } else if (IS_GEN3(dev
)) {
7429 dev
->mode_config
.max_width
= 4096;
7430 dev
->mode_config
.max_height
= 4096;
7432 dev
->mode_config
.max_width
= 8192;
7433 dev
->mode_config
.max_height
= 8192;
7435 dev
->mode_config
.fb_base
= dev
->agp
->base
;
7437 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7438 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
7440 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
7441 intel_crtc_init(dev
, i
);
7444 intel_setup_outputs(dev
);
7446 intel_enable_clock_gating(dev
);
7448 /* Just disable it once at startup */
7449 i915_disable_vga(dev
);
7451 if (IS_IRONLAKE_M(dev
)) {
7452 ironlake_enable_drps(dev
);
7453 intel_init_emon(dev
);
7457 gen6_enable_rps(dev_priv
);
7459 if (IS_IRONLAKE_M(dev
))
7460 ironlake_enable_rc6(dev
);
7462 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
7463 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
7464 (unsigned long)dev
);
7466 intel_setup_overlay(dev
);
7469 void intel_modeset_cleanup(struct drm_device
*dev
)
7471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7472 struct drm_crtc
*crtc
;
7473 struct intel_crtc
*intel_crtc
;
7475 drm_kms_helper_poll_fini(dev
);
7476 mutex_lock(&dev
->struct_mutex
);
7478 intel_unregister_dsm_handler();
7481 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7482 /* Skip inactive CRTCs */
7486 intel_crtc
= to_intel_crtc(crtc
);
7487 intel_increase_pllclock(crtc
);
7490 if (dev_priv
->display
.disable_fbc
)
7491 dev_priv
->display
.disable_fbc(dev
);
7493 if (IS_IRONLAKE_M(dev
))
7494 ironlake_disable_drps(dev
);
7496 gen6_disable_rps(dev
);
7498 if (IS_IRONLAKE_M(dev
))
7499 ironlake_disable_rc6(dev
);
7501 mutex_unlock(&dev
->struct_mutex
);
7503 /* Disable the irq before mode object teardown, for the irq might
7504 * enqueue unpin/hotplug work. */
7505 drm_irq_uninstall(dev
);
7506 cancel_work_sync(&dev_priv
->hotplug_work
);
7508 /* Shut off idle work before the crtcs get freed. */
7509 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7510 intel_crtc
= to_intel_crtc(crtc
);
7511 del_timer_sync(&intel_crtc
->idle_timer
);
7513 del_timer_sync(&dev_priv
->idle_timer
);
7514 cancel_work_sync(&dev_priv
->idle_work
);
7516 drm_mode_config_cleanup(dev
);
7520 * Return which encoder is currently attached for connector.
7522 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
7524 return &intel_attached_encoder(connector
)->base
;
7527 void intel_connector_attach_encoder(struct intel_connector
*connector
,
7528 struct intel_encoder
*encoder
)
7530 connector
->encoder
= encoder
;
7531 drm_mode_connector_attach_encoder(&connector
->base
,
7536 * set vga decode state - true == enable VGA decode
7538 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
7540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7543 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
7545 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
7547 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
7548 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
7552 #ifdef CONFIG_DEBUG_FS
7553 #include <linux/seq_file.h>
7555 struct intel_display_error_state
{
7556 struct intel_cursor_error_state
{
7563 struct intel_pipe_error_state
{
7575 struct intel_plane_error_state
{
7586 struct intel_display_error_state
*
7587 intel_display_capture_error_state(struct drm_device
*dev
)
7589 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7590 struct intel_display_error_state
*error
;
7593 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
7597 for (i
= 0; i
< 2; i
++) {
7598 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
7599 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
7600 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
7602 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
7603 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
7604 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
7605 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
7606 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
7607 if (INTEL_INFO(dev
)->gen
>= 4) {
7608 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
7609 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
7612 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
7613 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
7614 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
7615 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
7616 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
7617 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
7618 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
7619 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
7626 intel_display_print_error_state(struct seq_file
*m
,
7627 struct drm_device
*dev
,
7628 struct intel_display_error_state
*error
)
7632 for (i
= 0; i
< 2; i
++) {
7633 seq_printf(m
, "Pipe [%d]:\n", i
);
7634 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
7635 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
7636 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
7637 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
7638 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
7639 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
7640 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
7641 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
7643 seq_printf(m
, "Plane [%d]:\n", i
);
7644 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
7645 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
7646 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
7647 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
7648 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
7649 if (INTEL_INFO(dev
)->gen
>= 4) {
7650 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
7651 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
7654 seq_printf(m
, "Cursor [%d]:\n", i
);
7655 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
7656 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
7657 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);