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drm/i915: Separate intel_frontbuffer into its own header
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_device *dev,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
629 INTELPllInvalid("vco out of range\n");
630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
634 INTELPllInvalid("dot out of range\n");
635
636 return true;
637 }
638
639 static int
640 i9xx_select_p2_div(const struct intel_limit *limit,
641 const struct intel_crtc_state *crtc_state,
642 int target)
643 {
644 struct drm_device *dev = crtc_state->base.crtc->dev;
645
646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
647 /*
648 * For LVDS just rely on its current settings for dual-channel.
649 * We haven't figured out how to reliably set up different
650 * single/dual channel state, if we even can.
651 */
652 if (intel_is_dual_link_lvds(dev))
653 return limit->p2.p2_fast;
654 else
655 return limit->p2.p2_slow;
656 } else {
657 if (target < limit->p2.dot_limit)
658 return limit->p2.p2_slow;
659 else
660 return limit->p2.p2_fast;
661 }
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 i9xx_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 if (clock.m2 >= clock.m1)
693 break;
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 i9xx_calc_dpll_params(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 /*
722 * Returns a set of divisors for the desired target clock with the given
723 * refclk, or FALSE. The returned values represent the clock equation:
724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725 *
726 * Target and reference clocks are specified in kHz.
727 *
728 * If match_clock is provided, then best_clock P divider must match the P
729 * divider from @match_clock used for LVDS downclocking.
730 */
731 static bool
732 pnv_find_best_dpll(const struct intel_limit *limit,
733 struct intel_crtc_state *crtc_state,
734 int target, int refclk, struct dpll *match_clock,
735 struct dpll *best_clock)
736 {
737 struct drm_device *dev = crtc_state->base.crtc->dev;
738 struct dpll clock;
739 int err = target;
740
741 memset(best_clock, 0, sizeof(*best_clock));
742
743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
744
745 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
746 clock.m1++) {
747 for (clock.m2 = limit->m2.min;
748 clock.m2 <= limit->m2.max; clock.m2++) {
749 for (clock.n = limit->n.min;
750 clock.n <= limit->n.max; clock.n++) {
751 for (clock.p1 = limit->p1.min;
752 clock.p1 <= limit->p1.max; clock.p1++) {
753 int this_err;
754
755 pnv_calc_dpll_params(refclk, &clock);
756 if (!intel_PLL_is_valid(dev, limit,
757 &clock))
758 continue;
759 if (match_clock &&
760 clock.p != match_clock->p)
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err) {
765 *best_clock = clock;
766 err = this_err;
767 }
768 }
769 }
770 }
771 }
772
773 return (err != target);
774 }
775
776 /*
777 * Returns a set of divisors for the desired target clock with the given
778 * refclk, or FALSE. The returned values represent the clock equation:
779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
780 *
781 * Target and reference clocks are specified in kHz.
782 *
783 * If match_clock is provided, then best_clock P divider must match the P
784 * divider from @match_clock used for LVDS downclocking.
785 */
786 static bool
787 g4x_find_best_dpll(const struct intel_limit *limit,
788 struct intel_crtc_state *crtc_state,
789 int target, int refclk, struct dpll *match_clock,
790 struct dpll *best_clock)
791 {
792 struct drm_device *dev = crtc_state->base.crtc->dev;
793 struct dpll clock;
794 int max_n;
795 bool found = false;
796 /* approximately equals target * 0.00585 */
797 int err_most = (target >> 8) + (target >> 9);
798
799 memset(best_clock, 0, sizeof(*best_clock));
800
801 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
802
803 max_n = limit->n.max;
804 /* based on hardware requirement, prefer smaller n to precision */
805 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
806 /* based on hardware requirement, prefere larger m1,m2 */
807 for (clock.m1 = limit->m1.max;
808 clock.m1 >= limit->m1.min; clock.m1--) {
809 for (clock.m2 = limit->m2.max;
810 clock.m2 >= limit->m2.min; clock.m2--) {
811 for (clock.p1 = limit->p1.max;
812 clock.p1 >= limit->p1.min; clock.p1--) {
813 int this_err;
814
815 i9xx_calc_dpll_params(refclk, &clock);
816 if (!intel_PLL_is_valid(dev, limit,
817 &clock))
818 continue;
819
820 this_err = abs(clock.dot - target);
821 if (this_err < err_most) {
822 *best_clock = clock;
823 err_most = this_err;
824 max_n = clock.n;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831 return found;
832 }
833
834 /*
835 * Check if the calculated PLL configuration is more optimal compared to the
836 * best configuration and error found so far. Return the calculated error.
837 */
838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
839 const struct dpll *calculated_clock,
840 const struct dpll *best_clock,
841 unsigned int best_error_ppm,
842 unsigned int *error_ppm)
843 {
844 /*
845 * For CHV ignore the error and consider only the P value.
846 * Prefer a bigger P value based on HW requirements.
847 */
848 if (IS_CHERRYVIEW(dev)) {
849 *error_ppm = 0;
850
851 return calculated_clock->p > best_clock->p;
852 }
853
854 if (WARN_ON_ONCE(!target_freq))
855 return false;
856
857 *error_ppm = div_u64(1000000ULL *
858 abs(target_freq - calculated_clock->dot),
859 target_freq);
860 /*
861 * Prefer a better P value over a better (smaller) error if the error
862 * is small. Ensure this preference for future configurations too by
863 * setting the error to 0.
864 */
865 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
866 *error_ppm = 0;
867
868 return true;
869 }
870
871 return *error_ppm + 10 < best_error_ppm;
872 }
873
874 /*
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878 */
879 static bool
880 vlv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
884 {
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
887 struct dpll clock;
888 unsigned int bestppm = 1000000;
889 /* min update 19.2 MHz */
890 int max_n = min(limit->n.max, refclk / 19200);
891 bool found = false;
892
893 target *= 5; /* fast clock */
894
895 memset(best_clock, 0, sizeof(*best_clock));
896
897 /* based on hardware requirement, prefer smaller n to precision */
898 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
899 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
900 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
901 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
902 clock.p = clock.p1 * clock.p2;
903 /* based on hardware requirement, prefer bigger m1,m2 values */
904 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
905 unsigned int ppm;
906
907 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
908 refclk * clock.m1);
909
910 vlv_calc_dpll_params(refclk, &clock);
911
912 if (!intel_PLL_is_valid(dev, limit,
913 &clock))
914 continue;
915
916 if (!vlv_PLL_is_optimal(dev, target,
917 &clock,
918 best_clock,
919 bestppm, &ppm))
920 continue;
921
922 *best_clock = clock;
923 bestppm = ppm;
924 found = true;
925 }
926 }
927 }
928 }
929
930 return found;
931 }
932
933 /*
934 * Returns a set of divisors for the desired target clock with the given
935 * refclk, or FALSE. The returned values represent the clock equation:
936 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
937 */
938 static bool
939 chv_find_best_dpll(const struct intel_limit *limit,
940 struct intel_crtc_state *crtc_state,
941 int target, int refclk, struct dpll *match_clock,
942 struct dpll *best_clock)
943 {
944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
945 struct drm_device *dev = crtc->base.dev;
946 unsigned int best_error_ppm;
947 struct dpll clock;
948 uint64_t m2;
949 int found = false;
950
951 memset(best_clock, 0, sizeof(*best_clock));
952 best_error_ppm = 1000000;
953
954 /*
955 * Based on hardware doc, the n always set to 1, and m1 always
956 * set to 2. If requires to support 200Mhz refclk, we need to
957 * revisit this because n may not 1 anymore.
958 */
959 clock.n = 1, clock.m1 = 2;
960 target *= 5; /* fast clock */
961
962 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963 for (clock.p2 = limit->p2.p2_fast;
964 clock.p2 >= limit->p2.p2_slow;
965 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
966 unsigned int error_ppm;
967
968 clock.p = clock.p1 * clock.p2;
969
970 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971 clock.n) << 22, refclk * clock.m1);
972
973 if (m2 > INT_MAX/clock.m1)
974 continue;
975
976 clock.m2 = m2;
977
978 chv_calc_dpll_params(refclk, &clock);
979
980 if (!intel_PLL_is_valid(dev, limit, &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984 best_error_ppm, &error_ppm))
985 continue;
986
987 *best_clock = clock;
988 best_error_ppm = error_ppm;
989 found = true;
990 }
991 }
992
993 return found;
994 }
995
996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
997 struct dpll *best_clock)
998 {
999 int refclk = 100000;
1000 const struct intel_limit *limit = &intel_limits_bxt;
1001
1002 return chv_find_best_dpll(limit, crtc_state,
1003 target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010 /* Be paranoid as we can arrive here with only partial
1011 * state retrieved from the hardware during setup.
1012 *
1013 * We can ditch the adjusted_mode.crtc_clock check as soon
1014 * as Haswell has gained clock readout/fastboot support.
1015 *
1016 * We can ditch the crtc->primary->fb check as soon as we can
1017 * properly reconstruct framebuffers.
1018 *
1019 * FIXME: The intel_crtc->active here should be switched to
1020 * crtc->state->active once we have proper CRTC states wired up
1021 * for atomic.
1022 */
1023 return intel_crtc->active && crtc->primary->state->fb &&
1024 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029 {
1030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033 return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038 struct drm_i915_private *dev_priv = to_i915(dev);
1039 i915_reg_t reg = PIPEDSL(pipe);
1040 u32 line1, line2;
1041 u32 line_mask;
1042
1043 if (IS_GEN2(dev))
1044 line_mask = DSL_LINEMASK_GEN2;
1045 else
1046 line_mask = DSL_LINEMASK_GEN3;
1047
1048 line1 = I915_READ(reg) & line_mask;
1049 msleep(5);
1050 line2 = I915_READ(reg) & line_mask;
1051
1052 return line1 == line2;
1053 }
1054
1055 /*
1056 * intel_wait_for_pipe_off - wait for pipe to turn off
1057 * @crtc: crtc whose pipe to wait for
1058 *
1059 * After disabling a pipe, we can't wait for vblank in the usual way,
1060 * spinning on the vblank interrupt status bit, since we won't actually
1061 * see an interrupt when the pipe is disabled.
1062 *
1063 * On Gen4 and above:
1064 * wait for the pipe register state bit to turn off
1065 *
1066 * Otherwise:
1067 * wait for the display line value to settle (it usually
1068 * ends up stopping at the start of the next frame).
1069 *
1070 */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073 struct drm_device *dev = crtc->base.dev;
1074 struct drm_i915_private *dev_priv = to_i915(dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1077
1078 if (INTEL_INFO(dev)->gen >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
1085 WARN(1, "pipe_off wait timed out\n");
1086 } else {
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1090 }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 u32 val;
1098 bool cur_state;
1099
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110 u32 val;
1111 bool cur_state;
1112
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1116
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 } else {
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1171 return;
1172
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 u32 val;
1181 bool cur_state;
1182
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191 enum pipe pipe)
1192 {
1193 struct drm_device *dev = &dev_priv->drm;
1194 i915_reg_t pp_reg;
1195 u32 val;
1196 enum pipe panel_pipe = PIPE_A;
1197 bool locked = true;
1198
1199 if (WARN_ON(HAS_DDI(dev)))
1200 return;
1201
1202 if (HAS_PCH_SPLIT(dev)) {
1203 u32 port_sel;
1204
1205 pp_reg = PCH_PP_CONTROL;
1206 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1207
1208 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211 /* XXX: else fix for eDP */
1212 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213 /* presumably write lock depends on pipe, not port select */
1214 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1215 panel_pipe = pipe;
1216 } else {
1217 pp_reg = PP_CONTROL;
1218 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219 panel_pipe = PIPE_B;
1220 }
1221
1222 val = I915_READ(pp_reg);
1223 if (!(val & PANEL_POWER_ON) ||
1224 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225 locked = false;
1226
1227 I915_STATE_WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1229 pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1234 {
1235 struct drm_device *dev = &dev_priv->drm;
1236 bool cur_state;
1237
1238 if (IS_845G(dev) || IS_I865G(dev))
1239 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240 else
1241 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243 I915_STATE_WARN(cur_state != state,
1244 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe, bool state)
1252 {
1253 bool cur_state;
1254 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255 pipe);
1256 enum intel_display_power_domain power_domain;
1257
1258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261 state = true;
1262
1263 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268 intel_display_power_put(dev_priv, power_domain);
1269 } else {
1270 cur_state = false;
1271 }
1272
1273 I915_STATE_WARN(cur_state != state,
1274 "pipe %c assertion failure (expected %s, current %s)\n",
1275 pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279 enum plane plane, bool state)
1280 {
1281 u32 val;
1282 bool cur_state;
1283
1284 val = I915_READ(DSPCNTR(plane));
1285 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286 I915_STATE_WARN(cur_state != state,
1287 "plane %c assertion failure (expected %s, current %s)\n",
1288 plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 struct drm_device *dev = &dev_priv->drm;
1298 int i;
1299
1300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
1302 u32 val = I915_READ(DSPCNTR(pipe));
1303 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304 "plane %c assertion failure, should be disabled but not\n",
1305 plane_name(pipe));
1306 return;
1307 }
1308
1309 /* Need to check both planes against the pipe */
1310 for_each_pipe(dev_priv, i) {
1311 u32 val = I915_READ(DSPCNTR(i));
1312 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313 DISPPLANE_SEL_PIPE_SHIFT;
1314 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316 plane_name(i), pipe_name(pipe));
1317 }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe)
1322 {
1323 struct drm_device *dev = &dev_priv->drm;
1324 int sprite;
1325
1326 if (INTEL_INFO(dev)->gen >= 9) {
1327 for_each_sprite(dev_priv, pipe, sprite) {
1328 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331 sprite, pipe_name(pipe));
1332 }
1333 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334 for_each_sprite(dev_priv, pipe, sprite) {
1335 u32 val = I915_READ(SPCNTR(pipe, sprite));
1336 I915_STATE_WARN(val & SP_ENABLE,
1337 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338 sprite_name(pipe, sprite), pipe_name(pipe));
1339 }
1340 } else if (INTEL_INFO(dev)->gen >= 7) {
1341 u32 val = I915_READ(SPRCTL(pipe));
1342 I915_STATE_WARN(val & SPRITE_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 } else if (INTEL_INFO(dev)->gen >= 5) {
1346 u32 val = I915_READ(DVSCNTR(pipe));
1347 I915_STATE_WARN(val & DVS_ENABLE,
1348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
1350 }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 u32 val;
1363 bool enabled;
1364
1365 val = I915_READ(PCH_TRANSCONF(pipe));
1366 enabled = !!(val & TRANS_ENABLE);
1367 I915_STATE_WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375 if ((val & DP_PORT_EN) == 0)
1376 return false;
1377
1378 if (HAS_PCH_CPT(dev_priv)) {
1379 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381 return false;
1382 } else if (IS_CHERRYVIEW(dev_priv)) {
1383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384 return false;
1385 } else {
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & SDVO_ENABLE) == 0)
1396 return false;
1397
1398 if (HAS_PCH_CPT(dev_priv)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400 return false;
1401 } else if (IS_CHERRYVIEW(dev_priv)) {
1402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403 return false;
1404 } else {
1405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1413 {
1414 if ((val & LVDS_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419 return false;
1420 } else {
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 return false;
1423 }
1424 return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1429 {
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1431 return false;
1432 if (HAS_PCH_CPT(dev_priv)) {
1433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434 return false;
1435 } else {
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 return false;
1438 }
1439 return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, i915_reg_t reg,
1444 u32 port_sel)
1445 {
1446 u32 val = I915_READ(reg);
1447 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, i915_reg_t reg)
1458 {
1459 u32 val = I915_READ(reg);
1460 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471 {
1472 u32 val;
1473
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478 val = I915_READ(PCH_ADPA);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 val = I915_READ(PCH_LVDS);
1484 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *pipe_config)
1495 {
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1498
1499 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500 POSTING_READ(DPLL(pipe));
1501 udelay(150);
1502
1503 if (intel_wait_for_register(dev_priv,
1504 DPLL(pipe),
1505 DPLL_LOCK_VLV,
1506 DPLL_LOCK_VLV,
1507 1))
1508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *pipe_config)
1513 {
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 enum pipe pipe = crtc->pipe;
1516
1517 assert_pipe_disabled(dev_priv, pipe);
1518
1519 /* PLL is protected by panel, make sure we can write it */
1520 assert_panel_unlocked(dev_priv, pipe);
1521
1522 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523 _vlv_enable_pll(crtc, pipe_config);
1524
1525 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526 POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
1532 {
1533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534 enum pipe pipe = crtc->pipe;
1535 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536 u32 tmp;
1537
1538 mutex_lock(&dev_priv->sb_lock);
1539
1540 /* Enable back the 10bit clock to display controller */
1541 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542 tmp |= DPIO_DCLKP_EN;
1543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545 mutex_unlock(&dev_priv->sb_lock);
1546
1547 /*
1548 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549 */
1550 udelay(1);
1551
1552 /* Enable PLL */
1553 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555 /* Check PLL is locked */
1556 if (intel_wait_for_register(dev_priv,
1557 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558 1))
1559 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563 const struct intel_crtc_state *pipe_config)
1564 {
1565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566 enum pipe pipe = crtc->pipe;
1567
1568 assert_pipe_disabled(dev_priv, pipe);
1569
1570 /* PLL is protected by panel, make sure we can write it */
1571 assert_panel_unlocked(dev_priv, pipe);
1572
1573 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574 _chv_enable_pll(crtc, pipe_config);
1575
1576 if (pipe != PIPE_A) {
1577 /*
1578 * WaPixelRepeatModeFixForC0:chv
1579 *
1580 * DPLLCMD is AWOL. Use chicken bits to propagate
1581 * the value from DPLLBMD to either pipe B or C.
1582 */
1583 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585 I915_WRITE(CBR4_VLV, 0);
1586 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588 /*
1589 * DPLLB VGA mode also seems to cause problems.
1590 * We should always have it disabled.
1591 */
1592 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593 } else {
1594 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595 POSTING_READ(DPLL_MD(pipe));
1596 }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601 struct intel_crtc *crtc;
1602 int count = 0;
1603
1604 for_each_intel_crtc(dev, crtc) {
1605 count += crtc->base.state->active &&
1606 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607 }
1608
1609 return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = to_i915(dev);
1616 i915_reg_t reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 /* Enable DVO 2x clock on both PLLs if necessary */
1626 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627 /*
1628 * It appears to be important that we don't enable this
1629 * for the current pipe before otherwise configuring the
1630 * PLL. No idea how this should be handled if multiple
1631 * DVO outputs are enabled simultaneosly.
1632 */
1633 dpll |= DPLL_DVO_2X_MODE;
1634 I915_WRITE(DPLL(!crtc->pipe),
1635 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636 }
1637
1638 /*
1639 * Apparently we need to have VGA mode enabled prior to changing
1640 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641 * dividers, even though the register value does change.
1642 */
1643 I915_WRITE(reg, 0);
1644
1645 I915_WRITE(reg, dpll);
1646
1647 /* Wait for the clocks to stabilize. */
1648 POSTING_READ(reg);
1649 udelay(150);
1650
1651 if (INTEL_INFO(dev)->gen >= 4) {
1652 I915_WRITE(DPLL_MD(crtc->pipe),
1653 crtc->config->dpll_hw_state.dpll_md);
1654 } else {
1655 /* The pixel multiplier can only be updated once the
1656 * DPLL is enabled and the clocks are stable.
1657 *
1658 * So write it again.
1659 */
1660 I915_WRITE(reg, dpll);
1661 }
1662
1663 /* We do this three times for luck */
1664 I915_WRITE(reg, dpll);
1665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
1667 I915_WRITE(reg, dpll);
1668 POSTING_READ(reg);
1669 udelay(150); /* wait for warmup */
1670 I915_WRITE(reg, dpll);
1671 POSTING_READ(reg);
1672 udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676 * i9xx_disable_pll - disable a PLL
1677 * @dev_priv: i915 private structure
1678 * @pipe: pipe PLL to disable
1679 *
1680 * Disable the PLL for @pipe, making sure the pipe is off first.
1681 *
1682 * Note! This is for pre-ILK only.
1683 */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686 struct drm_device *dev = crtc->base.dev;
1687 struct drm_i915_private *dev_priv = to_i915(dev);
1688 enum pipe pipe = crtc->pipe;
1689
1690 /* Disable DVO 2x clock on both PLLs if necessary */
1691 if (IS_I830(dev) &&
1692 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693 !intel_num_dvo_pipes(dev)) {
1694 I915_WRITE(DPLL(PIPE_B),
1695 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696 I915_WRITE(DPLL(PIPE_A),
1697 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698 }
1699
1700 /* Don't disable pipe or pipe PLLs if needed */
1701 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703 return;
1704
1705 /* Make sure the pipe isn't still relying on us */
1706 assert_pipe_disabled(dev_priv, pipe);
1707
1708 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709 POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 u32 val;
1715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
1719 val = DPLL_INTEGRATED_REF_CLK_VLV |
1720 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731 u32 val;
1732
1733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
1735
1736 val = DPLL_SSC_REF_CLK_CHV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738 if (pipe != PIPE_A)
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
1743
1744 mutex_lock(&dev_priv->sb_lock);
1745
1746 /* Disable 10bit clock to display controller */
1747 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748 val &= ~DPIO_DCLKP_EN;
1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751 mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755 struct intel_digital_port *dport,
1756 unsigned int expected_mask)
1757 {
1758 u32 port_mask;
1759 i915_reg_t dpll_reg;
1760
1761 switch (dport->port) {
1762 case PORT_B:
1763 port_mask = DPLL_PORTB_READY_MASK;
1764 dpll_reg = DPLL(0);
1765 break;
1766 case PORT_C:
1767 port_mask = DPLL_PORTC_READY_MASK;
1768 dpll_reg = DPLL(0);
1769 expected_mask <<= 4;
1770 break;
1771 case PORT_D:
1772 port_mask = DPLL_PORTD_READY_MASK;
1773 dpll_reg = DPIO_PHY_STATUS;
1774 break;
1775 default:
1776 BUG();
1777 }
1778
1779 if (intel_wait_for_register(dev_priv,
1780 dpll_reg, port_mask, expected_mask,
1781 1000))
1782 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787 enum pipe pipe)
1788 {
1789 struct drm_device *dev = &dev_priv->drm;
1790 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792 i915_reg_t reg;
1793 uint32_t val, pipeconf_val;
1794
1795 /* Make sure PCH DPLL is enabled */
1796 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798 /* FDI must be feeding us bits for PCH ports */
1799 assert_fdi_tx_enabled(dev_priv, pipe);
1800 assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802 if (HAS_PCH_CPT(dev)) {
1803 /* Workaround: Set the timing override bit before enabling the
1804 * pch transcoder. */
1805 reg = TRANS_CHICKEN2(pipe);
1806 val = I915_READ(reg);
1807 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808 I915_WRITE(reg, val);
1809 }
1810
1811 reg = PCH_TRANSCONF(pipe);
1812 val = I915_READ(reg);
1813 pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815 if (HAS_PCH_IBX(dev_priv)) {
1816 /*
1817 * Make the BPC in transcoder be consistent with
1818 * that in pipeconf reg. For HDMI we must use 8bpc
1819 * here for both 8bpc and 12bpc.
1820 */
1821 val &= ~PIPECONF_BPC_MASK;
1822 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823 val |= PIPECONF_8BPC;
1824 else
1825 val |= pipeconf_val & PIPECONF_BPC_MASK;
1826 }
1827
1828 val &= ~TRANS_INTERLACE_MASK;
1829 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830 if (HAS_PCH_IBX(dev_priv) &&
1831 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832 val |= TRANS_LEGACY_INTERLACED_ILK;
1833 else
1834 val |= TRANS_INTERLACED;
1835 else
1836 val |= TRANS_PROGRESSIVE;
1837
1838 I915_WRITE(reg, val | TRANS_ENABLE);
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841 100))
1842 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846 enum transcoder cpu_transcoder)
1847 {
1848 u32 val, pipeconf_val;
1849
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854 /* Workaround: set timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859 val = TRANS_ENABLE;
1860 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863 PIPECONF_INTERLACED_ILK)
1864 val |= TRANS_INTERLACED;
1865 else
1866 val |= TRANS_PROGRESSIVE;
1867
1868 I915_WRITE(LPT_TRANSCONF, val);
1869 if (intel_wait_for_register(dev_priv,
1870 LPT_TRANSCONF,
1871 TRANS_STATE_ENABLE,
1872 TRANS_STATE_ENABLE,
1873 100))
1874 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum pipe pipe)
1879 {
1880 struct drm_device *dev = &dev_priv->drm;
1881 i915_reg_t reg;
1882 uint32_t val;
1883
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1890
1891 reg = PCH_TRANSCONF(pipe);
1892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
1896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1898 50))
1899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901 if (HAS_PCH_CPT(dev)) {
1902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1907 }
1908 }
1909
1910 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912 u32 val;
1913
1914 val = I915_READ(LPT_TRANSCONF);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(LPT_TRANSCONF, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920 50))
1921 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923 /* Workaround: clear timing override bit. */
1924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930 * intel_enable_pipe - enable a pipe, asserting requirements
1931 * @crtc: crtc responsible for the pipe
1932 *
1933 * Enable @crtc's pipe, making sure that various hardware specific requirements
1934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935 */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938 struct drm_device *dev = crtc->base.dev;
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 enum pipe pipe = crtc->pipe;
1941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942 enum pipe pch_transcoder;
1943 i915_reg_t reg;
1944 u32 val;
1945
1946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948 assert_planes_disabled(dev_priv, pipe);
1949 assert_cursor_disabled(dev_priv, pipe);
1950 assert_sprites_disabled(dev_priv, pipe);
1951
1952 if (HAS_PCH_LPT(dev_priv))
1953 pch_transcoder = TRANSCODER_A;
1954 else
1955 pch_transcoder = pipe;
1956
1957 /*
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1960 * need the check.
1961 */
1962 if (HAS_GMCH_DISPLAY(dev_priv))
1963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964 assert_dsi_pll_enabled(dev_priv);
1965 else
1966 assert_pll_enabled(dev_priv, pipe);
1967 else {
1968 if (crtc->config->has_pch_encoder) {
1969 /* if driving the PCH, we need FDI enabled */
1970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
1973 }
1974 /* FIXME: assert CPU port conditions for SNB+ */
1975 }
1976
1977 reg = PIPECONF(cpu_transcoder);
1978 val = I915_READ(reg);
1979 if (val & PIPECONF_ENABLE) {
1980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982 return;
1983 }
1984
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
1986 POSTING_READ(reg);
1987
1988 /*
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1994 */
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001 * intel_disable_pipe - disable a pipe, asserting requirements
2002 * @crtc: crtc whose pipes is to be disabled
2003 *
2004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
2007 *
2008 * Will wait until the pipe has shut down before returning.
2009 */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014 enum pipe pipe = crtc->pipe;
2015 i915_reg_t reg;
2016 u32 val;
2017
2018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020 /*
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2023 */
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if ((val & PIPECONF_ENABLE) == 0)
2031 return;
2032
2033 /*
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2036 */
2037 if (crtc->config->double_wide)
2038 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040 /* Don't disable pipe or pipe PLLs if needed */
2041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043 val &= ~PIPECONF_ENABLE;
2044
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
2057 {
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2060 return cpp;
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2063 return 128;
2064 else
2065 return 512;
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068 return 128;
2069 else
2070 return 512;
2071 case I915_FORMAT_MOD_Yf_TILED:
2072 switch (cpp) {
2073 case 1:
2074 return 64;
2075 case 2:
2076 case 4:
2077 return 128;
2078 case 8:
2079 case 16:
2080 return 256;
2081 default:
2082 MISSING_CASE(cpp);
2083 return cpp;
2084 }
2085 break;
2086 default:
2087 MISSING_CASE(fb_modifier);
2088 return cpp;
2089 }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
2094 {
2095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096 return 1;
2097 else
2098 return intel_tile_size(dev_priv) /
2099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2107 unsigned int cpp)
2108 {
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118 uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123 return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128 unsigned int size = 0;
2129 int i;
2130
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134 return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
2141 {
2142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145 } else {
2146 *view = i915_ggtt_view_normal;
2147 }
2148 }
2149
2150 static void
2151 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2152 struct drm_framebuffer *fb)
2153 {
2154 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2155 unsigned int tile_size, tile_width, tile_height, cpp;
2156
2157 tile_size = intel_tile_size(dev_priv);
2158
2159 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2160 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2161 fb->modifier[0], cpp);
2162
2163 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2164 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2165
2166 if (info->pixel_format == DRM_FORMAT_NV12) {
2167 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2168 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2169 fb->modifier[1], cpp);
2170
2171 info->uv_offset = fb->offsets[1];
2172 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2173 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2174 }
2175 }
2176
2177 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2178 {
2179 if (INTEL_INFO(dev_priv)->gen >= 9)
2180 return 256 * 1024;
2181 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2182 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2183 return 128 * 1024;
2184 else if (INTEL_INFO(dev_priv)->gen >= 4)
2185 return 4 * 1024;
2186 else
2187 return 0;
2188 }
2189
2190 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2191 uint64_t fb_modifier)
2192 {
2193 switch (fb_modifier) {
2194 case DRM_FORMAT_MOD_NONE:
2195 return intel_linear_alignment(dev_priv);
2196 case I915_FORMAT_MOD_X_TILED:
2197 if (INTEL_INFO(dev_priv)->gen >= 9)
2198 return 256 * 1024;
2199 return 0;
2200 case I915_FORMAT_MOD_Y_TILED:
2201 case I915_FORMAT_MOD_Yf_TILED:
2202 return 1 * 1024 * 1024;
2203 default:
2204 MISSING_CASE(fb_modifier);
2205 return 0;
2206 }
2207 }
2208
2209 int
2210 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2211 unsigned int rotation)
2212 {
2213 struct drm_device *dev = fb->dev;
2214 struct drm_i915_private *dev_priv = to_i915(dev);
2215 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2216 struct i915_ggtt_view view;
2217 u32 alignment;
2218 int ret;
2219
2220 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2221
2222 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2223
2224 intel_fill_fb_ggtt_view(&view, fb, rotation);
2225
2226 /* Note that the w/a also requires 64 PTE of padding following the
2227 * bo. We currently fill all unused PTE with the shadow page and so
2228 * we should always have valid PTE following the scanout preventing
2229 * the VT-d warning.
2230 */
2231 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2232 alignment = 256 * 1024;
2233
2234 /*
2235 * Global gtt pte registers are special registers which actually forward
2236 * writes to a chunk of system memory. Which means that there is no risk
2237 * that the register values disappear as soon as we call
2238 * intel_runtime_pm_put(), so it is correct to wrap only the
2239 * pin/unpin/fence and not more.
2240 */
2241 intel_runtime_pm_get(dev_priv);
2242
2243 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2244 &view);
2245 if (ret)
2246 goto err_pm;
2247
2248 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2249 * fence, whereas 965+ only requires a fence if using
2250 * framebuffer compression. For simplicity, we always install
2251 * a fence as the cost is not that onerous.
2252 */
2253 if (view.type == I915_GGTT_VIEW_NORMAL) {
2254 ret = i915_gem_object_get_fence(obj);
2255 if (ret == -EDEADLK) {
2256 /*
2257 * -EDEADLK means there are no free fences
2258 * no pending flips.
2259 *
2260 * This is propagated to atomic, but it uses
2261 * -EDEADLK to force a locking recovery, so
2262 * change the returned error to -EBUSY.
2263 */
2264 ret = -EBUSY;
2265 goto err_unpin;
2266 } else if (ret)
2267 goto err_unpin;
2268
2269 i915_gem_object_pin_fence(obj);
2270 }
2271
2272 intel_runtime_pm_put(dev_priv);
2273 return 0;
2274
2275 err_unpin:
2276 i915_gem_object_unpin_from_display_plane(obj, &view);
2277 err_pm:
2278 intel_runtime_pm_put(dev_priv);
2279 return ret;
2280 }
2281
2282 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2283 {
2284 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2285 struct i915_ggtt_view view;
2286
2287 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2288
2289 intel_fill_fb_ggtt_view(&view, fb, rotation);
2290
2291 if (view.type == I915_GGTT_VIEW_NORMAL)
2292 i915_gem_object_unpin_fence(obj);
2293
2294 i915_gem_object_unpin_from_display_plane(obj, &view);
2295 }
2296
2297 /*
2298 * Adjust the tile offset by moving the difference into
2299 * the x/y offsets.
2300 *
2301 * Input tile dimensions and pitch must already be
2302 * rotated to match x and y, and in pixel units.
2303 */
2304 static u32 intel_adjust_tile_offset(int *x, int *y,
2305 unsigned int tile_width,
2306 unsigned int tile_height,
2307 unsigned int tile_size,
2308 unsigned int pitch_tiles,
2309 u32 old_offset,
2310 u32 new_offset)
2311 {
2312 unsigned int tiles;
2313
2314 WARN_ON(old_offset & (tile_size - 1));
2315 WARN_ON(new_offset & (tile_size - 1));
2316 WARN_ON(new_offset > old_offset);
2317
2318 tiles = (old_offset - new_offset) / tile_size;
2319
2320 *y += tiles / pitch_tiles * tile_height;
2321 *x += tiles % pitch_tiles * tile_width;
2322
2323 return new_offset;
2324 }
2325
2326 /*
2327 * Computes the linear offset to the base tile and adjusts
2328 * x, y. bytes per pixel is assumed to be a power-of-two.
2329 *
2330 * In the 90/270 rotated case, x and y are assumed
2331 * to be already rotated to match the rotated GTT view, and
2332 * pitch is the tile_height aligned framebuffer height.
2333 */
2334 u32 intel_compute_tile_offset(int *x, int *y,
2335 const struct drm_framebuffer *fb, int plane,
2336 unsigned int pitch,
2337 unsigned int rotation)
2338 {
2339 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2340 uint64_t fb_modifier = fb->modifier[plane];
2341 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2342 u32 offset, offset_aligned, alignment;
2343
2344 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2345 if (alignment)
2346 alignment--;
2347
2348 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2349 unsigned int tile_size, tile_width, tile_height;
2350 unsigned int tile_rows, tiles, pitch_tiles;
2351
2352 tile_size = intel_tile_size(dev_priv);
2353 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2354 fb_modifier, cpp);
2355
2356 if (intel_rotation_90_or_270(rotation)) {
2357 pitch_tiles = pitch / tile_height;
2358 swap(tile_width, tile_height);
2359 } else {
2360 pitch_tiles = pitch / (tile_width * cpp);
2361 }
2362
2363 tile_rows = *y / tile_height;
2364 *y %= tile_height;
2365
2366 tiles = *x / tile_width;
2367 *x %= tile_width;
2368
2369 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2370 offset_aligned = offset & ~alignment;
2371
2372 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2373 tile_size, pitch_tiles,
2374 offset, offset_aligned);
2375 } else {
2376 offset = *y * pitch + *x * cpp;
2377 offset_aligned = offset & ~alignment;
2378
2379 *y = (offset & alignment) / pitch;
2380 *x = ((offset & alignment) - *y * pitch) / cpp;
2381 }
2382
2383 return offset_aligned;
2384 }
2385
2386 static int i9xx_format_to_fourcc(int format)
2387 {
2388 switch (format) {
2389 case DISPPLANE_8BPP:
2390 return DRM_FORMAT_C8;
2391 case DISPPLANE_BGRX555:
2392 return DRM_FORMAT_XRGB1555;
2393 case DISPPLANE_BGRX565:
2394 return DRM_FORMAT_RGB565;
2395 default:
2396 case DISPPLANE_BGRX888:
2397 return DRM_FORMAT_XRGB8888;
2398 case DISPPLANE_RGBX888:
2399 return DRM_FORMAT_XBGR8888;
2400 case DISPPLANE_BGRX101010:
2401 return DRM_FORMAT_XRGB2101010;
2402 case DISPPLANE_RGBX101010:
2403 return DRM_FORMAT_XBGR2101010;
2404 }
2405 }
2406
2407 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2408 {
2409 switch (format) {
2410 case PLANE_CTL_FORMAT_RGB_565:
2411 return DRM_FORMAT_RGB565;
2412 default:
2413 case PLANE_CTL_FORMAT_XRGB_8888:
2414 if (rgb_order) {
2415 if (alpha)
2416 return DRM_FORMAT_ABGR8888;
2417 else
2418 return DRM_FORMAT_XBGR8888;
2419 } else {
2420 if (alpha)
2421 return DRM_FORMAT_ARGB8888;
2422 else
2423 return DRM_FORMAT_XRGB8888;
2424 }
2425 case PLANE_CTL_FORMAT_XRGB_2101010:
2426 if (rgb_order)
2427 return DRM_FORMAT_XBGR2101010;
2428 else
2429 return DRM_FORMAT_XRGB2101010;
2430 }
2431 }
2432
2433 static bool
2434 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2435 struct intel_initial_plane_config *plane_config)
2436 {
2437 struct drm_device *dev = crtc->base.dev;
2438 struct drm_i915_private *dev_priv = to_i915(dev);
2439 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2440 struct drm_i915_gem_object *obj = NULL;
2441 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2442 struct drm_framebuffer *fb = &plane_config->fb->base;
2443 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2444 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2445 PAGE_SIZE);
2446
2447 size_aligned -= base_aligned;
2448
2449 if (plane_config->size == 0)
2450 return false;
2451
2452 /* If the FB is too big, just don't use it since fbdev is not very
2453 * important and we should probably use that space with FBC or other
2454 * features. */
2455 if (size_aligned * 2 > ggtt->stolen_usable_size)
2456 return false;
2457
2458 mutex_lock(&dev->struct_mutex);
2459
2460 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2461 base_aligned,
2462 base_aligned,
2463 size_aligned);
2464 if (!obj) {
2465 mutex_unlock(&dev->struct_mutex);
2466 return false;
2467 }
2468
2469 obj->tiling_mode = plane_config->tiling;
2470 if (obj->tiling_mode == I915_TILING_X)
2471 obj->stride = fb->pitches[0];
2472
2473 mode_cmd.pixel_format = fb->pixel_format;
2474 mode_cmd.width = fb->width;
2475 mode_cmd.height = fb->height;
2476 mode_cmd.pitches[0] = fb->pitches[0];
2477 mode_cmd.modifier[0] = fb->modifier[0];
2478 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2479
2480 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2481 &mode_cmd, obj)) {
2482 DRM_DEBUG_KMS("intel fb init failed\n");
2483 goto out_unref_obj;
2484 }
2485
2486 mutex_unlock(&dev->struct_mutex);
2487
2488 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2489 return true;
2490
2491 out_unref_obj:
2492 i915_gem_object_put(obj);
2493 mutex_unlock(&dev->struct_mutex);
2494 return false;
2495 }
2496
2497 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2498 static void
2499 update_state_fb(struct drm_plane *plane)
2500 {
2501 if (plane->fb == plane->state->fb)
2502 return;
2503
2504 if (plane->state->fb)
2505 drm_framebuffer_unreference(plane->state->fb);
2506 plane->state->fb = plane->fb;
2507 if (plane->state->fb)
2508 drm_framebuffer_reference(plane->state->fb);
2509 }
2510
2511 static void
2512 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2513 struct intel_initial_plane_config *plane_config)
2514 {
2515 struct drm_device *dev = intel_crtc->base.dev;
2516 struct drm_i915_private *dev_priv = to_i915(dev);
2517 struct drm_crtc *c;
2518 struct intel_crtc *i;
2519 struct drm_i915_gem_object *obj;
2520 struct drm_plane *primary = intel_crtc->base.primary;
2521 struct drm_plane_state *plane_state = primary->state;
2522 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2523 struct intel_plane *intel_plane = to_intel_plane(primary);
2524 struct intel_plane_state *intel_state =
2525 to_intel_plane_state(plane_state);
2526 struct drm_framebuffer *fb;
2527
2528 if (!plane_config->fb)
2529 return;
2530
2531 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2532 fb = &plane_config->fb->base;
2533 goto valid_fb;
2534 }
2535
2536 kfree(plane_config->fb);
2537
2538 /*
2539 * Failed to alloc the obj, check to see if we should share
2540 * an fb with another CRTC instead
2541 */
2542 for_each_crtc(dev, c) {
2543 i = to_intel_crtc(c);
2544
2545 if (c == &intel_crtc->base)
2546 continue;
2547
2548 if (!i->active)
2549 continue;
2550
2551 fb = c->primary->fb;
2552 if (!fb)
2553 continue;
2554
2555 obj = intel_fb_obj(fb);
2556 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2557 drm_framebuffer_reference(fb);
2558 goto valid_fb;
2559 }
2560 }
2561
2562 /*
2563 * We've failed to reconstruct the BIOS FB. Current display state
2564 * indicates that the primary plane is visible, but has a NULL FB,
2565 * which will lead to problems later if we don't fix it up. The
2566 * simplest solution is to just disable the primary plane now and
2567 * pretend the BIOS never had it enabled.
2568 */
2569 to_intel_plane_state(plane_state)->visible = false;
2570 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2571 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2572 intel_plane->disable_plane(primary, &intel_crtc->base);
2573
2574 return;
2575
2576 valid_fb:
2577 plane_state->src_x = 0;
2578 plane_state->src_y = 0;
2579 plane_state->src_w = fb->width << 16;
2580 plane_state->src_h = fb->height << 16;
2581
2582 plane_state->crtc_x = 0;
2583 plane_state->crtc_y = 0;
2584 plane_state->crtc_w = fb->width;
2585 plane_state->crtc_h = fb->height;
2586
2587 intel_state->src.x1 = plane_state->src_x;
2588 intel_state->src.y1 = plane_state->src_y;
2589 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2590 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2591 intel_state->dst.x1 = plane_state->crtc_x;
2592 intel_state->dst.y1 = plane_state->crtc_y;
2593 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2594 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2595
2596 obj = intel_fb_obj(fb);
2597 if (obj->tiling_mode != I915_TILING_NONE)
2598 dev_priv->preserve_bios_swizzle = true;
2599
2600 drm_framebuffer_reference(fb);
2601 primary->fb = primary->state->fb = fb;
2602 primary->crtc = primary->state->crtc = &intel_crtc->base;
2603 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2604 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2605 }
2606
2607 static void i9xx_update_primary_plane(struct drm_plane *primary,
2608 const struct intel_crtc_state *crtc_state,
2609 const struct intel_plane_state *plane_state)
2610 {
2611 struct drm_device *dev = primary->dev;
2612 struct drm_i915_private *dev_priv = to_i915(dev);
2613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2614 struct drm_framebuffer *fb = plane_state->base.fb;
2615 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2616 int plane = intel_crtc->plane;
2617 u32 linear_offset;
2618 u32 dspcntr;
2619 i915_reg_t reg = DSPCNTR(plane);
2620 unsigned int rotation = plane_state->base.rotation;
2621 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2622 int x = plane_state->src.x1 >> 16;
2623 int y = plane_state->src.y1 >> 16;
2624
2625 dspcntr = DISPPLANE_GAMMA_ENABLE;
2626
2627 dspcntr |= DISPLAY_PLANE_ENABLE;
2628
2629 if (INTEL_INFO(dev)->gen < 4) {
2630 if (intel_crtc->pipe == PIPE_B)
2631 dspcntr |= DISPPLANE_SEL_PIPE_B;
2632
2633 /* pipesrc and dspsize control the size that is scaled from,
2634 * which should always be the user's requested size.
2635 */
2636 I915_WRITE(DSPSIZE(plane),
2637 ((crtc_state->pipe_src_h - 1) << 16) |
2638 (crtc_state->pipe_src_w - 1));
2639 I915_WRITE(DSPPOS(plane), 0);
2640 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2641 I915_WRITE(PRIMSIZE(plane),
2642 ((crtc_state->pipe_src_h - 1) << 16) |
2643 (crtc_state->pipe_src_w - 1));
2644 I915_WRITE(PRIMPOS(plane), 0);
2645 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2646 }
2647
2648 switch (fb->pixel_format) {
2649 case DRM_FORMAT_C8:
2650 dspcntr |= DISPPLANE_8BPP;
2651 break;
2652 case DRM_FORMAT_XRGB1555:
2653 dspcntr |= DISPPLANE_BGRX555;
2654 break;
2655 case DRM_FORMAT_RGB565:
2656 dspcntr |= DISPPLANE_BGRX565;
2657 break;
2658 case DRM_FORMAT_XRGB8888:
2659 dspcntr |= DISPPLANE_BGRX888;
2660 break;
2661 case DRM_FORMAT_XBGR8888:
2662 dspcntr |= DISPPLANE_RGBX888;
2663 break;
2664 case DRM_FORMAT_XRGB2101010:
2665 dspcntr |= DISPPLANE_BGRX101010;
2666 break;
2667 case DRM_FORMAT_XBGR2101010:
2668 dspcntr |= DISPPLANE_RGBX101010;
2669 break;
2670 default:
2671 BUG();
2672 }
2673
2674 if (INTEL_INFO(dev)->gen >= 4 &&
2675 obj->tiling_mode != I915_TILING_NONE)
2676 dspcntr |= DISPPLANE_TILED;
2677
2678 if (IS_G4X(dev))
2679 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2680
2681 linear_offset = y * fb->pitches[0] + x * cpp;
2682
2683 if (INTEL_INFO(dev)->gen >= 4) {
2684 intel_crtc->dspaddr_offset =
2685 intel_compute_tile_offset(&x, &y, fb, 0,
2686 fb->pitches[0], rotation);
2687 linear_offset -= intel_crtc->dspaddr_offset;
2688 } else {
2689 intel_crtc->dspaddr_offset = linear_offset;
2690 }
2691
2692 if (rotation == BIT(DRM_ROTATE_180)) {
2693 dspcntr |= DISPPLANE_ROTATE_180;
2694
2695 x += (crtc_state->pipe_src_w - 1);
2696 y += (crtc_state->pipe_src_h - 1);
2697
2698 /* Finding the last pixel of the last line of the display
2699 data and adding to linear_offset*/
2700 linear_offset +=
2701 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2702 (crtc_state->pipe_src_w - 1) * cpp;
2703 }
2704
2705 intel_crtc->adjusted_x = x;
2706 intel_crtc->adjusted_y = y;
2707
2708 I915_WRITE(reg, dspcntr);
2709
2710 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2711 if (INTEL_INFO(dev)->gen >= 4) {
2712 I915_WRITE(DSPSURF(plane),
2713 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2714 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2715 I915_WRITE(DSPLINOFF(plane), linear_offset);
2716 } else
2717 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2718 POSTING_READ(reg);
2719 }
2720
2721 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2722 struct drm_crtc *crtc)
2723 {
2724 struct drm_device *dev = crtc->dev;
2725 struct drm_i915_private *dev_priv = to_i915(dev);
2726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2727 int plane = intel_crtc->plane;
2728
2729 I915_WRITE(DSPCNTR(plane), 0);
2730 if (INTEL_INFO(dev_priv)->gen >= 4)
2731 I915_WRITE(DSPSURF(plane), 0);
2732 else
2733 I915_WRITE(DSPADDR(plane), 0);
2734 POSTING_READ(DSPCNTR(plane));
2735 }
2736
2737 static void ironlake_update_primary_plane(struct drm_plane *primary,
2738 const struct intel_crtc_state *crtc_state,
2739 const struct intel_plane_state *plane_state)
2740 {
2741 struct drm_device *dev = primary->dev;
2742 struct drm_i915_private *dev_priv = to_i915(dev);
2743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2744 struct drm_framebuffer *fb = plane_state->base.fb;
2745 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2746 int plane = intel_crtc->plane;
2747 u32 linear_offset;
2748 u32 dspcntr;
2749 i915_reg_t reg = DSPCNTR(plane);
2750 unsigned int rotation = plane_state->base.rotation;
2751 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2752 int x = plane_state->src.x1 >> 16;
2753 int y = plane_state->src.y1 >> 16;
2754
2755 dspcntr = DISPPLANE_GAMMA_ENABLE;
2756 dspcntr |= DISPLAY_PLANE_ENABLE;
2757
2758 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2759 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2760
2761 switch (fb->pixel_format) {
2762 case DRM_FORMAT_C8:
2763 dspcntr |= DISPPLANE_8BPP;
2764 break;
2765 case DRM_FORMAT_RGB565:
2766 dspcntr |= DISPPLANE_BGRX565;
2767 break;
2768 case DRM_FORMAT_XRGB8888:
2769 dspcntr |= DISPPLANE_BGRX888;
2770 break;
2771 case DRM_FORMAT_XBGR8888:
2772 dspcntr |= DISPPLANE_RGBX888;
2773 break;
2774 case DRM_FORMAT_XRGB2101010:
2775 dspcntr |= DISPPLANE_BGRX101010;
2776 break;
2777 case DRM_FORMAT_XBGR2101010:
2778 dspcntr |= DISPPLANE_RGBX101010;
2779 break;
2780 default:
2781 BUG();
2782 }
2783
2784 if (obj->tiling_mode != I915_TILING_NONE)
2785 dspcntr |= DISPPLANE_TILED;
2786
2787 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2788 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2789
2790 linear_offset = y * fb->pitches[0] + x * cpp;
2791 intel_crtc->dspaddr_offset =
2792 intel_compute_tile_offset(&x, &y, fb, 0,
2793 fb->pitches[0], rotation);
2794 linear_offset -= intel_crtc->dspaddr_offset;
2795 if (rotation == BIT(DRM_ROTATE_180)) {
2796 dspcntr |= DISPPLANE_ROTATE_180;
2797
2798 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2799 x += (crtc_state->pipe_src_w - 1);
2800 y += (crtc_state->pipe_src_h - 1);
2801
2802 /* Finding the last pixel of the last line of the display
2803 data and adding to linear_offset*/
2804 linear_offset +=
2805 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2806 (crtc_state->pipe_src_w - 1) * cpp;
2807 }
2808 }
2809
2810 intel_crtc->adjusted_x = x;
2811 intel_crtc->adjusted_y = y;
2812
2813 I915_WRITE(reg, dspcntr);
2814
2815 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2816 I915_WRITE(DSPSURF(plane),
2817 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2819 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2820 } else {
2821 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2822 I915_WRITE(DSPLINOFF(plane), linear_offset);
2823 }
2824 POSTING_READ(reg);
2825 }
2826
2827 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2828 uint64_t fb_modifier, uint32_t pixel_format)
2829 {
2830 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2831 return 64;
2832 } else {
2833 int cpp = drm_format_plane_cpp(pixel_format, 0);
2834
2835 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2836 }
2837 }
2838
2839 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2840 struct drm_i915_gem_object *obj,
2841 unsigned int plane)
2842 {
2843 struct i915_ggtt_view view;
2844 struct i915_vma *vma;
2845 u64 offset;
2846
2847 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2848 intel_plane->base.state->rotation);
2849
2850 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2851 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2852 view.type))
2853 return -1;
2854
2855 offset = vma->node.start;
2856
2857 if (plane == 1) {
2858 offset += vma->ggtt_view.params.rotated.uv_start_page *
2859 PAGE_SIZE;
2860 }
2861
2862 WARN_ON(upper_32_bits(offset));
2863
2864 return lower_32_bits(offset);
2865 }
2866
2867 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2868 {
2869 struct drm_device *dev = intel_crtc->base.dev;
2870 struct drm_i915_private *dev_priv = to_i915(dev);
2871
2872 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2873 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2874 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2875 }
2876
2877 /*
2878 * This function detaches (aka. unbinds) unused scalers in hardware
2879 */
2880 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2881 {
2882 struct intel_crtc_scaler_state *scaler_state;
2883 int i;
2884
2885 scaler_state = &intel_crtc->config->scaler_state;
2886
2887 /* loop through and disable scalers that aren't in use */
2888 for (i = 0; i < intel_crtc->num_scalers; i++) {
2889 if (!scaler_state->scalers[i].in_use)
2890 skl_detach_scaler(intel_crtc, i);
2891 }
2892 }
2893
2894 u32 skl_plane_ctl_format(uint32_t pixel_format)
2895 {
2896 switch (pixel_format) {
2897 case DRM_FORMAT_C8:
2898 return PLANE_CTL_FORMAT_INDEXED;
2899 case DRM_FORMAT_RGB565:
2900 return PLANE_CTL_FORMAT_RGB_565;
2901 case DRM_FORMAT_XBGR8888:
2902 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2903 case DRM_FORMAT_XRGB8888:
2904 return PLANE_CTL_FORMAT_XRGB_8888;
2905 /*
2906 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2907 * to be already pre-multiplied. We need to add a knob (or a different
2908 * DRM_FORMAT) for user-space to configure that.
2909 */
2910 case DRM_FORMAT_ABGR8888:
2911 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2912 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2913 case DRM_FORMAT_ARGB8888:
2914 return PLANE_CTL_FORMAT_XRGB_8888 |
2915 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2916 case DRM_FORMAT_XRGB2101010:
2917 return PLANE_CTL_FORMAT_XRGB_2101010;
2918 case DRM_FORMAT_XBGR2101010:
2919 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2920 case DRM_FORMAT_YUYV:
2921 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2922 case DRM_FORMAT_YVYU:
2923 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2924 case DRM_FORMAT_UYVY:
2925 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2926 case DRM_FORMAT_VYUY:
2927 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2928 default:
2929 MISSING_CASE(pixel_format);
2930 }
2931
2932 return 0;
2933 }
2934
2935 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2936 {
2937 switch (fb_modifier) {
2938 case DRM_FORMAT_MOD_NONE:
2939 break;
2940 case I915_FORMAT_MOD_X_TILED:
2941 return PLANE_CTL_TILED_X;
2942 case I915_FORMAT_MOD_Y_TILED:
2943 return PLANE_CTL_TILED_Y;
2944 case I915_FORMAT_MOD_Yf_TILED:
2945 return PLANE_CTL_TILED_YF;
2946 default:
2947 MISSING_CASE(fb_modifier);
2948 }
2949
2950 return 0;
2951 }
2952
2953 u32 skl_plane_ctl_rotation(unsigned int rotation)
2954 {
2955 switch (rotation) {
2956 case BIT(DRM_ROTATE_0):
2957 break;
2958 /*
2959 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2960 * while i915 HW rotation is clockwise, thats why this swapping.
2961 */
2962 case BIT(DRM_ROTATE_90):
2963 return PLANE_CTL_ROTATE_270;
2964 case BIT(DRM_ROTATE_180):
2965 return PLANE_CTL_ROTATE_180;
2966 case BIT(DRM_ROTATE_270):
2967 return PLANE_CTL_ROTATE_90;
2968 default:
2969 MISSING_CASE(rotation);
2970 }
2971
2972 return 0;
2973 }
2974
2975 static void skylake_update_primary_plane(struct drm_plane *plane,
2976 const struct intel_crtc_state *crtc_state,
2977 const struct intel_plane_state *plane_state)
2978 {
2979 struct drm_device *dev = plane->dev;
2980 struct drm_i915_private *dev_priv = to_i915(dev);
2981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2982 struct drm_framebuffer *fb = plane_state->base.fb;
2983 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2984 int pipe = intel_crtc->pipe;
2985 u32 plane_ctl, stride_div, stride;
2986 u32 tile_height, plane_offset, plane_size;
2987 unsigned int rotation = plane_state->base.rotation;
2988 int x_offset, y_offset;
2989 u32 surf_addr;
2990 int scaler_id = plane_state->scaler_id;
2991 int src_x = plane_state->src.x1 >> 16;
2992 int src_y = plane_state->src.y1 >> 16;
2993 int src_w = drm_rect_width(&plane_state->src) >> 16;
2994 int src_h = drm_rect_height(&plane_state->src) >> 16;
2995 int dst_x = plane_state->dst.x1;
2996 int dst_y = plane_state->dst.y1;
2997 int dst_w = drm_rect_width(&plane_state->dst);
2998 int dst_h = drm_rect_height(&plane_state->dst);
2999
3000 plane_ctl = PLANE_CTL_ENABLE |
3001 PLANE_CTL_PIPE_GAMMA_ENABLE |
3002 PLANE_CTL_PIPE_CSC_ENABLE;
3003
3004 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3005 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3006 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3007 plane_ctl |= skl_plane_ctl_rotation(rotation);
3008
3009 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3010 fb->pixel_format);
3011 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3012
3013 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3014
3015 if (intel_rotation_90_or_270(rotation)) {
3016 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3017
3018 /* stride = Surface height in tiles */
3019 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3020 stride = DIV_ROUND_UP(fb->height, tile_height);
3021 x_offset = stride * tile_height - src_y - src_h;
3022 y_offset = src_x;
3023 plane_size = (src_w - 1) << 16 | (src_h - 1);
3024 } else {
3025 stride = fb->pitches[0] / stride_div;
3026 x_offset = src_x;
3027 y_offset = src_y;
3028 plane_size = (src_h - 1) << 16 | (src_w - 1);
3029 }
3030 plane_offset = y_offset << 16 | x_offset;
3031
3032 intel_crtc->adjusted_x = x_offset;
3033 intel_crtc->adjusted_y = y_offset;
3034
3035 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3036 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3037 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3038 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3039
3040 if (scaler_id >= 0) {
3041 uint32_t ps_ctrl = 0;
3042
3043 WARN_ON(!dst_w || !dst_h);
3044 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3045 crtc_state->scaler_state.scalers[scaler_id].mode;
3046 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3047 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3048 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3049 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3050 I915_WRITE(PLANE_POS(pipe, 0), 0);
3051 } else {
3052 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3053 }
3054
3055 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3056
3057 POSTING_READ(PLANE_SURF(pipe, 0));
3058 }
3059
3060 static void skylake_disable_primary_plane(struct drm_plane *primary,
3061 struct drm_crtc *crtc)
3062 {
3063 struct drm_device *dev = crtc->dev;
3064 struct drm_i915_private *dev_priv = to_i915(dev);
3065 int pipe = to_intel_crtc(crtc)->pipe;
3066
3067 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3068 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3069 POSTING_READ(PLANE_SURF(pipe, 0));
3070 }
3071
3072 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3073 static int
3074 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3075 int x, int y, enum mode_set_atomic state)
3076 {
3077 /* Support for kgdboc is disabled, this needs a major rework. */
3078 DRM_ERROR("legacy panic handler not supported any more.\n");
3079
3080 return -ENODEV;
3081 }
3082
3083 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3084 {
3085 struct intel_crtc *crtc;
3086
3087 for_each_intel_crtc(&dev_priv->drm, crtc)
3088 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3089 }
3090
3091 static void intel_update_primary_planes(struct drm_device *dev)
3092 {
3093 struct drm_crtc *crtc;
3094
3095 for_each_crtc(dev, crtc) {
3096 struct intel_plane *plane = to_intel_plane(crtc->primary);
3097 struct intel_plane_state *plane_state;
3098
3099 drm_modeset_lock_crtc(crtc, &plane->base);
3100 plane_state = to_intel_plane_state(plane->base.state);
3101
3102 if (plane_state->visible)
3103 plane->update_plane(&plane->base,
3104 to_intel_crtc_state(crtc->state),
3105 plane_state);
3106
3107 drm_modeset_unlock_crtc(crtc);
3108 }
3109 }
3110
3111 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3112 {
3113 /* no reset support for gen2 */
3114 if (IS_GEN2(dev_priv))
3115 return;
3116
3117 /* reset doesn't touch the display */
3118 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3119 return;
3120
3121 drm_modeset_lock_all(&dev_priv->drm);
3122 /*
3123 * Disabling the crtcs gracefully seems nicer. Also the
3124 * g33 docs say we should at least disable all the planes.
3125 */
3126 intel_display_suspend(&dev_priv->drm);
3127 }
3128
3129 void intel_finish_reset(struct drm_i915_private *dev_priv)
3130 {
3131 /*
3132 * Flips in the rings will be nuked by the reset,
3133 * so complete all pending flips so that user space
3134 * will get its events and not get stuck.
3135 */
3136 intel_complete_page_flips(dev_priv);
3137
3138 /* no reset support for gen2 */
3139 if (IS_GEN2(dev_priv))
3140 return;
3141
3142 /* reset doesn't touch the display */
3143 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3144 /*
3145 * Flips in the rings have been nuked by the reset,
3146 * so update the base address of all primary
3147 * planes to the the last fb to make sure we're
3148 * showing the correct fb after a reset.
3149 *
3150 * FIXME: Atomic will make this obsolete since we won't schedule
3151 * CS-based flips (which might get lost in gpu resets) any more.
3152 */
3153 intel_update_primary_planes(&dev_priv->drm);
3154 return;
3155 }
3156
3157 /*
3158 * The display has been reset as well,
3159 * so need a full re-initialization.
3160 */
3161 intel_runtime_pm_disable_interrupts(dev_priv);
3162 intel_runtime_pm_enable_interrupts(dev_priv);
3163
3164 intel_modeset_init_hw(&dev_priv->drm);
3165
3166 spin_lock_irq(&dev_priv->irq_lock);
3167 if (dev_priv->display.hpd_irq_setup)
3168 dev_priv->display.hpd_irq_setup(dev_priv);
3169 spin_unlock_irq(&dev_priv->irq_lock);
3170
3171 intel_display_resume(&dev_priv->drm);
3172
3173 intel_hpd_init(dev_priv);
3174
3175 drm_modeset_unlock_all(&dev_priv->drm);
3176 }
3177
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180 struct drm_device *dev = crtc->dev;
3181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182 unsigned reset_counter;
3183 bool pending;
3184
3185 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3186 if (intel_crtc->reset_counter != reset_counter)
3187 return false;
3188
3189 spin_lock_irq(&dev->event_lock);
3190 pending = to_intel_crtc(crtc)->flip_work != NULL;
3191 spin_unlock_irq(&dev->event_lock);
3192
3193 return pending;
3194 }
3195
3196 static void intel_update_pipe_config(struct intel_crtc *crtc,
3197 struct intel_crtc_state *old_crtc_state)
3198 {
3199 struct drm_device *dev = crtc->base.dev;
3200 struct drm_i915_private *dev_priv = to_i915(dev);
3201 struct intel_crtc_state *pipe_config =
3202 to_intel_crtc_state(crtc->base.state);
3203
3204 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3205 crtc->base.mode = crtc->base.state->mode;
3206
3207 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3208 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3209 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3210
3211 /*
3212 * Update pipe size and adjust fitter if needed: the reason for this is
3213 * that in compute_mode_changes we check the native mode (not the pfit
3214 * mode) to see if we can flip rather than do a full mode set. In the
3215 * fastboot case, we'll flip, but if we don't update the pipesrc and
3216 * pfit state, we'll end up with a big fb scanned out into the wrong
3217 * sized surface.
3218 */
3219
3220 I915_WRITE(PIPESRC(crtc->pipe),
3221 ((pipe_config->pipe_src_w - 1) << 16) |
3222 (pipe_config->pipe_src_h - 1));
3223
3224 /* on skylake this is done by detaching scalers */
3225 if (INTEL_INFO(dev)->gen >= 9) {
3226 skl_detach_scalers(crtc);
3227
3228 if (pipe_config->pch_pfit.enabled)
3229 skylake_pfit_enable(crtc);
3230 } else if (HAS_PCH_SPLIT(dev)) {
3231 if (pipe_config->pch_pfit.enabled)
3232 ironlake_pfit_enable(crtc);
3233 else if (old_crtc_state->pch_pfit.enabled)
3234 ironlake_pfit_disable(crtc, true);
3235 }
3236 }
3237
3238 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3239 {
3240 struct drm_device *dev = crtc->dev;
3241 struct drm_i915_private *dev_priv = to_i915(dev);
3242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243 int pipe = intel_crtc->pipe;
3244 i915_reg_t reg;
3245 u32 temp;
3246
3247 /* enable normal train */
3248 reg = FDI_TX_CTL(pipe);
3249 temp = I915_READ(reg);
3250 if (IS_IVYBRIDGE(dev)) {
3251 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3252 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3253 } else {
3254 temp &= ~FDI_LINK_TRAIN_NONE;
3255 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3256 }
3257 I915_WRITE(reg, temp);
3258
3259 reg = FDI_RX_CTL(pipe);
3260 temp = I915_READ(reg);
3261 if (HAS_PCH_CPT(dev)) {
3262 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3263 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3264 } else {
3265 temp &= ~FDI_LINK_TRAIN_NONE;
3266 temp |= FDI_LINK_TRAIN_NONE;
3267 }
3268 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3269
3270 /* wait one idle pattern time */
3271 POSTING_READ(reg);
3272 udelay(1000);
3273
3274 /* IVB wants error correction enabled */
3275 if (IS_IVYBRIDGE(dev))
3276 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3277 FDI_FE_ERRC_ENABLE);
3278 }
3279
3280 /* The FDI link training functions for ILK/Ibexpeak. */
3281 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3282 {
3283 struct drm_device *dev = crtc->dev;
3284 struct drm_i915_private *dev_priv = to_i915(dev);
3285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286 int pipe = intel_crtc->pipe;
3287 i915_reg_t reg;
3288 u32 temp, tries;
3289
3290 /* FDI needs bits from pipe first */
3291 assert_pipe_enabled(dev_priv, pipe);
3292
3293 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3294 for train result */
3295 reg = FDI_RX_IMR(pipe);
3296 temp = I915_READ(reg);
3297 temp &= ~FDI_RX_SYMBOL_LOCK;
3298 temp &= ~FDI_RX_BIT_LOCK;
3299 I915_WRITE(reg, temp);
3300 I915_READ(reg);
3301 udelay(150);
3302
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg = FDI_TX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_PATTERN_1;
3310 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3311
3312 reg = FDI_RX_CTL(pipe);
3313 temp = I915_READ(reg);
3314 temp &= ~FDI_LINK_TRAIN_NONE;
3315 temp |= FDI_LINK_TRAIN_PATTERN_1;
3316 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3317
3318 POSTING_READ(reg);
3319 udelay(150);
3320
3321 /* Ironlake workaround, enable clock pointer after FDI enable*/
3322 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3323 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3324 FDI_RX_PHASE_SYNC_POINTER_EN);
3325
3326 reg = FDI_RX_IIR(pipe);
3327 for (tries = 0; tries < 5; tries++) {
3328 temp = I915_READ(reg);
3329 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330
3331 if ((temp & FDI_RX_BIT_LOCK)) {
3332 DRM_DEBUG_KMS("FDI train 1 done.\n");
3333 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334 break;
3335 }
3336 }
3337 if (tries == 5)
3338 DRM_ERROR("FDI train 1 fail!\n");
3339
3340 /* Train 2 */
3341 reg = FDI_TX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 temp &= ~FDI_LINK_TRAIN_NONE;
3344 temp |= FDI_LINK_TRAIN_PATTERN_2;
3345 I915_WRITE(reg, temp);
3346
3347 reg = FDI_RX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp &= ~FDI_LINK_TRAIN_NONE;
3350 temp |= FDI_LINK_TRAIN_PATTERN_2;
3351 I915_WRITE(reg, temp);
3352
3353 POSTING_READ(reg);
3354 udelay(150);
3355
3356 reg = FDI_RX_IIR(pipe);
3357 for (tries = 0; tries < 5; tries++) {
3358 temp = I915_READ(reg);
3359 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3360
3361 if (temp & FDI_RX_SYMBOL_LOCK) {
3362 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3363 DRM_DEBUG_KMS("FDI train 2 done.\n");
3364 break;
3365 }
3366 }
3367 if (tries == 5)
3368 DRM_ERROR("FDI train 2 fail!\n");
3369
3370 DRM_DEBUG_KMS("FDI train done\n");
3371
3372 }
3373
3374 static const int snb_b_fdi_train_param[] = {
3375 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3376 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3377 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3378 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3379 };
3380
3381 /* The FDI link training functions for SNB/Cougarpoint. */
3382 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3383 {
3384 struct drm_device *dev = crtc->dev;
3385 struct drm_i915_private *dev_priv = to_i915(dev);
3386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3387 int pipe = intel_crtc->pipe;
3388 i915_reg_t reg;
3389 u32 temp, i, retry;
3390
3391 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3392 for train result */
3393 reg = FDI_RX_IMR(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~FDI_RX_SYMBOL_LOCK;
3396 temp &= ~FDI_RX_BIT_LOCK;
3397 I915_WRITE(reg, temp);
3398
3399 POSTING_READ(reg);
3400 udelay(150);
3401
3402 /* enable CPU FDI TX and PCH FDI RX */
3403 reg = FDI_TX_CTL(pipe);
3404 temp = I915_READ(reg);
3405 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3406 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3407 temp &= ~FDI_LINK_TRAIN_NONE;
3408 temp |= FDI_LINK_TRAIN_PATTERN_1;
3409 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3410 /* SNB-B */
3411 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3412 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3413
3414 I915_WRITE(FDI_RX_MISC(pipe),
3415 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3416
3417 reg = FDI_RX_CTL(pipe);
3418 temp = I915_READ(reg);
3419 if (HAS_PCH_CPT(dev)) {
3420 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3422 } else {
3423 temp &= ~FDI_LINK_TRAIN_NONE;
3424 temp |= FDI_LINK_TRAIN_PATTERN_1;
3425 }
3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
3429 udelay(150);
3430
3431 for (i = 0; i < 4; i++) {
3432 reg = FDI_TX_CTL(pipe);
3433 temp = I915_READ(reg);
3434 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3435 temp |= snb_b_fdi_train_param[i];
3436 I915_WRITE(reg, temp);
3437
3438 POSTING_READ(reg);
3439 udelay(500);
3440
3441 for (retry = 0; retry < 5; retry++) {
3442 reg = FDI_RX_IIR(pipe);
3443 temp = I915_READ(reg);
3444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3445 if (temp & FDI_RX_BIT_LOCK) {
3446 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3447 DRM_DEBUG_KMS("FDI train 1 done.\n");
3448 break;
3449 }
3450 udelay(50);
3451 }
3452 if (retry < 5)
3453 break;
3454 }
3455 if (i == 4)
3456 DRM_ERROR("FDI train 1 fail!\n");
3457
3458 /* Train 2 */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 temp &= ~FDI_LINK_TRAIN_NONE;
3462 temp |= FDI_LINK_TRAIN_PATTERN_2;
3463 if (IS_GEN6(dev)) {
3464 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3465 /* SNB-B */
3466 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3467 }
3468 I915_WRITE(reg, temp);
3469
3470 reg = FDI_RX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 if (HAS_PCH_CPT(dev)) {
3473 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3475 } else {
3476 temp &= ~FDI_LINK_TRAIN_NONE;
3477 temp |= FDI_LINK_TRAIN_PATTERN_2;
3478 }
3479 I915_WRITE(reg, temp);
3480
3481 POSTING_READ(reg);
3482 udelay(150);
3483
3484 for (i = 0; i < 4; i++) {
3485 reg = FDI_TX_CTL(pipe);
3486 temp = I915_READ(reg);
3487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3488 temp |= snb_b_fdi_train_param[i];
3489 I915_WRITE(reg, temp);
3490
3491 POSTING_READ(reg);
3492 udelay(500);
3493
3494 for (retry = 0; retry < 5; retry++) {
3495 reg = FDI_RX_IIR(pipe);
3496 temp = I915_READ(reg);
3497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3498 if (temp & FDI_RX_SYMBOL_LOCK) {
3499 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3500 DRM_DEBUG_KMS("FDI train 2 done.\n");
3501 break;
3502 }
3503 udelay(50);
3504 }
3505 if (retry < 5)
3506 break;
3507 }
3508 if (i == 4)
3509 DRM_ERROR("FDI train 2 fail!\n");
3510
3511 DRM_DEBUG_KMS("FDI train done.\n");
3512 }
3513
3514 /* Manual link training for Ivy Bridge A0 parts */
3515 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3516 {
3517 struct drm_device *dev = crtc->dev;
3518 struct drm_i915_private *dev_priv = to_i915(dev);
3519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3520 int pipe = intel_crtc->pipe;
3521 i915_reg_t reg;
3522 u32 temp, i, j;
3523
3524 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3525 for train result */
3526 reg = FDI_RX_IMR(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~FDI_RX_SYMBOL_LOCK;
3529 temp &= ~FDI_RX_BIT_LOCK;
3530 I915_WRITE(reg, temp);
3531
3532 POSTING_READ(reg);
3533 udelay(150);
3534
3535 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3536 I915_READ(FDI_RX_IIR(pipe)));
3537
3538 /* Try each vswing and preemphasis setting twice before moving on */
3539 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3540 /* disable first in case we need to retry */
3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
3543 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3544 temp &= ~FDI_TX_ENABLE;
3545 I915_WRITE(reg, temp);
3546
3547 reg = FDI_RX_CTL(pipe);
3548 temp = I915_READ(reg);
3549 temp &= ~FDI_LINK_TRAIN_AUTO;
3550 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3551 temp &= ~FDI_RX_ENABLE;
3552 I915_WRITE(reg, temp);
3553
3554 /* enable CPU FDI TX and PCH FDI RX */
3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3558 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3559 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561 temp |= snb_b_fdi_train_param[j/2];
3562 temp |= FDI_COMPOSITE_SYNC;
3563 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3564
3565 I915_WRITE(FDI_RX_MISC(pipe),
3566 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3567
3568 reg = FDI_RX_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3571 temp |= FDI_COMPOSITE_SYNC;
3572 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3573
3574 POSTING_READ(reg);
3575 udelay(1); /* should be 0.5us */
3576
3577 for (i = 0; i < 4; i++) {
3578 reg = FDI_RX_IIR(pipe);
3579 temp = I915_READ(reg);
3580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3581
3582 if (temp & FDI_RX_BIT_LOCK ||
3583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3586 i);
3587 break;
3588 }
3589 udelay(1); /* should be 0.5us */
3590 }
3591 if (i == 4) {
3592 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3593 continue;
3594 }
3595
3596 /* Train 2 */
3597 reg = FDI_TX_CTL(pipe);
3598 temp = I915_READ(reg);
3599 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3601 I915_WRITE(reg, temp);
3602
3603 reg = FDI_RX_CTL(pipe);
3604 temp = I915_READ(reg);
3605 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3606 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3607 I915_WRITE(reg, temp);
3608
3609 POSTING_READ(reg);
3610 udelay(2); /* should be 1.5us */
3611
3612 for (i = 0; i < 4; i++) {
3613 reg = FDI_RX_IIR(pipe);
3614 temp = I915_READ(reg);
3615 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3616
3617 if (temp & FDI_RX_SYMBOL_LOCK ||
3618 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3619 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3620 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3621 i);
3622 goto train_done;
3623 }
3624 udelay(2); /* should be 1.5us */
3625 }
3626 if (i == 4)
3627 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3628 }
3629
3630 train_done:
3631 DRM_DEBUG_KMS("FDI train done.\n");
3632 }
3633
3634 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3635 {
3636 struct drm_device *dev = intel_crtc->base.dev;
3637 struct drm_i915_private *dev_priv = to_i915(dev);
3638 int pipe = intel_crtc->pipe;
3639 i915_reg_t reg;
3640 u32 temp;
3641
3642 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3643 reg = FDI_RX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3646 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3647 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3648 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3649
3650 POSTING_READ(reg);
3651 udelay(200);
3652
3653 /* Switch from Rawclk to PCDclk */
3654 temp = I915_READ(reg);
3655 I915_WRITE(reg, temp | FDI_PCDCLK);
3656
3657 POSTING_READ(reg);
3658 udelay(200);
3659
3660 /* Enable CPU FDI TX PLL, always on for Ironlake */
3661 reg = FDI_TX_CTL(pipe);
3662 temp = I915_READ(reg);
3663 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3664 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3665
3666 POSTING_READ(reg);
3667 udelay(100);
3668 }
3669 }
3670
3671 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3672 {
3673 struct drm_device *dev = intel_crtc->base.dev;
3674 struct drm_i915_private *dev_priv = to_i915(dev);
3675 int pipe = intel_crtc->pipe;
3676 i915_reg_t reg;
3677 u32 temp;
3678
3679 /* Switch from PCDclk to Rawclk */
3680 reg = FDI_RX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3683
3684 /* Disable CPU FDI TX PLL */
3685 reg = FDI_TX_CTL(pipe);
3686 temp = I915_READ(reg);
3687 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3688
3689 POSTING_READ(reg);
3690 udelay(100);
3691
3692 reg = FDI_RX_CTL(pipe);
3693 temp = I915_READ(reg);
3694 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3695
3696 /* Wait for the clocks to turn off. */
3697 POSTING_READ(reg);
3698 udelay(100);
3699 }
3700
3701 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3702 {
3703 struct drm_device *dev = crtc->dev;
3704 struct drm_i915_private *dev_priv = to_i915(dev);
3705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3706 int pipe = intel_crtc->pipe;
3707 i915_reg_t reg;
3708 u32 temp;
3709
3710 /* disable CPU FDI tx and PCH FDI rx */
3711 reg = FDI_TX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3714 POSTING_READ(reg);
3715
3716 reg = FDI_RX_CTL(pipe);
3717 temp = I915_READ(reg);
3718 temp &= ~(0x7 << 16);
3719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3721
3722 POSTING_READ(reg);
3723 udelay(100);
3724
3725 /* Ironlake workaround, disable clock pointer after downing FDI */
3726 if (HAS_PCH_IBX(dev))
3727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3728
3729 /* still set train pattern 1 */
3730 reg = FDI_TX_CTL(pipe);
3731 temp = I915_READ(reg);
3732 temp &= ~FDI_LINK_TRAIN_NONE;
3733 temp |= FDI_LINK_TRAIN_PATTERN_1;
3734 I915_WRITE(reg, temp);
3735
3736 reg = FDI_RX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 if (HAS_PCH_CPT(dev)) {
3739 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3740 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3741 } else {
3742 temp &= ~FDI_LINK_TRAIN_NONE;
3743 temp |= FDI_LINK_TRAIN_PATTERN_1;
3744 }
3745 /* BPC in FDI rx is consistent with that in PIPECONF */
3746 temp &= ~(0x07 << 16);
3747 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3748 I915_WRITE(reg, temp);
3749
3750 POSTING_READ(reg);
3751 udelay(100);
3752 }
3753
3754 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3755 {
3756 struct intel_crtc *crtc;
3757
3758 /* Note that we don't need to be called with mode_config.lock here
3759 * as our list of CRTC objects is static for the lifetime of the
3760 * device and so cannot disappear as we iterate. Similarly, we can
3761 * happily treat the predicates as racy, atomic checks as userspace
3762 * cannot claim and pin a new fb without at least acquring the
3763 * struct_mutex and so serialising with us.
3764 */
3765 for_each_intel_crtc(dev, crtc) {
3766 if (atomic_read(&crtc->unpin_work_count) == 0)
3767 continue;
3768
3769 if (crtc->flip_work)
3770 intel_wait_for_vblank(dev, crtc->pipe);
3771
3772 return true;
3773 }
3774
3775 return false;
3776 }
3777
3778 static void page_flip_completed(struct intel_crtc *intel_crtc)
3779 {
3780 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3781 struct intel_flip_work *work = intel_crtc->flip_work;
3782
3783 intel_crtc->flip_work = NULL;
3784
3785 if (work->event)
3786 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3787
3788 drm_crtc_vblank_put(&intel_crtc->base);
3789
3790 wake_up_all(&dev_priv->pending_flip_queue);
3791 queue_work(dev_priv->wq, &work->unpin_work);
3792
3793 trace_i915_flip_complete(intel_crtc->plane,
3794 work->pending_flip_obj);
3795 }
3796
3797 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3798 {
3799 struct drm_device *dev = crtc->dev;
3800 struct drm_i915_private *dev_priv = to_i915(dev);
3801 long ret;
3802
3803 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3804
3805 ret = wait_event_interruptible_timeout(
3806 dev_priv->pending_flip_queue,
3807 !intel_crtc_has_pending_flip(crtc),
3808 60*HZ);
3809
3810 if (ret < 0)
3811 return ret;
3812
3813 if (ret == 0) {
3814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815 struct intel_flip_work *work;
3816
3817 spin_lock_irq(&dev->event_lock);
3818 work = intel_crtc->flip_work;
3819 if (work && !is_mmio_work(work)) {
3820 WARN_ONCE(1, "Removing stuck page flip\n");
3821 page_flip_completed(intel_crtc);
3822 }
3823 spin_unlock_irq(&dev->event_lock);
3824 }
3825
3826 return 0;
3827 }
3828
3829 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3830 {
3831 u32 temp;
3832
3833 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3834
3835 mutex_lock(&dev_priv->sb_lock);
3836
3837 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3838 temp |= SBI_SSCCTL_DISABLE;
3839 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3840
3841 mutex_unlock(&dev_priv->sb_lock);
3842 }
3843
3844 /* Program iCLKIP clock to the desired frequency */
3845 static void lpt_program_iclkip(struct drm_crtc *crtc)
3846 {
3847 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3848 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3849 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3850 u32 temp;
3851
3852 lpt_disable_iclkip(dev_priv);
3853
3854 /* The iCLK virtual clock root frequency is in MHz,
3855 * but the adjusted_mode->crtc_clock in in KHz. To get the
3856 * divisors, it is necessary to divide one by another, so we
3857 * convert the virtual clock precision to KHz here for higher
3858 * precision.
3859 */
3860 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3861 u32 iclk_virtual_root_freq = 172800 * 1000;
3862 u32 iclk_pi_range = 64;
3863 u32 desired_divisor;
3864
3865 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3866 clock << auxdiv);
3867 divsel = (desired_divisor / iclk_pi_range) - 2;
3868 phaseinc = desired_divisor % iclk_pi_range;
3869
3870 /*
3871 * Near 20MHz is a corner case which is
3872 * out of range for the 7-bit divisor
3873 */
3874 if (divsel <= 0x7f)
3875 break;
3876 }
3877
3878 /* This should not happen with any sane values */
3879 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3880 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3881 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3882 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3883
3884 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3885 clock,
3886 auxdiv,
3887 divsel,
3888 phasedir,
3889 phaseinc);
3890
3891 mutex_lock(&dev_priv->sb_lock);
3892
3893 /* Program SSCDIVINTPHASE6 */
3894 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3895 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3896 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3897 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3898 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3899 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3900 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3901 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3902
3903 /* Program SSCAUXDIV */
3904 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3905 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3906 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3907 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3908
3909 /* Enable modulator and associated divider */
3910 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3911 temp &= ~SBI_SSCCTL_DISABLE;
3912 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3913
3914 mutex_unlock(&dev_priv->sb_lock);
3915
3916 /* Wait for initialization time */
3917 udelay(24);
3918
3919 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3920 }
3921
3922 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3923 {
3924 u32 divsel, phaseinc, auxdiv;
3925 u32 iclk_virtual_root_freq = 172800 * 1000;
3926 u32 iclk_pi_range = 64;
3927 u32 desired_divisor;
3928 u32 temp;
3929
3930 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3931 return 0;
3932
3933 mutex_lock(&dev_priv->sb_lock);
3934
3935 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3936 if (temp & SBI_SSCCTL_DISABLE) {
3937 mutex_unlock(&dev_priv->sb_lock);
3938 return 0;
3939 }
3940
3941 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3942 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3943 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3944 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3945 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3946
3947 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3948 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3949 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3950
3951 mutex_unlock(&dev_priv->sb_lock);
3952
3953 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3954
3955 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3956 desired_divisor << auxdiv);
3957 }
3958
3959 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3960 enum pipe pch_transcoder)
3961 {
3962 struct drm_device *dev = crtc->base.dev;
3963 struct drm_i915_private *dev_priv = to_i915(dev);
3964 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3965
3966 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3967 I915_READ(HTOTAL(cpu_transcoder)));
3968 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3969 I915_READ(HBLANK(cpu_transcoder)));
3970 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3971 I915_READ(HSYNC(cpu_transcoder)));
3972
3973 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3974 I915_READ(VTOTAL(cpu_transcoder)));
3975 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3976 I915_READ(VBLANK(cpu_transcoder)));
3977 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3978 I915_READ(VSYNC(cpu_transcoder)));
3979 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3980 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3981 }
3982
3983 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3984 {
3985 struct drm_i915_private *dev_priv = to_i915(dev);
3986 uint32_t temp;
3987
3988 temp = I915_READ(SOUTH_CHICKEN1);
3989 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3990 return;
3991
3992 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3993 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3994
3995 temp &= ~FDI_BC_BIFURCATION_SELECT;
3996 if (enable)
3997 temp |= FDI_BC_BIFURCATION_SELECT;
3998
3999 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4000 I915_WRITE(SOUTH_CHICKEN1, temp);
4001 POSTING_READ(SOUTH_CHICKEN1);
4002 }
4003
4004 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4005 {
4006 struct drm_device *dev = intel_crtc->base.dev;
4007
4008 switch (intel_crtc->pipe) {
4009 case PIPE_A:
4010 break;
4011 case PIPE_B:
4012 if (intel_crtc->config->fdi_lanes > 2)
4013 cpt_set_fdi_bc_bifurcation(dev, false);
4014 else
4015 cpt_set_fdi_bc_bifurcation(dev, true);
4016
4017 break;
4018 case PIPE_C:
4019 cpt_set_fdi_bc_bifurcation(dev, true);
4020
4021 break;
4022 default:
4023 BUG();
4024 }
4025 }
4026
4027 /* Return which DP Port should be selected for Transcoder DP control */
4028 static enum port
4029 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4030 {
4031 struct drm_device *dev = crtc->dev;
4032 struct intel_encoder *encoder;
4033
4034 for_each_encoder_on_crtc(dev, crtc, encoder) {
4035 if (encoder->type == INTEL_OUTPUT_DP ||
4036 encoder->type == INTEL_OUTPUT_EDP)
4037 return enc_to_dig_port(&encoder->base)->port;
4038 }
4039
4040 return -1;
4041 }
4042
4043 /*
4044 * Enable PCH resources required for PCH ports:
4045 * - PCH PLLs
4046 * - FDI training & RX/TX
4047 * - update transcoder timings
4048 * - DP transcoding bits
4049 * - transcoder
4050 */
4051 static void ironlake_pch_enable(struct drm_crtc *crtc)
4052 {
4053 struct drm_device *dev = crtc->dev;
4054 struct drm_i915_private *dev_priv = to_i915(dev);
4055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4056 int pipe = intel_crtc->pipe;
4057 u32 temp;
4058
4059 assert_pch_transcoder_disabled(dev_priv, pipe);
4060
4061 if (IS_IVYBRIDGE(dev))
4062 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4063
4064 /* Write the TU size bits before fdi link training, so that error
4065 * detection works. */
4066 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4067 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4068
4069 /* For PCH output, training FDI link */
4070 dev_priv->display.fdi_link_train(crtc);
4071
4072 /* We need to program the right clock selection before writing the pixel
4073 * mutliplier into the DPLL. */
4074 if (HAS_PCH_CPT(dev)) {
4075 u32 sel;
4076
4077 temp = I915_READ(PCH_DPLL_SEL);
4078 temp |= TRANS_DPLL_ENABLE(pipe);
4079 sel = TRANS_DPLLB_SEL(pipe);
4080 if (intel_crtc->config->shared_dpll ==
4081 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4082 temp |= sel;
4083 else
4084 temp &= ~sel;
4085 I915_WRITE(PCH_DPLL_SEL, temp);
4086 }
4087
4088 /* XXX: pch pll's can be enabled any time before we enable the PCH
4089 * transcoder, and we actually should do this to not upset any PCH
4090 * transcoder that already use the clock when we share it.
4091 *
4092 * Note that enable_shared_dpll tries to do the right thing, but
4093 * get_shared_dpll unconditionally resets the pll - we need that to have
4094 * the right LVDS enable sequence. */
4095 intel_enable_shared_dpll(intel_crtc);
4096
4097 /* set transcoder timing, panel must allow it */
4098 assert_panel_unlocked(dev_priv, pipe);
4099 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4100
4101 intel_fdi_normal_train(crtc);
4102
4103 /* For PCH DP, enable TRANS_DP_CTL */
4104 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4105 const struct drm_display_mode *adjusted_mode =
4106 &intel_crtc->config->base.adjusted_mode;
4107 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4108 i915_reg_t reg = TRANS_DP_CTL(pipe);
4109 temp = I915_READ(reg);
4110 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4111 TRANS_DP_SYNC_MASK |
4112 TRANS_DP_BPC_MASK);
4113 temp |= TRANS_DP_OUTPUT_ENABLE;
4114 temp |= bpc << 9; /* same format but at 11:9 */
4115
4116 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4117 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4118 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4119 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4120
4121 switch (intel_trans_dp_port_sel(crtc)) {
4122 case PORT_B:
4123 temp |= TRANS_DP_PORT_SEL_B;
4124 break;
4125 case PORT_C:
4126 temp |= TRANS_DP_PORT_SEL_C;
4127 break;
4128 case PORT_D:
4129 temp |= TRANS_DP_PORT_SEL_D;
4130 break;
4131 default:
4132 BUG();
4133 }
4134
4135 I915_WRITE(reg, temp);
4136 }
4137
4138 ironlake_enable_pch_transcoder(dev_priv, pipe);
4139 }
4140
4141 static void lpt_pch_enable(struct drm_crtc *crtc)
4142 {
4143 struct drm_device *dev = crtc->dev;
4144 struct drm_i915_private *dev_priv = to_i915(dev);
4145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4146 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4147
4148 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4149
4150 lpt_program_iclkip(crtc);
4151
4152 /* Set transcoder timing. */
4153 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4154
4155 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4156 }
4157
4158 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4159 {
4160 struct drm_i915_private *dev_priv = to_i915(dev);
4161 i915_reg_t dslreg = PIPEDSL(pipe);
4162 u32 temp;
4163
4164 temp = I915_READ(dslreg);
4165 udelay(500);
4166 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4167 if (wait_for(I915_READ(dslreg) != temp, 5))
4168 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4169 }
4170 }
4171
4172 static int
4173 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4174 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4175 int src_w, int src_h, int dst_w, int dst_h)
4176 {
4177 struct intel_crtc_scaler_state *scaler_state =
4178 &crtc_state->scaler_state;
4179 struct intel_crtc *intel_crtc =
4180 to_intel_crtc(crtc_state->base.crtc);
4181 int need_scaling;
4182
4183 need_scaling = intel_rotation_90_or_270(rotation) ?
4184 (src_h != dst_w || src_w != dst_h):
4185 (src_w != dst_w || src_h != dst_h);
4186
4187 /*
4188 * if plane is being disabled or scaler is no more required or force detach
4189 * - free scaler binded to this plane/crtc
4190 * - in order to do this, update crtc->scaler_usage
4191 *
4192 * Here scaler state in crtc_state is set free so that
4193 * scaler can be assigned to other user. Actual register
4194 * update to free the scaler is done in plane/panel-fit programming.
4195 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4196 */
4197 if (force_detach || !need_scaling) {
4198 if (*scaler_id >= 0) {
4199 scaler_state->scaler_users &= ~(1 << scaler_user);
4200 scaler_state->scalers[*scaler_id].in_use = 0;
4201
4202 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4203 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4204 intel_crtc->pipe, scaler_user, *scaler_id,
4205 scaler_state->scaler_users);
4206 *scaler_id = -1;
4207 }
4208 return 0;
4209 }
4210
4211 /* range checks */
4212 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4213 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4214
4215 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4216 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4217 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4218 "size is out of scaler range\n",
4219 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4220 return -EINVAL;
4221 }
4222
4223 /* mark this plane as a scaler user in crtc_state */
4224 scaler_state->scaler_users |= (1 << scaler_user);
4225 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4226 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4227 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4228 scaler_state->scaler_users);
4229
4230 return 0;
4231 }
4232
4233 /**
4234 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4235 *
4236 * @state: crtc's scaler state
4237 *
4238 * Return
4239 * 0 - scaler_usage updated successfully
4240 * error - requested scaling cannot be supported or other error condition
4241 */
4242 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4243 {
4244 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4245 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4246
4247 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4248 intel_crtc->base.base.id, intel_crtc->base.name,
4249 intel_crtc->pipe, SKL_CRTC_INDEX);
4250
4251 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4252 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4253 state->pipe_src_w, state->pipe_src_h,
4254 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4255 }
4256
4257 /**
4258 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4259 *
4260 * @state: crtc's scaler state
4261 * @plane_state: atomic plane state to update
4262 *
4263 * Return
4264 * 0 - scaler_usage updated successfully
4265 * error - requested scaling cannot be supported or other error condition
4266 */
4267 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4268 struct intel_plane_state *plane_state)
4269 {
4270
4271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4272 struct intel_plane *intel_plane =
4273 to_intel_plane(plane_state->base.plane);
4274 struct drm_framebuffer *fb = plane_state->base.fb;
4275 int ret;
4276
4277 bool force_detach = !fb || !plane_state->visible;
4278
4279 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4280 intel_plane->base.base.id, intel_plane->base.name,
4281 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4282
4283 ret = skl_update_scaler(crtc_state, force_detach,
4284 drm_plane_index(&intel_plane->base),
4285 &plane_state->scaler_id,
4286 plane_state->base.rotation,
4287 drm_rect_width(&plane_state->src) >> 16,
4288 drm_rect_height(&plane_state->src) >> 16,
4289 drm_rect_width(&plane_state->dst),
4290 drm_rect_height(&plane_state->dst));
4291
4292 if (ret || plane_state->scaler_id < 0)
4293 return ret;
4294
4295 /* check colorkey */
4296 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4297 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4298 intel_plane->base.base.id,
4299 intel_plane->base.name);
4300 return -EINVAL;
4301 }
4302
4303 /* Check src format */
4304 switch (fb->pixel_format) {
4305 case DRM_FORMAT_RGB565:
4306 case DRM_FORMAT_XBGR8888:
4307 case DRM_FORMAT_XRGB8888:
4308 case DRM_FORMAT_ABGR8888:
4309 case DRM_FORMAT_ARGB8888:
4310 case DRM_FORMAT_XRGB2101010:
4311 case DRM_FORMAT_XBGR2101010:
4312 case DRM_FORMAT_YUYV:
4313 case DRM_FORMAT_YVYU:
4314 case DRM_FORMAT_UYVY:
4315 case DRM_FORMAT_VYUY:
4316 break;
4317 default:
4318 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4319 intel_plane->base.base.id, intel_plane->base.name,
4320 fb->base.id, fb->pixel_format);
4321 return -EINVAL;
4322 }
4323
4324 return 0;
4325 }
4326
4327 static void skylake_scaler_disable(struct intel_crtc *crtc)
4328 {
4329 int i;
4330
4331 for (i = 0; i < crtc->num_scalers; i++)
4332 skl_detach_scaler(crtc, i);
4333 }
4334
4335 static void skylake_pfit_enable(struct intel_crtc *crtc)
4336 {
4337 struct drm_device *dev = crtc->base.dev;
4338 struct drm_i915_private *dev_priv = to_i915(dev);
4339 int pipe = crtc->pipe;
4340 struct intel_crtc_scaler_state *scaler_state =
4341 &crtc->config->scaler_state;
4342
4343 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4344
4345 if (crtc->config->pch_pfit.enabled) {
4346 int id;
4347
4348 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4349 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4350 return;
4351 }
4352
4353 id = scaler_state->scaler_id;
4354 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4355 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4356 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4357 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4358
4359 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4360 }
4361 }
4362
4363 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4364 {
4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = to_i915(dev);
4367 int pipe = crtc->pipe;
4368
4369 if (crtc->config->pch_pfit.enabled) {
4370 /* Force use of hard-coded filter coefficients
4371 * as some pre-programmed values are broken,
4372 * e.g. x201.
4373 */
4374 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4375 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4376 PF_PIPE_SEL_IVB(pipe));
4377 else
4378 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4379 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4380 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4381 }
4382 }
4383
4384 void hsw_enable_ips(struct intel_crtc *crtc)
4385 {
4386 struct drm_device *dev = crtc->base.dev;
4387 struct drm_i915_private *dev_priv = to_i915(dev);
4388
4389 if (!crtc->config->ips_enabled)
4390 return;
4391
4392 /*
4393 * We can only enable IPS after we enable a plane and wait for a vblank
4394 * This function is called from post_plane_update, which is run after
4395 * a vblank wait.
4396 */
4397
4398 assert_plane_enabled(dev_priv, crtc->plane);
4399 if (IS_BROADWELL(dev)) {
4400 mutex_lock(&dev_priv->rps.hw_lock);
4401 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4402 mutex_unlock(&dev_priv->rps.hw_lock);
4403 /* Quoting Art Runyan: "its not safe to expect any particular
4404 * value in IPS_CTL bit 31 after enabling IPS through the
4405 * mailbox." Moreover, the mailbox may return a bogus state,
4406 * so we need to just enable it and continue on.
4407 */
4408 } else {
4409 I915_WRITE(IPS_CTL, IPS_ENABLE);
4410 /* The bit only becomes 1 in the next vblank, so this wait here
4411 * is essentially intel_wait_for_vblank. If we don't have this
4412 * and don't wait for vblanks until the end of crtc_enable, then
4413 * the HW state readout code will complain that the expected
4414 * IPS_CTL value is not the one we read. */
4415 if (intel_wait_for_register(dev_priv,
4416 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4417 50))
4418 DRM_ERROR("Timed out waiting for IPS enable\n");
4419 }
4420 }
4421
4422 void hsw_disable_ips(struct intel_crtc *crtc)
4423 {
4424 struct drm_device *dev = crtc->base.dev;
4425 struct drm_i915_private *dev_priv = to_i915(dev);
4426
4427 if (!crtc->config->ips_enabled)
4428 return;
4429
4430 assert_plane_enabled(dev_priv, crtc->plane);
4431 if (IS_BROADWELL(dev)) {
4432 mutex_lock(&dev_priv->rps.hw_lock);
4433 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4434 mutex_unlock(&dev_priv->rps.hw_lock);
4435 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4436 if (intel_wait_for_register(dev_priv,
4437 IPS_CTL, IPS_ENABLE, 0,
4438 42))
4439 DRM_ERROR("Timed out waiting for IPS disable\n");
4440 } else {
4441 I915_WRITE(IPS_CTL, 0);
4442 POSTING_READ(IPS_CTL);
4443 }
4444
4445 /* We need to wait for a vblank before we can disable the plane. */
4446 intel_wait_for_vblank(dev, crtc->pipe);
4447 }
4448
4449 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4450 {
4451 if (intel_crtc->overlay) {
4452 struct drm_device *dev = intel_crtc->base.dev;
4453 struct drm_i915_private *dev_priv = to_i915(dev);
4454
4455 mutex_lock(&dev->struct_mutex);
4456 dev_priv->mm.interruptible = false;
4457 (void) intel_overlay_switch_off(intel_crtc->overlay);
4458 dev_priv->mm.interruptible = true;
4459 mutex_unlock(&dev->struct_mutex);
4460 }
4461
4462 /* Let userspace switch the overlay on again. In most cases userspace
4463 * has to recompute where to put it anyway.
4464 */
4465 }
4466
4467 /**
4468 * intel_post_enable_primary - Perform operations after enabling primary plane
4469 * @crtc: the CRTC whose primary plane was just enabled
4470 *
4471 * Performs potentially sleeping operations that must be done after the primary
4472 * plane is enabled, such as updating FBC and IPS. Note that this may be
4473 * called due to an explicit primary plane update, or due to an implicit
4474 * re-enable that is caused when a sprite plane is updated to no longer
4475 * completely hide the primary plane.
4476 */
4477 static void
4478 intel_post_enable_primary(struct drm_crtc *crtc)
4479 {
4480 struct drm_device *dev = crtc->dev;
4481 struct drm_i915_private *dev_priv = to_i915(dev);
4482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4483 int pipe = intel_crtc->pipe;
4484
4485 /*
4486 * FIXME IPS should be fine as long as one plane is
4487 * enabled, but in practice it seems to have problems
4488 * when going from primary only to sprite only and vice
4489 * versa.
4490 */
4491 hsw_enable_ips(intel_crtc);
4492
4493 /*
4494 * Gen2 reports pipe underruns whenever all planes are disabled.
4495 * So don't enable underrun reporting before at least some planes
4496 * are enabled.
4497 * FIXME: Need to fix the logic to work when we turn off all planes
4498 * but leave the pipe running.
4499 */
4500 if (IS_GEN2(dev))
4501 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4502
4503 /* Underruns don't always raise interrupts, so check manually. */
4504 intel_check_cpu_fifo_underruns(dev_priv);
4505 intel_check_pch_fifo_underruns(dev_priv);
4506 }
4507
4508 /* FIXME move all this to pre_plane_update() with proper state tracking */
4509 static void
4510 intel_pre_disable_primary(struct drm_crtc *crtc)
4511 {
4512 struct drm_device *dev = crtc->dev;
4513 struct drm_i915_private *dev_priv = to_i915(dev);
4514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4515 int pipe = intel_crtc->pipe;
4516
4517 /*
4518 * Gen2 reports pipe underruns whenever all planes are disabled.
4519 * So diasble underrun reporting before all the planes get disabled.
4520 * FIXME: Need to fix the logic to work when we turn off all planes
4521 * but leave the pipe running.
4522 */
4523 if (IS_GEN2(dev))
4524 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4525
4526 /*
4527 * FIXME IPS should be fine as long as one plane is
4528 * enabled, but in practice it seems to have problems
4529 * when going from primary only to sprite only and vice
4530 * versa.
4531 */
4532 hsw_disable_ips(intel_crtc);
4533 }
4534
4535 /* FIXME get rid of this and use pre_plane_update */
4536 static void
4537 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->dev;
4540 struct drm_i915_private *dev_priv = to_i915(dev);
4541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4542 int pipe = intel_crtc->pipe;
4543
4544 intel_pre_disable_primary(crtc);
4545
4546 /*
4547 * Vblank time updates from the shadow to live plane control register
4548 * are blocked if the memory self-refresh mode is active at that
4549 * moment. So to make sure the plane gets truly disabled, disable
4550 * first the self-refresh mode. The self-refresh enable bit in turn
4551 * will be checked/applied by the HW only at the next frame start
4552 * event which is after the vblank start event, so we need to have a
4553 * wait-for-vblank between disabling the plane and the pipe.
4554 */
4555 if (HAS_GMCH_DISPLAY(dev)) {
4556 intel_set_memory_cxsr(dev_priv, false);
4557 dev_priv->wm.vlv.cxsr = false;
4558 intel_wait_for_vblank(dev, pipe);
4559 }
4560 }
4561
4562 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4563 {
4564 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4565 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4566 struct intel_crtc_state *pipe_config =
4567 to_intel_crtc_state(crtc->base.state);
4568 struct drm_device *dev = crtc->base.dev;
4569 struct drm_plane *primary = crtc->base.primary;
4570 struct drm_plane_state *old_pri_state =
4571 drm_atomic_get_existing_plane_state(old_state, primary);
4572
4573 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4574
4575 crtc->wm.cxsr_allowed = true;
4576
4577 if (pipe_config->update_wm_post && pipe_config->base.active)
4578 intel_update_watermarks(&crtc->base);
4579
4580 if (old_pri_state) {
4581 struct intel_plane_state *primary_state =
4582 to_intel_plane_state(primary->state);
4583 struct intel_plane_state *old_primary_state =
4584 to_intel_plane_state(old_pri_state);
4585
4586 intel_fbc_post_update(crtc);
4587
4588 if (primary_state->visible &&
4589 (needs_modeset(&pipe_config->base) ||
4590 !old_primary_state->visible))
4591 intel_post_enable_primary(&crtc->base);
4592 }
4593 }
4594
4595 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4596 {
4597 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4598 struct drm_device *dev = crtc->base.dev;
4599 struct drm_i915_private *dev_priv = to_i915(dev);
4600 struct intel_crtc_state *pipe_config =
4601 to_intel_crtc_state(crtc->base.state);
4602 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4603 struct drm_plane *primary = crtc->base.primary;
4604 struct drm_plane_state *old_pri_state =
4605 drm_atomic_get_existing_plane_state(old_state, primary);
4606 bool modeset = needs_modeset(&pipe_config->base);
4607
4608 if (old_pri_state) {
4609 struct intel_plane_state *primary_state =
4610 to_intel_plane_state(primary->state);
4611 struct intel_plane_state *old_primary_state =
4612 to_intel_plane_state(old_pri_state);
4613
4614 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4615
4616 if (old_primary_state->visible &&
4617 (modeset || !primary_state->visible))
4618 intel_pre_disable_primary(&crtc->base);
4619 }
4620
4621 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4622 crtc->wm.cxsr_allowed = false;
4623
4624 /*
4625 * Vblank time updates from the shadow to live plane control register
4626 * are blocked if the memory self-refresh mode is active at that
4627 * moment. So to make sure the plane gets truly disabled, disable
4628 * first the self-refresh mode. The self-refresh enable bit in turn
4629 * will be checked/applied by the HW only at the next frame start
4630 * event which is after the vblank start event, so we need to have a
4631 * wait-for-vblank between disabling the plane and the pipe.
4632 */
4633 if (old_crtc_state->base.active) {
4634 intel_set_memory_cxsr(dev_priv, false);
4635 dev_priv->wm.vlv.cxsr = false;
4636 intel_wait_for_vblank(dev, crtc->pipe);
4637 }
4638 }
4639
4640 /*
4641 * IVB workaround: must disable low power watermarks for at least
4642 * one frame before enabling scaling. LP watermarks can be re-enabled
4643 * when scaling is disabled.
4644 *
4645 * WaCxSRDisabledForSpriteScaling:ivb
4646 */
4647 if (pipe_config->disable_lp_wm) {
4648 ilk_disable_lp_wm(dev);
4649 intel_wait_for_vblank(dev, crtc->pipe);
4650 }
4651
4652 /*
4653 * If we're doing a modeset, we're done. No need to do any pre-vblank
4654 * watermark programming here.
4655 */
4656 if (needs_modeset(&pipe_config->base))
4657 return;
4658
4659 /*
4660 * For platforms that support atomic watermarks, program the
4661 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4662 * will be the intermediate values that are safe for both pre- and
4663 * post- vblank; when vblank happens, the 'active' values will be set
4664 * to the final 'target' values and we'll do this again to get the
4665 * optimal watermarks. For gen9+ platforms, the values we program here
4666 * will be the final target values which will get automatically latched
4667 * at vblank time; no further programming will be necessary.
4668 *
4669 * If a platform hasn't been transitioned to atomic watermarks yet,
4670 * we'll continue to update watermarks the old way, if flags tell
4671 * us to.
4672 */
4673 if (dev_priv->display.initial_watermarks != NULL)
4674 dev_priv->display.initial_watermarks(pipe_config);
4675 else if (pipe_config->update_wm_pre)
4676 intel_update_watermarks(&crtc->base);
4677 }
4678
4679 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4680 {
4681 struct drm_device *dev = crtc->dev;
4682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4683 struct drm_plane *p;
4684 int pipe = intel_crtc->pipe;
4685
4686 intel_crtc_dpms_overlay_disable(intel_crtc);
4687
4688 drm_for_each_plane_mask(p, dev, plane_mask)
4689 to_intel_plane(p)->disable_plane(p, crtc);
4690
4691 /*
4692 * FIXME: Once we grow proper nuclear flip support out of this we need
4693 * to compute the mask of flip planes precisely. For the time being
4694 * consider this a flip to a NULL plane.
4695 */
4696 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4697 }
4698
4699 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4700 {
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = to_i915(dev);
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 struct intel_encoder *encoder;
4705 int pipe = intel_crtc->pipe;
4706 struct intel_crtc_state *pipe_config =
4707 to_intel_crtc_state(crtc->state);
4708
4709 if (WARN_ON(intel_crtc->active))
4710 return;
4711
4712 /*
4713 * Sometimes spurious CPU pipe underruns happen during FDI
4714 * training, at least with VGA+HDMI cloning. Suppress them.
4715 *
4716 * On ILK we get an occasional spurious CPU pipe underruns
4717 * between eDP port A enable and vdd enable. Also PCH port
4718 * enable seems to result in the occasional CPU pipe underrun.
4719 *
4720 * Spurious PCH underruns also occur during PCH enabling.
4721 */
4722 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4723 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4724 if (intel_crtc->config->has_pch_encoder)
4725 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4726
4727 if (intel_crtc->config->has_pch_encoder)
4728 intel_prepare_shared_dpll(intel_crtc);
4729
4730 if (intel_crtc_has_dp_encoder(intel_crtc->config))
4731 intel_dp_set_m_n(intel_crtc, M1_N1);
4732
4733 intel_set_pipe_timings(intel_crtc);
4734 intel_set_pipe_src_size(intel_crtc);
4735
4736 if (intel_crtc->config->has_pch_encoder) {
4737 intel_cpu_transcoder_set_m_n(intel_crtc,
4738 &intel_crtc->config->fdi_m_n, NULL);
4739 }
4740
4741 ironlake_set_pipeconf(crtc);
4742
4743 intel_crtc->active = true;
4744
4745 for_each_encoder_on_crtc(dev, crtc, encoder)
4746 if (encoder->pre_enable)
4747 encoder->pre_enable(encoder);
4748
4749 if (intel_crtc->config->has_pch_encoder) {
4750 /* Note: FDI PLL enabling _must_ be done before we enable the
4751 * cpu pipes, hence this is separate from all the other fdi/pch
4752 * enabling. */
4753 ironlake_fdi_pll_enable(intel_crtc);
4754 } else {
4755 assert_fdi_tx_disabled(dev_priv, pipe);
4756 assert_fdi_rx_disabled(dev_priv, pipe);
4757 }
4758
4759 ironlake_pfit_enable(intel_crtc);
4760
4761 /*
4762 * On ILK+ LUT must be loaded before the pipe is running but with
4763 * clocks enabled
4764 */
4765 intel_color_load_luts(&pipe_config->base);
4766
4767 if (dev_priv->display.initial_watermarks != NULL)
4768 dev_priv->display.initial_watermarks(intel_crtc->config);
4769 intel_enable_pipe(intel_crtc);
4770
4771 if (intel_crtc->config->has_pch_encoder)
4772 ironlake_pch_enable(crtc);
4773
4774 assert_vblank_disabled(crtc);
4775 drm_crtc_vblank_on(crtc);
4776
4777 for_each_encoder_on_crtc(dev, crtc, encoder)
4778 encoder->enable(encoder);
4779
4780 if (HAS_PCH_CPT(dev))
4781 cpt_verify_modeset(dev, intel_crtc->pipe);
4782
4783 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4784 if (intel_crtc->config->has_pch_encoder)
4785 intel_wait_for_vblank(dev, pipe);
4786 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4787 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4788 }
4789
4790 /* IPS only exists on ULT machines and is tied to pipe A. */
4791 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4792 {
4793 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4794 }
4795
4796 static void haswell_crtc_enable(struct drm_crtc *crtc)
4797 {
4798 struct drm_device *dev = crtc->dev;
4799 struct drm_i915_private *dev_priv = to_i915(dev);
4800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4801 struct intel_encoder *encoder;
4802 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4803 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4804 struct intel_crtc_state *pipe_config =
4805 to_intel_crtc_state(crtc->state);
4806
4807 if (WARN_ON(intel_crtc->active))
4808 return;
4809
4810 if (intel_crtc->config->has_pch_encoder)
4811 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4812 false);
4813
4814 for_each_encoder_on_crtc(dev, crtc, encoder)
4815 if (encoder->pre_pll_enable)
4816 encoder->pre_pll_enable(encoder);
4817
4818 if (intel_crtc->config->shared_dpll)
4819 intel_enable_shared_dpll(intel_crtc);
4820
4821 if (intel_crtc_has_dp_encoder(intel_crtc->config))
4822 intel_dp_set_m_n(intel_crtc, M1_N1);
4823
4824 if (!transcoder_is_dsi(cpu_transcoder))
4825 intel_set_pipe_timings(intel_crtc);
4826
4827 intel_set_pipe_src_size(intel_crtc);
4828
4829 if (cpu_transcoder != TRANSCODER_EDP &&
4830 !transcoder_is_dsi(cpu_transcoder)) {
4831 I915_WRITE(PIPE_MULT(cpu_transcoder),
4832 intel_crtc->config->pixel_multiplier - 1);
4833 }
4834
4835 if (intel_crtc->config->has_pch_encoder) {
4836 intel_cpu_transcoder_set_m_n(intel_crtc,
4837 &intel_crtc->config->fdi_m_n, NULL);
4838 }
4839
4840 if (!transcoder_is_dsi(cpu_transcoder))
4841 haswell_set_pipeconf(crtc);
4842
4843 haswell_set_pipemisc(crtc);
4844
4845 intel_color_set_csc(&pipe_config->base);
4846
4847 intel_crtc->active = true;
4848
4849 if (intel_crtc->config->has_pch_encoder)
4850 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4851 else
4852 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4853
4854 for_each_encoder_on_crtc(dev, crtc, encoder) {
4855 if (encoder->pre_enable)
4856 encoder->pre_enable(encoder);
4857 }
4858
4859 if (intel_crtc->config->has_pch_encoder)
4860 dev_priv->display.fdi_link_train(crtc);
4861
4862 if (!transcoder_is_dsi(cpu_transcoder))
4863 intel_ddi_enable_pipe_clock(intel_crtc);
4864
4865 if (INTEL_INFO(dev)->gen >= 9)
4866 skylake_pfit_enable(intel_crtc);
4867 else
4868 ironlake_pfit_enable(intel_crtc);
4869
4870 /*
4871 * On ILK+ LUT must be loaded before the pipe is running but with
4872 * clocks enabled
4873 */
4874 intel_color_load_luts(&pipe_config->base);
4875
4876 intel_ddi_set_pipe_settings(crtc);
4877 if (!transcoder_is_dsi(cpu_transcoder))
4878 intel_ddi_enable_transcoder_func(crtc);
4879
4880 if (dev_priv->display.initial_watermarks != NULL)
4881 dev_priv->display.initial_watermarks(pipe_config);
4882 else
4883 intel_update_watermarks(crtc);
4884
4885 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4886 if (!transcoder_is_dsi(cpu_transcoder))
4887 intel_enable_pipe(intel_crtc);
4888
4889 if (intel_crtc->config->has_pch_encoder)
4890 lpt_pch_enable(crtc);
4891
4892 if (intel_crtc->config->dp_encoder_is_mst)
4893 intel_ddi_set_vc_payload_alloc(crtc, true);
4894
4895 assert_vblank_disabled(crtc);
4896 drm_crtc_vblank_on(crtc);
4897
4898 for_each_encoder_on_crtc(dev, crtc, encoder) {
4899 encoder->enable(encoder);
4900 intel_opregion_notify_encoder(encoder, true);
4901 }
4902
4903 if (intel_crtc->config->has_pch_encoder) {
4904 intel_wait_for_vblank(dev, pipe);
4905 intel_wait_for_vblank(dev, pipe);
4906 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4907 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4908 true);
4909 }
4910
4911 /* If we change the relative order between pipe/planes enabling, we need
4912 * to change the workaround. */
4913 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4914 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4915 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4916 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4917 }
4918 }
4919
4920 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4921 {
4922 struct drm_device *dev = crtc->base.dev;
4923 struct drm_i915_private *dev_priv = to_i915(dev);
4924 int pipe = crtc->pipe;
4925
4926 /* To avoid upsetting the power well on haswell only disable the pfit if
4927 * it's in use. The hw state code will make sure we get this right. */
4928 if (force || crtc->config->pch_pfit.enabled) {
4929 I915_WRITE(PF_CTL(pipe), 0);
4930 I915_WRITE(PF_WIN_POS(pipe), 0);
4931 I915_WRITE(PF_WIN_SZ(pipe), 0);
4932 }
4933 }
4934
4935 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4936 {
4937 struct drm_device *dev = crtc->dev;
4938 struct drm_i915_private *dev_priv = to_i915(dev);
4939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4940 struct intel_encoder *encoder;
4941 int pipe = intel_crtc->pipe;
4942
4943 /*
4944 * Sometimes spurious CPU pipe underruns happen when the
4945 * pipe is already disabled, but FDI RX/TX is still enabled.
4946 * Happens at least with VGA+HDMI cloning. Suppress them.
4947 */
4948 if (intel_crtc->config->has_pch_encoder) {
4949 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4950 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4951 }
4952
4953 for_each_encoder_on_crtc(dev, crtc, encoder)
4954 encoder->disable(encoder);
4955
4956 drm_crtc_vblank_off(crtc);
4957 assert_vblank_disabled(crtc);
4958
4959 intel_disable_pipe(intel_crtc);
4960
4961 ironlake_pfit_disable(intel_crtc, false);
4962
4963 if (intel_crtc->config->has_pch_encoder)
4964 ironlake_fdi_disable(crtc);
4965
4966 for_each_encoder_on_crtc(dev, crtc, encoder)
4967 if (encoder->post_disable)
4968 encoder->post_disable(encoder);
4969
4970 if (intel_crtc->config->has_pch_encoder) {
4971 ironlake_disable_pch_transcoder(dev_priv, pipe);
4972
4973 if (HAS_PCH_CPT(dev)) {
4974 i915_reg_t reg;
4975 u32 temp;
4976
4977 /* disable TRANS_DP_CTL */
4978 reg = TRANS_DP_CTL(pipe);
4979 temp = I915_READ(reg);
4980 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4981 TRANS_DP_PORT_SEL_MASK);
4982 temp |= TRANS_DP_PORT_SEL_NONE;
4983 I915_WRITE(reg, temp);
4984
4985 /* disable DPLL_SEL */
4986 temp = I915_READ(PCH_DPLL_SEL);
4987 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4988 I915_WRITE(PCH_DPLL_SEL, temp);
4989 }
4990
4991 ironlake_fdi_pll_disable(intel_crtc);
4992 }
4993
4994 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4995 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4996 }
4997
4998 static void haswell_crtc_disable(struct drm_crtc *crtc)
4999 {
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = to_i915(dev);
5002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5003 struct intel_encoder *encoder;
5004 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5005
5006 if (intel_crtc->config->has_pch_encoder)
5007 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5008 false);
5009
5010 for_each_encoder_on_crtc(dev, crtc, encoder) {
5011 intel_opregion_notify_encoder(encoder, false);
5012 encoder->disable(encoder);
5013 }
5014
5015 drm_crtc_vblank_off(crtc);
5016 assert_vblank_disabled(crtc);
5017
5018 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5019 if (!transcoder_is_dsi(cpu_transcoder))
5020 intel_disable_pipe(intel_crtc);
5021
5022 if (intel_crtc->config->dp_encoder_is_mst)
5023 intel_ddi_set_vc_payload_alloc(crtc, false);
5024
5025 if (!transcoder_is_dsi(cpu_transcoder))
5026 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5027
5028 if (INTEL_INFO(dev)->gen >= 9)
5029 skylake_scaler_disable(intel_crtc);
5030 else
5031 ironlake_pfit_disable(intel_crtc, false);
5032
5033 if (!transcoder_is_dsi(cpu_transcoder))
5034 intel_ddi_disable_pipe_clock(intel_crtc);
5035
5036 for_each_encoder_on_crtc(dev, crtc, encoder)
5037 if (encoder->post_disable)
5038 encoder->post_disable(encoder);
5039
5040 if (intel_crtc->config->has_pch_encoder) {
5041 lpt_disable_pch_transcoder(dev_priv);
5042 lpt_disable_iclkip(dev_priv);
5043 intel_ddi_fdi_disable(crtc);
5044
5045 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5046 true);
5047 }
5048 }
5049
5050 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5051 {
5052 struct drm_device *dev = crtc->base.dev;
5053 struct drm_i915_private *dev_priv = to_i915(dev);
5054 struct intel_crtc_state *pipe_config = crtc->config;
5055
5056 if (!pipe_config->gmch_pfit.control)
5057 return;
5058
5059 /*
5060 * The panel fitter should only be adjusted whilst the pipe is disabled,
5061 * according to register description and PRM.
5062 */
5063 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5064 assert_pipe_disabled(dev_priv, crtc->pipe);
5065
5066 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5067 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5068
5069 /* Border color in case we don't scale up to the full screen. Black by
5070 * default, change to something else for debugging. */
5071 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5072 }
5073
5074 static enum intel_display_power_domain port_to_power_domain(enum port port)
5075 {
5076 switch (port) {
5077 case PORT_A:
5078 return POWER_DOMAIN_PORT_DDI_A_LANES;
5079 case PORT_B:
5080 return POWER_DOMAIN_PORT_DDI_B_LANES;
5081 case PORT_C:
5082 return POWER_DOMAIN_PORT_DDI_C_LANES;
5083 case PORT_D:
5084 return POWER_DOMAIN_PORT_DDI_D_LANES;
5085 case PORT_E:
5086 return POWER_DOMAIN_PORT_DDI_E_LANES;
5087 default:
5088 MISSING_CASE(port);
5089 return POWER_DOMAIN_PORT_OTHER;
5090 }
5091 }
5092
5093 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5094 {
5095 switch (port) {
5096 case PORT_A:
5097 return POWER_DOMAIN_AUX_A;
5098 case PORT_B:
5099 return POWER_DOMAIN_AUX_B;
5100 case PORT_C:
5101 return POWER_DOMAIN_AUX_C;
5102 case PORT_D:
5103 return POWER_DOMAIN_AUX_D;
5104 case PORT_E:
5105 /* FIXME: Check VBT for actual wiring of PORT E */
5106 return POWER_DOMAIN_AUX_D;
5107 default:
5108 MISSING_CASE(port);
5109 return POWER_DOMAIN_AUX_A;
5110 }
5111 }
5112
5113 enum intel_display_power_domain
5114 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5115 {
5116 struct drm_device *dev = intel_encoder->base.dev;
5117 struct intel_digital_port *intel_dig_port;
5118
5119 switch (intel_encoder->type) {
5120 case INTEL_OUTPUT_UNKNOWN:
5121 /* Only DDI platforms should ever use this output type */
5122 WARN_ON_ONCE(!HAS_DDI(dev));
5123 case INTEL_OUTPUT_DP:
5124 case INTEL_OUTPUT_HDMI:
5125 case INTEL_OUTPUT_EDP:
5126 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5127 return port_to_power_domain(intel_dig_port->port);
5128 case INTEL_OUTPUT_DP_MST:
5129 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5130 return port_to_power_domain(intel_dig_port->port);
5131 case INTEL_OUTPUT_ANALOG:
5132 return POWER_DOMAIN_PORT_CRT;
5133 case INTEL_OUTPUT_DSI:
5134 return POWER_DOMAIN_PORT_DSI;
5135 default:
5136 return POWER_DOMAIN_PORT_OTHER;
5137 }
5138 }
5139
5140 enum intel_display_power_domain
5141 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5142 {
5143 struct drm_device *dev = intel_encoder->base.dev;
5144 struct intel_digital_port *intel_dig_port;
5145
5146 switch (intel_encoder->type) {
5147 case INTEL_OUTPUT_UNKNOWN:
5148 case INTEL_OUTPUT_HDMI:
5149 /*
5150 * Only DDI platforms should ever use these output types.
5151 * We can get here after the HDMI detect code has already set
5152 * the type of the shared encoder. Since we can't be sure
5153 * what's the status of the given connectors, play safe and
5154 * run the DP detection too.
5155 */
5156 WARN_ON_ONCE(!HAS_DDI(dev));
5157 case INTEL_OUTPUT_DP:
5158 case INTEL_OUTPUT_EDP:
5159 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5160 return port_to_aux_power_domain(intel_dig_port->port);
5161 case INTEL_OUTPUT_DP_MST:
5162 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5163 return port_to_aux_power_domain(intel_dig_port->port);
5164 default:
5165 MISSING_CASE(intel_encoder->type);
5166 return POWER_DOMAIN_AUX_A;
5167 }
5168 }
5169
5170 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5171 struct intel_crtc_state *crtc_state)
5172 {
5173 struct drm_device *dev = crtc->dev;
5174 struct drm_encoder *encoder;
5175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5176 enum pipe pipe = intel_crtc->pipe;
5177 unsigned long mask;
5178 enum transcoder transcoder = crtc_state->cpu_transcoder;
5179
5180 if (!crtc_state->base.active)
5181 return 0;
5182
5183 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5184 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5185 if (crtc_state->pch_pfit.enabled ||
5186 crtc_state->pch_pfit.force_thru)
5187 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5188
5189 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5190 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5191
5192 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5193 }
5194
5195 if (crtc_state->shared_dpll)
5196 mask |= BIT(POWER_DOMAIN_PLLS);
5197
5198 return mask;
5199 }
5200
5201 static unsigned long
5202 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5203 struct intel_crtc_state *crtc_state)
5204 {
5205 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5207 enum intel_display_power_domain domain;
5208 unsigned long domains, new_domains, old_domains;
5209
5210 old_domains = intel_crtc->enabled_power_domains;
5211 intel_crtc->enabled_power_domains = new_domains =
5212 get_crtc_power_domains(crtc, crtc_state);
5213
5214 domains = new_domains & ~old_domains;
5215
5216 for_each_power_domain(domain, domains)
5217 intel_display_power_get(dev_priv, domain);
5218
5219 return old_domains & ~new_domains;
5220 }
5221
5222 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5223 unsigned long domains)
5224 {
5225 enum intel_display_power_domain domain;
5226
5227 for_each_power_domain(domain, domains)
5228 intel_display_power_put(dev_priv, domain);
5229 }
5230
5231 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5232 {
5233 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5234
5235 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5236 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5237 return max_cdclk_freq;
5238 else if (IS_CHERRYVIEW(dev_priv))
5239 return max_cdclk_freq*95/100;
5240 else if (INTEL_INFO(dev_priv)->gen < 4)
5241 return 2*max_cdclk_freq*90/100;
5242 else
5243 return max_cdclk_freq*90/100;
5244 }
5245
5246 static int skl_calc_cdclk(int max_pixclk, int vco);
5247
5248 static void intel_update_max_cdclk(struct drm_device *dev)
5249 {
5250 struct drm_i915_private *dev_priv = to_i915(dev);
5251
5252 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5253 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5254 int max_cdclk, vco;
5255
5256 vco = dev_priv->skl_preferred_vco_freq;
5257 WARN_ON(vco != 8100000 && vco != 8640000);
5258
5259 /*
5260 * Use the lower (vco 8640) cdclk values as a
5261 * first guess. skl_calc_cdclk() will correct it
5262 * if the preferred vco is 8100 instead.
5263 */
5264 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5265 max_cdclk = 617143;
5266 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5267 max_cdclk = 540000;
5268 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5269 max_cdclk = 432000;
5270 else
5271 max_cdclk = 308571;
5272
5273 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5274 } else if (IS_BROXTON(dev)) {
5275 dev_priv->max_cdclk_freq = 624000;
5276 } else if (IS_BROADWELL(dev)) {
5277 /*
5278 * FIXME with extra cooling we can allow
5279 * 540 MHz for ULX and 675 Mhz for ULT.
5280 * How can we know if extra cooling is
5281 * available? PCI ID, VTB, something else?
5282 */
5283 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5284 dev_priv->max_cdclk_freq = 450000;
5285 else if (IS_BDW_ULX(dev))
5286 dev_priv->max_cdclk_freq = 450000;
5287 else if (IS_BDW_ULT(dev))
5288 dev_priv->max_cdclk_freq = 540000;
5289 else
5290 dev_priv->max_cdclk_freq = 675000;
5291 } else if (IS_CHERRYVIEW(dev)) {
5292 dev_priv->max_cdclk_freq = 320000;
5293 } else if (IS_VALLEYVIEW(dev)) {
5294 dev_priv->max_cdclk_freq = 400000;
5295 } else {
5296 /* otherwise assume cdclk is fixed */
5297 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5298 }
5299
5300 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5301
5302 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5303 dev_priv->max_cdclk_freq);
5304
5305 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5306 dev_priv->max_dotclk_freq);
5307 }
5308
5309 static void intel_update_cdclk(struct drm_device *dev)
5310 {
5311 struct drm_i915_private *dev_priv = to_i915(dev);
5312
5313 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5314
5315 if (INTEL_GEN(dev_priv) >= 9)
5316 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5317 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5318 dev_priv->cdclk_pll.ref);
5319 else
5320 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5321 dev_priv->cdclk_freq);
5322
5323 /*
5324 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5325 * Programmng [sic] note: bit[9:2] should be programmed to the number
5326 * of cdclk that generates 4MHz reference clock freq which is used to
5327 * generate GMBus clock. This will vary with the cdclk freq.
5328 */
5329 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5330 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5331 }
5332
5333 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5334 static int skl_cdclk_decimal(int cdclk)
5335 {
5336 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5337 }
5338
5339 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5340 {
5341 int ratio;
5342
5343 if (cdclk == dev_priv->cdclk_pll.ref)
5344 return 0;
5345
5346 switch (cdclk) {
5347 default:
5348 MISSING_CASE(cdclk);
5349 case 144000:
5350 case 288000:
5351 case 384000:
5352 case 576000:
5353 ratio = 60;
5354 break;
5355 case 624000:
5356 ratio = 65;
5357 break;
5358 }
5359
5360 return dev_priv->cdclk_pll.ref * ratio;
5361 }
5362
5363 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5364 {
5365 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5366
5367 /* Timeout 200us */
5368 if (intel_wait_for_register(dev_priv,
5369 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5370 1))
5371 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5372
5373 dev_priv->cdclk_pll.vco = 0;
5374 }
5375
5376 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5377 {
5378 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5379 u32 val;
5380
5381 val = I915_READ(BXT_DE_PLL_CTL);
5382 val &= ~BXT_DE_PLL_RATIO_MASK;
5383 val |= BXT_DE_PLL_RATIO(ratio);
5384 I915_WRITE(BXT_DE_PLL_CTL, val);
5385
5386 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5387
5388 /* Timeout 200us */
5389 if (intel_wait_for_register(dev_priv,
5390 BXT_DE_PLL_ENABLE,
5391 BXT_DE_PLL_LOCK,
5392 BXT_DE_PLL_LOCK,
5393 1))
5394 DRM_ERROR("timeout waiting for DE PLL lock\n");
5395
5396 dev_priv->cdclk_pll.vco = vco;
5397 }
5398
5399 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5400 {
5401 u32 val, divider;
5402 int vco, ret;
5403
5404 vco = bxt_de_pll_vco(dev_priv, cdclk);
5405
5406 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5407
5408 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5409 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5410 case 8:
5411 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5412 break;
5413 case 4:
5414 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5415 break;
5416 case 3:
5417 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5418 break;
5419 case 2:
5420 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5421 break;
5422 default:
5423 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5424 WARN_ON(vco != 0);
5425
5426 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5427 break;
5428 }
5429
5430 /* Inform power controller of upcoming frequency change */
5431 mutex_lock(&dev_priv->rps.hw_lock);
5432 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5433 0x80000000);
5434 mutex_unlock(&dev_priv->rps.hw_lock);
5435
5436 if (ret) {
5437 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5438 ret, cdclk);
5439 return;
5440 }
5441
5442 if (dev_priv->cdclk_pll.vco != 0 &&
5443 dev_priv->cdclk_pll.vco != vco)
5444 bxt_de_pll_disable(dev_priv);
5445
5446 if (dev_priv->cdclk_pll.vco != vco)
5447 bxt_de_pll_enable(dev_priv, vco);
5448
5449 val = divider | skl_cdclk_decimal(cdclk);
5450 /*
5451 * FIXME if only the cd2x divider needs changing, it could be done
5452 * without shutting off the pipe (if only one pipe is active).
5453 */
5454 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5455 /*
5456 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5457 * enable otherwise.
5458 */
5459 if (cdclk >= 500000)
5460 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5461 I915_WRITE(CDCLK_CTL, val);
5462
5463 mutex_lock(&dev_priv->rps.hw_lock);
5464 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5465 DIV_ROUND_UP(cdclk, 25000));
5466 mutex_unlock(&dev_priv->rps.hw_lock);
5467
5468 if (ret) {
5469 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5470 ret, cdclk);
5471 return;
5472 }
5473
5474 intel_update_cdclk(&dev_priv->drm);
5475 }
5476
5477 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5478 {
5479 u32 cdctl, expected;
5480
5481 intel_update_cdclk(&dev_priv->drm);
5482
5483 if (dev_priv->cdclk_pll.vco == 0 ||
5484 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5485 goto sanitize;
5486
5487 /* DPLL okay; verify the cdclock
5488 *
5489 * Some BIOS versions leave an incorrect decimal frequency value and
5490 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5491 * so sanitize this register.
5492 */
5493 cdctl = I915_READ(CDCLK_CTL);
5494 /*
5495 * Let's ignore the pipe field, since BIOS could have configured the
5496 * dividers both synching to an active pipe, or asynchronously
5497 * (PIPE_NONE).
5498 */
5499 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5500
5501 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5502 skl_cdclk_decimal(dev_priv->cdclk_freq);
5503 /*
5504 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5505 * enable otherwise.
5506 */
5507 if (dev_priv->cdclk_freq >= 500000)
5508 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5509
5510 if (cdctl == expected)
5511 /* All well; nothing to sanitize */
5512 return;
5513
5514 sanitize:
5515 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5516
5517 /* force cdclk programming */
5518 dev_priv->cdclk_freq = 0;
5519
5520 /* force full PLL disable + enable */
5521 dev_priv->cdclk_pll.vco = -1;
5522 }
5523
5524 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5525 {
5526 bxt_sanitize_cdclk(dev_priv);
5527
5528 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5529 return;
5530
5531 /*
5532 * FIXME:
5533 * - The initial CDCLK needs to be read from VBT.
5534 * Need to make this change after VBT has changes for BXT.
5535 */
5536 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5537 }
5538
5539 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5540 {
5541 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5542 }
5543
5544 static int skl_calc_cdclk(int max_pixclk, int vco)
5545 {
5546 if (vco == 8640000) {
5547 if (max_pixclk > 540000)
5548 return 617143;
5549 else if (max_pixclk > 432000)
5550 return 540000;
5551 else if (max_pixclk > 308571)
5552 return 432000;
5553 else
5554 return 308571;
5555 } else {
5556 if (max_pixclk > 540000)
5557 return 675000;
5558 else if (max_pixclk > 450000)
5559 return 540000;
5560 else if (max_pixclk > 337500)
5561 return 450000;
5562 else
5563 return 337500;
5564 }
5565 }
5566
5567 static void
5568 skl_dpll0_update(struct drm_i915_private *dev_priv)
5569 {
5570 u32 val;
5571
5572 dev_priv->cdclk_pll.ref = 24000;
5573 dev_priv->cdclk_pll.vco = 0;
5574
5575 val = I915_READ(LCPLL1_CTL);
5576 if ((val & LCPLL_PLL_ENABLE) == 0)
5577 return;
5578
5579 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5580 return;
5581
5582 val = I915_READ(DPLL_CTRL1);
5583
5584 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5585 DPLL_CTRL1_SSC(SKL_DPLL0) |
5586 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5587 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5588 return;
5589
5590 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5591 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5592 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5593 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5594 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5595 dev_priv->cdclk_pll.vco = 8100000;
5596 break;
5597 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5598 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5599 dev_priv->cdclk_pll.vco = 8640000;
5600 break;
5601 default:
5602 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5603 break;
5604 }
5605 }
5606
5607 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5608 {
5609 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5610
5611 dev_priv->skl_preferred_vco_freq = vco;
5612
5613 if (changed)
5614 intel_update_max_cdclk(&dev_priv->drm);
5615 }
5616
5617 static void
5618 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5619 {
5620 int min_cdclk = skl_calc_cdclk(0, vco);
5621 u32 val;
5622
5623 WARN_ON(vco != 8100000 && vco != 8640000);
5624
5625 /* select the minimum CDCLK before enabling DPLL 0 */
5626 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5627 I915_WRITE(CDCLK_CTL, val);
5628 POSTING_READ(CDCLK_CTL);
5629
5630 /*
5631 * We always enable DPLL0 with the lowest link rate possible, but still
5632 * taking into account the VCO required to operate the eDP panel at the
5633 * desired frequency. The usual DP link rates operate with a VCO of
5634 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5635 * The modeset code is responsible for the selection of the exact link
5636 * rate later on, with the constraint of choosing a frequency that
5637 * works with vco.
5638 */
5639 val = I915_READ(DPLL_CTRL1);
5640
5641 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5642 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5643 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5644 if (vco == 8640000)
5645 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5646 SKL_DPLL0);
5647 else
5648 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5649 SKL_DPLL0);
5650
5651 I915_WRITE(DPLL_CTRL1, val);
5652 POSTING_READ(DPLL_CTRL1);
5653
5654 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5655
5656 if (intel_wait_for_register(dev_priv,
5657 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5658 5))
5659 DRM_ERROR("DPLL0 not locked\n");
5660
5661 dev_priv->cdclk_pll.vco = vco;
5662
5663 /* We'll want to keep using the current vco from now on. */
5664 skl_set_preferred_cdclk_vco(dev_priv, vco);
5665 }
5666
5667 static void
5668 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5669 {
5670 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5671 if (intel_wait_for_register(dev_priv,
5672 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
5673 1))
5674 DRM_ERROR("Couldn't disable DPLL0\n");
5675
5676 dev_priv->cdclk_pll.vco = 0;
5677 }
5678
5679 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5680 {
5681 int ret;
5682 u32 val;
5683
5684 /* inform PCU we want to change CDCLK */
5685 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5686 mutex_lock(&dev_priv->rps.hw_lock);
5687 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5688 mutex_unlock(&dev_priv->rps.hw_lock);
5689
5690 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5691 }
5692
5693 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5694 {
5695 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
5696 }
5697
5698 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5699 {
5700 struct drm_device *dev = &dev_priv->drm;
5701 u32 freq_select, pcu_ack;
5702
5703 WARN_ON((cdclk == 24000) != (vco == 0));
5704
5705 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5706
5707 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5708 DRM_ERROR("failed to inform PCU about cdclk change\n");
5709 return;
5710 }
5711
5712 /* set CDCLK_CTL */
5713 switch (cdclk) {
5714 case 450000:
5715 case 432000:
5716 freq_select = CDCLK_FREQ_450_432;
5717 pcu_ack = 1;
5718 break;
5719 case 540000:
5720 freq_select = CDCLK_FREQ_540;
5721 pcu_ack = 2;
5722 break;
5723 case 308571:
5724 case 337500:
5725 default:
5726 freq_select = CDCLK_FREQ_337_308;
5727 pcu_ack = 0;
5728 break;
5729 case 617143:
5730 case 675000:
5731 freq_select = CDCLK_FREQ_675_617;
5732 pcu_ack = 3;
5733 break;
5734 }
5735
5736 if (dev_priv->cdclk_pll.vco != 0 &&
5737 dev_priv->cdclk_pll.vco != vco)
5738 skl_dpll0_disable(dev_priv);
5739
5740 if (dev_priv->cdclk_pll.vco != vco)
5741 skl_dpll0_enable(dev_priv, vco);
5742
5743 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5744 POSTING_READ(CDCLK_CTL);
5745
5746 /* inform PCU of the change */
5747 mutex_lock(&dev_priv->rps.hw_lock);
5748 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5749 mutex_unlock(&dev_priv->rps.hw_lock);
5750
5751 intel_update_cdclk(dev);
5752 }
5753
5754 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5755
5756 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5757 {
5758 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5759 }
5760
5761 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5762 {
5763 int cdclk, vco;
5764
5765 skl_sanitize_cdclk(dev_priv);
5766
5767 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5768 /*
5769 * Use the current vco as our initial
5770 * guess as to what the preferred vco is.
5771 */
5772 if (dev_priv->skl_preferred_vco_freq == 0)
5773 skl_set_preferred_cdclk_vco(dev_priv,
5774 dev_priv->cdclk_pll.vco);
5775 return;
5776 }
5777
5778 vco = dev_priv->skl_preferred_vco_freq;
5779 if (vco == 0)
5780 vco = 8100000;
5781 cdclk = skl_calc_cdclk(0, vco);
5782
5783 skl_set_cdclk(dev_priv, cdclk, vco);
5784 }
5785
5786 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5787 {
5788 uint32_t cdctl, expected;
5789
5790 /*
5791 * check if the pre-os intialized the display
5792 * There is SWF18 scratchpad register defined which is set by the
5793 * pre-os which can be used by the OS drivers to check the status
5794 */
5795 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5796 goto sanitize;
5797
5798 intel_update_cdclk(&dev_priv->drm);
5799 /* Is PLL enabled and locked ? */
5800 if (dev_priv->cdclk_pll.vco == 0 ||
5801 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5802 goto sanitize;
5803
5804 /* DPLL okay; verify the cdclock
5805 *
5806 * Noticed in some instances that the freq selection is correct but
5807 * decimal part is programmed wrong from BIOS where pre-os does not
5808 * enable display. Verify the same as well.
5809 */
5810 cdctl = I915_READ(CDCLK_CTL);
5811 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5812 skl_cdclk_decimal(dev_priv->cdclk_freq);
5813 if (cdctl == expected)
5814 /* All well; nothing to sanitize */
5815 return;
5816
5817 sanitize:
5818 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5819
5820 /* force cdclk programming */
5821 dev_priv->cdclk_freq = 0;
5822 /* force full PLL disable + enable */
5823 dev_priv->cdclk_pll.vco = -1;
5824 }
5825
5826 /* Adjust CDclk dividers to allow high res or save power if possible */
5827 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5828 {
5829 struct drm_i915_private *dev_priv = to_i915(dev);
5830 u32 val, cmd;
5831
5832 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5833 != dev_priv->cdclk_freq);
5834
5835 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5836 cmd = 2;
5837 else if (cdclk == 266667)
5838 cmd = 1;
5839 else
5840 cmd = 0;
5841
5842 mutex_lock(&dev_priv->rps.hw_lock);
5843 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5844 val &= ~DSPFREQGUAR_MASK;
5845 val |= (cmd << DSPFREQGUAR_SHIFT);
5846 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5847 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5848 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5849 50)) {
5850 DRM_ERROR("timed out waiting for CDclk change\n");
5851 }
5852 mutex_unlock(&dev_priv->rps.hw_lock);
5853
5854 mutex_lock(&dev_priv->sb_lock);
5855
5856 if (cdclk == 400000) {
5857 u32 divider;
5858
5859 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5860
5861 /* adjust cdclk divider */
5862 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5863 val &= ~CCK_FREQUENCY_VALUES;
5864 val |= divider;
5865 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5866
5867 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5868 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5869 50))
5870 DRM_ERROR("timed out waiting for CDclk change\n");
5871 }
5872
5873 /* adjust self-refresh exit latency value */
5874 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5875 val &= ~0x7f;
5876
5877 /*
5878 * For high bandwidth configs, we set a higher latency in the bunit
5879 * so that the core display fetch happens in time to avoid underruns.
5880 */
5881 if (cdclk == 400000)
5882 val |= 4500 / 250; /* 4.5 usec */
5883 else
5884 val |= 3000 / 250; /* 3.0 usec */
5885 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5886
5887 mutex_unlock(&dev_priv->sb_lock);
5888
5889 intel_update_cdclk(dev);
5890 }
5891
5892 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5893 {
5894 struct drm_i915_private *dev_priv = to_i915(dev);
5895 u32 val, cmd;
5896
5897 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5898 != dev_priv->cdclk_freq);
5899
5900 switch (cdclk) {
5901 case 333333:
5902 case 320000:
5903 case 266667:
5904 case 200000:
5905 break;
5906 default:
5907 MISSING_CASE(cdclk);
5908 return;
5909 }
5910
5911 /*
5912 * Specs are full of misinformation, but testing on actual
5913 * hardware has shown that we just need to write the desired
5914 * CCK divider into the Punit register.
5915 */
5916 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5917
5918 mutex_lock(&dev_priv->rps.hw_lock);
5919 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5920 val &= ~DSPFREQGUAR_MASK_CHV;
5921 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5922 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5923 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5924 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5925 50)) {
5926 DRM_ERROR("timed out waiting for CDclk change\n");
5927 }
5928 mutex_unlock(&dev_priv->rps.hw_lock);
5929
5930 intel_update_cdclk(dev);
5931 }
5932
5933 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5934 int max_pixclk)
5935 {
5936 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5937 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5938
5939 /*
5940 * Really only a few cases to deal with, as only 4 CDclks are supported:
5941 * 200MHz
5942 * 267MHz
5943 * 320/333MHz (depends on HPLL freq)
5944 * 400MHz (VLV only)
5945 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5946 * of the lower bin and adjust if needed.
5947 *
5948 * We seem to get an unstable or solid color picture at 200MHz.
5949 * Not sure what's wrong. For now use 200MHz only when all pipes
5950 * are off.
5951 */
5952 if (!IS_CHERRYVIEW(dev_priv) &&
5953 max_pixclk > freq_320*limit/100)
5954 return 400000;
5955 else if (max_pixclk > 266667*limit/100)
5956 return freq_320;
5957 else if (max_pixclk > 0)
5958 return 266667;
5959 else
5960 return 200000;
5961 }
5962
5963 static int bxt_calc_cdclk(int max_pixclk)
5964 {
5965 if (max_pixclk > 576000)
5966 return 624000;
5967 else if (max_pixclk > 384000)
5968 return 576000;
5969 else if (max_pixclk > 288000)
5970 return 384000;
5971 else if (max_pixclk > 144000)
5972 return 288000;
5973 else
5974 return 144000;
5975 }
5976
5977 /* Compute the max pixel clock for new configuration. */
5978 static int intel_mode_max_pixclk(struct drm_device *dev,
5979 struct drm_atomic_state *state)
5980 {
5981 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5982 struct drm_i915_private *dev_priv = to_i915(dev);
5983 struct drm_crtc *crtc;
5984 struct drm_crtc_state *crtc_state;
5985 unsigned max_pixclk = 0, i;
5986 enum pipe pipe;
5987
5988 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5989 sizeof(intel_state->min_pixclk));
5990
5991 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5992 int pixclk = 0;
5993
5994 if (crtc_state->enable)
5995 pixclk = crtc_state->adjusted_mode.crtc_clock;
5996
5997 intel_state->min_pixclk[i] = pixclk;
5998 }
5999
6000 for_each_pipe(dev_priv, pipe)
6001 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6002
6003 return max_pixclk;
6004 }
6005
6006 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6007 {
6008 struct drm_device *dev = state->dev;
6009 struct drm_i915_private *dev_priv = to_i915(dev);
6010 int max_pixclk = intel_mode_max_pixclk(dev, state);
6011 struct intel_atomic_state *intel_state =
6012 to_intel_atomic_state(state);
6013
6014 intel_state->cdclk = intel_state->dev_cdclk =
6015 valleyview_calc_cdclk(dev_priv, max_pixclk);
6016
6017 if (!intel_state->active_crtcs)
6018 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6019
6020 return 0;
6021 }
6022
6023 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6024 {
6025 int max_pixclk = ilk_max_pixel_rate(state);
6026 struct intel_atomic_state *intel_state =
6027 to_intel_atomic_state(state);
6028
6029 intel_state->cdclk = intel_state->dev_cdclk =
6030 bxt_calc_cdclk(max_pixclk);
6031
6032 if (!intel_state->active_crtcs)
6033 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6034
6035 return 0;
6036 }
6037
6038 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6039 {
6040 unsigned int credits, default_credits;
6041
6042 if (IS_CHERRYVIEW(dev_priv))
6043 default_credits = PFI_CREDIT(12);
6044 else
6045 default_credits = PFI_CREDIT(8);
6046
6047 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6048 /* CHV suggested value is 31 or 63 */
6049 if (IS_CHERRYVIEW(dev_priv))
6050 credits = PFI_CREDIT_63;
6051 else
6052 credits = PFI_CREDIT(15);
6053 } else {
6054 credits = default_credits;
6055 }
6056
6057 /*
6058 * WA - write default credits before re-programming
6059 * FIXME: should we also set the resend bit here?
6060 */
6061 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6062 default_credits);
6063
6064 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6065 credits | PFI_CREDIT_RESEND);
6066
6067 /*
6068 * FIXME is this guaranteed to clear
6069 * immediately or should we poll for it?
6070 */
6071 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6072 }
6073
6074 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6075 {
6076 struct drm_device *dev = old_state->dev;
6077 struct drm_i915_private *dev_priv = to_i915(dev);
6078 struct intel_atomic_state *old_intel_state =
6079 to_intel_atomic_state(old_state);
6080 unsigned req_cdclk = old_intel_state->dev_cdclk;
6081
6082 /*
6083 * FIXME: We can end up here with all power domains off, yet
6084 * with a CDCLK frequency other than the minimum. To account
6085 * for this take the PIPE-A power domain, which covers the HW
6086 * blocks needed for the following programming. This can be
6087 * removed once it's guaranteed that we get here either with
6088 * the minimum CDCLK set, or the required power domains
6089 * enabled.
6090 */
6091 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6092
6093 if (IS_CHERRYVIEW(dev))
6094 cherryview_set_cdclk(dev, req_cdclk);
6095 else
6096 valleyview_set_cdclk(dev, req_cdclk);
6097
6098 vlv_program_pfi_credits(dev_priv);
6099
6100 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6101 }
6102
6103 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6104 {
6105 struct drm_device *dev = crtc->dev;
6106 struct drm_i915_private *dev_priv = to_i915(dev);
6107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6108 struct intel_encoder *encoder;
6109 struct intel_crtc_state *pipe_config =
6110 to_intel_crtc_state(crtc->state);
6111 int pipe = intel_crtc->pipe;
6112
6113 if (WARN_ON(intel_crtc->active))
6114 return;
6115
6116 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6117 intel_dp_set_m_n(intel_crtc, M1_N1);
6118
6119 intel_set_pipe_timings(intel_crtc);
6120 intel_set_pipe_src_size(intel_crtc);
6121
6122 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6123 struct drm_i915_private *dev_priv = to_i915(dev);
6124
6125 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6126 I915_WRITE(CHV_CANVAS(pipe), 0);
6127 }
6128
6129 i9xx_set_pipeconf(intel_crtc);
6130
6131 intel_crtc->active = true;
6132
6133 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6134
6135 for_each_encoder_on_crtc(dev, crtc, encoder)
6136 if (encoder->pre_pll_enable)
6137 encoder->pre_pll_enable(encoder);
6138
6139 if (IS_CHERRYVIEW(dev)) {
6140 chv_prepare_pll(intel_crtc, intel_crtc->config);
6141 chv_enable_pll(intel_crtc, intel_crtc->config);
6142 } else {
6143 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6144 vlv_enable_pll(intel_crtc, intel_crtc->config);
6145 }
6146
6147 for_each_encoder_on_crtc(dev, crtc, encoder)
6148 if (encoder->pre_enable)
6149 encoder->pre_enable(encoder);
6150
6151 i9xx_pfit_enable(intel_crtc);
6152
6153 intel_color_load_luts(&pipe_config->base);
6154
6155 intel_update_watermarks(crtc);
6156 intel_enable_pipe(intel_crtc);
6157
6158 assert_vblank_disabled(crtc);
6159 drm_crtc_vblank_on(crtc);
6160
6161 for_each_encoder_on_crtc(dev, crtc, encoder)
6162 encoder->enable(encoder);
6163 }
6164
6165 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6166 {
6167 struct drm_device *dev = crtc->base.dev;
6168 struct drm_i915_private *dev_priv = to_i915(dev);
6169
6170 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6171 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6172 }
6173
6174 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6175 {
6176 struct drm_device *dev = crtc->dev;
6177 struct drm_i915_private *dev_priv = to_i915(dev);
6178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6179 struct intel_encoder *encoder;
6180 struct intel_crtc_state *pipe_config =
6181 to_intel_crtc_state(crtc->state);
6182 enum pipe pipe = intel_crtc->pipe;
6183
6184 if (WARN_ON(intel_crtc->active))
6185 return;
6186
6187 i9xx_set_pll_dividers(intel_crtc);
6188
6189 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6190 intel_dp_set_m_n(intel_crtc, M1_N1);
6191
6192 intel_set_pipe_timings(intel_crtc);
6193 intel_set_pipe_src_size(intel_crtc);
6194
6195 i9xx_set_pipeconf(intel_crtc);
6196
6197 intel_crtc->active = true;
6198
6199 if (!IS_GEN2(dev))
6200 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6201
6202 for_each_encoder_on_crtc(dev, crtc, encoder)
6203 if (encoder->pre_enable)
6204 encoder->pre_enable(encoder);
6205
6206 i9xx_enable_pll(intel_crtc);
6207
6208 i9xx_pfit_enable(intel_crtc);
6209
6210 intel_color_load_luts(&pipe_config->base);
6211
6212 intel_update_watermarks(crtc);
6213 intel_enable_pipe(intel_crtc);
6214
6215 assert_vblank_disabled(crtc);
6216 drm_crtc_vblank_on(crtc);
6217
6218 for_each_encoder_on_crtc(dev, crtc, encoder)
6219 encoder->enable(encoder);
6220 }
6221
6222 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6223 {
6224 struct drm_device *dev = crtc->base.dev;
6225 struct drm_i915_private *dev_priv = to_i915(dev);
6226
6227 if (!crtc->config->gmch_pfit.control)
6228 return;
6229
6230 assert_pipe_disabled(dev_priv, crtc->pipe);
6231
6232 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6233 I915_READ(PFIT_CONTROL));
6234 I915_WRITE(PFIT_CONTROL, 0);
6235 }
6236
6237 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6238 {
6239 struct drm_device *dev = crtc->dev;
6240 struct drm_i915_private *dev_priv = to_i915(dev);
6241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6242 struct intel_encoder *encoder;
6243 int pipe = intel_crtc->pipe;
6244
6245 /*
6246 * On gen2 planes are double buffered but the pipe isn't, so we must
6247 * wait for planes to fully turn off before disabling the pipe.
6248 */
6249 if (IS_GEN2(dev))
6250 intel_wait_for_vblank(dev, pipe);
6251
6252 for_each_encoder_on_crtc(dev, crtc, encoder)
6253 encoder->disable(encoder);
6254
6255 drm_crtc_vblank_off(crtc);
6256 assert_vblank_disabled(crtc);
6257
6258 intel_disable_pipe(intel_crtc);
6259
6260 i9xx_pfit_disable(intel_crtc);
6261
6262 for_each_encoder_on_crtc(dev, crtc, encoder)
6263 if (encoder->post_disable)
6264 encoder->post_disable(encoder);
6265
6266 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6267 if (IS_CHERRYVIEW(dev))
6268 chv_disable_pll(dev_priv, pipe);
6269 else if (IS_VALLEYVIEW(dev))
6270 vlv_disable_pll(dev_priv, pipe);
6271 else
6272 i9xx_disable_pll(intel_crtc);
6273 }
6274
6275 for_each_encoder_on_crtc(dev, crtc, encoder)
6276 if (encoder->post_pll_disable)
6277 encoder->post_pll_disable(encoder);
6278
6279 if (!IS_GEN2(dev))
6280 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6281 }
6282
6283 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6284 {
6285 struct intel_encoder *encoder;
6286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6287 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6288 enum intel_display_power_domain domain;
6289 unsigned long domains;
6290
6291 if (!intel_crtc->active)
6292 return;
6293
6294 if (to_intel_plane_state(crtc->primary->state)->visible) {
6295 WARN_ON(intel_crtc->flip_work);
6296
6297 intel_pre_disable_primary_noatomic(crtc);
6298
6299 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6300 to_intel_plane_state(crtc->primary->state)->visible = false;
6301 }
6302
6303 dev_priv->display.crtc_disable(crtc);
6304
6305 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6306 crtc->base.id, crtc->name);
6307
6308 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6309 crtc->state->active = false;
6310 intel_crtc->active = false;
6311 crtc->enabled = false;
6312 crtc->state->connector_mask = 0;
6313 crtc->state->encoder_mask = 0;
6314
6315 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6316 encoder->base.crtc = NULL;
6317
6318 intel_fbc_disable(intel_crtc);
6319 intel_update_watermarks(crtc);
6320 intel_disable_shared_dpll(intel_crtc);
6321
6322 domains = intel_crtc->enabled_power_domains;
6323 for_each_power_domain(domain, domains)
6324 intel_display_power_put(dev_priv, domain);
6325 intel_crtc->enabled_power_domains = 0;
6326
6327 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6328 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6329 }
6330
6331 /*
6332 * turn all crtc's off, but do not adjust state
6333 * This has to be paired with a call to intel_modeset_setup_hw_state.
6334 */
6335 int intel_display_suspend(struct drm_device *dev)
6336 {
6337 struct drm_i915_private *dev_priv = to_i915(dev);
6338 struct drm_atomic_state *state;
6339 int ret;
6340
6341 state = drm_atomic_helper_suspend(dev);
6342 ret = PTR_ERR_OR_ZERO(state);
6343 if (ret)
6344 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6345 else
6346 dev_priv->modeset_restore_state = state;
6347 return ret;
6348 }
6349
6350 void intel_encoder_destroy(struct drm_encoder *encoder)
6351 {
6352 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6353
6354 drm_encoder_cleanup(encoder);
6355 kfree(intel_encoder);
6356 }
6357
6358 /* Cross check the actual hw state with our own modeset state tracking (and it's
6359 * internal consistency). */
6360 static void intel_connector_verify_state(struct intel_connector *connector)
6361 {
6362 struct drm_crtc *crtc = connector->base.state->crtc;
6363
6364 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6365 connector->base.base.id,
6366 connector->base.name);
6367
6368 if (connector->get_hw_state(connector)) {
6369 struct intel_encoder *encoder = connector->encoder;
6370 struct drm_connector_state *conn_state = connector->base.state;
6371
6372 I915_STATE_WARN(!crtc,
6373 "connector enabled without attached crtc\n");
6374
6375 if (!crtc)
6376 return;
6377
6378 I915_STATE_WARN(!crtc->state->active,
6379 "connector is active, but attached crtc isn't\n");
6380
6381 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6382 return;
6383
6384 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6385 "atomic encoder doesn't match attached encoder\n");
6386
6387 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6388 "attached encoder crtc differs from connector crtc\n");
6389 } else {
6390 I915_STATE_WARN(crtc && crtc->state->active,
6391 "attached crtc is active, but connector isn't\n");
6392 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6393 "best encoder set without crtc!\n");
6394 }
6395 }
6396
6397 int intel_connector_init(struct intel_connector *connector)
6398 {
6399 drm_atomic_helper_connector_reset(&connector->base);
6400
6401 if (!connector->base.state)
6402 return -ENOMEM;
6403
6404 return 0;
6405 }
6406
6407 struct intel_connector *intel_connector_alloc(void)
6408 {
6409 struct intel_connector *connector;
6410
6411 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6412 if (!connector)
6413 return NULL;
6414
6415 if (intel_connector_init(connector) < 0) {
6416 kfree(connector);
6417 return NULL;
6418 }
6419
6420 return connector;
6421 }
6422
6423 /* Simple connector->get_hw_state implementation for encoders that support only
6424 * one connector and no cloning and hence the encoder state determines the state
6425 * of the connector. */
6426 bool intel_connector_get_hw_state(struct intel_connector *connector)
6427 {
6428 enum pipe pipe = 0;
6429 struct intel_encoder *encoder = connector->encoder;
6430
6431 return encoder->get_hw_state(encoder, &pipe);
6432 }
6433
6434 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6435 {
6436 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6437 return crtc_state->fdi_lanes;
6438
6439 return 0;
6440 }
6441
6442 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6443 struct intel_crtc_state *pipe_config)
6444 {
6445 struct drm_atomic_state *state = pipe_config->base.state;
6446 struct intel_crtc *other_crtc;
6447 struct intel_crtc_state *other_crtc_state;
6448
6449 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6451 if (pipe_config->fdi_lanes > 4) {
6452 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6453 pipe_name(pipe), pipe_config->fdi_lanes);
6454 return -EINVAL;
6455 }
6456
6457 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6458 if (pipe_config->fdi_lanes > 2) {
6459 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6460 pipe_config->fdi_lanes);
6461 return -EINVAL;
6462 } else {
6463 return 0;
6464 }
6465 }
6466
6467 if (INTEL_INFO(dev)->num_pipes == 2)
6468 return 0;
6469
6470 /* Ivybridge 3 pipe is really complicated */
6471 switch (pipe) {
6472 case PIPE_A:
6473 return 0;
6474 case PIPE_B:
6475 if (pipe_config->fdi_lanes <= 2)
6476 return 0;
6477
6478 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6479 other_crtc_state =
6480 intel_atomic_get_crtc_state(state, other_crtc);
6481 if (IS_ERR(other_crtc_state))
6482 return PTR_ERR(other_crtc_state);
6483
6484 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6485 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6486 pipe_name(pipe), pipe_config->fdi_lanes);
6487 return -EINVAL;
6488 }
6489 return 0;
6490 case PIPE_C:
6491 if (pipe_config->fdi_lanes > 2) {
6492 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6493 pipe_name(pipe), pipe_config->fdi_lanes);
6494 return -EINVAL;
6495 }
6496
6497 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6498 other_crtc_state =
6499 intel_atomic_get_crtc_state(state, other_crtc);
6500 if (IS_ERR(other_crtc_state))
6501 return PTR_ERR(other_crtc_state);
6502
6503 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6504 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6505 return -EINVAL;
6506 }
6507 return 0;
6508 default:
6509 BUG();
6510 }
6511 }
6512
6513 #define RETRY 1
6514 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6515 struct intel_crtc_state *pipe_config)
6516 {
6517 struct drm_device *dev = intel_crtc->base.dev;
6518 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6519 int lane, link_bw, fdi_dotclock, ret;
6520 bool needs_recompute = false;
6521
6522 retry:
6523 /* FDI is a binary signal running at ~2.7GHz, encoding
6524 * each output octet as 10 bits. The actual frequency
6525 * is stored as a divider into a 100MHz clock, and the
6526 * mode pixel clock is stored in units of 1KHz.
6527 * Hence the bw of each lane in terms of the mode signal
6528 * is:
6529 */
6530 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6531
6532 fdi_dotclock = adjusted_mode->crtc_clock;
6533
6534 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6535 pipe_config->pipe_bpp);
6536
6537 pipe_config->fdi_lanes = lane;
6538
6539 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6540 link_bw, &pipe_config->fdi_m_n);
6541
6542 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6543 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6544 pipe_config->pipe_bpp -= 2*3;
6545 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6546 pipe_config->pipe_bpp);
6547 needs_recompute = true;
6548 pipe_config->bw_constrained = true;
6549
6550 goto retry;
6551 }
6552
6553 if (needs_recompute)
6554 return RETRY;
6555
6556 return ret;
6557 }
6558
6559 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6560 struct intel_crtc_state *pipe_config)
6561 {
6562 if (pipe_config->pipe_bpp > 24)
6563 return false;
6564
6565 /* HSW can handle pixel rate up to cdclk? */
6566 if (IS_HASWELL(dev_priv))
6567 return true;
6568
6569 /*
6570 * We compare against max which means we must take
6571 * the increased cdclk requirement into account when
6572 * calculating the new cdclk.
6573 *
6574 * Should measure whether using a lower cdclk w/o IPS
6575 */
6576 return ilk_pipe_pixel_rate(pipe_config) <=
6577 dev_priv->max_cdclk_freq * 95 / 100;
6578 }
6579
6580 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6581 struct intel_crtc_state *pipe_config)
6582 {
6583 struct drm_device *dev = crtc->base.dev;
6584 struct drm_i915_private *dev_priv = to_i915(dev);
6585
6586 pipe_config->ips_enabled = i915.enable_ips &&
6587 hsw_crtc_supports_ips(crtc) &&
6588 pipe_config_supports_ips(dev_priv, pipe_config);
6589 }
6590
6591 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6592 {
6593 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6594
6595 /* GDG double wide on either pipe, otherwise pipe A only */
6596 return INTEL_INFO(dev_priv)->gen < 4 &&
6597 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6598 }
6599
6600 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6601 struct intel_crtc_state *pipe_config)
6602 {
6603 struct drm_device *dev = crtc->base.dev;
6604 struct drm_i915_private *dev_priv = to_i915(dev);
6605 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6606 int clock_limit = dev_priv->max_dotclk_freq;
6607
6608 if (INTEL_INFO(dev)->gen < 4) {
6609 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6610
6611 /*
6612 * Enable double wide mode when the dot clock
6613 * is > 90% of the (display) core speed.
6614 */
6615 if (intel_crtc_supports_double_wide(crtc) &&
6616 adjusted_mode->crtc_clock > clock_limit) {
6617 clock_limit = dev_priv->max_dotclk_freq;
6618 pipe_config->double_wide = true;
6619 }
6620 }
6621
6622 if (adjusted_mode->crtc_clock > clock_limit) {
6623 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6624 adjusted_mode->crtc_clock, clock_limit,
6625 yesno(pipe_config->double_wide));
6626 return -EINVAL;
6627 }
6628
6629 /*
6630 * Pipe horizontal size must be even in:
6631 * - DVO ganged mode
6632 * - LVDS dual channel mode
6633 * - Double wide pipe
6634 */
6635 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6636 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6637 pipe_config->pipe_src_w &= ~1;
6638
6639 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6640 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6641 */
6642 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6643 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6644 return -EINVAL;
6645
6646 if (HAS_IPS(dev))
6647 hsw_compute_ips_config(crtc, pipe_config);
6648
6649 if (pipe_config->has_pch_encoder)
6650 return ironlake_fdi_compute_config(crtc, pipe_config);
6651
6652 return 0;
6653 }
6654
6655 static int skylake_get_display_clock_speed(struct drm_device *dev)
6656 {
6657 struct drm_i915_private *dev_priv = to_i915(dev);
6658 uint32_t cdctl;
6659
6660 skl_dpll0_update(dev_priv);
6661
6662 if (dev_priv->cdclk_pll.vco == 0)
6663 return dev_priv->cdclk_pll.ref;
6664
6665 cdctl = I915_READ(CDCLK_CTL);
6666
6667 if (dev_priv->cdclk_pll.vco == 8640000) {
6668 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6669 case CDCLK_FREQ_450_432:
6670 return 432000;
6671 case CDCLK_FREQ_337_308:
6672 return 308571;
6673 case CDCLK_FREQ_540:
6674 return 540000;
6675 case CDCLK_FREQ_675_617:
6676 return 617143;
6677 default:
6678 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6679 }
6680 } else {
6681 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6682 case CDCLK_FREQ_450_432:
6683 return 450000;
6684 case CDCLK_FREQ_337_308:
6685 return 337500;
6686 case CDCLK_FREQ_540:
6687 return 540000;
6688 case CDCLK_FREQ_675_617:
6689 return 675000;
6690 default:
6691 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6692 }
6693 }
6694
6695 return dev_priv->cdclk_pll.ref;
6696 }
6697
6698 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6699 {
6700 u32 val;
6701
6702 dev_priv->cdclk_pll.ref = 19200;
6703 dev_priv->cdclk_pll.vco = 0;
6704
6705 val = I915_READ(BXT_DE_PLL_ENABLE);
6706 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6707 return;
6708
6709 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6710 return;
6711
6712 val = I915_READ(BXT_DE_PLL_CTL);
6713 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6714 dev_priv->cdclk_pll.ref;
6715 }
6716
6717 static int broxton_get_display_clock_speed(struct drm_device *dev)
6718 {
6719 struct drm_i915_private *dev_priv = to_i915(dev);
6720 u32 divider;
6721 int div, vco;
6722
6723 bxt_de_pll_update(dev_priv);
6724
6725 vco = dev_priv->cdclk_pll.vco;
6726 if (vco == 0)
6727 return dev_priv->cdclk_pll.ref;
6728
6729 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6730
6731 switch (divider) {
6732 case BXT_CDCLK_CD2X_DIV_SEL_1:
6733 div = 2;
6734 break;
6735 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6736 div = 3;
6737 break;
6738 case BXT_CDCLK_CD2X_DIV_SEL_2:
6739 div = 4;
6740 break;
6741 case BXT_CDCLK_CD2X_DIV_SEL_4:
6742 div = 8;
6743 break;
6744 default:
6745 MISSING_CASE(divider);
6746 return dev_priv->cdclk_pll.ref;
6747 }
6748
6749 return DIV_ROUND_CLOSEST(vco, div);
6750 }
6751
6752 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6753 {
6754 struct drm_i915_private *dev_priv = to_i915(dev);
6755 uint32_t lcpll = I915_READ(LCPLL_CTL);
6756 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6757
6758 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6759 return 800000;
6760 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6761 return 450000;
6762 else if (freq == LCPLL_CLK_FREQ_450)
6763 return 450000;
6764 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6765 return 540000;
6766 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6767 return 337500;
6768 else
6769 return 675000;
6770 }
6771
6772 static int haswell_get_display_clock_speed(struct drm_device *dev)
6773 {
6774 struct drm_i915_private *dev_priv = to_i915(dev);
6775 uint32_t lcpll = I915_READ(LCPLL_CTL);
6776 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6777
6778 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6779 return 800000;
6780 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6781 return 450000;
6782 else if (freq == LCPLL_CLK_FREQ_450)
6783 return 450000;
6784 else if (IS_HSW_ULT(dev))
6785 return 337500;
6786 else
6787 return 540000;
6788 }
6789
6790 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6791 {
6792 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6793 CCK_DISPLAY_CLOCK_CONTROL);
6794 }
6795
6796 static int ilk_get_display_clock_speed(struct drm_device *dev)
6797 {
6798 return 450000;
6799 }
6800
6801 static int i945_get_display_clock_speed(struct drm_device *dev)
6802 {
6803 return 400000;
6804 }
6805
6806 static int i915_get_display_clock_speed(struct drm_device *dev)
6807 {
6808 return 333333;
6809 }
6810
6811 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6812 {
6813 return 200000;
6814 }
6815
6816 static int pnv_get_display_clock_speed(struct drm_device *dev)
6817 {
6818 u16 gcfgc = 0;
6819
6820 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6821
6822 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6823 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6824 return 266667;
6825 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6826 return 333333;
6827 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6828 return 444444;
6829 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6830 return 200000;
6831 default:
6832 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6833 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6834 return 133333;
6835 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6836 return 166667;
6837 }
6838 }
6839
6840 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6841 {
6842 u16 gcfgc = 0;
6843
6844 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6845
6846 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6847 return 133333;
6848 else {
6849 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6850 case GC_DISPLAY_CLOCK_333_MHZ:
6851 return 333333;
6852 default:
6853 case GC_DISPLAY_CLOCK_190_200_MHZ:
6854 return 190000;
6855 }
6856 }
6857 }
6858
6859 static int i865_get_display_clock_speed(struct drm_device *dev)
6860 {
6861 return 266667;
6862 }
6863
6864 static int i85x_get_display_clock_speed(struct drm_device *dev)
6865 {
6866 u16 hpllcc = 0;
6867
6868 /*
6869 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6870 * encoding is different :(
6871 * FIXME is this the right way to detect 852GM/852GMV?
6872 */
6873 if (dev->pdev->revision == 0x1)
6874 return 133333;
6875
6876 pci_bus_read_config_word(dev->pdev->bus,
6877 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6878
6879 /* Assume that the hardware is in the high speed state. This
6880 * should be the default.
6881 */
6882 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6883 case GC_CLOCK_133_200:
6884 case GC_CLOCK_133_200_2:
6885 case GC_CLOCK_100_200:
6886 return 200000;
6887 case GC_CLOCK_166_250:
6888 return 250000;
6889 case GC_CLOCK_100_133:
6890 return 133333;
6891 case GC_CLOCK_133_266:
6892 case GC_CLOCK_133_266_2:
6893 case GC_CLOCK_166_266:
6894 return 266667;
6895 }
6896
6897 /* Shouldn't happen */
6898 return 0;
6899 }
6900
6901 static int i830_get_display_clock_speed(struct drm_device *dev)
6902 {
6903 return 133333;
6904 }
6905
6906 static unsigned int intel_hpll_vco(struct drm_device *dev)
6907 {
6908 struct drm_i915_private *dev_priv = to_i915(dev);
6909 static const unsigned int blb_vco[8] = {
6910 [0] = 3200000,
6911 [1] = 4000000,
6912 [2] = 5333333,
6913 [3] = 4800000,
6914 [4] = 6400000,
6915 };
6916 static const unsigned int pnv_vco[8] = {
6917 [0] = 3200000,
6918 [1] = 4000000,
6919 [2] = 5333333,
6920 [3] = 4800000,
6921 [4] = 2666667,
6922 };
6923 static const unsigned int cl_vco[8] = {
6924 [0] = 3200000,
6925 [1] = 4000000,
6926 [2] = 5333333,
6927 [3] = 6400000,
6928 [4] = 3333333,
6929 [5] = 3566667,
6930 [6] = 4266667,
6931 };
6932 static const unsigned int elk_vco[8] = {
6933 [0] = 3200000,
6934 [1] = 4000000,
6935 [2] = 5333333,
6936 [3] = 4800000,
6937 };
6938 static const unsigned int ctg_vco[8] = {
6939 [0] = 3200000,
6940 [1] = 4000000,
6941 [2] = 5333333,
6942 [3] = 6400000,
6943 [4] = 2666667,
6944 [5] = 4266667,
6945 };
6946 const unsigned int *vco_table;
6947 unsigned int vco;
6948 uint8_t tmp = 0;
6949
6950 /* FIXME other chipsets? */
6951 if (IS_GM45(dev))
6952 vco_table = ctg_vco;
6953 else if (IS_G4X(dev))
6954 vco_table = elk_vco;
6955 else if (IS_CRESTLINE(dev))
6956 vco_table = cl_vco;
6957 else if (IS_PINEVIEW(dev))
6958 vco_table = pnv_vco;
6959 else if (IS_G33(dev))
6960 vco_table = blb_vco;
6961 else
6962 return 0;
6963
6964 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6965
6966 vco = vco_table[tmp & 0x7];
6967 if (vco == 0)
6968 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6969 else
6970 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6971
6972 return vco;
6973 }
6974
6975 static int gm45_get_display_clock_speed(struct drm_device *dev)
6976 {
6977 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6978 uint16_t tmp = 0;
6979
6980 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6981
6982 cdclk_sel = (tmp >> 12) & 0x1;
6983
6984 switch (vco) {
6985 case 2666667:
6986 case 4000000:
6987 case 5333333:
6988 return cdclk_sel ? 333333 : 222222;
6989 case 3200000:
6990 return cdclk_sel ? 320000 : 228571;
6991 default:
6992 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6993 return 222222;
6994 }
6995 }
6996
6997 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6998 {
6999 static const uint8_t div_3200[] = { 16, 10, 8 };
7000 static const uint8_t div_4000[] = { 20, 12, 10 };
7001 static const uint8_t div_5333[] = { 24, 16, 14 };
7002 const uint8_t *div_table;
7003 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7004 uint16_t tmp = 0;
7005
7006 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7007
7008 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7009
7010 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7011 goto fail;
7012
7013 switch (vco) {
7014 case 3200000:
7015 div_table = div_3200;
7016 break;
7017 case 4000000:
7018 div_table = div_4000;
7019 break;
7020 case 5333333:
7021 div_table = div_5333;
7022 break;
7023 default:
7024 goto fail;
7025 }
7026
7027 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7028
7029 fail:
7030 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7031 return 200000;
7032 }
7033
7034 static int g33_get_display_clock_speed(struct drm_device *dev)
7035 {
7036 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7037 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7038 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7039 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7040 const uint8_t *div_table;
7041 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7042 uint16_t tmp = 0;
7043
7044 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7045
7046 cdclk_sel = (tmp >> 4) & 0x7;
7047
7048 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7049 goto fail;
7050
7051 switch (vco) {
7052 case 3200000:
7053 div_table = div_3200;
7054 break;
7055 case 4000000:
7056 div_table = div_4000;
7057 break;
7058 case 4800000:
7059 div_table = div_4800;
7060 break;
7061 case 5333333:
7062 div_table = div_5333;
7063 break;
7064 default:
7065 goto fail;
7066 }
7067
7068 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7069
7070 fail:
7071 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7072 return 190476;
7073 }
7074
7075 static void
7076 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7077 {
7078 while (*num > DATA_LINK_M_N_MASK ||
7079 *den > DATA_LINK_M_N_MASK) {
7080 *num >>= 1;
7081 *den >>= 1;
7082 }
7083 }
7084
7085 static void compute_m_n(unsigned int m, unsigned int n,
7086 uint32_t *ret_m, uint32_t *ret_n)
7087 {
7088 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7089 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7090 intel_reduce_m_n_ratio(ret_m, ret_n);
7091 }
7092
7093 void
7094 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7095 int pixel_clock, int link_clock,
7096 struct intel_link_m_n *m_n)
7097 {
7098 m_n->tu = 64;
7099
7100 compute_m_n(bits_per_pixel * pixel_clock,
7101 link_clock * nlanes * 8,
7102 &m_n->gmch_m, &m_n->gmch_n);
7103
7104 compute_m_n(pixel_clock, link_clock,
7105 &m_n->link_m, &m_n->link_n);
7106 }
7107
7108 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7109 {
7110 if (i915.panel_use_ssc >= 0)
7111 return i915.panel_use_ssc != 0;
7112 return dev_priv->vbt.lvds_use_ssc
7113 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7114 }
7115
7116 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7117 {
7118 return (1 << dpll->n) << 16 | dpll->m2;
7119 }
7120
7121 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7122 {
7123 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7124 }
7125
7126 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7127 struct intel_crtc_state *crtc_state,
7128 struct dpll *reduced_clock)
7129 {
7130 struct drm_device *dev = crtc->base.dev;
7131 u32 fp, fp2 = 0;
7132
7133 if (IS_PINEVIEW(dev)) {
7134 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7135 if (reduced_clock)
7136 fp2 = pnv_dpll_compute_fp(reduced_clock);
7137 } else {
7138 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7139 if (reduced_clock)
7140 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7141 }
7142
7143 crtc_state->dpll_hw_state.fp0 = fp;
7144
7145 crtc->lowfreq_avail = false;
7146 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7147 reduced_clock) {
7148 crtc_state->dpll_hw_state.fp1 = fp2;
7149 crtc->lowfreq_avail = true;
7150 } else {
7151 crtc_state->dpll_hw_state.fp1 = fp;
7152 }
7153 }
7154
7155 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7156 pipe)
7157 {
7158 u32 reg_val;
7159
7160 /*
7161 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7162 * and set it to a reasonable value instead.
7163 */
7164 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7165 reg_val &= 0xffffff00;
7166 reg_val |= 0x00000030;
7167 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7168
7169 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7170 reg_val &= 0x8cffffff;
7171 reg_val = 0x8c000000;
7172 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7173
7174 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7175 reg_val &= 0xffffff00;
7176 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7177
7178 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7179 reg_val &= 0x00ffffff;
7180 reg_val |= 0xb0000000;
7181 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7182 }
7183
7184 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7185 struct intel_link_m_n *m_n)
7186 {
7187 struct drm_device *dev = crtc->base.dev;
7188 struct drm_i915_private *dev_priv = to_i915(dev);
7189 int pipe = crtc->pipe;
7190
7191 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7192 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7193 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7194 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7195 }
7196
7197 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7198 struct intel_link_m_n *m_n,
7199 struct intel_link_m_n *m2_n2)
7200 {
7201 struct drm_device *dev = crtc->base.dev;
7202 struct drm_i915_private *dev_priv = to_i915(dev);
7203 int pipe = crtc->pipe;
7204 enum transcoder transcoder = crtc->config->cpu_transcoder;
7205
7206 if (INTEL_INFO(dev)->gen >= 5) {
7207 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7208 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7209 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7210 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7211 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7212 * for gen < 8) and if DRRS is supported (to make sure the
7213 * registers are not unnecessarily accessed).
7214 */
7215 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7216 crtc->config->has_drrs) {
7217 I915_WRITE(PIPE_DATA_M2(transcoder),
7218 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7219 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7220 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7221 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7222 }
7223 } else {
7224 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7225 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7226 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7227 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7228 }
7229 }
7230
7231 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7232 {
7233 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7234
7235 if (m_n == M1_N1) {
7236 dp_m_n = &crtc->config->dp_m_n;
7237 dp_m2_n2 = &crtc->config->dp_m2_n2;
7238 } else if (m_n == M2_N2) {
7239
7240 /*
7241 * M2_N2 registers are not supported. Hence m2_n2 divider value
7242 * needs to be programmed into M1_N1.
7243 */
7244 dp_m_n = &crtc->config->dp_m2_n2;
7245 } else {
7246 DRM_ERROR("Unsupported divider value\n");
7247 return;
7248 }
7249
7250 if (crtc->config->has_pch_encoder)
7251 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7252 else
7253 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7254 }
7255
7256 static void vlv_compute_dpll(struct intel_crtc *crtc,
7257 struct intel_crtc_state *pipe_config)
7258 {
7259 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7260 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7261 if (crtc->pipe != PIPE_A)
7262 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7263
7264 /* DPLL not used with DSI, but still need the rest set up */
7265 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7266 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7267 DPLL_EXT_BUFFER_ENABLE_VLV;
7268
7269 pipe_config->dpll_hw_state.dpll_md =
7270 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7271 }
7272
7273 static void chv_compute_dpll(struct intel_crtc *crtc,
7274 struct intel_crtc_state *pipe_config)
7275 {
7276 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7277 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7278 if (crtc->pipe != PIPE_A)
7279 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7280
7281 /* DPLL not used with DSI, but still need the rest set up */
7282 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7283 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7284
7285 pipe_config->dpll_hw_state.dpll_md =
7286 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7287 }
7288
7289 static void vlv_prepare_pll(struct intel_crtc *crtc,
7290 const struct intel_crtc_state *pipe_config)
7291 {
7292 struct drm_device *dev = crtc->base.dev;
7293 struct drm_i915_private *dev_priv = to_i915(dev);
7294 enum pipe pipe = crtc->pipe;
7295 u32 mdiv;
7296 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7297 u32 coreclk, reg_val;
7298
7299 /* Enable Refclk */
7300 I915_WRITE(DPLL(pipe),
7301 pipe_config->dpll_hw_state.dpll &
7302 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7303
7304 /* No need to actually set up the DPLL with DSI */
7305 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7306 return;
7307
7308 mutex_lock(&dev_priv->sb_lock);
7309
7310 bestn = pipe_config->dpll.n;
7311 bestm1 = pipe_config->dpll.m1;
7312 bestm2 = pipe_config->dpll.m2;
7313 bestp1 = pipe_config->dpll.p1;
7314 bestp2 = pipe_config->dpll.p2;
7315
7316 /* See eDP HDMI DPIO driver vbios notes doc */
7317
7318 /* PLL B needs special handling */
7319 if (pipe == PIPE_B)
7320 vlv_pllb_recal_opamp(dev_priv, pipe);
7321
7322 /* Set up Tx target for periodic Rcomp update */
7323 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7324
7325 /* Disable target IRef on PLL */
7326 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7327 reg_val &= 0x00ffffff;
7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7329
7330 /* Disable fast lock */
7331 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7332
7333 /* Set idtafcrecal before PLL is enabled */
7334 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7335 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7336 mdiv |= ((bestn << DPIO_N_SHIFT));
7337 mdiv |= (1 << DPIO_K_SHIFT);
7338
7339 /*
7340 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7341 * but we don't support that).
7342 * Note: don't use the DAC post divider as it seems unstable.
7343 */
7344 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7346
7347 mdiv |= DPIO_ENABLE_CALIBRATION;
7348 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7349
7350 /* Set HBR and RBR LPF coefficients */
7351 if (pipe_config->port_clock == 162000 ||
7352 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7353 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7354 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7355 0x009f0003);
7356 else
7357 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7358 0x00d0000f);
7359
7360 if (intel_crtc_has_dp_encoder(pipe_config)) {
7361 /* Use SSC source */
7362 if (pipe == PIPE_A)
7363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7364 0x0df40000);
7365 else
7366 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7367 0x0df70000);
7368 } else { /* HDMI or VGA */
7369 /* Use bend source */
7370 if (pipe == PIPE_A)
7371 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7372 0x0df70000);
7373 else
7374 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7375 0x0df40000);
7376 }
7377
7378 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7379 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7380 if (intel_crtc_has_dp_encoder(crtc->config))
7381 coreclk |= 0x01000000;
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7383
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7385 mutex_unlock(&dev_priv->sb_lock);
7386 }
7387
7388 static void chv_prepare_pll(struct intel_crtc *crtc,
7389 const struct intel_crtc_state *pipe_config)
7390 {
7391 struct drm_device *dev = crtc->base.dev;
7392 struct drm_i915_private *dev_priv = to_i915(dev);
7393 enum pipe pipe = crtc->pipe;
7394 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7395 u32 loopfilter, tribuf_calcntr;
7396 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7397 u32 dpio_val;
7398 int vco;
7399
7400 /* Enable Refclk and SSC */
7401 I915_WRITE(DPLL(pipe),
7402 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7403
7404 /* No need to actually set up the DPLL with DSI */
7405 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7406 return;
7407
7408 bestn = pipe_config->dpll.n;
7409 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7410 bestm1 = pipe_config->dpll.m1;
7411 bestm2 = pipe_config->dpll.m2 >> 22;
7412 bestp1 = pipe_config->dpll.p1;
7413 bestp2 = pipe_config->dpll.p2;
7414 vco = pipe_config->dpll.vco;
7415 dpio_val = 0;
7416 loopfilter = 0;
7417
7418 mutex_lock(&dev_priv->sb_lock);
7419
7420 /* p1 and p2 divider */
7421 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7422 5 << DPIO_CHV_S1_DIV_SHIFT |
7423 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7424 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7425 1 << DPIO_CHV_K_DIV_SHIFT);
7426
7427 /* Feedback post-divider - m2 */
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7429
7430 /* Feedback refclk divider - n and m1 */
7431 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7432 DPIO_CHV_M1_DIV_BY_2 |
7433 1 << DPIO_CHV_N_DIV_SHIFT);
7434
7435 /* M2 fraction division */
7436 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7437
7438 /* M2 fraction division enable */
7439 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7440 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7441 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7442 if (bestm2_frac)
7443 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7444 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7445
7446 /* Program digital lock detect threshold */
7447 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7448 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7449 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7450 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7451 if (!bestm2_frac)
7452 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7453 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7454
7455 /* Loop filter */
7456 if (vco == 5400000) {
7457 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7458 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7459 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7460 tribuf_calcntr = 0x9;
7461 } else if (vco <= 6200000) {
7462 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7463 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7464 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7465 tribuf_calcntr = 0x9;
7466 } else if (vco <= 6480000) {
7467 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7468 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7469 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7470 tribuf_calcntr = 0x8;
7471 } else {
7472 /* Not supported. Apply the same limits as in the max case */
7473 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7474 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7475 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7476 tribuf_calcntr = 0;
7477 }
7478 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7479
7480 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7481 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7482 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7483 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7484
7485 /* AFC Recal */
7486 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7487 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7488 DPIO_AFC_RECAL);
7489
7490 mutex_unlock(&dev_priv->sb_lock);
7491 }
7492
7493 /**
7494 * vlv_force_pll_on - forcibly enable just the PLL
7495 * @dev_priv: i915 private structure
7496 * @pipe: pipe PLL to enable
7497 * @dpll: PLL configuration
7498 *
7499 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7500 * in cases where we need the PLL enabled even when @pipe is not going to
7501 * be enabled.
7502 */
7503 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7504 const struct dpll *dpll)
7505 {
7506 struct intel_crtc *crtc =
7507 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7508 struct intel_crtc_state *pipe_config;
7509
7510 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7511 if (!pipe_config)
7512 return -ENOMEM;
7513
7514 pipe_config->base.crtc = &crtc->base;
7515 pipe_config->pixel_multiplier = 1;
7516 pipe_config->dpll = *dpll;
7517
7518 if (IS_CHERRYVIEW(dev)) {
7519 chv_compute_dpll(crtc, pipe_config);
7520 chv_prepare_pll(crtc, pipe_config);
7521 chv_enable_pll(crtc, pipe_config);
7522 } else {
7523 vlv_compute_dpll(crtc, pipe_config);
7524 vlv_prepare_pll(crtc, pipe_config);
7525 vlv_enable_pll(crtc, pipe_config);
7526 }
7527
7528 kfree(pipe_config);
7529
7530 return 0;
7531 }
7532
7533 /**
7534 * vlv_force_pll_off - forcibly disable just the PLL
7535 * @dev_priv: i915 private structure
7536 * @pipe: pipe PLL to disable
7537 *
7538 * Disable the PLL for @pipe. To be used in cases where we need
7539 * the PLL enabled even when @pipe is not going to be enabled.
7540 */
7541 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7542 {
7543 if (IS_CHERRYVIEW(dev))
7544 chv_disable_pll(to_i915(dev), pipe);
7545 else
7546 vlv_disable_pll(to_i915(dev), pipe);
7547 }
7548
7549 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7550 struct intel_crtc_state *crtc_state,
7551 struct dpll *reduced_clock)
7552 {
7553 struct drm_device *dev = crtc->base.dev;
7554 struct drm_i915_private *dev_priv = to_i915(dev);
7555 u32 dpll;
7556 struct dpll *clock = &crtc_state->dpll;
7557
7558 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7559
7560 dpll = DPLL_VGA_MODE_DIS;
7561
7562 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7563 dpll |= DPLLB_MODE_LVDS;
7564 else
7565 dpll |= DPLLB_MODE_DAC_SERIAL;
7566
7567 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7568 dpll |= (crtc_state->pixel_multiplier - 1)
7569 << SDVO_MULTIPLIER_SHIFT_HIRES;
7570 }
7571
7572 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7573 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7574 dpll |= DPLL_SDVO_HIGH_SPEED;
7575
7576 if (intel_crtc_has_dp_encoder(crtc_state))
7577 dpll |= DPLL_SDVO_HIGH_SPEED;
7578
7579 /* compute bitmask from p1 value */
7580 if (IS_PINEVIEW(dev))
7581 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7582 else {
7583 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7584 if (IS_G4X(dev) && reduced_clock)
7585 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7586 }
7587 switch (clock->p2) {
7588 case 5:
7589 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7590 break;
7591 case 7:
7592 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7593 break;
7594 case 10:
7595 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7596 break;
7597 case 14:
7598 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7599 break;
7600 }
7601 if (INTEL_INFO(dev)->gen >= 4)
7602 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7603
7604 if (crtc_state->sdvo_tv_clock)
7605 dpll |= PLL_REF_INPUT_TVCLKINBC;
7606 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7607 intel_panel_use_ssc(dev_priv))
7608 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7609 else
7610 dpll |= PLL_REF_INPUT_DREFCLK;
7611
7612 dpll |= DPLL_VCO_ENABLE;
7613 crtc_state->dpll_hw_state.dpll = dpll;
7614
7615 if (INTEL_INFO(dev)->gen >= 4) {
7616 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7617 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7618 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7619 }
7620 }
7621
7622 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7623 struct intel_crtc_state *crtc_state,
7624 struct dpll *reduced_clock)
7625 {
7626 struct drm_device *dev = crtc->base.dev;
7627 struct drm_i915_private *dev_priv = to_i915(dev);
7628 u32 dpll;
7629 struct dpll *clock = &crtc_state->dpll;
7630
7631 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7632
7633 dpll = DPLL_VGA_MODE_DIS;
7634
7635 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7636 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7637 } else {
7638 if (clock->p1 == 2)
7639 dpll |= PLL_P1_DIVIDE_BY_TWO;
7640 else
7641 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7642 if (clock->p2 == 4)
7643 dpll |= PLL_P2_DIVIDE_BY_4;
7644 }
7645
7646 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7647 dpll |= DPLL_DVO_2X_MODE;
7648
7649 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7650 intel_panel_use_ssc(dev_priv))
7651 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7652 else
7653 dpll |= PLL_REF_INPUT_DREFCLK;
7654
7655 dpll |= DPLL_VCO_ENABLE;
7656 crtc_state->dpll_hw_state.dpll = dpll;
7657 }
7658
7659 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7660 {
7661 struct drm_device *dev = intel_crtc->base.dev;
7662 struct drm_i915_private *dev_priv = to_i915(dev);
7663 enum pipe pipe = intel_crtc->pipe;
7664 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7665 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7666 uint32_t crtc_vtotal, crtc_vblank_end;
7667 int vsyncshift = 0;
7668
7669 /* We need to be careful not to changed the adjusted mode, for otherwise
7670 * the hw state checker will get angry at the mismatch. */
7671 crtc_vtotal = adjusted_mode->crtc_vtotal;
7672 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7673
7674 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7675 /* the chip adds 2 halflines automatically */
7676 crtc_vtotal -= 1;
7677 crtc_vblank_end -= 1;
7678
7679 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7680 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7681 else
7682 vsyncshift = adjusted_mode->crtc_hsync_start -
7683 adjusted_mode->crtc_htotal / 2;
7684 if (vsyncshift < 0)
7685 vsyncshift += adjusted_mode->crtc_htotal;
7686 }
7687
7688 if (INTEL_INFO(dev)->gen > 3)
7689 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7690
7691 I915_WRITE(HTOTAL(cpu_transcoder),
7692 (adjusted_mode->crtc_hdisplay - 1) |
7693 ((adjusted_mode->crtc_htotal - 1) << 16));
7694 I915_WRITE(HBLANK(cpu_transcoder),
7695 (adjusted_mode->crtc_hblank_start - 1) |
7696 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7697 I915_WRITE(HSYNC(cpu_transcoder),
7698 (adjusted_mode->crtc_hsync_start - 1) |
7699 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7700
7701 I915_WRITE(VTOTAL(cpu_transcoder),
7702 (adjusted_mode->crtc_vdisplay - 1) |
7703 ((crtc_vtotal - 1) << 16));
7704 I915_WRITE(VBLANK(cpu_transcoder),
7705 (adjusted_mode->crtc_vblank_start - 1) |
7706 ((crtc_vblank_end - 1) << 16));
7707 I915_WRITE(VSYNC(cpu_transcoder),
7708 (adjusted_mode->crtc_vsync_start - 1) |
7709 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7710
7711 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7712 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7713 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7714 * bits. */
7715 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7716 (pipe == PIPE_B || pipe == PIPE_C))
7717 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7718
7719 }
7720
7721 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7722 {
7723 struct drm_device *dev = intel_crtc->base.dev;
7724 struct drm_i915_private *dev_priv = to_i915(dev);
7725 enum pipe pipe = intel_crtc->pipe;
7726
7727 /* pipesrc controls the size that is scaled from, which should
7728 * always be the user's requested size.
7729 */
7730 I915_WRITE(PIPESRC(pipe),
7731 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7732 (intel_crtc->config->pipe_src_h - 1));
7733 }
7734
7735 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7736 struct intel_crtc_state *pipe_config)
7737 {
7738 struct drm_device *dev = crtc->base.dev;
7739 struct drm_i915_private *dev_priv = to_i915(dev);
7740 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7741 uint32_t tmp;
7742
7743 tmp = I915_READ(HTOTAL(cpu_transcoder));
7744 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7745 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7746 tmp = I915_READ(HBLANK(cpu_transcoder));
7747 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7748 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7749 tmp = I915_READ(HSYNC(cpu_transcoder));
7750 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7751 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7752
7753 tmp = I915_READ(VTOTAL(cpu_transcoder));
7754 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7755 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7756 tmp = I915_READ(VBLANK(cpu_transcoder));
7757 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7758 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7759 tmp = I915_READ(VSYNC(cpu_transcoder));
7760 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7761 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7762
7763 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7764 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7765 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7766 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7767 }
7768 }
7769
7770 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7771 struct intel_crtc_state *pipe_config)
7772 {
7773 struct drm_device *dev = crtc->base.dev;
7774 struct drm_i915_private *dev_priv = to_i915(dev);
7775 u32 tmp;
7776
7777 tmp = I915_READ(PIPESRC(crtc->pipe));
7778 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7779 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7780
7781 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7782 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7783 }
7784
7785 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7786 struct intel_crtc_state *pipe_config)
7787 {
7788 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7789 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7790 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7791 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7792
7793 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7794 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7795 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7796 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7797
7798 mode->flags = pipe_config->base.adjusted_mode.flags;
7799 mode->type = DRM_MODE_TYPE_DRIVER;
7800
7801 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7802 mode->flags |= pipe_config->base.adjusted_mode.flags;
7803
7804 mode->hsync = drm_mode_hsync(mode);
7805 mode->vrefresh = drm_mode_vrefresh(mode);
7806 drm_mode_set_name(mode);
7807 }
7808
7809 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7810 {
7811 struct drm_device *dev = intel_crtc->base.dev;
7812 struct drm_i915_private *dev_priv = to_i915(dev);
7813 uint32_t pipeconf;
7814
7815 pipeconf = 0;
7816
7817 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7818 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7819 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7820
7821 if (intel_crtc->config->double_wide)
7822 pipeconf |= PIPECONF_DOUBLE_WIDE;
7823
7824 /* only g4x and later have fancy bpc/dither controls */
7825 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7826 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7827 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7828 pipeconf |= PIPECONF_DITHER_EN |
7829 PIPECONF_DITHER_TYPE_SP;
7830
7831 switch (intel_crtc->config->pipe_bpp) {
7832 case 18:
7833 pipeconf |= PIPECONF_6BPC;
7834 break;
7835 case 24:
7836 pipeconf |= PIPECONF_8BPC;
7837 break;
7838 case 30:
7839 pipeconf |= PIPECONF_10BPC;
7840 break;
7841 default:
7842 /* Case prevented by intel_choose_pipe_bpp_dither. */
7843 BUG();
7844 }
7845 }
7846
7847 if (HAS_PIPE_CXSR(dev)) {
7848 if (intel_crtc->lowfreq_avail) {
7849 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7850 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7851 } else {
7852 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7853 }
7854 }
7855
7856 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7857 if (INTEL_INFO(dev)->gen < 4 ||
7858 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7859 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7860 else
7861 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7862 } else
7863 pipeconf |= PIPECONF_PROGRESSIVE;
7864
7865 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7866 intel_crtc->config->limited_color_range)
7867 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7868
7869 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7870 POSTING_READ(PIPECONF(intel_crtc->pipe));
7871 }
7872
7873 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7874 struct intel_crtc_state *crtc_state)
7875 {
7876 struct drm_device *dev = crtc->base.dev;
7877 struct drm_i915_private *dev_priv = to_i915(dev);
7878 const struct intel_limit *limit;
7879 int refclk = 48000;
7880
7881 memset(&crtc_state->dpll_hw_state, 0,
7882 sizeof(crtc_state->dpll_hw_state));
7883
7884 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7885 if (intel_panel_use_ssc(dev_priv)) {
7886 refclk = dev_priv->vbt.lvds_ssc_freq;
7887 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7888 }
7889
7890 limit = &intel_limits_i8xx_lvds;
7891 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7892 limit = &intel_limits_i8xx_dvo;
7893 } else {
7894 limit = &intel_limits_i8xx_dac;
7895 }
7896
7897 if (!crtc_state->clock_set &&
7898 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7899 refclk, NULL, &crtc_state->dpll)) {
7900 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7901 return -EINVAL;
7902 }
7903
7904 i8xx_compute_dpll(crtc, crtc_state, NULL);
7905
7906 return 0;
7907 }
7908
7909 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7910 struct intel_crtc_state *crtc_state)
7911 {
7912 struct drm_device *dev = crtc->base.dev;
7913 struct drm_i915_private *dev_priv = to_i915(dev);
7914 const struct intel_limit *limit;
7915 int refclk = 96000;
7916
7917 memset(&crtc_state->dpll_hw_state, 0,
7918 sizeof(crtc_state->dpll_hw_state));
7919
7920 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7921 if (intel_panel_use_ssc(dev_priv)) {
7922 refclk = dev_priv->vbt.lvds_ssc_freq;
7923 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7924 }
7925
7926 if (intel_is_dual_link_lvds(dev))
7927 limit = &intel_limits_g4x_dual_channel_lvds;
7928 else
7929 limit = &intel_limits_g4x_single_channel_lvds;
7930 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7931 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7932 limit = &intel_limits_g4x_hdmi;
7933 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7934 limit = &intel_limits_g4x_sdvo;
7935 } else {
7936 /* The option is for other outputs */
7937 limit = &intel_limits_i9xx_sdvo;
7938 }
7939
7940 if (!crtc_state->clock_set &&
7941 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7942 refclk, NULL, &crtc_state->dpll)) {
7943 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7944 return -EINVAL;
7945 }
7946
7947 i9xx_compute_dpll(crtc, crtc_state, NULL);
7948
7949 return 0;
7950 }
7951
7952 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7953 struct intel_crtc_state *crtc_state)
7954 {
7955 struct drm_device *dev = crtc->base.dev;
7956 struct drm_i915_private *dev_priv = to_i915(dev);
7957 const struct intel_limit *limit;
7958 int refclk = 96000;
7959
7960 memset(&crtc_state->dpll_hw_state, 0,
7961 sizeof(crtc_state->dpll_hw_state));
7962
7963 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7964 if (intel_panel_use_ssc(dev_priv)) {
7965 refclk = dev_priv->vbt.lvds_ssc_freq;
7966 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7967 }
7968
7969 limit = &intel_limits_pineview_lvds;
7970 } else {
7971 limit = &intel_limits_pineview_sdvo;
7972 }
7973
7974 if (!crtc_state->clock_set &&
7975 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7976 refclk, NULL, &crtc_state->dpll)) {
7977 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7978 return -EINVAL;
7979 }
7980
7981 i9xx_compute_dpll(crtc, crtc_state, NULL);
7982
7983 return 0;
7984 }
7985
7986 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7987 struct intel_crtc_state *crtc_state)
7988 {
7989 struct drm_device *dev = crtc->base.dev;
7990 struct drm_i915_private *dev_priv = to_i915(dev);
7991 const struct intel_limit *limit;
7992 int refclk = 96000;
7993
7994 memset(&crtc_state->dpll_hw_state, 0,
7995 sizeof(crtc_state->dpll_hw_state));
7996
7997 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7998 if (intel_panel_use_ssc(dev_priv)) {
7999 refclk = dev_priv->vbt.lvds_ssc_freq;
8000 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8001 }
8002
8003 limit = &intel_limits_i9xx_lvds;
8004 } else {
8005 limit = &intel_limits_i9xx_sdvo;
8006 }
8007
8008 if (!crtc_state->clock_set &&
8009 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8010 refclk, NULL, &crtc_state->dpll)) {
8011 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8012 return -EINVAL;
8013 }
8014
8015 i9xx_compute_dpll(crtc, crtc_state, NULL);
8016
8017 return 0;
8018 }
8019
8020 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8021 struct intel_crtc_state *crtc_state)
8022 {
8023 int refclk = 100000;
8024 const struct intel_limit *limit = &intel_limits_chv;
8025
8026 memset(&crtc_state->dpll_hw_state, 0,
8027 sizeof(crtc_state->dpll_hw_state));
8028
8029 if (!crtc_state->clock_set &&
8030 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8031 refclk, NULL, &crtc_state->dpll)) {
8032 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8033 return -EINVAL;
8034 }
8035
8036 chv_compute_dpll(crtc, crtc_state);
8037
8038 return 0;
8039 }
8040
8041 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8042 struct intel_crtc_state *crtc_state)
8043 {
8044 int refclk = 100000;
8045 const struct intel_limit *limit = &intel_limits_vlv;
8046
8047 memset(&crtc_state->dpll_hw_state, 0,
8048 sizeof(crtc_state->dpll_hw_state));
8049
8050 if (!crtc_state->clock_set &&
8051 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8052 refclk, NULL, &crtc_state->dpll)) {
8053 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8054 return -EINVAL;
8055 }
8056
8057 vlv_compute_dpll(crtc, crtc_state);
8058
8059 return 0;
8060 }
8061
8062 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8063 struct intel_crtc_state *pipe_config)
8064 {
8065 struct drm_device *dev = crtc->base.dev;
8066 struct drm_i915_private *dev_priv = to_i915(dev);
8067 uint32_t tmp;
8068
8069 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8070 return;
8071
8072 tmp = I915_READ(PFIT_CONTROL);
8073 if (!(tmp & PFIT_ENABLE))
8074 return;
8075
8076 /* Check whether the pfit is attached to our pipe. */
8077 if (INTEL_INFO(dev)->gen < 4) {
8078 if (crtc->pipe != PIPE_B)
8079 return;
8080 } else {
8081 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8082 return;
8083 }
8084
8085 pipe_config->gmch_pfit.control = tmp;
8086 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8087 }
8088
8089 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8090 struct intel_crtc_state *pipe_config)
8091 {
8092 struct drm_device *dev = crtc->base.dev;
8093 struct drm_i915_private *dev_priv = to_i915(dev);
8094 int pipe = pipe_config->cpu_transcoder;
8095 struct dpll clock;
8096 u32 mdiv;
8097 int refclk = 100000;
8098
8099 /* In case of DSI, DPLL will not be used */
8100 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8101 return;
8102
8103 mutex_lock(&dev_priv->sb_lock);
8104 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8105 mutex_unlock(&dev_priv->sb_lock);
8106
8107 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8108 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8109 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8110 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8111 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8112
8113 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8114 }
8115
8116 static void
8117 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8118 struct intel_initial_plane_config *plane_config)
8119 {
8120 struct drm_device *dev = crtc->base.dev;
8121 struct drm_i915_private *dev_priv = to_i915(dev);
8122 u32 val, base, offset;
8123 int pipe = crtc->pipe, plane = crtc->plane;
8124 int fourcc, pixel_format;
8125 unsigned int aligned_height;
8126 struct drm_framebuffer *fb;
8127 struct intel_framebuffer *intel_fb;
8128
8129 val = I915_READ(DSPCNTR(plane));
8130 if (!(val & DISPLAY_PLANE_ENABLE))
8131 return;
8132
8133 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8134 if (!intel_fb) {
8135 DRM_DEBUG_KMS("failed to alloc fb\n");
8136 return;
8137 }
8138
8139 fb = &intel_fb->base;
8140
8141 if (INTEL_INFO(dev)->gen >= 4) {
8142 if (val & DISPPLANE_TILED) {
8143 plane_config->tiling = I915_TILING_X;
8144 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8145 }
8146 }
8147
8148 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8149 fourcc = i9xx_format_to_fourcc(pixel_format);
8150 fb->pixel_format = fourcc;
8151 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8152
8153 if (INTEL_INFO(dev)->gen >= 4) {
8154 if (plane_config->tiling)
8155 offset = I915_READ(DSPTILEOFF(plane));
8156 else
8157 offset = I915_READ(DSPLINOFF(plane));
8158 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8159 } else {
8160 base = I915_READ(DSPADDR(plane));
8161 }
8162 plane_config->base = base;
8163
8164 val = I915_READ(PIPESRC(pipe));
8165 fb->width = ((val >> 16) & 0xfff) + 1;
8166 fb->height = ((val >> 0) & 0xfff) + 1;
8167
8168 val = I915_READ(DSPSTRIDE(pipe));
8169 fb->pitches[0] = val & 0xffffffc0;
8170
8171 aligned_height = intel_fb_align_height(dev, fb->height,
8172 fb->pixel_format,
8173 fb->modifier[0]);
8174
8175 plane_config->size = fb->pitches[0] * aligned_height;
8176
8177 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8178 pipe_name(pipe), plane, fb->width, fb->height,
8179 fb->bits_per_pixel, base, fb->pitches[0],
8180 plane_config->size);
8181
8182 plane_config->fb = intel_fb;
8183 }
8184
8185 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8186 struct intel_crtc_state *pipe_config)
8187 {
8188 struct drm_device *dev = crtc->base.dev;
8189 struct drm_i915_private *dev_priv = to_i915(dev);
8190 int pipe = pipe_config->cpu_transcoder;
8191 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8192 struct dpll clock;
8193 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8194 int refclk = 100000;
8195
8196 /* In case of DSI, DPLL will not be used */
8197 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8198 return;
8199
8200 mutex_lock(&dev_priv->sb_lock);
8201 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8202 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8203 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8204 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8205 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8206 mutex_unlock(&dev_priv->sb_lock);
8207
8208 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8209 clock.m2 = (pll_dw0 & 0xff) << 22;
8210 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8211 clock.m2 |= pll_dw2 & 0x3fffff;
8212 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8213 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8214 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8215
8216 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8217 }
8218
8219 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8220 struct intel_crtc_state *pipe_config)
8221 {
8222 struct drm_device *dev = crtc->base.dev;
8223 struct drm_i915_private *dev_priv = to_i915(dev);
8224 enum intel_display_power_domain power_domain;
8225 uint32_t tmp;
8226 bool ret;
8227
8228 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8229 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8230 return false;
8231
8232 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8233 pipe_config->shared_dpll = NULL;
8234
8235 ret = false;
8236
8237 tmp = I915_READ(PIPECONF(crtc->pipe));
8238 if (!(tmp & PIPECONF_ENABLE))
8239 goto out;
8240
8241 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8242 switch (tmp & PIPECONF_BPC_MASK) {
8243 case PIPECONF_6BPC:
8244 pipe_config->pipe_bpp = 18;
8245 break;
8246 case PIPECONF_8BPC:
8247 pipe_config->pipe_bpp = 24;
8248 break;
8249 case PIPECONF_10BPC:
8250 pipe_config->pipe_bpp = 30;
8251 break;
8252 default:
8253 break;
8254 }
8255 }
8256
8257 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8258 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8259 pipe_config->limited_color_range = true;
8260
8261 if (INTEL_INFO(dev)->gen < 4)
8262 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8263
8264 intel_get_pipe_timings(crtc, pipe_config);
8265 intel_get_pipe_src_size(crtc, pipe_config);
8266
8267 i9xx_get_pfit_config(crtc, pipe_config);
8268
8269 if (INTEL_INFO(dev)->gen >= 4) {
8270 /* No way to read it out on pipes B and C */
8271 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8272 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8273 else
8274 tmp = I915_READ(DPLL_MD(crtc->pipe));
8275 pipe_config->pixel_multiplier =
8276 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8277 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8278 pipe_config->dpll_hw_state.dpll_md = tmp;
8279 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8280 tmp = I915_READ(DPLL(crtc->pipe));
8281 pipe_config->pixel_multiplier =
8282 ((tmp & SDVO_MULTIPLIER_MASK)
8283 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8284 } else {
8285 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8286 * port and will be fixed up in the encoder->get_config
8287 * function. */
8288 pipe_config->pixel_multiplier = 1;
8289 }
8290 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8291 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8292 /*
8293 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8294 * on 830. Filter it out here so that we don't
8295 * report errors due to that.
8296 */
8297 if (IS_I830(dev))
8298 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8299
8300 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8301 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8302 } else {
8303 /* Mask out read-only status bits. */
8304 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8305 DPLL_PORTC_READY_MASK |
8306 DPLL_PORTB_READY_MASK);
8307 }
8308
8309 if (IS_CHERRYVIEW(dev))
8310 chv_crtc_clock_get(crtc, pipe_config);
8311 else if (IS_VALLEYVIEW(dev))
8312 vlv_crtc_clock_get(crtc, pipe_config);
8313 else
8314 i9xx_crtc_clock_get(crtc, pipe_config);
8315
8316 /*
8317 * Normally the dotclock is filled in by the encoder .get_config()
8318 * but in case the pipe is enabled w/o any ports we need a sane
8319 * default.
8320 */
8321 pipe_config->base.adjusted_mode.crtc_clock =
8322 pipe_config->port_clock / pipe_config->pixel_multiplier;
8323
8324 ret = true;
8325
8326 out:
8327 intel_display_power_put(dev_priv, power_domain);
8328
8329 return ret;
8330 }
8331
8332 static void ironlake_init_pch_refclk(struct drm_device *dev)
8333 {
8334 struct drm_i915_private *dev_priv = to_i915(dev);
8335 struct intel_encoder *encoder;
8336 int i;
8337 u32 val, final;
8338 bool has_lvds = false;
8339 bool has_cpu_edp = false;
8340 bool has_panel = false;
8341 bool has_ck505 = false;
8342 bool can_ssc = false;
8343 bool using_ssc_source = false;
8344
8345 /* We need to take the global config into account */
8346 for_each_intel_encoder(dev, encoder) {
8347 switch (encoder->type) {
8348 case INTEL_OUTPUT_LVDS:
8349 has_panel = true;
8350 has_lvds = true;
8351 break;
8352 case INTEL_OUTPUT_EDP:
8353 has_panel = true;
8354 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8355 has_cpu_edp = true;
8356 break;
8357 default:
8358 break;
8359 }
8360 }
8361
8362 if (HAS_PCH_IBX(dev)) {
8363 has_ck505 = dev_priv->vbt.display_clock_mode;
8364 can_ssc = has_ck505;
8365 } else {
8366 has_ck505 = false;
8367 can_ssc = true;
8368 }
8369
8370 /* Check if any DPLLs are using the SSC source */
8371 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8372 u32 temp = I915_READ(PCH_DPLL(i));
8373
8374 if (!(temp & DPLL_VCO_ENABLE))
8375 continue;
8376
8377 if ((temp & PLL_REF_INPUT_MASK) ==
8378 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8379 using_ssc_source = true;
8380 break;
8381 }
8382 }
8383
8384 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8385 has_panel, has_lvds, has_ck505, using_ssc_source);
8386
8387 /* Ironlake: try to setup display ref clock before DPLL
8388 * enabling. This is only under driver's control after
8389 * PCH B stepping, previous chipset stepping should be
8390 * ignoring this setting.
8391 */
8392 val = I915_READ(PCH_DREF_CONTROL);
8393
8394 /* As we must carefully and slowly disable/enable each source in turn,
8395 * compute the final state we want first and check if we need to
8396 * make any changes at all.
8397 */
8398 final = val;
8399 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8400 if (has_ck505)
8401 final |= DREF_NONSPREAD_CK505_ENABLE;
8402 else
8403 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8404
8405 final &= ~DREF_SSC_SOURCE_MASK;
8406 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8407 final &= ~DREF_SSC1_ENABLE;
8408
8409 if (has_panel) {
8410 final |= DREF_SSC_SOURCE_ENABLE;
8411
8412 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8413 final |= DREF_SSC1_ENABLE;
8414
8415 if (has_cpu_edp) {
8416 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8417 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8418 else
8419 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8420 } else
8421 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8422 } else if (using_ssc_source) {
8423 final |= DREF_SSC_SOURCE_ENABLE;
8424 final |= DREF_SSC1_ENABLE;
8425 }
8426
8427 if (final == val)
8428 return;
8429
8430 /* Always enable nonspread source */
8431 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8432
8433 if (has_ck505)
8434 val |= DREF_NONSPREAD_CK505_ENABLE;
8435 else
8436 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8437
8438 if (has_panel) {
8439 val &= ~DREF_SSC_SOURCE_MASK;
8440 val |= DREF_SSC_SOURCE_ENABLE;
8441
8442 /* SSC must be turned on before enabling the CPU output */
8443 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8444 DRM_DEBUG_KMS("Using SSC on panel\n");
8445 val |= DREF_SSC1_ENABLE;
8446 } else
8447 val &= ~DREF_SSC1_ENABLE;
8448
8449 /* Get SSC going before enabling the outputs */
8450 I915_WRITE(PCH_DREF_CONTROL, val);
8451 POSTING_READ(PCH_DREF_CONTROL);
8452 udelay(200);
8453
8454 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8455
8456 /* Enable CPU source on CPU attached eDP */
8457 if (has_cpu_edp) {
8458 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8459 DRM_DEBUG_KMS("Using SSC on eDP\n");
8460 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8461 } else
8462 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8463 } else
8464 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8465
8466 I915_WRITE(PCH_DREF_CONTROL, val);
8467 POSTING_READ(PCH_DREF_CONTROL);
8468 udelay(200);
8469 } else {
8470 DRM_DEBUG_KMS("Disabling CPU source output\n");
8471
8472 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8473
8474 /* Turn off CPU output */
8475 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8476
8477 I915_WRITE(PCH_DREF_CONTROL, val);
8478 POSTING_READ(PCH_DREF_CONTROL);
8479 udelay(200);
8480
8481 if (!using_ssc_source) {
8482 DRM_DEBUG_KMS("Disabling SSC source\n");
8483
8484 /* Turn off the SSC source */
8485 val &= ~DREF_SSC_SOURCE_MASK;
8486 val |= DREF_SSC_SOURCE_DISABLE;
8487
8488 /* Turn off SSC1 */
8489 val &= ~DREF_SSC1_ENABLE;
8490
8491 I915_WRITE(PCH_DREF_CONTROL, val);
8492 POSTING_READ(PCH_DREF_CONTROL);
8493 udelay(200);
8494 }
8495 }
8496
8497 BUG_ON(val != final);
8498 }
8499
8500 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8501 {
8502 uint32_t tmp;
8503
8504 tmp = I915_READ(SOUTH_CHICKEN2);
8505 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8506 I915_WRITE(SOUTH_CHICKEN2, tmp);
8507
8508 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8509 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8510 DRM_ERROR("FDI mPHY reset assert timeout\n");
8511
8512 tmp = I915_READ(SOUTH_CHICKEN2);
8513 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8514 I915_WRITE(SOUTH_CHICKEN2, tmp);
8515
8516 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8517 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8518 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8519 }
8520
8521 /* WaMPhyProgramming:hsw */
8522 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8523 {
8524 uint32_t tmp;
8525
8526 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8527 tmp &= ~(0xFF << 24);
8528 tmp |= (0x12 << 24);
8529 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8530
8531 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8532 tmp |= (1 << 11);
8533 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8534
8535 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8536 tmp |= (1 << 11);
8537 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8538
8539 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8540 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8541 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8542
8543 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8544 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8545 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8546
8547 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8548 tmp &= ~(7 << 13);
8549 tmp |= (5 << 13);
8550 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8551
8552 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8553 tmp &= ~(7 << 13);
8554 tmp |= (5 << 13);
8555 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8556
8557 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8558 tmp &= ~0xFF;
8559 tmp |= 0x1C;
8560 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8561
8562 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8563 tmp &= ~0xFF;
8564 tmp |= 0x1C;
8565 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8566
8567 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8568 tmp &= ~(0xFF << 16);
8569 tmp |= (0x1C << 16);
8570 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8571
8572 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8573 tmp &= ~(0xFF << 16);
8574 tmp |= (0x1C << 16);
8575 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8576
8577 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8578 tmp |= (1 << 27);
8579 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8580
8581 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8582 tmp |= (1 << 27);
8583 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8584
8585 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8586 tmp &= ~(0xF << 28);
8587 tmp |= (4 << 28);
8588 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8589
8590 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8591 tmp &= ~(0xF << 28);
8592 tmp |= (4 << 28);
8593 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8594 }
8595
8596 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8597 * Programming" based on the parameters passed:
8598 * - Sequence to enable CLKOUT_DP
8599 * - Sequence to enable CLKOUT_DP without spread
8600 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8601 */
8602 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8603 bool with_fdi)
8604 {
8605 struct drm_i915_private *dev_priv = to_i915(dev);
8606 uint32_t reg, tmp;
8607
8608 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8609 with_spread = true;
8610 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8611 with_fdi = false;
8612
8613 mutex_lock(&dev_priv->sb_lock);
8614
8615 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8616 tmp &= ~SBI_SSCCTL_DISABLE;
8617 tmp |= SBI_SSCCTL_PATHALT;
8618 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8619
8620 udelay(24);
8621
8622 if (with_spread) {
8623 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8624 tmp &= ~SBI_SSCCTL_PATHALT;
8625 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8626
8627 if (with_fdi) {
8628 lpt_reset_fdi_mphy(dev_priv);
8629 lpt_program_fdi_mphy(dev_priv);
8630 }
8631 }
8632
8633 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8634 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8635 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8636 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8637
8638 mutex_unlock(&dev_priv->sb_lock);
8639 }
8640
8641 /* Sequence to disable CLKOUT_DP */
8642 static void lpt_disable_clkout_dp(struct drm_device *dev)
8643 {
8644 struct drm_i915_private *dev_priv = to_i915(dev);
8645 uint32_t reg, tmp;
8646
8647 mutex_lock(&dev_priv->sb_lock);
8648
8649 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8650 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8651 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8652 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8653
8654 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8655 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8656 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8657 tmp |= SBI_SSCCTL_PATHALT;
8658 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8659 udelay(32);
8660 }
8661 tmp |= SBI_SSCCTL_DISABLE;
8662 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8663 }
8664
8665 mutex_unlock(&dev_priv->sb_lock);
8666 }
8667
8668 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8669
8670 static const uint16_t sscdivintphase[] = {
8671 [BEND_IDX( 50)] = 0x3B23,
8672 [BEND_IDX( 45)] = 0x3B23,
8673 [BEND_IDX( 40)] = 0x3C23,
8674 [BEND_IDX( 35)] = 0x3C23,
8675 [BEND_IDX( 30)] = 0x3D23,
8676 [BEND_IDX( 25)] = 0x3D23,
8677 [BEND_IDX( 20)] = 0x3E23,
8678 [BEND_IDX( 15)] = 0x3E23,
8679 [BEND_IDX( 10)] = 0x3F23,
8680 [BEND_IDX( 5)] = 0x3F23,
8681 [BEND_IDX( 0)] = 0x0025,
8682 [BEND_IDX( -5)] = 0x0025,
8683 [BEND_IDX(-10)] = 0x0125,
8684 [BEND_IDX(-15)] = 0x0125,
8685 [BEND_IDX(-20)] = 0x0225,
8686 [BEND_IDX(-25)] = 0x0225,
8687 [BEND_IDX(-30)] = 0x0325,
8688 [BEND_IDX(-35)] = 0x0325,
8689 [BEND_IDX(-40)] = 0x0425,
8690 [BEND_IDX(-45)] = 0x0425,
8691 [BEND_IDX(-50)] = 0x0525,
8692 };
8693
8694 /*
8695 * Bend CLKOUT_DP
8696 * steps -50 to 50 inclusive, in steps of 5
8697 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8698 * change in clock period = -(steps / 10) * 5.787 ps
8699 */
8700 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8701 {
8702 uint32_t tmp;
8703 int idx = BEND_IDX(steps);
8704
8705 if (WARN_ON(steps % 5 != 0))
8706 return;
8707
8708 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8709 return;
8710
8711 mutex_lock(&dev_priv->sb_lock);
8712
8713 if (steps % 10 != 0)
8714 tmp = 0xAAAAAAAB;
8715 else
8716 tmp = 0x00000000;
8717 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8718
8719 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8720 tmp &= 0xffff0000;
8721 tmp |= sscdivintphase[idx];
8722 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8723
8724 mutex_unlock(&dev_priv->sb_lock);
8725 }
8726
8727 #undef BEND_IDX
8728
8729 static void lpt_init_pch_refclk(struct drm_device *dev)
8730 {
8731 struct intel_encoder *encoder;
8732 bool has_vga = false;
8733
8734 for_each_intel_encoder(dev, encoder) {
8735 switch (encoder->type) {
8736 case INTEL_OUTPUT_ANALOG:
8737 has_vga = true;
8738 break;
8739 default:
8740 break;
8741 }
8742 }
8743
8744 if (has_vga) {
8745 lpt_bend_clkout_dp(to_i915(dev), 0);
8746 lpt_enable_clkout_dp(dev, true, true);
8747 } else {
8748 lpt_disable_clkout_dp(dev);
8749 }
8750 }
8751
8752 /*
8753 * Initialize reference clocks when the driver loads
8754 */
8755 void intel_init_pch_refclk(struct drm_device *dev)
8756 {
8757 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8758 ironlake_init_pch_refclk(dev);
8759 else if (HAS_PCH_LPT(dev))
8760 lpt_init_pch_refclk(dev);
8761 }
8762
8763 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8764 {
8765 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8767 int pipe = intel_crtc->pipe;
8768 uint32_t val;
8769
8770 val = 0;
8771
8772 switch (intel_crtc->config->pipe_bpp) {
8773 case 18:
8774 val |= PIPECONF_6BPC;
8775 break;
8776 case 24:
8777 val |= PIPECONF_8BPC;
8778 break;
8779 case 30:
8780 val |= PIPECONF_10BPC;
8781 break;
8782 case 36:
8783 val |= PIPECONF_12BPC;
8784 break;
8785 default:
8786 /* Case prevented by intel_choose_pipe_bpp_dither. */
8787 BUG();
8788 }
8789
8790 if (intel_crtc->config->dither)
8791 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8792
8793 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8794 val |= PIPECONF_INTERLACED_ILK;
8795 else
8796 val |= PIPECONF_PROGRESSIVE;
8797
8798 if (intel_crtc->config->limited_color_range)
8799 val |= PIPECONF_COLOR_RANGE_SELECT;
8800
8801 I915_WRITE(PIPECONF(pipe), val);
8802 POSTING_READ(PIPECONF(pipe));
8803 }
8804
8805 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8806 {
8807 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8809 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8810 u32 val = 0;
8811
8812 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8813 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8814
8815 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8816 val |= PIPECONF_INTERLACED_ILK;
8817 else
8818 val |= PIPECONF_PROGRESSIVE;
8819
8820 I915_WRITE(PIPECONF(cpu_transcoder), val);
8821 POSTING_READ(PIPECONF(cpu_transcoder));
8822 }
8823
8824 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8825 {
8826 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8828
8829 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8830 u32 val = 0;
8831
8832 switch (intel_crtc->config->pipe_bpp) {
8833 case 18:
8834 val |= PIPEMISC_DITHER_6_BPC;
8835 break;
8836 case 24:
8837 val |= PIPEMISC_DITHER_8_BPC;
8838 break;
8839 case 30:
8840 val |= PIPEMISC_DITHER_10_BPC;
8841 break;
8842 case 36:
8843 val |= PIPEMISC_DITHER_12_BPC;
8844 break;
8845 default:
8846 /* Case prevented by pipe_config_set_bpp. */
8847 BUG();
8848 }
8849
8850 if (intel_crtc->config->dither)
8851 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8852
8853 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8854 }
8855 }
8856
8857 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8858 {
8859 /*
8860 * Account for spread spectrum to avoid
8861 * oversubscribing the link. Max center spread
8862 * is 2.5%; use 5% for safety's sake.
8863 */
8864 u32 bps = target_clock * bpp * 21 / 20;
8865 return DIV_ROUND_UP(bps, link_bw * 8);
8866 }
8867
8868 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8869 {
8870 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8871 }
8872
8873 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8874 struct intel_crtc_state *crtc_state,
8875 struct dpll *reduced_clock)
8876 {
8877 struct drm_crtc *crtc = &intel_crtc->base;
8878 struct drm_device *dev = crtc->dev;
8879 struct drm_i915_private *dev_priv = to_i915(dev);
8880 u32 dpll, fp, fp2;
8881 int factor;
8882
8883 /* Enable autotuning of the PLL clock (if permissible) */
8884 factor = 21;
8885 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8886 if ((intel_panel_use_ssc(dev_priv) &&
8887 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8888 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8889 factor = 25;
8890 } else if (crtc_state->sdvo_tv_clock)
8891 factor = 20;
8892
8893 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8894
8895 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8896 fp |= FP_CB_TUNE;
8897
8898 if (reduced_clock) {
8899 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8900
8901 if (reduced_clock->m < factor * reduced_clock->n)
8902 fp2 |= FP_CB_TUNE;
8903 } else {
8904 fp2 = fp;
8905 }
8906
8907 dpll = 0;
8908
8909 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8910 dpll |= DPLLB_MODE_LVDS;
8911 else
8912 dpll |= DPLLB_MODE_DAC_SERIAL;
8913
8914 dpll |= (crtc_state->pixel_multiplier - 1)
8915 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8916
8917 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8918 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8919 dpll |= DPLL_SDVO_HIGH_SPEED;
8920
8921 if (intel_crtc_has_dp_encoder(crtc_state))
8922 dpll |= DPLL_SDVO_HIGH_SPEED;
8923
8924 /* compute bitmask from p1 value */
8925 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8926 /* also FPA1 */
8927 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8928
8929 switch (crtc_state->dpll.p2) {
8930 case 5:
8931 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8932 break;
8933 case 7:
8934 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8935 break;
8936 case 10:
8937 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8938 break;
8939 case 14:
8940 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8941 break;
8942 }
8943
8944 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8945 intel_panel_use_ssc(dev_priv))
8946 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8947 else
8948 dpll |= PLL_REF_INPUT_DREFCLK;
8949
8950 dpll |= DPLL_VCO_ENABLE;
8951
8952 crtc_state->dpll_hw_state.dpll = dpll;
8953 crtc_state->dpll_hw_state.fp0 = fp;
8954 crtc_state->dpll_hw_state.fp1 = fp2;
8955 }
8956
8957 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8958 struct intel_crtc_state *crtc_state)
8959 {
8960 struct drm_device *dev = crtc->base.dev;
8961 struct drm_i915_private *dev_priv = to_i915(dev);
8962 struct dpll reduced_clock;
8963 bool has_reduced_clock = false;
8964 struct intel_shared_dpll *pll;
8965 const struct intel_limit *limit;
8966 int refclk = 120000;
8967
8968 memset(&crtc_state->dpll_hw_state, 0,
8969 sizeof(crtc_state->dpll_hw_state));
8970
8971 crtc->lowfreq_avail = false;
8972
8973 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8974 if (!crtc_state->has_pch_encoder)
8975 return 0;
8976
8977 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8978 if (intel_panel_use_ssc(dev_priv)) {
8979 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8980 dev_priv->vbt.lvds_ssc_freq);
8981 refclk = dev_priv->vbt.lvds_ssc_freq;
8982 }
8983
8984 if (intel_is_dual_link_lvds(dev)) {
8985 if (refclk == 100000)
8986 limit = &intel_limits_ironlake_dual_lvds_100m;
8987 else
8988 limit = &intel_limits_ironlake_dual_lvds;
8989 } else {
8990 if (refclk == 100000)
8991 limit = &intel_limits_ironlake_single_lvds_100m;
8992 else
8993 limit = &intel_limits_ironlake_single_lvds;
8994 }
8995 } else {
8996 limit = &intel_limits_ironlake_dac;
8997 }
8998
8999 if (!crtc_state->clock_set &&
9000 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9001 refclk, NULL, &crtc_state->dpll)) {
9002 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9003 return -EINVAL;
9004 }
9005
9006 ironlake_compute_dpll(crtc, crtc_state,
9007 has_reduced_clock ? &reduced_clock : NULL);
9008
9009 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9010 if (pll == NULL) {
9011 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9012 pipe_name(crtc->pipe));
9013 return -EINVAL;
9014 }
9015
9016 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9017 has_reduced_clock)
9018 crtc->lowfreq_avail = true;
9019
9020 return 0;
9021 }
9022
9023 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9024 struct intel_link_m_n *m_n)
9025 {
9026 struct drm_device *dev = crtc->base.dev;
9027 struct drm_i915_private *dev_priv = to_i915(dev);
9028 enum pipe pipe = crtc->pipe;
9029
9030 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9031 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9032 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9033 & ~TU_SIZE_MASK;
9034 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9035 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9036 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9037 }
9038
9039 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9040 enum transcoder transcoder,
9041 struct intel_link_m_n *m_n,
9042 struct intel_link_m_n *m2_n2)
9043 {
9044 struct drm_device *dev = crtc->base.dev;
9045 struct drm_i915_private *dev_priv = to_i915(dev);
9046 enum pipe pipe = crtc->pipe;
9047
9048 if (INTEL_INFO(dev)->gen >= 5) {
9049 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9050 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9051 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9052 & ~TU_SIZE_MASK;
9053 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9054 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9055 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9056 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9057 * gen < 8) and if DRRS is supported (to make sure the
9058 * registers are not unnecessarily read).
9059 */
9060 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9061 crtc->config->has_drrs) {
9062 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9063 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9064 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9065 & ~TU_SIZE_MASK;
9066 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9067 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9068 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9069 }
9070 } else {
9071 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9072 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9073 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9074 & ~TU_SIZE_MASK;
9075 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9076 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9077 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9078 }
9079 }
9080
9081 void intel_dp_get_m_n(struct intel_crtc *crtc,
9082 struct intel_crtc_state *pipe_config)
9083 {
9084 if (pipe_config->has_pch_encoder)
9085 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9086 else
9087 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9088 &pipe_config->dp_m_n,
9089 &pipe_config->dp_m2_n2);
9090 }
9091
9092 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9093 struct intel_crtc_state *pipe_config)
9094 {
9095 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9096 &pipe_config->fdi_m_n, NULL);
9097 }
9098
9099 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9100 struct intel_crtc_state *pipe_config)
9101 {
9102 struct drm_device *dev = crtc->base.dev;
9103 struct drm_i915_private *dev_priv = to_i915(dev);
9104 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9105 uint32_t ps_ctrl = 0;
9106 int id = -1;
9107 int i;
9108
9109 /* find scaler attached to this pipe */
9110 for (i = 0; i < crtc->num_scalers; i++) {
9111 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9112 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9113 id = i;
9114 pipe_config->pch_pfit.enabled = true;
9115 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9116 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9117 break;
9118 }
9119 }
9120
9121 scaler_state->scaler_id = id;
9122 if (id >= 0) {
9123 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9124 } else {
9125 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9126 }
9127 }
9128
9129 static void
9130 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9131 struct intel_initial_plane_config *plane_config)
9132 {
9133 struct drm_device *dev = crtc->base.dev;
9134 struct drm_i915_private *dev_priv = to_i915(dev);
9135 u32 val, base, offset, stride_mult, tiling;
9136 int pipe = crtc->pipe;
9137 int fourcc, pixel_format;
9138 unsigned int aligned_height;
9139 struct drm_framebuffer *fb;
9140 struct intel_framebuffer *intel_fb;
9141
9142 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9143 if (!intel_fb) {
9144 DRM_DEBUG_KMS("failed to alloc fb\n");
9145 return;
9146 }
9147
9148 fb = &intel_fb->base;
9149
9150 val = I915_READ(PLANE_CTL(pipe, 0));
9151 if (!(val & PLANE_CTL_ENABLE))
9152 goto error;
9153
9154 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9155 fourcc = skl_format_to_fourcc(pixel_format,
9156 val & PLANE_CTL_ORDER_RGBX,
9157 val & PLANE_CTL_ALPHA_MASK);
9158 fb->pixel_format = fourcc;
9159 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9160
9161 tiling = val & PLANE_CTL_TILED_MASK;
9162 switch (tiling) {
9163 case PLANE_CTL_TILED_LINEAR:
9164 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9165 break;
9166 case PLANE_CTL_TILED_X:
9167 plane_config->tiling = I915_TILING_X;
9168 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9169 break;
9170 case PLANE_CTL_TILED_Y:
9171 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9172 break;
9173 case PLANE_CTL_TILED_YF:
9174 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9175 break;
9176 default:
9177 MISSING_CASE(tiling);
9178 goto error;
9179 }
9180
9181 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9182 plane_config->base = base;
9183
9184 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9185
9186 val = I915_READ(PLANE_SIZE(pipe, 0));
9187 fb->height = ((val >> 16) & 0xfff) + 1;
9188 fb->width = ((val >> 0) & 0x1fff) + 1;
9189
9190 val = I915_READ(PLANE_STRIDE(pipe, 0));
9191 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9192 fb->pixel_format);
9193 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9194
9195 aligned_height = intel_fb_align_height(dev, fb->height,
9196 fb->pixel_format,
9197 fb->modifier[0]);
9198
9199 plane_config->size = fb->pitches[0] * aligned_height;
9200
9201 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9202 pipe_name(pipe), fb->width, fb->height,
9203 fb->bits_per_pixel, base, fb->pitches[0],
9204 plane_config->size);
9205
9206 plane_config->fb = intel_fb;
9207 return;
9208
9209 error:
9210 kfree(fb);
9211 }
9212
9213 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9214 struct intel_crtc_state *pipe_config)
9215 {
9216 struct drm_device *dev = crtc->base.dev;
9217 struct drm_i915_private *dev_priv = to_i915(dev);
9218 uint32_t tmp;
9219
9220 tmp = I915_READ(PF_CTL(crtc->pipe));
9221
9222 if (tmp & PF_ENABLE) {
9223 pipe_config->pch_pfit.enabled = true;
9224 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9225 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9226
9227 /* We currently do not free assignements of panel fitters on
9228 * ivb/hsw (since we don't use the higher upscaling modes which
9229 * differentiates them) so just WARN about this case for now. */
9230 if (IS_GEN7(dev)) {
9231 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9232 PF_PIPE_SEL_IVB(crtc->pipe));
9233 }
9234 }
9235 }
9236
9237 static void
9238 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9239 struct intel_initial_plane_config *plane_config)
9240 {
9241 struct drm_device *dev = crtc->base.dev;
9242 struct drm_i915_private *dev_priv = to_i915(dev);
9243 u32 val, base, offset;
9244 int pipe = crtc->pipe;
9245 int fourcc, pixel_format;
9246 unsigned int aligned_height;
9247 struct drm_framebuffer *fb;
9248 struct intel_framebuffer *intel_fb;
9249
9250 val = I915_READ(DSPCNTR(pipe));
9251 if (!(val & DISPLAY_PLANE_ENABLE))
9252 return;
9253
9254 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9255 if (!intel_fb) {
9256 DRM_DEBUG_KMS("failed to alloc fb\n");
9257 return;
9258 }
9259
9260 fb = &intel_fb->base;
9261
9262 if (INTEL_INFO(dev)->gen >= 4) {
9263 if (val & DISPPLANE_TILED) {
9264 plane_config->tiling = I915_TILING_X;
9265 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9266 }
9267 }
9268
9269 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9270 fourcc = i9xx_format_to_fourcc(pixel_format);
9271 fb->pixel_format = fourcc;
9272 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9273
9274 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9275 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9276 offset = I915_READ(DSPOFFSET(pipe));
9277 } else {
9278 if (plane_config->tiling)
9279 offset = I915_READ(DSPTILEOFF(pipe));
9280 else
9281 offset = I915_READ(DSPLINOFF(pipe));
9282 }
9283 plane_config->base = base;
9284
9285 val = I915_READ(PIPESRC(pipe));
9286 fb->width = ((val >> 16) & 0xfff) + 1;
9287 fb->height = ((val >> 0) & 0xfff) + 1;
9288
9289 val = I915_READ(DSPSTRIDE(pipe));
9290 fb->pitches[0] = val & 0xffffffc0;
9291
9292 aligned_height = intel_fb_align_height(dev, fb->height,
9293 fb->pixel_format,
9294 fb->modifier[0]);
9295
9296 plane_config->size = fb->pitches[0] * aligned_height;
9297
9298 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9299 pipe_name(pipe), fb->width, fb->height,
9300 fb->bits_per_pixel, base, fb->pitches[0],
9301 plane_config->size);
9302
9303 plane_config->fb = intel_fb;
9304 }
9305
9306 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9307 struct intel_crtc_state *pipe_config)
9308 {
9309 struct drm_device *dev = crtc->base.dev;
9310 struct drm_i915_private *dev_priv = to_i915(dev);
9311 enum intel_display_power_domain power_domain;
9312 uint32_t tmp;
9313 bool ret;
9314
9315 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9316 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9317 return false;
9318
9319 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9320 pipe_config->shared_dpll = NULL;
9321
9322 ret = false;
9323 tmp = I915_READ(PIPECONF(crtc->pipe));
9324 if (!(tmp & PIPECONF_ENABLE))
9325 goto out;
9326
9327 switch (tmp & PIPECONF_BPC_MASK) {
9328 case PIPECONF_6BPC:
9329 pipe_config->pipe_bpp = 18;
9330 break;
9331 case PIPECONF_8BPC:
9332 pipe_config->pipe_bpp = 24;
9333 break;
9334 case PIPECONF_10BPC:
9335 pipe_config->pipe_bpp = 30;
9336 break;
9337 case PIPECONF_12BPC:
9338 pipe_config->pipe_bpp = 36;
9339 break;
9340 default:
9341 break;
9342 }
9343
9344 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9345 pipe_config->limited_color_range = true;
9346
9347 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9348 struct intel_shared_dpll *pll;
9349 enum intel_dpll_id pll_id;
9350
9351 pipe_config->has_pch_encoder = true;
9352
9353 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9354 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9355 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9356
9357 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9358
9359 if (HAS_PCH_IBX(dev_priv)) {
9360 /*
9361 * The pipe->pch transcoder and pch transcoder->pll
9362 * mapping is fixed.
9363 */
9364 pll_id = (enum intel_dpll_id) crtc->pipe;
9365 } else {
9366 tmp = I915_READ(PCH_DPLL_SEL);
9367 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9368 pll_id = DPLL_ID_PCH_PLL_B;
9369 else
9370 pll_id= DPLL_ID_PCH_PLL_A;
9371 }
9372
9373 pipe_config->shared_dpll =
9374 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9375 pll = pipe_config->shared_dpll;
9376
9377 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9378 &pipe_config->dpll_hw_state));
9379
9380 tmp = pipe_config->dpll_hw_state.dpll;
9381 pipe_config->pixel_multiplier =
9382 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9383 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9384
9385 ironlake_pch_clock_get(crtc, pipe_config);
9386 } else {
9387 pipe_config->pixel_multiplier = 1;
9388 }
9389
9390 intel_get_pipe_timings(crtc, pipe_config);
9391 intel_get_pipe_src_size(crtc, pipe_config);
9392
9393 ironlake_get_pfit_config(crtc, pipe_config);
9394
9395 ret = true;
9396
9397 out:
9398 intel_display_power_put(dev_priv, power_domain);
9399
9400 return ret;
9401 }
9402
9403 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9404 {
9405 struct drm_device *dev = &dev_priv->drm;
9406 struct intel_crtc *crtc;
9407
9408 for_each_intel_crtc(dev, crtc)
9409 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9410 pipe_name(crtc->pipe));
9411
9412 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9413 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9414 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9415 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9416 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9417 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9418 "CPU PWM1 enabled\n");
9419 if (IS_HASWELL(dev))
9420 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9421 "CPU PWM2 enabled\n");
9422 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9423 "PCH PWM1 enabled\n");
9424 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9425 "Utility pin enabled\n");
9426 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9427
9428 /*
9429 * In theory we can still leave IRQs enabled, as long as only the HPD
9430 * interrupts remain enabled. We used to check for that, but since it's
9431 * gen-specific and since we only disable LCPLL after we fully disable
9432 * the interrupts, the check below should be enough.
9433 */
9434 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9435 }
9436
9437 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9438 {
9439 struct drm_device *dev = &dev_priv->drm;
9440
9441 if (IS_HASWELL(dev))
9442 return I915_READ(D_COMP_HSW);
9443 else
9444 return I915_READ(D_COMP_BDW);
9445 }
9446
9447 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9448 {
9449 struct drm_device *dev = &dev_priv->drm;
9450
9451 if (IS_HASWELL(dev)) {
9452 mutex_lock(&dev_priv->rps.hw_lock);
9453 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9454 val))
9455 DRM_ERROR("Failed to write to D_COMP\n");
9456 mutex_unlock(&dev_priv->rps.hw_lock);
9457 } else {
9458 I915_WRITE(D_COMP_BDW, val);
9459 POSTING_READ(D_COMP_BDW);
9460 }
9461 }
9462
9463 /*
9464 * This function implements pieces of two sequences from BSpec:
9465 * - Sequence for display software to disable LCPLL
9466 * - Sequence for display software to allow package C8+
9467 * The steps implemented here are just the steps that actually touch the LCPLL
9468 * register. Callers should take care of disabling all the display engine
9469 * functions, doing the mode unset, fixing interrupts, etc.
9470 */
9471 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9472 bool switch_to_fclk, bool allow_power_down)
9473 {
9474 uint32_t val;
9475
9476 assert_can_disable_lcpll(dev_priv);
9477
9478 val = I915_READ(LCPLL_CTL);
9479
9480 if (switch_to_fclk) {
9481 val |= LCPLL_CD_SOURCE_FCLK;
9482 I915_WRITE(LCPLL_CTL, val);
9483
9484 if (wait_for_us(I915_READ(LCPLL_CTL) &
9485 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9486 DRM_ERROR("Switching to FCLK failed\n");
9487
9488 val = I915_READ(LCPLL_CTL);
9489 }
9490
9491 val |= LCPLL_PLL_DISABLE;
9492 I915_WRITE(LCPLL_CTL, val);
9493 POSTING_READ(LCPLL_CTL);
9494
9495 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9496 DRM_ERROR("LCPLL still locked\n");
9497
9498 val = hsw_read_dcomp(dev_priv);
9499 val |= D_COMP_COMP_DISABLE;
9500 hsw_write_dcomp(dev_priv, val);
9501 ndelay(100);
9502
9503 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9504 1))
9505 DRM_ERROR("D_COMP RCOMP still in progress\n");
9506
9507 if (allow_power_down) {
9508 val = I915_READ(LCPLL_CTL);
9509 val |= LCPLL_POWER_DOWN_ALLOW;
9510 I915_WRITE(LCPLL_CTL, val);
9511 POSTING_READ(LCPLL_CTL);
9512 }
9513 }
9514
9515 /*
9516 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9517 * source.
9518 */
9519 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9520 {
9521 uint32_t val;
9522
9523 val = I915_READ(LCPLL_CTL);
9524
9525 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9526 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9527 return;
9528
9529 /*
9530 * Make sure we're not on PC8 state before disabling PC8, otherwise
9531 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9532 */
9533 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9534
9535 if (val & LCPLL_POWER_DOWN_ALLOW) {
9536 val &= ~LCPLL_POWER_DOWN_ALLOW;
9537 I915_WRITE(LCPLL_CTL, val);
9538 POSTING_READ(LCPLL_CTL);
9539 }
9540
9541 val = hsw_read_dcomp(dev_priv);
9542 val |= D_COMP_COMP_FORCE;
9543 val &= ~D_COMP_COMP_DISABLE;
9544 hsw_write_dcomp(dev_priv, val);
9545
9546 val = I915_READ(LCPLL_CTL);
9547 val &= ~LCPLL_PLL_DISABLE;
9548 I915_WRITE(LCPLL_CTL, val);
9549
9550 if (intel_wait_for_register(dev_priv,
9551 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9552 5))
9553 DRM_ERROR("LCPLL not locked yet\n");
9554
9555 if (val & LCPLL_CD_SOURCE_FCLK) {
9556 val = I915_READ(LCPLL_CTL);
9557 val &= ~LCPLL_CD_SOURCE_FCLK;
9558 I915_WRITE(LCPLL_CTL, val);
9559
9560 if (wait_for_us((I915_READ(LCPLL_CTL) &
9561 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9562 DRM_ERROR("Switching back to LCPLL failed\n");
9563 }
9564
9565 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9566 intel_update_cdclk(&dev_priv->drm);
9567 }
9568
9569 /*
9570 * Package states C8 and deeper are really deep PC states that can only be
9571 * reached when all the devices on the system allow it, so even if the graphics
9572 * device allows PC8+, it doesn't mean the system will actually get to these
9573 * states. Our driver only allows PC8+ when going into runtime PM.
9574 *
9575 * The requirements for PC8+ are that all the outputs are disabled, the power
9576 * well is disabled and most interrupts are disabled, and these are also
9577 * requirements for runtime PM. When these conditions are met, we manually do
9578 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9579 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9580 * hang the machine.
9581 *
9582 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9583 * the state of some registers, so when we come back from PC8+ we need to
9584 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9585 * need to take care of the registers kept by RC6. Notice that this happens even
9586 * if we don't put the device in PCI D3 state (which is what currently happens
9587 * because of the runtime PM support).
9588 *
9589 * For more, read "Display Sequences for Package C8" on the hardware
9590 * documentation.
9591 */
9592 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9593 {
9594 struct drm_device *dev = &dev_priv->drm;
9595 uint32_t val;
9596
9597 DRM_DEBUG_KMS("Enabling package C8+\n");
9598
9599 if (HAS_PCH_LPT_LP(dev)) {
9600 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9601 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9602 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9603 }
9604
9605 lpt_disable_clkout_dp(dev);
9606 hsw_disable_lcpll(dev_priv, true, true);
9607 }
9608
9609 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9610 {
9611 struct drm_device *dev = &dev_priv->drm;
9612 uint32_t val;
9613
9614 DRM_DEBUG_KMS("Disabling package C8+\n");
9615
9616 hsw_restore_lcpll(dev_priv);
9617 lpt_init_pch_refclk(dev);
9618
9619 if (HAS_PCH_LPT_LP(dev)) {
9620 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9621 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9622 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9623 }
9624 }
9625
9626 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9627 {
9628 struct drm_device *dev = old_state->dev;
9629 struct intel_atomic_state *old_intel_state =
9630 to_intel_atomic_state(old_state);
9631 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9632
9633 bxt_set_cdclk(to_i915(dev), req_cdclk);
9634 }
9635
9636 /* compute the max rate for new configuration */
9637 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9638 {
9639 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9640 struct drm_i915_private *dev_priv = to_i915(state->dev);
9641 struct drm_crtc *crtc;
9642 struct drm_crtc_state *cstate;
9643 struct intel_crtc_state *crtc_state;
9644 unsigned max_pixel_rate = 0, i;
9645 enum pipe pipe;
9646
9647 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9648 sizeof(intel_state->min_pixclk));
9649
9650 for_each_crtc_in_state(state, crtc, cstate, i) {
9651 int pixel_rate;
9652
9653 crtc_state = to_intel_crtc_state(cstate);
9654 if (!crtc_state->base.enable) {
9655 intel_state->min_pixclk[i] = 0;
9656 continue;
9657 }
9658
9659 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9660
9661 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9662 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9663 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9664
9665 intel_state->min_pixclk[i] = pixel_rate;
9666 }
9667
9668 for_each_pipe(dev_priv, pipe)
9669 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9670
9671 return max_pixel_rate;
9672 }
9673
9674 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9675 {
9676 struct drm_i915_private *dev_priv = to_i915(dev);
9677 uint32_t val, data;
9678 int ret;
9679
9680 if (WARN((I915_READ(LCPLL_CTL) &
9681 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9682 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9683 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9684 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9685 "trying to change cdclk frequency with cdclk not enabled\n"))
9686 return;
9687
9688 mutex_lock(&dev_priv->rps.hw_lock);
9689 ret = sandybridge_pcode_write(dev_priv,
9690 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9691 mutex_unlock(&dev_priv->rps.hw_lock);
9692 if (ret) {
9693 DRM_ERROR("failed to inform pcode about cdclk change\n");
9694 return;
9695 }
9696
9697 val = I915_READ(LCPLL_CTL);
9698 val |= LCPLL_CD_SOURCE_FCLK;
9699 I915_WRITE(LCPLL_CTL, val);
9700
9701 if (wait_for_us(I915_READ(LCPLL_CTL) &
9702 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9703 DRM_ERROR("Switching to FCLK failed\n");
9704
9705 val = I915_READ(LCPLL_CTL);
9706 val &= ~LCPLL_CLK_FREQ_MASK;
9707
9708 switch (cdclk) {
9709 case 450000:
9710 val |= LCPLL_CLK_FREQ_450;
9711 data = 0;
9712 break;
9713 case 540000:
9714 val |= LCPLL_CLK_FREQ_54O_BDW;
9715 data = 1;
9716 break;
9717 case 337500:
9718 val |= LCPLL_CLK_FREQ_337_5_BDW;
9719 data = 2;
9720 break;
9721 case 675000:
9722 val |= LCPLL_CLK_FREQ_675_BDW;
9723 data = 3;
9724 break;
9725 default:
9726 WARN(1, "invalid cdclk frequency\n");
9727 return;
9728 }
9729
9730 I915_WRITE(LCPLL_CTL, val);
9731
9732 val = I915_READ(LCPLL_CTL);
9733 val &= ~LCPLL_CD_SOURCE_FCLK;
9734 I915_WRITE(LCPLL_CTL, val);
9735
9736 if (wait_for_us((I915_READ(LCPLL_CTL) &
9737 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9738 DRM_ERROR("Switching back to LCPLL failed\n");
9739
9740 mutex_lock(&dev_priv->rps.hw_lock);
9741 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9742 mutex_unlock(&dev_priv->rps.hw_lock);
9743
9744 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9745
9746 intel_update_cdclk(dev);
9747
9748 WARN(cdclk != dev_priv->cdclk_freq,
9749 "cdclk requested %d kHz but got %d kHz\n",
9750 cdclk, dev_priv->cdclk_freq);
9751 }
9752
9753 static int broadwell_calc_cdclk(int max_pixclk)
9754 {
9755 if (max_pixclk > 540000)
9756 return 675000;
9757 else if (max_pixclk > 450000)
9758 return 540000;
9759 else if (max_pixclk > 337500)
9760 return 450000;
9761 else
9762 return 337500;
9763 }
9764
9765 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9766 {
9767 struct drm_i915_private *dev_priv = to_i915(state->dev);
9768 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9769 int max_pixclk = ilk_max_pixel_rate(state);
9770 int cdclk;
9771
9772 /*
9773 * FIXME should also account for plane ratio
9774 * once 64bpp pixel formats are supported.
9775 */
9776 cdclk = broadwell_calc_cdclk(max_pixclk);
9777
9778 if (cdclk > dev_priv->max_cdclk_freq) {
9779 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9780 cdclk, dev_priv->max_cdclk_freq);
9781 return -EINVAL;
9782 }
9783
9784 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9785 if (!intel_state->active_crtcs)
9786 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9787
9788 return 0;
9789 }
9790
9791 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9792 {
9793 struct drm_device *dev = old_state->dev;
9794 struct intel_atomic_state *old_intel_state =
9795 to_intel_atomic_state(old_state);
9796 unsigned req_cdclk = old_intel_state->dev_cdclk;
9797
9798 broadwell_set_cdclk(dev, req_cdclk);
9799 }
9800
9801 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9802 {
9803 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9804 struct drm_i915_private *dev_priv = to_i915(state->dev);
9805 const int max_pixclk = ilk_max_pixel_rate(state);
9806 int vco = intel_state->cdclk_pll_vco;
9807 int cdclk;
9808
9809 /*
9810 * FIXME should also account for plane ratio
9811 * once 64bpp pixel formats are supported.
9812 */
9813 cdclk = skl_calc_cdclk(max_pixclk, vco);
9814
9815 /*
9816 * FIXME move the cdclk caclulation to
9817 * compute_config() so we can fail gracegully.
9818 */
9819 if (cdclk > dev_priv->max_cdclk_freq) {
9820 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9821 cdclk, dev_priv->max_cdclk_freq);
9822 cdclk = dev_priv->max_cdclk_freq;
9823 }
9824
9825 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9826 if (!intel_state->active_crtcs)
9827 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9828
9829 return 0;
9830 }
9831
9832 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9833 {
9834 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9835 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9836 unsigned int req_cdclk = intel_state->dev_cdclk;
9837 unsigned int req_vco = intel_state->cdclk_pll_vco;
9838
9839 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9840 }
9841
9842 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9843 struct intel_crtc_state *crtc_state)
9844 {
9845 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9846 if (!intel_ddi_pll_select(crtc, crtc_state))
9847 return -EINVAL;
9848 }
9849
9850 crtc->lowfreq_avail = false;
9851
9852 return 0;
9853 }
9854
9855 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9856 enum port port,
9857 struct intel_crtc_state *pipe_config)
9858 {
9859 enum intel_dpll_id id;
9860
9861 switch (port) {
9862 case PORT_A:
9863 pipe_config->ddi_pll_sel = SKL_DPLL0;
9864 id = DPLL_ID_SKL_DPLL0;
9865 break;
9866 case PORT_B:
9867 pipe_config->ddi_pll_sel = SKL_DPLL1;
9868 id = DPLL_ID_SKL_DPLL1;
9869 break;
9870 case PORT_C:
9871 pipe_config->ddi_pll_sel = SKL_DPLL2;
9872 id = DPLL_ID_SKL_DPLL2;
9873 break;
9874 default:
9875 DRM_ERROR("Incorrect port type\n");
9876 return;
9877 }
9878
9879 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9880 }
9881
9882 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9883 enum port port,
9884 struct intel_crtc_state *pipe_config)
9885 {
9886 enum intel_dpll_id id;
9887 u32 temp;
9888
9889 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9890 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9891
9892 switch (pipe_config->ddi_pll_sel) {
9893 case SKL_DPLL0:
9894 id = DPLL_ID_SKL_DPLL0;
9895 break;
9896 case SKL_DPLL1:
9897 id = DPLL_ID_SKL_DPLL1;
9898 break;
9899 case SKL_DPLL2:
9900 id = DPLL_ID_SKL_DPLL2;
9901 break;
9902 case SKL_DPLL3:
9903 id = DPLL_ID_SKL_DPLL3;
9904 break;
9905 default:
9906 MISSING_CASE(pipe_config->ddi_pll_sel);
9907 return;
9908 }
9909
9910 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9911 }
9912
9913 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9914 enum port port,
9915 struct intel_crtc_state *pipe_config)
9916 {
9917 enum intel_dpll_id id;
9918
9919 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9920
9921 switch (pipe_config->ddi_pll_sel) {
9922 case PORT_CLK_SEL_WRPLL1:
9923 id = DPLL_ID_WRPLL1;
9924 break;
9925 case PORT_CLK_SEL_WRPLL2:
9926 id = DPLL_ID_WRPLL2;
9927 break;
9928 case PORT_CLK_SEL_SPLL:
9929 id = DPLL_ID_SPLL;
9930 break;
9931 case PORT_CLK_SEL_LCPLL_810:
9932 id = DPLL_ID_LCPLL_810;
9933 break;
9934 case PORT_CLK_SEL_LCPLL_1350:
9935 id = DPLL_ID_LCPLL_1350;
9936 break;
9937 case PORT_CLK_SEL_LCPLL_2700:
9938 id = DPLL_ID_LCPLL_2700;
9939 break;
9940 default:
9941 MISSING_CASE(pipe_config->ddi_pll_sel);
9942 /* fall through */
9943 case PORT_CLK_SEL_NONE:
9944 return;
9945 }
9946
9947 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9948 }
9949
9950 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9951 struct intel_crtc_state *pipe_config,
9952 unsigned long *power_domain_mask)
9953 {
9954 struct drm_device *dev = crtc->base.dev;
9955 struct drm_i915_private *dev_priv = to_i915(dev);
9956 enum intel_display_power_domain power_domain;
9957 u32 tmp;
9958
9959 /*
9960 * The pipe->transcoder mapping is fixed with the exception of the eDP
9961 * transcoder handled below.
9962 */
9963 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9964
9965 /*
9966 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9967 * consistency and less surprising code; it's in always on power).
9968 */
9969 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9970 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9971 enum pipe trans_edp_pipe;
9972 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9973 default:
9974 WARN(1, "unknown pipe linked to edp transcoder\n");
9975 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9976 case TRANS_DDI_EDP_INPUT_A_ON:
9977 trans_edp_pipe = PIPE_A;
9978 break;
9979 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9980 trans_edp_pipe = PIPE_B;
9981 break;
9982 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9983 trans_edp_pipe = PIPE_C;
9984 break;
9985 }
9986
9987 if (trans_edp_pipe == crtc->pipe)
9988 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9989 }
9990
9991 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9992 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9993 return false;
9994 *power_domain_mask |= BIT(power_domain);
9995
9996 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9997
9998 return tmp & PIPECONF_ENABLE;
9999 }
10000
10001 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10002 struct intel_crtc_state *pipe_config,
10003 unsigned long *power_domain_mask)
10004 {
10005 struct drm_device *dev = crtc->base.dev;
10006 struct drm_i915_private *dev_priv = to_i915(dev);
10007 enum intel_display_power_domain power_domain;
10008 enum port port;
10009 enum transcoder cpu_transcoder;
10010 u32 tmp;
10011
10012 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10013 if (port == PORT_A)
10014 cpu_transcoder = TRANSCODER_DSI_A;
10015 else
10016 cpu_transcoder = TRANSCODER_DSI_C;
10017
10018 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10019 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10020 continue;
10021 *power_domain_mask |= BIT(power_domain);
10022
10023 /*
10024 * The PLL needs to be enabled with a valid divider
10025 * configuration, otherwise accessing DSI registers will hang
10026 * the machine. See BSpec North Display Engine
10027 * registers/MIPI[BXT]. We can break out here early, since we
10028 * need the same DSI PLL to be enabled for both DSI ports.
10029 */
10030 if (!intel_dsi_pll_is_enabled(dev_priv))
10031 break;
10032
10033 /* XXX: this works for video mode only */
10034 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10035 if (!(tmp & DPI_ENABLE))
10036 continue;
10037
10038 tmp = I915_READ(MIPI_CTRL(port));
10039 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10040 continue;
10041
10042 pipe_config->cpu_transcoder = cpu_transcoder;
10043 break;
10044 }
10045
10046 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10047 }
10048
10049 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10050 struct intel_crtc_state *pipe_config)
10051 {
10052 struct drm_device *dev = crtc->base.dev;
10053 struct drm_i915_private *dev_priv = to_i915(dev);
10054 struct intel_shared_dpll *pll;
10055 enum port port;
10056 uint32_t tmp;
10057
10058 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10059
10060 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10061
10062 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10063 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10064 else if (IS_BROXTON(dev))
10065 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10066 else
10067 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10068
10069 pll = pipe_config->shared_dpll;
10070 if (pll) {
10071 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10072 &pipe_config->dpll_hw_state));
10073 }
10074
10075 /*
10076 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10077 * DDI E. So just check whether this pipe is wired to DDI E and whether
10078 * the PCH transcoder is on.
10079 */
10080 if (INTEL_INFO(dev)->gen < 9 &&
10081 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10082 pipe_config->has_pch_encoder = true;
10083
10084 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10085 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10086 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10087
10088 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10089 }
10090 }
10091
10092 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10093 struct intel_crtc_state *pipe_config)
10094 {
10095 struct drm_device *dev = crtc->base.dev;
10096 struct drm_i915_private *dev_priv = to_i915(dev);
10097 enum intel_display_power_domain power_domain;
10098 unsigned long power_domain_mask;
10099 bool active;
10100
10101 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10102 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10103 return false;
10104 power_domain_mask = BIT(power_domain);
10105
10106 pipe_config->shared_dpll = NULL;
10107
10108 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10109
10110 if (IS_BROXTON(dev_priv) &&
10111 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10112 WARN_ON(active);
10113 active = true;
10114 }
10115
10116 if (!active)
10117 goto out;
10118
10119 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10120 haswell_get_ddi_port_state(crtc, pipe_config);
10121 intel_get_pipe_timings(crtc, pipe_config);
10122 }
10123
10124 intel_get_pipe_src_size(crtc, pipe_config);
10125
10126 pipe_config->gamma_mode =
10127 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10128
10129 if (INTEL_INFO(dev)->gen >= 9) {
10130 skl_init_scalers(dev, crtc, pipe_config);
10131 }
10132
10133 if (INTEL_INFO(dev)->gen >= 9) {
10134 pipe_config->scaler_state.scaler_id = -1;
10135 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10136 }
10137
10138 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10139 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10140 power_domain_mask |= BIT(power_domain);
10141 if (INTEL_INFO(dev)->gen >= 9)
10142 skylake_get_pfit_config(crtc, pipe_config);
10143 else
10144 ironlake_get_pfit_config(crtc, pipe_config);
10145 }
10146
10147 if (IS_HASWELL(dev))
10148 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10149 (I915_READ(IPS_CTL) & IPS_ENABLE);
10150
10151 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10152 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10153 pipe_config->pixel_multiplier =
10154 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10155 } else {
10156 pipe_config->pixel_multiplier = 1;
10157 }
10158
10159 out:
10160 for_each_power_domain(power_domain, power_domain_mask)
10161 intel_display_power_put(dev_priv, power_domain);
10162
10163 return active;
10164 }
10165
10166 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10167 const struct intel_plane_state *plane_state)
10168 {
10169 struct drm_device *dev = crtc->dev;
10170 struct drm_i915_private *dev_priv = to_i915(dev);
10171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10172 uint32_t cntl = 0, size = 0;
10173
10174 if (plane_state && plane_state->visible) {
10175 unsigned int width = plane_state->base.crtc_w;
10176 unsigned int height = plane_state->base.crtc_h;
10177 unsigned int stride = roundup_pow_of_two(width) * 4;
10178
10179 switch (stride) {
10180 default:
10181 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10182 width, stride);
10183 stride = 256;
10184 /* fallthrough */
10185 case 256:
10186 case 512:
10187 case 1024:
10188 case 2048:
10189 break;
10190 }
10191
10192 cntl |= CURSOR_ENABLE |
10193 CURSOR_GAMMA_ENABLE |
10194 CURSOR_FORMAT_ARGB |
10195 CURSOR_STRIDE(stride);
10196
10197 size = (height << 12) | width;
10198 }
10199
10200 if (intel_crtc->cursor_cntl != 0 &&
10201 (intel_crtc->cursor_base != base ||
10202 intel_crtc->cursor_size != size ||
10203 intel_crtc->cursor_cntl != cntl)) {
10204 /* On these chipsets we can only modify the base/size/stride
10205 * whilst the cursor is disabled.
10206 */
10207 I915_WRITE(CURCNTR(PIPE_A), 0);
10208 POSTING_READ(CURCNTR(PIPE_A));
10209 intel_crtc->cursor_cntl = 0;
10210 }
10211
10212 if (intel_crtc->cursor_base != base) {
10213 I915_WRITE(CURBASE(PIPE_A), base);
10214 intel_crtc->cursor_base = base;
10215 }
10216
10217 if (intel_crtc->cursor_size != size) {
10218 I915_WRITE(CURSIZE, size);
10219 intel_crtc->cursor_size = size;
10220 }
10221
10222 if (intel_crtc->cursor_cntl != cntl) {
10223 I915_WRITE(CURCNTR(PIPE_A), cntl);
10224 POSTING_READ(CURCNTR(PIPE_A));
10225 intel_crtc->cursor_cntl = cntl;
10226 }
10227 }
10228
10229 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10230 const struct intel_plane_state *plane_state)
10231 {
10232 struct drm_device *dev = crtc->dev;
10233 struct drm_i915_private *dev_priv = to_i915(dev);
10234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10235 int pipe = intel_crtc->pipe;
10236 uint32_t cntl = 0;
10237
10238 if (plane_state && plane_state->visible) {
10239 cntl = MCURSOR_GAMMA_ENABLE;
10240 switch (plane_state->base.crtc_w) {
10241 case 64:
10242 cntl |= CURSOR_MODE_64_ARGB_AX;
10243 break;
10244 case 128:
10245 cntl |= CURSOR_MODE_128_ARGB_AX;
10246 break;
10247 case 256:
10248 cntl |= CURSOR_MODE_256_ARGB_AX;
10249 break;
10250 default:
10251 MISSING_CASE(plane_state->base.crtc_w);
10252 return;
10253 }
10254 cntl |= pipe << 28; /* Connect to correct pipe */
10255
10256 if (HAS_DDI(dev))
10257 cntl |= CURSOR_PIPE_CSC_ENABLE;
10258
10259 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10260 cntl |= CURSOR_ROTATE_180;
10261 }
10262
10263 if (intel_crtc->cursor_cntl != cntl) {
10264 I915_WRITE(CURCNTR(pipe), cntl);
10265 POSTING_READ(CURCNTR(pipe));
10266 intel_crtc->cursor_cntl = cntl;
10267 }
10268
10269 /* and commit changes on next vblank */
10270 I915_WRITE(CURBASE(pipe), base);
10271 POSTING_READ(CURBASE(pipe));
10272
10273 intel_crtc->cursor_base = base;
10274 }
10275
10276 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10277 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10278 const struct intel_plane_state *plane_state)
10279 {
10280 struct drm_device *dev = crtc->dev;
10281 struct drm_i915_private *dev_priv = to_i915(dev);
10282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10283 int pipe = intel_crtc->pipe;
10284 u32 base = intel_crtc->cursor_addr;
10285 u32 pos = 0;
10286
10287 if (plane_state) {
10288 int x = plane_state->base.crtc_x;
10289 int y = plane_state->base.crtc_y;
10290
10291 if (x < 0) {
10292 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10293 x = -x;
10294 }
10295 pos |= x << CURSOR_X_SHIFT;
10296
10297 if (y < 0) {
10298 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10299 y = -y;
10300 }
10301 pos |= y << CURSOR_Y_SHIFT;
10302
10303 /* ILK+ do this automagically */
10304 if (HAS_GMCH_DISPLAY(dev) &&
10305 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10306 base += (plane_state->base.crtc_h *
10307 plane_state->base.crtc_w - 1) * 4;
10308 }
10309 }
10310
10311 I915_WRITE(CURPOS(pipe), pos);
10312
10313 if (IS_845G(dev) || IS_I865G(dev))
10314 i845_update_cursor(crtc, base, plane_state);
10315 else
10316 i9xx_update_cursor(crtc, base, plane_state);
10317 }
10318
10319 static bool cursor_size_ok(struct drm_device *dev,
10320 uint32_t width, uint32_t height)
10321 {
10322 if (width == 0 || height == 0)
10323 return false;
10324
10325 /*
10326 * 845g/865g are special in that they are only limited by
10327 * the width of their cursors, the height is arbitrary up to
10328 * the precision of the register. Everything else requires
10329 * square cursors, limited to a few power-of-two sizes.
10330 */
10331 if (IS_845G(dev) || IS_I865G(dev)) {
10332 if ((width & 63) != 0)
10333 return false;
10334
10335 if (width > (IS_845G(dev) ? 64 : 512))
10336 return false;
10337
10338 if (height > 1023)
10339 return false;
10340 } else {
10341 switch (width | height) {
10342 case 256:
10343 case 128:
10344 if (IS_GEN2(dev))
10345 return false;
10346 case 64:
10347 break;
10348 default:
10349 return false;
10350 }
10351 }
10352
10353 return true;
10354 }
10355
10356 /* VESA 640x480x72Hz mode to set on the pipe */
10357 static struct drm_display_mode load_detect_mode = {
10358 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10359 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10360 };
10361
10362 struct drm_framebuffer *
10363 __intel_framebuffer_create(struct drm_device *dev,
10364 struct drm_mode_fb_cmd2 *mode_cmd,
10365 struct drm_i915_gem_object *obj)
10366 {
10367 struct intel_framebuffer *intel_fb;
10368 int ret;
10369
10370 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10371 if (!intel_fb)
10372 return ERR_PTR(-ENOMEM);
10373
10374 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10375 if (ret)
10376 goto err;
10377
10378 return &intel_fb->base;
10379
10380 err:
10381 kfree(intel_fb);
10382 return ERR_PTR(ret);
10383 }
10384
10385 static struct drm_framebuffer *
10386 intel_framebuffer_create(struct drm_device *dev,
10387 struct drm_mode_fb_cmd2 *mode_cmd,
10388 struct drm_i915_gem_object *obj)
10389 {
10390 struct drm_framebuffer *fb;
10391 int ret;
10392
10393 ret = i915_mutex_lock_interruptible(dev);
10394 if (ret)
10395 return ERR_PTR(ret);
10396 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10397 mutex_unlock(&dev->struct_mutex);
10398
10399 return fb;
10400 }
10401
10402 static u32
10403 intel_framebuffer_pitch_for_width(int width, int bpp)
10404 {
10405 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10406 return ALIGN(pitch, 64);
10407 }
10408
10409 static u32
10410 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10411 {
10412 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10413 return PAGE_ALIGN(pitch * mode->vdisplay);
10414 }
10415
10416 static struct drm_framebuffer *
10417 intel_framebuffer_create_for_mode(struct drm_device *dev,
10418 struct drm_display_mode *mode,
10419 int depth, int bpp)
10420 {
10421 struct drm_framebuffer *fb;
10422 struct drm_i915_gem_object *obj;
10423 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10424
10425 obj = i915_gem_object_create(dev,
10426 intel_framebuffer_size_for_mode(mode, bpp));
10427 if (IS_ERR(obj))
10428 return ERR_CAST(obj);
10429
10430 mode_cmd.width = mode->hdisplay;
10431 mode_cmd.height = mode->vdisplay;
10432 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10433 bpp);
10434 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10435
10436 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10437 if (IS_ERR(fb))
10438 i915_gem_object_put_unlocked(obj);
10439
10440 return fb;
10441 }
10442
10443 static struct drm_framebuffer *
10444 mode_fits_in_fbdev(struct drm_device *dev,
10445 struct drm_display_mode *mode)
10446 {
10447 #ifdef CONFIG_DRM_FBDEV_EMULATION
10448 struct drm_i915_private *dev_priv = to_i915(dev);
10449 struct drm_i915_gem_object *obj;
10450 struct drm_framebuffer *fb;
10451
10452 if (!dev_priv->fbdev)
10453 return NULL;
10454
10455 if (!dev_priv->fbdev->fb)
10456 return NULL;
10457
10458 obj = dev_priv->fbdev->fb->obj;
10459 BUG_ON(!obj);
10460
10461 fb = &dev_priv->fbdev->fb->base;
10462 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10463 fb->bits_per_pixel))
10464 return NULL;
10465
10466 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10467 return NULL;
10468
10469 drm_framebuffer_reference(fb);
10470 return fb;
10471 #else
10472 return NULL;
10473 #endif
10474 }
10475
10476 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10477 struct drm_crtc *crtc,
10478 struct drm_display_mode *mode,
10479 struct drm_framebuffer *fb,
10480 int x, int y)
10481 {
10482 struct drm_plane_state *plane_state;
10483 int hdisplay, vdisplay;
10484 int ret;
10485
10486 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10487 if (IS_ERR(plane_state))
10488 return PTR_ERR(plane_state);
10489
10490 if (mode)
10491 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10492 else
10493 hdisplay = vdisplay = 0;
10494
10495 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10496 if (ret)
10497 return ret;
10498 drm_atomic_set_fb_for_plane(plane_state, fb);
10499 plane_state->crtc_x = 0;
10500 plane_state->crtc_y = 0;
10501 plane_state->crtc_w = hdisplay;
10502 plane_state->crtc_h = vdisplay;
10503 plane_state->src_x = x << 16;
10504 plane_state->src_y = y << 16;
10505 plane_state->src_w = hdisplay << 16;
10506 plane_state->src_h = vdisplay << 16;
10507
10508 return 0;
10509 }
10510
10511 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10512 struct drm_display_mode *mode,
10513 struct intel_load_detect_pipe *old,
10514 struct drm_modeset_acquire_ctx *ctx)
10515 {
10516 struct intel_crtc *intel_crtc;
10517 struct intel_encoder *intel_encoder =
10518 intel_attached_encoder(connector);
10519 struct drm_crtc *possible_crtc;
10520 struct drm_encoder *encoder = &intel_encoder->base;
10521 struct drm_crtc *crtc = NULL;
10522 struct drm_device *dev = encoder->dev;
10523 struct drm_framebuffer *fb;
10524 struct drm_mode_config *config = &dev->mode_config;
10525 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10526 struct drm_connector_state *connector_state;
10527 struct intel_crtc_state *crtc_state;
10528 int ret, i = -1;
10529
10530 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10531 connector->base.id, connector->name,
10532 encoder->base.id, encoder->name);
10533
10534 old->restore_state = NULL;
10535
10536 retry:
10537 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10538 if (ret)
10539 goto fail;
10540
10541 /*
10542 * Algorithm gets a little messy:
10543 *
10544 * - if the connector already has an assigned crtc, use it (but make
10545 * sure it's on first)
10546 *
10547 * - try to find the first unused crtc that can drive this connector,
10548 * and use that if we find one
10549 */
10550
10551 /* See if we already have a CRTC for this connector */
10552 if (connector->state->crtc) {
10553 crtc = connector->state->crtc;
10554
10555 ret = drm_modeset_lock(&crtc->mutex, ctx);
10556 if (ret)
10557 goto fail;
10558
10559 /* Make sure the crtc and connector are running */
10560 goto found;
10561 }
10562
10563 /* Find an unused one (if possible) */
10564 for_each_crtc(dev, possible_crtc) {
10565 i++;
10566 if (!(encoder->possible_crtcs & (1 << i)))
10567 continue;
10568
10569 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10570 if (ret)
10571 goto fail;
10572
10573 if (possible_crtc->state->enable) {
10574 drm_modeset_unlock(&possible_crtc->mutex);
10575 continue;
10576 }
10577
10578 crtc = possible_crtc;
10579 break;
10580 }
10581
10582 /*
10583 * If we didn't find an unused CRTC, don't use any.
10584 */
10585 if (!crtc) {
10586 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10587 goto fail;
10588 }
10589
10590 found:
10591 intel_crtc = to_intel_crtc(crtc);
10592
10593 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10594 if (ret)
10595 goto fail;
10596
10597 state = drm_atomic_state_alloc(dev);
10598 restore_state = drm_atomic_state_alloc(dev);
10599 if (!state || !restore_state) {
10600 ret = -ENOMEM;
10601 goto fail;
10602 }
10603
10604 state->acquire_ctx = ctx;
10605 restore_state->acquire_ctx = ctx;
10606
10607 connector_state = drm_atomic_get_connector_state(state, connector);
10608 if (IS_ERR(connector_state)) {
10609 ret = PTR_ERR(connector_state);
10610 goto fail;
10611 }
10612
10613 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10614 if (ret)
10615 goto fail;
10616
10617 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10618 if (IS_ERR(crtc_state)) {
10619 ret = PTR_ERR(crtc_state);
10620 goto fail;
10621 }
10622
10623 crtc_state->base.active = crtc_state->base.enable = true;
10624
10625 if (!mode)
10626 mode = &load_detect_mode;
10627
10628 /* We need a framebuffer large enough to accommodate all accesses
10629 * that the plane may generate whilst we perform load detection.
10630 * We can not rely on the fbcon either being present (we get called
10631 * during its initialisation to detect all boot displays, or it may
10632 * not even exist) or that it is large enough to satisfy the
10633 * requested mode.
10634 */
10635 fb = mode_fits_in_fbdev(dev, mode);
10636 if (fb == NULL) {
10637 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10638 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10639 } else
10640 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10641 if (IS_ERR(fb)) {
10642 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10643 goto fail;
10644 }
10645
10646 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10647 if (ret)
10648 goto fail;
10649
10650 drm_framebuffer_unreference(fb);
10651
10652 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10653 if (ret)
10654 goto fail;
10655
10656 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10657 if (!ret)
10658 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10659 if (!ret)
10660 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10661 if (ret) {
10662 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10663 goto fail;
10664 }
10665
10666 ret = drm_atomic_commit(state);
10667 if (ret) {
10668 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10669 goto fail;
10670 }
10671
10672 old->restore_state = restore_state;
10673
10674 /* let the connector get through one full cycle before testing */
10675 intel_wait_for_vblank(dev, intel_crtc->pipe);
10676 return true;
10677
10678 fail:
10679 drm_atomic_state_free(state);
10680 drm_atomic_state_free(restore_state);
10681 restore_state = state = NULL;
10682
10683 if (ret == -EDEADLK) {
10684 drm_modeset_backoff(ctx);
10685 goto retry;
10686 }
10687
10688 return false;
10689 }
10690
10691 void intel_release_load_detect_pipe(struct drm_connector *connector,
10692 struct intel_load_detect_pipe *old,
10693 struct drm_modeset_acquire_ctx *ctx)
10694 {
10695 struct intel_encoder *intel_encoder =
10696 intel_attached_encoder(connector);
10697 struct drm_encoder *encoder = &intel_encoder->base;
10698 struct drm_atomic_state *state = old->restore_state;
10699 int ret;
10700
10701 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10702 connector->base.id, connector->name,
10703 encoder->base.id, encoder->name);
10704
10705 if (!state)
10706 return;
10707
10708 ret = drm_atomic_commit(state);
10709 if (ret) {
10710 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10711 drm_atomic_state_free(state);
10712 }
10713 }
10714
10715 static int i9xx_pll_refclk(struct drm_device *dev,
10716 const struct intel_crtc_state *pipe_config)
10717 {
10718 struct drm_i915_private *dev_priv = to_i915(dev);
10719 u32 dpll = pipe_config->dpll_hw_state.dpll;
10720
10721 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10722 return dev_priv->vbt.lvds_ssc_freq;
10723 else if (HAS_PCH_SPLIT(dev))
10724 return 120000;
10725 else if (!IS_GEN2(dev))
10726 return 96000;
10727 else
10728 return 48000;
10729 }
10730
10731 /* Returns the clock of the currently programmed mode of the given pipe. */
10732 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10733 struct intel_crtc_state *pipe_config)
10734 {
10735 struct drm_device *dev = crtc->base.dev;
10736 struct drm_i915_private *dev_priv = to_i915(dev);
10737 int pipe = pipe_config->cpu_transcoder;
10738 u32 dpll = pipe_config->dpll_hw_state.dpll;
10739 u32 fp;
10740 struct dpll clock;
10741 int port_clock;
10742 int refclk = i9xx_pll_refclk(dev, pipe_config);
10743
10744 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10745 fp = pipe_config->dpll_hw_state.fp0;
10746 else
10747 fp = pipe_config->dpll_hw_state.fp1;
10748
10749 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10750 if (IS_PINEVIEW(dev)) {
10751 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10752 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10753 } else {
10754 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10755 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10756 }
10757
10758 if (!IS_GEN2(dev)) {
10759 if (IS_PINEVIEW(dev))
10760 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10761 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10762 else
10763 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10764 DPLL_FPA01_P1_POST_DIV_SHIFT);
10765
10766 switch (dpll & DPLL_MODE_MASK) {
10767 case DPLLB_MODE_DAC_SERIAL:
10768 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10769 5 : 10;
10770 break;
10771 case DPLLB_MODE_LVDS:
10772 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10773 7 : 14;
10774 break;
10775 default:
10776 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10777 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10778 return;
10779 }
10780
10781 if (IS_PINEVIEW(dev))
10782 port_clock = pnv_calc_dpll_params(refclk, &clock);
10783 else
10784 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10785 } else {
10786 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10787 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10788
10789 if (is_lvds) {
10790 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10791 DPLL_FPA01_P1_POST_DIV_SHIFT);
10792
10793 if (lvds & LVDS_CLKB_POWER_UP)
10794 clock.p2 = 7;
10795 else
10796 clock.p2 = 14;
10797 } else {
10798 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10799 clock.p1 = 2;
10800 else {
10801 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10802 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10803 }
10804 if (dpll & PLL_P2_DIVIDE_BY_4)
10805 clock.p2 = 4;
10806 else
10807 clock.p2 = 2;
10808 }
10809
10810 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10811 }
10812
10813 /*
10814 * This value includes pixel_multiplier. We will use
10815 * port_clock to compute adjusted_mode.crtc_clock in the
10816 * encoder's get_config() function.
10817 */
10818 pipe_config->port_clock = port_clock;
10819 }
10820
10821 int intel_dotclock_calculate(int link_freq,
10822 const struct intel_link_m_n *m_n)
10823 {
10824 /*
10825 * The calculation for the data clock is:
10826 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10827 * But we want to avoid losing precison if possible, so:
10828 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10829 *
10830 * and the link clock is simpler:
10831 * link_clock = (m * link_clock) / n
10832 */
10833
10834 if (!m_n->link_n)
10835 return 0;
10836
10837 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10838 }
10839
10840 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10841 struct intel_crtc_state *pipe_config)
10842 {
10843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10844
10845 /* read out port_clock from the DPLL */
10846 i9xx_crtc_clock_get(crtc, pipe_config);
10847
10848 /*
10849 * In case there is an active pipe without active ports,
10850 * we may need some idea for the dotclock anyway.
10851 * Calculate one based on the FDI configuration.
10852 */
10853 pipe_config->base.adjusted_mode.crtc_clock =
10854 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10855 &pipe_config->fdi_m_n);
10856 }
10857
10858 /** Returns the currently programmed mode of the given pipe. */
10859 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10860 struct drm_crtc *crtc)
10861 {
10862 struct drm_i915_private *dev_priv = to_i915(dev);
10863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10864 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10865 struct drm_display_mode *mode;
10866 struct intel_crtc_state *pipe_config;
10867 int htot = I915_READ(HTOTAL(cpu_transcoder));
10868 int hsync = I915_READ(HSYNC(cpu_transcoder));
10869 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10870 int vsync = I915_READ(VSYNC(cpu_transcoder));
10871 enum pipe pipe = intel_crtc->pipe;
10872
10873 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10874 if (!mode)
10875 return NULL;
10876
10877 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10878 if (!pipe_config) {
10879 kfree(mode);
10880 return NULL;
10881 }
10882
10883 /*
10884 * Construct a pipe_config sufficient for getting the clock info
10885 * back out of crtc_clock_get.
10886 *
10887 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10888 * to use a real value here instead.
10889 */
10890 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10891 pipe_config->pixel_multiplier = 1;
10892 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10893 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10894 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10895 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10896
10897 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10898 mode->hdisplay = (htot & 0xffff) + 1;
10899 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10900 mode->hsync_start = (hsync & 0xffff) + 1;
10901 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10902 mode->vdisplay = (vtot & 0xffff) + 1;
10903 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10904 mode->vsync_start = (vsync & 0xffff) + 1;
10905 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10906
10907 drm_mode_set_name(mode);
10908
10909 kfree(pipe_config);
10910
10911 return mode;
10912 }
10913
10914 static void intel_crtc_destroy(struct drm_crtc *crtc)
10915 {
10916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10917 struct drm_device *dev = crtc->dev;
10918 struct intel_flip_work *work;
10919
10920 spin_lock_irq(&dev->event_lock);
10921 work = intel_crtc->flip_work;
10922 intel_crtc->flip_work = NULL;
10923 spin_unlock_irq(&dev->event_lock);
10924
10925 if (work) {
10926 cancel_work_sync(&work->mmio_work);
10927 cancel_work_sync(&work->unpin_work);
10928 kfree(work);
10929 }
10930
10931 drm_crtc_cleanup(crtc);
10932
10933 kfree(intel_crtc);
10934 }
10935
10936 static void intel_unpin_work_fn(struct work_struct *__work)
10937 {
10938 struct intel_flip_work *work =
10939 container_of(__work, struct intel_flip_work, unpin_work);
10940 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10941 struct drm_device *dev = crtc->base.dev;
10942 struct drm_plane *primary = crtc->base.primary;
10943
10944 if (is_mmio_work(work))
10945 flush_work(&work->mmio_work);
10946
10947 mutex_lock(&dev->struct_mutex);
10948 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10949 i915_gem_object_put(work->pending_flip_obj);
10950 mutex_unlock(&dev->struct_mutex);
10951
10952 i915_gem_request_put(work->flip_queued_req);
10953
10954 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10955 intel_fbc_post_update(crtc);
10956 drm_framebuffer_unreference(work->old_fb);
10957
10958 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10959 atomic_dec(&crtc->unpin_work_count);
10960
10961 kfree(work);
10962 }
10963
10964 /* Is 'a' after or equal to 'b'? */
10965 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10966 {
10967 return !((a - b) & 0x80000000);
10968 }
10969
10970 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10971 struct intel_flip_work *work)
10972 {
10973 struct drm_device *dev = crtc->base.dev;
10974 struct drm_i915_private *dev_priv = to_i915(dev);
10975 unsigned reset_counter;
10976
10977 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10978 if (crtc->reset_counter != reset_counter)
10979 return true;
10980
10981 /*
10982 * The relevant registers doen't exist on pre-ctg.
10983 * As the flip done interrupt doesn't trigger for mmio
10984 * flips on gmch platforms, a flip count check isn't
10985 * really needed there. But since ctg has the registers,
10986 * include it in the check anyway.
10987 */
10988 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10989 return true;
10990
10991 /*
10992 * BDW signals flip done immediately if the plane
10993 * is disabled, even if the plane enable is already
10994 * armed to occur at the next vblank :(
10995 */
10996
10997 /*
10998 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10999 * used the same base address. In that case the mmio flip might
11000 * have completed, but the CS hasn't even executed the flip yet.
11001 *
11002 * A flip count check isn't enough as the CS might have updated
11003 * the base address just after start of vblank, but before we
11004 * managed to process the interrupt. This means we'd complete the
11005 * CS flip too soon.
11006 *
11007 * Combining both checks should get us a good enough result. It may
11008 * still happen that the CS flip has been executed, but has not
11009 * yet actually completed. But in case the base address is the same
11010 * anyway, we don't really care.
11011 */
11012 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11013 crtc->flip_work->gtt_offset &&
11014 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11015 crtc->flip_work->flip_count);
11016 }
11017
11018 static bool
11019 __pageflip_finished_mmio(struct intel_crtc *crtc,
11020 struct intel_flip_work *work)
11021 {
11022 /*
11023 * MMIO work completes when vblank is different from
11024 * flip_queued_vblank.
11025 *
11026 * Reset counter value doesn't matter, this is handled by
11027 * i915_wait_request finishing early, so no need to handle
11028 * reset here.
11029 */
11030 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11031 }
11032
11033
11034 static bool pageflip_finished(struct intel_crtc *crtc,
11035 struct intel_flip_work *work)
11036 {
11037 if (!atomic_read(&work->pending))
11038 return false;
11039
11040 smp_rmb();
11041
11042 if (is_mmio_work(work))
11043 return __pageflip_finished_mmio(crtc, work);
11044 else
11045 return __pageflip_finished_cs(crtc, work);
11046 }
11047
11048 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11049 {
11050 struct drm_device *dev = &dev_priv->drm;
11051 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11053 struct intel_flip_work *work;
11054 unsigned long flags;
11055
11056 /* Ignore early vblank irqs */
11057 if (!crtc)
11058 return;
11059
11060 /*
11061 * This is called both by irq handlers and the reset code (to complete
11062 * lost pageflips) so needs the full irqsave spinlocks.
11063 */
11064 spin_lock_irqsave(&dev->event_lock, flags);
11065 work = intel_crtc->flip_work;
11066
11067 if (work != NULL &&
11068 !is_mmio_work(work) &&
11069 pageflip_finished(intel_crtc, work))
11070 page_flip_completed(intel_crtc);
11071
11072 spin_unlock_irqrestore(&dev->event_lock, flags);
11073 }
11074
11075 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11076 {
11077 struct drm_device *dev = &dev_priv->drm;
11078 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11080 struct intel_flip_work *work;
11081 unsigned long flags;
11082
11083 /* Ignore early vblank irqs */
11084 if (!crtc)
11085 return;
11086
11087 /*
11088 * This is called both by irq handlers and the reset code (to complete
11089 * lost pageflips) so needs the full irqsave spinlocks.
11090 */
11091 spin_lock_irqsave(&dev->event_lock, flags);
11092 work = intel_crtc->flip_work;
11093
11094 if (work != NULL &&
11095 is_mmio_work(work) &&
11096 pageflip_finished(intel_crtc, work))
11097 page_flip_completed(intel_crtc);
11098
11099 spin_unlock_irqrestore(&dev->event_lock, flags);
11100 }
11101
11102 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11103 struct intel_flip_work *work)
11104 {
11105 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11106
11107 /* Ensure that the work item is consistent when activating it ... */
11108 smp_mb__before_atomic();
11109 atomic_set(&work->pending, 1);
11110 }
11111
11112 static int intel_gen2_queue_flip(struct drm_device *dev,
11113 struct drm_crtc *crtc,
11114 struct drm_framebuffer *fb,
11115 struct drm_i915_gem_object *obj,
11116 struct drm_i915_gem_request *req,
11117 uint32_t flags)
11118 {
11119 struct intel_ring *ring = req->ring;
11120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11121 u32 flip_mask;
11122 int ret;
11123
11124 ret = intel_ring_begin(req, 6);
11125 if (ret)
11126 return ret;
11127
11128 /* Can't queue multiple flips, so wait for the previous
11129 * one to finish before executing the next.
11130 */
11131 if (intel_crtc->plane)
11132 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11133 else
11134 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11135 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11136 intel_ring_emit(ring, MI_NOOP);
11137 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11139 intel_ring_emit(ring, fb->pitches[0]);
11140 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11141 intel_ring_emit(ring, 0); /* aux display base address, unused */
11142
11143 return 0;
11144 }
11145
11146 static int intel_gen3_queue_flip(struct drm_device *dev,
11147 struct drm_crtc *crtc,
11148 struct drm_framebuffer *fb,
11149 struct drm_i915_gem_object *obj,
11150 struct drm_i915_gem_request *req,
11151 uint32_t flags)
11152 {
11153 struct intel_ring *ring = req->ring;
11154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11155 u32 flip_mask;
11156 int ret;
11157
11158 ret = intel_ring_begin(req, 6);
11159 if (ret)
11160 return ret;
11161
11162 if (intel_crtc->plane)
11163 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11164 else
11165 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11166 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11167 intel_ring_emit(ring, MI_NOOP);
11168 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11169 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11170 intel_ring_emit(ring, fb->pitches[0]);
11171 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11172 intel_ring_emit(ring, MI_NOOP);
11173
11174 return 0;
11175 }
11176
11177 static int intel_gen4_queue_flip(struct drm_device *dev,
11178 struct drm_crtc *crtc,
11179 struct drm_framebuffer *fb,
11180 struct drm_i915_gem_object *obj,
11181 struct drm_i915_gem_request *req,
11182 uint32_t flags)
11183 {
11184 struct intel_ring *ring = req->ring;
11185 struct drm_i915_private *dev_priv = to_i915(dev);
11186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11187 uint32_t pf, pipesrc;
11188 int ret;
11189
11190 ret = intel_ring_begin(req, 4);
11191 if (ret)
11192 return ret;
11193
11194 /* i965+ uses the linear or tiled offsets from the
11195 * Display Registers (which do not change across a page-flip)
11196 * so we need only reprogram the base address.
11197 */
11198 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11199 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11200 intel_ring_emit(ring, fb->pitches[0]);
11201 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11202 obj->tiling_mode);
11203
11204 /* XXX Enabling the panel-fitter across page-flip is so far
11205 * untested on non-native modes, so ignore it for now.
11206 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11207 */
11208 pf = 0;
11209 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11210 intel_ring_emit(ring, pf | pipesrc);
11211
11212 return 0;
11213 }
11214
11215 static int intel_gen6_queue_flip(struct drm_device *dev,
11216 struct drm_crtc *crtc,
11217 struct drm_framebuffer *fb,
11218 struct drm_i915_gem_object *obj,
11219 struct drm_i915_gem_request *req,
11220 uint32_t flags)
11221 {
11222 struct intel_ring *ring = req->ring;
11223 struct drm_i915_private *dev_priv = to_i915(dev);
11224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11225 uint32_t pf, pipesrc;
11226 int ret;
11227
11228 ret = intel_ring_begin(req, 4);
11229 if (ret)
11230 return ret;
11231
11232 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11233 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11234 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11235 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11236
11237 /* Contrary to the suggestions in the documentation,
11238 * "Enable Panel Fitter" does not seem to be required when page
11239 * flipping with a non-native mode, and worse causes a normal
11240 * modeset to fail.
11241 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11242 */
11243 pf = 0;
11244 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11245 intel_ring_emit(ring, pf | pipesrc);
11246
11247 return 0;
11248 }
11249
11250 static int intel_gen7_queue_flip(struct drm_device *dev,
11251 struct drm_crtc *crtc,
11252 struct drm_framebuffer *fb,
11253 struct drm_i915_gem_object *obj,
11254 struct drm_i915_gem_request *req,
11255 uint32_t flags)
11256 {
11257 struct intel_ring *ring = req->ring;
11258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11259 uint32_t plane_bit = 0;
11260 int len, ret;
11261
11262 switch (intel_crtc->plane) {
11263 case PLANE_A:
11264 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11265 break;
11266 case PLANE_B:
11267 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11268 break;
11269 case PLANE_C:
11270 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11271 break;
11272 default:
11273 WARN_ONCE(1, "unknown plane in flip command\n");
11274 return -ENODEV;
11275 }
11276
11277 len = 4;
11278 if (req->engine->id == RCS) {
11279 len += 6;
11280 /*
11281 * On Gen 8, SRM is now taking an extra dword to accommodate
11282 * 48bits addresses, and we need a NOOP for the batch size to
11283 * stay even.
11284 */
11285 if (IS_GEN8(dev))
11286 len += 2;
11287 }
11288
11289 /*
11290 * BSpec MI_DISPLAY_FLIP for IVB:
11291 * "The full packet must be contained within the same cache line."
11292 *
11293 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11294 * cacheline, if we ever start emitting more commands before
11295 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11296 * then do the cacheline alignment, and finally emit the
11297 * MI_DISPLAY_FLIP.
11298 */
11299 ret = intel_ring_cacheline_align(req);
11300 if (ret)
11301 return ret;
11302
11303 ret = intel_ring_begin(req, len);
11304 if (ret)
11305 return ret;
11306
11307 /* Unmask the flip-done completion message. Note that the bspec says that
11308 * we should do this for both the BCS and RCS, and that we must not unmask
11309 * more than one flip event at any time (or ensure that one flip message
11310 * can be sent by waiting for flip-done prior to queueing new flips).
11311 * Experimentation says that BCS works despite DERRMR masking all
11312 * flip-done completion events and that unmasking all planes at once
11313 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11314 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11315 */
11316 if (req->engine->id == RCS) {
11317 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11318 intel_ring_emit_reg(ring, DERRMR);
11319 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11320 DERRMR_PIPEB_PRI_FLIP_DONE |
11321 DERRMR_PIPEC_PRI_FLIP_DONE));
11322 if (IS_GEN8(dev))
11323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11324 MI_SRM_LRM_GLOBAL_GTT);
11325 else
11326 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11327 MI_SRM_LRM_GLOBAL_GTT);
11328 intel_ring_emit_reg(ring, DERRMR);
11329 intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);
11330 if (IS_GEN8(dev)) {
11331 intel_ring_emit(ring, 0);
11332 intel_ring_emit(ring, MI_NOOP);
11333 }
11334 }
11335
11336 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11337 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11338 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11339 intel_ring_emit(ring, (MI_NOOP));
11340
11341 return 0;
11342 }
11343
11344 static bool use_mmio_flip(struct intel_engine_cs *engine,
11345 struct drm_i915_gem_object *obj)
11346 {
11347 struct reservation_object *resv;
11348
11349 /*
11350 * This is not being used for older platforms, because
11351 * non-availability of flip done interrupt forces us to use
11352 * CS flips. Older platforms derive flip done using some clever
11353 * tricks involving the flip_pending status bits and vblank irqs.
11354 * So using MMIO flips there would disrupt this mechanism.
11355 */
11356
11357 if (engine == NULL)
11358 return true;
11359
11360 if (INTEL_GEN(engine->i915) < 5)
11361 return false;
11362
11363 if (i915.use_mmio_flip < 0)
11364 return false;
11365 else if (i915.use_mmio_flip > 0)
11366 return true;
11367 else if (i915.enable_execlists)
11368 return true;
11369
11370 resv = i915_gem_object_get_dmabuf_resv(obj);
11371 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11372 return true;
11373
11374 return engine != i915_gem_active_get_engine(&obj->last_write,
11375 &obj->base.dev->struct_mutex);
11376 }
11377
11378 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11379 unsigned int rotation,
11380 struct intel_flip_work *work)
11381 {
11382 struct drm_device *dev = intel_crtc->base.dev;
11383 struct drm_i915_private *dev_priv = to_i915(dev);
11384 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11385 const enum pipe pipe = intel_crtc->pipe;
11386 u32 ctl, stride, tile_height;
11387
11388 ctl = I915_READ(PLANE_CTL(pipe, 0));
11389 ctl &= ~PLANE_CTL_TILED_MASK;
11390 switch (fb->modifier[0]) {
11391 case DRM_FORMAT_MOD_NONE:
11392 break;
11393 case I915_FORMAT_MOD_X_TILED:
11394 ctl |= PLANE_CTL_TILED_X;
11395 break;
11396 case I915_FORMAT_MOD_Y_TILED:
11397 ctl |= PLANE_CTL_TILED_Y;
11398 break;
11399 case I915_FORMAT_MOD_Yf_TILED:
11400 ctl |= PLANE_CTL_TILED_YF;
11401 break;
11402 default:
11403 MISSING_CASE(fb->modifier[0]);
11404 }
11405
11406 /*
11407 * The stride is either expressed as a multiple of 64 bytes chunks for
11408 * linear buffers or in number of tiles for tiled buffers.
11409 */
11410 if (intel_rotation_90_or_270(rotation)) {
11411 /* stride = Surface height in tiles */
11412 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11413 stride = DIV_ROUND_UP(fb->height, tile_height);
11414 } else {
11415 stride = fb->pitches[0] /
11416 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11417 fb->pixel_format);
11418 }
11419
11420 /*
11421 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11422 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11423 */
11424 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11425 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11426
11427 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11428 POSTING_READ(PLANE_SURF(pipe, 0));
11429 }
11430
11431 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11432 struct intel_flip_work *work)
11433 {
11434 struct drm_device *dev = intel_crtc->base.dev;
11435 struct drm_i915_private *dev_priv = to_i915(dev);
11436 struct intel_framebuffer *intel_fb =
11437 to_intel_framebuffer(intel_crtc->base.primary->fb);
11438 struct drm_i915_gem_object *obj = intel_fb->obj;
11439 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11440 u32 dspcntr;
11441
11442 dspcntr = I915_READ(reg);
11443
11444 if (obj->tiling_mode != I915_TILING_NONE)
11445 dspcntr |= DISPPLANE_TILED;
11446 else
11447 dspcntr &= ~DISPPLANE_TILED;
11448
11449 I915_WRITE(reg, dspcntr);
11450
11451 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11452 POSTING_READ(DSPSURF(intel_crtc->plane));
11453 }
11454
11455 static void intel_mmio_flip_work_func(struct work_struct *w)
11456 {
11457 struct intel_flip_work *work =
11458 container_of(w, struct intel_flip_work, mmio_work);
11459 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11460 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11461 struct intel_framebuffer *intel_fb =
11462 to_intel_framebuffer(crtc->base.primary->fb);
11463 struct drm_i915_gem_object *obj = intel_fb->obj;
11464 struct reservation_object *resv;
11465
11466 if (work->flip_queued_req)
11467 WARN_ON(i915_wait_request(work->flip_queued_req,
11468 false, NULL,
11469 NO_WAITBOOST));
11470
11471 /* For framebuffer backed by dmabuf, wait for fence */
11472 resv = i915_gem_object_get_dmabuf_resv(obj);
11473 if (resv)
11474 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11475 MAX_SCHEDULE_TIMEOUT) < 0);
11476
11477 intel_pipe_update_start(crtc);
11478
11479 if (INTEL_GEN(dev_priv) >= 9)
11480 skl_do_mmio_flip(crtc, work->rotation, work);
11481 else
11482 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11483 ilk_do_mmio_flip(crtc, work);
11484
11485 intel_pipe_update_end(crtc, work);
11486 }
11487
11488 static int intel_default_queue_flip(struct drm_device *dev,
11489 struct drm_crtc *crtc,
11490 struct drm_framebuffer *fb,
11491 struct drm_i915_gem_object *obj,
11492 struct drm_i915_gem_request *req,
11493 uint32_t flags)
11494 {
11495 return -ENODEV;
11496 }
11497
11498 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11499 struct intel_crtc *intel_crtc,
11500 struct intel_flip_work *work)
11501 {
11502 u32 addr, vblank;
11503
11504 if (!atomic_read(&work->pending))
11505 return false;
11506
11507 smp_rmb();
11508
11509 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11510 if (work->flip_ready_vblank == 0) {
11511 if (work->flip_queued_req &&
11512 !i915_gem_request_completed(work->flip_queued_req))
11513 return false;
11514
11515 work->flip_ready_vblank = vblank;
11516 }
11517
11518 if (vblank - work->flip_ready_vblank < 3)
11519 return false;
11520
11521 /* Potential stall - if we see that the flip has happened,
11522 * assume a missed interrupt. */
11523 if (INTEL_GEN(dev_priv) >= 4)
11524 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11525 else
11526 addr = I915_READ(DSPADDR(intel_crtc->plane));
11527
11528 /* There is a potential issue here with a false positive after a flip
11529 * to the same address. We could address this by checking for a
11530 * non-incrementing frame counter.
11531 */
11532 return addr == work->gtt_offset;
11533 }
11534
11535 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11536 {
11537 struct drm_device *dev = &dev_priv->drm;
11538 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11540 struct intel_flip_work *work;
11541
11542 WARN_ON(!in_interrupt());
11543
11544 if (crtc == NULL)
11545 return;
11546
11547 spin_lock(&dev->event_lock);
11548 work = intel_crtc->flip_work;
11549
11550 if (work != NULL && !is_mmio_work(work) &&
11551 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11552 WARN_ONCE(1,
11553 "Kicking stuck page flip: queued at %d, now %d\n",
11554 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11555 page_flip_completed(intel_crtc);
11556 work = NULL;
11557 }
11558
11559 if (work != NULL && !is_mmio_work(work) &&
11560 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11561 intel_queue_rps_boost_for_request(work->flip_queued_req);
11562 spin_unlock(&dev->event_lock);
11563 }
11564
11565 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11566 struct drm_framebuffer *fb,
11567 struct drm_pending_vblank_event *event,
11568 uint32_t page_flip_flags)
11569 {
11570 struct drm_device *dev = crtc->dev;
11571 struct drm_i915_private *dev_priv = to_i915(dev);
11572 struct drm_framebuffer *old_fb = crtc->primary->fb;
11573 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11575 struct drm_plane *primary = crtc->primary;
11576 enum pipe pipe = intel_crtc->pipe;
11577 struct intel_flip_work *work;
11578 struct intel_engine_cs *engine;
11579 bool mmio_flip;
11580 struct drm_i915_gem_request *request;
11581 int ret;
11582
11583 /*
11584 * drm_mode_page_flip_ioctl() should already catch this, but double
11585 * check to be safe. In the future we may enable pageflipping from
11586 * a disabled primary plane.
11587 */
11588 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11589 return -EBUSY;
11590
11591 /* Can't change pixel format via MI display flips. */
11592 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11593 return -EINVAL;
11594
11595 /*
11596 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11597 * Note that pitch changes could also affect these register.
11598 */
11599 if (INTEL_INFO(dev)->gen > 3 &&
11600 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11601 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11602 return -EINVAL;
11603
11604 if (i915_terminally_wedged(&dev_priv->gpu_error))
11605 goto out_hang;
11606
11607 work = kzalloc(sizeof(*work), GFP_KERNEL);
11608 if (work == NULL)
11609 return -ENOMEM;
11610
11611 work->event = event;
11612 work->crtc = crtc;
11613 work->old_fb = old_fb;
11614 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11615
11616 ret = drm_crtc_vblank_get(crtc);
11617 if (ret)
11618 goto free_work;
11619
11620 /* We borrow the event spin lock for protecting flip_work */
11621 spin_lock_irq(&dev->event_lock);
11622 if (intel_crtc->flip_work) {
11623 /* Before declaring the flip queue wedged, check if
11624 * the hardware completed the operation behind our backs.
11625 */
11626 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11627 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11628 page_flip_completed(intel_crtc);
11629 } else {
11630 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11631 spin_unlock_irq(&dev->event_lock);
11632
11633 drm_crtc_vblank_put(crtc);
11634 kfree(work);
11635 return -EBUSY;
11636 }
11637 }
11638 intel_crtc->flip_work = work;
11639 spin_unlock_irq(&dev->event_lock);
11640
11641 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11642 flush_workqueue(dev_priv->wq);
11643
11644 /* Reference the objects for the scheduled work. */
11645 drm_framebuffer_reference(work->old_fb);
11646
11647 crtc->primary->fb = fb;
11648 update_state_fb(crtc->primary);
11649
11650 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11651 to_intel_plane_state(primary->state));
11652
11653 work->pending_flip_obj = i915_gem_object_get(obj);
11654
11655 ret = i915_mutex_lock_interruptible(dev);
11656 if (ret)
11657 goto cleanup;
11658
11659 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11660 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11661 ret = -EIO;
11662 goto cleanup;
11663 }
11664
11665 atomic_inc(&intel_crtc->unpin_work_count);
11666
11667 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11668 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11669
11670 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11671 engine = &dev_priv->engine[BCS];
11672 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11673 /* vlv: DISPLAY_FLIP fails to change tiling */
11674 engine = NULL;
11675 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11676 engine = &dev_priv->engine[BCS];
11677 } else if (INTEL_INFO(dev)->gen >= 7) {
11678 engine = i915_gem_active_get_engine(&obj->last_write,
11679 &obj->base.dev->struct_mutex);
11680 if (engine == NULL || engine->id != RCS)
11681 engine = &dev_priv->engine[BCS];
11682 } else {
11683 engine = &dev_priv->engine[RCS];
11684 }
11685
11686 mmio_flip = use_mmio_flip(engine, obj);
11687
11688 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11689 if (ret)
11690 goto cleanup_pending;
11691
11692 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11693 obj, 0);
11694 work->gtt_offset += intel_crtc->dspaddr_offset;
11695 work->rotation = crtc->primary->state->rotation;
11696
11697 if (mmio_flip) {
11698 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11699
11700 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
11701 &obj->base.dev->struct_mutex);
11702 schedule_work(&work->mmio_work);
11703 } else {
11704 request = i915_gem_request_alloc(engine, engine->last_context);
11705 if (IS_ERR(request)) {
11706 ret = PTR_ERR(request);
11707 goto cleanup_unpin;
11708 }
11709
11710 ret = i915_gem_object_sync(obj, request);
11711 if (ret)
11712 goto cleanup_request;
11713
11714 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11715 page_flip_flags);
11716 if (ret)
11717 goto cleanup_request;
11718
11719 intel_mark_page_flip_active(intel_crtc, work);
11720
11721 work->flip_queued_req = i915_gem_request_get(request);
11722 i915_add_request_no_flush(request);
11723 }
11724
11725 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11726 to_intel_plane(primary)->frontbuffer_bit);
11727 mutex_unlock(&dev->struct_mutex);
11728
11729 intel_frontbuffer_flip_prepare(dev,
11730 to_intel_plane(primary)->frontbuffer_bit);
11731
11732 trace_i915_flip_request(intel_crtc->plane, obj);
11733
11734 return 0;
11735
11736 cleanup_request:
11737 i915_add_request_no_flush(request);
11738 cleanup_unpin:
11739 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11740 cleanup_pending:
11741 atomic_dec(&intel_crtc->unpin_work_count);
11742 mutex_unlock(&dev->struct_mutex);
11743 cleanup:
11744 crtc->primary->fb = old_fb;
11745 update_state_fb(crtc->primary);
11746
11747 i915_gem_object_put_unlocked(obj);
11748 drm_framebuffer_unreference(work->old_fb);
11749
11750 spin_lock_irq(&dev->event_lock);
11751 intel_crtc->flip_work = NULL;
11752 spin_unlock_irq(&dev->event_lock);
11753
11754 drm_crtc_vblank_put(crtc);
11755 free_work:
11756 kfree(work);
11757
11758 if (ret == -EIO) {
11759 struct drm_atomic_state *state;
11760 struct drm_plane_state *plane_state;
11761
11762 out_hang:
11763 state = drm_atomic_state_alloc(dev);
11764 if (!state)
11765 return -ENOMEM;
11766 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11767
11768 retry:
11769 plane_state = drm_atomic_get_plane_state(state, primary);
11770 ret = PTR_ERR_OR_ZERO(plane_state);
11771 if (!ret) {
11772 drm_atomic_set_fb_for_plane(plane_state, fb);
11773
11774 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11775 if (!ret)
11776 ret = drm_atomic_commit(state);
11777 }
11778
11779 if (ret == -EDEADLK) {
11780 drm_modeset_backoff(state->acquire_ctx);
11781 drm_atomic_state_clear(state);
11782 goto retry;
11783 }
11784
11785 if (ret)
11786 drm_atomic_state_free(state);
11787
11788 if (ret == 0 && event) {
11789 spin_lock_irq(&dev->event_lock);
11790 drm_crtc_send_vblank_event(crtc, event);
11791 spin_unlock_irq(&dev->event_lock);
11792 }
11793 }
11794 return ret;
11795 }
11796
11797
11798 /**
11799 * intel_wm_need_update - Check whether watermarks need updating
11800 * @plane: drm plane
11801 * @state: new plane state
11802 *
11803 * Check current plane state versus the new one to determine whether
11804 * watermarks need to be recalculated.
11805 *
11806 * Returns true or false.
11807 */
11808 static bool intel_wm_need_update(struct drm_plane *plane,
11809 struct drm_plane_state *state)
11810 {
11811 struct intel_plane_state *new = to_intel_plane_state(state);
11812 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11813
11814 /* Update watermarks on tiling or size changes. */
11815 if (new->visible != cur->visible)
11816 return true;
11817
11818 if (!cur->base.fb || !new->base.fb)
11819 return false;
11820
11821 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11822 cur->base.rotation != new->base.rotation ||
11823 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11824 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11825 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11826 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11827 return true;
11828
11829 return false;
11830 }
11831
11832 static bool needs_scaling(struct intel_plane_state *state)
11833 {
11834 int src_w = drm_rect_width(&state->src) >> 16;
11835 int src_h = drm_rect_height(&state->src) >> 16;
11836 int dst_w = drm_rect_width(&state->dst);
11837 int dst_h = drm_rect_height(&state->dst);
11838
11839 return (src_w != dst_w || src_h != dst_h);
11840 }
11841
11842 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11843 struct drm_plane_state *plane_state)
11844 {
11845 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11846 struct drm_crtc *crtc = crtc_state->crtc;
11847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11848 struct drm_plane *plane = plane_state->plane;
11849 struct drm_device *dev = crtc->dev;
11850 struct drm_i915_private *dev_priv = to_i915(dev);
11851 struct intel_plane_state *old_plane_state =
11852 to_intel_plane_state(plane->state);
11853 bool mode_changed = needs_modeset(crtc_state);
11854 bool was_crtc_enabled = crtc->state->active;
11855 bool is_crtc_enabled = crtc_state->active;
11856 bool turn_off, turn_on, visible, was_visible;
11857 struct drm_framebuffer *fb = plane_state->fb;
11858 int ret;
11859
11860 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
11861 ret = skl_update_scaler_plane(
11862 to_intel_crtc_state(crtc_state),
11863 to_intel_plane_state(plane_state));
11864 if (ret)
11865 return ret;
11866 }
11867
11868 was_visible = old_plane_state->visible;
11869 visible = to_intel_plane_state(plane_state)->visible;
11870
11871 if (!was_crtc_enabled && WARN_ON(was_visible))
11872 was_visible = false;
11873
11874 /*
11875 * Visibility is calculated as if the crtc was on, but
11876 * after scaler setup everything depends on it being off
11877 * when the crtc isn't active.
11878 *
11879 * FIXME this is wrong for watermarks. Watermarks should also
11880 * be computed as if the pipe would be active. Perhaps move
11881 * per-plane wm computation to the .check_plane() hook, and
11882 * only combine the results from all planes in the current place?
11883 */
11884 if (!is_crtc_enabled)
11885 to_intel_plane_state(plane_state)->visible = visible = false;
11886
11887 if (!was_visible && !visible)
11888 return 0;
11889
11890 if (fb != old_plane_state->base.fb)
11891 pipe_config->fb_changed = true;
11892
11893 turn_off = was_visible && (!visible || mode_changed);
11894 turn_on = visible && (!was_visible || mode_changed);
11895
11896 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11897 intel_crtc->base.base.id,
11898 intel_crtc->base.name,
11899 plane->base.id, plane->name,
11900 fb ? fb->base.id : -1);
11901
11902 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11903 plane->base.id, plane->name,
11904 was_visible, visible,
11905 turn_off, turn_on, mode_changed);
11906
11907 if (turn_on) {
11908 pipe_config->update_wm_pre = true;
11909
11910 /* must disable cxsr around plane enable/disable */
11911 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11912 pipe_config->disable_cxsr = true;
11913 } else if (turn_off) {
11914 pipe_config->update_wm_post = true;
11915
11916 /* must disable cxsr around plane enable/disable */
11917 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11918 pipe_config->disable_cxsr = true;
11919 } else if (intel_wm_need_update(plane, plane_state)) {
11920 /* FIXME bollocks */
11921 pipe_config->update_wm_pre = true;
11922 pipe_config->update_wm_post = true;
11923 }
11924
11925 /* Pre-gen9 platforms need two-step watermark updates */
11926 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11927 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11928 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11929
11930 if (visible || was_visible)
11931 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11932
11933 /*
11934 * WaCxSRDisabledForSpriteScaling:ivb
11935 *
11936 * cstate->update_wm was already set above, so this flag will
11937 * take effect when we commit and program watermarks.
11938 */
11939 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11940 needs_scaling(to_intel_plane_state(plane_state)) &&
11941 !needs_scaling(old_plane_state))
11942 pipe_config->disable_lp_wm = true;
11943
11944 return 0;
11945 }
11946
11947 static bool encoders_cloneable(const struct intel_encoder *a,
11948 const struct intel_encoder *b)
11949 {
11950 /* masks could be asymmetric, so check both ways */
11951 return a == b || (a->cloneable & (1 << b->type) &&
11952 b->cloneable & (1 << a->type));
11953 }
11954
11955 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11956 struct intel_crtc *crtc,
11957 struct intel_encoder *encoder)
11958 {
11959 struct intel_encoder *source_encoder;
11960 struct drm_connector *connector;
11961 struct drm_connector_state *connector_state;
11962 int i;
11963
11964 for_each_connector_in_state(state, connector, connector_state, i) {
11965 if (connector_state->crtc != &crtc->base)
11966 continue;
11967
11968 source_encoder =
11969 to_intel_encoder(connector_state->best_encoder);
11970 if (!encoders_cloneable(encoder, source_encoder))
11971 return false;
11972 }
11973
11974 return true;
11975 }
11976
11977 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11978 struct drm_crtc_state *crtc_state)
11979 {
11980 struct drm_device *dev = crtc->dev;
11981 struct drm_i915_private *dev_priv = to_i915(dev);
11982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11983 struct intel_crtc_state *pipe_config =
11984 to_intel_crtc_state(crtc_state);
11985 struct drm_atomic_state *state = crtc_state->state;
11986 int ret;
11987 bool mode_changed = needs_modeset(crtc_state);
11988
11989 if (mode_changed && !crtc_state->active)
11990 pipe_config->update_wm_post = true;
11991
11992 if (mode_changed && crtc_state->enable &&
11993 dev_priv->display.crtc_compute_clock &&
11994 !WARN_ON(pipe_config->shared_dpll)) {
11995 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11996 pipe_config);
11997 if (ret)
11998 return ret;
11999 }
12000
12001 if (crtc_state->color_mgmt_changed) {
12002 ret = intel_color_check(crtc, crtc_state);
12003 if (ret)
12004 return ret;
12005
12006 /*
12007 * Changing color management on Intel hardware is
12008 * handled as part of planes update.
12009 */
12010 crtc_state->planes_changed = true;
12011 }
12012
12013 ret = 0;
12014 if (dev_priv->display.compute_pipe_wm) {
12015 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12016 if (ret) {
12017 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12018 return ret;
12019 }
12020 }
12021
12022 if (dev_priv->display.compute_intermediate_wm &&
12023 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12024 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12025 return 0;
12026
12027 /*
12028 * Calculate 'intermediate' watermarks that satisfy both the
12029 * old state and the new state. We can program these
12030 * immediately.
12031 */
12032 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12033 intel_crtc,
12034 pipe_config);
12035 if (ret) {
12036 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12037 return ret;
12038 }
12039 } else if (dev_priv->display.compute_intermediate_wm) {
12040 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12041 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12042 }
12043
12044 if (INTEL_INFO(dev)->gen >= 9) {
12045 if (mode_changed)
12046 ret = skl_update_scaler_crtc(pipe_config);
12047
12048 if (!ret)
12049 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12050 pipe_config);
12051 }
12052
12053 return ret;
12054 }
12055
12056 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12057 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12058 .atomic_begin = intel_begin_crtc_commit,
12059 .atomic_flush = intel_finish_crtc_commit,
12060 .atomic_check = intel_crtc_atomic_check,
12061 };
12062
12063 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12064 {
12065 struct intel_connector *connector;
12066
12067 for_each_intel_connector(dev, connector) {
12068 if (connector->base.state->crtc)
12069 drm_connector_unreference(&connector->base);
12070
12071 if (connector->base.encoder) {
12072 connector->base.state->best_encoder =
12073 connector->base.encoder;
12074 connector->base.state->crtc =
12075 connector->base.encoder->crtc;
12076
12077 drm_connector_reference(&connector->base);
12078 } else {
12079 connector->base.state->best_encoder = NULL;
12080 connector->base.state->crtc = NULL;
12081 }
12082 }
12083 }
12084
12085 static void
12086 connected_sink_compute_bpp(struct intel_connector *connector,
12087 struct intel_crtc_state *pipe_config)
12088 {
12089 int bpp = pipe_config->pipe_bpp;
12090
12091 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12092 connector->base.base.id,
12093 connector->base.name);
12094
12095 /* Don't use an invalid EDID bpc value */
12096 if (connector->base.display_info.bpc &&
12097 connector->base.display_info.bpc * 3 < bpp) {
12098 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12099 bpp, connector->base.display_info.bpc*3);
12100 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12101 }
12102
12103 /* Clamp bpp to default limit on screens without EDID 1.4 */
12104 if (connector->base.display_info.bpc == 0) {
12105 int type = connector->base.connector_type;
12106 int clamp_bpp = 24;
12107
12108 /* Fall back to 18 bpp when DP sink capability is unknown. */
12109 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12110 type == DRM_MODE_CONNECTOR_eDP)
12111 clamp_bpp = 18;
12112
12113 if (bpp > clamp_bpp) {
12114 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12115 bpp, clamp_bpp);
12116 pipe_config->pipe_bpp = clamp_bpp;
12117 }
12118 }
12119 }
12120
12121 static int
12122 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12123 struct intel_crtc_state *pipe_config)
12124 {
12125 struct drm_device *dev = crtc->base.dev;
12126 struct drm_atomic_state *state;
12127 struct drm_connector *connector;
12128 struct drm_connector_state *connector_state;
12129 int bpp, i;
12130
12131 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12132 bpp = 10*3;
12133 else if (INTEL_INFO(dev)->gen >= 5)
12134 bpp = 12*3;
12135 else
12136 bpp = 8*3;
12137
12138
12139 pipe_config->pipe_bpp = bpp;
12140
12141 state = pipe_config->base.state;
12142
12143 /* Clamp display bpp to EDID value */
12144 for_each_connector_in_state(state, connector, connector_state, i) {
12145 if (connector_state->crtc != &crtc->base)
12146 continue;
12147
12148 connected_sink_compute_bpp(to_intel_connector(connector),
12149 pipe_config);
12150 }
12151
12152 return bpp;
12153 }
12154
12155 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12156 {
12157 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12158 "type: 0x%x flags: 0x%x\n",
12159 mode->crtc_clock,
12160 mode->crtc_hdisplay, mode->crtc_hsync_start,
12161 mode->crtc_hsync_end, mode->crtc_htotal,
12162 mode->crtc_vdisplay, mode->crtc_vsync_start,
12163 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12164 }
12165
12166 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12167 struct intel_crtc_state *pipe_config,
12168 const char *context)
12169 {
12170 struct drm_device *dev = crtc->base.dev;
12171 struct drm_plane *plane;
12172 struct intel_plane *intel_plane;
12173 struct intel_plane_state *state;
12174 struct drm_framebuffer *fb;
12175
12176 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12177 crtc->base.base.id, crtc->base.name,
12178 context, pipe_config, pipe_name(crtc->pipe));
12179
12180 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12181 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12182 pipe_config->pipe_bpp, pipe_config->dither);
12183 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12184 pipe_config->has_pch_encoder,
12185 pipe_config->fdi_lanes,
12186 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12187 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12188 pipe_config->fdi_m_n.tu);
12189 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12190 intel_crtc_has_dp_encoder(pipe_config),
12191 pipe_config->lane_count,
12192 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12193 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12194 pipe_config->dp_m_n.tu);
12195
12196 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12197 intel_crtc_has_dp_encoder(pipe_config),
12198 pipe_config->lane_count,
12199 pipe_config->dp_m2_n2.gmch_m,
12200 pipe_config->dp_m2_n2.gmch_n,
12201 pipe_config->dp_m2_n2.link_m,
12202 pipe_config->dp_m2_n2.link_n,
12203 pipe_config->dp_m2_n2.tu);
12204
12205 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12206 pipe_config->has_audio,
12207 pipe_config->has_infoframe);
12208
12209 DRM_DEBUG_KMS("requested mode:\n");
12210 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12211 DRM_DEBUG_KMS("adjusted mode:\n");
12212 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12213 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12214 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12215 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12216 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12217 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12218 crtc->num_scalers,
12219 pipe_config->scaler_state.scaler_users,
12220 pipe_config->scaler_state.scaler_id);
12221 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12222 pipe_config->gmch_pfit.control,
12223 pipe_config->gmch_pfit.pgm_ratios,
12224 pipe_config->gmch_pfit.lvds_border_bits);
12225 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12226 pipe_config->pch_pfit.pos,
12227 pipe_config->pch_pfit.size,
12228 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12229 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12230 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12231
12232 if (IS_BROXTON(dev)) {
12233 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12234 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12235 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12236 pipe_config->ddi_pll_sel,
12237 pipe_config->dpll_hw_state.ebb0,
12238 pipe_config->dpll_hw_state.ebb4,
12239 pipe_config->dpll_hw_state.pll0,
12240 pipe_config->dpll_hw_state.pll1,
12241 pipe_config->dpll_hw_state.pll2,
12242 pipe_config->dpll_hw_state.pll3,
12243 pipe_config->dpll_hw_state.pll6,
12244 pipe_config->dpll_hw_state.pll8,
12245 pipe_config->dpll_hw_state.pll9,
12246 pipe_config->dpll_hw_state.pll10,
12247 pipe_config->dpll_hw_state.pcsdw12);
12248 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12249 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12250 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12251 pipe_config->ddi_pll_sel,
12252 pipe_config->dpll_hw_state.ctrl1,
12253 pipe_config->dpll_hw_state.cfgcr1,
12254 pipe_config->dpll_hw_state.cfgcr2);
12255 } else if (HAS_DDI(dev)) {
12256 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12257 pipe_config->ddi_pll_sel,
12258 pipe_config->dpll_hw_state.wrpll,
12259 pipe_config->dpll_hw_state.spll);
12260 } else {
12261 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12262 "fp0: 0x%x, fp1: 0x%x\n",
12263 pipe_config->dpll_hw_state.dpll,
12264 pipe_config->dpll_hw_state.dpll_md,
12265 pipe_config->dpll_hw_state.fp0,
12266 pipe_config->dpll_hw_state.fp1);
12267 }
12268
12269 DRM_DEBUG_KMS("planes on this crtc\n");
12270 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12271 intel_plane = to_intel_plane(plane);
12272 if (intel_plane->pipe != crtc->pipe)
12273 continue;
12274
12275 state = to_intel_plane_state(plane->state);
12276 fb = state->base.fb;
12277 if (!fb) {
12278 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12279 plane->base.id, plane->name, state->scaler_id);
12280 continue;
12281 }
12282
12283 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12284 plane->base.id, plane->name);
12285 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12286 fb->base.id, fb->width, fb->height,
12287 drm_get_format_name(fb->pixel_format));
12288 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12289 state->scaler_id,
12290 state->src.x1 >> 16, state->src.y1 >> 16,
12291 drm_rect_width(&state->src) >> 16,
12292 drm_rect_height(&state->src) >> 16,
12293 state->dst.x1, state->dst.y1,
12294 drm_rect_width(&state->dst),
12295 drm_rect_height(&state->dst));
12296 }
12297 }
12298
12299 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12300 {
12301 struct drm_device *dev = state->dev;
12302 struct drm_connector *connector;
12303 unsigned int used_ports = 0;
12304 unsigned int used_mst_ports = 0;
12305
12306 /*
12307 * Walk the connector list instead of the encoder
12308 * list to detect the problem on ddi platforms
12309 * where there's just one encoder per digital port.
12310 */
12311 drm_for_each_connector(connector, dev) {
12312 struct drm_connector_state *connector_state;
12313 struct intel_encoder *encoder;
12314
12315 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12316 if (!connector_state)
12317 connector_state = connector->state;
12318
12319 if (!connector_state->best_encoder)
12320 continue;
12321
12322 encoder = to_intel_encoder(connector_state->best_encoder);
12323
12324 WARN_ON(!connector_state->crtc);
12325
12326 switch (encoder->type) {
12327 unsigned int port_mask;
12328 case INTEL_OUTPUT_UNKNOWN:
12329 if (WARN_ON(!HAS_DDI(dev)))
12330 break;
12331 case INTEL_OUTPUT_DP:
12332 case INTEL_OUTPUT_HDMI:
12333 case INTEL_OUTPUT_EDP:
12334 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12335
12336 /* the same port mustn't appear more than once */
12337 if (used_ports & port_mask)
12338 return false;
12339
12340 used_ports |= port_mask;
12341 break;
12342 case INTEL_OUTPUT_DP_MST:
12343 used_mst_ports |=
12344 1 << enc_to_mst(&encoder->base)->primary->port;
12345 break;
12346 default:
12347 break;
12348 }
12349 }
12350
12351 /* can't mix MST and SST/HDMI on the same port */
12352 if (used_ports & used_mst_ports)
12353 return false;
12354
12355 return true;
12356 }
12357
12358 static void
12359 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12360 {
12361 struct drm_crtc_state tmp_state;
12362 struct intel_crtc_scaler_state scaler_state;
12363 struct intel_dpll_hw_state dpll_hw_state;
12364 struct intel_shared_dpll *shared_dpll;
12365 uint32_t ddi_pll_sel;
12366 bool force_thru;
12367
12368 /* FIXME: before the switch to atomic started, a new pipe_config was
12369 * kzalloc'd. Code that depends on any field being zero should be
12370 * fixed, so that the crtc_state can be safely duplicated. For now,
12371 * only fields that are know to not cause problems are preserved. */
12372
12373 tmp_state = crtc_state->base;
12374 scaler_state = crtc_state->scaler_state;
12375 shared_dpll = crtc_state->shared_dpll;
12376 dpll_hw_state = crtc_state->dpll_hw_state;
12377 ddi_pll_sel = crtc_state->ddi_pll_sel;
12378 force_thru = crtc_state->pch_pfit.force_thru;
12379
12380 memset(crtc_state, 0, sizeof *crtc_state);
12381
12382 crtc_state->base = tmp_state;
12383 crtc_state->scaler_state = scaler_state;
12384 crtc_state->shared_dpll = shared_dpll;
12385 crtc_state->dpll_hw_state = dpll_hw_state;
12386 crtc_state->ddi_pll_sel = ddi_pll_sel;
12387 crtc_state->pch_pfit.force_thru = force_thru;
12388 }
12389
12390 static int
12391 intel_modeset_pipe_config(struct drm_crtc *crtc,
12392 struct intel_crtc_state *pipe_config)
12393 {
12394 struct drm_atomic_state *state = pipe_config->base.state;
12395 struct intel_encoder *encoder;
12396 struct drm_connector *connector;
12397 struct drm_connector_state *connector_state;
12398 int base_bpp, ret = -EINVAL;
12399 int i;
12400 bool retry = true;
12401
12402 clear_intel_crtc_state(pipe_config);
12403
12404 pipe_config->cpu_transcoder =
12405 (enum transcoder) to_intel_crtc(crtc)->pipe;
12406
12407 /*
12408 * Sanitize sync polarity flags based on requested ones. If neither
12409 * positive or negative polarity is requested, treat this as meaning
12410 * negative polarity.
12411 */
12412 if (!(pipe_config->base.adjusted_mode.flags &
12413 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12414 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12415
12416 if (!(pipe_config->base.adjusted_mode.flags &
12417 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12418 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12419
12420 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12421 pipe_config);
12422 if (base_bpp < 0)
12423 goto fail;
12424
12425 /*
12426 * Determine the real pipe dimensions. Note that stereo modes can
12427 * increase the actual pipe size due to the frame doubling and
12428 * insertion of additional space for blanks between the frame. This
12429 * is stored in the crtc timings. We use the requested mode to do this
12430 * computation to clearly distinguish it from the adjusted mode, which
12431 * can be changed by the connectors in the below retry loop.
12432 */
12433 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12434 &pipe_config->pipe_src_w,
12435 &pipe_config->pipe_src_h);
12436
12437 for_each_connector_in_state(state, connector, connector_state, i) {
12438 if (connector_state->crtc != crtc)
12439 continue;
12440
12441 encoder = to_intel_encoder(connector_state->best_encoder);
12442
12443 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12444 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12445 goto fail;
12446 }
12447
12448 /*
12449 * Determine output_types before calling the .compute_config()
12450 * hooks so that the hooks can use this information safely.
12451 */
12452 pipe_config->output_types |= 1 << encoder->type;
12453 }
12454
12455 encoder_retry:
12456 /* Ensure the port clock defaults are reset when retrying. */
12457 pipe_config->port_clock = 0;
12458 pipe_config->pixel_multiplier = 1;
12459
12460 /* Fill in default crtc timings, allow encoders to overwrite them. */
12461 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12462 CRTC_STEREO_DOUBLE);
12463
12464 /* Pass our mode to the connectors and the CRTC to give them a chance to
12465 * adjust it according to limitations or connector properties, and also
12466 * a chance to reject the mode entirely.
12467 */
12468 for_each_connector_in_state(state, connector, connector_state, i) {
12469 if (connector_state->crtc != crtc)
12470 continue;
12471
12472 encoder = to_intel_encoder(connector_state->best_encoder);
12473
12474 if (!(encoder->compute_config(encoder, pipe_config))) {
12475 DRM_DEBUG_KMS("Encoder config failure\n");
12476 goto fail;
12477 }
12478 }
12479
12480 /* Set default port clock if not overwritten by the encoder. Needs to be
12481 * done afterwards in case the encoder adjusts the mode. */
12482 if (!pipe_config->port_clock)
12483 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12484 * pipe_config->pixel_multiplier;
12485
12486 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12487 if (ret < 0) {
12488 DRM_DEBUG_KMS("CRTC fixup failed\n");
12489 goto fail;
12490 }
12491
12492 if (ret == RETRY) {
12493 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12494 ret = -EINVAL;
12495 goto fail;
12496 }
12497
12498 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12499 retry = false;
12500 goto encoder_retry;
12501 }
12502
12503 /* Dithering seems to not pass-through bits correctly when it should, so
12504 * only enable it on 6bpc panels. */
12505 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12506 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12507 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12508
12509 fail:
12510 return ret;
12511 }
12512
12513 static void
12514 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12515 {
12516 struct drm_crtc *crtc;
12517 struct drm_crtc_state *crtc_state;
12518 int i;
12519
12520 /* Double check state. */
12521 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12522 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12523
12524 /* Update hwmode for vblank functions */
12525 if (crtc->state->active)
12526 crtc->hwmode = crtc->state->adjusted_mode;
12527 else
12528 crtc->hwmode.crtc_clock = 0;
12529
12530 /*
12531 * Update legacy state to satisfy fbc code. This can
12532 * be removed when fbc uses the atomic state.
12533 */
12534 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12535 struct drm_plane_state *plane_state = crtc->primary->state;
12536
12537 crtc->primary->fb = plane_state->fb;
12538 crtc->x = plane_state->src_x >> 16;
12539 crtc->y = plane_state->src_y >> 16;
12540 }
12541 }
12542 }
12543
12544 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12545 {
12546 int diff;
12547
12548 if (clock1 == clock2)
12549 return true;
12550
12551 if (!clock1 || !clock2)
12552 return false;
12553
12554 diff = abs(clock1 - clock2);
12555
12556 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12557 return true;
12558
12559 return false;
12560 }
12561
12562 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12563 list_for_each_entry((intel_crtc), \
12564 &(dev)->mode_config.crtc_list, \
12565 base.head) \
12566 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12567
12568 static bool
12569 intel_compare_m_n(unsigned int m, unsigned int n,
12570 unsigned int m2, unsigned int n2,
12571 bool exact)
12572 {
12573 if (m == m2 && n == n2)
12574 return true;
12575
12576 if (exact || !m || !n || !m2 || !n2)
12577 return false;
12578
12579 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12580
12581 if (n > n2) {
12582 while (n > n2) {
12583 m2 <<= 1;
12584 n2 <<= 1;
12585 }
12586 } else if (n < n2) {
12587 while (n < n2) {
12588 m <<= 1;
12589 n <<= 1;
12590 }
12591 }
12592
12593 if (n != n2)
12594 return false;
12595
12596 return intel_fuzzy_clock_check(m, m2);
12597 }
12598
12599 static bool
12600 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12601 struct intel_link_m_n *m2_n2,
12602 bool adjust)
12603 {
12604 if (m_n->tu == m2_n2->tu &&
12605 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12606 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12607 intel_compare_m_n(m_n->link_m, m_n->link_n,
12608 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12609 if (adjust)
12610 *m2_n2 = *m_n;
12611
12612 return true;
12613 }
12614
12615 return false;
12616 }
12617
12618 static bool
12619 intel_pipe_config_compare(struct drm_device *dev,
12620 struct intel_crtc_state *current_config,
12621 struct intel_crtc_state *pipe_config,
12622 bool adjust)
12623 {
12624 bool ret = true;
12625
12626 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12627 do { \
12628 if (!adjust) \
12629 DRM_ERROR(fmt, ##__VA_ARGS__); \
12630 else \
12631 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12632 } while (0)
12633
12634 #define PIPE_CONF_CHECK_X(name) \
12635 if (current_config->name != pipe_config->name) { \
12636 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12637 "(expected 0x%08x, found 0x%08x)\n", \
12638 current_config->name, \
12639 pipe_config->name); \
12640 ret = false; \
12641 }
12642
12643 #define PIPE_CONF_CHECK_I(name) \
12644 if (current_config->name != pipe_config->name) { \
12645 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12646 "(expected %i, found %i)\n", \
12647 current_config->name, \
12648 pipe_config->name); \
12649 ret = false; \
12650 }
12651
12652 #define PIPE_CONF_CHECK_P(name) \
12653 if (current_config->name != pipe_config->name) { \
12654 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12655 "(expected %p, found %p)\n", \
12656 current_config->name, \
12657 pipe_config->name); \
12658 ret = false; \
12659 }
12660
12661 #define PIPE_CONF_CHECK_M_N(name) \
12662 if (!intel_compare_link_m_n(&current_config->name, \
12663 &pipe_config->name,\
12664 adjust)) { \
12665 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12666 "(expected tu %i gmch %i/%i link %i/%i, " \
12667 "found tu %i, gmch %i/%i link %i/%i)\n", \
12668 current_config->name.tu, \
12669 current_config->name.gmch_m, \
12670 current_config->name.gmch_n, \
12671 current_config->name.link_m, \
12672 current_config->name.link_n, \
12673 pipe_config->name.tu, \
12674 pipe_config->name.gmch_m, \
12675 pipe_config->name.gmch_n, \
12676 pipe_config->name.link_m, \
12677 pipe_config->name.link_n); \
12678 ret = false; \
12679 }
12680
12681 /* This is required for BDW+ where there is only one set of registers for
12682 * switching between high and low RR.
12683 * This macro can be used whenever a comparison has to be made between one
12684 * hw state and multiple sw state variables.
12685 */
12686 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12687 if (!intel_compare_link_m_n(&current_config->name, \
12688 &pipe_config->name, adjust) && \
12689 !intel_compare_link_m_n(&current_config->alt_name, \
12690 &pipe_config->name, adjust)) { \
12691 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12692 "(expected tu %i gmch %i/%i link %i/%i, " \
12693 "or tu %i gmch %i/%i link %i/%i, " \
12694 "found tu %i, gmch %i/%i link %i/%i)\n", \
12695 current_config->name.tu, \
12696 current_config->name.gmch_m, \
12697 current_config->name.gmch_n, \
12698 current_config->name.link_m, \
12699 current_config->name.link_n, \
12700 current_config->alt_name.tu, \
12701 current_config->alt_name.gmch_m, \
12702 current_config->alt_name.gmch_n, \
12703 current_config->alt_name.link_m, \
12704 current_config->alt_name.link_n, \
12705 pipe_config->name.tu, \
12706 pipe_config->name.gmch_m, \
12707 pipe_config->name.gmch_n, \
12708 pipe_config->name.link_m, \
12709 pipe_config->name.link_n); \
12710 ret = false; \
12711 }
12712
12713 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12714 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12715 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12716 "(expected %i, found %i)\n", \
12717 current_config->name & (mask), \
12718 pipe_config->name & (mask)); \
12719 ret = false; \
12720 }
12721
12722 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12723 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12724 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12725 "(expected %i, found %i)\n", \
12726 current_config->name, \
12727 pipe_config->name); \
12728 ret = false; \
12729 }
12730
12731 #define PIPE_CONF_QUIRK(quirk) \
12732 ((current_config->quirks | pipe_config->quirks) & (quirk))
12733
12734 PIPE_CONF_CHECK_I(cpu_transcoder);
12735
12736 PIPE_CONF_CHECK_I(has_pch_encoder);
12737 PIPE_CONF_CHECK_I(fdi_lanes);
12738 PIPE_CONF_CHECK_M_N(fdi_m_n);
12739
12740 PIPE_CONF_CHECK_I(lane_count);
12741 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12742
12743 if (INTEL_INFO(dev)->gen < 8) {
12744 PIPE_CONF_CHECK_M_N(dp_m_n);
12745
12746 if (current_config->has_drrs)
12747 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12748 } else
12749 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12750
12751 PIPE_CONF_CHECK_X(output_types);
12752
12753 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12754 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12755 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12756 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12757 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12758 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12759
12760 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12761 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12762 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12763 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12764 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12765 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12766
12767 PIPE_CONF_CHECK_I(pixel_multiplier);
12768 PIPE_CONF_CHECK_I(has_hdmi_sink);
12769 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12770 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12771 PIPE_CONF_CHECK_I(limited_color_range);
12772 PIPE_CONF_CHECK_I(has_infoframe);
12773
12774 PIPE_CONF_CHECK_I(has_audio);
12775
12776 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12777 DRM_MODE_FLAG_INTERLACE);
12778
12779 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12780 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12781 DRM_MODE_FLAG_PHSYNC);
12782 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12783 DRM_MODE_FLAG_NHSYNC);
12784 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12785 DRM_MODE_FLAG_PVSYNC);
12786 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12787 DRM_MODE_FLAG_NVSYNC);
12788 }
12789
12790 PIPE_CONF_CHECK_X(gmch_pfit.control);
12791 /* pfit ratios are autocomputed by the hw on gen4+ */
12792 if (INTEL_INFO(dev)->gen < 4)
12793 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12794 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12795
12796 if (!adjust) {
12797 PIPE_CONF_CHECK_I(pipe_src_w);
12798 PIPE_CONF_CHECK_I(pipe_src_h);
12799
12800 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12801 if (current_config->pch_pfit.enabled) {
12802 PIPE_CONF_CHECK_X(pch_pfit.pos);
12803 PIPE_CONF_CHECK_X(pch_pfit.size);
12804 }
12805
12806 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12807 }
12808
12809 /* BDW+ don't expose a synchronous way to read the state */
12810 if (IS_HASWELL(dev))
12811 PIPE_CONF_CHECK_I(ips_enabled);
12812
12813 PIPE_CONF_CHECK_I(double_wide);
12814
12815 PIPE_CONF_CHECK_X(ddi_pll_sel);
12816
12817 PIPE_CONF_CHECK_P(shared_dpll);
12818 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12819 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12820 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12821 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12822 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12823 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12824 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12825 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12826 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12827
12828 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12829 PIPE_CONF_CHECK_X(dsi_pll.div);
12830
12831 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12832 PIPE_CONF_CHECK_I(pipe_bpp);
12833
12834 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12835 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12836
12837 #undef PIPE_CONF_CHECK_X
12838 #undef PIPE_CONF_CHECK_I
12839 #undef PIPE_CONF_CHECK_P
12840 #undef PIPE_CONF_CHECK_FLAGS
12841 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12842 #undef PIPE_CONF_QUIRK
12843 #undef INTEL_ERR_OR_DBG_KMS
12844
12845 return ret;
12846 }
12847
12848 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12849 const struct intel_crtc_state *pipe_config)
12850 {
12851 if (pipe_config->has_pch_encoder) {
12852 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12853 &pipe_config->fdi_m_n);
12854 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12855
12856 /*
12857 * FDI already provided one idea for the dotclock.
12858 * Yell if the encoder disagrees.
12859 */
12860 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12861 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12862 fdi_dotclock, dotclock);
12863 }
12864 }
12865
12866 static void verify_wm_state(struct drm_crtc *crtc,
12867 struct drm_crtc_state *new_state)
12868 {
12869 struct drm_device *dev = crtc->dev;
12870 struct drm_i915_private *dev_priv = to_i915(dev);
12871 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12872 struct skl_ddb_entry *hw_entry, *sw_entry;
12873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12874 const enum pipe pipe = intel_crtc->pipe;
12875 int plane;
12876
12877 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12878 return;
12879
12880 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12881 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12882
12883 /* planes */
12884 for_each_plane(dev_priv, pipe, plane) {
12885 hw_entry = &hw_ddb.plane[pipe][plane];
12886 sw_entry = &sw_ddb->plane[pipe][plane];
12887
12888 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12889 continue;
12890
12891 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12892 "(expected (%u,%u), found (%u,%u))\n",
12893 pipe_name(pipe), plane + 1,
12894 sw_entry->start, sw_entry->end,
12895 hw_entry->start, hw_entry->end);
12896 }
12897
12898 /* cursor */
12899 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12900 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12901
12902 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12903 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12904 "(expected (%u,%u), found (%u,%u))\n",
12905 pipe_name(pipe),
12906 sw_entry->start, sw_entry->end,
12907 hw_entry->start, hw_entry->end);
12908 }
12909 }
12910
12911 static void
12912 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12913 {
12914 struct drm_connector *connector;
12915
12916 drm_for_each_connector(connector, dev) {
12917 struct drm_encoder *encoder = connector->encoder;
12918 struct drm_connector_state *state = connector->state;
12919
12920 if (state->crtc != crtc)
12921 continue;
12922
12923 intel_connector_verify_state(to_intel_connector(connector));
12924
12925 I915_STATE_WARN(state->best_encoder != encoder,
12926 "connector's atomic encoder doesn't match legacy encoder\n");
12927 }
12928 }
12929
12930 static void
12931 verify_encoder_state(struct drm_device *dev)
12932 {
12933 struct intel_encoder *encoder;
12934 struct intel_connector *connector;
12935
12936 for_each_intel_encoder(dev, encoder) {
12937 bool enabled = false;
12938 enum pipe pipe;
12939
12940 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12941 encoder->base.base.id,
12942 encoder->base.name);
12943
12944 for_each_intel_connector(dev, connector) {
12945 if (connector->base.state->best_encoder != &encoder->base)
12946 continue;
12947 enabled = true;
12948
12949 I915_STATE_WARN(connector->base.state->crtc !=
12950 encoder->base.crtc,
12951 "connector's crtc doesn't match encoder crtc\n");
12952 }
12953
12954 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12955 "encoder's enabled state mismatch "
12956 "(expected %i, found %i)\n",
12957 !!encoder->base.crtc, enabled);
12958
12959 if (!encoder->base.crtc) {
12960 bool active;
12961
12962 active = encoder->get_hw_state(encoder, &pipe);
12963 I915_STATE_WARN(active,
12964 "encoder detached but still enabled on pipe %c.\n",
12965 pipe_name(pipe));
12966 }
12967 }
12968 }
12969
12970 static void
12971 verify_crtc_state(struct drm_crtc *crtc,
12972 struct drm_crtc_state *old_crtc_state,
12973 struct drm_crtc_state *new_crtc_state)
12974 {
12975 struct drm_device *dev = crtc->dev;
12976 struct drm_i915_private *dev_priv = to_i915(dev);
12977 struct intel_encoder *encoder;
12978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12979 struct intel_crtc_state *pipe_config, *sw_config;
12980 struct drm_atomic_state *old_state;
12981 bool active;
12982
12983 old_state = old_crtc_state->state;
12984 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12985 pipe_config = to_intel_crtc_state(old_crtc_state);
12986 memset(pipe_config, 0, sizeof(*pipe_config));
12987 pipe_config->base.crtc = crtc;
12988 pipe_config->base.state = old_state;
12989
12990 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12991
12992 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12993
12994 /* hw state is inconsistent with the pipe quirk */
12995 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12996 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12997 active = new_crtc_state->active;
12998
12999 I915_STATE_WARN(new_crtc_state->active != active,
13000 "crtc active state doesn't match with hw state "
13001 "(expected %i, found %i)\n", new_crtc_state->active, active);
13002
13003 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13004 "transitional active state does not match atomic hw state "
13005 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13006
13007 for_each_encoder_on_crtc(dev, crtc, encoder) {
13008 enum pipe pipe;
13009
13010 active = encoder->get_hw_state(encoder, &pipe);
13011 I915_STATE_WARN(active != new_crtc_state->active,
13012 "[ENCODER:%i] active %i with crtc active %i\n",
13013 encoder->base.base.id, active, new_crtc_state->active);
13014
13015 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13016 "Encoder connected to wrong pipe %c\n",
13017 pipe_name(pipe));
13018
13019 if (active) {
13020 pipe_config->output_types |= 1 << encoder->type;
13021 encoder->get_config(encoder, pipe_config);
13022 }
13023 }
13024
13025 if (!new_crtc_state->active)
13026 return;
13027
13028 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13029
13030 sw_config = to_intel_crtc_state(crtc->state);
13031 if (!intel_pipe_config_compare(dev, sw_config,
13032 pipe_config, false)) {
13033 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13034 intel_dump_pipe_config(intel_crtc, pipe_config,
13035 "[hw state]");
13036 intel_dump_pipe_config(intel_crtc, sw_config,
13037 "[sw state]");
13038 }
13039 }
13040
13041 static void
13042 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13043 struct intel_shared_dpll *pll,
13044 struct drm_crtc *crtc,
13045 struct drm_crtc_state *new_state)
13046 {
13047 struct intel_dpll_hw_state dpll_hw_state;
13048 unsigned crtc_mask;
13049 bool active;
13050
13051 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13052
13053 DRM_DEBUG_KMS("%s\n", pll->name);
13054
13055 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13056
13057 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13058 I915_STATE_WARN(!pll->on && pll->active_mask,
13059 "pll in active use but not on in sw tracking\n");
13060 I915_STATE_WARN(pll->on && !pll->active_mask,
13061 "pll is on but not used by any active crtc\n");
13062 I915_STATE_WARN(pll->on != active,
13063 "pll on state mismatch (expected %i, found %i)\n",
13064 pll->on, active);
13065 }
13066
13067 if (!crtc) {
13068 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13069 "more active pll users than references: %x vs %x\n",
13070 pll->active_mask, pll->config.crtc_mask);
13071
13072 return;
13073 }
13074
13075 crtc_mask = 1 << drm_crtc_index(crtc);
13076
13077 if (new_state->active)
13078 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13079 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13080 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13081 else
13082 I915_STATE_WARN(pll->active_mask & crtc_mask,
13083 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13084 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13085
13086 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13087 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13088 crtc_mask, pll->config.crtc_mask);
13089
13090 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13091 &dpll_hw_state,
13092 sizeof(dpll_hw_state)),
13093 "pll hw state mismatch\n");
13094 }
13095
13096 static void
13097 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13098 struct drm_crtc_state *old_crtc_state,
13099 struct drm_crtc_state *new_crtc_state)
13100 {
13101 struct drm_i915_private *dev_priv = to_i915(dev);
13102 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13103 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13104
13105 if (new_state->shared_dpll)
13106 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13107
13108 if (old_state->shared_dpll &&
13109 old_state->shared_dpll != new_state->shared_dpll) {
13110 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13111 struct intel_shared_dpll *pll = old_state->shared_dpll;
13112
13113 I915_STATE_WARN(pll->active_mask & crtc_mask,
13114 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13115 pipe_name(drm_crtc_index(crtc)));
13116 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13117 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13118 pipe_name(drm_crtc_index(crtc)));
13119 }
13120 }
13121
13122 static void
13123 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13124 struct drm_crtc_state *old_state,
13125 struct drm_crtc_state *new_state)
13126 {
13127 if (!needs_modeset(new_state) &&
13128 !to_intel_crtc_state(new_state)->update_pipe)
13129 return;
13130
13131 verify_wm_state(crtc, new_state);
13132 verify_connector_state(crtc->dev, crtc);
13133 verify_crtc_state(crtc, old_state, new_state);
13134 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13135 }
13136
13137 static void
13138 verify_disabled_dpll_state(struct drm_device *dev)
13139 {
13140 struct drm_i915_private *dev_priv = to_i915(dev);
13141 int i;
13142
13143 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13144 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13145 }
13146
13147 static void
13148 intel_modeset_verify_disabled(struct drm_device *dev)
13149 {
13150 verify_encoder_state(dev);
13151 verify_connector_state(dev, NULL);
13152 verify_disabled_dpll_state(dev);
13153 }
13154
13155 static void update_scanline_offset(struct intel_crtc *crtc)
13156 {
13157 struct drm_device *dev = crtc->base.dev;
13158
13159 /*
13160 * The scanline counter increments at the leading edge of hsync.
13161 *
13162 * On most platforms it starts counting from vtotal-1 on the
13163 * first active line. That means the scanline counter value is
13164 * always one less than what we would expect. Ie. just after
13165 * start of vblank, which also occurs at start of hsync (on the
13166 * last active line), the scanline counter will read vblank_start-1.
13167 *
13168 * On gen2 the scanline counter starts counting from 1 instead
13169 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13170 * to keep the value positive), instead of adding one.
13171 *
13172 * On HSW+ the behaviour of the scanline counter depends on the output
13173 * type. For DP ports it behaves like most other platforms, but on HDMI
13174 * there's an extra 1 line difference. So we need to add two instead of
13175 * one to the value.
13176 */
13177 if (IS_GEN2(dev)) {
13178 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13179 int vtotal;
13180
13181 vtotal = adjusted_mode->crtc_vtotal;
13182 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13183 vtotal /= 2;
13184
13185 crtc->scanline_offset = vtotal - 1;
13186 } else if (HAS_DDI(dev) &&
13187 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13188 crtc->scanline_offset = 2;
13189 } else
13190 crtc->scanline_offset = 1;
13191 }
13192
13193 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13194 {
13195 struct drm_device *dev = state->dev;
13196 struct drm_i915_private *dev_priv = to_i915(dev);
13197 struct intel_shared_dpll_config *shared_dpll = NULL;
13198 struct drm_crtc *crtc;
13199 struct drm_crtc_state *crtc_state;
13200 int i;
13201
13202 if (!dev_priv->display.crtc_compute_clock)
13203 return;
13204
13205 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13207 struct intel_shared_dpll *old_dpll =
13208 to_intel_crtc_state(crtc->state)->shared_dpll;
13209
13210 if (!needs_modeset(crtc_state))
13211 continue;
13212
13213 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13214
13215 if (!old_dpll)
13216 continue;
13217
13218 if (!shared_dpll)
13219 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13220
13221 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13222 }
13223 }
13224
13225 /*
13226 * This implements the workaround described in the "notes" section of the mode
13227 * set sequence documentation. When going from no pipes or single pipe to
13228 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13229 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13230 */
13231 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13232 {
13233 struct drm_crtc_state *crtc_state;
13234 struct intel_crtc *intel_crtc;
13235 struct drm_crtc *crtc;
13236 struct intel_crtc_state *first_crtc_state = NULL;
13237 struct intel_crtc_state *other_crtc_state = NULL;
13238 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13239 int i;
13240
13241 /* look at all crtc's that are going to be enabled in during modeset */
13242 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13243 intel_crtc = to_intel_crtc(crtc);
13244
13245 if (!crtc_state->active || !needs_modeset(crtc_state))
13246 continue;
13247
13248 if (first_crtc_state) {
13249 other_crtc_state = to_intel_crtc_state(crtc_state);
13250 break;
13251 } else {
13252 first_crtc_state = to_intel_crtc_state(crtc_state);
13253 first_pipe = intel_crtc->pipe;
13254 }
13255 }
13256
13257 /* No workaround needed? */
13258 if (!first_crtc_state)
13259 return 0;
13260
13261 /* w/a possibly needed, check how many crtc's are already enabled. */
13262 for_each_intel_crtc(state->dev, intel_crtc) {
13263 struct intel_crtc_state *pipe_config;
13264
13265 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13266 if (IS_ERR(pipe_config))
13267 return PTR_ERR(pipe_config);
13268
13269 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13270
13271 if (!pipe_config->base.active ||
13272 needs_modeset(&pipe_config->base))
13273 continue;
13274
13275 /* 2 or more enabled crtcs means no need for w/a */
13276 if (enabled_pipe != INVALID_PIPE)
13277 return 0;
13278
13279 enabled_pipe = intel_crtc->pipe;
13280 }
13281
13282 if (enabled_pipe != INVALID_PIPE)
13283 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13284 else if (other_crtc_state)
13285 other_crtc_state->hsw_workaround_pipe = first_pipe;
13286
13287 return 0;
13288 }
13289
13290 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13291 {
13292 struct drm_crtc *crtc;
13293 struct drm_crtc_state *crtc_state;
13294 int ret = 0;
13295
13296 /* add all active pipes to the state */
13297 for_each_crtc(state->dev, crtc) {
13298 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13299 if (IS_ERR(crtc_state))
13300 return PTR_ERR(crtc_state);
13301
13302 if (!crtc_state->active || needs_modeset(crtc_state))
13303 continue;
13304
13305 crtc_state->mode_changed = true;
13306
13307 ret = drm_atomic_add_affected_connectors(state, crtc);
13308 if (ret)
13309 break;
13310
13311 ret = drm_atomic_add_affected_planes(state, crtc);
13312 if (ret)
13313 break;
13314 }
13315
13316 return ret;
13317 }
13318
13319 static int intel_modeset_checks(struct drm_atomic_state *state)
13320 {
13321 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13322 struct drm_i915_private *dev_priv = to_i915(state->dev);
13323 struct drm_crtc *crtc;
13324 struct drm_crtc_state *crtc_state;
13325 int ret = 0, i;
13326
13327 if (!check_digital_port_conflicts(state)) {
13328 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13329 return -EINVAL;
13330 }
13331
13332 intel_state->modeset = true;
13333 intel_state->active_crtcs = dev_priv->active_crtcs;
13334
13335 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13336 if (crtc_state->active)
13337 intel_state->active_crtcs |= 1 << i;
13338 else
13339 intel_state->active_crtcs &= ~(1 << i);
13340
13341 if (crtc_state->active != crtc->state->active)
13342 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13343 }
13344
13345 /*
13346 * See if the config requires any additional preparation, e.g.
13347 * to adjust global state with pipes off. We need to do this
13348 * here so we can get the modeset_pipe updated config for the new
13349 * mode set on this crtc. For other crtcs we need to use the
13350 * adjusted_mode bits in the crtc directly.
13351 */
13352 if (dev_priv->display.modeset_calc_cdclk) {
13353 if (!intel_state->cdclk_pll_vco)
13354 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13355 if (!intel_state->cdclk_pll_vco)
13356 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13357
13358 ret = dev_priv->display.modeset_calc_cdclk(state);
13359 if (ret < 0)
13360 return ret;
13361
13362 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13363 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13364 ret = intel_modeset_all_pipes(state);
13365
13366 if (ret < 0)
13367 return ret;
13368
13369 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13370 intel_state->cdclk, intel_state->dev_cdclk);
13371 } else
13372 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13373
13374 intel_modeset_clear_plls(state);
13375
13376 if (IS_HASWELL(dev_priv))
13377 return haswell_mode_set_planes_workaround(state);
13378
13379 return 0;
13380 }
13381
13382 /*
13383 * Handle calculation of various watermark data at the end of the atomic check
13384 * phase. The code here should be run after the per-crtc and per-plane 'check'
13385 * handlers to ensure that all derived state has been updated.
13386 */
13387 static int calc_watermark_data(struct drm_atomic_state *state)
13388 {
13389 struct drm_device *dev = state->dev;
13390 struct drm_i915_private *dev_priv = to_i915(dev);
13391
13392 /* Is there platform-specific watermark information to calculate? */
13393 if (dev_priv->display.compute_global_watermarks)
13394 return dev_priv->display.compute_global_watermarks(state);
13395
13396 return 0;
13397 }
13398
13399 /**
13400 * intel_atomic_check - validate state object
13401 * @dev: drm device
13402 * @state: state to validate
13403 */
13404 static int intel_atomic_check(struct drm_device *dev,
13405 struct drm_atomic_state *state)
13406 {
13407 struct drm_i915_private *dev_priv = to_i915(dev);
13408 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13409 struct drm_crtc *crtc;
13410 struct drm_crtc_state *crtc_state;
13411 int ret, i;
13412 bool any_ms = false;
13413
13414 ret = drm_atomic_helper_check_modeset(dev, state);
13415 if (ret)
13416 return ret;
13417
13418 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13419 struct intel_crtc_state *pipe_config =
13420 to_intel_crtc_state(crtc_state);
13421
13422 /* Catch I915_MODE_FLAG_INHERITED */
13423 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13424 crtc_state->mode_changed = true;
13425
13426 if (!needs_modeset(crtc_state))
13427 continue;
13428
13429 if (!crtc_state->enable) {
13430 any_ms = true;
13431 continue;
13432 }
13433
13434 /* FIXME: For only active_changed we shouldn't need to do any
13435 * state recomputation at all. */
13436
13437 ret = drm_atomic_add_affected_connectors(state, crtc);
13438 if (ret)
13439 return ret;
13440
13441 ret = intel_modeset_pipe_config(crtc, pipe_config);
13442 if (ret) {
13443 intel_dump_pipe_config(to_intel_crtc(crtc),
13444 pipe_config, "[failed]");
13445 return ret;
13446 }
13447
13448 if (i915.fastboot &&
13449 intel_pipe_config_compare(dev,
13450 to_intel_crtc_state(crtc->state),
13451 pipe_config, true)) {
13452 crtc_state->mode_changed = false;
13453 to_intel_crtc_state(crtc_state)->update_pipe = true;
13454 }
13455
13456 if (needs_modeset(crtc_state))
13457 any_ms = true;
13458
13459 ret = drm_atomic_add_affected_planes(state, crtc);
13460 if (ret)
13461 return ret;
13462
13463 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13464 needs_modeset(crtc_state) ?
13465 "[modeset]" : "[fastset]");
13466 }
13467
13468 if (any_ms) {
13469 ret = intel_modeset_checks(state);
13470
13471 if (ret)
13472 return ret;
13473 } else
13474 intel_state->cdclk = dev_priv->cdclk_freq;
13475
13476 ret = drm_atomic_helper_check_planes(dev, state);
13477 if (ret)
13478 return ret;
13479
13480 intel_fbc_choose_crtc(dev_priv, state);
13481 return calc_watermark_data(state);
13482 }
13483
13484 static int intel_atomic_prepare_commit(struct drm_device *dev,
13485 struct drm_atomic_state *state,
13486 bool nonblock)
13487 {
13488 struct drm_i915_private *dev_priv = to_i915(dev);
13489 struct drm_plane_state *plane_state;
13490 struct drm_crtc_state *crtc_state;
13491 struct drm_plane *plane;
13492 struct drm_crtc *crtc;
13493 int i, ret;
13494
13495 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13496 if (state->legacy_cursor_update)
13497 continue;
13498
13499 ret = intel_crtc_wait_for_pending_flips(crtc);
13500 if (ret)
13501 return ret;
13502
13503 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13504 flush_workqueue(dev_priv->wq);
13505 }
13506
13507 ret = mutex_lock_interruptible(&dev->struct_mutex);
13508 if (ret)
13509 return ret;
13510
13511 ret = drm_atomic_helper_prepare_planes(dev, state);
13512 mutex_unlock(&dev->struct_mutex);
13513
13514 if (!ret && !nonblock) {
13515 for_each_plane_in_state(state, plane, plane_state, i) {
13516 struct intel_plane_state *intel_plane_state =
13517 to_intel_plane_state(plane_state);
13518
13519 if (!intel_plane_state->wait_req)
13520 continue;
13521
13522 ret = i915_wait_request(intel_plane_state->wait_req,
13523 true, NULL, NULL);
13524 if (ret) {
13525 /* Any hang should be swallowed by the wait */
13526 WARN_ON(ret == -EIO);
13527 mutex_lock(&dev->struct_mutex);
13528 drm_atomic_helper_cleanup_planes(dev, state);
13529 mutex_unlock(&dev->struct_mutex);
13530 break;
13531 }
13532 }
13533 }
13534
13535 return ret;
13536 }
13537
13538 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13539 {
13540 struct drm_device *dev = crtc->base.dev;
13541
13542 if (!dev->max_vblank_count)
13543 return drm_accurate_vblank_count(&crtc->base);
13544
13545 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13546 }
13547
13548 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13549 struct drm_i915_private *dev_priv,
13550 unsigned crtc_mask)
13551 {
13552 unsigned last_vblank_count[I915_MAX_PIPES];
13553 enum pipe pipe;
13554 int ret;
13555
13556 if (!crtc_mask)
13557 return;
13558
13559 for_each_pipe(dev_priv, pipe) {
13560 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13561
13562 if (!((1 << pipe) & crtc_mask))
13563 continue;
13564
13565 ret = drm_crtc_vblank_get(crtc);
13566 if (WARN_ON(ret != 0)) {
13567 crtc_mask &= ~(1 << pipe);
13568 continue;
13569 }
13570
13571 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13572 }
13573
13574 for_each_pipe(dev_priv, pipe) {
13575 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13576 long lret;
13577
13578 if (!((1 << pipe) & crtc_mask))
13579 continue;
13580
13581 lret = wait_event_timeout(dev->vblank[pipe].queue,
13582 last_vblank_count[pipe] !=
13583 drm_crtc_vblank_count(crtc),
13584 msecs_to_jiffies(50));
13585
13586 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13587
13588 drm_crtc_vblank_put(crtc);
13589 }
13590 }
13591
13592 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13593 {
13594 /* fb updated, need to unpin old fb */
13595 if (crtc_state->fb_changed)
13596 return true;
13597
13598 /* wm changes, need vblank before final wm's */
13599 if (crtc_state->update_wm_post)
13600 return true;
13601
13602 /*
13603 * cxsr is re-enabled after vblank.
13604 * This is already handled by crtc_state->update_wm_post,
13605 * but added for clarity.
13606 */
13607 if (crtc_state->disable_cxsr)
13608 return true;
13609
13610 return false;
13611 }
13612
13613 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13614 {
13615 struct drm_device *dev = state->dev;
13616 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13617 struct drm_i915_private *dev_priv = to_i915(dev);
13618 struct drm_crtc_state *old_crtc_state;
13619 struct drm_crtc *crtc;
13620 struct intel_crtc_state *intel_cstate;
13621 struct drm_plane *plane;
13622 struct drm_plane_state *plane_state;
13623 bool hw_check = intel_state->modeset;
13624 unsigned long put_domains[I915_MAX_PIPES] = {};
13625 unsigned crtc_vblank_mask = 0;
13626 int i, ret;
13627
13628 for_each_plane_in_state(state, plane, plane_state, i) {
13629 struct intel_plane_state *intel_plane_state =
13630 to_intel_plane_state(plane_state);
13631
13632 if (!intel_plane_state->wait_req)
13633 continue;
13634
13635 ret = i915_wait_request(intel_plane_state->wait_req,
13636 true, NULL, NULL);
13637 /* EIO should be eaten, and we can't get interrupted in the
13638 * worker, and blocking commits have waited already. */
13639 WARN_ON(ret);
13640 }
13641
13642 drm_atomic_helper_wait_for_dependencies(state);
13643
13644 if (intel_state->modeset) {
13645 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13646 sizeof(intel_state->min_pixclk));
13647 dev_priv->active_crtcs = intel_state->active_crtcs;
13648 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13649
13650 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13651 }
13652
13653 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13655
13656 if (needs_modeset(crtc->state) ||
13657 to_intel_crtc_state(crtc->state)->update_pipe) {
13658 hw_check = true;
13659
13660 put_domains[to_intel_crtc(crtc)->pipe] =
13661 modeset_get_crtc_power_domains(crtc,
13662 to_intel_crtc_state(crtc->state));
13663 }
13664
13665 if (!needs_modeset(crtc->state))
13666 continue;
13667
13668 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13669
13670 if (old_crtc_state->active) {
13671 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13672 dev_priv->display.crtc_disable(crtc);
13673 intel_crtc->active = false;
13674 intel_fbc_disable(intel_crtc);
13675 intel_disable_shared_dpll(intel_crtc);
13676
13677 /*
13678 * Underruns don't always raise
13679 * interrupts, so check manually.
13680 */
13681 intel_check_cpu_fifo_underruns(dev_priv);
13682 intel_check_pch_fifo_underruns(dev_priv);
13683
13684 if (!crtc->state->active)
13685 intel_update_watermarks(crtc);
13686 }
13687 }
13688
13689 /* Only after disabling all output pipelines that will be changed can we
13690 * update the the output configuration. */
13691 intel_modeset_update_crtc_state(state);
13692
13693 if (intel_state->modeset) {
13694 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13695
13696 if (dev_priv->display.modeset_commit_cdclk &&
13697 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13698 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13699 dev_priv->display.modeset_commit_cdclk(state);
13700
13701 intel_modeset_verify_disabled(dev);
13702 }
13703
13704 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13705 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13707 bool modeset = needs_modeset(crtc->state);
13708 struct intel_crtc_state *pipe_config =
13709 to_intel_crtc_state(crtc->state);
13710
13711 if (modeset && crtc->state->active) {
13712 update_scanline_offset(to_intel_crtc(crtc));
13713 dev_priv->display.crtc_enable(crtc);
13714 }
13715
13716 /* Complete events for now disable pipes here. */
13717 if (modeset && !crtc->state->active && crtc->state->event) {
13718 spin_lock_irq(&dev->event_lock);
13719 drm_crtc_send_vblank_event(crtc, crtc->state->event);
13720 spin_unlock_irq(&dev->event_lock);
13721
13722 crtc->state->event = NULL;
13723 }
13724
13725 if (!modeset)
13726 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13727
13728 if (crtc->state->active &&
13729 drm_atomic_get_existing_plane_state(state, crtc->primary))
13730 intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
13731
13732 if (crtc->state->active)
13733 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13734
13735 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13736 crtc_vblank_mask |= 1 << i;
13737 }
13738
13739 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13740 * already, but still need the state for the delayed optimization. To
13741 * fix this:
13742 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13743 * - schedule that vblank worker _before_ calling hw_done
13744 * - at the start of commit_tail, cancel it _synchrously
13745 * - switch over to the vblank wait helper in the core after that since
13746 * we don't need out special handling any more.
13747 */
13748 if (!state->legacy_cursor_update)
13749 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13750
13751 /*
13752 * Now that the vblank has passed, we can go ahead and program the
13753 * optimal watermarks on platforms that need two-step watermark
13754 * programming.
13755 *
13756 * TODO: Move this (and other cleanup) to an async worker eventually.
13757 */
13758 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13759 intel_cstate = to_intel_crtc_state(crtc->state);
13760
13761 if (dev_priv->display.optimize_watermarks)
13762 dev_priv->display.optimize_watermarks(intel_cstate);
13763 }
13764
13765 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13766 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13767
13768 if (put_domains[i])
13769 modeset_put_power_domains(dev_priv, put_domains[i]);
13770
13771 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13772 }
13773
13774 drm_atomic_helper_commit_hw_done(state);
13775
13776 if (intel_state->modeset)
13777 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13778
13779 mutex_lock(&dev->struct_mutex);
13780 drm_atomic_helper_cleanup_planes(dev, state);
13781 mutex_unlock(&dev->struct_mutex);
13782
13783 drm_atomic_helper_commit_cleanup_done(state);
13784
13785 drm_atomic_state_free(state);
13786
13787 /* As one of the primary mmio accessors, KMS has a high likelihood
13788 * of triggering bugs in unclaimed access. After we finish
13789 * modesetting, see if an error has been flagged, and if so
13790 * enable debugging for the next modeset - and hope we catch
13791 * the culprit.
13792 *
13793 * XXX note that we assume display power is on at this point.
13794 * This might hold true now but we need to add pm helper to check
13795 * unclaimed only when the hardware is on, as atomic commits
13796 * can happen also when the device is completely off.
13797 */
13798 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13799 }
13800
13801 static void intel_atomic_commit_work(struct work_struct *work)
13802 {
13803 struct drm_atomic_state *state = container_of(work,
13804 struct drm_atomic_state,
13805 commit_work);
13806 intel_atomic_commit_tail(state);
13807 }
13808
13809 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13810 {
13811 struct drm_plane_state *old_plane_state;
13812 struct drm_plane *plane;
13813 struct drm_i915_gem_object *obj, *old_obj;
13814 struct intel_plane *intel_plane;
13815 int i;
13816
13817 mutex_lock(&state->dev->struct_mutex);
13818 for_each_plane_in_state(state, plane, old_plane_state, i) {
13819 obj = intel_fb_obj(plane->state->fb);
13820 old_obj = intel_fb_obj(old_plane_state->fb);
13821 intel_plane = to_intel_plane(plane);
13822
13823 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13824 }
13825 mutex_unlock(&state->dev->struct_mutex);
13826 }
13827
13828 /**
13829 * intel_atomic_commit - commit validated state object
13830 * @dev: DRM device
13831 * @state: the top-level driver state object
13832 * @nonblock: nonblocking commit
13833 *
13834 * This function commits a top-level state object that has been validated
13835 * with drm_atomic_helper_check().
13836 *
13837 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13838 * nonblocking commits are only safe for pure plane updates. Everything else
13839 * should work though.
13840 *
13841 * RETURNS
13842 * Zero for success or -errno.
13843 */
13844 static int intel_atomic_commit(struct drm_device *dev,
13845 struct drm_atomic_state *state,
13846 bool nonblock)
13847 {
13848 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13849 struct drm_i915_private *dev_priv = to_i915(dev);
13850 int ret = 0;
13851
13852 if (intel_state->modeset && nonblock) {
13853 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13854 return -EINVAL;
13855 }
13856
13857 ret = drm_atomic_helper_setup_commit(state, nonblock);
13858 if (ret)
13859 return ret;
13860
13861 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13862
13863 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13864 if (ret) {
13865 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13866 return ret;
13867 }
13868
13869 drm_atomic_helper_swap_state(state, true);
13870 dev_priv->wm.distrust_bios_wm = false;
13871 dev_priv->wm.skl_results = intel_state->wm_results;
13872 intel_shared_dpll_commit(state);
13873 intel_atomic_track_fbs(state);
13874
13875 if (nonblock)
13876 queue_work(system_unbound_wq, &state->commit_work);
13877 else
13878 intel_atomic_commit_tail(state);
13879
13880 return 0;
13881 }
13882
13883 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13884 {
13885 struct drm_device *dev = crtc->dev;
13886 struct drm_atomic_state *state;
13887 struct drm_crtc_state *crtc_state;
13888 int ret;
13889
13890 state = drm_atomic_state_alloc(dev);
13891 if (!state) {
13892 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13893 crtc->base.id, crtc->name);
13894 return;
13895 }
13896
13897 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13898
13899 retry:
13900 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13901 ret = PTR_ERR_OR_ZERO(crtc_state);
13902 if (!ret) {
13903 if (!crtc_state->active)
13904 goto out;
13905
13906 crtc_state->mode_changed = true;
13907 ret = drm_atomic_commit(state);
13908 }
13909
13910 if (ret == -EDEADLK) {
13911 drm_atomic_state_clear(state);
13912 drm_modeset_backoff(state->acquire_ctx);
13913 goto retry;
13914 }
13915
13916 if (ret)
13917 out:
13918 drm_atomic_state_free(state);
13919 }
13920
13921 #undef for_each_intel_crtc_masked
13922
13923 /*
13924 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13925 * drm_atomic_helper_legacy_gamma_set() directly.
13926 */
13927 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13928 u16 *red, u16 *green, u16 *blue,
13929 uint32_t size)
13930 {
13931 struct drm_device *dev = crtc->dev;
13932 struct drm_mode_config *config = &dev->mode_config;
13933 struct drm_crtc_state *state;
13934 int ret;
13935
13936 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13937 if (ret)
13938 return ret;
13939
13940 /*
13941 * Make sure we update the legacy properties so this works when
13942 * atomic is not enabled.
13943 */
13944
13945 state = crtc->state;
13946
13947 drm_object_property_set_value(&crtc->base,
13948 config->degamma_lut_property,
13949 (state->degamma_lut) ?
13950 state->degamma_lut->base.id : 0);
13951
13952 drm_object_property_set_value(&crtc->base,
13953 config->ctm_property,
13954 (state->ctm) ?
13955 state->ctm->base.id : 0);
13956
13957 drm_object_property_set_value(&crtc->base,
13958 config->gamma_lut_property,
13959 (state->gamma_lut) ?
13960 state->gamma_lut->base.id : 0);
13961
13962 return 0;
13963 }
13964
13965 static const struct drm_crtc_funcs intel_crtc_funcs = {
13966 .gamma_set = intel_atomic_legacy_gamma_set,
13967 .set_config = drm_atomic_helper_set_config,
13968 .set_property = drm_atomic_helper_crtc_set_property,
13969 .destroy = intel_crtc_destroy,
13970 .page_flip = intel_crtc_page_flip,
13971 .atomic_duplicate_state = intel_crtc_duplicate_state,
13972 .atomic_destroy_state = intel_crtc_destroy_state,
13973 };
13974
13975 /**
13976 * intel_prepare_plane_fb - Prepare fb for usage on plane
13977 * @plane: drm plane to prepare for
13978 * @fb: framebuffer to prepare for presentation
13979 *
13980 * Prepares a framebuffer for usage on a display plane. Generally this
13981 * involves pinning the underlying object and updating the frontbuffer tracking
13982 * bits. Some older platforms need special physical address handling for
13983 * cursor planes.
13984 *
13985 * Must be called with struct_mutex held.
13986 *
13987 * Returns 0 on success, negative error code on failure.
13988 */
13989 int
13990 intel_prepare_plane_fb(struct drm_plane *plane,
13991 const struct drm_plane_state *new_state)
13992 {
13993 struct drm_device *dev = plane->dev;
13994 struct drm_framebuffer *fb = new_state->fb;
13995 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13996 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13997 struct reservation_object *resv;
13998 int ret = 0;
13999
14000 if (!obj && !old_obj)
14001 return 0;
14002
14003 if (old_obj) {
14004 struct drm_crtc_state *crtc_state =
14005 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14006
14007 /* Big Hammer, we also need to ensure that any pending
14008 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14009 * current scanout is retired before unpinning the old
14010 * framebuffer. Note that we rely on userspace rendering
14011 * into the buffer attached to the pipe they are waiting
14012 * on. If not, userspace generates a GPU hang with IPEHR
14013 * point to the MI_WAIT_FOR_EVENT.
14014 *
14015 * This should only fail upon a hung GPU, in which case we
14016 * can safely continue.
14017 */
14018 if (needs_modeset(crtc_state))
14019 ret = i915_gem_object_wait_rendering(old_obj, true);
14020 if (ret) {
14021 /* GPU hangs should have been swallowed by the wait */
14022 WARN_ON(ret == -EIO);
14023 return ret;
14024 }
14025 }
14026
14027 if (!obj)
14028 return 0;
14029
14030 /* For framebuffer backed by dmabuf, wait for fence */
14031 resv = i915_gem_object_get_dmabuf_resv(obj);
14032 if (resv) {
14033 long lret;
14034
14035 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14036 MAX_SCHEDULE_TIMEOUT);
14037 if (lret == -ERESTARTSYS)
14038 return lret;
14039
14040 WARN(lret < 0, "waiting returns %li\n", lret);
14041 }
14042
14043 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14044 INTEL_INFO(dev)->cursor_needs_physical) {
14045 int align = IS_I830(dev) ? 16 * 1024 : 256;
14046 ret = i915_gem_object_attach_phys(obj, align);
14047 if (ret)
14048 DRM_DEBUG_KMS("failed to attach phys object\n");
14049 } else {
14050 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14051 }
14052
14053 if (ret == 0) {
14054 to_intel_plane_state(new_state)->wait_req =
14055 i915_gem_active_get(&obj->last_write,
14056 &obj->base.dev->struct_mutex);
14057 }
14058
14059 return ret;
14060 }
14061
14062 /**
14063 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14064 * @plane: drm plane to clean up for
14065 * @fb: old framebuffer that was on plane
14066 *
14067 * Cleans up a framebuffer that has just been removed from a plane.
14068 *
14069 * Must be called with struct_mutex held.
14070 */
14071 void
14072 intel_cleanup_plane_fb(struct drm_plane *plane,
14073 const struct drm_plane_state *old_state)
14074 {
14075 struct drm_device *dev = plane->dev;
14076 struct intel_plane_state *old_intel_state;
14077 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14078 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14079 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14080
14081 old_intel_state = to_intel_plane_state(old_state);
14082
14083 if (!obj && !old_obj)
14084 return;
14085
14086 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14087 !INTEL_INFO(dev)->cursor_needs_physical))
14088 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14089
14090 i915_gem_request_assign(&intel_state->wait_req, NULL);
14091 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14092 }
14093
14094 int
14095 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14096 {
14097 int max_scale;
14098 int crtc_clock, cdclk;
14099
14100 if (!intel_crtc || !crtc_state->base.enable)
14101 return DRM_PLANE_HELPER_NO_SCALING;
14102
14103 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14104 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14105
14106 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14107 return DRM_PLANE_HELPER_NO_SCALING;
14108
14109 /*
14110 * skl max scale is lower of:
14111 * close to 3 but not 3, -1 is for that purpose
14112 * or
14113 * cdclk/crtc_clock
14114 */
14115 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14116
14117 return max_scale;
14118 }
14119
14120 static int
14121 intel_check_primary_plane(struct drm_plane *plane,
14122 struct intel_crtc_state *crtc_state,
14123 struct intel_plane_state *state)
14124 {
14125 struct drm_crtc *crtc = state->base.crtc;
14126 struct drm_framebuffer *fb = state->base.fb;
14127 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14128 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14129 bool can_position = false;
14130
14131 if (INTEL_INFO(plane->dev)->gen >= 9) {
14132 /* use scaler when colorkey is not required */
14133 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14134 min_scale = 1;
14135 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14136 }
14137 can_position = true;
14138 }
14139
14140 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14141 &state->dst, &state->clip,
14142 state->base.rotation,
14143 min_scale, max_scale,
14144 can_position, true,
14145 &state->visible);
14146 }
14147
14148 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14149 struct drm_crtc_state *old_crtc_state)
14150 {
14151 struct drm_device *dev = crtc->dev;
14152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14153 struct intel_crtc_state *old_intel_state =
14154 to_intel_crtc_state(old_crtc_state);
14155 bool modeset = needs_modeset(crtc->state);
14156
14157 /* Perform vblank evasion around commit operation */
14158 intel_pipe_update_start(intel_crtc);
14159
14160 if (modeset)
14161 return;
14162
14163 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14164 intel_color_set_csc(crtc->state);
14165 intel_color_load_luts(crtc->state);
14166 }
14167
14168 if (to_intel_crtc_state(crtc->state)->update_pipe)
14169 intel_update_pipe_config(intel_crtc, old_intel_state);
14170 else if (INTEL_INFO(dev)->gen >= 9)
14171 skl_detach_scalers(intel_crtc);
14172 }
14173
14174 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14175 struct drm_crtc_state *old_crtc_state)
14176 {
14177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14178
14179 intel_pipe_update_end(intel_crtc, NULL);
14180 }
14181
14182 /**
14183 * intel_plane_destroy - destroy a plane
14184 * @plane: plane to destroy
14185 *
14186 * Common destruction function for all types of planes (primary, cursor,
14187 * sprite).
14188 */
14189 void intel_plane_destroy(struct drm_plane *plane)
14190 {
14191 if (!plane)
14192 return;
14193
14194 drm_plane_cleanup(plane);
14195 kfree(to_intel_plane(plane));
14196 }
14197
14198 const struct drm_plane_funcs intel_plane_funcs = {
14199 .update_plane = drm_atomic_helper_update_plane,
14200 .disable_plane = drm_atomic_helper_disable_plane,
14201 .destroy = intel_plane_destroy,
14202 .set_property = drm_atomic_helper_plane_set_property,
14203 .atomic_get_property = intel_plane_atomic_get_property,
14204 .atomic_set_property = intel_plane_atomic_set_property,
14205 .atomic_duplicate_state = intel_plane_duplicate_state,
14206 .atomic_destroy_state = intel_plane_destroy_state,
14207
14208 };
14209
14210 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14211 int pipe)
14212 {
14213 struct intel_plane *primary = NULL;
14214 struct intel_plane_state *state = NULL;
14215 const uint32_t *intel_primary_formats;
14216 unsigned int num_formats;
14217 int ret;
14218
14219 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14220 if (!primary)
14221 goto fail;
14222
14223 state = intel_create_plane_state(&primary->base);
14224 if (!state)
14225 goto fail;
14226 primary->base.state = &state->base;
14227
14228 primary->can_scale = false;
14229 primary->max_downscale = 1;
14230 if (INTEL_INFO(dev)->gen >= 9) {
14231 primary->can_scale = true;
14232 state->scaler_id = -1;
14233 }
14234 primary->pipe = pipe;
14235 primary->plane = pipe;
14236 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14237 primary->check_plane = intel_check_primary_plane;
14238 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14239 primary->plane = !pipe;
14240
14241 if (INTEL_INFO(dev)->gen >= 9) {
14242 intel_primary_formats = skl_primary_formats;
14243 num_formats = ARRAY_SIZE(skl_primary_formats);
14244
14245 primary->update_plane = skylake_update_primary_plane;
14246 primary->disable_plane = skylake_disable_primary_plane;
14247 } else if (HAS_PCH_SPLIT(dev)) {
14248 intel_primary_formats = i965_primary_formats;
14249 num_formats = ARRAY_SIZE(i965_primary_formats);
14250
14251 primary->update_plane = ironlake_update_primary_plane;
14252 primary->disable_plane = i9xx_disable_primary_plane;
14253 } else if (INTEL_INFO(dev)->gen >= 4) {
14254 intel_primary_formats = i965_primary_formats;
14255 num_formats = ARRAY_SIZE(i965_primary_formats);
14256
14257 primary->update_plane = i9xx_update_primary_plane;
14258 primary->disable_plane = i9xx_disable_primary_plane;
14259 } else {
14260 intel_primary_formats = i8xx_primary_formats;
14261 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14262
14263 primary->update_plane = i9xx_update_primary_plane;
14264 primary->disable_plane = i9xx_disable_primary_plane;
14265 }
14266
14267 if (INTEL_INFO(dev)->gen >= 9)
14268 ret = drm_universal_plane_init(dev, &primary->base, 0,
14269 &intel_plane_funcs,
14270 intel_primary_formats, num_formats,
14271 DRM_PLANE_TYPE_PRIMARY,
14272 "plane 1%c", pipe_name(pipe));
14273 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14274 ret = drm_universal_plane_init(dev, &primary->base, 0,
14275 &intel_plane_funcs,
14276 intel_primary_formats, num_formats,
14277 DRM_PLANE_TYPE_PRIMARY,
14278 "primary %c", pipe_name(pipe));
14279 else
14280 ret = drm_universal_plane_init(dev, &primary->base, 0,
14281 &intel_plane_funcs,
14282 intel_primary_formats, num_formats,
14283 DRM_PLANE_TYPE_PRIMARY,
14284 "plane %c", plane_name(primary->plane));
14285 if (ret)
14286 goto fail;
14287
14288 if (INTEL_INFO(dev)->gen >= 4)
14289 intel_create_rotation_property(dev, primary);
14290
14291 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14292
14293 return &primary->base;
14294
14295 fail:
14296 kfree(state);
14297 kfree(primary);
14298
14299 return NULL;
14300 }
14301
14302 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14303 {
14304 if (!dev->mode_config.rotation_property) {
14305 unsigned long flags = BIT(DRM_ROTATE_0) |
14306 BIT(DRM_ROTATE_180);
14307
14308 if (INTEL_INFO(dev)->gen >= 9)
14309 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14310
14311 dev->mode_config.rotation_property =
14312 drm_mode_create_rotation_property(dev, flags);
14313 }
14314 if (dev->mode_config.rotation_property)
14315 drm_object_attach_property(&plane->base.base,
14316 dev->mode_config.rotation_property,
14317 plane->base.state->rotation);
14318 }
14319
14320 static int
14321 intel_check_cursor_plane(struct drm_plane *plane,
14322 struct intel_crtc_state *crtc_state,
14323 struct intel_plane_state *state)
14324 {
14325 struct drm_crtc *crtc = crtc_state->base.crtc;
14326 struct drm_framebuffer *fb = state->base.fb;
14327 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14328 enum pipe pipe = to_intel_plane(plane)->pipe;
14329 unsigned stride;
14330 int ret;
14331
14332 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14333 &state->dst, &state->clip,
14334 state->base.rotation,
14335 DRM_PLANE_HELPER_NO_SCALING,
14336 DRM_PLANE_HELPER_NO_SCALING,
14337 true, true, &state->visible);
14338 if (ret)
14339 return ret;
14340
14341 /* if we want to turn off the cursor ignore width and height */
14342 if (!obj)
14343 return 0;
14344
14345 /* Check for which cursor types we support */
14346 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14347 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14348 state->base.crtc_w, state->base.crtc_h);
14349 return -EINVAL;
14350 }
14351
14352 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14353 if (obj->base.size < stride * state->base.crtc_h) {
14354 DRM_DEBUG_KMS("buffer is too small\n");
14355 return -ENOMEM;
14356 }
14357
14358 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14359 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14360 return -EINVAL;
14361 }
14362
14363 /*
14364 * There's something wrong with the cursor on CHV pipe C.
14365 * If it straddles the left edge of the screen then
14366 * moving it away from the edge or disabling it often
14367 * results in a pipe underrun, and often that can lead to
14368 * dead pipe (constant underrun reported, and it scans
14369 * out just a solid color). To recover from that, the
14370 * display power well must be turned off and on again.
14371 * Refuse the put the cursor into that compromised position.
14372 */
14373 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14374 state->visible && state->base.crtc_x < 0) {
14375 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14376 return -EINVAL;
14377 }
14378
14379 return 0;
14380 }
14381
14382 static void
14383 intel_disable_cursor_plane(struct drm_plane *plane,
14384 struct drm_crtc *crtc)
14385 {
14386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14387
14388 intel_crtc->cursor_addr = 0;
14389 intel_crtc_update_cursor(crtc, NULL);
14390 }
14391
14392 static void
14393 intel_update_cursor_plane(struct drm_plane *plane,
14394 const struct intel_crtc_state *crtc_state,
14395 const struct intel_plane_state *state)
14396 {
14397 struct drm_crtc *crtc = crtc_state->base.crtc;
14398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14399 struct drm_device *dev = plane->dev;
14400 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14401 uint32_t addr;
14402
14403 if (!obj)
14404 addr = 0;
14405 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14406 addr = i915_gem_obj_ggtt_offset(obj);
14407 else
14408 addr = obj->phys_handle->busaddr;
14409
14410 intel_crtc->cursor_addr = addr;
14411 intel_crtc_update_cursor(crtc, state);
14412 }
14413
14414 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14415 int pipe)
14416 {
14417 struct intel_plane *cursor = NULL;
14418 struct intel_plane_state *state = NULL;
14419 int ret;
14420
14421 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14422 if (!cursor)
14423 goto fail;
14424
14425 state = intel_create_plane_state(&cursor->base);
14426 if (!state)
14427 goto fail;
14428 cursor->base.state = &state->base;
14429
14430 cursor->can_scale = false;
14431 cursor->max_downscale = 1;
14432 cursor->pipe = pipe;
14433 cursor->plane = pipe;
14434 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14435 cursor->check_plane = intel_check_cursor_plane;
14436 cursor->update_plane = intel_update_cursor_plane;
14437 cursor->disable_plane = intel_disable_cursor_plane;
14438
14439 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14440 &intel_plane_funcs,
14441 intel_cursor_formats,
14442 ARRAY_SIZE(intel_cursor_formats),
14443 DRM_PLANE_TYPE_CURSOR,
14444 "cursor %c", pipe_name(pipe));
14445 if (ret)
14446 goto fail;
14447
14448 if (INTEL_INFO(dev)->gen >= 4) {
14449 if (!dev->mode_config.rotation_property)
14450 dev->mode_config.rotation_property =
14451 drm_mode_create_rotation_property(dev,
14452 BIT(DRM_ROTATE_0) |
14453 BIT(DRM_ROTATE_180));
14454 if (dev->mode_config.rotation_property)
14455 drm_object_attach_property(&cursor->base.base,
14456 dev->mode_config.rotation_property,
14457 state->base.rotation);
14458 }
14459
14460 if (INTEL_INFO(dev)->gen >=9)
14461 state->scaler_id = -1;
14462
14463 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14464
14465 return &cursor->base;
14466
14467 fail:
14468 kfree(state);
14469 kfree(cursor);
14470
14471 return NULL;
14472 }
14473
14474 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14475 struct intel_crtc_state *crtc_state)
14476 {
14477 int i;
14478 struct intel_scaler *intel_scaler;
14479 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14480
14481 for (i = 0; i < intel_crtc->num_scalers; i++) {
14482 intel_scaler = &scaler_state->scalers[i];
14483 intel_scaler->in_use = 0;
14484 intel_scaler->mode = PS_SCALER_MODE_DYN;
14485 }
14486
14487 scaler_state->scaler_id = -1;
14488 }
14489
14490 static void intel_crtc_init(struct drm_device *dev, int pipe)
14491 {
14492 struct drm_i915_private *dev_priv = to_i915(dev);
14493 struct intel_crtc *intel_crtc;
14494 struct intel_crtc_state *crtc_state = NULL;
14495 struct drm_plane *primary = NULL;
14496 struct drm_plane *cursor = NULL;
14497 int ret;
14498
14499 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14500 if (intel_crtc == NULL)
14501 return;
14502
14503 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14504 if (!crtc_state)
14505 goto fail;
14506 intel_crtc->config = crtc_state;
14507 intel_crtc->base.state = &crtc_state->base;
14508 crtc_state->base.crtc = &intel_crtc->base;
14509
14510 /* initialize shared scalers */
14511 if (INTEL_INFO(dev)->gen >= 9) {
14512 if (pipe == PIPE_C)
14513 intel_crtc->num_scalers = 1;
14514 else
14515 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14516
14517 skl_init_scalers(dev, intel_crtc, crtc_state);
14518 }
14519
14520 primary = intel_primary_plane_create(dev, pipe);
14521 if (!primary)
14522 goto fail;
14523
14524 cursor = intel_cursor_plane_create(dev, pipe);
14525 if (!cursor)
14526 goto fail;
14527
14528 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14529 cursor, &intel_crtc_funcs,
14530 "pipe %c", pipe_name(pipe));
14531 if (ret)
14532 goto fail;
14533
14534 /*
14535 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14536 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14537 */
14538 intel_crtc->pipe = pipe;
14539 intel_crtc->plane = pipe;
14540 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14541 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14542 intel_crtc->plane = !pipe;
14543 }
14544
14545 intel_crtc->cursor_base = ~0;
14546 intel_crtc->cursor_cntl = ~0;
14547 intel_crtc->cursor_size = ~0;
14548
14549 intel_crtc->wm.cxsr_allowed = true;
14550
14551 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14552 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14553 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14554 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14555
14556 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14557
14558 intel_color_init(&intel_crtc->base);
14559
14560 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14561 return;
14562
14563 fail:
14564 intel_plane_destroy(primary);
14565 intel_plane_destroy(cursor);
14566 kfree(crtc_state);
14567 kfree(intel_crtc);
14568 }
14569
14570 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14571 {
14572 struct drm_encoder *encoder = connector->base.encoder;
14573 struct drm_device *dev = connector->base.dev;
14574
14575 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14576
14577 if (!encoder || WARN_ON(!encoder->crtc))
14578 return INVALID_PIPE;
14579
14580 return to_intel_crtc(encoder->crtc)->pipe;
14581 }
14582
14583 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14584 struct drm_file *file)
14585 {
14586 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14587 struct drm_crtc *drmmode_crtc;
14588 struct intel_crtc *crtc;
14589
14590 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14591 if (!drmmode_crtc)
14592 return -ENOENT;
14593
14594 crtc = to_intel_crtc(drmmode_crtc);
14595 pipe_from_crtc_id->pipe = crtc->pipe;
14596
14597 return 0;
14598 }
14599
14600 static int intel_encoder_clones(struct intel_encoder *encoder)
14601 {
14602 struct drm_device *dev = encoder->base.dev;
14603 struct intel_encoder *source_encoder;
14604 int index_mask = 0;
14605 int entry = 0;
14606
14607 for_each_intel_encoder(dev, source_encoder) {
14608 if (encoders_cloneable(encoder, source_encoder))
14609 index_mask |= (1 << entry);
14610
14611 entry++;
14612 }
14613
14614 return index_mask;
14615 }
14616
14617 static bool has_edp_a(struct drm_device *dev)
14618 {
14619 struct drm_i915_private *dev_priv = to_i915(dev);
14620
14621 if (!IS_MOBILE(dev))
14622 return false;
14623
14624 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14625 return false;
14626
14627 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14628 return false;
14629
14630 return true;
14631 }
14632
14633 static bool intel_crt_present(struct drm_device *dev)
14634 {
14635 struct drm_i915_private *dev_priv = to_i915(dev);
14636
14637 if (INTEL_INFO(dev)->gen >= 9)
14638 return false;
14639
14640 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14641 return false;
14642
14643 if (IS_CHERRYVIEW(dev))
14644 return false;
14645
14646 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14647 return false;
14648
14649 /* DDI E can't be used if DDI A requires 4 lanes */
14650 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14651 return false;
14652
14653 if (!dev_priv->vbt.int_crt_support)
14654 return false;
14655
14656 return true;
14657 }
14658
14659 static void intel_setup_outputs(struct drm_device *dev)
14660 {
14661 struct drm_i915_private *dev_priv = to_i915(dev);
14662 struct intel_encoder *encoder;
14663 bool dpd_is_edp = false;
14664
14665 /*
14666 * intel_edp_init_connector() depends on this completing first, to
14667 * prevent the registeration of both eDP and LVDS and the incorrect
14668 * sharing of the PPS.
14669 */
14670 intel_lvds_init(dev);
14671
14672 if (intel_crt_present(dev))
14673 intel_crt_init(dev);
14674
14675 if (IS_BROXTON(dev)) {
14676 /*
14677 * FIXME: Broxton doesn't support port detection via the
14678 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14679 * detect the ports.
14680 */
14681 intel_ddi_init(dev, PORT_A);
14682 intel_ddi_init(dev, PORT_B);
14683 intel_ddi_init(dev, PORT_C);
14684
14685 intel_dsi_init(dev);
14686 } else if (HAS_DDI(dev)) {
14687 int found;
14688
14689 /*
14690 * Haswell uses DDI functions to detect digital outputs.
14691 * On SKL pre-D0 the strap isn't connected, so we assume
14692 * it's there.
14693 */
14694 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14695 /* WaIgnoreDDIAStrap: skl */
14696 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14697 intel_ddi_init(dev, PORT_A);
14698
14699 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14700 * register */
14701 found = I915_READ(SFUSE_STRAP);
14702
14703 if (found & SFUSE_STRAP_DDIB_DETECTED)
14704 intel_ddi_init(dev, PORT_B);
14705 if (found & SFUSE_STRAP_DDIC_DETECTED)
14706 intel_ddi_init(dev, PORT_C);
14707 if (found & SFUSE_STRAP_DDID_DETECTED)
14708 intel_ddi_init(dev, PORT_D);
14709 /*
14710 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14711 */
14712 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14713 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14714 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14715 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14716 intel_ddi_init(dev, PORT_E);
14717
14718 } else if (HAS_PCH_SPLIT(dev)) {
14719 int found;
14720 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14721
14722 if (has_edp_a(dev))
14723 intel_dp_init(dev, DP_A, PORT_A);
14724
14725 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14726 /* PCH SDVOB multiplex with HDMIB */
14727 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14728 if (!found)
14729 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14730 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14731 intel_dp_init(dev, PCH_DP_B, PORT_B);
14732 }
14733
14734 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14735 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14736
14737 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14738 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14739
14740 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14741 intel_dp_init(dev, PCH_DP_C, PORT_C);
14742
14743 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14744 intel_dp_init(dev, PCH_DP_D, PORT_D);
14745 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14746 bool has_edp, has_port;
14747
14748 /*
14749 * The DP_DETECTED bit is the latched state of the DDC
14750 * SDA pin at boot. However since eDP doesn't require DDC
14751 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14752 * eDP ports may have been muxed to an alternate function.
14753 * Thus we can't rely on the DP_DETECTED bit alone to detect
14754 * eDP ports. Consult the VBT as well as DP_DETECTED to
14755 * detect eDP ports.
14756 *
14757 * Sadly the straps seem to be missing sometimes even for HDMI
14758 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14759 * and VBT for the presence of the port. Additionally we can't
14760 * trust the port type the VBT declares as we've seen at least
14761 * HDMI ports that the VBT claim are DP or eDP.
14762 */
14763 has_edp = intel_dp_is_edp(dev, PORT_B);
14764 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14765 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14766 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14767 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14768 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14769
14770 has_edp = intel_dp_is_edp(dev, PORT_C);
14771 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14772 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14773 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14774 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14775 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14776
14777 if (IS_CHERRYVIEW(dev)) {
14778 /*
14779 * eDP not supported on port D,
14780 * so no need to worry about it
14781 */
14782 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14783 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14784 intel_dp_init(dev, CHV_DP_D, PORT_D);
14785 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14786 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14787 }
14788
14789 intel_dsi_init(dev);
14790 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14791 bool found = false;
14792
14793 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14794 DRM_DEBUG_KMS("probing SDVOB\n");
14795 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14796 if (!found && IS_G4X(dev)) {
14797 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14798 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14799 }
14800
14801 if (!found && IS_G4X(dev))
14802 intel_dp_init(dev, DP_B, PORT_B);
14803 }
14804
14805 /* Before G4X SDVOC doesn't have its own detect register */
14806
14807 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14808 DRM_DEBUG_KMS("probing SDVOC\n");
14809 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14810 }
14811
14812 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14813
14814 if (IS_G4X(dev)) {
14815 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14816 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14817 }
14818 if (IS_G4X(dev))
14819 intel_dp_init(dev, DP_C, PORT_C);
14820 }
14821
14822 if (IS_G4X(dev) &&
14823 (I915_READ(DP_D) & DP_DETECTED))
14824 intel_dp_init(dev, DP_D, PORT_D);
14825 } else if (IS_GEN2(dev))
14826 intel_dvo_init(dev);
14827
14828 if (SUPPORTS_TV(dev))
14829 intel_tv_init(dev);
14830
14831 intel_psr_init(dev);
14832
14833 for_each_intel_encoder(dev, encoder) {
14834 encoder->base.possible_crtcs = encoder->crtc_mask;
14835 encoder->base.possible_clones =
14836 intel_encoder_clones(encoder);
14837 }
14838
14839 intel_init_pch_refclk(dev);
14840
14841 drm_helper_move_panel_connectors_to_head(dev);
14842 }
14843
14844 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14845 {
14846 struct drm_device *dev = fb->dev;
14847 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14848
14849 drm_framebuffer_cleanup(fb);
14850 mutex_lock(&dev->struct_mutex);
14851 WARN_ON(!intel_fb->obj->framebuffer_references--);
14852 i915_gem_object_put(intel_fb->obj);
14853 mutex_unlock(&dev->struct_mutex);
14854 kfree(intel_fb);
14855 }
14856
14857 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14858 struct drm_file *file,
14859 unsigned int *handle)
14860 {
14861 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14862 struct drm_i915_gem_object *obj = intel_fb->obj;
14863
14864 if (obj->userptr.mm) {
14865 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14866 return -EINVAL;
14867 }
14868
14869 return drm_gem_handle_create(file, &obj->base, handle);
14870 }
14871
14872 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14873 struct drm_file *file,
14874 unsigned flags, unsigned color,
14875 struct drm_clip_rect *clips,
14876 unsigned num_clips)
14877 {
14878 struct drm_device *dev = fb->dev;
14879 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14880 struct drm_i915_gem_object *obj = intel_fb->obj;
14881
14882 mutex_lock(&dev->struct_mutex);
14883 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14884 mutex_unlock(&dev->struct_mutex);
14885
14886 return 0;
14887 }
14888
14889 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14890 .destroy = intel_user_framebuffer_destroy,
14891 .create_handle = intel_user_framebuffer_create_handle,
14892 .dirty = intel_user_framebuffer_dirty,
14893 };
14894
14895 static
14896 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14897 uint32_t pixel_format)
14898 {
14899 u32 gen = INTEL_INFO(dev)->gen;
14900
14901 if (gen >= 9) {
14902 int cpp = drm_format_plane_cpp(pixel_format, 0);
14903
14904 /* "The stride in bytes must not exceed the of the size of 8K
14905 * pixels and 32K bytes."
14906 */
14907 return min(8192 * cpp, 32768);
14908 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14909 return 32*1024;
14910 } else if (gen >= 4) {
14911 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14912 return 16*1024;
14913 else
14914 return 32*1024;
14915 } else if (gen >= 3) {
14916 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14917 return 8*1024;
14918 else
14919 return 16*1024;
14920 } else {
14921 /* XXX DSPC is limited to 4k tiled */
14922 return 8*1024;
14923 }
14924 }
14925
14926 static int intel_framebuffer_init(struct drm_device *dev,
14927 struct intel_framebuffer *intel_fb,
14928 struct drm_mode_fb_cmd2 *mode_cmd,
14929 struct drm_i915_gem_object *obj)
14930 {
14931 struct drm_i915_private *dev_priv = to_i915(dev);
14932 unsigned int aligned_height;
14933 int ret;
14934 u32 pitch_limit, stride_alignment;
14935
14936 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14937
14938 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14939 /* Enforce that fb modifier and tiling mode match, but only for
14940 * X-tiled. This is needed for FBC. */
14941 if (!!(obj->tiling_mode == I915_TILING_X) !=
14942 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14943 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14944 return -EINVAL;
14945 }
14946 } else {
14947 if (obj->tiling_mode == I915_TILING_X)
14948 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14949 else if (obj->tiling_mode == I915_TILING_Y) {
14950 DRM_DEBUG("No Y tiling for legacy addfb\n");
14951 return -EINVAL;
14952 }
14953 }
14954
14955 /* Passed in modifier sanity checking. */
14956 switch (mode_cmd->modifier[0]) {
14957 case I915_FORMAT_MOD_Y_TILED:
14958 case I915_FORMAT_MOD_Yf_TILED:
14959 if (INTEL_INFO(dev)->gen < 9) {
14960 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14961 mode_cmd->modifier[0]);
14962 return -EINVAL;
14963 }
14964 case DRM_FORMAT_MOD_NONE:
14965 case I915_FORMAT_MOD_X_TILED:
14966 break;
14967 default:
14968 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14969 mode_cmd->modifier[0]);
14970 return -EINVAL;
14971 }
14972
14973 stride_alignment = intel_fb_stride_alignment(dev_priv,
14974 mode_cmd->modifier[0],
14975 mode_cmd->pixel_format);
14976 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14977 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14978 mode_cmd->pitches[0], stride_alignment);
14979 return -EINVAL;
14980 }
14981
14982 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14983 mode_cmd->pixel_format);
14984 if (mode_cmd->pitches[0] > pitch_limit) {
14985 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14986 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14987 "tiled" : "linear",
14988 mode_cmd->pitches[0], pitch_limit);
14989 return -EINVAL;
14990 }
14991
14992 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14993 mode_cmd->pitches[0] != obj->stride) {
14994 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14995 mode_cmd->pitches[0], obj->stride);
14996 return -EINVAL;
14997 }
14998
14999 /* Reject formats not supported by any plane early. */
15000 switch (mode_cmd->pixel_format) {
15001 case DRM_FORMAT_C8:
15002 case DRM_FORMAT_RGB565:
15003 case DRM_FORMAT_XRGB8888:
15004 case DRM_FORMAT_ARGB8888:
15005 break;
15006 case DRM_FORMAT_XRGB1555:
15007 if (INTEL_INFO(dev)->gen > 3) {
15008 DRM_DEBUG("unsupported pixel format: %s\n",
15009 drm_get_format_name(mode_cmd->pixel_format));
15010 return -EINVAL;
15011 }
15012 break;
15013 case DRM_FORMAT_ABGR8888:
15014 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15015 INTEL_INFO(dev)->gen < 9) {
15016 DRM_DEBUG("unsupported pixel format: %s\n",
15017 drm_get_format_name(mode_cmd->pixel_format));
15018 return -EINVAL;
15019 }
15020 break;
15021 case DRM_FORMAT_XBGR8888:
15022 case DRM_FORMAT_XRGB2101010:
15023 case DRM_FORMAT_XBGR2101010:
15024 if (INTEL_INFO(dev)->gen < 4) {
15025 DRM_DEBUG("unsupported pixel format: %s\n",
15026 drm_get_format_name(mode_cmd->pixel_format));
15027 return -EINVAL;
15028 }
15029 break;
15030 case DRM_FORMAT_ABGR2101010:
15031 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15032 DRM_DEBUG("unsupported pixel format: %s\n",
15033 drm_get_format_name(mode_cmd->pixel_format));
15034 return -EINVAL;
15035 }
15036 break;
15037 case DRM_FORMAT_YUYV:
15038 case DRM_FORMAT_UYVY:
15039 case DRM_FORMAT_YVYU:
15040 case DRM_FORMAT_VYUY:
15041 if (INTEL_INFO(dev)->gen < 5) {
15042 DRM_DEBUG("unsupported pixel format: %s\n",
15043 drm_get_format_name(mode_cmd->pixel_format));
15044 return -EINVAL;
15045 }
15046 break;
15047 default:
15048 DRM_DEBUG("unsupported pixel format: %s\n",
15049 drm_get_format_name(mode_cmd->pixel_format));
15050 return -EINVAL;
15051 }
15052
15053 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15054 if (mode_cmd->offsets[0] != 0)
15055 return -EINVAL;
15056
15057 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15058 mode_cmd->pixel_format,
15059 mode_cmd->modifier[0]);
15060 /* FIXME drm helper for size checks (especially planar formats)? */
15061 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15062 return -EINVAL;
15063
15064 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15065 intel_fb->obj = obj;
15066
15067 intel_fill_fb_info(dev_priv, &intel_fb->base);
15068
15069 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15070 if (ret) {
15071 DRM_ERROR("framebuffer init failed %d\n", ret);
15072 return ret;
15073 }
15074
15075 intel_fb->obj->framebuffer_references++;
15076
15077 return 0;
15078 }
15079
15080 static struct drm_framebuffer *
15081 intel_user_framebuffer_create(struct drm_device *dev,
15082 struct drm_file *filp,
15083 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15084 {
15085 struct drm_framebuffer *fb;
15086 struct drm_i915_gem_object *obj;
15087 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15088
15089 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15090 if (!obj)
15091 return ERR_PTR(-ENOENT);
15092
15093 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15094 if (IS_ERR(fb))
15095 i915_gem_object_put_unlocked(obj);
15096
15097 return fb;
15098 }
15099
15100 #ifndef CONFIG_DRM_FBDEV_EMULATION
15101 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15102 {
15103 }
15104 #endif
15105
15106 static const struct drm_mode_config_funcs intel_mode_funcs = {
15107 .fb_create = intel_user_framebuffer_create,
15108 .output_poll_changed = intel_fbdev_output_poll_changed,
15109 .atomic_check = intel_atomic_check,
15110 .atomic_commit = intel_atomic_commit,
15111 .atomic_state_alloc = intel_atomic_state_alloc,
15112 .atomic_state_clear = intel_atomic_state_clear,
15113 };
15114
15115 /**
15116 * intel_init_display_hooks - initialize the display modesetting hooks
15117 * @dev_priv: device private
15118 */
15119 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15120 {
15121 if (INTEL_INFO(dev_priv)->gen >= 9) {
15122 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15123 dev_priv->display.get_initial_plane_config =
15124 skylake_get_initial_plane_config;
15125 dev_priv->display.crtc_compute_clock =
15126 haswell_crtc_compute_clock;
15127 dev_priv->display.crtc_enable = haswell_crtc_enable;
15128 dev_priv->display.crtc_disable = haswell_crtc_disable;
15129 } else if (HAS_DDI(dev_priv)) {
15130 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15131 dev_priv->display.get_initial_plane_config =
15132 ironlake_get_initial_plane_config;
15133 dev_priv->display.crtc_compute_clock =
15134 haswell_crtc_compute_clock;
15135 dev_priv->display.crtc_enable = haswell_crtc_enable;
15136 dev_priv->display.crtc_disable = haswell_crtc_disable;
15137 } else if (HAS_PCH_SPLIT(dev_priv)) {
15138 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15139 dev_priv->display.get_initial_plane_config =
15140 ironlake_get_initial_plane_config;
15141 dev_priv->display.crtc_compute_clock =
15142 ironlake_crtc_compute_clock;
15143 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15144 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15145 } else if (IS_CHERRYVIEW(dev_priv)) {
15146 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15147 dev_priv->display.get_initial_plane_config =
15148 i9xx_get_initial_plane_config;
15149 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15150 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15151 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15152 } else if (IS_VALLEYVIEW(dev_priv)) {
15153 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15154 dev_priv->display.get_initial_plane_config =
15155 i9xx_get_initial_plane_config;
15156 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15157 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15158 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15159 } else if (IS_G4X(dev_priv)) {
15160 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15161 dev_priv->display.get_initial_plane_config =
15162 i9xx_get_initial_plane_config;
15163 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15164 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15165 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15166 } else if (IS_PINEVIEW(dev_priv)) {
15167 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15168 dev_priv->display.get_initial_plane_config =
15169 i9xx_get_initial_plane_config;
15170 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15171 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15172 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15173 } else if (!IS_GEN2(dev_priv)) {
15174 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15175 dev_priv->display.get_initial_plane_config =
15176 i9xx_get_initial_plane_config;
15177 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15178 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15179 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15180 } else {
15181 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15182 dev_priv->display.get_initial_plane_config =
15183 i9xx_get_initial_plane_config;
15184 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15185 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15186 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15187 }
15188
15189 /* Returns the core display clock speed */
15190 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15191 dev_priv->display.get_display_clock_speed =
15192 skylake_get_display_clock_speed;
15193 else if (IS_BROXTON(dev_priv))
15194 dev_priv->display.get_display_clock_speed =
15195 broxton_get_display_clock_speed;
15196 else if (IS_BROADWELL(dev_priv))
15197 dev_priv->display.get_display_clock_speed =
15198 broadwell_get_display_clock_speed;
15199 else if (IS_HASWELL(dev_priv))
15200 dev_priv->display.get_display_clock_speed =
15201 haswell_get_display_clock_speed;
15202 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15203 dev_priv->display.get_display_clock_speed =
15204 valleyview_get_display_clock_speed;
15205 else if (IS_GEN5(dev_priv))
15206 dev_priv->display.get_display_clock_speed =
15207 ilk_get_display_clock_speed;
15208 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15209 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15210 dev_priv->display.get_display_clock_speed =
15211 i945_get_display_clock_speed;
15212 else if (IS_GM45(dev_priv))
15213 dev_priv->display.get_display_clock_speed =
15214 gm45_get_display_clock_speed;
15215 else if (IS_CRESTLINE(dev_priv))
15216 dev_priv->display.get_display_clock_speed =
15217 i965gm_get_display_clock_speed;
15218 else if (IS_PINEVIEW(dev_priv))
15219 dev_priv->display.get_display_clock_speed =
15220 pnv_get_display_clock_speed;
15221 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15222 dev_priv->display.get_display_clock_speed =
15223 g33_get_display_clock_speed;
15224 else if (IS_I915G(dev_priv))
15225 dev_priv->display.get_display_clock_speed =
15226 i915_get_display_clock_speed;
15227 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15228 dev_priv->display.get_display_clock_speed =
15229 i9xx_misc_get_display_clock_speed;
15230 else if (IS_I915GM(dev_priv))
15231 dev_priv->display.get_display_clock_speed =
15232 i915gm_get_display_clock_speed;
15233 else if (IS_I865G(dev_priv))
15234 dev_priv->display.get_display_clock_speed =
15235 i865_get_display_clock_speed;
15236 else if (IS_I85X(dev_priv))
15237 dev_priv->display.get_display_clock_speed =
15238 i85x_get_display_clock_speed;
15239 else { /* 830 */
15240 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15241 dev_priv->display.get_display_clock_speed =
15242 i830_get_display_clock_speed;
15243 }
15244
15245 if (IS_GEN5(dev_priv)) {
15246 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15247 } else if (IS_GEN6(dev_priv)) {
15248 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15249 } else if (IS_IVYBRIDGE(dev_priv)) {
15250 /* FIXME: detect B0+ stepping and use auto training */
15251 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15252 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15253 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15254 }
15255
15256 if (IS_BROADWELL(dev_priv)) {
15257 dev_priv->display.modeset_commit_cdclk =
15258 broadwell_modeset_commit_cdclk;
15259 dev_priv->display.modeset_calc_cdclk =
15260 broadwell_modeset_calc_cdclk;
15261 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15262 dev_priv->display.modeset_commit_cdclk =
15263 valleyview_modeset_commit_cdclk;
15264 dev_priv->display.modeset_calc_cdclk =
15265 valleyview_modeset_calc_cdclk;
15266 } else if (IS_BROXTON(dev_priv)) {
15267 dev_priv->display.modeset_commit_cdclk =
15268 bxt_modeset_commit_cdclk;
15269 dev_priv->display.modeset_calc_cdclk =
15270 bxt_modeset_calc_cdclk;
15271 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15272 dev_priv->display.modeset_commit_cdclk =
15273 skl_modeset_commit_cdclk;
15274 dev_priv->display.modeset_calc_cdclk =
15275 skl_modeset_calc_cdclk;
15276 }
15277
15278 switch (INTEL_INFO(dev_priv)->gen) {
15279 case 2:
15280 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15281 break;
15282
15283 case 3:
15284 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15285 break;
15286
15287 case 4:
15288 case 5:
15289 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15290 break;
15291
15292 case 6:
15293 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15294 break;
15295 case 7:
15296 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15297 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15298 break;
15299 case 9:
15300 /* Drop through - unsupported since execlist only. */
15301 default:
15302 /* Default just returns -ENODEV to indicate unsupported */
15303 dev_priv->display.queue_flip = intel_default_queue_flip;
15304 }
15305 }
15306
15307 /*
15308 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15309 * resume, or other times. This quirk makes sure that's the case for
15310 * affected systems.
15311 */
15312 static void quirk_pipea_force(struct drm_device *dev)
15313 {
15314 struct drm_i915_private *dev_priv = to_i915(dev);
15315
15316 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15317 DRM_INFO("applying pipe a force quirk\n");
15318 }
15319
15320 static void quirk_pipeb_force(struct drm_device *dev)
15321 {
15322 struct drm_i915_private *dev_priv = to_i915(dev);
15323
15324 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15325 DRM_INFO("applying pipe b force quirk\n");
15326 }
15327
15328 /*
15329 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15330 */
15331 static void quirk_ssc_force_disable(struct drm_device *dev)
15332 {
15333 struct drm_i915_private *dev_priv = to_i915(dev);
15334 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15335 DRM_INFO("applying lvds SSC disable quirk\n");
15336 }
15337
15338 /*
15339 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15340 * brightness value
15341 */
15342 static void quirk_invert_brightness(struct drm_device *dev)
15343 {
15344 struct drm_i915_private *dev_priv = to_i915(dev);
15345 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15346 DRM_INFO("applying inverted panel brightness quirk\n");
15347 }
15348
15349 /* Some VBT's incorrectly indicate no backlight is present */
15350 static void quirk_backlight_present(struct drm_device *dev)
15351 {
15352 struct drm_i915_private *dev_priv = to_i915(dev);
15353 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15354 DRM_INFO("applying backlight present quirk\n");
15355 }
15356
15357 struct intel_quirk {
15358 int device;
15359 int subsystem_vendor;
15360 int subsystem_device;
15361 void (*hook)(struct drm_device *dev);
15362 };
15363
15364 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15365 struct intel_dmi_quirk {
15366 void (*hook)(struct drm_device *dev);
15367 const struct dmi_system_id (*dmi_id_list)[];
15368 };
15369
15370 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15371 {
15372 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15373 return 1;
15374 }
15375
15376 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15377 {
15378 .dmi_id_list = &(const struct dmi_system_id[]) {
15379 {
15380 .callback = intel_dmi_reverse_brightness,
15381 .ident = "NCR Corporation",
15382 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15383 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15384 },
15385 },
15386 { } /* terminating entry */
15387 },
15388 .hook = quirk_invert_brightness,
15389 },
15390 };
15391
15392 static struct intel_quirk intel_quirks[] = {
15393 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15394 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15395
15396 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15397 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15398
15399 /* 830 needs to leave pipe A & dpll A up */
15400 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15401
15402 /* 830 needs to leave pipe B & dpll B up */
15403 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15404
15405 /* Lenovo U160 cannot use SSC on LVDS */
15406 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15407
15408 /* Sony Vaio Y cannot use SSC on LVDS */
15409 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15410
15411 /* Acer Aspire 5734Z must invert backlight brightness */
15412 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15413
15414 /* Acer/eMachines G725 */
15415 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15416
15417 /* Acer/eMachines e725 */
15418 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15419
15420 /* Acer/Packard Bell NCL20 */
15421 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15422
15423 /* Acer Aspire 4736Z */
15424 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15425
15426 /* Acer Aspire 5336 */
15427 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15428
15429 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15430 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15431
15432 /* Acer C720 Chromebook (Core i3 4005U) */
15433 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15434
15435 /* Apple Macbook 2,1 (Core 2 T7400) */
15436 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15437
15438 /* Apple Macbook 4,1 */
15439 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15440
15441 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15442 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15443
15444 /* HP Chromebook 14 (Celeron 2955U) */
15445 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15446
15447 /* Dell Chromebook 11 */
15448 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15449
15450 /* Dell Chromebook 11 (2015 version) */
15451 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15452 };
15453
15454 static void intel_init_quirks(struct drm_device *dev)
15455 {
15456 struct pci_dev *d = dev->pdev;
15457 int i;
15458
15459 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15460 struct intel_quirk *q = &intel_quirks[i];
15461
15462 if (d->device == q->device &&
15463 (d->subsystem_vendor == q->subsystem_vendor ||
15464 q->subsystem_vendor == PCI_ANY_ID) &&
15465 (d->subsystem_device == q->subsystem_device ||
15466 q->subsystem_device == PCI_ANY_ID))
15467 q->hook(dev);
15468 }
15469 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15470 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15471 intel_dmi_quirks[i].hook(dev);
15472 }
15473 }
15474
15475 /* Disable the VGA plane that we never use */
15476 static void i915_disable_vga(struct drm_device *dev)
15477 {
15478 struct drm_i915_private *dev_priv = to_i915(dev);
15479 u8 sr1;
15480 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15481
15482 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15483 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15484 outb(SR01, VGA_SR_INDEX);
15485 sr1 = inb(VGA_SR_DATA);
15486 outb(sr1 | 1<<5, VGA_SR_DATA);
15487 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15488 udelay(300);
15489
15490 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15491 POSTING_READ(vga_reg);
15492 }
15493
15494 void intel_modeset_init_hw(struct drm_device *dev)
15495 {
15496 struct drm_i915_private *dev_priv = to_i915(dev);
15497
15498 intel_update_cdclk(dev);
15499
15500 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15501
15502 intel_init_clock_gating(dev);
15503 }
15504
15505 /*
15506 * Calculate what we think the watermarks should be for the state we've read
15507 * out of the hardware and then immediately program those watermarks so that
15508 * we ensure the hardware settings match our internal state.
15509 *
15510 * We can calculate what we think WM's should be by creating a duplicate of the
15511 * current state (which was constructed during hardware readout) and running it
15512 * through the atomic check code to calculate new watermark values in the
15513 * state object.
15514 */
15515 static void sanitize_watermarks(struct drm_device *dev)
15516 {
15517 struct drm_i915_private *dev_priv = to_i915(dev);
15518 struct drm_atomic_state *state;
15519 struct drm_crtc *crtc;
15520 struct drm_crtc_state *cstate;
15521 struct drm_modeset_acquire_ctx ctx;
15522 int ret;
15523 int i;
15524
15525 /* Only supported on platforms that use atomic watermark design */
15526 if (!dev_priv->display.optimize_watermarks)
15527 return;
15528
15529 /*
15530 * We need to hold connection_mutex before calling duplicate_state so
15531 * that the connector loop is protected.
15532 */
15533 drm_modeset_acquire_init(&ctx, 0);
15534 retry:
15535 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15536 if (ret == -EDEADLK) {
15537 drm_modeset_backoff(&ctx);
15538 goto retry;
15539 } else if (WARN_ON(ret)) {
15540 goto fail;
15541 }
15542
15543 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15544 if (WARN_ON(IS_ERR(state)))
15545 goto fail;
15546
15547 /*
15548 * Hardware readout is the only time we don't want to calculate
15549 * intermediate watermarks (since we don't trust the current
15550 * watermarks).
15551 */
15552 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15553
15554 ret = intel_atomic_check(dev, state);
15555 if (ret) {
15556 /*
15557 * If we fail here, it means that the hardware appears to be
15558 * programmed in a way that shouldn't be possible, given our
15559 * understanding of watermark requirements. This might mean a
15560 * mistake in the hardware readout code or a mistake in the
15561 * watermark calculations for a given platform. Raise a WARN
15562 * so that this is noticeable.
15563 *
15564 * If this actually happens, we'll have to just leave the
15565 * BIOS-programmed watermarks untouched and hope for the best.
15566 */
15567 WARN(true, "Could not determine valid watermarks for inherited state\n");
15568 goto fail;
15569 }
15570
15571 /* Write calculated watermark values back */
15572 for_each_crtc_in_state(state, crtc, cstate, i) {
15573 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15574
15575 cs->wm.need_postvbl_update = true;
15576 dev_priv->display.optimize_watermarks(cs);
15577 }
15578
15579 drm_atomic_state_free(state);
15580 fail:
15581 drm_modeset_drop_locks(&ctx);
15582 drm_modeset_acquire_fini(&ctx);
15583 }
15584
15585 void intel_modeset_init(struct drm_device *dev)
15586 {
15587 struct drm_i915_private *dev_priv = to_i915(dev);
15588 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15589 int sprite, ret;
15590 enum pipe pipe;
15591 struct intel_crtc *crtc;
15592
15593 drm_mode_config_init(dev);
15594
15595 dev->mode_config.min_width = 0;
15596 dev->mode_config.min_height = 0;
15597
15598 dev->mode_config.preferred_depth = 24;
15599 dev->mode_config.prefer_shadow = 1;
15600
15601 dev->mode_config.allow_fb_modifiers = true;
15602
15603 dev->mode_config.funcs = &intel_mode_funcs;
15604
15605 intel_init_quirks(dev);
15606
15607 intel_init_pm(dev);
15608
15609 if (INTEL_INFO(dev)->num_pipes == 0)
15610 return;
15611
15612 /*
15613 * There may be no VBT; and if the BIOS enabled SSC we can
15614 * just keep using it to avoid unnecessary flicker. Whereas if the
15615 * BIOS isn't using it, don't assume it will work even if the VBT
15616 * indicates as much.
15617 */
15618 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15619 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15620 DREF_SSC1_ENABLE);
15621
15622 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15623 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15624 bios_lvds_use_ssc ? "en" : "dis",
15625 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15626 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15627 }
15628 }
15629
15630 if (IS_GEN2(dev)) {
15631 dev->mode_config.max_width = 2048;
15632 dev->mode_config.max_height = 2048;
15633 } else if (IS_GEN3(dev)) {
15634 dev->mode_config.max_width = 4096;
15635 dev->mode_config.max_height = 4096;
15636 } else {
15637 dev->mode_config.max_width = 8192;
15638 dev->mode_config.max_height = 8192;
15639 }
15640
15641 if (IS_845G(dev) || IS_I865G(dev)) {
15642 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15643 dev->mode_config.cursor_height = 1023;
15644 } else if (IS_GEN2(dev)) {
15645 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15646 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15647 } else {
15648 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15649 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15650 }
15651
15652 dev->mode_config.fb_base = ggtt->mappable_base;
15653
15654 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15655 INTEL_INFO(dev)->num_pipes,
15656 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15657
15658 for_each_pipe(dev_priv, pipe) {
15659 intel_crtc_init(dev, pipe);
15660 for_each_sprite(dev_priv, pipe, sprite) {
15661 ret = intel_plane_init(dev, pipe, sprite);
15662 if (ret)
15663 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15664 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15665 }
15666 }
15667
15668 intel_update_czclk(dev_priv);
15669 intel_update_cdclk(dev);
15670
15671 intel_shared_dpll_init(dev);
15672
15673 if (dev_priv->max_cdclk_freq == 0)
15674 intel_update_max_cdclk(dev);
15675
15676 /* Just disable it once at startup */
15677 i915_disable_vga(dev);
15678 intel_setup_outputs(dev);
15679
15680 drm_modeset_lock_all(dev);
15681 intel_modeset_setup_hw_state(dev);
15682 drm_modeset_unlock_all(dev);
15683
15684 for_each_intel_crtc(dev, crtc) {
15685 struct intel_initial_plane_config plane_config = {};
15686
15687 if (!crtc->active)
15688 continue;
15689
15690 /*
15691 * Note that reserving the BIOS fb up front prevents us
15692 * from stuffing other stolen allocations like the ring
15693 * on top. This prevents some ugliness at boot time, and
15694 * can even allow for smooth boot transitions if the BIOS
15695 * fb is large enough for the active pipe configuration.
15696 */
15697 dev_priv->display.get_initial_plane_config(crtc,
15698 &plane_config);
15699
15700 /*
15701 * If the fb is shared between multiple heads, we'll
15702 * just get the first one.
15703 */
15704 intel_find_initial_plane_obj(crtc, &plane_config);
15705 }
15706
15707 /*
15708 * Make sure hardware watermarks really match the state we read out.
15709 * Note that we need to do this after reconstructing the BIOS fb's
15710 * since the watermark calculation done here will use pstate->fb.
15711 */
15712 sanitize_watermarks(dev);
15713 }
15714
15715 static void intel_enable_pipe_a(struct drm_device *dev)
15716 {
15717 struct intel_connector *connector;
15718 struct drm_connector *crt = NULL;
15719 struct intel_load_detect_pipe load_detect_temp;
15720 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15721
15722 /* We can't just switch on the pipe A, we need to set things up with a
15723 * proper mode and output configuration. As a gross hack, enable pipe A
15724 * by enabling the load detect pipe once. */
15725 for_each_intel_connector(dev, connector) {
15726 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15727 crt = &connector->base;
15728 break;
15729 }
15730 }
15731
15732 if (!crt)
15733 return;
15734
15735 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15736 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15737 }
15738
15739 static bool
15740 intel_check_plane_mapping(struct intel_crtc *crtc)
15741 {
15742 struct drm_device *dev = crtc->base.dev;
15743 struct drm_i915_private *dev_priv = to_i915(dev);
15744 u32 val;
15745
15746 if (INTEL_INFO(dev)->num_pipes == 1)
15747 return true;
15748
15749 val = I915_READ(DSPCNTR(!crtc->plane));
15750
15751 if ((val & DISPLAY_PLANE_ENABLE) &&
15752 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15753 return false;
15754
15755 return true;
15756 }
15757
15758 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15759 {
15760 struct drm_device *dev = crtc->base.dev;
15761 struct intel_encoder *encoder;
15762
15763 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15764 return true;
15765
15766 return false;
15767 }
15768
15769 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15770 {
15771 struct drm_device *dev = encoder->base.dev;
15772 struct intel_connector *connector;
15773
15774 for_each_connector_on_encoder(dev, &encoder->base, connector)
15775 return true;
15776
15777 return false;
15778 }
15779
15780 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15781 {
15782 struct drm_device *dev = crtc->base.dev;
15783 struct drm_i915_private *dev_priv = to_i915(dev);
15784 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15785
15786 /* Clear any frame start delays used for debugging left by the BIOS */
15787 if (!transcoder_is_dsi(cpu_transcoder)) {
15788 i915_reg_t reg = PIPECONF(cpu_transcoder);
15789
15790 I915_WRITE(reg,
15791 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15792 }
15793
15794 /* restore vblank interrupts to correct state */
15795 drm_crtc_vblank_reset(&crtc->base);
15796 if (crtc->active) {
15797 struct intel_plane *plane;
15798
15799 drm_crtc_vblank_on(&crtc->base);
15800
15801 /* Disable everything but the primary plane */
15802 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15803 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15804 continue;
15805
15806 plane->disable_plane(&plane->base, &crtc->base);
15807 }
15808 }
15809
15810 /* We need to sanitize the plane -> pipe mapping first because this will
15811 * disable the crtc (and hence change the state) if it is wrong. Note
15812 * that gen4+ has a fixed plane -> pipe mapping. */
15813 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15814 bool plane;
15815
15816 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15817 crtc->base.base.id, crtc->base.name);
15818
15819 /* Pipe has the wrong plane attached and the plane is active.
15820 * Temporarily change the plane mapping and disable everything
15821 * ... */
15822 plane = crtc->plane;
15823 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15824 crtc->plane = !plane;
15825 intel_crtc_disable_noatomic(&crtc->base);
15826 crtc->plane = plane;
15827 }
15828
15829 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15830 crtc->pipe == PIPE_A && !crtc->active) {
15831 /* BIOS forgot to enable pipe A, this mostly happens after
15832 * resume. Force-enable the pipe to fix this, the update_dpms
15833 * call below we restore the pipe to the right state, but leave
15834 * the required bits on. */
15835 intel_enable_pipe_a(dev);
15836 }
15837
15838 /* Adjust the state of the output pipe according to whether we
15839 * have active connectors/encoders. */
15840 if (crtc->active && !intel_crtc_has_encoders(crtc))
15841 intel_crtc_disable_noatomic(&crtc->base);
15842
15843 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15844 /*
15845 * We start out with underrun reporting disabled to avoid races.
15846 * For correct bookkeeping mark this on active crtcs.
15847 *
15848 * Also on gmch platforms we dont have any hardware bits to
15849 * disable the underrun reporting. Which means we need to start
15850 * out with underrun reporting disabled also on inactive pipes,
15851 * since otherwise we'll complain about the garbage we read when
15852 * e.g. coming up after runtime pm.
15853 *
15854 * No protection against concurrent access is required - at
15855 * worst a fifo underrun happens which also sets this to false.
15856 */
15857 crtc->cpu_fifo_underrun_disabled = true;
15858 crtc->pch_fifo_underrun_disabled = true;
15859 }
15860 }
15861
15862 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15863 {
15864 struct intel_connector *connector;
15865 struct drm_device *dev = encoder->base.dev;
15866
15867 /* We need to check both for a crtc link (meaning that the
15868 * encoder is active and trying to read from a pipe) and the
15869 * pipe itself being active. */
15870 bool has_active_crtc = encoder->base.crtc &&
15871 to_intel_crtc(encoder->base.crtc)->active;
15872
15873 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15874 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15875 encoder->base.base.id,
15876 encoder->base.name);
15877
15878 /* Connector is active, but has no active pipe. This is
15879 * fallout from our resume register restoring. Disable
15880 * the encoder manually again. */
15881 if (encoder->base.crtc) {
15882 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15883 encoder->base.base.id,
15884 encoder->base.name);
15885 encoder->disable(encoder);
15886 if (encoder->post_disable)
15887 encoder->post_disable(encoder);
15888 }
15889 encoder->base.crtc = NULL;
15890
15891 /* Inconsistent output/port/pipe state happens presumably due to
15892 * a bug in one of the get_hw_state functions. Or someplace else
15893 * in our code, like the register restore mess on resume. Clamp
15894 * things to off as a safer default. */
15895 for_each_intel_connector(dev, connector) {
15896 if (connector->encoder != encoder)
15897 continue;
15898 connector->base.dpms = DRM_MODE_DPMS_OFF;
15899 connector->base.encoder = NULL;
15900 }
15901 }
15902 /* Enabled encoders without active connectors will be fixed in
15903 * the crtc fixup. */
15904 }
15905
15906 void i915_redisable_vga_power_on(struct drm_device *dev)
15907 {
15908 struct drm_i915_private *dev_priv = to_i915(dev);
15909 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15910
15911 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15912 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15913 i915_disable_vga(dev);
15914 }
15915 }
15916
15917 void i915_redisable_vga(struct drm_device *dev)
15918 {
15919 struct drm_i915_private *dev_priv = to_i915(dev);
15920
15921 /* This function can be called both from intel_modeset_setup_hw_state or
15922 * at a very early point in our resume sequence, where the power well
15923 * structures are not yet restored. Since this function is at a very
15924 * paranoid "someone might have enabled VGA while we were not looking"
15925 * level, just check if the power well is enabled instead of trying to
15926 * follow the "don't touch the power well if we don't need it" policy
15927 * the rest of the driver uses. */
15928 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15929 return;
15930
15931 i915_redisable_vga_power_on(dev);
15932
15933 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15934 }
15935
15936 static bool primary_get_hw_state(struct intel_plane *plane)
15937 {
15938 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15939
15940 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15941 }
15942
15943 /* FIXME read out full plane state for all planes */
15944 static void readout_plane_state(struct intel_crtc *crtc)
15945 {
15946 struct drm_plane *primary = crtc->base.primary;
15947 struct intel_plane_state *plane_state =
15948 to_intel_plane_state(primary->state);
15949
15950 plane_state->visible = crtc->active &&
15951 primary_get_hw_state(to_intel_plane(primary));
15952
15953 if (plane_state->visible)
15954 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15955 }
15956
15957 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15958 {
15959 struct drm_i915_private *dev_priv = to_i915(dev);
15960 enum pipe pipe;
15961 struct intel_crtc *crtc;
15962 struct intel_encoder *encoder;
15963 struct intel_connector *connector;
15964 int i;
15965
15966 dev_priv->active_crtcs = 0;
15967
15968 for_each_intel_crtc(dev, crtc) {
15969 struct intel_crtc_state *crtc_state = crtc->config;
15970 int pixclk = 0;
15971
15972 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15973 memset(crtc_state, 0, sizeof(*crtc_state));
15974 crtc_state->base.crtc = &crtc->base;
15975
15976 crtc_state->base.active = crtc_state->base.enable =
15977 dev_priv->display.get_pipe_config(crtc, crtc_state);
15978
15979 crtc->base.enabled = crtc_state->base.enable;
15980 crtc->active = crtc_state->base.active;
15981
15982 if (crtc_state->base.active) {
15983 dev_priv->active_crtcs |= 1 << crtc->pipe;
15984
15985 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15986 pixclk = ilk_pipe_pixel_rate(crtc_state);
15987 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15988 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15989 else
15990 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15991
15992 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15993 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15994 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15995 }
15996
15997 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15998
15999 readout_plane_state(crtc);
16000
16001 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16002 crtc->base.base.id, crtc->base.name,
16003 crtc->active ? "enabled" : "disabled");
16004 }
16005
16006 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16007 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16008
16009 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16010 &pll->config.hw_state);
16011 pll->config.crtc_mask = 0;
16012 for_each_intel_crtc(dev, crtc) {
16013 if (crtc->active && crtc->config->shared_dpll == pll)
16014 pll->config.crtc_mask |= 1 << crtc->pipe;
16015 }
16016 pll->active_mask = pll->config.crtc_mask;
16017
16018 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16019 pll->name, pll->config.crtc_mask, pll->on);
16020 }
16021
16022 for_each_intel_encoder(dev, encoder) {
16023 pipe = 0;
16024
16025 if (encoder->get_hw_state(encoder, &pipe)) {
16026 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16027 encoder->base.crtc = &crtc->base;
16028 crtc->config->output_types |= 1 << encoder->type;
16029 encoder->get_config(encoder, crtc->config);
16030 } else {
16031 encoder->base.crtc = NULL;
16032 }
16033
16034 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16035 encoder->base.base.id,
16036 encoder->base.name,
16037 encoder->base.crtc ? "enabled" : "disabled",
16038 pipe_name(pipe));
16039 }
16040
16041 for_each_intel_connector(dev, connector) {
16042 if (connector->get_hw_state(connector)) {
16043 connector->base.dpms = DRM_MODE_DPMS_ON;
16044
16045 encoder = connector->encoder;
16046 connector->base.encoder = &encoder->base;
16047
16048 if (encoder->base.crtc &&
16049 encoder->base.crtc->state->active) {
16050 /*
16051 * This has to be done during hardware readout
16052 * because anything calling .crtc_disable may
16053 * rely on the connector_mask being accurate.
16054 */
16055 encoder->base.crtc->state->connector_mask |=
16056 1 << drm_connector_index(&connector->base);
16057 encoder->base.crtc->state->encoder_mask |=
16058 1 << drm_encoder_index(&encoder->base);
16059 }
16060
16061 } else {
16062 connector->base.dpms = DRM_MODE_DPMS_OFF;
16063 connector->base.encoder = NULL;
16064 }
16065 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16066 connector->base.base.id,
16067 connector->base.name,
16068 connector->base.encoder ? "enabled" : "disabled");
16069 }
16070
16071 for_each_intel_crtc(dev, crtc) {
16072 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16073
16074 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16075 if (crtc->base.state->active) {
16076 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16077 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16078 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16079
16080 /*
16081 * The initial mode needs to be set in order to keep
16082 * the atomic core happy. It wants a valid mode if the
16083 * crtc's enabled, so we do the above call.
16084 *
16085 * At this point some state updated by the connectors
16086 * in their ->detect() callback has not run yet, so
16087 * no recalculation can be done yet.
16088 *
16089 * Even if we could do a recalculation and modeset
16090 * right now it would cause a double modeset if
16091 * fbdev or userspace chooses a different initial mode.
16092 *
16093 * If that happens, someone indicated they wanted a
16094 * mode change, which means it's safe to do a full
16095 * recalculation.
16096 */
16097 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16098
16099 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16100 update_scanline_offset(crtc);
16101 }
16102
16103 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16104 }
16105 }
16106
16107 /* Scan out the current hw modeset state,
16108 * and sanitizes it to the current state
16109 */
16110 static void
16111 intel_modeset_setup_hw_state(struct drm_device *dev)
16112 {
16113 struct drm_i915_private *dev_priv = to_i915(dev);
16114 enum pipe pipe;
16115 struct intel_crtc *crtc;
16116 struct intel_encoder *encoder;
16117 int i;
16118
16119 intel_modeset_readout_hw_state(dev);
16120
16121 /* HW state is read out, now we need to sanitize this mess. */
16122 for_each_intel_encoder(dev, encoder) {
16123 intel_sanitize_encoder(encoder);
16124 }
16125
16126 for_each_pipe(dev_priv, pipe) {
16127 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16128 intel_sanitize_crtc(crtc);
16129 intel_dump_pipe_config(crtc, crtc->config,
16130 "[setup_hw_state]");
16131 }
16132
16133 intel_modeset_update_connector_atomic_state(dev);
16134
16135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16136 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16137
16138 if (!pll->on || pll->active_mask)
16139 continue;
16140
16141 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16142
16143 pll->funcs.disable(dev_priv, pll);
16144 pll->on = false;
16145 }
16146
16147 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16148 vlv_wm_get_hw_state(dev);
16149 else if (IS_GEN9(dev))
16150 skl_wm_get_hw_state(dev);
16151 else if (HAS_PCH_SPLIT(dev))
16152 ilk_wm_get_hw_state(dev);
16153
16154 for_each_intel_crtc(dev, crtc) {
16155 unsigned long put_domains;
16156
16157 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16158 if (WARN_ON(put_domains))
16159 modeset_put_power_domains(dev_priv, put_domains);
16160 }
16161 intel_display_set_init_power(dev_priv, false);
16162
16163 intel_fbc_init_pipe_state(dev_priv);
16164 }
16165
16166 void intel_display_resume(struct drm_device *dev)
16167 {
16168 struct drm_i915_private *dev_priv = to_i915(dev);
16169 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16170 struct drm_modeset_acquire_ctx ctx;
16171 int ret;
16172 bool setup = false;
16173
16174 dev_priv->modeset_restore_state = NULL;
16175
16176 /*
16177 * This is a cludge because with real atomic modeset mode_config.mutex
16178 * won't be taken. Unfortunately some probed state like
16179 * audio_codec_enable is still protected by mode_config.mutex, so lock
16180 * it here for now.
16181 */
16182 mutex_lock(&dev->mode_config.mutex);
16183 drm_modeset_acquire_init(&ctx, 0);
16184
16185 retry:
16186 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16187
16188 if (ret == 0 && !setup) {
16189 setup = true;
16190
16191 intel_modeset_setup_hw_state(dev);
16192 i915_redisable_vga(dev);
16193 }
16194
16195 if (ret == 0 && state) {
16196 struct drm_crtc_state *crtc_state;
16197 struct drm_crtc *crtc;
16198 int i;
16199
16200 state->acquire_ctx = &ctx;
16201
16202 /* ignore any reset values/BIOS leftovers in the WM registers */
16203 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16204
16205 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16206 /*
16207 * Force recalculation even if we restore
16208 * current state. With fast modeset this may not result
16209 * in a modeset when the state is compatible.
16210 */
16211 crtc_state->mode_changed = true;
16212 }
16213
16214 ret = drm_atomic_commit(state);
16215 }
16216
16217 if (ret == -EDEADLK) {
16218 drm_modeset_backoff(&ctx);
16219 goto retry;
16220 }
16221
16222 drm_modeset_drop_locks(&ctx);
16223 drm_modeset_acquire_fini(&ctx);
16224 mutex_unlock(&dev->mode_config.mutex);
16225
16226 if (ret) {
16227 DRM_ERROR("Restoring old state failed with %i\n", ret);
16228 drm_atomic_state_free(state);
16229 }
16230 }
16231
16232 void intel_modeset_gem_init(struct drm_device *dev)
16233 {
16234 struct drm_i915_private *dev_priv = to_i915(dev);
16235 struct drm_crtc *c;
16236 struct drm_i915_gem_object *obj;
16237 int ret;
16238
16239 intel_init_gt_powersave(dev_priv);
16240
16241 intel_modeset_init_hw(dev);
16242
16243 intel_setup_overlay(dev_priv);
16244
16245 /*
16246 * Make sure any fbs we allocated at startup are properly
16247 * pinned & fenced. When we do the allocation it's too early
16248 * for this.
16249 */
16250 for_each_crtc(dev, c) {
16251 obj = intel_fb_obj(c->primary->fb);
16252 if (obj == NULL)
16253 continue;
16254
16255 mutex_lock(&dev->struct_mutex);
16256 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16257 c->primary->state->rotation);
16258 mutex_unlock(&dev->struct_mutex);
16259 if (ret) {
16260 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16261 to_intel_crtc(c)->pipe);
16262 drm_framebuffer_unreference(c->primary->fb);
16263 c->primary->fb = NULL;
16264 c->primary->crtc = c->primary->state->crtc = NULL;
16265 update_state_fb(c->primary);
16266 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16267 }
16268 }
16269 }
16270
16271 int intel_connector_register(struct drm_connector *connector)
16272 {
16273 struct intel_connector *intel_connector = to_intel_connector(connector);
16274 int ret;
16275
16276 ret = intel_backlight_device_register(intel_connector);
16277 if (ret)
16278 goto err;
16279
16280 return 0;
16281
16282 err:
16283 return ret;
16284 }
16285
16286 void intel_connector_unregister(struct drm_connector *connector)
16287 {
16288 struct intel_connector *intel_connector = to_intel_connector(connector);
16289
16290 intel_backlight_device_unregister(intel_connector);
16291 intel_panel_destroy_backlight(connector);
16292 }
16293
16294 void intel_modeset_cleanup(struct drm_device *dev)
16295 {
16296 struct drm_i915_private *dev_priv = to_i915(dev);
16297
16298 intel_disable_gt_powersave(dev_priv);
16299
16300 /*
16301 * Interrupts and polling as the first thing to avoid creating havoc.
16302 * Too much stuff here (turning of connectors, ...) would
16303 * experience fancy races otherwise.
16304 */
16305 intel_irq_uninstall(dev_priv);
16306
16307 /*
16308 * Due to the hpd irq storm handling the hotplug work can re-arm the
16309 * poll handlers. Hence disable polling after hpd handling is shut down.
16310 */
16311 drm_kms_helper_poll_fini(dev);
16312
16313 intel_unregister_dsm_handler();
16314
16315 intel_fbc_global_disable(dev_priv);
16316
16317 /* flush any delayed tasks or pending work */
16318 flush_scheduled_work();
16319
16320 drm_mode_config_cleanup(dev);
16321
16322 intel_cleanup_overlay(dev_priv);
16323
16324 intel_cleanup_gt_powersave(dev_priv);
16325
16326 intel_teardown_gmbus(dev);
16327 }
16328
16329 void intel_connector_attach_encoder(struct intel_connector *connector,
16330 struct intel_encoder *encoder)
16331 {
16332 connector->encoder = encoder;
16333 drm_mode_connector_attach_encoder(&connector->base,
16334 &encoder->base);
16335 }
16336
16337 /*
16338 * set vga decode state - true == enable VGA decode
16339 */
16340 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16341 {
16342 struct drm_i915_private *dev_priv = to_i915(dev);
16343 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16344 u16 gmch_ctrl;
16345
16346 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16347 DRM_ERROR("failed to read control word\n");
16348 return -EIO;
16349 }
16350
16351 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16352 return 0;
16353
16354 if (state)
16355 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16356 else
16357 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16358
16359 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16360 DRM_ERROR("failed to write control word\n");
16361 return -EIO;
16362 }
16363
16364 return 0;
16365 }
16366
16367 struct intel_display_error_state {
16368
16369 u32 power_well_driver;
16370
16371 int num_transcoders;
16372
16373 struct intel_cursor_error_state {
16374 u32 control;
16375 u32 position;
16376 u32 base;
16377 u32 size;
16378 } cursor[I915_MAX_PIPES];
16379
16380 struct intel_pipe_error_state {
16381 bool power_domain_on;
16382 u32 source;
16383 u32 stat;
16384 } pipe[I915_MAX_PIPES];
16385
16386 struct intel_plane_error_state {
16387 u32 control;
16388 u32 stride;
16389 u32 size;
16390 u32 pos;
16391 u32 addr;
16392 u32 surface;
16393 u32 tile_offset;
16394 } plane[I915_MAX_PIPES];
16395
16396 struct intel_transcoder_error_state {
16397 bool power_domain_on;
16398 enum transcoder cpu_transcoder;
16399
16400 u32 conf;
16401
16402 u32 htotal;
16403 u32 hblank;
16404 u32 hsync;
16405 u32 vtotal;
16406 u32 vblank;
16407 u32 vsync;
16408 } transcoder[4];
16409 };
16410
16411 struct intel_display_error_state *
16412 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16413 {
16414 struct intel_display_error_state *error;
16415 int transcoders[] = {
16416 TRANSCODER_A,
16417 TRANSCODER_B,
16418 TRANSCODER_C,
16419 TRANSCODER_EDP,
16420 };
16421 int i;
16422
16423 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16424 return NULL;
16425
16426 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16427 if (error == NULL)
16428 return NULL;
16429
16430 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16431 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16432
16433 for_each_pipe(dev_priv, i) {
16434 error->pipe[i].power_domain_on =
16435 __intel_display_power_is_enabled(dev_priv,
16436 POWER_DOMAIN_PIPE(i));
16437 if (!error->pipe[i].power_domain_on)
16438 continue;
16439
16440 error->cursor[i].control = I915_READ(CURCNTR(i));
16441 error->cursor[i].position = I915_READ(CURPOS(i));
16442 error->cursor[i].base = I915_READ(CURBASE(i));
16443
16444 error->plane[i].control = I915_READ(DSPCNTR(i));
16445 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16446 if (INTEL_GEN(dev_priv) <= 3) {
16447 error->plane[i].size = I915_READ(DSPSIZE(i));
16448 error->plane[i].pos = I915_READ(DSPPOS(i));
16449 }
16450 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16451 error->plane[i].addr = I915_READ(DSPADDR(i));
16452 if (INTEL_GEN(dev_priv) >= 4) {
16453 error->plane[i].surface = I915_READ(DSPSURF(i));
16454 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16455 }
16456
16457 error->pipe[i].source = I915_READ(PIPESRC(i));
16458
16459 if (HAS_GMCH_DISPLAY(dev_priv))
16460 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16461 }
16462
16463 /* Note: this does not include DSI transcoders. */
16464 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16465 if (HAS_DDI(dev_priv))
16466 error->num_transcoders++; /* Account for eDP. */
16467
16468 for (i = 0; i < error->num_transcoders; i++) {
16469 enum transcoder cpu_transcoder = transcoders[i];
16470
16471 error->transcoder[i].power_domain_on =
16472 __intel_display_power_is_enabled(dev_priv,
16473 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16474 if (!error->transcoder[i].power_domain_on)
16475 continue;
16476
16477 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16478
16479 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16480 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16481 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16482 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16483 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16484 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16485 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16486 }
16487
16488 return error;
16489 }
16490
16491 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16492
16493 void
16494 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16495 struct drm_device *dev,
16496 struct intel_display_error_state *error)
16497 {
16498 struct drm_i915_private *dev_priv = to_i915(dev);
16499 int i;
16500
16501 if (!error)
16502 return;
16503
16504 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16505 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16506 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16507 error->power_well_driver);
16508 for_each_pipe(dev_priv, i) {
16509 err_printf(m, "Pipe [%d]:\n", i);
16510 err_printf(m, " Power: %s\n",
16511 onoff(error->pipe[i].power_domain_on));
16512 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16513 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16514
16515 err_printf(m, "Plane [%d]:\n", i);
16516 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16517 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16518 if (INTEL_INFO(dev)->gen <= 3) {
16519 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16520 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16521 }
16522 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16523 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16524 if (INTEL_INFO(dev)->gen >= 4) {
16525 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16526 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16527 }
16528
16529 err_printf(m, "Cursor [%d]:\n", i);
16530 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16531 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16532 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16533 }
16534
16535 for (i = 0; i < error->num_transcoders; i++) {
16536 err_printf(m, "CPU transcoder: %s\n",
16537 transcoder_name(error->transcoder[i].cpu_transcoder));
16538 err_printf(m, " Power: %s\n",
16539 onoff(error->transcoder[i].power_domain_on));
16540 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16541 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16542 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16543 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16544 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16545 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16546 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16547 }
16548 }
Linux kernel - Deliverables
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