2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 930000, .max
= 1400000 },
94 .n
= { .min
= 3, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 930000, .max
= 1400000 },
107 .n
= { .min
= 3, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 930000, .max
= 1400000 },
120 .n
= { .min
= 3, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv
= {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
320 .vco
= { .min
= 4000000, .max
= 6000000 },
321 .n
= { .min
= 1, .max
= 7 },
322 .m1
= { .min
= 2, .max
= 3 },
323 .m2
= { .min
= 11, .max
= 156 },
324 .p1
= { .min
= 2, .max
= 3 },
325 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
330 clock
->m
= clock
->m1
* clock
->m2
;
331 clock
->p
= clock
->p1
* clock
->p2
;
332 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
333 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
337 * Returns whether any output on the specified pipe is of the specified type
339 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
341 struct drm_device
*dev
= crtc
->dev
;
342 struct intel_encoder
*encoder
;
344 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
345 if (encoder
->type
== type
)
351 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
354 struct drm_device
*dev
= crtc
->dev
;
355 const intel_limit_t
*limit
;
357 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
358 if (intel_is_dual_link_lvds(dev
)) {
359 if (refclk
== 100000)
360 limit
= &intel_limits_ironlake_dual_lvds_100m
;
362 limit
= &intel_limits_ironlake_dual_lvds
;
364 if (refclk
== 100000)
365 limit
= &intel_limits_ironlake_single_lvds_100m
;
367 limit
= &intel_limits_ironlake_single_lvds
;
370 limit
= &intel_limits_ironlake_dac
;
375 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
377 struct drm_device
*dev
= crtc
->dev
;
378 const intel_limit_t
*limit
;
380 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
381 if (intel_is_dual_link_lvds(dev
))
382 limit
= &intel_limits_g4x_dual_channel_lvds
;
384 limit
= &intel_limits_g4x_single_channel_lvds
;
385 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
386 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
387 limit
= &intel_limits_g4x_hdmi
;
388 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
389 limit
= &intel_limits_g4x_sdvo
;
390 } else /* The option is for other outputs */
391 limit
= &intel_limits_i9xx_sdvo
;
396 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
398 struct drm_device
*dev
= crtc
->dev
;
399 const intel_limit_t
*limit
;
401 if (HAS_PCH_SPLIT(dev
))
402 limit
= intel_ironlake_limit(crtc
, refclk
);
403 else if (IS_G4X(dev
)) {
404 limit
= intel_g4x_limit(crtc
);
405 } else if (IS_PINEVIEW(dev
)) {
406 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
407 limit
= &intel_limits_pineview_lvds
;
409 limit
= &intel_limits_pineview_sdvo
;
410 } else if (IS_VALLEYVIEW(dev
)) {
411 limit
= &intel_limits_vlv
;
412 } else if (!IS_GEN2(dev
)) {
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
414 limit
= &intel_limits_i9xx_lvds
;
416 limit
= &intel_limits_i9xx_sdvo
;
418 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
419 limit
= &intel_limits_i8xx_lvds
;
420 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
421 limit
= &intel_limits_i8xx_dvo
;
423 limit
= &intel_limits_i8xx_dac
;
428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
429 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
431 clock
->m
= clock
->m2
+ 2;
432 clock
->p
= clock
->p1
* clock
->p2
;
433 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
434 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
437 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
439 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
442 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
444 clock
->m
= i9xx_dpll_compute_m(clock
);
445 clock
->p
= clock
->p1
* clock
->p2
;
446 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
447 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
450 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
456 static bool intel_PLL_is_valid(struct drm_device
*dev
,
457 const intel_limit_t
*limit
,
458 const intel_clock_t
*clock
)
460 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
461 INTELPllInvalid("n out of range\n");
462 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
463 INTELPllInvalid("p1 out of range\n");
464 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
465 INTELPllInvalid("m2 out of range\n");
466 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
467 INTELPllInvalid("m1 out of range\n");
469 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
470 if (clock
->m1
<= clock
->m2
)
471 INTELPllInvalid("m1 <= m2\n");
473 if (!IS_VALLEYVIEW(dev
)) {
474 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
475 INTELPllInvalid("p out of range\n");
476 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
477 INTELPllInvalid("m out of range\n");
480 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
493 int target
, int refclk
, intel_clock_t
*match_clock
,
494 intel_clock_t
*best_clock
)
496 struct drm_device
*dev
= crtc
->dev
;
500 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev
))
507 clock
.p2
= limit
->p2
.p2_fast
;
509 clock
.p2
= limit
->p2
.p2_slow
;
511 if (target
< limit
->p2
.dot_limit
)
512 clock
.p2
= limit
->p2
.p2_slow
;
514 clock
.p2
= limit
->p2
.p2_fast
;
517 memset(best_clock
, 0, sizeof(*best_clock
));
519 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
521 for (clock
.m2
= limit
->m2
.min
;
522 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
523 if (clock
.m2
>= clock
.m1
)
525 for (clock
.n
= limit
->n
.min
;
526 clock
.n
<= limit
->n
.max
; clock
.n
++) {
527 for (clock
.p1
= limit
->p1
.min
;
528 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
531 i9xx_clock(refclk
, &clock
);
532 if (!intel_PLL_is_valid(dev
, limit
,
536 clock
.p
!= match_clock
->p
)
539 this_err
= abs(clock
.dot
- target
);
540 if (this_err
< err
) {
549 return (err
!= target
);
553 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
554 int target
, int refclk
, intel_clock_t
*match_clock
,
555 intel_clock_t
*best_clock
)
557 struct drm_device
*dev
= crtc
->dev
;
561 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev
))
568 clock
.p2
= limit
->p2
.p2_fast
;
570 clock
.p2
= limit
->p2
.p2_slow
;
572 if (target
< limit
->p2
.dot_limit
)
573 clock
.p2
= limit
->p2
.p2_slow
;
575 clock
.p2
= limit
->p2
.p2_fast
;
578 memset(best_clock
, 0, sizeof(*best_clock
));
580 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
582 for (clock
.m2
= limit
->m2
.min
;
583 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
584 for (clock
.n
= limit
->n
.min
;
585 clock
.n
<= limit
->n
.max
; clock
.n
++) {
586 for (clock
.p1
= limit
->p1
.min
;
587 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
590 pineview_clock(refclk
, &clock
);
591 if (!intel_PLL_is_valid(dev
, limit
,
595 clock
.p
!= match_clock
->p
)
598 this_err
= abs(clock
.dot
- target
);
599 if (this_err
< err
) {
608 return (err
!= target
);
612 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
613 int target
, int refclk
, intel_clock_t
*match_clock
,
614 intel_clock_t
*best_clock
)
616 struct drm_device
*dev
= crtc
->dev
;
620 /* approximately equals target * 0.00585 */
621 int err_most
= (target
>> 8) + (target
>> 9);
624 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
625 if (intel_is_dual_link_lvds(dev
))
626 clock
.p2
= limit
->p2
.p2_fast
;
628 clock
.p2
= limit
->p2
.p2_slow
;
630 if (target
< limit
->p2
.dot_limit
)
631 clock
.p2
= limit
->p2
.p2_slow
;
633 clock
.p2
= limit
->p2
.p2_fast
;
636 memset(best_clock
, 0, sizeof(*best_clock
));
637 max_n
= limit
->n
.max
;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock
.m1
= limit
->m1
.max
;
642 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
643 for (clock
.m2
= limit
->m2
.max
;
644 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
645 for (clock
.p1
= limit
->p1
.max
;
646 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
649 i9xx_clock(refclk
, &clock
);
650 if (!intel_PLL_is_valid(dev
, limit
,
654 this_err
= abs(clock
.dot
- target
);
655 if (this_err
< err_most
) {
669 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
670 int target
, int refclk
, intel_clock_t
*match_clock
,
671 intel_clock_t
*best_clock
)
673 struct drm_device
*dev
= crtc
->dev
;
675 unsigned int bestppm
= 1000000;
676 /* min update 19.2 MHz */
677 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
680 target
*= 5; /* fast clock */
682 memset(best_clock
, 0, sizeof(*best_clock
));
684 /* based on hardware requirement, prefer smaller n to precision */
685 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
686 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
687 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
688 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
689 clock
.p
= clock
.p1
* clock
.p2
;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
692 unsigned int ppm
, diff
;
694 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
697 vlv_clock(refclk
, &clock
);
699 if (!intel_PLL_is_valid(dev
, limit
,
703 diff
= abs(clock
.dot
- target
);
704 ppm
= div_u64(1000000ULL * diff
, target
);
706 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
712 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
725 bool intel_crtc_active(struct drm_crtc
*crtc
)
727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
732 * We can ditch the adjusted_mode.crtc_clock check as soon
733 * as Haswell has gained clock readout/fastboot support.
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
738 return intel_crtc
->active
&& crtc
->fb
&&
739 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
742 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
745 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
748 return intel_crtc
->config
.cpu_transcoder
;
751 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
754 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
756 frame
= I915_READ(frame_reg
);
758 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
763 * intel_wait_for_vblank - wait for vblank on a given pipe
765 * @pipe: pipe to wait for
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
770 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
773 int pipestat_reg
= PIPESTAT(pipe
);
775 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
776 g4x_wait_for_vblank(dev
, pipe
);
780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
793 I915_WRITE(pipestat_reg
,
794 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
796 /* Wait for vblank interrupt bit to set */
797 if (wait_for(I915_READ(pipestat_reg
) &
798 PIPE_VBLANK_INTERRUPT_STATUS
,
800 DRM_DEBUG_KMS("vblank wait timed out\n");
803 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
806 u32 reg
= PIPEDSL(pipe
);
811 line_mask
= DSL_LINEMASK_GEN2
;
813 line_mask
= DSL_LINEMASK_GEN3
;
815 line1
= I915_READ(reg
) & line_mask
;
817 line2
= I915_READ(reg
) & line_mask
;
819 return line1
== line2
;
823 * intel_wait_for_pipe_off - wait for pipe to turn off
825 * @pipe: pipe to wait for
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
832 * wait for the pipe register state bit to turn off
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
839 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
842 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
845 if (INTEL_INFO(dev
)->gen
>= 4) {
846 int reg
= PIPECONF(cpu_transcoder
);
848 /* Wait for the Pipe State to go off */
849 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
851 WARN(1, "pipe_off wait timed out\n");
853 /* Wait for the display line to settle */
854 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
855 WARN(1, "pipe_off wait timed out\n");
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
864 * Returns true if @port is connected, false otherwise.
866 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
867 struct intel_digital_port
*port
)
871 if (HAS_PCH_IBX(dev_priv
->dev
)) {
874 bit
= SDE_PORTB_HOTPLUG
;
877 bit
= SDE_PORTC_HOTPLUG
;
880 bit
= SDE_PORTD_HOTPLUG
;
888 bit
= SDE_PORTB_HOTPLUG_CPT
;
891 bit
= SDE_PORTC_HOTPLUG_CPT
;
894 bit
= SDE_PORTD_HOTPLUG_CPT
;
901 return I915_READ(SDEISR
) & bit
;
904 static const char *state_string(bool enabled
)
906 return enabled
? "on" : "off";
909 /* Only for pre-ILK configs */
910 void assert_pll(struct drm_i915_private
*dev_priv
,
911 enum pipe pipe
, bool state
)
918 val
= I915_READ(reg
);
919 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
920 WARN(cur_state
!= state
,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state
), state_string(cur_state
));
925 /* XXX: the dsi pll is shared between MIPI DSI ports */
926 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
931 mutex_lock(&dev_priv
->dpio_lock
);
932 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
933 mutex_unlock(&dev_priv
->dpio_lock
);
935 cur_state
= val
& DSI_PLL_VCO_EN
;
936 WARN(cur_state
!= state
,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state
), state_string(cur_state
));
940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
943 struct intel_shared_dpll
*
944 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
946 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
948 if (crtc
->config
.shared_dpll
< 0)
951 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
955 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
956 struct intel_shared_dpll
*pll
,
960 struct intel_dpll_hw_state hw_state
;
962 if (HAS_PCH_LPT(dev_priv
->dev
)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
968 "asserting DPLL %s with no DPLL\n", state_string(state
)))
971 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
972 WARN(cur_state
!= state
,
973 "%s assertion failure (expected %s, current %s)\n",
974 pll
->name
, state_string(state
), state_string(cur_state
));
977 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
978 enum pipe pipe
, bool state
)
983 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
986 if (HAS_DDI(dev_priv
->dev
)) {
987 /* DDI does not have a specific FDI_TX register */
988 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
989 val
= I915_READ(reg
);
990 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
992 reg
= FDI_TX_CTL(pipe
);
993 val
= I915_READ(reg
);
994 cur_state
= !!(val
& FDI_TX_ENABLE
);
996 WARN(cur_state
!= state
,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state
), state_string(cur_state
));
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1003 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1004 enum pipe pipe
, bool state
)
1010 reg
= FDI_RX_CTL(pipe
);
1011 val
= I915_READ(reg
);
1012 cur_state
= !!(val
& FDI_RX_ENABLE
);
1013 WARN(cur_state
!= state
,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state
), state_string(cur_state
));
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv
->info
->gen
== 5)
1030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031 if (HAS_DDI(dev_priv
->dev
))
1034 reg
= FDI_TX_CTL(pipe
);
1035 val
= I915_READ(reg
);
1036 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1039 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1040 enum pipe pipe
, bool state
)
1046 reg
= FDI_RX_CTL(pipe
);
1047 val
= I915_READ(reg
);
1048 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1049 WARN(cur_state
!= state
,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state
), state_string(cur_state
));
1054 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1057 int pp_reg
, lvds_reg
;
1059 enum pipe panel_pipe
= PIPE_A
;
1062 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1063 pp_reg
= PCH_PP_CONTROL
;
1064 lvds_reg
= PCH_LVDS
;
1066 pp_reg
= PP_CONTROL
;
1070 val
= I915_READ(pp_reg
);
1071 if (!(val
& PANEL_POWER_ON
) ||
1072 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1075 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1076 panel_pipe
= PIPE_B
;
1078 WARN(panel_pipe
== pipe
&& locked
,
1079 "panel assertion failure, pipe %c regs locked\n",
1083 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1084 enum pipe pipe
, bool state
)
1086 struct drm_device
*dev
= dev_priv
->dev
;
1089 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1090 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1091 else if (IS_845G(dev
) || IS_I865G(dev
))
1092 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1094 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1096 WARN(cur_state
!= state
,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1103 void assert_pipe(struct drm_i915_private
*dev_priv
,
1104 enum pipe pipe
, bool state
)
1109 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1116 if (!intel_display_power_enabled(dev_priv
->dev
,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1120 reg
= PIPECONF(cpu_transcoder
);
1121 val
= I915_READ(reg
);
1122 cur_state
= !!(val
& PIPECONF_ENABLE
);
1125 WARN(cur_state
!= state
,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
1127 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1130 static void assert_plane(struct drm_i915_private
*dev_priv
,
1131 enum plane plane
, bool state
)
1137 reg
= DSPCNTR(plane
);
1138 val
= I915_READ(reg
);
1139 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1140 WARN(cur_state
!= state
,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane
), state_string(state
), state_string(cur_state
));
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1148 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1151 struct drm_device
*dev
= dev_priv
->dev
;
1156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev
)->gen
>= 4) {
1158 reg
= DSPCNTR(pipe
);
1159 val
= I915_READ(reg
);
1160 WARN((val
& DISPLAY_PLANE_ENABLE
),
1161 "plane %c assertion failure, should be disabled but not\n",
1166 /* Need to check both planes against the pipe */
1169 val
= I915_READ(reg
);
1170 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1171 DISPPLANE_SEL_PIPE_SHIFT
;
1172 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i
), pipe_name(pipe
));
1178 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1181 struct drm_device
*dev
= dev_priv
->dev
;
1185 if (IS_VALLEYVIEW(dev
)) {
1186 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1187 reg
= SPCNTR(pipe
, i
);
1188 val
= I915_READ(reg
);
1189 WARN((val
& SP_ENABLE
),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe
, i
), pipe_name(pipe
));
1193 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1195 val
= I915_READ(reg
);
1196 WARN((val
& SPRITE_ENABLE
),
1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198 plane_name(pipe
), pipe_name(pipe
));
1199 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1200 reg
= DVSCNTR(pipe
);
1201 val
= I915_READ(reg
);
1202 WARN((val
& DVS_ENABLE
),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe
), pipe_name(pipe
));
1208 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1213 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1218 val
= I915_READ(PCH_DREF_CONTROL
);
1219 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1220 DREF_SUPERSPREAD_SOURCE_MASK
));
1221 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1231 reg
= PCH_TRANSCONF(pipe
);
1232 val
= I915_READ(reg
);
1233 enabled
= !!(val
& TRANS_ENABLE
);
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1240 enum pipe pipe
, u32 port_sel
, u32 val
)
1242 if ((val
& DP_PORT_EN
) == 0)
1245 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1246 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1247 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1248 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1251 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1257 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1258 enum pipe pipe
, u32 val
)
1260 if ((val
& SDVO_ENABLE
) == 0)
1263 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1264 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1267 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1273 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1274 enum pipe pipe
, u32 val
)
1276 if ((val
& LVDS_PORT_EN
) == 0)
1279 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1280 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1283 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1289 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1290 enum pipe pipe
, u32 val
)
1292 if ((val
& ADPA_DAC_ENABLE
) == 0)
1294 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1295 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1298 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1304 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1305 enum pipe pipe
, int reg
, u32 port_sel
)
1307 u32 val
= I915_READ(reg
);
1308 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310 reg
, pipe_name(pipe
));
1312 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1313 && (val
& DP_PIPEB_SELECT
),
1314 "IBX PCH dp port still using transcoder B\n");
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1318 enum pipe pipe
, int reg
)
1320 u32 val
= I915_READ(reg
);
1321 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323 reg
, pipe_name(pipe
));
1325 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1326 && (val
& SDVO_PIPE_B_SELECT
),
1327 "IBX PCH hdmi port still using transcoder B\n");
1330 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1336 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1337 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1338 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1341 val
= I915_READ(reg
);
1342 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1343 "PCH VGA enabled on transcoder %c, should be disabled\n",
1347 val
= I915_READ(reg
);
1348 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1352 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1353 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1354 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1357 static void intel_init_dpio(struct drm_device
*dev
)
1359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 if (!IS_VALLEYVIEW(dev
))
1364 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1366 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1367 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1368 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1369 * b. The other bits such as sfr settings / modesel may all be set
1372 * This should only be done on init and resume from S3 with both
1373 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1375 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
1378 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1380 struct drm_device
*dev
= crtc
->base
.dev
;
1381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1382 int reg
= DPLL(crtc
->pipe
);
1383 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1385 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1387 /* No really, not for ILK+ */
1388 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1390 /* PLL is protected by panel, make sure we can write it */
1391 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1392 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1394 I915_WRITE(reg
, dpll
);
1398 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1399 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1401 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1402 POSTING_READ(DPLL_MD(crtc
->pipe
));
1404 /* We do this three times for luck */
1405 I915_WRITE(reg
, dpll
);
1407 udelay(150); /* wait for warmup */
1408 I915_WRITE(reg
, dpll
);
1410 udelay(150); /* wait for warmup */
1411 I915_WRITE(reg
, dpll
);
1413 udelay(150); /* wait for warmup */
1416 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1418 struct drm_device
*dev
= crtc
->base
.dev
;
1419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1420 int reg
= DPLL(crtc
->pipe
);
1421 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1423 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1425 /* No really, not for ILK+ */
1426 BUG_ON(dev_priv
->info
->gen
>= 5);
1428 /* PLL is protected by panel, make sure we can write it */
1429 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1430 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1432 I915_WRITE(reg
, dpll
);
1434 /* Wait for the clocks to stabilize. */
1438 if (INTEL_INFO(dev
)->gen
>= 4) {
1439 I915_WRITE(DPLL_MD(crtc
->pipe
),
1440 crtc
->config
.dpll_hw_state
.dpll_md
);
1442 /* The pixel multiplier can only be updated once the
1443 * DPLL is enabled and the clocks are stable.
1445 * So write it again.
1447 I915_WRITE(reg
, dpll
);
1450 /* We do this three times for luck */
1451 I915_WRITE(reg
, dpll
);
1453 udelay(150); /* wait for warmup */
1454 I915_WRITE(reg
, dpll
);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg
, dpll
);
1459 udelay(150); /* wait for warmup */
1463 * i9xx_disable_pll - disable a PLL
1464 * @dev_priv: i915 private structure
1465 * @pipe: pipe PLL to disable
1467 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 * Note! This is for pre-ILK only.
1471 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1473 /* Don't disable pipe A or pipe A PLLs if needed */
1474 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1477 /* Make sure the pipe isn't still relying on us */
1478 assert_pipe_disabled(dev_priv
, pipe
);
1480 I915_WRITE(DPLL(pipe
), 0);
1481 POSTING_READ(DPLL(pipe
));
1484 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1488 /* Make sure the pipe isn't still relying on us */
1489 assert_pipe_disabled(dev_priv
, pipe
);
1491 /* Leave integrated clock source enabled */
1493 val
= DPLL_INTEGRATED_CRI_CLK_VLV
;
1494 I915_WRITE(DPLL(pipe
), val
);
1495 POSTING_READ(DPLL(pipe
));
1498 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1499 struct intel_digital_port
*dport
)
1503 switch (dport
->port
) {
1505 port_mask
= DPLL_PORTB_READY_MASK
;
1508 port_mask
= DPLL_PORTC_READY_MASK
;
1514 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1515 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1516 'B' + dport
->port
, I915_READ(DPLL(0)));
1520 * ironlake_enable_shared_dpll - enable PCH PLL
1521 * @dev_priv: i915 private structure
1522 * @pipe: pipe PLL to enable
1524 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1525 * drives the transcoder clock.
1527 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1529 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1530 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1532 /* PCH PLLs only available on ILK, SNB and IVB */
1533 BUG_ON(dev_priv
->info
->gen
< 5);
1534 if (WARN_ON(pll
== NULL
))
1537 if (WARN_ON(pll
->refcount
== 0))
1540 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1541 pll
->name
, pll
->active
, pll
->on
,
1542 crtc
->base
.base
.id
);
1544 if (pll
->active
++) {
1546 assert_shared_dpll_enabled(dev_priv
, pll
);
1551 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1552 pll
->enable(dev_priv
, pll
);
1556 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1558 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1559 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1561 /* PCH only available on ILK+ */
1562 BUG_ON(dev_priv
->info
->gen
< 5);
1563 if (WARN_ON(pll
== NULL
))
1566 if (WARN_ON(pll
->refcount
== 0))
1569 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1570 pll
->name
, pll
->active
, pll
->on
,
1571 crtc
->base
.base
.id
);
1573 if (WARN_ON(pll
->active
== 0)) {
1574 assert_shared_dpll_disabled(dev_priv
, pll
);
1578 assert_shared_dpll_enabled(dev_priv
, pll
);
1583 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1584 pll
->disable(dev_priv
, pll
);
1588 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1591 struct drm_device
*dev
= dev_priv
->dev
;
1592 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1593 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1594 uint32_t reg
, val
, pipeconf_val
;
1596 /* PCH only available on ILK+ */
1597 BUG_ON(dev_priv
->info
->gen
< 5);
1599 /* Make sure PCH DPLL is enabled */
1600 assert_shared_dpll_enabled(dev_priv
,
1601 intel_crtc_to_shared_dpll(intel_crtc
));
1603 /* FDI must be feeding us bits for PCH ports */
1604 assert_fdi_tx_enabled(dev_priv
, pipe
);
1605 assert_fdi_rx_enabled(dev_priv
, pipe
);
1607 if (HAS_PCH_CPT(dev
)) {
1608 /* Workaround: Set the timing override bit before enabling the
1609 * pch transcoder. */
1610 reg
= TRANS_CHICKEN2(pipe
);
1611 val
= I915_READ(reg
);
1612 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1613 I915_WRITE(reg
, val
);
1616 reg
= PCH_TRANSCONF(pipe
);
1617 val
= I915_READ(reg
);
1618 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1620 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1622 * make the BPC in transcoder be consistent with
1623 * that in pipeconf reg.
1625 val
&= ~PIPECONF_BPC_MASK
;
1626 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1629 val
&= ~TRANS_INTERLACE_MASK
;
1630 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1631 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1632 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1633 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1635 val
|= TRANS_INTERLACED
;
1637 val
|= TRANS_PROGRESSIVE
;
1639 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1640 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1641 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1644 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1645 enum transcoder cpu_transcoder
)
1647 u32 val
, pipeconf_val
;
1649 /* PCH only available on ILK+ */
1650 BUG_ON(dev_priv
->info
->gen
< 5);
1652 /* FDI must be feeding us bits for PCH ports */
1653 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1654 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1656 /* Workaround: set timing override bit. */
1657 val
= I915_READ(_TRANSA_CHICKEN2
);
1658 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1659 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1662 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1664 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1665 PIPECONF_INTERLACED_ILK
)
1666 val
|= TRANS_INTERLACED
;
1668 val
|= TRANS_PROGRESSIVE
;
1670 I915_WRITE(LPT_TRANSCONF
, val
);
1671 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1672 DRM_ERROR("Failed to enable PCH transcoder\n");
1675 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1678 struct drm_device
*dev
= dev_priv
->dev
;
1681 /* FDI relies on the transcoder */
1682 assert_fdi_tx_disabled(dev_priv
, pipe
);
1683 assert_fdi_rx_disabled(dev_priv
, pipe
);
1685 /* Ports must be off as well */
1686 assert_pch_ports_disabled(dev_priv
, pipe
);
1688 reg
= PCH_TRANSCONF(pipe
);
1689 val
= I915_READ(reg
);
1690 val
&= ~TRANS_ENABLE
;
1691 I915_WRITE(reg
, val
);
1692 /* wait for PCH transcoder off, transcoder state */
1693 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1694 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1696 if (!HAS_PCH_IBX(dev
)) {
1697 /* Workaround: Clear the timing override chicken bit again. */
1698 reg
= TRANS_CHICKEN2(pipe
);
1699 val
= I915_READ(reg
);
1700 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1701 I915_WRITE(reg
, val
);
1705 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1709 val
= I915_READ(LPT_TRANSCONF
);
1710 val
&= ~TRANS_ENABLE
;
1711 I915_WRITE(LPT_TRANSCONF
, val
);
1712 /* wait for PCH transcoder off, transcoder state */
1713 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1714 DRM_ERROR("Failed to disable PCH transcoder\n");
1716 /* Workaround: clear timing override bit. */
1717 val
= I915_READ(_TRANSA_CHICKEN2
);
1718 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1719 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1723 * intel_enable_pipe - enable a pipe, asserting requirements
1724 * @dev_priv: i915 private structure
1725 * @pipe: pipe to enable
1726 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1728 * Enable @pipe, making sure that various hardware specific requirements
1729 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1731 * @pipe should be %PIPE_A or %PIPE_B.
1733 * Will wait until the pipe is actually running (i.e. first vblank) before
1736 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1737 bool pch_port
, bool dsi
)
1739 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1741 enum pipe pch_transcoder
;
1745 assert_planes_disabled(dev_priv
, pipe
);
1746 assert_cursor_disabled(dev_priv
, pipe
);
1747 assert_sprites_disabled(dev_priv
, pipe
);
1749 if (HAS_PCH_LPT(dev_priv
->dev
))
1750 pch_transcoder
= TRANSCODER_A
;
1752 pch_transcoder
= pipe
;
1755 * A pipe without a PLL won't actually be able to drive bits from
1756 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1759 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1761 assert_dsi_pll_enabled(dev_priv
);
1763 assert_pll_enabled(dev_priv
, pipe
);
1766 /* if driving the PCH, we need FDI enabled */
1767 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1768 assert_fdi_tx_pll_enabled(dev_priv
,
1769 (enum pipe
) cpu_transcoder
);
1771 /* FIXME: assert CPU port conditions for SNB+ */
1774 reg
= PIPECONF(cpu_transcoder
);
1775 val
= I915_READ(reg
);
1776 if (val
& PIPECONF_ENABLE
)
1779 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1780 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1784 * intel_disable_pipe - disable a pipe, asserting requirements
1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to disable
1788 * Disable @pipe, making sure that various hardware specific requirements
1789 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1791 * @pipe should be %PIPE_A or %PIPE_B.
1793 * Will wait until the pipe has shut down before returning.
1795 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1798 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1804 * Make sure planes won't keep trying to pump pixels to us,
1805 * or we might hang the display.
1807 assert_planes_disabled(dev_priv
, pipe
);
1808 assert_cursor_disabled(dev_priv
, pipe
);
1809 assert_sprites_disabled(dev_priv
, pipe
);
1811 /* Don't disable pipe A or pipe A PLLs if needed */
1812 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1815 reg
= PIPECONF(cpu_transcoder
);
1816 val
= I915_READ(reg
);
1817 if ((val
& PIPECONF_ENABLE
) == 0)
1820 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1821 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1825 * Plane regs are double buffered, going from enabled->disabled needs a
1826 * trigger in order to latch. The display address reg provides this.
1828 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1831 u32 reg
= dev_priv
->info
->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
1833 I915_WRITE(reg
, I915_READ(reg
));
1838 * intel_enable_primary_plane - enable the primary plane on a given pipe
1839 * @dev_priv: i915 private structure
1840 * @plane: plane to enable
1841 * @pipe: pipe being fed
1843 * Enable @plane on @pipe, making sure that @pipe is running first.
1845 static void intel_enable_primary_plane(struct drm_i915_private
*dev_priv
,
1846 enum plane plane
, enum pipe pipe
)
1848 struct intel_crtc
*intel_crtc
=
1849 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1853 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1854 assert_pipe_enabled(dev_priv
, pipe
);
1856 WARN(intel_crtc
->primary_enabled
, "Primary plane already enabled\n");
1858 intel_crtc
->primary_enabled
= true;
1860 reg
= DSPCNTR(plane
);
1861 val
= I915_READ(reg
);
1862 if (val
& DISPLAY_PLANE_ENABLE
)
1865 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1866 intel_flush_primary_plane(dev_priv
, plane
);
1867 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1871 * intel_disable_primary_plane - disable the primary plane
1872 * @dev_priv: i915 private structure
1873 * @plane: plane to disable
1874 * @pipe: pipe consuming the data
1876 * Disable @plane; should be an independent operation.
1878 static void intel_disable_primary_plane(struct drm_i915_private
*dev_priv
,
1879 enum plane plane
, enum pipe pipe
)
1881 struct intel_crtc
*intel_crtc
=
1882 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1886 WARN(!intel_crtc
->primary_enabled
, "Primary plane already disabled\n");
1888 intel_crtc
->primary_enabled
= false;
1890 reg
= DSPCNTR(plane
);
1891 val
= I915_READ(reg
);
1892 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1895 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1896 intel_flush_primary_plane(dev_priv
, plane
);
1897 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1900 static bool need_vtd_wa(struct drm_device
*dev
)
1902 #ifdef CONFIG_INTEL_IOMMU
1903 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1910 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1911 struct drm_i915_gem_object
*obj
,
1912 struct intel_ring_buffer
*pipelined
)
1914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1918 switch (obj
->tiling_mode
) {
1919 case I915_TILING_NONE
:
1920 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1921 alignment
= 128 * 1024;
1922 else if (INTEL_INFO(dev
)->gen
>= 4)
1923 alignment
= 4 * 1024;
1925 alignment
= 64 * 1024;
1928 /* pin() will align the object as required by fence */
1932 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1938 /* Note that the w/a also requires 64 PTE of padding following the
1939 * bo. We currently fill all unused PTE with the shadow page and so
1940 * we should always have valid PTE following the scanout preventing
1943 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1944 alignment
= 256 * 1024;
1946 dev_priv
->mm
.interruptible
= false;
1947 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1949 goto err_interruptible
;
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1956 ret
= i915_gem_object_get_fence(obj
);
1960 i915_gem_object_pin_fence(obj
);
1962 dev_priv
->mm
.interruptible
= true;
1966 i915_gem_object_unpin_from_display_plane(obj
);
1968 dev_priv
->mm
.interruptible
= true;
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1974 i915_gem_object_unpin_fence(obj
);
1975 i915_gem_object_unpin_from_display_plane(obj
);
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1981 unsigned int tiling_mode
,
1985 if (tiling_mode
!= I915_TILING_NONE
) {
1986 unsigned int tile_rows
, tiles
;
1991 tiles
= *x
/ (512/cpp
);
1994 return tile_rows
* pitch
* 8 + tiles
* 4096;
1996 unsigned int offset
;
1998 offset
= *y
* pitch
+ *x
* cpp
;
2000 *x
= (offset
& 4095) / cpp
;
2001 return offset
& -4096;
2005 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2008 struct drm_device
*dev
= crtc
->dev
;
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2011 struct intel_framebuffer
*intel_fb
;
2012 struct drm_i915_gem_object
*obj
;
2013 int plane
= intel_crtc
->plane
;
2014 unsigned long linear_offset
;
2023 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2027 intel_fb
= to_intel_framebuffer(fb
);
2028 obj
= intel_fb
->obj
;
2030 reg
= DSPCNTR(plane
);
2031 dspcntr
= I915_READ(reg
);
2032 /* Mask out pixel format bits in case we change it */
2033 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2034 switch (fb
->pixel_format
) {
2036 dspcntr
|= DISPPLANE_8BPP
;
2038 case DRM_FORMAT_XRGB1555
:
2039 case DRM_FORMAT_ARGB1555
:
2040 dspcntr
|= DISPPLANE_BGRX555
;
2042 case DRM_FORMAT_RGB565
:
2043 dspcntr
|= DISPPLANE_BGRX565
;
2045 case DRM_FORMAT_XRGB8888
:
2046 case DRM_FORMAT_ARGB8888
:
2047 dspcntr
|= DISPPLANE_BGRX888
;
2049 case DRM_FORMAT_XBGR8888
:
2050 case DRM_FORMAT_ABGR8888
:
2051 dspcntr
|= DISPPLANE_RGBX888
;
2053 case DRM_FORMAT_XRGB2101010
:
2054 case DRM_FORMAT_ARGB2101010
:
2055 dspcntr
|= DISPPLANE_BGRX101010
;
2057 case DRM_FORMAT_XBGR2101010
:
2058 case DRM_FORMAT_ABGR2101010
:
2059 dspcntr
|= DISPPLANE_RGBX101010
;
2065 if (INTEL_INFO(dev
)->gen
>= 4) {
2066 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2067 dspcntr
|= DISPPLANE_TILED
;
2069 dspcntr
&= ~DISPPLANE_TILED
;
2073 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2075 I915_WRITE(reg
, dspcntr
);
2077 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2079 if (INTEL_INFO(dev
)->gen
>= 4) {
2080 intel_crtc
->dspaddr_offset
=
2081 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2082 fb
->bits_per_pixel
/ 8,
2084 linear_offset
-= intel_crtc
->dspaddr_offset
;
2086 intel_crtc
->dspaddr_offset
= linear_offset
;
2089 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2090 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2092 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2093 if (INTEL_INFO(dev
)->gen
>= 4) {
2094 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2095 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2096 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2097 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2099 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2105 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2106 struct drm_framebuffer
*fb
, int x
, int y
)
2108 struct drm_device
*dev
= crtc
->dev
;
2109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2110 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2111 struct intel_framebuffer
*intel_fb
;
2112 struct drm_i915_gem_object
*obj
;
2113 int plane
= intel_crtc
->plane
;
2114 unsigned long linear_offset
;
2124 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2128 intel_fb
= to_intel_framebuffer(fb
);
2129 obj
= intel_fb
->obj
;
2131 reg
= DSPCNTR(plane
);
2132 dspcntr
= I915_READ(reg
);
2133 /* Mask out pixel format bits in case we change it */
2134 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2135 switch (fb
->pixel_format
) {
2137 dspcntr
|= DISPPLANE_8BPP
;
2139 case DRM_FORMAT_RGB565
:
2140 dspcntr
|= DISPPLANE_BGRX565
;
2142 case DRM_FORMAT_XRGB8888
:
2143 case DRM_FORMAT_ARGB8888
:
2144 dspcntr
|= DISPPLANE_BGRX888
;
2146 case DRM_FORMAT_XBGR8888
:
2147 case DRM_FORMAT_ABGR8888
:
2148 dspcntr
|= DISPPLANE_RGBX888
;
2150 case DRM_FORMAT_XRGB2101010
:
2151 case DRM_FORMAT_ARGB2101010
:
2152 dspcntr
|= DISPPLANE_BGRX101010
;
2154 case DRM_FORMAT_XBGR2101010
:
2155 case DRM_FORMAT_ABGR2101010
:
2156 dspcntr
|= DISPPLANE_RGBX101010
;
2162 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2163 dspcntr
|= DISPPLANE_TILED
;
2165 dspcntr
&= ~DISPPLANE_TILED
;
2167 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2168 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2170 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2172 I915_WRITE(reg
, dspcntr
);
2174 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2175 intel_crtc
->dspaddr_offset
=
2176 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2177 fb
->bits_per_pixel
/ 8,
2179 linear_offset
-= intel_crtc
->dspaddr_offset
;
2181 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2182 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2184 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2185 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2186 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2187 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2188 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2190 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2191 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2198 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2200 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2201 int x
, int y
, enum mode_set_atomic state
)
2203 struct drm_device
*dev
= crtc
->dev
;
2204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2206 if (dev_priv
->display
.disable_fbc
)
2207 dev_priv
->display
.disable_fbc(dev
);
2208 intel_increase_pllclock(crtc
);
2210 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2213 void intel_display_handle_reset(struct drm_device
*dev
)
2215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2216 struct drm_crtc
*crtc
;
2219 * Flips in the rings have been nuked by the reset,
2220 * so complete all pending flips so that user space
2221 * will get its events and not get stuck.
2223 * Also update the base address of all primary
2224 * planes to the the last fb to make sure we're
2225 * showing the correct fb after a reset.
2227 * Need to make two loops over the crtcs so that we
2228 * don't try to grab a crtc mutex before the
2229 * pending_flip_queue really got woken up.
2232 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2233 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2234 enum plane plane
= intel_crtc
->plane
;
2236 intel_prepare_page_flip(dev
, plane
);
2237 intel_finish_page_flip_plane(dev
, plane
);
2240 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2243 mutex_lock(&crtc
->mutex
);
2244 if (intel_crtc
->active
)
2245 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2247 mutex_unlock(&crtc
->mutex
);
2252 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2254 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2255 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2256 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2259 /* Big Hammer, we also need to ensure that any pending
2260 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2261 * current scanout is retired before unpinning the old
2264 * This should only fail upon a hung GPU, in which case we
2265 * can safely continue.
2267 dev_priv
->mm
.interruptible
= false;
2268 ret
= i915_gem_object_finish_gpu(obj
);
2269 dev_priv
->mm
.interruptible
= was_interruptible
;
2274 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2276 struct drm_device
*dev
= crtc
->dev
;
2277 struct drm_i915_master_private
*master_priv
;
2278 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2280 if (!dev
->primary
->master
)
2283 master_priv
= dev
->primary
->master
->driver_priv
;
2284 if (!master_priv
->sarea_priv
)
2287 switch (intel_crtc
->pipe
) {
2289 master_priv
->sarea_priv
->pipeA_x
= x
;
2290 master_priv
->sarea_priv
->pipeA_y
= y
;
2293 master_priv
->sarea_priv
->pipeB_x
= x
;
2294 master_priv
->sarea_priv
->pipeB_y
= y
;
2302 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2303 struct drm_framebuffer
*fb
)
2305 struct drm_device
*dev
= crtc
->dev
;
2306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2307 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2308 struct drm_framebuffer
*old_fb
;
2313 DRM_ERROR("No FB bound\n");
2317 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2318 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2319 plane_name(intel_crtc
->plane
),
2320 INTEL_INFO(dev
)->num_pipes
);
2324 mutex_lock(&dev
->struct_mutex
);
2325 ret
= intel_pin_and_fence_fb_obj(dev
,
2326 to_intel_framebuffer(fb
)->obj
,
2329 mutex_unlock(&dev
->struct_mutex
);
2330 DRM_ERROR("pin & fence failed\n");
2335 * Update pipe size and adjust fitter if needed: the reason for this is
2336 * that in compute_mode_changes we check the native mode (not the pfit
2337 * mode) to see if we can flip rather than do a full mode set. In the
2338 * fastboot case, we'll flip, but if we don't update the pipesrc and
2339 * pfit state, we'll end up with a big fb scanned out into the wrong
2342 * To fix this properly, we need to hoist the checks up into
2343 * compute_mode_changes (or above), check the actual pfit state and
2344 * whether the platform allows pfit disable with pipe active, and only
2345 * then update the pipesrc and pfit state, even on the flip path.
2347 if (i915_fastboot
) {
2348 const struct drm_display_mode
*adjusted_mode
=
2349 &intel_crtc
->config
.adjusted_mode
;
2351 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2352 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2353 (adjusted_mode
->crtc_vdisplay
- 1));
2354 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2355 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2356 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2357 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2358 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2359 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2363 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2365 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2366 mutex_unlock(&dev
->struct_mutex
);
2367 DRM_ERROR("failed to update base address\n");
2377 if (intel_crtc
->active
&& old_fb
!= fb
)
2378 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2379 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2382 intel_update_fbc(dev
);
2383 intel_edp_psr_update(dev
);
2384 mutex_unlock(&dev
->struct_mutex
);
2386 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2391 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2393 struct drm_device
*dev
= crtc
->dev
;
2394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2395 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2396 int pipe
= intel_crtc
->pipe
;
2399 /* enable normal train */
2400 reg
= FDI_TX_CTL(pipe
);
2401 temp
= I915_READ(reg
);
2402 if (IS_IVYBRIDGE(dev
)) {
2403 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2404 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2406 temp
&= ~FDI_LINK_TRAIN_NONE
;
2407 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2409 I915_WRITE(reg
, temp
);
2411 reg
= FDI_RX_CTL(pipe
);
2412 temp
= I915_READ(reg
);
2413 if (HAS_PCH_CPT(dev
)) {
2414 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2415 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2417 temp
&= ~FDI_LINK_TRAIN_NONE
;
2418 temp
|= FDI_LINK_TRAIN_NONE
;
2420 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2422 /* wait one idle pattern time */
2426 /* IVB wants error correction enabled */
2427 if (IS_IVYBRIDGE(dev
))
2428 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2429 FDI_FE_ERRC_ENABLE
);
2432 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2434 return crtc
->base
.enabled
&& crtc
->active
&&
2435 crtc
->config
.has_pch_encoder
;
2438 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2441 struct intel_crtc
*pipe_B_crtc
=
2442 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2443 struct intel_crtc
*pipe_C_crtc
=
2444 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2448 * When everything is off disable fdi C so that we could enable fdi B
2449 * with all lanes. Note that we don't care about enabled pipes without
2450 * an enabled pch encoder.
2452 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2453 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2454 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2455 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2457 temp
= I915_READ(SOUTH_CHICKEN1
);
2458 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2459 DRM_DEBUG_KMS("disabling fdi C rx\n");
2460 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2464 /* The FDI link training functions for ILK/Ibexpeak. */
2465 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2467 struct drm_device
*dev
= crtc
->dev
;
2468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2469 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2470 int pipe
= intel_crtc
->pipe
;
2471 int plane
= intel_crtc
->plane
;
2472 u32 reg
, temp
, tries
;
2474 /* FDI needs bits from pipe & plane first */
2475 assert_pipe_enabled(dev_priv
, pipe
);
2476 assert_plane_enabled(dev_priv
, plane
);
2478 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480 reg
= FDI_RX_IMR(pipe
);
2481 temp
= I915_READ(reg
);
2482 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2483 temp
&= ~FDI_RX_BIT_LOCK
;
2484 I915_WRITE(reg
, temp
);
2488 /* enable CPU FDI TX and PCH FDI RX */
2489 reg
= FDI_TX_CTL(pipe
);
2490 temp
= I915_READ(reg
);
2491 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2492 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2493 temp
&= ~FDI_LINK_TRAIN_NONE
;
2494 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2495 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2497 reg
= FDI_RX_CTL(pipe
);
2498 temp
= I915_READ(reg
);
2499 temp
&= ~FDI_LINK_TRAIN_NONE
;
2500 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2501 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2506 /* Ironlake workaround, enable clock pointer after FDI enable*/
2507 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2508 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2509 FDI_RX_PHASE_SYNC_POINTER_EN
);
2511 reg
= FDI_RX_IIR(pipe
);
2512 for (tries
= 0; tries
< 5; tries
++) {
2513 temp
= I915_READ(reg
);
2514 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2516 if ((temp
& FDI_RX_BIT_LOCK
)) {
2517 DRM_DEBUG_KMS("FDI train 1 done.\n");
2518 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2523 DRM_ERROR("FDI train 1 fail!\n");
2526 reg
= FDI_TX_CTL(pipe
);
2527 temp
= I915_READ(reg
);
2528 temp
&= ~FDI_LINK_TRAIN_NONE
;
2529 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2530 I915_WRITE(reg
, temp
);
2532 reg
= FDI_RX_CTL(pipe
);
2533 temp
= I915_READ(reg
);
2534 temp
&= ~FDI_LINK_TRAIN_NONE
;
2535 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2536 I915_WRITE(reg
, temp
);
2541 reg
= FDI_RX_IIR(pipe
);
2542 for (tries
= 0; tries
< 5; tries
++) {
2543 temp
= I915_READ(reg
);
2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2546 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2547 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2548 DRM_DEBUG_KMS("FDI train 2 done.\n");
2553 DRM_ERROR("FDI train 2 fail!\n");
2555 DRM_DEBUG_KMS("FDI train done\n");
2559 static const int snb_b_fdi_train_param
[] = {
2560 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2561 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2562 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2563 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2566 /* The FDI link training functions for SNB/Cougarpoint. */
2567 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2569 struct drm_device
*dev
= crtc
->dev
;
2570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2571 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2572 int pipe
= intel_crtc
->pipe
;
2573 u32 reg
, temp
, i
, retry
;
2575 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2577 reg
= FDI_RX_IMR(pipe
);
2578 temp
= I915_READ(reg
);
2579 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2580 temp
&= ~FDI_RX_BIT_LOCK
;
2581 I915_WRITE(reg
, temp
);
2586 /* enable CPU FDI TX and PCH FDI RX */
2587 reg
= FDI_TX_CTL(pipe
);
2588 temp
= I915_READ(reg
);
2589 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2590 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2591 temp
&= ~FDI_LINK_TRAIN_NONE
;
2592 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2593 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2595 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2596 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2598 I915_WRITE(FDI_RX_MISC(pipe
),
2599 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2601 reg
= FDI_RX_CTL(pipe
);
2602 temp
= I915_READ(reg
);
2603 if (HAS_PCH_CPT(dev
)) {
2604 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2605 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2607 temp
&= ~FDI_LINK_TRAIN_NONE
;
2608 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2610 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2615 for (i
= 0; i
< 4; i
++) {
2616 reg
= FDI_TX_CTL(pipe
);
2617 temp
= I915_READ(reg
);
2618 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2619 temp
|= snb_b_fdi_train_param
[i
];
2620 I915_WRITE(reg
, temp
);
2625 for (retry
= 0; retry
< 5; retry
++) {
2626 reg
= FDI_RX_IIR(pipe
);
2627 temp
= I915_READ(reg
);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2629 if (temp
& FDI_RX_BIT_LOCK
) {
2630 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2631 DRM_DEBUG_KMS("FDI train 1 done.\n");
2640 DRM_ERROR("FDI train 1 fail!\n");
2643 reg
= FDI_TX_CTL(pipe
);
2644 temp
= I915_READ(reg
);
2645 temp
&= ~FDI_LINK_TRAIN_NONE
;
2646 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2648 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2650 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2652 I915_WRITE(reg
, temp
);
2654 reg
= FDI_RX_CTL(pipe
);
2655 temp
= I915_READ(reg
);
2656 if (HAS_PCH_CPT(dev
)) {
2657 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2658 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2660 temp
&= ~FDI_LINK_TRAIN_NONE
;
2661 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2663 I915_WRITE(reg
, temp
);
2668 for (i
= 0; i
< 4; i
++) {
2669 reg
= FDI_TX_CTL(pipe
);
2670 temp
= I915_READ(reg
);
2671 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2672 temp
|= snb_b_fdi_train_param
[i
];
2673 I915_WRITE(reg
, temp
);
2678 for (retry
= 0; retry
< 5; retry
++) {
2679 reg
= FDI_RX_IIR(pipe
);
2680 temp
= I915_READ(reg
);
2681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2682 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2683 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2684 DRM_DEBUG_KMS("FDI train 2 done.\n");
2693 DRM_ERROR("FDI train 2 fail!\n");
2695 DRM_DEBUG_KMS("FDI train done.\n");
2698 /* Manual link training for Ivy Bridge A0 parts */
2699 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2701 struct drm_device
*dev
= crtc
->dev
;
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2703 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2704 int pipe
= intel_crtc
->pipe
;
2705 u32 reg
, temp
, i
, j
;
2707 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2709 reg
= FDI_RX_IMR(pipe
);
2710 temp
= I915_READ(reg
);
2711 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2712 temp
&= ~FDI_RX_BIT_LOCK
;
2713 I915_WRITE(reg
, temp
);
2718 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2719 I915_READ(FDI_RX_IIR(pipe
)));
2721 /* Try each vswing and preemphasis setting twice before moving on */
2722 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2723 /* disable first in case we need to retry */
2724 reg
= FDI_TX_CTL(pipe
);
2725 temp
= I915_READ(reg
);
2726 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2727 temp
&= ~FDI_TX_ENABLE
;
2728 I915_WRITE(reg
, temp
);
2730 reg
= FDI_RX_CTL(pipe
);
2731 temp
= I915_READ(reg
);
2732 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2733 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2734 temp
&= ~FDI_RX_ENABLE
;
2735 I915_WRITE(reg
, temp
);
2737 /* enable CPU FDI TX and PCH FDI RX */
2738 reg
= FDI_TX_CTL(pipe
);
2739 temp
= I915_READ(reg
);
2740 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2741 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2742 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2743 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2744 temp
|= snb_b_fdi_train_param
[j
/2];
2745 temp
|= FDI_COMPOSITE_SYNC
;
2746 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2748 I915_WRITE(FDI_RX_MISC(pipe
),
2749 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2751 reg
= FDI_RX_CTL(pipe
);
2752 temp
= I915_READ(reg
);
2753 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2754 temp
|= FDI_COMPOSITE_SYNC
;
2755 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2758 udelay(1); /* should be 0.5us */
2760 for (i
= 0; i
< 4; i
++) {
2761 reg
= FDI_RX_IIR(pipe
);
2762 temp
= I915_READ(reg
);
2763 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2765 if (temp
& FDI_RX_BIT_LOCK
||
2766 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2767 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2768 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2772 udelay(1); /* should be 0.5us */
2775 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2780 reg
= FDI_TX_CTL(pipe
);
2781 temp
= I915_READ(reg
);
2782 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2783 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2784 I915_WRITE(reg
, temp
);
2786 reg
= FDI_RX_CTL(pipe
);
2787 temp
= I915_READ(reg
);
2788 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2789 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2790 I915_WRITE(reg
, temp
);
2793 udelay(2); /* should be 1.5us */
2795 for (i
= 0; i
< 4; i
++) {
2796 reg
= FDI_RX_IIR(pipe
);
2797 temp
= I915_READ(reg
);
2798 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2800 if (temp
& FDI_RX_SYMBOL_LOCK
||
2801 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2802 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2803 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2807 udelay(2); /* should be 1.5us */
2810 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2814 DRM_DEBUG_KMS("FDI train done.\n");
2817 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2819 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2821 int pipe
= intel_crtc
->pipe
;
2825 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2826 reg
= FDI_RX_CTL(pipe
);
2827 temp
= I915_READ(reg
);
2828 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2829 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2830 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2831 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2836 /* Switch from Rawclk to PCDclk */
2837 temp
= I915_READ(reg
);
2838 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2843 /* Enable CPU FDI TX PLL, always on for Ironlake */
2844 reg
= FDI_TX_CTL(pipe
);
2845 temp
= I915_READ(reg
);
2846 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2847 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2854 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2856 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2858 int pipe
= intel_crtc
->pipe
;
2861 /* Switch from PCDclk to Rawclk */
2862 reg
= FDI_RX_CTL(pipe
);
2863 temp
= I915_READ(reg
);
2864 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2866 /* Disable CPU FDI TX PLL */
2867 reg
= FDI_TX_CTL(pipe
);
2868 temp
= I915_READ(reg
);
2869 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2874 reg
= FDI_RX_CTL(pipe
);
2875 temp
= I915_READ(reg
);
2876 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2878 /* Wait for the clocks to turn off. */
2883 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2885 struct drm_device
*dev
= crtc
->dev
;
2886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2887 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2888 int pipe
= intel_crtc
->pipe
;
2891 /* disable CPU FDI tx and PCH FDI rx */
2892 reg
= FDI_TX_CTL(pipe
);
2893 temp
= I915_READ(reg
);
2894 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2897 reg
= FDI_RX_CTL(pipe
);
2898 temp
= I915_READ(reg
);
2899 temp
&= ~(0x7 << 16);
2900 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2901 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2906 /* Ironlake workaround, disable clock pointer after downing FDI */
2907 if (HAS_PCH_IBX(dev
)) {
2908 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2911 /* still set train pattern 1 */
2912 reg
= FDI_TX_CTL(pipe
);
2913 temp
= I915_READ(reg
);
2914 temp
&= ~FDI_LINK_TRAIN_NONE
;
2915 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2916 I915_WRITE(reg
, temp
);
2918 reg
= FDI_RX_CTL(pipe
);
2919 temp
= I915_READ(reg
);
2920 if (HAS_PCH_CPT(dev
)) {
2921 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2922 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2924 temp
&= ~FDI_LINK_TRAIN_NONE
;
2925 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2927 /* BPC in FDI rx is consistent with that in PIPECONF */
2928 temp
&= ~(0x07 << 16);
2929 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2930 I915_WRITE(reg
, temp
);
2936 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2938 struct drm_device
*dev
= crtc
->dev
;
2939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2941 unsigned long flags
;
2944 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2945 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2948 spin_lock_irqsave(&dev
->event_lock
, flags
);
2949 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2950 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2955 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2957 struct drm_device
*dev
= crtc
->dev
;
2958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2960 if (crtc
->fb
== NULL
)
2963 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2965 wait_event(dev_priv
->pending_flip_queue
,
2966 !intel_crtc_has_pending_flip(crtc
));
2968 mutex_lock(&dev
->struct_mutex
);
2969 intel_finish_fb(crtc
->fb
);
2970 mutex_unlock(&dev
->struct_mutex
);
2973 /* Program iCLKIP clock to the desired frequency */
2974 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2976 struct drm_device
*dev
= crtc
->dev
;
2977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2978 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
2979 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2982 mutex_lock(&dev_priv
->dpio_lock
);
2984 /* It is necessary to ungate the pixclk gate prior to programming
2985 * the divisors, and gate it back when it is done.
2987 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2989 /* Disable SSCCTL */
2990 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2991 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2995 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2996 if (clock
== 20000) {
3001 /* The iCLK virtual clock root frequency is in MHz,
3002 * but the adjusted_mode->crtc_clock in in KHz. To get the
3003 * divisors, it is necessary to divide one by another, so we
3004 * convert the virtual clock precision to KHz here for higher
3007 u32 iclk_virtual_root_freq
= 172800 * 1000;
3008 u32 iclk_pi_range
= 64;
3009 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3011 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3012 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3013 pi_value
= desired_divisor
% iclk_pi_range
;
3016 divsel
= msb_divisor_value
- 2;
3017 phaseinc
= pi_value
;
3020 /* This should not happen with any sane values */
3021 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3022 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3023 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3024 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3026 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3033 /* Program SSCDIVINTPHASE6 */
3034 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3035 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3036 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3037 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3038 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3039 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3040 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3041 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3043 /* Program SSCAUXDIV */
3044 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3045 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3046 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3047 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3049 /* Enable modulator and associated divider */
3050 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3051 temp
&= ~SBI_SSCCTL_DISABLE
;
3052 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3054 /* Wait for initialization time */
3057 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3059 mutex_unlock(&dev_priv
->dpio_lock
);
3062 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3063 enum pipe pch_transcoder
)
3065 struct drm_device
*dev
= crtc
->base
.dev
;
3066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3067 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3069 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3070 I915_READ(HTOTAL(cpu_transcoder
)));
3071 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3072 I915_READ(HBLANK(cpu_transcoder
)));
3073 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3074 I915_READ(HSYNC(cpu_transcoder
)));
3076 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3077 I915_READ(VTOTAL(cpu_transcoder
)));
3078 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3079 I915_READ(VBLANK(cpu_transcoder
)));
3080 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3081 I915_READ(VSYNC(cpu_transcoder
)));
3082 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3083 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3086 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3091 temp
= I915_READ(SOUTH_CHICKEN1
);
3092 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3095 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3096 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3098 temp
|= FDI_BC_BIFURCATION_SELECT
;
3099 DRM_DEBUG_KMS("enabling fdi C rx\n");
3100 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3101 POSTING_READ(SOUTH_CHICKEN1
);
3104 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3106 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3109 switch (intel_crtc
->pipe
) {
3113 if (intel_crtc
->config
.fdi_lanes
> 2)
3114 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3116 cpt_enable_fdi_bc_bifurcation(dev
);
3120 cpt_enable_fdi_bc_bifurcation(dev
);
3129 * Enable PCH resources required for PCH ports:
3131 * - FDI training & RX/TX
3132 * - update transcoder timings
3133 * - DP transcoding bits
3136 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3138 struct drm_device
*dev
= crtc
->dev
;
3139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3141 int pipe
= intel_crtc
->pipe
;
3144 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3146 if (IS_IVYBRIDGE(dev
))
3147 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3149 /* Write the TU size bits before fdi link training, so that error
3150 * detection works. */
3151 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3152 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3154 /* For PCH output, training FDI link */
3155 dev_priv
->display
.fdi_link_train(crtc
);
3157 /* We need to program the right clock selection before writing the pixel
3158 * mutliplier into the DPLL. */
3159 if (HAS_PCH_CPT(dev
)) {
3162 temp
= I915_READ(PCH_DPLL_SEL
);
3163 temp
|= TRANS_DPLL_ENABLE(pipe
);
3164 sel
= TRANS_DPLLB_SEL(pipe
);
3165 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3169 I915_WRITE(PCH_DPLL_SEL
, temp
);
3172 /* XXX: pch pll's can be enabled any time before we enable the PCH
3173 * transcoder, and we actually should do this to not upset any PCH
3174 * transcoder that already use the clock when we share it.
3176 * Note that enable_shared_dpll tries to do the right thing, but
3177 * get_shared_dpll unconditionally resets the pll - we need that to have
3178 * the right LVDS enable sequence. */
3179 ironlake_enable_shared_dpll(intel_crtc
);
3181 /* set transcoder timing, panel must allow it */
3182 assert_panel_unlocked(dev_priv
, pipe
);
3183 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3185 intel_fdi_normal_train(crtc
);
3187 /* For PCH DP, enable TRANS_DP_CTL */
3188 if (HAS_PCH_CPT(dev
) &&
3189 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3190 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3191 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3192 reg
= TRANS_DP_CTL(pipe
);
3193 temp
= I915_READ(reg
);
3194 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3195 TRANS_DP_SYNC_MASK
|
3197 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3198 TRANS_DP_ENH_FRAMING
);
3199 temp
|= bpc
<< 9; /* same format but at 11:9 */
3201 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3202 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3203 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3204 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3206 switch (intel_trans_dp_port_sel(crtc
)) {
3208 temp
|= TRANS_DP_PORT_SEL_B
;
3211 temp
|= TRANS_DP_PORT_SEL_C
;
3214 temp
|= TRANS_DP_PORT_SEL_D
;
3220 I915_WRITE(reg
, temp
);
3223 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3226 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3228 struct drm_device
*dev
= crtc
->dev
;
3229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3230 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3231 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3233 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3235 lpt_program_iclkip(crtc
);
3237 /* Set transcoder timing. */
3238 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3240 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3243 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3245 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3250 if (pll
->refcount
== 0) {
3251 WARN(1, "bad %s refcount\n", pll
->name
);
3255 if (--pll
->refcount
== 0) {
3257 WARN_ON(pll
->active
);
3260 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3263 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3265 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3266 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3267 enum intel_dpll_id i
;
3270 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3271 crtc
->base
.base
.id
, pll
->name
);
3272 intel_put_shared_dpll(crtc
);
3275 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3276 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3277 i
= (enum intel_dpll_id
) crtc
->pipe
;
3278 pll
= &dev_priv
->shared_dplls
[i
];
3280 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3281 crtc
->base
.base
.id
, pll
->name
);
3286 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3287 pll
= &dev_priv
->shared_dplls
[i
];
3289 /* Only want to check enabled timings first */
3290 if (pll
->refcount
== 0)
3293 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3294 sizeof(pll
->hw_state
)) == 0) {
3295 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3297 pll
->name
, pll
->refcount
, pll
->active
);
3303 /* Ok no matching timings, maybe there's a free one? */
3304 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3305 pll
= &dev_priv
->shared_dplls
[i
];
3306 if (pll
->refcount
== 0) {
3307 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3308 crtc
->base
.base
.id
, pll
->name
);
3316 crtc
->config
.shared_dpll
= i
;
3317 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3318 pipe_name(crtc
->pipe
));
3320 if (pll
->active
== 0) {
3321 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3322 sizeof(pll
->hw_state
));
3324 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3326 assert_shared_dpll_disabled(dev_priv
, pll
);
3328 pll
->mode_set(dev_priv
, pll
);
3335 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3338 int dslreg
= PIPEDSL(pipe
);
3341 temp
= I915_READ(dslreg
);
3343 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3344 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3345 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3349 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3351 struct drm_device
*dev
= crtc
->base
.dev
;
3352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3353 int pipe
= crtc
->pipe
;
3355 if (crtc
->config
.pch_pfit
.enabled
) {
3356 /* Force use of hard-coded filter coefficients
3357 * as some pre-programmed values are broken,
3360 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3361 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3362 PF_PIPE_SEL_IVB(pipe
));
3364 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3365 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3366 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3370 static void intel_enable_planes(struct drm_crtc
*crtc
)
3372 struct drm_device
*dev
= crtc
->dev
;
3373 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3374 struct intel_plane
*intel_plane
;
3376 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3377 if (intel_plane
->pipe
== pipe
)
3378 intel_plane_restore(&intel_plane
->base
);
3381 static void intel_disable_planes(struct drm_crtc
*crtc
)
3383 struct drm_device
*dev
= crtc
->dev
;
3384 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3385 struct intel_plane
*intel_plane
;
3387 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3388 if (intel_plane
->pipe
== pipe
)
3389 intel_plane_disable(&intel_plane
->base
);
3392 void hsw_enable_ips(struct intel_crtc
*crtc
)
3394 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3396 if (!crtc
->config
.ips_enabled
)
3399 /* We can only enable IPS after we enable a plane and wait for a vblank.
3400 * We guarantee that the plane is enabled by calling intel_enable_ips
3401 * only after intel_enable_plane. And intel_enable_plane already waits
3402 * for a vblank, so all we need to do here is to enable the IPS bit. */
3403 assert_plane_enabled(dev_priv
, crtc
->plane
);
3404 if (IS_BROADWELL(crtc
->base
.dev
)) {
3405 mutex_lock(&dev_priv
->rps
.hw_lock
);
3406 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3407 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3408 /* Quoting Art Runyan: "its not safe to expect any particular
3409 * value in IPS_CTL bit 31 after enabling IPS through the
3410 * mailbox." Therefore we need to defer waiting on the state
3412 * TODO: need to fix this for state checker
3415 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3416 /* The bit only becomes 1 in the next vblank, so this wait here
3417 * is essentially intel_wait_for_vblank. If we don't have this
3418 * and don't wait for vblanks until the end of crtc_enable, then
3419 * the HW state readout code will complain that the expected
3420 * IPS_CTL value is not the one we read. */
3421 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3422 DRM_ERROR("Timed out waiting for IPS enable\n");
3426 void hsw_disable_ips(struct intel_crtc
*crtc
)
3428 struct drm_device
*dev
= crtc
->base
.dev
;
3429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3431 if (!crtc
->config
.ips_enabled
)
3434 assert_plane_enabled(dev_priv
, crtc
->plane
);
3435 if (IS_BROADWELL(crtc
->base
.dev
)) {
3436 mutex_lock(&dev_priv
->rps
.hw_lock
);
3437 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3438 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3440 I915_WRITE(IPS_CTL
, 0);
3441 POSTING_READ(IPS_CTL
);
3443 /* We need to wait for a vblank before we can disable the plane. */
3444 intel_wait_for_vblank(dev
, crtc
->pipe
);
3447 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3448 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3450 struct drm_device
*dev
= crtc
->dev
;
3451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3452 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3453 enum pipe pipe
= intel_crtc
->pipe
;
3454 int palreg
= PALETTE(pipe
);
3456 bool reenable_ips
= false;
3458 /* The clocks have to be on to load the palette. */
3459 if (!crtc
->enabled
|| !intel_crtc
->active
)
3462 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3463 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3464 assert_dsi_pll_enabled(dev_priv
);
3466 assert_pll_enabled(dev_priv
, pipe
);
3469 /* use legacy palette for Ironlake */
3470 if (HAS_PCH_SPLIT(dev
))
3471 palreg
= LGC_PALETTE(pipe
);
3473 /* Workaround : Do not read or write the pipe palette/gamma data while
3474 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3476 if (intel_crtc
->config
.ips_enabled
&&
3477 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3478 GAMMA_MODE_MODE_SPLIT
)) {
3479 hsw_disable_ips(intel_crtc
);
3480 reenable_ips
= true;
3483 for (i
= 0; i
< 256; i
++) {
3484 I915_WRITE(palreg
+ 4 * i
,
3485 (intel_crtc
->lut_r
[i
] << 16) |
3486 (intel_crtc
->lut_g
[i
] << 8) |
3487 intel_crtc
->lut_b
[i
]);
3491 hsw_enable_ips(intel_crtc
);
3494 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3496 struct drm_device
*dev
= crtc
->dev
;
3497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3498 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3499 struct intel_encoder
*encoder
;
3500 int pipe
= intel_crtc
->pipe
;
3501 int plane
= intel_crtc
->plane
;
3503 WARN_ON(!crtc
->enabled
);
3505 if (intel_crtc
->active
)
3508 intel_crtc
->active
= true;
3510 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3511 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3513 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3514 if (encoder
->pre_enable
)
3515 encoder
->pre_enable(encoder
);
3517 if (intel_crtc
->config
.has_pch_encoder
) {
3518 /* Note: FDI PLL enabling _must_ be done before we enable the
3519 * cpu pipes, hence this is separate from all the other fdi/pch
3521 ironlake_fdi_pll_enable(intel_crtc
);
3523 assert_fdi_tx_disabled(dev_priv
, pipe
);
3524 assert_fdi_rx_disabled(dev_priv
, pipe
);
3527 ironlake_pfit_enable(intel_crtc
);
3530 * On ILK+ LUT must be loaded before the pipe is running but with
3533 intel_crtc_load_lut(crtc
);
3535 intel_update_watermarks(crtc
);
3536 intel_enable_pipe(dev_priv
, pipe
,
3537 intel_crtc
->config
.has_pch_encoder
, false);
3538 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3539 intel_enable_planes(crtc
);
3540 intel_crtc_update_cursor(crtc
, true);
3542 if (intel_crtc
->config
.has_pch_encoder
)
3543 ironlake_pch_enable(crtc
);
3545 mutex_lock(&dev
->struct_mutex
);
3546 intel_update_fbc(dev
);
3547 mutex_unlock(&dev
->struct_mutex
);
3549 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3550 encoder
->enable(encoder
);
3552 if (HAS_PCH_CPT(dev
))
3553 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3556 * There seems to be a race in PCH platform hw (at least on some
3557 * outputs) where an enabled pipe still completes any pageflip right
3558 * away (as if the pipe is off) instead of waiting for vblank. As soon
3559 * as the first vblank happend, everything works as expected. Hence just
3560 * wait for one vblank before returning to avoid strange things
3563 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3566 /* IPS only exists on ULT machines and is tied to pipe A. */
3567 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3569 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3572 static void haswell_crtc_enable_planes(struct drm_crtc
*crtc
)
3574 struct drm_device
*dev
= crtc
->dev
;
3575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3576 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3577 int pipe
= intel_crtc
->pipe
;
3578 int plane
= intel_crtc
->plane
;
3580 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3581 intel_enable_planes(crtc
);
3582 intel_crtc_update_cursor(crtc
, true);
3584 hsw_enable_ips(intel_crtc
);
3586 mutex_lock(&dev
->struct_mutex
);
3587 intel_update_fbc(dev
);
3588 mutex_unlock(&dev
->struct_mutex
);
3591 static void haswell_crtc_disable_planes(struct drm_crtc
*crtc
)
3593 struct drm_device
*dev
= crtc
->dev
;
3594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3595 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3596 int pipe
= intel_crtc
->pipe
;
3597 int plane
= intel_crtc
->plane
;
3599 intel_crtc_wait_for_pending_flips(crtc
);
3600 drm_vblank_off(dev
, pipe
);
3602 /* FBC must be disabled before disabling the plane on HSW. */
3603 if (dev_priv
->fbc
.plane
== plane
)
3604 intel_disable_fbc(dev
);
3606 hsw_disable_ips(intel_crtc
);
3608 intel_crtc_update_cursor(crtc
, false);
3609 intel_disable_planes(crtc
);
3610 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3614 * This implements the workaround described in the "notes" section of the mode
3615 * set sequence documentation. When going from no pipes or single pipe to
3616 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3617 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3619 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
3621 struct drm_device
*dev
= crtc
->base
.dev
;
3622 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
3624 /* We want to get the other_active_crtc only if there's only 1 other
3626 list_for_each_entry(crtc_it
, &dev
->mode_config
.crtc_list
, base
.head
) {
3627 if (!crtc_it
->active
|| crtc_it
== crtc
)
3630 if (other_active_crtc
)
3633 other_active_crtc
= crtc_it
;
3635 if (!other_active_crtc
)
3638 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3639 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3642 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3644 struct drm_device
*dev
= crtc
->dev
;
3645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3647 struct intel_encoder
*encoder
;
3648 int pipe
= intel_crtc
->pipe
;
3650 WARN_ON(!crtc
->enabled
);
3652 if (intel_crtc
->active
)
3655 intel_crtc
->active
= true;
3657 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3658 if (intel_crtc
->config
.has_pch_encoder
)
3659 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3661 if (intel_crtc
->config
.has_pch_encoder
)
3662 dev_priv
->display
.fdi_link_train(crtc
);
3664 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3665 if (encoder
->pre_enable
)
3666 encoder
->pre_enable(encoder
);
3668 intel_ddi_enable_pipe_clock(intel_crtc
);
3670 ironlake_pfit_enable(intel_crtc
);
3673 * On ILK+ LUT must be loaded before the pipe is running but with
3676 intel_crtc_load_lut(crtc
);
3678 intel_ddi_set_pipe_settings(crtc
);
3679 intel_ddi_enable_transcoder_func(crtc
);
3681 intel_update_watermarks(crtc
);
3682 intel_enable_pipe(dev_priv
, pipe
,
3683 intel_crtc
->config
.has_pch_encoder
, false);
3685 if (intel_crtc
->config
.has_pch_encoder
)
3686 lpt_pch_enable(crtc
);
3688 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3689 encoder
->enable(encoder
);
3690 intel_opregion_notify_encoder(encoder
, true);
3693 /* If we change the relative order between pipe/planes enabling, we need
3694 * to change the workaround. */
3695 haswell_mode_set_planes_workaround(intel_crtc
);
3696 haswell_crtc_enable_planes(crtc
);
3699 * There seems to be a race in PCH platform hw (at least on some
3700 * outputs) where an enabled pipe still completes any pageflip right
3701 * away (as if the pipe is off) instead of waiting for vblank. As soon
3702 * as the first vblank happend, everything works as expected. Hence just
3703 * wait for one vblank before returning to avoid strange things
3706 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3709 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3711 struct drm_device
*dev
= crtc
->base
.dev
;
3712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3713 int pipe
= crtc
->pipe
;
3715 /* To avoid upsetting the power well on haswell only disable the pfit if
3716 * it's in use. The hw state code will make sure we get this right. */
3717 if (crtc
->config
.pch_pfit
.enabled
) {
3718 I915_WRITE(PF_CTL(pipe
), 0);
3719 I915_WRITE(PF_WIN_POS(pipe
), 0);
3720 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3724 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3726 struct drm_device
*dev
= crtc
->dev
;
3727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3728 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3729 struct intel_encoder
*encoder
;
3730 int pipe
= intel_crtc
->pipe
;
3731 int plane
= intel_crtc
->plane
;
3735 if (!intel_crtc
->active
)
3738 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3739 encoder
->disable(encoder
);
3741 intel_crtc_wait_for_pending_flips(crtc
);
3742 drm_vblank_off(dev
, pipe
);
3744 if (dev_priv
->fbc
.plane
== plane
)
3745 intel_disable_fbc(dev
);
3747 intel_crtc_update_cursor(crtc
, false);
3748 intel_disable_planes(crtc
);
3749 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3751 if (intel_crtc
->config
.has_pch_encoder
)
3752 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3754 intel_disable_pipe(dev_priv
, pipe
);
3756 ironlake_pfit_disable(intel_crtc
);
3758 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3759 if (encoder
->post_disable
)
3760 encoder
->post_disable(encoder
);
3762 if (intel_crtc
->config
.has_pch_encoder
) {
3763 ironlake_fdi_disable(crtc
);
3765 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3766 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3768 if (HAS_PCH_CPT(dev
)) {
3769 /* disable TRANS_DP_CTL */
3770 reg
= TRANS_DP_CTL(pipe
);
3771 temp
= I915_READ(reg
);
3772 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3773 TRANS_DP_PORT_SEL_MASK
);
3774 temp
|= TRANS_DP_PORT_SEL_NONE
;
3775 I915_WRITE(reg
, temp
);
3777 /* disable DPLL_SEL */
3778 temp
= I915_READ(PCH_DPLL_SEL
);
3779 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3780 I915_WRITE(PCH_DPLL_SEL
, temp
);
3783 /* disable PCH DPLL */
3784 intel_disable_shared_dpll(intel_crtc
);
3786 ironlake_fdi_pll_disable(intel_crtc
);
3789 intel_crtc
->active
= false;
3790 intel_update_watermarks(crtc
);
3792 mutex_lock(&dev
->struct_mutex
);
3793 intel_update_fbc(dev
);
3794 mutex_unlock(&dev
->struct_mutex
);
3797 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3799 struct drm_device
*dev
= crtc
->dev
;
3800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3801 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3802 struct intel_encoder
*encoder
;
3803 int pipe
= intel_crtc
->pipe
;
3804 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3806 if (!intel_crtc
->active
)
3809 haswell_crtc_disable_planes(crtc
);
3811 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3812 intel_opregion_notify_encoder(encoder
, false);
3813 encoder
->disable(encoder
);
3816 if (intel_crtc
->config
.has_pch_encoder
)
3817 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3818 intel_disable_pipe(dev_priv
, pipe
);
3820 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3822 ironlake_pfit_disable(intel_crtc
);
3824 intel_ddi_disable_pipe_clock(intel_crtc
);
3826 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3827 if (encoder
->post_disable
)
3828 encoder
->post_disable(encoder
);
3830 if (intel_crtc
->config
.has_pch_encoder
) {
3831 lpt_disable_pch_transcoder(dev_priv
);
3832 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3833 intel_ddi_fdi_disable(crtc
);
3836 intel_crtc
->active
= false;
3837 intel_update_watermarks(crtc
);
3839 mutex_lock(&dev
->struct_mutex
);
3840 intel_update_fbc(dev
);
3841 mutex_unlock(&dev
->struct_mutex
);
3844 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3847 intel_put_shared_dpll(intel_crtc
);
3850 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3852 intel_ddi_put_crtc_pll(crtc
);
3855 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3857 if (!enable
&& intel_crtc
->overlay
) {
3858 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3861 mutex_lock(&dev
->struct_mutex
);
3862 dev_priv
->mm
.interruptible
= false;
3863 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3864 dev_priv
->mm
.interruptible
= true;
3865 mutex_unlock(&dev
->struct_mutex
);
3868 /* Let userspace switch the overlay on again. In most cases userspace
3869 * has to recompute where to put it anyway.
3874 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3875 * cursor plane briefly if not already running after enabling the display
3877 * This workaround avoids occasional blank screens when self refresh is
3881 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3883 u32 cntl
= I915_READ(CURCNTR(pipe
));
3885 if ((cntl
& CURSOR_MODE
) == 0) {
3886 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3888 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3889 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3890 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3891 I915_WRITE(CURCNTR(pipe
), cntl
);
3892 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3893 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3897 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3899 struct drm_device
*dev
= crtc
->base
.dev
;
3900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3901 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3903 if (!crtc
->config
.gmch_pfit
.control
)
3907 * The panel fitter should only be adjusted whilst the pipe is disabled,
3908 * according to register description and PRM.
3910 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3911 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3913 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3914 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3916 /* Border color in case we don't scale up to the full screen. Black by
3917 * default, change to something else for debugging. */
3918 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3921 int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
3923 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
3925 /* Obtain SKU information */
3926 mutex_lock(&dev_priv
->dpio_lock
);
3927 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
3928 CCK_FUSE_HPLL_FREQ_MASK
;
3929 mutex_unlock(&dev_priv
->dpio_lock
);
3931 return vco_freq
[hpll_freq
];
3934 /* Adjust CDclk dividers to allow high res or save power if possible */
3935 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3940 if (cdclk
>= 320) /* jump to highest voltage for 400MHz too */
3942 else if (cdclk
== 266)
3947 mutex_lock(&dev_priv
->rps
.hw_lock
);
3948 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
3949 val
&= ~DSPFREQGUAR_MASK
;
3950 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
3951 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
3952 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
3953 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
3955 DRM_ERROR("timed out waiting for CDclk change\n");
3957 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3962 vco
= valleyview_get_vco(dev_priv
);
3963 divider
= ((vco
<< 1) / cdclk
) - 1;
3965 mutex_lock(&dev_priv
->dpio_lock
);
3966 /* adjust cdclk divider */
3967 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
3970 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
3971 mutex_unlock(&dev_priv
->dpio_lock
);
3974 mutex_lock(&dev_priv
->dpio_lock
);
3975 /* adjust self-refresh exit latency value */
3976 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
3980 * For high bandwidth configs, we set a higher latency in the bunit
3981 * so that the core display fetch happens in time to avoid underruns.
3984 val
|= 4500 / 250; /* 4.5 usec */
3986 val
|= 3000 / 250; /* 3.0 usec */
3987 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
3988 mutex_unlock(&dev_priv
->dpio_lock
);
3990 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
3991 intel_i2c_reset(dev
);
3994 static int valleyview_cur_cdclk(struct drm_i915_private
*dev_priv
)
3999 vco
= valleyview_get_vco(dev_priv
);
4001 mutex_lock(&dev_priv
->dpio_lock
);
4002 divider
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4003 mutex_unlock(&dev_priv
->dpio_lock
);
4007 cur_cdclk
= (vco
<< 1) / (divider
+ 1);
4012 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4017 cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4020 * Really only a few cases to deal with, as only 4 CDclks are supported:
4025 * So we check to see whether we're above 90% of the lower bin and
4028 if (max_pixclk
> 288000) {
4030 } else if (max_pixclk
> 240000) {
4034 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4037 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
,
4038 unsigned modeset_pipes
,
4039 struct intel_crtc_config
*pipe_config
)
4041 struct drm_device
*dev
= dev_priv
->dev
;
4042 struct intel_crtc
*intel_crtc
;
4045 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
4047 if (modeset_pipes
& (1 << intel_crtc
->pipe
))
4048 max_pixclk
= max(max_pixclk
,
4049 pipe_config
->adjusted_mode
.crtc_clock
);
4050 else if (intel_crtc
->base
.enabled
)
4051 max_pixclk
= max(max_pixclk
,
4052 intel_crtc
->config
.adjusted_mode
.crtc_clock
);
4058 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4059 unsigned *prepare_pipes
,
4060 unsigned modeset_pipes
,
4061 struct intel_crtc_config
*pipe_config
)
4063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4064 struct intel_crtc
*intel_crtc
;
4065 int max_pixclk
= intel_mode_max_pixclk(dev_priv
, modeset_pipes
,
4067 int cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4069 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) == cur_cdclk
)
4072 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
4074 if (intel_crtc
->base
.enabled
)
4075 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4078 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4081 int max_pixclk
= intel_mode_max_pixclk(dev_priv
, 0, NULL
);
4082 int cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4083 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4085 if (req_cdclk
!= cur_cdclk
)
4086 valleyview_set_cdclk(dev
, req_cdclk
);
4089 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4091 struct drm_device
*dev
= crtc
->dev
;
4092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4093 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4094 struct intel_encoder
*encoder
;
4095 int pipe
= intel_crtc
->pipe
;
4096 int plane
= intel_crtc
->plane
;
4099 WARN_ON(!crtc
->enabled
);
4101 if (intel_crtc
->active
)
4104 intel_crtc
->active
= true;
4106 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4107 if (encoder
->pre_pll_enable
)
4108 encoder
->pre_pll_enable(encoder
);
4110 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4113 vlv_enable_pll(intel_crtc
);
4115 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4116 if (encoder
->pre_enable
)
4117 encoder
->pre_enable(encoder
);
4119 i9xx_pfit_enable(intel_crtc
);
4121 intel_crtc_load_lut(crtc
);
4123 intel_update_watermarks(crtc
);
4124 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
4125 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
4126 intel_enable_planes(crtc
);
4127 intel_crtc_update_cursor(crtc
, true);
4129 intel_update_fbc(dev
);
4131 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4132 encoder
->enable(encoder
);
4135 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4137 struct drm_device
*dev
= crtc
->dev
;
4138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4139 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4140 struct intel_encoder
*encoder
;
4141 int pipe
= intel_crtc
->pipe
;
4142 int plane
= intel_crtc
->plane
;
4144 WARN_ON(!crtc
->enabled
);
4146 if (intel_crtc
->active
)
4149 intel_crtc
->active
= true;
4151 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4152 if (encoder
->pre_enable
)
4153 encoder
->pre_enable(encoder
);
4155 i9xx_enable_pll(intel_crtc
);
4157 i9xx_pfit_enable(intel_crtc
);
4159 intel_crtc_load_lut(crtc
);
4161 intel_update_watermarks(crtc
);
4162 intel_enable_pipe(dev_priv
, pipe
, false, false);
4163 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
4164 intel_enable_planes(crtc
);
4165 /* The fixup needs to happen before cursor is enabled */
4167 g4x_fixup_plane(dev_priv
, pipe
);
4168 intel_crtc_update_cursor(crtc
, true);
4170 /* Give the overlay scaler a chance to enable if it's on this pipe */
4171 intel_crtc_dpms_overlay(intel_crtc
, true);
4173 intel_update_fbc(dev
);
4175 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4176 encoder
->enable(encoder
);
4179 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4181 struct drm_device
*dev
= crtc
->base
.dev
;
4182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4184 if (!crtc
->config
.gmch_pfit
.control
)
4187 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4189 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4190 I915_READ(PFIT_CONTROL
));
4191 I915_WRITE(PFIT_CONTROL
, 0);
4194 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4196 struct drm_device
*dev
= crtc
->dev
;
4197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4199 struct intel_encoder
*encoder
;
4200 int pipe
= intel_crtc
->pipe
;
4201 int plane
= intel_crtc
->plane
;
4203 if (!intel_crtc
->active
)
4206 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4207 encoder
->disable(encoder
);
4209 /* Give the overlay scaler a chance to disable if it's on this pipe */
4210 intel_crtc_wait_for_pending_flips(crtc
);
4211 drm_vblank_off(dev
, pipe
);
4213 if (dev_priv
->fbc
.plane
== plane
)
4214 intel_disable_fbc(dev
);
4216 intel_crtc_dpms_overlay(intel_crtc
, false);
4217 intel_crtc_update_cursor(crtc
, false);
4218 intel_disable_planes(crtc
);
4219 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
4221 intel_disable_pipe(dev_priv
, pipe
);
4223 i9xx_pfit_disable(intel_crtc
);
4225 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4226 if (encoder
->post_disable
)
4227 encoder
->post_disable(encoder
);
4229 if (IS_VALLEYVIEW(dev
) && !intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
4230 vlv_disable_pll(dev_priv
, pipe
);
4231 else if (!IS_VALLEYVIEW(dev
))
4232 i9xx_disable_pll(dev_priv
, pipe
);
4234 intel_crtc
->active
= false;
4235 intel_update_watermarks(crtc
);
4237 intel_update_fbc(dev
);
4240 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4244 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4247 struct drm_device
*dev
= crtc
->dev
;
4248 struct drm_i915_master_private
*master_priv
;
4249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4250 int pipe
= intel_crtc
->pipe
;
4252 if (!dev
->primary
->master
)
4255 master_priv
= dev
->primary
->master
->driver_priv
;
4256 if (!master_priv
->sarea_priv
)
4261 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4262 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4265 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4266 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4269 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4275 * Sets the power management mode of the pipe and plane.
4277 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4279 struct drm_device
*dev
= crtc
->dev
;
4280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4281 struct intel_encoder
*intel_encoder
;
4282 bool enable
= false;
4284 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4285 enable
|= intel_encoder
->connectors_active
;
4288 dev_priv
->display
.crtc_enable(crtc
);
4290 dev_priv
->display
.crtc_disable(crtc
);
4292 intel_crtc_update_sarea(crtc
, enable
);
4295 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4297 struct drm_device
*dev
= crtc
->dev
;
4298 struct drm_connector
*connector
;
4299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4302 /* crtc should still be enabled when we disable it. */
4303 WARN_ON(!crtc
->enabled
);
4305 dev_priv
->display
.crtc_disable(crtc
);
4306 intel_crtc
->eld_vld
= false;
4307 intel_crtc_update_sarea(crtc
, false);
4308 dev_priv
->display
.off(crtc
);
4310 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4311 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
4312 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
4315 mutex_lock(&dev
->struct_mutex
);
4316 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
4317 mutex_unlock(&dev
->struct_mutex
);
4321 /* Update computed state. */
4322 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4323 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4326 if (connector
->encoder
->crtc
!= crtc
)
4329 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4330 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4334 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4336 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4338 drm_encoder_cleanup(encoder
);
4339 kfree(intel_encoder
);
4342 /* Simple dpms helper for encoders with just one connector, no cloning and only
4343 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4344 * state of the entire output pipe. */
4345 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4347 if (mode
== DRM_MODE_DPMS_ON
) {
4348 encoder
->connectors_active
= true;
4350 intel_crtc_update_dpms(encoder
->base
.crtc
);
4352 encoder
->connectors_active
= false;
4354 intel_crtc_update_dpms(encoder
->base
.crtc
);
4358 /* Cross check the actual hw state with our own modeset state tracking (and it's
4359 * internal consistency). */
4360 static void intel_connector_check_state(struct intel_connector
*connector
)
4362 if (connector
->get_hw_state(connector
)) {
4363 struct intel_encoder
*encoder
= connector
->encoder
;
4364 struct drm_crtc
*crtc
;
4365 bool encoder_enabled
;
4368 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4369 connector
->base
.base
.id
,
4370 drm_get_connector_name(&connector
->base
));
4372 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4373 "wrong connector dpms state\n");
4374 WARN(connector
->base
.encoder
!= &encoder
->base
,
4375 "active connector not linked to encoder\n");
4376 WARN(!encoder
->connectors_active
,
4377 "encoder->connectors_active not set\n");
4379 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4380 WARN(!encoder_enabled
, "encoder not enabled\n");
4381 if (WARN_ON(!encoder
->base
.crtc
))
4384 crtc
= encoder
->base
.crtc
;
4386 WARN(!crtc
->enabled
, "crtc not enabled\n");
4387 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4388 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4389 "encoder active on the wrong pipe\n");
4393 /* Even simpler default implementation, if there's really no special case to
4395 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4397 /* All the simple cases only support two dpms states. */
4398 if (mode
!= DRM_MODE_DPMS_ON
)
4399 mode
= DRM_MODE_DPMS_OFF
;
4401 if (mode
== connector
->dpms
)
4404 connector
->dpms
= mode
;
4406 /* Only need to change hw state when actually enabled */
4407 if (connector
->encoder
)
4408 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
4410 intel_modeset_check_state(connector
->dev
);
4413 /* Simple connector->get_hw_state implementation for encoders that support only
4414 * one connector and no cloning and hence the encoder state determines the state
4415 * of the connector. */
4416 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4419 struct intel_encoder
*encoder
= connector
->encoder
;
4421 return encoder
->get_hw_state(encoder
, &pipe
);
4424 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4425 struct intel_crtc_config
*pipe_config
)
4427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4428 struct intel_crtc
*pipe_B_crtc
=
4429 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4431 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4432 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4433 if (pipe_config
->fdi_lanes
> 4) {
4434 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4435 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4439 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4440 if (pipe_config
->fdi_lanes
> 2) {
4441 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4442 pipe_config
->fdi_lanes
);
4449 if (INTEL_INFO(dev
)->num_pipes
== 2)
4452 /* Ivybridge 3 pipe is really complicated */
4457 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4458 pipe_config
->fdi_lanes
> 2) {
4459 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4460 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4465 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4466 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4467 if (pipe_config
->fdi_lanes
> 2) {
4468 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4469 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4473 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4483 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4484 struct intel_crtc_config
*pipe_config
)
4486 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4487 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4488 int lane
, link_bw
, fdi_dotclock
;
4489 bool setup_ok
, needs_recompute
= false;
4492 /* FDI is a binary signal running at ~2.7GHz, encoding
4493 * each output octet as 10 bits. The actual frequency
4494 * is stored as a divider into a 100MHz clock, and the
4495 * mode pixel clock is stored in units of 1KHz.
4496 * Hence the bw of each lane in terms of the mode signal
4499 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4501 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4503 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4504 pipe_config
->pipe_bpp
);
4506 pipe_config
->fdi_lanes
= lane
;
4508 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4509 link_bw
, &pipe_config
->fdi_m_n
);
4511 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4512 intel_crtc
->pipe
, pipe_config
);
4513 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4514 pipe_config
->pipe_bpp
-= 2*3;
4515 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4516 pipe_config
->pipe_bpp
);
4517 needs_recompute
= true;
4518 pipe_config
->bw_constrained
= true;
4523 if (needs_recompute
)
4526 return setup_ok
? 0 : -EINVAL
;
4529 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4530 struct intel_crtc_config
*pipe_config
)
4532 pipe_config
->ips_enabled
= i915_enable_ips
&&
4533 hsw_crtc_supports_ips(crtc
) &&
4534 pipe_config
->pipe_bpp
<= 24;
4537 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4538 struct intel_crtc_config
*pipe_config
)
4540 struct drm_device
*dev
= crtc
->base
.dev
;
4541 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4543 /* FIXME should check pixel clock limits on all platforms */
4544 if (INTEL_INFO(dev
)->gen
< 4) {
4545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4547 dev_priv
->display
.get_display_clock_speed(dev
);
4550 * Enable pixel doubling when the dot clock
4551 * is > 90% of the (display) core speed.
4553 * GDG double wide on either pipe,
4554 * otherwise pipe A only.
4556 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4557 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4559 pipe_config
->double_wide
= true;
4562 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4567 * Pipe horizontal size must be even in:
4569 * - LVDS dual channel mode
4570 * - Double wide pipe
4572 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4573 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4574 pipe_config
->pipe_src_w
&= ~1;
4576 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4577 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4579 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4580 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4583 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4584 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4585 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4586 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4588 pipe_config
->pipe_bpp
= 8*3;
4592 hsw_compute_ips_config(crtc
, pipe_config
);
4594 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4595 * clock survives for now. */
4596 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4597 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4599 if (pipe_config
->has_pch_encoder
)
4600 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4605 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4607 return 400000; /* FIXME */
4610 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4615 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4620 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4625 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4629 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4631 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4632 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4634 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4636 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4638 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4641 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4642 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4644 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4649 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4653 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4655 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4658 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4659 case GC_DISPLAY_CLOCK_333_MHZ
:
4662 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4668 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4673 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4676 /* Assume that the hardware is in the high speed state. This
4677 * should be the default.
4679 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4680 case GC_CLOCK_133_200
:
4681 case GC_CLOCK_100_200
:
4683 case GC_CLOCK_166_250
:
4685 case GC_CLOCK_100_133
:
4689 /* Shouldn't happen */
4693 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4699 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4701 while (*num
> DATA_LINK_M_N_MASK
||
4702 *den
> DATA_LINK_M_N_MASK
) {
4708 static void compute_m_n(unsigned int m
, unsigned int n
,
4709 uint32_t *ret_m
, uint32_t *ret_n
)
4711 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4712 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4713 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4717 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4718 int pixel_clock
, int link_clock
,
4719 struct intel_link_m_n
*m_n
)
4723 compute_m_n(bits_per_pixel
* pixel_clock
,
4724 link_clock
* nlanes
* 8,
4725 &m_n
->gmch_m
, &m_n
->gmch_n
);
4727 compute_m_n(pixel_clock
, link_clock
,
4728 &m_n
->link_m
, &m_n
->link_n
);
4731 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4733 if (i915_panel_use_ssc
>= 0)
4734 return i915_panel_use_ssc
!= 0;
4735 return dev_priv
->vbt
.lvds_use_ssc
4736 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4739 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4741 struct drm_device
*dev
= crtc
->dev
;
4742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4745 if (IS_VALLEYVIEW(dev
)) {
4747 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4748 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4749 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4750 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4752 } else if (!IS_GEN2(dev
)) {
4761 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4763 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4766 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4768 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4771 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4772 intel_clock_t
*reduced_clock
)
4774 struct drm_device
*dev
= crtc
->base
.dev
;
4775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4776 int pipe
= crtc
->pipe
;
4779 if (IS_PINEVIEW(dev
)) {
4780 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4782 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4784 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4786 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4789 I915_WRITE(FP0(pipe
), fp
);
4790 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4792 crtc
->lowfreq_avail
= false;
4793 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4794 reduced_clock
&& i915_powersave
) {
4795 I915_WRITE(FP1(pipe
), fp2
);
4796 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4797 crtc
->lowfreq_avail
= true;
4799 I915_WRITE(FP1(pipe
), fp
);
4800 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4804 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4810 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4811 * and set it to a reasonable value instead.
4813 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
4814 reg_val
&= 0xffffff00;
4815 reg_val
|= 0x00000030;
4816 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
4818 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
4819 reg_val
&= 0x8cffffff;
4820 reg_val
= 0x8c000000;
4821 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
4823 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
4824 reg_val
&= 0xffffff00;
4825 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
4827 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
4828 reg_val
&= 0x00ffffff;
4829 reg_val
|= 0xb0000000;
4830 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
4833 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4834 struct intel_link_m_n
*m_n
)
4836 struct drm_device
*dev
= crtc
->base
.dev
;
4837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4838 int pipe
= crtc
->pipe
;
4840 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4841 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4842 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4843 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4846 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4847 struct intel_link_m_n
*m_n
)
4849 struct drm_device
*dev
= crtc
->base
.dev
;
4850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4851 int pipe
= crtc
->pipe
;
4852 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4854 if (INTEL_INFO(dev
)->gen
>= 5) {
4855 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4856 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4857 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4858 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4860 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4861 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4862 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4863 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4867 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4869 if (crtc
->config
.has_pch_encoder
)
4870 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4872 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4875 static void vlv_update_pll(struct intel_crtc
*crtc
)
4877 struct drm_device
*dev
= crtc
->base
.dev
;
4878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4879 int pipe
= crtc
->pipe
;
4881 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4882 u32 coreclk
, reg_val
, dpll_md
;
4884 mutex_lock(&dev_priv
->dpio_lock
);
4886 bestn
= crtc
->config
.dpll
.n
;
4887 bestm1
= crtc
->config
.dpll
.m1
;
4888 bestm2
= crtc
->config
.dpll
.m2
;
4889 bestp1
= crtc
->config
.dpll
.p1
;
4890 bestp2
= crtc
->config
.dpll
.p2
;
4892 /* See eDP HDMI DPIO driver vbios notes doc */
4894 /* PLL B needs special handling */
4896 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4898 /* Set up Tx target for periodic Rcomp update */
4899 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
4901 /* Disable target IRef on PLL */
4902 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
4903 reg_val
&= 0x00ffffff;
4904 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
4906 /* Disable fast lock */
4907 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
4909 /* Set idtafcrecal before PLL is enabled */
4910 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4911 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4912 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4913 mdiv
|= (1 << DPIO_K_SHIFT
);
4916 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4917 * but we don't support that).
4918 * Note: don't use the DAC post divider as it seems unstable.
4920 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4921 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
4923 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4924 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
4926 /* Set HBR and RBR LPF coefficients */
4927 if (crtc
->config
.port_clock
== 162000 ||
4928 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4929 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4930 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
4933 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
4936 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4937 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4938 /* Use SSC source */
4940 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4943 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4945 } else { /* HDMI or VGA */
4946 /* Use bend source */
4948 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4951 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4955 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
4956 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4957 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4958 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4959 coreclk
|= 0x01000000;
4960 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
4962 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
4964 /* Enable DPIO clock input */
4965 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4966 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4967 /* We should never disable this, set it here for state tracking */
4969 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4970 dpll
|= DPLL_VCO_ENABLE
;
4971 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4973 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4974 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4975 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4977 if (crtc
->config
.has_dp_encoder
)
4978 intel_dp_set_m_n(crtc
);
4980 mutex_unlock(&dev_priv
->dpio_lock
);
4983 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4984 intel_clock_t
*reduced_clock
,
4987 struct drm_device
*dev
= crtc
->base
.dev
;
4988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4991 struct dpll
*clock
= &crtc
->config
.dpll
;
4993 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4995 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4996 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4998 dpll
= DPLL_VGA_MODE_DIS
;
5000 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5001 dpll
|= DPLLB_MODE_LVDS
;
5003 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5005 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5006 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5007 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5011 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5013 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5014 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5016 /* compute bitmask from p1 value */
5017 if (IS_PINEVIEW(dev
))
5018 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5020 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5021 if (IS_G4X(dev
) && reduced_clock
)
5022 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5024 switch (clock
->p2
) {
5026 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5029 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5032 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5035 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5038 if (INTEL_INFO(dev
)->gen
>= 4)
5039 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5041 if (crtc
->config
.sdvo_tv_clock
)
5042 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5043 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5044 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5045 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5047 dpll
|= PLL_REF_INPUT_DREFCLK
;
5049 dpll
|= DPLL_VCO_ENABLE
;
5050 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5052 if (INTEL_INFO(dev
)->gen
>= 4) {
5053 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5054 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5055 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5058 if (crtc
->config
.has_dp_encoder
)
5059 intel_dp_set_m_n(crtc
);
5062 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5063 intel_clock_t
*reduced_clock
,
5066 struct drm_device
*dev
= crtc
->base
.dev
;
5067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5069 struct dpll
*clock
= &crtc
->config
.dpll
;
5071 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5073 dpll
= DPLL_VGA_MODE_DIS
;
5075 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5076 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5079 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5081 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5083 dpll
|= PLL_P2_DIVIDE_BY_4
;
5086 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5087 dpll
|= DPLL_DVO_2X_MODE
;
5089 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5090 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5091 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5093 dpll
|= PLL_REF_INPUT_DREFCLK
;
5095 dpll
|= DPLL_VCO_ENABLE
;
5096 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5099 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5101 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5103 enum pipe pipe
= intel_crtc
->pipe
;
5104 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5105 struct drm_display_mode
*adjusted_mode
=
5106 &intel_crtc
->config
.adjusted_mode
;
5107 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
5109 /* We need to be careful not to changed the adjusted mode, for otherwise
5110 * the hw state checker will get angry at the mismatch. */
5111 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5112 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5114 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5115 /* the chip adds 2 halflines automatically */
5117 crtc_vblank_end
-= 1;
5118 vsyncshift
= adjusted_mode
->crtc_hsync_start
5119 - adjusted_mode
->crtc_htotal
/ 2;
5124 if (INTEL_INFO(dev
)->gen
> 3)
5125 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5127 I915_WRITE(HTOTAL(cpu_transcoder
),
5128 (adjusted_mode
->crtc_hdisplay
- 1) |
5129 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5130 I915_WRITE(HBLANK(cpu_transcoder
),
5131 (adjusted_mode
->crtc_hblank_start
- 1) |
5132 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5133 I915_WRITE(HSYNC(cpu_transcoder
),
5134 (adjusted_mode
->crtc_hsync_start
- 1) |
5135 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5137 I915_WRITE(VTOTAL(cpu_transcoder
),
5138 (adjusted_mode
->crtc_vdisplay
- 1) |
5139 ((crtc_vtotal
- 1) << 16));
5140 I915_WRITE(VBLANK(cpu_transcoder
),
5141 (adjusted_mode
->crtc_vblank_start
- 1) |
5142 ((crtc_vblank_end
- 1) << 16));
5143 I915_WRITE(VSYNC(cpu_transcoder
),
5144 (adjusted_mode
->crtc_vsync_start
- 1) |
5145 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5147 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5148 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5149 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5151 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5152 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5153 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5155 /* pipesrc controls the size that is scaled from, which should
5156 * always be the user's requested size.
5158 I915_WRITE(PIPESRC(pipe
),
5159 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5160 (intel_crtc
->config
.pipe_src_h
- 1));
5163 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5164 struct intel_crtc_config
*pipe_config
)
5166 struct drm_device
*dev
= crtc
->base
.dev
;
5167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5168 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5171 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5172 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5173 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5174 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5175 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5176 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5177 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5178 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5179 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5181 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5182 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5183 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5184 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5185 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5186 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5187 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5188 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5189 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5191 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
5192 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
5193 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
5194 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
5197 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
5198 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
5199 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
5201 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
5202 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
5205 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
5206 struct intel_crtc_config
*pipe_config
)
5208 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5210 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
5211 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
5212 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
5213 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
5215 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
5216 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
5217 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
5218 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
5220 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
5222 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
5223 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
5226 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
5228 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5234 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
5235 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
5236 pipeconf
|= PIPECONF_ENABLE
;
5238 if (intel_crtc
->config
.double_wide
)
5239 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5241 /* only g4x and later have fancy bpc/dither controls */
5242 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5243 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5244 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
5245 pipeconf
|= PIPECONF_DITHER_EN
|
5246 PIPECONF_DITHER_TYPE_SP
;
5248 switch (intel_crtc
->config
.pipe_bpp
) {
5250 pipeconf
|= PIPECONF_6BPC
;
5253 pipeconf
|= PIPECONF_8BPC
;
5256 pipeconf
|= PIPECONF_10BPC
;
5259 /* Case prevented by intel_choose_pipe_bpp_dither. */
5264 if (HAS_PIPE_CXSR(dev
)) {
5265 if (intel_crtc
->lowfreq_avail
) {
5266 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5267 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5269 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5273 if (!IS_GEN2(dev
) &&
5274 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5275 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5277 pipeconf
|= PIPECONF_PROGRESSIVE
;
5279 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
5280 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
5282 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
5283 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
5286 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5288 struct drm_framebuffer
*fb
)
5290 struct drm_device
*dev
= crtc
->dev
;
5291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5292 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5293 int pipe
= intel_crtc
->pipe
;
5294 int plane
= intel_crtc
->plane
;
5295 int refclk
, num_connectors
= 0;
5296 intel_clock_t clock
, reduced_clock
;
5298 bool ok
, has_reduced_clock
= false;
5299 bool is_lvds
= false, is_dsi
= false;
5300 struct intel_encoder
*encoder
;
5301 const intel_limit_t
*limit
;
5304 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5305 switch (encoder
->type
) {
5306 case INTEL_OUTPUT_LVDS
:
5309 case INTEL_OUTPUT_DSI
:
5320 if (!intel_crtc
->config
.clock_set
) {
5321 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5324 * Returns a set of divisors for the desired target clock with
5325 * the given refclk, or FALSE. The returned values represent
5326 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5329 limit
= intel_limit(crtc
, refclk
);
5330 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
5331 intel_crtc
->config
.port_clock
,
5332 refclk
, NULL
, &clock
);
5334 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5338 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5340 * Ensure we match the reduced clock's P to the target
5341 * clock. If the clocks don't match, we can't switch
5342 * the display clock by using the FP0/FP1. In such case
5343 * we will disable the LVDS downclock feature.
5346 dev_priv
->display
.find_dpll(limit
, crtc
,
5347 dev_priv
->lvds_downclock
,
5351 /* Compat-code for transition, will disappear. */
5352 intel_crtc
->config
.dpll
.n
= clock
.n
;
5353 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5354 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5355 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5356 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5360 i8xx_update_pll(intel_crtc
,
5361 has_reduced_clock
? &reduced_clock
: NULL
,
5363 } else if (IS_VALLEYVIEW(dev
)) {
5364 vlv_update_pll(intel_crtc
);
5366 i9xx_update_pll(intel_crtc
,
5367 has_reduced_clock
? &reduced_clock
: NULL
,
5372 /* Set up the display plane register */
5373 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5375 if (!IS_VALLEYVIEW(dev
)) {
5377 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5379 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5382 intel_set_pipe_timings(intel_crtc
);
5384 /* pipesrc and dspsize control the size that is scaled from,
5385 * which should always be the user's requested size.
5387 I915_WRITE(DSPSIZE(plane
),
5388 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5389 (intel_crtc
->config
.pipe_src_w
- 1));
5390 I915_WRITE(DSPPOS(plane
), 0);
5392 i9xx_set_pipeconf(intel_crtc
);
5394 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5395 POSTING_READ(DSPCNTR(plane
));
5397 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5402 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5403 struct intel_crtc_config
*pipe_config
)
5405 struct drm_device
*dev
= crtc
->base
.dev
;
5406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5409 tmp
= I915_READ(PFIT_CONTROL
);
5410 if (!(tmp
& PFIT_ENABLE
))
5413 /* Check whether the pfit is attached to our pipe. */
5414 if (INTEL_INFO(dev
)->gen
< 4) {
5415 if (crtc
->pipe
!= PIPE_B
)
5418 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5422 pipe_config
->gmch_pfit
.control
= tmp
;
5423 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5424 if (INTEL_INFO(dev
)->gen
< 5)
5425 pipe_config
->gmch_pfit
.lvds_border_bits
=
5426 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5429 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5430 struct intel_crtc_config
*pipe_config
)
5432 struct drm_device
*dev
= crtc
->base
.dev
;
5433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5434 int pipe
= pipe_config
->cpu_transcoder
;
5435 intel_clock_t clock
;
5437 int refclk
= 100000;
5439 mutex_lock(&dev_priv
->dpio_lock
);
5440 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
5441 mutex_unlock(&dev_priv
->dpio_lock
);
5443 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5444 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5445 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5446 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5447 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5449 vlv_clock(refclk
, &clock
);
5451 /* clock.dot is the fast clock */
5452 pipe_config
->port_clock
= clock
.dot
/ 5;
5455 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5456 struct intel_crtc_config
*pipe_config
)
5458 struct drm_device
*dev
= crtc
->base
.dev
;
5459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5462 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5463 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5465 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5466 if (!(tmp
& PIPECONF_ENABLE
))
5469 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5470 switch (tmp
& PIPECONF_BPC_MASK
) {
5472 pipe_config
->pipe_bpp
= 18;
5475 pipe_config
->pipe_bpp
= 24;
5477 case PIPECONF_10BPC
:
5478 pipe_config
->pipe_bpp
= 30;
5485 if (INTEL_INFO(dev
)->gen
< 4)
5486 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5488 intel_get_pipe_timings(crtc
, pipe_config
);
5490 i9xx_get_pfit_config(crtc
, pipe_config
);
5492 if (INTEL_INFO(dev
)->gen
>= 4) {
5493 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5494 pipe_config
->pixel_multiplier
=
5495 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5496 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5497 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5498 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5499 tmp
= I915_READ(DPLL(crtc
->pipe
));
5500 pipe_config
->pixel_multiplier
=
5501 ((tmp
& SDVO_MULTIPLIER_MASK
)
5502 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5504 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5505 * port and will be fixed up in the encoder->get_config
5507 pipe_config
->pixel_multiplier
= 1;
5509 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5510 if (!IS_VALLEYVIEW(dev
)) {
5511 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5512 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5514 /* Mask out read-only status bits. */
5515 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5516 DPLL_PORTC_READY_MASK
|
5517 DPLL_PORTB_READY_MASK
);
5520 if (IS_VALLEYVIEW(dev
))
5521 vlv_crtc_clock_get(crtc
, pipe_config
);
5523 i9xx_crtc_clock_get(crtc
, pipe_config
);
5528 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5531 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5532 struct intel_encoder
*encoder
;
5534 bool has_lvds
= false;
5535 bool has_cpu_edp
= false;
5536 bool has_panel
= false;
5537 bool has_ck505
= false;
5538 bool can_ssc
= false;
5540 /* We need to take the global config into account */
5541 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5543 switch (encoder
->type
) {
5544 case INTEL_OUTPUT_LVDS
:
5548 case INTEL_OUTPUT_EDP
:
5550 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5556 if (HAS_PCH_IBX(dev
)) {
5557 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5558 can_ssc
= has_ck505
;
5564 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5565 has_panel
, has_lvds
, has_ck505
);
5567 /* Ironlake: try to setup display ref clock before DPLL
5568 * enabling. This is only under driver's control after
5569 * PCH B stepping, previous chipset stepping should be
5570 * ignoring this setting.
5572 val
= I915_READ(PCH_DREF_CONTROL
);
5574 /* As we must carefully and slowly disable/enable each source in turn,
5575 * compute the final state we want first and check if we need to
5576 * make any changes at all.
5579 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5581 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5583 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5585 final
&= ~DREF_SSC_SOURCE_MASK
;
5586 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5587 final
&= ~DREF_SSC1_ENABLE
;
5590 final
|= DREF_SSC_SOURCE_ENABLE
;
5592 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5593 final
|= DREF_SSC1_ENABLE
;
5596 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5597 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5599 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5601 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5603 final
|= DREF_SSC_SOURCE_DISABLE
;
5604 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5610 /* Always enable nonspread source */
5611 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5614 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5616 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5619 val
&= ~DREF_SSC_SOURCE_MASK
;
5620 val
|= DREF_SSC_SOURCE_ENABLE
;
5622 /* SSC must be turned on before enabling the CPU output */
5623 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5624 DRM_DEBUG_KMS("Using SSC on panel\n");
5625 val
|= DREF_SSC1_ENABLE
;
5627 val
&= ~DREF_SSC1_ENABLE
;
5629 /* Get SSC going before enabling the outputs */
5630 I915_WRITE(PCH_DREF_CONTROL
, val
);
5631 POSTING_READ(PCH_DREF_CONTROL
);
5634 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5636 /* Enable CPU source on CPU attached eDP */
5638 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5639 DRM_DEBUG_KMS("Using SSC on eDP\n");
5640 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5643 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5645 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5647 I915_WRITE(PCH_DREF_CONTROL
, val
);
5648 POSTING_READ(PCH_DREF_CONTROL
);
5651 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5653 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5655 /* Turn off CPU output */
5656 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5658 I915_WRITE(PCH_DREF_CONTROL
, val
);
5659 POSTING_READ(PCH_DREF_CONTROL
);
5662 /* Turn off the SSC source */
5663 val
&= ~DREF_SSC_SOURCE_MASK
;
5664 val
|= DREF_SSC_SOURCE_DISABLE
;
5667 val
&= ~DREF_SSC1_ENABLE
;
5669 I915_WRITE(PCH_DREF_CONTROL
, val
);
5670 POSTING_READ(PCH_DREF_CONTROL
);
5674 BUG_ON(val
!= final
);
5677 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5681 tmp
= I915_READ(SOUTH_CHICKEN2
);
5682 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5683 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5685 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5686 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5687 DRM_ERROR("FDI mPHY reset assert timeout\n");
5689 tmp
= I915_READ(SOUTH_CHICKEN2
);
5690 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5691 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5693 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5694 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5695 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5698 /* WaMPhyProgramming:hsw */
5699 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5703 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5704 tmp
&= ~(0xFF << 24);
5705 tmp
|= (0x12 << 24);
5706 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5708 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5710 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5712 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5714 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5716 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5717 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5718 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5720 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5721 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5722 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5724 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5727 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5729 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5732 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5734 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5737 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5739 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5742 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5744 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5745 tmp
&= ~(0xFF << 16);
5746 tmp
|= (0x1C << 16);
5747 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5749 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5750 tmp
&= ~(0xFF << 16);
5751 tmp
|= (0x1C << 16);
5752 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5754 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5756 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5758 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5760 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5762 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5763 tmp
&= ~(0xF << 28);
5765 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5767 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5768 tmp
&= ~(0xF << 28);
5770 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5773 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5774 * Programming" based on the parameters passed:
5775 * - Sequence to enable CLKOUT_DP
5776 * - Sequence to enable CLKOUT_DP without spread
5777 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5779 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5785 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5787 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5788 with_fdi
, "LP PCH doesn't have FDI\n"))
5791 mutex_lock(&dev_priv
->dpio_lock
);
5793 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5794 tmp
&= ~SBI_SSCCTL_DISABLE
;
5795 tmp
|= SBI_SSCCTL_PATHALT
;
5796 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5801 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5802 tmp
&= ~SBI_SSCCTL_PATHALT
;
5803 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5806 lpt_reset_fdi_mphy(dev_priv
);
5807 lpt_program_fdi_mphy(dev_priv
);
5811 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5812 SBI_GEN0
: SBI_DBUFF0
;
5813 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5814 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5815 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5817 mutex_unlock(&dev_priv
->dpio_lock
);
5820 /* Sequence to disable CLKOUT_DP */
5821 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5826 mutex_lock(&dev_priv
->dpio_lock
);
5828 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5829 SBI_GEN0
: SBI_DBUFF0
;
5830 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5831 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5832 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5834 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5835 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5836 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5837 tmp
|= SBI_SSCCTL_PATHALT
;
5838 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5841 tmp
|= SBI_SSCCTL_DISABLE
;
5842 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5845 mutex_unlock(&dev_priv
->dpio_lock
);
5848 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5850 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5851 struct intel_encoder
*encoder
;
5852 bool has_vga
= false;
5854 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5855 switch (encoder
->type
) {
5856 case INTEL_OUTPUT_ANALOG
:
5863 lpt_enable_clkout_dp(dev
, true, true);
5865 lpt_disable_clkout_dp(dev
);
5869 * Initialize reference clocks when the driver loads
5871 void intel_init_pch_refclk(struct drm_device
*dev
)
5873 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5874 ironlake_init_pch_refclk(dev
);
5875 else if (HAS_PCH_LPT(dev
))
5876 lpt_init_pch_refclk(dev
);
5879 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5881 struct drm_device
*dev
= crtc
->dev
;
5882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5883 struct intel_encoder
*encoder
;
5884 int num_connectors
= 0;
5885 bool is_lvds
= false;
5887 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5888 switch (encoder
->type
) {
5889 case INTEL_OUTPUT_LVDS
:
5896 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5897 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5898 dev_priv
->vbt
.lvds_ssc_freq
);
5899 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5905 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5907 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5908 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5909 int pipe
= intel_crtc
->pipe
;
5914 switch (intel_crtc
->config
.pipe_bpp
) {
5916 val
|= PIPECONF_6BPC
;
5919 val
|= PIPECONF_8BPC
;
5922 val
|= PIPECONF_10BPC
;
5925 val
|= PIPECONF_12BPC
;
5928 /* Case prevented by intel_choose_pipe_bpp_dither. */
5932 if (intel_crtc
->config
.dither
)
5933 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5935 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5936 val
|= PIPECONF_INTERLACED_ILK
;
5938 val
|= PIPECONF_PROGRESSIVE
;
5940 if (intel_crtc
->config
.limited_color_range
)
5941 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5943 I915_WRITE(PIPECONF(pipe
), val
);
5944 POSTING_READ(PIPECONF(pipe
));
5948 * Set up the pipe CSC unit.
5950 * Currently only full range RGB to limited range RGB conversion
5951 * is supported, but eventually this should handle various
5952 * RGB<->YCbCr scenarios as well.
5954 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5956 struct drm_device
*dev
= crtc
->dev
;
5957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5958 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5959 int pipe
= intel_crtc
->pipe
;
5960 uint16_t coeff
= 0x7800; /* 1.0 */
5963 * TODO: Check what kind of values actually come out of the pipe
5964 * with these coeff/postoff values and adjust to get the best
5965 * accuracy. Perhaps we even need to take the bpc value into
5969 if (intel_crtc
->config
.limited_color_range
)
5970 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5973 * GY/GU and RY/RU should be the other way around according
5974 * to BSpec, but reality doesn't agree. Just set them up in
5975 * a way that results in the correct picture.
5977 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5978 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5980 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5981 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5983 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5984 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5986 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5987 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5988 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5990 if (INTEL_INFO(dev
)->gen
> 6) {
5991 uint16_t postoff
= 0;
5993 if (intel_crtc
->config
.limited_color_range
)
5994 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5996 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5997 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5998 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6000 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6002 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6004 if (intel_crtc
->config
.limited_color_range
)
6005 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6007 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6011 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6013 struct drm_device
*dev
= crtc
->dev
;
6014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6016 enum pipe pipe
= intel_crtc
->pipe
;
6017 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6022 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6023 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6025 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6026 val
|= PIPECONF_INTERLACED_ILK
;
6028 val
|= PIPECONF_PROGRESSIVE
;
6030 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6031 POSTING_READ(PIPECONF(cpu_transcoder
));
6033 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6034 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6036 if (IS_BROADWELL(dev
)) {
6039 switch (intel_crtc
->config
.pipe_bpp
) {
6041 val
|= PIPEMISC_DITHER_6_BPC
;
6044 val
|= PIPEMISC_DITHER_8_BPC
;
6047 val
|= PIPEMISC_DITHER_10_BPC
;
6050 val
|= PIPEMISC_DITHER_12_BPC
;
6053 /* Case prevented by pipe_config_set_bpp. */
6057 if (intel_crtc
->config
.dither
)
6058 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6060 I915_WRITE(PIPEMISC(pipe
), val
);
6064 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6065 intel_clock_t
*clock
,
6066 bool *has_reduced_clock
,
6067 intel_clock_t
*reduced_clock
)
6069 struct drm_device
*dev
= crtc
->dev
;
6070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6071 struct intel_encoder
*intel_encoder
;
6073 const intel_limit_t
*limit
;
6074 bool ret
, is_lvds
= false;
6076 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6077 switch (intel_encoder
->type
) {
6078 case INTEL_OUTPUT_LVDS
:
6084 refclk
= ironlake_get_refclk(crtc
);
6087 * Returns a set of divisors for the desired target clock with the given
6088 * refclk, or FALSE. The returned values represent the clock equation:
6089 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6091 limit
= intel_limit(crtc
, refclk
);
6092 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6093 to_intel_crtc(crtc
)->config
.port_clock
,
6094 refclk
, NULL
, clock
);
6098 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6100 * Ensure we match the reduced clock's P to the target clock.
6101 * If the clocks don't match, we can't switch the display clock
6102 * by using the FP0/FP1. In such case we will disable the LVDS
6103 * downclock feature.
6105 *has_reduced_clock
=
6106 dev_priv
->display
.find_dpll(limit
, crtc
,
6107 dev_priv
->lvds_downclock
,
6115 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
6118 * Account for spread spectrum to avoid
6119 * oversubscribing the link. Max center spread
6120 * is 2.5%; use 5% for safety's sake.
6122 u32 bps
= target_clock
* bpp
* 21 / 20;
6123 return bps
/ (link_bw
* 8) + 1;
6126 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
6128 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
6131 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
6133 intel_clock_t
*reduced_clock
, u32
*fp2
)
6135 struct drm_crtc
*crtc
= &intel_crtc
->base
;
6136 struct drm_device
*dev
= crtc
->dev
;
6137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6138 struct intel_encoder
*intel_encoder
;
6140 int factor
, num_connectors
= 0;
6141 bool is_lvds
= false, is_sdvo
= false;
6143 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6144 switch (intel_encoder
->type
) {
6145 case INTEL_OUTPUT_LVDS
:
6148 case INTEL_OUTPUT_SDVO
:
6149 case INTEL_OUTPUT_HDMI
:
6157 /* Enable autotuning of the PLL clock (if permissible) */
6160 if ((intel_panel_use_ssc(dev_priv
) &&
6161 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
6162 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
6164 } else if (intel_crtc
->config
.sdvo_tv_clock
)
6167 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
6170 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
6176 dpll
|= DPLLB_MODE_LVDS
;
6178 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6180 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
6181 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
6184 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6185 if (intel_crtc
->config
.has_dp_encoder
)
6186 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6188 /* compute bitmask from p1 value */
6189 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6191 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6193 switch (intel_crtc
->config
.dpll
.p2
) {
6195 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6198 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6201 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6204 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6208 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6209 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6211 dpll
|= PLL_REF_INPUT_DREFCLK
;
6213 return dpll
| DPLL_VCO_ENABLE
;
6216 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
6218 struct drm_framebuffer
*fb
)
6220 struct drm_device
*dev
= crtc
->dev
;
6221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6223 int pipe
= intel_crtc
->pipe
;
6224 int plane
= intel_crtc
->plane
;
6225 int num_connectors
= 0;
6226 intel_clock_t clock
, reduced_clock
;
6227 u32 dpll
= 0, fp
= 0, fp2
= 0;
6228 bool ok
, has_reduced_clock
= false;
6229 bool is_lvds
= false;
6230 struct intel_encoder
*encoder
;
6231 struct intel_shared_dpll
*pll
;
6234 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6235 switch (encoder
->type
) {
6236 case INTEL_OUTPUT_LVDS
:
6244 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
6245 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
6247 ok
= ironlake_compute_clocks(crtc
, &clock
,
6248 &has_reduced_clock
, &reduced_clock
);
6249 if (!ok
&& !intel_crtc
->config
.clock_set
) {
6250 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6253 /* Compat-code for transition, will disappear. */
6254 if (!intel_crtc
->config
.clock_set
) {
6255 intel_crtc
->config
.dpll
.n
= clock
.n
;
6256 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6257 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6258 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6259 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6262 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6263 if (intel_crtc
->config
.has_pch_encoder
) {
6264 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
6265 if (has_reduced_clock
)
6266 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
6268 dpll
= ironlake_compute_dpll(intel_crtc
,
6269 &fp
, &reduced_clock
,
6270 has_reduced_clock
? &fp2
: NULL
);
6272 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6273 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
6274 if (has_reduced_clock
)
6275 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
6277 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
6279 pll
= intel_get_shared_dpll(intel_crtc
);
6281 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6286 intel_put_shared_dpll(intel_crtc
);
6288 if (intel_crtc
->config
.has_dp_encoder
)
6289 intel_dp_set_m_n(intel_crtc
);
6291 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
6292 intel_crtc
->lowfreq_avail
= true;
6294 intel_crtc
->lowfreq_avail
= false;
6296 intel_set_pipe_timings(intel_crtc
);
6298 if (intel_crtc
->config
.has_pch_encoder
) {
6299 intel_cpu_transcoder_set_m_n(intel_crtc
,
6300 &intel_crtc
->config
.fdi_m_n
);
6303 ironlake_set_pipeconf(crtc
);
6305 /* Set up the display plane register */
6306 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
6307 POSTING_READ(DSPCNTR(plane
));
6309 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6314 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
6315 struct intel_link_m_n
*m_n
)
6317 struct drm_device
*dev
= crtc
->base
.dev
;
6318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6319 enum pipe pipe
= crtc
->pipe
;
6321 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
6322 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
6323 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
6325 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
6326 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
6327 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6330 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6331 enum transcoder transcoder
,
6332 struct intel_link_m_n
*m_n
)
6334 struct drm_device
*dev
= crtc
->base
.dev
;
6335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6336 enum pipe pipe
= crtc
->pipe
;
6338 if (INTEL_INFO(dev
)->gen
>= 5) {
6339 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6340 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6341 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6343 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6344 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6345 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6347 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6348 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6349 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6351 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6352 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6353 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6357 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6358 struct intel_crtc_config
*pipe_config
)
6360 if (crtc
->config
.has_pch_encoder
)
6361 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6363 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6364 &pipe_config
->dp_m_n
);
6367 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6368 struct intel_crtc_config
*pipe_config
)
6370 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6371 &pipe_config
->fdi_m_n
);
6374 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6375 struct intel_crtc_config
*pipe_config
)
6377 struct drm_device
*dev
= crtc
->base
.dev
;
6378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6381 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6383 if (tmp
& PF_ENABLE
) {
6384 pipe_config
->pch_pfit
.enabled
= true;
6385 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6386 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6388 /* We currently do not free assignements of panel fitters on
6389 * ivb/hsw (since we don't use the higher upscaling modes which
6390 * differentiates them) so just WARN about this case for now. */
6392 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6393 PF_PIPE_SEL_IVB(crtc
->pipe
));
6398 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6399 struct intel_crtc_config
*pipe_config
)
6401 struct drm_device
*dev
= crtc
->base
.dev
;
6402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6405 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6406 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6408 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6409 if (!(tmp
& PIPECONF_ENABLE
))
6412 switch (tmp
& PIPECONF_BPC_MASK
) {
6414 pipe_config
->pipe_bpp
= 18;
6417 pipe_config
->pipe_bpp
= 24;
6419 case PIPECONF_10BPC
:
6420 pipe_config
->pipe_bpp
= 30;
6422 case PIPECONF_12BPC
:
6423 pipe_config
->pipe_bpp
= 36;
6429 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6430 struct intel_shared_dpll
*pll
;
6432 pipe_config
->has_pch_encoder
= true;
6434 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6435 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6436 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6438 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6440 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6441 pipe_config
->shared_dpll
=
6442 (enum intel_dpll_id
) crtc
->pipe
;
6444 tmp
= I915_READ(PCH_DPLL_SEL
);
6445 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6446 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6448 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6451 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6453 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6454 &pipe_config
->dpll_hw_state
));
6456 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6457 pipe_config
->pixel_multiplier
=
6458 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6459 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6461 ironlake_pch_clock_get(crtc
, pipe_config
);
6463 pipe_config
->pixel_multiplier
= 1;
6466 intel_get_pipe_timings(crtc
, pipe_config
);
6468 ironlake_get_pfit_config(crtc
, pipe_config
);
6473 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6475 struct drm_device
*dev
= dev_priv
->dev
;
6476 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6477 struct intel_crtc
*crtc
;
6478 unsigned long irqflags
;
6481 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6482 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6483 pipe_name(crtc
->pipe
));
6485 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6486 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6487 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6488 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6489 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6490 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6491 "CPU PWM1 enabled\n");
6492 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6493 "CPU PWM2 enabled\n");
6494 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6495 "PCH PWM1 enabled\n");
6496 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6497 "Utility pin enabled\n");
6498 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6500 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6501 val
= I915_READ(DEIMR
);
6502 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6503 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6504 val
= I915_READ(SDEIMR
);
6505 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6506 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6507 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6511 * This function implements pieces of two sequences from BSpec:
6512 * - Sequence for display software to disable LCPLL
6513 * - Sequence for display software to allow package C8+
6514 * The steps implemented here are just the steps that actually touch the LCPLL
6515 * register. Callers should take care of disabling all the display engine
6516 * functions, doing the mode unset, fixing interrupts, etc.
6518 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6519 bool switch_to_fclk
, bool allow_power_down
)
6523 assert_can_disable_lcpll(dev_priv
);
6525 val
= I915_READ(LCPLL_CTL
);
6527 if (switch_to_fclk
) {
6528 val
|= LCPLL_CD_SOURCE_FCLK
;
6529 I915_WRITE(LCPLL_CTL
, val
);
6531 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6532 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6533 DRM_ERROR("Switching to FCLK failed\n");
6535 val
= I915_READ(LCPLL_CTL
);
6538 val
|= LCPLL_PLL_DISABLE
;
6539 I915_WRITE(LCPLL_CTL
, val
);
6540 POSTING_READ(LCPLL_CTL
);
6542 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6543 DRM_ERROR("LCPLL still locked\n");
6545 val
= I915_READ(D_COMP
);
6546 val
|= D_COMP_COMP_DISABLE
;
6547 mutex_lock(&dev_priv
->rps
.hw_lock
);
6548 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6549 DRM_ERROR("Failed to disable D_COMP\n");
6550 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6551 POSTING_READ(D_COMP
);
6554 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6555 DRM_ERROR("D_COMP RCOMP still in progress\n");
6557 if (allow_power_down
) {
6558 val
= I915_READ(LCPLL_CTL
);
6559 val
|= LCPLL_POWER_DOWN_ALLOW
;
6560 I915_WRITE(LCPLL_CTL
, val
);
6561 POSTING_READ(LCPLL_CTL
);
6566 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6569 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6573 val
= I915_READ(LCPLL_CTL
);
6575 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6576 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6579 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6580 * we'll hang the machine! */
6581 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6583 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6584 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6585 I915_WRITE(LCPLL_CTL
, val
);
6586 POSTING_READ(LCPLL_CTL
);
6589 val
= I915_READ(D_COMP
);
6590 val
|= D_COMP_COMP_FORCE
;
6591 val
&= ~D_COMP_COMP_DISABLE
;
6592 mutex_lock(&dev_priv
->rps
.hw_lock
);
6593 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6594 DRM_ERROR("Failed to enable D_COMP\n");
6595 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6596 POSTING_READ(D_COMP
);
6598 val
= I915_READ(LCPLL_CTL
);
6599 val
&= ~LCPLL_PLL_DISABLE
;
6600 I915_WRITE(LCPLL_CTL
, val
);
6602 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6603 DRM_ERROR("LCPLL not locked yet\n");
6605 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6606 val
= I915_READ(LCPLL_CTL
);
6607 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6608 I915_WRITE(LCPLL_CTL
, val
);
6610 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6611 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6612 DRM_ERROR("Switching back to LCPLL failed\n");
6615 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6618 void hsw_enable_pc8_work(struct work_struct
*__work
)
6620 struct drm_i915_private
*dev_priv
=
6621 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6623 struct drm_device
*dev
= dev_priv
->dev
;
6626 if (dev_priv
->pc8
.enabled
)
6629 DRM_DEBUG_KMS("Enabling package C8+\n");
6631 dev_priv
->pc8
.enabled
= true;
6633 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6634 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6635 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6636 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6639 lpt_disable_clkout_dp(dev
);
6640 hsw_pc8_disable_interrupts(dev
);
6641 hsw_disable_lcpll(dev_priv
, true, true);
6644 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6646 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6647 WARN(dev_priv
->pc8
.disable_count
< 1,
6648 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6650 dev_priv
->pc8
.disable_count
--;
6651 if (dev_priv
->pc8
.disable_count
!= 0)
6654 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6655 msecs_to_jiffies(i915_pc8_timeout
));
6658 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6660 struct drm_device
*dev
= dev_priv
->dev
;
6663 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6664 WARN(dev_priv
->pc8
.disable_count
< 0,
6665 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6667 dev_priv
->pc8
.disable_count
++;
6668 if (dev_priv
->pc8
.disable_count
!= 1)
6671 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6672 if (!dev_priv
->pc8
.enabled
)
6675 DRM_DEBUG_KMS("Disabling package C8+\n");
6677 hsw_restore_lcpll(dev_priv
);
6678 hsw_pc8_restore_interrupts(dev
);
6679 lpt_init_pch_refclk(dev
);
6681 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6682 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6683 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6684 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6687 intel_prepare_ddi(dev
);
6688 i915_gem_init_swizzling(dev
);
6689 mutex_lock(&dev_priv
->rps
.hw_lock
);
6690 gen6_update_ring_freq(dev
);
6691 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6692 dev_priv
->pc8
.enabled
= false;
6695 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6697 mutex_lock(&dev_priv
->pc8
.lock
);
6698 __hsw_enable_package_c8(dev_priv
);
6699 mutex_unlock(&dev_priv
->pc8
.lock
);
6702 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6704 mutex_lock(&dev_priv
->pc8
.lock
);
6705 __hsw_disable_package_c8(dev_priv
);
6706 mutex_unlock(&dev_priv
->pc8
.lock
);
6709 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6711 struct drm_device
*dev
= dev_priv
->dev
;
6712 struct intel_crtc
*crtc
;
6715 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6716 if (crtc
->base
.enabled
)
6719 /* This case is still possible since we have the i915.disable_power_well
6720 * parameter and also the KVMr or something else might be requesting the
6722 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6724 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6731 /* Since we're called from modeset_global_resources there's no way to
6732 * symmetrically increase and decrease the refcount, so we use
6733 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6736 static void hsw_update_package_c8(struct drm_device
*dev
)
6738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6741 if (!i915_enable_pc8
)
6744 mutex_lock(&dev_priv
->pc8
.lock
);
6746 allow
= hsw_can_enable_package_c8(dev_priv
);
6748 if (allow
== dev_priv
->pc8
.requirements_met
)
6751 dev_priv
->pc8
.requirements_met
= allow
;
6754 __hsw_enable_package_c8(dev_priv
);
6756 __hsw_disable_package_c8(dev_priv
);
6759 mutex_unlock(&dev_priv
->pc8
.lock
);
6762 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6764 mutex_lock(&dev_priv
->pc8
.lock
);
6765 if (!dev_priv
->pc8
.gpu_idle
) {
6766 dev_priv
->pc8
.gpu_idle
= true;
6767 __hsw_enable_package_c8(dev_priv
);
6769 mutex_unlock(&dev_priv
->pc8
.lock
);
6772 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6774 mutex_lock(&dev_priv
->pc8
.lock
);
6775 if (dev_priv
->pc8
.gpu_idle
) {
6776 dev_priv
->pc8
.gpu_idle
= false;
6777 __hsw_disable_package_c8(dev_priv
);
6779 mutex_unlock(&dev_priv
->pc8
.lock
);
6782 #define for_each_power_domain(domain, mask) \
6783 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6784 if ((1 << (domain)) & (mask))
6786 static unsigned long get_pipe_power_domains(struct drm_device
*dev
,
6787 enum pipe pipe
, bool pfit_enabled
)
6790 enum transcoder transcoder
;
6792 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
6794 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
6795 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
6797 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
6802 void intel_display_set_init_power(struct drm_device
*dev
, bool enable
)
6804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6806 if (dev_priv
->power_domains
.init_power_on
== enable
)
6810 intel_display_power_get(dev
, POWER_DOMAIN_INIT
);
6812 intel_display_power_put(dev
, POWER_DOMAIN_INIT
);
6814 dev_priv
->power_domains
.init_power_on
= enable
;
6817 static void modeset_update_power_wells(struct drm_device
*dev
)
6819 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
6820 struct intel_crtc
*crtc
;
6823 * First get all needed power domains, then put all unneeded, to avoid
6824 * any unnecessary toggling of the power wells.
6826 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6827 enum intel_display_power_domain domain
;
6829 if (!crtc
->base
.enabled
)
6832 pipe_domains
[crtc
->pipe
] = get_pipe_power_domains(dev
,
6834 crtc
->config
.pch_pfit
.enabled
);
6836 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
6837 intel_display_power_get(dev
, domain
);
6840 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6841 enum intel_display_power_domain domain
;
6843 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
6844 intel_display_power_put(dev
, domain
);
6846 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
6849 intel_display_set_init_power(dev
, false);
6852 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6854 modeset_update_power_wells(dev
);
6855 hsw_update_package_c8(dev
);
6858 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6860 struct drm_framebuffer
*fb
)
6862 struct drm_device
*dev
= crtc
->dev
;
6863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6864 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6865 int plane
= intel_crtc
->plane
;
6868 if (!intel_ddi_pll_mode_set(crtc
))
6871 if (intel_crtc
->config
.has_dp_encoder
)
6872 intel_dp_set_m_n(intel_crtc
);
6874 intel_crtc
->lowfreq_avail
= false;
6876 intel_set_pipe_timings(intel_crtc
);
6878 if (intel_crtc
->config
.has_pch_encoder
) {
6879 intel_cpu_transcoder_set_m_n(intel_crtc
,
6880 &intel_crtc
->config
.fdi_m_n
);
6883 haswell_set_pipeconf(crtc
);
6885 intel_set_pipe_csc(crtc
);
6887 /* Set up the display plane register */
6888 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6889 POSTING_READ(DSPCNTR(plane
));
6891 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6896 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6897 struct intel_crtc_config
*pipe_config
)
6899 struct drm_device
*dev
= crtc
->base
.dev
;
6900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6901 enum intel_display_power_domain pfit_domain
;
6904 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6905 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6907 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6908 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6909 enum pipe trans_edp_pipe
;
6910 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6912 WARN(1, "unknown pipe linked to edp transcoder\n");
6913 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6914 case TRANS_DDI_EDP_INPUT_A_ON
:
6915 trans_edp_pipe
= PIPE_A
;
6917 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6918 trans_edp_pipe
= PIPE_B
;
6920 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6921 trans_edp_pipe
= PIPE_C
;
6925 if (trans_edp_pipe
== crtc
->pipe
)
6926 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6929 if (!intel_display_power_enabled(dev
,
6930 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6933 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6934 if (!(tmp
& PIPECONF_ENABLE
))
6938 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6939 * DDI E. So just check whether this pipe is wired to DDI E and whether
6940 * the PCH transcoder is on.
6942 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6943 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6944 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6945 pipe_config
->has_pch_encoder
= true;
6947 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6948 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6949 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6951 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6954 intel_get_pipe_timings(crtc
, pipe_config
);
6956 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6957 if (intel_display_power_enabled(dev
, pfit_domain
))
6958 ironlake_get_pfit_config(crtc
, pipe_config
);
6960 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6961 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6963 pipe_config
->pixel_multiplier
= 1;
6968 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6970 struct drm_framebuffer
*fb
)
6972 struct drm_device
*dev
= crtc
->dev
;
6973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6974 struct intel_encoder
*encoder
;
6975 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6976 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6977 int pipe
= intel_crtc
->pipe
;
6980 drm_vblank_pre_modeset(dev
, pipe
);
6982 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6984 drm_vblank_post_modeset(dev
, pipe
);
6989 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6990 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6991 encoder
->base
.base
.id
,
6992 drm_get_encoder_name(&encoder
->base
),
6993 mode
->base
.id
, mode
->name
);
6994 encoder
->mode_set(encoder
);
7003 } hdmi_audio_clock
[] = {
7004 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7005 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7006 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7007 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7008 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7009 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7010 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7011 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7012 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7013 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7016 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7017 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7021 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7022 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7026 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7027 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7031 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7032 hdmi_audio_clock
[i
].clock
,
7033 hdmi_audio_clock
[i
].config
);
7035 return hdmi_audio_clock
[i
].config
;
7038 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7039 int reg_eldv
, uint32_t bits_eldv
,
7040 int reg_elda
, uint32_t bits_elda
,
7043 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7044 uint8_t *eld
= connector
->eld
;
7047 i
= I915_READ(reg_eldv
);
7056 i
= I915_READ(reg_elda
);
7058 I915_WRITE(reg_elda
, i
);
7060 for (i
= 0; i
< eld
[2]; i
++)
7061 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7067 static void g4x_write_eld(struct drm_connector
*connector
,
7068 struct drm_crtc
*crtc
,
7069 struct drm_display_mode
*mode
)
7071 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7072 uint8_t *eld
= connector
->eld
;
7077 i
= I915_READ(G4X_AUD_VID_DID
);
7079 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7080 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7082 eldv
= G4X_ELDV_DEVCTG
;
7084 if (intel_eld_uptodate(connector
,
7085 G4X_AUD_CNTL_ST
, eldv
,
7086 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7087 G4X_HDMIW_HDMIEDID
))
7090 i
= I915_READ(G4X_AUD_CNTL_ST
);
7091 i
&= ~(eldv
| G4X_ELD_ADDR
);
7092 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7093 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7098 len
= min_t(uint8_t, eld
[2], len
);
7099 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7100 for (i
= 0; i
< len
; i
++)
7101 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7103 i
= I915_READ(G4X_AUD_CNTL_ST
);
7105 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7108 static void haswell_write_eld(struct drm_connector
*connector
,
7109 struct drm_crtc
*crtc
,
7110 struct drm_display_mode
*mode
)
7112 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7113 uint8_t *eld
= connector
->eld
;
7114 struct drm_device
*dev
= crtc
->dev
;
7115 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7119 int pipe
= to_intel_crtc(crtc
)->pipe
;
7122 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7123 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7124 int aud_config
= HSW_AUD_CFG(pipe
);
7125 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7128 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7130 /* Audio output enable */
7131 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7132 tmp
= I915_READ(aud_cntrl_st2
);
7133 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7134 I915_WRITE(aud_cntrl_st2
, tmp
);
7136 /* Wait for 1 vertical blank */
7137 intel_wait_for_vblank(dev
, pipe
);
7139 /* Set ELD valid state */
7140 tmp
= I915_READ(aud_cntrl_st2
);
7141 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7142 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7143 I915_WRITE(aud_cntrl_st2
, tmp
);
7144 tmp
= I915_READ(aud_cntrl_st2
);
7145 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7147 /* Enable HDMI mode */
7148 tmp
= I915_READ(aud_config
);
7149 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7150 /* clear N_programing_enable and N_value_index */
7151 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7152 I915_WRITE(aud_config
, tmp
);
7154 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7156 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7157 intel_crtc
->eld_vld
= true;
7159 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7160 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7161 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7162 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7164 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7167 if (intel_eld_uptodate(connector
,
7168 aud_cntrl_st2
, eldv
,
7169 aud_cntl_st
, IBX_ELD_ADDRESS
,
7173 i
= I915_READ(aud_cntrl_st2
);
7175 I915_WRITE(aud_cntrl_st2
, i
);
7180 i
= I915_READ(aud_cntl_st
);
7181 i
&= ~IBX_ELD_ADDRESS
;
7182 I915_WRITE(aud_cntl_st
, i
);
7183 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7184 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7186 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7187 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7188 for (i
= 0; i
< len
; i
++)
7189 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7191 i
= I915_READ(aud_cntrl_st2
);
7193 I915_WRITE(aud_cntrl_st2
, i
);
7197 static void ironlake_write_eld(struct drm_connector
*connector
,
7198 struct drm_crtc
*crtc
,
7199 struct drm_display_mode
*mode
)
7201 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7202 uint8_t *eld
= connector
->eld
;
7210 int pipe
= to_intel_crtc(crtc
)->pipe
;
7212 if (HAS_PCH_IBX(connector
->dev
)) {
7213 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
7214 aud_config
= IBX_AUD_CFG(pipe
);
7215 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
7216 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
7217 } else if (IS_VALLEYVIEW(connector
->dev
)) {
7218 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
7219 aud_config
= VLV_AUD_CFG(pipe
);
7220 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
7221 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
7223 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
7224 aud_config
= CPT_AUD_CFG(pipe
);
7225 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
7226 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
7229 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7231 if (IS_VALLEYVIEW(connector
->dev
)) {
7232 struct intel_encoder
*intel_encoder
;
7233 struct intel_digital_port
*intel_dig_port
;
7235 intel_encoder
= intel_attached_encoder(connector
);
7236 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
7237 i
= intel_dig_port
->port
;
7239 i
= I915_READ(aud_cntl_st
);
7240 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
7241 /* DIP_Port_Select, 0x1 = PortB */
7245 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7246 /* operate blindly on all ports */
7247 eldv
= IBX_ELD_VALIDB
;
7248 eldv
|= IBX_ELD_VALIDB
<< 4;
7249 eldv
|= IBX_ELD_VALIDB
<< 8;
7251 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
7252 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
7255 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7256 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7257 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7258 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7260 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7263 if (intel_eld_uptodate(connector
,
7264 aud_cntrl_st2
, eldv
,
7265 aud_cntl_st
, IBX_ELD_ADDRESS
,
7269 i
= I915_READ(aud_cntrl_st2
);
7271 I915_WRITE(aud_cntrl_st2
, i
);
7276 i
= I915_READ(aud_cntl_st
);
7277 i
&= ~IBX_ELD_ADDRESS
;
7278 I915_WRITE(aud_cntl_st
, i
);
7280 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7281 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7282 for (i
= 0; i
< len
; i
++)
7283 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7285 i
= I915_READ(aud_cntrl_st2
);
7287 I915_WRITE(aud_cntrl_st2
, i
);
7290 void intel_write_eld(struct drm_encoder
*encoder
,
7291 struct drm_display_mode
*mode
)
7293 struct drm_crtc
*crtc
= encoder
->crtc
;
7294 struct drm_connector
*connector
;
7295 struct drm_device
*dev
= encoder
->dev
;
7296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7298 connector
= drm_select_eld(encoder
, mode
);
7302 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7304 drm_get_connector_name(connector
),
7305 connector
->encoder
->base
.id
,
7306 drm_get_encoder_name(connector
->encoder
));
7308 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
7310 if (dev_priv
->display
.write_eld
)
7311 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
7314 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7316 struct drm_device
*dev
= crtc
->dev
;
7317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7318 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7319 bool visible
= base
!= 0;
7322 if (intel_crtc
->cursor_visible
== visible
)
7325 cntl
= I915_READ(_CURACNTR
);
7327 /* On these chipsets we can only modify the base whilst
7328 * the cursor is disabled.
7330 I915_WRITE(_CURABASE
, base
);
7332 cntl
&= ~(CURSOR_FORMAT_MASK
);
7333 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7334 cntl
|= CURSOR_ENABLE
|
7335 CURSOR_GAMMA_ENABLE
|
7338 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
7339 I915_WRITE(_CURACNTR
, cntl
);
7341 intel_crtc
->cursor_visible
= visible
;
7344 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7346 struct drm_device
*dev
= crtc
->dev
;
7347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7349 int pipe
= intel_crtc
->pipe
;
7350 bool visible
= base
!= 0;
7352 if (intel_crtc
->cursor_visible
!= visible
) {
7353 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
7355 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
7356 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7357 cntl
|= pipe
<< 28; /* Connect to correct pipe */
7359 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7360 cntl
|= CURSOR_MODE_DISABLE
;
7362 I915_WRITE(CURCNTR(pipe
), cntl
);
7364 intel_crtc
->cursor_visible
= visible
;
7366 /* and commit changes on next vblank */
7367 I915_WRITE(CURBASE(pipe
), base
);
7370 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7372 struct drm_device
*dev
= crtc
->dev
;
7373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7374 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7375 int pipe
= intel_crtc
->pipe
;
7376 bool visible
= base
!= 0;
7378 if (intel_crtc
->cursor_visible
!= visible
) {
7379 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
7381 cntl
&= ~CURSOR_MODE
;
7382 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7384 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7385 cntl
|= CURSOR_MODE_DISABLE
;
7387 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7388 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
7389 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
7391 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
7393 intel_crtc
->cursor_visible
= visible
;
7395 /* and commit changes on next vblank */
7396 I915_WRITE(CURBASE_IVB(pipe
), base
);
7399 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7400 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
7403 struct drm_device
*dev
= crtc
->dev
;
7404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7405 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7406 int pipe
= intel_crtc
->pipe
;
7407 int x
= intel_crtc
->cursor_x
;
7408 int y
= intel_crtc
->cursor_y
;
7409 u32 base
= 0, pos
= 0;
7413 base
= intel_crtc
->cursor_addr
;
7415 if (x
>= intel_crtc
->config
.pipe_src_w
)
7418 if (y
>= intel_crtc
->config
.pipe_src_h
)
7422 if (x
+ intel_crtc
->cursor_width
<= 0)
7425 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
7428 pos
|= x
<< CURSOR_X_SHIFT
;
7431 if (y
+ intel_crtc
->cursor_height
<= 0)
7434 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
7437 pos
|= y
<< CURSOR_Y_SHIFT
;
7439 visible
= base
!= 0;
7440 if (!visible
&& !intel_crtc
->cursor_visible
)
7443 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7444 I915_WRITE(CURPOS_IVB(pipe
), pos
);
7445 ivb_update_cursor(crtc
, base
);
7447 I915_WRITE(CURPOS(pipe
), pos
);
7448 if (IS_845G(dev
) || IS_I865G(dev
))
7449 i845_update_cursor(crtc
, base
);
7451 i9xx_update_cursor(crtc
, base
);
7455 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7456 struct drm_file
*file
,
7458 uint32_t width
, uint32_t height
)
7460 struct drm_device
*dev
= crtc
->dev
;
7461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7462 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7463 struct drm_i915_gem_object
*obj
;
7467 /* if we want to turn off the cursor ignore width and height */
7469 DRM_DEBUG_KMS("cursor off\n");
7472 mutex_lock(&dev
->struct_mutex
);
7476 /* Currently we only support 64x64 cursors */
7477 if (width
!= 64 || height
!= 64) {
7478 DRM_ERROR("we currently only support 64x64 cursors\n");
7482 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7483 if (&obj
->base
== NULL
)
7486 if (obj
->base
.size
< width
* height
* 4) {
7487 DRM_ERROR("buffer is to small\n");
7492 /* we only need to pin inside GTT if cursor is non-phy */
7493 mutex_lock(&dev
->struct_mutex
);
7494 if (!dev_priv
->info
->cursor_needs_physical
) {
7497 if (obj
->tiling_mode
) {
7498 DRM_ERROR("cursor cannot be tiled\n");
7503 /* Note that the w/a also requires 2 PTE of padding following
7504 * the bo. We currently fill all unused PTE with the shadow
7505 * page and so we should always have valid PTE following the
7506 * cursor preventing the VT-d warning.
7509 if (need_vtd_wa(dev
))
7510 alignment
= 64*1024;
7512 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7514 DRM_ERROR("failed to move cursor bo into the GTT\n");
7518 ret
= i915_gem_object_put_fence(obj
);
7520 DRM_ERROR("failed to release fence for cursor");
7524 addr
= i915_gem_obj_ggtt_offset(obj
);
7526 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7527 ret
= i915_gem_attach_phys_object(dev
, obj
,
7528 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7531 DRM_ERROR("failed to attach phys object\n");
7534 addr
= obj
->phys_obj
->handle
->busaddr
;
7538 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7541 if (intel_crtc
->cursor_bo
) {
7542 if (dev_priv
->info
->cursor_needs_physical
) {
7543 if (intel_crtc
->cursor_bo
!= obj
)
7544 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7546 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7547 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7550 mutex_unlock(&dev
->struct_mutex
);
7552 intel_crtc
->cursor_addr
= addr
;
7553 intel_crtc
->cursor_bo
= obj
;
7554 intel_crtc
->cursor_width
= width
;
7555 intel_crtc
->cursor_height
= height
;
7557 if (intel_crtc
->active
)
7558 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7562 i915_gem_object_unpin_from_display_plane(obj
);
7564 mutex_unlock(&dev
->struct_mutex
);
7566 drm_gem_object_unreference_unlocked(&obj
->base
);
7570 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7572 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7574 intel_crtc
->cursor_x
= clamp_t(int, x
, SHRT_MIN
, SHRT_MAX
);
7575 intel_crtc
->cursor_y
= clamp_t(int, y
, SHRT_MIN
, SHRT_MAX
);
7577 if (intel_crtc
->active
)
7578 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7583 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7584 u16
*blue
, uint32_t start
, uint32_t size
)
7586 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7587 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7589 for (i
= start
; i
< end
; i
++) {
7590 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7591 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7592 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7595 intel_crtc_load_lut(crtc
);
7598 /* VESA 640x480x72Hz mode to set on the pipe */
7599 static struct drm_display_mode load_detect_mode
= {
7600 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7601 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7604 static struct drm_framebuffer
*
7605 intel_framebuffer_create(struct drm_device
*dev
,
7606 struct drm_mode_fb_cmd2
*mode_cmd
,
7607 struct drm_i915_gem_object
*obj
)
7609 struct intel_framebuffer
*intel_fb
;
7612 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7614 drm_gem_object_unreference_unlocked(&obj
->base
);
7615 return ERR_PTR(-ENOMEM
);
7618 ret
= i915_mutex_lock_interruptible(dev
);
7622 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7623 mutex_unlock(&dev
->struct_mutex
);
7627 return &intel_fb
->base
;
7629 drm_gem_object_unreference_unlocked(&obj
->base
);
7632 return ERR_PTR(ret
);
7636 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7638 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7639 return ALIGN(pitch
, 64);
7643 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7645 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7646 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7649 static struct drm_framebuffer
*
7650 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7651 struct drm_display_mode
*mode
,
7654 struct drm_i915_gem_object
*obj
;
7655 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7657 obj
= i915_gem_alloc_object(dev
,
7658 intel_framebuffer_size_for_mode(mode
, bpp
));
7660 return ERR_PTR(-ENOMEM
);
7662 mode_cmd
.width
= mode
->hdisplay
;
7663 mode_cmd
.height
= mode
->vdisplay
;
7664 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7666 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7668 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7671 static struct drm_framebuffer
*
7672 mode_fits_in_fbdev(struct drm_device
*dev
,
7673 struct drm_display_mode
*mode
)
7675 #ifdef CONFIG_DRM_I915_FBDEV
7676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7677 struct drm_i915_gem_object
*obj
;
7678 struct drm_framebuffer
*fb
;
7680 if (dev_priv
->fbdev
== NULL
)
7683 obj
= dev_priv
->fbdev
->ifb
.obj
;
7687 fb
= &dev_priv
->fbdev
->ifb
.base
;
7688 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7689 fb
->bits_per_pixel
))
7692 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7701 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7702 struct drm_display_mode
*mode
,
7703 struct intel_load_detect_pipe
*old
)
7705 struct intel_crtc
*intel_crtc
;
7706 struct intel_encoder
*intel_encoder
=
7707 intel_attached_encoder(connector
);
7708 struct drm_crtc
*possible_crtc
;
7709 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7710 struct drm_crtc
*crtc
= NULL
;
7711 struct drm_device
*dev
= encoder
->dev
;
7712 struct drm_framebuffer
*fb
;
7715 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7716 connector
->base
.id
, drm_get_connector_name(connector
),
7717 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7720 * Algorithm gets a little messy:
7722 * - if the connector already has an assigned crtc, use it (but make
7723 * sure it's on first)
7725 * - try to find the first unused crtc that can drive this connector,
7726 * and use that if we find one
7729 /* See if we already have a CRTC for this connector */
7730 if (encoder
->crtc
) {
7731 crtc
= encoder
->crtc
;
7733 mutex_lock(&crtc
->mutex
);
7735 old
->dpms_mode
= connector
->dpms
;
7736 old
->load_detect_temp
= false;
7738 /* Make sure the crtc and connector are running */
7739 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7740 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7745 /* Find an unused one (if possible) */
7746 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7748 if (!(encoder
->possible_crtcs
& (1 << i
)))
7750 if (!possible_crtc
->enabled
) {
7751 crtc
= possible_crtc
;
7757 * If we didn't find an unused CRTC, don't use any.
7760 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7764 mutex_lock(&crtc
->mutex
);
7765 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7766 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7768 intel_crtc
= to_intel_crtc(crtc
);
7769 old
->dpms_mode
= connector
->dpms
;
7770 old
->load_detect_temp
= true;
7771 old
->release_fb
= NULL
;
7774 mode
= &load_detect_mode
;
7776 /* We need a framebuffer large enough to accommodate all accesses
7777 * that the plane may generate whilst we perform load detection.
7778 * We can not rely on the fbcon either being present (we get called
7779 * during its initialisation to detect all boot displays, or it may
7780 * not even exist) or that it is large enough to satisfy the
7783 fb
= mode_fits_in_fbdev(dev
, mode
);
7785 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7786 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7787 old
->release_fb
= fb
;
7789 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7791 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7792 mutex_unlock(&crtc
->mutex
);
7796 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7797 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7798 if (old
->release_fb
)
7799 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7800 mutex_unlock(&crtc
->mutex
);
7804 /* let the connector get through one full cycle before testing */
7805 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7809 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7810 struct intel_load_detect_pipe
*old
)
7812 struct intel_encoder
*intel_encoder
=
7813 intel_attached_encoder(connector
);
7814 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7815 struct drm_crtc
*crtc
= encoder
->crtc
;
7817 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7818 connector
->base
.id
, drm_get_connector_name(connector
),
7819 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7821 if (old
->load_detect_temp
) {
7822 to_intel_connector(connector
)->new_encoder
= NULL
;
7823 intel_encoder
->new_crtc
= NULL
;
7824 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7826 if (old
->release_fb
) {
7827 drm_framebuffer_unregister_private(old
->release_fb
);
7828 drm_framebuffer_unreference(old
->release_fb
);
7831 mutex_unlock(&crtc
->mutex
);
7835 /* Switch crtc and encoder back off if necessary */
7836 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7837 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7839 mutex_unlock(&crtc
->mutex
);
7842 static int i9xx_pll_refclk(struct drm_device
*dev
,
7843 const struct intel_crtc_config
*pipe_config
)
7845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7846 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7848 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7849 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7850 else if (HAS_PCH_SPLIT(dev
))
7852 else if (!IS_GEN2(dev
))
7858 /* Returns the clock of the currently programmed mode of the given pipe. */
7859 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7860 struct intel_crtc_config
*pipe_config
)
7862 struct drm_device
*dev
= crtc
->base
.dev
;
7863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7864 int pipe
= pipe_config
->cpu_transcoder
;
7865 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7867 intel_clock_t clock
;
7868 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7870 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7871 fp
= pipe_config
->dpll_hw_state
.fp0
;
7873 fp
= pipe_config
->dpll_hw_state
.fp1
;
7875 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7876 if (IS_PINEVIEW(dev
)) {
7877 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7878 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7880 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7881 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7884 if (!IS_GEN2(dev
)) {
7885 if (IS_PINEVIEW(dev
))
7886 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7887 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7889 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7890 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7892 switch (dpll
& DPLL_MODE_MASK
) {
7893 case DPLLB_MODE_DAC_SERIAL
:
7894 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7897 case DPLLB_MODE_LVDS
:
7898 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7902 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7903 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7907 if (IS_PINEVIEW(dev
))
7908 pineview_clock(refclk
, &clock
);
7910 i9xx_clock(refclk
, &clock
);
7912 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7915 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7916 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7919 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7922 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7923 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7925 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7931 i9xx_clock(refclk
, &clock
);
7935 * This value includes pixel_multiplier. We will use
7936 * port_clock to compute adjusted_mode.crtc_clock in the
7937 * encoder's get_config() function.
7939 pipe_config
->port_clock
= clock
.dot
;
7942 int intel_dotclock_calculate(int link_freq
,
7943 const struct intel_link_m_n
*m_n
)
7946 * The calculation for the data clock is:
7947 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7948 * But we want to avoid losing precison if possible, so:
7949 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7951 * and the link clock is simpler:
7952 * link_clock = (m * link_clock) / n
7958 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7961 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7962 struct intel_crtc_config
*pipe_config
)
7964 struct drm_device
*dev
= crtc
->base
.dev
;
7966 /* read out port_clock from the DPLL */
7967 i9xx_crtc_clock_get(crtc
, pipe_config
);
7970 * This value does not include pixel_multiplier.
7971 * We will check that port_clock and adjusted_mode.crtc_clock
7972 * agree once we know their relationship in the encoder's
7973 * get_config() function.
7975 pipe_config
->adjusted_mode
.crtc_clock
=
7976 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7977 &pipe_config
->fdi_m_n
);
7980 /** Returns the currently programmed mode of the given pipe. */
7981 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7982 struct drm_crtc
*crtc
)
7984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7985 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7986 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7987 struct drm_display_mode
*mode
;
7988 struct intel_crtc_config pipe_config
;
7989 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7990 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7991 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7992 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7993 enum pipe pipe
= intel_crtc
->pipe
;
7995 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8000 * Construct a pipe_config sufficient for getting the clock info
8001 * back out of crtc_clock_get.
8003 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8004 * to use a real value here instead.
8006 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8007 pipe_config
.pixel_multiplier
= 1;
8008 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8009 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8010 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8011 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8013 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8014 mode
->hdisplay
= (htot
& 0xffff) + 1;
8015 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8016 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8017 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8018 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8019 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8020 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8021 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8023 drm_mode_set_name(mode
);
8028 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
8030 struct drm_device
*dev
= crtc
->dev
;
8031 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8032 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8033 int pipe
= intel_crtc
->pipe
;
8034 int dpll_reg
= DPLL(pipe
);
8037 if (HAS_PCH_SPLIT(dev
))
8040 if (!dev_priv
->lvds_downclock_avail
)
8043 dpll
= I915_READ(dpll_reg
);
8044 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8045 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8047 assert_panel_unlocked(dev_priv
, pipe
);
8049 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8050 I915_WRITE(dpll_reg
, dpll
);
8051 intel_wait_for_vblank(dev
, pipe
);
8053 dpll
= I915_READ(dpll_reg
);
8054 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8055 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8059 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8061 struct drm_device
*dev
= crtc
->dev
;
8062 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8063 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8065 if (HAS_PCH_SPLIT(dev
))
8068 if (!dev_priv
->lvds_downclock_avail
)
8072 * Since this is called by a timer, we should never get here in
8075 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8076 int pipe
= intel_crtc
->pipe
;
8077 int dpll_reg
= DPLL(pipe
);
8080 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8082 assert_panel_unlocked(dev_priv
, pipe
);
8084 dpll
= I915_READ(dpll_reg
);
8085 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8086 I915_WRITE(dpll_reg
, dpll
);
8087 intel_wait_for_vblank(dev
, pipe
);
8088 dpll
= I915_READ(dpll_reg
);
8089 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8090 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8095 void intel_mark_busy(struct drm_device
*dev
)
8097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8099 hsw_package_c8_gpu_busy(dev_priv
);
8100 i915_update_gfx_val(dev_priv
);
8103 void intel_mark_idle(struct drm_device
*dev
)
8105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8106 struct drm_crtc
*crtc
;
8108 hsw_package_c8_gpu_idle(dev_priv
);
8110 if (!i915_powersave
)
8113 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8117 intel_decrease_pllclock(crtc
);
8120 if (dev_priv
->info
->gen
>= 6)
8121 gen6_rps_idle(dev
->dev_private
);
8124 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
8125 struct intel_ring_buffer
*ring
)
8127 struct drm_device
*dev
= obj
->base
.dev
;
8128 struct drm_crtc
*crtc
;
8130 if (!i915_powersave
)
8133 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8137 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
8140 intel_increase_pllclock(crtc
);
8141 if (ring
&& intel_fbc_enabled(dev
))
8142 ring
->fbc_dirty
= true;
8146 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
8148 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8149 struct drm_device
*dev
= crtc
->dev
;
8150 struct intel_unpin_work
*work
;
8151 unsigned long flags
;
8153 spin_lock_irqsave(&dev
->event_lock
, flags
);
8154 work
= intel_crtc
->unpin_work
;
8155 intel_crtc
->unpin_work
= NULL
;
8156 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8159 cancel_work_sync(&work
->work
);
8163 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
8165 drm_crtc_cleanup(crtc
);
8170 static void intel_unpin_work_fn(struct work_struct
*__work
)
8172 struct intel_unpin_work
*work
=
8173 container_of(__work
, struct intel_unpin_work
, work
);
8174 struct drm_device
*dev
= work
->crtc
->dev
;
8176 mutex_lock(&dev
->struct_mutex
);
8177 intel_unpin_fb_obj(work
->old_fb_obj
);
8178 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
8179 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8181 intel_update_fbc(dev
);
8182 mutex_unlock(&dev
->struct_mutex
);
8184 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
8185 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
8190 static void do_intel_finish_page_flip(struct drm_device
*dev
,
8191 struct drm_crtc
*crtc
)
8193 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8195 struct intel_unpin_work
*work
;
8196 unsigned long flags
;
8198 /* Ignore early vblank irqs */
8199 if (intel_crtc
== NULL
)
8202 spin_lock_irqsave(&dev
->event_lock
, flags
);
8203 work
= intel_crtc
->unpin_work
;
8205 /* Ensure we don't miss a work->pending update ... */
8208 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
8209 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8213 /* and that the unpin work is consistent wrt ->pending. */
8216 intel_crtc
->unpin_work
= NULL
;
8219 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
8221 drm_vblank_put(dev
, intel_crtc
->pipe
);
8223 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8225 wake_up_all(&dev_priv
->pending_flip_queue
);
8227 queue_work(dev_priv
->wq
, &work
->work
);
8229 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
8232 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
8234 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8235 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
8237 do_intel_finish_page_flip(dev
, crtc
);
8240 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
8242 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8243 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
8245 do_intel_finish_page_flip(dev
, crtc
);
8248 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
8250 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8251 struct intel_crtc
*intel_crtc
=
8252 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
8253 unsigned long flags
;
8255 /* NB: An MMIO update of the plane base pointer will also
8256 * generate a page-flip completion irq, i.e. every modeset
8257 * is also accompanied by a spurious intel_prepare_page_flip().
8259 spin_lock_irqsave(&dev
->event_lock
, flags
);
8260 if (intel_crtc
->unpin_work
)
8261 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
8262 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8265 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
8267 /* Ensure that the work item is consistent when activating it ... */
8269 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
8270 /* and that it is marked active as soon as the irq could fire. */
8274 static int intel_gen2_queue_flip(struct drm_device
*dev
,
8275 struct drm_crtc
*crtc
,
8276 struct drm_framebuffer
*fb
,
8277 struct drm_i915_gem_object
*obj
,
8280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8283 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8286 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8290 ret
= intel_ring_begin(ring
, 6);
8294 /* Can't queue multiple flips, so wait for the previous
8295 * one to finish before executing the next.
8297 if (intel_crtc
->plane
)
8298 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8300 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8301 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8302 intel_ring_emit(ring
, MI_NOOP
);
8303 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8304 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8305 intel_ring_emit(ring
, fb
->pitches
[0]);
8306 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8307 intel_ring_emit(ring
, 0); /* aux display base address, unused */
8309 intel_mark_page_flip_active(intel_crtc
);
8310 __intel_ring_advance(ring
);
8314 intel_unpin_fb_obj(obj
);
8319 static int intel_gen3_queue_flip(struct drm_device
*dev
,
8320 struct drm_crtc
*crtc
,
8321 struct drm_framebuffer
*fb
,
8322 struct drm_i915_gem_object
*obj
,
8325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8326 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8328 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8331 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8335 ret
= intel_ring_begin(ring
, 6);
8339 if (intel_crtc
->plane
)
8340 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8342 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8343 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8344 intel_ring_emit(ring
, MI_NOOP
);
8345 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
8346 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8347 intel_ring_emit(ring
, fb
->pitches
[0]);
8348 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8349 intel_ring_emit(ring
, MI_NOOP
);
8351 intel_mark_page_flip_active(intel_crtc
);
8352 __intel_ring_advance(ring
);
8356 intel_unpin_fb_obj(obj
);
8361 static int intel_gen4_queue_flip(struct drm_device
*dev
,
8362 struct drm_crtc
*crtc
,
8363 struct drm_framebuffer
*fb
,
8364 struct drm_i915_gem_object
*obj
,
8367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8368 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8369 uint32_t pf
, pipesrc
;
8370 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8373 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8377 ret
= intel_ring_begin(ring
, 4);
8381 /* i965+ uses the linear or tiled offsets from the
8382 * Display Registers (which do not change across a page-flip)
8383 * so we need only reprogram the base address.
8385 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8386 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8387 intel_ring_emit(ring
, fb
->pitches
[0]);
8388 intel_ring_emit(ring
,
8389 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
8392 /* XXX Enabling the panel-fitter across page-flip is so far
8393 * untested on non-native modes, so ignore it for now.
8394 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8397 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8398 intel_ring_emit(ring
, pf
| pipesrc
);
8400 intel_mark_page_flip_active(intel_crtc
);
8401 __intel_ring_advance(ring
);
8405 intel_unpin_fb_obj(obj
);
8410 static int intel_gen6_queue_flip(struct drm_device
*dev
,
8411 struct drm_crtc
*crtc
,
8412 struct drm_framebuffer
*fb
,
8413 struct drm_i915_gem_object
*obj
,
8416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8417 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8418 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8419 uint32_t pf
, pipesrc
;
8422 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8426 ret
= intel_ring_begin(ring
, 4);
8430 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8431 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8432 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
8433 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8435 /* Contrary to the suggestions in the documentation,
8436 * "Enable Panel Fitter" does not seem to be required when page
8437 * flipping with a non-native mode, and worse causes a normal
8439 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8442 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8443 intel_ring_emit(ring
, pf
| pipesrc
);
8445 intel_mark_page_flip_active(intel_crtc
);
8446 __intel_ring_advance(ring
);
8450 intel_unpin_fb_obj(obj
);
8455 static int intel_gen7_queue_flip(struct drm_device
*dev
,
8456 struct drm_crtc
*crtc
,
8457 struct drm_framebuffer
*fb
,
8458 struct drm_i915_gem_object
*obj
,
8461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8462 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8463 struct intel_ring_buffer
*ring
;
8464 uint32_t plane_bit
= 0;
8468 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8469 ring
= &dev_priv
->ring
[BCS
];
8471 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8475 switch(intel_crtc
->plane
) {
8477 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8480 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8483 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8486 WARN_ONCE(1, "unknown plane in flip command\n");
8492 if (ring
->id
== RCS
)
8495 ret
= intel_ring_begin(ring
, len
);
8499 /* Unmask the flip-done completion message. Note that the bspec says that
8500 * we should do this for both the BCS and RCS, and that we must not unmask
8501 * more than one flip event at any time (or ensure that one flip message
8502 * can be sent by waiting for flip-done prior to queueing new flips).
8503 * Experimentation says that BCS works despite DERRMR masking all
8504 * flip-done completion events and that unmasking all planes at once
8505 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8506 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8508 if (ring
->id
== RCS
) {
8509 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8510 intel_ring_emit(ring
, DERRMR
);
8511 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8512 DERRMR_PIPEB_PRI_FLIP_DONE
|
8513 DERRMR_PIPEC_PRI_FLIP_DONE
));
8514 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8515 intel_ring_emit(ring
, DERRMR
);
8516 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8519 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8520 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8521 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8522 intel_ring_emit(ring
, (MI_NOOP
));
8524 intel_mark_page_flip_active(intel_crtc
);
8525 __intel_ring_advance(ring
);
8529 intel_unpin_fb_obj(obj
);
8534 static int intel_default_queue_flip(struct drm_device
*dev
,
8535 struct drm_crtc
*crtc
,
8536 struct drm_framebuffer
*fb
,
8537 struct drm_i915_gem_object
*obj
,
8543 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8544 struct drm_framebuffer
*fb
,
8545 struct drm_pending_vblank_event
*event
,
8546 uint32_t page_flip_flags
)
8548 struct drm_device
*dev
= crtc
->dev
;
8549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8550 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8551 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8552 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8553 struct intel_unpin_work
*work
;
8554 unsigned long flags
;
8557 /* Can't change pixel format via MI display flips. */
8558 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8562 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8563 * Note that pitch changes could also affect these register.
8565 if (INTEL_INFO(dev
)->gen
> 3 &&
8566 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8567 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8570 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8574 work
->event
= event
;
8576 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8577 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8579 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8583 /* We borrow the event spin lock for protecting unpin_work */
8584 spin_lock_irqsave(&dev
->event_lock
, flags
);
8585 if (intel_crtc
->unpin_work
) {
8586 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8588 drm_vblank_put(dev
, intel_crtc
->pipe
);
8590 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8593 intel_crtc
->unpin_work
= work
;
8594 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8596 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8597 flush_workqueue(dev_priv
->wq
);
8599 ret
= i915_mutex_lock_interruptible(dev
);
8603 /* Reference the objects for the scheduled work. */
8604 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8605 drm_gem_object_reference(&obj
->base
);
8609 work
->pending_flip_obj
= obj
;
8611 work
->enable_stall_check
= true;
8613 atomic_inc(&intel_crtc
->unpin_work_count
);
8614 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8616 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8618 goto cleanup_pending
;
8620 intel_disable_fbc(dev
);
8621 intel_mark_fb_busy(obj
, NULL
);
8622 mutex_unlock(&dev
->struct_mutex
);
8624 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8629 atomic_dec(&intel_crtc
->unpin_work_count
);
8631 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8632 drm_gem_object_unreference(&obj
->base
);
8633 mutex_unlock(&dev
->struct_mutex
);
8636 spin_lock_irqsave(&dev
->event_lock
, flags
);
8637 intel_crtc
->unpin_work
= NULL
;
8638 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8640 drm_vblank_put(dev
, intel_crtc
->pipe
);
8647 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8648 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8649 .load_lut
= intel_crtc_load_lut
,
8652 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8653 struct drm_crtc
*crtc
)
8655 struct drm_device
*dev
;
8656 struct drm_crtc
*tmp
;
8659 WARN(!crtc
, "checking null crtc?\n");
8663 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8669 if (encoder
->possible_crtcs
& crtc_mask
)
8675 * intel_modeset_update_staged_output_state
8677 * Updates the staged output configuration state, e.g. after we've read out the
8680 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8682 struct intel_encoder
*encoder
;
8683 struct intel_connector
*connector
;
8685 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8687 connector
->new_encoder
=
8688 to_intel_encoder(connector
->base
.encoder
);
8691 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8694 to_intel_crtc(encoder
->base
.crtc
);
8699 * intel_modeset_commit_output_state
8701 * This function copies the stage display pipe configuration to the real one.
8703 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8705 struct intel_encoder
*encoder
;
8706 struct intel_connector
*connector
;
8708 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8710 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8713 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8715 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8720 connected_sink_compute_bpp(struct intel_connector
* connector
,
8721 struct intel_crtc_config
*pipe_config
)
8723 int bpp
= pipe_config
->pipe_bpp
;
8725 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8726 connector
->base
.base
.id
,
8727 drm_get_connector_name(&connector
->base
));
8729 /* Don't use an invalid EDID bpc value */
8730 if (connector
->base
.display_info
.bpc
&&
8731 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8732 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8733 bpp
, connector
->base
.display_info
.bpc
*3);
8734 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8737 /* Clamp bpp to 8 on screens without EDID 1.4 */
8738 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8739 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8741 pipe_config
->pipe_bpp
= 24;
8746 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8747 struct drm_framebuffer
*fb
,
8748 struct intel_crtc_config
*pipe_config
)
8750 struct drm_device
*dev
= crtc
->base
.dev
;
8751 struct intel_connector
*connector
;
8754 switch (fb
->pixel_format
) {
8756 bpp
= 8*3; /* since we go through a colormap */
8758 case DRM_FORMAT_XRGB1555
:
8759 case DRM_FORMAT_ARGB1555
:
8760 /* checked in intel_framebuffer_init already */
8761 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8763 case DRM_FORMAT_RGB565
:
8764 bpp
= 6*3; /* min is 18bpp */
8766 case DRM_FORMAT_XBGR8888
:
8767 case DRM_FORMAT_ABGR8888
:
8768 /* checked in intel_framebuffer_init already */
8769 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8771 case DRM_FORMAT_XRGB8888
:
8772 case DRM_FORMAT_ARGB8888
:
8775 case DRM_FORMAT_XRGB2101010
:
8776 case DRM_FORMAT_ARGB2101010
:
8777 case DRM_FORMAT_XBGR2101010
:
8778 case DRM_FORMAT_ABGR2101010
:
8779 /* checked in intel_framebuffer_init already */
8780 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8784 /* TODO: gen4+ supports 16 bpc floating point, too. */
8786 DRM_DEBUG_KMS("unsupported depth\n");
8790 pipe_config
->pipe_bpp
= bpp
;
8792 /* Clamp display bpp to EDID value */
8793 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8795 if (!connector
->new_encoder
||
8796 connector
->new_encoder
->new_crtc
!= crtc
)
8799 connected_sink_compute_bpp(connector
, pipe_config
);
8805 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8807 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8808 "type: 0x%x flags: 0x%x\n",
8810 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8811 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8812 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8813 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8816 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8817 struct intel_crtc_config
*pipe_config
,
8818 const char *context
)
8820 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8821 context
, pipe_name(crtc
->pipe
));
8823 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8824 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8825 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8826 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8827 pipe_config
->has_pch_encoder
,
8828 pipe_config
->fdi_lanes
,
8829 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8830 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8831 pipe_config
->fdi_m_n
.tu
);
8832 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8833 pipe_config
->has_dp_encoder
,
8834 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8835 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8836 pipe_config
->dp_m_n
.tu
);
8837 DRM_DEBUG_KMS("requested mode:\n");
8838 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8839 DRM_DEBUG_KMS("adjusted mode:\n");
8840 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8841 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8842 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8843 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8844 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8845 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8846 pipe_config
->gmch_pfit
.control
,
8847 pipe_config
->gmch_pfit
.pgm_ratios
,
8848 pipe_config
->gmch_pfit
.lvds_border_bits
);
8849 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8850 pipe_config
->pch_pfit
.pos
,
8851 pipe_config
->pch_pfit
.size
,
8852 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8853 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8854 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8857 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8859 int num_encoders
= 0;
8860 bool uncloneable_encoders
= false;
8861 struct intel_encoder
*encoder
;
8863 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8865 if (&encoder
->new_crtc
->base
!= crtc
)
8869 if (!encoder
->cloneable
)
8870 uncloneable_encoders
= true;
8873 return !(num_encoders
> 1 && uncloneable_encoders
);
8876 static struct intel_crtc_config
*
8877 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8878 struct drm_framebuffer
*fb
,
8879 struct drm_display_mode
*mode
)
8881 struct drm_device
*dev
= crtc
->dev
;
8882 struct intel_encoder
*encoder
;
8883 struct intel_crtc_config
*pipe_config
;
8884 int plane_bpp
, ret
= -EINVAL
;
8887 if (!check_encoder_cloning(crtc
)) {
8888 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8889 return ERR_PTR(-EINVAL
);
8892 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8894 return ERR_PTR(-ENOMEM
);
8896 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8897 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8899 pipe_config
->cpu_transcoder
=
8900 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8901 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8904 * Sanitize sync polarity flags based on requested ones. If neither
8905 * positive or negative polarity is requested, treat this as meaning
8906 * negative polarity.
8908 if (!(pipe_config
->adjusted_mode
.flags
&
8909 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8910 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8912 if (!(pipe_config
->adjusted_mode
.flags
&
8913 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8914 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8916 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8917 * plane pixel format and any sink constraints into account. Returns the
8918 * source plane bpp so that dithering can be selected on mismatches
8919 * after encoders and crtc also have had their say. */
8920 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8926 * Determine the real pipe dimensions. Note that stereo modes can
8927 * increase the actual pipe size due to the frame doubling and
8928 * insertion of additional space for blanks between the frame. This
8929 * is stored in the crtc timings. We use the requested mode to do this
8930 * computation to clearly distinguish it from the adjusted mode, which
8931 * can be changed by the connectors in the below retry loop.
8933 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
8934 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
8935 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
8938 /* Ensure the port clock defaults are reset when retrying. */
8939 pipe_config
->port_clock
= 0;
8940 pipe_config
->pixel_multiplier
= 1;
8942 /* Fill in default crtc timings, allow encoders to overwrite them. */
8943 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
8945 /* Pass our mode to the connectors and the CRTC to give them a chance to
8946 * adjust it according to limitations or connector properties, and also
8947 * a chance to reject the mode entirely.
8949 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8952 if (&encoder
->new_crtc
->base
!= crtc
)
8955 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8956 DRM_DEBUG_KMS("Encoder config failure\n");
8961 /* Set default port clock if not overwritten by the encoder. Needs to be
8962 * done afterwards in case the encoder adjusts the mode. */
8963 if (!pipe_config
->port_clock
)
8964 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
8965 * pipe_config
->pixel_multiplier
;
8967 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8969 DRM_DEBUG_KMS("CRTC fixup failed\n");
8974 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8979 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8984 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8985 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8986 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8991 return ERR_PTR(ret
);
8994 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8995 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8997 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8998 unsigned *prepare_pipes
, unsigned *disable_pipes
)
9000 struct intel_crtc
*intel_crtc
;
9001 struct drm_device
*dev
= crtc
->dev
;
9002 struct intel_encoder
*encoder
;
9003 struct intel_connector
*connector
;
9004 struct drm_crtc
*tmp_crtc
;
9006 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
9008 /* Check which crtcs have changed outputs connected to them, these need
9009 * to be part of the prepare_pipes mask. We don't (yet) support global
9010 * modeset across multiple crtcs, so modeset_pipes will only have one
9011 * bit set at most. */
9012 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9014 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
9017 if (connector
->base
.encoder
) {
9018 tmp_crtc
= connector
->base
.encoder
->crtc
;
9020 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9023 if (connector
->new_encoder
)
9025 1 << connector
->new_encoder
->new_crtc
->pipe
;
9028 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9030 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
9033 if (encoder
->base
.crtc
) {
9034 tmp_crtc
= encoder
->base
.crtc
;
9036 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9039 if (encoder
->new_crtc
)
9040 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
9043 /* Check for any pipes that will be fully disabled ... */
9044 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
9048 /* Don't try to disable disabled crtcs. */
9049 if (!intel_crtc
->base
.enabled
)
9052 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9054 if (encoder
->new_crtc
== intel_crtc
)
9059 *disable_pipes
|= 1 << intel_crtc
->pipe
;
9063 /* set_mode is also used to update properties on life display pipes. */
9064 intel_crtc
= to_intel_crtc(crtc
);
9066 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
9069 * For simplicity do a full modeset on any pipe where the output routing
9070 * changed. We could be more clever, but that would require us to be
9071 * more careful with calling the relevant encoder->mode_set functions.
9074 *modeset_pipes
= *prepare_pipes
;
9076 /* ... and mask these out. */
9077 *modeset_pipes
&= ~(*disable_pipes
);
9078 *prepare_pipes
&= ~(*disable_pipes
);
9081 * HACK: We don't (yet) fully support global modesets. intel_set_config
9082 * obies this rule, but the modeset restore mode of
9083 * intel_modeset_setup_hw_state does not.
9085 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
9086 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
9088 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9089 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
9092 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
9094 struct drm_encoder
*encoder
;
9095 struct drm_device
*dev
= crtc
->dev
;
9097 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
9098 if (encoder
->crtc
== crtc
)
9105 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
9107 struct intel_encoder
*intel_encoder
;
9108 struct intel_crtc
*intel_crtc
;
9109 struct drm_connector
*connector
;
9111 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
9113 if (!intel_encoder
->base
.crtc
)
9116 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
9118 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
9119 intel_encoder
->connectors_active
= false;
9122 intel_modeset_commit_output_state(dev
);
9124 /* Update computed state. */
9125 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
9127 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
9130 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9131 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
9134 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
9136 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
9137 struct drm_property
*dpms_property
=
9138 dev
->mode_config
.dpms_property
;
9140 connector
->dpms
= DRM_MODE_DPMS_ON
;
9141 drm_object_property_set_value(&connector
->base
,
9145 intel_encoder
= to_intel_encoder(connector
->encoder
);
9146 intel_encoder
->connectors_active
= true;
9152 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
9156 if (clock1
== clock2
)
9159 if (!clock1
|| !clock2
)
9162 diff
= abs(clock1
- clock2
);
9164 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
9170 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9171 list_for_each_entry((intel_crtc), \
9172 &(dev)->mode_config.crtc_list, \
9174 if (mask & (1 <<(intel_crtc)->pipe))
9177 intel_pipe_config_compare(struct drm_device
*dev
,
9178 struct intel_crtc_config
*current_config
,
9179 struct intel_crtc_config
*pipe_config
)
9181 #define PIPE_CONF_CHECK_X(name) \
9182 if (current_config->name != pipe_config->name) { \
9183 DRM_ERROR("mismatch in " #name " " \
9184 "(expected 0x%08x, found 0x%08x)\n", \
9185 current_config->name, \
9186 pipe_config->name); \
9190 #define PIPE_CONF_CHECK_I(name) \
9191 if (current_config->name != pipe_config->name) { \
9192 DRM_ERROR("mismatch in " #name " " \
9193 "(expected %i, found %i)\n", \
9194 current_config->name, \
9195 pipe_config->name); \
9199 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9200 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9201 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9202 "(expected %i, found %i)\n", \
9203 current_config->name & (mask), \
9204 pipe_config->name & (mask)); \
9208 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9209 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9210 DRM_ERROR("mismatch in " #name " " \
9211 "(expected %i, found %i)\n", \
9212 current_config->name, \
9213 pipe_config->name); \
9217 #define PIPE_CONF_QUIRK(quirk) \
9218 ((current_config->quirks | pipe_config->quirks) & (quirk))
9220 PIPE_CONF_CHECK_I(cpu_transcoder
);
9222 PIPE_CONF_CHECK_I(has_pch_encoder
);
9223 PIPE_CONF_CHECK_I(fdi_lanes
);
9224 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
9225 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
9226 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
9227 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
9228 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
9230 PIPE_CONF_CHECK_I(has_dp_encoder
);
9231 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
9232 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
9233 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
9234 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
9235 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
9237 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
9238 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
9239 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
9240 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
9241 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
9242 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
9244 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
9245 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
9246 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
9247 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
9248 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
9249 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
9251 PIPE_CONF_CHECK_I(pixel_multiplier
);
9253 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9254 DRM_MODE_FLAG_INTERLACE
);
9256 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
9257 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9258 DRM_MODE_FLAG_PHSYNC
);
9259 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9260 DRM_MODE_FLAG_NHSYNC
);
9261 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9262 DRM_MODE_FLAG_PVSYNC
);
9263 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9264 DRM_MODE_FLAG_NVSYNC
);
9267 PIPE_CONF_CHECK_I(pipe_src_w
);
9268 PIPE_CONF_CHECK_I(pipe_src_h
);
9270 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
9271 /* pfit ratios are autocomputed by the hw on gen4+ */
9272 if (INTEL_INFO(dev
)->gen
< 4)
9273 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
9274 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
9275 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
9276 if (current_config
->pch_pfit
.enabled
) {
9277 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
9278 PIPE_CONF_CHECK_I(pch_pfit
.size
);
9281 PIPE_CONF_CHECK_I(ips_enabled
);
9283 PIPE_CONF_CHECK_I(double_wide
);
9285 PIPE_CONF_CHECK_I(shared_dpll
);
9286 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
9287 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
9288 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
9289 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
9291 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
9292 PIPE_CONF_CHECK_I(pipe_bpp
);
9294 if (!IS_HASWELL(dev
)) {
9295 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
9296 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
9299 #undef PIPE_CONF_CHECK_X
9300 #undef PIPE_CONF_CHECK_I
9301 #undef PIPE_CONF_CHECK_FLAGS
9302 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9303 #undef PIPE_CONF_QUIRK
9309 check_connector_state(struct drm_device
*dev
)
9311 struct intel_connector
*connector
;
9313 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9315 /* This also checks the encoder/connector hw state with the
9316 * ->get_hw_state callbacks. */
9317 intel_connector_check_state(connector
);
9319 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
9320 "connector's staged encoder doesn't match current encoder\n");
9325 check_encoder_state(struct drm_device
*dev
)
9327 struct intel_encoder
*encoder
;
9328 struct intel_connector
*connector
;
9330 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9332 bool enabled
= false;
9333 bool active
= false;
9334 enum pipe pipe
, tracked_pipe
;
9336 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9337 encoder
->base
.base
.id
,
9338 drm_get_encoder_name(&encoder
->base
));
9340 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
9341 "encoder's stage crtc doesn't match current crtc\n");
9342 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
9343 "encoder's active_connectors set, but no crtc\n");
9345 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9347 if (connector
->base
.encoder
!= &encoder
->base
)
9350 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
9353 WARN(!!encoder
->base
.crtc
!= enabled
,
9354 "encoder's enabled state mismatch "
9355 "(expected %i, found %i)\n",
9356 !!encoder
->base
.crtc
, enabled
);
9357 WARN(active
&& !encoder
->base
.crtc
,
9358 "active encoder with no crtc\n");
9360 WARN(encoder
->connectors_active
!= active
,
9361 "encoder's computed active state doesn't match tracked active state "
9362 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
9364 active
= encoder
->get_hw_state(encoder
, &pipe
);
9365 WARN(active
!= encoder
->connectors_active
,
9366 "encoder's hw state doesn't match sw tracking "
9367 "(expected %i, found %i)\n",
9368 encoder
->connectors_active
, active
);
9370 if (!encoder
->base
.crtc
)
9373 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
9374 WARN(active
&& pipe
!= tracked_pipe
,
9375 "active encoder's pipe doesn't match"
9376 "(expected %i, found %i)\n",
9377 tracked_pipe
, pipe
);
9383 check_crtc_state(struct drm_device
*dev
)
9385 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9386 struct intel_crtc
*crtc
;
9387 struct intel_encoder
*encoder
;
9388 struct intel_crtc_config pipe_config
;
9390 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9392 bool enabled
= false;
9393 bool active
= false;
9395 memset(&pipe_config
, 0, sizeof(pipe_config
));
9397 DRM_DEBUG_KMS("[CRTC:%d]\n",
9398 crtc
->base
.base
.id
);
9400 WARN(crtc
->active
&& !crtc
->base
.enabled
,
9401 "active crtc, but not enabled in sw tracking\n");
9403 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9405 if (encoder
->base
.crtc
!= &crtc
->base
)
9408 if (encoder
->connectors_active
)
9412 WARN(active
!= crtc
->active
,
9413 "crtc's computed active state doesn't match tracked active state "
9414 "(expected %i, found %i)\n", active
, crtc
->active
);
9415 WARN(enabled
!= crtc
->base
.enabled
,
9416 "crtc's computed enabled state doesn't match tracked enabled state "
9417 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
9419 active
= dev_priv
->display
.get_pipe_config(crtc
,
9422 /* hw state is inconsistent with the pipe A quirk */
9423 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
9424 active
= crtc
->active
;
9426 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9429 if (encoder
->base
.crtc
!= &crtc
->base
)
9431 if (encoder
->get_config
&&
9432 encoder
->get_hw_state(encoder
, &pipe
))
9433 encoder
->get_config(encoder
, &pipe_config
);
9436 WARN(crtc
->active
!= active
,
9437 "crtc active state doesn't match with hw state "
9438 "(expected %i, found %i)\n", crtc
->active
, active
);
9441 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
9442 WARN(1, "pipe state doesn't match!\n");
9443 intel_dump_pipe_config(crtc
, &pipe_config
,
9445 intel_dump_pipe_config(crtc
, &crtc
->config
,
9452 check_shared_dpll_state(struct drm_device
*dev
)
9454 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9455 struct intel_crtc
*crtc
;
9456 struct intel_dpll_hw_state dpll_hw_state
;
9459 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9460 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9461 int enabled_crtcs
= 0, active_crtcs
= 0;
9464 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
9466 DRM_DEBUG_KMS("%s\n", pll
->name
);
9468 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9470 WARN(pll
->active
> pll
->refcount
,
9471 "more active pll users than references: %i vs %i\n",
9472 pll
->active
, pll
->refcount
);
9473 WARN(pll
->active
&& !pll
->on
,
9474 "pll in active use but not on in sw tracking\n");
9475 WARN(pll
->on
&& !pll
->active
,
9476 "pll in on but not on in use in sw tracking\n");
9477 WARN(pll
->on
!= active
,
9478 "pll on state mismatch (expected %i, found %i)\n",
9481 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9483 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9485 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9488 WARN(pll
->active
!= active_crtcs
,
9489 "pll active crtcs mismatch (expected %i, found %i)\n",
9490 pll
->active
, active_crtcs
);
9491 WARN(pll
->refcount
!= enabled_crtcs
,
9492 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9493 pll
->refcount
, enabled_crtcs
);
9495 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9496 sizeof(dpll_hw_state
)),
9497 "pll hw state mismatch\n");
9502 intel_modeset_check_state(struct drm_device
*dev
)
9504 check_connector_state(dev
);
9505 check_encoder_state(dev
);
9506 check_crtc_state(dev
);
9507 check_shared_dpll_state(dev
);
9510 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9514 * FDI already provided one idea for the dotclock.
9515 * Yell if the encoder disagrees.
9517 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9518 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9519 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9522 static int __intel_set_mode(struct drm_crtc
*crtc
,
9523 struct drm_display_mode
*mode
,
9524 int x
, int y
, struct drm_framebuffer
*fb
)
9526 struct drm_device
*dev
= crtc
->dev
;
9527 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9528 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
9529 struct intel_crtc_config
*pipe_config
= NULL
;
9530 struct intel_crtc
*intel_crtc
;
9531 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9534 saved_mode
= kcalloc(2, sizeof(*saved_mode
), GFP_KERNEL
);
9537 saved_hwmode
= saved_mode
+ 1;
9539 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9540 &prepare_pipes
, &disable_pipes
);
9542 *saved_hwmode
= crtc
->hwmode
;
9543 *saved_mode
= crtc
->mode
;
9545 /* Hack: Because we don't (yet) support global modeset on multiple
9546 * crtcs, we don't keep track of the new mode for more than one crtc.
9547 * Hence simply check whether any bit is set in modeset_pipes in all the
9548 * pieces of code that are not yet converted to deal with mutliple crtcs
9549 * changing their mode at the same time. */
9550 if (modeset_pipes
) {
9551 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9552 if (IS_ERR(pipe_config
)) {
9553 ret
= PTR_ERR(pipe_config
);
9558 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9563 * See if the config requires any additional preparation, e.g.
9564 * to adjust global state with pipes off. We need to do this
9565 * here so we can get the modeset_pipe updated config for the new
9566 * mode set on this crtc. For other crtcs we need to use the
9567 * adjusted_mode bits in the crtc directly.
9569 if (IS_VALLEYVIEW(dev
)) {
9570 valleyview_modeset_global_pipes(dev
, &prepare_pipes
,
9571 modeset_pipes
, pipe_config
);
9573 /* may have added more to prepare_pipes than we should */
9574 prepare_pipes
&= ~disable_pipes
;
9577 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9578 intel_crtc_disable(&intel_crtc
->base
);
9580 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9581 if (intel_crtc
->base
.enabled
)
9582 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9585 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9586 * to set it here already despite that we pass it down the callchain.
9588 if (modeset_pipes
) {
9590 /* mode_set/enable/disable functions rely on a correct pipe
9592 to_intel_crtc(crtc
)->config
= *pipe_config
;
9595 /* Only after disabling all output pipelines that will be changed can we
9596 * update the the output configuration. */
9597 intel_modeset_update_state(dev
, prepare_pipes
);
9599 if (dev_priv
->display
.modeset_global_resources
)
9600 dev_priv
->display
.modeset_global_resources(dev
);
9602 /* Set up the DPLL and any encoders state that needs to adjust or depend
9605 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9606 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9612 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9613 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9614 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9616 if (modeset_pipes
) {
9617 /* Store real post-adjustment hardware mode. */
9618 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9620 /* Calculate and store various constants which
9621 * are later needed by vblank and swap-completion
9622 * timestamping. They are derived from true hwmode.
9624 drm_calc_timestamping_constants(crtc
);
9627 /* FIXME: add subpixel order */
9629 if (ret
&& crtc
->enabled
) {
9630 crtc
->hwmode
= *saved_hwmode
;
9631 crtc
->mode
= *saved_mode
;
9640 static int intel_set_mode(struct drm_crtc
*crtc
,
9641 struct drm_display_mode
*mode
,
9642 int x
, int y
, struct drm_framebuffer
*fb
)
9646 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9649 intel_modeset_check_state(crtc
->dev
);
9654 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9656 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9659 #undef for_each_intel_crtc_masked
9661 static void intel_set_config_free(struct intel_set_config
*config
)
9666 kfree(config
->save_connector_encoders
);
9667 kfree(config
->save_encoder_crtcs
);
9671 static int intel_set_config_save_state(struct drm_device
*dev
,
9672 struct intel_set_config
*config
)
9674 struct drm_encoder
*encoder
;
9675 struct drm_connector
*connector
;
9678 config
->save_encoder_crtcs
=
9679 kcalloc(dev
->mode_config
.num_encoder
,
9680 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9681 if (!config
->save_encoder_crtcs
)
9684 config
->save_connector_encoders
=
9685 kcalloc(dev
->mode_config
.num_connector
,
9686 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9687 if (!config
->save_connector_encoders
)
9690 /* Copy data. Note that driver private data is not affected.
9691 * Should anything bad happen only the expected state is
9692 * restored, not the drivers personal bookkeeping.
9695 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9696 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9700 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9701 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9707 static void intel_set_config_restore_state(struct drm_device
*dev
,
9708 struct intel_set_config
*config
)
9710 struct intel_encoder
*encoder
;
9711 struct intel_connector
*connector
;
9715 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9717 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9721 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9722 connector
->new_encoder
=
9723 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9728 is_crtc_connector_off(struct drm_mode_set
*set
)
9732 if (set
->num_connectors
== 0)
9735 if (WARN_ON(set
->connectors
== NULL
))
9738 for (i
= 0; i
< set
->num_connectors
; i
++)
9739 if (set
->connectors
[i
]->encoder
&&
9740 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9741 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9748 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9749 struct intel_set_config
*config
)
9752 /* We should be able to check here if the fb has the same properties
9753 * and then just flip_or_move it */
9754 if (is_crtc_connector_off(set
)) {
9755 config
->mode_changed
= true;
9756 } else if (set
->crtc
->fb
!= set
->fb
) {
9757 /* If we have no fb then treat it as a full mode set */
9758 if (set
->crtc
->fb
== NULL
) {
9759 struct intel_crtc
*intel_crtc
=
9760 to_intel_crtc(set
->crtc
);
9762 if (intel_crtc
->active
&& i915_fastboot
) {
9763 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9764 config
->fb_changed
= true;
9766 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9767 config
->mode_changed
= true;
9769 } else if (set
->fb
== NULL
) {
9770 config
->mode_changed
= true;
9771 } else if (set
->fb
->pixel_format
!=
9772 set
->crtc
->fb
->pixel_format
) {
9773 config
->mode_changed
= true;
9775 config
->fb_changed
= true;
9779 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9780 config
->fb_changed
= true;
9782 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9783 DRM_DEBUG_KMS("modes are different, full mode set\n");
9784 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9785 drm_mode_debug_printmodeline(set
->mode
);
9786 config
->mode_changed
= true;
9789 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9790 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9794 intel_modeset_stage_output_state(struct drm_device
*dev
,
9795 struct drm_mode_set
*set
,
9796 struct intel_set_config
*config
)
9798 struct drm_crtc
*new_crtc
;
9799 struct intel_connector
*connector
;
9800 struct intel_encoder
*encoder
;
9803 /* The upper layers ensure that we either disable a crtc or have a list
9804 * of connectors. For paranoia, double-check this. */
9805 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9806 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9808 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9810 /* Otherwise traverse passed in connector list and get encoders
9812 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9813 if (set
->connectors
[ro
] == &connector
->base
) {
9814 connector
->new_encoder
= connector
->encoder
;
9819 /* If we disable the crtc, disable all its connectors. Also, if
9820 * the connector is on the changing crtc but not on the new
9821 * connector list, disable it. */
9822 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9823 connector
->base
.encoder
&&
9824 connector
->base
.encoder
->crtc
== set
->crtc
) {
9825 connector
->new_encoder
= NULL
;
9827 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9828 connector
->base
.base
.id
,
9829 drm_get_connector_name(&connector
->base
));
9833 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9834 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9835 config
->mode_changed
= true;
9838 /* connector->new_encoder is now updated for all connectors. */
9840 /* Update crtc of enabled connectors. */
9841 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9843 if (!connector
->new_encoder
)
9846 new_crtc
= connector
->new_encoder
->base
.crtc
;
9848 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9849 if (set
->connectors
[ro
] == &connector
->base
)
9850 new_crtc
= set
->crtc
;
9853 /* Make sure the new CRTC will work with the encoder */
9854 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9858 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9860 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9861 connector
->base
.base
.id
,
9862 drm_get_connector_name(&connector
->base
),
9866 /* Check for any encoders that needs to be disabled. */
9867 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9869 list_for_each_entry(connector
,
9870 &dev
->mode_config
.connector_list
,
9872 if (connector
->new_encoder
== encoder
) {
9873 WARN_ON(!connector
->new_encoder
->new_crtc
);
9878 encoder
->new_crtc
= NULL
;
9880 /* Only now check for crtc changes so we don't miss encoders
9881 * that will be disabled. */
9882 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9883 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9884 config
->mode_changed
= true;
9887 /* Now we've also updated encoder->new_crtc for all encoders. */
9892 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9894 struct drm_device
*dev
;
9895 struct drm_mode_set save_set
;
9896 struct intel_set_config
*config
;
9901 BUG_ON(!set
->crtc
->helper_private
);
9903 /* Enforce sane interface api - has been abused by the fb helper. */
9904 BUG_ON(!set
->mode
&& set
->fb
);
9905 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9908 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9909 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9910 (int)set
->num_connectors
, set
->x
, set
->y
);
9912 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9915 dev
= set
->crtc
->dev
;
9918 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9922 ret
= intel_set_config_save_state(dev
, config
);
9926 save_set
.crtc
= set
->crtc
;
9927 save_set
.mode
= &set
->crtc
->mode
;
9928 save_set
.x
= set
->crtc
->x
;
9929 save_set
.y
= set
->crtc
->y
;
9930 save_set
.fb
= set
->crtc
->fb
;
9932 /* Compute whether we need a full modeset, only an fb base update or no
9933 * change at all. In the future we might also check whether only the
9934 * mode changed, e.g. for LVDS where we only change the panel fitter in
9936 intel_set_config_compute_mode_changes(set
, config
);
9938 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9942 if (config
->mode_changed
) {
9943 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9944 set
->x
, set
->y
, set
->fb
);
9945 } else if (config
->fb_changed
) {
9946 intel_crtc_wait_for_pending_flips(set
->crtc
);
9948 ret
= intel_pipe_set_base(set
->crtc
,
9949 set
->x
, set
->y
, set
->fb
);
9953 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9954 set
->crtc
->base
.id
, ret
);
9956 intel_set_config_restore_state(dev
, config
);
9958 /* Try to restore the config */
9959 if (config
->mode_changed
&&
9960 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9961 save_set
.x
, save_set
.y
, save_set
.fb
))
9962 DRM_ERROR("failed to restore config after modeset failure\n");
9966 intel_set_config_free(config
);
9970 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9971 .cursor_set
= intel_crtc_cursor_set
,
9972 .cursor_move
= intel_crtc_cursor_move
,
9973 .gamma_set
= intel_crtc_gamma_set
,
9974 .set_config
= intel_crtc_set_config
,
9975 .destroy
= intel_crtc_destroy
,
9976 .page_flip
= intel_crtc_page_flip
,
9979 static void intel_cpu_pll_init(struct drm_device
*dev
)
9982 intel_ddi_pll_init(dev
);
9985 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9986 struct intel_shared_dpll
*pll
,
9987 struct intel_dpll_hw_state
*hw_state
)
9991 val
= I915_READ(PCH_DPLL(pll
->id
));
9992 hw_state
->dpll
= val
;
9993 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9994 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9996 return val
& DPLL_VCO_ENABLE
;
9999 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
10000 struct intel_shared_dpll
*pll
)
10002 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
10003 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
10006 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
10007 struct intel_shared_dpll
*pll
)
10009 /* PCH refclock must be enabled first */
10010 assert_pch_refclk_enabled(dev_priv
);
10012 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10014 /* Wait for the clocks to stabilize. */
10015 POSTING_READ(PCH_DPLL(pll
->id
));
10018 /* The pixel multiplier can only be updated once the
10019 * DPLL is enabled and the clocks are stable.
10021 * So write it again.
10023 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10024 POSTING_READ(PCH_DPLL(pll
->id
));
10028 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
10029 struct intel_shared_dpll
*pll
)
10031 struct drm_device
*dev
= dev_priv
->dev
;
10032 struct intel_crtc
*crtc
;
10034 /* Make sure no transcoder isn't still depending on us. */
10035 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
10036 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
10037 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
10040 I915_WRITE(PCH_DPLL(pll
->id
), 0);
10041 POSTING_READ(PCH_DPLL(pll
->id
));
10045 static char *ibx_pch_dpll_names
[] = {
10050 static void ibx_pch_dpll_init(struct drm_device
*dev
)
10052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10055 dev_priv
->num_shared_dpll
= 2;
10057 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10058 dev_priv
->shared_dplls
[i
].id
= i
;
10059 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
10060 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
10061 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
10062 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
10063 dev_priv
->shared_dplls
[i
].get_hw_state
=
10064 ibx_pch_dpll_get_hw_state
;
10068 static void intel_shared_dpll_init(struct drm_device
*dev
)
10070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10072 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
10073 ibx_pch_dpll_init(dev
);
10075 dev_priv
->num_shared_dpll
= 0;
10077 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
10078 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10079 dev_priv
->num_shared_dpll
);
10082 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
10084 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10085 struct intel_crtc
*intel_crtc
;
10088 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
10089 if (intel_crtc
== NULL
)
10092 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
10094 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
10095 for (i
= 0; i
< 256; i
++) {
10096 intel_crtc
->lut_r
[i
] = i
;
10097 intel_crtc
->lut_g
[i
] = i
;
10098 intel_crtc
->lut_b
[i
] = i
;
10101 /* Swap pipes & planes for FBC on pre-965 */
10102 intel_crtc
->pipe
= pipe
;
10103 intel_crtc
->plane
= pipe
;
10104 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
10105 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10106 intel_crtc
->plane
= !pipe
;
10109 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
10110 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
10111 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
10112 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
10114 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
10117 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
10119 struct drm_encoder
*encoder
= connector
->base
.encoder
;
10121 WARN_ON(!mutex_is_locked(&connector
->base
.dev
->mode_config
.mutex
));
10124 return INVALID_PIPE
;
10126 return to_intel_crtc(encoder
->crtc
)->pipe
;
10129 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
10130 struct drm_file
*file
)
10132 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
10133 struct drm_mode_object
*drmmode_obj
;
10134 struct intel_crtc
*crtc
;
10136 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
10139 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
10140 DRM_MODE_OBJECT_CRTC
);
10142 if (!drmmode_obj
) {
10143 DRM_ERROR("no such CRTC id\n");
10147 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
10148 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
10153 static int intel_encoder_clones(struct intel_encoder
*encoder
)
10155 struct drm_device
*dev
= encoder
->base
.dev
;
10156 struct intel_encoder
*source_encoder
;
10157 int index_mask
= 0;
10160 list_for_each_entry(source_encoder
,
10161 &dev
->mode_config
.encoder_list
, base
.head
) {
10163 if (encoder
== source_encoder
)
10164 index_mask
|= (1 << entry
);
10166 /* Intel hw has only one MUX where enocoders could be cloned. */
10167 if (encoder
->cloneable
&& source_encoder
->cloneable
)
10168 index_mask
|= (1 << entry
);
10176 static bool has_edp_a(struct drm_device
*dev
)
10178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10180 if (!IS_MOBILE(dev
))
10183 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
10186 if (IS_GEN5(dev
) &&
10187 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
10193 static void intel_setup_outputs(struct drm_device
*dev
)
10195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10196 struct intel_encoder
*encoder
;
10197 bool dpd_is_edp
= false;
10199 intel_lvds_init(dev
);
10202 intel_crt_init(dev
);
10204 if (HAS_DDI(dev
)) {
10207 /* Haswell uses DDI functions to detect digital outputs */
10208 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
10209 /* DDI A only supports eDP */
10211 intel_ddi_init(dev
, PORT_A
);
10213 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10215 found
= I915_READ(SFUSE_STRAP
);
10217 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
10218 intel_ddi_init(dev
, PORT_B
);
10219 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
10220 intel_ddi_init(dev
, PORT_C
);
10221 if (found
& SFUSE_STRAP_DDID_DETECTED
)
10222 intel_ddi_init(dev
, PORT_D
);
10223 } else if (HAS_PCH_SPLIT(dev
)) {
10225 dpd_is_edp
= intel_dpd_is_edp(dev
);
10227 if (has_edp_a(dev
))
10228 intel_dp_init(dev
, DP_A
, PORT_A
);
10230 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
10231 /* PCH SDVOB multiplex with HDMIB */
10232 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
10234 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
10235 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
10236 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
10239 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
10240 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
10242 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
10243 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
10245 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
10246 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
10248 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
10249 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
10250 } else if (IS_VALLEYVIEW(dev
)) {
10251 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
10252 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
10254 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
10255 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
10258 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
10259 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
10261 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
10262 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
10266 intel_dsi_init(dev
);
10267 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
10268 bool found
= false;
10270 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
10271 DRM_DEBUG_KMS("probing SDVOB\n");
10272 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
10273 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
10274 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10275 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
10278 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
10279 intel_dp_init(dev
, DP_B
, PORT_B
);
10282 /* Before G4X SDVOC doesn't have its own detect register */
10284 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
10285 DRM_DEBUG_KMS("probing SDVOC\n");
10286 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
10289 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
10291 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
10292 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10293 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
10295 if (SUPPORTS_INTEGRATED_DP(dev
))
10296 intel_dp_init(dev
, DP_C
, PORT_C
);
10299 if (SUPPORTS_INTEGRATED_DP(dev
) &&
10300 (I915_READ(DP_D
) & DP_DETECTED
))
10301 intel_dp_init(dev
, DP_D
, PORT_D
);
10302 } else if (IS_GEN2(dev
))
10303 intel_dvo_init(dev
);
10305 if (SUPPORTS_TV(dev
))
10306 intel_tv_init(dev
);
10308 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
10309 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
10310 encoder
->base
.possible_clones
=
10311 intel_encoder_clones(encoder
);
10314 intel_init_pch_refclk(dev
);
10316 drm_helper_move_panel_connectors_to_head(dev
);
10319 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
10321 drm_framebuffer_cleanup(&fb
->base
);
10322 WARN_ON(!fb
->obj
->framebuffer_references
--);
10323 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
10326 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
10328 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
10330 intel_framebuffer_fini(intel_fb
);
10334 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
10335 struct drm_file
*file
,
10336 unsigned int *handle
)
10338 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
10339 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10341 return drm_gem_handle_create(file
, &obj
->base
, handle
);
10344 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
10345 .destroy
= intel_user_framebuffer_destroy
,
10346 .create_handle
= intel_user_framebuffer_create_handle
,
10349 int intel_framebuffer_init(struct drm_device
*dev
,
10350 struct intel_framebuffer
*intel_fb
,
10351 struct drm_mode_fb_cmd2
*mode_cmd
,
10352 struct drm_i915_gem_object
*obj
)
10354 int aligned_height
, tile_height
;
10358 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
10360 if (obj
->tiling_mode
== I915_TILING_Y
) {
10361 DRM_DEBUG("hardware does not support tiling Y\n");
10365 if (mode_cmd
->pitches
[0] & 63) {
10366 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10367 mode_cmd
->pitches
[0]);
10371 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
10372 pitch_limit
= 32*1024;
10373 } else if (INTEL_INFO(dev
)->gen
>= 4) {
10374 if (obj
->tiling_mode
)
10375 pitch_limit
= 16*1024;
10377 pitch_limit
= 32*1024;
10378 } else if (INTEL_INFO(dev
)->gen
>= 3) {
10379 if (obj
->tiling_mode
)
10380 pitch_limit
= 8*1024;
10382 pitch_limit
= 16*1024;
10384 /* XXX DSPC is limited to 4k tiled */
10385 pitch_limit
= 8*1024;
10387 if (mode_cmd
->pitches
[0] > pitch_limit
) {
10388 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10389 obj
->tiling_mode
? "tiled" : "linear",
10390 mode_cmd
->pitches
[0], pitch_limit
);
10394 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
10395 mode_cmd
->pitches
[0] != obj
->stride
) {
10396 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10397 mode_cmd
->pitches
[0], obj
->stride
);
10401 /* Reject formats not supported by any plane early. */
10402 switch (mode_cmd
->pixel_format
) {
10403 case DRM_FORMAT_C8
:
10404 case DRM_FORMAT_RGB565
:
10405 case DRM_FORMAT_XRGB8888
:
10406 case DRM_FORMAT_ARGB8888
:
10408 case DRM_FORMAT_XRGB1555
:
10409 case DRM_FORMAT_ARGB1555
:
10410 if (INTEL_INFO(dev
)->gen
> 3) {
10411 DRM_DEBUG("unsupported pixel format: %s\n",
10412 drm_get_format_name(mode_cmd
->pixel_format
));
10416 case DRM_FORMAT_XBGR8888
:
10417 case DRM_FORMAT_ABGR8888
:
10418 case DRM_FORMAT_XRGB2101010
:
10419 case DRM_FORMAT_ARGB2101010
:
10420 case DRM_FORMAT_XBGR2101010
:
10421 case DRM_FORMAT_ABGR2101010
:
10422 if (INTEL_INFO(dev
)->gen
< 4) {
10423 DRM_DEBUG("unsupported pixel format: %s\n",
10424 drm_get_format_name(mode_cmd
->pixel_format
));
10428 case DRM_FORMAT_YUYV
:
10429 case DRM_FORMAT_UYVY
:
10430 case DRM_FORMAT_YVYU
:
10431 case DRM_FORMAT_VYUY
:
10432 if (INTEL_INFO(dev
)->gen
< 5) {
10433 DRM_DEBUG("unsupported pixel format: %s\n",
10434 drm_get_format_name(mode_cmd
->pixel_format
));
10439 DRM_DEBUG("unsupported pixel format: %s\n",
10440 drm_get_format_name(mode_cmd
->pixel_format
));
10444 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10445 if (mode_cmd
->offsets
[0] != 0)
10448 tile_height
= IS_GEN2(dev
) ? 16 : 8;
10449 aligned_height
= ALIGN(mode_cmd
->height
,
10450 obj
->tiling_mode
? tile_height
: 1);
10451 /* FIXME drm helper for size checks (especially planar formats)? */
10452 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
10455 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
10456 intel_fb
->obj
= obj
;
10457 intel_fb
->obj
->framebuffer_references
++;
10459 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
10461 DRM_ERROR("framebuffer init failed %d\n", ret
);
10468 static struct drm_framebuffer
*
10469 intel_user_framebuffer_create(struct drm_device
*dev
,
10470 struct drm_file
*filp
,
10471 struct drm_mode_fb_cmd2
*mode_cmd
)
10473 struct drm_i915_gem_object
*obj
;
10475 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
10476 mode_cmd
->handles
[0]));
10477 if (&obj
->base
== NULL
)
10478 return ERR_PTR(-ENOENT
);
10480 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
10483 #ifndef CONFIG_DRM_I915_FBDEV
10484 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
10489 static const struct drm_mode_config_funcs intel_mode_funcs
= {
10490 .fb_create
= intel_user_framebuffer_create
,
10491 .output_poll_changed
= intel_fbdev_output_poll_changed
,
10494 /* Set up chip specific display functions */
10495 static void intel_init_display(struct drm_device
*dev
)
10497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10499 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
10500 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
10501 else if (IS_VALLEYVIEW(dev
))
10502 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
10503 else if (IS_PINEVIEW(dev
))
10504 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
10506 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
10508 if (HAS_DDI(dev
)) {
10509 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
10510 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
10511 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
10512 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
10513 dev_priv
->display
.off
= haswell_crtc_off
;
10514 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10515 } else if (HAS_PCH_SPLIT(dev
)) {
10516 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10517 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10518 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10519 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10520 dev_priv
->display
.off
= ironlake_crtc_off
;
10521 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10522 } else if (IS_VALLEYVIEW(dev
)) {
10523 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10524 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10525 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10526 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10527 dev_priv
->display
.off
= i9xx_crtc_off
;
10528 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10530 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10531 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10532 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10533 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10534 dev_priv
->display
.off
= i9xx_crtc_off
;
10535 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10538 /* Returns the core display clock speed */
10539 if (IS_VALLEYVIEW(dev
))
10540 dev_priv
->display
.get_display_clock_speed
=
10541 valleyview_get_display_clock_speed
;
10542 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10543 dev_priv
->display
.get_display_clock_speed
=
10544 i945_get_display_clock_speed
;
10545 else if (IS_I915G(dev
))
10546 dev_priv
->display
.get_display_clock_speed
=
10547 i915_get_display_clock_speed
;
10548 else if (IS_I945GM(dev
) || IS_845G(dev
))
10549 dev_priv
->display
.get_display_clock_speed
=
10550 i9xx_misc_get_display_clock_speed
;
10551 else if (IS_PINEVIEW(dev
))
10552 dev_priv
->display
.get_display_clock_speed
=
10553 pnv_get_display_clock_speed
;
10554 else if (IS_I915GM(dev
))
10555 dev_priv
->display
.get_display_clock_speed
=
10556 i915gm_get_display_clock_speed
;
10557 else if (IS_I865G(dev
))
10558 dev_priv
->display
.get_display_clock_speed
=
10559 i865_get_display_clock_speed
;
10560 else if (IS_I85X(dev
))
10561 dev_priv
->display
.get_display_clock_speed
=
10562 i855_get_display_clock_speed
;
10563 else /* 852, 830 */
10564 dev_priv
->display
.get_display_clock_speed
=
10565 i830_get_display_clock_speed
;
10567 if (HAS_PCH_SPLIT(dev
)) {
10568 if (IS_GEN5(dev
)) {
10569 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10570 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10571 } else if (IS_GEN6(dev
)) {
10572 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10573 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10574 } else if (IS_IVYBRIDGE(dev
)) {
10575 /* FIXME: detect B0+ stepping and use auto training */
10576 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10577 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10578 dev_priv
->display
.modeset_global_resources
=
10579 ivb_modeset_global_resources
;
10580 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
10581 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10582 dev_priv
->display
.write_eld
= haswell_write_eld
;
10583 dev_priv
->display
.modeset_global_resources
=
10584 haswell_modeset_global_resources
;
10586 } else if (IS_G4X(dev
)) {
10587 dev_priv
->display
.write_eld
= g4x_write_eld
;
10588 } else if (IS_VALLEYVIEW(dev
)) {
10589 dev_priv
->display
.modeset_global_resources
=
10590 valleyview_modeset_global_resources
;
10591 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10594 /* Default just returns -ENODEV to indicate unsupported */
10595 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10597 switch (INTEL_INFO(dev
)->gen
) {
10599 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10603 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10608 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10612 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10615 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10616 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10620 intel_panel_init_backlight_funcs(dev
);
10624 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10625 * resume, or other times. This quirk makes sure that's the case for
10626 * affected systems.
10628 static void quirk_pipea_force(struct drm_device
*dev
)
10630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10632 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10633 DRM_INFO("applying pipe a force quirk\n");
10637 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10639 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10642 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10643 DRM_INFO("applying lvds SSC disable quirk\n");
10647 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10650 static void quirk_invert_brightness(struct drm_device
*dev
)
10652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10653 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10654 DRM_INFO("applying inverted panel brightness quirk\n");
10657 struct intel_quirk
{
10659 int subsystem_vendor
;
10660 int subsystem_device
;
10661 void (*hook
)(struct drm_device
*dev
);
10664 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10665 struct intel_dmi_quirk
{
10666 void (*hook
)(struct drm_device
*dev
);
10667 const struct dmi_system_id (*dmi_id_list
)[];
10670 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10672 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10676 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10678 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10680 .callback
= intel_dmi_reverse_brightness
,
10681 .ident
= "NCR Corporation",
10682 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10683 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10686 { } /* terminating entry */
10688 .hook
= quirk_invert_brightness
,
10692 static struct intel_quirk intel_quirks
[] = {
10693 /* HP Mini needs pipe A force quirk (LP: #322104) */
10694 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10696 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10697 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10699 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10700 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10702 /* 830 needs to leave pipe A & dpll A up */
10703 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10705 /* Lenovo U160 cannot use SSC on LVDS */
10706 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10708 /* Sony Vaio Y cannot use SSC on LVDS */
10709 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10712 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10713 * seem to use inverted backlight PWM.
10715 { 0x2a42, 0x1025, PCI_ANY_ID
, quirk_invert_brightness
},
10718 static void intel_init_quirks(struct drm_device
*dev
)
10720 struct pci_dev
*d
= dev
->pdev
;
10723 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10724 struct intel_quirk
*q
= &intel_quirks
[i
];
10726 if (d
->device
== q
->device
&&
10727 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10728 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10729 (d
->subsystem_device
== q
->subsystem_device
||
10730 q
->subsystem_device
== PCI_ANY_ID
))
10733 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10734 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10735 intel_dmi_quirks
[i
].hook(dev
);
10739 /* Disable the VGA plane that we never use */
10740 static void i915_disable_vga(struct drm_device
*dev
)
10742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10744 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10746 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10747 outb(SR01
, VGA_SR_INDEX
);
10748 sr1
= inb(VGA_SR_DATA
);
10749 outb(sr1
| 1<<5, VGA_SR_DATA
);
10750 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10753 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10754 POSTING_READ(vga_reg
);
10757 void intel_modeset_init_hw(struct drm_device
*dev
)
10759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10761 intel_prepare_ddi(dev
);
10763 intel_init_clock_gating(dev
);
10765 /* Enable the CRI clock source so we can get at the display */
10766 if (IS_VALLEYVIEW(dev
))
10767 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
10768 DPLL_INTEGRATED_CRI_CLK_VLV
);
10770 intel_init_dpio(dev
);
10772 mutex_lock(&dev
->struct_mutex
);
10773 intel_enable_gt_powersave(dev
);
10774 mutex_unlock(&dev
->struct_mutex
);
10777 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10779 intel_suspend_hw(dev
);
10782 void intel_modeset_init(struct drm_device
*dev
)
10784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10787 drm_mode_config_init(dev
);
10789 dev
->mode_config
.min_width
= 0;
10790 dev
->mode_config
.min_height
= 0;
10792 dev
->mode_config
.preferred_depth
= 24;
10793 dev
->mode_config
.prefer_shadow
= 1;
10795 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10797 intel_init_quirks(dev
);
10799 intel_init_pm(dev
);
10801 if (INTEL_INFO(dev
)->num_pipes
== 0)
10804 intel_init_display(dev
);
10806 if (IS_GEN2(dev
)) {
10807 dev
->mode_config
.max_width
= 2048;
10808 dev
->mode_config
.max_height
= 2048;
10809 } else if (IS_GEN3(dev
)) {
10810 dev
->mode_config
.max_width
= 4096;
10811 dev
->mode_config
.max_height
= 4096;
10813 dev
->mode_config
.max_width
= 8192;
10814 dev
->mode_config
.max_height
= 8192;
10816 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10818 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10819 INTEL_INFO(dev
)->num_pipes
,
10820 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10823 intel_crtc_init(dev
, i
);
10824 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10825 ret
= intel_plane_init(dev
, i
, j
);
10827 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10828 pipe_name(i
), sprite_name(i
, j
), ret
);
10832 intel_cpu_pll_init(dev
);
10833 intel_shared_dpll_init(dev
);
10835 /* Just disable it once at startup */
10836 i915_disable_vga(dev
);
10837 intel_setup_outputs(dev
);
10839 /* Just in case the BIOS is doing something questionable. */
10840 intel_disable_fbc(dev
);
10844 intel_connector_break_all_links(struct intel_connector
*connector
)
10846 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10847 connector
->base
.encoder
= NULL
;
10848 connector
->encoder
->connectors_active
= false;
10849 connector
->encoder
->base
.crtc
= NULL
;
10852 static void intel_enable_pipe_a(struct drm_device
*dev
)
10854 struct intel_connector
*connector
;
10855 struct drm_connector
*crt
= NULL
;
10856 struct intel_load_detect_pipe load_detect_temp
;
10858 /* We can't just switch on the pipe A, we need to set things up with a
10859 * proper mode and output configuration. As a gross hack, enable pipe A
10860 * by enabling the load detect pipe once. */
10861 list_for_each_entry(connector
,
10862 &dev
->mode_config
.connector_list
,
10864 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10865 crt
= &connector
->base
;
10873 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10874 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10880 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10882 struct drm_device
*dev
= crtc
->base
.dev
;
10883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10886 if (INTEL_INFO(dev
)->num_pipes
== 1)
10889 reg
= DSPCNTR(!crtc
->plane
);
10890 val
= I915_READ(reg
);
10892 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10893 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10899 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10901 struct drm_device
*dev
= crtc
->base
.dev
;
10902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10905 /* Clear any frame start delays used for debugging left by the BIOS */
10906 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10907 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10909 /* We need to sanitize the plane -> pipe mapping first because this will
10910 * disable the crtc (and hence change the state) if it is wrong. Note
10911 * that gen4+ has a fixed plane -> pipe mapping. */
10912 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10913 struct intel_connector
*connector
;
10916 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10917 crtc
->base
.base
.id
);
10919 /* Pipe has the wrong plane attached and the plane is active.
10920 * Temporarily change the plane mapping and disable everything
10922 plane
= crtc
->plane
;
10923 crtc
->plane
= !plane
;
10924 dev_priv
->display
.crtc_disable(&crtc
->base
);
10925 crtc
->plane
= plane
;
10927 /* ... and break all links. */
10928 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10930 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10933 intel_connector_break_all_links(connector
);
10936 WARN_ON(crtc
->active
);
10937 crtc
->base
.enabled
= false;
10940 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10941 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10942 /* BIOS forgot to enable pipe A, this mostly happens after
10943 * resume. Force-enable the pipe to fix this, the update_dpms
10944 * call below we restore the pipe to the right state, but leave
10945 * the required bits on. */
10946 intel_enable_pipe_a(dev
);
10949 /* Adjust the state of the output pipe according to whether we
10950 * have active connectors/encoders. */
10951 intel_crtc_update_dpms(&crtc
->base
);
10953 if (crtc
->active
!= crtc
->base
.enabled
) {
10954 struct intel_encoder
*encoder
;
10956 /* This can happen either due to bugs in the get_hw_state
10957 * functions or because the pipe is force-enabled due to the
10959 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10960 crtc
->base
.base
.id
,
10961 crtc
->base
.enabled
? "enabled" : "disabled",
10962 crtc
->active
? "enabled" : "disabled");
10964 crtc
->base
.enabled
= crtc
->active
;
10966 /* Because we only establish the connector -> encoder ->
10967 * crtc links if something is active, this means the
10968 * crtc is now deactivated. Break the links. connector
10969 * -> encoder links are only establish when things are
10970 * actually up, hence no need to break them. */
10971 WARN_ON(crtc
->active
);
10973 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10974 WARN_ON(encoder
->connectors_active
);
10975 encoder
->base
.crtc
= NULL
;
10980 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10982 struct intel_connector
*connector
;
10983 struct drm_device
*dev
= encoder
->base
.dev
;
10985 /* We need to check both for a crtc link (meaning that the
10986 * encoder is active and trying to read from a pipe) and the
10987 * pipe itself being active. */
10988 bool has_active_crtc
= encoder
->base
.crtc
&&
10989 to_intel_crtc(encoder
->base
.crtc
)->active
;
10991 if (encoder
->connectors_active
&& !has_active_crtc
) {
10992 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10993 encoder
->base
.base
.id
,
10994 drm_get_encoder_name(&encoder
->base
));
10996 /* Connector is active, but has no active pipe. This is
10997 * fallout from our resume register restoring. Disable
10998 * the encoder manually again. */
10999 if (encoder
->base
.crtc
) {
11000 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11001 encoder
->base
.base
.id
,
11002 drm_get_encoder_name(&encoder
->base
));
11003 encoder
->disable(encoder
);
11006 /* Inconsistent output/port/pipe state happens presumably due to
11007 * a bug in one of the get_hw_state functions. Or someplace else
11008 * in our code, like the register restore mess on resume. Clamp
11009 * things to off as a safer default. */
11010 list_for_each_entry(connector
,
11011 &dev
->mode_config
.connector_list
,
11013 if (connector
->encoder
!= encoder
)
11016 intel_connector_break_all_links(connector
);
11019 /* Enabled encoders without active connectors will be fixed in
11020 * the crtc fixup. */
11023 void i915_redisable_vga(struct drm_device
*dev
)
11025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11026 u32 vga_reg
= i915_vgacntrl_reg(dev
);
11028 /* This function can be called both from intel_modeset_setup_hw_state or
11029 * at a very early point in our resume sequence, where the power well
11030 * structures are not yet restored. Since this function is at a very
11031 * paranoid "someone might have enabled VGA while we were not looking"
11032 * level, just check if the power well is enabled instead of trying to
11033 * follow the "don't touch the power well if we don't need it" policy
11034 * the rest of the driver uses. */
11035 if ((IS_HASWELL(dev
) || IS_BROADWELL(dev
)) &&
11036 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
11039 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
11040 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11041 i915_disable_vga(dev
);
11045 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
11047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11049 struct intel_crtc
*crtc
;
11050 struct intel_encoder
*encoder
;
11051 struct intel_connector
*connector
;
11054 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11056 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
11058 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
11061 crtc
->base
.enabled
= crtc
->active
;
11062 crtc
->primary_enabled
= crtc
->active
;
11064 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11065 crtc
->base
.base
.id
,
11066 crtc
->active
? "enabled" : "disabled");
11069 /* FIXME: Smash this into the new shared dpll infrastructure. */
11071 intel_ddi_setup_hw_pll_state(dev
);
11073 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11074 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11076 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
11078 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11080 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11083 pll
->refcount
= pll
->active
;
11085 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11086 pll
->name
, pll
->refcount
, pll
->on
);
11089 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11093 if (encoder
->get_hw_state(encoder
, &pipe
)) {
11094 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
11095 encoder
->base
.crtc
= &crtc
->base
;
11096 if (encoder
->get_config
)
11097 encoder
->get_config(encoder
, &crtc
->config
);
11099 encoder
->base
.crtc
= NULL
;
11102 encoder
->connectors_active
= false;
11103 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11104 encoder
->base
.base
.id
,
11105 drm_get_encoder_name(&encoder
->base
),
11106 encoder
->base
.crtc
? "enabled" : "disabled",
11110 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11112 if (connector
->get_hw_state(connector
)) {
11113 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
11114 connector
->encoder
->connectors_active
= true;
11115 connector
->base
.encoder
= &connector
->encoder
->base
;
11117 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
11118 connector
->base
.encoder
= NULL
;
11120 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11121 connector
->base
.base
.id
,
11122 drm_get_connector_name(&connector
->base
),
11123 connector
->base
.encoder
? "enabled" : "disabled");
11127 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11128 * and i915 state tracking structures. */
11129 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
11130 bool force_restore
)
11132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11134 struct intel_crtc
*crtc
;
11135 struct intel_encoder
*encoder
;
11138 intel_modeset_readout_hw_state(dev
);
11141 * Now that we have the config, copy it to each CRTC struct
11142 * Note that this could go away if we move to using crtc_config
11143 * checking everywhere.
11145 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11147 if (crtc
->active
&& i915_fastboot
) {
11148 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
11150 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11151 crtc
->base
.base
.id
);
11152 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
11156 /* HW state is read out, now we need to sanitize this mess. */
11157 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11159 intel_sanitize_encoder(encoder
);
11162 for_each_pipe(pipe
) {
11163 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
11164 intel_sanitize_crtc(crtc
);
11165 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
11168 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11169 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11171 if (!pll
->on
|| pll
->active
)
11174 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
11176 pll
->disable(dev_priv
, pll
);
11180 if (IS_HASWELL(dev
))
11181 ilk_wm_get_hw_state(dev
);
11183 if (force_restore
) {
11184 i915_redisable_vga(dev
);
11187 * We need to use raw interfaces for restoring state to avoid
11188 * checking (bogus) intermediate states.
11190 for_each_pipe(pipe
) {
11191 struct drm_crtc
*crtc
=
11192 dev_priv
->pipe_to_crtc_mapping
[pipe
];
11194 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
11198 intel_modeset_update_staged_output_state(dev
);
11201 intel_modeset_check_state(dev
);
11203 drm_mode_config_reset(dev
);
11206 void intel_modeset_gem_init(struct drm_device
*dev
)
11208 intel_modeset_init_hw(dev
);
11210 intel_setup_overlay(dev
);
11212 intel_modeset_setup_hw_state(dev
, false);
11215 void intel_modeset_cleanup(struct drm_device
*dev
)
11217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11218 struct drm_crtc
*crtc
;
11219 struct drm_connector
*connector
;
11222 * Interrupts and polling as the first thing to avoid creating havoc.
11223 * Too much stuff here (turning of rps, connectors, ...) would
11224 * experience fancy races otherwise.
11226 drm_irq_uninstall(dev
);
11227 cancel_work_sync(&dev_priv
->hotplug_work
);
11229 * Due to the hpd irq storm handling the hotplug work can re-arm the
11230 * poll handlers. Hence disable polling after hpd handling is shut down.
11232 drm_kms_helper_poll_fini(dev
);
11234 mutex_lock(&dev
->struct_mutex
);
11236 intel_unregister_dsm_handler();
11238 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
11239 /* Skip inactive CRTCs */
11243 intel_increase_pllclock(crtc
);
11246 intel_disable_fbc(dev
);
11248 intel_disable_gt_powersave(dev
);
11250 ironlake_teardown_rc6(dev
);
11252 mutex_unlock(&dev
->struct_mutex
);
11254 /* flush any delayed tasks or pending work */
11255 flush_scheduled_work();
11257 /* destroy the backlight and sysfs files before encoders/connectors */
11258 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11259 intel_panel_destroy_backlight(connector
);
11260 drm_sysfs_connector_remove(connector
);
11263 drm_mode_config_cleanup(dev
);
11265 intel_cleanup_overlay(dev
);
11269 * Return which encoder is currently attached for connector.
11271 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
11273 return &intel_attached_encoder(connector
)->base
;
11276 void intel_connector_attach_encoder(struct intel_connector
*connector
,
11277 struct intel_encoder
*encoder
)
11279 connector
->encoder
= encoder
;
11280 drm_mode_connector_attach_encoder(&connector
->base
,
11285 * set vga decode state - true == enable VGA decode
11287 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
11289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11292 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
11294 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
11296 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
11297 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
11301 struct intel_display_error_state
{
11303 u32 power_well_driver
;
11305 int num_transcoders
;
11307 struct intel_cursor_error_state
{
11312 } cursor
[I915_MAX_PIPES
];
11314 struct intel_pipe_error_state
{
11316 } pipe
[I915_MAX_PIPES
];
11318 struct intel_plane_error_state
{
11326 } plane
[I915_MAX_PIPES
];
11328 struct intel_transcoder_error_state
{
11329 enum transcoder cpu_transcoder
;
11342 struct intel_display_error_state
*
11343 intel_display_capture_error_state(struct drm_device
*dev
)
11345 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
11346 struct intel_display_error_state
*error
;
11347 int transcoders
[] = {
11355 if (INTEL_INFO(dev
)->num_pipes
== 0)
11358 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
11362 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
11363 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
11366 if (!intel_display_power_enabled(dev
, POWER_DOMAIN_PIPE(i
)))
11369 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
11370 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
11371 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
11372 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
11374 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
11375 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
11376 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
11379 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
11380 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
11381 if (INTEL_INFO(dev
)->gen
<= 3) {
11382 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
11383 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
11385 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11386 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
11387 if (INTEL_INFO(dev
)->gen
>= 4) {
11388 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
11389 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
11392 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
11395 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
11396 if (HAS_DDI(dev_priv
->dev
))
11397 error
->num_transcoders
++; /* Account for eDP. */
11399 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11400 enum transcoder cpu_transcoder
= transcoders
[i
];
11402 if (!intel_display_power_enabled(dev
,
11403 POWER_DOMAIN_TRANSCODER(cpu_transcoder
)))
11406 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
11408 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
11409 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
11410 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
11411 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
11412 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
11413 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
11414 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
11420 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11423 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
11424 struct drm_device
*dev
,
11425 struct intel_display_error_state
*error
)
11432 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
11433 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
11434 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
11435 error
->power_well_driver
);
11437 err_printf(m
, "Pipe [%d]:\n", i
);
11438 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
11440 err_printf(m
, "Plane [%d]:\n", i
);
11441 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
11442 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
11443 if (INTEL_INFO(dev
)->gen
<= 3) {
11444 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
11445 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
11447 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11448 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
11449 if (INTEL_INFO(dev
)->gen
>= 4) {
11450 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
11451 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
11454 err_printf(m
, "Cursor [%d]:\n", i
);
11455 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
11456 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
11457 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
11460 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11461 err_printf(m
, "CPU transcoder: %c\n",
11462 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
11463 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
11464 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
11465 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
11466 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
11467 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
11468 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
11469 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);