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drm/i915: Don't use the intel_ prefix for gen-specific data
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t i8xx_primary_formats[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t i965_primary_formats[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc,
86 struct drm_atomic_state *state);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
107 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
109 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
111
112 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113 {
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118 }
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 int
136 intel_pch_rawclk(struct drm_device *dev)
137 {
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143 }
144
145 static inline u32 /* units of 100MHz */
146 intel_fdi_link_freq(struct drm_device *dev)
147 {
148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
153 }
154
155 static const intel_limit_t intel_limits_i8xx_dac = {
156 .dot = { .min = 25000, .max = 350000 },
157 .vco = { .min = 908000, .max = 1512000 },
158 .n = { .min = 2, .max = 16 },
159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
166 };
167
168 static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
170 .vco = { .min = 908000, .max = 1512000 },
171 .n = { .min = 2, .max = 16 },
172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179 };
180
181 static const intel_limit_t intel_limits_i8xx_lvds = {
182 .dot = { .min = 25000, .max = 350000 },
183 .vco = { .min = 908000, .max = 1512000 },
184 .n = { .min = 2, .max = 16 },
185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
192 };
193
194 static const intel_limit_t intel_limits_i9xx_sdvo = {
195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
205 };
206
207 static const intel_limit_t intel_limits_i9xx_lvds = {
208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
218 };
219
220
221 static const intel_limit_t intel_limits_g4x_sdvo = {
222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
233 },
234 };
235
236 static const intel_limit_t intel_limits_g4x_hdmi = {
237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
247 };
248
249 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
260 },
261 };
262
263 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
274 },
275 };
276
277 static const intel_limit_t intel_limits_pineview_sdvo = {
278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
280 /* Pineview's Ncounter is a ring counter */
281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
283 /* Pineview only has one combined m divider, which we treat as m2. */
284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
290 };
291
292 static const intel_limit_t intel_limits_pineview_lvds = {
293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
303 };
304
305 /* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
310 static const intel_limit_t intel_limits_ironlake_dac = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
321 };
322
323 static const intel_limit_t intel_limits_ironlake_single_lvds = {
324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
334 };
335
336 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
347 };
348
349 /* LVDS 100mhz refclk limits. */
350 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
358 .p1 = { .min = 2, .max = 8 },
359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 };
375
376 static const intel_limit_t intel_limits_vlv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
384 .vco = { .min = 4000000, .max = 6000000 },
385 .n = { .min = 1, .max = 7 },
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p1 = { .min = 2, .max = 3 },
389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
390 };
391
392 static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
400 .vco = { .min = 4800000, .max = 6480000 },
401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406 };
407
408 static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418 };
419
420 static void vlv_clock(int refclk, intel_clock_t *clock)
421 {
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
428 }
429
430 /**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
433 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
439 if (encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 /**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
451 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
453 {
454 struct drm_atomic_state *state = crtc_state->base.state;
455 struct drm_connector *connector;
456 struct drm_connector_state *connector_state;
457 struct intel_encoder *encoder;
458 int i, num_connectors = 0;
459
460 for_each_connector_in_state(state, connector, connector_state, i) {
461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
465
466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
468 return true;
469 }
470
471 WARN_ON(num_connectors == 0);
472
473 return false;
474 }
475
476 static const intel_limit_t *
477 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
478 {
479 struct drm_device *dev = crtc_state->base.crtc->dev;
480 const intel_limit_t *limit;
481
482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
483 if (intel_is_dual_link_lvds(dev)) {
484 if (refclk == 100000)
485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
489 if (refclk == 100000)
490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
494 } else
495 limit = &intel_limits_ironlake_dac;
496
497 return limit;
498 }
499
500 static const intel_limit_t *
501 intel_g4x_limit(struct intel_crtc_state *crtc_state)
502 {
503 struct drm_device *dev = crtc_state->base.crtc->dev;
504 const intel_limit_t *limit;
505
506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
507 if (intel_is_dual_link_lvds(dev))
508 limit = &intel_limits_g4x_dual_channel_lvds;
509 else
510 limit = &intel_limits_g4x_single_channel_lvds;
511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
513 limit = &intel_limits_g4x_hdmi;
514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
515 limit = &intel_limits_g4x_sdvo;
516 } else /* The option is for other outputs */
517 limit = &intel_limits_i9xx_sdvo;
518
519 return limit;
520 }
521
522 static const intel_limit_t *
523 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
524 {
525 struct drm_device *dev = crtc_state->base.crtc->dev;
526 const intel_limit_t *limit;
527
528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
531 limit = intel_ironlake_limit(crtc_state, refclk);
532 else if (IS_G4X(dev)) {
533 limit = intel_g4x_limit(crtc_state);
534 } else if (IS_PINEVIEW(dev)) {
535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
536 limit = &intel_limits_pineview_lvds;
537 else
538 limit = &intel_limits_pineview_sdvo;
539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
541 } else if (IS_VALLEYVIEW(dev)) {
542 limit = &intel_limits_vlv;
543 } else if (!IS_GEN2(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
548 } else {
549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
550 limit = &intel_limits_i8xx_lvds;
551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
552 limit = &intel_limits_i8xx_dvo;
553 else
554 limit = &intel_limits_i8xx_dac;
555 }
556 return limit;
557 }
558
559 /* m1 is reserved as 0 in Pineview, n is a ring counter */
560 static void pineview_clock(int refclk, intel_clock_t *clock)
561 {
562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568 }
569
570 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 {
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573 }
574
575 static void i9xx_clock(int refclk, intel_clock_t *clock)
576 {
577 clock->m = i9xx_dpll_compute_m(clock);
578 clock->p = clock->p1 * clock->p2;
579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
583 }
584
585 static void chv_clock(int refclk, intel_clock_t *clock)
586 {
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 }
595
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
597 /**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
602 static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
605 {
606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
613 INTELPllInvalid("m1 out of range\n");
614
615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid("dot out of range\n");
633
634 return true;
635 }
636
637 static bool
638 i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642 {
643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
644 struct drm_device *dev = crtc->base.dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 if (clock.m2 >= clock.m1)
672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
677 int this_err;
678
679 i9xx_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698 }
699
700 static bool
701 pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
707 struct drm_device *dev = crtc->base.dev;
708 intel_clock_t clock;
709 int err = target;
710
711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
712 /*
713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
716 */
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 static bool
762 g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
766 {
767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
768 struct drm_device *dev = crtc->base.dev;
769 intel_clock_t clock;
770 int max_n;
771 bool found;
772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
774 found = false;
775
776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
777 if (intel_is_dual_link_lvds(dev))
778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
790 /* based on hardware requirement, prefer smaller n to precision */
791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
792 /* based on hardware requirement, prefere larger m1,m2 */
793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
801 i9xx_clock(refclk, &clock);
802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
804 continue;
805
806 this_err = abs(clock.dot - target);
807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
817 return found;
818 }
819
820 /*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829 {
830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858 }
859
860 static bool
861 vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
867 struct drm_device *dev = crtc->base.dev;
868 intel_clock_t clock;
869 unsigned int bestppm = 1000000;
870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
872 bool found = false;
873
874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
877
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
883 clock.p = clock.p1 * clock.p2;
884 /* based on hardware requirement, prefer bigger m1,m2 values */
885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
886 unsigned int ppm;
887
888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
890
891 vlv_clock(refclk, &clock);
892
893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
895 continue;
896
897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
902
903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
906 }
907 }
908 }
909 }
910
911 return found;
912 }
913
914 static bool
915 chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919 {
920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
921 struct drm_device *dev = crtc->base.dev;
922 unsigned int best_error_ppm;
923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
928 best_error_ppm = 1000000;
929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
942 unsigned int error_ppm;
943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
966 }
967 }
968
969 return found;
970 }
971
972 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974 {
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979 }
980
981 bool intel_crtc_active(struct drm_crtc *crtc)
982 {
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
988 * We can ditch the adjusted_mode.crtc_clock check as soon
989 * as Haswell has gained clock readout/fastboot support.
990 *
991 * We can ditch the crtc->primary->fb check as soon as we can
992 * properly reconstruct framebuffers.
993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
997 */
998 return intel_crtc->active && crtc->primary->state->fb &&
999 intel_crtc->config->base.adjusted_mode.crtc_clock;
1000 }
1001
1002 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004 {
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
1008 return intel_crtc->config->cpu_transcoder;
1009 }
1010
1011 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012 {
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028 }
1029
1030 /*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
1032 * @crtc: crtc whose pipe to wait for
1033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
1044 *
1045 */
1046 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1047 {
1048 struct drm_device *dev = crtc->base.dev;
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1051 enum pipe pipe = crtc->pipe;
1052
1053 if (INTEL_INFO(dev)->gen >= 4) {
1054 int reg = PIPECONF(cpu_transcoder);
1055
1056 /* Wait for the Pipe State to go off */
1057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
1059 WARN(1, "pipe_off wait timed out\n");
1060 } else {
1061 /* Wait for the display line to settle */
1062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 }
1065 }
1066
1067 /*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076 {
1077 u32 bit;
1078
1079 if (HAS_PCH_IBX(dev_priv->dev)) {
1080 switch (port->port) {
1081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
1094 switch (port->port) {
1095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114 return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
1128 I915_STATE_WARN(cur_state != state,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
1144 I915_STATE_WARN(cur_state != state,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156 if (crtc->config->shared_dpll < 0)
1157 return NULL;
1158
1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
1166 {
1167 bool cur_state;
1168 struct intel_dpll_hw_state hw_state;
1169
1170 if (WARN (!pll,
1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
1172 return;
1173
1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175 I915_STATE_WARN(cur_state != state,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
1188
1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208 {
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
1216 I915_STATE_WARN(cur_state != state,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225 {
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231 return;
1232
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv->dev))
1235 return;
1236
1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252 I915_STATE_WARN(cur_state != state,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259 {
1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
1264 bool locked = true;
1265
1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
1272 pp_reg = PCH_PP_CONTROL;
1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
1283 } else {
1284 pp_reg = PP_CONTROL;
1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292 locked = false;
1293
1294 I915_STATE_WARN(panel_pipe == pipe && locked,
1295 "panel assertion failure, pipe %c regs locked\n",
1296 pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
1305 if (IS_845G(dev) || IS_I865G(dev))
1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307 else
1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310 I915_STATE_WARN(cur_state != state,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
1319 {
1320 int reg;
1321 u32 val;
1322 bool cur_state;
1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
1325
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329 state = true;
1330
1331 if (!intel_display_power_is_enabled(dev_priv,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
1340 I915_STATE_WARN(cur_state != state,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
1347 {
1348 int reg;
1349 u32 val;
1350 bool cur_state;
1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355 I915_STATE_WARN(cur_state != state,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365 {
1366 struct drm_device *dev = dev_priv->dev;
1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
1378 return;
1379 }
1380
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv, i) {
1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395 {
1396 struct drm_device *dev = dev_priv->dev;
1397 int reg, sprite;
1398 u32 val;
1399
1400 if (INTEL_INFO(dev)->gen >= 9) {
1401 for_each_sprite(dev_priv, pipe, sprite) {
1402 val = I915_READ(PLANE_CTL(pipe, sprite));
1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 reg = SPCNTR(pipe, sprite);
1410 val = I915_READ(reg);
1411 I915_STATE_WARN(val & SP_ENABLE,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe, sprite), pipe_name(pipe));
1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
1424 I915_STATE_WARN(val & DVS_ENABLE,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
1427 }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438 u32 val;
1439 bool enabled;
1440
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
1451 {
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
1456 reg = PCH_TRANSCONF(pipe);
1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
1459 I915_STATE_WARN(enabled,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487 {
1488 if ((val & SDVO_ENABLE) == 0)
1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493 return false;
1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1497 } else {
1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499 return false;
1500 }
1501 return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506 {
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522 {
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, int reg, u32 port_sel)
1537 {
1538 u32 val = I915_READ(reg);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg, pipe_name(pipe));
1542
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544 && (val & DP_PIPEB_SELECT),
1545 "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550 {
1551 u32 val = I915_READ(reg);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg, pipe_name(pipe));
1555
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557 && (val & SDVO_PIPE_B_SELECT),
1558 "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563 {
1564 int reg;
1565 u32 val;
1566
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 pipe_name(pipe));
1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609 const struct intel_crtc_state *pipe_config)
1610 {
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv->dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635 /* We do this three times for luck */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648 const struct intel_crtc_state *pipe_config)
1649 {
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
1673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674
1675 /* Check PLL is locked */
1676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
1679 /* not sure when this should be written */
1680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1681 POSTING_READ(DPLL_MD(pipe));
1682
1683 mutex_unlock(&dev_priv->dpio_lock);
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695 return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705 assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
1733 crtc->config->dpll_hw_state.dpll_md);
1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
1742
1743 /* We do this three times for luck */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 I915_WRITE(reg, dpll);
1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756 * i9xx_disable_pll - disable a PLL
1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
1803 if (pipe == PIPE_B)
1804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
1807
1808 }
1809
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811 {
1812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 u32 val;
1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
1818 /* Set PLL en = 0 */
1819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
1843 mutex_unlock(&dev_priv->dpio_lock);
1844 }
1845
1846 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1847 struct intel_digital_port *dport,
1848 unsigned int expected_mask)
1849 {
1850 u32 port_mask;
1851 int dpll_reg;
1852
1853 switch (dport->port) {
1854 case PORT_B:
1855 port_mask = DPLL_PORTB_READY_MASK;
1856 dpll_reg = DPLL(0);
1857 break;
1858 case PORT_C:
1859 port_mask = DPLL_PORTC_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 expected_mask <<= 4;
1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
1866 break;
1867 default:
1868 BUG();
1869 }
1870
1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1872 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1874 }
1875
1876 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877 {
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
1882 if (WARN_ON(pll == NULL))
1883 return;
1884
1885 WARN_ON(!pll->config.crtc_mask);
1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893 }
1894
1895 /**
1896 * intel_enable_shared_dpll - enable PCH PLL
1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
1903 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1904 {
1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1908
1909 if (WARN_ON(pll == NULL))
1910 return;
1911
1912 if (WARN_ON(pll->config.crtc_mask == 0))
1913 return;
1914
1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1916 pll->name, pll->active, pll->on,
1917 crtc->base.base.id);
1918
1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
1921 assert_shared_dpll_enabled(dev_priv, pll);
1922 return;
1923 }
1924 WARN_ON(pll->on);
1925
1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1929 pll->enable(dev_priv, pll);
1930 pll->on = true;
1931 }
1932
1933 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1934 {
1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1938
1939 /* PCH only available on ILK+ */
1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
1941 if (WARN_ON(pll == NULL))
1942 return;
1943
1944 if (WARN_ON(pll->config.crtc_mask == 0))
1945 return;
1946
1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
1949 crtc->base.base.id);
1950
1951 if (WARN_ON(pll->active == 0)) {
1952 assert_shared_dpll_disabled(dev_priv, pll);
1953 return;
1954 }
1955
1956 assert_shared_dpll_enabled(dev_priv, pll);
1957 WARN_ON(!pll->on);
1958 if (--pll->active)
1959 return;
1960
1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1962 pll->disable(dev_priv, pll);
1963 pll->on = false;
1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1966 }
1967
1968 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
1970 {
1971 struct drm_device *dev = dev_priv->dev;
1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1974 uint32_t reg, val, pipeconf_val;
1975
1976 /* PCH only available on ILK+ */
1977 BUG_ON(!HAS_PCH_SPLIT(dev));
1978
1979 /* Make sure PCH DPLL is enabled */
1980 assert_shared_dpll_enabled(dev_priv,
1981 intel_crtc_to_shared_dpll(intel_crtc));
1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
1994 }
1995
1996 reg = PCH_TRANSCONF(pipe);
1997 val = I915_READ(reg);
1998 pipeconf_val = I915_READ(PIPECONF(pipe));
1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
2007 }
2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2011 if (HAS_PCH_IBX(dev_priv->dev) &&
2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2022 }
2023
2024 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2025 enum transcoder cpu_transcoder)
2026 {
2027 u32 val, pipeconf_val;
2028
2029 /* PCH only available on ILK+ */
2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2031
2032 /* FDI must be feeding us bits for PCH ports */
2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2035
2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
2041 val = TRANS_ENABLE;
2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2043
2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
2046 val |= TRANS_INTERLACED;
2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2052 DRM_ERROR("Failed to enable PCH transcoder\n");
2053 }
2054
2055 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
2057 {
2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
2068 reg = PCH_TRANSCONF(pipe);
2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
2083 }
2084
2085 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2086 {
2087 u32 val;
2088
2089 val = I915_READ(LPT_TRANSCONF);
2090 val &= ~TRANS_ENABLE;
2091 I915_WRITE(LPT_TRANSCONF, val);
2092 /* wait for PCH transcoder off, transcoder state */
2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2094 DRM_ERROR("Failed to disable PCH transcoder\n");
2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2099 I915_WRITE(_TRANSA_CHICKEN2, val);
2100 }
2101
2102 /**
2103 * intel_enable_pipe - enable a pipe, asserting requirements
2104 * @crtc: crtc responsible for the pipe
2105 *
2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2108 */
2109 static void intel_enable_pipe(struct intel_crtc *crtc)
2110 {
2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
2116 enum pipe pch_transcoder;
2117 int reg;
2118 u32 val;
2119
2120 assert_planes_disabled(dev_priv, pipe);
2121 assert_cursor_disabled(dev_priv, pipe);
2122 assert_sprites_disabled(dev_priv, pipe);
2123
2124 if (HAS_PCH_LPT(dev_priv->dev))
2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
2134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
2139 else {
2140 if (crtc->config->has_pch_encoder) {
2141 /* if driving the PCH, we need FDI enabled */
2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
2148
2149 reg = PIPECONF(cpu_transcoder);
2150 val = I915_READ(reg);
2151 if (val & PIPECONF_ENABLE) {
2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154 return;
2155 }
2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
2158 POSTING_READ(reg);
2159 }
2160
2161 /**
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2164 *
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175 enum pipe pipe = crtc->pipe;
2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
2184 assert_cursor_disabled(dev_priv, pipe);
2185 assert_sprites_disabled(dev_priv, pipe);
2186
2187 reg = PIPECONF(cpu_transcoder);
2188 val = I915_READ(reg);
2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
2196 if (crtc->config->double_wide)
2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 /*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
2213 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
2215 {
2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
2221 }
2222
2223 /**
2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
2227 *
2228 * Enable @plane on @crtc, making sure that the pipe is running first.
2229 */
2230 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
2232 {
2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2239 to_intel_plane_state(plane->state)->visible = true;
2240
2241 dev_priv->display.update_primary_plane(crtc, plane->fb,
2242 crtc->x, crtc->y);
2243 }
2244
2245 static bool need_vtd_wa(struct drm_device *dev)
2246 {
2247 #ifdef CONFIG_INTEL_IOMMU
2248 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2249 return true;
2250 #endif
2251 return false;
2252 }
2253
2254 unsigned int
2255 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2256 uint64_t fb_format_modifier)
2257 {
2258 unsigned int tile_height;
2259 uint32_t pixel_bytes;
2260
2261 switch (fb_format_modifier) {
2262 case DRM_FORMAT_MOD_NONE:
2263 tile_height = 1;
2264 break;
2265 case I915_FORMAT_MOD_X_TILED:
2266 tile_height = IS_GEN2(dev) ? 16 : 8;
2267 break;
2268 case I915_FORMAT_MOD_Y_TILED:
2269 tile_height = 32;
2270 break;
2271 case I915_FORMAT_MOD_Yf_TILED:
2272 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2273 switch (pixel_bytes) {
2274 default:
2275 case 1:
2276 tile_height = 64;
2277 break;
2278 case 2:
2279 case 4:
2280 tile_height = 32;
2281 break;
2282 case 8:
2283 tile_height = 16;
2284 break;
2285 case 16:
2286 WARN_ONCE(1,
2287 "128-bit pixels are not supported for display!");
2288 tile_height = 16;
2289 break;
2290 }
2291 break;
2292 default:
2293 MISSING_CASE(fb_format_modifier);
2294 tile_height = 1;
2295 break;
2296 }
2297
2298 return tile_height;
2299 }
2300
2301 unsigned int
2302 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2303 uint32_t pixel_format, uint64_t fb_format_modifier)
2304 {
2305 return ALIGN(height, intel_tile_height(dev, pixel_format,
2306 fb_format_modifier));
2307 }
2308
2309 static int
2310 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2311 const struct drm_plane_state *plane_state)
2312 {
2313 struct intel_rotation_info *info = &view->rotation_info;
2314
2315 *view = i915_ggtt_view_normal;
2316
2317 if (!plane_state)
2318 return 0;
2319
2320 if (!intel_rotation_90_or_270(plane_state->rotation))
2321 return 0;
2322
2323 *view = i915_ggtt_view_rotated;
2324
2325 info->height = fb->height;
2326 info->pixel_format = fb->pixel_format;
2327 info->pitch = fb->pitches[0];
2328 info->fb_modifier = fb->modifier[0];
2329
2330 return 0;
2331 }
2332
2333 int
2334 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
2336 const struct drm_plane_state *plane_state,
2337 struct intel_engine_cs *pipelined)
2338 {
2339 struct drm_device *dev = fb->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2342 struct i915_ggtt_view view;
2343 u32 alignment;
2344 int ret;
2345
2346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
2348 switch (fb->modifier[0]) {
2349 case DRM_FORMAT_MOD_NONE:
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2353 alignment = 128 * 1024;
2354 else if (INTEL_INFO(dev)->gen >= 4)
2355 alignment = 4 * 1024;
2356 else
2357 alignment = 64 * 1024;
2358 break;
2359 case I915_FORMAT_MOD_X_TILED:
2360 if (INTEL_INFO(dev)->gen >= 9)
2361 alignment = 256 * 1024;
2362 else {
2363 /* pin() will align the object as required by fence */
2364 alignment = 0;
2365 }
2366 break;
2367 case I915_FORMAT_MOD_Y_TILED:
2368 case I915_FORMAT_MOD_Yf_TILED:
2369 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370 "Y tiling bo slipped through, driver bug!\n"))
2371 return -EINVAL;
2372 alignment = 1 * 1024 * 1024;
2373 break;
2374 default:
2375 MISSING_CASE(fb->modifier[0]);
2376 return -EINVAL;
2377 }
2378
2379 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380 if (ret)
2381 return ret;
2382
2383 /* Note that the w/a also requires 64 PTE of padding following the
2384 * bo. We currently fill all unused PTE with the shadow page and so
2385 * we should always have valid PTE following the scanout preventing
2386 * the VT-d warning.
2387 */
2388 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389 alignment = 256 * 1024;
2390
2391 /*
2392 * Global gtt pte registers are special registers which actually forward
2393 * writes to a chunk of system memory. Which means that there is no risk
2394 * that the register values disappear as soon as we call
2395 * intel_runtime_pm_put(), so it is correct to wrap only the
2396 * pin/unpin/fence and not more.
2397 */
2398 intel_runtime_pm_get(dev_priv);
2399
2400 dev_priv->mm.interruptible = false;
2401 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2402 &view);
2403 if (ret)
2404 goto err_interruptible;
2405
2406 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407 * fence, whereas 965+ only requires a fence if using
2408 * framebuffer compression. For simplicity, we always install
2409 * a fence as the cost is not that onerous.
2410 */
2411 ret = i915_gem_object_get_fence(obj);
2412 if (ret)
2413 goto err_unpin;
2414
2415 i915_gem_object_pin_fence(obj);
2416
2417 dev_priv->mm.interruptible = true;
2418 intel_runtime_pm_put(dev_priv);
2419 return 0;
2420
2421 err_unpin:
2422 i915_gem_object_unpin_from_display_plane(obj, &view);
2423 err_interruptible:
2424 dev_priv->mm.interruptible = true;
2425 intel_runtime_pm_put(dev_priv);
2426 return ret;
2427 }
2428
2429 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2430 const struct drm_plane_state *plane_state)
2431 {
2432 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2433 struct i915_ggtt_view view;
2434 int ret;
2435
2436 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2437
2438 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2439 WARN_ONCE(ret, "Couldn't get view from plane state!");
2440
2441 i915_gem_object_unpin_fence(obj);
2442 i915_gem_object_unpin_from_display_plane(obj, &view);
2443 }
2444
2445 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446 * is assumed to be a power-of-two. */
2447 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
2451 {
2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
2454
2455 tile_rows = *y / 8;
2456 *y %= 8;
2457
2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
2463 unsigned int offset;
2464
2465 offset = *y * pitch + *x * cpp;
2466 *y = 0;
2467 *x = (offset & 4095) / cpp;
2468 return offset & -4096;
2469 }
2470 }
2471
2472 static int i9xx_format_to_fourcc(int format)
2473 {
2474 switch (format) {
2475 case DISPPLANE_8BPP:
2476 return DRM_FORMAT_C8;
2477 case DISPPLANE_BGRX555:
2478 return DRM_FORMAT_XRGB1555;
2479 case DISPPLANE_BGRX565:
2480 return DRM_FORMAT_RGB565;
2481 default:
2482 case DISPPLANE_BGRX888:
2483 return DRM_FORMAT_XRGB8888;
2484 case DISPPLANE_RGBX888:
2485 return DRM_FORMAT_XBGR8888;
2486 case DISPPLANE_BGRX101010:
2487 return DRM_FORMAT_XRGB2101010;
2488 case DISPPLANE_RGBX101010:
2489 return DRM_FORMAT_XBGR2101010;
2490 }
2491 }
2492
2493 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2494 {
2495 switch (format) {
2496 case PLANE_CTL_FORMAT_RGB_565:
2497 return DRM_FORMAT_RGB565;
2498 default:
2499 case PLANE_CTL_FORMAT_XRGB_8888:
2500 if (rgb_order) {
2501 if (alpha)
2502 return DRM_FORMAT_ABGR8888;
2503 else
2504 return DRM_FORMAT_XBGR8888;
2505 } else {
2506 if (alpha)
2507 return DRM_FORMAT_ARGB8888;
2508 else
2509 return DRM_FORMAT_XRGB8888;
2510 }
2511 case PLANE_CTL_FORMAT_XRGB_2101010:
2512 if (rgb_order)
2513 return DRM_FORMAT_XBGR2101010;
2514 else
2515 return DRM_FORMAT_XRGB2101010;
2516 }
2517 }
2518
2519 static bool
2520 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2521 struct intel_initial_plane_config *plane_config)
2522 {
2523 struct drm_device *dev = crtc->base.dev;
2524 struct drm_i915_gem_object *obj = NULL;
2525 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526 struct drm_framebuffer *fb = &plane_config->fb->base;
2527 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529 PAGE_SIZE);
2530
2531 size_aligned -= base_aligned;
2532
2533 if (plane_config->size == 0)
2534 return false;
2535
2536 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537 base_aligned,
2538 base_aligned,
2539 size_aligned);
2540 if (!obj)
2541 return false;
2542
2543 obj->tiling_mode = plane_config->tiling;
2544 if (obj->tiling_mode == I915_TILING_X)
2545 obj->stride = fb->pitches[0];
2546
2547 mode_cmd.pixel_format = fb->pixel_format;
2548 mode_cmd.width = fb->width;
2549 mode_cmd.height = fb->height;
2550 mode_cmd.pitches[0] = fb->pitches[0];
2551 mode_cmd.modifier[0] = fb->modifier[0];
2552 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2553
2554 mutex_lock(&dev->struct_mutex);
2555 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2556 &mode_cmd, obj)) {
2557 DRM_DEBUG_KMS("intel fb init failed\n");
2558 goto out_unref_obj;
2559 }
2560 mutex_unlock(&dev->struct_mutex);
2561
2562 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2563 return true;
2564
2565 out_unref_obj:
2566 drm_gem_object_unreference(&obj->base);
2567 mutex_unlock(&dev->struct_mutex);
2568 return false;
2569 }
2570
2571 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2572 static void
2573 update_state_fb(struct drm_plane *plane)
2574 {
2575 if (plane->fb == plane->state->fb)
2576 return;
2577
2578 if (plane->state->fb)
2579 drm_framebuffer_unreference(plane->state->fb);
2580 plane->state->fb = plane->fb;
2581 if (plane->state->fb)
2582 drm_framebuffer_reference(plane->state->fb);
2583 }
2584
2585 static void
2586 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2587 struct intel_initial_plane_config *plane_config)
2588 {
2589 struct drm_device *dev = intel_crtc->base.dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct drm_crtc *c;
2592 struct intel_crtc *i;
2593 struct drm_i915_gem_object *obj;
2594 struct drm_plane *primary = intel_crtc->base.primary;
2595 struct drm_framebuffer *fb;
2596
2597 if (!plane_config->fb)
2598 return;
2599
2600 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2601 fb = &plane_config->fb->base;
2602 goto valid_fb;
2603 }
2604
2605 kfree(plane_config->fb);
2606
2607 /*
2608 * Failed to alloc the obj, check to see if we should share
2609 * an fb with another CRTC instead
2610 */
2611 for_each_crtc(dev, c) {
2612 i = to_intel_crtc(c);
2613
2614 if (c == &intel_crtc->base)
2615 continue;
2616
2617 if (!i->active)
2618 continue;
2619
2620 fb = c->primary->fb;
2621 if (!fb)
2622 continue;
2623
2624 obj = intel_fb_obj(fb);
2625 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2626 drm_framebuffer_reference(fb);
2627 goto valid_fb;
2628 }
2629 }
2630
2631 return;
2632
2633 valid_fb:
2634 obj = intel_fb_obj(fb);
2635 if (obj->tiling_mode != I915_TILING_NONE)
2636 dev_priv->preserve_bios_swizzle = true;
2637
2638 primary->fb = fb;
2639 primary->state->crtc = &intel_crtc->base;
2640 primary->crtc = &intel_crtc->base;
2641 update_state_fb(primary);
2642 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2643 }
2644
2645 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646 struct drm_framebuffer *fb,
2647 int x, int y)
2648 {
2649 struct drm_device *dev = crtc->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2652 struct drm_plane *primary = crtc->primary;
2653 bool visible = to_intel_plane_state(primary->state)->visible;
2654 struct drm_i915_gem_object *obj;
2655 int plane = intel_crtc->plane;
2656 unsigned long linear_offset;
2657 u32 dspcntr;
2658 u32 reg = DSPCNTR(plane);
2659 int pixel_size;
2660
2661 if (!visible || !fb) {
2662 I915_WRITE(reg, 0);
2663 if (INTEL_INFO(dev)->gen >= 4)
2664 I915_WRITE(DSPSURF(plane), 0);
2665 else
2666 I915_WRITE(DSPADDR(plane), 0);
2667 POSTING_READ(reg);
2668 return;
2669 }
2670
2671 obj = intel_fb_obj(fb);
2672 if (WARN_ON(obj == NULL))
2673 return;
2674
2675 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
2677 dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
2679 dspcntr |= DISPLAY_PLANE_ENABLE;
2680
2681 if (INTEL_INFO(dev)->gen < 4) {
2682 if (intel_crtc->pipe == PIPE_B)
2683 dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685 /* pipesrc and dspsize control the size that is scaled from,
2686 * which should always be the user's requested size.
2687 */
2688 I915_WRITE(DSPSIZE(plane),
2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
2691 I915_WRITE(DSPPOS(plane), 0);
2692 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693 I915_WRITE(PRIMSIZE(plane),
2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
2696 I915_WRITE(PRIMPOS(plane), 0);
2697 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2698 }
2699
2700 switch (fb->pixel_format) {
2701 case DRM_FORMAT_C8:
2702 dspcntr |= DISPPLANE_8BPP;
2703 break;
2704 case DRM_FORMAT_XRGB1555:
2705 case DRM_FORMAT_ARGB1555:
2706 dspcntr |= DISPPLANE_BGRX555;
2707 break;
2708 case DRM_FORMAT_RGB565:
2709 dspcntr |= DISPPLANE_BGRX565;
2710 break;
2711 case DRM_FORMAT_XRGB8888:
2712 case DRM_FORMAT_ARGB8888:
2713 dspcntr |= DISPPLANE_BGRX888;
2714 break;
2715 case DRM_FORMAT_XBGR8888:
2716 case DRM_FORMAT_ABGR8888:
2717 dspcntr |= DISPPLANE_RGBX888;
2718 break;
2719 case DRM_FORMAT_XRGB2101010:
2720 case DRM_FORMAT_ARGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 case DRM_FORMAT_ABGR2101010:
2725 dspcntr |= DISPPLANE_RGBX101010;
2726 break;
2727 default:
2728 BUG();
2729 }
2730
2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
2734
2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
2739
2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
2742 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2743 pixel_size,
2744 fb->pitches[0]);
2745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
2747 intel_crtc->dspaddr_offset = linear_offset;
2748 }
2749
2750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2751 dspcntr |= DISPPLANE_ROTATE_180;
2752
2753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
2755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
2759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
2765 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2766 if (INTEL_INFO(dev)->gen >= 4) {
2767 I915_WRITE(DSPSURF(plane),
2768 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2769 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2770 I915_WRITE(DSPLINOFF(plane), linear_offset);
2771 } else
2772 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2773 POSTING_READ(reg);
2774 }
2775
2776 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2777 struct drm_framebuffer *fb,
2778 int x, int y)
2779 {
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783 struct drm_plane *primary = crtc->primary;
2784 bool visible = to_intel_plane_state(primary->state)->visible;
2785 struct drm_i915_gem_object *obj;
2786 int plane = intel_crtc->plane;
2787 unsigned long linear_offset;
2788 u32 dspcntr;
2789 u32 reg = DSPCNTR(plane);
2790 int pixel_size;
2791
2792 if (!visible || !fb) {
2793 I915_WRITE(reg, 0);
2794 I915_WRITE(DSPSURF(plane), 0);
2795 POSTING_READ(reg);
2796 return;
2797 }
2798
2799 obj = intel_fb_obj(fb);
2800 if (WARN_ON(obj == NULL))
2801 return;
2802
2803 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2804
2805 dspcntr = DISPPLANE_GAMMA_ENABLE;
2806
2807 dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812 switch (fb->pixel_format) {
2813 case DRM_FORMAT_C8:
2814 dspcntr |= DISPPLANE_8BPP;
2815 break;
2816 case DRM_FORMAT_RGB565:
2817 dspcntr |= DISPPLANE_BGRX565;
2818 break;
2819 case DRM_FORMAT_XRGB8888:
2820 case DRM_FORMAT_ARGB8888:
2821 dspcntr |= DISPPLANE_BGRX888;
2822 break;
2823 case DRM_FORMAT_XBGR8888:
2824 case DRM_FORMAT_ABGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 case DRM_FORMAT_ARGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 case DRM_FORMAT_ABGR2101010:
2833 dspcntr |= DISPPLANE_RGBX101010;
2834 break;
2835 default:
2836 BUG();
2837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
2841
2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2844
2845 linear_offset = y * fb->pitches[0] + x * pixel_size;
2846 intel_crtc->dspaddr_offset =
2847 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2848 pixel_size,
2849 fb->pitches[0]);
2850 linear_offset -= intel_crtc->dspaddr_offset;
2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
2867
2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
2877 POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882 {
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912 }
2913
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916 {
2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920 view = &i915_ggtt_view_rotated;
2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923 }
2924
2925 /*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929 {
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952 }
2953
2954 u32 skl_plane_ctl_format(uint32_t pixel_format)
2955 {
2956 u32 format = 0;
2957
2958 switch (pixel_format) {
2959 case DRM_FORMAT_C8:
2960 format = PLANE_CTL_FORMAT_INDEXED;
2961 break;
2962 case DRM_FORMAT_RGB565:
2963 format = PLANE_CTL_FORMAT_RGB_565;
2964 break;
2965 case DRM_FORMAT_XBGR8888:
2966 format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2967 break;
2968 case DRM_FORMAT_XRGB8888:
2969 format = PLANE_CTL_FORMAT_XRGB_8888;
2970 break;
2971 /*
2972 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2973 * to be already pre-multiplied. We need to add a knob (or a different
2974 * DRM_FORMAT) for user-space to configure that.
2975 */
2976 case DRM_FORMAT_ABGR8888:
2977 format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979 break;
2980 case DRM_FORMAT_ARGB8888:
2981 format = PLANE_CTL_FORMAT_XRGB_8888 |
2982 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2983 break;
2984 case DRM_FORMAT_XRGB2101010:
2985 format = PLANE_CTL_FORMAT_XRGB_2101010;
2986 break;
2987 case DRM_FORMAT_XBGR2101010:
2988 format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2989 break;
2990 case DRM_FORMAT_YUYV:
2991 format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2992 break;
2993 case DRM_FORMAT_YVYU:
2994 format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2995 break;
2996 case DRM_FORMAT_UYVY:
2997 format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2998 break;
2999 case DRM_FORMAT_VYUY:
3000 format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3001 break;
3002 default:
3003 MISSING_CASE(pixel_format);
3004 }
3005
3006 return format;
3007 }
3008
3009 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3010 {
3011 u32 plane_ctl_tiling = 0;
3012
3013 switch (fb_modifier) {
3014 case DRM_FORMAT_MOD_NONE:
3015 break;
3016 case I915_FORMAT_MOD_X_TILED:
3017 plane_ctl_tiling = PLANE_CTL_TILED_X;
3018 break;
3019 case I915_FORMAT_MOD_Y_TILED:
3020 plane_ctl_tiling = PLANE_CTL_TILED_Y;
3021 break;
3022 case I915_FORMAT_MOD_Yf_TILED:
3023 plane_ctl_tiling = PLANE_CTL_TILED_YF;
3024 break;
3025 default:
3026 MISSING_CASE(fb_modifier);
3027 }
3028
3029 return plane_ctl_tiling;
3030 }
3031
3032 u32 skl_plane_ctl_rotation(unsigned int rotation)
3033 {
3034 u32 plane_ctl_rotation = 0;
3035
3036 switch (rotation) {
3037 case BIT(DRM_ROTATE_0):
3038 break;
3039 case BIT(DRM_ROTATE_90):
3040 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3041 break;
3042 case BIT(DRM_ROTATE_180):
3043 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3044 break;
3045 case BIT(DRM_ROTATE_270):
3046 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3047 break;
3048 default:
3049 MISSING_CASE(rotation);
3050 }
3051
3052 return plane_ctl_rotation;
3053 }
3054
3055 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3056 struct drm_framebuffer *fb,
3057 int x, int y)
3058 {
3059 struct drm_device *dev = crtc->dev;
3060 struct drm_i915_private *dev_priv = dev->dev_private;
3061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3062 struct drm_plane *plane = crtc->primary;
3063 bool visible = to_intel_plane_state(plane->state)->visible;
3064 struct drm_i915_gem_object *obj;
3065 int pipe = intel_crtc->pipe;
3066 u32 plane_ctl, stride_div, stride;
3067 u32 tile_height, plane_offset, plane_size;
3068 unsigned int rotation;
3069 int x_offset, y_offset;
3070 unsigned long surf_addr;
3071 struct intel_crtc_state *crtc_state = intel_crtc->config;
3072 struct intel_plane_state *plane_state;
3073 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3074 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3075 int scaler_id = -1;
3076
3077 plane_state = to_intel_plane_state(plane->state);
3078
3079 if (!visible || !fb) {
3080 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3081 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3082 POSTING_READ(PLANE_CTL(pipe, 0));
3083 return;
3084 }
3085
3086 plane_ctl = PLANE_CTL_ENABLE |
3087 PLANE_CTL_PIPE_GAMMA_ENABLE |
3088 PLANE_CTL_PIPE_CSC_ENABLE;
3089
3090 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3091 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3092 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3093
3094 rotation = plane->state->rotation;
3095 plane_ctl |= skl_plane_ctl_rotation(rotation);
3096
3097 obj = intel_fb_obj(fb);
3098 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3099 fb->pixel_format);
3100 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3101
3102 /*
3103 * FIXME: intel_plane_state->src, dst aren't set when transitional
3104 * update_plane helpers are called from legacy paths.
3105 * Once full atomic crtc is available, below check can be avoided.
3106 */
3107 if (drm_rect_width(&plane_state->src)) {
3108 scaler_id = plane_state->scaler_id;
3109 src_x = plane_state->src.x1 >> 16;
3110 src_y = plane_state->src.y1 >> 16;
3111 src_w = drm_rect_width(&plane_state->src) >> 16;
3112 src_h = drm_rect_height(&plane_state->src) >> 16;
3113 dst_x = plane_state->dst.x1;
3114 dst_y = plane_state->dst.y1;
3115 dst_w = drm_rect_width(&plane_state->dst);
3116 dst_h = drm_rect_height(&plane_state->dst);
3117
3118 WARN_ON(x != src_x || y != src_y);
3119 } else {
3120 src_w = intel_crtc->config->pipe_src_w;
3121 src_h = intel_crtc->config->pipe_src_h;
3122 }
3123
3124 if (intel_rotation_90_or_270(rotation)) {
3125 /* stride = Surface height in tiles */
3126 tile_height = intel_tile_height(dev, fb->pixel_format,
3127 fb->modifier[0]);
3128 stride = DIV_ROUND_UP(fb->height, tile_height);
3129 x_offset = stride * tile_height - y - src_h;
3130 y_offset = x;
3131 plane_size = (src_w - 1) << 16 | (src_h - 1);
3132 } else {
3133 stride = fb->pitches[0] / stride_div;
3134 x_offset = x;
3135 y_offset = y;
3136 plane_size = (src_h - 1) << 16 | (src_w - 1);
3137 }
3138 plane_offset = y_offset << 16 | x_offset;
3139
3140 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3141 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3142 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3143 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3144
3145 if (scaler_id >= 0) {
3146 uint32_t ps_ctrl = 0;
3147
3148 WARN_ON(!dst_w || !dst_h);
3149 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3150 crtc_state->scaler_state.scalers[scaler_id].mode;
3151 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3152 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3153 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3154 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3155 I915_WRITE(PLANE_POS(pipe, 0), 0);
3156 } else {
3157 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3158 }
3159
3160 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3161
3162 POSTING_READ(PLANE_SURF(pipe, 0));
3163 }
3164
3165 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3166 static int
3167 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3168 int x, int y, enum mode_set_atomic state)
3169 {
3170 struct drm_device *dev = crtc->dev;
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172
3173 if (dev_priv->display.disable_fbc)
3174 dev_priv->display.disable_fbc(dev);
3175
3176 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3177
3178 return 0;
3179 }
3180
3181 static void intel_complete_page_flips(struct drm_device *dev)
3182 {
3183 struct drm_crtc *crtc;
3184
3185 for_each_crtc(dev, crtc) {
3186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187 enum plane plane = intel_crtc->plane;
3188
3189 intel_prepare_page_flip(dev, plane);
3190 intel_finish_page_flip_plane(dev, plane);
3191 }
3192 }
3193
3194 static void intel_update_primary_planes(struct drm_device *dev)
3195 {
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 struct drm_crtc *crtc;
3198
3199 for_each_crtc(dev, crtc) {
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201
3202 drm_modeset_lock(&crtc->mutex, NULL);
3203 /*
3204 * FIXME: Once we have proper support for primary planes (and
3205 * disabling them without disabling the entire crtc) allow again
3206 * a NULL crtc->primary->fb.
3207 */
3208 if (intel_crtc->active && crtc->primary->fb)
3209 dev_priv->display.update_primary_plane(crtc,
3210 crtc->primary->fb,
3211 crtc->x,
3212 crtc->y);
3213 drm_modeset_unlock(&crtc->mutex);
3214 }
3215 }
3216
3217 void intel_crtc_reset(struct intel_crtc *crtc)
3218 {
3219 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3220
3221 if (!crtc->active)
3222 return;
3223
3224 intel_crtc_disable_planes(&crtc->base);
3225 dev_priv->display.crtc_disable(&crtc->base);
3226 dev_priv->display.crtc_enable(&crtc->base);
3227 intel_crtc_enable_planes(&crtc->base);
3228 }
3229
3230 void intel_prepare_reset(struct drm_device *dev)
3231 {
3232 struct drm_i915_private *dev_priv = to_i915(dev);
3233 struct intel_crtc *crtc;
3234
3235 /* no reset support for gen2 */
3236 if (IS_GEN2(dev))
3237 return;
3238
3239 /* reset doesn't touch the display */
3240 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3241 return;
3242
3243 drm_modeset_lock_all(dev);
3244
3245 /*
3246 * Disabling the crtcs gracefully seems nicer. Also the
3247 * g33 docs say we should at least disable all the planes.
3248 */
3249 for_each_intel_crtc(dev, crtc) {
3250 if (!crtc->active)
3251 continue;
3252
3253 intel_crtc_disable_planes(&crtc->base);
3254 dev_priv->display.crtc_disable(&crtc->base);
3255 }
3256 }
3257
3258 void intel_finish_reset(struct drm_device *dev)
3259 {
3260 struct drm_i915_private *dev_priv = to_i915(dev);
3261
3262 /*
3263 * Flips in the rings will be nuked by the reset,
3264 * so complete all pending flips so that user space
3265 * will get its events and not get stuck.
3266 */
3267 intel_complete_page_flips(dev);
3268
3269 /* no reset support for gen2 */
3270 if (IS_GEN2(dev))
3271 return;
3272
3273 /* reset doesn't touch the display */
3274 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3275 /*
3276 * Flips in the rings have been nuked by the reset,
3277 * so update the base address of all primary
3278 * planes to the the last fb to make sure we're
3279 * showing the correct fb after a reset.
3280 */
3281 intel_update_primary_planes(dev);
3282 return;
3283 }
3284
3285 /*
3286 * The display has been reset as well,
3287 * so need a full re-initialization.
3288 */
3289 intel_runtime_pm_disable_interrupts(dev_priv);
3290 intel_runtime_pm_enable_interrupts(dev_priv);
3291
3292 intel_modeset_init_hw(dev);
3293
3294 spin_lock_irq(&dev_priv->irq_lock);
3295 if (dev_priv->display.hpd_irq_setup)
3296 dev_priv->display.hpd_irq_setup(dev);
3297 spin_unlock_irq(&dev_priv->irq_lock);
3298
3299 intel_modeset_setup_hw_state(dev, true);
3300
3301 intel_hpd_init(dev_priv);
3302
3303 drm_modeset_unlock_all(dev);
3304 }
3305
3306 static void
3307 intel_finish_fb(struct drm_framebuffer *old_fb)
3308 {
3309 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3310 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3311 bool was_interruptible = dev_priv->mm.interruptible;
3312 int ret;
3313
3314 /* Big Hammer, we also need to ensure that any pending
3315 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3316 * current scanout is retired before unpinning the old
3317 * framebuffer. Note that we rely on userspace rendering
3318 * into the buffer attached to the pipe they are waiting
3319 * on. If not, userspace generates a GPU hang with IPEHR
3320 * point to the MI_WAIT_FOR_EVENT.
3321 *
3322 * This should only fail upon a hung GPU, in which case we
3323 * can safely continue.
3324 */
3325 dev_priv->mm.interruptible = false;
3326 ret = i915_gem_object_wait_rendering(obj, true);
3327 dev_priv->mm.interruptible = was_interruptible;
3328
3329 WARN_ON(ret);
3330 }
3331
3332 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3333 {
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 bool pending;
3338
3339 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3340 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3341 return false;
3342
3343 spin_lock_irq(&dev->event_lock);
3344 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3345 spin_unlock_irq(&dev->event_lock);
3346
3347 return pending;
3348 }
3349
3350 static void intel_update_pipe_size(struct intel_crtc *crtc)
3351 {
3352 struct drm_device *dev = crtc->base.dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 const struct drm_display_mode *adjusted_mode;
3355
3356 if (!i915.fastboot)
3357 return;
3358
3359 /*
3360 * Update pipe size and adjust fitter if needed: the reason for this is
3361 * that in compute_mode_changes we check the native mode (not the pfit
3362 * mode) to see if we can flip rather than do a full mode set. In the
3363 * fastboot case, we'll flip, but if we don't update the pipesrc and
3364 * pfit state, we'll end up with a big fb scanned out into the wrong
3365 * sized surface.
3366 *
3367 * To fix this properly, we need to hoist the checks up into
3368 * compute_mode_changes (or above), check the actual pfit state and
3369 * whether the platform allows pfit disable with pipe active, and only
3370 * then update the pipesrc and pfit state, even on the flip path.
3371 */
3372
3373 adjusted_mode = &crtc->config->base.adjusted_mode;
3374
3375 I915_WRITE(PIPESRC(crtc->pipe),
3376 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3377 (adjusted_mode->crtc_vdisplay - 1));
3378 if (!crtc->config->pch_pfit.enabled &&
3379 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3381 I915_WRITE(PF_CTL(crtc->pipe), 0);
3382 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3383 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3384 }
3385 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3386 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3387 }
3388
3389 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3390 {
3391 struct drm_device *dev = crtc->dev;
3392 struct drm_i915_private *dev_priv = dev->dev_private;
3393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3394 int pipe = intel_crtc->pipe;
3395 u32 reg, temp;
3396
3397 /* enable normal train */
3398 reg = FDI_TX_CTL(pipe);
3399 temp = I915_READ(reg);
3400 if (IS_IVYBRIDGE(dev)) {
3401 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3402 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3403 } else {
3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3406 }
3407 I915_WRITE(reg, temp);
3408
3409 reg = FDI_RX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 if (HAS_PCH_CPT(dev)) {
3412 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3413 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3414 } else {
3415 temp &= ~FDI_LINK_TRAIN_NONE;
3416 temp |= FDI_LINK_TRAIN_NONE;
3417 }
3418 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3419
3420 /* wait one idle pattern time */
3421 POSTING_READ(reg);
3422 udelay(1000);
3423
3424 /* IVB wants error correction enabled */
3425 if (IS_IVYBRIDGE(dev))
3426 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3427 FDI_FE_ERRC_ENABLE);
3428 }
3429
3430 /* The FDI link training functions for ILK/Ibexpeak. */
3431 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3432 {
3433 struct drm_device *dev = crtc->dev;
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436 int pipe = intel_crtc->pipe;
3437 u32 reg, temp, tries;
3438
3439 /* FDI needs bits from pipe first */
3440 assert_pipe_enabled(dev_priv, pipe);
3441
3442 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3443 for train result */
3444 reg = FDI_RX_IMR(pipe);
3445 temp = I915_READ(reg);
3446 temp &= ~FDI_RX_SYMBOL_LOCK;
3447 temp &= ~FDI_RX_BIT_LOCK;
3448 I915_WRITE(reg, temp);
3449 I915_READ(reg);
3450 udelay(150);
3451
3452 /* enable CPU FDI TX and PCH FDI RX */
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3456 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_1;
3459 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3460
3461 reg = FDI_RX_CTL(pipe);
3462 temp = I915_READ(reg);
3463 temp &= ~FDI_LINK_TRAIN_NONE;
3464 temp |= FDI_LINK_TRAIN_PATTERN_1;
3465 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3466
3467 POSTING_READ(reg);
3468 udelay(150);
3469
3470 /* Ironlake workaround, enable clock pointer after FDI enable*/
3471 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3472 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3473 FDI_RX_PHASE_SYNC_POINTER_EN);
3474
3475 reg = FDI_RX_IIR(pipe);
3476 for (tries = 0; tries < 5; tries++) {
3477 temp = I915_READ(reg);
3478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3479
3480 if ((temp & FDI_RX_BIT_LOCK)) {
3481 DRM_DEBUG_KMS("FDI train 1 done.\n");
3482 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3483 break;
3484 }
3485 }
3486 if (tries == 5)
3487 DRM_ERROR("FDI train 1 fail!\n");
3488
3489 /* Train 2 */
3490 reg = FDI_TX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 temp &= ~FDI_LINK_TRAIN_NONE;
3493 temp |= FDI_LINK_TRAIN_PATTERN_2;
3494 I915_WRITE(reg, temp);
3495
3496 reg = FDI_RX_CTL(pipe);
3497 temp = I915_READ(reg);
3498 temp &= ~FDI_LINK_TRAIN_NONE;
3499 temp |= FDI_LINK_TRAIN_PATTERN_2;
3500 I915_WRITE(reg, temp);
3501
3502 POSTING_READ(reg);
3503 udelay(150);
3504
3505 reg = FDI_RX_IIR(pipe);
3506 for (tries = 0; tries < 5; tries++) {
3507 temp = I915_READ(reg);
3508 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3509
3510 if (temp & FDI_RX_SYMBOL_LOCK) {
3511 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3512 DRM_DEBUG_KMS("FDI train 2 done.\n");
3513 break;
3514 }
3515 }
3516 if (tries == 5)
3517 DRM_ERROR("FDI train 2 fail!\n");
3518
3519 DRM_DEBUG_KMS("FDI train done\n");
3520
3521 }
3522
3523 static const int snb_b_fdi_train_param[] = {
3524 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3525 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3526 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3527 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3528 };
3529
3530 /* The FDI link training functions for SNB/Cougarpoint. */
3531 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3532 {
3533 struct drm_device *dev = crtc->dev;
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3536 int pipe = intel_crtc->pipe;
3537 u32 reg, temp, i, retry;
3538
3539 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3540 for train result */
3541 reg = FDI_RX_IMR(pipe);
3542 temp = I915_READ(reg);
3543 temp &= ~FDI_RX_SYMBOL_LOCK;
3544 temp &= ~FDI_RX_BIT_LOCK;
3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
3548 udelay(150);
3549
3550 /* enable CPU FDI TX and PCH FDI RX */
3551 reg = FDI_TX_CTL(pipe);
3552 temp = I915_READ(reg);
3553 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3554 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3555 temp &= ~FDI_LINK_TRAIN_NONE;
3556 temp |= FDI_LINK_TRAIN_PATTERN_1;
3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 /* SNB-B */
3559 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3560 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3561
3562 I915_WRITE(FDI_RX_MISC(pipe),
3563 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3564
3565 reg = FDI_RX_CTL(pipe);
3566 temp = I915_READ(reg);
3567 if (HAS_PCH_CPT(dev)) {
3568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3570 } else {
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_1;
3573 }
3574 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3575
3576 POSTING_READ(reg);
3577 udelay(150);
3578
3579 for (i = 0; i < 4; i++) {
3580 reg = FDI_TX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583 temp |= snb_b_fdi_train_param[i];
3584 I915_WRITE(reg, temp);
3585
3586 POSTING_READ(reg);
3587 udelay(500);
3588
3589 for (retry = 0; retry < 5; retry++) {
3590 reg = FDI_RX_IIR(pipe);
3591 temp = I915_READ(reg);
3592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593 if (temp & FDI_RX_BIT_LOCK) {
3594 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3595 DRM_DEBUG_KMS("FDI train 1 done.\n");
3596 break;
3597 }
3598 udelay(50);
3599 }
3600 if (retry < 5)
3601 break;
3602 }
3603 if (i == 4)
3604 DRM_ERROR("FDI train 1 fail!\n");
3605
3606 /* Train 2 */
3607 reg = FDI_TX_CTL(pipe);
3608 temp = I915_READ(reg);
3609 temp &= ~FDI_LINK_TRAIN_NONE;
3610 temp |= FDI_LINK_TRAIN_PATTERN_2;
3611 if (IS_GEN6(dev)) {
3612 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3613 /* SNB-B */
3614 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3615 }
3616 I915_WRITE(reg, temp);
3617
3618 reg = FDI_RX_CTL(pipe);
3619 temp = I915_READ(reg);
3620 if (HAS_PCH_CPT(dev)) {
3621 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3622 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3623 } else {
3624 temp &= ~FDI_LINK_TRAIN_NONE;
3625 temp |= FDI_LINK_TRAIN_PATTERN_2;
3626 }
3627 I915_WRITE(reg, temp);
3628
3629 POSTING_READ(reg);
3630 udelay(150);
3631
3632 for (i = 0; i < 4; i++) {
3633 reg = FDI_TX_CTL(pipe);
3634 temp = I915_READ(reg);
3635 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3636 temp |= snb_b_fdi_train_param[i];
3637 I915_WRITE(reg, temp);
3638
3639 POSTING_READ(reg);
3640 udelay(500);
3641
3642 for (retry = 0; retry < 5; retry++) {
3643 reg = FDI_RX_IIR(pipe);
3644 temp = I915_READ(reg);
3645 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3646 if (temp & FDI_RX_SYMBOL_LOCK) {
3647 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3648 DRM_DEBUG_KMS("FDI train 2 done.\n");
3649 break;
3650 }
3651 udelay(50);
3652 }
3653 if (retry < 5)
3654 break;
3655 }
3656 if (i == 4)
3657 DRM_ERROR("FDI train 2 fail!\n");
3658
3659 DRM_DEBUG_KMS("FDI train done.\n");
3660 }
3661
3662 /* Manual link training for Ivy Bridge A0 parts */
3663 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3664 {
3665 struct drm_device *dev = crtc->dev;
3666 struct drm_i915_private *dev_priv = dev->dev_private;
3667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3668 int pipe = intel_crtc->pipe;
3669 u32 reg, temp, i, j;
3670
3671 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3672 for train result */
3673 reg = FDI_RX_IMR(pipe);
3674 temp = I915_READ(reg);
3675 temp &= ~FDI_RX_SYMBOL_LOCK;
3676 temp &= ~FDI_RX_BIT_LOCK;
3677 I915_WRITE(reg, temp);
3678
3679 POSTING_READ(reg);
3680 udelay(150);
3681
3682 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3683 I915_READ(FDI_RX_IIR(pipe)));
3684
3685 /* Try each vswing and preemphasis setting twice before moving on */
3686 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3687 /* disable first in case we need to retry */
3688 reg = FDI_TX_CTL(pipe);
3689 temp = I915_READ(reg);
3690 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3691 temp &= ~FDI_TX_ENABLE;
3692 I915_WRITE(reg, temp);
3693
3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_LINK_TRAIN_AUTO;
3697 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3698 temp &= ~FDI_RX_ENABLE;
3699 I915_WRITE(reg, temp);
3700
3701 /* enable CPU FDI TX and PCH FDI RX */
3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3705 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3706 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3708 temp |= snb_b_fdi_train_param[j/2];
3709 temp |= FDI_COMPOSITE_SYNC;
3710 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3711
3712 I915_WRITE(FDI_RX_MISC(pipe),
3713 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3714
3715 reg = FDI_RX_CTL(pipe);
3716 temp = I915_READ(reg);
3717 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3718 temp |= FDI_COMPOSITE_SYNC;
3719 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3720
3721 POSTING_READ(reg);
3722 udelay(1); /* should be 0.5us */
3723
3724 for (i = 0; i < 4; i++) {
3725 reg = FDI_RX_IIR(pipe);
3726 temp = I915_READ(reg);
3727 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3728
3729 if (temp & FDI_RX_BIT_LOCK ||
3730 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3731 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3732 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3733 i);
3734 break;
3735 }
3736 udelay(1); /* should be 0.5us */
3737 }
3738 if (i == 4) {
3739 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3740 continue;
3741 }
3742
3743 /* Train 2 */
3744 reg = FDI_TX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3747 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3748 I915_WRITE(reg, temp);
3749
3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3753 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3754 I915_WRITE(reg, temp);
3755
3756 POSTING_READ(reg);
3757 udelay(2); /* should be 1.5us */
3758
3759 for (i = 0; i < 4; i++) {
3760 reg = FDI_RX_IIR(pipe);
3761 temp = I915_READ(reg);
3762 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3763
3764 if (temp & FDI_RX_SYMBOL_LOCK ||
3765 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3766 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3767 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3768 i);
3769 goto train_done;
3770 }
3771 udelay(2); /* should be 1.5us */
3772 }
3773 if (i == 4)
3774 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3775 }
3776
3777 train_done:
3778 DRM_DEBUG_KMS("FDI train done.\n");
3779 }
3780
3781 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3782 {
3783 struct drm_device *dev = intel_crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 int pipe = intel_crtc->pipe;
3786 u32 reg, temp;
3787
3788
3789 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3790 reg = FDI_RX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3793 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3794 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3795 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3796
3797 POSTING_READ(reg);
3798 udelay(200);
3799
3800 /* Switch from Rawclk to PCDclk */
3801 temp = I915_READ(reg);
3802 I915_WRITE(reg, temp | FDI_PCDCLK);
3803
3804 POSTING_READ(reg);
3805 udelay(200);
3806
3807 /* Enable CPU FDI TX PLL, always on for Ironlake */
3808 reg = FDI_TX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3811 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3812
3813 POSTING_READ(reg);
3814 udelay(100);
3815 }
3816 }
3817
3818 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3819 {
3820 struct drm_device *dev = intel_crtc->base.dev;
3821 struct drm_i915_private *dev_priv = dev->dev_private;
3822 int pipe = intel_crtc->pipe;
3823 u32 reg, temp;
3824
3825 /* Switch from PCDclk to Rawclk */
3826 reg = FDI_RX_CTL(pipe);
3827 temp = I915_READ(reg);
3828 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3829
3830 /* Disable CPU FDI TX PLL */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3834
3835 POSTING_READ(reg);
3836 udelay(100);
3837
3838 reg = FDI_RX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3841
3842 /* Wait for the clocks to turn off. */
3843 POSTING_READ(reg);
3844 udelay(100);
3845 }
3846
3847 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3848 {
3849 struct drm_device *dev = crtc->dev;
3850 struct drm_i915_private *dev_priv = dev->dev_private;
3851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3852 int pipe = intel_crtc->pipe;
3853 u32 reg, temp;
3854
3855 /* disable CPU FDI tx and PCH FDI rx */
3856 reg = FDI_TX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3859 POSTING_READ(reg);
3860
3861 reg = FDI_RX_CTL(pipe);
3862 temp = I915_READ(reg);
3863 temp &= ~(0x7 << 16);
3864 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3865 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3866
3867 POSTING_READ(reg);
3868 udelay(100);
3869
3870 /* Ironlake workaround, disable clock pointer after downing FDI */
3871 if (HAS_PCH_IBX(dev))
3872 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3873
3874 /* still set train pattern 1 */
3875 reg = FDI_TX_CTL(pipe);
3876 temp = I915_READ(reg);
3877 temp &= ~FDI_LINK_TRAIN_NONE;
3878 temp |= FDI_LINK_TRAIN_PATTERN_1;
3879 I915_WRITE(reg, temp);
3880
3881 reg = FDI_RX_CTL(pipe);
3882 temp = I915_READ(reg);
3883 if (HAS_PCH_CPT(dev)) {
3884 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3885 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3886 } else {
3887 temp &= ~FDI_LINK_TRAIN_NONE;
3888 temp |= FDI_LINK_TRAIN_PATTERN_1;
3889 }
3890 /* BPC in FDI rx is consistent with that in PIPECONF */
3891 temp &= ~(0x07 << 16);
3892 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3893 I915_WRITE(reg, temp);
3894
3895 POSTING_READ(reg);
3896 udelay(100);
3897 }
3898
3899 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3900 {
3901 struct intel_crtc *crtc;
3902
3903 /* Note that we don't need to be called with mode_config.lock here
3904 * as our list of CRTC objects is static for the lifetime of the
3905 * device and so cannot disappear as we iterate. Similarly, we can
3906 * happily treat the predicates as racy, atomic checks as userspace
3907 * cannot claim and pin a new fb without at least acquring the
3908 * struct_mutex and so serialising with us.
3909 */
3910 for_each_intel_crtc(dev, crtc) {
3911 if (atomic_read(&crtc->unpin_work_count) == 0)
3912 continue;
3913
3914 if (crtc->unpin_work)
3915 intel_wait_for_vblank(dev, crtc->pipe);
3916
3917 return true;
3918 }
3919
3920 return false;
3921 }
3922
3923 static void page_flip_completed(struct intel_crtc *intel_crtc)
3924 {
3925 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3926 struct intel_unpin_work *work = intel_crtc->unpin_work;
3927
3928 /* ensure that the unpin work is consistent wrt ->pending. */
3929 smp_rmb();
3930 intel_crtc->unpin_work = NULL;
3931
3932 if (work->event)
3933 drm_send_vblank_event(intel_crtc->base.dev,
3934 intel_crtc->pipe,
3935 work->event);
3936
3937 drm_crtc_vblank_put(&intel_crtc->base);
3938
3939 wake_up_all(&dev_priv->pending_flip_queue);
3940 queue_work(dev_priv->wq, &work->work);
3941
3942 trace_i915_flip_complete(intel_crtc->plane,
3943 work->pending_flip_obj);
3944 }
3945
3946 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3947 {
3948 struct drm_device *dev = crtc->dev;
3949 struct drm_i915_private *dev_priv = dev->dev_private;
3950
3951 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3952 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3953 !intel_crtc_has_pending_flip(crtc),
3954 60*HZ) == 0)) {
3955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3956
3957 spin_lock_irq(&dev->event_lock);
3958 if (intel_crtc->unpin_work) {
3959 WARN_ONCE(1, "Removing stuck page flip\n");
3960 page_flip_completed(intel_crtc);
3961 }
3962 spin_unlock_irq(&dev->event_lock);
3963 }
3964
3965 if (crtc->primary->fb) {
3966 mutex_lock(&dev->struct_mutex);
3967 intel_finish_fb(crtc->primary->fb);
3968 mutex_unlock(&dev->struct_mutex);
3969 }
3970 }
3971
3972 /* Program iCLKIP clock to the desired frequency */
3973 static void lpt_program_iclkip(struct drm_crtc *crtc)
3974 {
3975 struct drm_device *dev = crtc->dev;
3976 struct drm_i915_private *dev_priv = dev->dev_private;
3977 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3978 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3979 u32 temp;
3980
3981 mutex_lock(&dev_priv->dpio_lock);
3982
3983 /* It is necessary to ungate the pixclk gate prior to programming
3984 * the divisors, and gate it back when it is done.
3985 */
3986 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3987
3988 /* Disable SSCCTL */
3989 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3990 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3991 SBI_SSCCTL_DISABLE,
3992 SBI_ICLK);
3993
3994 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3995 if (clock == 20000) {
3996 auxdiv = 1;
3997 divsel = 0x41;
3998 phaseinc = 0x20;
3999 } else {
4000 /* The iCLK virtual clock root frequency is in MHz,
4001 * but the adjusted_mode->crtc_clock in in KHz. To get the
4002 * divisors, it is necessary to divide one by another, so we
4003 * convert the virtual clock precision to KHz here for higher
4004 * precision.
4005 */
4006 u32 iclk_virtual_root_freq = 172800 * 1000;
4007 u32 iclk_pi_range = 64;
4008 u32 desired_divisor, msb_divisor_value, pi_value;
4009
4010 desired_divisor = (iclk_virtual_root_freq / clock);
4011 msb_divisor_value = desired_divisor / iclk_pi_range;
4012 pi_value = desired_divisor % iclk_pi_range;
4013
4014 auxdiv = 0;
4015 divsel = msb_divisor_value - 2;
4016 phaseinc = pi_value;
4017 }
4018
4019 /* This should not happen with any sane values */
4020 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4021 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4022 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4023 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4024
4025 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4026 clock,
4027 auxdiv,
4028 divsel,
4029 phasedir,
4030 phaseinc);
4031
4032 /* Program SSCDIVINTPHASE6 */
4033 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4034 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4035 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4036 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4037 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4038 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4039 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4040 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4041
4042 /* Program SSCAUXDIV */
4043 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4044 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4045 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4046 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4047
4048 /* Enable modulator and associated divider */
4049 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4050 temp &= ~SBI_SSCCTL_DISABLE;
4051 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4052
4053 /* Wait for initialization time */
4054 udelay(24);
4055
4056 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4057
4058 mutex_unlock(&dev_priv->dpio_lock);
4059 }
4060
4061 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4062 enum pipe pch_transcoder)
4063 {
4064 struct drm_device *dev = crtc->base.dev;
4065 struct drm_i915_private *dev_priv = dev->dev_private;
4066 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4067
4068 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4069 I915_READ(HTOTAL(cpu_transcoder)));
4070 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4071 I915_READ(HBLANK(cpu_transcoder)));
4072 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4073 I915_READ(HSYNC(cpu_transcoder)));
4074
4075 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4076 I915_READ(VTOTAL(cpu_transcoder)));
4077 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4078 I915_READ(VBLANK(cpu_transcoder)));
4079 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4080 I915_READ(VSYNC(cpu_transcoder)));
4081 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4082 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4083 }
4084
4085 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4086 {
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 uint32_t temp;
4089
4090 temp = I915_READ(SOUTH_CHICKEN1);
4091 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4092 return;
4093
4094 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4095 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4096
4097 temp &= ~FDI_BC_BIFURCATION_SELECT;
4098 if (enable)
4099 temp |= FDI_BC_BIFURCATION_SELECT;
4100
4101 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4102 I915_WRITE(SOUTH_CHICKEN1, temp);
4103 POSTING_READ(SOUTH_CHICKEN1);
4104 }
4105
4106 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4107 {
4108 struct drm_device *dev = intel_crtc->base.dev;
4109
4110 switch (intel_crtc->pipe) {
4111 case PIPE_A:
4112 break;
4113 case PIPE_B:
4114 if (intel_crtc->config->fdi_lanes > 2)
4115 cpt_set_fdi_bc_bifurcation(dev, false);
4116 else
4117 cpt_set_fdi_bc_bifurcation(dev, true);
4118
4119 break;
4120 case PIPE_C:
4121 cpt_set_fdi_bc_bifurcation(dev, true);
4122
4123 break;
4124 default:
4125 BUG();
4126 }
4127 }
4128
4129 /*
4130 * Enable PCH resources required for PCH ports:
4131 * - PCH PLLs
4132 * - FDI training & RX/TX
4133 * - update transcoder timings
4134 * - DP transcoding bits
4135 * - transcoder
4136 */
4137 static void ironlake_pch_enable(struct drm_crtc *crtc)
4138 {
4139 struct drm_device *dev = crtc->dev;
4140 struct drm_i915_private *dev_priv = dev->dev_private;
4141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4142 int pipe = intel_crtc->pipe;
4143 u32 reg, temp;
4144
4145 assert_pch_transcoder_disabled(dev_priv, pipe);
4146
4147 if (IS_IVYBRIDGE(dev))
4148 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4149
4150 /* Write the TU size bits before fdi link training, so that error
4151 * detection works. */
4152 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4153 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4154
4155 /* For PCH output, training FDI link */
4156 dev_priv->display.fdi_link_train(crtc);
4157
4158 /* We need to program the right clock selection before writing the pixel
4159 * mutliplier into the DPLL. */
4160 if (HAS_PCH_CPT(dev)) {
4161 u32 sel;
4162
4163 temp = I915_READ(PCH_DPLL_SEL);
4164 temp |= TRANS_DPLL_ENABLE(pipe);
4165 sel = TRANS_DPLLB_SEL(pipe);
4166 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4167 temp |= sel;
4168 else
4169 temp &= ~sel;
4170 I915_WRITE(PCH_DPLL_SEL, temp);
4171 }
4172
4173 /* XXX: pch pll's can be enabled any time before we enable the PCH
4174 * transcoder, and we actually should do this to not upset any PCH
4175 * transcoder that already use the clock when we share it.
4176 *
4177 * Note that enable_shared_dpll tries to do the right thing, but
4178 * get_shared_dpll unconditionally resets the pll - we need that to have
4179 * the right LVDS enable sequence. */
4180 intel_enable_shared_dpll(intel_crtc);
4181
4182 /* set transcoder timing, panel must allow it */
4183 assert_panel_unlocked(dev_priv, pipe);
4184 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4185
4186 intel_fdi_normal_train(crtc);
4187
4188 /* For PCH DP, enable TRANS_DP_CTL */
4189 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4190 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4191 reg = TRANS_DP_CTL(pipe);
4192 temp = I915_READ(reg);
4193 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4194 TRANS_DP_SYNC_MASK |
4195 TRANS_DP_BPC_MASK);
4196 temp |= (TRANS_DP_OUTPUT_ENABLE |
4197 TRANS_DP_ENH_FRAMING);
4198 temp |= bpc << 9; /* same format but at 11:9 */
4199
4200 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4201 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4202 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4203 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4204
4205 switch (intel_trans_dp_port_sel(crtc)) {
4206 case PCH_DP_B:
4207 temp |= TRANS_DP_PORT_SEL_B;
4208 break;
4209 case PCH_DP_C:
4210 temp |= TRANS_DP_PORT_SEL_C;
4211 break;
4212 case PCH_DP_D:
4213 temp |= TRANS_DP_PORT_SEL_D;
4214 break;
4215 default:
4216 BUG();
4217 }
4218
4219 I915_WRITE(reg, temp);
4220 }
4221
4222 ironlake_enable_pch_transcoder(dev_priv, pipe);
4223 }
4224
4225 static void lpt_pch_enable(struct drm_crtc *crtc)
4226 {
4227 struct drm_device *dev = crtc->dev;
4228 struct drm_i915_private *dev_priv = dev->dev_private;
4229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4230 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4231
4232 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4233
4234 lpt_program_iclkip(crtc);
4235
4236 /* Set transcoder timing. */
4237 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4238
4239 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4240 }
4241
4242 void intel_put_shared_dpll(struct intel_crtc *crtc)
4243 {
4244 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4245
4246 if (pll == NULL)
4247 return;
4248
4249 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4250 WARN(1, "bad %s crtc mask\n", pll->name);
4251 return;
4252 }
4253
4254 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4255 if (pll->config.crtc_mask == 0) {
4256 WARN_ON(pll->on);
4257 WARN_ON(pll->active);
4258 }
4259
4260 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4261 }
4262
4263 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4264 struct intel_crtc_state *crtc_state)
4265 {
4266 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4267 struct intel_shared_dpll *pll;
4268 enum intel_dpll_id i;
4269
4270 if (HAS_PCH_IBX(dev_priv->dev)) {
4271 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4272 i = (enum intel_dpll_id) crtc->pipe;
4273 pll = &dev_priv->shared_dplls[i];
4274
4275 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4276 crtc->base.base.id, pll->name);
4277
4278 WARN_ON(pll->new_config->crtc_mask);
4279
4280 goto found;
4281 }
4282
4283 if (IS_BROXTON(dev_priv->dev)) {
4284 /* PLL is attached to port in bxt */
4285 struct intel_encoder *encoder;
4286 struct intel_digital_port *intel_dig_port;
4287
4288 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4289 if (WARN_ON(!encoder))
4290 return NULL;
4291
4292 intel_dig_port = enc_to_dig_port(&encoder->base);
4293 /* 1:1 mapping between ports and PLLs */
4294 i = (enum intel_dpll_id)intel_dig_port->port;
4295 pll = &dev_priv->shared_dplls[i];
4296 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4297 crtc->base.base.id, pll->name);
4298 WARN_ON(pll->new_config->crtc_mask);
4299
4300 goto found;
4301 }
4302
4303 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4304 pll = &dev_priv->shared_dplls[i];
4305
4306 /* Only want to check enabled timings first */
4307 if (pll->new_config->crtc_mask == 0)
4308 continue;
4309
4310 if (memcmp(&crtc_state->dpll_hw_state,
4311 &pll->new_config->hw_state,
4312 sizeof(pll->new_config->hw_state)) == 0) {
4313 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4314 crtc->base.base.id, pll->name,
4315 pll->new_config->crtc_mask,
4316 pll->active);
4317 goto found;
4318 }
4319 }
4320
4321 /* Ok no matching timings, maybe there's a free one? */
4322 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4323 pll = &dev_priv->shared_dplls[i];
4324 if (pll->new_config->crtc_mask == 0) {
4325 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4326 crtc->base.base.id, pll->name);
4327 goto found;
4328 }
4329 }
4330
4331 return NULL;
4332
4333 found:
4334 if (pll->new_config->crtc_mask == 0)
4335 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4336
4337 crtc_state->shared_dpll = i;
4338 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4339 pipe_name(crtc->pipe));
4340
4341 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4342
4343 return pll;
4344 }
4345
4346 /**
4347 * intel_shared_dpll_start_config - start a new PLL staged config
4348 * @dev_priv: DRM device
4349 * @clear_pipes: mask of pipes that will have their PLLs freed
4350 *
4351 * Starts a new PLL staged config, copying the current config but
4352 * releasing the references of pipes specified in clear_pipes.
4353 */
4354 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4355 unsigned clear_pipes)
4356 {
4357 struct intel_shared_dpll *pll;
4358 enum intel_dpll_id i;
4359
4360 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4361 pll = &dev_priv->shared_dplls[i];
4362
4363 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4364 GFP_KERNEL);
4365 if (!pll->new_config)
4366 goto cleanup;
4367
4368 pll->new_config->crtc_mask &= ~clear_pipes;
4369 }
4370
4371 return 0;
4372
4373 cleanup:
4374 while (--i >= 0) {
4375 pll = &dev_priv->shared_dplls[i];
4376 kfree(pll->new_config);
4377 pll->new_config = NULL;
4378 }
4379
4380 return -ENOMEM;
4381 }
4382
4383 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4384 {
4385 struct intel_shared_dpll *pll;
4386 enum intel_dpll_id i;
4387
4388 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4389 pll = &dev_priv->shared_dplls[i];
4390
4391 WARN_ON(pll->new_config == &pll->config);
4392
4393 pll->config = *pll->new_config;
4394 kfree(pll->new_config);
4395 pll->new_config = NULL;
4396 }
4397 }
4398
4399 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4400 {
4401 struct intel_shared_dpll *pll;
4402 enum intel_dpll_id i;
4403
4404 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4405 pll = &dev_priv->shared_dplls[i];
4406
4407 WARN_ON(pll->new_config == &pll->config);
4408
4409 kfree(pll->new_config);
4410 pll->new_config = NULL;
4411 }
4412 }
4413
4414 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4415 {
4416 struct drm_i915_private *dev_priv = dev->dev_private;
4417 int dslreg = PIPEDSL(pipe);
4418 u32 temp;
4419
4420 temp = I915_READ(dslreg);
4421 udelay(500);
4422 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4423 if (wait_for(I915_READ(dslreg) != temp, 5))
4424 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4425 }
4426 }
4427
4428 /**
4429 * skl_update_scaler_users - Stages update to crtc's scaler state
4430 * @intel_crtc: crtc
4431 * @crtc_state: crtc_state
4432 * @plane: plane (NULL indicates crtc is requesting update)
4433 * @plane_state: plane's state
4434 * @force_detach: request unconditional detachment of scaler
4435 *
4436 * This function updates scaler state for requested plane or crtc.
4437 * To request scaler usage update for a plane, caller shall pass plane pointer.
4438 * To request scaler usage update for crtc, caller shall pass plane pointer
4439 * as NULL.
4440 *
4441 * Return
4442 * 0 - scaler_usage updated successfully
4443 * error - requested scaling cannot be supported or other error condition
4444 */
4445 int
4446 skl_update_scaler_users(
4447 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4448 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4449 int force_detach)
4450 {
4451 int need_scaling;
4452 int idx;
4453 int src_w, src_h, dst_w, dst_h;
4454 int *scaler_id;
4455 struct drm_framebuffer *fb;
4456 struct intel_crtc_scaler_state *scaler_state;
4457 unsigned int rotation;
4458
4459 if (!intel_crtc || !crtc_state)
4460 return 0;
4461
4462 scaler_state = &crtc_state->scaler_state;
4463
4464 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4465 fb = intel_plane ? plane_state->base.fb : NULL;
4466
4467 if (intel_plane) {
4468 src_w = drm_rect_width(&plane_state->src) >> 16;
4469 src_h = drm_rect_height(&plane_state->src) >> 16;
4470 dst_w = drm_rect_width(&plane_state->dst);
4471 dst_h = drm_rect_height(&plane_state->dst);
4472 scaler_id = &plane_state->scaler_id;
4473 rotation = plane_state->base.rotation;
4474 } else {
4475 struct drm_display_mode *adjusted_mode =
4476 &crtc_state->base.adjusted_mode;
4477 src_w = crtc_state->pipe_src_w;
4478 src_h = crtc_state->pipe_src_h;
4479 dst_w = adjusted_mode->hdisplay;
4480 dst_h = adjusted_mode->vdisplay;
4481 scaler_id = &scaler_state->scaler_id;
4482 rotation = DRM_ROTATE_0;
4483 }
4484
4485 need_scaling = intel_rotation_90_or_270(rotation) ?
4486 (src_h != dst_w || src_w != dst_h):
4487 (src_w != dst_w || src_h != dst_h);
4488
4489 /*
4490 * if plane is being disabled or scaler is no more required or force detach
4491 * - free scaler binded to this plane/crtc
4492 * - in order to do this, update crtc->scaler_usage
4493 *
4494 * Here scaler state in crtc_state is set free so that
4495 * scaler can be assigned to other user. Actual register
4496 * update to free the scaler is done in plane/panel-fit programming.
4497 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4498 */
4499 if (force_detach || !need_scaling || (intel_plane &&
4500 (!fb || !plane_state->visible))) {
4501 if (*scaler_id >= 0) {
4502 scaler_state->scaler_users &= ~(1 << idx);
4503 scaler_state->scalers[*scaler_id].in_use = 0;
4504
4505 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4506 "crtc_state = %p scaler_users = 0x%x\n",
4507 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4508 intel_plane ? intel_plane->base.base.id :
4509 intel_crtc->base.base.id, crtc_state,
4510 scaler_state->scaler_users);
4511 *scaler_id = -1;
4512 }
4513 return 0;
4514 }
4515
4516 /* range checks */
4517 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4518 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4519
4520 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4521 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4522 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4523 "size is out of scaler range\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4527 return -EINVAL;
4528 }
4529
4530 /* check colorkey */
4531 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4532 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4533 intel_plane->base.base.id);
4534 return -EINVAL;
4535 }
4536
4537 /* Check src format */
4538 if (intel_plane) {
4539 switch (fb->pixel_format) {
4540 case DRM_FORMAT_RGB565:
4541 case DRM_FORMAT_XBGR8888:
4542 case DRM_FORMAT_XRGB8888:
4543 case DRM_FORMAT_ABGR8888:
4544 case DRM_FORMAT_ARGB8888:
4545 case DRM_FORMAT_XRGB2101010:
4546 case DRM_FORMAT_ARGB2101010:
4547 case DRM_FORMAT_XBGR2101010:
4548 case DRM_FORMAT_ABGR2101010:
4549 case DRM_FORMAT_YUYV:
4550 case DRM_FORMAT_YVYU:
4551 case DRM_FORMAT_UYVY:
4552 case DRM_FORMAT_VYUY:
4553 break;
4554 default:
4555 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4556 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4557 return -EINVAL;
4558 }
4559 }
4560
4561 /* mark this plane as a scaler user in crtc_state */
4562 scaler_state->scaler_users |= (1 << idx);
4563 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4564 "crtc_state = %p scaler_users = 0x%x\n",
4565 intel_plane ? "PLANE" : "CRTC",
4566 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4567 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4568 return 0;
4569 }
4570
4571 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4572 {
4573 struct drm_device *dev = crtc->base.dev;
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 int pipe = crtc->pipe;
4576 struct intel_crtc_scaler_state *scaler_state =
4577 &crtc->config->scaler_state;
4578
4579 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4580
4581 /* To update pfit, first update scaler state */
4582 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4583 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4584 skl_detach_scalers(crtc);
4585 if (!enable)
4586 return;
4587
4588 if (crtc->config->pch_pfit.enabled) {
4589 int id;
4590
4591 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4592 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4593 return;
4594 }
4595
4596 id = scaler_state->scaler_id;
4597 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4598 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4599 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4600 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4601
4602 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4603 }
4604 }
4605
4606 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4607 {
4608 struct drm_device *dev = crtc->base.dev;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610 int pipe = crtc->pipe;
4611
4612 if (crtc->config->pch_pfit.enabled) {
4613 /* Force use of hard-coded filter coefficients
4614 * as some pre-programmed values are broken,
4615 * e.g. x201.
4616 */
4617 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4618 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4619 PF_PIPE_SEL_IVB(pipe));
4620 else
4621 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4622 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4623 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4624 }
4625 }
4626
4627 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4628 {
4629 struct drm_device *dev = crtc->dev;
4630 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4631 struct drm_plane *plane;
4632 struct intel_plane *intel_plane;
4633
4634 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4635 intel_plane = to_intel_plane(plane);
4636 if (intel_plane->pipe == pipe)
4637 intel_plane_restore(&intel_plane->base);
4638 }
4639 }
4640
4641 void hsw_enable_ips(struct intel_crtc *crtc)
4642 {
4643 struct drm_device *dev = crtc->base.dev;
4644 struct drm_i915_private *dev_priv = dev->dev_private;
4645
4646 if (!crtc->config->ips_enabled)
4647 return;
4648
4649 /* We can only enable IPS after we enable a plane and wait for a vblank */
4650 intel_wait_for_vblank(dev, crtc->pipe);
4651
4652 assert_plane_enabled(dev_priv, crtc->plane);
4653 if (IS_BROADWELL(dev)) {
4654 mutex_lock(&dev_priv->rps.hw_lock);
4655 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4656 mutex_unlock(&dev_priv->rps.hw_lock);
4657 /* Quoting Art Runyan: "its not safe to expect any particular
4658 * value in IPS_CTL bit 31 after enabling IPS through the
4659 * mailbox." Moreover, the mailbox may return a bogus state,
4660 * so we need to just enable it and continue on.
4661 */
4662 } else {
4663 I915_WRITE(IPS_CTL, IPS_ENABLE);
4664 /* The bit only becomes 1 in the next vblank, so this wait here
4665 * is essentially intel_wait_for_vblank. If we don't have this
4666 * and don't wait for vblanks until the end of crtc_enable, then
4667 * the HW state readout code will complain that the expected
4668 * IPS_CTL value is not the one we read. */
4669 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4670 DRM_ERROR("Timed out waiting for IPS enable\n");
4671 }
4672 }
4673
4674 void hsw_disable_ips(struct intel_crtc *crtc)
4675 {
4676 struct drm_device *dev = crtc->base.dev;
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678
4679 if (!crtc->config->ips_enabled)
4680 return;
4681
4682 assert_plane_enabled(dev_priv, crtc->plane);
4683 if (IS_BROADWELL(dev)) {
4684 mutex_lock(&dev_priv->rps.hw_lock);
4685 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4686 mutex_unlock(&dev_priv->rps.hw_lock);
4687 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4688 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4689 DRM_ERROR("Timed out waiting for IPS disable\n");
4690 } else {
4691 I915_WRITE(IPS_CTL, 0);
4692 POSTING_READ(IPS_CTL);
4693 }
4694
4695 /* We need to wait for a vblank before we can disable the plane. */
4696 intel_wait_for_vblank(dev, crtc->pipe);
4697 }
4698
4699 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4700 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4701 {
4702 struct drm_device *dev = crtc->dev;
4703 struct drm_i915_private *dev_priv = dev->dev_private;
4704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4705 enum pipe pipe = intel_crtc->pipe;
4706 int palreg = PALETTE(pipe);
4707 int i;
4708 bool reenable_ips = false;
4709
4710 /* The clocks have to be on to load the palette. */
4711 if (!crtc->state->enable || !intel_crtc->active)
4712 return;
4713
4714 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4715 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4716 assert_dsi_pll_enabled(dev_priv);
4717 else
4718 assert_pll_enabled(dev_priv, pipe);
4719 }
4720
4721 /* use legacy palette for Ironlake */
4722 if (!HAS_GMCH_DISPLAY(dev))
4723 palreg = LGC_PALETTE(pipe);
4724
4725 /* Workaround : Do not read or write the pipe palette/gamma data while
4726 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4727 */
4728 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4729 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4730 GAMMA_MODE_MODE_SPLIT)) {
4731 hsw_disable_ips(intel_crtc);
4732 reenable_ips = true;
4733 }
4734
4735 for (i = 0; i < 256; i++) {
4736 I915_WRITE(palreg + 4 * i,
4737 (intel_crtc->lut_r[i] << 16) |
4738 (intel_crtc->lut_g[i] << 8) |
4739 intel_crtc->lut_b[i]);
4740 }
4741
4742 if (reenable_ips)
4743 hsw_enable_ips(intel_crtc);
4744 }
4745
4746 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4747 {
4748 if (intel_crtc->overlay) {
4749 struct drm_device *dev = intel_crtc->base.dev;
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751
4752 mutex_lock(&dev->struct_mutex);
4753 dev_priv->mm.interruptible = false;
4754 (void) intel_overlay_switch_off(intel_crtc->overlay);
4755 dev_priv->mm.interruptible = true;
4756 mutex_unlock(&dev->struct_mutex);
4757 }
4758
4759 /* Let userspace switch the overlay on again. In most cases userspace
4760 * has to recompute where to put it anyway.
4761 */
4762 }
4763
4764 /**
4765 * intel_post_enable_primary - Perform operations after enabling primary plane
4766 * @crtc: the CRTC whose primary plane was just enabled
4767 *
4768 * Performs potentially sleeping operations that must be done after the primary
4769 * plane is enabled, such as updating FBC and IPS. Note that this may be
4770 * called due to an explicit primary plane update, or due to an implicit
4771 * re-enable that is caused when a sprite plane is updated to no longer
4772 * completely hide the primary plane.
4773 */
4774 static void
4775 intel_post_enable_primary(struct drm_crtc *crtc)
4776 {
4777 struct drm_device *dev = crtc->dev;
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4780 int pipe = intel_crtc->pipe;
4781
4782 /*
4783 * BDW signals flip done immediately if the plane
4784 * is disabled, even if the plane enable is already
4785 * armed to occur at the next vblank :(
4786 */
4787 if (IS_BROADWELL(dev))
4788 intel_wait_for_vblank(dev, pipe);
4789
4790 /*
4791 * FIXME IPS should be fine as long as one plane is
4792 * enabled, but in practice it seems to have problems
4793 * when going from primary only to sprite only and vice
4794 * versa.
4795 */
4796 hsw_enable_ips(intel_crtc);
4797
4798 mutex_lock(&dev->struct_mutex);
4799 intel_fbc_update(dev);
4800 mutex_unlock(&dev->struct_mutex);
4801
4802 /*
4803 * Gen2 reports pipe underruns whenever all planes are disabled.
4804 * So don't enable underrun reporting before at least some planes
4805 * are enabled.
4806 * FIXME: Need to fix the logic to work when we turn off all planes
4807 * but leave the pipe running.
4808 */
4809 if (IS_GEN2(dev))
4810 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4811
4812 /* Underruns don't raise interrupts, so check manually. */
4813 if (HAS_GMCH_DISPLAY(dev))
4814 i9xx_check_fifo_underruns(dev_priv);
4815 }
4816
4817 /**
4818 * intel_pre_disable_primary - Perform operations before disabling primary plane
4819 * @crtc: the CRTC whose primary plane is to be disabled
4820 *
4821 * Performs potentially sleeping operations that must be done before the
4822 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4823 * be called due to an explicit primary plane update, or due to an implicit
4824 * disable that is caused when a sprite plane completely hides the primary
4825 * plane.
4826 */
4827 static void
4828 intel_pre_disable_primary(struct drm_crtc *crtc)
4829 {
4830 struct drm_device *dev = crtc->dev;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833 int pipe = intel_crtc->pipe;
4834
4835 /*
4836 * Gen2 reports pipe underruns whenever all planes are disabled.
4837 * So diasble underrun reporting before all the planes get disabled.
4838 * FIXME: Need to fix the logic to work when we turn off all planes
4839 * but leave the pipe running.
4840 */
4841 if (IS_GEN2(dev))
4842 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4843
4844 /*
4845 * Vblank time updates from the shadow to live plane control register
4846 * are blocked if the memory self-refresh mode is active at that
4847 * moment. So to make sure the plane gets truly disabled, disable
4848 * first the self-refresh mode. The self-refresh enable bit in turn
4849 * will be checked/applied by the HW only at the next frame start
4850 * event which is after the vblank start event, so we need to have a
4851 * wait-for-vblank between disabling the plane and the pipe.
4852 */
4853 if (HAS_GMCH_DISPLAY(dev))
4854 intel_set_memory_cxsr(dev_priv, false);
4855
4856 mutex_lock(&dev->struct_mutex);
4857 if (dev_priv->fbc.crtc == intel_crtc)
4858 intel_fbc_disable(dev);
4859 mutex_unlock(&dev->struct_mutex);
4860
4861 /*
4862 * FIXME IPS should be fine as long as one plane is
4863 * enabled, but in practice it seems to have problems
4864 * when going from primary only to sprite only and vice
4865 * versa.
4866 */
4867 hsw_disable_ips(intel_crtc);
4868 }
4869
4870 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4871 {
4872 intel_enable_primary_hw_plane(crtc->primary, crtc);
4873 intel_enable_sprite_planes(crtc);
4874 intel_crtc_update_cursor(crtc, true);
4875
4876 intel_post_enable_primary(crtc);
4877 }
4878
4879 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4880 {
4881 struct drm_device *dev = crtc->dev;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883 struct intel_plane *intel_plane;
4884 int pipe = intel_crtc->pipe;
4885
4886 intel_crtc_wait_for_pending_flips(crtc);
4887
4888 intel_pre_disable_primary(crtc);
4889
4890 intel_crtc_dpms_overlay_disable(intel_crtc);
4891 for_each_intel_plane(dev, intel_plane) {
4892 if (intel_plane->pipe == pipe) {
4893 struct drm_crtc *from = intel_plane->base.crtc;
4894
4895 intel_plane->disable_plane(&intel_plane->base,
4896 from ?: crtc, true);
4897 }
4898 }
4899
4900 /*
4901 * FIXME: Once we grow proper nuclear flip support out of this we need
4902 * to compute the mask of flip planes precisely. For the time being
4903 * consider this a flip to a NULL plane.
4904 */
4905 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4906 }
4907
4908 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4909 {
4910 struct drm_device *dev = crtc->dev;
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4913 struct intel_encoder *encoder;
4914 int pipe = intel_crtc->pipe;
4915
4916 WARN_ON(!crtc->state->enable);
4917
4918 if (intel_crtc->active)
4919 return;
4920
4921 if (intel_crtc->config->has_pch_encoder)
4922 intel_prepare_shared_dpll(intel_crtc);
4923
4924 if (intel_crtc->config->has_dp_encoder)
4925 intel_dp_set_m_n(intel_crtc, M1_N1);
4926
4927 intel_set_pipe_timings(intel_crtc);
4928
4929 if (intel_crtc->config->has_pch_encoder) {
4930 intel_cpu_transcoder_set_m_n(intel_crtc,
4931 &intel_crtc->config->fdi_m_n, NULL);
4932 }
4933
4934 ironlake_set_pipeconf(crtc);
4935
4936 intel_crtc->active = true;
4937
4938 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4939 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4940
4941 for_each_encoder_on_crtc(dev, crtc, encoder)
4942 if (encoder->pre_enable)
4943 encoder->pre_enable(encoder);
4944
4945 if (intel_crtc->config->has_pch_encoder) {
4946 /* Note: FDI PLL enabling _must_ be done before we enable the
4947 * cpu pipes, hence this is separate from all the other fdi/pch
4948 * enabling. */
4949 ironlake_fdi_pll_enable(intel_crtc);
4950 } else {
4951 assert_fdi_tx_disabled(dev_priv, pipe);
4952 assert_fdi_rx_disabled(dev_priv, pipe);
4953 }
4954
4955 ironlake_pfit_enable(intel_crtc);
4956
4957 /*
4958 * On ILK+ LUT must be loaded before the pipe is running but with
4959 * clocks enabled
4960 */
4961 intel_crtc_load_lut(crtc);
4962
4963 intel_update_watermarks(crtc);
4964 intel_enable_pipe(intel_crtc);
4965
4966 if (intel_crtc->config->has_pch_encoder)
4967 ironlake_pch_enable(crtc);
4968
4969 assert_vblank_disabled(crtc);
4970 drm_crtc_vblank_on(crtc);
4971
4972 for_each_encoder_on_crtc(dev, crtc, encoder)
4973 encoder->enable(encoder);
4974
4975 if (HAS_PCH_CPT(dev))
4976 cpt_verify_modeset(dev, intel_crtc->pipe);
4977 }
4978
4979 /* IPS only exists on ULT machines and is tied to pipe A. */
4980 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4981 {
4982 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4983 }
4984
4985 /*
4986 * This implements the workaround described in the "notes" section of the mode
4987 * set sequence documentation. When going from no pipes or single pipe to
4988 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4989 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4990 */
4991 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4992 {
4993 struct drm_device *dev = crtc->base.dev;
4994 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4995
4996 /* We want to get the other_active_crtc only if there's only 1 other
4997 * active crtc. */
4998 for_each_intel_crtc(dev, crtc_it) {
4999 if (!crtc_it->active || crtc_it == crtc)
5000 continue;
5001
5002 if (other_active_crtc)
5003 return;
5004
5005 other_active_crtc = crtc_it;
5006 }
5007 if (!other_active_crtc)
5008 return;
5009
5010 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5011 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5012 }
5013
5014 static void haswell_crtc_enable(struct drm_crtc *crtc)
5015 {
5016 struct drm_device *dev = crtc->dev;
5017 struct drm_i915_private *dev_priv = dev->dev_private;
5018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5019 struct intel_encoder *encoder;
5020 int pipe = intel_crtc->pipe;
5021
5022 WARN_ON(!crtc->state->enable);
5023
5024 if (intel_crtc->active)
5025 return;
5026
5027 if (intel_crtc_to_shared_dpll(intel_crtc))
5028 intel_enable_shared_dpll(intel_crtc);
5029
5030 if (intel_crtc->config->has_dp_encoder)
5031 intel_dp_set_m_n(intel_crtc, M1_N1);
5032
5033 intel_set_pipe_timings(intel_crtc);
5034
5035 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5036 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5037 intel_crtc->config->pixel_multiplier - 1);
5038 }
5039
5040 if (intel_crtc->config->has_pch_encoder) {
5041 intel_cpu_transcoder_set_m_n(intel_crtc,
5042 &intel_crtc->config->fdi_m_n, NULL);
5043 }
5044
5045 haswell_set_pipeconf(crtc);
5046
5047 intel_set_pipe_csc(crtc);
5048
5049 intel_crtc->active = true;
5050
5051 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5052 for_each_encoder_on_crtc(dev, crtc, encoder)
5053 if (encoder->pre_enable)
5054 encoder->pre_enable(encoder);
5055
5056 if (intel_crtc->config->has_pch_encoder) {
5057 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5058 true);
5059 dev_priv->display.fdi_link_train(crtc);
5060 }
5061
5062 intel_ddi_enable_pipe_clock(intel_crtc);
5063
5064 if (INTEL_INFO(dev)->gen == 9)
5065 skylake_pfit_update(intel_crtc, 1);
5066 else if (INTEL_INFO(dev)->gen < 9)
5067 ironlake_pfit_enable(intel_crtc);
5068 else
5069 MISSING_CASE(INTEL_INFO(dev)->gen);
5070
5071 /*
5072 * On ILK+ LUT must be loaded before the pipe is running but with
5073 * clocks enabled
5074 */
5075 intel_crtc_load_lut(crtc);
5076
5077 intel_ddi_set_pipe_settings(crtc);
5078 intel_ddi_enable_transcoder_func(crtc);
5079
5080 intel_update_watermarks(crtc);
5081 intel_enable_pipe(intel_crtc);
5082
5083 if (intel_crtc->config->has_pch_encoder)
5084 lpt_pch_enable(crtc);
5085
5086 if (intel_crtc->config->dp_encoder_is_mst)
5087 intel_ddi_set_vc_payload_alloc(crtc, true);
5088
5089 assert_vblank_disabled(crtc);
5090 drm_crtc_vblank_on(crtc);
5091
5092 for_each_encoder_on_crtc(dev, crtc, encoder) {
5093 encoder->enable(encoder);
5094 intel_opregion_notify_encoder(encoder, true);
5095 }
5096
5097 /* If we change the relative order between pipe/planes enabling, we need
5098 * to change the workaround. */
5099 haswell_mode_set_planes_workaround(intel_crtc);
5100 }
5101
5102 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5103 {
5104 struct drm_device *dev = crtc->base.dev;
5105 struct drm_i915_private *dev_priv = dev->dev_private;
5106 int pipe = crtc->pipe;
5107
5108 /* To avoid upsetting the power well on haswell only disable the pfit if
5109 * it's in use. The hw state code will make sure we get this right. */
5110 if (crtc->config->pch_pfit.enabled) {
5111 I915_WRITE(PF_CTL(pipe), 0);
5112 I915_WRITE(PF_WIN_POS(pipe), 0);
5113 I915_WRITE(PF_WIN_SZ(pipe), 0);
5114 }
5115 }
5116
5117 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5118 {
5119 struct drm_device *dev = crtc->dev;
5120 struct drm_i915_private *dev_priv = dev->dev_private;
5121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5122 struct intel_encoder *encoder;
5123 int pipe = intel_crtc->pipe;
5124 u32 reg, temp;
5125
5126 if (!intel_crtc->active)
5127 return;
5128
5129 for_each_encoder_on_crtc(dev, crtc, encoder)
5130 encoder->disable(encoder);
5131
5132 drm_crtc_vblank_off(crtc);
5133 assert_vblank_disabled(crtc);
5134
5135 if (intel_crtc->config->has_pch_encoder)
5136 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5137
5138 intel_disable_pipe(intel_crtc);
5139
5140 ironlake_pfit_disable(intel_crtc);
5141
5142 for_each_encoder_on_crtc(dev, crtc, encoder)
5143 if (encoder->post_disable)
5144 encoder->post_disable(encoder);
5145
5146 if (intel_crtc->config->has_pch_encoder) {
5147 ironlake_fdi_disable(crtc);
5148
5149 ironlake_disable_pch_transcoder(dev_priv, pipe);
5150
5151 if (HAS_PCH_CPT(dev)) {
5152 /* disable TRANS_DP_CTL */
5153 reg = TRANS_DP_CTL(pipe);
5154 temp = I915_READ(reg);
5155 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5156 TRANS_DP_PORT_SEL_MASK);
5157 temp |= TRANS_DP_PORT_SEL_NONE;
5158 I915_WRITE(reg, temp);
5159
5160 /* disable DPLL_SEL */
5161 temp = I915_READ(PCH_DPLL_SEL);
5162 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5163 I915_WRITE(PCH_DPLL_SEL, temp);
5164 }
5165
5166 /* disable PCH DPLL */
5167 intel_disable_shared_dpll(intel_crtc);
5168
5169 ironlake_fdi_pll_disable(intel_crtc);
5170 }
5171
5172 intel_crtc->active = false;
5173 intel_update_watermarks(crtc);
5174
5175 mutex_lock(&dev->struct_mutex);
5176 intel_fbc_update(dev);
5177 mutex_unlock(&dev->struct_mutex);
5178 }
5179
5180 static void haswell_crtc_disable(struct drm_crtc *crtc)
5181 {
5182 struct drm_device *dev = crtc->dev;
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5185 struct intel_encoder *encoder;
5186 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5187
5188 if (!intel_crtc->active)
5189 return;
5190
5191 for_each_encoder_on_crtc(dev, crtc, encoder) {
5192 intel_opregion_notify_encoder(encoder, false);
5193 encoder->disable(encoder);
5194 }
5195
5196 drm_crtc_vblank_off(crtc);
5197 assert_vblank_disabled(crtc);
5198
5199 if (intel_crtc->config->has_pch_encoder)
5200 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5201 false);
5202 intel_disable_pipe(intel_crtc);
5203
5204 if (intel_crtc->config->dp_encoder_is_mst)
5205 intel_ddi_set_vc_payload_alloc(crtc, false);
5206
5207 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5208
5209 if (INTEL_INFO(dev)->gen == 9)
5210 skylake_pfit_update(intel_crtc, 0);
5211 else if (INTEL_INFO(dev)->gen < 9)
5212 ironlake_pfit_disable(intel_crtc);
5213 else
5214 MISSING_CASE(INTEL_INFO(dev)->gen);
5215
5216 intel_ddi_disable_pipe_clock(intel_crtc);
5217
5218 if (intel_crtc->config->has_pch_encoder) {
5219 lpt_disable_pch_transcoder(dev_priv);
5220 intel_ddi_fdi_disable(crtc);
5221 }
5222
5223 for_each_encoder_on_crtc(dev, crtc, encoder)
5224 if (encoder->post_disable)
5225 encoder->post_disable(encoder);
5226
5227 intel_crtc->active = false;
5228 intel_update_watermarks(crtc);
5229
5230 mutex_lock(&dev->struct_mutex);
5231 intel_fbc_update(dev);
5232 mutex_unlock(&dev->struct_mutex);
5233
5234 if (intel_crtc_to_shared_dpll(intel_crtc))
5235 intel_disable_shared_dpll(intel_crtc);
5236 }
5237
5238 static void ironlake_crtc_off(struct drm_crtc *crtc)
5239 {
5240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5241 intel_put_shared_dpll(intel_crtc);
5242 }
5243
5244
5245 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5246 {
5247 struct drm_device *dev = crtc->base.dev;
5248 struct drm_i915_private *dev_priv = dev->dev_private;
5249 struct intel_crtc_state *pipe_config = crtc->config;
5250
5251 if (!pipe_config->gmch_pfit.control)
5252 return;
5253
5254 /*
5255 * The panel fitter should only be adjusted whilst the pipe is disabled,
5256 * according to register description and PRM.
5257 */
5258 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5259 assert_pipe_disabled(dev_priv, crtc->pipe);
5260
5261 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5262 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5263
5264 /* Border color in case we don't scale up to the full screen. Black by
5265 * default, change to something else for debugging. */
5266 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5267 }
5268
5269 static enum intel_display_power_domain port_to_power_domain(enum port port)
5270 {
5271 switch (port) {
5272 case PORT_A:
5273 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5274 case PORT_B:
5275 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5276 case PORT_C:
5277 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5278 case PORT_D:
5279 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5280 default:
5281 WARN_ON_ONCE(1);
5282 return POWER_DOMAIN_PORT_OTHER;
5283 }
5284 }
5285
5286 #define for_each_power_domain(domain, mask) \
5287 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5288 if ((1 << (domain)) & (mask))
5289
5290 enum intel_display_power_domain
5291 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5292 {
5293 struct drm_device *dev = intel_encoder->base.dev;
5294 struct intel_digital_port *intel_dig_port;
5295
5296 switch (intel_encoder->type) {
5297 case INTEL_OUTPUT_UNKNOWN:
5298 /* Only DDI platforms should ever use this output type */
5299 WARN_ON_ONCE(!HAS_DDI(dev));
5300 case INTEL_OUTPUT_DISPLAYPORT:
5301 case INTEL_OUTPUT_HDMI:
5302 case INTEL_OUTPUT_EDP:
5303 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5304 return port_to_power_domain(intel_dig_port->port);
5305 case INTEL_OUTPUT_DP_MST:
5306 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5307 return port_to_power_domain(intel_dig_port->port);
5308 case INTEL_OUTPUT_ANALOG:
5309 return POWER_DOMAIN_PORT_CRT;
5310 case INTEL_OUTPUT_DSI:
5311 return POWER_DOMAIN_PORT_DSI;
5312 default:
5313 return POWER_DOMAIN_PORT_OTHER;
5314 }
5315 }
5316
5317 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5318 {
5319 struct drm_device *dev = crtc->dev;
5320 struct intel_encoder *intel_encoder;
5321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5322 enum pipe pipe = intel_crtc->pipe;
5323 unsigned long mask;
5324 enum transcoder transcoder;
5325
5326 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5327
5328 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5329 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5330 if (intel_crtc->config->pch_pfit.enabled ||
5331 intel_crtc->config->pch_pfit.force_thru)
5332 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5333
5334 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5335 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5336
5337 return mask;
5338 }
5339
5340 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5341 {
5342 struct drm_device *dev = state->dev;
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5345 struct intel_crtc *crtc;
5346
5347 /*
5348 * First get all needed power domains, then put all unneeded, to avoid
5349 * any unnecessary toggling of the power wells.
5350 */
5351 for_each_intel_crtc(dev, crtc) {
5352 enum intel_display_power_domain domain;
5353
5354 if (!crtc->base.state->enable)
5355 continue;
5356
5357 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5358
5359 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5360 intel_display_power_get(dev_priv, domain);
5361 }
5362
5363 if (dev_priv->display.modeset_global_resources)
5364 dev_priv->display.modeset_global_resources(state);
5365
5366 for_each_intel_crtc(dev, crtc) {
5367 enum intel_display_power_domain domain;
5368
5369 for_each_power_domain(domain, crtc->enabled_power_domains)
5370 intel_display_power_put(dev_priv, domain);
5371
5372 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5373 }
5374
5375 intel_display_set_init_power(dev_priv, false);
5376 }
5377
5378 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5379 {
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 uint32_t divider;
5382 uint32_t ratio;
5383 uint32_t current_freq;
5384 int ret;
5385
5386 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5387 switch (frequency) {
5388 case 144000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 288000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5394 ratio = BXT_DE_PLL_RATIO(60);
5395 break;
5396 case 384000:
5397 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5398 ratio = BXT_DE_PLL_RATIO(60);
5399 break;
5400 case 576000:
5401 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5402 ratio = BXT_DE_PLL_RATIO(60);
5403 break;
5404 case 624000:
5405 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5406 ratio = BXT_DE_PLL_RATIO(65);
5407 break;
5408 case 19200:
5409 /*
5410 * Bypass frequency with DE PLL disabled. Init ratio, divider
5411 * to suppress GCC warning.
5412 */
5413 ratio = 0;
5414 divider = 0;
5415 break;
5416 default:
5417 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5418
5419 return;
5420 }
5421
5422 mutex_lock(&dev_priv->rps.hw_lock);
5423 /* Inform power controller of upcoming frequency change */
5424 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5425 0x80000000);
5426 mutex_unlock(&dev_priv->rps.hw_lock);
5427
5428 if (ret) {
5429 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5430 ret, frequency);
5431 return;
5432 }
5433
5434 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5435 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5436 current_freq = current_freq * 500 + 1000;
5437
5438 /*
5439 * DE PLL has to be disabled when
5440 * - setting to 19.2MHz (bypass, PLL isn't used)
5441 * - before setting to 624MHz (PLL needs toggling)
5442 * - before setting to any frequency from 624MHz (PLL needs toggling)
5443 */
5444 if (frequency == 19200 || frequency == 624000 ||
5445 current_freq == 624000) {
5446 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5447 /* Timeout 200us */
5448 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5449 1))
5450 DRM_ERROR("timout waiting for DE PLL unlock\n");
5451 }
5452
5453 if (frequency != 19200) {
5454 uint32_t val;
5455
5456 val = I915_READ(BXT_DE_PLL_CTL);
5457 val &= ~BXT_DE_PLL_RATIO_MASK;
5458 val |= ratio;
5459 I915_WRITE(BXT_DE_PLL_CTL, val);
5460
5461 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5462 /* Timeout 200us */
5463 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5464 DRM_ERROR("timeout waiting for DE PLL lock\n");
5465
5466 val = I915_READ(CDCLK_CTL);
5467 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5468 val |= divider;
5469 /*
5470 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5471 * enable otherwise.
5472 */
5473 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5474 if (frequency >= 500000)
5475 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5476
5477 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5478 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5479 val |= (frequency - 1000) / 500;
5480 I915_WRITE(CDCLK_CTL, val);
5481 }
5482
5483 mutex_lock(&dev_priv->rps.hw_lock);
5484 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5485 DIV_ROUND_UP(frequency, 25000));
5486 mutex_unlock(&dev_priv->rps.hw_lock);
5487
5488 if (ret) {
5489 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5490 ret, frequency);
5491 return;
5492 }
5493
5494 dev_priv->cdclk_freq = frequency;
5495 }
5496
5497 void broxton_init_cdclk(struct drm_device *dev)
5498 {
5499 struct drm_i915_private *dev_priv = dev->dev_private;
5500 uint32_t val;
5501
5502 /*
5503 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5504 * or else the reset will hang because there is no PCH to respond.
5505 * Move the handshake programming to initialization sequence.
5506 * Previously was left up to BIOS.
5507 */
5508 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5509 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5510 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5511
5512 /* Enable PG1 for cdclk */
5513 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5514
5515 /* check if cd clock is enabled */
5516 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5517 DRM_DEBUG_KMS("Display already initialized\n");
5518 return;
5519 }
5520
5521 /*
5522 * FIXME:
5523 * - The initial CDCLK needs to be read from VBT.
5524 * Need to make this change after VBT has changes for BXT.
5525 * - check if setting the max (or any) cdclk freq is really necessary
5526 * here, it belongs to modeset time
5527 */
5528 broxton_set_cdclk(dev, 624000);
5529
5530 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5531 POSTING_READ(DBUF_CTL);
5532
5533 udelay(10);
5534
5535 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5536 DRM_ERROR("DBuf power enable timeout!\n");
5537 }
5538
5539 void broxton_uninit_cdclk(struct drm_device *dev)
5540 {
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542
5543 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5544 POSTING_READ(DBUF_CTL);
5545
5546 udelay(10);
5547
5548 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5549 DRM_ERROR("DBuf power disable timeout!\n");
5550
5551 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5552 broxton_set_cdclk(dev, 19200);
5553
5554 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5555 }
5556
5557 /* returns HPLL frequency in kHz */
5558 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5559 {
5560 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5561
5562 /* Obtain SKU information */
5563 mutex_lock(&dev_priv->dpio_lock);
5564 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5565 CCK_FUSE_HPLL_FREQ_MASK;
5566 mutex_unlock(&dev_priv->dpio_lock);
5567
5568 return vco_freq[hpll_freq] * 1000;
5569 }
5570
5571 static void vlv_update_cdclk(struct drm_device *dev)
5572 {
5573 struct drm_i915_private *dev_priv = dev->dev_private;
5574
5575 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5576 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5577 dev_priv->cdclk_freq);
5578
5579 /*
5580 * Program the gmbus_freq based on the cdclk frequency.
5581 * BSpec erroneously claims we should aim for 4MHz, but
5582 * in fact 1MHz is the correct frequency.
5583 */
5584 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5585 }
5586
5587 /* Adjust CDclk dividers to allow high res or save power if possible */
5588 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5589 {
5590 struct drm_i915_private *dev_priv = dev->dev_private;
5591 u32 val, cmd;
5592
5593 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5594 != dev_priv->cdclk_freq);
5595
5596 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5597 cmd = 2;
5598 else if (cdclk == 266667)
5599 cmd = 1;
5600 else
5601 cmd = 0;
5602
5603 mutex_lock(&dev_priv->rps.hw_lock);
5604 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5605 val &= ~DSPFREQGUAR_MASK;
5606 val |= (cmd << DSPFREQGUAR_SHIFT);
5607 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5608 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5609 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5610 50)) {
5611 DRM_ERROR("timed out waiting for CDclk change\n");
5612 }
5613 mutex_unlock(&dev_priv->rps.hw_lock);
5614
5615 if (cdclk == 400000) {
5616 u32 divider;
5617
5618 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5619
5620 mutex_lock(&dev_priv->dpio_lock);
5621 /* adjust cdclk divider */
5622 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5623 val &= ~DISPLAY_FREQUENCY_VALUES;
5624 val |= divider;
5625 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5626
5627 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5628 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5629 50))
5630 DRM_ERROR("timed out waiting for CDclk change\n");
5631 mutex_unlock(&dev_priv->dpio_lock);
5632 }
5633
5634 mutex_lock(&dev_priv->dpio_lock);
5635 /* adjust self-refresh exit latency value */
5636 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5637 val &= ~0x7f;
5638
5639 /*
5640 * For high bandwidth configs, we set a higher latency in the bunit
5641 * so that the core display fetch happens in time to avoid underruns.
5642 */
5643 if (cdclk == 400000)
5644 val |= 4500 / 250; /* 4.5 usec */
5645 else
5646 val |= 3000 / 250; /* 3.0 usec */
5647 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5648 mutex_unlock(&dev_priv->dpio_lock);
5649
5650 vlv_update_cdclk(dev);
5651 }
5652
5653 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5654 {
5655 struct drm_i915_private *dev_priv = dev->dev_private;
5656 u32 val, cmd;
5657
5658 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5659 != dev_priv->cdclk_freq);
5660
5661 switch (cdclk) {
5662 case 333333:
5663 case 320000:
5664 case 266667:
5665 case 200000:
5666 break;
5667 default:
5668 MISSING_CASE(cdclk);
5669 return;
5670 }
5671
5672 /*
5673 * Specs are full of misinformation, but testing on actual
5674 * hardware has shown that we just need to write the desired
5675 * CCK divider into the Punit register.
5676 */
5677 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5678
5679 mutex_lock(&dev_priv->rps.hw_lock);
5680 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5681 val &= ~DSPFREQGUAR_MASK_CHV;
5682 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5683 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5684 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5685 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5686 50)) {
5687 DRM_ERROR("timed out waiting for CDclk change\n");
5688 }
5689 mutex_unlock(&dev_priv->rps.hw_lock);
5690
5691 vlv_update_cdclk(dev);
5692 }
5693
5694 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5695 int max_pixclk)
5696 {
5697 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5698 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5699
5700 /*
5701 * Really only a few cases to deal with, as only 4 CDclks are supported:
5702 * 200MHz
5703 * 267MHz
5704 * 320/333MHz (depends on HPLL freq)
5705 * 400MHz (VLV only)
5706 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5707 * of the lower bin and adjust if needed.
5708 *
5709 * We seem to get an unstable or solid color picture at 200MHz.
5710 * Not sure what's wrong. For now use 200MHz only when all pipes
5711 * are off.
5712 */
5713 if (!IS_CHERRYVIEW(dev_priv) &&
5714 max_pixclk > freq_320*limit/100)
5715 return 400000;
5716 else if (max_pixclk > 266667*limit/100)
5717 return freq_320;
5718 else if (max_pixclk > 0)
5719 return 266667;
5720 else
5721 return 200000;
5722 }
5723
5724 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5725 int max_pixclk)
5726 {
5727 /*
5728 * FIXME:
5729 * - remove the guardband, it's not needed on BXT
5730 * - set 19.2MHz bypass frequency if there are no active pipes
5731 */
5732 if (max_pixclk > 576000*9/10)
5733 return 624000;
5734 else if (max_pixclk > 384000*9/10)
5735 return 576000;
5736 else if (max_pixclk > 288000*9/10)
5737 return 384000;
5738 else if (max_pixclk > 144000*9/10)
5739 return 288000;
5740 else
5741 return 144000;
5742 }
5743
5744 /* Compute the max pixel clock for new configuration. Uses atomic state if
5745 * that's non-NULL, look at current state otherwise. */
5746 static int intel_mode_max_pixclk(struct drm_device *dev,
5747 struct drm_atomic_state *state)
5748 {
5749 struct intel_crtc *intel_crtc;
5750 struct intel_crtc_state *crtc_state;
5751 int max_pixclk = 0;
5752
5753 for_each_intel_crtc(dev, intel_crtc) {
5754 if (state)
5755 crtc_state =
5756 intel_atomic_get_crtc_state(state, intel_crtc);
5757 else
5758 crtc_state = intel_crtc->config;
5759 if (IS_ERR(crtc_state))
5760 return PTR_ERR(crtc_state);
5761
5762 if (!crtc_state->base.enable)
5763 continue;
5764
5765 max_pixclk = max(max_pixclk,
5766 crtc_state->base.adjusted_mode.crtc_clock);
5767 }
5768
5769 return max_pixclk;
5770 }
5771
5772 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5773 {
5774 struct drm_i915_private *dev_priv = to_i915(state->dev);
5775 struct drm_crtc *crtc;
5776 struct drm_crtc_state *crtc_state;
5777 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5778 int cdclk, i;
5779
5780 if (max_pixclk < 0)
5781 return max_pixclk;
5782
5783 if (IS_VALLEYVIEW(dev_priv))
5784 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5785 else
5786 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5787
5788 if (cdclk == dev_priv->cdclk_freq)
5789 return 0;
5790
5791 /* add all active pipes to the state */
5792 for_each_crtc(state->dev, crtc) {
5793 if (!crtc->state->enable)
5794 continue;
5795
5796 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5797 if (IS_ERR(crtc_state))
5798 return PTR_ERR(crtc_state);
5799 }
5800
5801 /* disable/enable all currently active pipes while we change cdclk */
5802 for_each_crtc_in_state(state, crtc, crtc_state, i)
5803 if (crtc_state->enable)
5804 crtc_state->mode_changed = true;
5805
5806 return 0;
5807 }
5808
5809 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5810 {
5811 unsigned int credits, default_credits;
5812
5813 if (IS_CHERRYVIEW(dev_priv))
5814 default_credits = PFI_CREDIT(12);
5815 else
5816 default_credits = PFI_CREDIT(8);
5817
5818 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5819 /* CHV suggested value is 31 or 63 */
5820 if (IS_CHERRYVIEW(dev_priv))
5821 credits = PFI_CREDIT_31;
5822 else
5823 credits = PFI_CREDIT(15);
5824 } else {
5825 credits = default_credits;
5826 }
5827
5828 /*
5829 * WA - write default credits before re-programming
5830 * FIXME: should we also set the resend bit here?
5831 */
5832 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5833 default_credits);
5834
5835 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5836 credits | PFI_CREDIT_RESEND);
5837
5838 /*
5839 * FIXME is this guaranteed to clear
5840 * immediately or should we poll for it?
5841 */
5842 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5843 }
5844
5845 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5846 {
5847 struct drm_device *dev = old_state->dev;
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5850 int req_cdclk;
5851
5852 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5853 * never fail. */
5854 if (WARN_ON(max_pixclk < 0))
5855 return;
5856
5857 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5858
5859 if (req_cdclk != dev_priv->cdclk_freq) {
5860 /*
5861 * FIXME: We can end up here with all power domains off, yet
5862 * with a CDCLK frequency other than the minimum. To account
5863 * for this take the PIPE-A power domain, which covers the HW
5864 * blocks needed for the following programming. This can be
5865 * removed once it's guaranteed that we get here either with
5866 * the minimum CDCLK set, or the required power domains
5867 * enabled.
5868 */
5869 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5870
5871 if (IS_CHERRYVIEW(dev))
5872 cherryview_set_cdclk(dev, req_cdclk);
5873 else
5874 valleyview_set_cdclk(dev, req_cdclk);
5875
5876 vlv_program_pfi_credits(dev_priv);
5877
5878 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5879 }
5880 }
5881
5882 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5883 {
5884 struct drm_device *dev = crtc->dev;
5885 struct drm_i915_private *dev_priv = to_i915(dev);
5886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5887 struct intel_encoder *encoder;
5888 int pipe = intel_crtc->pipe;
5889 bool is_dsi;
5890
5891 WARN_ON(!crtc->state->enable);
5892
5893 if (intel_crtc->active)
5894 return;
5895
5896 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5897
5898 if (!is_dsi) {
5899 if (IS_CHERRYVIEW(dev))
5900 chv_prepare_pll(intel_crtc, intel_crtc->config);
5901 else
5902 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5903 }
5904
5905 if (intel_crtc->config->has_dp_encoder)
5906 intel_dp_set_m_n(intel_crtc, M1_N1);
5907
5908 intel_set_pipe_timings(intel_crtc);
5909
5910 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5912
5913 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5914 I915_WRITE(CHV_CANVAS(pipe), 0);
5915 }
5916
5917 i9xx_set_pipeconf(intel_crtc);
5918
5919 intel_crtc->active = true;
5920
5921 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5922
5923 for_each_encoder_on_crtc(dev, crtc, encoder)
5924 if (encoder->pre_pll_enable)
5925 encoder->pre_pll_enable(encoder);
5926
5927 if (!is_dsi) {
5928 if (IS_CHERRYVIEW(dev))
5929 chv_enable_pll(intel_crtc, intel_crtc->config);
5930 else
5931 vlv_enable_pll(intel_crtc, intel_crtc->config);
5932 }
5933
5934 for_each_encoder_on_crtc(dev, crtc, encoder)
5935 if (encoder->pre_enable)
5936 encoder->pre_enable(encoder);
5937
5938 i9xx_pfit_enable(intel_crtc);
5939
5940 intel_crtc_load_lut(crtc);
5941
5942 intel_update_watermarks(crtc);
5943 intel_enable_pipe(intel_crtc);
5944
5945 assert_vblank_disabled(crtc);
5946 drm_crtc_vblank_on(crtc);
5947
5948 for_each_encoder_on_crtc(dev, crtc, encoder)
5949 encoder->enable(encoder);
5950 }
5951
5952 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5953 {
5954 struct drm_device *dev = crtc->base.dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956
5957 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5958 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5959 }
5960
5961 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5962 {
5963 struct drm_device *dev = crtc->dev;
5964 struct drm_i915_private *dev_priv = to_i915(dev);
5965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5966 struct intel_encoder *encoder;
5967 int pipe = intel_crtc->pipe;
5968
5969 WARN_ON(!crtc->state->enable);
5970
5971 if (intel_crtc->active)
5972 return;
5973
5974 i9xx_set_pll_dividers(intel_crtc);
5975
5976 if (intel_crtc->config->has_dp_encoder)
5977 intel_dp_set_m_n(intel_crtc, M1_N1);
5978
5979 intel_set_pipe_timings(intel_crtc);
5980
5981 i9xx_set_pipeconf(intel_crtc);
5982
5983 intel_crtc->active = true;
5984
5985 if (!IS_GEN2(dev))
5986 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5987
5988 for_each_encoder_on_crtc(dev, crtc, encoder)
5989 if (encoder->pre_enable)
5990 encoder->pre_enable(encoder);
5991
5992 i9xx_enable_pll(intel_crtc);
5993
5994 i9xx_pfit_enable(intel_crtc);
5995
5996 intel_crtc_load_lut(crtc);
5997
5998 intel_update_watermarks(crtc);
5999 intel_enable_pipe(intel_crtc);
6000
6001 assert_vblank_disabled(crtc);
6002 drm_crtc_vblank_on(crtc);
6003
6004 for_each_encoder_on_crtc(dev, crtc, encoder)
6005 encoder->enable(encoder);
6006 }
6007
6008 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6009 {
6010 struct drm_device *dev = crtc->base.dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012
6013 if (!crtc->config->gmch_pfit.control)
6014 return;
6015
6016 assert_pipe_disabled(dev_priv, crtc->pipe);
6017
6018 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6019 I915_READ(PFIT_CONTROL));
6020 I915_WRITE(PFIT_CONTROL, 0);
6021 }
6022
6023 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6024 {
6025 struct drm_device *dev = crtc->dev;
6026 struct drm_i915_private *dev_priv = dev->dev_private;
6027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6028 struct intel_encoder *encoder;
6029 int pipe = intel_crtc->pipe;
6030
6031 if (!intel_crtc->active)
6032 return;
6033
6034 /*
6035 * On gen2 planes are double buffered but the pipe isn't, so we must
6036 * wait for planes to fully turn off before disabling the pipe.
6037 * We also need to wait on all gmch platforms because of the
6038 * self-refresh mode constraint explained above.
6039 */
6040 intel_wait_for_vblank(dev, pipe);
6041
6042 for_each_encoder_on_crtc(dev, crtc, encoder)
6043 encoder->disable(encoder);
6044
6045 drm_crtc_vblank_off(crtc);
6046 assert_vblank_disabled(crtc);
6047
6048 intel_disable_pipe(intel_crtc);
6049
6050 i9xx_pfit_disable(intel_crtc);
6051
6052 for_each_encoder_on_crtc(dev, crtc, encoder)
6053 if (encoder->post_disable)
6054 encoder->post_disable(encoder);
6055
6056 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6057 if (IS_CHERRYVIEW(dev))
6058 chv_disable_pll(dev_priv, pipe);
6059 else if (IS_VALLEYVIEW(dev))
6060 vlv_disable_pll(dev_priv, pipe);
6061 else
6062 i9xx_disable_pll(intel_crtc);
6063 }
6064
6065 if (!IS_GEN2(dev))
6066 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6067
6068 intel_crtc->active = false;
6069 intel_update_watermarks(crtc);
6070
6071 mutex_lock(&dev->struct_mutex);
6072 intel_fbc_update(dev);
6073 mutex_unlock(&dev->struct_mutex);
6074 }
6075
6076 static void i9xx_crtc_off(struct drm_crtc *crtc)
6077 {
6078 }
6079
6080 /* Master function to enable/disable CRTC and corresponding power wells */
6081 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6082 {
6083 struct drm_device *dev = crtc->dev;
6084 struct drm_i915_private *dev_priv = dev->dev_private;
6085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6086 enum intel_display_power_domain domain;
6087 unsigned long domains;
6088
6089 if (enable) {
6090 if (!intel_crtc->active) {
6091 domains = get_crtc_power_domains(crtc);
6092 for_each_power_domain(domain, domains)
6093 intel_display_power_get(dev_priv, domain);
6094 intel_crtc->enabled_power_domains = domains;
6095
6096 dev_priv->display.crtc_enable(crtc);
6097 intel_crtc_enable_planes(crtc);
6098 }
6099 } else {
6100 if (intel_crtc->active) {
6101 intel_crtc_disable_planes(crtc);
6102 dev_priv->display.crtc_disable(crtc);
6103
6104 domains = intel_crtc->enabled_power_domains;
6105 for_each_power_domain(domain, domains)
6106 intel_display_power_put(dev_priv, domain);
6107 intel_crtc->enabled_power_domains = 0;
6108 }
6109 }
6110 }
6111
6112 /**
6113 * Sets the power management mode of the pipe and plane.
6114 */
6115 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6116 {
6117 struct drm_device *dev = crtc->dev;
6118 struct intel_encoder *intel_encoder;
6119 bool enable = false;
6120
6121 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6122 enable |= intel_encoder->connectors_active;
6123
6124 intel_crtc_control(crtc, enable);
6125
6126 crtc->state->active = enable;
6127 }
6128
6129 static void intel_crtc_disable(struct drm_crtc *crtc)
6130 {
6131 struct drm_device *dev = crtc->dev;
6132 struct drm_connector *connector;
6133 struct drm_i915_private *dev_priv = dev->dev_private;
6134
6135 /* crtc should still be enabled when we disable it. */
6136 WARN_ON(!crtc->state->enable);
6137
6138 intel_crtc_disable_planes(crtc);
6139 dev_priv->display.crtc_disable(crtc);
6140 dev_priv->display.off(crtc);
6141
6142 drm_plane_helper_disable(crtc->primary);
6143
6144 /* Update computed state. */
6145 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6146 if (!connector->encoder || !connector->encoder->crtc)
6147 continue;
6148
6149 if (connector->encoder->crtc != crtc)
6150 continue;
6151
6152 connector->dpms = DRM_MODE_DPMS_OFF;
6153 to_intel_encoder(connector->encoder)->connectors_active = false;
6154 }
6155 }
6156
6157 void intel_encoder_destroy(struct drm_encoder *encoder)
6158 {
6159 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6160
6161 drm_encoder_cleanup(encoder);
6162 kfree(intel_encoder);
6163 }
6164
6165 /* Simple dpms helper for encoders with just one connector, no cloning and only
6166 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6167 * state of the entire output pipe. */
6168 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6169 {
6170 if (mode == DRM_MODE_DPMS_ON) {
6171 encoder->connectors_active = true;
6172
6173 intel_crtc_update_dpms(encoder->base.crtc);
6174 } else {
6175 encoder->connectors_active = false;
6176
6177 intel_crtc_update_dpms(encoder->base.crtc);
6178 }
6179 }
6180
6181 /* Cross check the actual hw state with our own modeset state tracking (and it's
6182 * internal consistency). */
6183 static void intel_connector_check_state(struct intel_connector *connector)
6184 {
6185 if (connector->get_hw_state(connector)) {
6186 struct intel_encoder *encoder = connector->encoder;
6187 struct drm_crtc *crtc;
6188 bool encoder_enabled;
6189 enum pipe pipe;
6190
6191 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6192 connector->base.base.id,
6193 connector->base.name);
6194
6195 /* there is no real hw state for MST connectors */
6196 if (connector->mst_port)
6197 return;
6198
6199 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6200 "wrong connector dpms state\n");
6201 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6202 "active connector not linked to encoder\n");
6203
6204 if (encoder) {
6205 I915_STATE_WARN(!encoder->connectors_active,
6206 "encoder->connectors_active not set\n");
6207
6208 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6209 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6210 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6211 return;
6212
6213 crtc = encoder->base.crtc;
6214
6215 I915_STATE_WARN(!crtc->state->enable,
6216 "crtc not enabled\n");
6217 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6218 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6219 "encoder active on the wrong pipe\n");
6220 }
6221 }
6222 }
6223
6224 int intel_connector_init(struct intel_connector *connector)
6225 {
6226 struct drm_connector_state *connector_state;
6227
6228 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6229 if (!connector_state)
6230 return -ENOMEM;
6231
6232 connector->base.state = connector_state;
6233 return 0;
6234 }
6235
6236 struct intel_connector *intel_connector_alloc(void)
6237 {
6238 struct intel_connector *connector;
6239
6240 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6241 if (!connector)
6242 return NULL;
6243
6244 if (intel_connector_init(connector) < 0) {
6245 kfree(connector);
6246 return NULL;
6247 }
6248
6249 return connector;
6250 }
6251
6252 /* Even simpler default implementation, if there's really no special case to
6253 * consider. */
6254 void intel_connector_dpms(struct drm_connector *connector, int mode)
6255 {
6256 /* All the simple cases only support two dpms states. */
6257 if (mode != DRM_MODE_DPMS_ON)
6258 mode = DRM_MODE_DPMS_OFF;
6259
6260 if (mode == connector->dpms)
6261 return;
6262
6263 connector->dpms = mode;
6264
6265 /* Only need to change hw state when actually enabled */
6266 if (connector->encoder)
6267 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6268
6269 intel_modeset_check_state(connector->dev);
6270 }
6271
6272 /* Simple connector->get_hw_state implementation for encoders that support only
6273 * one connector and no cloning and hence the encoder state determines the state
6274 * of the connector. */
6275 bool intel_connector_get_hw_state(struct intel_connector *connector)
6276 {
6277 enum pipe pipe = 0;
6278 struct intel_encoder *encoder = connector->encoder;
6279
6280 return encoder->get_hw_state(encoder, &pipe);
6281 }
6282
6283 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6284 {
6285 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6286 return crtc_state->fdi_lanes;
6287
6288 return 0;
6289 }
6290
6291 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6292 struct intel_crtc_state *pipe_config)
6293 {
6294 struct drm_atomic_state *state = pipe_config->base.state;
6295 struct intel_crtc *other_crtc;
6296 struct intel_crtc_state *other_crtc_state;
6297
6298 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6299 pipe_name(pipe), pipe_config->fdi_lanes);
6300 if (pipe_config->fdi_lanes > 4) {
6301 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6302 pipe_name(pipe), pipe_config->fdi_lanes);
6303 return -EINVAL;
6304 }
6305
6306 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6307 if (pipe_config->fdi_lanes > 2) {
6308 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6309 pipe_config->fdi_lanes);
6310 return -EINVAL;
6311 } else {
6312 return 0;
6313 }
6314 }
6315
6316 if (INTEL_INFO(dev)->num_pipes == 2)
6317 return 0;
6318
6319 /* Ivybridge 3 pipe is really complicated */
6320 switch (pipe) {
6321 case PIPE_A:
6322 return 0;
6323 case PIPE_B:
6324 if (pipe_config->fdi_lanes <= 2)
6325 return 0;
6326
6327 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6328 other_crtc_state =
6329 intel_atomic_get_crtc_state(state, other_crtc);
6330 if (IS_ERR(other_crtc_state))
6331 return PTR_ERR(other_crtc_state);
6332
6333 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6334 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6335 pipe_name(pipe), pipe_config->fdi_lanes);
6336 return -EINVAL;
6337 }
6338 return 0;
6339 case PIPE_C:
6340 if (pipe_config->fdi_lanes > 2) {
6341 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6342 pipe_name(pipe), pipe_config->fdi_lanes);
6343 return -EINVAL;
6344 }
6345
6346 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6347 other_crtc_state =
6348 intel_atomic_get_crtc_state(state, other_crtc);
6349 if (IS_ERR(other_crtc_state))
6350 return PTR_ERR(other_crtc_state);
6351
6352 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6353 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6354 return -EINVAL;
6355 }
6356 return 0;
6357 default:
6358 BUG();
6359 }
6360 }
6361
6362 #define RETRY 1
6363 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6364 struct intel_crtc_state *pipe_config)
6365 {
6366 struct drm_device *dev = intel_crtc->base.dev;
6367 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6368 int lane, link_bw, fdi_dotclock, ret;
6369 bool needs_recompute = false;
6370
6371 retry:
6372 /* FDI is a binary signal running at ~2.7GHz, encoding
6373 * each output octet as 10 bits. The actual frequency
6374 * is stored as a divider into a 100MHz clock, and the
6375 * mode pixel clock is stored in units of 1KHz.
6376 * Hence the bw of each lane in terms of the mode signal
6377 * is:
6378 */
6379 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6380
6381 fdi_dotclock = adjusted_mode->crtc_clock;
6382
6383 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6384 pipe_config->pipe_bpp);
6385
6386 pipe_config->fdi_lanes = lane;
6387
6388 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6389 link_bw, &pipe_config->fdi_m_n);
6390
6391 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6392 intel_crtc->pipe, pipe_config);
6393 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6394 pipe_config->pipe_bpp -= 2*3;
6395 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6396 pipe_config->pipe_bpp);
6397 needs_recompute = true;
6398 pipe_config->bw_constrained = true;
6399
6400 goto retry;
6401 }
6402
6403 if (needs_recompute)
6404 return RETRY;
6405
6406 return ret;
6407 }
6408
6409 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6410 struct intel_crtc_state *pipe_config)
6411 {
6412 pipe_config->ips_enabled = i915.enable_ips &&
6413 hsw_crtc_supports_ips(crtc) &&
6414 pipe_config->pipe_bpp <= 24;
6415 }
6416
6417 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6418 struct intel_crtc_state *pipe_config)
6419 {
6420 struct drm_device *dev = crtc->base.dev;
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6423 int ret;
6424
6425 /* FIXME should check pixel clock limits on all platforms */
6426 if (INTEL_INFO(dev)->gen < 4) {
6427 int clock_limit =
6428 dev_priv->display.get_display_clock_speed(dev);
6429
6430 /*
6431 * Enable pixel doubling when the dot clock
6432 * is > 90% of the (display) core speed.
6433 *
6434 * GDG double wide on either pipe,
6435 * otherwise pipe A only.
6436 */
6437 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6438 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6439 clock_limit *= 2;
6440 pipe_config->double_wide = true;
6441 }
6442
6443 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6444 return -EINVAL;
6445 }
6446
6447 /*
6448 * Pipe horizontal size must be even in:
6449 * - DVO ganged mode
6450 * - LVDS dual channel mode
6451 * - Double wide pipe
6452 */
6453 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6454 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6455 pipe_config->pipe_src_w &= ~1;
6456
6457 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6458 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6459 */
6460 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6461 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6462 return -EINVAL;
6463
6464 if (HAS_IPS(dev))
6465 hsw_compute_ips_config(crtc, pipe_config);
6466
6467 if (pipe_config->has_pch_encoder)
6468 return ironlake_fdi_compute_config(crtc, pipe_config);
6469
6470 /* FIXME: remove below call once atomic mode set is place and all crtc
6471 * related checks called from atomic_crtc_check function */
6472 ret = 0;
6473 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6474 crtc, pipe_config->base.state);
6475 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6476
6477 return ret;
6478 }
6479
6480 static int skylake_get_display_clock_speed(struct drm_device *dev)
6481 {
6482 struct drm_i915_private *dev_priv = to_i915(dev);
6483 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6484 uint32_t cdctl = I915_READ(CDCLK_CTL);
6485 uint32_t linkrate;
6486
6487 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6488 WARN(1, "LCPLL1 not enabled\n");
6489 return 24000; /* 24MHz is the cd freq with NSSC ref */
6490 }
6491
6492 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6493 return 540000;
6494
6495 linkrate = (I915_READ(DPLL_CTRL1) &
6496 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6497
6498 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6499 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6500 /* vco 8640 */
6501 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6502 case CDCLK_FREQ_450_432:
6503 return 432000;
6504 case CDCLK_FREQ_337_308:
6505 return 308570;
6506 case CDCLK_FREQ_675_617:
6507 return 617140;
6508 default:
6509 WARN(1, "Unknown cd freq selection\n");
6510 }
6511 } else {
6512 /* vco 8100 */
6513 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6514 case CDCLK_FREQ_450_432:
6515 return 450000;
6516 case CDCLK_FREQ_337_308:
6517 return 337500;
6518 case CDCLK_FREQ_675_617:
6519 return 675000;
6520 default:
6521 WARN(1, "Unknown cd freq selection\n");
6522 }
6523 }
6524
6525 /* error case, do as if DPLL0 isn't enabled */
6526 return 24000;
6527 }
6528
6529 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6530 {
6531 struct drm_i915_private *dev_priv = dev->dev_private;
6532 uint32_t lcpll = I915_READ(LCPLL_CTL);
6533 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6534
6535 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6536 return 800000;
6537 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6538 return 450000;
6539 else if (freq == LCPLL_CLK_FREQ_450)
6540 return 450000;
6541 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6542 return 540000;
6543 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6544 return 337500;
6545 else
6546 return 675000;
6547 }
6548
6549 static int haswell_get_display_clock_speed(struct drm_device *dev)
6550 {
6551 struct drm_i915_private *dev_priv = dev->dev_private;
6552 uint32_t lcpll = I915_READ(LCPLL_CTL);
6553 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6554
6555 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6556 return 800000;
6557 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6558 return 450000;
6559 else if (freq == LCPLL_CLK_FREQ_450)
6560 return 450000;
6561 else if (IS_HSW_ULT(dev))
6562 return 337500;
6563 else
6564 return 540000;
6565 }
6566
6567 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6568 {
6569 struct drm_i915_private *dev_priv = dev->dev_private;
6570 u32 val;
6571 int divider;
6572
6573 if (dev_priv->hpll_freq == 0)
6574 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6575
6576 mutex_lock(&dev_priv->dpio_lock);
6577 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6578 mutex_unlock(&dev_priv->dpio_lock);
6579
6580 divider = val & DISPLAY_FREQUENCY_VALUES;
6581
6582 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6583 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6584 "cdclk change in progress\n");
6585
6586 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6587 }
6588
6589 static int ilk_get_display_clock_speed(struct drm_device *dev)
6590 {
6591 return 450000;
6592 }
6593
6594 static int i945_get_display_clock_speed(struct drm_device *dev)
6595 {
6596 return 400000;
6597 }
6598
6599 static int i915_get_display_clock_speed(struct drm_device *dev)
6600 {
6601 return 333333;
6602 }
6603
6604 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6605 {
6606 return 200000;
6607 }
6608
6609 static int pnv_get_display_clock_speed(struct drm_device *dev)
6610 {
6611 u16 gcfgc = 0;
6612
6613 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6614
6615 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6616 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6617 return 266667;
6618 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6619 return 333333;
6620 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6621 return 444444;
6622 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6623 return 200000;
6624 default:
6625 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6626 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6627 return 133333;
6628 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6629 return 166667;
6630 }
6631 }
6632
6633 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6634 {
6635 u16 gcfgc = 0;
6636
6637 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6638
6639 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6640 return 133333;
6641 else {
6642 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6643 case GC_DISPLAY_CLOCK_333_MHZ:
6644 return 333333;
6645 default:
6646 case GC_DISPLAY_CLOCK_190_200_MHZ:
6647 return 190000;
6648 }
6649 }
6650 }
6651
6652 static int i865_get_display_clock_speed(struct drm_device *dev)
6653 {
6654 return 266667;
6655 }
6656
6657 static int i855_get_display_clock_speed(struct drm_device *dev)
6658 {
6659 u16 hpllcc = 0;
6660 /* Assume that the hardware is in the high speed state. This
6661 * should be the default.
6662 */
6663 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6664 case GC_CLOCK_133_200:
6665 case GC_CLOCK_100_200:
6666 return 200000;
6667 case GC_CLOCK_166_250:
6668 return 250000;
6669 case GC_CLOCK_100_133:
6670 return 133333;
6671 }
6672
6673 /* Shouldn't happen */
6674 return 0;
6675 }
6676
6677 static int i830_get_display_clock_speed(struct drm_device *dev)
6678 {
6679 return 133333;
6680 }
6681
6682 static void
6683 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6684 {
6685 while (*num > DATA_LINK_M_N_MASK ||
6686 *den > DATA_LINK_M_N_MASK) {
6687 *num >>= 1;
6688 *den >>= 1;
6689 }
6690 }
6691
6692 static void compute_m_n(unsigned int m, unsigned int n,
6693 uint32_t *ret_m, uint32_t *ret_n)
6694 {
6695 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6696 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6697 intel_reduce_m_n_ratio(ret_m, ret_n);
6698 }
6699
6700 void
6701 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6702 int pixel_clock, int link_clock,
6703 struct intel_link_m_n *m_n)
6704 {
6705 m_n->tu = 64;
6706
6707 compute_m_n(bits_per_pixel * pixel_clock,
6708 link_clock * nlanes * 8,
6709 &m_n->gmch_m, &m_n->gmch_n);
6710
6711 compute_m_n(pixel_clock, link_clock,
6712 &m_n->link_m, &m_n->link_n);
6713 }
6714
6715 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6716 {
6717 if (i915.panel_use_ssc >= 0)
6718 return i915.panel_use_ssc != 0;
6719 return dev_priv->vbt.lvds_use_ssc
6720 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6721 }
6722
6723 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6724 int num_connectors)
6725 {
6726 struct drm_device *dev = crtc_state->base.crtc->dev;
6727 struct drm_i915_private *dev_priv = dev->dev_private;
6728 int refclk;
6729
6730 WARN_ON(!crtc_state->base.state);
6731
6732 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6733 refclk = 100000;
6734 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6735 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6736 refclk = dev_priv->vbt.lvds_ssc_freq;
6737 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6738 } else if (!IS_GEN2(dev)) {
6739 refclk = 96000;
6740 } else {
6741 refclk = 48000;
6742 }
6743
6744 return refclk;
6745 }
6746
6747 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6748 {
6749 return (1 << dpll->n) << 16 | dpll->m2;
6750 }
6751
6752 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6753 {
6754 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6755 }
6756
6757 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6758 struct intel_crtc_state *crtc_state,
6759 intel_clock_t *reduced_clock)
6760 {
6761 struct drm_device *dev = crtc->base.dev;
6762 u32 fp, fp2 = 0;
6763
6764 if (IS_PINEVIEW(dev)) {
6765 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6766 if (reduced_clock)
6767 fp2 = pnv_dpll_compute_fp(reduced_clock);
6768 } else {
6769 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6770 if (reduced_clock)
6771 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6772 }
6773
6774 crtc_state->dpll_hw_state.fp0 = fp;
6775
6776 crtc->lowfreq_avail = false;
6777 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6778 reduced_clock) {
6779 crtc_state->dpll_hw_state.fp1 = fp2;
6780 crtc->lowfreq_avail = true;
6781 } else {
6782 crtc_state->dpll_hw_state.fp1 = fp;
6783 }
6784 }
6785
6786 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6787 pipe)
6788 {
6789 u32 reg_val;
6790
6791 /*
6792 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6793 * and set it to a reasonable value instead.
6794 */
6795 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6796 reg_val &= 0xffffff00;
6797 reg_val |= 0x00000030;
6798 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6799
6800 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6801 reg_val &= 0x8cffffff;
6802 reg_val = 0x8c000000;
6803 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6804
6805 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6806 reg_val &= 0xffffff00;
6807 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6808
6809 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6810 reg_val &= 0x00ffffff;
6811 reg_val |= 0xb0000000;
6812 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6813 }
6814
6815 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6816 struct intel_link_m_n *m_n)
6817 {
6818 struct drm_device *dev = crtc->base.dev;
6819 struct drm_i915_private *dev_priv = dev->dev_private;
6820 int pipe = crtc->pipe;
6821
6822 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6823 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6824 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6825 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6826 }
6827
6828 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6829 struct intel_link_m_n *m_n,
6830 struct intel_link_m_n *m2_n2)
6831 {
6832 struct drm_device *dev = crtc->base.dev;
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6834 int pipe = crtc->pipe;
6835 enum transcoder transcoder = crtc->config->cpu_transcoder;
6836
6837 if (INTEL_INFO(dev)->gen >= 5) {
6838 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6839 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6840 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6841 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6842 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6843 * for gen < 8) and if DRRS is supported (to make sure the
6844 * registers are not unnecessarily accessed).
6845 */
6846 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6847 crtc->config->has_drrs) {
6848 I915_WRITE(PIPE_DATA_M2(transcoder),
6849 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6850 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6851 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6852 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6853 }
6854 } else {
6855 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6856 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6857 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6858 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6859 }
6860 }
6861
6862 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6863 {
6864 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6865
6866 if (m_n == M1_N1) {
6867 dp_m_n = &crtc->config->dp_m_n;
6868 dp_m2_n2 = &crtc->config->dp_m2_n2;
6869 } else if (m_n == M2_N2) {
6870
6871 /*
6872 * M2_N2 registers are not supported. Hence m2_n2 divider value
6873 * needs to be programmed into M1_N1.
6874 */
6875 dp_m_n = &crtc->config->dp_m2_n2;
6876 } else {
6877 DRM_ERROR("Unsupported divider value\n");
6878 return;
6879 }
6880
6881 if (crtc->config->has_pch_encoder)
6882 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6883 else
6884 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6885 }
6886
6887 static void vlv_update_pll(struct intel_crtc *crtc,
6888 struct intel_crtc_state *pipe_config)
6889 {
6890 u32 dpll, dpll_md;
6891
6892 /*
6893 * Enable DPIO clock input. We should never disable the reference
6894 * clock for pipe B, since VGA hotplug / manual detection depends
6895 * on it.
6896 */
6897 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6898 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6899 /* We should never disable this, set it here for state tracking */
6900 if (crtc->pipe == PIPE_B)
6901 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6902 dpll |= DPLL_VCO_ENABLE;
6903 pipe_config->dpll_hw_state.dpll = dpll;
6904
6905 dpll_md = (pipe_config->pixel_multiplier - 1)
6906 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6907 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6908 }
6909
6910 static void vlv_prepare_pll(struct intel_crtc *crtc,
6911 const struct intel_crtc_state *pipe_config)
6912 {
6913 struct drm_device *dev = crtc->base.dev;
6914 struct drm_i915_private *dev_priv = dev->dev_private;
6915 int pipe = crtc->pipe;
6916 u32 mdiv;
6917 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6918 u32 coreclk, reg_val;
6919
6920 mutex_lock(&dev_priv->dpio_lock);
6921
6922 bestn = pipe_config->dpll.n;
6923 bestm1 = pipe_config->dpll.m1;
6924 bestm2 = pipe_config->dpll.m2;
6925 bestp1 = pipe_config->dpll.p1;
6926 bestp2 = pipe_config->dpll.p2;
6927
6928 /* See eDP HDMI DPIO driver vbios notes doc */
6929
6930 /* PLL B needs special handling */
6931 if (pipe == PIPE_B)
6932 vlv_pllb_recal_opamp(dev_priv, pipe);
6933
6934 /* Set up Tx target for periodic Rcomp update */
6935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6936
6937 /* Disable target IRef on PLL */
6938 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6939 reg_val &= 0x00ffffff;
6940 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6941
6942 /* Disable fast lock */
6943 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6944
6945 /* Set idtafcrecal before PLL is enabled */
6946 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6947 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6948 mdiv |= ((bestn << DPIO_N_SHIFT));
6949 mdiv |= (1 << DPIO_K_SHIFT);
6950
6951 /*
6952 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6953 * but we don't support that).
6954 * Note: don't use the DAC post divider as it seems unstable.
6955 */
6956 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6957 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6958
6959 mdiv |= DPIO_ENABLE_CALIBRATION;
6960 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6961
6962 /* Set HBR and RBR LPF coefficients */
6963 if (pipe_config->port_clock == 162000 ||
6964 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6965 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6967 0x009f0003);
6968 else
6969 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6970 0x00d0000f);
6971
6972 if (pipe_config->has_dp_encoder) {
6973 /* Use SSC source */
6974 if (pipe == PIPE_A)
6975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6976 0x0df40000);
6977 else
6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6979 0x0df70000);
6980 } else { /* HDMI or VGA */
6981 /* Use bend source */
6982 if (pipe == PIPE_A)
6983 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6984 0x0df70000);
6985 else
6986 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6987 0x0df40000);
6988 }
6989
6990 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6991 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6992 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6993 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6994 coreclk |= 0x01000000;
6995 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6996
6997 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6998 mutex_unlock(&dev_priv->dpio_lock);
6999 }
7000
7001 static void chv_update_pll(struct intel_crtc *crtc,
7002 struct intel_crtc_state *pipe_config)
7003 {
7004 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7005 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7006 DPLL_VCO_ENABLE;
7007 if (crtc->pipe != PIPE_A)
7008 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7009
7010 pipe_config->dpll_hw_state.dpll_md =
7011 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7012 }
7013
7014 static void chv_prepare_pll(struct intel_crtc *crtc,
7015 const struct intel_crtc_state *pipe_config)
7016 {
7017 struct drm_device *dev = crtc->base.dev;
7018 struct drm_i915_private *dev_priv = dev->dev_private;
7019 int pipe = crtc->pipe;
7020 int dpll_reg = DPLL(crtc->pipe);
7021 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7022 u32 loopfilter, tribuf_calcntr;
7023 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7024 u32 dpio_val;
7025 int vco;
7026
7027 bestn = pipe_config->dpll.n;
7028 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7029 bestm1 = pipe_config->dpll.m1;
7030 bestm2 = pipe_config->dpll.m2 >> 22;
7031 bestp1 = pipe_config->dpll.p1;
7032 bestp2 = pipe_config->dpll.p2;
7033 vco = pipe_config->dpll.vco;
7034 dpio_val = 0;
7035 loopfilter = 0;
7036
7037 /*
7038 * Enable Refclk and SSC
7039 */
7040 I915_WRITE(dpll_reg,
7041 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7042
7043 mutex_lock(&dev_priv->dpio_lock);
7044
7045 /* p1 and p2 divider */
7046 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7047 5 << DPIO_CHV_S1_DIV_SHIFT |
7048 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7049 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7050 1 << DPIO_CHV_K_DIV_SHIFT);
7051
7052 /* Feedback post-divider - m2 */
7053 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7054
7055 /* Feedback refclk divider - n and m1 */
7056 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7057 DPIO_CHV_M1_DIV_BY_2 |
7058 1 << DPIO_CHV_N_DIV_SHIFT);
7059
7060 /* M2 fraction division */
7061 if (bestm2_frac)
7062 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7063
7064 /* M2 fraction division enable */
7065 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7066 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7067 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7068 if (bestm2_frac)
7069 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7070 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7071
7072 /* Program digital lock detect threshold */
7073 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7074 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7075 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7076 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7077 if (!bestm2_frac)
7078 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7079 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7080
7081 /* Loop filter */
7082 if (vco == 5400000) {
7083 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7084 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7085 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7086 tribuf_calcntr = 0x9;
7087 } else if (vco <= 6200000) {
7088 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7089 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7090 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7091 tribuf_calcntr = 0x9;
7092 } else if (vco <= 6480000) {
7093 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7094 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7095 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7096 tribuf_calcntr = 0x8;
7097 } else {
7098 /* Not supported. Apply the same limits as in the max case */
7099 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7100 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7101 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7102 tribuf_calcntr = 0;
7103 }
7104 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7105
7106 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7107 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7108 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7109 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7110
7111 /* AFC Recal */
7112 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7113 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7114 DPIO_AFC_RECAL);
7115
7116 mutex_unlock(&dev_priv->dpio_lock);
7117 }
7118
7119 /**
7120 * vlv_force_pll_on - forcibly enable just the PLL
7121 * @dev_priv: i915 private structure
7122 * @pipe: pipe PLL to enable
7123 * @dpll: PLL configuration
7124 *
7125 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7126 * in cases where we need the PLL enabled even when @pipe is not going to
7127 * be enabled.
7128 */
7129 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7130 const struct dpll *dpll)
7131 {
7132 struct intel_crtc *crtc =
7133 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7134 struct intel_crtc_state pipe_config = {
7135 .base.crtc = &crtc->base,
7136 .pixel_multiplier = 1,
7137 .dpll = *dpll,
7138 };
7139
7140 if (IS_CHERRYVIEW(dev)) {
7141 chv_update_pll(crtc, &pipe_config);
7142 chv_prepare_pll(crtc, &pipe_config);
7143 chv_enable_pll(crtc, &pipe_config);
7144 } else {
7145 vlv_update_pll(crtc, &pipe_config);
7146 vlv_prepare_pll(crtc, &pipe_config);
7147 vlv_enable_pll(crtc, &pipe_config);
7148 }
7149 }
7150
7151 /**
7152 * vlv_force_pll_off - forcibly disable just the PLL
7153 * @dev_priv: i915 private structure
7154 * @pipe: pipe PLL to disable
7155 *
7156 * Disable the PLL for @pipe. To be used in cases where we need
7157 * the PLL enabled even when @pipe is not going to be enabled.
7158 */
7159 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7160 {
7161 if (IS_CHERRYVIEW(dev))
7162 chv_disable_pll(to_i915(dev), pipe);
7163 else
7164 vlv_disable_pll(to_i915(dev), pipe);
7165 }
7166
7167 static void i9xx_update_pll(struct intel_crtc *crtc,
7168 struct intel_crtc_state *crtc_state,
7169 intel_clock_t *reduced_clock,
7170 int num_connectors)
7171 {
7172 struct drm_device *dev = crtc->base.dev;
7173 struct drm_i915_private *dev_priv = dev->dev_private;
7174 u32 dpll;
7175 bool is_sdvo;
7176 struct dpll *clock = &crtc_state->dpll;
7177
7178 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7179
7180 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7181 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7182
7183 dpll = DPLL_VGA_MODE_DIS;
7184
7185 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7186 dpll |= DPLLB_MODE_LVDS;
7187 else
7188 dpll |= DPLLB_MODE_DAC_SERIAL;
7189
7190 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7191 dpll |= (crtc_state->pixel_multiplier - 1)
7192 << SDVO_MULTIPLIER_SHIFT_HIRES;
7193 }
7194
7195 if (is_sdvo)
7196 dpll |= DPLL_SDVO_HIGH_SPEED;
7197
7198 if (crtc_state->has_dp_encoder)
7199 dpll |= DPLL_SDVO_HIGH_SPEED;
7200
7201 /* compute bitmask from p1 value */
7202 if (IS_PINEVIEW(dev))
7203 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7204 else {
7205 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7206 if (IS_G4X(dev) && reduced_clock)
7207 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7208 }
7209 switch (clock->p2) {
7210 case 5:
7211 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7212 break;
7213 case 7:
7214 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7215 break;
7216 case 10:
7217 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7218 break;
7219 case 14:
7220 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7221 break;
7222 }
7223 if (INTEL_INFO(dev)->gen >= 4)
7224 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7225
7226 if (crtc_state->sdvo_tv_clock)
7227 dpll |= PLL_REF_INPUT_TVCLKINBC;
7228 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7229 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7230 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7231 else
7232 dpll |= PLL_REF_INPUT_DREFCLK;
7233
7234 dpll |= DPLL_VCO_ENABLE;
7235 crtc_state->dpll_hw_state.dpll = dpll;
7236
7237 if (INTEL_INFO(dev)->gen >= 4) {
7238 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7239 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7240 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7241 }
7242 }
7243
7244 static void i8xx_update_pll(struct intel_crtc *crtc,
7245 struct intel_crtc_state *crtc_state,
7246 intel_clock_t *reduced_clock,
7247 int num_connectors)
7248 {
7249 struct drm_device *dev = crtc->base.dev;
7250 struct drm_i915_private *dev_priv = dev->dev_private;
7251 u32 dpll;
7252 struct dpll *clock = &crtc_state->dpll;
7253
7254 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7255
7256 dpll = DPLL_VGA_MODE_DIS;
7257
7258 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7259 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7260 } else {
7261 if (clock->p1 == 2)
7262 dpll |= PLL_P1_DIVIDE_BY_TWO;
7263 else
7264 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7265 if (clock->p2 == 4)
7266 dpll |= PLL_P2_DIVIDE_BY_4;
7267 }
7268
7269 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7270 dpll |= DPLL_DVO_2X_MODE;
7271
7272 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7273 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7274 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7275 else
7276 dpll |= PLL_REF_INPUT_DREFCLK;
7277
7278 dpll |= DPLL_VCO_ENABLE;
7279 crtc_state->dpll_hw_state.dpll = dpll;
7280 }
7281
7282 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7283 {
7284 struct drm_device *dev = intel_crtc->base.dev;
7285 struct drm_i915_private *dev_priv = dev->dev_private;
7286 enum pipe pipe = intel_crtc->pipe;
7287 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7288 struct drm_display_mode *adjusted_mode =
7289 &intel_crtc->config->base.adjusted_mode;
7290 uint32_t crtc_vtotal, crtc_vblank_end;
7291 int vsyncshift = 0;
7292
7293 /* We need to be careful not to changed the adjusted mode, for otherwise
7294 * the hw state checker will get angry at the mismatch. */
7295 crtc_vtotal = adjusted_mode->crtc_vtotal;
7296 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7297
7298 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7299 /* the chip adds 2 halflines automatically */
7300 crtc_vtotal -= 1;
7301 crtc_vblank_end -= 1;
7302
7303 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7304 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7305 else
7306 vsyncshift = adjusted_mode->crtc_hsync_start -
7307 adjusted_mode->crtc_htotal / 2;
7308 if (vsyncshift < 0)
7309 vsyncshift += adjusted_mode->crtc_htotal;
7310 }
7311
7312 if (INTEL_INFO(dev)->gen > 3)
7313 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7314
7315 I915_WRITE(HTOTAL(cpu_transcoder),
7316 (adjusted_mode->crtc_hdisplay - 1) |
7317 ((adjusted_mode->crtc_htotal - 1) << 16));
7318 I915_WRITE(HBLANK(cpu_transcoder),
7319 (adjusted_mode->crtc_hblank_start - 1) |
7320 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7321 I915_WRITE(HSYNC(cpu_transcoder),
7322 (adjusted_mode->crtc_hsync_start - 1) |
7323 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7324
7325 I915_WRITE(VTOTAL(cpu_transcoder),
7326 (adjusted_mode->crtc_vdisplay - 1) |
7327 ((crtc_vtotal - 1) << 16));
7328 I915_WRITE(VBLANK(cpu_transcoder),
7329 (adjusted_mode->crtc_vblank_start - 1) |
7330 ((crtc_vblank_end - 1) << 16));
7331 I915_WRITE(VSYNC(cpu_transcoder),
7332 (adjusted_mode->crtc_vsync_start - 1) |
7333 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7334
7335 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7336 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7337 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7338 * bits. */
7339 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7340 (pipe == PIPE_B || pipe == PIPE_C))
7341 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7342
7343 /* pipesrc controls the size that is scaled from, which should
7344 * always be the user's requested size.
7345 */
7346 I915_WRITE(PIPESRC(pipe),
7347 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7348 (intel_crtc->config->pipe_src_h - 1));
7349 }
7350
7351 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7352 struct intel_crtc_state *pipe_config)
7353 {
7354 struct drm_device *dev = crtc->base.dev;
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7357 uint32_t tmp;
7358
7359 tmp = I915_READ(HTOTAL(cpu_transcoder));
7360 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7361 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7362 tmp = I915_READ(HBLANK(cpu_transcoder));
7363 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7364 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7365 tmp = I915_READ(HSYNC(cpu_transcoder));
7366 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7367 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7368
7369 tmp = I915_READ(VTOTAL(cpu_transcoder));
7370 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7371 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7372 tmp = I915_READ(VBLANK(cpu_transcoder));
7373 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7374 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7375 tmp = I915_READ(VSYNC(cpu_transcoder));
7376 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7377 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7378
7379 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7380 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7381 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7382 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7383 }
7384
7385 tmp = I915_READ(PIPESRC(crtc->pipe));
7386 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7387 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7388
7389 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7390 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7391 }
7392
7393 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7394 struct intel_crtc_state *pipe_config)
7395 {
7396 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7397 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7398 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7399 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7400
7401 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7402 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7403 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7404 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7405
7406 mode->flags = pipe_config->base.adjusted_mode.flags;
7407
7408 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7409 mode->flags |= pipe_config->base.adjusted_mode.flags;
7410 }
7411
7412 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7413 {
7414 struct drm_device *dev = intel_crtc->base.dev;
7415 struct drm_i915_private *dev_priv = dev->dev_private;
7416 uint32_t pipeconf;
7417
7418 pipeconf = 0;
7419
7420 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7421 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7422 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7423
7424 if (intel_crtc->config->double_wide)
7425 pipeconf |= PIPECONF_DOUBLE_WIDE;
7426
7427 /* only g4x and later have fancy bpc/dither controls */
7428 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7429 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7430 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7431 pipeconf |= PIPECONF_DITHER_EN |
7432 PIPECONF_DITHER_TYPE_SP;
7433
7434 switch (intel_crtc->config->pipe_bpp) {
7435 case 18:
7436 pipeconf |= PIPECONF_6BPC;
7437 break;
7438 case 24:
7439 pipeconf |= PIPECONF_8BPC;
7440 break;
7441 case 30:
7442 pipeconf |= PIPECONF_10BPC;
7443 break;
7444 default:
7445 /* Case prevented by intel_choose_pipe_bpp_dither. */
7446 BUG();
7447 }
7448 }
7449
7450 if (HAS_PIPE_CXSR(dev)) {
7451 if (intel_crtc->lowfreq_avail) {
7452 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7453 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7454 } else {
7455 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7456 }
7457 }
7458
7459 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7460 if (INTEL_INFO(dev)->gen < 4 ||
7461 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7462 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7463 else
7464 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7465 } else
7466 pipeconf |= PIPECONF_PROGRESSIVE;
7467
7468 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7469 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7470
7471 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7472 POSTING_READ(PIPECONF(intel_crtc->pipe));
7473 }
7474
7475 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7476 struct intel_crtc_state *crtc_state)
7477 {
7478 struct drm_device *dev = crtc->base.dev;
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480 int refclk, num_connectors = 0;
7481 intel_clock_t clock, reduced_clock;
7482 bool ok, has_reduced_clock = false;
7483 bool is_lvds = false, is_dsi = false;
7484 struct intel_encoder *encoder;
7485 const intel_limit_t *limit;
7486 struct drm_atomic_state *state = crtc_state->base.state;
7487 struct drm_connector *connector;
7488 struct drm_connector_state *connector_state;
7489 int i;
7490
7491 for_each_connector_in_state(state, connector, connector_state, i) {
7492 if (connector_state->crtc != &crtc->base)
7493 continue;
7494
7495 encoder = to_intel_encoder(connector_state->best_encoder);
7496
7497 switch (encoder->type) {
7498 case INTEL_OUTPUT_LVDS:
7499 is_lvds = true;
7500 break;
7501 case INTEL_OUTPUT_DSI:
7502 is_dsi = true;
7503 break;
7504 default:
7505 break;
7506 }
7507
7508 num_connectors++;
7509 }
7510
7511 if (is_dsi)
7512 return 0;
7513
7514 if (!crtc_state->clock_set) {
7515 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7516
7517 /*
7518 * Returns a set of divisors for the desired target clock with
7519 * the given refclk, or FALSE. The returned values represent
7520 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7521 * 2) / p1 / p2.
7522 */
7523 limit = intel_limit(crtc_state, refclk);
7524 ok = dev_priv->display.find_dpll(limit, crtc_state,
7525 crtc_state->port_clock,
7526 refclk, NULL, &clock);
7527 if (!ok) {
7528 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7529 return -EINVAL;
7530 }
7531
7532 if (is_lvds && dev_priv->lvds_downclock_avail) {
7533 /*
7534 * Ensure we match the reduced clock's P to the target
7535 * clock. If the clocks don't match, we can't switch
7536 * the display clock by using the FP0/FP1. In such case
7537 * we will disable the LVDS downclock feature.
7538 */
7539 has_reduced_clock =
7540 dev_priv->display.find_dpll(limit, crtc_state,
7541 dev_priv->lvds_downclock,
7542 refclk, &clock,
7543 &reduced_clock);
7544 }
7545 /* Compat-code for transition, will disappear. */
7546 crtc_state->dpll.n = clock.n;
7547 crtc_state->dpll.m1 = clock.m1;
7548 crtc_state->dpll.m2 = clock.m2;
7549 crtc_state->dpll.p1 = clock.p1;
7550 crtc_state->dpll.p2 = clock.p2;
7551 }
7552
7553 if (IS_GEN2(dev)) {
7554 i8xx_update_pll(crtc, crtc_state,
7555 has_reduced_clock ? &reduced_clock : NULL,
7556 num_connectors);
7557 } else if (IS_CHERRYVIEW(dev)) {
7558 chv_update_pll(crtc, crtc_state);
7559 } else if (IS_VALLEYVIEW(dev)) {
7560 vlv_update_pll(crtc, crtc_state);
7561 } else {
7562 i9xx_update_pll(crtc, crtc_state,
7563 has_reduced_clock ? &reduced_clock : NULL,
7564 num_connectors);
7565 }
7566
7567 return 0;
7568 }
7569
7570 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7571 struct intel_crtc_state *pipe_config)
7572 {
7573 struct drm_device *dev = crtc->base.dev;
7574 struct drm_i915_private *dev_priv = dev->dev_private;
7575 uint32_t tmp;
7576
7577 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7578 return;
7579
7580 tmp = I915_READ(PFIT_CONTROL);
7581 if (!(tmp & PFIT_ENABLE))
7582 return;
7583
7584 /* Check whether the pfit is attached to our pipe. */
7585 if (INTEL_INFO(dev)->gen < 4) {
7586 if (crtc->pipe != PIPE_B)
7587 return;
7588 } else {
7589 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7590 return;
7591 }
7592
7593 pipe_config->gmch_pfit.control = tmp;
7594 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7595 if (INTEL_INFO(dev)->gen < 5)
7596 pipe_config->gmch_pfit.lvds_border_bits =
7597 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7598 }
7599
7600 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7601 struct intel_crtc_state *pipe_config)
7602 {
7603 struct drm_device *dev = crtc->base.dev;
7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605 int pipe = pipe_config->cpu_transcoder;
7606 intel_clock_t clock;
7607 u32 mdiv;
7608 int refclk = 100000;
7609
7610 /* In case of MIPI DPLL will not even be used */
7611 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7612 return;
7613
7614 mutex_lock(&dev_priv->dpio_lock);
7615 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7616 mutex_unlock(&dev_priv->dpio_lock);
7617
7618 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7619 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7620 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7621 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7622 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7623
7624 vlv_clock(refclk, &clock);
7625
7626 /* clock.dot is the fast clock */
7627 pipe_config->port_clock = clock.dot / 5;
7628 }
7629
7630 static void
7631 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7632 struct intel_initial_plane_config *plane_config)
7633 {
7634 struct drm_device *dev = crtc->base.dev;
7635 struct drm_i915_private *dev_priv = dev->dev_private;
7636 u32 val, base, offset;
7637 int pipe = crtc->pipe, plane = crtc->plane;
7638 int fourcc, pixel_format;
7639 unsigned int aligned_height;
7640 struct drm_framebuffer *fb;
7641 struct intel_framebuffer *intel_fb;
7642
7643 val = I915_READ(DSPCNTR(plane));
7644 if (!(val & DISPLAY_PLANE_ENABLE))
7645 return;
7646
7647 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7648 if (!intel_fb) {
7649 DRM_DEBUG_KMS("failed to alloc fb\n");
7650 return;
7651 }
7652
7653 fb = &intel_fb->base;
7654
7655 if (INTEL_INFO(dev)->gen >= 4) {
7656 if (val & DISPPLANE_TILED) {
7657 plane_config->tiling = I915_TILING_X;
7658 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7659 }
7660 }
7661
7662 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7663 fourcc = i9xx_format_to_fourcc(pixel_format);
7664 fb->pixel_format = fourcc;
7665 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7666
7667 if (INTEL_INFO(dev)->gen >= 4) {
7668 if (plane_config->tiling)
7669 offset = I915_READ(DSPTILEOFF(plane));
7670 else
7671 offset = I915_READ(DSPLINOFF(plane));
7672 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7673 } else {
7674 base = I915_READ(DSPADDR(plane));
7675 }
7676 plane_config->base = base;
7677
7678 val = I915_READ(PIPESRC(pipe));
7679 fb->width = ((val >> 16) & 0xfff) + 1;
7680 fb->height = ((val >> 0) & 0xfff) + 1;
7681
7682 val = I915_READ(DSPSTRIDE(pipe));
7683 fb->pitches[0] = val & 0xffffffc0;
7684
7685 aligned_height = intel_fb_align_height(dev, fb->height,
7686 fb->pixel_format,
7687 fb->modifier[0]);
7688
7689 plane_config->size = fb->pitches[0] * aligned_height;
7690
7691 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7692 pipe_name(pipe), plane, fb->width, fb->height,
7693 fb->bits_per_pixel, base, fb->pitches[0],
7694 plane_config->size);
7695
7696 plane_config->fb = intel_fb;
7697 }
7698
7699 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7700 struct intel_crtc_state *pipe_config)
7701 {
7702 struct drm_device *dev = crtc->base.dev;
7703 struct drm_i915_private *dev_priv = dev->dev_private;
7704 int pipe = pipe_config->cpu_transcoder;
7705 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7706 intel_clock_t clock;
7707 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7708 int refclk = 100000;
7709
7710 mutex_lock(&dev_priv->dpio_lock);
7711 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7712 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7713 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7714 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7715 mutex_unlock(&dev_priv->dpio_lock);
7716
7717 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7718 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7719 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7720 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7721 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7722
7723 chv_clock(refclk, &clock);
7724
7725 /* clock.dot is the fast clock */
7726 pipe_config->port_clock = clock.dot / 5;
7727 }
7728
7729 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7730 struct intel_crtc_state *pipe_config)
7731 {
7732 struct drm_device *dev = crtc->base.dev;
7733 struct drm_i915_private *dev_priv = dev->dev_private;
7734 uint32_t tmp;
7735
7736 if (!intel_display_power_is_enabled(dev_priv,
7737 POWER_DOMAIN_PIPE(crtc->pipe)))
7738 return false;
7739
7740 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7741 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7742
7743 tmp = I915_READ(PIPECONF(crtc->pipe));
7744 if (!(tmp & PIPECONF_ENABLE))
7745 return false;
7746
7747 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7748 switch (tmp & PIPECONF_BPC_MASK) {
7749 case PIPECONF_6BPC:
7750 pipe_config->pipe_bpp = 18;
7751 break;
7752 case PIPECONF_8BPC:
7753 pipe_config->pipe_bpp = 24;
7754 break;
7755 case PIPECONF_10BPC:
7756 pipe_config->pipe_bpp = 30;
7757 break;
7758 default:
7759 break;
7760 }
7761 }
7762
7763 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7764 pipe_config->limited_color_range = true;
7765
7766 if (INTEL_INFO(dev)->gen < 4)
7767 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7768
7769 intel_get_pipe_timings(crtc, pipe_config);
7770
7771 i9xx_get_pfit_config(crtc, pipe_config);
7772
7773 if (INTEL_INFO(dev)->gen >= 4) {
7774 tmp = I915_READ(DPLL_MD(crtc->pipe));
7775 pipe_config->pixel_multiplier =
7776 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7777 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7778 pipe_config->dpll_hw_state.dpll_md = tmp;
7779 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7780 tmp = I915_READ(DPLL(crtc->pipe));
7781 pipe_config->pixel_multiplier =
7782 ((tmp & SDVO_MULTIPLIER_MASK)
7783 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7784 } else {
7785 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7786 * port and will be fixed up in the encoder->get_config
7787 * function. */
7788 pipe_config->pixel_multiplier = 1;
7789 }
7790 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7791 if (!IS_VALLEYVIEW(dev)) {
7792 /*
7793 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7794 * on 830. Filter it out here so that we don't
7795 * report errors due to that.
7796 */
7797 if (IS_I830(dev))
7798 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7799
7800 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7801 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7802 } else {
7803 /* Mask out read-only status bits. */
7804 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7805 DPLL_PORTC_READY_MASK |
7806 DPLL_PORTB_READY_MASK);
7807 }
7808
7809 if (IS_CHERRYVIEW(dev))
7810 chv_crtc_clock_get(crtc, pipe_config);
7811 else if (IS_VALLEYVIEW(dev))
7812 vlv_crtc_clock_get(crtc, pipe_config);
7813 else
7814 i9xx_crtc_clock_get(crtc, pipe_config);
7815
7816 return true;
7817 }
7818
7819 static void ironlake_init_pch_refclk(struct drm_device *dev)
7820 {
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 struct intel_encoder *encoder;
7823 u32 val, final;
7824 bool has_lvds = false;
7825 bool has_cpu_edp = false;
7826 bool has_panel = false;
7827 bool has_ck505 = false;
7828 bool can_ssc = false;
7829
7830 /* We need to take the global config into account */
7831 for_each_intel_encoder(dev, encoder) {
7832 switch (encoder->type) {
7833 case INTEL_OUTPUT_LVDS:
7834 has_panel = true;
7835 has_lvds = true;
7836 break;
7837 case INTEL_OUTPUT_EDP:
7838 has_panel = true;
7839 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7840 has_cpu_edp = true;
7841 break;
7842 default:
7843 break;
7844 }
7845 }
7846
7847 if (HAS_PCH_IBX(dev)) {
7848 has_ck505 = dev_priv->vbt.display_clock_mode;
7849 can_ssc = has_ck505;
7850 } else {
7851 has_ck505 = false;
7852 can_ssc = true;
7853 }
7854
7855 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7856 has_panel, has_lvds, has_ck505);
7857
7858 /* Ironlake: try to setup display ref clock before DPLL
7859 * enabling. This is only under driver's control after
7860 * PCH B stepping, previous chipset stepping should be
7861 * ignoring this setting.
7862 */
7863 val = I915_READ(PCH_DREF_CONTROL);
7864
7865 /* As we must carefully and slowly disable/enable each source in turn,
7866 * compute the final state we want first and check if we need to
7867 * make any changes at all.
7868 */
7869 final = val;
7870 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7871 if (has_ck505)
7872 final |= DREF_NONSPREAD_CK505_ENABLE;
7873 else
7874 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7875
7876 final &= ~DREF_SSC_SOURCE_MASK;
7877 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7878 final &= ~DREF_SSC1_ENABLE;
7879
7880 if (has_panel) {
7881 final |= DREF_SSC_SOURCE_ENABLE;
7882
7883 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7884 final |= DREF_SSC1_ENABLE;
7885
7886 if (has_cpu_edp) {
7887 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7888 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7889 else
7890 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7891 } else
7892 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7893 } else {
7894 final |= DREF_SSC_SOURCE_DISABLE;
7895 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7896 }
7897
7898 if (final == val)
7899 return;
7900
7901 /* Always enable nonspread source */
7902 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7903
7904 if (has_ck505)
7905 val |= DREF_NONSPREAD_CK505_ENABLE;
7906 else
7907 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7908
7909 if (has_panel) {
7910 val &= ~DREF_SSC_SOURCE_MASK;
7911 val |= DREF_SSC_SOURCE_ENABLE;
7912
7913 /* SSC must be turned on before enabling the CPU output */
7914 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7915 DRM_DEBUG_KMS("Using SSC on panel\n");
7916 val |= DREF_SSC1_ENABLE;
7917 } else
7918 val &= ~DREF_SSC1_ENABLE;
7919
7920 /* Get SSC going before enabling the outputs */
7921 I915_WRITE(PCH_DREF_CONTROL, val);
7922 POSTING_READ(PCH_DREF_CONTROL);
7923 udelay(200);
7924
7925 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7926
7927 /* Enable CPU source on CPU attached eDP */
7928 if (has_cpu_edp) {
7929 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7930 DRM_DEBUG_KMS("Using SSC on eDP\n");
7931 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7932 } else
7933 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7934 } else
7935 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7936
7937 I915_WRITE(PCH_DREF_CONTROL, val);
7938 POSTING_READ(PCH_DREF_CONTROL);
7939 udelay(200);
7940 } else {
7941 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7942
7943 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7944
7945 /* Turn off CPU output */
7946 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7947
7948 I915_WRITE(PCH_DREF_CONTROL, val);
7949 POSTING_READ(PCH_DREF_CONTROL);
7950 udelay(200);
7951
7952 /* Turn off the SSC source */
7953 val &= ~DREF_SSC_SOURCE_MASK;
7954 val |= DREF_SSC_SOURCE_DISABLE;
7955
7956 /* Turn off SSC1 */
7957 val &= ~DREF_SSC1_ENABLE;
7958
7959 I915_WRITE(PCH_DREF_CONTROL, val);
7960 POSTING_READ(PCH_DREF_CONTROL);
7961 udelay(200);
7962 }
7963
7964 BUG_ON(val != final);
7965 }
7966
7967 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7968 {
7969 uint32_t tmp;
7970
7971 tmp = I915_READ(SOUTH_CHICKEN2);
7972 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7973 I915_WRITE(SOUTH_CHICKEN2, tmp);
7974
7975 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7976 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7977 DRM_ERROR("FDI mPHY reset assert timeout\n");
7978
7979 tmp = I915_READ(SOUTH_CHICKEN2);
7980 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7981 I915_WRITE(SOUTH_CHICKEN2, tmp);
7982
7983 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7984 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7985 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7986 }
7987
7988 /* WaMPhyProgramming:hsw */
7989 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7990 {
7991 uint32_t tmp;
7992
7993 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7994 tmp &= ~(0xFF << 24);
7995 tmp |= (0x12 << 24);
7996 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7997
7998 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7999 tmp |= (1 << 11);
8000 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8001
8002 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8003 tmp |= (1 << 11);
8004 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8005
8006 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8007 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8008 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8009
8010 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8011 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8012 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8013
8014 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8015 tmp &= ~(7 << 13);
8016 tmp |= (5 << 13);
8017 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8018
8019 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8020 tmp &= ~(7 << 13);
8021 tmp |= (5 << 13);
8022 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8023
8024 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8025 tmp &= ~0xFF;
8026 tmp |= 0x1C;
8027 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8028
8029 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8030 tmp &= ~0xFF;
8031 tmp |= 0x1C;
8032 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8033
8034 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8035 tmp &= ~(0xFF << 16);
8036 tmp |= (0x1C << 16);
8037 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8038
8039 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8040 tmp &= ~(0xFF << 16);
8041 tmp |= (0x1C << 16);
8042 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8043
8044 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8045 tmp |= (1 << 27);
8046 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8047
8048 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8049 tmp |= (1 << 27);
8050 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8051
8052 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8053 tmp &= ~(0xF << 28);
8054 tmp |= (4 << 28);
8055 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8056
8057 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8058 tmp &= ~(0xF << 28);
8059 tmp |= (4 << 28);
8060 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8061 }
8062
8063 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8064 * Programming" based on the parameters passed:
8065 * - Sequence to enable CLKOUT_DP
8066 * - Sequence to enable CLKOUT_DP without spread
8067 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8068 */
8069 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8070 bool with_fdi)
8071 {
8072 struct drm_i915_private *dev_priv = dev->dev_private;
8073 uint32_t reg, tmp;
8074
8075 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8076 with_spread = true;
8077 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8078 with_fdi, "LP PCH doesn't have FDI\n"))
8079 with_fdi = false;
8080
8081 mutex_lock(&dev_priv->dpio_lock);
8082
8083 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8084 tmp &= ~SBI_SSCCTL_DISABLE;
8085 tmp |= SBI_SSCCTL_PATHALT;
8086 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8087
8088 udelay(24);
8089
8090 if (with_spread) {
8091 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8092 tmp &= ~SBI_SSCCTL_PATHALT;
8093 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8094
8095 if (with_fdi) {
8096 lpt_reset_fdi_mphy(dev_priv);
8097 lpt_program_fdi_mphy(dev_priv);
8098 }
8099 }
8100
8101 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8102 SBI_GEN0 : SBI_DBUFF0;
8103 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8104 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8105 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8106
8107 mutex_unlock(&dev_priv->dpio_lock);
8108 }
8109
8110 /* Sequence to disable CLKOUT_DP */
8111 static void lpt_disable_clkout_dp(struct drm_device *dev)
8112 {
8113 struct drm_i915_private *dev_priv = dev->dev_private;
8114 uint32_t reg, tmp;
8115
8116 mutex_lock(&dev_priv->dpio_lock);
8117
8118 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8119 SBI_GEN0 : SBI_DBUFF0;
8120 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8121 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8122 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8123
8124 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8125 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8126 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8127 tmp |= SBI_SSCCTL_PATHALT;
8128 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8129 udelay(32);
8130 }
8131 tmp |= SBI_SSCCTL_DISABLE;
8132 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8133 }
8134
8135 mutex_unlock(&dev_priv->dpio_lock);
8136 }
8137
8138 static void lpt_init_pch_refclk(struct drm_device *dev)
8139 {
8140 struct intel_encoder *encoder;
8141 bool has_vga = false;
8142
8143 for_each_intel_encoder(dev, encoder) {
8144 switch (encoder->type) {
8145 case INTEL_OUTPUT_ANALOG:
8146 has_vga = true;
8147 break;
8148 default:
8149 break;
8150 }
8151 }
8152
8153 if (has_vga)
8154 lpt_enable_clkout_dp(dev, true, true);
8155 else
8156 lpt_disable_clkout_dp(dev);
8157 }
8158
8159 /*
8160 * Initialize reference clocks when the driver loads
8161 */
8162 void intel_init_pch_refclk(struct drm_device *dev)
8163 {
8164 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8165 ironlake_init_pch_refclk(dev);
8166 else if (HAS_PCH_LPT(dev))
8167 lpt_init_pch_refclk(dev);
8168 }
8169
8170 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8171 {
8172 struct drm_device *dev = crtc_state->base.crtc->dev;
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 struct drm_atomic_state *state = crtc_state->base.state;
8175 struct drm_connector *connector;
8176 struct drm_connector_state *connector_state;
8177 struct intel_encoder *encoder;
8178 int num_connectors = 0, i;
8179 bool is_lvds = false;
8180
8181 for_each_connector_in_state(state, connector, connector_state, i) {
8182 if (connector_state->crtc != crtc_state->base.crtc)
8183 continue;
8184
8185 encoder = to_intel_encoder(connector_state->best_encoder);
8186
8187 switch (encoder->type) {
8188 case INTEL_OUTPUT_LVDS:
8189 is_lvds = true;
8190 break;
8191 default:
8192 break;
8193 }
8194 num_connectors++;
8195 }
8196
8197 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8198 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8199 dev_priv->vbt.lvds_ssc_freq);
8200 return dev_priv->vbt.lvds_ssc_freq;
8201 }
8202
8203 return 120000;
8204 }
8205
8206 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8207 {
8208 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8210 int pipe = intel_crtc->pipe;
8211 uint32_t val;
8212
8213 val = 0;
8214
8215 switch (intel_crtc->config->pipe_bpp) {
8216 case 18:
8217 val |= PIPECONF_6BPC;
8218 break;
8219 case 24:
8220 val |= PIPECONF_8BPC;
8221 break;
8222 case 30:
8223 val |= PIPECONF_10BPC;
8224 break;
8225 case 36:
8226 val |= PIPECONF_12BPC;
8227 break;
8228 default:
8229 /* Case prevented by intel_choose_pipe_bpp_dither. */
8230 BUG();
8231 }
8232
8233 if (intel_crtc->config->dither)
8234 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8235
8236 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8237 val |= PIPECONF_INTERLACED_ILK;
8238 else
8239 val |= PIPECONF_PROGRESSIVE;
8240
8241 if (intel_crtc->config->limited_color_range)
8242 val |= PIPECONF_COLOR_RANGE_SELECT;
8243
8244 I915_WRITE(PIPECONF(pipe), val);
8245 POSTING_READ(PIPECONF(pipe));
8246 }
8247
8248 /*
8249 * Set up the pipe CSC unit.
8250 *
8251 * Currently only full range RGB to limited range RGB conversion
8252 * is supported, but eventually this should handle various
8253 * RGB<->YCbCr scenarios as well.
8254 */
8255 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8256 {
8257 struct drm_device *dev = crtc->dev;
8258 struct drm_i915_private *dev_priv = dev->dev_private;
8259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8260 int pipe = intel_crtc->pipe;
8261 uint16_t coeff = 0x7800; /* 1.0 */
8262
8263 /*
8264 * TODO: Check what kind of values actually come out of the pipe
8265 * with these coeff/postoff values and adjust to get the best
8266 * accuracy. Perhaps we even need to take the bpc value into
8267 * consideration.
8268 */
8269
8270 if (intel_crtc->config->limited_color_range)
8271 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8272
8273 /*
8274 * GY/GU and RY/RU should be the other way around according
8275 * to BSpec, but reality doesn't agree. Just set them up in
8276 * a way that results in the correct picture.
8277 */
8278 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8279 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8280
8281 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8282 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8283
8284 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8285 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8286
8287 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8288 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8289 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8290
8291 if (INTEL_INFO(dev)->gen > 6) {
8292 uint16_t postoff = 0;
8293
8294 if (intel_crtc->config->limited_color_range)
8295 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8296
8297 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8298 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8299 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8300
8301 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8302 } else {
8303 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8304
8305 if (intel_crtc->config->limited_color_range)
8306 mode |= CSC_BLACK_SCREEN_OFFSET;
8307
8308 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8309 }
8310 }
8311
8312 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8313 {
8314 struct drm_device *dev = crtc->dev;
8315 struct drm_i915_private *dev_priv = dev->dev_private;
8316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8317 enum pipe pipe = intel_crtc->pipe;
8318 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8319 uint32_t val;
8320
8321 val = 0;
8322
8323 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8324 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8325
8326 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8327 val |= PIPECONF_INTERLACED_ILK;
8328 else
8329 val |= PIPECONF_PROGRESSIVE;
8330
8331 I915_WRITE(PIPECONF(cpu_transcoder), val);
8332 POSTING_READ(PIPECONF(cpu_transcoder));
8333
8334 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8335 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8336
8337 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8338 val = 0;
8339
8340 switch (intel_crtc->config->pipe_bpp) {
8341 case 18:
8342 val |= PIPEMISC_DITHER_6_BPC;
8343 break;
8344 case 24:
8345 val |= PIPEMISC_DITHER_8_BPC;
8346 break;
8347 case 30:
8348 val |= PIPEMISC_DITHER_10_BPC;
8349 break;
8350 case 36:
8351 val |= PIPEMISC_DITHER_12_BPC;
8352 break;
8353 default:
8354 /* Case prevented by pipe_config_set_bpp. */
8355 BUG();
8356 }
8357
8358 if (intel_crtc->config->dither)
8359 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8360
8361 I915_WRITE(PIPEMISC(pipe), val);
8362 }
8363 }
8364
8365 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8366 struct intel_crtc_state *crtc_state,
8367 intel_clock_t *clock,
8368 bool *has_reduced_clock,
8369 intel_clock_t *reduced_clock)
8370 {
8371 struct drm_device *dev = crtc->dev;
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 int refclk;
8374 const intel_limit_t *limit;
8375 bool ret, is_lvds = false;
8376
8377 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8378
8379 refclk = ironlake_get_refclk(crtc_state);
8380
8381 /*
8382 * Returns a set of divisors for the desired target clock with the given
8383 * refclk, or FALSE. The returned values represent the clock equation:
8384 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8385 */
8386 limit = intel_limit(crtc_state, refclk);
8387 ret = dev_priv->display.find_dpll(limit, crtc_state,
8388 crtc_state->port_clock,
8389 refclk, NULL, clock);
8390 if (!ret)
8391 return false;
8392
8393 if (is_lvds && dev_priv->lvds_downclock_avail) {
8394 /*
8395 * Ensure we match the reduced clock's P to the target clock.
8396 * If the clocks don't match, we can't switch the display clock
8397 * by using the FP0/FP1. In such case we will disable the LVDS
8398 * downclock feature.
8399 */
8400 *has_reduced_clock =
8401 dev_priv->display.find_dpll(limit, crtc_state,
8402 dev_priv->lvds_downclock,
8403 refclk, clock,
8404 reduced_clock);
8405 }
8406
8407 return true;
8408 }
8409
8410 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8411 {
8412 /*
8413 * Account for spread spectrum to avoid
8414 * oversubscribing the link. Max center spread
8415 * is 2.5%; use 5% for safety's sake.
8416 */
8417 u32 bps = target_clock * bpp * 21 / 20;
8418 return DIV_ROUND_UP(bps, link_bw * 8);
8419 }
8420
8421 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8422 {
8423 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8424 }
8425
8426 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8427 struct intel_crtc_state *crtc_state,
8428 u32 *fp,
8429 intel_clock_t *reduced_clock, u32 *fp2)
8430 {
8431 struct drm_crtc *crtc = &intel_crtc->base;
8432 struct drm_device *dev = crtc->dev;
8433 struct drm_i915_private *dev_priv = dev->dev_private;
8434 struct drm_atomic_state *state = crtc_state->base.state;
8435 struct drm_connector *connector;
8436 struct drm_connector_state *connector_state;
8437 struct intel_encoder *encoder;
8438 uint32_t dpll;
8439 int factor, num_connectors = 0, i;
8440 bool is_lvds = false, is_sdvo = false;
8441
8442 for_each_connector_in_state(state, connector, connector_state, i) {
8443 if (connector_state->crtc != crtc_state->base.crtc)
8444 continue;
8445
8446 encoder = to_intel_encoder(connector_state->best_encoder);
8447
8448 switch (encoder->type) {
8449 case INTEL_OUTPUT_LVDS:
8450 is_lvds = true;
8451 break;
8452 case INTEL_OUTPUT_SDVO:
8453 case INTEL_OUTPUT_HDMI:
8454 is_sdvo = true;
8455 break;
8456 default:
8457 break;
8458 }
8459
8460 num_connectors++;
8461 }
8462
8463 /* Enable autotuning of the PLL clock (if permissible) */
8464 factor = 21;
8465 if (is_lvds) {
8466 if ((intel_panel_use_ssc(dev_priv) &&
8467 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8468 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8469 factor = 25;
8470 } else if (crtc_state->sdvo_tv_clock)
8471 factor = 20;
8472
8473 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8474 *fp |= FP_CB_TUNE;
8475
8476 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8477 *fp2 |= FP_CB_TUNE;
8478
8479 dpll = 0;
8480
8481 if (is_lvds)
8482 dpll |= DPLLB_MODE_LVDS;
8483 else
8484 dpll |= DPLLB_MODE_DAC_SERIAL;
8485
8486 dpll |= (crtc_state->pixel_multiplier - 1)
8487 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8488
8489 if (is_sdvo)
8490 dpll |= DPLL_SDVO_HIGH_SPEED;
8491 if (crtc_state->has_dp_encoder)
8492 dpll |= DPLL_SDVO_HIGH_SPEED;
8493
8494 /* compute bitmask from p1 value */
8495 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8496 /* also FPA1 */
8497 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8498
8499 switch (crtc_state->dpll.p2) {
8500 case 5:
8501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8502 break;
8503 case 7:
8504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8505 break;
8506 case 10:
8507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8508 break;
8509 case 14:
8510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8511 break;
8512 }
8513
8514 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8515 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8516 else
8517 dpll |= PLL_REF_INPUT_DREFCLK;
8518
8519 return dpll | DPLL_VCO_ENABLE;
8520 }
8521
8522 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8523 struct intel_crtc_state *crtc_state)
8524 {
8525 struct drm_device *dev = crtc->base.dev;
8526 intel_clock_t clock, reduced_clock;
8527 u32 dpll = 0, fp = 0, fp2 = 0;
8528 bool ok, has_reduced_clock = false;
8529 bool is_lvds = false;
8530 struct intel_shared_dpll *pll;
8531
8532 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8533
8534 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8535 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8536
8537 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8538 &has_reduced_clock, &reduced_clock);
8539 if (!ok && !crtc_state->clock_set) {
8540 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8541 return -EINVAL;
8542 }
8543 /* Compat-code for transition, will disappear. */
8544 if (!crtc_state->clock_set) {
8545 crtc_state->dpll.n = clock.n;
8546 crtc_state->dpll.m1 = clock.m1;
8547 crtc_state->dpll.m2 = clock.m2;
8548 crtc_state->dpll.p1 = clock.p1;
8549 crtc_state->dpll.p2 = clock.p2;
8550 }
8551
8552 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8553 if (crtc_state->has_pch_encoder) {
8554 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8555 if (has_reduced_clock)
8556 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8557
8558 dpll = ironlake_compute_dpll(crtc, crtc_state,
8559 &fp, &reduced_clock,
8560 has_reduced_clock ? &fp2 : NULL);
8561
8562 crtc_state->dpll_hw_state.dpll = dpll;
8563 crtc_state->dpll_hw_state.fp0 = fp;
8564 if (has_reduced_clock)
8565 crtc_state->dpll_hw_state.fp1 = fp2;
8566 else
8567 crtc_state->dpll_hw_state.fp1 = fp;
8568
8569 pll = intel_get_shared_dpll(crtc, crtc_state);
8570 if (pll == NULL) {
8571 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8572 pipe_name(crtc->pipe));
8573 return -EINVAL;
8574 }
8575 }
8576
8577 if (is_lvds && has_reduced_clock)
8578 crtc->lowfreq_avail = true;
8579 else
8580 crtc->lowfreq_avail = false;
8581
8582 return 0;
8583 }
8584
8585 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8586 struct intel_link_m_n *m_n)
8587 {
8588 struct drm_device *dev = crtc->base.dev;
8589 struct drm_i915_private *dev_priv = dev->dev_private;
8590 enum pipe pipe = crtc->pipe;
8591
8592 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8593 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8594 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8595 & ~TU_SIZE_MASK;
8596 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8597 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8598 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8599 }
8600
8601 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8602 enum transcoder transcoder,
8603 struct intel_link_m_n *m_n,
8604 struct intel_link_m_n *m2_n2)
8605 {
8606 struct drm_device *dev = crtc->base.dev;
8607 struct drm_i915_private *dev_priv = dev->dev_private;
8608 enum pipe pipe = crtc->pipe;
8609
8610 if (INTEL_INFO(dev)->gen >= 5) {
8611 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8612 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8613 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8614 & ~TU_SIZE_MASK;
8615 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8616 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8617 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8618 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8619 * gen < 8) and if DRRS is supported (to make sure the
8620 * registers are not unnecessarily read).
8621 */
8622 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8623 crtc->config->has_drrs) {
8624 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8625 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8626 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8627 & ~TU_SIZE_MASK;
8628 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8629 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8630 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8631 }
8632 } else {
8633 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8634 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8635 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8636 & ~TU_SIZE_MASK;
8637 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8638 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8639 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8640 }
8641 }
8642
8643 void intel_dp_get_m_n(struct intel_crtc *crtc,
8644 struct intel_crtc_state *pipe_config)
8645 {
8646 if (pipe_config->has_pch_encoder)
8647 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8648 else
8649 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8650 &pipe_config->dp_m_n,
8651 &pipe_config->dp_m2_n2);
8652 }
8653
8654 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8655 struct intel_crtc_state *pipe_config)
8656 {
8657 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8658 &pipe_config->fdi_m_n, NULL);
8659 }
8660
8661 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8662 struct intel_crtc_state *pipe_config)
8663 {
8664 struct drm_device *dev = crtc->base.dev;
8665 struct drm_i915_private *dev_priv = dev->dev_private;
8666 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8667 uint32_t ps_ctrl = 0;
8668 int id = -1;
8669 int i;
8670
8671 /* find scaler attached to this pipe */
8672 for (i = 0; i < crtc->num_scalers; i++) {
8673 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8674 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8675 id = i;
8676 pipe_config->pch_pfit.enabled = true;
8677 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8678 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8679 break;
8680 }
8681 }
8682
8683 scaler_state->scaler_id = id;
8684 if (id >= 0) {
8685 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8686 } else {
8687 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8688 }
8689 }
8690
8691 static void
8692 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8693 struct intel_initial_plane_config *plane_config)
8694 {
8695 struct drm_device *dev = crtc->base.dev;
8696 struct drm_i915_private *dev_priv = dev->dev_private;
8697 u32 val, base, offset, stride_mult, tiling;
8698 int pipe = crtc->pipe;
8699 int fourcc, pixel_format;
8700 unsigned int aligned_height;
8701 struct drm_framebuffer *fb;
8702 struct intel_framebuffer *intel_fb;
8703
8704 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8705 if (!intel_fb) {
8706 DRM_DEBUG_KMS("failed to alloc fb\n");
8707 return;
8708 }
8709
8710 fb = &intel_fb->base;
8711
8712 val = I915_READ(PLANE_CTL(pipe, 0));
8713 if (!(val & PLANE_CTL_ENABLE))
8714 goto error;
8715
8716 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8717 fourcc = skl_format_to_fourcc(pixel_format,
8718 val & PLANE_CTL_ORDER_RGBX,
8719 val & PLANE_CTL_ALPHA_MASK);
8720 fb->pixel_format = fourcc;
8721 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8722
8723 tiling = val & PLANE_CTL_TILED_MASK;
8724 switch (tiling) {
8725 case PLANE_CTL_TILED_LINEAR:
8726 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8727 break;
8728 case PLANE_CTL_TILED_X:
8729 plane_config->tiling = I915_TILING_X;
8730 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8731 break;
8732 case PLANE_CTL_TILED_Y:
8733 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8734 break;
8735 case PLANE_CTL_TILED_YF:
8736 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8737 break;
8738 default:
8739 MISSING_CASE(tiling);
8740 goto error;
8741 }
8742
8743 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8744 plane_config->base = base;
8745
8746 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8747
8748 val = I915_READ(PLANE_SIZE(pipe, 0));
8749 fb->height = ((val >> 16) & 0xfff) + 1;
8750 fb->width = ((val >> 0) & 0x1fff) + 1;
8751
8752 val = I915_READ(PLANE_STRIDE(pipe, 0));
8753 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8754 fb->pixel_format);
8755 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8756
8757 aligned_height = intel_fb_align_height(dev, fb->height,
8758 fb->pixel_format,
8759 fb->modifier[0]);
8760
8761 plane_config->size = fb->pitches[0] * aligned_height;
8762
8763 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8764 pipe_name(pipe), fb->width, fb->height,
8765 fb->bits_per_pixel, base, fb->pitches[0],
8766 plane_config->size);
8767
8768 plane_config->fb = intel_fb;
8769 return;
8770
8771 error:
8772 kfree(fb);
8773 }
8774
8775 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8776 struct intel_crtc_state *pipe_config)
8777 {
8778 struct drm_device *dev = crtc->base.dev;
8779 struct drm_i915_private *dev_priv = dev->dev_private;
8780 uint32_t tmp;
8781
8782 tmp = I915_READ(PF_CTL(crtc->pipe));
8783
8784 if (tmp & PF_ENABLE) {
8785 pipe_config->pch_pfit.enabled = true;
8786 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8787 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8788
8789 /* We currently do not free assignements of panel fitters on
8790 * ivb/hsw (since we don't use the higher upscaling modes which
8791 * differentiates them) so just WARN about this case for now. */
8792 if (IS_GEN7(dev)) {
8793 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8794 PF_PIPE_SEL_IVB(crtc->pipe));
8795 }
8796 }
8797 }
8798
8799 static void
8800 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8801 struct intel_initial_plane_config *plane_config)
8802 {
8803 struct drm_device *dev = crtc->base.dev;
8804 struct drm_i915_private *dev_priv = dev->dev_private;
8805 u32 val, base, offset;
8806 int pipe = crtc->pipe;
8807 int fourcc, pixel_format;
8808 unsigned int aligned_height;
8809 struct drm_framebuffer *fb;
8810 struct intel_framebuffer *intel_fb;
8811
8812 val = I915_READ(DSPCNTR(pipe));
8813 if (!(val & DISPLAY_PLANE_ENABLE))
8814 return;
8815
8816 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8817 if (!intel_fb) {
8818 DRM_DEBUG_KMS("failed to alloc fb\n");
8819 return;
8820 }
8821
8822 fb = &intel_fb->base;
8823
8824 if (INTEL_INFO(dev)->gen >= 4) {
8825 if (val & DISPPLANE_TILED) {
8826 plane_config->tiling = I915_TILING_X;
8827 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8828 }
8829 }
8830
8831 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8832 fourcc = i9xx_format_to_fourcc(pixel_format);
8833 fb->pixel_format = fourcc;
8834 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8835
8836 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8837 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8838 offset = I915_READ(DSPOFFSET(pipe));
8839 } else {
8840 if (plane_config->tiling)
8841 offset = I915_READ(DSPTILEOFF(pipe));
8842 else
8843 offset = I915_READ(DSPLINOFF(pipe));
8844 }
8845 plane_config->base = base;
8846
8847 val = I915_READ(PIPESRC(pipe));
8848 fb->width = ((val >> 16) & 0xfff) + 1;
8849 fb->height = ((val >> 0) & 0xfff) + 1;
8850
8851 val = I915_READ(DSPSTRIDE(pipe));
8852 fb->pitches[0] = val & 0xffffffc0;
8853
8854 aligned_height = intel_fb_align_height(dev, fb->height,
8855 fb->pixel_format,
8856 fb->modifier[0]);
8857
8858 plane_config->size = fb->pitches[0] * aligned_height;
8859
8860 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8861 pipe_name(pipe), fb->width, fb->height,
8862 fb->bits_per_pixel, base, fb->pitches[0],
8863 plane_config->size);
8864
8865 plane_config->fb = intel_fb;
8866 }
8867
8868 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8869 struct intel_crtc_state *pipe_config)
8870 {
8871 struct drm_device *dev = crtc->base.dev;
8872 struct drm_i915_private *dev_priv = dev->dev_private;
8873 uint32_t tmp;
8874
8875 if (!intel_display_power_is_enabled(dev_priv,
8876 POWER_DOMAIN_PIPE(crtc->pipe)))
8877 return false;
8878
8879 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8880 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8881
8882 tmp = I915_READ(PIPECONF(crtc->pipe));
8883 if (!(tmp & PIPECONF_ENABLE))
8884 return false;
8885
8886 switch (tmp & PIPECONF_BPC_MASK) {
8887 case PIPECONF_6BPC:
8888 pipe_config->pipe_bpp = 18;
8889 break;
8890 case PIPECONF_8BPC:
8891 pipe_config->pipe_bpp = 24;
8892 break;
8893 case PIPECONF_10BPC:
8894 pipe_config->pipe_bpp = 30;
8895 break;
8896 case PIPECONF_12BPC:
8897 pipe_config->pipe_bpp = 36;
8898 break;
8899 default:
8900 break;
8901 }
8902
8903 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8904 pipe_config->limited_color_range = true;
8905
8906 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8907 struct intel_shared_dpll *pll;
8908
8909 pipe_config->has_pch_encoder = true;
8910
8911 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8912 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8913 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8914
8915 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8916
8917 if (HAS_PCH_IBX(dev_priv->dev)) {
8918 pipe_config->shared_dpll =
8919 (enum intel_dpll_id) crtc->pipe;
8920 } else {
8921 tmp = I915_READ(PCH_DPLL_SEL);
8922 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8923 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8924 else
8925 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8926 }
8927
8928 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8929
8930 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8931 &pipe_config->dpll_hw_state));
8932
8933 tmp = pipe_config->dpll_hw_state.dpll;
8934 pipe_config->pixel_multiplier =
8935 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8936 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8937
8938 ironlake_pch_clock_get(crtc, pipe_config);
8939 } else {
8940 pipe_config->pixel_multiplier = 1;
8941 }
8942
8943 intel_get_pipe_timings(crtc, pipe_config);
8944
8945 ironlake_get_pfit_config(crtc, pipe_config);
8946
8947 return true;
8948 }
8949
8950 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8951 {
8952 struct drm_device *dev = dev_priv->dev;
8953 struct intel_crtc *crtc;
8954
8955 for_each_intel_crtc(dev, crtc)
8956 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8957 pipe_name(crtc->pipe));
8958
8959 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8960 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8961 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8962 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8963 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8964 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8965 "CPU PWM1 enabled\n");
8966 if (IS_HASWELL(dev))
8967 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8968 "CPU PWM2 enabled\n");
8969 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8970 "PCH PWM1 enabled\n");
8971 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8972 "Utility pin enabled\n");
8973 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8974
8975 /*
8976 * In theory we can still leave IRQs enabled, as long as only the HPD
8977 * interrupts remain enabled. We used to check for that, but since it's
8978 * gen-specific and since we only disable LCPLL after we fully disable
8979 * the interrupts, the check below should be enough.
8980 */
8981 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8982 }
8983
8984 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8985 {
8986 struct drm_device *dev = dev_priv->dev;
8987
8988 if (IS_HASWELL(dev))
8989 return I915_READ(D_COMP_HSW);
8990 else
8991 return I915_READ(D_COMP_BDW);
8992 }
8993
8994 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8995 {
8996 struct drm_device *dev = dev_priv->dev;
8997
8998 if (IS_HASWELL(dev)) {
8999 mutex_lock(&dev_priv->rps.hw_lock);
9000 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9001 val))
9002 DRM_ERROR("Failed to write to D_COMP\n");
9003 mutex_unlock(&dev_priv->rps.hw_lock);
9004 } else {
9005 I915_WRITE(D_COMP_BDW, val);
9006 POSTING_READ(D_COMP_BDW);
9007 }
9008 }
9009
9010 /*
9011 * This function implements pieces of two sequences from BSpec:
9012 * - Sequence for display software to disable LCPLL
9013 * - Sequence for display software to allow package C8+
9014 * The steps implemented here are just the steps that actually touch the LCPLL
9015 * register. Callers should take care of disabling all the display engine
9016 * functions, doing the mode unset, fixing interrupts, etc.
9017 */
9018 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9019 bool switch_to_fclk, bool allow_power_down)
9020 {
9021 uint32_t val;
9022
9023 assert_can_disable_lcpll(dev_priv);
9024
9025 val = I915_READ(LCPLL_CTL);
9026
9027 if (switch_to_fclk) {
9028 val |= LCPLL_CD_SOURCE_FCLK;
9029 I915_WRITE(LCPLL_CTL, val);
9030
9031 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9032 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9033 DRM_ERROR("Switching to FCLK failed\n");
9034
9035 val = I915_READ(LCPLL_CTL);
9036 }
9037
9038 val |= LCPLL_PLL_DISABLE;
9039 I915_WRITE(LCPLL_CTL, val);
9040 POSTING_READ(LCPLL_CTL);
9041
9042 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9043 DRM_ERROR("LCPLL still locked\n");
9044
9045 val = hsw_read_dcomp(dev_priv);
9046 val |= D_COMP_COMP_DISABLE;
9047 hsw_write_dcomp(dev_priv, val);
9048 ndelay(100);
9049
9050 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9051 1))
9052 DRM_ERROR("D_COMP RCOMP still in progress\n");
9053
9054 if (allow_power_down) {
9055 val = I915_READ(LCPLL_CTL);
9056 val |= LCPLL_POWER_DOWN_ALLOW;
9057 I915_WRITE(LCPLL_CTL, val);
9058 POSTING_READ(LCPLL_CTL);
9059 }
9060 }
9061
9062 /*
9063 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9064 * source.
9065 */
9066 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9067 {
9068 uint32_t val;
9069
9070 val = I915_READ(LCPLL_CTL);
9071
9072 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9073 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9074 return;
9075
9076 /*
9077 * Make sure we're not on PC8 state before disabling PC8, otherwise
9078 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9079 */
9080 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9081
9082 if (val & LCPLL_POWER_DOWN_ALLOW) {
9083 val &= ~LCPLL_POWER_DOWN_ALLOW;
9084 I915_WRITE(LCPLL_CTL, val);
9085 POSTING_READ(LCPLL_CTL);
9086 }
9087
9088 val = hsw_read_dcomp(dev_priv);
9089 val |= D_COMP_COMP_FORCE;
9090 val &= ~D_COMP_COMP_DISABLE;
9091 hsw_write_dcomp(dev_priv, val);
9092
9093 val = I915_READ(LCPLL_CTL);
9094 val &= ~LCPLL_PLL_DISABLE;
9095 I915_WRITE(LCPLL_CTL, val);
9096
9097 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9098 DRM_ERROR("LCPLL not locked yet\n");
9099
9100 if (val & LCPLL_CD_SOURCE_FCLK) {
9101 val = I915_READ(LCPLL_CTL);
9102 val &= ~LCPLL_CD_SOURCE_FCLK;
9103 I915_WRITE(LCPLL_CTL, val);
9104
9105 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9106 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9107 DRM_ERROR("Switching back to LCPLL failed\n");
9108 }
9109
9110 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9111 }
9112
9113 /*
9114 * Package states C8 and deeper are really deep PC states that can only be
9115 * reached when all the devices on the system allow it, so even if the graphics
9116 * device allows PC8+, it doesn't mean the system will actually get to these
9117 * states. Our driver only allows PC8+ when going into runtime PM.
9118 *
9119 * The requirements for PC8+ are that all the outputs are disabled, the power
9120 * well is disabled and most interrupts are disabled, and these are also
9121 * requirements for runtime PM. When these conditions are met, we manually do
9122 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9123 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9124 * hang the machine.
9125 *
9126 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9127 * the state of some registers, so when we come back from PC8+ we need to
9128 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9129 * need to take care of the registers kept by RC6. Notice that this happens even
9130 * if we don't put the device in PCI D3 state (which is what currently happens
9131 * because of the runtime PM support).
9132 *
9133 * For more, read "Display Sequences for Package C8" on the hardware
9134 * documentation.
9135 */
9136 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9137 {
9138 struct drm_device *dev = dev_priv->dev;
9139 uint32_t val;
9140
9141 DRM_DEBUG_KMS("Enabling package C8+\n");
9142
9143 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9144 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9145 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9146 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9147 }
9148
9149 lpt_disable_clkout_dp(dev);
9150 hsw_disable_lcpll(dev_priv, true, true);
9151 }
9152
9153 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9154 {
9155 struct drm_device *dev = dev_priv->dev;
9156 uint32_t val;
9157
9158 DRM_DEBUG_KMS("Disabling package C8+\n");
9159
9160 hsw_restore_lcpll(dev_priv);
9161 lpt_init_pch_refclk(dev);
9162
9163 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9164 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9165 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9166 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9167 }
9168
9169 intel_prepare_ddi(dev);
9170 }
9171
9172 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9173 {
9174 struct drm_device *dev = old_state->dev;
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9177 int req_cdclk;
9178
9179 /* see the comment in valleyview_modeset_global_resources */
9180 if (WARN_ON(max_pixclk < 0))
9181 return;
9182
9183 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9184
9185 if (req_cdclk != dev_priv->cdclk_freq)
9186 broxton_set_cdclk(dev, req_cdclk);
9187 }
9188
9189 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9190 struct intel_crtc_state *crtc_state)
9191 {
9192 if (!intel_ddi_pll_select(crtc, crtc_state))
9193 return -EINVAL;
9194
9195 crtc->lowfreq_avail = false;
9196
9197 return 0;
9198 }
9199
9200 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9201 enum port port,
9202 struct intel_crtc_state *pipe_config)
9203 {
9204 switch (port) {
9205 case PORT_A:
9206 pipe_config->ddi_pll_sel = SKL_DPLL0;
9207 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9208 break;
9209 case PORT_B:
9210 pipe_config->ddi_pll_sel = SKL_DPLL1;
9211 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9212 break;
9213 case PORT_C:
9214 pipe_config->ddi_pll_sel = SKL_DPLL2;
9215 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9216 break;
9217 default:
9218 DRM_ERROR("Incorrect port type\n");
9219 }
9220 }
9221
9222 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9223 enum port port,
9224 struct intel_crtc_state *pipe_config)
9225 {
9226 u32 temp, dpll_ctl1;
9227
9228 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9229 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9230
9231 switch (pipe_config->ddi_pll_sel) {
9232 case SKL_DPLL0:
9233 /*
9234 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9235 * of the shared DPLL framework and thus needs to be read out
9236 * separately
9237 */
9238 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9239 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9240 break;
9241 case SKL_DPLL1:
9242 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9243 break;
9244 case SKL_DPLL2:
9245 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9246 break;
9247 case SKL_DPLL3:
9248 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9249 break;
9250 }
9251 }
9252
9253 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9254 enum port port,
9255 struct intel_crtc_state *pipe_config)
9256 {
9257 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9258
9259 switch (pipe_config->ddi_pll_sel) {
9260 case PORT_CLK_SEL_WRPLL1:
9261 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9262 break;
9263 case PORT_CLK_SEL_WRPLL2:
9264 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9265 break;
9266 }
9267 }
9268
9269 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9270 struct intel_crtc_state *pipe_config)
9271 {
9272 struct drm_device *dev = crtc->base.dev;
9273 struct drm_i915_private *dev_priv = dev->dev_private;
9274 struct intel_shared_dpll *pll;
9275 enum port port;
9276 uint32_t tmp;
9277
9278 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9279
9280 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9281
9282 if (IS_SKYLAKE(dev))
9283 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9284 else if (IS_BROXTON(dev))
9285 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9286 else
9287 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9288
9289 if (pipe_config->shared_dpll >= 0) {
9290 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9291
9292 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9293 &pipe_config->dpll_hw_state));
9294 }
9295
9296 /*
9297 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9298 * DDI E. So just check whether this pipe is wired to DDI E and whether
9299 * the PCH transcoder is on.
9300 */
9301 if (INTEL_INFO(dev)->gen < 9 &&
9302 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9303 pipe_config->has_pch_encoder = true;
9304
9305 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9306 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9307 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9308
9309 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9310 }
9311 }
9312
9313 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9314 struct intel_crtc_state *pipe_config)
9315 {
9316 struct drm_device *dev = crtc->base.dev;
9317 struct drm_i915_private *dev_priv = dev->dev_private;
9318 enum intel_display_power_domain pfit_domain;
9319 uint32_t tmp;
9320
9321 if (!intel_display_power_is_enabled(dev_priv,
9322 POWER_DOMAIN_PIPE(crtc->pipe)))
9323 return false;
9324
9325 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9326 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9327
9328 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9329 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9330 enum pipe trans_edp_pipe;
9331 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9332 default:
9333 WARN(1, "unknown pipe linked to edp transcoder\n");
9334 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9335 case TRANS_DDI_EDP_INPUT_A_ON:
9336 trans_edp_pipe = PIPE_A;
9337 break;
9338 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9339 trans_edp_pipe = PIPE_B;
9340 break;
9341 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9342 trans_edp_pipe = PIPE_C;
9343 break;
9344 }
9345
9346 if (trans_edp_pipe == crtc->pipe)
9347 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9348 }
9349
9350 if (!intel_display_power_is_enabled(dev_priv,
9351 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9352 return false;
9353
9354 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9355 if (!(tmp & PIPECONF_ENABLE))
9356 return false;
9357
9358 haswell_get_ddi_port_state(crtc, pipe_config);
9359
9360 intel_get_pipe_timings(crtc, pipe_config);
9361
9362 if (INTEL_INFO(dev)->gen >= 9) {
9363 skl_init_scalers(dev, crtc, pipe_config);
9364 }
9365
9366 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9367
9368 if (INTEL_INFO(dev)->gen >= 9) {
9369 pipe_config->scaler_state.scaler_id = -1;
9370 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9371 }
9372
9373 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9374 if (INTEL_INFO(dev)->gen == 9)
9375 skylake_get_pfit_config(crtc, pipe_config);
9376 else if (INTEL_INFO(dev)->gen < 9)
9377 ironlake_get_pfit_config(crtc, pipe_config);
9378 else
9379 MISSING_CASE(INTEL_INFO(dev)->gen);
9380 }
9381
9382 if (IS_HASWELL(dev))
9383 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9384 (I915_READ(IPS_CTL) & IPS_ENABLE);
9385
9386 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9387 pipe_config->pixel_multiplier =
9388 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9389 } else {
9390 pipe_config->pixel_multiplier = 1;
9391 }
9392
9393 return true;
9394 }
9395
9396 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9397 {
9398 struct drm_device *dev = crtc->dev;
9399 struct drm_i915_private *dev_priv = dev->dev_private;
9400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9401 uint32_t cntl = 0, size = 0;
9402
9403 if (base) {
9404 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9405 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9406 unsigned int stride = roundup_pow_of_two(width) * 4;
9407
9408 switch (stride) {
9409 default:
9410 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9411 width, stride);
9412 stride = 256;
9413 /* fallthrough */
9414 case 256:
9415 case 512:
9416 case 1024:
9417 case 2048:
9418 break;
9419 }
9420
9421 cntl |= CURSOR_ENABLE |
9422 CURSOR_GAMMA_ENABLE |
9423 CURSOR_FORMAT_ARGB |
9424 CURSOR_STRIDE(stride);
9425
9426 size = (height << 12) | width;
9427 }
9428
9429 if (intel_crtc->cursor_cntl != 0 &&
9430 (intel_crtc->cursor_base != base ||
9431 intel_crtc->cursor_size != size ||
9432 intel_crtc->cursor_cntl != cntl)) {
9433 /* On these chipsets we can only modify the base/size/stride
9434 * whilst the cursor is disabled.
9435 */
9436 I915_WRITE(_CURACNTR, 0);
9437 POSTING_READ(_CURACNTR);
9438 intel_crtc->cursor_cntl = 0;
9439 }
9440
9441 if (intel_crtc->cursor_base != base) {
9442 I915_WRITE(_CURABASE, base);
9443 intel_crtc->cursor_base = base;
9444 }
9445
9446 if (intel_crtc->cursor_size != size) {
9447 I915_WRITE(CURSIZE, size);
9448 intel_crtc->cursor_size = size;
9449 }
9450
9451 if (intel_crtc->cursor_cntl != cntl) {
9452 I915_WRITE(_CURACNTR, cntl);
9453 POSTING_READ(_CURACNTR);
9454 intel_crtc->cursor_cntl = cntl;
9455 }
9456 }
9457
9458 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9459 {
9460 struct drm_device *dev = crtc->dev;
9461 struct drm_i915_private *dev_priv = dev->dev_private;
9462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9463 int pipe = intel_crtc->pipe;
9464 uint32_t cntl;
9465
9466 cntl = 0;
9467 if (base) {
9468 cntl = MCURSOR_GAMMA_ENABLE;
9469 switch (intel_crtc->base.cursor->state->crtc_w) {
9470 case 64:
9471 cntl |= CURSOR_MODE_64_ARGB_AX;
9472 break;
9473 case 128:
9474 cntl |= CURSOR_MODE_128_ARGB_AX;
9475 break;
9476 case 256:
9477 cntl |= CURSOR_MODE_256_ARGB_AX;
9478 break;
9479 default:
9480 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9481 return;
9482 }
9483 cntl |= pipe << 28; /* Connect to correct pipe */
9484
9485 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9486 cntl |= CURSOR_PIPE_CSC_ENABLE;
9487 }
9488
9489 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9490 cntl |= CURSOR_ROTATE_180;
9491
9492 if (intel_crtc->cursor_cntl != cntl) {
9493 I915_WRITE(CURCNTR(pipe), cntl);
9494 POSTING_READ(CURCNTR(pipe));
9495 intel_crtc->cursor_cntl = cntl;
9496 }
9497
9498 /* and commit changes on next vblank */
9499 I915_WRITE(CURBASE(pipe), base);
9500 POSTING_READ(CURBASE(pipe));
9501
9502 intel_crtc->cursor_base = base;
9503 }
9504
9505 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9506 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9507 bool on)
9508 {
9509 struct drm_device *dev = crtc->dev;
9510 struct drm_i915_private *dev_priv = dev->dev_private;
9511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9512 int pipe = intel_crtc->pipe;
9513 int x = crtc->cursor_x;
9514 int y = crtc->cursor_y;
9515 u32 base = 0, pos = 0;
9516
9517 if (on)
9518 base = intel_crtc->cursor_addr;
9519
9520 if (x >= intel_crtc->config->pipe_src_w)
9521 base = 0;
9522
9523 if (y >= intel_crtc->config->pipe_src_h)
9524 base = 0;
9525
9526 if (x < 0) {
9527 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9528 base = 0;
9529
9530 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9531 x = -x;
9532 }
9533 pos |= x << CURSOR_X_SHIFT;
9534
9535 if (y < 0) {
9536 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9537 base = 0;
9538
9539 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9540 y = -y;
9541 }
9542 pos |= y << CURSOR_Y_SHIFT;
9543
9544 if (base == 0 && intel_crtc->cursor_base == 0)
9545 return;
9546
9547 I915_WRITE(CURPOS(pipe), pos);
9548
9549 /* ILK+ do this automagically */
9550 if (HAS_GMCH_DISPLAY(dev) &&
9551 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9552 base += (intel_crtc->base.cursor->state->crtc_h *
9553 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9554 }
9555
9556 if (IS_845G(dev) || IS_I865G(dev))
9557 i845_update_cursor(crtc, base);
9558 else
9559 i9xx_update_cursor(crtc, base);
9560 }
9561
9562 static bool cursor_size_ok(struct drm_device *dev,
9563 uint32_t width, uint32_t height)
9564 {
9565 if (width == 0 || height == 0)
9566 return false;
9567
9568 /*
9569 * 845g/865g are special in that they are only limited by
9570 * the width of their cursors, the height is arbitrary up to
9571 * the precision of the register. Everything else requires
9572 * square cursors, limited to a few power-of-two sizes.
9573 */
9574 if (IS_845G(dev) || IS_I865G(dev)) {
9575 if ((width & 63) != 0)
9576 return false;
9577
9578 if (width > (IS_845G(dev) ? 64 : 512))
9579 return false;
9580
9581 if (height > 1023)
9582 return false;
9583 } else {
9584 switch (width | height) {
9585 case 256:
9586 case 128:
9587 if (IS_GEN2(dev))
9588 return false;
9589 case 64:
9590 break;
9591 default:
9592 return false;
9593 }
9594 }
9595
9596 return true;
9597 }
9598
9599 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9600 u16 *blue, uint32_t start, uint32_t size)
9601 {
9602 int end = (start + size > 256) ? 256 : start + size, i;
9603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9604
9605 for (i = start; i < end; i++) {
9606 intel_crtc->lut_r[i] = red[i] >> 8;
9607 intel_crtc->lut_g[i] = green[i] >> 8;
9608 intel_crtc->lut_b[i] = blue[i] >> 8;
9609 }
9610
9611 intel_crtc_load_lut(crtc);
9612 }
9613
9614 /* VESA 640x480x72Hz mode to set on the pipe */
9615 static struct drm_display_mode load_detect_mode = {
9616 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9617 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9618 };
9619
9620 struct drm_framebuffer *
9621 __intel_framebuffer_create(struct drm_device *dev,
9622 struct drm_mode_fb_cmd2 *mode_cmd,
9623 struct drm_i915_gem_object *obj)
9624 {
9625 struct intel_framebuffer *intel_fb;
9626 int ret;
9627
9628 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9629 if (!intel_fb) {
9630 drm_gem_object_unreference(&obj->base);
9631 return ERR_PTR(-ENOMEM);
9632 }
9633
9634 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9635 if (ret)
9636 goto err;
9637
9638 return &intel_fb->base;
9639 err:
9640 drm_gem_object_unreference(&obj->base);
9641 kfree(intel_fb);
9642
9643 return ERR_PTR(ret);
9644 }
9645
9646 static struct drm_framebuffer *
9647 intel_framebuffer_create(struct drm_device *dev,
9648 struct drm_mode_fb_cmd2 *mode_cmd,
9649 struct drm_i915_gem_object *obj)
9650 {
9651 struct drm_framebuffer *fb;
9652 int ret;
9653
9654 ret = i915_mutex_lock_interruptible(dev);
9655 if (ret)
9656 return ERR_PTR(ret);
9657 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9658 mutex_unlock(&dev->struct_mutex);
9659
9660 return fb;
9661 }
9662
9663 static u32
9664 intel_framebuffer_pitch_for_width(int width, int bpp)
9665 {
9666 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9667 return ALIGN(pitch, 64);
9668 }
9669
9670 static u32
9671 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9672 {
9673 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9674 return PAGE_ALIGN(pitch * mode->vdisplay);
9675 }
9676
9677 static struct drm_framebuffer *
9678 intel_framebuffer_create_for_mode(struct drm_device *dev,
9679 struct drm_display_mode *mode,
9680 int depth, int bpp)
9681 {
9682 struct drm_i915_gem_object *obj;
9683 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9684
9685 obj = i915_gem_alloc_object(dev,
9686 intel_framebuffer_size_for_mode(mode, bpp));
9687 if (obj == NULL)
9688 return ERR_PTR(-ENOMEM);
9689
9690 mode_cmd.width = mode->hdisplay;
9691 mode_cmd.height = mode->vdisplay;
9692 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9693 bpp);
9694 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9695
9696 return intel_framebuffer_create(dev, &mode_cmd, obj);
9697 }
9698
9699 static struct drm_framebuffer *
9700 mode_fits_in_fbdev(struct drm_device *dev,
9701 struct drm_display_mode *mode)
9702 {
9703 #ifdef CONFIG_DRM_I915_FBDEV
9704 struct drm_i915_private *dev_priv = dev->dev_private;
9705 struct drm_i915_gem_object *obj;
9706 struct drm_framebuffer *fb;
9707
9708 if (!dev_priv->fbdev)
9709 return NULL;
9710
9711 if (!dev_priv->fbdev->fb)
9712 return NULL;
9713
9714 obj = dev_priv->fbdev->fb->obj;
9715 BUG_ON(!obj);
9716
9717 fb = &dev_priv->fbdev->fb->base;
9718 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9719 fb->bits_per_pixel))
9720 return NULL;
9721
9722 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9723 return NULL;
9724
9725 return fb;
9726 #else
9727 return NULL;
9728 #endif
9729 }
9730
9731 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9732 struct drm_crtc *crtc,
9733 struct drm_display_mode *mode,
9734 struct drm_framebuffer *fb,
9735 int x, int y)
9736 {
9737 struct drm_plane_state *plane_state;
9738 int hdisplay, vdisplay;
9739 int ret;
9740
9741 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9742 if (IS_ERR(plane_state))
9743 return PTR_ERR(plane_state);
9744
9745 if (mode)
9746 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9747 else
9748 hdisplay = vdisplay = 0;
9749
9750 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9751 if (ret)
9752 return ret;
9753 drm_atomic_set_fb_for_plane(plane_state, fb);
9754 plane_state->crtc_x = 0;
9755 plane_state->crtc_y = 0;
9756 plane_state->crtc_w = hdisplay;
9757 plane_state->crtc_h = vdisplay;
9758 plane_state->src_x = x << 16;
9759 plane_state->src_y = y << 16;
9760 plane_state->src_w = hdisplay << 16;
9761 plane_state->src_h = vdisplay << 16;
9762
9763 return 0;
9764 }
9765
9766 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9767 struct drm_display_mode *mode,
9768 struct intel_load_detect_pipe *old,
9769 struct drm_modeset_acquire_ctx *ctx)
9770 {
9771 struct intel_crtc *intel_crtc;
9772 struct intel_encoder *intel_encoder =
9773 intel_attached_encoder(connector);
9774 struct drm_crtc *possible_crtc;
9775 struct drm_encoder *encoder = &intel_encoder->base;
9776 struct drm_crtc *crtc = NULL;
9777 struct drm_device *dev = encoder->dev;
9778 struct drm_framebuffer *fb;
9779 struct drm_mode_config *config = &dev->mode_config;
9780 struct drm_atomic_state *state = NULL;
9781 struct drm_connector_state *connector_state;
9782 struct intel_crtc_state *crtc_state;
9783 int ret, i = -1;
9784
9785 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9786 connector->base.id, connector->name,
9787 encoder->base.id, encoder->name);
9788
9789 retry:
9790 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9791 if (ret)
9792 goto fail_unlock;
9793
9794 /*
9795 * Algorithm gets a little messy:
9796 *
9797 * - if the connector already has an assigned crtc, use it (but make
9798 * sure it's on first)
9799 *
9800 * - try to find the first unused crtc that can drive this connector,
9801 * and use that if we find one
9802 */
9803
9804 /* See if we already have a CRTC for this connector */
9805 if (encoder->crtc) {
9806 crtc = encoder->crtc;
9807
9808 ret = drm_modeset_lock(&crtc->mutex, ctx);
9809 if (ret)
9810 goto fail_unlock;
9811 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9812 if (ret)
9813 goto fail_unlock;
9814
9815 old->dpms_mode = connector->dpms;
9816 old->load_detect_temp = false;
9817
9818 /* Make sure the crtc and connector are running */
9819 if (connector->dpms != DRM_MODE_DPMS_ON)
9820 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9821
9822 return true;
9823 }
9824
9825 /* Find an unused one (if possible) */
9826 for_each_crtc(dev, possible_crtc) {
9827 i++;
9828 if (!(encoder->possible_crtcs & (1 << i)))
9829 continue;
9830 if (possible_crtc->state->enable)
9831 continue;
9832 /* This can occur when applying the pipe A quirk on resume. */
9833 if (to_intel_crtc(possible_crtc)->new_enabled)
9834 continue;
9835
9836 crtc = possible_crtc;
9837 break;
9838 }
9839
9840 /*
9841 * If we didn't find an unused CRTC, don't use any.
9842 */
9843 if (!crtc) {
9844 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9845 goto fail_unlock;
9846 }
9847
9848 ret = drm_modeset_lock(&crtc->mutex, ctx);
9849 if (ret)
9850 goto fail_unlock;
9851 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9852 if (ret)
9853 goto fail_unlock;
9854 intel_encoder->new_crtc = to_intel_crtc(crtc);
9855 to_intel_connector(connector)->new_encoder = intel_encoder;
9856
9857 intel_crtc = to_intel_crtc(crtc);
9858 intel_crtc->new_enabled = true;
9859 old->dpms_mode = connector->dpms;
9860 old->load_detect_temp = true;
9861 old->release_fb = NULL;
9862
9863 state = drm_atomic_state_alloc(dev);
9864 if (!state)
9865 return false;
9866
9867 state->acquire_ctx = ctx;
9868
9869 connector_state = drm_atomic_get_connector_state(state, connector);
9870 if (IS_ERR(connector_state)) {
9871 ret = PTR_ERR(connector_state);
9872 goto fail;
9873 }
9874
9875 connector_state->crtc = crtc;
9876 connector_state->best_encoder = &intel_encoder->base;
9877
9878 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9879 if (IS_ERR(crtc_state)) {
9880 ret = PTR_ERR(crtc_state);
9881 goto fail;
9882 }
9883
9884 crtc_state->base.active = crtc_state->base.enable = true;
9885
9886 if (!mode)
9887 mode = &load_detect_mode;
9888
9889 /* We need a framebuffer large enough to accommodate all accesses
9890 * that the plane may generate whilst we perform load detection.
9891 * We can not rely on the fbcon either being present (we get called
9892 * during its initialisation to detect all boot displays, or it may
9893 * not even exist) or that it is large enough to satisfy the
9894 * requested mode.
9895 */
9896 fb = mode_fits_in_fbdev(dev, mode);
9897 if (fb == NULL) {
9898 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9899 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9900 old->release_fb = fb;
9901 } else
9902 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9903 if (IS_ERR(fb)) {
9904 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9905 goto fail;
9906 }
9907
9908 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9909 if (ret)
9910 goto fail;
9911
9912 drm_mode_copy(&crtc_state->base.mode, mode);
9913
9914 if (intel_set_mode(crtc, state)) {
9915 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9916 if (old->release_fb)
9917 old->release_fb->funcs->destroy(old->release_fb);
9918 goto fail;
9919 }
9920 crtc->primary->crtc = crtc;
9921
9922 /* let the connector get through one full cycle before testing */
9923 intel_wait_for_vblank(dev, intel_crtc->pipe);
9924 return true;
9925
9926 fail:
9927 intel_crtc->new_enabled = crtc->state->enable;
9928 fail_unlock:
9929 drm_atomic_state_free(state);
9930 state = NULL;
9931
9932 if (ret == -EDEADLK) {
9933 drm_modeset_backoff(ctx);
9934 goto retry;
9935 }
9936
9937 return false;
9938 }
9939
9940 void intel_release_load_detect_pipe(struct drm_connector *connector,
9941 struct intel_load_detect_pipe *old,
9942 struct drm_modeset_acquire_ctx *ctx)
9943 {
9944 struct drm_device *dev = connector->dev;
9945 struct intel_encoder *intel_encoder =
9946 intel_attached_encoder(connector);
9947 struct drm_encoder *encoder = &intel_encoder->base;
9948 struct drm_crtc *crtc = encoder->crtc;
9949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9950 struct drm_atomic_state *state;
9951 struct drm_connector_state *connector_state;
9952 struct intel_crtc_state *crtc_state;
9953 int ret;
9954
9955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9956 connector->base.id, connector->name,
9957 encoder->base.id, encoder->name);
9958
9959 if (old->load_detect_temp) {
9960 state = drm_atomic_state_alloc(dev);
9961 if (!state)
9962 goto fail;
9963
9964 state->acquire_ctx = ctx;
9965
9966 connector_state = drm_atomic_get_connector_state(state, connector);
9967 if (IS_ERR(connector_state))
9968 goto fail;
9969
9970 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9971 if (IS_ERR(crtc_state))
9972 goto fail;
9973
9974 to_intel_connector(connector)->new_encoder = NULL;
9975 intel_encoder->new_crtc = NULL;
9976 intel_crtc->new_enabled = false;
9977
9978 connector_state->best_encoder = NULL;
9979 connector_state->crtc = NULL;
9980
9981 crtc_state->base.enable = crtc_state->base.active = false;
9982
9983 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9984 0, 0);
9985 if (ret)
9986 goto fail;
9987
9988 ret = intel_set_mode(crtc, state);
9989 if (ret)
9990 goto fail;
9991
9992 if (old->release_fb) {
9993 drm_framebuffer_unregister_private(old->release_fb);
9994 drm_framebuffer_unreference(old->release_fb);
9995 }
9996
9997 return;
9998 }
9999
10000 /* Switch crtc and encoder back off if necessary */
10001 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10002 connector->funcs->dpms(connector, old->dpms_mode);
10003
10004 return;
10005 fail:
10006 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10007 drm_atomic_state_free(state);
10008 }
10009
10010 static int i9xx_pll_refclk(struct drm_device *dev,
10011 const struct intel_crtc_state *pipe_config)
10012 {
10013 struct drm_i915_private *dev_priv = dev->dev_private;
10014 u32 dpll = pipe_config->dpll_hw_state.dpll;
10015
10016 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10017 return dev_priv->vbt.lvds_ssc_freq;
10018 else if (HAS_PCH_SPLIT(dev))
10019 return 120000;
10020 else if (!IS_GEN2(dev))
10021 return 96000;
10022 else
10023 return 48000;
10024 }
10025
10026 /* Returns the clock of the currently programmed mode of the given pipe. */
10027 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10028 struct intel_crtc_state *pipe_config)
10029 {
10030 struct drm_device *dev = crtc->base.dev;
10031 struct drm_i915_private *dev_priv = dev->dev_private;
10032 int pipe = pipe_config->cpu_transcoder;
10033 u32 dpll = pipe_config->dpll_hw_state.dpll;
10034 u32 fp;
10035 intel_clock_t clock;
10036 int refclk = i9xx_pll_refclk(dev, pipe_config);
10037
10038 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10039 fp = pipe_config->dpll_hw_state.fp0;
10040 else
10041 fp = pipe_config->dpll_hw_state.fp1;
10042
10043 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10044 if (IS_PINEVIEW(dev)) {
10045 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10046 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10047 } else {
10048 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10049 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10050 }
10051
10052 if (!IS_GEN2(dev)) {
10053 if (IS_PINEVIEW(dev))
10054 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10055 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10056 else
10057 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10058 DPLL_FPA01_P1_POST_DIV_SHIFT);
10059
10060 switch (dpll & DPLL_MODE_MASK) {
10061 case DPLLB_MODE_DAC_SERIAL:
10062 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10063 5 : 10;
10064 break;
10065 case DPLLB_MODE_LVDS:
10066 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10067 7 : 14;
10068 break;
10069 default:
10070 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10071 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10072 return;
10073 }
10074
10075 if (IS_PINEVIEW(dev))
10076 pineview_clock(refclk, &clock);
10077 else
10078 i9xx_clock(refclk, &clock);
10079 } else {
10080 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10081 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10082
10083 if (is_lvds) {
10084 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10085 DPLL_FPA01_P1_POST_DIV_SHIFT);
10086
10087 if (lvds & LVDS_CLKB_POWER_UP)
10088 clock.p2 = 7;
10089 else
10090 clock.p2 = 14;
10091 } else {
10092 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10093 clock.p1 = 2;
10094 else {
10095 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10096 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10097 }
10098 if (dpll & PLL_P2_DIVIDE_BY_4)
10099 clock.p2 = 4;
10100 else
10101 clock.p2 = 2;
10102 }
10103
10104 i9xx_clock(refclk, &clock);
10105 }
10106
10107 /*
10108 * This value includes pixel_multiplier. We will use
10109 * port_clock to compute adjusted_mode.crtc_clock in the
10110 * encoder's get_config() function.
10111 */
10112 pipe_config->port_clock = clock.dot;
10113 }
10114
10115 int intel_dotclock_calculate(int link_freq,
10116 const struct intel_link_m_n *m_n)
10117 {
10118 /*
10119 * The calculation for the data clock is:
10120 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10121 * But we want to avoid losing precison if possible, so:
10122 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10123 *
10124 * and the link clock is simpler:
10125 * link_clock = (m * link_clock) / n
10126 */
10127
10128 if (!m_n->link_n)
10129 return 0;
10130
10131 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10132 }
10133
10134 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10135 struct intel_crtc_state *pipe_config)
10136 {
10137 struct drm_device *dev = crtc->base.dev;
10138
10139 /* read out port_clock from the DPLL */
10140 i9xx_crtc_clock_get(crtc, pipe_config);
10141
10142 /*
10143 * This value does not include pixel_multiplier.
10144 * We will check that port_clock and adjusted_mode.crtc_clock
10145 * agree once we know their relationship in the encoder's
10146 * get_config() function.
10147 */
10148 pipe_config->base.adjusted_mode.crtc_clock =
10149 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10150 &pipe_config->fdi_m_n);
10151 }
10152
10153 /** Returns the currently programmed mode of the given pipe. */
10154 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10155 struct drm_crtc *crtc)
10156 {
10157 struct drm_i915_private *dev_priv = dev->dev_private;
10158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10159 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10160 struct drm_display_mode *mode;
10161 struct intel_crtc_state pipe_config;
10162 int htot = I915_READ(HTOTAL(cpu_transcoder));
10163 int hsync = I915_READ(HSYNC(cpu_transcoder));
10164 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10165 int vsync = I915_READ(VSYNC(cpu_transcoder));
10166 enum pipe pipe = intel_crtc->pipe;
10167
10168 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10169 if (!mode)
10170 return NULL;
10171
10172 /*
10173 * Construct a pipe_config sufficient for getting the clock info
10174 * back out of crtc_clock_get.
10175 *
10176 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10177 * to use a real value here instead.
10178 */
10179 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10180 pipe_config.pixel_multiplier = 1;
10181 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10182 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10183 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10184 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10185
10186 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10187 mode->hdisplay = (htot & 0xffff) + 1;
10188 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10189 mode->hsync_start = (hsync & 0xffff) + 1;
10190 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10191 mode->vdisplay = (vtot & 0xffff) + 1;
10192 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10193 mode->vsync_start = (vsync & 0xffff) + 1;
10194 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10195
10196 drm_mode_set_name(mode);
10197
10198 return mode;
10199 }
10200
10201 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10202 {
10203 struct drm_device *dev = crtc->dev;
10204 struct drm_i915_private *dev_priv = dev->dev_private;
10205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10206
10207 if (!HAS_GMCH_DISPLAY(dev))
10208 return;
10209
10210 if (!dev_priv->lvds_downclock_avail)
10211 return;
10212
10213 /*
10214 * Since this is called by a timer, we should never get here in
10215 * the manual case.
10216 */
10217 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10218 int pipe = intel_crtc->pipe;
10219 int dpll_reg = DPLL(pipe);
10220 int dpll;
10221
10222 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10223
10224 assert_panel_unlocked(dev_priv, pipe);
10225
10226 dpll = I915_READ(dpll_reg);
10227 dpll |= DISPLAY_RATE_SELECT_FPA1;
10228 I915_WRITE(dpll_reg, dpll);
10229 intel_wait_for_vblank(dev, pipe);
10230 dpll = I915_READ(dpll_reg);
10231 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10232 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10233 }
10234
10235 }
10236
10237 void intel_mark_busy(struct drm_device *dev)
10238 {
10239 struct drm_i915_private *dev_priv = dev->dev_private;
10240
10241 if (dev_priv->mm.busy)
10242 return;
10243
10244 intel_runtime_pm_get(dev_priv);
10245 i915_update_gfx_val(dev_priv);
10246 if (INTEL_INFO(dev)->gen >= 6)
10247 gen6_rps_busy(dev_priv);
10248 dev_priv->mm.busy = true;
10249 }
10250
10251 void intel_mark_idle(struct drm_device *dev)
10252 {
10253 struct drm_i915_private *dev_priv = dev->dev_private;
10254 struct drm_crtc *crtc;
10255
10256 if (!dev_priv->mm.busy)
10257 return;
10258
10259 dev_priv->mm.busy = false;
10260
10261 for_each_crtc(dev, crtc) {
10262 if (!crtc->primary->fb)
10263 continue;
10264
10265 intel_decrease_pllclock(crtc);
10266 }
10267
10268 if (INTEL_INFO(dev)->gen >= 6)
10269 gen6_rps_idle(dev->dev_private);
10270
10271 intel_runtime_pm_put(dev_priv);
10272 }
10273
10274 static void intel_crtc_destroy(struct drm_crtc *crtc)
10275 {
10276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10277 struct drm_device *dev = crtc->dev;
10278 struct intel_unpin_work *work;
10279
10280 spin_lock_irq(&dev->event_lock);
10281 work = intel_crtc->unpin_work;
10282 intel_crtc->unpin_work = NULL;
10283 spin_unlock_irq(&dev->event_lock);
10284
10285 if (work) {
10286 cancel_work_sync(&work->work);
10287 kfree(work);
10288 }
10289
10290 drm_crtc_cleanup(crtc);
10291
10292 kfree(intel_crtc);
10293 }
10294
10295 static void intel_unpin_work_fn(struct work_struct *__work)
10296 {
10297 struct intel_unpin_work *work =
10298 container_of(__work, struct intel_unpin_work, work);
10299 struct drm_device *dev = work->crtc->dev;
10300 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10301
10302 mutex_lock(&dev->struct_mutex);
10303 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10304 drm_gem_object_unreference(&work->pending_flip_obj->base);
10305
10306 intel_fbc_update(dev);
10307
10308 if (work->flip_queued_req)
10309 i915_gem_request_assign(&work->flip_queued_req, NULL);
10310 mutex_unlock(&dev->struct_mutex);
10311
10312 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10313 drm_framebuffer_unreference(work->old_fb);
10314
10315 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10316 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10317
10318 kfree(work);
10319 }
10320
10321 static void do_intel_finish_page_flip(struct drm_device *dev,
10322 struct drm_crtc *crtc)
10323 {
10324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10325 struct intel_unpin_work *work;
10326 unsigned long flags;
10327
10328 /* Ignore early vblank irqs */
10329 if (intel_crtc == NULL)
10330 return;
10331
10332 /*
10333 * This is called both by irq handlers and the reset code (to complete
10334 * lost pageflips) so needs the full irqsave spinlocks.
10335 */
10336 spin_lock_irqsave(&dev->event_lock, flags);
10337 work = intel_crtc->unpin_work;
10338
10339 /* Ensure we don't miss a work->pending update ... */
10340 smp_rmb();
10341
10342 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10343 spin_unlock_irqrestore(&dev->event_lock, flags);
10344 return;
10345 }
10346
10347 page_flip_completed(intel_crtc);
10348
10349 spin_unlock_irqrestore(&dev->event_lock, flags);
10350 }
10351
10352 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10353 {
10354 struct drm_i915_private *dev_priv = dev->dev_private;
10355 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10356
10357 do_intel_finish_page_flip(dev, crtc);
10358 }
10359
10360 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10361 {
10362 struct drm_i915_private *dev_priv = dev->dev_private;
10363 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10364
10365 do_intel_finish_page_flip(dev, crtc);
10366 }
10367
10368 /* Is 'a' after or equal to 'b'? */
10369 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10370 {
10371 return !((a - b) & 0x80000000);
10372 }
10373
10374 static bool page_flip_finished(struct intel_crtc *crtc)
10375 {
10376 struct drm_device *dev = crtc->base.dev;
10377 struct drm_i915_private *dev_priv = dev->dev_private;
10378
10379 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10380 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10381 return true;
10382
10383 /*
10384 * The relevant registers doen't exist on pre-ctg.
10385 * As the flip done interrupt doesn't trigger for mmio
10386 * flips on gmch platforms, a flip count check isn't
10387 * really needed there. But since ctg has the registers,
10388 * include it in the check anyway.
10389 */
10390 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10391 return true;
10392
10393 /*
10394 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10395 * used the same base address. In that case the mmio flip might
10396 * have completed, but the CS hasn't even executed the flip yet.
10397 *
10398 * A flip count check isn't enough as the CS might have updated
10399 * the base address just after start of vblank, but before we
10400 * managed to process the interrupt. This means we'd complete the
10401 * CS flip too soon.
10402 *
10403 * Combining both checks should get us a good enough result. It may
10404 * still happen that the CS flip has been executed, but has not
10405 * yet actually completed. But in case the base address is the same
10406 * anyway, we don't really care.
10407 */
10408 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10409 crtc->unpin_work->gtt_offset &&
10410 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10411 crtc->unpin_work->flip_count);
10412 }
10413
10414 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10415 {
10416 struct drm_i915_private *dev_priv = dev->dev_private;
10417 struct intel_crtc *intel_crtc =
10418 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10419 unsigned long flags;
10420
10421
10422 /*
10423 * This is called both by irq handlers and the reset code (to complete
10424 * lost pageflips) so needs the full irqsave spinlocks.
10425 *
10426 * NB: An MMIO update of the plane base pointer will also
10427 * generate a page-flip completion irq, i.e. every modeset
10428 * is also accompanied by a spurious intel_prepare_page_flip().
10429 */
10430 spin_lock_irqsave(&dev->event_lock, flags);
10431 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10432 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10433 spin_unlock_irqrestore(&dev->event_lock, flags);
10434 }
10435
10436 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10437 {
10438 /* Ensure that the work item is consistent when activating it ... */
10439 smp_wmb();
10440 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10441 /* and that it is marked active as soon as the irq could fire. */
10442 smp_wmb();
10443 }
10444
10445 static int intel_gen2_queue_flip(struct drm_device *dev,
10446 struct drm_crtc *crtc,
10447 struct drm_framebuffer *fb,
10448 struct drm_i915_gem_object *obj,
10449 struct intel_engine_cs *ring,
10450 uint32_t flags)
10451 {
10452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10453 u32 flip_mask;
10454 int ret;
10455
10456 ret = intel_ring_begin(ring, 6);
10457 if (ret)
10458 return ret;
10459
10460 /* Can't queue multiple flips, so wait for the previous
10461 * one to finish before executing the next.
10462 */
10463 if (intel_crtc->plane)
10464 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10465 else
10466 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10467 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10468 intel_ring_emit(ring, MI_NOOP);
10469 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10470 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10471 intel_ring_emit(ring, fb->pitches[0]);
10472 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10473 intel_ring_emit(ring, 0); /* aux display base address, unused */
10474
10475 intel_mark_page_flip_active(intel_crtc);
10476 __intel_ring_advance(ring);
10477 return 0;
10478 }
10479
10480 static int intel_gen3_queue_flip(struct drm_device *dev,
10481 struct drm_crtc *crtc,
10482 struct drm_framebuffer *fb,
10483 struct drm_i915_gem_object *obj,
10484 struct intel_engine_cs *ring,
10485 uint32_t flags)
10486 {
10487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10488 u32 flip_mask;
10489 int ret;
10490
10491 ret = intel_ring_begin(ring, 6);
10492 if (ret)
10493 return ret;
10494
10495 if (intel_crtc->plane)
10496 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10497 else
10498 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10499 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10500 intel_ring_emit(ring, MI_NOOP);
10501 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10502 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10503 intel_ring_emit(ring, fb->pitches[0]);
10504 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10505 intel_ring_emit(ring, MI_NOOP);
10506
10507 intel_mark_page_flip_active(intel_crtc);
10508 __intel_ring_advance(ring);
10509 return 0;
10510 }
10511
10512 static int intel_gen4_queue_flip(struct drm_device *dev,
10513 struct drm_crtc *crtc,
10514 struct drm_framebuffer *fb,
10515 struct drm_i915_gem_object *obj,
10516 struct intel_engine_cs *ring,
10517 uint32_t flags)
10518 {
10519 struct drm_i915_private *dev_priv = dev->dev_private;
10520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10521 uint32_t pf, pipesrc;
10522 int ret;
10523
10524 ret = intel_ring_begin(ring, 4);
10525 if (ret)
10526 return ret;
10527
10528 /* i965+ uses the linear or tiled offsets from the
10529 * Display Registers (which do not change across a page-flip)
10530 * so we need only reprogram the base address.
10531 */
10532 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10533 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10534 intel_ring_emit(ring, fb->pitches[0]);
10535 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10536 obj->tiling_mode);
10537
10538 /* XXX Enabling the panel-fitter across page-flip is so far
10539 * untested on non-native modes, so ignore it for now.
10540 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10541 */
10542 pf = 0;
10543 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10544 intel_ring_emit(ring, pf | pipesrc);
10545
10546 intel_mark_page_flip_active(intel_crtc);
10547 __intel_ring_advance(ring);
10548 return 0;
10549 }
10550
10551 static int intel_gen6_queue_flip(struct drm_device *dev,
10552 struct drm_crtc *crtc,
10553 struct drm_framebuffer *fb,
10554 struct drm_i915_gem_object *obj,
10555 struct intel_engine_cs *ring,
10556 uint32_t flags)
10557 {
10558 struct drm_i915_private *dev_priv = dev->dev_private;
10559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10560 uint32_t pf, pipesrc;
10561 int ret;
10562
10563 ret = intel_ring_begin(ring, 4);
10564 if (ret)
10565 return ret;
10566
10567 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10568 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10569 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10570 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10571
10572 /* Contrary to the suggestions in the documentation,
10573 * "Enable Panel Fitter" does not seem to be required when page
10574 * flipping with a non-native mode, and worse causes a normal
10575 * modeset to fail.
10576 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10577 */
10578 pf = 0;
10579 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10580 intel_ring_emit(ring, pf | pipesrc);
10581
10582 intel_mark_page_flip_active(intel_crtc);
10583 __intel_ring_advance(ring);
10584 return 0;
10585 }
10586
10587 static int intel_gen7_queue_flip(struct drm_device *dev,
10588 struct drm_crtc *crtc,
10589 struct drm_framebuffer *fb,
10590 struct drm_i915_gem_object *obj,
10591 struct intel_engine_cs *ring,
10592 uint32_t flags)
10593 {
10594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10595 uint32_t plane_bit = 0;
10596 int len, ret;
10597
10598 switch (intel_crtc->plane) {
10599 case PLANE_A:
10600 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10601 break;
10602 case PLANE_B:
10603 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10604 break;
10605 case PLANE_C:
10606 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10607 break;
10608 default:
10609 WARN_ONCE(1, "unknown plane in flip command\n");
10610 return -ENODEV;
10611 }
10612
10613 len = 4;
10614 if (ring->id == RCS) {
10615 len += 6;
10616 /*
10617 * On Gen 8, SRM is now taking an extra dword to accommodate
10618 * 48bits addresses, and we need a NOOP for the batch size to
10619 * stay even.
10620 */
10621 if (IS_GEN8(dev))
10622 len += 2;
10623 }
10624
10625 /*
10626 * BSpec MI_DISPLAY_FLIP for IVB:
10627 * "The full packet must be contained within the same cache line."
10628 *
10629 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10630 * cacheline, if we ever start emitting more commands before
10631 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10632 * then do the cacheline alignment, and finally emit the
10633 * MI_DISPLAY_FLIP.
10634 */
10635 ret = intel_ring_cacheline_align(ring);
10636 if (ret)
10637 return ret;
10638
10639 ret = intel_ring_begin(ring, len);
10640 if (ret)
10641 return ret;
10642
10643 /* Unmask the flip-done completion message. Note that the bspec says that
10644 * we should do this for both the BCS and RCS, and that we must not unmask
10645 * more than one flip event at any time (or ensure that one flip message
10646 * can be sent by waiting for flip-done prior to queueing new flips).
10647 * Experimentation says that BCS works despite DERRMR masking all
10648 * flip-done completion events and that unmasking all planes at once
10649 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10650 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10651 */
10652 if (ring->id == RCS) {
10653 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10654 intel_ring_emit(ring, DERRMR);
10655 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10656 DERRMR_PIPEB_PRI_FLIP_DONE |
10657 DERRMR_PIPEC_PRI_FLIP_DONE));
10658 if (IS_GEN8(dev))
10659 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10660 MI_SRM_LRM_GLOBAL_GTT);
10661 else
10662 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10663 MI_SRM_LRM_GLOBAL_GTT);
10664 intel_ring_emit(ring, DERRMR);
10665 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10666 if (IS_GEN8(dev)) {
10667 intel_ring_emit(ring, 0);
10668 intel_ring_emit(ring, MI_NOOP);
10669 }
10670 }
10671
10672 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10673 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10674 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10675 intel_ring_emit(ring, (MI_NOOP));
10676
10677 intel_mark_page_flip_active(intel_crtc);
10678 __intel_ring_advance(ring);
10679 return 0;
10680 }
10681
10682 static bool use_mmio_flip(struct intel_engine_cs *ring,
10683 struct drm_i915_gem_object *obj)
10684 {
10685 /*
10686 * This is not being used for older platforms, because
10687 * non-availability of flip done interrupt forces us to use
10688 * CS flips. Older platforms derive flip done using some clever
10689 * tricks involving the flip_pending status bits and vblank irqs.
10690 * So using MMIO flips there would disrupt this mechanism.
10691 */
10692
10693 if (ring == NULL)
10694 return true;
10695
10696 if (INTEL_INFO(ring->dev)->gen < 5)
10697 return false;
10698
10699 if (i915.use_mmio_flip < 0)
10700 return false;
10701 else if (i915.use_mmio_flip > 0)
10702 return true;
10703 else if (i915.enable_execlists)
10704 return true;
10705 else
10706 return ring != i915_gem_request_get_ring(obj->last_read_req);
10707 }
10708
10709 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10710 {
10711 struct drm_device *dev = intel_crtc->base.dev;
10712 struct drm_i915_private *dev_priv = dev->dev_private;
10713 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10714 const enum pipe pipe = intel_crtc->pipe;
10715 u32 ctl, stride;
10716
10717 ctl = I915_READ(PLANE_CTL(pipe, 0));
10718 ctl &= ~PLANE_CTL_TILED_MASK;
10719 switch (fb->modifier[0]) {
10720 case DRM_FORMAT_MOD_NONE:
10721 break;
10722 case I915_FORMAT_MOD_X_TILED:
10723 ctl |= PLANE_CTL_TILED_X;
10724 break;
10725 case I915_FORMAT_MOD_Y_TILED:
10726 ctl |= PLANE_CTL_TILED_Y;
10727 break;
10728 case I915_FORMAT_MOD_Yf_TILED:
10729 ctl |= PLANE_CTL_TILED_YF;
10730 break;
10731 default:
10732 MISSING_CASE(fb->modifier[0]);
10733 }
10734
10735 /*
10736 * The stride is either expressed as a multiple of 64 bytes chunks for
10737 * linear buffers or in number of tiles for tiled buffers.
10738 */
10739 stride = fb->pitches[0] /
10740 intel_fb_stride_alignment(dev, fb->modifier[0],
10741 fb->pixel_format);
10742
10743 /*
10744 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10745 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10746 */
10747 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10748 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10749
10750 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10751 POSTING_READ(PLANE_SURF(pipe, 0));
10752 }
10753
10754 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10755 {
10756 struct drm_device *dev = intel_crtc->base.dev;
10757 struct drm_i915_private *dev_priv = dev->dev_private;
10758 struct intel_framebuffer *intel_fb =
10759 to_intel_framebuffer(intel_crtc->base.primary->fb);
10760 struct drm_i915_gem_object *obj = intel_fb->obj;
10761 u32 dspcntr;
10762 u32 reg;
10763
10764 reg = DSPCNTR(intel_crtc->plane);
10765 dspcntr = I915_READ(reg);
10766
10767 if (obj->tiling_mode != I915_TILING_NONE)
10768 dspcntr |= DISPPLANE_TILED;
10769 else
10770 dspcntr &= ~DISPPLANE_TILED;
10771
10772 I915_WRITE(reg, dspcntr);
10773
10774 I915_WRITE(DSPSURF(intel_crtc->plane),
10775 intel_crtc->unpin_work->gtt_offset);
10776 POSTING_READ(DSPSURF(intel_crtc->plane));
10777
10778 }
10779
10780 /*
10781 * XXX: This is the temporary way to update the plane registers until we get
10782 * around to using the usual plane update functions for MMIO flips
10783 */
10784 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10785 {
10786 struct drm_device *dev = intel_crtc->base.dev;
10787 bool atomic_update;
10788 u32 start_vbl_count;
10789
10790 intel_mark_page_flip_active(intel_crtc);
10791
10792 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10793
10794 if (INTEL_INFO(dev)->gen >= 9)
10795 skl_do_mmio_flip(intel_crtc);
10796 else
10797 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10798 ilk_do_mmio_flip(intel_crtc);
10799
10800 if (atomic_update)
10801 intel_pipe_update_end(intel_crtc, start_vbl_count);
10802 }
10803
10804 static void intel_mmio_flip_work_func(struct work_struct *work)
10805 {
10806 struct intel_mmio_flip *mmio_flip =
10807 container_of(work, struct intel_mmio_flip, work);
10808
10809 if (mmio_flip->rq)
10810 WARN_ON(__i915_wait_request(mmio_flip->rq,
10811 mmio_flip->crtc->reset_counter,
10812 false, NULL, NULL));
10813
10814 intel_do_mmio_flip(mmio_flip->crtc);
10815
10816 i915_gem_request_unreference__unlocked(mmio_flip->rq);
10817 kfree(mmio_flip);
10818 }
10819
10820 static int intel_queue_mmio_flip(struct drm_device *dev,
10821 struct drm_crtc *crtc,
10822 struct drm_framebuffer *fb,
10823 struct drm_i915_gem_object *obj,
10824 struct intel_engine_cs *ring,
10825 uint32_t flags)
10826 {
10827 struct intel_mmio_flip *mmio_flip;
10828
10829 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10830 if (mmio_flip == NULL)
10831 return -ENOMEM;
10832
10833 mmio_flip->rq = i915_gem_request_reference(obj->last_write_req);
10834 mmio_flip->crtc = to_intel_crtc(crtc);
10835
10836 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10837 schedule_work(&mmio_flip->work);
10838
10839 return 0;
10840 }
10841
10842 static int intel_default_queue_flip(struct drm_device *dev,
10843 struct drm_crtc *crtc,
10844 struct drm_framebuffer *fb,
10845 struct drm_i915_gem_object *obj,
10846 struct intel_engine_cs *ring,
10847 uint32_t flags)
10848 {
10849 return -ENODEV;
10850 }
10851
10852 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10853 struct drm_crtc *crtc)
10854 {
10855 struct drm_i915_private *dev_priv = dev->dev_private;
10856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10857 struct intel_unpin_work *work = intel_crtc->unpin_work;
10858 u32 addr;
10859
10860 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10861 return true;
10862
10863 if (!work->enable_stall_check)
10864 return false;
10865
10866 if (work->flip_ready_vblank == 0) {
10867 if (work->flip_queued_req &&
10868 !i915_gem_request_completed(work->flip_queued_req, true))
10869 return false;
10870
10871 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10872 }
10873
10874 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10875 return false;
10876
10877 /* Potential stall - if we see that the flip has happened,
10878 * assume a missed interrupt. */
10879 if (INTEL_INFO(dev)->gen >= 4)
10880 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10881 else
10882 addr = I915_READ(DSPADDR(intel_crtc->plane));
10883
10884 /* There is a potential issue here with a false positive after a flip
10885 * to the same address. We could address this by checking for a
10886 * non-incrementing frame counter.
10887 */
10888 return addr == work->gtt_offset;
10889 }
10890
10891 void intel_check_page_flip(struct drm_device *dev, int pipe)
10892 {
10893 struct drm_i915_private *dev_priv = dev->dev_private;
10894 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10896 struct intel_unpin_work *work;
10897
10898 WARN_ON(!in_interrupt());
10899
10900 if (crtc == NULL)
10901 return;
10902
10903 spin_lock(&dev->event_lock);
10904 work = intel_crtc->unpin_work;
10905 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10906 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10907 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10908 page_flip_completed(intel_crtc);
10909 work = NULL;
10910 }
10911 if (work != NULL &&
10912 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10913 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10914 spin_unlock(&dev->event_lock);
10915 }
10916
10917 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10918 struct drm_framebuffer *fb,
10919 struct drm_pending_vblank_event *event,
10920 uint32_t page_flip_flags)
10921 {
10922 struct drm_device *dev = crtc->dev;
10923 struct drm_i915_private *dev_priv = dev->dev_private;
10924 struct drm_framebuffer *old_fb = crtc->primary->fb;
10925 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10927 struct drm_plane *primary = crtc->primary;
10928 enum pipe pipe = intel_crtc->pipe;
10929 struct intel_unpin_work *work;
10930 struct intel_engine_cs *ring;
10931 bool mmio_flip;
10932 int ret;
10933
10934 /*
10935 * drm_mode_page_flip_ioctl() should already catch this, but double
10936 * check to be safe. In the future we may enable pageflipping from
10937 * a disabled primary plane.
10938 */
10939 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10940 return -EBUSY;
10941
10942 /* Can't change pixel format via MI display flips. */
10943 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10944 return -EINVAL;
10945
10946 /*
10947 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10948 * Note that pitch changes could also affect these register.
10949 */
10950 if (INTEL_INFO(dev)->gen > 3 &&
10951 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10952 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10953 return -EINVAL;
10954
10955 if (i915_terminally_wedged(&dev_priv->gpu_error))
10956 goto out_hang;
10957
10958 work = kzalloc(sizeof(*work), GFP_KERNEL);
10959 if (work == NULL)
10960 return -ENOMEM;
10961
10962 work->event = event;
10963 work->crtc = crtc;
10964 work->old_fb = old_fb;
10965 INIT_WORK(&work->work, intel_unpin_work_fn);
10966
10967 ret = drm_crtc_vblank_get(crtc);
10968 if (ret)
10969 goto free_work;
10970
10971 /* We borrow the event spin lock for protecting unpin_work */
10972 spin_lock_irq(&dev->event_lock);
10973 if (intel_crtc->unpin_work) {
10974 /* Before declaring the flip queue wedged, check if
10975 * the hardware completed the operation behind our backs.
10976 */
10977 if (__intel_pageflip_stall_check(dev, crtc)) {
10978 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10979 page_flip_completed(intel_crtc);
10980 } else {
10981 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10982 spin_unlock_irq(&dev->event_lock);
10983
10984 drm_crtc_vblank_put(crtc);
10985 kfree(work);
10986 return -EBUSY;
10987 }
10988 }
10989 intel_crtc->unpin_work = work;
10990 spin_unlock_irq(&dev->event_lock);
10991
10992 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10993 flush_workqueue(dev_priv->wq);
10994
10995 /* Reference the objects for the scheduled work. */
10996 drm_framebuffer_reference(work->old_fb);
10997 drm_gem_object_reference(&obj->base);
10998
10999 crtc->primary->fb = fb;
11000 update_state_fb(crtc->primary);
11001
11002 work->pending_flip_obj = obj;
11003
11004 ret = i915_mutex_lock_interruptible(dev);
11005 if (ret)
11006 goto cleanup;
11007
11008 atomic_inc(&intel_crtc->unpin_work_count);
11009 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11010
11011 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11012 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11013
11014 if (IS_VALLEYVIEW(dev)) {
11015 ring = &dev_priv->ring[BCS];
11016 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11017 /* vlv: DISPLAY_FLIP fails to change tiling */
11018 ring = NULL;
11019 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11020 ring = &dev_priv->ring[BCS];
11021 } else if (INTEL_INFO(dev)->gen >= 7) {
11022 ring = i915_gem_request_get_ring(obj->last_read_req);
11023 if (ring == NULL || ring->id != RCS)
11024 ring = &dev_priv->ring[BCS];
11025 } else {
11026 ring = &dev_priv->ring[RCS];
11027 }
11028
11029 mmio_flip = use_mmio_flip(ring, obj);
11030
11031 /* When using CS flips, we want to emit semaphores between rings.
11032 * However, when using mmio flips we will create a task to do the
11033 * synchronisation, so all we want here is to pin the framebuffer
11034 * into the display plane and skip any waits.
11035 */
11036 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11037 crtc->primary->state,
11038 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11039 if (ret)
11040 goto cleanup_pending;
11041
11042 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11043 + intel_crtc->dspaddr_offset;
11044
11045 if (mmio_flip) {
11046 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11047 page_flip_flags);
11048 if (ret)
11049 goto cleanup_unpin;
11050
11051 i915_gem_request_assign(&work->flip_queued_req,
11052 obj->last_write_req);
11053 } else {
11054 if (obj->last_write_req) {
11055 ret = i915_gem_check_olr(obj->last_write_req);
11056 if (ret)
11057 goto cleanup_unpin;
11058 }
11059
11060 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11061 page_flip_flags);
11062 if (ret)
11063 goto cleanup_unpin;
11064
11065 i915_gem_request_assign(&work->flip_queued_req,
11066 intel_ring_get_request(ring));
11067 }
11068
11069 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11070 work->enable_stall_check = true;
11071
11072 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11073 INTEL_FRONTBUFFER_PRIMARY(pipe));
11074
11075 intel_fbc_disable(dev);
11076 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11077 mutex_unlock(&dev->struct_mutex);
11078
11079 trace_i915_flip_request(intel_crtc->plane, obj);
11080
11081 return 0;
11082
11083 cleanup_unpin:
11084 intel_unpin_fb_obj(fb, crtc->primary->state);
11085 cleanup_pending:
11086 atomic_dec(&intel_crtc->unpin_work_count);
11087 mutex_unlock(&dev->struct_mutex);
11088 cleanup:
11089 crtc->primary->fb = old_fb;
11090 update_state_fb(crtc->primary);
11091
11092 drm_gem_object_unreference_unlocked(&obj->base);
11093 drm_framebuffer_unreference(work->old_fb);
11094
11095 spin_lock_irq(&dev->event_lock);
11096 intel_crtc->unpin_work = NULL;
11097 spin_unlock_irq(&dev->event_lock);
11098
11099 drm_crtc_vblank_put(crtc);
11100 free_work:
11101 kfree(work);
11102
11103 if (ret == -EIO) {
11104 out_hang:
11105 ret = intel_plane_restore(primary);
11106 if (ret == 0 && event) {
11107 spin_lock_irq(&dev->event_lock);
11108 drm_send_vblank_event(dev, pipe, event);
11109 spin_unlock_irq(&dev->event_lock);
11110 }
11111 }
11112 return ret;
11113 }
11114
11115 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11116 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11117 .load_lut = intel_crtc_load_lut,
11118 .atomic_begin = intel_begin_crtc_commit,
11119 .atomic_flush = intel_finish_crtc_commit,
11120 };
11121
11122 /**
11123 * intel_modeset_update_staged_output_state
11124 *
11125 * Updates the staged output configuration state, e.g. after we've read out the
11126 * current hw state.
11127 */
11128 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11129 {
11130 struct intel_crtc *crtc;
11131 struct intel_encoder *encoder;
11132 struct intel_connector *connector;
11133
11134 for_each_intel_connector(dev, connector) {
11135 connector->new_encoder =
11136 to_intel_encoder(connector->base.encoder);
11137 }
11138
11139 for_each_intel_encoder(dev, encoder) {
11140 encoder->new_crtc =
11141 to_intel_crtc(encoder->base.crtc);
11142 }
11143
11144 for_each_intel_crtc(dev, crtc) {
11145 crtc->new_enabled = crtc->base.state->enable;
11146 }
11147 }
11148
11149 /* Transitional helper to copy current connector/encoder state to
11150 * connector->state. This is needed so that code that is partially
11151 * converted to atomic does the right thing.
11152 */
11153 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11154 {
11155 struct intel_connector *connector;
11156
11157 for_each_intel_connector(dev, connector) {
11158 if (connector->base.encoder) {
11159 connector->base.state->best_encoder =
11160 connector->base.encoder;
11161 connector->base.state->crtc =
11162 connector->base.encoder->crtc;
11163 } else {
11164 connector->base.state->best_encoder = NULL;
11165 connector->base.state->crtc = NULL;
11166 }
11167 }
11168 }
11169
11170 /* Fixup legacy state after an atomic state swap.
11171 */
11172 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11173 {
11174 struct intel_crtc *crtc;
11175 struct intel_encoder *encoder;
11176 struct intel_connector *connector;
11177
11178 for_each_intel_connector(state->dev, connector) {
11179 connector->base.encoder = connector->base.state->best_encoder;
11180 if (connector->base.encoder)
11181 connector->base.encoder->crtc =
11182 connector->base.state->crtc;
11183 }
11184
11185 /* Update crtc of disabled encoders */
11186 for_each_intel_encoder(state->dev, encoder) {
11187 int num_connectors = 0;
11188
11189 for_each_intel_connector(state->dev, connector)
11190 if (connector->base.encoder == &encoder->base)
11191 num_connectors++;
11192
11193 if (num_connectors == 0)
11194 encoder->base.crtc = NULL;
11195 }
11196
11197 for_each_intel_crtc(state->dev, crtc) {
11198 crtc->base.enabled = crtc->base.state->enable;
11199 crtc->config = to_intel_crtc_state(crtc->base.state);
11200 }
11201
11202 /* Copy the new configuration to the staged state, to keep the few
11203 * pieces of code that haven't been converted yet happy */
11204 intel_modeset_update_staged_output_state(state->dev);
11205 }
11206
11207 static void
11208 connected_sink_compute_bpp(struct intel_connector *connector,
11209 struct intel_crtc_state *pipe_config)
11210 {
11211 int bpp = pipe_config->pipe_bpp;
11212
11213 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11214 connector->base.base.id,
11215 connector->base.name);
11216
11217 /* Don't use an invalid EDID bpc value */
11218 if (connector->base.display_info.bpc &&
11219 connector->base.display_info.bpc * 3 < bpp) {
11220 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11221 bpp, connector->base.display_info.bpc*3);
11222 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11223 }
11224
11225 /* Clamp bpp to 8 on screens without EDID 1.4 */
11226 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11227 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11228 bpp);
11229 pipe_config->pipe_bpp = 24;
11230 }
11231 }
11232
11233 static int
11234 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11235 struct intel_crtc_state *pipe_config)
11236 {
11237 struct drm_device *dev = crtc->base.dev;
11238 struct drm_atomic_state *state;
11239 struct drm_connector *connector;
11240 struct drm_connector_state *connector_state;
11241 int bpp, i;
11242
11243 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11244 bpp = 10*3;
11245 else if (INTEL_INFO(dev)->gen >= 5)
11246 bpp = 12*3;
11247 else
11248 bpp = 8*3;
11249
11250
11251 pipe_config->pipe_bpp = bpp;
11252
11253 state = pipe_config->base.state;
11254
11255 /* Clamp display bpp to EDID value */
11256 for_each_connector_in_state(state, connector, connector_state, i) {
11257 if (connector_state->crtc != &crtc->base)
11258 continue;
11259
11260 connected_sink_compute_bpp(to_intel_connector(connector),
11261 pipe_config);
11262 }
11263
11264 return bpp;
11265 }
11266
11267 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11268 {
11269 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11270 "type: 0x%x flags: 0x%x\n",
11271 mode->crtc_clock,
11272 mode->crtc_hdisplay, mode->crtc_hsync_start,
11273 mode->crtc_hsync_end, mode->crtc_htotal,
11274 mode->crtc_vdisplay, mode->crtc_vsync_start,
11275 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11276 }
11277
11278 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11279 struct intel_crtc_state *pipe_config,
11280 const char *context)
11281 {
11282 struct drm_device *dev = crtc->base.dev;
11283 struct drm_plane *plane;
11284 struct intel_plane *intel_plane;
11285 struct intel_plane_state *state;
11286 struct drm_framebuffer *fb;
11287
11288 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11289 context, pipe_config, pipe_name(crtc->pipe));
11290
11291 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11292 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11293 pipe_config->pipe_bpp, pipe_config->dither);
11294 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11295 pipe_config->has_pch_encoder,
11296 pipe_config->fdi_lanes,
11297 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11298 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11299 pipe_config->fdi_m_n.tu);
11300 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11301 pipe_config->has_dp_encoder,
11302 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11303 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11304 pipe_config->dp_m_n.tu);
11305
11306 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11307 pipe_config->has_dp_encoder,
11308 pipe_config->dp_m2_n2.gmch_m,
11309 pipe_config->dp_m2_n2.gmch_n,
11310 pipe_config->dp_m2_n2.link_m,
11311 pipe_config->dp_m2_n2.link_n,
11312 pipe_config->dp_m2_n2.tu);
11313
11314 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11315 pipe_config->has_audio,
11316 pipe_config->has_infoframe);
11317
11318 DRM_DEBUG_KMS("requested mode:\n");
11319 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11320 DRM_DEBUG_KMS("adjusted mode:\n");
11321 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11322 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11323 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11324 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11325 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11326 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11327 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11328 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
11329 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11330 pipe_config->gmch_pfit.control,
11331 pipe_config->gmch_pfit.pgm_ratios,
11332 pipe_config->gmch_pfit.lvds_border_bits);
11333 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11334 pipe_config->pch_pfit.pos,
11335 pipe_config->pch_pfit.size,
11336 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11337 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11338 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11339
11340 DRM_DEBUG_KMS("planes on this crtc\n");
11341 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11342 intel_plane = to_intel_plane(plane);
11343 if (intel_plane->pipe != crtc->pipe)
11344 continue;
11345
11346 state = to_intel_plane_state(plane->state);
11347 fb = state->base.fb;
11348 if (!fb) {
11349 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11350 "disabled, scaler_id = %d\n",
11351 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11352 plane->base.id, intel_plane->pipe,
11353 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11354 drm_plane_index(plane), state->scaler_id);
11355 continue;
11356 }
11357
11358 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11359 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11360 plane->base.id, intel_plane->pipe,
11361 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11362 drm_plane_index(plane));
11363 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11364 fb->base.id, fb->width, fb->height, fb->pixel_format);
11365 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11366 state->scaler_id,
11367 state->src.x1 >> 16, state->src.y1 >> 16,
11368 drm_rect_width(&state->src) >> 16,
11369 drm_rect_height(&state->src) >> 16,
11370 state->dst.x1, state->dst.y1,
11371 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11372 }
11373 }
11374
11375 static bool encoders_cloneable(const struct intel_encoder *a,
11376 const struct intel_encoder *b)
11377 {
11378 /* masks could be asymmetric, so check both ways */
11379 return a == b || (a->cloneable & (1 << b->type) &&
11380 b->cloneable & (1 << a->type));
11381 }
11382
11383 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11384 struct intel_crtc *crtc,
11385 struct intel_encoder *encoder)
11386 {
11387 struct intel_encoder *source_encoder;
11388 struct drm_connector *connector;
11389 struct drm_connector_state *connector_state;
11390 int i;
11391
11392 for_each_connector_in_state(state, connector, connector_state, i) {
11393 if (connector_state->crtc != &crtc->base)
11394 continue;
11395
11396 source_encoder =
11397 to_intel_encoder(connector_state->best_encoder);
11398 if (!encoders_cloneable(encoder, source_encoder))
11399 return false;
11400 }
11401
11402 return true;
11403 }
11404
11405 static bool check_encoder_cloning(struct drm_atomic_state *state,
11406 struct intel_crtc *crtc)
11407 {
11408 struct intel_encoder *encoder;
11409 struct drm_connector *connector;
11410 struct drm_connector_state *connector_state;
11411 int i;
11412
11413 for_each_connector_in_state(state, connector, connector_state, i) {
11414 if (connector_state->crtc != &crtc->base)
11415 continue;
11416
11417 encoder = to_intel_encoder(connector_state->best_encoder);
11418 if (!check_single_encoder_cloning(state, crtc, encoder))
11419 return false;
11420 }
11421
11422 return true;
11423 }
11424
11425 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11426 {
11427 struct drm_device *dev = state->dev;
11428 struct intel_encoder *encoder;
11429 struct drm_connector *connector;
11430 struct drm_connector_state *connector_state;
11431 unsigned int used_ports = 0;
11432 int i;
11433
11434 /*
11435 * Walk the connector list instead of the encoder
11436 * list to detect the problem on ddi platforms
11437 * where there's just one encoder per digital port.
11438 */
11439 for_each_connector_in_state(state, connector, connector_state, i) {
11440 if (!connector_state->best_encoder)
11441 continue;
11442
11443 encoder = to_intel_encoder(connector_state->best_encoder);
11444
11445 WARN_ON(!connector_state->crtc);
11446
11447 switch (encoder->type) {
11448 unsigned int port_mask;
11449 case INTEL_OUTPUT_UNKNOWN:
11450 if (WARN_ON(!HAS_DDI(dev)))
11451 break;
11452 case INTEL_OUTPUT_DISPLAYPORT:
11453 case INTEL_OUTPUT_HDMI:
11454 case INTEL_OUTPUT_EDP:
11455 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11456
11457 /* the same port mustn't appear more than once */
11458 if (used_ports & port_mask)
11459 return false;
11460
11461 used_ports |= port_mask;
11462 default:
11463 break;
11464 }
11465 }
11466
11467 return true;
11468 }
11469
11470 static void
11471 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11472 {
11473 struct drm_crtc_state tmp_state;
11474 struct intel_crtc_scaler_state scaler_state;
11475 struct intel_dpll_hw_state dpll_hw_state;
11476 enum intel_dpll_id shared_dpll;
11477
11478 /* Clear only the intel specific part of the crtc state excluding scalers */
11479 tmp_state = crtc_state->base;
11480 scaler_state = crtc_state->scaler_state;
11481 shared_dpll = crtc_state->shared_dpll;
11482 dpll_hw_state = crtc_state->dpll_hw_state;
11483
11484 memset(crtc_state, 0, sizeof *crtc_state);
11485
11486 crtc_state->base = tmp_state;
11487 crtc_state->scaler_state = scaler_state;
11488 crtc_state->shared_dpll = shared_dpll;
11489 crtc_state->dpll_hw_state = dpll_hw_state;
11490 }
11491
11492 static int
11493 intel_modeset_pipe_config(struct drm_crtc *crtc,
11494 struct drm_atomic_state *state,
11495 struct intel_crtc_state *pipe_config)
11496 {
11497 struct intel_encoder *encoder;
11498 struct drm_connector *connector;
11499 struct drm_connector_state *connector_state;
11500 int base_bpp, ret = -EINVAL;
11501 int i;
11502 bool retry = true;
11503
11504 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11505 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11506 return -EINVAL;
11507 }
11508
11509 if (!check_digital_port_conflicts(state)) {
11510 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11511 return -EINVAL;
11512 }
11513
11514 clear_intel_crtc_state(pipe_config);
11515
11516 pipe_config->cpu_transcoder =
11517 (enum transcoder) to_intel_crtc(crtc)->pipe;
11518
11519 /*
11520 * Sanitize sync polarity flags based on requested ones. If neither
11521 * positive or negative polarity is requested, treat this as meaning
11522 * negative polarity.
11523 */
11524 if (!(pipe_config->base.adjusted_mode.flags &
11525 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11526 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11527
11528 if (!(pipe_config->base.adjusted_mode.flags &
11529 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11530 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11531
11532 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11533 * plane pixel format and any sink constraints into account. Returns the
11534 * source plane bpp so that dithering can be selected on mismatches
11535 * after encoders and crtc also have had their say. */
11536 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11537 pipe_config);
11538 if (base_bpp < 0)
11539 goto fail;
11540
11541 /*
11542 * Determine the real pipe dimensions. Note that stereo modes can
11543 * increase the actual pipe size due to the frame doubling and
11544 * insertion of additional space for blanks between the frame. This
11545 * is stored in the crtc timings. We use the requested mode to do this
11546 * computation to clearly distinguish it from the adjusted mode, which
11547 * can be changed by the connectors in the below retry loop.
11548 */
11549 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11550 &pipe_config->pipe_src_w,
11551 &pipe_config->pipe_src_h);
11552
11553 encoder_retry:
11554 /* Ensure the port clock defaults are reset when retrying. */
11555 pipe_config->port_clock = 0;
11556 pipe_config->pixel_multiplier = 1;
11557
11558 /* Fill in default crtc timings, allow encoders to overwrite them. */
11559 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11560 CRTC_STEREO_DOUBLE);
11561
11562 /* Pass our mode to the connectors and the CRTC to give them a chance to
11563 * adjust it according to limitations or connector properties, and also
11564 * a chance to reject the mode entirely.
11565 */
11566 for_each_connector_in_state(state, connector, connector_state, i) {
11567 if (connector_state->crtc != crtc)
11568 continue;
11569
11570 encoder = to_intel_encoder(connector_state->best_encoder);
11571
11572 if (!(encoder->compute_config(encoder, pipe_config))) {
11573 DRM_DEBUG_KMS("Encoder config failure\n");
11574 goto fail;
11575 }
11576 }
11577
11578 /* Set default port clock if not overwritten by the encoder. Needs to be
11579 * done afterwards in case the encoder adjusts the mode. */
11580 if (!pipe_config->port_clock)
11581 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11582 * pipe_config->pixel_multiplier;
11583
11584 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11585 if (ret < 0) {
11586 DRM_DEBUG_KMS("CRTC fixup failed\n");
11587 goto fail;
11588 }
11589
11590 if (ret == RETRY) {
11591 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11592 ret = -EINVAL;
11593 goto fail;
11594 }
11595
11596 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11597 retry = false;
11598 goto encoder_retry;
11599 }
11600
11601 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11602 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11603 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11604
11605 return 0;
11606 fail:
11607 return ret;
11608 }
11609
11610 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11611 {
11612 struct drm_encoder *encoder;
11613 struct drm_device *dev = crtc->dev;
11614
11615 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11616 if (encoder->crtc == crtc)
11617 return true;
11618
11619 return false;
11620 }
11621
11622 static bool
11623 needs_modeset(struct drm_crtc_state *state)
11624 {
11625 return state->mode_changed || state->active_changed;
11626 }
11627
11628 static void
11629 intel_modeset_update_state(struct drm_atomic_state *state)
11630 {
11631 struct drm_device *dev = state->dev;
11632 struct drm_i915_private *dev_priv = dev->dev_private;
11633 struct intel_encoder *intel_encoder;
11634 struct drm_crtc *crtc;
11635 struct drm_crtc_state *crtc_state;
11636 struct drm_connector *connector;
11637 int i;
11638
11639 intel_shared_dpll_commit(dev_priv);
11640
11641 for_each_intel_encoder(dev, intel_encoder) {
11642 if (!intel_encoder->base.crtc)
11643 continue;
11644
11645 for_each_crtc_in_state(state, crtc, crtc_state, i)
11646 if (crtc == intel_encoder->base.crtc)
11647 break;
11648
11649 if (crtc != intel_encoder->base.crtc)
11650 continue;
11651
11652 if (crtc_state->enable && needs_modeset(crtc_state))
11653 intel_encoder->connectors_active = false;
11654 }
11655
11656 drm_atomic_helper_swap_state(state->dev, state);
11657 intel_modeset_fixup_state(state);
11658
11659 /* Double check state. */
11660 for_each_crtc(dev, crtc) {
11661 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11662 }
11663
11664 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11665 if (!connector->encoder || !connector->encoder->crtc)
11666 continue;
11667
11668 for_each_crtc_in_state(state, crtc, crtc_state, i)
11669 if (crtc == connector->encoder->crtc)
11670 break;
11671
11672 if (crtc != connector->encoder->crtc)
11673 continue;
11674
11675 if (crtc->state->enable && needs_modeset(crtc->state)) {
11676 struct drm_property *dpms_property =
11677 dev->mode_config.dpms_property;
11678
11679 connector->dpms = DRM_MODE_DPMS_ON;
11680 drm_object_property_set_value(&connector->base,
11681 dpms_property,
11682 DRM_MODE_DPMS_ON);
11683
11684 intel_encoder = to_intel_encoder(connector->encoder);
11685 intel_encoder->connectors_active = true;
11686 }
11687 }
11688
11689 }
11690
11691 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11692 {
11693 int diff;
11694
11695 if (clock1 == clock2)
11696 return true;
11697
11698 if (!clock1 || !clock2)
11699 return false;
11700
11701 diff = abs(clock1 - clock2);
11702
11703 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11704 return true;
11705
11706 return false;
11707 }
11708
11709 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11710 list_for_each_entry((intel_crtc), \
11711 &(dev)->mode_config.crtc_list, \
11712 base.head) \
11713 if (mask & (1 <<(intel_crtc)->pipe))
11714
11715 static bool
11716 intel_pipe_config_compare(struct drm_device *dev,
11717 struct intel_crtc_state *current_config,
11718 struct intel_crtc_state *pipe_config)
11719 {
11720 #define PIPE_CONF_CHECK_X(name) \
11721 if (current_config->name != pipe_config->name) { \
11722 DRM_ERROR("mismatch in " #name " " \
11723 "(expected 0x%08x, found 0x%08x)\n", \
11724 current_config->name, \
11725 pipe_config->name); \
11726 return false; \
11727 }
11728
11729 #define PIPE_CONF_CHECK_I(name) \
11730 if (current_config->name != pipe_config->name) { \
11731 DRM_ERROR("mismatch in " #name " " \
11732 "(expected %i, found %i)\n", \
11733 current_config->name, \
11734 pipe_config->name); \
11735 return false; \
11736 }
11737
11738 /* This is required for BDW+ where there is only one set of registers for
11739 * switching between high and low RR.
11740 * This macro can be used whenever a comparison has to be made between one
11741 * hw state and multiple sw state variables.
11742 */
11743 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11744 if ((current_config->name != pipe_config->name) && \
11745 (current_config->alt_name != pipe_config->name)) { \
11746 DRM_ERROR("mismatch in " #name " " \
11747 "(expected %i or %i, found %i)\n", \
11748 current_config->name, \
11749 current_config->alt_name, \
11750 pipe_config->name); \
11751 return false; \
11752 }
11753
11754 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11755 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11756 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11757 "(expected %i, found %i)\n", \
11758 current_config->name & (mask), \
11759 pipe_config->name & (mask)); \
11760 return false; \
11761 }
11762
11763 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11764 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11765 DRM_ERROR("mismatch in " #name " " \
11766 "(expected %i, found %i)\n", \
11767 current_config->name, \
11768 pipe_config->name); \
11769 return false; \
11770 }
11771
11772 #define PIPE_CONF_QUIRK(quirk) \
11773 ((current_config->quirks | pipe_config->quirks) & (quirk))
11774
11775 PIPE_CONF_CHECK_I(cpu_transcoder);
11776
11777 PIPE_CONF_CHECK_I(has_pch_encoder);
11778 PIPE_CONF_CHECK_I(fdi_lanes);
11779 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11780 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11781 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11782 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11783 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11784
11785 PIPE_CONF_CHECK_I(has_dp_encoder);
11786
11787 if (INTEL_INFO(dev)->gen < 8) {
11788 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11789 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11790 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11791 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11792 PIPE_CONF_CHECK_I(dp_m_n.tu);
11793
11794 if (current_config->has_drrs) {
11795 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11796 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11797 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11798 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11799 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11800 }
11801 } else {
11802 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11803 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11804 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11805 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11806 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11807 }
11808
11809 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11810 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11811 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11812 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11813 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11814 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11815
11816 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11817 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11818 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11819 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11820 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11821 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11822
11823 PIPE_CONF_CHECK_I(pixel_multiplier);
11824 PIPE_CONF_CHECK_I(has_hdmi_sink);
11825 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11826 IS_VALLEYVIEW(dev))
11827 PIPE_CONF_CHECK_I(limited_color_range);
11828 PIPE_CONF_CHECK_I(has_infoframe);
11829
11830 PIPE_CONF_CHECK_I(has_audio);
11831
11832 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11833 DRM_MODE_FLAG_INTERLACE);
11834
11835 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11836 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11837 DRM_MODE_FLAG_PHSYNC);
11838 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11839 DRM_MODE_FLAG_NHSYNC);
11840 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11841 DRM_MODE_FLAG_PVSYNC);
11842 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11843 DRM_MODE_FLAG_NVSYNC);
11844 }
11845
11846 PIPE_CONF_CHECK_I(pipe_src_w);
11847 PIPE_CONF_CHECK_I(pipe_src_h);
11848
11849 /*
11850 * FIXME: BIOS likes to set up a cloned config with lvds+external
11851 * screen. Since we don't yet re-compute the pipe config when moving
11852 * just the lvds port away to another pipe the sw tracking won't match.
11853 *
11854 * Proper atomic modesets with recomputed global state will fix this.
11855 * Until then just don't check gmch state for inherited modes.
11856 */
11857 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11858 PIPE_CONF_CHECK_I(gmch_pfit.control);
11859 /* pfit ratios are autocomputed by the hw on gen4+ */
11860 if (INTEL_INFO(dev)->gen < 4)
11861 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11862 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11863 }
11864
11865 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11866 if (current_config->pch_pfit.enabled) {
11867 PIPE_CONF_CHECK_I(pch_pfit.pos);
11868 PIPE_CONF_CHECK_I(pch_pfit.size);
11869 }
11870
11871 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11872
11873 /* BDW+ don't expose a synchronous way to read the state */
11874 if (IS_HASWELL(dev))
11875 PIPE_CONF_CHECK_I(ips_enabled);
11876
11877 PIPE_CONF_CHECK_I(double_wide);
11878
11879 PIPE_CONF_CHECK_X(ddi_pll_sel);
11880
11881 PIPE_CONF_CHECK_I(shared_dpll);
11882 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11883 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11884 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11885 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11886 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11887 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11888 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11889 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11890
11891 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11892 PIPE_CONF_CHECK_I(pipe_bpp);
11893
11894 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11895 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11896
11897 #undef PIPE_CONF_CHECK_X
11898 #undef PIPE_CONF_CHECK_I
11899 #undef PIPE_CONF_CHECK_I_ALT
11900 #undef PIPE_CONF_CHECK_FLAGS
11901 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11902 #undef PIPE_CONF_QUIRK
11903
11904 return true;
11905 }
11906
11907 static void check_wm_state(struct drm_device *dev)
11908 {
11909 struct drm_i915_private *dev_priv = dev->dev_private;
11910 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11911 struct intel_crtc *intel_crtc;
11912 int plane;
11913
11914 if (INTEL_INFO(dev)->gen < 9)
11915 return;
11916
11917 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11918 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11919
11920 for_each_intel_crtc(dev, intel_crtc) {
11921 struct skl_ddb_entry *hw_entry, *sw_entry;
11922 const enum pipe pipe = intel_crtc->pipe;
11923
11924 if (!intel_crtc->active)
11925 continue;
11926
11927 /* planes */
11928 for_each_plane(dev_priv, pipe, plane) {
11929 hw_entry = &hw_ddb.plane[pipe][plane];
11930 sw_entry = &sw_ddb->plane[pipe][plane];
11931
11932 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11933 continue;
11934
11935 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11936 "(expected (%u,%u), found (%u,%u))\n",
11937 pipe_name(pipe), plane + 1,
11938 sw_entry->start, sw_entry->end,
11939 hw_entry->start, hw_entry->end);
11940 }
11941
11942 /* cursor */
11943 hw_entry = &hw_ddb.cursor[pipe];
11944 sw_entry = &sw_ddb->cursor[pipe];
11945
11946 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11947 continue;
11948
11949 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11950 "(expected (%u,%u), found (%u,%u))\n",
11951 pipe_name(pipe),
11952 sw_entry->start, sw_entry->end,
11953 hw_entry->start, hw_entry->end);
11954 }
11955 }
11956
11957 static void
11958 check_connector_state(struct drm_device *dev)
11959 {
11960 struct intel_connector *connector;
11961
11962 for_each_intel_connector(dev, connector) {
11963 /* This also checks the encoder/connector hw state with the
11964 * ->get_hw_state callbacks. */
11965 intel_connector_check_state(connector);
11966
11967 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11968 "connector's staged encoder doesn't match current encoder\n");
11969 }
11970 }
11971
11972 static void
11973 check_encoder_state(struct drm_device *dev)
11974 {
11975 struct intel_encoder *encoder;
11976 struct intel_connector *connector;
11977
11978 for_each_intel_encoder(dev, encoder) {
11979 bool enabled = false;
11980 bool active = false;
11981 enum pipe pipe, tracked_pipe;
11982
11983 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11984 encoder->base.base.id,
11985 encoder->base.name);
11986
11987 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11988 "encoder's stage crtc doesn't match current crtc\n");
11989 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11990 "encoder's active_connectors set, but no crtc\n");
11991
11992 for_each_intel_connector(dev, connector) {
11993 if (connector->base.encoder != &encoder->base)
11994 continue;
11995 enabled = true;
11996 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11997 active = true;
11998 }
11999 /*
12000 * for MST connectors if we unplug the connector is gone
12001 * away but the encoder is still connected to a crtc
12002 * until a modeset happens in response to the hotplug.
12003 */
12004 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12005 continue;
12006
12007 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12008 "encoder's enabled state mismatch "
12009 "(expected %i, found %i)\n",
12010 !!encoder->base.crtc, enabled);
12011 I915_STATE_WARN(active && !encoder->base.crtc,
12012 "active encoder with no crtc\n");
12013
12014 I915_STATE_WARN(encoder->connectors_active != active,
12015 "encoder's computed active state doesn't match tracked active state "
12016 "(expected %i, found %i)\n", active, encoder->connectors_active);
12017
12018 active = encoder->get_hw_state(encoder, &pipe);
12019 I915_STATE_WARN(active != encoder->connectors_active,
12020 "encoder's hw state doesn't match sw tracking "
12021 "(expected %i, found %i)\n",
12022 encoder->connectors_active, active);
12023
12024 if (!encoder->base.crtc)
12025 continue;
12026
12027 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12028 I915_STATE_WARN(active && pipe != tracked_pipe,
12029 "active encoder's pipe doesn't match"
12030 "(expected %i, found %i)\n",
12031 tracked_pipe, pipe);
12032
12033 }
12034 }
12035
12036 static void
12037 check_crtc_state(struct drm_device *dev)
12038 {
12039 struct drm_i915_private *dev_priv = dev->dev_private;
12040 struct intel_crtc *crtc;
12041 struct intel_encoder *encoder;
12042 struct intel_crtc_state pipe_config;
12043
12044 for_each_intel_crtc(dev, crtc) {
12045 bool enabled = false;
12046 bool active = false;
12047
12048 memset(&pipe_config, 0, sizeof(pipe_config));
12049
12050 DRM_DEBUG_KMS("[CRTC:%d]\n",
12051 crtc->base.base.id);
12052
12053 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12054 "active crtc, but not enabled in sw tracking\n");
12055
12056 for_each_intel_encoder(dev, encoder) {
12057 if (encoder->base.crtc != &crtc->base)
12058 continue;
12059 enabled = true;
12060 if (encoder->connectors_active)
12061 active = true;
12062 }
12063
12064 I915_STATE_WARN(active != crtc->active,
12065 "crtc's computed active state doesn't match tracked active state "
12066 "(expected %i, found %i)\n", active, crtc->active);
12067 I915_STATE_WARN(enabled != crtc->base.state->enable,
12068 "crtc's computed enabled state doesn't match tracked enabled state "
12069 "(expected %i, found %i)\n", enabled,
12070 crtc->base.state->enable);
12071
12072 active = dev_priv->display.get_pipe_config(crtc,
12073 &pipe_config);
12074
12075 /* hw state is inconsistent with the pipe quirk */
12076 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12077 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12078 active = crtc->active;
12079
12080 for_each_intel_encoder(dev, encoder) {
12081 enum pipe pipe;
12082 if (encoder->base.crtc != &crtc->base)
12083 continue;
12084 if (encoder->get_hw_state(encoder, &pipe))
12085 encoder->get_config(encoder, &pipe_config);
12086 }
12087
12088 I915_STATE_WARN(crtc->active != active,
12089 "crtc active state doesn't match with hw state "
12090 "(expected %i, found %i)\n", crtc->active, active);
12091
12092 if (active &&
12093 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12094 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12095 intel_dump_pipe_config(crtc, &pipe_config,
12096 "[hw state]");
12097 intel_dump_pipe_config(crtc, crtc->config,
12098 "[sw state]");
12099 }
12100 }
12101 }
12102
12103 static void
12104 check_shared_dpll_state(struct drm_device *dev)
12105 {
12106 struct drm_i915_private *dev_priv = dev->dev_private;
12107 struct intel_crtc *crtc;
12108 struct intel_dpll_hw_state dpll_hw_state;
12109 int i;
12110
12111 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12112 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12113 int enabled_crtcs = 0, active_crtcs = 0;
12114 bool active;
12115
12116 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12117
12118 DRM_DEBUG_KMS("%s\n", pll->name);
12119
12120 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12121
12122 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12123 "more active pll users than references: %i vs %i\n",
12124 pll->active, hweight32(pll->config.crtc_mask));
12125 I915_STATE_WARN(pll->active && !pll->on,
12126 "pll in active use but not on in sw tracking\n");
12127 I915_STATE_WARN(pll->on && !pll->active,
12128 "pll in on but not on in use in sw tracking\n");
12129 I915_STATE_WARN(pll->on != active,
12130 "pll on state mismatch (expected %i, found %i)\n",
12131 pll->on, active);
12132
12133 for_each_intel_crtc(dev, crtc) {
12134 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12135 enabled_crtcs++;
12136 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12137 active_crtcs++;
12138 }
12139 I915_STATE_WARN(pll->active != active_crtcs,
12140 "pll active crtcs mismatch (expected %i, found %i)\n",
12141 pll->active, active_crtcs);
12142 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12143 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12144 hweight32(pll->config.crtc_mask), enabled_crtcs);
12145
12146 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12147 sizeof(dpll_hw_state)),
12148 "pll hw state mismatch\n");
12149 }
12150 }
12151
12152 void
12153 intel_modeset_check_state(struct drm_device *dev)
12154 {
12155 check_wm_state(dev);
12156 check_connector_state(dev);
12157 check_encoder_state(dev);
12158 check_crtc_state(dev);
12159 check_shared_dpll_state(dev);
12160 }
12161
12162 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12163 int dotclock)
12164 {
12165 /*
12166 * FDI already provided one idea for the dotclock.
12167 * Yell if the encoder disagrees.
12168 */
12169 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12170 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12171 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12172 }
12173
12174 static void update_scanline_offset(struct intel_crtc *crtc)
12175 {
12176 struct drm_device *dev = crtc->base.dev;
12177
12178 /*
12179 * The scanline counter increments at the leading edge of hsync.
12180 *
12181 * On most platforms it starts counting from vtotal-1 on the
12182 * first active line. That means the scanline counter value is
12183 * always one less than what we would expect. Ie. just after
12184 * start of vblank, which also occurs at start of hsync (on the
12185 * last active line), the scanline counter will read vblank_start-1.
12186 *
12187 * On gen2 the scanline counter starts counting from 1 instead
12188 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12189 * to keep the value positive), instead of adding one.
12190 *
12191 * On HSW+ the behaviour of the scanline counter depends on the output
12192 * type. For DP ports it behaves like most other platforms, but on HDMI
12193 * there's an extra 1 line difference. So we need to add two instead of
12194 * one to the value.
12195 */
12196 if (IS_GEN2(dev)) {
12197 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12198 int vtotal;
12199
12200 vtotal = mode->crtc_vtotal;
12201 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12202 vtotal /= 2;
12203
12204 crtc->scanline_offset = vtotal - 1;
12205 } else if (HAS_DDI(dev) &&
12206 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12207 crtc->scanline_offset = 2;
12208 } else
12209 crtc->scanline_offset = 1;
12210 }
12211
12212 static struct intel_crtc_state *
12213 intel_modeset_compute_config(struct drm_crtc *crtc,
12214 struct drm_atomic_state *state)
12215 {
12216 struct intel_crtc_state *pipe_config;
12217 int ret = 0;
12218
12219 ret = drm_atomic_add_affected_connectors(state, crtc);
12220 if (ret)
12221 return ERR_PTR(ret);
12222
12223 ret = drm_atomic_helper_check_modeset(state->dev, state);
12224 if (ret)
12225 return ERR_PTR(ret);
12226
12227 /*
12228 * Note this needs changes when we start tracking multiple modes
12229 * and crtcs. At that point we'll need to compute the whole config
12230 * (i.e. one pipe_config for each crtc) rather than just the one
12231 * for this crtc.
12232 */
12233 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12234 if (IS_ERR(pipe_config))
12235 return pipe_config;
12236
12237 if (!pipe_config->base.enable)
12238 return pipe_config;
12239
12240 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12241 if (ret)
12242 return ERR_PTR(ret);
12243
12244 /* Check things that can only be changed through modeset */
12245 if (pipe_config->has_audio !=
12246 to_intel_crtc(crtc)->config->has_audio)
12247 pipe_config->base.mode_changed = true;
12248
12249 /*
12250 * Note we have an issue here with infoframes: current code
12251 * only updates them on the full mode set path per hw
12252 * requirements. So here we should be checking for any
12253 * required changes and forcing a mode set.
12254 */
12255
12256 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12257
12258 ret = drm_atomic_helper_check_planes(state->dev, state);
12259 if (ret)
12260 return ERR_PTR(ret);
12261
12262 return pipe_config;
12263 }
12264
12265 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12266 {
12267 struct drm_device *dev = state->dev;
12268 struct drm_i915_private *dev_priv = to_i915(dev);
12269 unsigned clear_pipes = 0;
12270 struct intel_crtc *intel_crtc;
12271 struct intel_crtc_state *intel_crtc_state;
12272 struct drm_crtc *crtc;
12273 struct drm_crtc_state *crtc_state;
12274 int ret = 0;
12275 int i;
12276
12277 if (!dev_priv->display.crtc_compute_clock)
12278 return 0;
12279
12280 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12281 intel_crtc = to_intel_crtc(crtc);
12282 intel_crtc_state = to_intel_crtc_state(crtc_state);
12283
12284 if (needs_modeset(crtc_state)) {
12285 clear_pipes |= 1 << intel_crtc->pipe;
12286 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12287 memset(&intel_crtc_state->dpll_hw_state, 0,
12288 sizeof(intel_crtc_state->dpll_hw_state));
12289 }
12290 }
12291
12292 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12293 if (ret)
12294 goto done;
12295
12296 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12297 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12298 continue;
12299
12300 intel_crtc = to_intel_crtc(crtc);
12301 intel_crtc_state = to_intel_crtc_state(crtc_state);
12302
12303 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12304 intel_crtc_state);
12305 if (ret) {
12306 intel_shared_dpll_abort_config(dev_priv);
12307 goto done;
12308 }
12309 }
12310
12311 done:
12312 return ret;
12313 }
12314
12315 /* Code that should eventually be part of atomic_check() */
12316 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12317 {
12318 struct drm_device *dev = state->dev;
12319 int ret;
12320
12321 /*
12322 * See if the config requires any additional preparation, e.g.
12323 * to adjust global state with pipes off. We need to do this
12324 * here so we can get the modeset_pipe updated config for the new
12325 * mode set on this crtc. For other crtcs we need to use the
12326 * adjusted_mode bits in the crtc directly.
12327 */
12328 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12329 ret = valleyview_modeset_global_pipes(state);
12330 if (ret)
12331 return ret;
12332 }
12333
12334 ret = __intel_set_mode_setup_plls(state);
12335 if (ret)
12336 return ret;
12337
12338 return 0;
12339 }
12340
12341 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12342 struct intel_crtc_state *pipe_config)
12343 {
12344 struct drm_device *dev = modeset_crtc->dev;
12345 struct drm_i915_private *dev_priv = dev->dev_private;
12346 struct drm_atomic_state *state = pipe_config->base.state;
12347 struct drm_crtc *crtc;
12348 struct drm_crtc_state *crtc_state;
12349 int ret = 0;
12350 int i;
12351
12352 ret = __intel_set_mode_checks(state);
12353 if (ret < 0)
12354 return ret;
12355
12356 ret = drm_atomic_helper_prepare_planes(dev, state);
12357 if (ret)
12358 return ret;
12359
12360 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12361 if (!needs_modeset(crtc_state))
12362 continue;
12363
12364 if (!crtc_state->enable) {
12365 intel_crtc_disable(crtc);
12366 } else if (crtc->state->enable) {
12367 intel_crtc_disable_planes(crtc);
12368 dev_priv->display.crtc_disable(crtc);
12369 }
12370 }
12371
12372 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12373 * to set it here already despite that we pass it down the callchain.
12374 *
12375 * Note we'll need to fix this up when we start tracking multiple
12376 * pipes; here we assume a single modeset_pipe and only track the
12377 * single crtc and mode.
12378 */
12379 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12380 modeset_crtc->mode = pipe_config->base.mode;
12381
12382 /*
12383 * Calculate and store various constants which
12384 * are later needed by vblank and swap-completion
12385 * timestamping. They are derived from true hwmode.
12386 */
12387 drm_calc_timestamping_constants(modeset_crtc,
12388 &pipe_config->base.adjusted_mode);
12389 }
12390
12391 /* Only after disabling all output pipelines that will be changed can we
12392 * update the the output configuration. */
12393 intel_modeset_update_state(state);
12394
12395 /* The state has been swaped above, so state actually contains the
12396 * old state now. */
12397
12398 modeset_update_crtc_power_domains(state);
12399
12400 drm_atomic_helper_commit_planes(dev, state);
12401
12402 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12403 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12404 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12405 continue;
12406
12407 update_scanline_offset(to_intel_crtc(crtc));
12408
12409 dev_priv->display.crtc_enable(crtc);
12410 intel_crtc_enable_planes(crtc);
12411 }
12412
12413 /* FIXME: add subpixel order */
12414
12415 drm_atomic_helper_cleanup_planes(dev, state);
12416
12417 drm_atomic_state_free(state);
12418
12419 return 0;
12420 }
12421
12422 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12423 struct intel_crtc_state *pipe_config)
12424 {
12425 int ret;
12426
12427 ret = __intel_set_mode(crtc, pipe_config);
12428
12429 if (ret == 0)
12430 intel_modeset_check_state(crtc->dev);
12431
12432 return ret;
12433 }
12434
12435 static int intel_set_mode(struct drm_crtc *crtc,
12436 struct drm_atomic_state *state)
12437 {
12438 struct intel_crtc_state *pipe_config;
12439 int ret = 0;
12440
12441 pipe_config = intel_modeset_compute_config(crtc, state);
12442 if (IS_ERR(pipe_config)) {
12443 ret = PTR_ERR(pipe_config);
12444 goto out;
12445 }
12446
12447 ret = intel_set_mode_with_config(crtc, pipe_config);
12448 if (ret)
12449 goto out;
12450
12451 out:
12452 return ret;
12453 }
12454
12455 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12456 {
12457 struct drm_device *dev = crtc->dev;
12458 struct drm_atomic_state *state;
12459 struct intel_crtc *intel_crtc;
12460 struct intel_encoder *encoder;
12461 struct intel_connector *connector;
12462 struct drm_connector_state *connector_state;
12463 struct intel_crtc_state *crtc_state;
12464 int ret;
12465
12466 state = drm_atomic_state_alloc(dev);
12467 if (!state) {
12468 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12469 crtc->base.id);
12470 return;
12471 }
12472
12473 state->acquire_ctx = dev->mode_config.acquire_ctx;
12474
12475 /* The force restore path in the HW readout code relies on the staged
12476 * config still keeping the user requested config while the actual
12477 * state has been overwritten by the configuration read from HW. We
12478 * need to copy the staged config to the atomic state, otherwise the
12479 * mode set will just reapply the state the HW is already in. */
12480 for_each_intel_encoder(dev, encoder) {
12481 if (&encoder->new_crtc->base != crtc)
12482 continue;
12483
12484 for_each_intel_connector(dev, connector) {
12485 if (connector->new_encoder != encoder)
12486 continue;
12487
12488 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12489 if (IS_ERR(connector_state)) {
12490 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12491 connector->base.base.id,
12492 connector->base.name,
12493 PTR_ERR(connector_state));
12494 continue;
12495 }
12496
12497 connector_state->crtc = crtc;
12498 connector_state->best_encoder = &encoder->base;
12499 }
12500 }
12501
12502 for_each_intel_crtc(dev, intel_crtc) {
12503 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12504 continue;
12505
12506 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12507 if (IS_ERR(crtc_state)) {
12508 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12509 intel_crtc->base.base.id,
12510 PTR_ERR(crtc_state));
12511 continue;
12512 }
12513
12514 crtc_state->base.active = crtc_state->base.enable =
12515 intel_crtc->new_enabled;
12516
12517 if (&intel_crtc->base == crtc)
12518 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12519 }
12520
12521 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12522 crtc->primary->fb, crtc->x, crtc->y);
12523
12524 ret = intel_set_mode(crtc, state);
12525 if (ret)
12526 drm_atomic_state_free(state);
12527 }
12528
12529 #undef for_each_intel_crtc_masked
12530
12531 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12532 struct drm_mode_set *set)
12533 {
12534 int ro;
12535
12536 for (ro = 0; ro < set->num_connectors; ro++)
12537 if (set->connectors[ro] == &connector->base)
12538 return true;
12539
12540 return false;
12541 }
12542
12543 static int
12544 intel_modeset_stage_output_state(struct drm_device *dev,
12545 struct drm_mode_set *set,
12546 struct drm_atomic_state *state)
12547 {
12548 struct intel_connector *connector;
12549 struct drm_connector *drm_connector;
12550 struct drm_connector_state *connector_state;
12551 struct drm_crtc *crtc;
12552 struct drm_crtc_state *crtc_state;
12553 int i, ret;
12554
12555 /* The upper layers ensure that we either disable a crtc or have a list
12556 * of connectors. For paranoia, double-check this. */
12557 WARN_ON(!set->fb && (set->num_connectors != 0));
12558 WARN_ON(set->fb && (set->num_connectors == 0));
12559
12560 for_each_intel_connector(dev, connector) {
12561 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12562
12563 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12564 continue;
12565
12566 connector_state =
12567 drm_atomic_get_connector_state(state, &connector->base);
12568 if (IS_ERR(connector_state))
12569 return PTR_ERR(connector_state);
12570
12571 if (in_mode_set) {
12572 int pipe = to_intel_crtc(set->crtc)->pipe;
12573 connector_state->best_encoder =
12574 &intel_find_encoder(connector, pipe)->base;
12575 }
12576
12577 if (connector->base.state->crtc != set->crtc)
12578 continue;
12579
12580 /* If we disable the crtc, disable all its connectors. Also, if
12581 * the connector is on the changing crtc but not on the new
12582 * connector list, disable it. */
12583 if (!set->fb || !in_mode_set) {
12584 connector_state->best_encoder = NULL;
12585
12586 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12587 connector->base.base.id,
12588 connector->base.name);
12589 }
12590 }
12591 /* connector->new_encoder is now updated for all connectors. */
12592
12593 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12594 connector = to_intel_connector(drm_connector);
12595
12596 if (!connector_state->best_encoder) {
12597 ret = drm_atomic_set_crtc_for_connector(connector_state,
12598 NULL);
12599 if (ret)
12600 return ret;
12601
12602 continue;
12603 }
12604
12605 if (intel_connector_in_mode_set(connector, set)) {
12606 struct drm_crtc *crtc = connector->base.state->crtc;
12607
12608 /* If this connector was in a previous crtc, add it
12609 * to the state. We might need to disable it. */
12610 if (crtc) {
12611 crtc_state =
12612 drm_atomic_get_crtc_state(state, crtc);
12613 if (IS_ERR(crtc_state))
12614 return PTR_ERR(crtc_state);
12615 }
12616
12617 ret = drm_atomic_set_crtc_for_connector(connector_state,
12618 set->crtc);
12619 if (ret)
12620 return ret;
12621 }
12622
12623 /* Make sure the new CRTC will work with the encoder */
12624 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12625 connector_state->crtc)) {
12626 return -EINVAL;
12627 }
12628
12629 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12630 connector->base.base.id,
12631 connector->base.name,
12632 connector_state->crtc->base.id);
12633
12634 if (connector_state->best_encoder != &connector->encoder->base)
12635 connector->encoder =
12636 to_intel_encoder(connector_state->best_encoder);
12637 }
12638
12639 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12640 bool has_connectors;
12641
12642 ret = drm_atomic_add_affected_connectors(state, crtc);
12643 if (ret)
12644 return ret;
12645
12646 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12647 if (has_connectors != crtc_state->enable)
12648 crtc_state->enable =
12649 crtc_state->active = has_connectors;
12650 }
12651
12652 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12653 set->fb, set->x, set->y);
12654 if (ret)
12655 return ret;
12656
12657 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12658 if (IS_ERR(crtc_state))
12659 return PTR_ERR(crtc_state);
12660
12661 if (set->mode)
12662 drm_mode_copy(&crtc_state->mode, set->mode);
12663
12664 if (set->num_connectors)
12665 crtc_state->active = true;
12666
12667 return 0;
12668 }
12669
12670 static bool primary_plane_visible(struct drm_crtc *crtc)
12671 {
12672 struct intel_plane_state *plane_state =
12673 to_intel_plane_state(crtc->primary->state);
12674
12675 return plane_state->visible;
12676 }
12677
12678 static int intel_crtc_set_config(struct drm_mode_set *set)
12679 {
12680 struct drm_device *dev;
12681 struct drm_atomic_state *state = NULL;
12682 struct intel_crtc_state *pipe_config;
12683 bool primary_plane_was_visible;
12684 int ret;
12685
12686 BUG_ON(!set);
12687 BUG_ON(!set->crtc);
12688 BUG_ON(!set->crtc->helper_private);
12689
12690 /* Enforce sane interface api - has been abused by the fb helper. */
12691 BUG_ON(!set->mode && set->fb);
12692 BUG_ON(set->fb && set->num_connectors == 0);
12693
12694 if (set->fb) {
12695 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12696 set->crtc->base.id, set->fb->base.id,
12697 (int)set->num_connectors, set->x, set->y);
12698 } else {
12699 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12700 }
12701
12702 dev = set->crtc->dev;
12703
12704 state = drm_atomic_state_alloc(dev);
12705 if (!state)
12706 return -ENOMEM;
12707
12708 state->acquire_ctx = dev->mode_config.acquire_ctx;
12709
12710 ret = intel_modeset_stage_output_state(dev, set, state);
12711 if (ret)
12712 goto out;
12713
12714 pipe_config = intel_modeset_compute_config(set->crtc, state);
12715 if (IS_ERR(pipe_config)) {
12716 ret = PTR_ERR(pipe_config);
12717 goto out;
12718 }
12719
12720 intel_update_pipe_size(to_intel_crtc(set->crtc));
12721
12722 primary_plane_was_visible = primary_plane_visible(set->crtc);
12723
12724 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12725
12726 if (ret == 0 &&
12727 pipe_config->base.enable &&
12728 pipe_config->base.planes_changed &&
12729 !needs_modeset(&pipe_config->base)) {
12730 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12731
12732 /*
12733 * We need to make sure the primary plane is re-enabled if it
12734 * has previously been turned off.
12735 */
12736 if (ret == 0 && !primary_plane_was_visible &&
12737 primary_plane_visible(set->crtc)) {
12738 WARN_ON(!intel_crtc->active);
12739 intel_post_enable_primary(set->crtc);
12740 }
12741
12742 /*
12743 * In the fastboot case this may be our only check of the
12744 * state after boot. It would be better to only do it on
12745 * the first update, but we don't have a nice way of doing that
12746 * (and really, set_config isn't used much for high freq page
12747 * flipping, so increasing its cost here shouldn't be a big
12748 * deal).
12749 */
12750 if (i915.fastboot && ret == 0)
12751 intel_modeset_check_state(set->crtc->dev);
12752 }
12753
12754 if (ret) {
12755 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12756 set->crtc->base.id, ret);
12757 }
12758
12759 out:
12760 if (ret)
12761 drm_atomic_state_free(state);
12762 return ret;
12763 }
12764
12765 static const struct drm_crtc_funcs intel_crtc_funcs = {
12766 .gamma_set = intel_crtc_gamma_set,
12767 .set_config = intel_crtc_set_config,
12768 .destroy = intel_crtc_destroy,
12769 .page_flip = intel_crtc_page_flip,
12770 .atomic_duplicate_state = intel_crtc_duplicate_state,
12771 .atomic_destroy_state = intel_crtc_destroy_state,
12772 };
12773
12774 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12775 struct intel_shared_dpll *pll,
12776 struct intel_dpll_hw_state *hw_state)
12777 {
12778 uint32_t val;
12779
12780 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12781 return false;
12782
12783 val = I915_READ(PCH_DPLL(pll->id));
12784 hw_state->dpll = val;
12785 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12786 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12787
12788 return val & DPLL_VCO_ENABLE;
12789 }
12790
12791 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12792 struct intel_shared_dpll *pll)
12793 {
12794 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12795 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12796 }
12797
12798 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12799 struct intel_shared_dpll *pll)
12800 {
12801 /* PCH refclock must be enabled first */
12802 ibx_assert_pch_refclk_enabled(dev_priv);
12803
12804 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12805
12806 /* Wait for the clocks to stabilize. */
12807 POSTING_READ(PCH_DPLL(pll->id));
12808 udelay(150);
12809
12810 /* The pixel multiplier can only be updated once the
12811 * DPLL is enabled and the clocks are stable.
12812 *
12813 * So write it again.
12814 */
12815 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12816 POSTING_READ(PCH_DPLL(pll->id));
12817 udelay(200);
12818 }
12819
12820 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12821 struct intel_shared_dpll *pll)
12822 {
12823 struct drm_device *dev = dev_priv->dev;
12824 struct intel_crtc *crtc;
12825
12826 /* Make sure no transcoder isn't still depending on us. */
12827 for_each_intel_crtc(dev, crtc) {
12828 if (intel_crtc_to_shared_dpll(crtc) == pll)
12829 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12830 }
12831
12832 I915_WRITE(PCH_DPLL(pll->id), 0);
12833 POSTING_READ(PCH_DPLL(pll->id));
12834 udelay(200);
12835 }
12836
12837 static char *ibx_pch_dpll_names[] = {
12838 "PCH DPLL A",
12839 "PCH DPLL B",
12840 };
12841
12842 static void ibx_pch_dpll_init(struct drm_device *dev)
12843 {
12844 struct drm_i915_private *dev_priv = dev->dev_private;
12845 int i;
12846
12847 dev_priv->num_shared_dpll = 2;
12848
12849 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12850 dev_priv->shared_dplls[i].id = i;
12851 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12852 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12853 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12854 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12855 dev_priv->shared_dplls[i].get_hw_state =
12856 ibx_pch_dpll_get_hw_state;
12857 }
12858 }
12859
12860 static void intel_shared_dpll_init(struct drm_device *dev)
12861 {
12862 struct drm_i915_private *dev_priv = dev->dev_private;
12863
12864 if (HAS_DDI(dev))
12865 intel_ddi_pll_init(dev);
12866 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12867 ibx_pch_dpll_init(dev);
12868 else
12869 dev_priv->num_shared_dpll = 0;
12870
12871 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12872 }
12873
12874 /**
12875 * intel_wm_need_update - Check whether watermarks need updating
12876 * @plane: drm plane
12877 * @state: new plane state
12878 *
12879 * Check current plane state versus the new one to determine whether
12880 * watermarks need to be recalculated.
12881 *
12882 * Returns true or false.
12883 */
12884 bool intel_wm_need_update(struct drm_plane *plane,
12885 struct drm_plane_state *state)
12886 {
12887 /* Update watermarks on tiling changes. */
12888 if (!plane->state->fb || !state->fb ||
12889 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12890 plane->state->rotation != state->rotation)
12891 return true;
12892
12893 return false;
12894 }
12895
12896 /**
12897 * intel_prepare_plane_fb - Prepare fb for usage on plane
12898 * @plane: drm plane to prepare for
12899 * @fb: framebuffer to prepare for presentation
12900 *
12901 * Prepares a framebuffer for usage on a display plane. Generally this
12902 * involves pinning the underlying object and updating the frontbuffer tracking
12903 * bits. Some older platforms need special physical address handling for
12904 * cursor planes.
12905 *
12906 * Returns 0 on success, negative error code on failure.
12907 */
12908 int
12909 intel_prepare_plane_fb(struct drm_plane *plane,
12910 struct drm_framebuffer *fb,
12911 const struct drm_plane_state *new_state)
12912 {
12913 struct drm_device *dev = plane->dev;
12914 struct intel_plane *intel_plane = to_intel_plane(plane);
12915 enum pipe pipe = intel_plane->pipe;
12916 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12917 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12918 unsigned frontbuffer_bits = 0;
12919 int ret = 0;
12920
12921 if (!obj)
12922 return 0;
12923
12924 switch (plane->type) {
12925 case DRM_PLANE_TYPE_PRIMARY:
12926 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12927 break;
12928 case DRM_PLANE_TYPE_CURSOR:
12929 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12930 break;
12931 case DRM_PLANE_TYPE_OVERLAY:
12932 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12933 break;
12934 }
12935
12936 mutex_lock(&dev->struct_mutex);
12937
12938 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12939 INTEL_INFO(dev)->cursor_needs_physical) {
12940 int align = IS_I830(dev) ? 16 * 1024 : 256;
12941 ret = i915_gem_object_attach_phys(obj, align);
12942 if (ret)
12943 DRM_DEBUG_KMS("failed to attach phys object\n");
12944 } else {
12945 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12946 }
12947
12948 if (ret == 0)
12949 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12950
12951 mutex_unlock(&dev->struct_mutex);
12952
12953 return ret;
12954 }
12955
12956 /**
12957 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12958 * @plane: drm plane to clean up for
12959 * @fb: old framebuffer that was on plane
12960 *
12961 * Cleans up a framebuffer that has just been removed from a plane.
12962 */
12963 void
12964 intel_cleanup_plane_fb(struct drm_plane *plane,
12965 struct drm_framebuffer *fb,
12966 const struct drm_plane_state *old_state)
12967 {
12968 struct drm_device *dev = plane->dev;
12969 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12970
12971 if (WARN_ON(!obj))
12972 return;
12973
12974 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12975 !INTEL_INFO(dev)->cursor_needs_physical) {
12976 mutex_lock(&dev->struct_mutex);
12977 intel_unpin_fb_obj(fb, old_state);
12978 mutex_unlock(&dev->struct_mutex);
12979 }
12980 }
12981
12982 int
12983 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12984 {
12985 int max_scale;
12986 struct drm_device *dev;
12987 struct drm_i915_private *dev_priv;
12988 int crtc_clock, cdclk;
12989
12990 if (!intel_crtc || !crtc_state)
12991 return DRM_PLANE_HELPER_NO_SCALING;
12992
12993 dev = intel_crtc->base.dev;
12994 dev_priv = dev->dev_private;
12995 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12996 cdclk = dev_priv->display.get_display_clock_speed(dev);
12997
12998 if (!crtc_clock || !cdclk)
12999 return DRM_PLANE_HELPER_NO_SCALING;
13000
13001 /*
13002 * skl max scale is lower of:
13003 * close to 3 but not 3, -1 is for that purpose
13004 * or
13005 * cdclk/crtc_clock
13006 */
13007 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13008
13009 return max_scale;
13010 }
13011
13012 static int
13013 intel_check_primary_plane(struct drm_plane *plane,
13014 struct intel_plane_state *state)
13015 {
13016 struct drm_device *dev = plane->dev;
13017 struct drm_i915_private *dev_priv = dev->dev_private;
13018 struct drm_crtc *crtc = state->base.crtc;
13019 struct intel_crtc *intel_crtc;
13020 struct intel_crtc_state *crtc_state;
13021 struct drm_framebuffer *fb = state->base.fb;
13022 struct drm_rect *dest = &state->dst;
13023 struct drm_rect *src = &state->src;
13024 const struct drm_rect *clip = &state->clip;
13025 bool can_position = false;
13026 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13027 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13028 int ret;
13029
13030 crtc = crtc ? crtc : plane->crtc;
13031 intel_crtc = to_intel_crtc(crtc);
13032 crtc_state = state->base.state ?
13033 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13034
13035 if (INTEL_INFO(dev)->gen >= 9) {
13036 min_scale = 1;
13037 max_scale = skl_max_scale(intel_crtc, crtc_state);
13038 can_position = true;
13039 }
13040
13041 ret = drm_plane_helper_check_update(plane, crtc, fb,
13042 src, dest, clip,
13043 min_scale,
13044 max_scale,
13045 can_position, true,
13046 &state->visible);
13047 if (ret)
13048 return ret;
13049
13050 if (intel_crtc->active) {
13051 struct intel_plane_state *old_state =
13052 to_intel_plane_state(plane->state);
13053
13054 intel_crtc->atomic.wait_for_flips = true;
13055
13056 /*
13057 * FBC does not work on some platforms for rotated
13058 * planes, so disable it when rotation is not 0 and
13059 * update it when rotation is set back to 0.
13060 *
13061 * FIXME: This is redundant with the fbc update done in
13062 * the primary plane enable function except that that
13063 * one is done too late. We eventually need to unify
13064 * this.
13065 */
13066 if (state->visible &&
13067 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13068 dev_priv->fbc.crtc == intel_crtc &&
13069 state->base.rotation != BIT(DRM_ROTATE_0)) {
13070 intel_crtc->atomic.disable_fbc = true;
13071 }
13072
13073 if (state->visible && !old_state->visible) {
13074 /*
13075 * BDW signals flip done immediately if the plane
13076 * is disabled, even if the plane enable is already
13077 * armed to occur at the next vblank :(
13078 */
13079 if (IS_BROADWELL(dev))
13080 intel_crtc->atomic.wait_vblank = true;
13081 }
13082
13083 intel_crtc->atomic.fb_bits |=
13084 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13085
13086 intel_crtc->atomic.update_fbc = true;
13087
13088 if (intel_wm_need_update(plane, &state->base))
13089 intel_crtc->atomic.update_wm = true;
13090 }
13091
13092 if (INTEL_INFO(dev)->gen >= 9) {
13093 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13094 to_intel_plane(plane), state, 0);
13095 if (ret)
13096 return ret;
13097 }
13098
13099 return 0;
13100 }
13101
13102 static void
13103 intel_commit_primary_plane(struct drm_plane *plane,
13104 struct intel_plane_state *state)
13105 {
13106 struct drm_crtc *crtc = state->base.crtc;
13107 struct drm_framebuffer *fb = state->base.fb;
13108 struct drm_device *dev = plane->dev;
13109 struct drm_i915_private *dev_priv = dev->dev_private;
13110 struct intel_crtc *intel_crtc;
13111 struct drm_rect *src = &state->src;
13112
13113 crtc = crtc ? crtc : plane->crtc;
13114 intel_crtc = to_intel_crtc(crtc);
13115
13116 plane->fb = fb;
13117 crtc->x = src->x1 >> 16;
13118 crtc->y = src->y1 >> 16;
13119
13120 if (intel_crtc->active) {
13121 if (state->visible)
13122 /* FIXME: kill this fastboot hack */
13123 intel_update_pipe_size(intel_crtc);
13124
13125 dev_priv->display.update_primary_plane(crtc, plane->fb,
13126 crtc->x, crtc->y);
13127 }
13128 }
13129
13130 static void
13131 intel_disable_primary_plane(struct drm_plane *plane,
13132 struct drm_crtc *crtc,
13133 bool force)
13134 {
13135 struct drm_device *dev = plane->dev;
13136 struct drm_i915_private *dev_priv = dev->dev_private;
13137
13138 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13139 }
13140
13141 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13142 {
13143 struct drm_device *dev = crtc->dev;
13144 struct drm_i915_private *dev_priv = dev->dev_private;
13145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13146 struct intel_plane *intel_plane;
13147 struct drm_plane *p;
13148 unsigned fb_bits = 0;
13149
13150 /* Track fb's for any planes being disabled */
13151 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13152 intel_plane = to_intel_plane(p);
13153
13154 if (intel_crtc->atomic.disabled_planes &
13155 (1 << drm_plane_index(p))) {
13156 switch (p->type) {
13157 case DRM_PLANE_TYPE_PRIMARY:
13158 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13159 break;
13160 case DRM_PLANE_TYPE_CURSOR:
13161 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13162 break;
13163 case DRM_PLANE_TYPE_OVERLAY:
13164 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13165 break;
13166 }
13167
13168 mutex_lock(&dev->struct_mutex);
13169 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13170 mutex_unlock(&dev->struct_mutex);
13171 }
13172 }
13173
13174 if (intel_crtc->atomic.wait_for_flips)
13175 intel_crtc_wait_for_pending_flips(crtc);
13176
13177 if (intel_crtc->atomic.disable_fbc)
13178 intel_fbc_disable(dev);
13179
13180 if (intel_crtc->atomic.pre_disable_primary)
13181 intel_pre_disable_primary(crtc);
13182
13183 if (intel_crtc->atomic.update_wm)
13184 intel_update_watermarks(crtc);
13185
13186 intel_runtime_pm_get(dev_priv);
13187
13188 /* Perform vblank evasion around commit operation */
13189 if (intel_crtc->active)
13190 intel_crtc->atomic.evade =
13191 intel_pipe_update_start(intel_crtc,
13192 &intel_crtc->atomic.start_vbl_count);
13193 }
13194
13195 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13196 {
13197 struct drm_device *dev = crtc->dev;
13198 struct drm_i915_private *dev_priv = dev->dev_private;
13199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13200 struct drm_plane *p;
13201
13202 if (intel_crtc->atomic.evade)
13203 intel_pipe_update_end(intel_crtc,
13204 intel_crtc->atomic.start_vbl_count);
13205
13206 intel_runtime_pm_put(dev_priv);
13207
13208 if (intel_crtc->atomic.wait_vblank)
13209 intel_wait_for_vblank(dev, intel_crtc->pipe);
13210
13211 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13212
13213 if (intel_crtc->atomic.update_fbc) {
13214 mutex_lock(&dev->struct_mutex);
13215 intel_fbc_update(dev);
13216 mutex_unlock(&dev->struct_mutex);
13217 }
13218
13219 if (intel_crtc->atomic.post_enable_primary)
13220 intel_post_enable_primary(crtc);
13221
13222 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13223 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13224 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13225 false, false);
13226
13227 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13228 }
13229
13230 /**
13231 * intel_plane_destroy - destroy a plane
13232 * @plane: plane to destroy
13233 *
13234 * Common destruction function for all types of planes (primary, cursor,
13235 * sprite).
13236 */
13237 void intel_plane_destroy(struct drm_plane *plane)
13238 {
13239 struct intel_plane *intel_plane = to_intel_plane(plane);
13240 drm_plane_cleanup(plane);
13241 kfree(intel_plane);
13242 }
13243
13244 const struct drm_plane_funcs intel_plane_funcs = {
13245 .update_plane = drm_atomic_helper_update_plane,
13246 .disable_plane = drm_atomic_helper_disable_plane,
13247 .destroy = intel_plane_destroy,
13248 .set_property = drm_atomic_helper_plane_set_property,
13249 .atomic_get_property = intel_plane_atomic_get_property,
13250 .atomic_set_property = intel_plane_atomic_set_property,
13251 .atomic_duplicate_state = intel_plane_duplicate_state,
13252 .atomic_destroy_state = intel_plane_destroy_state,
13253
13254 };
13255
13256 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13257 int pipe)
13258 {
13259 struct intel_plane *primary;
13260 struct intel_plane_state *state;
13261 const uint32_t *intel_primary_formats;
13262 int num_formats;
13263
13264 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13265 if (primary == NULL)
13266 return NULL;
13267
13268 state = intel_create_plane_state(&primary->base);
13269 if (!state) {
13270 kfree(primary);
13271 return NULL;
13272 }
13273 primary->base.state = &state->base;
13274
13275 primary->can_scale = false;
13276 primary->max_downscale = 1;
13277 if (INTEL_INFO(dev)->gen >= 9) {
13278 primary->can_scale = true;
13279 state->scaler_id = -1;
13280 }
13281 primary->pipe = pipe;
13282 primary->plane = pipe;
13283 primary->check_plane = intel_check_primary_plane;
13284 primary->commit_plane = intel_commit_primary_plane;
13285 primary->disable_plane = intel_disable_primary_plane;
13286 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13287 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13288 primary->plane = !pipe;
13289
13290 if (INTEL_INFO(dev)->gen <= 3) {
13291 intel_primary_formats = i8xx_primary_formats;
13292 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13293 } else {
13294 intel_primary_formats = i965_primary_formats;
13295 num_formats = ARRAY_SIZE(i965_primary_formats);
13296 }
13297
13298 drm_universal_plane_init(dev, &primary->base, 0,
13299 &intel_plane_funcs,
13300 intel_primary_formats, num_formats,
13301 DRM_PLANE_TYPE_PRIMARY);
13302
13303 if (INTEL_INFO(dev)->gen >= 4)
13304 intel_create_rotation_property(dev, primary);
13305
13306 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13307
13308 return &primary->base;
13309 }
13310
13311 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13312 {
13313 if (!dev->mode_config.rotation_property) {
13314 unsigned long flags = BIT(DRM_ROTATE_0) |
13315 BIT(DRM_ROTATE_180);
13316
13317 if (INTEL_INFO(dev)->gen >= 9)
13318 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13319
13320 dev->mode_config.rotation_property =
13321 drm_mode_create_rotation_property(dev, flags);
13322 }
13323 if (dev->mode_config.rotation_property)
13324 drm_object_attach_property(&plane->base.base,
13325 dev->mode_config.rotation_property,
13326 plane->base.state->rotation);
13327 }
13328
13329 static int
13330 intel_check_cursor_plane(struct drm_plane *plane,
13331 struct intel_plane_state *state)
13332 {
13333 struct drm_crtc *crtc = state->base.crtc;
13334 struct drm_device *dev = plane->dev;
13335 struct drm_framebuffer *fb = state->base.fb;
13336 struct drm_rect *dest = &state->dst;
13337 struct drm_rect *src = &state->src;
13338 const struct drm_rect *clip = &state->clip;
13339 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13340 struct intel_crtc *intel_crtc;
13341 unsigned stride;
13342 int ret;
13343
13344 crtc = crtc ? crtc : plane->crtc;
13345 intel_crtc = to_intel_crtc(crtc);
13346
13347 ret = drm_plane_helper_check_update(plane, crtc, fb,
13348 src, dest, clip,
13349 DRM_PLANE_HELPER_NO_SCALING,
13350 DRM_PLANE_HELPER_NO_SCALING,
13351 true, true, &state->visible);
13352 if (ret)
13353 return ret;
13354
13355
13356 /* if we want to turn off the cursor ignore width and height */
13357 if (!obj)
13358 goto finish;
13359
13360 /* Check for which cursor types we support */
13361 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13362 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13363 state->base.crtc_w, state->base.crtc_h);
13364 return -EINVAL;
13365 }
13366
13367 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13368 if (obj->base.size < stride * state->base.crtc_h) {
13369 DRM_DEBUG_KMS("buffer is too small\n");
13370 return -ENOMEM;
13371 }
13372
13373 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13374 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13375 ret = -EINVAL;
13376 }
13377
13378 finish:
13379 if (intel_crtc->active) {
13380 if (plane->state->crtc_w != state->base.crtc_w)
13381 intel_crtc->atomic.update_wm = true;
13382
13383 intel_crtc->atomic.fb_bits |=
13384 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13385 }
13386
13387 return ret;
13388 }
13389
13390 static void
13391 intel_disable_cursor_plane(struct drm_plane *plane,
13392 struct drm_crtc *crtc,
13393 bool force)
13394 {
13395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13396
13397 if (!force) {
13398 plane->fb = NULL;
13399 intel_crtc->cursor_bo = NULL;
13400 intel_crtc->cursor_addr = 0;
13401 }
13402
13403 intel_crtc_update_cursor(crtc, false);
13404 }
13405
13406 static void
13407 intel_commit_cursor_plane(struct drm_plane *plane,
13408 struct intel_plane_state *state)
13409 {
13410 struct drm_crtc *crtc = state->base.crtc;
13411 struct drm_device *dev = plane->dev;
13412 struct intel_crtc *intel_crtc;
13413 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13414 uint32_t addr;
13415
13416 crtc = crtc ? crtc : plane->crtc;
13417 intel_crtc = to_intel_crtc(crtc);
13418
13419 plane->fb = state->base.fb;
13420 crtc->cursor_x = state->base.crtc_x;
13421 crtc->cursor_y = state->base.crtc_y;
13422
13423 if (intel_crtc->cursor_bo == obj)
13424 goto update;
13425
13426 if (!obj)
13427 addr = 0;
13428 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13429 addr = i915_gem_obj_ggtt_offset(obj);
13430 else
13431 addr = obj->phys_handle->busaddr;
13432
13433 intel_crtc->cursor_addr = addr;
13434 intel_crtc->cursor_bo = obj;
13435 update:
13436
13437 if (intel_crtc->active)
13438 intel_crtc_update_cursor(crtc, state->visible);
13439 }
13440
13441 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13442 int pipe)
13443 {
13444 struct intel_plane *cursor;
13445 struct intel_plane_state *state;
13446
13447 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13448 if (cursor == NULL)
13449 return NULL;
13450
13451 state = intel_create_plane_state(&cursor->base);
13452 if (!state) {
13453 kfree(cursor);
13454 return NULL;
13455 }
13456 cursor->base.state = &state->base;
13457
13458 cursor->can_scale = false;
13459 cursor->max_downscale = 1;
13460 cursor->pipe = pipe;
13461 cursor->plane = pipe;
13462 cursor->check_plane = intel_check_cursor_plane;
13463 cursor->commit_plane = intel_commit_cursor_plane;
13464 cursor->disable_plane = intel_disable_cursor_plane;
13465
13466 drm_universal_plane_init(dev, &cursor->base, 0,
13467 &intel_plane_funcs,
13468 intel_cursor_formats,
13469 ARRAY_SIZE(intel_cursor_formats),
13470 DRM_PLANE_TYPE_CURSOR);
13471
13472 if (INTEL_INFO(dev)->gen >= 4) {
13473 if (!dev->mode_config.rotation_property)
13474 dev->mode_config.rotation_property =
13475 drm_mode_create_rotation_property(dev,
13476 BIT(DRM_ROTATE_0) |
13477 BIT(DRM_ROTATE_180));
13478 if (dev->mode_config.rotation_property)
13479 drm_object_attach_property(&cursor->base.base,
13480 dev->mode_config.rotation_property,
13481 state->base.rotation);
13482 }
13483
13484 if (INTEL_INFO(dev)->gen >=9)
13485 state->scaler_id = -1;
13486
13487 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13488
13489 return &cursor->base;
13490 }
13491
13492 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13493 struct intel_crtc_state *crtc_state)
13494 {
13495 int i;
13496 struct intel_scaler *intel_scaler;
13497 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13498
13499 for (i = 0; i < intel_crtc->num_scalers; i++) {
13500 intel_scaler = &scaler_state->scalers[i];
13501 intel_scaler->in_use = 0;
13502 intel_scaler->id = i;
13503
13504 intel_scaler->mode = PS_SCALER_MODE_DYN;
13505 }
13506
13507 scaler_state->scaler_id = -1;
13508 }
13509
13510 static void intel_crtc_init(struct drm_device *dev, int pipe)
13511 {
13512 struct drm_i915_private *dev_priv = dev->dev_private;
13513 struct intel_crtc *intel_crtc;
13514 struct intel_crtc_state *crtc_state = NULL;
13515 struct drm_plane *primary = NULL;
13516 struct drm_plane *cursor = NULL;
13517 int i, ret;
13518
13519 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13520 if (intel_crtc == NULL)
13521 return;
13522
13523 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13524 if (!crtc_state)
13525 goto fail;
13526 intel_crtc->config = crtc_state;
13527 intel_crtc->base.state = &crtc_state->base;
13528 crtc_state->base.crtc = &intel_crtc->base;
13529
13530 /* initialize shared scalers */
13531 if (INTEL_INFO(dev)->gen >= 9) {
13532 if (pipe == PIPE_C)
13533 intel_crtc->num_scalers = 1;
13534 else
13535 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13536
13537 skl_init_scalers(dev, intel_crtc, crtc_state);
13538 }
13539
13540 primary = intel_primary_plane_create(dev, pipe);
13541 if (!primary)
13542 goto fail;
13543
13544 cursor = intel_cursor_plane_create(dev, pipe);
13545 if (!cursor)
13546 goto fail;
13547
13548 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13549 cursor, &intel_crtc_funcs);
13550 if (ret)
13551 goto fail;
13552
13553 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13554 for (i = 0; i < 256; i++) {
13555 intel_crtc->lut_r[i] = i;
13556 intel_crtc->lut_g[i] = i;
13557 intel_crtc->lut_b[i] = i;
13558 }
13559
13560 /*
13561 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13562 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13563 */
13564 intel_crtc->pipe = pipe;
13565 intel_crtc->plane = pipe;
13566 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13567 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13568 intel_crtc->plane = !pipe;
13569 }
13570
13571 intel_crtc->cursor_base = ~0;
13572 intel_crtc->cursor_cntl = ~0;
13573 intel_crtc->cursor_size = ~0;
13574
13575 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13576 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13577 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13578 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13579
13580 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13581
13582 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13583 return;
13584
13585 fail:
13586 if (primary)
13587 drm_plane_cleanup(primary);
13588 if (cursor)
13589 drm_plane_cleanup(cursor);
13590 kfree(crtc_state);
13591 kfree(intel_crtc);
13592 }
13593
13594 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13595 {
13596 struct drm_encoder *encoder = connector->base.encoder;
13597 struct drm_device *dev = connector->base.dev;
13598
13599 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13600
13601 if (!encoder || WARN_ON(!encoder->crtc))
13602 return INVALID_PIPE;
13603
13604 return to_intel_crtc(encoder->crtc)->pipe;
13605 }
13606
13607 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13608 struct drm_file *file)
13609 {
13610 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13611 struct drm_crtc *drmmode_crtc;
13612 struct intel_crtc *crtc;
13613
13614 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13615
13616 if (!drmmode_crtc) {
13617 DRM_ERROR("no such CRTC id\n");
13618 return -ENOENT;
13619 }
13620
13621 crtc = to_intel_crtc(drmmode_crtc);
13622 pipe_from_crtc_id->pipe = crtc->pipe;
13623
13624 return 0;
13625 }
13626
13627 static int intel_encoder_clones(struct intel_encoder *encoder)
13628 {
13629 struct drm_device *dev = encoder->base.dev;
13630 struct intel_encoder *source_encoder;
13631 int index_mask = 0;
13632 int entry = 0;
13633
13634 for_each_intel_encoder(dev, source_encoder) {
13635 if (encoders_cloneable(encoder, source_encoder))
13636 index_mask |= (1 << entry);
13637
13638 entry++;
13639 }
13640
13641 return index_mask;
13642 }
13643
13644 static bool has_edp_a(struct drm_device *dev)
13645 {
13646 struct drm_i915_private *dev_priv = dev->dev_private;
13647
13648 if (!IS_MOBILE(dev))
13649 return false;
13650
13651 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13652 return false;
13653
13654 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13655 return false;
13656
13657 return true;
13658 }
13659
13660 static bool intel_crt_present(struct drm_device *dev)
13661 {
13662 struct drm_i915_private *dev_priv = dev->dev_private;
13663
13664 if (INTEL_INFO(dev)->gen >= 9)
13665 return false;
13666
13667 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13668 return false;
13669
13670 if (IS_CHERRYVIEW(dev))
13671 return false;
13672
13673 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13674 return false;
13675
13676 return true;
13677 }
13678
13679 static void intel_setup_outputs(struct drm_device *dev)
13680 {
13681 struct drm_i915_private *dev_priv = dev->dev_private;
13682 struct intel_encoder *encoder;
13683 bool dpd_is_edp = false;
13684
13685 intel_lvds_init(dev);
13686
13687 if (intel_crt_present(dev))
13688 intel_crt_init(dev);
13689
13690 if (IS_BROXTON(dev)) {
13691 /*
13692 * FIXME: Broxton doesn't support port detection via the
13693 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13694 * detect the ports.
13695 */
13696 intel_ddi_init(dev, PORT_A);
13697 intel_ddi_init(dev, PORT_B);
13698 intel_ddi_init(dev, PORT_C);
13699 } else if (HAS_DDI(dev)) {
13700 int found;
13701
13702 /*
13703 * Haswell uses DDI functions to detect digital outputs.
13704 * On SKL pre-D0 the strap isn't connected, so we assume
13705 * it's there.
13706 */
13707 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13708 /* WaIgnoreDDIAStrap: skl */
13709 if (found ||
13710 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13711 intel_ddi_init(dev, PORT_A);
13712
13713 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13714 * register */
13715 found = I915_READ(SFUSE_STRAP);
13716
13717 if (found & SFUSE_STRAP_DDIB_DETECTED)
13718 intel_ddi_init(dev, PORT_B);
13719 if (found & SFUSE_STRAP_DDIC_DETECTED)
13720 intel_ddi_init(dev, PORT_C);
13721 if (found & SFUSE_STRAP_DDID_DETECTED)
13722 intel_ddi_init(dev, PORT_D);
13723 } else if (HAS_PCH_SPLIT(dev)) {
13724 int found;
13725 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13726
13727 if (has_edp_a(dev))
13728 intel_dp_init(dev, DP_A, PORT_A);
13729
13730 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13731 /* PCH SDVOB multiplex with HDMIB */
13732 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13733 if (!found)
13734 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13735 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13736 intel_dp_init(dev, PCH_DP_B, PORT_B);
13737 }
13738
13739 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13740 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13741
13742 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13743 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13744
13745 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13746 intel_dp_init(dev, PCH_DP_C, PORT_C);
13747
13748 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13749 intel_dp_init(dev, PCH_DP_D, PORT_D);
13750 } else if (IS_VALLEYVIEW(dev)) {
13751 /*
13752 * The DP_DETECTED bit is the latched state of the DDC
13753 * SDA pin at boot. However since eDP doesn't require DDC
13754 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13755 * eDP ports may have been muxed to an alternate function.
13756 * Thus we can't rely on the DP_DETECTED bit alone to detect
13757 * eDP ports. Consult the VBT as well as DP_DETECTED to
13758 * detect eDP ports.
13759 */
13760 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13761 !intel_dp_is_edp(dev, PORT_B))
13762 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13763 PORT_B);
13764 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13765 intel_dp_is_edp(dev, PORT_B))
13766 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13767
13768 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13769 !intel_dp_is_edp(dev, PORT_C))
13770 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13771 PORT_C);
13772 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13773 intel_dp_is_edp(dev, PORT_C))
13774 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13775
13776 if (IS_CHERRYVIEW(dev)) {
13777 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13778 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13779 PORT_D);
13780 /* eDP not supported on port D, so don't check VBT */
13781 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13782 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13783 }
13784
13785 intel_dsi_init(dev);
13786 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13787 bool found = false;
13788
13789 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13790 DRM_DEBUG_KMS("probing SDVOB\n");
13791 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13792 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13793 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13794 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13795 }
13796
13797 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13798 intel_dp_init(dev, DP_B, PORT_B);
13799 }
13800
13801 /* Before G4X SDVOC doesn't have its own detect register */
13802
13803 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13804 DRM_DEBUG_KMS("probing SDVOC\n");
13805 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13806 }
13807
13808 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13809
13810 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13811 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13812 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13813 }
13814 if (SUPPORTS_INTEGRATED_DP(dev))
13815 intel_dp_init(dev, DP_C, PORT_C);
13816 }
13817
13818 if (SUPPORTS_INTEGRATED_DP(dev) &&
13819 (I915_READ(DP_D) & DP_DETECTED))
13820 intel_dp_init(dev, DP_D, PORT_D);
13821 } else if (IS_GEN2(dev))
13822 intel_dvo_init(dev);
13823
13824 if (SUPPORTS_TV(dev))
13825 intel_tv_init(dev);
13826
13827 intel_psr_init(dev);
13828
13829 for_each_intel_encoder(dev, encoder) {
13830 encoder->base.possible_crtcs = encoder->crtc_mask;
13831 encoder->base.possible_clones =
13832 intel_encoder_clones(encoder);
13833 }
13834
13835 intel_init_pch_refclk(dev);
13836
13837 drm_helper_move_panel_connectors_to_head(dev);
13838 }
13839
13840 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13841 {
13842 struct drm_device *dev = fb->dev;
13843 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13844
13845 drm_framebuffer_cleanup(fb);
13846 mutex_lock(&dev->struct_mutex);
13847 WARN_ON(!intel_fb->obj->framebuffer_references--);
13848 drm_gem_object_unreference(&intel_fb->obj->base);
13849 mutex_unlock(&dev->struct_mutex);
13850 kfree(intel_fb);
13851 }
13852
13853 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13854 struct drm_file *file,
13855 unsigned int *handle)
13856 {
13857 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13858 struct drm_i915_gem_object *obj = intel_fb->obj;
13859
13860 return drm_gem_handle_create(file, &obj->base, handle);
13861 }
13862
13863 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13864 .destroy = intel_user_framebuffer_destroy,
13865 .create_handle = intel_user_framebuffer_create_handle,
13866 };
13867
13868 static
13869 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13870 uint32_t pixel_format)
13871 {
13872 u32 gen = INTEL_INFO(dev)->gen;
13873
13874 if (gen >= 9) {
13875 /* "The stride in bytes must not exceed the of the size of 8K
13876 * pixels and 32K bytes."
13877 */
13878 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13879 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13880 return 32*1024;
13881 } else if (gen >= 4) {
13882 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13883 return 16*1024;
13884 else
13885 return 32*1024;
13886 } else if (gen >= 3) {
13887 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13888 return 8*1024;
13889 else
13890 return 16*1024;
13891 } else {
13892 /* XXX DSPC is limited to 4k tiled */
13893 return 8*1024;
13894 }
13895 }
13896
13897 static int intel_framebuffer_init(struct drm_device *dev,
13898 struct intel_framebuffer *intel_fb,
13899 struct drm_mode_fb_cmd2 *mode_cmd,
13900 struct drm_i915_gem_object *obj)
13901 {
13902 unsigned int aligned_height;
13903 int ret;
13904 u32 pitch_limit, stride_alignment;
13905
13906 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13907
13908 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13909 /* Enforce that fb modifier and tiling mode match, but only for
13910 * X-tiled. This is needed for FBC. */
13911 if (!!(obj->tiling_mode == I915_TILING_X) !=
13912 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13913 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13914 return -EINVAL;
13915 }
13916 } else {
13917 if (obj->tiling_mode == I915_TILING_X)
13918 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13919 else if (obj->tiling_mode == I915_TILING_Y) {
13920 DRM_DEBUG("No Y tiling for legacy addfb\n");
13921 return -EINVAL;
13922 }
13923 }
13924
13925 /* Passed in modifier sanity checking. */
13926 switch (mode_cmd->modifier[0]) {
13927 case I915_FORMAT_MOD_Y_TILED:
13928 case I915_FORMAT_MOD_Yf_TILED:
13929 if (INTEL_INFO(dev)->gen < 9) {
13930 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13931 mode_cmd->modifier[0]);
13932 return -EINVAL;
13933 }
13934 case DRM_FORMAT_MOD_NONE:
13935 case I915_FORMAT_MOD_X_TILED:
13936 break;
13937 default:
13938 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13939 mode_cmd->modifier[0]);
13940 return -EINVAL;
13941 }
13942
13943 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13944 mode_cmd->pixel_format);
13945 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13946 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13947 mode_cmd->pitches[0], stride_alignment);
13948 return -EINVAL;
13949 }
13950
13951 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13952 mode_cmd->pixel_format);
13953 if (mode_cmd->pitches[0] > pitch_limit) {
13954 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13955 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13956 "tiled" : "linear",
13957 mode_cmd->pitches[0], pitch_limit);
13958 return -EINVAL;
13959 }
13960
13961 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13962 mode_cmd->pitches[0] != obj->stride) {
13963 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13964 mode_cmd->pitches[0], obj->stride);
13965 return -EINVAL;
13966 }
13967
13968 /* Reject formats not supported by any plane early. */
13969 switch (mode_cmd->pixel_format) {
13970 case DRM_FORMAT_C8:
13971 case DRM_FORMAT_RGB565:
13972 case DRM_FORMAT_XRGB8888:
13973 case DRM_FORMAT_ARGB8888:
13974 break;
13975 case DRM_FORMAT_XRGB1555:
13976 case DRM_FORMAT_ARGB1555:
13977 if (INTEL_INFO(dev)->gen > 3) {
13978 DRM_DEBUG("unsupported pixel format: %s\n",
13979 drm_get_format_name(mode_cmd->pixel_format));
13980 return -EINVAL;
13981 }
13982 break;
13983 case DRM_FORMAT_XBGR8888:
13984 case DRM_FORMAT_ABGR8888:
13985 case DRM_FORMAT_XRGB2101010:
13986 case DRM_FORMAT_ARGB2101010:
13987 case DRM_FORMAT_XBGR2101010:
13988 case DRM_FORMAT_ABGR2101010:
13989 if (INTEL_INFO(dev)->gen < 4) {
13990 DRM_DEBUG("unsupported pixel format: %s\n",
13991 drm_get_format_name(mode_cmd->pixel_format));
13992 return -EINVAL;
13993 }
13994 break;
13995 case DRM_FORMAT_YUYV:
13996 case DRM_FORMAT_UYVY:
13997 case DRM_FORMAT_YVYU:
13998 case DRM_FORMAT_VYUY:
13999 if (INTEL_INFO(dev)->gen < 5) {
14000 DRM_DEBUG("unsupported pixel format: %s\n",
14001 drm_get_format_name(mode_cmd->pixel_format));
14002 return -EINVAL;
14003 }
14004 break;
14005 default:
14006 DRM_DEBUG("unsupported pixel format: %s\n",
14007 drm_get_format_name(mode_cmd->pixel_format));
14008 return -EINVAL;
14009 }
14010
14011 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14012 if (mode_cmd->offsets[0] != 0)
14013 return -EINVAL;
14014
14015 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14016 mode_cmd->pixel_format,
14017 mode_cmd->modifier[0]);
14018 /* FIXME drm helper for size checks (especially planar formats)? */
14019 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14020 return -EINVAL;
14021
14022 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14023 intel_fb->obj = obj;
14024 intel_fb->obj->framebuffer_references++;
14025
14026 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14027 if (ret) {
14028 DRM_ERROR("framebuffer init failed %d\n", ret);
14029 return ret;
14030 }
14031
14032 return 0;
14033 }
14034
14035 static struct drm_framebuffer *
14036 intel_user_framebuffer_create(struct drm_device *dev,
14037 struct drm_file *filp,
14038 struct drm_mode_fb_cmd2 *mode_cmd)
14039 {
14040 struct drm_i915_gem_object *obj;
14041
14042 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14043 mode_cmd->handles[0]));
14044 if (&obj->base == NULL)
14045 return ERR_PTR(-ENOENT);
14046
14047 return intel_framebuffer_create(dev, mode_cmd, obj);
14048 }
14049
14050 #ifndef CONFIG_DRM_I915_FBDEV
14051 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14052 {
14053 }
14054 #endif
14055
14056 static const struct drm_mode_config_funcs intel_mode_funcs = {
14057 .fb_create = intel_user_framebuffer_create,
14058 .output_poll_changed = intel_fbdev_output_poll_changed,
14059 .atomic_check = intel_atomic_check,
14060 .atomic_commit = intel_atomic_commit,
14061 };
14062
14063 /* Set up chip specific display functions */
14064 static void intel_init_display(struct drm_device *dev)
14065 {
14066 struct drm_i915_private *dev_priv = dev->dev_private;
14067
14068 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14069 dev_priv->display.find_dpll = g4x_find_best_dpll;
14070 else if (IS_CHERRYVIEW(dev))
14071 dev_priv->display.find_dpll = chv_find_best_dpll;
14072 else if (IS_VALLEYVIEW(dev))
14073 dev_priv->display.find_dpll = vlv_find_best_dpll;
14074 else if (IS_PINEVIEW(dev))
14075 dev_priv->display.find_dpll = pnv_find_best_dpll;
14076 else
14077 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14078
14079 if (INTEL_INFO(dev)->gen >= 9) {
14080 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14081 dev_priv->display.get_initial_plane_config =
14082 skylake_get_initial_plane_config;
14083 dev_priv->display.crtc_compute_clock =
14084 haswell_crtc_compute_clock;
14085 dev_priv->display.crtc_enable = haswell_crtc_enable;
14086 dev_priv->display.crtc_disable = haswell_crtc_disable;
14087 dev_priv->display.off = ironlake_crtc_off;
14088 dev_priv->display.update_primary_plane =
14089 skylake_update_primary_plane;
14090 } else if (HAS_DDI(dev)) {
14091 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14092 dev_priv->display.get_initial_plane_config =
14093 ironlake_get_initial_plane_config;
14094 dev_priv->display.crtc_compute_clock =
14095 haswell_crtc_compute_clock;
14096 dev_priv->display.crtc_enable = haswell_crtc_enable;
14097 dev_priv->display.crtc_disable = haswell_crtc_disable;
14098 dev_priv->display.off = ironlake_crtc_off;
14099 dev_priv->display.update_primary_plane =
14100 ironlake_update_primary_plane;
14101 } else if (HAS_PCH_SPLIT(dev)) {
14102 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14103 dev_priv->display.get_initial_plane_config =
14104 ironlake_get_initial_plane_config;
14105 dev_priv->display.crtc_compute_clock =
14106 ironlake_crtc_compute_clock;
14107 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14108 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14109 dev_priv->display.off = ironlake_crtc_off;
14110 dev_priv->display.update_primary_plane =
14111 ironlake_update_primary_plane;
14112 } else if (IS_VALLEYVIEW(dev)) {
14113 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14114 dev_priv->display.get_initial_plane_config =
14115 i9xx_get_initial_plane_config;
14116 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14117 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14118 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14119 dev_priv->display.off = i9xx_crtc_off;
14120 dev_priv->display.update_primary_plane =
14121 i9xx_update_primary_plane;
14122 } else {
14123 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14124 dev_priv->display.get_initial_plane_config =
14125 i9xx_get_initial_plane_config;
14126 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14127 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14128 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14129 dev_priv->display.off = i9xx_crtc_off;
14130 dev_priv->display.update_primary_plane =
14131 i9xx_update_primary_plane;
14132 }
14133
14134 /* Returns the core display clock speed */
14135 if (IS_SKYLAKE(dev))
14136 dev_priv->display.get_display_clock_speed =
14137 skylake_get_display_clock_speed;
14138 else if (IS_BROADWELL(dev))
14139 dev_priv->display.get_display_clock_speed =
14140 broadwell_get_display_clock_speed;
14141 else if (IS_HASWELL(dev))
14142 dev_priv->display.get_display_clock_speed =
14143 haswell_get_display_clock_speed;
14144 else if (IS_VALLEYVIEW(dev))
14145 dev_priv->display.get_display_clock_speed =
14146 valleyview_get_display_clock_speed;
14147 else if (IS_GEN5(dev))
14148 dev_priv->display.get_display_clock_speed =
14149 ilk_get_display_clock_speed;
14150 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14151 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14152 dev_priv->display.get_display_clock_speed =
14153 i945_get_display_clock_speed;
14154 else if (IS_I915G(dev))
14155 dev_priv->display.get_display_clock_speed =
14156 i915_get_display_clock_speed;
14157 else if (IS_I945GM(dev) || IS_845G(dev))
14158 dev_priv->display.get_display_clock_speed =
14159 i9xx_misc_get_display_clock_speed;
14160 else if (IS_PINEVIEW(dev))
14161 dev_priv->display.get_display_clock_speed =
14162 pnv_get_display_clock_speed;
14163 else if (IS_I915GM(dev))
14164 dev_priv->display.get_display_clock_speed =
14165 i915gm_get_display_clock_speed;
14166 else if (IS_I865G(dev))
14167 dev_priv->display.get_display_clock_speed =
14168 i865_get_display_clock_speed;
14169 else if (IS_I85X(dev))
14170 dev_priv->display.get_display_clock_speed =
14171 i855_get_display_clock_speed;
14172 else /* 852, 830 */
14173 dev_priv->display.get_display_clock_speed =
14174 i830_get_display_clock_speed;
14175
14176 if (IS_GEN5(dev)) {
14177 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14178 } else if (IS_GEN6(dev)) {
14179 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14180 } else if (IS_IVYBRIDGE(dev)) {
14181 /* FIXME: detect B0+ stepping and use auto training */
14182 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14183 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14184 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14185 } else if (IS_VALLEYVIEW(dev)) {
14186 dev_priv->display.modeset_global_resources =
14187 valleyview_modeset_global_resources;
14188 } else if (IS_BROXTON(dev)) {
14189 dev_priv->display.modeset_global_resources =
14190 broxton_modeset_global_resources;
14191 }
14192
14193 switch (INTEL_INFO(dev)->gen) {
14194 case 2:
14195 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14196 break;
14197
14198 case 3:
14199 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14200 break;
14201
14202 case 4:
14203 case 5:
14204 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14205 break;
14206
14207 case 6:
14208 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14209 break;
14210 case 7:
14211 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14212 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14213 break;
14214 case 9:
14215 /* Drop through - unsupported since execlist only. */
14216 default:
14217 /* Default just returns -ENODEV to indicate unsupported */
14218 dev_priv->display.queue_flip = intel_default_queue_flip;
14219 }
14220
14221 intel_panel_init_backlight_funcs(dev);
14222
14223 mutex_init(&dev_priv->pps_mutex);
14224 }
14225
14226 /*
14227 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14228 * resume, or other times. This quirk makes sure that's the case for
14229 * affected systems.
14230 */
14231 static void quirk_pipea_force(struct drm_device *dev)
14232 {
14233 struct drm_i915_private *dev_priv = dev->dev_private;
14234
14235 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14236 DRM_INFO("applying pipe a force quirk\n");
14237 }
14238
14239 static void quirk_pipeb_force(struct drm_device *dev)
14240 {
14241 struct drm_i915_private *dev_priv = dev->dev_private;
14242
14243 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14244 DRM_INFO("applying pipe b force quirk\n");
14245 }
14246
14247 /*
14248 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14249 */
14250 static void quirk_ssc_force_disable(struct drm_device *dev)
14251 {
14252 struct drm_i915_private *dev_priv = dev->dev_private;
14253 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14254 DRM_INFO("applying lvds SSC disable quirk\n");
14255 }
14256
14257 /*
14258 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14259 * brightness value
14260 */
14261 static void quirk_invert_brightness(struct drm_device *dev)
14262 {
14263 struct drm_i915_private *dev_priv = dev->dev_private;
14264 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14265 DRM_INFO("applying inverted panel brightness quirk\n");
14266 }
14267
14268 /* Some VBT's incorrectly indicate no backlight is present */
14269 static void quirk_backlight_present(struct drm_device *dev)
14270 {
14271 struct drm_i915_private *dev_priv = dev->dev_private;
14272 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14273 DRM_INFO("applying backlight present quirk\n");
14274 }
14275
14276 struct intel_quirk {
14277 int device;
14278 int subsystem_vendor;
14279 int subsystem_device;
14280 void (*hook)(struct drm_device *dev);
14281 };
14282
14283 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14284 struct intel_dmi_quirk {
14285 void (*hook)(struct drm_device *dev);
14286 const struct dmi_system_id (*dmi_id_list)[];
14287 };
14288
14289 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14290 {
14291 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14292 return 1;
14293 }
14294
14295 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14296 {
14297 .dmi_id_list = &(const struct dmi_system_id[]) {
14298 {
14299 .callback = intel_dmi_reverse_brightness,
14300 .ident = "NCR Corporation",
14301 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14302 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14303 },
14304 },
14305 { } /* terminating entry */
14306 },
14307 .hook = quirk_invert_brightness,
14308 },
14309 };
14310
14311 static struct intel_quirk intel_quirks[] = {
14312 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14313 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14314
14315 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14316 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14317
14318 /* 830 needs to leave pipe A & dpll A up */
14319 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14320
14321 /* 830 needs to leave pipe B & dpll B up */
14322 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14323
14324 /* Lenovo U160 cannot use SSC on LVDS */
14325 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14326
14327 /* Sony Vaio Y cannot use SSC on LVDS */
14328 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14329
14330 /* Acer Aspire 5734Z must invert backlight brightness */
14331 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14332
14333 /* Acer/eMachines G725 */
14334 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14335
14336 /* Acer/eMachines e725 */
14337 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14338
14339 /* Acer/Packard Bell NCL20 */
14340 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14341
14342 /* Acer Aspire 4736Z */
14343 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14344
14345 /* Acer Aspire 5336 */
14346 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14347
14348 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14349 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14350
14351 /* Acer C720 Chromebook (Core i3 4005U) */
14352 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14353
14354 /* Apple Macbook 2,1 (Core 2 T7400) */
14355 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14356
14357 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14358 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14359
14360 /* HP Chromebook 14 (Celeron 2955U) */
14361 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14362
14363 /* Dell Chromebook 11 */
14364 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14365 };
14366
14367 static void intel_init_quirks(struct drm_device *dev)
14368 {
14369 struct pci_dev *d = dev->pdev;
14370 int i;
14371
14372 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14373 struct intel_quirk *q = &intel_quirks[i];
14374
14375 if (d->device == q->device &&
14376 (d->subsystem_vendor == q->subsystem_vendor ||
14377 q->subsystem_vendor == PCI_ANY_ID) &&
14378 (d->subsystem_device == q->subsystem_device ||
14379 q->subsystem_device == PCI_ANY_ID))
14380 q->hook(dev);
14381 }
14382 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14383 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14384 intel_dmi_quirks[i].hook(dev);
14385 }
14386 }
14387
14388 /* Disable the VGA plane that we never use */
14389 static void i915_disable_vga(struct drm_device *dev)
14390 {
14391 struct drm_i915_private *dev_priv = dev->dev_private;
14392 u8 sr1;
14393 u32 vga_reg = i915_vgacntrl_reg(dev);
14394
14395 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14396 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14397 outb(SR01, VGA_SR_INDEX);
14398 sr1 = inb(VGA_SR_DATA);
14399 outb(sr1 | 1<<5, VGA_SR_DATA);
14400 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14401 udelay(300);
14402
14403 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14404 POSTING_READ(vga_reg);
14405 }
14406
14407 void intel_modeset_init_hw(struct drm_device *dev)
14408 {
14409 intel_prepare_ddi(dev);
14410
14411 if (IS_VALLEYVIEW(dev))
14412 vlv_update_cdclk(dev);
14413
14414 intel_init_clock_gating(dev);
14415
14416 intel_enable_gt_powersave(dev);
14417 }
14418
14419 void intel_modeset_init(struct drm_device *dev)
14420 {
14421 struct drm_i915_private *dev_priv = dev->dev_private;
14422 int sprite, ret;
14423 enum pipe pipe;
14424 struct intel_crtc *crtc;
14425
14426 drm_mode_config_init(dev);
14427
14428 dev->mode_config.min_width = 0;
14429 dev->mode_config.min_height = 0;
14430
14431 dev->mode_config.preferred_depth = 24;
14432 dev->mode_config.prefer_shadow = 1;
14433
14434 dev->mode_config.allow_fb_modifiers = true;
14435
14436 dev->mode_config.funcs = &intel_mode_funcs;
14437
14438 intel_init_quirks(dev);
14439
14440 intel_init_pm(dev);
14441
14442 if (INTEL_INFO(dev)->num_pipes == 0)
14443 return;
14444
14445 intel_init_display(dev);
14446 intel_init_audio(dev);
14447
14448 if (IS_GEN2(dev)) {
14449 dev->mode_config.max_width = 2048;
14450 dev->mode_config.max_height = 2048;
14451 } else if (IS_GEN3(dev)) {
14452 dev->mode_config.max_width = 4096;
14453 dev->mode_config.max_height = 4096;
14454 } else {
14455 dev->mode_config.max_width = 8192;
14456 dev->mode_config.max_height = 8192;
14457 }
14458
14459 if (IS_845G(dev) || IS_I865G(dev)) {
14460 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14461 dev->mode_config.cursor_height = 1023;
14462 } else if (IS_GEN2(dev)) {
14463 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14464 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14465 } else {
14466 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14467 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14468 }
14469
14470 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14471
14472 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14473 INTEL_INFO(dev)->num_pipes,
14474 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14475
14476 for_each_pipe(dev_priv, pipe) {
14477 intel_crtc_init(dev, pipe);
14478 for_each_sprite(dev_priv, pipe, sprite) {
14479 ret = intel_plane_init(dev, pipe, sprite);
14480 if (ret)
14481 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14482 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14483 }
14484 }
14485
14486 intel_init_dpio(dev);
14487
14488 intel_shared_dpll_init(dev);
14489
14490 /* Just disable it once at startup */
14491 i915_disable_vga(dev);
14492 intel_setup_outputs(dev);
14493
14494 /* Just in case the BIOS is doing something questionable. */
14495 intel_fbc_disable(dev);
14496
14497 drm_modeset_lock_all(dev);
14498 intel_modeset_setup_hw_state(dev, false);
14499 drm_modeset_unlock_all(dev);
14500
14501 for_each_intel_crtc(dev, crtc) {
14502 if (!crtc->active)
14503 continue;
14504
14505 /*
14506 * Note that reserving the BIOS fb up front prevents us
14507 * from stuffing other stolen allocations like the ring
14508 * on top. This prevents some ugliness at boot time, and
14509 * can even allow for smooth boot transitions if the BIOS
14510 * fb is large enough for the active pipe configuration.
14511 */
14512 if (dev_priv->display.get_initial_plane_config) {
14513 dev_priv->display.get_initial_plane_config(crtc,
14514 &crtc->plane_config);
14515 /*
14516 * If the fb is shared between multiple heads, we'll
14517 * just get the first one.
14518 */
14519 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14520 }
14521 }
14522 }
14523
14524 static void intel_enable_pipe_a(struct drm_device *dev)
14525 {
14526 struct intel_connector *connector;
14527 struct drm_connector *crt = NULL;
14528 struct intel_load_detect_pipe load_detect_temp;
14529 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14530
14531 /* We can't just switch on the pipe A, we need to set things up with a
14532 * proper mode and output configuration. As a gross hack, enable pipe A
14533 * by enabling the load detect pipe once. */
14534 for_each_intel_connector(dev, connector) {
14535 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14536 crt = &connector->base;
14537 break;
14538 }
14539 }
14540
14541 if (!crt)
14542 return;
14543
14544 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14545 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14546 }
14547
14548 static bool
14549 intel_check_plane_mapping(struct intel_crtc *crtc)
14550 {
14551 struct drm_device *dev = crtc->base.dev;
14552 struct drm_i915_private *dev_priv = dev->dev_private;
14553 u32 reg, val;
14554
14555 if (INTEL_INFO(dev)->num_pipes == 1)
14556 return true;
14557
14558 reg = DSPCNTR(!crtc->plane);
14559 val = I915_READ(reg);
14560
14561 if ((val & DISPLAY_PLANE_ENABLE) &&
14562 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14563 return false;
14564
14565 return true;
14566 }
14567
14568 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14569 {
14570 struct drm_device *dev = crtc->base.dev;
14571 struct drm_i915_private *dev_priv = dev->dev_private;
14572 u32 reg;
14573
14574 /* Clear any frame start delays used for debugging left by the BIOS */
14575 reg = PIPECONF(crtc->config->cpu_transcoder);
14576 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14577
14578 /* restore vblank interrupts to correct state */
14579 drm_crtc_vblank_reset(&crtc->base);
14580 if (crtc->active) {
14581 update_scanline_offset(crtc);
14582 drm_crtc_vblank_on(&crtc->base);
14583 }
14584
14585 /* We need to sanitize the plane -> pipe mapping first because this will
14586 * disable the crtc (and hence change the state) if it is wrong. Note
14587 * that gen4+ has a fixed plane -> pipe mapping. */
14588 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14589 struct intel_connector *connector;
14590 bool plane;
14591
14592 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14593 crtc->base.base.id);
14594
14595 /* Pipe has the wrong plane attached and the plane is active.
14596 * Temporarily change the plane mapping and disable everything
14597 * ... */
14598 plane = crtc->plane;
14599 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14600 crtc->plane = !plane;
14601 intel_crtc_disable_planes(&crtc->base);
14602 dev_priv->display.crtc_disable(&crtc->base);
14603 crtc->plane = plane;
14604
14605 /* ... and break all links. */
14606 for_each_intel_connector(dev, connector) {
14607 if (connector->encoder->base.crtc != &crtc->base)
14608 continue;
14609
14610 connector->base.dpms = DRM_MODE_DPMS_OFF;
14611 connector->base.encoder = NULL;
14612 }
14613 /* multiple connectors may have the same encoder:
14614 * handle them and break crtc link separately */
14615 for_each_intel_connector(dev, connector)
14616 if (connector->encoder->base.crtc == &crtc->base) {
14617 connector->encoder->base.crtc = NULL;
14618 connector->encoder->connectors_active = false;
14619 }
14620
14621 WARN_ON(crtc->active);
14622 crtc->base.state->enable = false;
14623 crtc->base.state->active = false;
14624 crtc->base.enabled = false;
14625 }
14626
14627 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14628 crtc->pipe == PIPE_A && !crtc->active) {
14629 /* BIOS forgot to enable pipe A, this mostly happens after
14630 * resume. Force-enable the pipe to fix this, the update_dpms
14631 * call below we restore the pipe to the right state, but leave
14632 * the required bits on. */
14633 intel_enable_pipe_a(dev);
14634 }
14635
14636 /* Adjust the state of the output pipe according to whether we
14637 * have active connectors/encoders. */
14638 intel_crtc_update_dpms(&crtc->base);
14639
14640 if (crtc->active != crtc->base.state->enable) {
14641 struct intel_encoder *encoder;
14642
14643 /* This can happen either due to bugs in the get_hw_state
14644 * functions or because the pipe is force-enabled due to the
14645 * pipe A quirk. */
14646 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14647 crtc->base.base.id,
14648 crtc->base.state->enable ? "enabled" : "disabled",
14649 crtc->active ? "enabled" : "disabled");
14650
14651 crtc->base.state->enable = crtc->active;
14652 crtc->base.state->active = crtc->active;
14653 crtc->base.enabled = crtc->active;
14654
14655 /* Because we only establish the connector -> encoder ->
14656 * crtc links if something is active, this means the
14657 * crtc is now deactivated. Break the links. connector
14658 * -> encoder links are only establish when things are
14659 * actually up, hence no need to break them. */
14660 WARN_ON(crtc->active);
14661
14662 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14663 WARN_ON(encoder->connectors_active);
14664 encoder->base.crtc = NULL;
14665 }
14666 }
14667
14668 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14669 /*
14670 * We start out with underrun reporting disabled to avoid races.
14671 * For correct bookkeeping mark this on active crtcs.
14672 *
14673 * Also on gmch platforms we dont have any hardware bits to
14674 * disable the underrun reporting. Which means we need to start
14675 * out with underrun reporting disabled also on inactive pipes,
14676 * since otherwise we'll complain about the garbage we read when
14677 * e.g. coming up after runtime pm.
14678 *
14679 * No protection against concurrent access is required - at
14680 * worst a fifo underrun happens which also sets this to false.
14681 */
14682 crtc->cpu_fifo_underrun_disabled = true;
14683 crtc->pch_fifo_underrun_disabled = true;
14684 }
14685 }
14686
14687 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14688 {
14689 struct intel_connector *connector;
14690 struct drm_device *dev = encoder->base.dev;
14691
14692 /* We need to check both for a crtc link (meaning that the
14693 * encoder is active and trying to read from a pipe) and the
14694 * pipe itself being active. */
14695 bool has_active_crtc = encoder->base.crtc &&
14696 to_intel_crtc(encoder->base.crtc)->active;
14697
14698 if (encoder->connectors_active && !has_active_crtc) {
14699 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14700 encoder->base.base.id,
14701 encoder->base.name);
14702
14703 /* Connector is active, but has no active pipe. This is
14704 * fallout from our resume register restoring. Disable
14705 * the encoder manually again. */
14706 if (encoder->base.crtc) {
14707 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14708 encoder->base.base.id,
14709 encoder->base.name);
14710 encoder->disable(encoder);
14711 if (encoder->post_disable)
14712 encoder->post_disable(encoder);
14713 }
14714 encoder->base.crtc = NULL;
14715 encoder->connectors_active = false;
14716
14717 /* Inconsistent output/port/pipe state happens presumably due to
14718 * a bug in one of the get_hw_state functions. Or someplace else
14719 * in our code, like the register restore mess on resume. Clamp
14720 * things to off as a safer default. */
14721 for_each_intel_connector(dev, connector) {
14722 if (connector->encoder != encoder)
14723 continue;
14724 connector->base.dpms = DRM_MODE_DPMS_OFF;
14725 connector->base.encoder = NULL;
14726 }
14727 }
14728 /* Enabled encoders without active connectors will be fixed in
14729 * the crtc fixup. */
14730 }
14731
14732 void i915_redisable_vga_power_on(struct drm_device *dev)
14733 {
14734 struct drm_i915_private *dev_priv = dev->dev_private;
14735 u32 vga_reg = i915_vgacntrl_reg(dev);
14736
14737 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14738 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14739 i915_disable_vga(dev);
14740 }
14741 }
14742
14743 void i915_redisable_vga(struct drm_device *dev)
14744 {
14745 struct drm_i915_private *dev_priv = dev->dev_private;
14746
14747 /* This function can be called both from intel_modeset_setup_hw_state or
14748 * at a very early point in our resume sequence, where the power well
14749 * structures are not yet restored. Since this function is at a very
14750 * paranoid "someone might have enabled VGA while we were not looking"
14751 * level, just check if the power well is enabled instead of trying to
14752 * follow the "don't touch the power well if we don't need it" policy
14753 * the rest of the driver uses. */
14754 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14755 return;
14756
14757 i915_redisable_vga_power_on(dev);
14758 }
14759
14760 static bool primary_get_hw_state(struct intel_crtc *crtc)
14761 {
14762 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14763
14764 if (!crtc->active)
14765 return false;
14766
14767 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14768 }
14769
14770 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14771 {
14772 struct drm_i915_private *dev_priv = dev->dev_private;
14773 enum pipe pipe;
14774 struct intel_crtc *crtc;
14775 struct intel_encoder *encoder;
14776 struct intel_connector *connector;
14777 int i;
14778
14779 for_each_intel_crtc(dev, crtc) {
14780 struct drm_plane *primary = crtc->base.primary;
14781 struct intel_plane_state *plane_state;
14782
14783 memset(crtc->config, 0, sizeof(*crtc->config));
14784
14785 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14786
14787 crtc->active = dev_priv->display.get_pipe_config(crtc,
14788 crtc->config);
14789
14790 crtc->base.state->enable = crtc->active;
14791 crtc->base.state->active = crtc->active;
14792 crtc->base.enabled = crtc->active;
14793
14794 plane_state = to_intel_plane_state(primary->state);
14795 plane_state->visible = primary_get_hw_state(crtc);
14796
14797 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14798 crtc->base.base.id,
14799 crtc->active ? "enabled" : "disabled");
14800 }
14801
14802 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14803 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14804
14805 pll->on = pll->get_hw_state(dev_priv, pll,
14806 &pll->config.hw_state);
14807 pll->active = 0;
14808 pll->config.crtc_mask = 0;
14809 for_each_intel_crtc(dev, crtc) {
14810 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14811 pll->active++;
14812 pll->config.crtc_mask |= 1 << crtc->pipe;
14813 }
14814 }
14815
14816 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14817 pll->name, pll->config.crtc_mask, pll->on);
14818
14819 if (pll->config.crtc_mask)
14820 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14821 }
14822
14823 for_each_intel_encoder(dev, encoder) {
14824 pipe = 0;
14825
14826 if (encoder->get_hw_state(encoder, &pipe)) {
14827 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14828 encoder->base.crtc = &crtc->base;
14829 encoder->get_config(encoder, crtc->config);
14830 } else {
14831 encoder->base.crtc = NULL;
14832 }
14833
14834 encoder->connectors_active = false;
14835 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14836 encoder->base.base.id,
14837 encoder->base.name,
14838 encoder->base.crtc ? "enabled" : "disabled",
14839 pipe_name(pipe));
14840 }
14841
14842 for_each_intel_connector(dev, connector) {
14843 if (connector->get_hw_state(connector)) {
14844 connector->base.dpms = DRM_MODE_DPMS_ON;
14845 connector->encoder->connectors_active = true;
14846 connector->base.encoder = &connector->encoder->base;
14847 } else {
14848 connector->base.dpms = DRM_MODE_DPMS_OFF;
14849 connector->base.encoder = NULL;
14850 }
14851 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14852 connector->base.base.id,
14853 connector->base.name,
14854 connector->base.encoder ? "enabled" : "disabled");
14855 }
14856 }
14857
14858 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14859 * and i915 state tracking structures. */
14860 void intel_modeset_setup_hw_state(struct drm_device *dev,
14861 bool force_restore)
14862 {
14863 struct drm_i915_private *dev_priv = dev->dev_private;
14864 enum pipe pipe;
14865 struct intel_crtc *crtc;
14866 struct intel_encoder *encoder;
14867 int i;
14868
14869 intel_modeset_readout_hw_state(dev);
14870
14871 /*
14872 * Now that we have the config, copy it to each CRTC struct
14873 * Note that this could go away if we move to using crtc_config
14874 * checking everywhere.
14875 */
14876 for_each_intel_crtc(dev, crtc) {
14877 if (crtc->active && i915.fastboot) {
14878 intel_mode_from_pipe_config(&crtc->base.mode,
14879 crtc->config);
14880 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14881 crtc->base.base.id);
14882 drm_mode_debug_printmodeline(&crtc->base.mode);
14883 }
14884 }
14885
14886 /* HW state is read out, now we need to sanitize this mess. */
14887 for_each_intel_encoder(dev, encoder) {
14888 intel_sanitize_encoder(encoder);
14889 }
14890
14891 for_each_pipe(dev_priv, pipe) {
14892 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14893 intel_sanitize_crtc(crtc);
14894 intel_dump_pipe_config(crtc, crtc->config,
14895 "[setup_hw_state]");
14896 }
14897
14898 intel_modeset_update_connector_atomic_state(dev);
14899
14900 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14901 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14902
14903 if (!pll->on || pll->active)
14904 continue;
14905
14906 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14907
14908 pll->disable(dev_priv, pll);
14909 pll->on = false;
14910 }
14911
14912 if (IS_GEN9(dev))
14913 skl_wm_get_hw_state(dev);
14914 else if (HAS_PCH_SPLIT(dev))
14915 ilk_wm_get_hw_state(dev);
14916
14917 if (force_restore) {
14918 i915_redisable_vga(dev);
14919
14920 /*
14921 * We need to use raw interfaces for restoring state to avoid
14922 * checking (bogus) intermediate states.
14923 */
14924 for_each_pipe(dev_priv, pipe) {
14925 struct drm_crtc *crtc =
14926 dev_priv->pipe_to_crtc_mapping[pipe];
14927
14928 intel_crtc_restore_mode(crtc);
14929 }
14930 } else {
14931 intel_modeset_update_staged_output_state(dev);
14932 }
14933
14934 intel_modeset_check_state(dev);
14935 }
14936
14937 void intel_modeset_gem_init(struct drm_device *dev)
14938 {
14939 struct drm_i915_private *dev_priv = dev->dev_private;
14940 struct drm_crtc *c;
14941 struct drm_i915_gem_object *obj;
14942 int ret;
14943
14944 mutex_lock(&dev->struct_mutex);
14945 intel_init_gt_powersave(dev);
14946 mutex_unlock(&dev->struct_mutex);
14947
14948 /*
14949 * There may be no VBT; and if the BIOS enabled SSC we can
14950 * just keep using it to avoid unnecessary flicker. Whereas if the
14951 * BIOS isn't using it, don't assume it will work even if the VBT
14952 * indicates as much.
14953 */
14954 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14955 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14956 DREF_SSC1_ENABLE);
14957
14958 intel_modeset_init_hw(dev);
14959
14960 intel_setup_overlay(dev);
14961
14962 /*
14963 * Make sure any fbs we allocated at startup are properly
14964 * pinned & fenced. When we do the allocation it's too early
14965 * for this.
14966 */
14967 for_each_crtc(dev, c) {
14968 obj = intel_fb_obj(c->primary->fb);
14969 if (obj == NULL)
14970 continue;
14971
14972 mutex_lock(&dev->struct_mutex);
14973 ret = intel_pin_and_fence_fb_obj(c->primary,
14974 c->primary->fb,
14975 c->primary->state,
14976 NULL);
14977 mutex_unlock(&dev->struct_mutex);
14978 if (ret) {
14979 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14980 to_intel_crtc(c)->pipe);
14981 drm_framebuffer_unreference(c->primary->fb);
14982 c->primary->fb = NULL;
14983 update_state_fb(c->primary);
14984 }
14985 }
14986
14987 intel_backlight_register(dev);
14988 }
14989
14990 void intel_connector_unregister(struct intel_connector *intel_connector)
14991 {
14992 struct drm_connector *connector = &intel_connector->base;
14993
14994 intel_panel_destroy_backlight(connector);
14995 drm_connector_unregister(connector);
14996 }
14997
14998 void intel_modeset_cleanup(struct drm_device *dev)
14999 {
15000 struct drm_i915_private *dev_priv = dev->dev_private;
15001 struct drm_connector *connector;
15002
15003 intel_disable_gt_powersave(dev);
15004
15005 intel_backlight_unregister(dev);
15006
15007 /*
15008 * Interrupts and polling as the first thing to avoid creating havoc.
15009 * Too much stuff here (turning of connectors, ...) would
15010 * experience fancy races otherwise.
15011 */
15012 intel_irq_uninstall(dev_priv);
15013
15014 /*
15015 * Due to the hpd irq storm handling the hotplug work can re-arm the
15016 * poll handlers. Hence disable polling after hpd handling is shut down.
15017 */
15018 drm_kms_helper_poll_fini(dev);
15019
15020 mutex_lock(&dev->struct_mutex);
15021
15022 intel_unregister_dsm_handler();
15023
15024 intel_fbc_disable(dev);
15025
15026 mutex_unlock(&dev->struct_mutex);
15027
15028 /* flush any delayed tasks or pending work */
15029 flush_scheduled_work();
15030
15031 /* destroy the backlight and sysfs files before encoders/connectors */
15032 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15033 struct intel_connector *intel_connector;
15034
15035 intel_connector = to_intel_connector(connector);
15036 intel_connector->unregister(intel_connector);
15037 }
15038
15039 drm_mode_config_cleanup(dev);
15040
15041 intel_cleanup_overlay(dev);
15042
15043 mutex_lock(&dev->struct_mutex);
15044 intel_cleanup_gt_powersave(dev);
15045 mutex_unlock(&dev->struct_mutex);
15046 }
15047
15048 /*
15049 * Return which encoder is currently attached for connector.
15050 */
15051 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15052 {
15053 return &intel_attached_encoder(connector)->base;
15054 }
15055
15056 void intel_connector_attach_encoder(struct intel_connector *connector,
15057 struct intel_encoder *encoder)
15058 {
15059 connector->encoder = encoder;
15060 drm_mode_connector_attach_encoder(&connector->base,
15061 &encoder->base);
15062 }
15063
15064 /*
15065 * set vga decode state - true == enable VGA decode
15066 */
15067 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15068 {
15069 struct drm_i915_private *dev_priv = dev->dev_private;
15070 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15071 u16 gmch_ctrl;
15072
15073 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15074 DRM_ERROR("failed to read control word\n");
15075 return -EIO;
15076 }
15077
15078 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15079 return 0;
15080
15081 if (state)
15082 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15083 else
15084 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15085
15086 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15087 DRM_ERROR("failed to write control word\n");
15088 return -EIO;
15089 }
15090
15091 return 0;
15092 }
15093
15094 struct intel_display_error_state {
15095
15096 u32 power_well_driver;
15097
15098 int num_transcoders;
15099
15100 struct intel_cursor_error_state {
15101 u32 control;
15102 u32 position;
15103 u32 base;
15104 u32 size;
15105 } cursor[I915_MAX_PIPES];
15106
15107 struct intel_pipe_error_state {
15108 bool power_domain_on;
15109 u32 source;
15110 u32 stat;
15111 } pipe[I915_MAX_PIPES];
15112
15113 struct intel_plane_error_state {
15114 u32 control;
15115 u32 stride;
15116 u32 size;
15117 u32 pos;
15118 u32 addr;
15119 u32 surface;
15120 u32 tile_offset;
15121 } plane[I915_MAX_PIPES];
15122
15123 struct intel_transcoder_error_state {
15124 bool power_domain_on;
15125 enum transcoder cpu_transcoder;
15126
15127 u32 conf;
15128
15129 u32 htotal;
15130 u32 hblank;
15131 u32 hsync;
15132 u32 vtotal;
15133 u32 vblank;
15134 u32 vsync;
15135 } transcoder[4];
15136 };
15137
15138 struct intel_display_error_state *
15139 intel_display_capture_error_state(struct drm_device *dev)
15140 {
15141 struct drm_i915_private *dev_priv = dev->dev_private;
15142 struct intel_display_error_state *error;
15143 int transcoders[] = {
15144 TRANSCODER_A,
15145 TRANSCODER_B,
15146 TRANSCODER_C,
15147 TRANSCODER_EDP,
15148 };
15149 int i;
15150
15151 if (INTEL_INFO(dev)->num_pipes == 0)
15152 return NULL;
15153
15154 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15155 if (error == NULL)
15156 return NULL;
15157
15158 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15159 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15160
15161 for_each_pipe(dev_priv, i) {
15162 error->pipe[i].power_domain_on =
15163 __intel_display_power_is_enabled(dev_priv,
15164 POWER_DOMAIN_PIPE(i));
15165 if (!error->pipe[i].power_domain_on)
15166 continue;
15167
15168 error->cursor[i].control = I915_READ(CURCNTR(i));
15169 error->cursor[i].position = I915_READ(CURPOS(i));
15170 error->cursor[i].base = I915_READ(CURBASE(i));
15171
15172 error->plane[i].control = I915_READ(DSPCNTR(i));
15173 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15174 if (INTEL_INFO(dev)->gen <= 3) {
15175 error->plane[i].size = I915_READ(DSPSIZE(i));
15176 error->plane[i].pos = I915_READ(DSPPOS(i));
15177 }
15178 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15179 error->plane[i].addr = I915_READ(DSPADDR(i));
15180 if (INTEL_INFO(dev)->gen >= 4) {
15181 error->plane[i].surface = I915_READ(DSPSURF(i));
15182 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15183 }
15184
15185 error->pipe[i].source = I915_READ(PIPESRC(i));
15186
15187 if (HAS_GMCH_DISPLAY(dev))
15188 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15189 }
15190
15191 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15192 if (HAS_DDI(dev_priv->dev))
15193 error->num_transcoders++; /* Account for eDP. */
15194
15195 for (i = 0; i < error->num_transcoders; i++) {
15196 enum transcoder cpu_transcoder = transcoders[i];
15197
15198 error->transcoder[i].power_domain_on =
15199 __intel_display_power_is_enabled(dev_priv,
15200 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15201 if (!error->transcoder[i].power_domain_on)
15202 continue;
15203
15204 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15205
15206 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15207 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15208 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15209 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15210 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15211 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15212 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15213 }
15214
15215 return error;
15216 }
15217
15218 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15219
15220 void
15221 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15222 struct drm_device *dev,
15223 struct intel_display_error_state *error)
15224 {
15225 struct drm_i915_private *dev_priv = dev->dev_private;
15226 int i;
15227
15228 if (!error)
15229 return;
15230
15231 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15232 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15233 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15234 error->power_well_driver);
15235 for_each_pipe(dev_priv, i) {
15236 err_printf(m, "Pipe [%d]:\n", i);
15237 err_printf(m, " Power: %s\n",
15238 error->pipe[i].power_domain_on ? "on" : "off");
15239 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15240 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15241
15242 err_printf(m, "Plane [%d]:\n", i);
15243 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15244 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15245 if (INTEL_INFO(dev)->gen <= 3) {
15246 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15247 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15248 }
15249 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15250 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15251 if (INTEL_INFO(dev)->gen >= 4) {
15252 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15253 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15254 }
15255
15256 err_printf(m, "Cursor [%d]:\n", i);
15257 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15258 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15259 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15260 }
15261
15262 for (i = 0; i < error->num_transcoders; i++) {
15263 err_printf(m, "CPU transcoder: %c\n",
15264 transcoder_name(error->transcoder[i].cpu_transcoder));
15265 err_printf(m, " Power: %s\n",
15266 error->transcoder[i].power_domain_on ? "on" : "off");
15267 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15268 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15269 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15270 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15271 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15272 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15273 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15274 }
15275 }
15276
15277 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15278 {
15279 struct intel_crtc *crtc;
15280
15281 for_each_intel_crtc(dev, crtc) {
15282 struct intel_unpin_work *work;
15283
15284 spin_lock_irq(&dev->event_lock);
15285
15286 work = crtc->unpin_work;
15287
15288 if (work && work->event &&
15289 work->event->base.file_priv == file) {
15290 kfree(work->event);
15291 work->event = NULL;
15292 }
15293
15294 spin_unlock_irq(&dev->event_lock);
15295 }
15296 }
Linux kernel - Deliverables
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