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drm/i915/sdvo: Markup a few constant strings.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "drm_dp_helper.h"
38
39 #include "drm_crtc_helper.h"
40
41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42
43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
44 static void intel_update_watermarks(struct drm_device *dev);
45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *);
76 };
77
78 #define I8XX_DOT_MIN 25000
79 #define I8XX_DOT_MAX 350000
80 #define I8XX_VCO_MIN 930000
81 #define I8XX_VCO_MAX 1400000
82 #define I8XX_N_MIN 3
83 #define I8XX_N_MAX 16
84 #define I8XX_M_MIN 96
85 #define I8XX_M_MAX 140
86 #define I8XX_M1_MIN 18
87 #define I8XX_M1_MAX 26
88 #define I8XX_M2_MIN 6
89 #define I8XX_M2_MAX 16
90 #define I8XX_P_MIN 4
91 #define I8XX_P_MAX 128
92 #define I8XX_P1_MIN 2
93 #define I8XX_P1_MAX 33
94 #define I8XX_P1_LVDS_MIN 1
95 #define I8XX_P1_LVDS_MAX 6
96 #define I8XX_P2_SLOW 4
97 #define I8XX_P2_FAST 2
98 #define I8XX_P2_LVDS_SLOW 14
99 #define I8XX_P2_LVDS_FAST 7
100 #define I8XX_P2_SLOW_LIMIT 165000
101
102 #define I9XX_DOT_MIN 20000
103 #define I9XX_DOT_MAX 400000
104 #define I9XX_VCO_MIN 1400000
105 #define I9XX_VCO_MAX 2800000
106 #define PINEVIEW_VCO_MIN 1700000
107 #define PINEVIEW_VCO_MAX 3500000
108 #define I9XX_N_MIN 1
109 #define I9XX_N_MAX 6
110 /* Pineview's Ncounter is a ring counter */
111 #define PINEVIEW_N_MIN 3
112 #define PINEVIEW_N_MAX 6
113 #define I9XX_M_MIN 70
114 #define I9XX_M_MAX 120
115 #define PINEVIEW_M_MIN 2
116 #define PINEVIEW_M_MAX 256
117 #define I9XX_M1_MIN 10
118 #define I9XX_M1_MAX 22
119 #define I9XX_M2_MIN 5
120 #define I9XX_M2_MAX 9
121 /* Pineview M1 is reserved, and must be 0 */
122 #define PINEVIEW_M1_MIN 0
123 #define PINEVIEW_M1_MAX 0
124 #define PINEVIEW_M2_MIN 0
125 #define PINEVIEW_M2_MAX 254
126 #define I9XX_P_SDVO_DAC_MIN 5
127 #define I9XX_P_SDVO_DAC_MAX 80
128 #define I9XX_P_LVDS_MIN 7
129 #define I9XX_P_LVDS_MAX 98
130 #define PINEVIEW_P_LVDS_MIN 7
131 #define PINEVIEW_P_LVDS_MAX 112
132 #define I9XX_P1_MIN 1
133 #define I9XX_P1_MAX 8
134 #define I9XX_P2_SDVO_DAC_SLOW 10
135 #define I9XX_P2_SDVO_DAC_FAST 5
136 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
137 #define I9XX_P2_LVDS_SLOW 14
138 #define I9XX_P2_LVDS_FAST 7
139 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
140
141 /*The parameter is for SDVO on G4x platform*/
142 #define G4X_DOT_SDVO_MIN 25000
143 #define G4X_DOT_SDVO_MAX 270000
144 #define G4X_VCO_MIN 1750000
145 #define G4X_VCO_MAX 3500000
146 #define G4X_N_SDVO_MIN 1
147 #define G4X_N_SDVO_MAX 4
148 #define G4X_M_SDVO_MIN 104
149 #define G4X_M_SDVO_MAX 138
150 #define G4X_M1_SDVO_MIN 17
151 #define G4X_M1_SDVO_MAX 23
152 #define G4X_M2_SDVO_MIN 5
153 #define G4X_M2_SDVO_MAX 11
154 #define G4X_P_SDVO_MIN 10
155 #define G4X_P_SDVO_MAX 30
156 #define G4X_P1_SDVO_MIN 1
157 #define G4X_P1_SDVO_MAX 3
158 #define G4X_P2_SDVO_SLOW 10
159 #define G4X_P2_SDVO_FAST 10
160 #define G4X_P2_SDVO_LIMIT 270000
161
162 /*The parameter is for HDMI_DAC on G4x platform*/
163 #define G4X_DOT_HDMI_DAC_MIN 22000
164 #define G4X_DOT_HDMI_DAC_MAX 400000
165 #define G4X_N_HDMI_DAC_MIN 1
166 #define G4X_N_HDMI_DAC_MAX 4
167 #define G4X_M_HDMI_DAC_MIN 104
168 #define G4X_M_HDMI_DAC_MAX 138
169 #define G4X_M1_HDMI_DAC_MIN 16
170 #define G4X_M1_HDMI_DAC_MAX 23
171 #define G4X_M2_HDMI_DAC_MIN 5
172 #define G4X_M2_HDMI_DAC_MAX 11
173 #define G4X_P_HDMI_DAC_MIN 5
174 #define G4X_P_HDMI_DAC_MAX 80
175 #define G4X_P1_HDMI_DAC_MIN 1
176 #define G4X_P1_HDMI_DAC_MAX 8
177 #define G4X_P2_HDMI_DAC_SLOW 10
178 #define G4X_P2_HDMI_DAC_FAST 5
179 #define G4X_P2_HDMI_DAC_LIMIT 165000
180
181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
199
200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
218
219 /*The parameter is for DISPLAY PORT on G4x platform*/
220 #define G4X_DOT_DISPLAY_PORT_MIN 161670
221 #define G4X_DOT_DISPLAY_PORT_MAX 227000
222 #define G4X_N_DISPLAY_PORT_MIN 1
223 #define G4X_N_DISPLAY_PORT_MAX 2
224 #define G4X_M_DISPLAY_PORT_MIN 97
225 #define G4X_M_DISPLAY_PORT_MAX 108
226 #define G4X_M1_DISPLAY_PORT_MIN 0x10
227 #define G4X_M1_DISPLAY_PORT_MAX 0x12
228 #define G4X_M2_DISPLAY_PORT_MIN 0x05
229 #define G4X_M2_DISPLAY_PORT_MAX 0x06
230 #define G4X_P_DISPLAY_PORT_MIN 10
231 #define G4X_P_DISPLAY_PORT_MAX 20
232 #define G4X_P1_DISPLAY_PORT_MIN 1
233 #define G4X_P1_DISPLAY_PORT_MAX 2
234 #define G4X_P2_DISPLAY_PORT_SLOW 10
235 #define G4X_P2_DISPLAY_PORT_FAST 10
236 #define G4X_P2_DISPLAY_PORT_LIMIT 0
237
238 /* Ironlake / Sandybridge */
239 /* as we calculate clock using (register_value + 2) for
240 N/M1/M2, so here the range value for them is (actual_value-2).
241 */
242 #define IRONLAKE_DOT_MIN 25000
243 #define IRONLAKE_DOT_MAX 350000
244 #define IRONLAKE_VCO_MIN 1760000
245 #define IRONLAKE_VCO_MAX 3510000
246 #define IRONLAKE_M1_MIN 12
247 #define IRONLAKE_M1_MAX 22
248 #define IRONLAKE_M2_MIN 5
249 #define IRONLAKE_M2_MAX 9
250 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
251
252 /* We have parameter ranges for different type of outputs. */
253
254 /* DAC & HDMI Refclk 120Mhz */
255 #define IRONLAKE_DAC_N_MIN 1
256 #define IRONLAKE_DAC_N_MAX 5
257 #define IRONLAKE_DAC_M_MIN 79
258 #define IRONLAKE_DAC_M_MAX 127
259 #define IRONLAKE_DAC_P_MIN 5
260 #define IRONLAKE_DAC_P_MAX 80
261 #define IRONLAKE_DAC_P1_MIN 1
262 #define IRONLAKE_DAC_P1_MAX 8
263 #define IRONLAKE_DAC_P2_SLOW 10
264 #define IRONLAKE_DAC_P2_FAST 5
265
266 /* LVDS single-channel 120Mhz refclk */
267 #define IRONLAKE_LVDS_S_N_MIN 1
268 #define IRONLAKE_LVDS_S_N_MAX 3
269 #define IRONLAKE_LVDS_S_M_MIN 79
270 #define IRONLAKE_LVDS_S_M_MAX 118
271 #define IRONLAKE_LVDS_S_P_MIN 28
272 #define IRONLAKE_LVDS_S_P_MAX 112
273 #define IRONLAKE_LVDS_S_P1_MIN 2
274 #define IRONLAKE_LVDS_S_P1_MAX 8
275 #define IRONLAKE_LVDS_S_P2_SLOW 14
276 #define IRONLAKE_LVDS_S_P2_FAST 14
277
278 /* LVDS dual-channel 120Mhz refclk */
279 #define IRONLAKE_LVDS_D_N_MIN 1
280 #define IRONLAKE_LVDS_D_N_MAX 3
281 #define IRONLAKE_LVDS_D_M_MIN 79
282 #define IRONLAKE_LVDS_D_M_MAX 127
283 #define IRONLAKE_LVDS_D_P_MIN 14
284 #define IRONLAKE_LVDS_D_P_MAX 56
285 #define IRONLAKE_LVDS_D_P1_MIN 2
286 #define IRONLAKE_LVDS_D_P1_MAX 8
287 #define IRONLAKE_LVDS_D_P2_SLOW 7
288 #define IRONLAKE_LVDS_D_P2_FAST 7
289
290 /* LVDS single-channel 100Mhz refclk */
291 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
292 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
293 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
294 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
295 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
296 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
297 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
298 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
299 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
300 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
301
302 /* LVDS dual-channel 100Mhz refclk */
303 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
304 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
305 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
306 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
307 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
308 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
309 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
310 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
311 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
312 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313
314 /* DisplayPort */
315 #define IRONLAKE_DP_N_MIN 1
316 #define IRONLAKE_DP_N_MAX 2
317 #define IRONLAKE_DP_M_MIN 81
318 #define IRONLAKE_DP_M_MAX 90
319 #define IRONLAKE_DP_P_MIN 10
320 #define IRONLAKE_DP_P_MAX 20
321 #define IRONLAKE_DP_P2_FAST 10
322 #define IRONLAKE_DP_P2_SLOW 10
323 #define IRONLAKE_DP_P2_LIMIT 0
324 #define IRONLAKE_DP_P1_MIN 1
325 #define IRONLAKE_DP_P1_MAX 2
326
327 /* FDI */
328 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
329
330 static bool
331 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
332 int target, int refclk, intel_clock_t *best_clock);
333 static bool
334 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
335 int target, int refclk, intel_clock_t *best_clock);
336
337 static bool
338 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
339 int target, int refclk, intel_clock_t *best_clock);
340 static bool
341 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
342 int target, int refclk, intel_clock_t *best_clock);
343
344 static const intel_limit_t intel_limits_i8xx_dvo = {
345 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
346 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
347 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
348 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
349 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
350 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
351 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
352 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
353 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
354 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
355 .find_pll = intel_find_best_PLL,
356 };
357
358 static const intel_limit_t intel_limits_i8xx_lvds = {
359 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
360 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
361 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
362 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
363 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
364 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
365 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
366 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
367 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
368 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
369 .find_pll = intel_find_best_PLL,
370 };
371
372 static const intel_limit_t intel_limits_i9xx_sdvo = {
373 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
374 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
375 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
376 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
377 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
378 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
379 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
380 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
381 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
382 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
383 .find_pll = intel_find_best_PLL,
384 };
385
386 static const intel_limit_t intel_limits_i9xx_lvds = {
387 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
388 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
389 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
390 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
391 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
392 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
393 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
394 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
395 /* The single-channel range is 25-112Mhz, and dual-channel
396 * is 80-224Mhz. Prefer single channel as much as possible.
397 */
398 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
399 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
400 .find_pll = intel_find_best_PLL,
401 };
402
403 /* below parameter and function is for G4X Chipset Family*/
404 static const intel_limit_t intel_limits_g4x_sdvo = {
405 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
406 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
407 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
408 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
409 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
410 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
411 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
412 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
413 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
414 .p2_slow = G4X_P2_SDVO_SLOW,
415 .p2_fast = G4X_P2_SDVO_FAST
416 },
417 .find_pll = intel_g4x_find_best_PLL,
418 };
419
420 static const intel_limit_t intel_limits_g4x_hdmi = {
421 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
422 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
423 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
424 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
425 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
426 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
427 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
428 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
429 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
430 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
431 .p2_fast = G4X_P2_HDMI_DAC_FAST
432 },
433 .find_pll = intel_g4x_find_best_PLL,
434 };
435
436 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
437 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
438 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
439 .vco = { .min = G4X_VCO_MIN,
440 .max = G4X_VCO_MAX },
441 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
442 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
443 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
444 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
445 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
447 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
448 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
449 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
450 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
451 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
452 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
453 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
454 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
455 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
456 },
457 .find_pll = intel_g4x_find_best_PLL,
458 };
459
460 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
461 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
462 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
463 .vco = { .min = G4X_VCO_MIN,
464 .max = G4X_VCO_MAX },
465 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
466 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
467 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
468 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
469 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
471 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
472 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
473 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
474 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
475 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
476 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
477 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
478 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
479 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
480 },
481 .find_pll = intel_g4x_find_best_PLL,
482 };
483
484 static const intel_limit_t intel_limits_g4x_display_port = {
485 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
486 .max = G4X_DOT_DISPLAY_PORT_MAX },
487 .vco = { .min = G4X_VCO_MIN,
488 .max = G4X_VCO_MAX},
489 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
490 .max = G4X_N_DISPLAY_PORT_MAX },
491 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
492 .max = G4X_M_DISPLAY_PORT_MAX },
493 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
494 .max = G4X_M1_DISPLAY_PORT_MAX },
495 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
496 .max = G4X_M2_DISPLAY_PORT_MAX },
497 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
498 .max = G4X_P_DISPLAY_PORT_MAX },
499 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
500 .max = G4X_P1_DISPLAY_PORT_MAX},
501 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
502 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
503 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
504 .find_pll = intel_find_pll_g4x_dp,
505 };
506
507 static const intel_limit_t intel_limits_pineview_sdvo = {
508 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
509 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
510 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
511 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
512 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
513 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
514 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
515 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
516 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
517 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
518 .find_pll = intel_find_best_PLL,
519 };
520
521 static const intel_limit_t intel_limits_pineview_lvds = {
522 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
523 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
524 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
525 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
526 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
527 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
528 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
529 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
530 /* Pineview only supports single-channel mode. */
531 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
532 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
533 .find_pll = intel_find_best_PLL,
534 };
535
536 static const intel_limit_t intel_limits_ironlake_dac = {
537 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
538 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
539 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
540 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
541 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
542 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
543 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
544 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
545 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
546 .p2_slow = IRONLAKE_DAC_P2_SLOW,
547 .p2_fast = IRONLAKE_DAC_P2_FAST },
548 .find_pll = intel_g4x_find_best_PLL,
549 };
550
551 static const intel_limit_t intel_limits_ironlake_single_lvds = {
552 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
553 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
554 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
555 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
556 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
557 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
558 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
559 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
560 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
561 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
562 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
563 .find_pll = intel_g4x_find_best_PLL,
564 };
565
566 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
567 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
568 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
569 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
570 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
571 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
572 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
573 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
574 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
575 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
576 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
577 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
578 .find_pll = intel_g4x_find_best_PLL,
579 };
580
581 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
582 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
583 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
584 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
585 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
586 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
587 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
588 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
589 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
590 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
591 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
592 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
593 .find_pll = intel_g4x_find_best_PLL,
594 };
595
596 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
597 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
598 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
599 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
600 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
601 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
602 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
603 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
604 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
605 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
606 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
607 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
608 .find_pll = intel_g4x_find_best_PLL,
609 };
610
611 static const intel_limit_t intel_limits_ironlake_display_port = {
612 .dot = { .min = IRONLAKE_DOT_MIN,
613 .max = IRONLAKE_DOT_MAX },
614 .vco = { .min = IRONLAKE_VCO_MIN,
615 .max = IRONLAKE_VCO_MAX},
616 .n = { .min = IRONLAKE_DP_N_MIN,
617 .max = IRONLAKE_DP_N_MAX },
618 .m = { .min = IRONLAKE_DP_M_MIN,
619 .max = IRONLAKE_DP_M_MAX },
620 .m1 = { .min = IRONLAKE_M1_MIN,
621 .max = IRONLAKE_M1_MAX },
622 .m2 = { .min = IRONLAKE_M2_MIN,
623 .max = IRONLAKE_M2_MAX },
624 .p = { .min = IRONLAKE_DP_P_MIN,
625 .max = IRONLAKE_DP_P_MAX },
626 .p1 = { .min = IRONLAKE_DP_P1_MIN,
627 .max = IRONLAKE_DP_P1_MAX},
628 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
629 .p2_slow = IRONLAKE_DP_P2_SLOW,
630 .p2_fast = IRONLAKE_DP_P2_FAST },
631 .find_pll = intel_find_pll_ironlake_dp,
632 };
633
634 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
635 {
636 struct drm_device *dev = crtc->dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 const intel_limit_t *limit;
639 int refclk = 120;
640
641 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
642 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
643 refclk = 100;
644
645 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
646 LVDS_CLKB_POWER_UP) {
647 /* LVDS dual channel */
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_dual_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_dual_lvds;
652 } else {
653 if (refclk == 100)
654 limit = &intel_limits_ironlake_single_lvds_100m;
655 else
656 limit = &intel_limits_ironlake_single_lvds;
657 }
658 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
659 HAS_eDP)
660 limit = &intel_limits_ironlake_display_port;
661 else
662 limit = &intel_limits_ironlake_dac;
663
664 return limit;
665 }
666
667 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
668 {
669 struct drm_device *dev = crtc->dev;
670 struct drm_i915_private *dev_priv = dev->dev_private;
671 const intel_limit_t *limit;
672
673 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
674 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
675 LVDS_CLKB_POWER_UP)
676 /* LVDS with dual channel */
677 limit = &intel_limits_g4x_dual_channel_lvds;
678 else
679 /* LVDS with dual channel */
680 limit = &intel_limits_g4x_single_channel_lvds;
681 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
682 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
683 limit = &intel_limits_g4x_hdmi;
684 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
685 limit = &intel_limits_g4x_sdvo;
686 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
687 limit = &intel_limits_g4x_display_port;
688 } else /* The option is for other outputs */
689 limit = &intel_limits_i9xx_sdvo;
690
691 return limit;
692 }
693
694 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
695 {
696 struct drm_device *dev = crtc->dev;
697 const intel_limit_t *limit;
698
699 if (HAS_PCH_SPLIT(dev))
700 limit = intel_ironlake_limit(crtc);
701 else if (IS_G4X(dev)) {
702 limit = intel_g4x_limit(crtc);
703 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705 limit = &intel_limits_i9xx_lvds;
706 else
707 limit = &intel_limits_i9xx_sdvo;
708 } else if (IS_PINEVIEW(dev)) {
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710 limit = &intel_limits_pineview_lvds;
711 else
712 limit = &intel_limits_pineview_sdvo;
713 } else {
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
715 limit = &intel_limits_i8xx_lvds;
716 else
717 limit = &intel_limits_i8xx_dvo;
718 }
719 return limit;
720 }
721
722 /* m1 is reserved as 0 in Pineview, n is a ring counter */
723 static void pineview_clock(int refclk, intel_clock_t *clock)
724 {
725 clock->m = clock->m2 + 2;
726 clock->p = clock->p1 * clock->p2;
727 clock->vco = refclk * clock->m / clock->n;
728 clock->dot = clock->vco / clock->p;
729 }
730
731 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
732 {
733 if (IS_PINEVIEW(dev)) {
734 pineview_clock(refclk, clock);
735 return;
736 }
737 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
738 clock->p = clock->p1 * clock->p2;
739 clock->vco = refclk * clock->m / (clock->n + 2);
740 clock->dot = clock->vco / clock->p;
741 }
742
743 /**
744 * Returns whether any output on the specified pipe is of the specified type
745 */
746 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
747 {
748 struct drm_device *dev = crtc->dev;
749 struct drm_mode_config *mode_config = &dev->mode_config;
750 struct drm_encoder *l_entry;
751
752 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
753 if (l_entry && l_entry->crtc == crtc) {
754 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
755 if (intel_encoder->type == type)
756 return true;
757 }
758 }
759 return false;
760 }
761
762 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
763 /**
764 * Returns whether the given set of divisors are valid for a given refclk with
765 * the given connectors.
766 */
767
768 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
769 {
770 const intel_limit_t *limit = intel_limit (crtc);
771 struct drm_device *dev = crtc->dev;
772
773 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
774 INTELPllInvalid ("p1 out of range\n");
775 if (clock->p < limit->p.min || limit->p.max < clock->p)
776 INTELPllInvalid ("p out of range\n");
777 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
778 INTELPllInvalid ("m2 out of range\n");
779 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
780 INTELPllInvalid ("m1 out of range\n");
781 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
782 INTELPllInvalid ("m1 <= m2\n");
783 if (clock->m < limit->m.min || limit->m.max < clock->m)
784 INTELPllInvalid ("m out of range\n");
785 if (clock->n < limit->n.min || limit->n.max < clock->n)
786 INTELPllInvalid ("n out of range\n");
787 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
788 INTELPllInvalid ("vco out of range\n");
789 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
790 * connector, etc., rather than just a single range.
791 */
792 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
793 INTELPllInvalid ("dot out of range\n");
794
795 return true;
796 }
797
798 static bool
799 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
800 int target, int refclk, intel_clock_t *best_clock)
801
802 {
803 struct drm_device *dev = crtc->dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 intel_clock_t clock;
806 int err = target;
807
808 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
809 (I915_READ(LVDS)) != 0) {
810 /*
811 * For LVDS, if the panel is on, just rely on its current
812 * settings for dual-channel. We haven't figured out how to
813 * reliably set up different single/dual channel state, if we
814 * even can.
815 */
816 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
817 LVDS_CLKB_POWER_UP)
818 clock.p2 = limit->p2.p2_fast;
819 else
820 clock.p2 = limit->p2.p2_slow;
821 } else {
822 if (target < limit->p2.dot_limit)
823 clock.p2 = limit->p2.p2_slow;
824 else
825 clock.p2 = limit->p2.p2_fast;
826 }
827
828 memset (best_clock, 0, sizeof (*best_clock));
829
830 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
831 clock.m1++) {
832 for (clock.m2 = limit->m2.min;
833 clock.m2 <= limit->m2.max; clock.m2++) {
834 /* m1 is always 0 in Pineview */
835 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
836 break;
837 for (clock.n = limit->n.min;
838 clock.n <= limit->n.max; clock.n++) {
839 for (clock.p1 = limit->p1.min;
840 clock.p1 <= limit->p1.max; clock.p1++) {
841 int this_err;
842
843 intel_clock(dev, refclk, &clock);
844
845 if (!intel_PLL_is_valid(crtc, &clock))
846 continue;
847
848 this_err = abs(clock.dot - target);
849 if (this_err < err) {
850 *best_clock = clock;
851 err = this_err;
852 }
853 }
854 }
855 }
856 }
857
858 return (err != target);
859 }
860
861 static bool
862 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *best_clock)
864 {
865 struct drm_device *dev = crtc->dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 intel_clock_t clock;
868 int max_n;
869 bool found;
870 /* approximately equals target * 0.00585 */
871 int err_most = (target >> 8) + (target >> 9);
872 found = false;
873
874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
875 int lvds_reg;
876
877 if (HAS_PCH_SPLIT(dev))
878 lvds_reg = PCH_LVDS;
879 else
880 lvds_reg = LVDS;
881 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
882 LVDS_CLKB_POWER_UP)
883 clock.p2 = limit->p2.p2_fast;
884 else
885 clock.p2 = limit->p2.p2_slow;
886 } else {
887 if (target < limit->p2.dot_limit)
888 clock.p2 = limit->p2.p2_slow;
889 else
890 clock.p2 = limit->p2.p2_fast;
891 }
892
893 memset(best_clock, 0, sizeof(*best_clock));
894 max_n = limit->n.max;
895 /* based on hardware requirement, prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
897 /* based on hardware requirement, prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) {
900 for (clock.m2 = limit->m2.max;
901 clock.m2 >= limit->m2.min; clock.m2--) {
902 for (clock.p1 = limit->p1.max;
903 clock.p1 >= limit->p1.min; clock.p1--) {
904 int this_err;
905
906 intel_clock(dev, refclk, &clock);
907 if (!intel_PLL_is_valid(crtc, &clock))
908 continue;
909 this_err = abs(clock.dot - target) ;
910 if (this_err < err_most) {
911 *best_clock = clock;
912 err_most = this_err;
913 max_n = clock.n;
914 found = true;
915 }
916 }
917 }
918 }
919 }
920 return found;
921 }
922
923 static bool
924 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
925 int target, int refclk, intel_clock_t *best_clock)
926 {
927 struct drm_device *dev = crtc->dev;
928 intel_clock_t clock;
929
930 /* return directly when it is eDP */
931 if (HAS_eDP)
932 return true;
933
934 if (target < 200000) {
935 clock.n = 1;
936 clock.p1 = 2;
937 clock.p2 = 10;
938 clock.m1 = 12;
939 clock.m2 = 9;
940 } else {
941 clock.n = 2;
942 clock.p1 = 1;
943 clock.p2 = 10;
944 clock.m1 = 14;
945 clock.m2 = 8;
946 }
947 intel_clock(dev, refclk, &clock);
948 memcpy(best_clock, &clock, sizeof(intel_clock_t));
949 return true;
950 }
951
952 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
953 static bool
954 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
955 int target, int refclk, intel_clock_t *best_clock)
956 {
957 intel_clock_t clock;
958 if (target < 200000) {
959 clock.p1 = 2;
960 clock.p2 = 10;
961 clock.n = 2;
962 clock.m1 = 23;
963 clock.m2 = 8;
964 } else {
965 clock.p1 = 1;
966 clock.p2 = 10;
967 clock.n = 1;
968 clock.m1 = 14;
969 clock.m2 = 2;
970 }
971 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
972 clock.p = (clock.p1 * clock.p2);
973 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
974 clock.vco = 0;
975 memcpy(best_clock, &clock, sizeof(intel_clock_t));
976 return true;
977 }
978
979 void
980 intel_wait_for_vblank(struct drm_device *dev)
981 {
982 /* Wait for 20ms, i.e. one cycle at 50hz. */
983 if (in_dbg_master())
984 mdelay(20); /* The kernel debugger cannot call msleep() */
985 else
986 msleep(20);
987 }
988
989 /* Parameters have changed, update FBC info */
990 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
991 {
992 struct drm_device *dev = crtc->dev;
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 struct drm_framebuffer *fb = crtc->fb;
995 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
996 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
998 int plane, i;
999 u32 fbc_ctl, fbc_ctl2;
1000
1001 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1002
1003 if (fb->pitch < dev_priv->cfb_pitch)
1004 dev_priv->cfb_pitch = fb->pitch;
1005
1006 /* FBC_CTL wants 64B units */
1007 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1008 dev_priv->cfb_fence = obj_priv->fence_reg;
1009 dev_priv->cfb_plane = intel_crtc->plane;
1010 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1011
1012 /* Clear old tags */
1013 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1014 I915_WRITE(FBC_TAG + (i * 4), 0);
1015
1016 /* Set it up... */
1017 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1018 if (obj_priv->tiling_mode != I915_TILING_NONE)
1019 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1020 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1021 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1022
1023 /* enable it... */
1024 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1025 if (IS_I945GM(dev))
1026 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1027 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1028 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1029 if (obj_priv->tiling_mode != I915_TILING_NONE)
1030 fbc_ctl |= dev_priv->cfb_fence;
1031 I915_WRITE(FBC_CONTROL, fbc_ctl);
1032
1033 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1034 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1035 }
1036
1037 void i8xx_disable_fbc(struct drm_device *dev)
1038 {
1039 struct drm_i915_private *dev_priv = dev->dev_private;
1040 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1041 u32 fbc_ctl;
1042
1043 if (!I915_HAS_FBC(dev))
1044 return;
1045
1046 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1047 return; /* Already off, just return */
1048
1049 /* Disable compression */
1050 fbc_ctl = I915_READ(FBC_CONTROL);
1051 fbc_ctl &= ~FBC_CTL_EN;
1052 I915_WRITE(FBC_CONTROL, fbc_ctl);
1053
1054 /* Wait for compressing bit to clear */
1055 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1056 if (time_after(jiffies, timeout)) {
1057 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1058 break;
1059 }
1060 ; /* do nothing */
1061 }
1062
1063 intel_wait_for_vblank(dev);
1064
1065 DRM_DEBUG_KMS("disabled FBC\n");
1066 }
1067
1068 static bool i8xx_fbc_enabled(struct drm_device *dev)
1069 {
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1073 }
1074
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1076 {
1077 struct drm_device *dev = crtc->dev;
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 struct drm_framebuffer *fb = crtc->fb;
1080 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1084 DPFC_CTL_PLANEB);
1085 unsigned long stall_watermark = 200;
1086 u32 dpfc_ctl;
1087
1088 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089 dev_priv->cfb_fence = obj_priv->fence_reg;
1090 dev_priv->cfb_plane = intel_crtc->plane;
1091
1092 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1096 } else {
1097 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1098 }
1099
1100 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1105
1106 /* enable it... */
1107 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1108
1109 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1110 }
1111
1112 void g4x_disable_fbc(struct drm_device *dev)
1113 {
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 u32 dpfc_ctl;
1116
1117 /* Disable compression */
1118 dpfc_ctl = I915_READ(DPFC_CONTROL);
1119 dpfc_ctl &= ~DPFC_CTL_EN;
1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121 intel_wait_for_vblank(dev);
1122
1123 DRM_DEBUG_KMS("disabled FBC\n");
1124 }
1125
1126 static bool g4x_fbc_enabled(struct drm_device *dev)
1127 {
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1131 }
1132
1133 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1134 {
1135 struct drm_device *dev = crtc->dev;
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 struct drm_framebuffer *fb = crtc->fb;
1138 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1139 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1141 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1142 DPFC_CTL_PLANEB;
1143 unsigned long stall_watermark = 200;
1144 u32 dpfc_ctl;
1145
1146 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1147 dev_priv->cfb_fence = obj_priv->fence_reg;
1148 dev_priv->cfb_plane = intel_crtc->plane;
1149
1150 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1151 dpfc_ctl &= DPFC_RESERVED;
1152 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1153 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1154 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1155 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1156 } else {
1157 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1158 }
1159
1160 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1161 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1162 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1163 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1164 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1165 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1166 /* enable it... */
1167 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1168 DPFC_CTL_EN);
1169
1170 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1171 }
1172
1173 void ironlake_disable_fbc(struct drm_device *dev)
1174 {
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 u32 dpfc_ctl;
1177
1178 /* Disable compression */
1179 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1180 dpfc_ctl &= ~DPFC_CTL_EN;
1181 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1182 intel_wait_for_vblank(dev);
1183
1184 DRM_DEBUG_KMS("disabled FBC\n");
1185 }
1186
1187 static bool ironlake_fbc_enabled(struct drm_device *dev)
1188 {
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190
1191 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1192 }
1193
1194 bool intel_fbc_enabled(struct drm_device *dev)
1195 {
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197
1198 if (!dev_priv->display.fbc_enabled)
1199 return false;
1200
1201 return dev_priv->display.fbc_enabled(dev);
1202 }
1203
1204 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1205 {
1206 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1207
1208 if (!dev_priv->display.enable_fbc)
1209 return;
1210
1211 dev_priv->display.enable_fbc(crtc, interval);
1212 }
1213
1214 void intel_disable_fbc(struct drm_device *dev)
1215 {
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217
1218 if (!dev_priv->display.disable_fbc)
1219 return;
1220
1221 dev_priv->display.disable_fbc(dev);
1222 }
1223
1224 /**
1225 * intel_update_fbc - enable/disable FBC as needed
1226 * @crtc: CRTC to point the compressor at
1227 * @mode: mode in use
1228 *
1229 * Set up the framebuffer compression hardware at mode set time. We
1230 * enable it if possible:
1231 * - plane A only (on pre-965)
1232 * - no pixel mulitply/line duplication
1233 * - no alpha buffer discard
1234 * - no dual wide
1235 * - framebuffer <= 2048 in width, 1536 in height
1236 *
1237 * We can't assume that any compression will take place (worst case),
1238 * so the compressed buffer has to be the same size as the uncompressed
1239 * one. It also must reside (along with the line length buffer) in
1240 * stolen memory.
1241 *
1242 * We need to enable/disable FBC on a global basis.
1243 */
1244 static void intel_update_fbc(struct drm_crtc *crtc,
1245 struct drm_display_mode *mode)
1246 {
1247 struct drm_device *dev = crtc->dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 struct drm_framebuffer *fb = crtc->fb;
1250 struct intel_framebuffer *intel_fb;
1251 struct drm_i915_gem_object *obj_priv;
1252 struct drm_crtc *tmp_crtc;
1253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1254 int plane = intel_crtc->plane;
1255 int crtcs_enabled = 0;
1256
1257 DRM_DEBUG_KMS("\n");
1258
1259 if (!i915_powersave)
1260 return;
1261
1262 if (!I915_HAS_FBC(dev))
1263 return;
1264
1265 if (!crtc->fb)
1266 return;
1267
1268 intel_fb = to_intel_framebuffer(fb);
1269 obj_priv = to_intel_bo(intel_fb->obj);
1270
1271 /*
1272 * If FBC is already on, we just have to verify that we can
1273 * keep it that way...
1274 * Need to disable if:
1275 * - more than one pipe is active
1276 * - changing FBC params (stride, fence, mode)
1277 * - new fb is too large to fit in compressed buffer
1278 * - going to an unsupported config (interlace, pixel multiply, etc.)
1279 */
1280 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1281 if (tmp_crtc->enabled)
1282 crtcs_enabled++;
1283 }
1284 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1285 if (crtcs_enabled > 1) {
1286 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1287 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1288 goto out_disable;
1289 }
1290 if (intel_fb->obj->size > dev_priv->cfb_size) {
1291 DRM_DEBUG_KMS("framebuffer too large, disabling "
1292 "compression\n");
1293 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1294 goto out_disable;
1295 }
1296 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1297 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1298 DRM_DEBUG_KMS("mode incompatible with compression, "
1299 "disabling\n");
1300 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1301 goto out_disable;
1302 }
1303 if ((mode->hdisplay > 2048) ||
1304 (mode->vdisplay > 1536)) {
1305 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1306 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1307 goto out_disable;
1308 }
1309 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1310 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1311 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1312 goto out_disable;
1313 }
1314 if (obj_priv->tiling_mode != I915_TILING_X) {
1315 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1316 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1317 goto out_disable;
1318 }
1319
1320 /* If the kernel debugger is active, always disable compression */
1321 if (in_dbg_master())
1322 goto out_disable;
1323
1324 if (intel_fbc_enabled(dev)) {
1325 /* We can re-enable it in this case, but need to update pitch */
1326 if ((fb->pitch > dev_priv->cfb_pitch) ||
1327 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1328 (plane != dev_priv->cfb_plane))
1329 intel_disable_fbc(dev);
1330 }
1331
1332 /* Now try to turn it back on if possible */
1333 if (!intel_fbc_enabled(dev))
1334 intel_enable_fbc(crtc, 500);
1335
1336 return;
1337
1338 out_disable:
1339 /* Multiple disables should be harmless */
1340 if (intel_fbc_enabled(dev)) {
1341 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1342 intel_disable_fbc(dev);
1343 }
1344 }
1345
1346 int
1347 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1348 {
1349 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1350 u32 alignment;
1351 int ret;
1352
1353 switch (obj_priv->tiling_mode) {
1354 case I915_TILING_NONE:
1355 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1356 alignment = 128 * 1024;
1357 else if (IS_I965G(dev))
1358 alignment = 4 * 1024;
1359 else
1360 alignment = 64 * 1024;
1361 break;
1362 case I915_TILING_X:
1363 /* pin() will align the object as required by fence */
1364 alignment = 0;
1365 break;
1366 case I915_TILING_Y:
1367 /* FIXME: Is this true? */
1368 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1369 return -EINVAL;
1370 default:
1371 BUG();
1372 }
1373
1374 ret = i915_gem_object_pin(obj, alignment);
1375 if (ret != 0)
1376 return ret;
1377
1378 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1379 * fence, whereas 965+ only requires a fence if using
1380 * framebuffer compression. For simplicity, we always install
1381 * a fence as the cost is not that onerous.
1382 */
1383 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1384 obj_priv->tiling_mode != I915_TILING_NONE) {
1385 ret = i915_gem_object_get_fence_reg(obj);
1386 if (ret != 0) {
1387 i915_gem_object_unpin(obj);
1388 return ret;
1389 }
1390 }
1391
1392 return 0;
1393 }
1394
1395 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1396 static int
1397 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1398 int x, int y)
1399 {
1400 struct drm_device *dev = crtc->dev;
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1403 struct intel_framebuffer *intel_fb;
1404 struct drm_i915_gem_object *obj_priv;
1405 struct drm_gem_object *obj;
1406 int plane = intel_crtc->plane;
1407 unsigned long Start, Offset;
1408 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1409 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1410 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1411 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1412 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1413 u32 dspcntr;
1414
1415 switch (plane) {
1416 case 0:
1417 case 1:
1418 break;
1419 default:
1420 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1421 return -EINVAL;
1422 }
1423
1424 intel_fb = to_intel_framebuffer(fb);
1425 obj = intel_fb->obj;
1426 obj_priv = to_intel_bo(obj);
1427
1428 dspcntr = I915_READ(dspcntr_reg);
1429 /* Mask out pixel format bits in case we change it */
1430 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1431 switch (fb->bits_per_pixel) {
1432 case 8:
1433 dspcntr |= DISPPLANE_8BPP;
1434 break;
1435 case 16:
1436 if (fb->depth == 15)
1437 dspcntr |= DISPPLANE_15_16BPP;
1438 else
1439 dspcntr |= DISPPLANE_16BPP;
1440 break;
1441 case 24:
1442 case 32:
1443 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1444 break;
1445 default:
1446 DRM_ERROR("Unknown color depth\n");
1447 return -EINVAL;
1448 }
1449 if (IS_I965G(dev)) {
1450 if (obj_priv->tiling_mode != I915_TILING_NONE)
1451 dspcntr |= DISPPLANE_TILED;
1452 else
1453 dspcntr &= ~DISPPLANE_TILED;
1454 }
1455
1456 if (IS_IRONLAKE(dev))
1457 /* must disable */
1458 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1459
1460 I915_WRITE(dspcntr_reg, dspcntr);
1461
1462 Start = obj_priv->gtt_offset;
1463 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1464
1465 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1466 I915_WRITE(dspstride, fb->pitch);
1467 if (IS_I965G(dev)) {
1468 I915_WRITE(dspbase, Offset);
1469 I915_READ(dspbase);
1470 I915_WRITE(dspsurf, Start);
1471 I915_READ(dspsurf);
1472 I915_WRITE(dsptileoff, (y << 16) | x);
1473 } else {
1474 I915_WRITE(dspbase, Start + Offset);
1475 I915_READ(dspbase);
1476 }
1477
1478 if ((IS_I965G(dev) || plane == 0))
1479 intel_update_fbc(crtc, &crtc->mode);
1480
1481 intel_wait_for_vblank(dev);
1482 intel_increase_pllclock(crtc, true);
1483
1484 return 0;
1485 }
1486
1487 static int
1488 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1489 struct drm_framebuffer *old_fb)
1490 {
1491 struct drm_device *dev = crtc->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 struct drm_i915_master_private *master_priv;
1494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495 struct intel_framebuffer *intel_fb;
1496 struct drm_i915_gem_object *obj_priv;
1497 struct drm_gem_object *obj;
1498 int pipe = intel_crtc->pipe;
1499 int plane = intel_crtc->plane;
1500 unsigned long Start, Offset;
1501 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1502 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1503 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1504 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1505 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1506 u32 dspcntr;
1507 int ret;
1508
1509 /* no fb bound */
1510 if (!crtc->fb) {
1511 DRM_DEBUG_KMS("No FB bound\n");
1512 return 0;
1513 }
1514
1515 switch (plane) {
1516 case 0:
1517 case 1:
1518 break;
1519 default:
1520 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1521 return -EINVAL;
1522 }
1523
1524 intel_fb = to_intel_framebuffer(crtc->fb);
1525 obj = intel_fb->obj;
1526 obj_priv = to_intel_bo(obj);
1527
1528 mutex_lock(&dev->struct_mutex);
1529 ret = intel_pin_and_fence_fb_obj(dev, obj);
1530 if (ret != 0) {
1531 mutex_unlock(&dev->struct_mutex);
1532 return ret;
1533 }
1534
1535 ret = i915_gem_object_set_to_display_plane(obj);
1536 if (ret != 0) {
1537 i915_gem_object_unpin(obj);
1538 mutex_unlock(&dev->struct_mutex);
1539 return ret;
1540 }
1541
1542 dspcntr = I915_READ(dspcntr_reg);
1543 /* Mask out pixel format bits in case we change it */
1544 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545 switch (crtc->fb->bits_per_pixel) {
1546 case 8:
1547 dspcntr |= DISPPLANE_8BPP;
1548 break;
1549 case 16:
1550 if (crtc->fb->depth == 15)
1551 dspcntr |= DISPPLANE_15_16BPP;
1552 else
1553 dspcntr |= DISPPLANE_16BPP;
1554 break;
1555 case 24:
1556 case 32:
1557 if (crtc->fb->depth == 30)
1558 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1559 else
1560 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1561 break;
1562 default:
1563 DRM_ERROR("Unknown color depth\n");
1564 i915_gem_object_unpin(obj);
1565 mutex_unlock(&dev->struct_mutex);
1566 return -EINVAL;
1567 }
1568 if (IS_I965G(dev)) {
1569 if (obj_priv->tiling_mode != I915_TILING_NONE)
1570 dspcntr |= DISPPLANE_TILED;
1571 else
1572 dspcntr &= ~DISPPLANE_TILED;
1573 }
1574
1575 if (HAS_PCH_SPLIT(dev))
1576 /* must disable */
1577 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1578
1579 I915_WRITE(dspcntr_reg, dspcntr);
1580
1581 Start = obj_priv->gtt_offset;
1582 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1583
1584 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585 Start, Offset, x, y, crtc->fb->pitch);
1586 I915_WRITE(dspstride, crtc->fb->pitch);
1587 if (IS_I965G(dev)) {
1588 I915_WRITE(dspbase, Offset);
1589 I915_READ(dspbase);
1590 I915_WRITE(dspsurf, Start);
1591 I915_READ(dspsurf);
1592 I915_WRITE(dsptileoff, (y << 16) | x);
1593 } else {
1594 I915_WRITE(dspbase, Start + Offset);
1595 I915_READ(dspbase);
1596 }
1597
1598 if ((IS_I965G(dev) || plane == 0))
1599 intel_update_fbc(crtc, &crtc->mode);
1600
1601 intel_wait_for_vblank(dev);
1602
1603 if (old_fb) {
1604 intel_fb = to_intel_framebuffer(old_fb);
1605 obj_priv = to_intel_bo(intel_fb->obj);
1606 i915_gem_object_unpin(intel_fb->obj);
1607 }
1608 intel_increase_pllclock(crtc, true);
1609
1610 mutex_unlock(&dev->struct_mutex);
1611
1612 if (!dev->primary->master)
1613 return 0;
1614
1615 master_priv = dev->primary->master->driver_priv;
1616 if (!master_priv->sarea_priv)
1617 return 0;
1618
1619 if (pipe) {
1620 master_priv->sarea_priv->pipeB_x = x;
1621 master_priv->sarea_priv->pipeB_y = y;
1622 } else {
1623 master_priv->sarea_priv->pipeA_x = x;
1624 master_priv->sarea_priv->pipeA_y = y;
1625 }
1626
1627 return 0;
1628 }
1629
1630 /* Disable the VGA plane that we never use */
1631 static void i915_disable_vga (struct drm_device *dev)
1632 {
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 u8 sr1;
1635 u32 vga_reg;
1636
1637 if (HAS_PCH_SPLIT(dev))
1638 vga_reg = CPU_VGACNTRL;
1639 else
1640 vga_reg = VGACNTRL;
1641
1642 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1643 return;
1644
1645 I915_WRITE8(VGA_SR_INDEX, 1);
1646 sr1 = I915_READ8(VGA_SR_DATA);
1647 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1648 udelay(100);
1649
1650 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1651 }
1652
1653 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1654 {
1655 struct drm_device *dev = crtc->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 u32 dpa_ctl;
1658
1659 DRM_DEBUG_KMS("\n");
1660 dpa_ctl = I915_READ(DP_A);
1661 dpa_ctl &= ~DP_PLL_ENABLE;
1662 I915_WRITE(DP_A, dpa_ctl);
1663 }
1664
1665 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1666 {
1667 struct drm_device *dev = crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 dpa_ctl;
1670
1671 dpa_ctl = I915_READ(DP_A);
1672 dpa_ctl |= DP_PLL_ENABLE;
1673 I915_WRITE(DP_A, dpa_ctl);
1674 udelay(200);
1675 }
1676
1677
1678 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1679 {
1680 struct drm_device *dev = crtc->dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 u32 dpa_ctl;
1683
1684 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1685 dpa_ctl = I915_READ(DP_A);
1686 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1687
1688 if (clock < 200000) {
1689 u32 temp;
1690 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1691 /* workaround for 160Mhz:
1692 1) program 0x4600c bits 15:0 = 0x8124
1693 2) program 0x46010 bit 0 = 1
1694 3) program 0x46034 bit 24 = 1
1695 4) program 0x64000 bit 14 = 1
1696 */
1697 temp = I915_READ(0x4600c);
1698 temp &= 0xffff0000;
1699 I915_WRITE(0x4600c, temp | 0x8124);
1700
1701 temp = I915_READ(0x46010);
1702 I915_WRITE(0x46010, temp | 1);
1703
1704 temp = I915_READ(0x46034);
1705 I915_WRITE(0x46034, temp | (1 << 24));
1706 } else {
1707 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1708 }
1709 I915_WRITE(DP_A, dpa_ctl);
1710
1711 udelay(500);
1712 }
1713
1714 /* The FDI link training functions for ILK/Ibexpeak. */
1715 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1716 {
1717 struct drm_device *dev = crtc->dev;
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1720 int pipe = intel_crtc->pipe;
1721 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1722 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1723 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1724 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1725 u32 temp, tries = 0;
1726
1727 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1728 for train result */
1729 temp = I915_READ(fdi_rx_imr_reg);
1730 temp &= ~FDI_RX_SYMBOL_LOCK;
1731 temp &= ~FDI_RX_BIT_LOCK;
1732 I915_WRITE(fdi_rx_imr_reg, temp);
1733 I915_READ(fdi_rx_imr_reg);
1734 udelay(150);
1735
1736 /* enable CPU FDI TX and PCH FDI RX */
1737 temp = I915_READ(fdi_tx_reg);
1738 temp |= FDI_TX_ENABLE;
1739 temp &= ~(7 << 19);
1740 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1741 temp &= ~FDI_LINK_TRAIN_NONE;
1742 temp |= FDI_LINK_TRAIN_PATTERN_1;
1743 I915_WRITE(fdi_tx_reg, temp);
1744 I915_READ(fdi_tx_reg);
1745
1746 temp = I915_READ(fdi_rx_reg);
1747 temp &= ~FDI_LINK_TRAIN_NONE;
1748 temp |= FDI_LINK_TRAIN_PATTERN_1;
1749 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1750 I915_READ(fdi_rx_reg);
1751 udelay(150);
1752
1753 for (tries = 0; tries < 5; tries++) {
1754 temp = I915_READ(fdi_rx_iir_reg);
1755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1756
1757 if ((temp & FDI_RX_BIT_LOCK)) {
1758 DRM_DEBUG_KMS("FDI train 1 done.\n");
1759 I915_WRITE(fdi_rx_iir_reg,
1760 temp | FDI_RX_BIT_LOCK);
1761 break;
1762 }
1763 }
1764 if (tries == 5)
1765 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1766
1767 /* Train 2 */
1768 temp = I915_READ(fdi_tx_reg);
1769 temp &= ~FDI_LINK_TRAIN_NONE;
1770 temp |= FDI_LINK_TRAIN_PATTERN_2;
1771 I915_WRITE(fdi_tx_reg, temp);
1772
1773 temp = I915_READ(fdi_rx_reg);
1774 temp &= ~FDI_LINK_TRAIN_NONE;
1775 temp |= FDI_LINK_TRAIN_PATTERN_2;
1776 I915_WRITE(fdi_rx_reg, temp);
1777 udelay(150);
1778
1779 tries = 0;
1780
1781 for (tries = 0; tries < 5; tries++) {
1782 temp = I915_READ(fdi_rx_iir_reg);
1783 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1784
1785 if (temp & FDI_RX_SYMBOL_LOCK) {
1786 I915_WRITE(fdi_rx_iir_reg,
1787 temp | FDI_RX_SYMBOL_LOCK);
1788 DRM_DEBUG_KMS("FDI train 2 done.\n");
1789 break;
1790 }
1791 }
1792 if (tries == 5)
1793 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1794
1795 DRM_DEBUG_KMS("FDI train done\n");
1796 }
1797
1798 static int snb_b_fdi_train_param [] = {
1799 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1800 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1801 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1802 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1803 };
1804
1805 /* The FDI link training functions for SNB/Cougarpoint. */
1806 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1807 {
1808 struct drm_device *dev = crtc->dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1811 int pipe = intel_crtc->pipe;
1812 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1813 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1814 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1815 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1816 u32 temp, i;
1817
1818 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1819 for train result */
1820 temp = I915_READ(fdi_rx_imr_reg);
1821 temp &= ~FDI_RX_SYMBOL_LOCK;
1822 temp &= ~FDI_RX_BIT_LOCK;
1823 I915_WRITE(fdi_rx_imr_reg, temp);
1824 I915_READ(fdi_rx_imr_reg);
1825 udelay(150);
1826
1827 /* enable CPU FDI TX and PCH FDI RX */
1828 temp = I915_READ(fdi_tx_reg);
1829 temp |= FDI_TX_ENABLE;
1830 temp &= ~(7 << 19);
1831 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1832 temp &= ~FDI_LINK_TRAIN_NONE;
1833 temp |= FDI_LINK_TRAIN_PATTERN_1;
1834 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1835 /* SNB-B */
1836 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1837 I915_WRITE(fdi_tx_reg, temp);
1838 I915_READ(fdi_tx_reg);
1839
1840 temp = I915_READ(fdi_rx_reg);
1841 if (HAS_PCH_CPT(dev)) {
1842 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1843 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1844 } else {
1845 temp &= ~FDI_LINK_TRAIN_NONE;
1846 temp |= FDI_LINK_TRAIN_PATTERN_1;
1847 }
1848 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1849 I915_READ(fdi_rx_reg);
1850 udelay(150);
1851
1852 for (i = 0; i < 4; i++ ) {
1853 temp = I915_READ(fdi_tx_reg);
1854 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1855 temp |= snb_b_fdi_train_param[i];
1856 I915_WRITE(fdi_tx_reg, temp);
1857 udelay(500);
1858
1859 temp = I915_READ(fdi_rx_iir_reg);
1860 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1861
1862 if (temp & FDI_RX_BIT_LOCK) {
1863 I915_WRITE(fdi_rx_iir_reg,
1864 temp | FDI_RX_BIT_LOCK);
1865 DRM_DEBUG_KMS("FDI train 1 done.\n");
1866 break;
1867 }
1868 }
1869 if (i == 4)
1870 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1871
1872 /* Train 2 */
1873 temp = I915_READ(fdi_tx_reg);
1874 temp &= ~FDI_LINK_TRAIN_NONE;
1875 temp |= FDI_LINK_TRAIN_PATTERN_2;
1876 if (IS_GEN6(dev)) {
1877 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1878 /* SNB-B */
1879 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1880 }
1881 I915_WRITE(fdi_tx_reg, temp);
1882
1883 temp = I915_READ(fdi_rx_reg);
1884 if (HAS_PCH_CPT(dev)) {
1885 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1886 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1887 } else {
1888 temp &= ~FDI_LINK_TRAIN_NONE;
1889 temp |= FDI_LINK_TRAIN_PATTERN_2;
1890 }
1891 I915_WRITE(fdi_rx_reg, temp);
1892 udelay(150);
1893
1894 for (i = 0; i < 4; i++ ) {
1895 temp = I915_READ(fdi_tx_reg);
1896 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1897 temp |= snb_b_fdi_train_param[i];
1898 I915_WRITE(fdi_tx_reg, temp);
1899 udelay(500);
1900
1901 temp = I915_READ(fdi_rx_iir_reg);
1902 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1903
1904 if (temp & FDI_RX_SYMBOL_LOCK) {
1905 I915_WRITE(fdi_rx_iir_reg,
1906 temp | FDI_RX_SYMBOL_LOCK);
1907 DRM_DEBUG_KMS("FDI train 2 done.\n");
1908 break;
1909 }
1910 }
1911 if (i == 4)
1912 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1913
1914 DRM_DEBUG_KMS("FDI train done.\n");
1915 }
1916
1917 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1918 {
1919 struct drm_device *dev = crtc->dev;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922 int pipe = intel_crtc->pipe;
1923 int plane = intel_crtc->plane;
1924 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1925 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1926 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1927 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1928 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1929 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1930 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1931 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1932 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1933 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1934 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1935 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1936 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1937 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1938 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1939 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1940 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1941 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1942 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1943 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1944 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1945 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1946 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1947 u32 temp;
1948 int n;
1949 u32 pipe_bpc;
1950
1951 temp = I915_READ(pipeconf_reg);
1952 pipe_bpc = temp & PIPE_BPC_MASK;
1953
1954 /* XXX: When our outputs are all unaware of DPMS modes other than off
1955 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1956 */
1957 switch (mode) {
1958 case DRM_MODE_DPMS_ON:
1959 case DRM_MODE_DPMS_STANDBY:
1960 case DRM_MODE_DPMS_SUSPEND:
1961 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1962
1963 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1964 temp = I915_READ(PCH_LVDS);
1965 if ((temp & LVDS_PORT_EN) == 0) {
1966 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1967 POSTING_READ(PCH_LVDS);
1968 }
1969 }
1970
1971 if (HAS_eDP) {
1972 /* enable eDP PLL */
1973 ironlake_enable_pll_edp(crtc);
1974 } else {
1975
1976 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1977 temp = I915_READ(fdi_rx_reg);
1978 /*
1979 * make the BPC in FDI Rx be consistent with that in
1980 * pipeconf reg.
1981 */
1982 temp &= ~(0x7 << 16);
1983 temp |= (pipe_bpc << 11);
1984 temp &= ~(7 << 19);
1985 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1986 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1987 I915_READ(fdi_rx_reg);
1988 udelay(200);
1989
1990 /* Switch from Rawclk to PCDclk */
1991 temp = I915_READ(fdi_rx_reg);
1992 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1993 I915_READ(fdi_rx_reg);
1994 udelay(200);
1995
1996 /* Enable CPU FDI TX PLL, always on for Ironlake */
1997 temp = I915_READ(fdi_tx_reg);
1998 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1999 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
2000 I915_READ(fdi_tx_reg);
2001 udelay(100);
2002 }
2003 }
2004
2005 /* Enable panel fitting for LVDS */
2006 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2007 || HAS_eDP || intel_pch_has_edp(crtc)) {
2008 temp = I915_READ(pf_ctl_reg);
2009 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
2010
2011 /* currently full aspect */
2012 I915_WRITE(pf_win_pos, 0);
2013
2014 I915_WRITE(pf_win_size,
2015 (dev_priv->panel_fixed_mode->hdisplay << 16) |
2016 (dev_priv->panel_fixed_mode->vdisplay));
2017 }
2018
2019 /* Enable CPU pipe */
2020 temp = I915_READ(pipeconf_reg);
2021 if ((temp & PIPEACONF_ENABLE) == 0) {
2022 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2023 I915_READ(pipeconf_reg);
2024 udelay(100);
2025 }
2026
2027 /* configure and enable CPU plane */
2028 temp = I915_READ(dspcntr_reg);
2029 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2030 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2031 /* Flush the plane changes */
2032 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2033 }
2034
2035 if (!HAS_eDP) {
2036 /* For PCH output, training FDI link */
2037 if (IS_GEN6(dev))
2038 gen6_fdi_link_train(crtc);
2039 else
2040 ironlake_fdi_link_train(crtc);
2041
2042 /* enable PCH DPLL */
2043 temp = I915_READ(pch_dpll_reg);
2044 if ((temp & DPLL_VCO_ENABLE) == 0) {
2045 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2046 I915_READ(pch_dpll_reg);
2047 }
2048 udelay(200);
2049
2050 if (HAS_PCH_CPT(dev)) {
2051 /* Be sure PCH DPLL SEL is set */
2052 temp = I915_READ(PCH_DPLL_SEL);
2053 if (trans_dpll_sel == 0 &&
2054 (temp & TRANSA_DPLL_ENABLE) == 0)
2055 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2056 else if (trans_dpll_sel == 1 &&
2057 (temp & TRANSB_DPLL_ENABLE) == 0)
2058 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2059 I915_WRITE(PCH_DPLL_SEL, temp);
2060 I915_READ(PCH_DPLL_SEL);
2061 }
2062
2063 /* set transcoder timing */
2064 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2065 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2066 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2067
2068 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2069 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2070 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2071
2072 /* enable normal train */
2073 temp = I915_READ(fdi_tx_reg);
2074 temp &= ~FDI_LINK_TRAIN_NONE;
2075 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2076 FDI_TX_ENHANCE_FRAME_ENABLE);
2077 I915_READ(fdi_tx_reg);
2078
2079 temp = I915_READ(fdi_rx_reg);
2080 if (HAS_PCH_CPT(dev)) {
2081 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2082 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2083 } else {
2084 temp &= ~FDI_LINK_TRAIN_NONE;
2085 temp |= FDI_LINK_TRAIN_NONE;
2086 }
2087 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2088 I915_READ(fdi_rx_reg);
2089
2090 /* wait one idle pattern time */
2091 udelay(100);
2092
2093 /* For PCH DP, enable TRANS_DP_CTL */
2094 if (HAS_PCH_CPT(dev) &&
2095 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2096 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2097 int reg;
2098
2099 reg = I915_READ(trans_dp_ctl);
2100 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2101 TRANS_DP_SYNC_MASK);
2102 reg |= (TRANS_DP_OUTPUT_ENABLE |
2103 TRANS_DP_ENH_FRAMING);
2104
2105 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2106 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2107 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2108 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2109
2110 switch (intel_trans_dp_port_sel(crtc)) {
2111 case PCH_DP_B:
2112 reg |= TRANS_DP_PORT_SEL_B;
2113 break;
2114 case PCH_DP_C:
2115 reg |= TRANS_DP_PORT_SEL_C;
2116 break;
2117 case PCH_DP_D:
2118 reg |= TRANS_DP_PORT_SEL_D;
2119 break;
2120 default:
2121 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2122 reg |= TRANS_DP_PORT_SEL_B;
2123 break;
2124 }
2125
2126 I915_WRITE(trans_dp_ctl, reg);
2127 POSTING_READ(trans_dp_ctl);
2128 }
2129
2130 /* enable PCH transcoder */
2131 temp = I915_READ(transconf_reg);
2132 /*
2133 * make the BPC in transcoder be consistent with
2134 * that in pipeconf reg.
2135 */
2136 temp &= ~PIPE_BPC_MASK;
2137 temp |= pipe_bpc;
2138 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2139 I915_READ(transconf_reg);
2140
2141 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2142 ;
2143
2144 }
2145
2146 intel_crtc_load_lut(crtc);
2147
2148 intel_update_fbc(crtc, &crtc->mode);
2149
2150 break;
2151 case DRM_MODE_DPMS_OFF:
2152 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2153
2154 drm_vblank_off(dev, pipe);
2155 /* Disable display plane */
2156 temp = I915_READ(dspcntr_reg);
2157 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2158 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2159 /* Flush the plane changes */
2160 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2161 I915_READ(dspbase_reg);
2162 }
2163
2164 if (dev_priv->cfb_plane == plane &&
2165 dev_priv->display.disable_fbc)
2166 dev_priv->display.disable_fbc(dev);
2167
2168 i915_disable_vga(dev);
2169
2170 /* disable cpu pipe, disable after all planes disabled */
2171 temp = I915_READ(pipeconf_reg);
2172 if ((temp & PIPEACONF_ENABLE) != 0) {
2173 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2174 I915_READ(pipeconf_reg);
2175 n = 0;
2176 /* wait for cpu pipe off, pipe state */
2177 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2178 n++;
2179 if (n < 60) {
2180 udelay(500);
2181 continue;
2182 } else {
2183 DRM_DEBUG_KMS("pipe %d off delay\n",
2184 pipe);
2185 break;
2186 }
2187 }
2188 } else
2189 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2190
2191 udelay(100);
2192
2193 /* Disable PF */
2194 temp = I915_READ(pf_ctl_reg);
2195 if ((temp & PF_ENABLE) != 0) {
2196 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2197 I915_READ(pf_ctl_reg);
2198 }
2199 I915_WRITE(pf_win_size, 0);
2200 POSTING_READ(pf_win_size);
2201
2202
2203 /* disable CPU FDI tx and PCH FDI rx */
2204 temp = I915_READ(fdi_tx_reg);
2205 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2206 I915_READ(fdi_tx_reg);
2207
2208 temp = I915_READ(fdi_rx_reg);
2209 /* BPC in FDI rx is consistent with that in pipeconf */
2210 temp &= ~(0x07 << 16);
2211 temp |= (pipe_bpc << 11);
2212 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2213 I915_READ(fdi_rx_reg);
2214
2215 udelay(100);
2216
2217 /* still set train pattern 1 */
2218 temp = I915_READ(fdi_tx_reg);
2219 temp &= ~FDI_LINK_TRAIN_NONE;
2220 temp |= FDI_LINK_TRAIN_PATTERN_1;
2221 I915_WRITE(fdi_tx_reg, temp);
2222 POSTING_READ(fdi_tx_reg);
2223
2224 temp = I915_READ(fdi_rx_reg);
2225 if (HAS_PCH_CPT(dev)) {
2226 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2227 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2228 } else {
2229 temp &= ~FDI_LINK_TRAIN_NONE;
2230 temp |= FDI_LINK_TRAIN_PATTERN_1;
2231 }
2232 I915_WRITE(fdi_rx_reg, temp);
2233 POSTING_READ(fdi_rx_reg);
2234
2235 udelay(100);
2236
2237 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2238 temp = I915_READ(PCH_LVDS);
2239 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2240 I915_READ(PCH_LVDS);
2241 udelay(100);
2242 }
2243
2244 /* disable PCH transcoder */
2245 temp = I915_READ(transconf_reg);
2246 if ((temp & TRANS_ENABLE) != 0) {
2247 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2248 I915_READ(transconf_reg);
2249 n = 0;
2250 /* wait for PCH transcoder off, transcoder state */
2251 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2252 n++;
2253 if (n < 60) {
2254 udelay(500);
2255 continue;
2256 } else {
2257 DRM_DEBUG_KMS("transcoder %d off "
2258 "delay\n", pipe);
2259 break;
2260 }
2261 }
2262 }
2263
2264 temp = I915_READ(transconf_reg);
2265 /* BPC in transcoder is consistent with that in pipeconf */
2266 temp &= ~PIPE_BPC_MASK;
2267 temp |= pipe_bpc;
2268 I915_WRITE(transconf_reg, temp);
2269 I915_READ(transconf_reg);
2270 udelay(100);
2271
2272 if (HAS_PCH_CPT(dev)) {
2273 /* disable TRANS_DP_CTL */
2274 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2275 int reg;
2276
2277 reg = I915_READ(trans_dp_ctl);
2278 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2279 I915_WRITE(trans_dp_ctl, reg);
2280 POSTING_READ(trans_dp_ctl);
2281
2282 /* disable DPLL_SEL */
2283 temp = I915_READ(PCH_DPLL_SEL);
2284 if (trans_dpll_sel == 0)
2285 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2286 else
2287 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2288 I915_WRITE(PCH_DPLL_SEL, temp);
2289 I915_READ(PCH_DPLL_SEL);
2290
2291 }
2292
2293 /* disable PCH DPLL */
2294 temp = I915_READ(pch_dpll_reg);
2295 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2296 I915_READ(pch_dpll_reg);
2297
2298 if (HAS_eDP) {
2299 ironlake_disable_pll_edp(crtc);
2300 }
2301
2302 /* Switch from PCDclk to Rawclk */
2303 temp = I915_READ(fdi_rx_reg);
2304 temp &= ~FDI_SEL_PCDCLK;
2305 I915_WRITE(fdi_rx_reg, temp);
2306 I915_READ(fdi_rx_reg);
2307
2308 /* Disable CPU FDI TX PLL */
2309 temp = I915_READ(fdi_tx_reg);
2310 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2311 I915_READ(fdi_tx_reg);
2312 udelay(100);
2313
2314 temp = I915_READ(fdi_rx_reg);
2315 temp &= ~FDI_RX_PLL_ENABLE;
2316 I915_WRITE(fdi_rx_reg, temp);
2317 I915_READ(fdi_rx_reg);
2318
2319 /* Wait for the clocks to turn off. */
2320 udelay(100);
2321 break;
2322 }
2323 }
2324
2325 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2326 {
2327 struct intel_overlay *overlay;
2328 int ret;
2329
2330 if (!enable && intel_crtc->overlay) {
2331 overlay = intel_crtc->overlay;
2332 mutex_lock(&overlay->dev->struct_mutex);
2333 for (;;) {
2334 ret = intel_overlay_switch_off(overlay);
2335 if (ret == 0)
2336 break;
2337
2338 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2339 if (ret != 0) {
2340 /* overlay doesn't react anymore. Usually
2341 * results in a black screen and an unkillable
2342 * X server. */
2343 BUG();
2344 overlay->hw_wedged = HW_WEDGED;
2345 break;
2346 }
2347 }
2348 mutex_unlock(&overlay->dev->struct_mutex);
2349 }
2350 /* Let userspace switch the overlay on again. In most cases userspace
2351 * has to recompute where to put it anyway. */
2352
2353 return;
2354 }
2355
2356 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2357 {
2358 struct drm_device *dev = crtc->dev;
2359 struct drm_i915_private *dev_priv = dev->dev_private;
2360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2361 int pipe = intel_crtc->pipe;
2362 int plane = intel_crtc->plane;
2363 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2364 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2365 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2366 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2367 u32 temp;
2368
2369 /* XXX: When our outputs are all unaware of DPMS modes other than off
2370 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2371 */
2372 switch (mode) {
2373 case DRM_MODE_DPMS_ON:
2374 case DRM_MODE_DPMS_STANDBY:
2375 case DRM_MODE_DPMS_SUSPEND:
2376 intel_update_watermarks(dev);
2377
2378 /* Enable the DPLL */
2379 temp = I915_READ(dpll_reg);
2380 if ((temp & DPLL_VCO_ENABLE) == 0) {
2381 I915_WRITE(dpll_reg, temp);
2382 I915_READ(dpll_reg);
2383 /* Wait for the clocks to stabilize. */
2384 udelay(150);
2385 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2386 I915_READ(dpll_reg);
2387 /* Wait for the clocks to stabilize. */
2388 udelay(150);
2389 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2390 I915_READ(dpll_reg);
2391 /* Wait for the clocks to stabilize. */
2392 udelay(150);
2393 }
2394
2395 /* Enable the pipe */
2396 temp = I915_READ(pipeconf_reg);
2397 if ((temp & PIPEACONF_ENABLE) == 0)
2398 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2399
2400 /* Enable the plane */
2401 temp = I915_READ(dspcntr_reg);
2402 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2403 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2404 /* Flush the plane changes */
2405 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2406 }
2407
2408 intel_crtc_load_lut(crtc);
2409
2410 if ((IS_I965G(dev) || plane == 0))
2411 intel_update_fbc(crtc, &crtc->mode);
2412
2413 /* Give the overlay scaler a chance to enable if it's on this pipe */
2414 intel_crtc_dpms_overlay(intel_crtc, true);
2415 break;
2416 case DRM_MODE_DPMS_OFF:
2417 intel_update_watermarks(dev);
2418
2419 /* Give the overlay scaler a chance to disable if it's on this pipe */
2420 intel_crtc_dpms_overlay(intel_crtc, false);
2421 drm_vblank_off(dev, pipe);
2422
2423 if (dev_priv->cfb_plane == plane &&
2424 dev_priv->display.disable_fbc)
2425 dev_priv->display.disable_fbc(dev);
2426
2427 /* Disable the VGA plane that we never use */
2428 i915_disable_vga(dev);
2429
2430 /* Disable display plane */
2431 temp = I915_READ(dspcntr_reg);
2432 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2433 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2434 /* Flush the plane changes */
2435 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2436 I915_READ(dspbase_reg);
2437 }
2438
2439 if (!IS_I9XX(dev)) {
2440 /* Wait for vblank for the disable to take effect */
2441 intel_wait_for_vblank(dev);
2442 }
2443
2444 /* Don't disable pipe A or pipe A PLLs if needed */
2445 if (pipeconf_reg == PIPEACONF &&
2446 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2447 goto skip_pipe_off;
2448
2449 /* Next, disable display pipes */
2450 temp = I915_READ(pipeconf_reg);
2451 if ((temp & PIPEACONF_ENABLE) != 0) {
2452 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2453 I915_READ(pipeconf_reg);
2454 }
2455
2456 /* Wait for vblank for the disable to take effect. */
2457 intel_wait_for_vblank(dev);
2458
2459 temp = I915_READ(dpll_reg);
2460 if ((temp & DPLL_VCO_ENABLE) != 0) {
2461 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2462 I915_READ(dpll_reg);
2463 }
2464 skip_pipe_off:
2465 /* Wait for the clocks to turn off. */
2466 udelay(150);
2467 break;
2468 }
2469 }
2470
2471 /**
2472 * Sets the power management mode of the pipe and plane.
2473 */
2474 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2475 {
2476 struct drm_device *dev = crtc->dev;
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct drm_i915_master_private *master_priv;
2479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2480 int pipe = intel_crtc->pipe;
2481 bool enabled;
2482
2483 dev_priv->display.dpms(crtc, mode);
2484
2485 intel_crtc->dpms_mode = mode;
2486
2487 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2488 intel_crtc_update_cursor(crtc);
2489
2490 if (!dev->primary->master)
2491 return;
2492
2493 master_priv = dev->primary->master->driver_priv;
2494 if (!master_priv->sarea_priv)
2495 return;
2496
2497 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2498
2499 switch (pipe) {
2500 case 0:
2501 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2502 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2503 break;
2504 case 1:
2505 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2506 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2507 break;
2508 default:
2509 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2510 break;
2511 }
2512 }
2513
2514 static void intel_crtc_prepare (struct drm_crtc *crtc)
2515 {
2516 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2517 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2518 }
2519
2520 static void intel_crtc_commit (struct drm_crtc *crtc)
2521 {
2522 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2523 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2524 }
2525
2526 void intel_encoder_prepare (struct drm_encoder *encoder)
2527 {
2528 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2529 /* lvds has its own version of prepare see intel_lvds_prepare */
2530 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2531 }
2532
2533 void intel_encoder_commit (struct drm_encoder *encoder)
2534 {
2535 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2536 /* lvds has its own version of commit see intel_lvds_commit */
2537 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2538 }
2539
2540 void intel_encoder_destroy(struct drm_encoder *encoder)
2541 {
2542 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2543
2544 if (intel_encoder->ddc_bus)
2545 intel_i2c_destroy(intel_encoder->ddc_bus);
2546
2547 if (intel_encoder->i2c_bus)
2548 intel_i2c_destroy(intel_encoder->i2c_bus);
2549
2550 drm_encoder_cleanup(encoder);
2551 kfree(intel_encoder);
2552 }
2553
2554 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2555 struct drm_display_mode *mode,
2556 struct drm_display_mode *adjusted_mode)
2557 {
2558 struct drm_device *dev = crtc->dev;
2559 if (HAS_PCH_SPLIT(dev)) {
2560 /* FDI link clock is fixed at 2.7G */
2561 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2562 return false;
2563 }
2564 return true;
2565 }
2566
2567 static int i945_get_display_clock_speed(struct drm_device *dev)
2568 {
2569 return 400000;
2570 }
2571
2572 static int i915_get_display_clock_speed(struct drm_device *dev)
2573 {
2574 return 333000;
2575 }
2576
2577 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2578 {
2579 return 200000;
2580 }
2581
2582 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2583 {
2584 u16 gcfgc = 0;
2585
2586 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2587
2588 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2589 return 133000;
2590 else {
2591 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2592 case GC_DISPLAY_CLOCK_333_MHZ:
2593 return 333000;
2594 default:
2595 case GC_DISPLAY_CLOCK_190_200_MHZ:
2596 return 190000;
2597 }
2598 }
2599 }
2600
2601 static int i865_get_display_clock_speed(struct drm_device *dev)
2602 {
2603 return 266000;
2604 }
2605
2606 static int i855_get_display_clock_speed(struct drm_device *dev)
2607 {
2608 u16 hpllcc = 0;
2609 /* Assume that the hardware is in the high speed state. This
2610 * should be the default.
2611 */
2612 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2613 case GC_CLOCK_133_200:
2614 case GC_CLOCK_100_200:
2615 return 200000;
2616 case GC_CLOCK_166_250:
2617 return 250000;
2618 case GC_CLOCK_100_133:
2619 return 133000;
2620 }
2621
2622 /* Shouldn't happen */
2623 return 0;
2624 }
2625
2626 static int i830_get_display_clock_speed(struct drm_device *dev)
2627 {
2628 return 133000;
2629 }
2630
2631 /**
2632 * Return the pipe currently connected to the panel fitter,
2633 * or -1 if the panel fitter is not present or not in use
2634 */
2635 int intel_panel_fitter_pipe (struct drm_device *dev)
2636 {
2637 struct drm_i915_private *dev_priv = dev->dev_private;
2638 u32 pfit_control;
2639
2640 /* i830 doesn't have a panel fitter */
2641 if (IS_I830(dev))
2642 return -1;
2643
2644 pfit_control = I915_READ(PFIT_CONTROL);
2645
2646 /* See if the panel fitter is in use */
2647 if ((pfit_control & PFIT_ENABLE) == 0)
2648 return -1;
2649
2650 /* 965 can place panel fitter on either pipe */
2651 if (IS_I965G(dev))
2652 return (pfit_control >> 29) & 0x3;
2653
2654 /* older chips can only use pipe 1 */
2655 return 1;
2656 }
2657
2658 struct fdi_m_n {
2659 u32 tu;
2660 u32 gmch_m;
2661 u32 gmch_n;
2662 u32 link_m;
2663 u32 link_n;
2664 };
2665
2666 static void
2667 fdi_reduce_ratio(u32 *num, u32 *den)
2668 {
2669 while (*num > 0xffffff || *den > 0xffffff) {
2670 *num >>= 1;
2671 *den >>= 1;
2672 }
2673 }
2674
2675 #define DATA_N 0x800000
2676 #define LINK_N 0x80000
2677
2678 static void
2679 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2680 int link_clock, struct fdi_m_n *m_n)
2681 {
2682 u64 temp;
2683
2684 m_n->tu = 64; /* default size */
2685
2686 temp = (u64) DATA_N * pixel_clock;
2687 temp = div_u64(temp, link_clock);
2688 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2689 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2690 m_n->gmch_n = DATA_N;
2691 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2692
2693 temp = (u64) LINK_N * pixel_clock;
2694 m_n->link_m = div_u64(temp, link_clock);
2695 m_n->link_n = LINK_N;
2696 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2697 }
2698
2699
2700 struct intel_watermark_params {
2701 unsigned long fifo_size;
2702 unsigned long max_wm;
2703 unsigned long default_wm;
2704 unsigned long guard_size;
2705 unsigned long cacheline_size;
2706 };
2707
2708 /* Pineview has different values for various configs */
2709 static struct intel_watermark_params pineview_display_wm = {
2710 PINEVIEW_DISPLAY_FIFO,
2711 PINEVIEW_MAX_WM,
2712 PINEVIEW_DFT_WM,
2713 PINEVIEW_GUARD_WM,
2714 PINEVIEW_FIFO_LINE_SIZE
2715 };
2716 static struct intel_watermark_params pineview_display_hplloff_wm = {
2717 PINEVIEW_DISPLAY_FIFO,
2718 PINEVIEW_MAX_WM,
2719 PINEVIEW_DFT_HPLLOFF_WM,
2720 PINEVIEW_GUARD_WM,
2721 PINEVIEW_FIFO_LINE_SIZE
2722 };
2723 static struct intel_watermark_params pineview_cursor_wm = {
2724 PINEVIEW_CURSOR_FIFO,
2725 PINEVIEW_CURSOR_MAX_WM,
2726 PINEVIEW_CURSOR_DFT_WM,
2727 PINEVIEW_CURSOR_GUARD_WM,
2728 PINEVIEW_FIFO_LINE_SIZE,
2729 };
2730 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2731 PINEVIEW_CURSOR_FIFO,
2732 PINEVIEW_CURSOR_MAX_WM,
2733 PINEVIEW_CURSOR_DFT_WM,
2734 PINEVIEW_CURSOR_GUARD_WM,
2735 PINEVIEW_FIFO_LINE_SIZE
2736 };
2737 static struct intel_watermark_params g4x_wm_info = {
2738 G4X_FIFO_SIZE,
2739 G4X_MAX_WM,
2740 G4X_MAX_WM,
2741 2,
2742 G4X_FIFO_LINE_SIZE,
2743 };
2744 static struct intel_watermark_params g4x_cursor_wm_info = {
2745 I965_CURSOR_FIFO,
2746 I965_CURSOR_MAX_WM,
2747 I965_CURSOR_DFT_WM,
2748 2,
2749 G4X_FIFO_LINE_SIZE,
2750 };
2751 static struct intel_watermark_params i965_cursor_wm_info = {
2752 I965_CURSOR_FIFO,
2753 I965_CURSOR_MAX_WM,
2754 I965_CURSOR_DFT_WM,
2755 2,
2756 I915_FIFO_LINE_SIZE,
2757 };
2758 static struct intel_watermark_params i945_wm_info = {
2759 I945_FIFO_SIZE,
2760 I915_MAX_WM,
2761 1,
2762 2,
2763 I915_FIFO_LINE_SIZE
2764 };
2765 static struct intel_watermark_params i915_wm_info = {
2766 I915_FIFO_SIZE,
2767 I915_MAX_WM,
2768 1,
2769 2,
2770 I915_FIFO_LINE_SIZE
2771 };
2772 static struct intel_watermark_params i855_wm_info = {
2773 I855GM_FIFO_SIZE,
2774 I915_MAX_WM,
2775 1,
2776 2,
2777 I830_FIFO_LINE_SIZE
2778 };
2779 static struct intel_watermark_params i830_wm_info = {
2780 I830_FIFO_SIZE,
2781 I915_MAX_WM,
2782 1,
2783 2,
2784 I830_FIFO_LINE_SIZE
2785 };
2786
2787 static struct intel_watermark_params ironlake_display_wm_info = {
2788 ILK_DISPLAY_FIFO,
2789 ILK_DISPLAY_MAXWM,
2790 ILK_DISPLAY_DFTWM,
2791 2,
2792 ILK_FIFO_LINE_SIZE
2793 };
2794
2795 static struct intel_watermark_params ironlake_cursor_wm_info = {
2796 ILK_CURSOR_FIFO,
2797 ILK_CURSOR_MAXWM,
2798 ILK_CURSOR_DFTWM,
2799 2,
2800 ILK_FIFO_LINE_SIZE
2801 };
2802
2803 static struct intel_watermark_params ironlake_display_srwm_info = {
2804 ILK_DISPLAY_SR_FIFO,
2805 ILK_DISPLAY_MAX_SRWM,
2806 ILK_DISPLAY_DFT_SRWM,
2807 2,
2808 ILK_FIFO_LINE_SIZE
2809 };
2810
2811 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2812 ILK_CURSOR_SR_FIFO,
2813 ILK_CURSOR_MAX_SRWM,
2814 ILK_CURSOR_DFT_SRWM,
2815 2,
2816 ILK_FIFO_LINE_SIZE
2817 };
2818
2819 /**
2820 * intel_calculate_wm - calculate watermark level
2821 * @clock_in_khz: pixel clock
2822 * @wm: chip FIFO params
2823 * @pixel_size: display pixel size
2824 * @latency_ns: memory latency for the platform
2825 *
2826 * Calculate the watermark level (the level at which the display plane will
2827 * start fetching from memory again). Each chip has a different display
2828 * FIFO size and allocation, so the caller needs to figure that out and pass
2829 * in the correct intel_watermark_params structure.
2830 *
2831 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2832 * on the pixel size. When it reaches the watermark level, it'll start
2833 * fetching FIFO line sized based chunks from memory until the FIFO fills
2834 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2835 * will occur, and a display engine hang could result.
2836 */
2837 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2838 struct intel_watermark_params *wm,
2839 int pixel_size,
2840 unsigned long latency_ns)
2841 {
2842 long entries_required, wm_size;
2843
2844 /*
2845 * Note: we need to make sure we don't overflow for various clock &
2846 * latency values.
2847 * clocks go from a few thousand to several hundred thousand.
2848 * latency is usually a few thousand
2849 */
2850 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2851 1000;
2852 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2853
2854 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2855
2856 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2857
2858 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2859
2860 /* Don't promote wm_size to unsigned... */
2861 if (wm_size > (long)wm->max_wm)
2862 wm_size = wm->max_wm;
2863 if (wm_size <= 0) {
2864 wm_size = wm->default_wm;
2865 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2866 " entries required = %ld, available = %lu.\n",
2867 entries_required + wm->guard_size,
2868 wm->fifo_size);
2869 }
2870
2871 return wm_size;
2872 }
2873
2874 struct cxsr_latency {
2875 int is_desktop;
2876 int is_ddr3;
2877 unsigned long fsb_freq;
2878 unsigned long mem_freq;
2879 unsigned long display_sr;
2880 unsigned long display_hpll_disable;
2881 unsigned long cursor_sr;
2882 unsigned long cursor_hpll_disable;
2883 };
2884
2885 static const struct cxsr_latency cxsr_latency_table[] = {
2886 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2887 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2888 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2889 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2890 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2891
2892 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2893 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2894 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2895 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2896 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2897
2898 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2899 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2900 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2901 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2902 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2903
2904 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2905 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2906 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2907 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2908 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2909
2910 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2911 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2912 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2913 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2914 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2915
2916 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2917 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2918 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2919 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2920 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2921 };
2922
2923 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2924 int is_ddr3,
2925 int fsb,
2926 int mem)
2927 {
2928 const struct cxsr_latency *latency;
2929 int i;
2930
2931 if (fsb == 0 || mem == 0)
2932 return NULL;
2933
2934 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2935 latency = &cxsr_latency_table[i];
2936 if (is_desktop == latency->is_desktop &&
2937 is_ddr3 == latency->is_ddr3 &&
2938 fsb == latency->fsb_freq && mem == latency->mem_freq)
2939 return latency;
2940 }
2941
2942 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2943
2944 return NULL;
2945 }
2946
2947 static void pineview_disable_cxsr(struct drm_device *dev)
2948 {
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951 /* deactivate cxsr */
2952 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2953 }
2954
2955 /*
2956 * Latency for FIFO fetches is dependent on several factors:
2957 * - memory configuration (speed, channels)
2958 * - chipset
2959 * - current MCH state
2960 * It can be fairly high in some situations, so here we assume a fairly
2961 * pessimal value. It's a tradeoff between extra memory fetches (if we
2962 * set this value too high, the FIFO will fetch frequently to stay full)
2963 * and power consumption (set it too low to save power and we might see
2964 * FIFO underruns and display "flicker").
2965 *
2966 * A value of 5us seems to be a good balance; safe for very low end
2967 * platforms but not overly aggressive on lower latency configs.
2968 */
2969 static const int latency_ns = 5000;
2970
2971 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2972 {
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2974 uint32_t dsparb = I915_READ(DSPARB);
2975 int size;
2976
2977 size = dsparb & 0x7f;
2978 if (plane)
2979 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2980
2981 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2982 plane ? "B" : "A", size);
2983
2984 return size;
2985 }
2986
2987 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2988 {
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2990 uint32_t dsparb = I915_READ(DSPARB);
2991 int size;
2992
2993 size = dsparb & 0x1ff;
2994 if (plane)
2995 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2996 size >>= 1; /* Convert to cachelines */
2997
2998 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2999 plane ? "B" : "A", size);
3000
3001 return size;
3002 }
3003
3004 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3005 {
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 uint32_t dsparb = I915_READ(DSPARB);
3008 int size;
3009
3010 size = dsparb & 0x7f;
3011 size >>= 2; /* Convert to cachelines */
3012
3013 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3014 plane ? "B" : "A",
3015 size);
3016
3017 return size;
3018 }
3019
3020 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3021 {
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 uint32_t dsparb = I915_READ(DSPARB);
3024 int size;
3025
3026 size = dsparb & 0x7f;
3027 size >>= 1; /* Convert to cachelines */
3028
3029 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3030 plane ? "B" : "A", size);
3031
3032 return size;
3033 }
3034
3035 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3036 int planeb_clock, int sr_hdisplay, int unused,
3037 int pixel_size)
3038 {
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 const struct cxsr_latency *latency;
3041 u32 reg;
3042 unsigned long wm;
3043 int sr_clock;
3044
3045 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3046 dev_priv->fsb_freq, dev_priv->mem_freq);
3047 if (!latency) {
3048 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3049 pineview_disable_cxsr(dev);
3050 return;
3051 }
3052
3053 if (!planea_clock || !planeb_clock) {
3054 sr_clock = planea_clock ? planea_clock : planeb_clock;
3055
3056 /* Display SR */
3057 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3058 pixel_size, latency->display_sr);
3059 reg = I915_READ(DSPFW1);
3060 reg &= ~DSPFW_SR_MASK;
3061 reg |= wm << DSPFW_SR_SHIFT;
3062 I915_WRITE(DSPFW1, reg);
3063 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3064
3065 /* cursor SR */
3066 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3067 pixel_size, latency->cursor_sr);
3068 reg = I915_READ(DSPFW3);
3069 reg &= ~DSPFW_CURSOR_SR_MASK;
3070 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3071 I915_WRITE(DSPFW3, reg);
3072
3073 /* Display HPLL off SR */
3074 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3075 pixel_size, latency->display_hpll_disable);
3076 reg = I915_READ(DSPFW3);
3077 reg &= ~DSPFW_HPLL_SR_MASK;
3078 reg |= wm & DSPFW_HPLL_SR_MASK;
3079 I915_WRITE(DSPFW3, reg);
3080
3081 /* cursor HPLL off SR */
3082 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3083 pixel_size, latency->cursor_hpll_disable);
3084 reg = I915_READ(DSPFW3);
3085 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3086 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3087 I915_WRITE(DSPFW3, reg);
3088 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3089
3090 /* activate cxsr */
3091 I915_WRITE(DSPFW3,
3092 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3093 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3094 } else {
3095 pineview_disable_cxsr(dev);
3096 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3097 }
3098 }
3099
3100 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3101 int planeb_clock, int sr_hdisplay, int sr_htotal,
3102 int pixel_size)
3103 {
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3105 int total_size, cacheline_size;
3106 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3107 struct intel_watermark_params planea_params, planeb_params;
3108 unsigned long line_time_us;
3109 int sr_clock, sr_entries = 0, entries_required;
3110
3111 /* Create copies of the base settings for each pipe */
3112 planea_params = planeb_params = g4x_wm_info;
3113
3114 /* Grab a couple of global values before we overwrite them */
3115 total_size = planea_params.fifo_size;
3116 cacheline_size = planea_params.cacheline_size;
3117
3118 /*
3119 * Note: we need to make sure we don't overflow for various clock &
3120 * latency values.
3121 * clocks go from a few thousand to several hundred thousand.
3122 * latency is usually a few thousand
3123 */
3124 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3125 1000;
3126 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3127 planea_wm = entries_required + planea_params.guard_size;
3128
3129 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3130 1000;
3131 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3132 planeb_wm = entries_required + planeb_params.guard_size;
3133
3134 cursora_wm = cursorb_wm = 16;
3135 cursor_sr = 32;
3136
3137 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3138
3139 /* Calc sr entries for one plane configs */
3140 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3141 /* self-refresh has much higher latency */
3142 static const int sr_latency_ns = 12000;
3143
3144 sr_clock = planea_clock ? planea_clock : planeb_clock;
3145 line_time_us = ((sr_htotal * 1000) / sr_clock);
3146
3147 /* Use ns/us then divide to preserve precision */
3148 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3149 pixel_size * sr_hdisplay;
3150 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3151
3152 entries_required = (((sr_latency_ns / line_time_us) +
3153 1000) / 1000) * pixel_size * 64;
3154 entries_required = DIV_ROUND_UP(entries_required,
3155 g4x_cursor_wm_info.cacheline_size);
3156 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3157
3158 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3159 cursor_sr = g4x_cursor_wm_info.max_wm;
3160 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3161 "cursor %d\n", sr_entries, cursor_sr);
3162
3163 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3164 } else {
3165 /* Turn off self refresh if both pipes are enabled */
3166 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3167 & ~FW_BLC_SELF_EN);
3168 }
3169
3170 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3171 planea_wm, planeb_wm, sr_entries);
3172
3173 planea_wm &= 0x3f;
3174 planeb_wm &= 0x3f;
3175
3176 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3177 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3178 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3179 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3180 (cursora_wm << DSPFW_CURSORA_SHIFT));
3181 /* HPLL off in SR has some issues on G4x... disable it */
3182 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3183 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3184 }
3185
3186 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3187 int planeb_clock, int sr_hdisplay, int sr_htotal,
3188 int pixel_size)
3189 {
3190 struct drm_i915_private *dev_priv = dev->dev_private;
3191 unsigned long line_time_us;
3192 int sr_clock, sr_entries, srwm = 1;
3193 int cursor_sr = 16;
3194
3195 /* Calc sr entries for one plane configs */
3196 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3197 /* self-refresh has much higher latency */
3198 static const int sr_latency_ns = 12000;
3199
3200 sr_clock = planea_clock ? planea_clock : planeb_clock;
3201 line_time_us = ((sr_htotal * 1000) / sr_clock);
3202
3203 /* Use ns/us then divide to preserve precision */
3204 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3205 pixel_size * sr_hdisplay;
3206 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3207 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3208 srwm = I965_FIFO_SIZE - sr_entries;
3209 if (srwm < 0)
3210 srwm = 1;
3211 srwm &= 0x1ff;
3212
3213 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3214 pixel_size * 64;
3215 sr_entries = DIV_ROUND_UP(sr_entries,
3216 i965_cursor_wm_info.cacheline_size);
3217 cursor_sr = i965_cursor_wm_info.fifo_size -
3218 (sr_entries + i965_cursor_wm_info.guard_size);
3219
3220 if (cursor_sr > i965_cursor_wm_info.max_wm)
3221 cursor_sr = i965_cursor_wm_info.max_wm;
3222
3223 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3224 "cursor %d\n", srwm, cursor_sr);
3225
3226 if (IS_I965GM(dev))
3227 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3228 } else {
3229 /* Turn off self refresh if both pipes are enabled */
3230 if (IS_I965GM(dev))
3231 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3232 & ~FW_BLC_SELF_EN);
3233 }
3234
3235 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3236 srwm);
3237
3238 /* 965 has limitations... */
3239 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3240 (8 << 0));
3241 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3242 /* update cursor SR watermark */
3243 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3244 }
3245
3246 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3247 int planeb_clock, int sr_hdisplay, int sr_htotal,
3248 int pixel_size)
3249 {
3250 struct drm_i915_private *dev_priv = dev->dev_private;
3251 uint32_t fwater_lo;
3252 uint32_t fwater_hi;
3253 int total_size, cacheline_size, cwm, srwm = 1;
3254 int planea_wm, planeb_wm;
3255 struct intel_watermark_params planea_params, planeb_params;
3256 unsigned long line_time_us;
3257 int sr_clock, sr_entries = 0;
3258
3259 /* Create copies of the base settings for each pipe */
3260 if (IS_I965GM(dev) || IS_I945GM(dev))
3261 planea_params = planeb_params = i945_wm_info;
3262 else if (IS_I9XX(dev))
3263 planea_params = planeb_params = i915_wm_info;
3264 else
3265 planea_params = planeb_params = i855_wm_info;
3266
3267 /* Grab a couple of global values before we overwrite them */
3268 total_size = planea_params.fifo_size;
3269 cacheline_size = planea_params.cacheline_size;
3270
3271 /* Update per-plane FIFO sizes */
3272 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3273 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3274
3275 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3276 pixel_size, latency_ns);
3277 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3278 pixel_size, latency_ns);
3279 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3280
3281 /*
3282 * Overlay gets an aggressive default since video jitter is bad.
3283 */
3284 cwm = 2;
3285
3286 /* Calc sr entries for one plane configs */
3287 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3288 (!planea_clock || !planeb_clock)) {
3289 /* self-refresh has much higher latency */
3290 static const int sr_latency_ns = 6000;
3291
3292 sr_clock = planea_clock ? planea_clock : planeb_clock;
3293 line_time_us = ((sr_htotal * 1000) / sr_clock);
3294
3295 /* Use ns/us then divide to preserve precision */
3296 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3297 pixel_size * sr_hdisplay;
3298 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3299 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3300 srwm = total_size - sr_entries;
3301 if (srwm < 0)
3302 srwm = 1;
3303
3304 if (IS_I945G(dev) || IS_I945GM(dev))
3305 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3306 else if (IS_I915GM(dev)) {
3307 /* 915M has a smaller SRWM field */
3308 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3309 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3310 }
3311 } else {
3312 /* Turn off self refresh if both pipes are enabled */
3313 if (IS_I945G(dev) || IS_I945GM(dev)) {
3314 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3315 & ~FW_BLC_SELF_EN);
3316 } else if (IS_I915GM(dev)) {
3317 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3318 }
3319 }
3320
3321 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3322 planea_wm, planeb_wm, cwm, srwm);
3323
3324 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3325 fwater_hi = (cwm & 0x1f);
3326
3327 /* Set request length to 8 cachelines per fetch */
3328 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3329 fwater_hi = fwater_hi | (1 << 8);
3330
3331 I915_WRITE(FW_BLC, fwater_lo);
3332 I915_WRITE(FW_BLC2, fwater_hi);
3333 }
3334
3335 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3336 int unused2, int unused3, int pixel_size)
3337 {
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3340 int planea_wm;
3341
3342 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3343
3344 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3345 pixel_size, latency_ns);
3346 fwater_lo |= (3<<8) | planea_wm;
3347
3348 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3349
3350 I915_WRITE(FW_BLC, fwater_lo);
3351 }
3352
3353 #define ILK_LP0_PLANE_LATENCY 700
3354 #define ILK_LP0_CURSOR_LATENCY 1300
3355
3356 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3357 int planeb_clock, int sr_hdisplay, int sr_htotal,
3358 int pixel_size)
3359 {
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3362 int sr_wm, cursor_wm;
3363 unsigned long line_time_us;
3364 int sr_clock, entries_required;
3365 u32 reg_value;
3366 int line_count;
3367 int planea_htotal = 0, planeb_htotal = 0;
3368 struct drm_crtc *crtc;
3369 struct intel_crtc *intel_crtc;
3370
3371 /* Need htotal for all active display plane */
3372 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3373 intel_crtc = to_intel_crtc(crtc);
3374 if (crtc->enabled) {
3375 if (intel_crtc->plane == 0)
3376 planea_htotal = crtc->mode.htotal;
3377 else
3378 planeb_htotal = crtc->mode.htotal;
3379 }
3380 }
3381
3382 /* Calculate and update the watermark for plane A */
3383 if (planea_clock) {
3384 entries_required = ((planea_clock / 1000) * pixel_size *
3385 ILK_LP0_PLANE_LATENCY) / 1000;
3386 entries_required = DIV_ROUND_UP(entries_required,
3387 ironlake_display_wm_info.cacheline_size);
3388 planea_wm = entries_required +
3389 ironlake_display_wm_info.guard_size;
3390
3391 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3392 planea_wm = ironlake_display_wm_info.max_wm;
3393
3394 /* Use the large buffer method to calculate cursor watermark */
3395 line_time_us = (planea_htotal * 1000) / planea_clock;
3396
3397 /* Use ns/us then divide to preserve precision */
3398 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3399
3400 /* calculate the cursor watermark for cursor A */
3401 entries_required = line_count * 64 * pixel_size;
3402 entries_required = DIV_ROUND_UP(entries_required,
3403 ironlake_cursor_wm_info.cacheline_size);
3404 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3405 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3406 cursora_wm = ironlake_cursor_wm_info.max_wm;
3407
3408 reg_value = I915_READ(WM0_PIPEA_ILK);
3409 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3410 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3411 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3412 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3413 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3414 "cursor: %d\n", planea_wm, cursora_wm);
3415 }
3416 /* Calculate and update the watermark for plane B */
3417 if (planeb_clock) {
3418 entries_required = ((planeb_clock / 1000) * pixel_size *
3419 ILK_LP0_PLANE_LATENCY) / 1000;
3420 entries_required = DIV_ROUND_UP(entries_required,
3421 ironlake_display_wm_info.cacheline_size);
3422 planeb_wm = entries_required +
3423 ironlake_display_wm_info.guard_size;
3424
3425 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3426 planeb_wm = ironlake_display_wm_info.max_wm;
3427
3428 /* Use the large buffer method to calculate cursor watermark */
3429 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3430
3431 /* Use ns/us then divide to preserve precision */
3432 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3433
3434 /* calculate the cursor watermark for cursor B */
3435 entries_required = line_count * 64 * pixel_size;
3436 entries_required = DIV_ROUND_UP(entries_required,
3437 ironlake_cursor_wm_info.cacheline_size);
3438 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3439 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3440 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3441
3442 reg_value = I915_READ(WM0_PIPEB_ILK);
3443 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3444 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3445 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3446 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3447 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3448 "cursor: %d\n", planeb_wm, cursorb_wm);
3449 }
3450
3451 /*
3452 * Calculate and update the self-refresh watermark only when one
3453 * display plane is used.
3454 */
3455 if (!planea_clock || !planeb_clock) {
3456
3457 /* Read the self-refresh latency. The unit is 0.5us */
3458 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3459
3460 sr_clock = planea_clock ? planea_clock : planeb_clock;
3461 line_time_us = ((sr_htotal * 1000) / sr_clock);
3462
3463 /* Use ns/us then divide to preserve precision */
3464 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3465 / 1000;
3466
3467 /* calculate the self-refresh watermark for display plane */
3468 entries_required = line_count * sr_hdisplay * pixel_size;
3469 entries_required = DIV_ROUND_UP(entries_required,
3470 ironlake_display_srwm_info.cacheline_size);
3471 sr_wm = entries_required +
3472 ironlake_display_srwm_info.guard_size;
3473
3474 /* calculate the self-refresh watermark for display cursor */
3475 entries_required = line_count * pixel_size * 64;
3476 entries_required = DIV_ROUND_UP(entries_required,
3477 ironlake_cursor_srwm_info.cacheline_size);
3478 cursor_wm = entries_required +
3479 ironlake_cursor_srwm_info.guard_size;
3480
3481 /* configure watermark and enable self-refresh */
3482 reg_value = I915_READ(WM1_LP_ILK);
3483 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3484 WM1_LP_CURSOR_MASK);
3485 reg_value |= WM1_LP_SR_EN |
3486 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3487 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3488
3489 I915_WRITE(WM1_LP_ILK, reg_value);
3490 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3491 "cursor %d\n", sr_wm, cursor_wm);
3492
3493 } else {
3494 /* Turn off self refresh if both pipes are enabled */
3495 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3496 }
3497 }
3498 /**
3499 * intel_update_watermarks - update FIFO watermark values based on current modes
3500 *
3501 * Calculate watermark values for the various WM regs based on current mode
3502 * and plane configuration.
3503 *
3504 * There are several cases to deal with here:
3505 * - normal (i.e. non-self-refresh)
3506 * - self-refresh (SR) mode
3507 * - lines are large relative to FIFO size (buffer can hold up to 2)
3508 * - lines are small relative to FIFO size (buffer can hold more than 2
3509 * lines), so need to account for TLB latency
3510 *
3511 * The normal calculation is:
3512 * watermark = dotclock * bytes per pixel * latency
3513 * where latency is platform & configuration dependent (we assume pessimal
3514 * values here).
3515 *
3516 * The SR calculation is:
3517 * watermark = (trunc(latency/line time)+1) * surface width *
3518 * bytes per pixel
3519 * where
3520 * line time = htotal / dotclock
3521 * surface width = hdisplay for normal plane and 64 for cursor
3522 * and latency is assumed to be high, as above.
3523 *
3524 * The final value programmed to the register should always be rounded up,
3525 * and include an extra 2 entries to account for clock crossings.
3526 *
3527 * We don't use the sprite, so we can ignore that. And on Crestline we have
3528 * to set the non-SR watermarks to 8.
3529 */
3530 static void intel_update_watermarks(struct drm_device *dev)
3531 {
3532 struct drm_i915_private *dev_priv = dev->dev_private;
3533 struct drm_crtc *crtc;
3534 struct intel_crtc *intel_crtc;
3535 int sr_hdisplay = 0;
3536 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3537 int enabled = 0, pixel_size = 0;
3538 int sr_htotal = 0;
3539
3540 if (!dev_priv->display.update_wm)
3541 return;
3542
3543 /* Get the clock config from both planes */
3544 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3545 intel_crtc = to_intel_crtc(crtc);
3546 if (crtc->enabled) {
3547 enabled++;
3548 if (intel_crtc->plane == 0) {
3549 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3550 intel_crtc->pipe, crtc->mode.clock);
3551 planea_clock = crtc->mode.clock;
3552 } else {
3553 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3554 intel_crtc->pipe, crtc->mode.clock);
3555 planeb_clock = crtc->mode.clock;
3556 }
3557 sr_hdisplay = crtc->mode.hdisplay;
3558 sr_clock = crtc->mode.clock;
3559 sr_htotal = crtc->mode.htotal;
3560 if (crtc->fb)
3561 pixel_size = crtc->fb->bits_per_pixel / 8;
3562 else
3563 pixel_size = 4; /* by default */
3564 }
3565 }
3566
3567 if (enabled <= 0)
3568 return;
3569
3570 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3571 sr_hdisplay, sr_htotal, pixel_size);
3572 }
3573
3574 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3575 struct drm_display_mode *mode,
3576 struct drm_display_mode *adjusted_mode,
3577 int x, int y,
3578 struct drm_framebuffer *old_fb)
3579 {
3580 struct drm_device *dev = crtc->dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583 int pipe = intel_crtc->pipe;
3584 int plane = intel_crtc->plane;
3585 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3586 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3587 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3588 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3589 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3590 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3591 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3592 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3593 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3594 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3595 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3596 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3597 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3598 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3599 int refclk, num_connectors = 0;
3600 intel_clock_t clock, reduced_clock;
3601 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3602 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3603 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3604 bool is_edp = false;
3605 struct drm_mode_config *mode_config = &dev->mode_config;
3606 struct drm_encoder *encoder;
3607 struct intel_encoder *intel_encoder = NULL;
3608 const intel_limit_t *limit;
3609 int ret;
3610 struct fdi_m_n m_n = {0};
3611 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3612 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3613 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3614 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3615 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3616 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3617 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3618 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3619 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3620 int lvds_reg = LVDS;
3621 u32 temp;
3622 int sdvo_pixel_multiply;
3623 int target_clock;
3624
3625 drm_vblank_pre_modeset(dev, pipe);
3626
3627 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3628
3629 if (!encoder || encoder->crtc != crtc)
3630 continue;
3631
3632 intel_encoder = enc_to_intel_encoder(encoder);
3633
3634 switch (intel_encoder->type) {
3635 case INTEL_OUTPUT_LVDS:
3636 is_lvds = true;
3637 break;
3638 case INTEL_OUTPUT_SDVO:
3639 case INTEL_OUTPUT_HDMI:
3640 is_sdvo = true;
3641 if (intel_encoder->needs_tv_clock)
3642 is_tv = true;
3643 break;
3644 case INTEL_OUTPUT_DVO:
3645 is_dvo = true;
3646 break;
3647 case INTEL_OUTPUT_TVOUT:
3648 is_tv = true;
3649 break;
3650 case INTEL_OUTPUT_ANALOG:
3651 is_crt = true;
3652 break;
3653 case INTEL_OUTPUT_DISPLAYPORT:
3654 is_dp = true;
3655 break;
3656 case INTEL_OUTPUT_EDP:
3657 is_edp = true;
3658 break;
3659 }
3660
3661 num_connectors++;
3662 }
3663
3664 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3665 refclk = dev_priv->lvds_ssc_freq * 1000;
3666 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3667 refclk / 1000);
3668 } else if (IS_I9XX(dev)) {
3669 refclk = 96000;
3670 if (HAS_PCH_SPLIT(dev))
3671 refclk = 120000; /* 120Mhz refclk */
3672 } else {
3673 refclk = 48000;
3674 }
3675
3676
3677 /*
3678 * Returns a set of divisors for the desired target clock with the given
3679 * refclk, or FALSE. The returned values represent the clock equation:
3680 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3681 */
3682 limit = intel_limit(crtc);
3683 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3684 if (!ok) {
3685 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3686 drm_vblank_post_modeset(dev, pipe);
3687 return -EINVAL;
3688 }
3689
3690 /* Ensure that the cursor is valid for the new mode before changing... */
3691 intel_crtc_update_cursor(crtc);
3692
3693 if (is_lvds && dev_priv->lvds_downclock_avail) {
3694 has_reduced_clock = limit->find_pll(limit, crtc,
3695 dev_priv->lvds_downclock,
3696 refclk,
3697 &reduced_clock);
3698 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3699 /*
3700 * If the different P is found, it means that we can't
3701 * switch the display clock by using the FP0/FP1.
3702 * In such case we will disable the LVDS downclock
3703 * feature.
3704 */
3705 DRM_DEBUG_KMS("Different P is found for "
3706 "LVDS clock/downclock\n");
3707 has_reduced_clock = 0;
3708 }
3709 }
3710 /* SDVO TV has fixed PLL values depend on its clock range,
3711 this mirrors vbios setting. */
3712 if (is_sdvo && is_tv) {
3713 if (adjusted_mode->clock >= 100000
3714 && adjusted_mode->clock < 140500) {
3715 clock.p1 = 2;
3716 clock.p2 = 10;
3717 clock.n = 3;
3718 clock.m1 = 16;
3719 clock.m2 = 8;
3720 } else if (adjusted_mode->clock >= 140500
3721 && adjusted_mode->clock <= 200000) {
3722 clock.p1 = 1;
3723 clock.p2 = 10;
3724 clock.n = 6;
3725 clock.m1 = 12;
3726 clock.m2 = 8;
3727 }
3728 }
3729
3730 /* FDI link */
3731 if (HAS_PCH_SPLIT(dev)) {
3732 int lane = 0, link_bw, bpp;
3733 /* eDP doesn't require FDI link, so just set DP M/N
3734 according to current link config */
3735 if (is_edp) {
3736 target_clock = mode->clock;
3737 intel_edp_link_config(intel_encoder,
3738 &lane, &link_bw);
3739 } else {
3740 /* DP over FDI requires target mode clock
3741 instead of link clock */
3742 if (is_dp)
3743 target_clock = mode->clock;
3744 else
3745 target_clock = adjusted_mode->clock;
3746 link_bw = 270000;
3747 }
3748
3749 /* determine panel color depth */
3750 temp = I915_READ(pipeconf_reg);
3751 temp &= ~PIPE_BPC_MASK;
3752 if (is_lvds) {
3753 int lvds_reg = I915_READ(PCH_LVDS);
3754 /* the BPC will be 6 if it is 18-bit LVDS panel */
3755 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3756 temp |= PIPE_8BPC;
3757 else
3758 temp |= PIPE_6BPC;
3759 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3760 switch (dev_priv->edp_bpp/3) {
3761 case 8:
3762 temp |= PIPE_8BPC;
3763 break;
3764 case 10:
3765 temp |= PIPE_10BPC;
3766 break;
3767 case 6:
3768 temp |= PIPE_6BPC;
3769 break;
3770 case 12:
3771 temp |= PIPE_12BPC;
3772 break;
3773 }
3774 } else
3775 temp |= PIPE_8BPC;
3776 I915_WRITE(pipeconf_reg, temp);
3777 I915_READ(pipeconf_reg);
3778
3779 switch (temp & PIPE_BPC_MASK) {
3780 case PIPE_8BPC:
3781 bpp = 24;
3782 break;
3783 case PIPE_10BPC:
3784 bpp = 30;
3785 break;
3786 case PIPE_6BPC:
3787 bpp = 18;
3788 break;
3789 case PIPE_12BPC:
3790 bpp = 36;
3791 break;
3792 default:
3793 DRM_ERROR("unknown pipe bpc value\n");
3794 bpp = 24;
3795 }
3796
3797 if (!lane) {
3798 /*
3799 * Account for spread spectrum to avoid
3800 * oversubscribing the link. Max center spread
3801 * is 2.5%; use 5% for safety's sake.
3802 */
3803 u32 bps = target_clock * bpp * 21 / 20;
3804 lane = bps / (link_bw * 8) + 1;
3805 }
3806
3807 intel_crtc->fdi_lanes = lane;
3808
3809 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3810 }
3811
3812 /* Ironlake: try to setup display ref clock before DPLL
3813 * enabling. This is only under driver's control after
3814 * PCH B stepping, previous chipset stepping should be
3815 * ignoring this setting.
3816 */
3817 if (HAS_PCH_SPLIT(dev)) {
3818 temp = I915_READ(PCH_DREF_CONTROL);
3819 /* Always enable nonspread source */
3820 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3821 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3822 I915_WRITE(PCH_DREF_CONTROL, temp);
3823 POSTING_READ(PCH_DREF_CONTROL);
3824
3825 temp &= ~DREF_SSC_SOURCE_MASK;
3826 temp |= DREF_SSC_SOURCE_ENABLE;
3827 I915_WRITE(PCH_DREF_CONTROL, temp);
3828 POSTING_READ(PCH_DREF_CONTROL);
3829
3830 udelay(200);
3831
3832 if (is_edp) {
3833 if (dev_priv->lvds_use_ssc) {
3834 temp |= DREF_SSC1_ENABLE;
3835 I915_WRITE(PCH_DREF_CONTROL, temp);
3836 POSTING_READ(PCH_DREF_CONTROL);
3837
3838 udelay(200);
3839
3840 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3841 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3842 I915_WRITE(PCH_DREF_CONTROL, temp);
3843 POSTING_READ(PCH_DREF_CONTROL);
3844 } else {
3845 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3846 I915_WRITE(PCH_DREF_CONTROL, temp);
3847 POSTING_READ(PCH_DREF_CONTROL);
3848 }
3849 }
3850 }
3851
3852 if (IS_PINEVIEW(dev)) {
3853 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3854 if (has_reduced_clock)
3855 fp2 = (1 << reduced_clock.n) << 16 |
3856 reduced_clock.m1 << 8 | reduced_clock.m2;
3857 } else {
3858 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3859 if (has_reduced_clock)
3860 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3861 reduced_clock.m2;
3862 }
3863
3864 if (!HAS_PCH_SPLIT(dev))
3865 dpll = DPLL_VGA_MODE_DIS;
3866
3867 if (IS_I9XX(dev)) {
3868 if (is_lvds)
3869 dpll |= DPLLB_MODE_LVDS;
3870 else
3871 dpll |= DPLLB_MODE_DAC_SERIAL;
3872 if (is_sdvo) {
3873 dpll |= DPLL_DVO_HIGH_SPEED;
3874 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3875 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3876 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3877 else if (HAS_PCH_SPLIT(dev))
3878 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3879 }
3880 if (is_dp)
3881 dpll |= DPLL_DVO_HIGH_SPEED;
3882
3883 /* compute bitmask from p1 value */
3884 if (IS_PINEVIEW(dev))
3885 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3886 else {
3887 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3888 /* also FPA1 */
3889 if (HAS_PCH_SPLIT(dev))
3890 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3891 if (IS_G4X(dev) && has_reduced_clock)
3892 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3893 }
3894 switch (clock.p2) {
3895 case 5:
3896 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3897 break;
3898 case 7:
3899 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3900 break;
3901 case 10:
3902 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3903 break;
3904 case 14:
3905 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3906 break;
3907 }
3908 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3909 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3910 } else {
3911 if (is_lvds) {
3912 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3913 } else {
3914 if (clock.p1 == 2)
3915 dpll |= PLL_P1_DIVIDE_BY_TWO;
3916 else
3917 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3918 if (clock.p2 == 4)
3919 dpll |= PLL_P2_DIVIDE_BY_4;
3920 }
3921 }
3922
3923 if (is_sdvo && is_tv)
3924 dpll |= PLL_REF_INPUT_TVCLKINBC;
3925 else if (is_tv)
3926 /* XXX: just matching BIOS for now */
3927 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3928 dpll |= 3;
3929 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3930 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3931 else
3932 dpll |= PLL_REF_INPUT_DREFCLK;
3933
3934 /* setup pipeconf */
3935 pipeconf = I915_READ(pipeconf_reg);
3936
3937 /* Set up the display plane register */
3938 dspcntr = DISPPLANE_GAMMA_ENABLE;
3939
3940 /* Ironlake's plane is forced to pipe, bit 24 is to
3941 enable color space conversion */
3942 if (!HAS_PCH_SPLIT(dev)) {
3943 if (pipe == 0)
3944 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3945 else
3946 dspcntr |= DISPPLANE_SEL_PIPE_B;
3947 }
3948
3949 if (pipe == 0 && !IS_I965G(dev)) {
3950 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3951 * core speed.
3952 *
3953 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3954 * pipe == 0 check?
3955 */
3956 if (mode->clock >
3957 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3958 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3959 else
3960 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3961 }
3962
3963 dspcntr |= DISPLAY_PLANE_ENABLE;
3964 pipeconf |= PIPEACONF_ENABLE;
3965 dpll |= DPLL_VCO_ENABLE;
3966
3967
3968 /* Disable the panel fitter if it was on our pipe */
3969 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3970 I915_WRITE(PFIT_CONTROL, 0);
3971
3972 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3973 drm_mode_debug_printmodeline(mode);
3974
3975 /* assign to Ironlake registers */
3976 if (HAS_PCH_SPLIT(dev)) {
3977 fp_reg = pch_fp_reg;
3978 dpll_reg = pch_dpll_reg;
3979 }
3980
3981 if (is_edp) {
3982 ironlake_disable_pll_edp(crtc);
3983 } else if ((dpll & DPLL_VCO_ENABLE)) {
3984 I915_WRITE(fp_reg, fp);
3985 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3986 I915_READ(dpll_reg);
3987 udelay(150);
3988 }
3989
3990 /* enable transcoder DPLL */
3991 if (HAS_PCH_CPT(dev)) {
3992 temp = I915_READ(PCH_DPLL_SEL);
3993 if (trans_dpll_sel == 0)
3994 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3995 else
3996 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3997 I915_WRITE(PCH_DPLL_SEL, temp);
3998 I915_READ(PCH_DPLL_SEL);
3999 udelay(150);
4000 }
4001
4002 if (HAS_PCH_SPLIT(dev)) {
4003 pipeconf &= ~PIPE_ENABLE_DITHER;
4004 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
4005 }
4006
4007 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4008 * This is an exception to the general rule that mode_set doesn't turn
4009 * things on.
4010 */
4011 if (is_lvds) {
4012 u32 lvds;
4013
4014 if (HAS_PCH_SPLIT(dev))
4015 lvds_reg = PCH_LVDS;
4016
4017 lvds = I915_READ(lvds_reg);
4018 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4019 if (pipe == 1) {
4020 if (HAS_PCH_CPT(dev))
4021 lvds |= PORT_TRANS_B_SEL_CPT;
4022 else
4023 lvds |= LVDS_PIPEB_SELECT;
4024 } else {
4025 if (HAS_PCH_CPT(dev))
4026 lvds &= ~PORT_TRANS_SEL_MASK;
4027 else
4028 lvds &= ~LVDS_PIPEB_SELECT;
4029 }
4030 /* set the corresponsding LVDS_BORDER bit */
4031 lvds |= dev_priv->lvds_border_bits;
4032 /* Set the B0-B3 data pairs corresponding to whether we're going to
4033 * set the DPLLs for dual-channel mode or not.
4034 */
4035 if (clock.p2 == 7)
4036 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4037 else
4038 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4039
4040 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4041 * appropriately here, but we need to look more thoroughly into how
4042 * panels behave in the two modes.
4043 */
4044 /* set the dithering flag */
4045 if (IS_I965G(dev)) {
4046 if (dev_priv->lvds_dither) {
4047 if (HAS_PCH_SPLIT(dev)) {
4048 pipeconf |= PIPE_ENABLE_DITHER;
4049 pipeconf |= PIPE_DITHER_TYPE_ST01;
4050 } else
4051 lvds |= LVDS_ENABLE_DITHER;
4052 } else {
4053 if (!HAS_PCH_SPLIT(dev)) {
4054 lvds &= ~LVDS_ENABLE_DITHER;
4055 }
4056 }
4057 }
4058 I915_WRITE(lvds_reg, lvds);
4059 I915_READ(lvds_reg);
4060 }
4061 if (is_dp)
4062 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4063 else if (HAS_PCH_SPLIT(dev)) {
4064 /* For non-DP output, clear any trans DP clock recovery setting.*/
4065 if (pipe == 0) {
4066 I915_WRITE(TRANSA_DATA_M1, 0);
4067 I915_WRITE(TRANSA_DATA_N1, 0);
4068 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4069 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4070 } else {
4071 I915_WRITE(TRANSB_DATA_M1, 0);
4072 I915_WRITE(TRANSB_DATA_N1, 0);
4073 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4074 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4075 }
4076 }
4077
4078 if (!is_edp) {
4079 I915_WRITE(fp_reg, fp);
4080 I915_WRITE(dpll_reg, dpll);
4081 I915_READ(dpll_reg);
4082 /* Wait for the clocks to stabilize. */
4083 udelay(150);
4084
4085 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4086 if (is_sdvo) {
4087 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4088 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4089 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4090 } else
4091 I915_WRITE(dpll_md_reg, 0);
4092 } else {
4093 /* write it again -- the BIOS does, after all */
4094 I915_WRITE(dpll_reg, dpll);
4095 }
4096 I915_READ(dpll_reg);
4097 /* Wait for the clocks to stabilize. */
4098 udelay(150);
4099 }
4100
4101 if (is_lvds && has_reduced_clock && i915_powersave) {
4102 I915_WRITE(fp_reg + 4, fp2);
4103 intel_crtc->lowfreq_avail = true;
4104 if (HAS_PIPE_CXSR(dev)) {
4105 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4106 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4107 }
4108 } else {
4109 I915_WRITE(fp_reg + 4, fp);
4110 intel_crtc->lowfreq_avail = false;
4111 if (HAS_PIPE_CXSR(dev)) {
4112 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4113 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4114 }
4115 }
4116
4117 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4118 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4119 /* the chip adds 2 halflines automatically */
4120 adjusted_mode->crtc_vdisplay -= 1;
4121 adjusted_mode->crtc_vtotal -= 1;
4122 adjusted_mode->crtc_vblank_start -= 1;
4123 adjusted_mode->crtc_vblank_end -= 1;
4124 adjusted_mode->crtc_vsync_end -= 1;
4125 adjusted_mode->crtc_vsync_start -= 1;
4126 } else
4127 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4128
4129 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4130 ((adjusted_mode->crtc_htotal - 1) << 16));
4131 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4132 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4133 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4134 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4135 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4136 ((adjusted_mode->crtc_vtotal - 1) << 16));
4137 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4138 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4139 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4140 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4141 /* pipesrc and dspsize control the size that is scaled from, which should
4142 * always be the user's requested size.
4143 */
4144 if (!HAS_PCH_SPLIT(dev)) {
4145 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4146 (mode->hdisplay - 1));
4147 I915_WRITE(dsppos_reg, 0);
4148 }
4149 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4150
4151 if (HAS_PCH_SPLIT(dev)) {
4152 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4153 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4154 I915_WRITE(link_m1_reg, m_n.link_m);
4155 I915_WRITE(link_n1_reg, m_n.link_n);
4156
4157 if (is_edp) {
4158 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4159 } else {
4160 /* enable FDI RX PLL too */
4161 temp = I915_READ(fdi_rx_reg);
4162 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4163 I915_READ(fdi_rx_reg);
4164 udelay(200);
4165
4166 /* enable FDI TX PLL too */
4167 temp = I915_READ(fdi_tx_reg);
4168 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4169 I915_READ(fdi_tx_reg);
4170
4171 /* enable FDI RX PCDCLK */
4172 temp = I915_READ(fdi_rx_reg);
4173 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4174 I915_READ(fdi_rx_reg);
4175 udelay(200);
4176 }
4177 }
4178
4179 I915_WRITE(pipeconf_reg, pipeconf);
4180 I915_READ(pipeconf_reg);
4181
4182 intel_wait_for_vblank(dev);
4183
4184 if (IS_IRONLAKE(dev)) {
4185 /* enable address swizzle for tiling buffer */
4186 temp = I915_READ(DISP_ARB_CTL);
4187 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4188 }
4189
4190 I915_WRITE(dspcntr_reg, dspcntr);
4191
4192 /* Flush the plane changes */
4193 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4194
4195 if ((IS_I965G(dev) || plane == 0))
4196 intel_update_fbc(crtc, &crtc->mode);
4197
4198 intel_update_watermarks(dev);
4199
4200 drm_vblank_post_modeset(dev, pipe);
4201
4202 return ret;
4203 }
4204
4205 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4206 void intel_crtc_load_lut(struct drm_crtc *crtc)
4207 {
4208 struct drm_device *dev = crtc->dev;
4209 struct drm_i915_private *dev_priv = dev->dev_private;
4210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4212 int i;
4213
4214 /* The clocks have to be on to load the palette. */
4215 if (!crtc->enabled)
4216 return;
4217
4218 /* use legacy palette for Ironlake */
4219 if (HAS_PCH_SPLIT(dev))
4220 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4221 LGC_PALETTE_B;
4222
4223 for (i = 0; i < 256; i++) {
4224 I915_WRITE(palreg + 4 * i,
4225 (intel_crtc->lut_r[i] << 16) |
4226 (intel_crtc->lut_g[i] << 8) |
4227 intel_crtc->lut_b[i]);
4228 }
4229 }
4230
4231 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4232 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4233 {
4234 struct drm_device *dev = crtc->dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4237 int pipe = intel_crtc->pipe;
4238 int x = intel_crtc->cursor_x;
4239 int y = intel_crtc->cursor_y;
4240 uint32_t base, pos;
4241 bool visible;
4242
4243 pos = 0;
4244
4245 if (intel_crtc->cursor_on && crtc->fb) {
4246 base = intel_crtc->cursor_addr;
4247 if (x > (int) crtc->fb->width)
4248 base = 0;
4249
4250 if (y > (int) crtc->fb->height)
4251 base = 0;
4252 } else
4253 base = 0;
4254
4255 if (x < 0) {
4256 if (x + intel_crtc->cursor_width < 0)
4257 base = 0;
4258
4259 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4260 x = -x;
4261 }
4262 pos |= x << CURSOR_X_SHIFT;
4263
4264 if (y < 0) {
4265 if (y + intel_crtc->cursor_height < 0)
4266 base = 0;
4267
4268 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4269 y = -y;
4270 }
4271 pos |= y << CURSOR_Y_SHIFT;
4272
4273 visible = base != 0;
4274 if (!visible && !intel_crtc->cursor_visble)
4275 return;
4276
4277 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4278 if (intel_crtc->cursor_visble != visible) {
4279 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4280 if (base) {
4281 /* Hooray for CUR*CNTR differences */
4282 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4283 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4284 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4285 cntl |= pipe << 28; /* Connect to correct pipe */
4286 } else {
4287 cntl &= ~(CURSOR_FORMAT_MASK);
4288 cntl |= CURSOR_ENABLE;
4289 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4290 }
4291 } else {
4292 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4293 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4294 cntl |= CURSOR_MODE_DISABLE;
4295 } else {
4296 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4297 }
4298 }
4299 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4300
4301 intel_crtc->cursor_visble = visible;
4302 }
4303 /* and commit changes on next vblank */
4304 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4305
4306 if (visible)
4307 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4308 }
4309
4310 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4311 struct drm_file *file_priv,
4312 uint32_t handle,
4313 uint32_t width, uint32_t height)
4314 {
4315 struct drm_device *dev = crtc->dev;
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4318 struct drm_gem_object *bo;
4319 struct drm_i915_gem_object *obj_priv;
4320 uint32_t addr;
4321 int ret;
4322
4323 DRM_DEBUG_KMS("\n");
4324
4325 /* if we want to turn off the cursor ignore width and height */
4326 if (!handle) {
4327 DRM_DEBUG_KMS("cursor off\n");
4328 addr = 0;
4329 bo = NULL;
4330 mutex_lock(&dev->struct_mutex);
4331 goto finish;
4332 }
4333
4334 /* Currently we only support 64x64 cursors */
4335 if (width != 64 || height != 64) {
4336 DRM_ERROR("we currently only support 64x64 cursors\n");
4337 return -EINVAL;
4338 }
4339
4340 bo = drm_gem_object_lookup(dev, file_priv, handle);
4341 if (!bo)
4342 return -ENOENT;
4343
4344 obj_priv = to_intel_bo(bo);
4345
4346 if (bo->size < width * height * 4) {
4347 DRM_ERROR("buffer is to small\n");
4348 ret = -ENOMEM;
4349 goto fail;
4350 }
4351
4352 /* we only need to pin inside GTT if cursor is non-phy */
4353 mutex_lock(&dev->struct_mutex);
4354 if (!dev_priv->info->cursor_needs_physical) {
4355 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4356 if (ret) {
4357 DRM_ERROR("failed to pin cursor bo\n");
4358 goto fail_locked;
4359 }
4360
4361 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4362 if (ret) {
4363 DRM_ERROR("failed to move cursor bo into the GTT\n");
4364 goto fail_unpin;
4365 }
4366
4367 addr = obj_priv->gtt_offset;
4368 } else {
4369 ret = i915_gem_attach_phys_object(dev, bo,
4370 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4371 if (ret) {
4372 DRM_ERROR("failed to attach phys object\n");
4373 goto fail_locked;
4374 }
4375 addr = obj_priv->phys_obj->handle->busaddr;
4376 }
4377
4378 if (!IS_I9XX(dev))
4379 I915_WRITE(CURSIZE, (height << 12) | width);
4380
4381 finish:
4382 if (intel_crtc->cursor_bo) {
4383 if (dev_priv->info->cursor_needs_physical) {
4384 if (intel_crtc->cursor_bo != bo)
4385 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4386 } else
4387 i915_gem_object_unpin(intel_crtc->cursor_bo);
4388 drm_gem_object_unreference(intel_crtc->cursor_bo);
4389 }
4390
4391 mutex_unlock(&dev->struct_mutex);
4392
4393 intel_crtc->cursor_addr = addr;
4394 intel_crtc->cursor_bo = bo;
4395 intel_crtc->cursor_width = width;
4396 intel_crtc->cursor_height = height;
4397
4398 intel_crtc_update_cursor(crtc);
4399
4400 return 0;
4401 fail_unpin:
4402 i915_gem_object_unpin(bo);
4403 fail_locked:
4404 mutex_unlock(&dev->struct_mutex);
4405 fail:
4406 drm_gem_object_unreference_unlocked(bo);
4407 return ret;
4408 }
4409
4410 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4411 {
4412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4413
4414 intel_crtc->cursor_x = x;
4415 intel_crtc->cursor_y = y;
4416
4417 intel_crtc_update_cursor(crtc);
4418
4419 return 0;
4420 }
4421
4422 /** Sets the color ramps on behalf of RandR */
4423 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4424 u16 blue, int regno)
4425 {
4426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4427
4428 intel_crtc->lut_r[regno] = red >> 8;
4429 intel_crtc->lut_g[regno] = green >> 8;
4430 intel_crtc->lut_b[regno] = blue >> 8;
4431 }
4432
4433 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4434 u16 *blue, int regno)
4435 {
4436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4437
4438 *red = intel_crtc->lut_r[regno] << 8;
4439 *green = intel_crtc->lut_g[regno] << 8;
4440 *blue = intel_crtc->lut_b[regno] << 8;
4441 }
4442
4443 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4444 u16 *blue, uint32_t size)
4445 {
4446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4447 int i;
4448
4449 if (size != 256)
4450 return;
4451
4452 for (i = 0; i < 256; i++) {
4453 intel_crtc->lut_r[i] = red[i] >> 8;
4454 intel_crtc->lut_g[i] = green[i] >> 8;
4455 intel_crtc->lut_b[i] = blue[i] >> 8;
4456 }
4457
4458 intel_crtc_load_lut(crtc);
4459 }
4460
4461 /**
4462 * Get a pipe with a simple mode set on it for doing load-based monitor
4463 * detection.
4464 *
4465 * It will be up to the load-detect code to adjust the pipe as appropriate for
4466 * its requirements. The pipe will be connected to no other encoders.
4467 *
4468 * Currently this code will only succeed if there is a pipe with no encoders
4469 * configured for it. In the future, it could choose to temporarily disable
4470 * some outputs to free up a pipe for its use.
4471 *
4472 * \return crtc, or NULL if no pipes are available.
4473 */
4474
4475 /* VESA 640x480x72Hz mode to set on the pipe */
4476 static struct drm_display_mode load_detect_mode = {
4477 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4478 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4479 };
4480
4481 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4482 struct drm_connector *connector,
4483 struct drm_display_mode *mode,
4484 int *dpms_mode)
4485 {
4486 struct intel_crtc *intel_crtc;
4487 struct drm_crtc *possible_crtc;
4488 struct drm_crtc *supported_crtc =NULL;
4489 struct drm_encoder *encoder = &intel_encoder->enc;
4490 struct drm_crtc *crtc = NULL;
4491 struct drm_device *dev = encoder->dev;
4492 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4493 struct drm_crtc_helper_funcs *crtc_funcs;
4494 int i = -1;
4495
4496 /*
4497 * Algorithm gets a little messy:
4498 * - if the connector already has an assigned crtc, use it (but make
4499 * sure it's on first)
4500 * - try to find the first unused crtc that can drive this connector,
4501 * and use that if we find one
4502 * - if there are no unused crtcs available, try to use the first
4503 * one we found that supports the connector
4504 */
4505
4506 /* See if we already have a CRTC for this connector */
4507 if (encoder->crtc) {
4508 crtc = encoder->crtc;
4509 /* Make sure the crtc and connector are running */
4510 intel_crtc = to_intel_crtc(crtc);
4511 *dpms_mode = intel_crtc->dpms_mode;
4512 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4513 crtc_funcs = crtc->helper_private;
4514 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4515 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4516 }
4517 return crtc;
4518 }
4519
4520 /* Find an unused one (if possible) */
4521 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4522 i++;
4523 if (!(encoder->possible_crtcs & (1 << i)))
4524 continue;
4525 if (!possible_crtc->enabled) {
4526 crtc = possible_crtc;
4527 break;
4528 }
4529 if (!supported_crtc)
4530 supported_crtc = possible_crtc;
4531 }
4532
4533 /*
4534 * If we didn't find an unused CRTC, don't use any.
4535 */
4536 if (!crtc) {
4537 return NULL;
4538 }
4539
4540 encoder->crtc = crtc;
4541 connector->encoder = encoder;
4542 intel_encoder->load_detect_temp = true;
4543
4544 intel_crtc = to_intel_crtc(crtc);
4545 *dpms_mode = intel_crtc->dpms_mode;
4546
4547 if (!crtc->enabled) {
4548 if (!mode)
4549 mode = &load_detect_mode;
4550 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4551 } else {
4552 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4553 crtc_funcs = crtc->helper_private;
4554 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4555 }
4556
4557 /* Add this connector to the crtc */
4558 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4559 encoder_funcs->commit(encoder);
4560 }
4561 /* let the connector get through one full cycle before testing */
4562 intel_wait_for_vblank(dev);
4563
4564 return crtc;
4565 }
4566
4567 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4568 struct drm_connector *connector, int dpms_mode)
4569 {
4570 struct drm_encoder *encoder = &intel_encoder->enc;
4571 struct drm_device *dev = encoder->dev;
4572 struct drm_crtc *crtc = encoder->crtc;
4573 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4574 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4575
4576 if (intel_encoder->load_detect_temp) {
4577 encoder->crtc = NULL;
4578 connector->encoder = NULL;
4579 intel_encoder->load_detect_temp = false;
4580 crtc->enabled = drm_helper_crtc_in_use(crtc);
4581 drm_helper_disable_unused_functions(dev);
4582 }
4583
4584 /* Switch crtc and encoder back off if necessary */
4585 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4586 if (encoder->crtc == crtc)
4587 encoder_funcs->dpms(encoder, dpms_mode);
4588 crtc_funcs->dpms(crtc, dpms_mode);
4589 }
4590 }
4591
4592 /* Returns the clock of the currently programmed mode of the given pipe. */
4593 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4594 {
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597 int pipe = intel_crtc->pipe;
4598 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4599 u32 fp;
4600 intel_clock_t clock;
4601
4602 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4603 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4604 else
4605 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4606
4607 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4608 if (IS_PINEVIEW(dev)) {
4609 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4610 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4611 } else {
4612 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4613 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4614 }
4615
4616 if (IS_I9XX(dev)) {
4617 if (IS_PINEVIEW(dev))
4618 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4619 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4620 else
4621 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4622 DPLL_FPA01_P1_POST_DIV_SHIFT);
4623
4624 switch (dpll & DPLL_MODE_MASK) {
4625 case DPLLB_MODE_DAC_SERIAL:
4626 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4627 5 : 10;
4628 break;
4629 case DPLLB_MODE_LVDS:
4630 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4631 7 : 14;
4632 break;
4633 default:
4634 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4635 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4636 return 0;
4637 }
4638
4639 /* XXX: Handle the 100Mhz refclk */
4640 intel_clock(dev, 96000, &clock);
4641 } else {
4642 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4643
4644 if (is_lvds) {
4645 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4646 DPLL_FPA01_P1_POST_DIV_SHIFT);
4647 clock.p2 = 14;
4648
4649 if ((dpll & PLL_REF_INPUT_MASK) ==
4650 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4651 /* XXX: might not be 66MHz */
4652 intel_clock(dev, 66000, &clock);
4653 } else
4654 intel_clock(dev, 48000, &clock);
4655 } else {
4656 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4657 clock.p1 = 2;
4658 else {
4659 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4660 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4661 }
4662 if (dpll & PLL_P2_DIVIDE_BY_4)
4663 clock.p2 = 4;
4664 else
4665 clock.p2 = 2;
4666
4667 intel_clock(dev, 48000, &clock);
4668 }
4669 }
4670
4671 /* XXX: It would be nice to validate the clocks, but we can't reuse
4672 * i830PllIsValid() because it relies on the xf86_config connector
4673 * configuration being accurate, which it isn't necessarily.
4674 */
4675
4676 return clock.dot;
4677 }
4678
4679 /** Returns the currently programmed mode of the given pipe. */
4680 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4681 struct drm_crtc *crtc)
4682 {
4683 struct drm_i915_private *dev_priv = dev->dev_private;
4684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4685 int pipe = intel_crtc->pipe;
4686 struct drm_display_mode *mode;
4687 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4688 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4689 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4690 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4691
4692 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4693 if (!mode)
4694 return NULL;
4695
4696 mode->clock = intel_crtc_clock_get(dev, crtc);
4697 mode->hdisplay = (htot & 0xffff) + 1;
4698 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4699 mode->hsync_start = (hsync & 0xffff) + 1;
4700 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4701 mode->vdisplay = (vtot & 0xffff) + 1;
4702 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4703 mode->vsync_start = (vsync & 0xffff) + 1;
4704 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4705
4706 drm_mode_set_name(mode);
4707 drm_mode_set_crtcinfo(mode, 0);
4708
4709 return mode;
4710 }
4711
4712 #define GPU_IDLE_TIMEOUT 500 /* ms */
4713
4714 /* When this timer fires, we've been idle for awhile */
4715 static void intel_gpu_idle_timer(unsigned long arg)
4716 {
4717 struct drm_device *dev = (struct drm_device *)arg;
4718 drm_i915_private_t *dev_priv = dev->dev_private;
4719
4720 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4721
4722 dev_priv->busy = false;
4723
4724 queue_work(dev_priv->wq, &dev_priv->idle_work);
4725 }
4726
4727 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4728
4729 static void intel_crtc_idle_timer(unsigned long arg)
4730 {
4731 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4732 struct drm_crtc *crtc = &intel_crtc->base;
4733 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4734
4735 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4736
4737 intel_crtc->busy = false;
4738
4739 queue_work(dev_priv->wq, &dev_priv->idle_work);
4740 }
4741
4742 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4743 {
4744 struct drm_device *dev = crtc->dev;
4745 drm_i915_private_t *dev_priv = dev->dev_private;
4746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4747 int pipe = intel_crtc->pipe;
4748 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4749 int dpll = I915_READ(dpll_reg);
4750
4751 if (HAS_PCH_SPLIT(dev))
4752 return;
4753
4754 if (!dev_priv->lvds_downclock_avail)
4755 return;
4756
4757 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4758 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4759
4760 /* Unlock panel regs */
4761 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4762 PANEL_UNLOCK_REGS);
4763
4764 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4765 I915_WRITE(dpll_reg, dpll);
4766 dpll = I915_READ(dpll_reg);
4767 intel_wait_for_vblank(dev);
4768 dpll = I915_READ(dpll_reg);
4769 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4770 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4771
4772 /* ...and lock them again */
4773 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4774 }
4775
4776 /* Schedule downclock */
4777 if (schedule)
4778 mod_timer(&intel_crtc->idle_timer, jiffies +
4779 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4780 }
4781
4782 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4783 {
4784 struct drm_device *dev = crtc->dev;
4785 drm_i915_private_t *dev_priv = dev->dev_private;
4786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4787 int pipe = intel_crtc->pipe;
4788 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4789 int dpll = I915_READ(dpll_reg);
4790
4791 if (HAS_PCH_SPLIT(dev))
4792 return;
4793
4794 if (!dev_priv->lvds_downclock_avail)
4795 return;
4796
4797 /*
4798 * Since this is called by a timer, we should never get here in
4799 * the manual case.
4800 */
4801 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4802 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4803
4804 /* Unlock panel regs */
4805 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4806 PANEL_UNLOCK_REGS);
4807
4808 dpll |= DISPLAY_RATE_SELECT_FPA1;
4809 I915_WRITE(dpll_reg, dpll);
4810 dpll = I915_READ(dpll_reg);
4811 intel_wait_for_vblank(dev);
4812 dpll = I915_READ(dpll_reg);
4813 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4814 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4815
4816 /* ...and lock them again */
4817 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4818 }
4819
4820 }
4821
4822 /**
4823 * intel_idle_update - adjust clocks for idleness
4824 * @work: work struct
4825 *
4826 * Either the GPU or display (or both) went idle. Check the busy status
4827 * here and adjust the CRTC and GPU clocks as necessary.
4828 */
4829 static void intel_idle_update(struct work_struct *work)
4830 {
4831 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4832 idle_work);
4833 struct drm_device *dev = dev_priv->dev;
4834 struct drm_crtc *crtc;
4835 struct intel_crtc *intel_crtc;
4836 int enabled = 0;
4837
4838 if (!i915_powersave)
4839 return;
4840
4841 mutex_lock(&dev->struct_mutex);
4842
4843 i915_update_gfx_val(dev_priv);
4844
4845 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4846 /* Skip inactive CRTCs */
4847 if (!crtc->fb)
4848 continue;
4849
4850 enabled++;
4851 intel_crtc = to_intel_crtc(crtc);
4852 if (!intel_crtc->busy)
4853 intel_decrease_pllclock(crtc);
4854 }
4855
4856 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4857 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4858 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4859 }
4860
4861 mutex_unlock(&dev->struct_mutex);
4862 }
4863
4864 /**
4865 * intel_mark_busy - mark the GPU and possibly the display busy
4866 * @dev: drm device
4867 * @obj: object we're operating on
4868 *
4869 * Callers can use this function to indicate that the GPU is busy processing
4870 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4871 * buffer), we'll also mark the display as busy, so we know to increase its
4872 * clock frequency.
4873 */
4874 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4875 {
4876 drm_i915_private_t *dev_priv = dev->dev_private;
4877 struct drm_crtc *crtc = NULL;
4878 struct intel_framebuffer *intel_fb;
4879 struct intel_crtc *intel_crtc;
4880
4881 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4882 return;
4883
4884 if (!dev_priv->busy) {
4885 if (IS_I945G(dev) || IS_I945GM(dev)) {
4886 u32 fw_blc_self;
4887
4888 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4889 fw_blc_self = I915_READ(FW_BLC_SELF);
4890 fw_blc_self &= ~FW_BLC_SELF_EN;
4891 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4892 }
4893 dev_priv->busy = true;
4894 } else
4895 mod_timer(&dev_priv->idle_timer, jiffies +
4896 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4897
4898 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4899 if (!crtc->fb)
4900 continue;
4901
4902 intel_crtc = to_intel_crtc(crtc);
4903 intel_fb = to_intel_framebuffer(crtc->fb);
4904 if (intel_fb->obj == obj) {
4905 if (!intel_crtc->busy) {
4906 if (IS_I945G(dev) || IS_I945GM(dev)) {
4907 u32 fw_blc_self;
4908
4909 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4910 fw_blc_self = I915_READ(FW_BLC_SELF);
4911 fw_blc_self &= ~FW_BLC_SELF_EN;
4912 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4913 }
4914 /* Non-busy -> busy, upclock */
4915 intel_increase_pllclock(crtc, true);
4916 intel_crtc->busy = true;
4917 } else {
4918 /* Busy -> busy, put off timer */
4919 mod_timer(&intel_crtc->idle_timer, jiffies +
4920 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4921 }
4922 }
4923 }
4924 }
4925
4926 static void intel_crtc_destroy(struct drm_crtc *crtc)
4927 {
4928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4929
4930 drm_crtc_cleanup(crtc);
4931 kfree(intel_crtc);
4932 }
4933
4934 struct intel_unpin_work {
4935 struct work_struct work;
4936 struct drm_device *dev;
4937 struct drm_gem_object *old_fb_obj;
4938 struct drm_gem_object *pending_flip_obj;
4939 struct drm_pending_vblank_event *event;
4940 int pending;
4941 };
4942
4943 static void intel_unpin_work_fn(struct work_struct *__work)
4944 {
4945 struct intel_unpin_work *work =
4946 container_of(__work, struct intel_unpin_work, work);
4947
4948 mutex_lock(&work->dev->struct_mutex);
4949 i915_gem_object_unpin(work->old_fb_obj);
4950 drm_gem_object_unreference(work->pending_flip_obj);
4951 drm_gem_object_unreference(work->old_fb_obj);
4952 mutex_unlock(&work->dev->struct_mutex);
4953 kfree(work);
4954 }
4955
4956 static void do_intel_finish_page_flip(struct drm_device *dev,
4957 struct drm_crtc *crtc)
4958 {
4959 drm_i915_private_t *dev_priv = dev->dev_private;
4960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4961 struct intel_unpin_work *work;
4962 struct drm_i915_gem_object *obj_priv;
4963 struct drm_pending_vblank_event *e;
4964 struct timeval now;
4965 unsigned long flags;
4966
4967 /* Ignore early vblank irqs */
4968 if (intel_crtc == NULL)
4969 return;
4970
4971 spin_lock_irqsave(&dev->event_lock, flags);
4972 work = intel_crtc->unpin_work;
4973 if (work == NULL || !work->pending) {
4974 spin_unlock_irqrestore(&dev->event_lock, flags);
4975 return;
4976 }
4977
4978 intel_crtc->unpin_work = NULL;
4979 drm_vblank_put(dev, intel_crtc->pipe);
4980
4981 if (work->event) {
4982 e = work->event;
4983 do_gettimeofday(&now);
4984 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4985 e->event.tv_sec = now.tv_sec;
4986 e->event.tv_usec = now.tv_usec;
4987 list_add_tail(&e->base.link,
4988 &e->base.file_priv->event_list);
4989 wake_up_interruptible(&e->base.file_priv->event_wait);
4990 }
4991
4992 spin_unlock_irqrestore(&dev->event_lock, flags);
4993
4994 obj_priv = to_intel_bo(work->pending_flip_obj);
4995
4996 /* Initial scanout buffer will have a 0 pending flip count */
4997 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4998 atomic_dec_and_test(&obj_priv->pending_flip))
4999 DRM_WAKEUP(&dev_priv->pending_flip_queue);
5000 schedule_work(&work->work);
5001
5002 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5003 }
5004
5005 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5006 {
5007 drm_i915_private_t *dev_priv = dev->dev_private;
5008 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5009
5010 do_intel_finish_page_flip(dev, crtc);
5011 }
5012
5013 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5014 {
5015 drm_i915_private_t *dev_priv = dev->dev_private;
5016 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5017
5018 do_intel_finish_page_flip(dev, crtc);
5019 }
5020
5021 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5022 {
5023 drm_i915_private_t *dev_priv = dev->dev_private;
5024 struct intel_crtc *intel_crtc =
5025 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5026 unsigned long flags;
5027
5028 spin_lock_irqsave(&dev->event_lock, flags);
5029 if (intel_crtc->unpin_work) {
5030 intel_crtc->unpin_work->pending = 1;
5031 } else {
5032 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5033 }
5034 spin_unlock_irqrestore(&dev->event_lock, flags);
5035 }
5036
5037 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5038 struct drm_framebuffer *fb,
5039 struct drm_pending_vblank_event *event)
5040 {
5041 struct drm_device *dev = crtc->dev;
5042 struct drm_i915_private *dev_priv = dev->dev_private;
5043 struct intel_framebuffer *intel_fb;
5044 struct drm_i915_gem_object *obj_priv;
5045 struct drm_gem_object *obj;
5046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5047 struct intel_unpin_work *work;
5048 unsigned long flags, offset;
5049 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5050 int ret, pipesrc;
5051 u32 flip_mask;
5052
5053 work = kzalloc(sizeof *work, GFP_KERNEL);
5054 if (work == NULL)
5055 return -ENOMEM;
5056
5057 work->event = event;
5058 work->dev = crtc->dev;
5059 intel_fb = to_intel_framebuffer(crtc->fb);
5060 work->old_fb_obj = intel_fb->obj;
5061 INIT_WORK(&work->work, intel_unpin_work_fn);
5062
5063 /* We borrow the event spin lock for protecting unpin_work */
5064 spin_lock_irqsave(&dev->event_lock, flags);
5065 if (intel_crtc->unpin_work) {
5066 spin_unlock_irqrestore(&dev->event_lock, flags);
5067 kfree(work);
5068
5069 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5070 return -EBUSY;
5071 }
5072 intel_crtc->unpin_work = work;
5073 spin_unlock_irqrestore(&dev->event_lock, flags);
5074
5075 intel_fb = to_intel_framebuffer(fb);
5076 obj = intel_fb->obj;
5077
5078 mutex_lock(&dev->struct_mutex);
5079 ret = intel_pin_and_fence_fb_obj(dev, obj);
5080 if (ret)
5081 goto cleanup_work;
5082
5083 /* Reference the objects for the scheduled work. */
5084 drm_gem_object_reference(work->old_fb_obj);
5085 drm_gem_object_reference(obj);
5086
5087 crtc->fb = fb;
5088 ret = i915_gem_object_flush_write_domain(obj);
5089 if (ret)
5090 goto cleanup_objs;
5091
5092 ret = drm_vblank_get(dev, intel_crtc->pipe);
5093 if (ret)
5094 goto cleanup_objs;
5095
5096 obj_priv = to_intel_bo(obj);
5097 atomic_inc(&obj_priv->pending_flip);
5098 work->pending_flip_obj = obj;
5099
5100 if (intel_crtc->plane)
5101 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5102 else
5103 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5104
5105 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5106 BEGIN_LP_RING(2);
5107 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5108 OUT_RING(0);
5109 ADVANCE_LP_RING();
5110 }
5111
5112 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5113 offset = obj_priv->gtt_offset;
5114 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5115
5116 BEGIN_LP_RING(4);
5117 if (IS_I965G(dev)) {
5118 OUT_RING(MI_DISPLAY_FLIP |
5119 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5120 OUT_RING(fb->pitch);
5121 OUT_RING(offset | obj_priv->tiling_mode);
5122 pipesrc = I915_READ(pipesrc_reg);
5123 OUT_RING(pipesrc & 0x0fff0fff);
5124 } else if (IS_GEN3(dev)) {
5125 OUT_RING(MI_DISPLAY_FLIP_I915 |
5126 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5127 OUT_RING(fb->pitch);
5128 OUT_RING(offset);
5129 OUT_RING(MI_NOOP);
5130 } else {
5131 OUT_RING(MI_DISPLAY_FLIP |
5132 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5133 OUT_RING(fb->pitch);
5134 OUT_RING(offset);
5135 OUT_RING(MI_NOOP);
5136 }
5137 ADVANCE_LP_RING();
5138
5139 mutex_unlock(&dev->struct_mutex);
5140
5141 trace_i915_flip_request(intel_crtc->plane, obj);
5142
5143 return 0;
5144
5145 cleanup_objs:
5146 drm_gem_object_unreference(work->old_fb_obj);
5147 drm_gem_object_unreference(obj);
5148 cleanup_work:
5149 mutex_unlock(&dev->struct_mutex);
5150
5151 spin_lock_irqsave(&dev->event_lock, flags);
5152 intel_crtc->unpin_work = NULL;
5153 spin_unlock_irqrestore(&dev->event_lock, flags);
5154
5155 kfree(work);
5156
5157 return ret;
5158 }
5159
5160 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5161 .dpms = intel_crtc_dpms,
5162 .mode_fixup = intel_crtc_mode_fixup,
5163 .mode_set = intel_crtc_mode_set,
5164 .mode_set_base = intel_pipe_set_base,
5165 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5166 .prepare = intel_crtc_prepare,
5167 .commit = intel_crtc_commit,
5168 .load_lut = intel_crtc_load_lut,
5169 };
5170
5171 static const struct drm_crtc_funcs intel_crtc_funcs = {
5172 .cursor_set = intel_crtc_cursor_set,
5173 .cursor_move = intel_crtc_cursor_move,
5174 .gamma_set = intel_crtc_gamma_set,
5175 .set_config = drm_crtc_helper_set_config,
5176 .destroy = intel_crtc_destroy,
5177 .page_flip = intel_crtc_page_flip,
5178 };
5179
5180
5181 static void intel_crtc_init(struct drm_device *dev, int pipe)
5182 {
5183 drm_i915_private_t *dev_priv = dev->dev_private;
5184 struct intel_crtc *intel_crtc;
5185 int i;
5186
5187 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5188 if (intel_crtc == NULL)
5189 return;
5190
5191 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5192
5193 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5194 intel_crtc->pipe = pipe;
5195 intel_crtc->plane = pipe;
5196 for (i = 0; i < 256; i++) {
5197 intel_crtc->lut_r[i] = i;
5198 intel_crtc->lut_g[i] = i;
5199 intel_crtc->lut_b[i] = i;
5200 }
5201
5202 /* Swap pipes & planes for FBC on pre-965 */
5203 intel_crtc->pipe = pipe;
5204 intel_crtc->plane = pipe;
5205 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5206 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5207 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5208 }
5209
5210 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5211 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5212 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5213 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5214
5215 intel_crtc->cursor_addr = 0;
5216 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5217 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5218
5219 intel_crtc->busy = false;
5220
5221 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5222 (unsigned long)intel_crtc);
5223 }
5224
5225 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5226 struct drm_file *file_priv)
5227 {
5228 drm_i915_private_t *dev_priv = dev->dev_private;
5229 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5230 struct drm_mode_object *drmmode_obj;
5231 struct intel_crtc *crtc;
5232
5233 if (!dev_priv) {
5234 DRM_ERROR("called with no initialization\n");
5235 return -EINVAL;
5236 }
5237
5238 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5239 DRM_MODE_OBJECT_CRTC);
5240
5241 if (!drmmode_obj) {
5242 DRM_ERROR("no such CRTC id\n");
5243 return -EINVAL;
5244 }
5245
5246 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5247 pipe_from_crtc_id->pipe = crtc->pipe;
5248
5249 return 0;
5250 }
5251
5252 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5253 {
5254 struct drm_crtc *crtc = NULL;
5255
5256 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5258 if (intel_crtc->pipe == pipe)
5259 break;
5260 }
5261 return crtc;
5262 }
5263
5264 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5265 {
5266 int index_mask = 0;
5267 struct drm_encoder *encoder;
5268 int entry = 0;
5269
5270 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5271 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5272 if (type_mask & intel_encoder->clone_mask)
5273 index_mask |= (1 << entry);
5274 entry++;
5275 }
5276 return index_mask;
5277 }
5278
5279
5280 static void intel_setup_outputs(struct drm_device *dev)
5281 {
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283 struct drm_encoder *encoder;
5284 bool dpd_is_edp = false;
5285
5286 if (IS_MOBILE(dev) && !IS_I830(dev))
5287 intel_lvds_init(dev);
5288
5289 if (HAS_PCH_SPLIT(dev)) {
5290 dpd_is_edp = intel_dpd_is_edp(dev);
5291
5292 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5293 intel_dp_init(dev, DP_A);
5294
5295 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5296 intel_dp_init(dev, PCH_DP_D);
5297 }
5298
5299 intel_crt_init(dev);
5300
5301 if (HAS_PCH_SPLIT(dev)) {
5302 int found;
5303
5304 if (I915_READ(HDMIB) & PORT_DETECTED) {
5305 /* PCH SDVOB multiplex with HDMIB */
5306 found = intel_sdvo_init(dev, PCH_SDVOB);
5307 if (!found)
5308 intel_hdmi_init(dev, HDMIB);
5309 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5310 intel_dp_init(dev, PCH_DP_B);
5311 }
5312
5313 if (I915_READ(HDMIC) & PORT_DETECTED)
5314 intel_hdmi_init(dev, HDMIC);
5315
5316 if (I915_READ(HDMID) & PORT_DETECTED)
5317 intel_hdmi_init(dev, HDMID);
5318
5319 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5320 intel_dp_init(dev, PCH_DP_C);
5321
5322 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5323 intel_dp_init(dev, PCH_DP_D);
5324
5325 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5326 bool found = false;
5327
5328 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5329 DRM_DEBUG_KMS("probing SDVOB\n");
5330 found = intel_sdvo_init(dev, SDVOB);
5331 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5332 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5333 intel_hdmi_init(dev, SDVOB);
5334 }
5335
5336 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5337 DRM_DEBUG_KMS("probing DP_B\n");
5338 intel_dp_init(dev, DP_B);
5339 }
5340 }
5341
5342 /* Before G4X SDVOC doesn't have its own detect register */
5343
5344 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5345 DRM_DEBUG_KMS("probing SDVOC\n");
5346 found = intel_sdvo_init(dev, SDVOC);
5347 }
5348
5349 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5350
5351 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5352 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5353 intel_hdmi_init(dev, SDVOC);
5354 }
5355 if (SUPPORTS_INTEGRATED_DP(dev)) {
5356 DRM_DEBUG_KMS("probing DP_C\n");
5357 intel_dp_init(dev, DP_C);
5358 }
5359 }
5360
5361 if (SUPPORTS_INTEGRATED_DP(dev) &&
5362 (I915_READ(DP_D) & DP_DETECTED)) {
5363 DRM_DEBUG_KMS("probing DP_D\n");
5364 intel_dp_init(dev, DP_D);
5365 }
5366 } else if (IS_GEN2(dev))
5367 intel_dvo_init(dev);
5368
5369 if (SUPPORTS_TV(dev))
5370 intel_tv_init(dev);
5371
5372 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5373 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5374
5375 encoder->possible_crtcs = intel_encoder->crtc_mask;
5376 encoder->possible_clones = intel_encoder_clones(dev,
5377 intel_encoder->clone_mask);
5378 }
5379 }
5380
5381 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5382 {
5383 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5384
5385 drm_framebuffer_cleanup(fb);
5386 drm_gem_object_unreference_unlocked(intel_fb->obj);
5387
5388 kfree(intel_fb);
5389 }
5390
5391 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5392 struct drm_file *file_priv,
5393 unsigned int *handle)
5394 {
5395 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5396 struct drm_gem_object *object = intel_fb->obj;
5397
5398 return drm_gem_handle_create(file_priv, object, handle);
5399 }
5400
5401 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5402 .destroy = intel_user_framebuffer_destroy,
5403 .create_handle = intel_user_framebuffer_create_handle,
5404 };
5405
5406 int intel_framebuffer_init(struct drm_device *dev,
5407 struct intel_framebuffer *intel_fb,
5408 struct drm_mode_fb_cmd *mode_cmd,
5409 struct drm_gem_object *obj)
5410 {
5411 int ret;
5412
5413 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5414 if (ret) {
5415 DRM_ERROR("framebuffer init failed %d\n", ret);
5416 return ret;
5417 }
5418
5419 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5420 intel_fb->obj = obj;
5421 return 0;
5422 }
5423
5424 static struct drm_framebuffer *
5425 intel_user_framebuffer_create(struct drm_device *dev,
5426 struct drm_file *filp,
5427 struct drm_mode_fb_cmd *mode_cmd)
5428 {
5429 struct drm_gem_object *obj;
5430 struct intel_framebuffer *intel_fb;
5431 int ret;
5432
5433 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5434 if (!obj)
5435 return NULL;
5436
5437 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5438 if (!intel_fb)
5439 return NULL;
5440
5441 ret = intel_framebuffer_init(dev, intel_fb,
5442 mode_cmd, obj);
5443 if (ret) {
5444 drm_gem_object_unreference_unlocked(obj);
5445 kfree(intel_fb);
5446 return NULL;
5447 }
5448
5449 return &intel_fb->base;
5450 }
5451
5452 static const struct drm_mode_config_funcs intel_mode_funcs = {
5453 .fb_create = intel_user_framebuffer_create,
5454 .output_poll_changed = intel_fb_output_poll_changed,
5455 };
5456
5457 static struct drm_gem_object *
5458 intel_alloc_power_context(struct drm_device *dev)
5459 {
5460 struct drm_gem_object *pwrctx;
5461 int ret;
5462
5463 pwrctx = i915_gem_alloc_object(dev, 4096);
5464 if (!pwrctx) {
5465 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5466 return NULL;
5467 }
5468
5469 mutex_lock(&dev->struct_mutex);
5470 ret = i915_gem_object_pin(pwrctx, 4096);
5471 if (ret) {
5472 DRM_ERROR("failed to pin power context: %d\n", ret);
5473 goto err_unref;
5474 }
5475
5476 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5477 if (ret) {
5478 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5479 goto err_unpin;
5480 }
5481 mutex_unlock(&dev->struct_mutex);
5482
5483 return pwrctx;
5484
5485 err_unpin:
5486 i915_gem_object_unpin(pwrctx);
5487 err_unref:
5488 drm_gem_object_unreference(pwrctx);
5489 mutex_unlock(&dev->struct_mutex);
5490 return NULL;
5491 }
5492
5493 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5494 {
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 u16 rgvswctl;
5497
5498 rgvswctl = I915_READ16(MEMSWCTL);
5499 if (rgvswctl & MEMCTL_CMD_STS) {
5500 DRM_DEBUG("gpu busy, RCS change rejected\n");
5501 return false; /* still busy with another command */
5502 }
5503
5504 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5505 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5506 I915_WRITE16(MEMSWCTL, rgvswctl);
5507 POSTING_READ16(MEMSWCTL);
5508
5509 rgvswctl |= MEMCTL_CMD_STS;
5510 I915_WRITE16(MEMSWCTL, rgvswctl);
5511
5512 return true;
5513 }
5514
5515 void ironlake_enable_drps(struct drm_device *dev)
5516 {
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518 u32 rgvmodectl = I915_READ(MEMMODECTL);
5519 u8 fmax, fmin, fstart, vstart;
5520 int i = 0;
5521
5522 /* 100ms RC evaluation intervals */
5523 I915_WRITE(RCUPEI, 100000);
5524 I915_WRITE(RCDNEI, 100000);
5525
5526 /* Set max/min thresholds to 90ms and 80ms respectively */
5527 I915_WRITE(RCBMAXAVG, 90000);
5528 I915_WRITE(RCBMINAVG, 80000);
5529
5530 I915_WRITE(MEMIHYST, 1);
5531
5532 /* Set up min, max, and cur for interrupt handling */
5533 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5534 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5535 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5536 MEMMODE_FSTART_SHIFT;
5537 fstart = fmax;
5538
5539 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5540 PXVFREQ_PX_SHIFT;
5541
5542 dev_priv->fmax = fstart; /* IPS callback will increase this */
5543 dev_priv->fstart = fstart;
5544
5545 dev_priv->max_delay = fmax;
5546 dev_priv->min_delay = fmin;
5547 dev_priv->cur_delay = fstart;
5548
5549 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5550 fstart);
5551
5552 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5553
5554 /*
5555 * Interrupts will be enabled in ironlake_irq_postinstall
5556 */
5557
5558 I915_WRITE(VIDSTART, vstart);
5559 POSTING_READ(VIDSTART);
5560
5561 rgvmodectl |= MEMMODE_SWMODE_EN;
5562 I915_WRITE(MEMMODECTL, rgvmodectl);
5563
5564 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5565 if (i++ > 100) {
5566 DRM_ERROR("stuck trying to change perf mode\n");
5567 break;
5568 }
5569 msleep(1);
5570 }
5571 msleep(1);
5572
5573 ironlake_set_drps(dev, fstart);
5574
5575 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5576 I915_READ(0x112e0);
5577 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5578 dev_priv->last_count2 = I915_READ(0x112f4);
5579 getrawmonotonic(&dev_priv->last_time2);
5580 }
5581
5582 void ironlake_disable_drps(struct drm_device *dev)
5583 {
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585 u16 rgvswctl = I915_READ16(MEMSWCTL);
5586
5587 /* Ack interrupts, disable EFC interrupt */
5588 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5589 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5590 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5591 I915_WRITE(DEIIR, DE_PCU_EVENT);
5592 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5593
5594 /* Go back to the starting frequency */
5595 ironlake_set_drps(dev, dev_priv->fstart);
5596 msleep(1);
5597 rgvswctl |= MEMCTL_CMD_STS;
5598 I915_WRITE(MEMSWCTL, rgvswctl);
5599 msleep(1);
5600
5601 }
5602
5603 static unsigned long intel_pxfreq(u32 vidfreq)
5604 {
5605 unsigned long freq;
5606 int div = (vidfreq & 0x3f0000) >> 16;
5607 int post = (vidfreq & 0x3000) >> 12;
5608 int pre = (vidfreq & 0x7);
5609
5610 if (!pre)
5611 return 0;
5612
5613 freq = ((div * 133333) / ((1<<post) * pre));
5614
5615 return freq;
5616 }
5617
5618 void intel_init_emon(struct drm_device *dev)
5619 {
5620 struct drm_i915_private *dev_priv = dev->dev_private;
5621 u32 lcfuse;
5622 u8 pxw[16];
5623 int i;
5624
5625 /* Disable to program */
5626 I915_WRITE(ECR, 0);
5627 POSTING_READ(ECR);
5628
5629 /* Program energy weights for various events */
5630 I915_WRITE(SDEW, 0x15040d00);
5631 I915_WRITE(CSIEW0, 0x007f0000);
5632 I915_WRITE(CSIEW1, 0x1e220004);
5633 I915_WRITE(CSIEW2, 0x04000004);
5634
5635 for (i = 0; i < 5; i++)
5636 I915_WRITE(PEW + (i * 4), 0);
5637 for (i = 0; i < 3; i++)
5638 I915_WRITE(DEW + (i * 4), 0);
5639
5640 /* Program P-state weights to account for frequency power adjustment */
5641 for (i = 0; i < 16; i++) {
5642 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5643 unsigned long freq = intel_pxfreq(pxvidfreq);
5644 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5645 PXVFREQ_PX_SHIFT;
5646 unsigned long val;
5647
5648 val = vid * vid;
5649 val *= (freq / 1000);
5650 val *= 255;
5651 val /= (127*127*900);
5652 if (val > 0xff)
5653 DRM_ERROR("bad pxval: %ld\n", val);
5654 pxw[i] = val;
5655 }
5656 /* Render standby states get 0 weight */
5657 pxw[14] = 0;
5658 pxw[15] = 0;
5659
5660 for (i = 0; i < 4; i++) {
5661 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5662 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5663 I915_WRITE(PXW + (i * 4), val);
5664 }
5665
5666 /* Adjust magic regs to magic values (more experimental results) */
5667 I915_WRITE(OGW0, 0);
5668 I915_WRITE(OGW1, 0);
5669 I915_WRITE(EG0, 0x00007f00);
5670 I915_WRITE(EG1, 0x0000000e);
5671 I915_WRITE(EG2, 0x000e0000);
5672 I915_WRITE(EG3, 0x68000300);
5673 I915_WRITE(EG4, 0x42000000);
5674 I915_WRITE(EG5, 0x00140031);
5675 I915_WRITE(EG6, 0);
5676 I915_WRITE(EG7, 0);
5677
5678 for (i = 0; i < 8; i++)
5679 I915_WRITE(PXWL + (i * 4), 0);
5680
5681 /* Enable PMON + select events */
5682 I915_WRITE(ECR, 0x80000019);
5683
5684 lcfuse = I915_READ(LCFUSE02);
5685
5686 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5687 }
5688
5689 void intel_init_clock_gating(struct drm_device *dev)
5690 {
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692
5693 /*
5694 * Disable clock gating reported to work incorrectly according to the
5695 * specs, but enable as much else as we can.
5696 */
5697 if (HAS_PCH_SPLIT(dev)) {
5698 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5699
5700 if (IS_IRONLAKE(dev)) {
5701 /* Required for FBC */
5702 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5703 /* Required for CxSR */
5704 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5705
5706 I915_WRITE(PCH_3DCGDIS0,
5707 MARIUNIT_CLOCK_GATE_DISABLE |
5708 SVSMUNIT_CLOCK_GATE_DISABLE);
5709 }
5710
5711 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5712
5713 /*
5714 * According to the spec the following bits should be set in
5715 * order to enable memory self-refresh
5716 * The bit 22/21 of 0x42004
5717 * The bit 5 of 0x42020
5718 * The bit 15 of 0x45000
5719 */
5720 if (IS_IRONLAKE(dev)) {
5721 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5722 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5723 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5724 I915_WRITE(ILK_DSPCLK_GATE,
5725 (I915_READ(ILK_DSPCLK_GATE) |
5726 ILK_DPARB_CLK_GATE));
5727 I915_WRITE(DISP_ARB_CTL,
5728 (I915_READ(DISP_ARB_CTL) |
5729 DISP_FBC_WM_DIS));
5730 }
5731 /*
5732 * Based on the document from hardware guys the following bits
5733 * should be set unconditionally in order to enable FBC.
5734 * The bit 22 of 0x42000
5735 * The bit 22 of 0x42004
5736 * The bit 7,8,9 of 0x42020.
5737 */
5738 if (IS_IRONLAKE_M(dev)) {
5739 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5740 I915_READ(ILK_DISPLAY_CHICKEN1) |
5741 ILK_FBCQ_DIS);
5742 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5743 I915_READ(ILK_DISPLAY_CHICKEN2) |
5744 ILK_DPARB_GATE);
5745 I915_WRITE(ILK_DSPCLK_GATE,
5746 I915_READ(ILK_DSPCLK_GATE) |
5747 ILK_DPFC_DIS1 |
5748 ILK_DPFC_DIS2 |
5749 ILK_CLK_FBC);
5750 }
5751 return;
5752 } else if (IS_G4X(dev)) {
5753 uint32_t dspclk_gate;
5754 I915_WRITE(RENCLK_GATE_D1, 0);
5755 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5756 GS_UNIT_CLOCK_GATE_DISABLE |
5757 CL_UNIT_CLOCK_GATE_DISABLE);
5758 I915_WRITE(RAMCLK_GATE_D, 0);
5759 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5760 OVRUNIT_CLOCK_GATE_DISABLE |
5761 OVCUNIT_CLOCK_GATE_DISABLE;
5762 if (IS_GM45(dev))
5763 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5764 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5765 } else if (IS_I965GM(dev)) {
5766 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5767 I915_WRITE(RENCLK_GATE_D2, 0);
5768 I915_WRITE(DSPCLK_GATE_D, 0);
5769 I915_WRITE(RAMCLK_GATE_D, 0);
5770 I915_WRITE16(DEUC, 0);
5771 } else if (IS_I965G(dev)) {
5772 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5773 I965_RCC_CLOCK_GATE_DISABLE |
5774 I965_RCPB_CLOCK_GATE_DISABLE |
5775 I965_ISC_CLOCK_GATE_DISABLE |
5776 I965_FBC_CLOCK_GATE_DISABLE);
5777 I915_WRITE(RENCLK_GATE_D2, 0);
5778 } else if (IS_I9XX(dev)) {
5779 u32 dstate = I915_READ(D_STATE);
5780
5781 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5782 DSTATE_DOT_CLOCK_GATING;
5783 I915_WRITE(D_STATE, dstate);
5784 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5785 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5786 } else if (IS_I830(dev)) {
5787 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5788 }
5789
5790 /*
5791 * GPU can automatically power down the render unit if given a page
5792 * to save state.
5793 */
5794 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5795 struct drm_i915_gem_object *obj_priv = NULL;
5796
5797 if (dev_priv->pwrctx) {
5798 obj_priv = to_intel_bo(dev_priv->pwrctx);
5799 } else {
5800 struct drm_gem_object *pwrctx;
5801
5802 pwrctx = intel_alloc_power_context(dev);
5803 if (pwrctx) {
5804 dev_priv->pwrctx = pwrctx;
5805 obj_priv = to_intel_bo(pwrctx);
5806 }
5807 }
5808
5809 if (obj_priv) {
5810 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5811 I915_WRITE(MCHBAR_RENDER_STANDBY,
5812 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5813 }
5814 }
5815 }
5816
5817 /* Set up chip specific display functions */
5818 static void intel_init_display(struct drm_device *dev)
5819 {
5820 struct drm_i915_private *dev_priv = dev->dev_private;
5821
5822 /* We always want a DPMS function */
5823 if (HAS_PCH_SPLIT(dev))
5824 dev_priv->display.dpms = ironlake_crtc_dpms;
5825 else
5826 dev_priv->display.dpms = i9xx_crtc_dpms;
5827
5828 if (I915_HAS_FBC(dev)) {
5829 if (IS_IRONLAKE_M(dev)) {
5830 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5831 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5832 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5833 } else if (IS_GM45(dev)) {
5834 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5835 dev_priv->display.enable_fbc = g4x_enable_fbc;
5836 dev_priv->display.disable_fbc = g4x_disable_fbc;
5837 } else if (IS_I965GM(dev)) {
5838 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5839 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5840 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5841 }
5842 /* 855GM needs testing */
5843 }
5844
5845 /* Returns the core display clock speed */
5846 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5847 dev_priv->display.get_display_clock_speed =
5848 i945_get_display_clock_speed;
5849 else if (IS_I915G(dev))
5850 dev_priv->display.get_display_clock_speed =
5851 i915_get_display_clock_speed;
5852 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5853 dev_priv->display.get_display_clock_speed =
5854 i9xx_misc_get_display_clock_speed;
5855 else if (IS_I915GM(dev))
5856 dev_priv->display.get_display_clock_speed =
5857 i915gm_get_display_clock_speed;
5858 else if (IS_I865G(dev))
5859 dev_priv->display.get_display_clock_speed =
5860 i865_get_display_clock_speed;
5861 else if (IS_I85X(dev))
5862 dev_priv->display.get_display_clock_speed =
5863 i855_get_display_clock_speed;
5864 else /* 852, 830 */
5865 dev_priv->display.get_display_clock_speed =
5866 i830_get_display_clock_speed;
5867
5868 /* For FIFO watermark updates */
5869 if (HAS_PCH_SPLIT(dev)) {
5870 if (IS_IRONLAKE(dev)) {
5871 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5872 dev_priv->display.update_wm = ironlake_update_wm;
5873 else {
5874 DRM_DEBUG_KMS("Failed to get proper latency. "
5875 "Disable CxSR\n");
5876 dev_priv->display.update_wm = NULL;
5877 }
5878 } else
5879 dev_priv->display.update_wm = NULL;
5880 } else if (IS_PINEVIEW(dev)) {
5881 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5882 dev_priv->is_ddr3,
5883 dev_priv->fsb_freq,
5884 dev_priv->mem_freq)) {
5885 DRM_INFO("failed to find known CxSR latency "
5886 "(found ddr%s fsb freq %d, mem freq %d), "
5887 "disabling CxSR\n",
5888 (dev_priv->is_ddr3 == 1) ? "3": "2",
5889 dev_priv->fsb_freq, dev_priv->mem_freq);
5890 /* Disable CxSR and never update its watermark again */
5891 pineview_disable_cxsr(dev);
5892 dev_priv->display.update_wm = NULL;
5893 } else
5894 dev_priv->display.update_wm = pineview_update_wm;
5895 } else if (IS_G4X(dev))
5896 dev_priv->display.update_wm = g4x_update_wm;
5897 else if (IS_I965G(dev))
5898 dev_priv->display.update_wm = i965_update_wm;
5899 else if (IS_I9XX(dev)) {
5900 dev_priv->display.update_wm = i9xx_update_wm;
5901 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5902 } else if (IS_I85X(dev)) {
5903 dev_priv->display.update_wm = i9xx_update_wm;
5904 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5905 } else {
5906 dev_priv->display.update_wm = i830_update_wm;
5907 if (IS_845G(dev))
5908 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5909 else
5910 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5911 }
5912 }
5913
5914 /*
5915 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5916 * resume, or other times. This quirk makes sure that's the case for
5917 * affected systems.
5918 */
5919 static void quirk_pipea_force (struct drm_device *dev)
5920 {
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5922
5923 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5924 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5925 }
5926
5927 struct intel_quirk {
5928 int device;
5929 int subsystem_vendor;
5930 int subsystem_device;
5931 void (*hook)(struct drm_device *dev);
5932 };
5933
5934 struct intel_quirk intel_quirks[] = {
5935 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5936 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5937 /* HP Mini needs pipe A force quirk (LP: #322104) */
5938 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5939
5940 /* Thinkpad R31 needs pipe A force quirk */
5941 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5942 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5943 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5944
5945 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5946 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5947 /* ThinkPad X40 needs pipe A force quirk */
5948
5949 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5950 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5951
5952 /* 855 & before need to leave pipe A & dpll A up */
5953 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5954 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5955 };
5956
5957 static void intel_init_quirks(struct drm_device *dev)
5958 {
5959 struct pci_dev *d = dev->pdev;
5960 int i;
5961
5962 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5963 struct intel_quirk *q = &intel_quirks[i];
5964
5965 if (d->device == q->device &&
5966 (d->subsystem_vendor == q->subsystem_vendor ||
5967 q->subsystem_vendor == PCI_ANY_ID) &&
5968 (d->subsystem_device == q->subsystem_device ||
5969 q->subsystem_device == PCI_ANY_ID))
5970 q->hook(dev);
5971 }
5972 }
5973
5974 void intel_modeset_init(struct drm_device *dev)
5975 {
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977 int i;
5978
5979 drm_mode_config_init(dev);
5980
5981 dev->mode_config.min_width = 0;
5982 dev->mode_config.min_height = 0;
5983
5984 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5985
5986 intel_init_quirks(dev);
5987
5988 intel_init_display(dev);
5989
5990 if (IS_I965G(dev)) {
5991 dev->mode_config.max_width = 8192;
5992 dev->mode_config.max_height = 8192;
5993 } else if (IS_I9XX(dev)) {
5994 dev->mode_config.max_width = 4096;
5995 dev->mode_config.max_height = 4096;
5996 } else {
5997 dev->mode_config.max_width = 2048;
5998 dev->mode_config.max_height = 2048;
5999 }
6000
6001 /* set memory base */
6002 if (IS_I9XX(dev))
6003 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6004 else
6005 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6006
6007 if (IS_MOBILE(dev) || IS_I9XX(dev))
6008 dev_priv->num_pipe = 2;
6009 else
6010 dev_priv->num_pipe = 1;
6011 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6012 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6013
6014 for (i = 0; i < dev_priv->num_pipe; i++) {
6015 intel_crtc_init(dev, i);
6016 }
6017
6018 intel_setup_outputs(dev);
6019
6020 intel_init_clock_gating(dev);
6021
6022 if (IS_IRONLAKE_M(dev)) {
6023 ironlake_enable_drps(dev);
6024 intel_init_emon(dev);
6025 }
6026
6027 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6028 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6029 (unsigned long)dev);
6030
6031 intel_setup_overlay(dev);
6032 }
6033
6034 void intel_modeset_cleanup(struct drm_device *dev)
6035 {
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6037 struct drm_crtc *crtc;
6038 struct intel_crtc *intel_crtc;
6039
6040 mutex_lock(&dev->struct_mutex);
6041
6042 drm_kms_helper_poll_fini(dev);
6043 intel_fbdev_fini(dev);
6044
6045 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6046 /* Skip inactive CRTCs */
6047 if (!crtc->fb)
6048 continue;
6049
6050 intel_crtc = to_intel_crtc(crtc);
6051 intel_increase_pllclock(crtc, false);
6052 del_timer_sync(&intel_crtc->idle_timer);
6053 }
6054
6055 del_timer_sync(&dev_priv->idle_timer);
6056
6057 if (dev_priv->display.disable_fbc)
6058 dev_priv->display.disable_fbc(dev);
6059
6060 if (dev_priv->pwrctx) {
6061 struct drm_i915_gem_object *obj_priv;
6062
6063 obj_priv = to_intel_bo(dev_priv->pwrctx);
6064 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6065 I915_READ(PWRCTXA);
6066 i915_gem_object_unpin(dev_priv->pwrctx);
6067 drm_gem_object_unreference(dev_priv->pwrctx);
6068 }
6069
6070 if (IS_IRONLAKE_M(dev))
6071 ironlake_disable_drps(dev);
6072
6073 mutex_unlock(&dev->struct_mutex);
6074
6075 drm_mode_config_cleanup(dev);
6076 }
6077
6078
6079 /*
6080 * Return which encoder is currently attached for connector.
6081 */
6082 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6083 {
6084 struct drm_mode_object *obj;
6085 struct drm_encoder *encoder;
6086 int i;
6087
6088 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6089 if (connector->encoder_ids[i] == 0)
6090 break;
6091
6092 obj = drm_mode_object_find(connector->dev,
6093 connector->encoder_ids[i],
6094 DRM_MODE_OBJECT_ENCODER);
6095 if (!obj)
6096 continue;
6097
6098 encoder = obj_to_encoder(obj);
6099 return encoder;
6100 }
6101 return NULL;
6102 }
6103
6104 /*
6105 * set vga decode state - true == enable VGA decode
6106 */
6107 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6108 {
6109 struct drm_i915_private *dev_priv = dev->dev_private;
6110 u16 gmch_ctrl;
6111
6112 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6113 if (state)
6114 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6115 else
6116 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6117 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6118 return 0;
6119 }
Linux kernel - Deliverables
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