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2617ab580dff13383aebbfad8a430e6f91515ac1
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static inline u32 /* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device *dev)
103 {
104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
109 }
110
111 static const intel_limit_t intel_limits_i8xx_dvo = {
112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
122 .find_pll = intel_find_best_PLL,
123 };
124
125 static const intel_limit_t intel_limits_i8xx_lvds = {
126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
136 .find_pll = intel_find_best_PLL,
137 };
138
139 static const intel_limit_t intel_limits_i9xx_sdvo = {
140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
150 .find_pll = intel_find_best_PLL,
151 };
152
153 static const intel_limit_t intel_limits_i9xx_lvds = {
154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
164 .find_pll = intel_find_best_PLL,
165 };
166
167
168 static const intel_limit_t intel_limits_g4x_sdvo = {
169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
180 },
181 .find_pll = intel_g4x_find_best_PLL,
182 };
183
184 static const intel_limit_t intel_limits_g4x_hdmi = {
185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
195 .find_pll = intel_g4x_find_best_PLL,
196 };
197
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
224 },
225 .find_pll = intel_g4x_find_best_PLL,
226 };
227
228 static const intel_limit_t intel_limits_g4x_display_port = {
229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 10, .p2_fast = 10 },
239 .find_pll = intel_find_pll_g4x_dp,
240 };
241
242 static const intel_limit_t intel_limits_pineview_sdvo = {
243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
255 .find_pll = intel_find_best_PLL,
256 };
257
258 static const intel_limit_t intel_limits_pineview_lvds = {
259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
269 .find_pll = intel_find_best_PLL,
270 };
271
272 /* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
277 static const intel_limit_t intel_limits_ironlake_dac = {
278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
288 .find_pll = intel_g4x_find_best_PLL,
289 };
290
291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
302 .find_pll = intel_g4x_find_best_PLL,
303 };
304
305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
316 .find_pll = intel_g4x_find_best_PLL,
317 };
318
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 static const intel_limit_t intel_limits_ironlake_display_port = {
349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 10, .p2_fast = 10 },
359 .find_pll = intel_find_pll_ironlake_dp,
360 };
361
362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363 {
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382 out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385 }
386
387 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
388 u32 val)
389 {
390 unsigned long flags;
391
392 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
393 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
394 DRM_ERROR("DPIO idle wait timed out\n");
395 goto out_unlock;
396 }
397
398 I915_WRITE(DPIO_DATA, val);
399 I915_WRITE(DPIO_REG, reg);
400 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
401 DPIO_BYTE);
402 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
403 DRM_ERROR("DPIO write wait timed out\n");
404
405 out_unlock:
406 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
407 }
408
409 static void vlv_init_dpio(struct drm_device *dev)
410 {
411 struct drm_i915_private *dev_priv = dev->dev_private;
412
413 /* Reset the DPIO config */
414 I915_WRITE(DPIO_CTL, 0);
415 POSTING_READ(DPIO_CTL);
416 I915_WRITE(DPIO_CTL, 1);
417 POSTING_READ(DPIO_CTL);
418 }
419
420 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
421 {
422 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
423 return 1;
424 }
425
426 static const struct dmi_system_id intel_dual_link_lvds[] = {
427 {
428 .callback = intel_dual_link_lvds_callback,
429 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
430 .matches = {
431 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
432 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
433 },
434 },
435 { } /* terminating entry */
436 };
437
438 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
439 unsigned int reg)
440 {
441 unsigned int val;
442
443 /* use the module option value if specified */
444 if (i915_lvds_channel_mode > 0)
445 return i915_lvds_channel_mode == 2;
446
447 if (dmi_check_system(intel_dual_link_lvds))
448 return true;
449
450 if (dev_priv->lvds_val)
451 val = dev_priv->lvds_val;
452 else {
453 /* BIOS should set the proper LVDS register value at boot, but
454 * in reality, it doesn't set the value when the lid is closed;
455 * we need to check "the value to be set" in VBT when LVDS
456 * register is uninitialized.
457 */
458 val = I915_READ(reg);
459 if (!(val & ~LVDS_DETECTED))
460 val = dev_priv->bios_lvds_val;
461 dev_priv->lvds_val = val;
462 }
463 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
464 }
465
466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
468 {
469 struct drm_device *dev = crtc->dev;
470 struct drm_i915_private *dev_priv = dev->dev_private;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
475 /* LVDS dual channel */
476 if (refclk == 100000)
477 limit = &intel_limits_ironlake_dual_lvds_100m;
478 else
479 limit = &intel_limits_ironlake_dual_lvds;
480 } else {
481 if (refclk == 100000)
482 limit = &intel_limits_ironlake_single_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_single_lvds;
485 }
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
487 HAS_eDP)
488 limit = &intel_limits_ironlake_display_port;
489 else
490 limit = &intel_limits_ironlake_dac;
491
492 return limit;
493 }
494
495 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
496 {
497 struct drm_device *dev = crtc->dev;
498 struct drm_i915_private *dev_priv = dev->dev_private;
499 const intel_limit_t *limit;
500
501 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
502 if (is_dual_link_lvds(dev_priv, LVDS))
503 /* LVDS with dual channel */
504 limit = &intel_limits_g4x_dual_channel_lvds;
505 else
506 /* LVDS with dual channel */
507 limit = &intel_limits_g4x_single_channel_lvds;
508 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
510 limit = &intel_limits_g4x_hdmi;
511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
512 limit = &intel_limits_g4x_sdvo;
513 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
514 limit = &intel_limits_g4x_display_port;
515 } else /* The option is for other outputs */
516 limit = &intel_limits_i9xx_sdvo;
517
518 return limit;
519 }
520
521 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
522 {
523 struct drm_device *dev = crtc->dev;
524 const intel_limit_t *limit;
525
526 if (HAS_PCH_SPLIT(dev))
527 limit = intel_ironlake_limit(crtc, refclk);
528 else if (IS_G4X(dev)) {
529 limit = intel_g4x_limit(crtc);
530 } else if (IS_PINEVIEW(dev)) {
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
532 limit = &intel_limits_pineview_lvds;
533 else
534 limit = &intel_limits_pineview_sdvo;
535 } else if (!IS_GEN2(dev)) {
536 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
537 limit = &intel_limits_i9xx_lvds;
538 else
539 limit = &intel_limits_i9xx_sdvo;
540 } else {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i8xx_lvds;
543 else
544 limit = &intel_limits_i8xx_dvo;
545 }
546 return limit;
547 }
548
549 /* m1 is reserved as 0 in Pineview, n is a ring counter */
550 static void pineview_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m2 + 2;
553 clock->p = clock->p1 * clock->p2;
554 clock->vco = refclk * clock->m / clock->n;
555 clock->dot = clock->vco / clock->p;
556 }
557
558 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
559 {
560 if (IS_PINEVIEW(dev)) {
561 pineview_clock(refclk, clock);
562 return;
563 }
564 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
565 clock->p = clock->p1 * clock->p2;
566 clock->vco = refclk * clock->m / (clock->n + 2);
567 clock->dot = clock->vco / clock->p;
568 }
569
570 /**
571 * Returns whether any output on the specified pipe is of the specified type
572 */
573 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
574 {
575 struct drm_device *dev = crtc->dev;
576 struct drm_mode_config *mode_config = &dev->mode_config;
577 struct intel_encoder *encoder;
578
579 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
580 if (encoder->base.crtc == crtc && encoder->type == type)
581 return true;
582
583 return false;
584 }
585
586 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
587 /**
588 * Returns whether the given set of divisors are valid for a given refclk with
589 * the given connectors.
590 */
591
592 static bool intel_PLL_is_valid(struct drm_device *dev,
593 const intel_limit_t *limit,
594 const intel_clock_t *clock)
595 {
596 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
597 INTELPllInvalid("p1 out of range\n");
598 if (clock->p < limit->p.min || limit->p.max < clock->p)
599 INTELPllInvalid("p out of range\n");
600 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
601 INTELPllInvalid("m2 out of range\n");
602 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
603 INTELPllInvalid("m1 out of range\n");
604 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
605 INTELPllInvalid("m1 <= m2\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 if (clock->n < limit->n.min || limit->n.max < clock->n)
609 INTELPllInvalid("n out of range\n");
610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
616 INTELPllInvalid("dot out of range\n");
617
618 return true;
619 }
620
621 static bool
622 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
623 int target, int refclk, intel_clock_t *match_clock,
624 intel_clock_t *best_clock)
625
626 {
627 struct drm_device *dev = crtc->dev;
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 intel_clock_t clock;
630 int err = target;
631
632 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
633 (I915_READ(LVDS)) != 0) {
634 /*
635 * For LVDS, if the panel is on, just rely on its current
636 * settings for dual-channel. We haven't figured out how to
637 * reliably set up different single/dual channel state, if we
638 * even can.
639 */
640 if (is_dual_link_lvds(dev_priv, LVDS))
641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
651 memset(best_clock, 0, sizeof(*best_clock));
652
653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
654 clock.m1++) {
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
657 /* m1 is always 0 in Pineview */
658 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
664 int this_err;
665
666 intel_clock(dev, refclk, &clock);
667 if (!intel_PLL_is_valid(dev, limit,
668 &clock))
669 continue;
670 if (match_clock &&
671 clock.p != match_clock->p)
672 continue;
673
674 this_err = abs(clock.dot - target);
675 if (this_err < err) {
676 *best_clock = clock;
677 err = this_err;
678 }
679 }
680 }
681 }
682 }
683
684 return (err != target);
685 }
686
687 static bool
688 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
691 {
692 struct drm_device *dev = crtc->dev;
693 struct drm_i915_private *dev_priv = dev->dev_private;
694 intel_clock_t clock;
695 int max_n;
696 bool found;
697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
702 int lvds_reg;
703
704 if (HAS_PCH_SPLIT(dev))
705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
708 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
709 LVDS_CLKB_POWER_UP)
710 clock.p2 = limit->p2.p2_fast;
711 else
712 clock.p2 = limit->p2.p2_slow;
713 } else {
714 if (target < limit->p2.dot_limit)
715 clock.p2 = limit->p2.p2_slow;
716 else
717 clock.p2 = limit->p2.p2_fast;
718 }
719
720 memset(best_clock, 0, sizeof(*best_clock));
721 max_n = limit->n.max;
722 /* based on hardware requirement, prefer smaller n to precision */
723 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
724 /* based on hardware requirement, prefere larger m1,m2 */
725 for (clock.m1 = limit->m1.max;
726 clock.m1 >= limit->m1.min; clock.m1--) {
727 for (clock.m2 = limit->m2.max;
728 clock.m2 >= limit->m2.min; clock.m2--) {
729 for (clock.p1 = limit->p1.max;
730 clock.p1 >= limit->p1.min; clock.p1--) {
731 int this_err;
732
733 intel_clock(dev, refclk, &clock);
734 if (!intel_PLL_is_valid(dev, limit,
735 &clock))
736 continue;
737 if (match_clock &&
738 clock.p != match_clock->p)
739 continue;
740
741 this_err = abs(clock.dot - target);
742 if (this_err < err_most) {
743 *best_clock = clock;
744 err_most = this_err;
745 max_n = clock.n;
746 found = true;
747 }
748 }
749 }
750 }
751 }
752 return found;
753 }
754
755 static bool
756 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
757 int target, int refclk, intel_clock_t *match_clock,
758 intel_clock_t *best_clock)
759 {
760 struct drm_device *dev = crtc->dev;
761 intel_clock_t clock;
762
763 if (target < 200000) {
764 clock.n = 1;
765 clock.p1 = 2;
766 clock.p2 = 10;
767 clock.m1 = 12;
768 clock.m2 = 9;
769 } else {
770 clock.n = 2;
771 clock.p1 = 1;
772 clock.p2 = 10;
773 clock.m1 = 14;
774 clock.m2 = 8;
775 }
776 intel_clock(dev, refclk, &clock);
777 memcpy(best_clock, &clock, sizeof(intel_clock_t));
778 return true;
779 }
780
781 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
782 static bool
783 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
784 int target, int refclk, intel_clock_t *match_clock,
785 intel_clock_t *best_clock)
786 {
787 intel_clock_t clock;
788 if (target < 200000) {
789 clock.p1 = 2;
790 clock.p2 = 10;
791 clock.n = 2;
792 clock.m1 = 23;
793 clock.m2 = 8;
794 } else {
795 clock.p1 = 1;
796 clock.p2 = 10;
797 clock.n = 1;
798 clock.m1 = 14;
799 clock.m2 = 2;
800 }
801 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
802 clock.p = (clock.p1 * clock.p2);
803 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
804 clock.vco = 0;
805 memcpy(best_clock, &clock, sizeof(intel_clock_t));
806 return true;
807 }
808
809 /**
810 * intel_wait_for_vblank - wait for vblank on a given pipe
811 * @dev: drm device
812 * @pipe: pipe to wait for
813 *
814 * Wait for vblank to occur on a given pipe. Needed for various bits of
815 * mode setting code.
816 */
817 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
818 {
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 int pipestat_reg = PIPESTAT(pipe);
821
822 /* Clear existing vblank status. Note this will clear any other
823 * sticky status fields as well.
824 *
825 * This races with i915_driver_irq_handler() with the result
826 * that either function could miss a vblank event. Here it is not
827 * fatal, as we will either wait upon the next vblank interrupt or
828 * timeout. Generally speaking intel_wait_for_vblank() is only
829 * called during modeset at which time the GPU should be idle and
830 * should *not* be performing page flips and thus not waiting on
831 * vblanks...
832 * Currently, the result of us stealing a vblank from the irq
833 * handler is that a single frame will be skipped during swapbuffers.
834 */
835 I915_WRITE(pipestat_reg,
836 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
837
838 /* Wait for vblank interrupt bit to set */
839 if (wait_for(I915_READ(pipestat_reg) &
840 PIPE_VBLANK_INTERRUPT_STATUS,
841 50))
842 DRM_DEBUG_KMS("vblank wait timed out\n");
843 }
844
845 /*
846 * intel_wait_for_pipe_off - wait for pipe to turn off
847 * @dev: drm device
848 * @pipe: pipe to wait for
849 *
850 * After disabling a pipe, we can't wait for vblank in the usual way,
851 * spinning on the vblank interrupt status bit, since we won't actually
852 * see an interrupt when the pipe is disabled.
853 *
854 * On Gen4 and above:
855 * wait for the pipe register state bit to turn off
856 *
857 * Otherwise:
858 * wait for the display line value to settle (it usually
859 * ends up stopping at the start of the next frame).
860 *
861 */
862 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
863 {
864 struct drm_i915_private *dev_priv = dev->dev_private;
865
866 if (INTEL_INFO(dev)->gen >= 4) {
867 int reg = PIPECONF(pipe);
868
869 /* Wait for the Pipe State to go off */
870 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
871 100))
872 DRM_DEBUG_KMS("pipe_off wait timed out\n");
873 } else {
874 u32 last_line;
875 int reg = PIPEDSL(pipe);
876 unsigned long timeout = jiffies + msecs_to_jiffies(100);
877
878 /* Wait for the display line to settle */
879 do {
880 last_line = I915_READ(reg) & DSL_LINEMASK;
881 mdelay(5);
882 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
883 time_after(timeout, jiffies));
884 if (time_after(jiffies, timeout))
885 DRM_DEBUG_KMS("pipe_off wait timed out\n");
886 }
887 }
888
889 static const char *state_string(bool enabled)
890 {
891 return enabled ? "on" : "off";
892 }
893
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897 {
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908 }
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
912 /* For ILK+ */
913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
914 struct intel_crtc *intel_crtc, bool state)
915 {
916 int reg;
917 u32 val;
918 bool cur_state;
919
920 if (!intel_crtc->pch_pll) {
921 WARN(1, "asserting PCH PLL enabled with no PLL\n");
922 return;
923 }
924
925 if (HAS_PCH_CPT(dev_priv->dev)) {
926 u32 pch_dpll;
927
928 pch_dpll = I915_READ(PCH_DPLL_SEL);
929
930 /* Make sure the selected PLL is enabled to the transcoder */
931 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
932 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
933 }
934
935 reg = intel_crtc->pch_pll->pll_reg;
936 val = I915_READ(reg);
937 cur_state = !!(val & DPLL_VCO_ENABLE);
938 WARN(cur_state != state,
939 "PCH PLL state assertion failure (expected %s, current %s)\n",
940 state_string(state), state_string(cur_state));
941 }
942 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
943 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
944
945 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
946 enum pipe pipe, bool state)
947 {
948 int reg;
949 u32 val;
950 bool cur_state;
951
952 reg = FDI_TX_CTL(pipe);
953 val = I915_READ(reg);
954 cur_state = !!(val & FDI_TX_ENABLE);
955 WARN(cur_state != state,
956 "FDI TX state assertion failure (expected %s, current %s)\n",
957 state_string(state), state_string(cur_state));
958 }
959 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
960 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
961
962 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
963 enum pipe pipe, bool state)
964 {
965 int reg;
966 u32 val;
967 bool cur_state;
968
969 reg = FDI_RX_CTL(pipe);
970 val = I915_READ(reg);
971 cur_state = !!(val & FDI_RX_ENABLE);
972 WARN(cur_state != state,
973 "FDI RX state assertion failure (expected %s, current %s)\n",
974 state_string(state), state_string(cur_state));
975 }
976 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
977 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
978
979 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
980 enum pipe pipe)
981 {
982 int reg;
983 u32 val;
984
985 /* ILK FDI PLL is always enabled */
986 if (dev_priv->info->gen == 5)
987 return;
988
989 reg = FDI_TX_CTL(pipe);
990 val = I915_READ(reg);
991 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
992 }
993
994 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
995 enum pipe pipe)
996 {
997 int reg;
998 u32 val;
999
1000 reg = FDI_RX_CTL(pipe);
1001 val = I915_READ(reg);
1002 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1003 }
1004
1005 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1006 enum pipe pipe)
1007 {
1008 int pp_reg, lvds_reg;
1009 u32 val;
1010 enum pipe panel_pipe = PIPE_A;
1011 bool locked = true;
1012
1013 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1014 pp_reg = PCH_PP_CONTROL;
1015 lvds_reg = PCH_LVDS;
1016 } else {
1017 pp_reg = PP_CONTROL;
1018 lvds_reg = LVDS;
1019 }
1020
1021 val = I915_READ(pp_reg);
1022 if (!(val & PANEL_POWER_ON) ||
1023 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1024 locked = false;
1025
1026 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1027 panel_pipe = PIPE_B;
1028
1029 WARN(panel_pipe == pipe && locked,
1030 "panel assertion failure, pipe %c regs locked\n",
1031 pipe_name(pipe));
1032 }
1033
1034 void assert_pipe(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
1036 {
1037 int reg;
1038 u32 val;
1039 bool cur_state;
1040
1041 /* if we need the pipe A quirk it must be always on */
1042 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1043 state = true;
1044
1045 reg = PIPECONF(pipe);
1046 val = I915_READ(reg);
1047 cur_state = !!(val & PIPECONF_ENABLE);
1048 WARN(cur_state != state,
1049 "pipe %c assertion failure (expected %s, current %s)\n",
1050 pipe_name(pipe), state_string(state), state_string(cur_state));
1051 }
1052
1053 static void assert_plane(struct drm_i915_private *dev_priv,
1054 enum plane plane, bool state)
1055 {
1056 int reg;
1057 u32 val;
1058 bool cur_state;
1059
1060 reg = DSPCNTR(plane);
1061 val = I915_READ(reg);
1062 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1063 WARN(cur_state != state,
1064 "plane %c assertion failure (expected %s, current %s)\n",
1065 plane_name(plane), state_string(state), state_string(cur_state));
1066 }
1067
1068 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1069 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1070
1071 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073 {
1074 int reg, i;
1075 u32 val;
1076 int cur_pipe;
1077
1078 /* Planes are fixed to pipes on ILK+ */
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 reg = DSPCNTR(pipe);
1081 val = I915_READ(reg);
1082 WARN((val & DISPLAY_PLANE_ENABLE),
1083 "plane %c assertion failure, should be disabled but not\n",
1084 plane_name(pipe));
1085 return;
1086 }
1087
1088 /* Need to check both planes against the pipe */
1089 for (i = 0; i < 2; i++) {
1090 reg = DSPCNTR(i);
1091 val = I915_READ(reg);
1092 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1093 DISPPLANE_SEL_PIPE_SHIFT;
1094 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1095 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1096 plane_name(i), pipe_name(pipe));
1097 }
1098 }
1099
1100 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1101 {
1102 u32 val;
1103 bool enabled;
1104
1105 val = I915_READ(PCH_DREF_CONTROL);
1106 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1107 DREF_SUPERSPREAD_SOURCE_MASK));
1108 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1109 }
1110
1111 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1112 enum pipe pipe)
1113 {
1114 int reg;
1115 u32 val;
1116 bool enabled;
1117
1118 reg = TRANSCONF(pipe);
1119 val = I915_READ(reg);
1120 enabled = !!(val & TRANS_ENABLE);
1121 WARN(enabled,
1122 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1123 pipe_name(pipe));
1124 }
1125
1126 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, u32 port_sel, u32 val)
1128 {
1129 if ((val & DP_PORT_EN) == 0)
1130 return false;
1131
1132 if (HAS_PCH_CPT(dev_priv->dev)) {
1133 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1134 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1135 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1136 return false;
1137 } else {
1138 if ((val & DP_PIPE_MASK) != (pipe << 30))
1139 return false;
1140 }
1141 return true;
1142 }
1143
1144 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, u32 val)
1146 {
1147 if ((val & PORT_ENABLE) == 0)
1148 return false;
1149
1150 if (HAS_PCH_CPT(dev_priv->dev)) {
1151 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1152 return false;
1153 } else {
1154 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1155 return false;
1156 }
1157 return true;
1158 }
1159
1160 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe, u32 val)
1162 {
1163 if ((val & LVDS_PORT_EN) == 0)
1164 return false;
1165
1166 if (HAS_PCH_CPT(dev_priv->dev)) {
1167 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1168 return false;
1169 } else {
1170 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1171 return false;
1172 }
1173 return true;
1174 }
1175
1176 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe, u32 val)
1178 {
1179 if ((val & ADPA_DAC_ENABLE) == 0)
1180 return false;
1181 if (HAS_PCH_CPT(dev_priv->dev)) {
1182 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1183 return false;
1184 } else {
1185 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1186 return false;
1187 }
1188 return true;
1189 }
1190
1191 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, int reg, u32 port_sel)
1193 {
1194 u32 val = I915_READ(reg);
1195 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1196 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1197 reg, pipe_name(pipe));
1198 }
1199
1200 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe, int reg)
1202 {
1203 u32 val = I915_READ(reg);
1204 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1205 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1206 reg, pipe_name(pipe));
1207 }
1208
1209 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211 {
1212 int reg;
1213 u32 val;
1214
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1216 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1217 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1218
1219 reg = PCH_ADPA;
1220 val = I915_READ(reg);
1221 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1222 "PCH VGA enabled on transcoder %c, should be disabled\n",
1223 pipe_name(pipe));
1224
1225 reg = PCH_LVDS;
1226 val = I915_READ(reg);
1227 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1228 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1229 pipe_name(pipe));
1230
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1232 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1233 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1234 }
1235
1236 /**
1237 * intel_enable_pll - enable a PLL
1238 * @dev_priv: i915 private structure
1239 * @pipe: pipe PLL to enable
1240 *
1241 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1242 * make sure the PLL reg is writable first though, since the panel write
1243 * protect mechanism may be enabled.
1244 *
1245 * Note! This is for pre-ILK only.
1246 */
1247 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1248 {
1249 int reg;
1250 u32 val;
1251
1252 /* No really, not for ILK+ */
1253 BUG_ON(dev_priv->info->gen >= 5);
1254
1255 /* PLL is protected by panel, make sure we can write it */
1256 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1257 assert_panel_unlocked(dev_priv, pipe);
1258
1259 reg = DPLL(pipe);
1260 val = I915_READ(reg);
1261 val |= DPLL_VCO_ENABLE;
1262
1263 /* We do this three times for luck */
1264 I915_WRITE(reg, val);
1265 POSTING_READ(reg);
1266 udelay(150); /* wait for warmup */
1267 I915_WRITE(reg, val);
1268 POSTING_READ(reg);
1269 udelay(150); /* wait for warmup */
1270 I915_WRITE(reg, val);
1271 POSTING_READ(reg);
1272 udelay(150); /* wait for warmup */
1273 }
1274
1275 /**
1276 * intel_disable_pll - disable a PLL
1277 * @dev_priv: i915 private structure
1278 * @pipe: pipe PLL to disable
1279 *
1280 * Disable the PLL for @pipe, making sure the pipe is off first.
1281 *
1282 * Note! This is for pre-ILK only.
1283 */
1284 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1285 {
1286 int reg;
1287 u32 val;
1288
1289 /* Don't disable pipe A or pipe A PLLs if needed */
1290 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1291 return;
1292
1293 /* Make sure the pipe isn't still relying on us */
1294 assert_pipe_disabled(dev_priv, pipe);
1295
1296 reg = DPLL(pipe);
1297 val = I915_READ(reg);
1298 val &= ~DPLL_VCO_ENABLE;
1299 I915_WRITE(reg, val);
1300 POSTING_READ(reg);
1301 }
1302
1303 /**
1304 * intel_enable_pch_pll - enable PCH PLL
1305 * @dev_priv: i915 private structure
1306 * @pipe: pipe PLL to enable
1307 *
1308 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1309 * drives the transcoder clock.
1310 */
1311 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1312 {
1313 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1314 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1315 int reg;
1316 u32 val;
1317
1318 /* PCH only available on ILK+ */
1319 BUG_ON(dev_priv->info->gen < 5);
1320 BUG_ON(pll == NULL);
1321 BUG_ON(pll->refcount == 0);
1322
1323 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1324 pll->pll_reg, pll->active, pll->on,
1325 intel_crtc->base.base.id);
1326
1327 /* PCH refclock must be enabled first */
1328 assert_pch_refclk_enabled(dev_priv);
1329
1330 if (pll->active++ && pll->on) {
1331 assert_pch_pll_enabled(dev_priv, intel_crtc);
1332 return;
1333 }
1334
1335 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1336
1337 reg = pll->pll_reg;
1338 val = I915_READ(reg);
1339 val |= DPLL_VCO_ENABLE;
1340 I915_WRITE(reg, val);
1341 POSTING_READ(reg);
1342 udelay(200);
1343
1344 pll->on = true;
1345 }
1346
1347 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1348 {
1349 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1350 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1351 int reg;
1352 u32 val;
1353
1354 /* PCH only available on ILK+ */
1355 BUG_ON(dev_priv->info->gen < 5);
1356 if (pll == NULL)
1357 return;
1358
1359 BUG_ON(pll->refcount == 0);
1360
1361 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1362 pll->pll_reg, pll->active, pll->on,
1363 intel_crtc->base.base.id);
1364
1365 BUG_ON(pll->active == 0);
1366 if (--pll->active) {
1367 assert_pch_pll_enabled(dev_priv, intel_crtc);
1368 return;
1369 }
1370
1371 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1372
1373 /* Make sure transcoder isn't still depending on us */
1374 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1375
1376 reg = pll->pll_reg;
1377 val = I915_READ(reg);
1378 val &= ~DPLL_VCO_ENABLE;
1379 I915_WRITE(reg, val);
1380 POSTING_READ(reg);
1381 udelay(200);
1382
1383 pll->on = false;
1384 }
1385
1386 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1387 enum pipe pipe)
1388 {
1389 int reg;
1390 u32 val, pipeconf_val;
1391 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1392
1393 /* PCH only available on ILK+ */
1394 BUG_ON(dev_priv->info->gen < 5);
1395
1396 /* Make sure PCH DPLL is enabled */
1397 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1398
1399 /* FDI must be feeding us bits for PCH ports */
1400 assert_fdi_tx_enabled(dev_priv, pipe);
1401 assert_fdi_rx_enabled(dev_priv, pipe);
1402
1403 reg = TRANSCONF(pipe);
1404 val = I915_READ(reg);
1405 pipeconf_val = I915_READ(PIPECONF(pipe));
1406
1407 if (HAS_PCH_IBX(dev_priv->dev)) {
1408 /*
1409 * make the BPC in transcoder be consistent with
1410 * that in pipeconf reg.
1411 */
1412 val &= ~PIPE_BPC_MASK;
1413 val |= pipeconf_val & PIPE_BPC_MASK;
1414 }
1415
1416 val &= ~TRANS_INTERLACE_MASK;
1417 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1418 if (HAS_PCH_IBX(dev_priv->dev) &&
1419 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1420 val |= TRANS_LEGACY_INTERLACED_ILK;
1421 else
1422 val |= TRANS_INTERLACED;
1423 else
1424 val |= TRANS_PROGRESSIVE;
1425
1426 I915_WRITE(reg, val | TRANS_ENABLE);
1427 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1428 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1429 }
1430
1431 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1432 enum pipe pipe)
1433 {
1434 int reg;
1435 u32 val;
1436
1437 /* FDI relies on the transcoder */
1438 assert_fdi_tx_disabled(dev_priv, pipe);
1439 assert_fdi_rx_disabled(dev_priv, pipe);
1440
1441 /* Ports must be off as well */
1442 assert_pch_ports_disabled(dev_priv, pipe);
1443
1444 reg = TRANSCONF(pipe);
1445 val = I915_READ(reg);
1446 val &= ~TRANS_ENABLE;
1447 I915_WRITE(reg, val);
1448 /* wait for PCH transcoder off, transcoder state */
1449 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1450 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1451 }
1452
1453 /**
1454 * intel_enable_pipe - enable a pipe, asserting requirements
1455 * @dev_priv: i915 private structure
1456 * @pipe: pipe to enable
1457 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1458 *
1459 * Enable @pipe, making sure that various hardware specific requirements
1460 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1461 *
1462 * @pipe should be %PIPE_A or %PIPE_B.
1463 *
1464 * Will wait until the pipe is actually running (i.e. first vblank) before
1465 * returning.
1466 */
1467 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1468 bool pch_port)
1469 {
1470 int reg;
1471 u32 val;
1472
1473 /*
1474 * A pipe without a PLL won't actually be able to drive bits from
1475 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1476 * need the check.
1477 */
1478 if (!HAS_PCH_SPLIT(dev_priv->dev))
1479 assert_pll_enabled(dev_priv, pipe);
1480 else {
1481 if (pch_port) {
1482 /* if driving the PCH, we need FDI enabled */
1483 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1484 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1485 }
1486 /* FIXME: assert CPU port conditions for SNB+ */
1487 }
1488
1489 reg = PIPECONF(pipe);
1490 val = I915_READ(reg);
1491 if (val & PIPECONF_ENABLE)
1492 return;
1493
1494 I915_WRITE(reg, val | PIPECONF_ENABLE);
1495 intel_wait_for_vblank(dev_priv->dev, pipe);
1496 }
1497
1498 /**
1499 * intel_disable_pipe - disable a pipe, asserting requirements
1500 * @dev_priv: i915 private structure
1501 * @pipe: pipe to disable
1502 *
1503 * Disable @pipe, making sure that various hardware specific requirements
1504 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1505 *
1506 * @pipe should be %PIPE_A or %PIPE_B.
1507 *
1508 * Will wait until the pipe has shut down before returning.
1509 */
1510 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1511 enum pipe pipe)
1512 {
1513 int reg;
1514 u32 val;
1515
1516 /*
1517 * Make sure planes won't keep trying to pump pixels to us,
1518 * or we might hang the display.
1519 */
1520 assert_planes_disabled(dev_priv, pipe);
1521
1522 /* Don't disable pipe A or pipe A PLLs if needed */
1523 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1524 return;
1525
1526 reg = PIPECONF(pipe);
1527 val = I915_READ(reg);
1528 if ((val & PIPECONF_ENABLE) == 0)
1529 return;
1530
1531 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1532 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1533 }
1534
1535 /*
1536 * Plane regs are double buffered, going from enabled->disabled needs a
1537 * trigger in order to latch. The display address reg provides this.
1538 */
1539 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1540 enum plane plane)
1541 {
1542 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1543 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1544 }
1545
1546 /**
1547 * intel_enable_plane - enable a display plane on a given pipe
1548 * @dev_priv: i915 private structure
1549 * @plane: plane to enable
1550 * @pipe: pipe being fed
1551 *
1552 * Enable @plane on @pipe, making sure that @pipe is running first.
1553 */
1554 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1555 enum plane plane, enum pipe pipe)
1556 {
1557 int reg;
1558 u32 val;
1559
1560 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1561 assert_pipe_enabled(dev_priv, pipe);
1562
1563 reg = DSPCNTR(plane);
1564 val = I915_READ(reg);
1565 if (val & DISPLAY_PLANE_ENABLE)
1566 return;
1567
1568 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1569 intel_flush_display_plane(dev_priv, plane);
1570 intel_wait_for_vblank(dev_priv->dev, pipe);
1571 }
1572
1573 /**
1574 * intel_disable_plane - disable a display plane
1575 * @dev_priv: i915 private structure
1576 * @plane: plane to disable
1577 * @pipe: pipe consuming the data
1578 *
1579 * Disable @plane; should be an independent operation.
1580 */
1581 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1582 enum plane plane, enum pipe pipe)
1583 {
1584 int reg;
1585 u32 val;
1586
1587 reg = DSPCNTR(plane);
1588 val = I915_READ(reg);
1589 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1590 return;
1591
1592 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1593 intel_flush_display_plane(dev_priv, plane);
1594 intel_wait_for_vblank(dev_priv->dev, pipe);
1595 }
1596
1597 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1598 enum pipe pipe, int reg, u32 port_sel)
1599 {
1600 u32 val = I915_READ(reg);
1601 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1602 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1603 I915_WRITE(reg, val & ~DP_PORT_EN);
1604 }
1605 }
1606
1607 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1608 enum pipe pipe, int reg)
1609 {
1610 u32 val = I915_READ(reg);
1611 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1612 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1613 reg, pipe);
1614 I915_WRITE(reg, val & ~PORT_ENABLE);
1615 }
1616 }
1617
1618 /* Disable any ports connected to this transcoder */
1619 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1620 enum pipe pipe)
1621 {
1622 u32 reg, val;
1623
1624 val = I915_READ(PCH_PP_CONTROL);
1625 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1626
1627 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1628 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1629 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1630
1631 reg = PCH_ADPA;
1632 val = I915_READ(reg);
1633 if (adpa_pipe_enabled(dev_priv, val, pipe))
1634 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1635
1636 reg = PCH_LVDS;
1637 val = I915_READ(reg);
1638 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1639 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1640 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1641 POSTING_READ(reg);
1642 udelay(100);
1643 }
1644
1645 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1646 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1647 disable_pch_hdmi(dev_priv, pipe, HDMID);
1648 }
1649
1650 int
1651 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1652 struct drm_i915_gem_object *obj,
1653 struct intel_ring_buffer *pipelined)
1654 {
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 u32 alignment;
1657 int ret;
1658
1659 switch (obj->tiling_mode) {
1660 case I915_TILING_NONE:
1661 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1662 alignment = 128 * 1024;
1663 else if (INTEL_INFO(dev)->gen >= 4)
1664 alignment = 4 * 1024;
1665 else
1666 alignment = 64 * 1024;
1667 break;
1668 case I915_TILING_X:
1669 /* pin() will align the object as required by fence */
1670 alignment = 0;
1671 break;
1672 case I915_TILING_Y:
1673 /* FIXME: Is this true? */
1674 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1675 return -EINVAL;
1676 default:
1677 BUG();
1678 }
1679
1680 dev_priv->mm.interruptible = false;
1681 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1682 if (ret)
1683 goto err_interruptible;
1684
1685 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1686 * fence, whereas 965+ only requires a fence if using
1687 * framebuffer compression. For simplicity, we always install
1688 * a fence as the cost is not that onerous.
1689 */
1690 ret = i915_gem_object_get_fence(obj);
1691 if (ret)
1692 goto err_unpin;
1693
1694 i915_gem_object_pin_fence(obj);
1695
1696 dev_priv->mm.interruptible = true;
1697 return 0;
1698
1699 err_unpin:
1700 i915_gem_object_unpin(obj);
1701 err_interruptible:
1702 dev_priv->mm.interruptible = true;
1703 return ret;
1704 }
1705
1706 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1707 {
1708 i915_gem_object_unpin_fence(obj);
1709 i915_gem_object_unpin(obj);
1710 }
1711
1712 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1713 int x, int y)
1714 {
1715 struct drm_device *dev = crtc->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1718 struct intel_framebuffer *intel_fb;
1719 struct drm_i915_gem_object *obj;
1720 int plane = intel_crtc->plane;
1721 unsigned long Start, Offset;
1722 u32 dspcntr;
1723 u32 reg;
1724
1725 switch (plane) {
1726 case 0:
1727 case 1:
1728 break;
1729 default:
1730 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1731 return -EINVAL;
1732 }
1733
1734 intel_fb = to_intel_framebuffer(fb);
1735 obj = intel_fb->obj;
1736
1737 reg = DSPCNTR(plane);
1738 dspcntr = I915_READ(reg);
1739 /* Mask out pixel format bits in case we change it */
1740 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1741 switch (fb->bits_per_pixel) {
1742 case 8:
1743 dspcntr |= DISPPLANE_8BPP;
1744 break;
1745 case 16:
1746 if (fb->depth == 15)
1747 dspcntr |= DISPPLANE_15_16BPP;
1748 else
1749 dspcntr |= DISPPLANE_16BPP;
1750 break;
1751 case 24:
1752 case 32:
1753 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1754 break;
1755 default:
1756 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1757 return -EINVAL;
1758 }
1759 if (INTEL_INFO(dev)->gen >= 4) {
1760 if (obj->tiling_mode != I915_TILING_NONE)
1761 dspcntr |= DISPPLANE_TILED;
1762 else
1763 dspcntr &= ~DISPPLANE_TILED;
1764 }
1765
1766 I915_WRITE(reg, dspcntr);
1767
1768 Start = obj->gtt_offset;
1769 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1770
1771 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1772 Start, Offset, x, y, fb->pitches[0]);
1773 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1774 if (INTEL_INFO(dev)->gen >= 4) {
1775 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1776 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1777 I915_WRITE(DSPADDR(plane), Offset);
1778 } else
1779 I915_WRITE(DSPADDR(plane), Start + Offset);
1780 POSTING_READ(reg);
1781
1782 return 0;
1783 }
1784
1785 static int ironlake_update_plane(struct drm_crtc *crtc,
1786 struct drm_framebuffer *fb, int x, int y)
1787 {
1788 struct drm_device *dev = crtc->dev;
1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791 struct intel_framebuffer *intel_fb;
1792 struct drm_i915_gem_object *obj;
1793 int plane = intel_crtc->plane;
1794 unsigned long Start, Offset;
1795 u32 dspcntr;
1796 u32 reg;
1797
1798 switch (plane) {
1799 case 0:
1800 case 1:
1801 case 2:
1802 break;
1803 default:
1804 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1805 return -EINVAL;
1806 }
1807
1808 intel_fb = to_intel_framebuffer(fb);
1809 obj = intel_fb->obj;
1810
1811 reg = DSPCNTR(plane);
1812 dspcntr = I915_READ(reg);
1813 /* Mask out pixel format bits in case we change it */
1814 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1815 switch (fb->bits_per_pixel) {
1816 case 8:
1817 dspcntr |= DISPPLANE_8BPP;
1818 break;
1819 case 16:
1820 if (fb->depth != 16)
1821 return -EINVAL;
1822
1823 dspcntr |= DISPPLANE_16BPP;
1824 break;
1825 case 24:
1826 case 32:
1827 if (fb->depth == 24)
1828 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1829 else if (fb->depth == 30)
1830 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1831 else
1832 return -EINVAL;
1833 break;
1834 default:
1835 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1836 return -EINVAL;
1837 }
1838
1839 if (obj->tiling_mode != I915_TILING_NONE)
1840 dspcntr |= DISPPLANE_TILED;
1841 else
1842 dspcntr &= ~DISPPLANE_TILED;
1843
1844 /* must disable */
1845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1846
1847 I915_WRITE(reg, dspcntr);
1848
1849 Start = obj->gtt_offset;
1850 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1851
1852 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1853 Start, Offset, x, y, fb->pitches[0]);
1854 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1855 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1856 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1857 I915_WRITE(DSPADDR(plane), Offset);
1858 POSTING_READ(reg);
1859
1860 return 0;
1861 }
1862
1863 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1864 static int
1865 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1866 int x, int y, enum mode_set_atomic state)
1867 {
1868 struct drm_device *dev = crtc->dev;
1869 struct drm_i915_private *dev_priv = dev->dev_private;
1870
1871 if (dev_priv->display.disable_fbc)
1872 dev_priv->display.disable_fbc(dev);
1873 intel_increase_pllclock(crtc);
1874
1875 return dev_priv->display.update_plane(crtc, fb, x, y);
1876 }
1877
1878 static int
1879 intel_finish_fb(struct drm_framebuffer *old_fb)
1880 {
1881 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1882 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1883 bool was_interruptible = dev_priv->mm.interruptible;
1884 int ret;
1885
1886 wait_event(dev_priv->pending_flip_queue,
1887 atomic_read(&dev_priv->mm.wedged) ||
1888 atomic_read(&obj->pending_flip) == 0);
1889
1890 /* Big Hammer, we also need to ensure that any pending
1891 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1892 * current scanout is retired before unpinning the old
1893 * framebuffer.
1894 *
1895 * This should only fail upon a hung GPU, in which case we
1896 * can safely continue.
1897 */
1898 dev_priv->mm.interruptible = false;
1899 ret = i915_gem_object_finish_gpu(obj);
1900 dev_priv->mm.interruptible = was_interruptible;
1901
1902 return ret;
1903 }
1904
1905 static int
1906 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1907 struct drm_framebuffer *old_fb)
1908 {
1909 struct drm_device *dev = crtc->dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct drm_i915_master_private *master_priv;
1912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1913 int ret;
1914
1915 /* no fb bound */
1916 if (!crtc->fb) {
1917 DRM_ERROR("No FB bound\n");
1918 return 0;
1919 }
1920
1921 switch (intel_crtc->plane) {
1922 case 0:
1923 case 1:
1924 break;
1925 case 2:
1926 if (IS_IVYBRIDGE(dev))
1927 break;
1928 /* fall through otherwise */
1929 default:
1930 DRM_ERROR("no plane for crtc\n");
1931 return -EINVAL;
1932 }
1933
1934 mutex_lock(&dev->struct_mutex);
1935 ret = intel_pin_and_fence_fb_obj(dev,
1936 to_intel_framebuffer(crtc->fb)->obj,
1937 NULL);
1938 if (ret != 0) {
1939 mutex_unlock(&dev->struct_mutex);
1940 DRM_ERROR("pin & fence failed\n");
1941 return ret;
1942 }
1943
1944 if (old_fb)
1945 intel_finish_fb(old_fb);
1946
1947 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
1948 if (ret) {
1949 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1950 mutex_unlock(&dev->struct_mutex);
1951 DRM_ERROR("failed to update base address\n");
1952 return ret;
1953 }
1954
1955 if (old_fb) {
1956 intel_wait_for_vblank(dev, intel_crtc->pipe);
1957 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1958 }
1959
1960 intel_update_fbc(dev);
1961 mutex_unlock(&dev->struct_mutex);
1962
1963 if (!dev->primary->master)
1964 return 0;
1965
1966 master_priv = dev->primary->master->driver_priv;
1967 if (!master_priv->sarea_priv)
1968 return 0;
1969
1970 if (intel_crtc->pipe) {
1971 master_priv->sarea_priv->pipeB_x = x;
1972 master_priv->sarea_priv->pipeB_y = y;
1973 } else {
1974 master_priv->sarea_priv->pipeA_x = x;
1975 master_priv->sarea_priv->pipeA_y = y;
1976 }
1977
1978 return 0;
1979 }
1980
1981 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1982 {
1983 struct drm_device *dev = crtc->dev;
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985 u32 dpa_ctl;
1986
1987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1988 dpa_ctl = I915_READ(DP_A);
1989 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1990
1991 if (clock < 200000) {
1992 u32 temp;
1993 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1994 /* workaround for 160Mhz:
1995 1) program 0x4600c bits 15:0 = 0x8124
1996 2) program 0x46010 bit 0 = 1
1997 3) program 0x46034 bit 24 = 1
1998 4) program 0x64000 bit 14 = 1
1999 */
2000 temp = I915_READ(0x4600c);
2001 temp &= 0xffff0000;
2002 I915_WRITE(0x4600c, temp | 0x8124);
2003
2004 temp = I915_READ(0x46010);
2005 I915_WRITE(0x46010, temp | 1);
2006
2007 temp = I915_READ(0x46034);
2008 I915_WRITE(0x46034, temp | (1 << 24));
2009 } else {
2010 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2011 }
2012 I915_WRITE(DP_A, dpa_ctl);
2013
2014 POSTING_READ(DP_A);
2015 udelay(500);
2016 }
2017
2018 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2019 {
2020 struct drm_device *dev = crtc->dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2023 int pipe = intel_crtc->pipe;
2024 u32 reg, temp;
2025
2026 /* enable normal train */
2027 reg = FDI_TX_CTL(pipe);
2028 temp = I915_READ(reg);
2029 if (IS_IVYBRIDGE(dev)) {
2030 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2031 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2032 } else {
2033 temp &= ~FDI_LINK_TRAIN_NONE;
2034 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2035 }
2036 I915_WRITE(reg, temp);
2037
2038 reg = FDI_RX_CTL(pipe);
2039 temp = I915_READ(reg);
2040 if (HAS_PCH_CPT(dev)) {
2041 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2042 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2043 } else {
2044 temp &= ~FDI_LINK_TRAIN_NONE;
2045 temp |= FDI_LINK_TRAIN_NONE;
2046 }
2047 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2048
2049 /* wait one idle pattern time */
2050 POSTING_READ(reg);
2051 udelay(1000);
2052
2053 /* IVB wants error correction enabled */
2054 if (IS_IVYBRIDGE(dev))
2055 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2056 FDI_FE_ERRC_ENABLE);
2057 }
2058
2059 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2060 {
2061 struct drm_i915_private *dev_priv = dev->dev_private;
2062 u32 flags = I915_READ(SOUTH_CHICKEN1);
2063
2064 flags |= FDI_PHASE_SYNC_OVR(pipe);
2065 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2066 flags |= FDI_PHASE_SYNC_EN(pipe);
2067 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2068 POSTING_READ(SOUTH_CHICKEN1);
2069 }
2070
2071 /* The FDI link training functions for ILK/Ibexpeak. */
2072 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2073 {
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077 int pipe = intel_crtc->pipe;
2078 int plane = intel_crtc->plane;
2079 u32 reg, temp, tries;
2080
2081 /* FDI needs bits from pipe & plane first */
2082 assert_pipe_enabled(dev_priv, pipe);
2083 assert_plane_enabled(dev_priv, plane);
2084
2085 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2086 for train result */
2087 reg = FDI_RX_IMR(pipe);
2088 temp = I915_READ(reg);
2089 temp &= ~FDI_RX_SYMBOL_LOCK;
2090 temp &= ~FDI_RX_BIT_LOCK;
2091 I915_WRITE(reg, temp);
2092 I915_READ(reg);
2093 udelay(150);
2094
2095 /* enable CPU FDI TX and PCH FDI RX */
2096 reg = FDI_TX_CTL(pipe);
2097 temp = I915_READ(reg);
2098 temp &= ~(7 << 19);
2099 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2100 temp &= ~FDI_LINK_TRAIN_NONE;
2101 temp |= FDI_LINK_TRAIN_PATTERN_1;
2102 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2103
2104 reg = FDI_RX_CTL(pipe);
2105 temp = I915_READ(reg);
2106 temp &= ~FDI_LINK_TRAIN_NONE;
2107 temp |= FDI_LINK_TRAIN_PATTERN_1;
2108 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2109
2110 POSTING_READ(reg);
2111 udelay(150);
2112
2113 /* Ironlake workaround, enable clock pointer after FDI enable*/
2114 if (HAS_PCH_IBX(dev)) {
2115 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2116 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2117 FDI_RX_PHASE_SYNC_POINTER_EN);
2118 }
2119
2120 reg = FDI_RX_IIR(pipe);
2121 for (tries = 0; tries < 5; tries++) {
2122 temp = I915_READ(reg);
2123 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2124
2125 if ((temp & FDI_RX_BIT_LOCK)) {
2126 DRM_DEBUG_KMS("FDI train 1 done.\n");
2127 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2128 break;
2129 }
2130 }
2131 if (tries == 5)
2132 DRM_ERROR("FDI train 1 fail!\n");
2133
2134 /* Train 2 */
2135 reg = FDI_TX_CTL(pipe);
2136 temp = I915_READ(reg);
2137 temp &= ~FDI_LINK_TRAIN_NONE;
2138 temp |= FDI_LINK_TRAIN_PATTERN_2;
2139 I915_WRITE(reg, temp);
2140
2141 reg = FDI_RX_CTL(pipe);
2142 temp = I915_READ(reg);
2143 temp &= ~FDI_LINK_TRAIN_NONE;
2144 temp |= FDI_LINK_TRAIN_PATTERN_2;
2145 I915_WRITE(reg, temp);
2146
2147 POSTING_READ(reg);
2148 udelay(150);
2149
2150 reg = FDI_RX_IIR(pipe);
2151 for (tries = 0; tries < 5; tries++) {
2152 temp = I915_READ(reg);
2153 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2154
2155 if (temp & FDI_RX_SYMBOL_LOCK) {
2156 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2157 DRM_DEBUG_KMS("FDI train 2 done.\n");
2158 break;
2159 }
2160 }
2161 if (tries == 5)
2162 DRM_ERROR("FDI train 2 fail!\n");
2163
2164 DRM_DEBUG_KMS("FDI train done\n");
2165
2166 }
2167
2168 static const int snb_b_fdi_train_param[] = {
2169 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2170 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2171 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2172 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2173 };
2174
2175 /* The FDI link training functions for SNB/Cougarpoint. */
2176 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2177 {
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 int pipe = intel_crtc->pipe;
2182 u32 reg, temp, i, retry;
2183
2184 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2185 for train result */
2186 reg = FDI_RX_IMR(pipe);
2187 temp = I915_READ(reg);
2188 temp &= ~FDI_RX_SYMBOL_LOCK;
2189 temp &= ~FDI_RX_BIT_LOCK;
2190 I915_WRITE(reg, temp);
2191
2192 POSTING_READ(reg);
2193 udelay(150);
2194
2195 /* enable CPU FDI TX and PCH FDI RX */
2196 reg = FDI_TX_CTL(pipe);
2197 temp = I915_READ(reg);
2198 temp &= ~(7 << 19);
2199 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2200 temp &= ~FDI_LINK_TRAIN_NONE;
2201 temp |= FDI_LINK_TRAIN_PATTERN_1;
2202 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2203 /* SNB-B */
2204 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2205 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2206
2207 reg = FDI_RX_CTL(pipe);
2208 temp = I915_READ(reg);
2209 if (HAS_PCH_CPT(dev)) {
2210 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2211 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2212 } else {
2213 temp &= ~FDI_LINK_TRAIN_NONE;
2214 temp |= FDI_LINK_TRAIN_PATTERN_1;
2215 }
2216 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2217
2218 POSTING_READ(reg);
2219 udelay(150);
2220
2221 if (HAS_PCH_CPT(dev))
2222 cpt_phase_pointer_enable(dev, pipe);
2223
2224 for (i = 0; i < 4; i++) {
2225 reg = FDI_TX_CTL(pipe);
2226 temp = I915_READ(reg);
2227 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2228 temp |= snb_b_fdi_train_param[i];
2229 I915_WRITE(reg, temp);
2230
2231 POSTING_READ(reg);
2232 udelay(500);
2233
2234 for (retry = 0; retry < 5; retry++) {
2235 reg = FDI_RX_IIR(pipe);
2236 temp = I915_READ(reg);
2237 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2238 if (temp & FDI_RX_BIT_LOCK) {
2239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2240 DRM_DEBUG_KMS("FDI train 1 done.\n");
2241 break;
2242 }
2243 udelay(50);
2244 }
2245 if (retry < 5)
2246 break;
2247 }
2248 if (i == 4)
2249 DRM_ERROR("FDI train 1 fail!\n");
2250
2251 /* Train 2 */
2252 reg = FDI_TX_CTL(pipe);
2253 temp = I915_READ(reg);
2254 temp &= ~FDI_LINK_TRAIN_NONE;
2255 temp |= FDI_LINK_TRAIN_PATTERN_2;
2256 if (IS_GEN6(dev)) {
2257 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2258 /* SNB-B */
2259 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2260 }
2261 I915_WRITE(reg, temp);
2262
2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2268 } else {
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_PATTERN_2;
2271 }
2272 I915_WRITE(reg, temp);
2273
2274 POSTING_READ(reg);
2275 udelay(150);
2276
2277 for (i = 0; i < 4; i++) {
2278 reg = FDI_TX_CTL(pipe);
2279 temp = I915_READ(reg);
2280 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2281 temp |= snb_b_fdi_train_param[i];
2282 I915_WRITE(reg, temp);
2283
2284 POSTING_READ(reg);
2285 udelay(500);
2286
2287 for (retry = 0; retry < 5; retry++) {
2288 reg = FDI_RX_IIR(pipe);
2289 temp = I915_READ(reg);
2290 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2291 if (temp & FDI_RX_SYMBOL_LOCK) {
2292 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2293 DRM_DEBUG_KMS("FDI train 2 done.\n");
2294 break;
2295 }
2296 udelay(50);
2297 }
2298 if (retry < 5)
2299 break;
2300 }
2301 if (i == 4)
2302 DRM_ERROR("FDI train 2 fail!\n");
2303
2304 DRM_DEBUG_KMS("FDI train done.\n");
2305 }
2306
2307 /* Manual link training for Ivy Bridge A0 parts */
2308 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2309 {
2310 struct drm_device *dev = crtc->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2313 int pipe = intel_crtc->pipe;
2314 u32 reg, temp, i;
2315
2316 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2317 for train result */
2318 reg = FDI_RX_IMR(pipe);
2319 temp = I915_READ(reg);
2320 temp &= ~FDI_RX_SYMBOL_LOCK;
2321 temp &= ~FDI_RX_BIT_LOCK;
2322 I915_WRITE(reg, temp);
2323
2324 POSTING_READ(reg);
2325 udelay(150);
2326
2327 /* enable CPU FDI TX and PCH FDI RX */
2328 reg = FDI_TX_CTL(pipe);
2329 temp = I915_READ(reg);
2330 temp &= ~(7 << 19);
2331 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2332 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2333 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2334 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2335 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2336 temp |= FDI_COMPOSITE_SYNC;
2337 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2338
2339 reg = FDI_RX_CTL(pipe);
2340 temp = I915_READ(reg);
2341 temp &= ~FDI_LINK_TRAIN_AUTO;
2342 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2343 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2344 temp |= FDI_COMPOSITE_SYNC;
2345 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2346
2347 POSTING_READ(reg);
2348 udelay(150);
2349
2350 if (HAS_PCH_CPT(dev))
2351 cpt_phase_pointer_enable(dev, pipe);
2352
2353 for (i = 0; i < 4; i++) {
2354 reg = FDI_TX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2357 temp |= snb_b_fdi_train_param[i];
2358 I915_WRITE(reg, temp);
2359
2360 POSTING_READ(reg);
2361 udelay(500);
2362
2363 reg = FDI_RX_IIR(pipe);
2364 temp = I915_READ(reg);
2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if (temp & FDI_RX_BIT_LOCK ||
2368 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2369 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2370 DRM_DEBUG_KMS("FDI train 1 done.\n");
2371 break;
2372 }
2373 }
2374 if (i == 4)
2375 DRM_ERROR("FDI train 1 fail!\n");
2376
2377 /* Train 2 */
2378 reg = FDI_TX_CTL(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2381 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2382 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2383 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2384 I915_WRITE(reg, temp);
2385
2386 reg = FDI_RX_CTL(pipe);
2387 temp = I915_READ(reg);
2388 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2389 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2390 I915_WRITE(reg, temp);
2391
2392 POSTING_READ(reg);
2393 udelay(150);
2394
2395 for (i = 0; i < 4; i++) {
2396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
2398 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2399 temp |= snb_b_fdi_train_param[i];
2400 I915_WRITE(reg, temp);
2401
2402 POSTING_READ(reg);
2403 udelay(500);
2404
2405 reg = FDI_RX_IIR(pipe);
2406 temp = I915_READ(reg);
2407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409 if (temp & FDI_RX_SYMBOL_LOCK) {
2410 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2411 DRM_DEBUG_KMS("FDI train 2 done.\n");
2412 break;
2413 }
2414 }
2415 if (i == 4)
2416 DRM_ERROR("FDI train 2 fail!\n");
2417
2418 DRM_DEBUG_KMS("FDI train done.\n");
2419 }
2420
2421 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2422 {
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
2427 u32 reg, temp;
2428
2429 /* Write the TU size bits so error detection works */
2430 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2431 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2432
2433 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2434 reg = FDI_RX_CTL(pipe);
2435 temp = I915_READ(reg);
2436 temp &= ~((0x7 << 19) | (0x7 << 16));
2437 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2438 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2439 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2440
2441 POSTING_READ(reg);
2442 udelay(200);
2443
2444 /* Switch from Rawclk to PCDclk */
2445 temp = I915_READ(reg);
2446 I915_WRITE(reg, temp | FDI_PCDCLK);
2447
2448 POSTING_READ(reg);
2449 udelay(200);
2450
2451 /* Enable CPU FDI TX PLL, always on for Ironlake */
2452 reg = FDI_TX_CTL(pipe);
2453 temp = I915_READ(reg);
2454 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2455 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2456
2457 POSTING_READ(reg);
2458 udelay(100);
2459 }
2460 }
2461
2462 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2463 {
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 u32 flags = I915_READ(SOUTH_CHICKEN1);
2466
2467 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2468 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2469 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2470 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2471 POSTING_READ(SOUTH_CHICKEN1);
2472 }
2473 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2474 {
2475 struct drm_device *dev = crtc->dev;
2476 struct drm_i915_private *dev_priv = dev->dev_private;
2477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2478 int pipe = intel_crtc->pipe;
2479 u32 reg, temp;
2480
2481 /* disable CPU FDI tx and PCH FDI rx */
2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
2484 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2485 POSTING_READ(reg);
2486
2487 reg = FDI_RX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~(0x7 << 16);
2490 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2491 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2492
2493 POSTING_READ(reg);
2494 udelay(100);
2495
2496 /* Ironlake workaround, disable clock pointer after downing FDI */
2497 if (HAS_PCH_IBX(dev)) {
2498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2499 I915_WRITE(FDI_RX_CHICKEN(pipe),
2500 I915_READ(FDI_RX_CHICKEN(pipe) &
2501 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2502 } else if (HAS_PCH_CPT(dev)) {
2503 cpt_phase_pointer_disable(dev, pipe);
2504 }
2505
2506 /* still set train pattern 1 */
2507 reg = FDI_TX_CTL(pipe);
2508 temp = I915_READ(reg);
2509 temp &= ~FDI_LINK_TRAIN_NONE;
2510 temp |= FDI_LINK_TRAIN_PATTERN_1;
2511 I915_WRITE(reg, temp);
2512
2513 reg = FDI_RX_CTL(pipe);
2514 temp = I915_READ(reg);
2515 if (HAS_PCH_CPT(dev)) {
2516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2517 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2518 } else {
2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_1;
2521 }
2522 /* BPC in FDI rx is consistent with that in PIPECONF */
2523 temp &= ~(0x07 << 16);
2524 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2525 I915_WRITE(reg, temp);
2526
2527 POSTING_READ(reg);
2528 udelay(100);
2529 }
2530
2531 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2532 {
2533 struct drm_device *dev = crtc->dev;
2534
2535 if (crtc->fb == NULL)
2536 return;
2537
2538 mutex_lock(&dev->struct_mutex);
2539 intel_finish_fb(crtc->fb);
2540 mutex_unlock(&dev->struct_mutex);
2541 }
2542
2543 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2544 {
2545 struct drm_device *dev = crtc->dev;
2546 struct drm_mode_config *mode_config = &dev->mode_config;
2547 struct intel_encoder *encoder;
2548
2549 /*
2550 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2551 * must be driven by its own crtc; no sharing is possible.
2552 */
2553 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2554 if (encoder->base.crtc != crtc)
2555 continue;
2556
2557 switch (encoder->type) {
2558 case INTEL_OUTPUT_EDP:
2559 if (!intel_encoder_is_pch_edp(&encoder->base))
2560 return false;
2561 continue;
2562 }
2563 }
2564
2565 return true;
2566 }
2567
2568 /*
2569 * Enable PCH resources required for PCH ports:
2570 * - PCH PLLs
2571 * - FDI training & RX/TX
2572 * - update transcoder timings
2573 * - DP transcoding bits
2574 * - transcoder
2575 */
2576 static void ironlake_pch_enable(struct drm_crtc *crtc)
2577 {
2578 struct drm_device *dev = crtc->dev;
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2581 int pipe = intel_crtc->pipe;
2582 u32 reg, temp;
2583
2584 /* For PCH output, training FDI link */
2585 dev_priv->display.fdi_link_train(crtc);
2586
2587 intel_enable_pch_pll(intel_crtc);
2588
2589 if (HAS_PCH_CPT(dev)) {
2590 u32 sel;
2591
2592 temp = I915_READ(PCH_DPLL_SEL);
2593 switch (pipe) {
2594 default:
2595 case 0:
2596 temp |= TRANSA_DPLL_ENABLE;
2597 sel = TRANSA_DPLLB_SEL;
2598 break;
2599 case 1:
2600 temp |= TRANSB_DPLL_ENABLE;
2601 sel = TRANSB_DPLLB_SEL;
2602 break;
2603 case 2:
2604 temp |= TRANSC_DPLL_ENABLE;
2605 sel = TRANSC_DPLLB_SEL;
2606 break;
2607 }
2608 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2609 temp |= sel;
2610 else
2611 temp &= ~sel;
2612 I915_WRITE(PCH_DPLL_SEL, temp);
2613 }
2614
2615 /* set transcoder timing, panel must allow it */
2616 assert_panel_unlocked(dev_priv, pipe);
2617 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2618 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2619 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2620
2621 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2622 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2623 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2624 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2625
2626 intel_fdi_normal_train(crtc);
2627
2628 /* For PCH DP, enable TRANS_DP_CTL */
2629 if (HAS_PCH_CPT(dev) &&
2630 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2631 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2632 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2633 reg = TRANS_DP_CTL(pipe);
2634 temp = I915_READ(reg);
2635 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2636 TRANS_DP_SYNC_MASK |
2637 TRANS_DP_BPC_MASK);
2638 temp |= (TRANS_DP_OUTPUT_ENABLE |
2639 TRANS_DP_ENH_FRAMING);
2640 temp |= bpc << 9; /* same format but at 11:9 */
2641
2642 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2643 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2644 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2645 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2646
2647 switch (intel_trans_dp_port_sel(crtc)) {
2648 case PCH_DP_B:
2649 temp |= TRANS_DP_PORT_SEL_B;
2650 break;
2651 case PCH_DP_C:
2652 temp |= TRANS_DP_PORT_SEL_C;
2653 break;
2654 case PCH_DP_D:
2655 temp |= TRANS_DP_PORT_SEL_D;
2656 break;
2657 default:
2658 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2659 temp |= TRANS_DP_PORT_SEL_B;
2660 break;
2661 }
2662
2663 I915_WRITE(reg, temp);
2664 }
2665
2666 intel_enable_transcoder(dev_priv, pipe);
2667 }
2668
2669 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2670 {
2671 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2672
2673 if (pll == NULL)
2674 return;
2675
2676 if (pll->refcount == 0) {
2677 WARN(1, "bad PCH PLL refcount\n");
2678 return;
2679 }
2680
2681 --pll->refcount;
2682 intel_crtc->pch_pll = NULL;
2683 }
2684
2685 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2686 {
2687 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2688 struct intel_pch_pll *pll;
2689 int i;
2690
2691 pll = intel_crtc->pch_pll;
2692 if (pll) {
2693 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2694 intel_crtc->base.base.id, pll->pll_reg);
2695 goto prepare;
2696 }
2697
2698 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2699 pll = &dev_priv->pch_plls[i];
2700
2701 /* Only want to check enabled timings first */
2702 if (pll->refcount == 0)
2703 continue;
2704
2705 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2706 fp == I915_READ(pll->fp0_reg)) {
2707 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2708 intel_crtc->base.base.id,
2709 pll->pll_reg, pll->refcount, pll->active);
2710
2711 goto found;
2712 }
2713 }
2714
2715 /* Ok no matching timings, maybe there's a free one? */
2716 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2717 pll = &dev_priv->pch_plls[i];
2718 if (pll->refcount == 0) {
2719 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2720 intel_crtc->base.base.id, pll->pll_reg);
2721 goto found;
2722 }
2723 }
2724
2725 return NULL;
2726
2727 found:
2728 intel_crtc->pch_pll = pll;
2729 pll->refcount++;
2730 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2731 prepare: /* separate function? */
2732 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2733 I915_WRITE(pll->fp0_reg, fp);
2734 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2735
2736 POSTING_READ(pll->pll_reg);
2737 udelay(150);
2738 pll->on = false;
2739 return pll;
2740 }
2741
2742 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2743 {
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2746 u32 temp;
2747
2748 temp = I915_READ(dslreg);
2749 udelay(500);
2750 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2751 /* Without this, mode sets may fail silently on FDI */
2752 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2753 udelay(250);
2754 I915_WRITE(tc2reg, 0);
2755 if (wait_for(I915_READ(dslreg) != temp, 5))
2756 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2757 }
2758 }
2759
2760 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2761 {
2762 struct drm_device *dev = crtc->dev;
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2765 int pipe = intel_crtc->pipe;
2766 int plane = intel_crtc->plane;
2767 u32 temp;
2768 bool is_pch_port;
2769
2770 if (intel_crtc->active)
2771 return;
2772
2773 intel_crtc->active = true;
2774 intel_update_watermarks(dev);
2775
2776 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2777 temp = I915_READ(PCH_LVDS);
2778 if ((temp & LVDS_PORT_EN) == 0)
2779 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2780 }
2781
2782 is_pch_port = intel_crtc_driving_pch(crtc);
2783
2784 if (is_pch_port)
2785 ironlake_fdi_pll_enable(crtc);
2786 else
2787 ironlake_fdi_disable(crtc);
2788
2789 /* Enable panel fitting for LVDS */
2790 if (dev_priv->pch_pf_size &&
2791 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2792 /* Force use of hard-coded filter coefficients
2793 * as some pre-programmed values are broken,
2794 * e.g. x201.
2795 */
2796 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2797 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2798 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2799 }
2800
2801 /*
2802 * On ILK+ LUT must be loaded before the pipe is running but with
2803 * clocks enabled
2804 */
2805 intel_crtc_load_lut(crtc);
2806
2807 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2808 intel_enable_plane(dev_priv, plane, pipe);
2809
2810 if (is_pch_port)
2811 ironlake_pch_enable(crtc);
2812
2813 mutex_lock(&dev->struct_mutex);
2814 intel_update_fbc(dev);
2815 mutex_unlock(&dev->struct_mutex);
2816
2817 intel_crtc_update_cursor(crtc, true);
2818 }
2819
2820 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2821 {
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 int plane = intel_crtc->plane;
2827 u32 reg, temp;
2828
2829 if (!intel_crtc->active)
2830 return;
2831
2832 intel_crtc_wait_for_pending_flips(crtc);
2833 drm_vblank_off(dev, pipe);
2834 intel_crtc_update_cursor(crtc, false);
2835
2836 intel_disable_plane(dev_priv, plane, pipe);
2837
2838 if (dev_priv->cfb_plane == plane)
2839 intel_disable_fbc(dev);
2840
2841 intel_disable_pipe(dev_priv, pipe);
2842
2843 /* Disable PF */
2844 I915_WRITE(PF_CTL(pipe), 0);
2845 I915_WRITE(PF_WIN_SZ(pipe), 0);
2846
2847 ironlake_fdi_disable(crtc);
2848
2849 /* This is a horrible layering violation; we should be doing this in
2850 * the connector/encoder ->prepare instead, but we don't always have
2851 * enough information there about the config to know whether it will
2852 * actually be necessary or just cause undesired flicker.
2853 */
2854 intel_disable_pch_ports(dev_priv, pipe);
2855
2856 intel_disable_transcoder(dev_priv, pipe);
2857
2858 if (HAS_PCH_CPT(dev)) {
2859 /* disable TRANS_DP_CTL */
2860 reg = TRANS_DP_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2863 temp |= TRANS_DP_PORT_SEL_NONE;
2864 I915_WRITE(reg, temp);
2865
2866 /* disable DPLL_SEL */
2867 temp = I915_READ(PCH_DPLL_SEL);
2868 switch (pipe) {
2869 case 0:
2870 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2871 break;
2872 case 1:
2873 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2874 break;
2875 case 2:
2876 /* C shares PLL A or B */
2877 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2878 break;
2879 default:
2880 BUG(); /* wtf */
2881 }
2882 I915_WRITE(PCH_DPLL_SEL, temp);
2883 }
2884
2885 /* disable PCH DPLL */
2886 intel_disable_pch_pll(intel_crtc);
2887
2888 /* Switch from PCDclk to Rawclk */
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2892
2893 /* Disable CPU FDI TX PLL */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2897
2898 POSTING_READ(reg);
2899 udelay(100);
2900
2901 reg = FDI_RX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2904
2905 /* Wait for the clocks to turn off. */
2906 POSTING_READ(reg);
2907 udelay(100);
2908
2909 intel_crtc->active = false;
2910 intel_update_watermarks(dev);
2911
2912 mutex_lock(&dev->struct_mutex);
2913 intel_update_fbc(dev);
2914 mutex_unlock(&dev->struct_mutex);
2915 }
2916
2917 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2918 {
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 int pipe = intel_crtc->pipe;
2921 int plane = intel_crtc->plane;
2922
2923 /* XXX: When our outputs are all unaware of DPMS modes other than off
2924 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2925 */
2926 switch (mode) {
2927 case DRM_MODE_DPMS_ON:
2928 case DRM_MODE_DPMS_STANDBY:
2929 case DRM_MODE_DPMS_SUSPEND:
2930 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2931 ironlake_crtc_enable(crtc);
2932 break;
2933
2934 case DRM_MODE_DPMS_OFF:
2935 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2936 ironlake_crtc_disable(crtc);
2937 break;
2938 }
2939 }
2940
2941 static void ironlake_crtc_off(struct drm_crtc *crtc)
2942 {
2943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2944 intel_put_pch_pll(intel_crtc);
2945 }
2946
2947 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2948 {
2949 if (!enable && intel_crtc->overlay) {
2950 struct drm_device *dev = intel_crtc->base.dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952
2953 mutex_lock(&dev->struct_mutex);
2954 dev_priv->mm.interruptible = false;
2955 (void) intel_overlay_switch_off(intel_crtc->overlay);
2956 dev_priv->mm.interruptible = true;
2957 mutex_unlock(&dev->struct_mutex);
2958 }
2959
2960 /* Let userspace switch the overlay on again. In most cases userspace
2961 * has to recompute where to put it anyway.
2962 */
2963 }
2964
2965 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2966 {
2967 struct drm_device *dev = crtc->dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2970 int pipe = intel_crtc->pipe;
2971 int plane = intel_crtc->plane;
2972
2973 if (intel_crtc->active)
2974 return;
2975
2976 intel_crtc->active = true;
2977 intel_update_watermarks(dev);
2978
2979 intel_enable_pll(dev_priv, pipe);
2980 intel_enable_pipe(dev_priv, pipe, false);
2981 intel_enable_plane(dev_priv, plane, pipe);
2982
2983 intel_crtc_load_lut(crtc);
2984 intel_update_fbc(dev);
2985
2986 /* Give the overlay scaler a chance to enable if it's on this pipe */
2987 intel_crtc_dpms_overlay(intel_crtc, true);
2988 intel_crtc_update_cursor(crtc, true);
2989 }
2990
2991 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2992 {
2993 struct drm_device *dev = crtc->dev;
2994 struct drm_i915_private *dev_priv = dev->dev_private;
2995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2996 int pipe = intel_crtc->pipe;
2997 int plane = intel_crtc->plane;
2998
2999 if (!intel_crtc->active)
3000 return;
3001
3002 /* Give the overlay scaler a chance to disable if it's on this pipe */
3003 intel_crtc_wait_for_pending_flips(crtc);
3004 drm_vblank_off(dev, pipe);
3005 intel_crtc_dpms_overlay(intel_crtc, false);
3006 intel_crtc_update_cursor(crtc, false);
3007
3008 if (dev_priv->cfb_plane == plane)
3009 intel_disable_fbc(dev);
3010
3011 intel_disable_plane(dev_priv, plane, pipe);
3012 intel_disable_pipe(dev_priv, pipe);
3013 intel_disable_pll(dev_priv, pipe);
3014
3015 intel_crtc->active = false;
3016 intel_update_fbc(dev);
3017 intel_update_watermarks(dev);
3018 }
3019
3020 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3021 {
3022 /* XXX: When our outputs are all unaware of DPMS modes other than off
3023 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3024 */
3025 switch (mode) {
3026 case DRM_MODE_DPMS_ON:
3027 case DRM_MODE_DPMS_STANDBY:
3028 case DRM_MODE_DPMS_SUSPEND:
3029 i9xx_crtc_enable(crtc);
3030 break;
3031 case DRM_MODE_DPMS_OFF:
3032 i9xx_crtc_disable(crtc);
3033 break;
3034 }
3035 }
3036
3037 static void i9xx_crtc_off(struct drm_crtc *crtc)
3038 {
3039 }
3040
3041 /**
3042 * Sets the power management mode of the pipe and plane.
3043 */
3044 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3045 {
3046 struct drm_device *dev = crtc->dev;
3047 struct drm_i915_private *dev_priv = dev->dev_private;
3048 struct drm_i915_master_private *master_priv;
3049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3050 int pipe = intel_crtc->pipe;
3051 bool enabled;
3052
3053 if (intel_crtc->dpms_mode == mode)
3054 return;
3055
3056 intel_crtc->dpms_mode = mode;
3057
3058 dev_priv->display.dpms(crtc, mode);
3059
3060 if (!dev->primary->master)
3061 return;
3062
3063 master_priv = dev->primary->master->driver_priv;
3064 if (!master_priv->sarea_priv)
3065 return;
3066
3067 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3068
3069 switch (pipe) {
3070 case 0:
3071 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3072 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3073 break;
3074 case 1:
3075 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3076 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3077 break;
3078 default:
3079 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3080 break;
3081 }
3082 }
3083
3084 static void intel_crtc_disable(struct drm_crtc *crtc)
3085 {
3086 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3087 struct drm_device *dev = crtc->dev;
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089
3090 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3091 dev_priv->display.off(crtc);
3092
3093 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3094 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3095
3096 if (crtc->fb) {
3097 mutex_lock(&dev->struct_mutex);
3098 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3099 mutex_unlock(&dev->struct_mutex);
3100 }
3101 }
3102
3103 /* Prepare for a mode set.
3104 *
3105 * Note we could be a lot smarter here. We need to figure out which outputs
3106 * will be enabled, which disabled (in short, how the config will changes)
3107 * and perform the minimum necessary steps to accomplish that, e.g. updating
3108 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3109 * panel fitting is in the proper state, etc.
3110 */
3111 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3112 {
3113 i9xx_crtc_disable(crtc);
3114 }
3115
3116 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3117 {
3118 i9xx_crtc_enable(crtc);
3119 }
3120
3121 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3122 {
3123 ironlake_crtc_disable(crtc);
3124 }
3125
3126 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3127 {
3128 ironlake_crtc_enable(crtc);
3129 }
3130
3131 void intel_encoder_prepare(struct drm_encoder *encoder)
3132 {
3133 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3134 /* lvds has its own version of prepare see intel_lvds_prepare */
3135 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3136 }
3137
3138 void intel_encoder_commit(struct drm_encoder *encoder)
3139 {
3140 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3141 struct drm_device *dev = encoder->dev;
3142 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3143 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3144
3145 /* lvds has its own version of commit see intel_lvds_commit */
3146 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3147
3148 if (HAS_PCH_CPT(dev))
3149 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3150 }
3151
3152 void intel_encoder_destroy(struct drm_encoder *encoder)
3153 {
3154 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3155
3156 drm_encoder_cleanup(encoder);
3157 kfree(intel_encoder);
3158 }
3159
3160 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3161 struct drm_display_mode *mode,
3162 struct drm_display_mode *adjusted_mode)
3163 {
3164 struct drm_device *dev = crtc->dev;
3165
3166 if (HAS_PCH_SPLIT(dev)) {
3167 /* FDI link clock is fixed at 2.7G */
3168 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3169 return false;
3170 }
3171
3172 /* All interlaced capable intel hw wants timings in frames. */
3173 drm_mode_set_crtcinfo(adjusted_mode, 0);
3174
3175 return true;
3176 }
3177
3178 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3179 {
3180 return 400000; /* FIXME */
3181 }
3182
3183 static int i945_get_display_clock_speed(struct drm_device *dev)
3184 {
3185 return 400000;
3186 }
3187
3188 static int i915_get_display_clock_speed(struct drm_device *dev)
3189 {
3190 return 333000;
3191 }
3192
3193 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3194 {
3195 return 200000;
3196 }
3197
3198 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3199 {
3200 u16 gcfgc = 0;
3201
3202 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3203
3204 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3205 return 133000;
3206 else {
3207 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3208 case GC_DISPLAY_CLOCK_333_MHZ:
3209 return 333000;
3210 default:
3211 case GC_DISPLAY_CLOCK_190_200_MHZ:
3212 return 190000;
3213 }
3214 }
3215 }
3216
3217 static int i865_get_display_clock_speed(struct drm_device *dev)
3218 {
3219 return 266000;
3220 }
3221
3222 static int i855_get_display_clock_speed(struct drm_device *dev)
3223 {
3224 u16 hpllcc = 0;
3225 /* Assume that the hardware is in the high speed state. This
3226 * should be the default.
3227 */
3228 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3229 case GC_CLOCK_133_200:
3230 case GC_CLOCK_100_200:
3231 return 200000;
3232 case GC_CLOCK_166_250:
3233 return 250000;
3234 case GC_CLOCK_100_133:
3235 return 133000;
3236 }
3237
3238 /* Shouldn't happen */
3239 return 0;
3240 }
3241
3242 static int i830_get_display_clock_speed(struct drm_device *dev)
3243 {
3244 return 133000;
3245 }
3246
3247 struct fdi_m_n {
3248 u32 tu;
3249 u32 gmch_m;
3250 u32 gmch_n;
3251 u32 link_m;
3252 u32 link_n;
3253 };
3254
3255 static void
3256 fdi_reduce_ratio(u32 *num, u32 *den)
3257 {
3258 while (*num > 0xffffff || *den > 0xffffff) {
3259 *num >>= 1;
3260 *den >>= 1;
3261 }
3262 }
3263
3264 static void
3265 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3266 int link_clock, struct fdi_m_n *m_n)
3267 {
3268 m_n->tu = 64; /* default size */
3269
3270 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3271 m_n->gmch_m = bits_per_pixel * pixel_clock;
3272 m_n->gmch_n = link_clock * nlanes * 8;
3273 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3274
3275 m_n->link_m = pixel_clock;
3276 m_n->link_n = link_clock;
3277 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3278 }
3279
3280 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3281 {
3282 if (i915_panel_use_ssc >= 0)
3283 return i915_panel_use_ssc != 0;
3284 return dev_priv->lvds_use_ssc
3285 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3286 }
3287
3288 /**
3289 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3290 * @crtc: CRTC structure
3291 * @mode: requested mode
3292 *
3293 * A pipe may be connected to one or more outputs. Based on the depth of the
3294 * attached framebuffer, choose a good color depth to use on the pipe.
3295 *
3296 * If possible, match the pipe depth to the fb depth. In some cases, this
3297 * isn't ideal, because the connected output supports a lesser or restricted
3298 * set of depths. Resolve that here:
3299 * LVDS typically supports only 6bpc, so clamp down in that case
3300 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3301 * Displays may support a restricted set as well, check EDID and clamp as
3302 * appropriate.
3303 * DP may want to dither down to 6bpc to fit larger modes
3304 *
3305 * RETURNS:
3306 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3307 * true if they don't match).
3308 */
3309 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3310 unsigned int *pipe_bpp,
3311 struct drm_display_mode *mode)
3312 {
3313 struct drm_device *dev = crtc->dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 struct drm_encoder *encoder;
3316 struct drm_connector *connector;
3317 unsigned int display_bpc = UINT_MAX, bpc;
3318
3319 /* Walk the encoders & connectors on this crtc, get min bpc */
3320 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3321 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3322
3323 if (encoder->crtc != crtc)
3324 continue;
3325
3326 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3327 unsigned int lvds_bpc;
3328
3329 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3330 LVDS_A3_POWER_UP)
3331 lvds_bpc = 8;
3332 else
3333 lvds_bpc = 6;
3334
3335 if (lvds_bpc < display_bpc) {
3336 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3337 display_bpc = lvds_bpc;
3338 }
3339 continue;
3340 }
3341
3342 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3343 /* Use VBT settings if we have an eDP panel */
3344 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3345
3346 if (edp_bpc < display_bpc) {
3347 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3348 display_bpc = edp_bpc;
3349 }
3350 continue;
3351 }
3352
3353 /* Not one of the known troublemakers, check the EDID */
3354 list_for_each_entry(connector, &dev->mode_config.connector_list,
3355 head) {
3356 if (connector->encoder != encoder)
3357 continue;
3358
3359 /* Don't use an invalid EDID bpc value */
3360 if (connector->display_info.bpc &&
3361 connector->display_info.bpc < display_bpc) {
3362 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3363 display_bpc = connector->display_info.bpc;
3364 }
3365 }
3366
3367 /*
3368 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3369 * through, clamp it down. (Note: >12bpc will be caught below.)
3370 */
3371 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3372 if (display_bpc > 8 && display_bpc < 12) {
3373 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3374 display_bpc = 12;
3375 } else {
3376 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3377 display_bpc = 8;
3378 }
3379 }
3380 }
3381
3382 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3383 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3384 display_bpc = 6;
3385 }
3386
3387 /*
3388 * We could just drive the pipe at the highest bpc all the time and
3389 * enable dithering as needed, but that costs bandwidth. So choose
3390 * the minimum value that expresses the full color range of the fb but
3391 * also stays within the max display bpc discovered above.
3392 */
3393
3394 switch (crtc->fb->depth) {
3395 case 8:
3396 bpc = 8; /* since we go through a colormap */
3397 break;
3398 case 15:
3399 case 16:
3400 bpc = 6; /* min is 18bpp */
3401 break;
3402 case 24:
3403 bpc = 8;
3404 break;
3405 case 30:
3406 bpc = 10;
3407 break;
3408 case 48:
3409 bpc = 12;
3410 break;
3411 default:
3412 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3413 bpc = min((unsigned int)8, display_bpc);
3414 break;
3415 }
3416
3417 display_bpc = min(display_bpc, bpc);
3418
3419 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3420 bpc, display_bpc);
3421
3422 *pipe_bpp = display_bpc * 3;
3423
3424 return display_bpc != bpc;
3425 }
3426
3427 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3428 {
3429 struct drm_device *dev = crtc->dev;
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3431 int refclk;
3432
3433 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3434 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3435 refclk = dev_priv->lvds_ssc_freq * 1000;
3436 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3437 refclk / 1000);
3438 } else if (!IS_GEN2(dev)) {
3439 refclk = 96000;
3440 } else {
3441 refclk = 48000;
3442 }
3443
3444 return refclk;
3445 }
3446
3447 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3448 intel_clock_t *clock)
3449 {
3450 /* SDVO TV has fixed PLL values depend on its clock range,
3451 this mirrors vbios setting. */
3452 if (adjusted_mode->clock >= 100000
3453 && adjusted_mode->clock < 140500) {
3454 clock->p1 = 2;
3455 clock->p2 = 10;
3456 clock->n = 3;
3457 clock->m1 = 16;
3458 clock->m2 = 8;
3459 } else if (adjusted_mode->clock >= 140500
3460 && adjusted_mode->clock <= 200000) {
3461 clock->p1 = 1;
3462 clock->p2 = 10;
3463 clock->n = 6;
3464 clock->m1 = 12;
3465 clock->m2 = 8;
3466 }
3467 }
3468
3469 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3470 intel_clock_t *clock,
3471 intel_clock_t *reduced_clock)
3472 {
3473 struct drm_device *dev = crtc->dev;
3474 struct drm_i915_private *dev_priv = dev->dev_private;
3475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3476 int pipe = intel_crtc->pipe;
3477 u32 fp, fp2 = 0;
3478
3479 if (IS_PINEVIEW(dev)) {
3480 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3481 if (reduced_clock)
3482 fp2 = (1 << reduced_clock->n) << 16 |
3483 reduced_clock->m1 << 8 | reduced_clock->m2;
3484 } else {
3485 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3486 if (reduced_clock)
3487 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3488 reduced_clock->m2;
3489 }
3490
3491 I915_WRITE(FP0(pipe), fp);
3492
3493 intel_crtc->lowfreq_avail = false;
3494 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3495 reduced_clock && i915_powersave) {
3496 I915_WRITE(FP1(pipe), fp2);
3497 intel_crtc->lowfreq_avail = true;
3498 } else {
3499 I915_WRITE(FP1(pipe), fp);
3500 }
3501 }
3502
3503 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3504 struct drm_display_mode *adjusted_mode)
3505 {
3506 struct drm_device *dev = crtc->dev;
3507 struct drm_i915_private *dev_priv = dev->dev_private;
3508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509 int pipe = intel_crtc->pipe;
3510 u32 temp;
3511
3512 temp = I915_READ(LVDS);
3513 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3514 if (pipe == 1) {
3515 temp |= LVDS_PIPEB_SELECT;
3516 } else {
3517 temp &= ~LVDS_PIPEB_SELECT;
3518 }
3519 /* set the corresponsding LVDS_BORDER bit */
3520 temp |= dev_priv->lvds_border_bits;
3521 /* Set the B0-B3 data pairs corresponding to whether we're going to
3522 * set the DPLLs for dual-channel mode or not.
3523 */
3524 if (clock->p2 == 7)
3525 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3526 else
3527 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3528
3529 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3530 * appropriately here, but we need to look more thoroughly into how
3531 * panels behave in the two modes.
3532 */
3533 /* set the dithering flag on LVDS as needed */
3534 if (INTEL_INFO(dev)->gen >= 4) {
3535 if (dev_priv->lvds_dither)
3536 temp |= LVDS_ENABLE_DITHER;
3537 else
3538 temp &= ~LVDS_ENABLE_DITHER;
3539 }
3540 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3541 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3542 temp |= LVDS_HSYNC_POLARITY;
3543 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3544 temp |= LVDS_VSYNC_POLARITY;
3545 I915_WRITE(LVDS, temp);
3546 }
3547
3548 static void i9xx_update_pll(struct drm_crtc *crtc,
3549 struct drm_display_mode *mode,
3550 struct drm_display_mode *adjusted_mode,
3551 intel_clock_t *clock, intel_clock_t *reduced_clock,
3552 int num_connectors)
3553 {
3554 struct drm_device *dev = crtc->dev;
3555 struct drm_i915_private *dev_priv = dev->dev_private;
3556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557 int pipe = intel_crtc->pipe;
3558 u32 dpll;
3559 bool is_sdvo;
3560
3561 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3562 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3563
3564 dpll = DPLL_VGA_MODE_DIS;
3565
3566 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3567 dpll |= DPLLB_MODE_LVDS;
3568 else
3569 dpll |= DPLLB_MODE_DAC_SERIAL;
3570 if (is_sdvo) {
3571 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3572 if (pixel_multiplier > 1) {
3573 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3574 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3575 }
3576 dpll |= DPLL_DVO_HIGH_SPEED;
3577 }
3578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3579 dpll |= DPLL_DVO_HIGH_SPEED;
3580
3581 /* compute bitmask from p1 value */
3582 if (IS_PINEVIEW(dev))
3583 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3584 else {
3585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3586 if (IS_G4X(dev) && reduced_clock)
3587 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3588 }
3589 switch (clock->p2) {
3590 case 5:
3591 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3592 break;
3593 case 7:
3594 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3595 break;
3596 case 10:
3597 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3598 break;
3599 case 14:
3600 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3601 break;
3602 }
3603 if (INTEL_INFO(dev)->gen >= 4)
3604 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3605
3606 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3607 dpll |= PLL_REF_INPUT_TVCLKINBC;
3608 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3609 /* XXX: just matching BIOS for now */
3610 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3611 dpll |= 3;
3612 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3613 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3614 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3615 else
3616 dpll |= PLL_REF_INPUT_DREFCLK;
3617
3618 dpll |= DPLL_VCO_ENABLE;
3619 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3620 POSTING_READ(DPLL(pipe));
3621 udelay(150);
3622
3623 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3624 * This is an exception to the general rule that mode_set doesn't turn
3625 * things on.
3626 */
3627 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3628 intel_update_lvds(crtc, clock, adjusted_mode);
3629
3630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3631 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3632
3633 I915_WRITE(DPLL(pipe), dpll);
3634
3635 /* Wait for the clocks to stabilize. */
3636 POSTING_READ(DPLL(pipe));
3637 udelay(150);
3638
3639 if (INTEL_INFO(dev)->gen >= 4) {
3640 u32 temp = 0;
3641 if (is_sdvo) {
3642 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3643 if (temp > 1)
3644 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3645 else
3646 temp = 0;
3647 }
3648 I915_WRITE(DPLL_MD(pipe), temp);
3649 } else {
3650 /* The pixel multiplier can only be updated once the
3651 * DPLL is enabled and the clocks are stable.
3652 *
3653 * So write it again.
3654 */
3655 I915_WRITE(DPLL(pipe), dpll);
3656 }
3657 }
3658
3659 static void i8xx_update_pll(struct drm_crtc *crtc,
3660 struct drm_display_mode *adjusted_mode,
3661 intel_clock_t *clock,
3662 int num_connectors)
3663 {
3664 struct drm_device *dev = crtc->dev;
3665 struct drm_i915_private *dev_priv = dev->dev_private;
3666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3667 int pipe = intel_crtc->pipe;
3668 u32 dpll;
3669
3670 dpll = DPLL_VGA_MODE_DIS;
3671
3672 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3673 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3674 } else {
3675 if (clock->p1 == 2)
3676 dpll |= PLL_P1_DIVIDE_BY_TWO;
3677 else
3678 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3679 if (clock->p2 == 4)
3680 dpll |= PLL_P2_DIVIDE_BY_4;
3681 }
3682
3683 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3684 /* XXX: just matching BIOS for now */
3685 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3686 dpll |= 3;
3687 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3688 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3689 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3690 else
3691 dpll |= PLL_REF_INPUT_DREFCLK;
3692
3693 dpll |= DPLL_VCO_ENABLE;
3694 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3695 POSTING_READ(DPLL(pipe));
3696 udelay(150);
3697
3698 I915_WRITE(DPLL(pipe), dpll);
3699
3700 /* Wait for the clocks to stabilize. */
3701 POSTING_READ(DPLL(pipe));
3702 udelay(150);
3703
3704 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3705 * This is an exception to the general rule that mode_set doesn't turn
3706 * things on.
3707 */
3708 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3709 intel_update_lvds(crtc, clock, adjusted_mode);
3710
3711 /* The pixel multiplier can only be updated once the
3712 * DPLL is enabled and the clocks are stable.
3713 *
3714 * So write it again.
3715 */
3716 I915_WRITE(DPLL(pipe), dpll);
3717 }
3718
3719 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3720 struct drm_display_mode *mode,
3721 struct drm_display_mode *adjusted_mode,
3722 int x, int y,
3723 struct drm_framebuffer *old_fb)
3724 {
3725 struct drm_device *dev = crtc->dev;
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728 int pipe = intel_crtc->pipe;
3729 int plane = intel_crtc->plane;
3730 int refclk, num_connectors = 0;
3731 intel_clock_t clock, reduced_clock;
3732 u32 dspcntr, pipeconf, vsyncshift;
3733 bool ok, has_reduced_clock = false, is_sdvo = false;
3734 bool is_lvds = false, is_tv = false, is_dp = false;
3735 struct drm_mode_config *mode_config = &dev->mode_config;
3736 struct intel_encoder *encoder;
3737 const intel_limit_t *limit;
3738 int ret;
3739
3740 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3741 if (encoder->base.crtc != crtc)
3742 continue;
3743
3744 switch (encoder->type) {
3745 case INTEL_OUTPUT_LVDS:
3746 is_lvds = true;
3747 break;
3748 case INTEL_OUTPUT_SDVO:
3749 case INTEL_OUTPUT_HDMI:
3750 is_sdvo = true;
3751 if (encoder->needs_tv_clock)
3752 is_tv = true;
3753 break;
3754 case INTEL_OUTPUT_TVOUT:
3755 is_tv = true;
3756 break;
3757 case INTEL_OUTPUT_DISPLAYPORT:
3758 is_dp = true;
3759 break;
3760 }
3761
3762 num_connectors++;
3763 }
3764
3765 refclk = i9xx_get_refclk(crtc, num_connectors);
3766
3767 /*
3768 * Returns a set of divisors for the desired target clock with the given
3769 * refclk, or FALSE. The returned values represent the clock equation:
3770 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3771 */
3772 limit = intel_limit(crtc, refclk);
3773 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3774 &clock);
3775 if (!ok) {
3776 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3777 return -EINVAL;
3778 }
3779
3780 /* Ensure that the cursor is valid for the new mode before changing... */
3781 intel_crtc_update_cursor(crtc, true);
3782
3783 if (is_lvds && dev_priv->lvds_downclock_avail) {
3784 /*
3785 * Ensure we match the reduced clock's P to the target clock.
3786 * If the clocks don't match, we can't switch the display clock
3787 * by using the FP0/FP1. In such case we will disable the LVDS
3788 * downclock feature.
3789 */
3790 has_reduced_clock = limit->find_pll(limit, crtc,
3791 dev_priv->lvds_downclock,
3792 refclk,
3793 &clock,
3794 &reduced_clock);
3795 }
3796
3797 if (is_sdvo && is_tv)
3798 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3799
3800 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3801 &reduced_clock : NULL);
3802
3803 if (IS_GEN2(dev))
3804 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3805 else
3806 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3807 has_reduced_clock ? &reduced_clock : NULL,
3808 num_connectors);
3809
3810 /* setup pipeconf */
3811 pipeconf = I915_READ(PIPECONF(pipe));
3812
3813 /* Set up the display plane register */
3814 dspcntr = DISPPLANE_GAMMA_ENABLE;
3815
3816 if (pipe == 0)
3817 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3818 else
3819 dspcntr |= DISPPLANE_SEL_PIPE_B;
3820
3821 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3822 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3823 * core speed.
3824 *
3825 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3826 * pipe == 0 check?
3827 */
3828 if (mode->clock >
3829 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3830 pipeconf |= PIPECONF_DOUBLE_WIDE;
3831 else
3832 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3833 }
3834
3835 /* default to 8bpc */
3836 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3837 if (is_dp) {
3838 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3839 pipeconf |= PIPECONF_BPP_6 |
3840 PIPECONF_DITHER_EN |
3841 PIPECONF_DITHER_TYPE_SP;
3842 }
3843 }
3844
3845 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3846 drm_mode_debug_printmodeline(mode);
3847
3848 if (HAS_PIPE_CXSR(dev)) {
3849 if (intel_crtc->lowfreq_avail) {
3850 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3851 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3852 } else {
3853 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3854 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3855 }
3856 }
3857
3858 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3859 if (!IS_GEN2(dev) &&
3860 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3861 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3862 /* the chip adds 2 halflines automatically */
3863 adjusted_mode->crtc_vtotal -= 1;
3864 adjusted_mode->crtc_vblank_end -= 1;
3865 vsyncshift = adjusted_mode->crtc_hsync_start
3866 - adjusted_mode->crtc_htotal/2;
3867 } else {
3868 pipeconf |= PIPECONF_PROGRESSIVE;
3869 vsyncshift = 0;
3870 }
3871
3872 if (!IS_GEN3(dev))
3873 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3874
3875 I915_WRITE(HTOTAL(pipe),
3876 (adjusted_mode->crtc_hdisplay - 1) |
3877 ((adjusted_mode->crtc_htotal - 1) << 16));
3878 I915_WRITE(HBLANK(pipe),
3879 (adjusted_mode->crtc_hblank_start - 1) |
3880 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3881 I915_WRITE(HSYNC(pipe),
3882 (adjusted_mode->crtc_hsync_start - 1) |
3883 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3884
3885 I915_WRITE(VTOTAL(pipe),
3886 (adjusted_mode->crtc_vdisplay - 1) |
3887 ((adjusted_mode->crtc_vtotal - 1) << 16));
3888 I915_WRITE(VBLANK(pipe),
3889 (adjusted_mode->crtc_vblank_start - 1) |
3890 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3891 I915_WRITE(VSYNC(pipe),
3892 (adjusted_mode->crtc_vsync_start - 1) |
3893 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3894
3895 /* pipesrc and dspsize control the size that is scaled from,
3896 * which should always be the user's requested size.
3897 */
3898 I915_WRITE(DSPSIZE(plane),
3899 ((mode->vdisplay - 1) << 16) |
3900 (mode->hdisplay - 1));
3901 I915_WRITE(DSPPOS(plane), 0);
3902 I915_WRITE(PIPESRC(pipe),
3903 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3904
3905 I915_WRITE(PIPECONF(pipe), pipeconf);
3906 POSTING_READ(PIPECONF(pipe));
3907 intel_enable_pipe(dev_priv, pipe, false);
3908
3909 intel_wait_for_vblank(dev, pipe);
3910
3911 I915_WRITE(DSPCNTR(plane), dspcntr);
3912 POSTING_READ(DSPCNTR(plane));
3913
3914 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3915
3916 intel_update_watermarks(dev);
3917
3918 return ret;
3919 }
3920
3921 /*
3922 * Initialize reference clocks when the driver loads
3923 */
3924 void ironlake_init_pch_refclk(struct drm_device *dev)
3925 {
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 struct drm_mode_config *mode_config = &dev->mode_config;
3928 struct intel_encoder *encoder;
3929 u32 temp;
3930 bool has_lvds = false;
3931 bool has_cpu_edp = false;
3932 bool has_pch_edp = false;
3933 bool has_panel = false;
3934 bool has_ck505 = false;
3935 bool can_ssc = false;
3936
3937 /* We need to take the global config into account */
3938 list_for_each_entry(encoder, &mode_config->encoder_list,
3939 base.head) {
3940 switch (encoder->type) {
3941 case INTEL_OUTPUT_LVDS:
3942 has_panel = true;
3943 has_lvds = true;
3944 break;
3945 case INTEL_OUTPUT_EDP:
3946 has_panel = true;
3947 if (intel_encoder_is_pch_edp(&encoder->base))
3948 has_pch_edp = true;
3949 else
3950 has_cpu_edp = true;
3951 break;
3952 }
3953 }
3954
3955 if (HAS_PCH_IBX(dev)) {
3956 has_ck505 = dev_priv->display_clock_mode;
3957 can_ssc = has_ck505;
3958 } else {
3959 has_ck505 = false;
3960 can_ssc = true;
3961 }
3962
3963 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3964 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3965 has_ck505);
3966
3967 /* Ironlake: try to setup display ref clock before DPLL
3968 * enabling. This is only under driver's control after
3969 * PCH B stepping, previous chipset stepping should be
3970 * ignoring this setting.
3971 */
3972 temp = I915_READ(PCH_DREF_CONTROL);
3973 /* Always enable nonspread source */
3974 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3975
3976 if (has_ck505)
3977 temp |= DREF_NONSPREAD_CK505_ENABLE;
3978 else
3979 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3980
3981 if (has_panel) {
3982 temp &= ~DREF_SSC_SOURCE_MASK;
3983 temp |= DREF_SSC_SOURCE_ENABLE;
3984
3985 /* SSC must be turned on before enabling the CPU output */
3986 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3987 DRM_DEBUG_KMS("Using SSC on panel\n");
3988 temp |= DREF_SSC1_ENABLE;
3989 } else
3990 temp &= ~DREF_SSC1_ENABLE;
3991
3992 /* Get SSC going before enabling the outputs */
3993 I915_WRITE(PCH_DREF_CONTROL, temp);
3994 POSTING_READ(PCH_DREF_CONTROL);
3995 udelay(200);
3996
3997 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3998
3999 /* Enable CPU source on CPU attached eDP */
4000 if (has_cpu_edp) {
4001 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4002 DRM_DEBUG_KMS("Using SSC on eDP\n");
4003 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4004 }
4005 else
4006 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4007 } else
4008 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4009
4010 I915_WRITE(PCH_DREF_CONTROL, temp);
4011 POSTING_READ(PCH_DREF_CONTROL);
4012 udelay(200);
4013 } else {
4014 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4015
4016 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4017
4018 /* Turn off CPU output */
4019 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4020
4021 I915_WRITE(PCH_DREF_CONTROL, temp);
4022 POSTING_READ(PCH_DREF_CONTROL);
4023 udelay(200);
4024
4025 /* Turn off the SSC source */
4026 temp &= ~DREF_SSC_SOURCE_MASK;
4027 temp |= DREF_SSC_SOURCE_DISABLE;
4028
4029 /* Turn off SSC1 */
4030 temp &= ~ DREF_SSC1_ENABLE;
4031
4032 I915_WRITE(PCH_DREF_CONTROL, temp);
4033 POSTING_READ(PCH_DREF_CONTROL);
4034 udelay(200);
4035 }
4036 }
4037
4038 static int ironlake_get_refclk(struct drm_crtc *crtc)
4039 {
4040 struct drm_device *dev = crtc->dev;
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042 struct intel_encoder *encoder;
4043 struct drm_mode_config *mode_config = &dev->mode_config;
4044 struct intel_encoder *edp_encoder = NULL;
4045 int num_connectors = 0;
4046 bool is_lvds = false;
4047
4048 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4049 if (encoder->base.crtc != crtc)
4050 continue;
4051
4052 switch (encoder->type) {
4053 case INTEL_OUTPUT_LVDS:
4054 is_lvds = true;
4055 break;
4056 case INTEL_OUTPUT_EDP:
4057 edp_encoder = encoder;
4058 break;
4059 }
4060 num_connectors++;
4061 }
4062
4063 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4064 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4065 dev_priv->lvds_ssc_freq);
4066 return dev_priv->lvds_ssc_freq * 1000;
4067 }
4068
4069 return 120000;
4070 }
4071
4072 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4073 struct drm_display_mode *mode,
4074 struct drm_display_mode *adjusted_mode,
4075 int x, int y,
4076 struct drm_framebuffer *old_fb)
4077 {
4078 struct drm_device *dev = crtc->dev;
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4081 int pipe = intel_crtc->pipe;
4082 int plane = intel_crtc->plane;
4083 int refclk, num_connectors = 0;
4084 intel_clock_t clock, reduced_clock;
4085 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4086 bool ok, has_reduced_clock = false, is_sdvo = false;
4087 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4088 struct drm_mode_config *mode_config = &dev->mode_config;
4089 struct intel_encoder *encoder, *edp_encoder = NULL;
4090 const intel_limit_t *limit;
4091 int ret;
4092 struct fdi_m_n m_n = {0};
4093 u32 temp;
4094 int target_clock, pixel_multiplier, lane, link_bw, factor;
4095 unsigned int pipe_bpp;
4096 bool dither;
4097 bool is_cpu_edp = false, is_pch_edp = false;
4098
4099 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4100 if (encoder->base.crtc != crtc)
4101 continue;
4102
4103 switch (encoder->type) {
4104 case INTEL_OUTPUT_LVDS:
4105 is_lvds = true;
4106 break;
4107 case INTEL_OUTPUT_SDVO:
4108 case INTEL_OUTPUT_HDMI:
4109 is_sdvo = true;
4110 if (encoder->needs_tv_clock)
4111 is_tv = true;
4112 break;
4113 case INTEL_OUTPUT_TVOUT:
4114 is_tv = true;
4115 break;
4116 case INTEL_OUTPUT_ANALOG:
4117 is_crt = true;
4118 break;
4119 case INTEL_OUTPUT_DISPLAYPORT:
4120 is_dp = true;
4121 break;
4122 case INTEL_OUTPUT_EDP:
4123 is_dp = true;
4124 if (intel_encoder_is_pch_edp(&encoder->base))
4125 is_pch_edp = true;
4126 else
4127 is_cpu_edp = true;
4128 edp_encoder = encoder;
4129 break;
4130 }
4131
4132 num_connectors++;
4133 }
4134
4135 refclk = ironlake_get_refclk(crtc);
4136
4137 /*
4138 * Returns a set of divisors for the desired target clock with the given
4139 * refclk, or FALSE. The returned values represent the clock equation:
4140 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4141 */
4142 limit = intel_limit(crtc, refclk);
4143 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4144 &clock);
4145 if (!ok) {
4146 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4147 return -EINVAL;
4148 }
4149
4150 /* Ensure that the cursor is valid for the new mode before changing... */
4151 intel_crtc_update_cursor(crtc, true);
4152
4153 if (is_lvds && dev_priv->lvds_downclock_avail) {
4154 /*
4155 * Ensure we match the reduced clock's P to the target clock.
4156 * If the clocks don't match, we can't switch the display clock
4157 * by using the FP0/FP1. In such case we will disable the LVDS
4158 * downclock feature.
4159 */
4160 has_reduced_clock = limit->find_pll(limit, crtc,
4161 dev_priv->lvds_downclock,
4162 refclk,
4163 &clock,
4164 &reduced_clock);
4165 }
4166 /* SDVO TV has fixed PLL values depend on its clock range,
4167 this mirrors vbios setting. */
4168 if (is_sdvo && is_tv) {
4169 if (adjusted_mode->clock >= 100000
4170 && adjusted_mode->clock < 140500) {
4171 clock.p1 = 2;
4172 clock.p2 = 10;
4173 clock.n = 3;
4174 clock.m1 = 16;
4175 clock.m2 = 8;
4176 } else if (adjusted_mode->clock >= 140500
4177 && adjusted_mode->clock <= 200000) {
4178 clock.p1 = 1;
4179 clock.p2 = 10;
4180 clock.n = 6;
4181 clock.m1 = 12;
4182 clock.m2 = 8;
4183 }
4184 }
4185
4186 /* FDI link */
4187 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4188 lane = 0;
4189 /* CPU eDP doesn't require FDI link, so just set DP M/N
4190 according to current link config */
4191 if (is_cpu_edp) {
4192 target_clock = mode->clock;
4193 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4194 } else {
4195 /* [e]DP over FDI requires target mode clock
4196 instead of link clock */
4197 if (is_dp)
4198 target_clock = mode->clock;
4199 else
4200 target_clock = adjusted_mode->clock;
4201
4202 /* FDI is a binary signal running at ~2.7GHz, encoding
4203 * each output octet as 10 bits. The actual frequency
4204 * is stored as a divider into a 100MHz clock, and the
4205 * mode pixel clock is stored in units of 1KHz.
4206 * Hence the bw of each lane in terms of the mode signal
4207 * is:
4208 */
4209 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4210 }
4211
4212 /* determine panel color depth */
4213 temp = I915_READ(PIPECONF(pipe));
4214 temp &= ~PIPE_BPC_MASK;
4215 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4216 switch (pipe_bpp) {
4217 case 18:
4218 temp |= PIPE_6BPC;
4219 break;
4220 case 24:
4221 temp |= PIPE_8BPC;
4222 break;
4223 case 30:
4224 temp |= PIPE_10BPC;
4225 break;
4226 case 36:
4227 temp |= PIPE_12BPC;
4228 break;
4229 default:
4230 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4231 pipe_bpp);
4232 temp |= PIPE_8BPC;
4233 pipe_bpp = 24;
4234 break;
4235 }
4236
4237 intel_crtc->bpp = pipe_bpp;
4238 I915_WRITE(PIPECONF(pipe), temp);
4239
4240 if (!lane) {
4241 /*
4242 * Account for spread spectrum to avoid
4243 * oversubscribing the link. Max center spread
4244 * is 2.5%; use 5% for safety's sake.
4245 */
4246 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4247 lane = bps / (link_bw * 8) + 1;
4248 }
4249
4250 intel_crtc->fdi_lanes = lane;
4251
4252 if (pixel_multiplier > 1)
4253 link_bw *= pixel_multiplier;
4254 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4255 &m_n);
4256
4257 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4258 if (has_reduced_clock)
4259 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4260 reduced_clock.m2;
4261
4262 /* Enable autotuning of the PLL clock (if permissible) */
4263 factor = 21;
4264 if (is_lvds) {
4265 if ((intel_panel_use_ssc(dev_priv) &&
4266 dev_priv->lvds_ssc_freq == 100) ||
4267 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4268 factor = 25;
4269 } else if (is_sdvo && is_tv)
4270 factor = 20;
4271
4272 if (clock.m < factor * clock.n)
4273 fp |= FP_CB_TUNE;
4274
4275 dpll = 0;
4276
4277 if (is_lvds)
4278 dpll |= DPLLB_MODE_LVDS;
4279 else
4280 dpll |= DPLLB_MODE_DAC_SERIAL;
4281 if (is_sdvo) {
4282 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4283 if (pixel_multiplier > 1) {
4284 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4285 }
4286 dpll |= DPLL_DVO_HIGH_SPEED;
4287 }
4288 if (is_dp && !is_cpu_edp)
4289 dpll |= DPLL_DVO_HIGH_SPEED;
4290
4291 /* compute bitmask from p1 value */
4292 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4293 /* also FPA1 */
4294 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4295
4296 switch (clock.p2) {
4297 case 5:
4298 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4299 break;
4300 case 7:
4301 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4302 break;
4303 case 10:
4304 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4305 break;
4306 case 14:
4307 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4308 break;
4309 }
4310
4311 if (is_sdvo && is_tv)
4312 dpll |= PLL_REF_INPUT_TVCLKINBC;
4313 else if (is_tv)
4314 /* XXX: just matching BIOS for now */
4315 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4316 dpll |= 3;
4317 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4318 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4319 else
4320 dpll |= PLL_REF_INPUT_DREFCLK;
4321
4322 /* setup pipeconf */
4323 pipeconf = I915_READ(PIPECONF(pipe));
4324
4325 /* Set up the display plane register */
4326 dspcntr = DISPPLANE_GAMMA_ENABLE;
4327
4328 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4329 drm_mode_debug_printmodeline(mode);
4330
4331 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4332 if (!is_cpu_edp) {
4333 struct intel_pch_pll *pll;
4334
4335 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4336 if (pll == NULL) {
4337 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4338 pipe);
4339 return -EINVAL;
4340 }
4341 } else
4342 intel_put_pch_pll(intel_crtc);
4343
4344 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4345 * This is an exception to the general rule that mode_set doesn't turn
4346 * things on.
4347 */
4348 if (is_lvds) {
4349 temp = I915_READ(PCH_LVDS);
4350 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4351 if (HAS_PCH_CPT(dev)) {
4352 temp &= ~PORT_TRANS_SEL_MASK;
4353 temp |= PORT_TRANS_SEL_CPT(pipe);
4354 } else {
4355 if (pipe == 1)
4356 temp |= LVDS_PIPEB_SELECT;
4357 else
4358 temp &= ~LVDS_PIPEB_SELECT;
4359 }
4360
4361 /* set the corresponsding LVDS_BORDER bit */
4362 temp |= dev_priv->lvds_border_bits;
4363 /* Set the B0-B3 data pairs corresponding to whether we're going to
4364 * set the DPLLs for dual-channel mode or not.
4365 */
4366 if (clock.p2 == 7)
4367 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4368 else
4369 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4370
4371 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4372 * appropriately here, but we need to look more thoroughly into how
4373 * panels behave in the two modes.
4374 */
4375 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4376 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4377 temp |= LVDS_HSYNC_POLARITY;
4378 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4379 temp |= LVDS_VSYNC_POLARITY;
4380 I915_WRITE(PCH_LVDS, temp);
4381 }
4382
4383 pipeconf &= ~PIPECONF_DITHER_EN;
4384 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4385 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4386 pipeconf |= PIPECONF_DITHER_EN;
4387 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4388 }
4389 if (is_dp && !is_cpu_edp) {
4390 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4391 } else {
4392 /* For non-DP output, clear any trans DP clock recovery setting.*/
4393 I915_WRITE(TRANSDATA_M1(pipe), 0);
4394 I915_WRITE(TRANSDATA_N1(pipe), 0);
4395 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4396 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4397 }
4398
4399 if (intel_crtc->pch_pll) {
4400 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4401
4402 /* Wait for the clocks to stabilize. */
4403 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4404 udelay(150);
4405
4406 /* The pixel multiplier can only be updated once the
4407 * DPLL is enabled and the clocks are stable.
4408 *
4409 * So write it again.
4410 */
4411 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4412 }
4413
4414 intel_crtc->lowfreq_avail = false;
4415 if (intel_crtc->pch_pll) {
4416 if (is_lvds && has_reduced_clock && i915_powersave) {
4417 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4418 intel_crtc->lowfreq_avail = true;
4419 if (HAS_PIPE_CXSR(dev)) {
4420 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4421 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4422 }
4423 } else {
4424 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4425 if (HAS_PIPE_CXSR(dev)) {
4426 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4427 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4428 }
4429 }
4430 }
4431
4432 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4433 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4434 pipeconf |= PIPECONF_INTERLACED_ILK;
4435 /* the chip adds 2 halflines automatically */
4436 adjusted_mode->crtc_vtotal -= 1;
4437 adjusted_mode->crtc_vblank_end -= 1;
4438 I915_WRITE(VSYNCSHIFT(pipe),
4439 adjusted_mode->crtc_hsync_start
4440 - adjusted_mode->crtc_htotal/2);
4441 } else {
4442 pipeconf |= PIPECONF_PROGRESSIVE;
4443 I915_WRITE(VSYNCSHIFT(pipe), 0);
4444 }
4445
4446 I915_WRITE(HTOTAL(pipe),
4447 (adjusted_mode->crtc_hdisplay - 1) |
4448 ((adjusted_mode->crtc_htotal - 1) << 16));
4449 I915_WRITE(HBLANK(pipe),
4450 (adjusted_mode->crtc_hblank_start - 1) |
4451 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4452 I915_WRITE(HSYNC(pipe),
4453 (adjusted_mode->crtc_hsync_start - 1) |
4454 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4455
4456 I915_WRITE(VTOTAL(pipe),
4457 (adjusted_mode->crtc_vdisplay - 1) |
4458 ((adjusted_mode->crtc_vtotal - 1) << 16));
4459 I915_WRITE(VBLANK(pipe),
4460 (adjusted_mode->crtc_vblank_start - 1) |
4461 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4462 I915_WRITE(VSYNC(pipe),
4463 (adjusted_mode->crtc_vsync_start - 1) |
4464 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4465
4466 /* pipesrc controls the size that is scaled from, which should
4467 * always be the user's requested size.
4468 */
4469 I915_WRITE(PIPESRC(pipe),
4470 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4471
4472 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4473 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4474 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4475 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4476
4477 if (is_cpu_edp)
4478 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4479
4480 I915_WRITE(PIPECONF(pipe), pipeconf);
4481 POSTING_READ(PIPECONF(pipe));
4482
4483 intel_wait_for_vblank(dev, pipe);
4484
4485 I915_WRITE(DSPCNTR(plane), dspcntr);
4486 POSTING_READ(DSPCNTR(plane));
4487
4488 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4489
4490 intel_update_watermarks(dev);
4491
4492 return ret;
4493 }
4494
4495 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4496 struct drm_display_mode *mode,
4497 struct drm_display_mode *adjusted_mode,
4498 int x, int y,
4499 struct drm_framebuffer *old_fb)
4500 {
4501 struct drm_device *dev = crtc->dev;
4502 struct drm_i915_private *dev_priv = dev->dev_private;
4503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4504 int pipe = intel_crtc->pipe;
4505 int ret;
4506
4507 drm_vblank_pre_modeset(dev, pipe);
4508
4509 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4510 x, y, old_fb);
4511 drm_vblank_post_modeset(dev, pipe);
4512
4513 if (ret)
4514 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4515 else
4516 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4517
4518 return ret;
4519 }
4520
4521 static bool intel_eld_uptodate(struct drm_connector *connector,
4522 int reg_eldv, uint32_t bits_eldv,
4523 int reg_elda, uint32_t bits_elda,
4524 int reg_edid)
4525 {
4526 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4527 uint8_t *eld = connector->eld;
4528 uint32_t i;
4529
4530 i = I915_READ(reg_eldv);
4531 i &= bits_eldv;
4532
4533 if (!eld[0])
4534 return !i;
4535
4536 if (!i)
4537 return false;
4538
4539 i = I915_READ(reg_elda);
4540 i &= ~bits_elda;
4541 I915_WRITE(reg_elda, i);
4542
4543 for (i = 0; i < eld[2]; i++)
4544 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4545 return false;
4546
4547 return true;
4548 }
4549
4550 static void g4x_write_eld(struct drm_connector *connector,
4551 struct drm_crtc *crtc)
4552 {
4553 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4554 uint8_t *eld = connector->eld;
4555 uint32_t eldv;
4556 uint32_t len;
4557 uint32_t i;
4558
4559 i = I915_READ(G4X_AUD_VID_DID);
4560
4561 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4562 eldv = G4X_ELDV_DEVCL_DEVBLC;
4563 else
4564 eldv = G4X_ELDV_DEVCTG;
4565
4566 if (intel_eld_uptodate(connector,
4567 G4X_AUD_CNTL_ST, eldv,
4568 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4569 G4X_HDMIW_HDMIEDID))
4570 return;
4571
4572 i = I915_READ(G4X_AUD_CNTL_ST);
4573 i &= ~(eldv | G4X_ELD_ADDR);
4574 len = (i >> 9) & 0x1f; /* ELD buffer size */
4575 I915_WRITE(G4X_AUD_CNTL_ST, i);
4576
4577 if (!eld[0])
4578 return;
4579
4580 len = min_t(uint8_t, eld[2], len);
4581 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4582 for (i = 0; i < len; i++)
4583 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4584
4585 i = I915_READ(G4X_AUD_CNTL_ST);
4586 i |= eldv;
4587 I915_WRITE(G4X_AUD_CNTL_ST, i);
4588 }
4589
4590 static void ironlake_write_eld(struct drm_connector *connector,
4591 struct drm_crtc *crtc)
4592 {
4593 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4594 uint8_t *eld = connector->eld;
4595 uint32_t eldv;
4596 uint32_t i;
4597 int len;
4598 int hdmiw_hdmiedid;
4599 int aud_config;
4600 int aud_cntl_st;
4601 int aud_cntrl_st2;
4602
4603 if (HAS_PCH_IBX(connector->dev)) {
4604 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4605 aud_config = IBX_AUD_CONFIG_A;
4606 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4607 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4608 } else {
4609 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4610 aud_config = CPT_AUD_CONFIG_A;
4611 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4612 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4613 }
4614
4615 i = to_intel_crtc(crtc)->pipe;
4616 hdmiw_hdmiedid += i * 0x100;
4617 aud_cntl_st += i * 0x100;
4618 aud_config += i * 0x100;
4619
4620 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4621
4622 i = I915_READ(aud_cntl_st);
4623 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4624 if (!i) {
4625 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4626 /* operate blindly on all ports */
4627 eldv = IBX_ELD_VALIDB;
4628 eldv |= IBX_ELD_VALIDB << 4;
4629 eldv |= IBX_ELD_VALIDB << 8;
4630 } else {
4631 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4632 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4633 }
4634
4635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4636 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4637 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4638 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4639 } else
4640 I915_WRITE(aud_config, 0);
4641
4642 if (intel_eld_uptodate(connector,
4643 aud_cntrl_st2, eldv,
4644 aud_cntl_st, IBX_ELD_ADDRESS,
4645 hdmiw_hdmiedid))
4646 return;
4647
4648 i = I915_READ(aud_cntrl_st2);
4649 i &= ~eldv;
4650 I915_WRITE(aud_cntrl_st2, i);
4651
4652 if (!eld[0])
4653 return;
4654
4655 i = I915_READ(aud_cntl_st);
4656 i &= ~IBX_ELD_ADDRESS;
4657 I915_WRITE(aud_cntl_st, i);
4658
4659 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4660 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4661 for (i = 0; i < len; i++)
4662 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4663
4664 i = I915_READ(aud_cntrl_st2);
4665 i |= eldv;
4666 I915_WRITE(aud_cntrl_st2, i);
4667 }
4668
4669 void intel_write_eld(struct drm_encoder *encoder,
4670 struct drm_display_mode *mode)
4671 {
4672 struct drm_crtc *crtc = encoder->crtc;
4673 struct drm_connector *connector;
4674 struct drm_device *dev = encoder->dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676
4677 connector = drm_select_eld(encoder, mode);
4678 if (!connector)
4679 return;
4680
4681 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4682 connector->base.id,
4683 drm_get_connector_name(connector),
4684 connector->encoder->base.id,
4685 drm_get_encoder_name(connector->encoder));
4686
4687 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4688
4689 if (dev_priv->display.write_eld)
4690 dev_priv->display.write_eld(connector, crtc);
4691 }
4692
4693 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4694 void intel_crtc_load_lut(struct drm_crtc *crtc)
4695 {
4696 struct drm_device *dev = crtc->dev;
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699 int palreg = PALETTE(intel_crtc->pipe);
4700 int i;
4701
4702 /* The clocks have to be on to load the palette. */
4703 if (!crtc->enabled || !intel_crtc->active)
4704 return;
4705
4706 /* use legacy palette for Ironlake */
4707 if (HAS_PCH_SPLIT(dev))
4708 palreg = LGC_PALETTE(intel_crtc->pipe);
4709
4710 for (i = 0; i < 256; i++) {
4711 I915_WRITE(palreg + 4 * i,
4712 (intel_crtc->lut_r[i] << 16) |
4713 (intel_crtc->lut_g[i] << 8) |
4714 intel_crtc->lut_b[i]);
4715 }
4716 }
4717
4718 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4719 {
4720 struct drm_device *dev = crtc->dev;
4721 struct drm_i915_private *dev_priv = dev->dev_private;
4722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4723 bool visible = base != 0;
4724 u32 cntl;
4725
4726 if (intel_crtc->cursor_visible == visible)
4727 return;
4728
4729 cntl = I915_READ(_CURACNTR);
4730 if (visible) {
4731 /* On these chipsets we can only modify the base whilst
4732 * the cursor is disabled.
4733 */
4734 I915_WRITE(_CURABASE, base);
4735
4736 cntl &= ~(CURSOR_FORMAT_MASK);
4737 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4738 cntl |= CURSOR_ENABLE |
4739 CURSOR_GAMMA_ENABLE |
4740 CURSOR_FORMAT_ARGB;
4741 } else
4742 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4743 I915_WRITE(_CURACNTR, cntl);
4744
4745 intel_crtc->cursor_visible = visible;
4746 }
4747
4748 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4749 {
4750 struct drm_device *dev = crtc->dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 int pipe = intel_crtc->pipe;
4754 bool visible = base != 0;
4755
4756 if (intel_crtc->cursor_visible != visible) {
4757 uint32_t cntl = I915_READ(CURCNTR(pipe));
4758 if (base) {
4759 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4760 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4761 cntl |= pipe << 28; /* Connect to correct pipe */
4762 } else {
4763 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4764 cntl |= CURSOR_MODE_DISABLE;
4765 }
4766 I915_WRITE(CURCNTR(pipe), cntl);
4767
4768 intel_crtc->cursor_visible = visible;
4769 }
4770 /* and commit changes on next vblank */
4771 I915_WRITE(CURBASE(pipe), base);
4772 }
4773
4774 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4775 {
4776 struct drm_device *dev = crtc->dev;
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4779 int pipe = intel_crtc->pipe;
4780 bool visible = base != 0;
4781
4782 if (intel_crtc->cursor_visible != visible) {
4783 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4784 if (base) {
4785 cntl &= ~CURSOR_MODE;
4786 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4787 } else {
4788 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4789 cntl |= CURSOR_MODE_DISABLE;
4790 }
4791 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4792
4793 intel_crtc->cursor_visible = visible;
4794 }
4795 /* and commit changes on next vblank */
4796 I915_WRITE(CURBASE_IVB(pipe), base);
4797 }
4798
4799 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4800 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4801 bool on)
4802 {
4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806 int pipe = intel_crtc->pipe;
4807 int x = intel_crtc->cursor_x;
4808 int y = intel_crtc->cursor_y;
4809 u32 base, pos;
4810 bool visible;
4811
4812 pos = 0;
4813
4814 if (on && crtc->enabled && crtc->fb) {
4815 base = intel_crtc->cursor_addr;
4816 if (x > (int) crtc->fb->width)
4817 base = 0;
4818
4819 if (y > (int) crtc->fb->height)
4820 base = 0;
4821 } else
4822 base = 0;
4823
4824 if (x < 0) {
4825 if (x + intel_crtc->cursor_width < 0)
4826 base = 0;
4827
4828 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4829 x = -x;
4830 }
4831 pos |= x << CURSOR_X_SHIFT;
4832
4833 if (y < 0) {
4834 if (y + intel_crtc->cursor_height < 0)
4835 base = 0;
4836
4837 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4838 y = -y;
4839 }
4840 pos |= y << CURSOR_Y_SHIFT;
4841
4842 visible = base != 0;
4843 if (!visible && !intel_crtc->cursor_visible)
4844 return;
4845
4846 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4847 I915_WRITE(CURPOS_IVB(pipe), pos);
4848 ivb_update_cursor(crtc, base);
4849 } else {
4850 I915_WRITE(CURPOS(pipe), pos);
4851 if (IS_845G(dev) || IS_I865G(dev))
4852 i845_update_cursor(crtc, base);
4853 else
4854 i9xx_update_cursor(crtc, base);
4855 }
4856
4857 if (visible)
4858 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4859 }
4860
4861 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4862 struct drm_file *file,
4863 uint32_t handle,
4864 uint32_t width, uint32_t height)
4865 {
4866 struct drm_device *dev = crtc->dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4869 struct drm_i915_gem_object *obj;
4870 uint32_t addr;
4871 int ret;
4872
4873 DRM_DEBUG_KMS("\n");
4874
4875 /* if we want to turn off the cursor ignore width and height */
4876 if (!handle) {
4877 DRM_DEBUG_KMS("cursor off\n");
4878 addr = 0;
4879 obj = NULL;
4880 mutex_lock(&dev->struct_mutex);
4881 goto finish;
4882 }
4883
4884 /* Currently we only support 64x64 cursors */
4885 if (width != 64 || height != 64) {
4886 DRM_ERROR("we currently only support 64x64 cursors\n");
4887 return -EINVAL;
4888 }
4889
4890 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4891 if (&obj->base == NULL)
4892 return -ENOENT;
4893
4894 if (obj->base.size < width * height * 4) {
4895 DRM_ERROR("buffer is to small\n");
4896 ret = -ENOMEM;
4897 goto fail;
4898 }
4899
4900 /* we only need to pin inside GTT if cursor is non-phy */
4901 mutex_lock(&dev->struct_mutex);
4902 if (!dev_priv->info->cursor_needs_physical) {
4903 if (obj->tiling_mode) {
4904 DRM_ERROR("cursor cannot be tiled\n");
4905 ret = -EINVAL;
4906 goto fail_locked;
4907 }
4908
4909 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4910 if (ret) {
4911 DRM_ERROR("failed to move cursor bo into the GTT\n");
4912 goto fail_locked;
4913 }
4914
4915 ret = i915_gem_object_put_fence(obj);
4916 if (ret) {
4917 DRM_ERROR("failed to release fence for cursor");
4918 goto fail_unpin;
4919 }
4920
4921 addr = obj->gtt_offset;
4922 } else {
4923 int align = IS_I830(dev) ? 16 * 1024 : 256;
4924 ret = i915_gem_attach_phys_object(dev, obj,
4925 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4926 align);
4927 if (ret) {
4928 DRM_ERROR("failed to attach phys object\n");
4929 goto fail_locked;
4930 }
4931 addr = obj->phys_obj->handle->busaddr;
4932 }
4933
4934 if (IS_GEN2(dev))
4935 I915_WRITE(CURSIZE, (height << 12) | width);
4936
4937 finish:
4938 if (intel_crtc->cursor_bo) {
4939 if (dev_priv->info->cursor_needs_physical) {
4940 if (intel_crtc->cursor_bo != obj)
4941 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4942 } else
4943 i915_gem_object_unpin(intel_crtc->cursor_bo);
4944 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4945 }
4946
4947 mutex_unlock(&dev->struct_mutex);
4948
4949 intel_crtc->cursor_addr = addr;
4950 intel_crtc->cursor_bo = obj;
4951 intel_crtc->cursor_width = width;
4952 intel_crtc->cursor_height = height;
4953
4954 intel_crtc_update_cursor(crtc, true);
4955
4956 return 0;
4957 fail_unpin:
4958 i915_gem_object_unpin(obj);
4959 fail_locked:
4960 mutex_unlock(&dev->struct_mutex);
4961 fail:
4962 drm_gem_object_unreference_unlocked(&obj->base);
4963 return ret;
4964 }
4965
4966 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4967 {
4968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969
4970 intel_crtc->cursor_x = x;
4971 intel_crtc->cursor_y = y;
4972
4973 intel_crtc_update_cursor(crtc, true);
4974
4975 return 0;
4976 }
4977
4978 /** Sets the color ramps on behalf of RandR */
4979 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4980 u16 blue, int regno)
4981 {
4982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983
4984 intel_crtc->lut_r[regno] = red >> 8;
4985 intel_crtc->lut_g[regno] = green >> 8;
4986 intel_crtc->lut_b[regno] = blue >> 8;
4987 }
4988
4989 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4990 u16 *blue, int regno)
4991 {
4992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993
4994 *red = intel_crtc->lut_r[regno] << 8;
4995 *green = intel_crtc->lut_g[regno] << 8;
4996 *blue = intel_crtc->lut_b[regno] << 8;
4997 }
4998
4999 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5000 u16 *blue, uint32_t start, uint32_t size)
5001 {
5002 int end = (start + size > 256) ? 256 : start + size, i;
5003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004
5005 for (i = start; i < end; i++) {
5006 intel_crtc->lut_r[i] = red[i] >> 8;
5007 intel_crtc->lut_g[i] = green[i] >> 8;
5008 intel_crtc->lut_b[i] = blue[i] >> 8;
5009 }
5010
5011 intel_crtc_load_lut(crtc);
5012 }
5013
5014 /**
5015 * Get a pipe with a simple mode set on it for doing load-based monitor
5016 * detection.
5017 *
5018 * It will be up to the load-detect code to adjust the pipe as appropriate for
5019 * its requirements. The pipe will be connected to no other encoders.
5020 *
5021 * Currently this code will only succeed if there is a pipe with no encoders
5022 * configured for it. In the future, it could choose to temporarily disable
5023 * some outputs to free up a pipe for its use.
5024 *
5025 * \return crtc, or NULL if no pipes are available.
5026 */
5027
5028 /* VESA 640x480x72Hz mode to set on the pipe */
5029 static struct drm_display_mode load_detect_mode = {
5030 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5031 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5032 };
5033
5034 static struct drm_framebuffer *
5035 intel_framebuffer_create(struct drm_device *dev,
5036 struct drm_mode_fb_cmd2 *mode_cmd,
5037 struct drm_i915_gem_object *obj)
5038 {
5039 struct intel_framebuffer *intel_fb;
5040 int ret;
5041
5042 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5043 if (!intel_fb) {
5044 drm_gem_object_unreference_unlocked(&obj->base);
5045 return ERR_PTR(-ENOMEM);
5046 }
5047
5048 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5049 if (ret) {
5050 drm_gem_object_unreference_unlocked(&obj->base);
5051 kfree(intel_fb);
5052 return ERR_PTR(ret);
5053 }
5054
5055 return &intel_fb->base;
5056 }
5057
5058 static u32
5059 intel_framebuffer_pitch_for_width(int width, int bpp)
5060 {
5061 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5062 return ALIGN(pitch, 64);
5063 }
5064
5065 static u32
5066 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5067 {
5068 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5069 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5070 }
5071
5072 static struct drm_framebuffer *
5073 intel_framebuffer_create_for_mode(struct drm_device *dev,
5074 struct drm_display_mode *mode,
5075 int depth, int bpp)
5076 {
5077 struct drm_i915_gem_object *obj;
5078 struct drm_mode_fb_cmd2 mode_cmd;
5079
5080 obj = i915_gem_alloc_object(dev,
5081 intel_framebuffer_size_for_mode(mode, bpp));
5082 if (obj == NULL)
5083 return ERR_PTR(-ENOMEM);
5084
5085 mode_cmd.width = mode->hdisplay;
5086 mode_cmd.height = mode->vdisplay;
5087 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5088 bpp);
5089 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5090
5091 return intel_framebuffer_create(dev, &mode_cmd, obj);
5092 }
5093
5094 static struct drm_framebuffer *
5095 mode_fits_in_fbdev(struct drm_device *dev,
5096 struct drm_display_mode *mode)
5097 {
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 struct drm_i915_gem_object *obj;
5100 struct drm_framebuffer *fb;
5101
5102 if (dev_priv->fbdev == NULL)
5103 return NULL;
5104
5105 obj = dev_priv->fbdev->ifb.obj;
5106 if (obj == NULL)
5107 return NULL;
5108
5109 fb = &dev_priv->fbdev->ifb.base;
5110 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5111 fb->bits_per_pixel))
5112 return NULL;
5113
5114 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5115 return NULL;
5116
5117 return fb;
5118 }
5119
5120 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5121 struct drm_connector *connector,
5122 struct drm_display_mode *mode,
5123 struct intel_load_detect_pipe *old)
5124 {
5125 struct intel_crtc *intel_crtc;
5126 struct drm_crtc *possible_crtc;
5127 struct drm_encoder *encoder = &intel_encoder->base;
5128 struct drm_crtc *crtc = NULL;
5129 struct drm_device *dev = encoder->dev;
5130 struct drm_framebuffer *old_fb;
5131 int i = -1;
5132
5133 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5134 connector->base.id, drm_get_connector_name(connector),
5135 encoder->base.id, drm_get_encoder_name(encoder));
5136
5137 /*
5138 * Algorithm gets a little messy:
5139 *
5140 * - if the connector already has an assigned crtc, use it (but make
5141 * sure it's on first)
5142 *
5143 * - try to find the first unused crtc that can drive this connector,
5144 * and use that if we find one
5145 */
5146
5147 /* See if we already have a CRTC for this connector */
5148 if (encoder->crtc) {
5149 crtc = encoder->crtc;
5150
5151 intel_crtc = to_intel_crtc(crtc);
5152 old->dpms_mode = intel_crtc->dpms_mode;
5153 old->load_detect_temp = false;
5154
5155 /* Make sure the crtc and connector are running */
5156 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5157 struct drm_encoder_helper_funcs *encoder_funcs;
5158 struct drm_crtc_helper_funcs *crtc_funcs;
5159
5160 crtc_funcs = crtc->helper_private;
5161 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5162
5163 encoder_funcs = encoder->helper_private;
5164 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5165 }
5166
5167 return true;
5168 }
5169
5170 /* Find an unused one (if possible) */
5171 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5172 i++;
5173 if (!(encoder->possible_crtcs & (1 << i)))
5174 continue;
5175 if (!possible_crtc->enabled) {
5176 crtc = possible_crtc;
5177 break;
5178 }
5179 }
5180
5181 /*
5182 * If we didn't find an unused CRTC, don't use any.
5183 */
5184 if (!crtc) {
5185 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5186 return false;
5187 }
5188
5189 encoder->crtc = crtc;
5190 connector->encoder = encoder;
5191
5192 intel_crtc = to_intel_crtc(crtc);
5193 old->dpms_mode = intel_crtc->dpms_mode;
5194 old->load_detect_temp = true;
5195 old->release_fb = NULL;
5196
5197 if (!mode)
5198 mode = &load_detect_mode;
5199
5200 old_fb = crtc->fb;
5201
5202 /* We need a framebuffer large enough to accommodate all accesses
5203 * that the plane may generate whilst we perform load detection.
5204 * We can not rely on the fbcon either being present (we get called
5205 * during its initialisation to detect all boot displays, or it may
5206 * not even exist) or that it is large enough to satisfy the
5207 * requested mode.
5208 */
5209 crtc->fb = mode_fits_in_fbdev(dev, mode);
5210 if (crtc->fb == NULL) {
5211 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5212 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5213 old->release_fb = crtc->fb;
5214 } else
5215 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5216 if (IS_ERR(crtc->fb)) {
5217 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5218 crtc->fb = old_fb;
5219 return false;
5220 }
5221
5222 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5223 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5224 if (old->release_fb)
5225 old->release_fb->funcs->destroy(old->release_fb);
5226 crtc->fb = old_fb;
5227 return false;
5228 }
5229
5230 /* let the connector get through one full cycle before testing */
5231 intel_wait_for_vblank(dev, intel_crtc->pipe);
5232
5233 return true;
5234 }
5235
5236 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5237 struct drm_connector *connector,
5238 struct intel_load_detect_pipe *old)
5239 {
5240 struct drm_encoder *encoder = &intel_encoder->base;
5241 struct drm_device *dev = encoder->dev;
5242 struct drm_crtc *crtc = encoder->crtc;
5243 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5244 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5245
5246 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5247 connector->base.id, drm_get_connector_name(connector),
5248 encoder->base.id, drm_get_encoder_name(encoder));
5249
5250 if (old->load_detect_temp) {
5251 connector->encoder = NULL;
5252 drm_helper_disable_unused_functions(dev);
5253
5254 if (old->release_fb)
5255 old->release_fb->funcs->destroy(old->release_fb);
5256
5257 return;
5258 }
5259
5260 /* Switch crtc and encoder back off if necessary */
5261 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5262 encoder_funcs->dpms(encoder, old->dpms_mode);
5263 crtc_funcs->dpms(crtc, old->dpms_mode);
5264 }
5265 }
5266
5267 /* Returns the clock of the currently programmed mode of the given pipe. */
5268 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5269 {
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5272 int pipe = intel_crtc->pipe;
5273 u32 dpll = I915_READ(DPLL(pipe));
5274 u32 fp;
5275 intel_clock_t clock;
5276
5277 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5278 fp = I915_READ(FP0(pipe));
5279 else
5280 fp = I915_READ(FP1(pipe));
5281
5282 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5283 if (IS_PINEVIEW(dev)) {
5284 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5285 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5286 } else {
5287 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5288 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5289 }
5290
5291 if (!IS_GEN2(dev)) {
5292 if (IS_PINEVIEW(dev))
5293 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5294 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5295 else
5296 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5297 DPLL_FPA01_P1_POST_DIV_SHIFT);
5298
5299 switch (dpll & DPLL_MODE_MASK) {
5300 case DPLLB_MODE_DAC_SERIAL:
5301 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5302 5 : 10;
5303 break;
5304 case DPLLB_MODE_LVDS:
5305 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5306 7 : 14;
5307 break;
5308 default:
5309 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5310 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5311 return 0;
5312 }
5313
5314 /* XXX: Handle the 100Mhz refclk */
5315 intel_clock(dev, 96000, &clock);
5316 } else {
5317 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5318
5319 if (is_lvds) {
5320 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5321 DPLL_FPA01_P1_POST_DIV_SHIFT);
5322 clock.p2 = 14;
5323
5324 if ((dpll & PLL_REF_INPUT_MASK) ==
5325 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5326 /* XXX: might not be 66MHz */
5327 intel_clock(dev, 66000, &clock);
5328 } else
5329 intel_clock(dev, 48000, &clock);
5330 } else {
5331 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5332 clock.p1 = 2;
5333 else {
5334 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5335 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5336 }
5337 if (dpll & PLL_P2_DIVIDE_BY_4)
5338 clock.p2 = 4;
5339 else
5340 clock.p2 = 2;
5341
5342 intel_clock(dev, 48000, &clock);
5343 }
5344 }
5345
5346 /* XXX: It would be nice to validate the clocks, but we can't reuse
5347 * i830PllIsValid() because it relies on the xf86_config connector
5348 * configuration being accurate, which it isn't necessarily.
5349 */
5350
5351 return clock.dot;
5352 }
5353
5354 /** Returns the currently programmed mode of the given pipe. */
5355 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5356 struct drm_crtc *crtc)
5357 {
5358 struct drm_i915_private *dev_priv = dev->dev_private;
5359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5360 int pipe = intel_crtc->pipe;
5361 struct drm_display_mode *mode;
5362 int htot = I915_READ(HTOTAL(pipe));
5363 int hsync = I915_READ(HSYNC(pipe));
5364 int vtot = I915_READ(VTOTAL(pipe));
5365 int vsync = I915_READ(VSYNC(pipe));
5366
5367 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5368 if (!mode)
5369 return NULL;
5370
5371 mode->clock = intel_crtc_clock_get(dev, crtc);
5372 mode->hdisplay = (htot & 0xffff) + 1;
5373 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5374 mode->hsync_start = (hsync & 0xffff) + 1;
5375 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5376 mode->vdisplay = (vtot & 0xffff) + 1;
5377 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5378 mode->vsync_start = (vsync & 0xffff) + 1;
5379 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5380
5381 drm_mode_set_name(mode);
5382 drm_mode_set_crtcinfo(mode, 0);
5383
5384 return mode;
5385 }
5386
5387 #define GPU_IDLE_TIMEOUT 500 /* ms */
5388
5389 /* When this timer fires, we've been idle for awhile */
5390 static void intel_gpu_idle_timer(unsigned long arg)
5391 {
5392 struct drm_device *dev = (struct drm_device *)arg;
5393 drm_i915_private_t *dev_priv = dev->dev_private;
5394
5395 if (!list_empty(&dev_priv->mm.active_list)) {
5396 /* Still processing requests, so just re-arm the timer. */
5397 mod_timer(&dev_priv->idle_timer, jiffies +
5398 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5399 return;
5400 }
5401
5402 dev_priv->busy = false;
5403 queue_work(dev_priv->wq, &dev_priv->idle_work);
5404 }
5405
5406 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5407
5408 static void intel_crtc_idle_timer(unsigned long arg)
5409 {
5410 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5411 struct drm_crtc *crtc = &intel_crtc->base;
5412 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5413 struct intel_framebuffer *intel_fb;
5414
5415 intel_fb = to_intel_framebuffer(crtc->fb);
5416 if (intel_fb && intel_fb->obj->active) {
5417 /* The framebuffer is still being accessed by the GPU. */
5418 mod_timer(&intel_crtc->idle_timer, jiffies +
5419 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5420 return;
5421 }
5422
5423 intel_crtc->busy = false;
5424 queue_work(dev_priv->wq, &dev_priv->idle_work);
5425 }
5426
5427 static void intel_increase_pllclock(struct drm_crtc *crtc)
5428 {
5429 struct drm_device *dev = crtc->dev;
5430 drm_i915_private_t *dev_priv = dev->dev_private;
5431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5432 int pipe = intel_crtc->pipe;
5433 int dpll_reg = DPLL(pipe);
5434 int dpll;
5435
5436 if (HAS_PCH_SPLIT(dev))
5437 return;
5438
5439 if (!dev_priv->lvds_downclock_avail)
5440 return;
5441
5442 dpll = I915_READ(dpll_reg);
5443 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5444 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5445
5446 assert_panel_unlocked(dev_priv, pipe);
5447
5448 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5449 I915_WRITE(dpll_reg, dpll);
5450 intel_wait_for_vblank(dev, pipe);
5451
5452 dpll = I915_READ(dpll_reg);
5453 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5454 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5455 }
5456
5457 /* Schedule downclock */
5458 mod_timer(&intel_crtc->idle_timer, jiffies +
5459 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5460 }
5461
5462 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5463 {
5464 struct drm_device *dev = crtc->dev;
5465 drm_i915_private_t *dev_priv = dev->dev_private;
5466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5467 int pipe = intel_crtc->pipe;
5468 int dpll_reg = DPLL(pipe);
5469 int dpll = I915_READ(dpll_reg);
5470
5471 if (HAS_PCH_SPLIT(dev))
5472 return;
5473
5474 if (!dev_priv->lvds_downclock_avail)
5475 return;
5476
5477 /*
5478 * Since this is called by a timer, we should never get here in
5479 * the manual case.
5480 */
5481 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5482 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5483
5484 assert_panel_unlocked(dev_priv, pipe);
5485
5486 dpll |= DISPLAY_RATE_SELECT_FPA1;
5487 I915_WRITE(dpll_reg, dpll);
5488 intel_wait_for_vblank(dev, pipe);
5489 dpll = I915_READ(dpll_reg);
5490 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5491 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5492 }
5493
5494 }
5495
5496 /**
5497 * intel_idle_update - adjust clocks for idleness
5498 * @work: work struct
5499 *
5500 * Either the GPU or display (or both) went idle. Check the busy status
5501 * here and adjust the CRTC and GPU clocks as necessary.
5502 */
5503 static void intel_idle_update(struct work_struct *work)
5504 {
5505 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5506 idle_work);
5507 struct drm_device *dev = dev_priv->dev;
5508 struct drm_crtc *crtc;
5509 struct intel_crtc *intel_crtc;
5510
5511 if (!i915_powersave)
5512 return;
5513
5514 mutex_lock(&dev->struct_mutex);
5515
5516 i915_update_gfx_val(dev_priv);
5517
5518 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5519 /* Skip inactive CRTCs */
5520 if (!crtc->fb)
5521 continue;
5522
5523 intel_crtc = to_intel_crtc(crtc);
5524 if (!intel_crtc->busy)
5525 intel_decrease_pllclock(crtc);
5526 }
5527
5528
5529 mutex_unlock(&dev->struct_mutex);
5530 }
5531
5532 /**
5533 * intel_mark_busy - mark the GPU and possibly the display busy
5534 * @dev: drm device
5535 * @obj: object we're operating on
5536 *
5537 * Callers can use this function to indicate that the GPU is busy processing
5538 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5539 * buffer), we'll also mark the display as busy, so we know to increase its
5540 * clock frequency.
5541 */
5542 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5543 {
5544 drm_i915_private_t *dev_priv = dev->dev_private;
5545 struct drm_crtc *crtc = NULL;
5546 struct intel_framebuffer *intel_fb;
5547 struct intel_crtc *intel_crtc;
5548
5549 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5550 return;
5551
5552 if (!dev_priv->busy)
5553 dev_priv->busy = true;
5554 else
5555 mod_timer(&dev_priv->idle_timer, jiffies +
5556 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5557
5558 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5559 if (!crtc->fb)
5560 continue;
5561
5562 intel_crtc = to_intel_crtc(crtc);
5563 intel_fb = to_intel_framebuffer(crtc->fb);
5564 if (intel_fb->obj == obj) {
5565 if (!intel_crtc->busy) {
5566 /* Non-busy -> busy, upclock */
5567 intel_increase_pllclock(crtc);
5568 intel_crtc->busy = true;
5569 } else {
5570 /* Busy -> busy, put off timer */
5571 mod_timer(&intel_crtc->idle_timer, jiffies +
5572 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5573 }
5574 }
5575 }
5576 }
5577
5578 static void intel_crtc_destroy(struct drm_crtc *crtc)
5579 {
5580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5581 struct drm_device *dev = crtc->dev;
5582 struct intel_unpin_work *work;
5583 unsigned long flags;
5584
5585 spin_lock_irqsave(&dev->event_lock, flags);
5586 work = intel_crtc->unpin_work;
5587 intel_crtc->unpin_work = NULL;
5588 spin_unlock_irqrestore(&dev->event_lock, flags);
5589
5590 if (work) {
5591 cancel_work_sync(&work->work);
5592 kfree(work);
5593 }
5594
5595 drm_crtc_cleanup(crtc);
5596
5597 kfree(intel_crtc);
5598 }
5599
5600 static void intel_unpin_work_fn(struct work_struct *__work)
5601 {
5602 struct intel_unpin_work *work =
5603 container_of(__work, struct intel_unpin_work, work);
5604
5605 mutex_lock(&work->dev->struct_mutex);
5606 intel_unpin_fb_obj(work->old_fb_obj);
5607 drm_gem_object_unreference(&work->pending_flip_obj->base);
5608 drm_gem_object_unreference(&work->old_fb_obj->base);
5609
5610 intel_update_fbc(work->dev);
5611 mutex_unlock(&work->dev->struct_mutex);
5612 kfree(work);
5613 }
5614
5615 static void do_intel_finish_page_flip(struct drm_device *dev,
5616 struct drm_crtc *crtc)
5617 {
5618 drm_i915_private_t *dev_priv = dev->dev_private;
5619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5620 struct intel_unpin_work *work;
5621 struct drm_i915_gem_object *obj;
5622 struct drm_pending_vblank_event *e;
5623 struct timeval tnow, tvbl;
5624 unsigned long flags;
5625
5626 /* Ignore early vblank irqs */
5627 if (intel_crtc == NULL)
5628 return;
5629
5630 do_gettimeofday(&tnow);
5631
5632 spin_lock_irqsave(&dev->event_lock, flags);
5633 work = intel_crtc->unpin_work;
5634 if (work == NULL || !work->pending) {
5635 spin_unlock_irqrestore(&dev->event_lock, flags);
5636 return;
5637 }
5638
5639 intel_crtc->unpin_work = NULL;
5640
5641 if (work->event) {
5642 e = work->event;
5643 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5644
5645 /* Called before vblank count and timestamps have
5646 * been updated for the vblank interval of flip
5647 * completion? Need to increment vblank count and
5648 * add one videorefresh duration to returned timestamp
5649 * to account for this. We assume this happened if we
5650 * get called over 0.9 frame durations after the last
5651 * timestamped vblank.
5652 *
5653 * This calculation can not be used with vrefresh rates
5654 * below 5Hz (10Hz to be on the safe side) without
5655 * promoting to 64 integers.
5656 */
5657 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5658 9 * crtc->framedur_ns) {
5659 e->event.sequence++;
5660 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5661 crtc->framedur_ns);
5662 }
5663
5664 e->event.tv_sec = tvbl.tv_sec;
5665 e->event.tv_usec = tvbl.tv_usec;
5666
5667 list_add_tail(&e->base.link,
5668 &e->base.file_priv->event_list);
5669 wake_up_interruptible(&e->base.file_priv->event_wait);
5670 }
5671
5672 drm_vblank_put(dev, intel_crtc->pipe);
5673
5674 spin_unlock_irqrestore(&dev->event_lock, flags);
5675
5676 obj = work->old_fb_obj;
5677
5678 atomic_clear_mask(1 << intel_crtc->plane,
5679 &obj->pending_flip.counter);
5680 if (atomic_read(&obj->pending_flip) == 0)
5681 wake_up(&dev_priv->pending_flip_queue);
5682
5683 schedule_work(&work->work);
5684
5685 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5686 }
5687
5688 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5689 {
5690 drm_i915_private_t *dev_priv = dev->dev_private;
5691 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5692
5693 do_intel_finish_page_flip(dev, crtc);
5694 }
5695
5696 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5697 {
5698 drm_i915_private_t *dev_priv = dev->dev_private;
5699 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5700
5701 do_intel_finish_page_flip(dev, crtc);
5702 }
5703
5704 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5705 {
5706 drm_i915_private_t *dev_priv = dev->dev_private;
5707 struct intel_crtc *intel_crtc =
5708 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5709 unsigned long flags;
5710
5711 spin_lock_irqsave(&dev->event_lock, flags);
5712 if (intel_crtc->unpin_work) {
5713 if ((++intel_crtc->unpin_work->pending) > 1)
5714 DRM_ERROR("Prepared flip multiple times\n");
5715 } else {
5716 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5717 }
5718 spin_unlock_irqrestore(&dev->event_lock, flags);
5719 }
5720
5721 static int intel_gen2_queue_flip(struct drm_device *dev,
5722 struct drm_crtc *crtc,
5723 struct drm_framebuffer *fb,
5724 struct drm_i915_gem_object *obj)
5725 {
5726 struct drm_i915_private *dev_priv = dev->dev_private;
5727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5728 unsigned long offset;
5729 u32 flip_mask;
5730 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5731 int ret;
5732
5733 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5734 if (ret)
5735 goto err;
5736
5737 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5738 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5739
5740 ret = intel_ring_begin(ring, 6);
5741 if (ret)
5742 goto err_unpin;
5743
5744 /* Can't queue multiple flips, so wait for the previous
5745 * one to finish before executing the next.
5746 */
5747 if (intel_crtc->plane)
5748 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5749 else
5750 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5751 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5752 intel_ring_emit(ring, MI_NOOP);
5753 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5754 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5755 intel_ring_emit(ring, fb->pitches[0]);
5756 intel_ring_emit(ring, obj->gtt_offset + offset);
5757 intel_ring_emit(ring, 0); /* aux display base address, unused */
5758 intel_ring_advance(ring);
5759 return 0;
5760
5761 err_unpin:
5762 intel_unpin_fb_obj(obj);
5763 err:
5764 return ret;
5765 }
5766
5767 static int intel_gen3_queue_flip(struct drm_device *dev,
5768 struct drm_crtc *crtc,
5769 struct drm_framebuffer *fb,
5770 struct drm_i915_gem_object *obj)
5771 {
5772 struct drm_i915_private *dev_priv = dev->dev_private;
5773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5774 unsigned long offset;
5775 u32 flip_mask;
5776 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5777 int ret;
5778
5779 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5780 if (ret)
5781 goto err;
5782
5783 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5784 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5785
5786 ret = intel_ring_begin(ring, 6);
5787 if (ret)
5788 goto err_unpin;
5789
5790 if (intel_crtc->plane)
5791 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5792 else
5793 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5794 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5795 intel_ring_emit(ring, MI_NOOP);
5796 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5797 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5798 intel_ring_emit(ring, fb->pitches[0]);
5799 intel_ring_emit(ring, obj->gtt_offset + offset);
5800 intel_ring_emit(ring, MI_NOOP);
5801
5802 intel_ring_advance(ring);
5803 return 0;
5804
5805 err_unpin:
5806 intel_unpin_fb_obj(obj);
5807 err:
5808 return ret;
5809 }
5810
5811 static int intel_gen4_queue_flip(struct drm_device *dev,
5812 struct drm_crtc *crtc,
5813 struct drm_framebuffer *fb,
5814 struct drm_i915_gem_object *obj)
5815 {
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5818 uint32_t pf, pipesrc;
5819 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5820 int ret;
5821
5822 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5823 if (ret)
5824 goto err;
5825
5826 ret = intel_ring_begin(ring, 4);
5827 if (ret)
5828 goto err_unpin;
5829
5830 /* i965+ uses the linear or tiled offsets from the
5831 * Display Registers (which do not change across a page-flip)
5832 * so we need only reprogram the base address.
5833 */
5834 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5835 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5836 intel_ring_emit(ring, fb->pitches[0]);
5837 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
5838
5839 /* XXX Enabling the panel-fitter across page-flip is so far
5840 * untested on non-native modes, so ignore it for now.
5841 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5842 */
5843 pf = 0;
5844 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5845 intel_ring_emit(ring, pf | pipesrc);
5846 intel_ring_advance(ring);
5847 return 0;
5848
5849 err_unpin:
5850 intel_unpin_fb_obj(obj);
5851 err:
5852 return ret;
5853 }
5854
5855 static int intel_gen6_queue_flip(struct drm_device *dev,
5856 struct drm_crtc *crtc,
5857 struct drm_framebuffer *fb,
5858 struct drm_i915_gem_object *obj)
5859 {
5860 struct drm_i915_private *dev_priv = dev->dev_private;
5861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5862 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5863 uint32_t pf, pipesrc;
5864 int ret;
5865
5866 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5867 if (ret)
5868 goto err;
5869
5870 ret = intel_ring_begin(ring, 4);
5871 if (ret)
5872 goto err_unpin;
5873
5874 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5875 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5876 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5877 intel_ring_emit(ring, obj->gtt_offset);
5878
5879 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5880 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5881 intel_ring_emit(ring, pf | pipesrc);
5882 intel_ring_advance(ring);
5883 return 0;
5884
5885 err_unpin:
5886 intel_unpin_fb_obj(obj);
5887 err:
5888 return ret;
5889 }
5890
5891 /*
5892 * On gen7 we currently use the blit ring because (in early silicon at least)
5893 * the render ring doesn't give us interrpts for page flip completion, which
5894 * means clients will hang after the first flip is queued. Fortunately the
5895 * blit ring generates interrupts properly, so use it instead.
5896 */
5897 static int intel_gen7_queue_flip(struct drm_device *dev,
5898 struct drm_crtc *crtc,
5899 struct drm_framebuffer *fb,
5900 struct drm_i915_gem_object *obj)
5901 {
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5904 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5905 int ret;
5906
5907 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5908 if (ret)
5909 goto err;
5910
5911 ret = intel_ring_begin(ring, 4);
5912 if (ret)
5913 goto err_unpin;
5914
5915 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5916 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5917 intel_ring_emit(ring, (obj->gtt_offset));
5918 intel_ring_emit(ring, (MI_NOOP));
5919 intel_ring_advance(ring);
5920 return 0;
5921
5922 err_unpin:
5923 intel_unpin_fb_obj(obj);
5924 err:
5925 return ret;
5926 }
5927
5928 static int intel_default_queue_flip(struct drm_device *dev,
5929 struct drm_crtc *crtc,
5930 struct drm_framebuffer *fb,
5931 struct drm_i915_gem_object *obj)
5932 {
5933 return -ENODEV;
5934 }
5935
5936 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5937 struct drm_framebuffer *fb,
5938 struct drm_pending_vblank_event *event)
5939 {
5940 struct drm_device *dev = crtc->dev;
5941 struct drm_i915_private *dev_priv = dev->dev_private;
5942 struct intel_framebuffer *intel_fb;
5943 struct drm_i915_gem_object *obj;
5944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5945 struct intel_unpin_work *work;
5946 unsigned long flags;
5947 int ret;
5948
5949 work = kzalloc(sizeof *work, GFP_KERNEL);
5950 if (work == NULL)
5951 return -ENOMEM;
5952
5953 work->event = event;
5954 work->dev = crtc->dev;
5955 intel_fb = to_intel_framebuffer(crtc->fb);
5956 work->old_fb_obj = intel_fb->obj;
5957 INIT_WORK(&work->work, intel_unpin_work_fn);
5958
5959 ret = drm_vblank_get(dev, intel_crtc->pipe);
5960 if (ret)
5961 goto free_work;
5962
5963 /* We borrow the event spin lock for protecting unpin_work */
5964 spin_lock_irqsave(&dev->event_lock, flags);
5965 if (intel_crtc->unpin_work) {
5966 spin_unlock_irqrestore(&dev->event_lock, flags);
5967 kfree(work);
5968 drm_vblank_put(dev, intel_crtc->pipe);
5969
5970 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5971 return -EBUSY;
5972 }
5973 intel_crtc->unpin_work = work;
5974 spin_unlock_irqrestore(&dev->event_lock, flags);
5975
5976 intel_fb = to_intel_framebuffer(fb);
5977 obj = intel_fb->obj;
5978
5979 mutex_lock(&dev->struct_mutex);
5980
5981 /* Reference the objects for the scheduled work. */
5982 drm_gem_object_reference(&work->old_fb_obj->base);
5983 drm_gem_object_reference(&obj->base);
5984
5985 crtc->fb = fb;
5986
5987 work->pending_flip_obj = obj;
5988
5989 work->enable_stall_check = true;
5990
5991 /* Block clients from rendering to the new back buffer until
5992 * the flip occurs and the object is no longer visible.
5993 */
5994 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5995
5996 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5997 if (ret)
5998 goto cleanup_pending;
5999
6000 intel_disable_fbc(dev);
6001 mutex_unlock(&dev->struct_mutex);
6002
6003 trace_i915_flip_request(intel_crtc->plane, obj);
6004
6005 return 0;
6006
6007 cleanup_pending:
6008 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6009 drm_gem_object_unreference(&work->old_fb_obj->base);
6010 drm_gem_object_unreference(&obj->base);
6011 mutex_unlock(&dev->struct_mutex);
6012
6013 spin_lock_irqsave(&dev->event_lock, flags);
6014 intel_crtc->unpin_work = NULL;
6015 spin_unlock_irqrestore(&dev->event_lock, flags);
6016
6017 drm_vblank_put(dev, intel_crtc->pipe);
6018 free_work:
6019 kfree(work);
6020
6021 return ret;
6022 }
6023
6024 static void intel_sanitize_modesetting(struct drm_device *dev,
6025 int pipe, int plane)
6026 {
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028 u32 reg, val;
6029
6030 /* Clear any frame start delays used for debugging left by the BIOS */
6031 for_each_pipe(pipe) {
6032 reg = PIPECONF(pipe);
6033 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6034 }
6035
6036 if (HAS_PCH_SPLIT(dev))
6037 return;
6038
6039 /* Who knows what state these registers were left in by the BIOS or
6040 * grub?
6041 *
6042 * If we leave the registers in a conflicting state (e.g. with the
6043 * display plane reading from the other pipe than the one we intend
6044 * to use) then when we attempt to teardown the active mode, we will
6045 * not disable the pipes and planes in the correct order -- leaving
6046 * a plane reading from a disabled pipe and possibly leading to
6047 * undefined behaviour.
6048 */
6049
6050 reg = DSPCNTR(plane);
6051 val = I915_READ(reg);
6052
6053 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6054 return;
6055 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6056 return;
6057
6058 /* This display plane is active and attached to the other CPU pipe. */
6059 pipe = !pipe;
6060
6061 /* Disable the plane and wait for it to stop reading from the pipe. */
6062 intel_disable_plane(dev_priv, plane, pipe);
6063 intel_disable_pipe(dev_priv, pipe);
6064 }
6065
6066 static void intel_crtc_reset(struct drm_crtc *crtc)
6067 {
6068 struct drm_device *dev = crtc->dev;
6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070
6071 /* Reset flags back to the 'unknown' status so that they
6072 * will be correctly set on the initial modeset.
6073 */
6074 intel_crtc->dpms_mode = -1;
6075
6076 /* We need to fix up any BIOS configuration that conflicts with
6077 * our expectations.
6078 */
6079 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6080 }
6081
6082 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6083 .dpms = intel_crtc_dpms,
6084 .mode_fixup = intel_crtc_mode_fixup,
6085 .mode_set = intel_crtc_mode_set,
6086 .mode_set_base = intel_pipe_set_base,
6087 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6088 .load_lut = intel_crtc_load_lut,
6089 .disable = intel_crtc_disable,
6090 };
6091
6092 static const struct drm_crtc_funcs intel_crtc_funcs = {
6093 .reset = intel_crtc_reset,
6094 .cursor_set = intel_crtc_cursor_set,
6095 .cursor_move = intel_crtc_cursor_move,
6096 .gamma_set = intel_crtc_gamma_set,
6097 .set_config = drm_crtc_helper_set_config,
6098 .destroy = intel_crtc_destroy,
6099 .page_flip = intel_crtc_page_flip,
6100 };
6101
6102 static void intel_pch_pll_init(struct drm_device *dev)
6103 {
6104 drm_i915_private_t *dev_priv = dev->dev_private;
6105 int i;
6106
6107 if (dev_priv->num_pch_pll == 0) {
6108 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6109 return;
6110 }
6111
6112 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6113 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6114 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6115 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6116 }
6117 }
6118
6119 static void intel_crtc_init(struct drm_device *dev, int pipe)
6120 {
6121 drm_i915_private_t *dev_priv = dev->dev_private;
6122 struct intel_crtc *intel_crtc;
6123 int i;
6124
6125 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6126 if (intel_crtc == NULL)
6127 return;
6128
6129 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6130
6131 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6132 for (i = 0; i < 256; i++) {
6133 intel_crtc->lut_r[i] = i;
6134 intel_crtc->lut_g[i] = i;
6135 intel_crtc->lut_b[i] = i;
6136 }
6137
6138 /* Swap pipes & planes for FBC on pre-965 */
6139 intel_crtc->pipe = pipe;
6140 intel_crtc->plane = pipe;
6141 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6142 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6143 intel_crtc->plane = !pipe;
6144 }
6145
6146 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6147 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6148 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6149 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6150
6151 intel_crtc_reset(&intel_crtc->base);
6152 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6153 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6154
6155 if (HAS_PCH_SPLIT(dev)) {
6156 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6157 intel_helper_funcs.commit = ironlake_crtc_commit;
6158 } else {
6159 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6160 intel_helper_funcs.commit = i9xx_crtc_commit;
6161 }
6162
6163 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6164
6165 intel_crtc->busy = false;
6166
6167 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6168 (unsigned long)intel_crtc);
6169 }
6170
6171 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6172 struct drm_file *file)
6173 {
6174 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6175 struct drm_mode_object *drmmode_obj;
6176 struct intel_crtc *crtc;
6177
6178 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6179 return -ENODEV;
6180
6181 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6182 DRM_MODE_OBJECT_CRTC);
6183
6184 if (!drmmode_obj) {
6185 DRM_ERROR("no such CRTC id\n");
6186 return -EINVAL;
6187 }
6188
6189 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6190 pipe_from_crtc_id->pipe = crtc->pipe;
6191
6192 return 0;
6193 }
6194
6195 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6196 {
6197 struct intel_encoder *encoder;
6198 int index_mask = 0;
6199 int entry = 0;
6200
6201 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6202 if (type_mask & encoder->clone_mask)
6203 index_mask |= (1 << entry);
6204 entry++;
6205 }
6206
6207 return index_mask;
6208 }
6209
6210 static bool has_edp_a(struct drm_device *dev)
6211 {
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213
6214 if (!IS_MOBILE(dev))
6215 return false;
6216
6217 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6218 return false;
6219
6220 if (IS_GEN5(dev) &&
6221 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6222 return false;
6223
6224 return true;
6225 }
6226
6227 static void intel_setup_outputs(struct drm_device *dev)
6228 {
6229 struct drm_i915_private *dev_priv = dev->dev_private;
6230 struct intel_encoder *encoder;
6231 bool dpd_is_edp = false;
6232 bool has_lvds;
6233
6234 has_lvds = intel_lvds_init(dev);
6235 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6236 /* disable the panel fitter on everything but LVDS */
6237 I915_WRITE(PFIT_CONTROL, 0);
6238 }
6239
6240 if (HAS_PCH_SPLIT(dev)) {
6241 dpd_is_edp = intel_dpd_is_edp(dev);
6242
6243 if (has_edp_a(dev))
6244 intel_dp_init(dev, DP_A);
6245
6246 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6247 intel_dp_init(dev, PCH_DP_D);
6248 }
6249
6250 intel_crt_init(dev);
6251
6252 if (HAS_PCH_SPLIT(dev)) {
6253 int found;
6254
6255 if (I915_READ(HDMIB) & PORT_DETECTED) {
6256 /* PCH SDVOB multiplex with HDMIB */
6257 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6258 if (!found)
6259 intel_hdmi_init(dev, HDMIB);
6260 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6261 intel_dp_init(dev, PCH_DP_B);
6262 }
6263
6264 if (I915_READ(HDMIC) & PORT_DETECTED)
6265 intel_hdmi_init(dev, HDMIC);
6266
6267 if (I915_READ(HDMID) & PORT_DETECTED)
6268 intel_hdmi_init(dev, HDMID);
6269
6270 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6271 intel_dp_init(dev, PCH_DP_C);
6272
6273 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6274 intel_dp_init(dev, PCH_DP_D);
6275
6276 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6277 bool found = false;
6278
6279 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6280 DRM_DEBUG_KMS("probing SDVOB\n");
6281 found = intel_sdvo_init(dev, SDVOB, true);
6282 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6283 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6284 intel_hdmi_init(dev, SDVOB);
6285 }
6286
6287 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6288 DRM_DEBUG_KMS("probing DP_B\n");
6289 intel_dp_init(dev, DP_B);
6290 }
6291 }
6292
6293 /* Before G4X SDVOC doesn't have its own detect register */
6294
6295 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6296 DRM_DEBUG_KMS("probing SDVOC\n");
6297 found = intel_sdvo_init(dev, SDVOC, false);
6298 }
6299
6300 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6301
6302 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6303 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6304 intel_hdmi_init(dev, SDVOC);
6305 }
6306 if (SUPPORTS_INTEGRATED_DP(dev)) {
6307 DRM_DEBUG_KMS("probing DP_C\n");
6308 intel_dp_init(dev, DP_C);
6309 }
6310 }
6311
6312 if (SUPPORTS_INTEGRATED_DP(dev) &&
6313 (I915_READ(DP_D) & DP_DETECTED)) {
6314 DRM_DEBUG_KMS("probing DP_D\n");
6315 intel_dp_init(dev, DP_D);
6316 }
6317 } else if (IS_GEN2(dev))
6318 intel_dvo_init(dev);
6319
6320 if (SUPPORTS_TV(dev))
6321 intel_tv_init(dev);
6322
6323 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6324 encoder->base.possible_crtcs = encoder->crtc_mask;
6325 encoder->base.possible_clones =
6326 intel_encoder_clones(dev, encoder->clone_mask);
6327 }
6328
6329 /* disable all the possible outputs/crtcs before entering KMS mode */
6330 drm_helper_disable_unused_functions(dev);
6331
6332 if (HAS_PCH_SPLIT(dev))
6333 ironlake_init_pch_refclk(dev);
6334 }
6335
6336 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6337 {
6338 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6339
6340 drm_framebuffer_cleanup(fb);
6341 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6342
6343 kfree(intel_fb);
6344 }
6345
6346 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6347 struct drm_file *file,
6348 unsigned int *handle)
6349 {
6350 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6351 struct drm_i915_gem_object *obj = intel_fb->obj;
6352
6353 return drm_gem_handle_create(file, &obj->base, handle);
6354 }
6355
6356 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6357 .destroy = intel_user_framebuffer_destroy,
6358 .create_handle = intel_user_framebuffer_create_handle,
6359 };
6360
6361 int intel_framebuffer_init(struct drm_device *dev,
6362 struct intel_framebuffer *intel_fb,
6363 struct drm_mode_fb_cmd2 *mode_cmd,
6364 struct drm_i915_gem_object *obj)
6365 {
6366 int ret;
6367
6368 if (obj->tiling_mode == I915_TILING_Y)
6369 return -EINVAL;
6370
6371 if (mode_cmd->pitches[0] & 63)
6372 return -EINVAL;
6373
6374 switch (mode_cmd->pixel_format) {
6375 case DRM_FORMAT_RGB332:
6376 case DRM_FORMAT_RGB565:
6377 case DRM_FORMAT_XRGB8888:
6378 case DRM_FORMAT_XBGR8888:
6379 case DRM_FORMAT_ARGB8888:
6380 case DRM_FORMAT_XRGB2101010:
6381 case DRM_FORMAT_ARGB2101010:
6382 /* RGB formats are common across chipsets */
6383 break;
6384 case DRM_FORMAT_YUYV:
6385 case DRM_FORMAT_UYVY:
6386 case DRM_FORMAT_YVYU:
6387 case DRM_FORMAT_VYUY:
6388 break;
6389 default:
6390 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6391 mode_cmd->pixel_format);
6392 return -EINVAL;
6393 }
6394
6395 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6396 if (ret) {
6397 DRM_ERROR("framebuffer init failed %d\n", ret);
6398 return ret;
6399 }
6400
6401 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6402 intel_fb->obj = obj;
6403 return 0;
6404 }
6405
6406 static struct drm_framebuffer *
6407 intel_user_framebuffer_create(struct drm_device *dev,
6408 struct drm_file *filp,
6409 struct drm_mode_fb_cmd2 *mode_cmd)
6410 {
6411 struct drm_i915_gem_object *obj;
6412
6413 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6414 mode_cmd->handles[0]));
6415 if (&obj->base == NULL)
6416 return ERR_PTR(-ENOENT);
6417
6418 return intel_framebuffer_create(dev, mode_cmd, obj);
6419 }
6420
6421 static const struct drm_mode_config_funcs intel_mode_funcs = {
6422 .fb_create = intel_user_framebuffer_create,
6423 .output_poll_changed = intel_fb_output_poll_changed,
6424 };
6425
6426 /* Set up chip specific display functions */
6427 static void intel_init_display(struct drm_device *dev)
6428 {
6429 struct drm_i915_private *dev_priv = dev->dev_private;
6430
6431 /* We always want a DPMS function */
6432 if (HAS_PCH_SPLIT(dev)) {
6433 dev_priv->display.dpms = ironlake_crtc_dpms;
6434 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6435 dev_priv->display.off = ironlake_crtc_off;
6436 dev_priv->display.update_plane = ironlake_update_plane;
6437 } else {
6438 dev_priv->display.dpms = i9xx_crtc_dpms;
6439 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6440 dev_priv->display.off = i9xx_crtc_off;
6441 dev_priv->display.update_plane = i9xx_update_plane;
6442 }
6443
6444 /* Returns the core display clock speed */
6445 if (IS_VALLEYVIEW(dev))
6446 dev_priv->display.get_display_clock_speed =
6447 valleyview_get_display_clock_speed;
6448 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6449 dev_priv->display.get_display_clock_speed =
6450 i945_get_display_clock_speed;
6451 else if (IS_I915G(dev))
6452 dev_priv->display.get_display_clock_speed =
6453 i915_get_display_clock_speed;
6454 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6455 dev_priv->display.get_display_clock_speed =
6456 i9xx_misc_get_display_clock_speed;
6457 else if (IS_I915GM(dev))
6458 dev_priv->display.get_display_clock_speed =
6459 i915gm_get_display_clock_speed;
6460 else if (IS_I865G(dev))
6461 dev_priv->display.get_display_clock_speed =
6462 i865_get_display_clock_speed;
6463 else if (IS_I85X(dev))
6464 dev_priv->display.get_display_clock_speed =
6465 i855_get_display_clock_speed;
6466 else /* 852, 830 */
6467 dev_priv->display.get_display_clock_speed =
6468 i830_get_display_clock_speed;
6469
6470 if (HAS_PCH_SPLIT(dev)) {
6471 if (IS_GEN5(dev)) {
6472 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6473 dev_priv->display.write_eld = ironlake_write_eld;
6474 } else if (IS_GEN6(dev)) {
6475 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6476 dev_priv->display.write_eld = ironlake_write_eld;
6477 } else if (IS_IVYBRIDGE(dev)) {
6478 /* FIXME: detect B0+ stepping and use auto training */
6479 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6480 dev_priv->display.write_eld = ironlake_write_eld;
6481 } else
6482 dev_priv->display.update_wm = NULL;
6483 } else if (IS_VALLEYVIEW(dev)) {
6484 dev_priv->display.force_wake_get = vlv_force_wake_get;
6485 dev_priv->display.force_wake_put = vlv_force_wake_put;
6486 } else if (IS_G4X(dev)) {
6487 dev_priv->display.write_eld = g4x_write_eld;
6488 }
6489
6490 /* Default just returns -ENODEV to indicate unsupported */
6491 dev_priv->display.queue_flip = intel_default_queue_flip;
6492
6493 switch (INTEL_INFO(dev)->gen) {
6494 case 2:
6495 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6496 break;
6497
6498 case 3:
6499 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6500 break;
6501
6502 case 4:
6503 case 5:
6504 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6505 break;
6506
6507 case 6:
6508 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6509 break;
6510 case 7:
6511 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6512 break;
6513 }
6514 }
6515
6516 /*
6517 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6518 * resume, or other times. This quirk makes sure that's the case for
6519 * affected systems.
6520 */
6521 static void quirk_pipea_force(struct drm_device *dev)
6522 {
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524
6525 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6526 DRM_INFO("applying pipe a force quirk\n");
6527 }
6528
6529 /*
6530 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6531 */
6532 static void quirk_ssc_force_disable(struct drm_device *dev)
6533 {
6534 struct drm_i915_private *dev_priv = dev->dev_private;
6535 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6536 DRM_INFO("applying lvds SSC disable quirk\n");
6537 }
6538
6539 /*
6540 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6541 * brightness value
6542 */
6543 static void quirk_invert_brightness(struct drm_device *dev)
6544 {
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6547 DRM_INFO("applying inverted panel brightness quirk\n");
6548 }
6549
6550 struct intel_quirk {
6551 int device;
6552 int subsystem_vendor;
6553 int subsystem_device;
6554 void (*hook)(struct drm_device *dev);
6555 };
6556
6557 static struct intel_quirk intel_quirks[] = {
6558 /* HP Mini needs pipe A force quirk (LP: #322104) */
6559 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6560
6561 /* Thinkpad R31 needs pipe A force quirk */
6562 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6563 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6564 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6565
6566 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6567 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6568 /* ThinkPad X40 needs pipe A force quirk */
6569
6570 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6571 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6572
6573 /* 855 & before need to leave pipe A & dpll A up */
6574 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6575 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6576
6577 /* Lenovo U160 cannot use SSC on LVDS */
6578 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6579
6580 /* Sony Vaio Y cannot use SSC on LVDS */
6581 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6582
6583 /* Acer Aspire 5734Z must invert backlight brightness */
6584 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6585 };
6586
6587 static void intel_init_quirks(struct drm_device *dev)
6588 {
6589 struct pci_dev *d = dev->pdev;
6590 int i;
6591
6592 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6593 struct intel_quirk *q = &intel_quirks[i];
6594
6595 if (d->device == q->device &&
6596 (d->subsystem_vendor == q->subsystem_vendor ||
6597 q->subsystem_vendor == PCI_ANY_ID) &&
6598 (d->subsystem_device == q->subsystem_device ||
6599 q->subsystem_device == PCI_ANY_ID))
6600 q->hook(dev);
6601 }
6602 }
6603
6604 /* Disable the VGA plane that we never use */
6605 static void i915_disable_vga(struct drm_device *dev)
6606 {
6607 struct drm_i915_private *dev_priv = dev->dev_private;
6608 u8 sr1;
6609 u32 vga_reg;
6610
6611 if (HAS_PCH_SPLIT(dev))
6612 vga_reg = CPU_VGACNTRL;
6613 else
6614 vga_reg = VGACNTRL;
6615
6616 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6617 outb(SR01, VGA_SR_INDEX);
6618 sr1 = inb(VGA_SR_DATA);
6619 outb(sr1 | 1<<5, VGA_SR_DATA);
6620 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6621 udelay(300);
6622
6623 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6624 POSTING_READ(vga_reg);
6625 }
6626
6627 static void ivb_pch_pwm_override(struct drm_device *dev)
6628 {
6629 struct drm_i915_private *dev_priv = dev->dev_private;
6630
6631 /*
6632 * IVB has CPU eDP backlight regs too, set things up to let the
6633 * PCH regs control the backlight
6634 */
6635 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6636 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6637 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6638 }
6639
6640 void intel_modeset_init_hw(struct drm_device *dev)
6641 {
6642 struct drm_i915_private *dev_priv = dev->dev_private;
6643
6644 intel_init_clock_gating(dev);
6645
6646 if (IS_IRONLAKE_M(dev)) {
6647 ironlake_enable_drps(dev);
6648 intel_init_emon(dev);
6649 }
6650
6651 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6652 gen6_enable_rps(dev_priv);
6653 gen6_update_ring_freq(dev_priv);
6654 }
6655
6656 if (IS_IVYBRIDGE(dev))
6657 ivb_pch_pwm_override(dev);
6658 }
6659
6660 void intel_modeset_init(struct drm_device *dev)
6661 {
6662 struct drm_i915_private *dev_priv = dev->dev_private;
6663 int i, ret;
6664
6665 drm_mode_config_init(dev);
6666
6667 dev->mode_config.min_width = 0;
6668 dev->mode_config.min_height = 0;
6669
6670 dev->mode_config.preferred_depth = 24;
6671 dev->mode_config.prefer_shadow = 1;
6672
6673 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6674
6675 intel_init_quirks(dev);
6676
6677 intel_init_pm(dev);
6678
6679 intel_init_display(dev);
6680
6681 if (IS_GEN2(dev)) {
6682 dev->mode_config.max_width = 2048;
6683 dev->mode_config.max_height = 2048;
6684 } else if (IS_GEN3(dev)) {
6685 dev->mode_config.max_width = 4096;
6686 dev->mode_config.max_height = 4096;
6687 } else {
6688 dev->mode_config.max_width = 8192;
6689 dev->mode_config.max_height = 8192;
6690 }
6691 dev->mode_config.fb_base = dev->agp->base;
6692
6693 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6694 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6695
6696 for (i = 0; i < dev_priv->num_pipe; i++) {
6697 intel_crtc_init(dev, i);
6698 ret = intel_plane_init(dev, i);
6699 if (ret)
6700 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6701 }
6702
6703 intel_pch_pll_init(dev);
6704
6705 /* Just disable it once at startup */
6706 i915_disable_vga(dev);
6707 intel_setup_outputs(dev);
6708
6709 intel_modeset_init_hw(dev);
6710
6711 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6712 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6713 (unsigned long)dev);
6714 }
6715
6716 void intel_modeset_gem_init(struct drm_device *dev)
6717 {
6718 if (IS_IRONLAKE_M(dev))
6719 ironlake_enable_rc6(dev);
6720
6721 intel_setup_overlay(dev);
6722 }
6723
6724 void intel_modeset_cleanup(struct drm_device *dev)
6725 {
6726 struct drm_i915_private *dev_priv = dev->dev_private;
6727 struct drm_crtc *crtc;
6728 struct intel_crtc *intel_crtc;
6729
6730 drm_kms_helper_poll_fini(dev);
6731 mutex_lock(&dev->struct_mutex);
6732
6733 intel_unregister_dsm_handler();
6734
6735
6736 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6737 /* Skip inactive CRTCs */
6738 if (!crtc->fb)
6739 continue;
6740
6741 intel_crtc = to_intel_crtc(crtc);
6742 intel_increase_pllclock(crtc);
6743 }
6744
6745 intel_disable_fbc(dev);
6746
6747 if (IS_IRONLAKE_M(dev))
6748 ironlake_disable_drps(dev);
6749 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6750 gen6_disable_rps(dev);
6751
6752 if (IS_IRONLAKE_M(dev))
6753 ironlake_disable_rc6(dev);
6754
6755 if (IS_VALLEYVIEW(dev))
6756 vlv_init_dpio(dev);
6757
6758 mutex_unlock(&dev->struct_mutex);
6759
6760 /* Disable the irq before mode object teardown, for the irq might
6761 * enqueue unpin/hotplug work. */
6762 drm_irq_uninstall(dev);
6763 cancel_work_sync(&dev_priv->hotplug_work);
6764 cancel_work_sync(&dev_priv->rps_work);
6765
6766 /* flush any delayed tasks or pending work */
6767 flush_scheduled_work();
6768
6769 /* Shut off idle work before the crtcs get freed. */
6770 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6771 intel_crtc = to_intel_crtc(crtc);
6772 del_timer_sync(&intel_crtc->idle_timer);
6773 }
6774 del_timer_sync(&dev_priv->idle_timer);
6775 cancel_work_sync(&dev_priv->idle_work);
6776
6777 drm_mode_config_cleanup(dev);
6778 }
6779
6780 /*
6781 * Return which encoder is currently attached for connector.
6782 */
6783 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6784 {
6785 return &intel_attached_encoder(connector)->base;
6786 }
6787
6788 void intel_connector_attach_encoder(struct intel_connector *connector,
6789 struct intel_encoder *encoder)
6790 {
6791 connector->encoder = encoder;
6792 drm_mode_connector_attach_encoder(&connector->base,
6793 &encoder->base);
6794 }
6795
6796 /*
6797 * set vga decode state - true == enable VGA decode
6798 */
6799 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6800 {
6801 struct drm_i915_private *dev_priv = dev->dev_private;
6802 u16 gmch_ctrl;
6803
6804 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6805 if (state)
6806 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6807 else
6808 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6809 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6810 return 0;
6811 }
6812
6813 #ifdef CONFIG_DEBUG_FS
6814 #include <linux/seq_file.h>
6815
6816 struct intel_display_error_state {
6817 struct intel_cursor_error_state {
6818 u32 control;
6819 u32 position;
6820 u32 base;
6821 u32 size;
6822 } cursor[2];
6823
6824 struct intel_pipe_error_state {
6825 u32 conf;
6826 u32 source;
6827
6828 u32 htotal;
6829 u32 hblank;
6830 u32 hsync;
6831 u32 vtotal;
6832 u32 vblank;
6833 u32 vsync;
6834 } pipe[2];
6835
6836 struct intel_plane_error_state {
6837 u32 control;
6838 u32 stride;
6839 u32 size;
6840 u32 pos;
6841 u32 addr;
6842 u32 surface;
6843 u32 tile_offset;
6844 } plane[2];
6845 };
6846
6847 struct intel_display_error_state *
6848 intel_display_capture_error_state(struct drm_device *dev)
6849 {
6850 drm_i915_private_t *dev_priv = dev->dev_private;
6851 struct intel_display_error_state *error;
6852 int i;
6853
6854 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6855 if (error == NULL)
6856 return NULL;
6857
6858 for (i = 0; i < 2; i++) {
6859 error->cursor[i].control = I915_READ(CURCNTR(i));
6860 error->cursor[i].position = I915_READ(CURPOS(i));
6861 error->cursor[i].base = I915_READ(CURBASE(i));
6862
6863 error->plane[i].control = I915_READ(DSPCNTR(i));
6864 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6865 error->plane[i].size = I915_READ(DSPSIZE(i));
6866 error->plane[i].pos = I915_READ(DSPPOS(i));
6867 error->plane[i].addr = I915_READ(DSPADDR(i));
6868 if (INTEL_INFO(dev)->gen >= 4) {
6869 error->plane[i].surface = I915_READ(DSPSURF(i));
6870 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6871 }
6872
6873 error->pipe[i].conf = I915_READ(PIPECONF(i));
6874 error->pipe[i].source = I915_READ(PIPESRC(i));
6875 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6876 error->pipe[i].hblank = I915_READ(HBLANK(i));
6877 error->pipe[i].hsync = I915_READ(HSYNC(i));
6878 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6879 error->pipe[i].vblank = I915_READ(VBLANK(i));
6880 error->pipe[i].vsync = I915_READ(VSYNC(i));
6881 }
6882
6883 return error;
6884 }
6885
6886 void
6887 intel_display_print_error_state(struct seq_file *m,
6888 struct drm_device *dev,
6889 struct intel_display_error_state *error)
6890 {
6891 int i;
6892
6893 for (i = 0; i < 2; i++) {
6894 seq_printf(m, "Pipe [%d]:\n", i);
6895 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6896 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6897 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6898 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6899 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6900 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6901 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6902 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6903
6904 seq_printf(m, "Plane [%d]:\n", i);
6905 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6906 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6907 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6908 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6909 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6910 if (INTEL_INFO(dev)->gen >= 4) {
6911 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6912 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6913 }
6914
6915 seq_printf(m, "Cursor [%d]:\n", i);
6916 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6917 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6918 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6919 }
6920 }
6921 #endif
Linux kernel - Deliverables
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