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drm/i915/bxt: Rename broxton to bxt in PHY/CDCLK function prefixes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126 static int bxt_calc_cdclk(int max_pixclk);
127
128 struct intel_limit {
129 struct {
130 int min, max;
131 } dot, vco, n, m, m1, m2, p, p1;
132
133 struct {
134 int dot_limit;
135 int p2_slow, p2_fast;
136 } p2;
137 };
138
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 {
142 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv->sb_lock);
146 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 CCK_FUSE_HPLL_FREQ_MASK;
148 mutex_unlock(&dev_priv->sb_lock);
149
150 return vco_freq[hpll_freq] * 1000;
151 }
152
153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154 const char *name, u32 reg, int ref_freq)
155 {
156 u32 val;
157 int divider;
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 }
171
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173 const char *name, u32 reg)
174 {
175 if (dev_priv->hpll_freq == 0)
176 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177
178 return vlv_get_cck_clock(dev_priv, name, reg,
179 dev_priv->hpll_freq);
180 }
181
182 static int
183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
184 {
185 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 }
187
188 static int
189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190 {
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL);
194 }
195
196 static int
197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 {
199 uint32_t clkcfg;
200
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_400:
205 return 100000;
206 case CLKCFG_FSB_533:
207 return 133333;
208 case CLKCFG_FSB_667:
209 return 166667;
210 case CLKCFG_FSB_800:
211 return 200000;
212 case CLKCFG_FSB_1067:
213 return 266667;
214 case CLKCFG_FSB_1333:
215 return 333333;
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
219 return 400000;
220 default:
221 return 133333;
222 }
223 }
224
225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
226 {
227 if (HAS_PCH_SPLIT(dev_priv))
228 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233 else
234 return; /* no rawclk on other platforms, or no need to know it */
235
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237 }
238
239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
240 {
241 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
242 return;
243
244 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245 CCK_CZ_CLOCK_CONTROL);
246
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248 }
249
250 static inline u32 /* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252 const struct intel_crtc_state *pipe_config)
253 {
254 if (HAS_DDI(dev_priv))
255 return pipe_config->port_clock; /* SPLL */
256 else if (IS_GEN5(dev_priv))
257 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
258 else
259 return 270000;
260 }
261
262 static const struct intel_limit intel_limits_i8xx_dac = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 2, .max = 33 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 4, .p2_fast = 2 },
273 };
274
275 static const struct intel_limit intel_limits_i8xx_dvo = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 908000, .max = 1512000 },
278 .n = { .min = 2, .max = 16 },
279 .m = { .min = 96, .max = 140 },
280 .m1 = { .min = 18, .max = 26 },
281 .m2 = { .min = 6, .max = 16 },
282 .p = { .min = 4, .max = 128 },
283 .p1 = { .min = 2, .max = 33 },
284 .p2 = { .dot_limit = 165000,
285 .p2_slow = 4, .p2_fast = 4 },
286 };
287
288 static const struct intel_limit intel_limits_i8xx_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 908000, .max = 1512000 },
291 .n = { .min = 2, .max = 16 },
292 .m = { .min = 96, .max = 140 },
293 .m1 = { .min = 18, .max = 26 },
294 .m2 = { .min = 6, .max = 16 },
295 .p = { .min = 4, .max = 128 },
296 .p1 = { .min = 1, .max = 6 },
297 .p2 = { .dot_limit = 165000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301 static const struct intel_limit intel_limits_i9xx_sdvo = {
302 .dot = { .min = 20000, .max = 400000 },
303 .vco = { .min = 1400000, .max = 2800000 },
304 .n = { .min = 1, .max = 6 },
305 .m = { .min = 70, .max = 120 },
306 .m1 = { .min = 8, .max = 18 },
307 .m2 = { .min = 3, .max = 7 },
308 .p = { .min = 5, .max = 80 },
309 .p1 = { .min = 1, .max = 8 },
310 .p2 = { .dot_limit = 200000,
311 .p2_slow = 10, .p2_fast = 5 },
312 };
313
314 static const struct intel_limit intel_limits_i9xx_lvds = {
315 .dot = { .min = 20000, .max = 400000 },
316 .vco = { .min = 1400000, .max = 2800000 },
317 .n = { .min = 1, .max = 6 },
318 .m = { .min = 70, .max = 120 },
319 .m1 = { .min = 8, .max = 18 },
320 .m2 = { .min = 3, .max = 7 },
321 .p = { .min = 7, .max = 98 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 112000,
324 .p2_slow = 14, .p2_fast = 7 },
325 };
326
327
328 static const struct intel_limit intel_limits_g4x_sdvo = {
329 .dot = { .min = 25000, .max = 270000 },
330 .vco = { .min = 1750000, .max = 3500000},
331 .n = { .min = 1, .max = 4 },
332 .m = { .min = 104, .max = 138 },
333 .m1 = { .min = 17, .max = 23 },
334 .m2 = { .min = 5, .max = 11 },
335 .p = { .min = 10, .max = 30 },
336 .p1 = { .min = 1, .max = 3},
337 .p2 = { .dot_limit = 270000,
338 .p2_slow = 10,
339 .p2_fast = 10
340 },
341 };
342
343 static const struct intel_limit intel_limits_g4x_hdmi = {
344 .dot = { .min = 22000, .max = 400000 },
345 .vco = { .min = 1750000, .max = 3500000},
346 .n = { .min = 1, .max = 4 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 16, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8},
352 .p2 = { .dot_limit = 165000,
353 .p2_slow = 10, .p2_fast = 5 },
354 };
355
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
357 .dot = { .min = 20000, .max = 115000 },
358 .vco = { .min = 1750000, .max = 3500000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 104, .max = 138 },
361 .m1 = { .min = 17, .max = 23 },
362 .m2 = { .min = 5, .max = 11 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 0,
366 .p2_slow = 14, .p2_fast = 14
367 },
368 };
369
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
371 .dot = { .min = 80000, .max = 224000 },
372 .vco = { .min = 1750000, .max = 3500000 },
373 .n = { .min = 1, .max = 3 },
374 .m = { .min = 104, .max = 138 },
375 .m1 = { .min = 17, .max = 23 },
376 .m2 = { .min = 5, .max = 11 },
377 .p = { .min = 14, .max = 42 },
378 .p1 = { .min = 2, .max = 6 },
379 .p2 = { .dot_limit = 0,
380 .p2_slow = 7, .p2_fast = 7
381 },
382 };
383
384 static const struct intel_limit intel_limits_pineview_sdvo = {
385 .dot = { .min = 20000, .max = 400000},
386 .vco = { .min = 1700000, .max = 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n = { .min = 3, .max = 6 },
389 .m = { .min = 2, .max = 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1 = { .min = 0, .max = 0 },
392 .m2 = { .min = 0, .max = 254 },
393 .p = { .min = 5, .max = 80 },
394 .p1 = { .min = 1, .max = 8 },
395 .p2 = { .dot_limit = 200000,
396 .p2_slow = 10, .p2_fast = 5 },
397 };
398
399 static const struct intel_limit intel_limits_pineview_lvds = {
400 .dot = { .min = 20000, .max = 400000 },
401 .vco = { .min = 1700000, .max = 3500000 },
402 .n = { .min = 3, .max = 6 },
403 .m = { .min = 2, .max = 256 },
404 .m1 = { .min = 0, .max = 0 },
405 .m2 = { .min = 0, .max = 254 },
406 .p = { .min = 7, .max = 112 },
407 .p1 = { .min = 1, .max = 8 },
408 .p2 = { .dot_limit = 112000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 /* Ironlake / Sandybridge
413 *
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
416 */
417 static const struct intel_limit intel_limits_ironlake_dac = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 5 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 5, .max = 80 },
425 .p1 = { .min = 1, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 10, .p2_fast = 5 },
428 };
429
430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 3 },
434 .m = { .min = 79, .max = 118 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 127 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 56 },
451 .p1 = { .min = 2, .max = 8 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
458 .dot = { .min = 25000, .max = 350000 },
459 .vco = { .min = 1760000, .max = 3510000 },
460 .n = { .min = 1, .max = 2 },
461 .m = { .min = 79, .max = 126 },
462 .m1 = { .min = 12, .max = 22 },
463 .m2 = { .min = 5, .max = 9 },
464 .p = { .min = 28, .max = 112 },
465 .p1 = { .min = 2, .max = 8 },
466 .p2 = { .dot_limit = 225000,
467 .p2_slow = 14, .p2_fast = 14 },
468 };
469
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
471 .dot = { .min = 25000, .max = 350000 },
472 .vco = { .min = 1760000, .max = 3510000 },
473 .n = { .min = 1, .max = 3 },
474 .m = { .min = 79, .max = 126 },
475 .m1 = { .min = 12, .max = 22 },
476 .m2 = { .min = 5, .max = 9 },
477 .p = { .min = 14, .max = 42 },
478 .p1 = { .min = 2, .max = 6 },
479 .p2 = { .dot_limit = 225000,
480 .p2_slow = 7, .p2_fast = 7 },
481 };
482
483 static const struct intel_limit intel_limits_vlv = {
484 /*
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
489 */
490 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
491 .vco = { .min = 4000000, .max = 6000000 },
492 .n = { .min = 1, .max = 7 },
493 .m1 = { .min = 2, .max = 3 },
494 .m2 = { .min = 11, .max = 156 },
495 .p1 = { .min = 2, .max = 3 },
496 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
497 };
498
499 static const struct intel_limit intel_limits_chv = {
500 /*
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
505 */
506 .dot = { .min = 25000 * 5, .max = 540000 * 5},
507 .vco = { .min = 4800000, .max = 6480000 },
508 .n = { .min = 1, .max = 1 },
509 .m1 = { .min = 2, .max = 2 },
510 .m2 = { .min = 24 << 22, .max = 175 << 22 },
511 .p1 = { .min = 2, .max = 4 },
512 .p2 = { .p2_slow = 1, .p2_fast = 14 },
513 };
514
515 static const struct intel_limit intel_limits_bxt = {
516 /* FIXME: find real dot limits */
517 .dot = { .min = 0, .max = INT_MAX },
518 .vco = { .min = 4800000, .max = 6700000 },
519 .n = { .min = 1, .max = 1 },
520 .m1 = { .min = 2, .max = 2 },
521 /* FIXME: find real m2 limits */
522 .m2 = { .min = 2 << 22, .max = 255 << 22 },
523 .p1 = { .min = 2, .max = 4 },
524 .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 };
526
527 static bool
528 needs_modeset(struct drm_crtc_state *state)
529 {
530 return drm_atomic_crtc_needs_modeset(state);
531 }
532
533 /**
534 * Returns whether any output on the specified pipe is of the specified type
535 */
536 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
537 {
538 struct drm_device *dev = crtc->base.dev;
539 struct intel_encoder *encoder;
540
541 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
542 if (encoder->type == type)
543 return true;
544
545 return false;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
552 * encoder->crtc.
553 */
554 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
555 int type)
556 {
557 struct drm_atomic_state *state = crtc_state->base.state;
558 struct drm_connector *connector;
559 struct drm_connector_state *connector_state;
560 struct intel_encoder *encoder;
561 int i, num_connectors = 0;
562
563 for_each_connector_in_state(state, connector, connector_state, i) {
564 if (connector_state->crtc != crtc_state->base.crtc)
565 continue;
566
567 num_connectors++;
568
569 encoder = to_intel_encoder(connector_state->best_encoder);
570 if (encoder->type == type)
571 return true;
572 }
573
574 WARN_ON(num_connectors == 0);
575
576 return false;
577 }
578
579 /*
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
582 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
583 * The helpers' return value is the rate of the clock that is fed to the
584 * display engine's pipe which can be the above fast dot clock rate or a
585 * divided-down version of it.
586 */
587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
588 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
589 {
590 clock->m = clock->m2 + 2;
591 clock->p = clock->p1 * clock->p2;
592 if (WARN_ON(clock->n == 0 || clock->p == 0))
593 return 0;
594 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596
597 return clock->dot;
598 }
599
600 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
601 {
602 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
603 }
604
605 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
606 {
607 clock->m = i9xx_dpll_compute_m(clock);
608 clock->p = clock->p1 * clock->p2;
609 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
610 return 0;
611 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
612 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
613
614 return clock->dot;
615 }
616
617 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
618 {
619 clock->m = clock->m1 * clock->m2;
620 clock->p = clock->p1 * clock->p2;
621 if (WARN_ON(clock->n == 0 || clock->p == 0))
622 return 0;
623 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
624 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
625
626 return clock->dot / 5;
627 }
628
629 int chv_calc_dpll_params(int refclk, struct dpll *clock)
630 {
631 clock->m = clock->m1 * clock->m2;
632 clock->p = clock->p1 * clock->p2;
633 if (WARN_ON(clock->n == 0 || clock->p == 0))
634 return 0;
635 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
636 clock->n << 22);
637 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
638
639 return clock->dot / 5;
640 }
641
642 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
643 /**
644 * Returns whether the given set of divisors are valid for a given refclk with
645 * the given connectors.
646 */
647
648 static bool intel_PLL_is_valid(struct drm_device *dev,
649 const struct intel_limit *limit,
650 const struct dpll *clock)
651 {
652 if (clock->n < limit->n.min || limit->n.max < clock->n)
653 INTELPllInvalid("n out of range\n");
654 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
655 INTELPllInvalid("p1 out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid("m1 out of range\n");
660
661 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
662 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
663 if (clock->m1 <= clock->m2)
664 INTELPllInvalid("m1 <= m2\n");
665
666 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
667 if (clock->p < limit->p.min || limit->p.max < clock->p)
668 INTELPllInvalid("p out of range\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 }
672
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
680
681 return true;
682 }
683
684 static int
685 i9xx_select_p2_div(const struct intel_limit *limit,
686 const struct intel_crtc_state *crtc_state,
687 int target)
688 {
689 struct drm_device *dev = crtc_state->base.crtc->dev;
690
691 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
692 /*
693 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different
695 * single/dual channel state, if we even can.
696 */
697 if (intel_is_dual_link_lvds(dev))
698 return limit->p2.p2_fast;
699 else
700 return limit->p2.p2_slow;
701 } else {
702 if (target < limit->p2.dot_limit)
703 return limit->p2.p2_slow;
704 else
705 return limit->p2.p2_fast;
706 }
707 }
708
709 /*
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
713 *
714 * Target and reference clocks are specified in kHz.
715 *
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
718 */
719 static bool
720 i9xx_find_best_dpll(const struct intel_limit *limit,
721 struct intel_crtc_state *crtc_state,
722 int target, int refclk, struct dpll *match_clock,
723 struct dpll *best_clock)
724 {
725 struct drm_device *dev = crtc_state->base.crtc->dev;
726 struct dpll clock;
727 int err = target;
728
729 memset(best_clock, 0, sizeof(*best_clock));
730
731 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
732
733 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
734 clock.m1++) {
735 for (clock.m2 = limit->m2.min;
736 clock.m2 <= limit->m2.max; clock.m2++) {
737 if (clock.m2 >= clock.m1)
738 break;
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
743 int this_err;
744
745 i9xx_calc_dpll_params(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
755 *best_clock = clock;
756 err = this_err;
757 }
758 }
759 }
760 }
761 }
762
763 return (err != target);
764 }
765
766 /*
767 * Returns a set of divisors for the desired target clock with the given
768 * refclk, or FALSE. The returned values represent the clock equation:
769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
770 *
771 * Target and reference clocks are specified in kHz.
772 *
773 * If match_clock is provided, then best_clock P divider must match the P
774 * divider from @match_clock used for LVDS downclocking.
775 */
776 static bool
777 pnv_find_best_dpll(const struct intel_limit *limit,
778 struct intel_crtc_state *crtc_state,
779 int target, int refclk, struct dpll *match_clock,
780 struct dpll *best_clock)
781 {
782 struct drm_device *dev = crtc_state->base.crtc->dev;
783 struct dpll clock;
784 int err = target;
785
786 memset(best_clock, 0, sizeof(*best_clock));
787
788 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
789
790 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
791 clock.m1++) {
792 for (clock.m2 = limit->m2.min;
793 clock.m2 <= limit->m2.max; clock.m2++) {
794 for (clock.n = limit->n.min;
795 clock.n <= limit->n.max; clock.n++) {
796 for (clock.p1 = limit->p1.min;
797 clock.p1 <= limit->p1.max; clock.p1++) {
798 int this_err;
799
800 pnv_calc_dpll_params(refclk, &clock);
801 if (!intel_PLL_is_valid(dev, limit,
802 &clock))
803 continue;
804 if (match_clock &&
805 clock.p != match_clock->p)
806 continue;
807
808 this_err = abs(clock.dot - target);
809 if (this_err < err) {
810 *best_clock = clock;
811 err = this_err;
812 }
813 }
814 }
815 }
816 }
817
818 return (err != target);
819 }
820
821 /*
822 * Returns a set of divisors for the desired target clock with the given
823 * refclk, or FALSE. The returned values represent the clock equation:
824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
825 *
826 * Target and reference clocks are specified in kHz.
827 *
828 * If match_clock is provided, then best_clock P divider must match the P
829 * divider from @match_clock used for LVDS downclocking.
830 */
831 static bool
832 g4x_find_best_dpll(const struct intel_limit *limit,
833 struct intel_crtc_state *crtc_state,
834 int target, int refclk, struct dpll *match_clock,
835 struct dpll *best_clock)
836 {
837 struct drm_device *dev = crtc_state->base.crtc->dev;
838 struct dpll clock;
839 int max_n;
840 bool found = false;
841 /* approximately equals target * 0.00585 */
842 int err_most = (target >> 8) + (target >> 9);
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
847
848 max_n = limit->n.max;
849 /* based on hardware requirement, prefer smaller n to precision */
850 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
851 /* based on hardware requirement, prefere larger m1,m2 */
852 for (clock.m1 = limit->m1.max;
853 clock.m1 >= limit->m1.min; clock.m1--) {
854 for (clock.m2 = limit->m2.max;
855 clock.m2 >= limit->m2.min; clock.m2--) {
856 for (clock.p1 = limit->p1.max;
857 clock.p1 >= limit->p1.min; clock.p1--) {
858 int this_err;
859
860 i9xx_calc_dpll_params(refclk, &clock);
861 if (!intel_PLL_is_valid(dev, limit,
862 &clock))
863 continue;
864
865 this_err = abs(clock.dot - target);
866 if (this_err < err_most) {
867 *best_clock = clock;
868 err_most = this_err;
869 max_n = clock.n;
870 found = true;
871 }
872 }
873 }
874 }
875 }
876 return found;
877 }
878
879 /*
880 * Check if the calculated PLL configuration is more optimal compared to the
881 * best configuration and error found so far. Return the calculated error.
882 */
883 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
884 const struct dpll *calculated_clock,
885 const struct dpll *best_clock,
886 unsigned int best_error_ppm,
887 unsigned int *error_ppm)
888 {
889 /*
890 * For CHV ignore the error and consider only the P value.
891 * Prefer a bigger P value based on HW requirements.
892 */
893 if (IS_CHERRYVIEW(dev)) {
894 *error_ppm = 0;
895
896 return calculated_clock->p > best_clock->p;
897 }
898
899 if (WARN_ON_ONCE(!target_freq))
900 return false;
901
902 *error_ppm = div_u64(1000000ULL *
903 abs(target_freq - calculated_clock->dot),
904 target_freq);
905 /*
906 * Prefer a better P value over a better (smaller) error if the error
907 * is small. Ensure this preference for future configurations too by
908 * setting the error to 0.
909 */
910 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
911 *error_ppm = 0;
912
913 return true;
914 }
915
916 return *error_ppm + 10 < best_error_ppm;
917 }
918
919 /*
920 * Returns a set of divisors for the desired target clock with the given
921 * refclk, or FALSE. The returned values represent the clock equation:
922 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
923 */
924 static bool
925 vlv_find_best_dpll(const struct intel_limit *limit,
926 struct intel_crtc_state *crtc_state,
927 int target, int refclk, struct dpll *match_clock,
928 struct dpll *best_clock)
929 {
930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
931 struct drm_device *dev = crtc->base.dev;
932 struct dpll clock;
933 unsigned int bestppm = 1000000;
934 /* min update 19.2 MHz */
935 int max_n = min(limit->n.max, refclk / 19200);
936 bool found = false;
937
938 target *= 5; /* fast clock */
939
940 memset(best_clock, 0, sizeof(*best_clock));
941
942 /* based on hardware requirement, prefer smaller n to precision */
943 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
944 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
945 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 clock.p = clock.p1 * clock.p2;
948 /* based on hardware requirement, prefer bigger m1,m2 values */
949 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
950 unsigned int ppm;
951
952 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
953 refclk * clock.m1);
954
955 vlv_calc_dpll_params(refclk, &clock);
956
957 if (!intel_PLL_is_valid(dev, limit,
958 &clock))
959 continue;
960
961 if (!vlv_PLL_is_optimal(dev, target,
962 &clock,
963 best_clock,
964 bestppm, &ppm))
965 continue;
966
967 *best_clock = clock;
968 bestppm = ppm;
969 found = true;
970 }
971 }
972 }
973 }
974
975 return found;
976 }
977
978 /*
979 * Returns a set of divisors for the desired target clock with the given
980 * refclk, or FALSE. The returned values represent the clock equation:
981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
982 */
983 static bool
984 chv_find_best_dpll(const struct intel_limit *limit,
985 struct intel_crtc_state *crtc_state,
986 int target, int refclk, struct dpll *match_clock,
987 struct dpll *best_clock)
988 {
989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
990 struct drm_device *dev = crtc->base.dev;
991 unsigned int best_error_ppm;
992 struct dpll clock;
993 uint64_t m2;
994 int found = false;
995
996 memset(best_clock, 0, sizeof(*best_clock));
997 best_error_ppm = 1000000;
998
999 /*
1000 * Based on hardware doc, the n always set to 1, and m1 always
1001 * set to 2. If requires to support 200Mhz refclk, we need to
1002 * revisit this because n may not 1 anymore.
1003 */
1004 clock.n = 1, clock.m1 = 2;
1005 target *= 5; /* fast clock */
1006
1007 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008 for (clock.p2 = limit->p2.p2_fast;
1009 clock.p2 >= limit->p2.p2_slow;
1010 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1011 unsigned int error_ppm;
1012
1013 clock.p = clock.p1 * clock.p2;
1014
1015 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016 clock.n) << 22, refclk * clock.m1);
1017
1018 if (m2 > INT_MAX/clock.m1)
1019 continue;
1020
1021 clock.m2 = m2;
1022
1023 chv_calc_dpll_params(refclk, &clock);
1024
1025 if (!intel_PLL_is_valid(dev, limit, &clock))
1026 continue;
1027
1028 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029 best_error_ppm, &error_ppm))
1030 continue;
1031
1032 *best_clock = clock;
1033 best_error_ppm = error_ppm;
1034 found = true;
1035 }
1036 }
1037
1038 return found;
1039 }
1040
1041 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1042 struct dpll *best_clock)
1043 {
1044 int refclk = 100000;
1045 const struct intel_limit *limit = &intel_limits_bxt;
1046
1047 return chv_find_best_dpll(limit, crtc_state,
1048 target_clock, refclk, NULL, best_clock);
1049 }
1050
1051 bool intel_crtc_active(struct drm_crtc *crtc)
1052 {
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055 /* Be paranoid as we can arrive here with only partial
1056 * state retrieved from the hardware during setup.
1057 *
1058 * We can ditch the adjusted_mode.crtc_clock check as soon
1059 * as Haswell has gained clock readout/fastboot support.
1060 *
1061 * We can ditch the crtc->primary->fb check as soon as we can
1062 * properly reconstruct framebuffers.
1063 *
1064 * FIXME: The intel_crtc->active here should be switched to
1065 * crtc->state->active once we have proper CRTC states wired up
1066 * for atomic.
1067 */
1068 return intel_crtc->active && crtc->primary->state->fb &&
1069 intel_crtc->config->base.adjusted_mode.crtc_clock;
1070 }
1071
1072 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073 enum pipe pipe)
1074 {
1075 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
1078 return intel_crtc->config->cpu_transcoder;
1079 }
1080
1081 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082 {
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 i915_reg_t reg = PIPEDSL(pipe);
1085 u32 line1, line2;
1086 u32 line_mask;
1087
1088 if (IS_GEN2(dev))
1089 line_mask = DSL_LINEMASK_GEN2;
1090 else
1091 line_mask = DSL_LINEMASK_GEN3;
1092
1093 line1 = I915_READ(reg) & line_mask;
1094 msleep(5);
1095 line2 = I915_READ(reg) & line_mask;
1096
1097 return line1 == line2;
1098 }
1099
1100 /*
1101 * intel_wait_for_pipe_off - wait for pipe to turn off
1102 * @crtc: crtc whose pipe to wait for
1103 *
1104 * After disabling a pipe, we can't wait for vblank in the usual way,
1105 * spinning on the vblank interrupt status bit, since we won't actually
1106 * see an interrupt when the pipe is disabled.
1107 *
1108 * On Gen4 and above:
1109 * wait for the pipe register state bit to turn off
1110 *
1111 * Otherwise:
1112 * wait for the display line value to settle (it usually
1113 * ends up stopping at the start of the next frame).
1114 *
1115 */
1116 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117 {
1118 struct drm_device *dev = crtc->base.dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121 enum pipe pipe = crtc->pipe;
1122
1123 if (INTEL_INFO(dev)->gen >= 4) {
1124 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125
1126 /* Wait for the Pipe State to go off */
1127 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1128 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 } else {
1131 /* Wait for the display line to settle */
1132 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1133 WARN(1, "pipe_off wait timed out\n");
1134 }
1135 }
1136
1137 /* Only for pre-ILK configs */
1138 void assert_pll(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 u32 val;
1142 bool cur_state;
1143
1144 val = I915_READ(DPLL(pipe));
1145 cur_state = !!(val & DPLL_VCO_ENABLE);
1146 I915_STATE_WARN(cur_state != state,
1147 "PLL state assertion failure (expected %s, current %s)\n",
1148 onoff(state), onoff(cur_state));
1149 }
1150
1151 /* XXX: the dsi pll is shared between MIPI DSI ports */
1152 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1153 {
1154 u32 val;
1155 bool cur_state;
1156
1157 mutex_lock(&dev_priv->sb_lock);
1158 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1159 mutex_unlock(&dev_priv->sb_lock);
1160
1161 cur_state = val & DSI_PLL_VCO_EN;
1162 I915_STATE_WARN(cur_state != state,
1163 "DSI PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1168 enum pipe pipe, bool state)
1169 {
1170 bool cur_state;
1171 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1172 pipe);
1173
1174 if (HAS_DDI(dev_priv)) {
1175 /* DDI does not have a specific FDI_TX register */
1176 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1177 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1178 } else {
1179 u32 val = I915_READ(FDI_TX_CTL(pipe));
1180 cur_state = !!(val & FDI_TX_ENABLE);
1181 }
1182 I915_STATE_WARN(cur_state != state,
1183 "FDI TX state assertion failure (expected %s, current %s)\n",
1184 onoff(state), onoff(cur_state));
1185 }
1186 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1187 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1188
1189 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 u32 val;
1193 bool cur_state;
1194
1195 val = I915_READ(FDI_RX_CTL(pipe));
1196 cur_state = !!(val & FDI_RX_ENABLE);
1197 I915_STATE_WARN(cur_state != state,
1198 "FDI RX state assertion failure (expected %s, current %s)\n",
1199 onoff(state), onoff(cur_state));
1200 }
1201 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1202 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1203
1204 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe)
1206 {
1207 u32 val;
1208
1209 /* ILK FDI PLL is always enabled */
1210 if (IS_GEN5(dev_priv))
1211 return;
1212
1213 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1214 if (HAS_DDI(dev_priv))
1215 return;
1216
1217 val = I915_READ(FDI_TX_CTL(pipe));
1218 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1219 }
1220
1221 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 u32 val;
1225 bool cur_state;
1226
1227 val = I915_READ(FDI_RX_CTL(pipe));
1228 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1229 I915_STATE_WARN(cur_state != state,
1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 onoff(state), onoff(cur_state));
1232 }
1233
1234 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe)
1236 {
1237 struct drm_device *dev = dev_priv->dev;
1238 i915_reg_t pp_reg;
1239 u32 val;
1240 enum pipe panel_pipe = PIPE_A;
1241 bool locked = true;
1242
1243 if (WARN_ON(HAS_DDI(dev)))
1244 return;
1245
1246 if (HAS_PCH_SPLIT(dev)) {
1247 u32 port_sel;
1248
1249 pp_reg = PCH_PP_CONTROL;
1250 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1251
1252 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1253 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1254 panel_pipe = PIPE_B;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1259 panel_pipe = pipe;
1260 } else {
1261 pp_reg = PP_CONTROL;
1262 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1263 panel_pipe = PIPE_B;
1264 }
1265
1266 val = I915_READ(pp_reg);
1267 if (!(val & PANEL_POWER_ON) ||
1268 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1269 locked = false;
1270
1271 I915_STATE_WARN(panel_pipe == pipe && locked,
1272 "panel assertion failure, pipe %c regs locked\n",
1273 pipe_name(pipe));
1274 }
1275
1276 static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state)
1278 {
1279 struct drm_device *dev = dev_priv->dev;
1280 bool cur_state;
1281
1282 if (IS_845G(dev) || IS_I865G(dev))
1283 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1284 else
1285 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1286
1287 I915_STATE_WARN(cur_state != state,
1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), onoff(state), onoff(cur_state));
1290 }
1291 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1293
1294 void assert_pipe(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, bool state)
1296 {
1297 bool cur_state;
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
1300 enum intel_display_power_domain power_domain;
1301
1302 /* if we need the pipe quirk it must be always on */
1303 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1304 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1305 state = true;
1306
1307 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1308 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1309 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1310 cur_state = !!(val & PIPECONF_ENABLE);
1311
1312 intel_display_power_put(dev_priv, power_domain);
1313 } else {
1314 cur_state = false;
1315 }
1316
1317 I915_STATE_WARN(cur_state != state,
1318 "pipe %c assertion failure (expected %s, current %s)\n",
1319 pipe_name(pipe), onoff(state), onoff(cur_state));
1320 }
1321
1322 static void assert_plane(struct drm_i915_private *dev_priv,
1323 enum plane plane, bool state)
1324 {
1325 u32 val;
1326 bool cur_state;
1327
1328 val = I915_READ(DSPCNTR(plane));
1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330 I915_STATE_WARN(cur_state != state,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), onoff(state), onoff(cur_state));
1333 }
1334
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 int i;
1343
1344 /* Primary planes are fixed to pipes on gen4+ */
1345 if (INTEL_INFO(dev)->gen >= 4) {
1346 u32 val = I915_READ(DSPCNTR(pipe));
1347 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1348 "plane %c assertion failure, should be disabled but not\n",
1349 plane_name(pipe));
1350 return;
1351 }
1352
1353 /* Need to check both planes against the pipe */
1354 for_each_pipe(dev_priv, i) {
1355 u32 val = I915_READ(DSPCNTR(i));
1356 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1357 DISPPLANE_SEL_PIPE_SHIFT;
1358 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1359 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1360 plane_name(i), pipe_name(pipe));
1361 }
1362 }
1363
1364 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 struct drm_device *dev = dev_priv->dev;
1368 int sprite;
1369
1370 if (INTEL_INFO(dev)->gen >= 9) {
1371 for_each_sprite(dev_priv, pipe, sprite) {
1372 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1373 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1374 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1375 sprite, pipe_name(pipe));
1376 }
1377 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1378 for_each_sprite(dev_priv, pipe, sprite) {
1379 u32 val = I915_READ(SPCNTR(pipe, sprite));
1380 I915_STATE_WARN(val & SP_ENABLE,
1381 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1382 sprite_name(pipe, sprite), pipe_name(pipe));
1383 }
1384 } else if (INTEL_INFO(dev)->gen >= 7) {
1385 u32 val = I915_READ(SPRCTL(pipe));
1386 I915_STATE_WARN(val & SPRITE_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(pipe), pipe_name(pipe));
1389 } else if (INTEL_INFO(dev)->gen >= 5) {
1390 u32 val = I915_READ(DVSCNTR(pipe));
1391 I915_STATE_WARN(val & DVS_ENABLE,
1392 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(pipe), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_vblank_disabled(struct drm_crtc *crtc)
1398 {
1399 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1400 drm_crtc_vblank_put(crtc);
1401 }
1402
1403 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405 {
1406 u32 val;
1407 bool enabled;
1408
1409 val = I915_READ(PCH_TRANSCONF(pipe));
1410 enabled = !!(val & TRANS_ENABLE);
1411 I915_STATE_WARN(enabled,
1412 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1413 pipe_name(pipe));
1414 }
1415
1416 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 port_sel, u32 val)
1418 {
1419 if ((val & DP_PORT_EN) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv)) {
1423 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1424 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1425 return false;
1426 } else if (IS_CHERRYVIEW(dev_priv)) {
1427 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1428 return false;
1429 } else {
1430 if ((val & DP_PIPE_MASK) != (pipe << 30))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, u32 val)
1438 {
1439 if ((val & SDVO_ENABLE) == 0)
1440 return false;
1441
1442 if (HAS_PCH_CPT(dev_priv)) {
1443 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1444 return false;
1445 } else if (IS_CHERRYVIEW(dev_priv)) {
1446 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1447 return false;
1448 } else {
1449 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1450 return false;
1451 }
1452 return true;
1453 }
1454
1455 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1456 enum pipe pipe, u32 val)
1457 {
1458 if ((val & LVDS_PORT_EN) == 0)
1459 return false;
1460
1461 if (HAS_PCH_CPT(dev_priv)) {
1462 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1463 return false;
1464 } else {
1465 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1466 return false;
1467 }
1468 return true;
1469 }
1470
1471 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1472 enum pipe pipe, u32 val)
1473 {
1474 if ((val & ADPA_DAC_ENABLE) == 0)
1475 return false;
1476 if (HAS_PCH_CPT(dev_priv)) {
1477 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1478 return false;
1479 } else {
1480 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1481 return false;
1482 }
1483 return true;
1484 }
1485
1486 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, i915_reg_t reg,
1488 u32 port_sel)
1489 {
1490 u32 val = I915_READ(reg);
1491 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1492 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1493 i915_mmio_reg_offset(reg), pipe_name(pipe));
1494
1495 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1496 && (val & DP_PIPEB_SELECT),
1497 "IBX PCH dp port still using transcoder B\n");
1498 }
1499
1500 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, i915_reg_t reg)
1502 {
1503 u32 val = I915_READ(reg);
1504 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1505 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1506 i915_mmio_reg_offset(reg), pipe_name(pipe));
1507
1508 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1509 && (val & SDVO_PIPE_B_SELECT),
1510 "IBX PCH hdmi port still using transcoder B\n");
1511 }
1512
1513 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe)
1515 {
1516 u32 val;
1517
1518 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1520 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1521
1522 val = I915_READ(PCH_ADPA);
1523 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1524 "PCH VGA enabled on transcoder %c, should be disabled\n",
1525 pipe_name(pipe));
1526
1527 val = I915_READ(PCH_LVDS);
1528 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1529 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1530 pipe_name(pipe));
1531
1532 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1533 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1534 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1535 }
1536
1537 static void _vlv_enable_pll(struct intel_crtc *crtc,
1538 const struct intel_crtc_state *pipe_config)
1539 {
1540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1541 enum pipe pipe = crtc->pipe;
1542
1543 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1544 POSTING_READ(DPLL(pipe));
1545 udelay(150);
1546
1547 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1548 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1549 }
1550
1551 static void vlv_enable_pll(struct intel_crtc *crtc,
1552 const struct intel_crtc_state *pipe_config)
1553 {
1554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1555 enum pipe pipe = crtc->pipe;
1556
1557 assert_pipe_disabled(dev_priv, pipe);
1558
1559 /* PLL is protected by panel, make sure we can write it */
1560 assert_panel_unlocked(dev_priv, pipe);
1561
1562 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1563 _vlv_enable_pll(crtc, pipe_config);
1564
1565 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1566 POSTING_READ(DPLL_MD(pipe));
1567 }
1568
1569
1570 static void _chv_enable_pll(struct intel_crtc *crtc,
1571 const struct intel_crtc_state *pipe_config)
1572 {
1573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574 enum pipe pipe = crtc->pipe;
1575 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1576 u32 tmp;
1577
1578 mutex_lock(&dev_priv->sb_lock);
1579
1580 /* Enable back the 10bit clock to display controller */
1581 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1582 tmp |= DPIO_DCLKP_EN;
1583 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1584
1585 mutex_unlock(&dev_priv->sb_lock);
1586
1587 /*
1588 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1589 */
1590 udelay(1);
1591
1592 /* Enable PLL */
1593 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1594
1595 /* Check PLL is locked */
1596 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1597 DRM_ERROR("PLL %d failed to lock\n", pipe);
1598 }
1599
1600 static void chv_enable_pll(struct intel_crtc *crtc,
1601 const struct intel_crtc_state *pipe_config)
1602 {
1603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1604 enum pipe pipe = crtc->pipe;
1605
1606 assert_pipe_disabled(dev_priv, pipe);
1607
1608 /* PLL is protected by panel, make sure we can write it */
1609 assert_panel_unlocked(dev_priv, pipe);
1610
1611 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1612 _chv_enable_pll(crtc, pipe_config);
1613
1614 if (pipe != PIPE_A) {
1615 /*
1616 * WaPixelRepeatModeFixForC0:chv
1617 *
1618 * DPLLCMD is AWOL. Use chicken bits to propagate
1619 * the value from DPLLBMD to either pipe B or C.
1620 */
1621 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1622 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1623 I915_WRITE(CBR4_VLV, 0);
1624 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1625
1626 /*
1627 * DPLLB VGA mode also seems to cause problems.
1628 * We should always have it disabled.
1629 */
1630 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1631 } else {
1632 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(pipe));
1634 }
1635 }
1636
1637 static int intel_num_dvo_pipes(struct drm_device *dev)
1638 {
1639 struct intel_crtc *crtc;
1640 int count = 0;
1641
1642 for_each_intel_crtc(dev, crtc)
1643 count += crtc->base.state->active &&
1644 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1645
1646 return count;
1647 }
1648
1649 static void i9xx_enable_pll(struct intel_crtc *crtc)
1650 {
1651 struct drm_device *dev = crtc->base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 i915_reg_t reg = DPLL(crtc->pipe);
1654 u32 dpll = crtc->config->dpll_hw_state.dpll;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 /* PLL is protected by panel, make sure we can write it */
1659 if (IS_MOBILE(dev) && !IS_I830(dev))
1660 assert_panel_unlocked(dev_priv, crtc->pipe);
1661
1662 /* Enable DVO 2x clock on both PLLs if necessary */
1663 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1664 /*
1665 * It appears to be important that we don't enable this
1666 * for the current pipe before otherwise configuring the
1667 * PLL. No idea how this should be handled if multiple
1668 * DVO outputs are enabled simultaneosly.
1669 */
1670 dpll |= DPLL_DVO_2X_MODE;
1671 I915_WRITE(DPLL(!crtc->pipe),
1672 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1673 }
1674
1675 /*
1676 * Apparently we need to have VGA mode enabled prior to changing
1677 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1678 * dividers, even though the register value does change.
1679 */
1680 I915_WRITE(reg, 0);
1681
1682 I915_WRITE(reg, dpll);
1683
1684 /* Wait for the clocks to stabilize. */
1685 POSTING_READ(reg);
1686 udelay(150);
1687
1688 if (INTEL_INFO(dev)->gen >= 4) {
1689 I915_WRITE(DPLL_MD(crtc->pipe),
1690 crtc->config->dpll_hw_state.dpll_md);
1691 } else {
1692 /* The pixel multiplier can only be updated once the
1693 * DPLL is enabled and the clocks are stable.
1694 *
1695 * So write it again.
1696 */
1697 I915_WRITE(reg, dpll);
1698 }
1699
1700 /* We do this three times for luck */
1701 I915_WRITE(reg, dpll);
1702 POSTING_READ(reg);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg, dpll);
1705 POSTING_READ(reg);
1706 udelay(150); /* wait for warmup */
1707 I915_WRITE(reg, dpll);
1708 POSTING_READ(reg);
1709 udelay(150); /* wait for warmup */
1710 }
1711
1712 /**
1713 * i9xx_disable_pll - disable a PLL
1714 * @dev_priv: i915 private structure
1715 * @pipe: pipe PLL to disable
1716 *
1717 * Disable the PLL for @pipe, making sure the pipe is off first.
1718 *
1719 * Note! This is for pre-ILK only.
1720 */
1721 static void i9xx_disable_pll(struct intel_crtc *crtc)
1722 {
1723 struct drm_device *dev = crtc->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 enum pipe pipe = crtc->pipe;
1726
1727 /* Disable DVO 2x clock on both PLLs if necessary */
1728 if (IS_I830(dev) &&
1729 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1730 !intel_num_dvo_pipes(dev)) {
1731 I915_WRITE(DPLL(PIPE_B),
1732 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1733 I915_WRITE(DPLL(PIPE_A),
1734 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1735 }
1736
1737 /* Don't disable pipe or pipe PLLs if needed */
1738 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1739 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1740 return;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
1745 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1746 POSTING_READ(DPLL(pipe));
1747 }
1748
1749 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1750 {
1751 u32 val;
1752
1753 /* Make sure the pipe isn't still relying on us */
1754 assert_pipe_disabled(dev_priv, pipe);
1755
1756 val = DPLL_INTEGRATED_REF_CLK_VLV |
1757 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1758 if (pipe != PIPE_A)
1759 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1760
1761 I915_WRITE(DPLL(pipe), val);
1762 POSTING_READ(DPLL(pipe));
1763 }
1764
1765 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1766 {
1767 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1768 u32 val;
1769
1770 /* Make sure the pipe isn't still relying on us */
1771 assert_pipe_disabled(dev_priv, pipe);
1772
1773 val = DPLL_SSC_REF_CLK_CHV |
1774 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1775 if (pipe != PIPE_A)
1776 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1777
1778 I915_WRITE(DPLL(pipe), val);
1779 POSTING_READ(DPLL(pipe));
1780
1781 mutex_lock(&dev_priv->sb_lock);
1782
1783 /* Disable 10bit clock to display controller */
1784 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1785 val &= ~DPIO_DCLKP_EN;
1786 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1787
1788 mutex_unlock(&dev_priv->sb_lock);
1789 }
1790
1791 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1792 struct intel_digital_port *dport,
1793 unsigned int expected_mask)
1794 {
1795 u32 port_mask;
1796 i915_reg_t dpll_reg;
1797
1798 switch (dport->port) {
1799 case PORT_B:
1800 port_mask = DPLL_PORTB_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 break;
1803 case PORT_C:
1804 port_mask = DPLL_PORTC_READY_MASK;
1805 dpll_reg = DPLL(0);
1806 expected_mask <<= 4;
1807 break;
1808 case PORT_D:
1809 port_mask = DPLL_PORTD_READY_MASK;
1810 dpll_reg = DPIO_PHY_STATUS;
1811 break;
1812 default:
1813 BUG();
1814 }
1815
1816 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1817 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1818 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1819 }
1820
1821 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1822 enum pipe pipe)
1823 {
1824 struct drm_device *dev = dev_priv->dev;
1825 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1827 i915_reg_t reg;
1828 uint32_t val, pipeconf_val;
1829
1830 /* Make sure PCH DPLL is enabled */
1831 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1832
1833 /* FDI must be feeding us bits for PCH ports */
1834 assert_fdi_tx_enabled(dev_priv, pipe);
1835 assert_fdi_rx_enabled(dev_priv, pipe);
1836
1837 if (HAS_PCH_CPT(dev)) {
1838 /* Workaround: Set the timing override bit before enabling the
1839 * pch transcoder. */
1840 reg = TRANS_CHICKEN2(pipe);
1841 val = I915_READ(reg);
1842 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1843 I915_WRITE(reg, val);
1844 }
1845
1846 reg = PCH_TRANSCONF(pipe);
1847 val = I915_READ(reg);
1848 pipeconf_val = I915_READ(PIPECONF(pipe));
1849
1850 if (HAS_PCH_IBX(dev_priv)) {
1851 /*
1852 * Make the BPC in transcoder be consistent with
1853 * that in pipeconf reg. For HDMI we must use 8bpc
1854 * here for both 8bpc and 12bpc.
1855 */
1856 val &= ~PIPECONF_BPC_MASK;
1857 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1858 val |= PIPECONF_8BPC;
1859 else
1860 val |= pipeconf_val & PIPECONF_BPC_MASK;
1861 }
1862
1863 val &= ~TRANS_INTERLACE_MASK;
1864 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1865 if (HAS_PCH_IBX(dev_priv) &&
1866 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1867 val |= TRANS_LEGACY_INTERLACED_ILK;
1868 else
1869 val |= TRANS_INTERLACED;
1870 else
1871 val |= TRANS_PROGRESSIVE;
1872
1873 I915_WRITE(reg, val | TRANS_ENABLE);
1874 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1875 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1876 }
1877
1878 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1879 enum transcoder cpu_transcoder)
1880 {
1881 u32 val, pipeconf_val;
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1885 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1886
1887 /* Workaround: set timing override bit. */
1888 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1891
1892 val = TRANS_ENABLE;
1893 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1894
1895 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1896 PIPECONF_INTERLACED_ILK)
1897 val |= TRANS_INTERLACED;
1898 else
1899 val |= TRANS_PROGRESSIVE;
1900
1901 I915_WRITE(LPT_TRANSCONF, val);
1902 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1903 DRM_ERROR("Failed to enable PCH transcoder\n");
1904 }
1905
1906 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1907 enum pipe pipe)
1908 {
1909 struct drm_device *dev = dev_priv->dev;
1910 i915_reg_t reg;
1911 uint32_t val;
1912
1913 /* FDI relies on the transcoder */
1914 assert_fdi_tx_disabled(dev_priv, pipe);
1915 assert_fdi_rx_disabled(dev_priv, pipe);
1916
1917 /* Ports must be off as well */
1918 assert_pch_ports_disabled(dev_priv, pipe);
1919
1920 reg = PCH_TRANSCONF(pipe);
1921 val = I915_READ(reg);
1922 val &= ~TRANS_ENABLE;
1923 I915_WRITE(reg, val);
1924 /* wait for PCH transcoder off, transcoder state */
1925 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1926 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1927
1928 if (HAS_PCH_CPT(dev)) {
1929 /* Workaround: Clear the timing override chicken bit again. */
1930 reg = TRANS_CHICKEN2(pipe);
1931 val = I915_READ(reg);
1932 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1933 I915_WRITE(reg, val);
1934 }
1935 }
1936
1937 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1938 {
1939 u32 val;
1940
1941 val = I915_READ(LPT_TRANSCONF);
1942 val &= ~TRANS_ENABLE;
1943 I915_WRITE(LPT_TRANSCONF, val);
1944 /* wait for PCH transcoder off, transcoder state */
1945 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1946 DRM_ERROR("Failed to disable PCH transcoder\n");
1947
1948 /* Workaround: clear timing override bit. */
1949 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1950 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1952 }
1953
1954 /**
1955 * intel_enable_pipe - enable a pipe, asserting requirements
1956 * @crtc: crtc responsible for the pipe
1957 *
1958 * Enable @crtc's pipe, making sure that various hardware specific requirements
1959 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1960 */
1961 static void intel_enable_pipe(struct intel_crtc *crtc)
1962 {
1963 struct drm_device *dev = crtc->base.dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 enum pipe pipe = crtc->pipe;
1966 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1967 enum pipe pch_transcoder;
1968 i915_reg_t reg;
1969 u32 val;
1970
1971 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1972
1973 assert_planes_disabled(dev_priv, pipe);
1974 assert_cursor_disabled(dev_priv, pipe);
1975 assert_sprites_disabled(dev_priv, pipe);
1976
1977 if (HAS_PCH_LPT(dev_priv))
1978 pch_transcoder = TRANSCODER_A;
1979 else
1980 pch_transcoder = pipe;
1981
1982 /*
1983 * A pipe without a PLL won't actually be able to drive bits from
1984 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1985 * need the check.
1986 */
1987 if (HAS_GMCH_DISPLAY(dev_priv))
1988 if (crtc->config->has_dsi_encoder)
1989 assert_dsi_pll_enabled(dev_priv);
1990 else
1991 assert_pll_enabled(dev_priv, pipe);
1992 else {
1993 if (crtc->config->has_pch_encoder) {
1994 /* if driving the PCH, we need FDI enabled */
1995 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1996 assert_fdi_tx_pll_enabled(dev_priv,
1997 (enum pipe) cpu_transcoder);
1998 }
1999 /* FIXME: assert CPU port conditions for SNB+ */
2000 }
2001
2002 reg = PIPECONF(cpu_transcoder);
2003 val = I915_READ(reg);
2004 if (val & PIPECONF_ENABLE) {
2005 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2006 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2007 return;
2008 }
2009
2010 I915_WRITE(reg, val | PIPECONF_ENABLE);
2011 POSTING_READ(reg);
2012
2013 /*
2014 * Until the pipe starts DSL will read as 0, which would cause
2015 * an apparent vblank timestamp jump, which messes up also the
2016 * frame count when it's derived from the timestamps. So let's
2017 * wait for the pipe to start properly before we call
2018 * drm_crtc_vblank_on()
2019 */
2020 if (dev->max_vblank_count == 0 &&
2021 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2022 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2023 }
2024
2025 /**
2026 * intel_disable_pipe - disable a pipe, asserting requirements
2027 * @crtc: crtc whose pipes is to be disabled
2028 *
2029 * Disable the pipe of @crtc, making sure that various hardware
2030 * specific requirements are met, if applicable, e.g. plane
2031 * disabled, panel fitter off, etc.
2032 *
2033 * Will wait until the pipe has shut down before returning.
2034 */
2035 static void intel_disable_pipe(struct intel_crtc *crtc)
2036 {
2037 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2038 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2039 enum pipe pipe = crtc->pipe;
2040 i915_reg_t reg;
2041 u32 val;
2042
2043 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2044
2045 /*
2046 * Make sure planes won't keep trying to pump pixels to us,
2047 * or we might hang the display.
2048 */
2049 assert_planes_disabled(dev_priv, pipe);
2050 assert_cursor_disabled(dev_priv, pipe);
2051 assert_sprites_disabled(dev_priv, pipe);
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if ((val & PIPECONF_ENABLE) == 0)
2056 return;
2057
2058 /*
2059 * Double wide has implications for planes
2060 * so best keep it disabled when not needed.
2061 */
2062 if (crtc->config->double_wide)
2063 val &= ~PIPECONF_DOUBLE_WIDE;
2064
2065 /* Don't disable pipe or pipe PLLs if needed */
2066 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2067 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2068 val &= ~PIPECONF_ENABLE;
2069
2070 I915_WRITE(reg, val);
2071 if ((val & PIPECONF_ENABLE) == 0)
2072 intel_wait_for_pipe_off(crtc);
2073 }
2074
2075 static bool need_vtd_wa(struct drm_device *dev)
2076 {
2077 #ifdef CONFIG_INTEL_IOMMU
2078 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2079 return true;
2080 #endif
2081 return false;
2082 }
2083
2084 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2085 {
2086 return IS_GEN2(dev_priv) ? 2048 : 4096;
2087 }
2088
2089 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2090 uint64_t fb_modifier, unsigned int cpp)
2091 {
2092 switch (fb_modifier) {
2093 case DRM_FORMAT_MOD_NONE:
2094 return cpp;
2095 case I915_FORMAT_MOD_X_TILED:
2096 if (IS_GEN2(dev_priv))
2097 return 128;
2098 else
2099 return 512;
2100 case I915_FORMAT_MOD_Y_TILED:
2101 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2102 return 128;
2103 else
2104 return 512;
2105 case I915_FORMAT_MOD_Yf_TILED:
2106 switch (cpp) {
2107 case 1:
2108 return 64;
2109 case 2:
2110 case 4:
2111 return 128;
2112 case 8:
2113 case 16:
2114 return 256;
2115 default:
2116 MISSING_CASE(cpp);
2117 return cpp;
2118 }
2119 break;
2120 default:
2121 MISSING_CASE(fb_modifier);
2122 return cpp;
2123 }
2124 }
2125
2126 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2127 uint64_t fb_modifier, unsigned int cpp)
2128 {
2129 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2130 return 1;
2131 else
2132 return intel_tile_size(dev_priv) /
2133 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2134 }
2135
2136 /* Return the tile dimensions in pixel units */
2137 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2138 unsigned int *tile_width,
2139 unsigned int *tile_height,
2140 uint64_t fb_modifier,
2141 unsigned int cpp)
2142 {
2143 unsigned int tile_width_bytes =
2144 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2145
2146 *tile_width = tile_width_bytes / cpp;
2147 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2148 }
2149
2150 unsigned int
2151 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2152 uint32_t pixel_format, uint64_t fb_modifier)
2153 {
2154 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2155 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2156
2157 return ALIGN(height, tile_height);
2158 }
2159
2160 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2161 {
2162 unsigned int size = 0;
2163 int i;
2164
2165 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2166 size += rot_info->plane[i].width * rot_info->plane[i].height;
2167
2168 return size;
2169 }
2170
2171 static void
2172 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2173 const struct drm_framebuffer *fb,
2174 unsigned int rotation)
2175 {
2176 if (intel_rotation_90_or_270(rotation)) {
2177 *view = i915_ggtt_view_rotated;
2178 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2179 } else {
2180 *view = i915_ggtt_view_normal;
2181 }
2182 }
2183
2184 static void
2185 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2186 struct drm_framebuffer *fb)
2187 {
2188 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2189 unsigned int tile_size, tile_width, tile_height, cpp;
2190
2191 tile_size = intel_tile_size(dev_priv);
2192
2193 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2194 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2195 fb->modifier[0], cpp);
2196
2197 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2198 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2199
2200 if (info->pixel_format == DRM_FORMAT_NV12) {
2201 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2202 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2203 fb->modifier[1], cpp);
2204
2205 info->uv_offset = fb->offsets[1];
2206 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2207 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2208 }
2209 }
2210
2211 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2212 {
2213 if (INTEL_INFO(dev_priv)->gen >= 9)
2214 return 256 * 1024;
2215 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2216 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2217 return 128 * 1024;
2218 else if (INTEL_INFO(dev_priv)->gen >= 4)
2219 return 4 * 1024;
2220 else
2221 return 0;
2222 }
2223
2224 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2225 uint64_t fb_modifier)
2226 {
2227 switch (fb_modifier) {
2228 case DRM_FORMAT_MOD_NONE:
2229 return intel_linear_alignment(dev_priv);
2230 case I915_FORMAT_MOD_X_TILED:
2231 if (INTEL_INFO(dev_priv)->gen >= 9)
2232 return 256 * 1024;
2233 return 0;
2234 case I915_FORMAT_MOD_Y_TILED:
2235 case I915_FORMAT_MOD_Yf_TILED:
2236 return 1 * 1024 * 1024;
2237 default:
2238 MISSING_CASE(fb_modifier);
2239 return 0;
2240 }
2241 }
2242
2243 int
2244 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2245 unsigned int rotation)
2246 {
2247 struct drm_device *dev = fb->dev;
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2250 struct i915_ggtt_view view;
2251 u32 alignment;
2252 int ret;
2253
2254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2255
2256 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2257
2258 intel_fill_fb_ggtt_view(&view, fb, rotation);
2259
2260 /* Note that the w/a also requires 64 PTE of padding following the
2261 * bo. We currently fill all unused PTE with the shadow page and so
2262 * we should always have valid PTE following the scanout preventing
2263 * the VT-d warning.
2264 */
2265 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2266 alignment = 256 * 1024;
2267
2268 /*
2269 * Global gtt pte registers are special registers which actually forward
2270 * writes to a chunk of system memory. Which means that there is no risk
2271 * that the register values disappear as soon as we call
2272 * intel_runtime_pm_put(), so it is correct to wrap only the
2273 * pin/unpin/fence and not more.
2274 */
2275 intel_runtime_pm_get(dev_priv);
2276
2277 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2278 &view);
2279 if (ret)
2280 goto err_pm;
2281
2282 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2283 * fence, whereas 965+ only requires a fence if using
2284 * framebuffer compression. For simplicity, we always install
2285 * a fence as the cost is not that onerous.
2286 */
2287 if (view.type == I915_GGTT_VIEW_NORMAL) {
2288 ret = i915_gem_object_get_fence(obj);
2289 if (ret == -EDEADLK) {
2290 /*
2291 * -EDEADLK means there are no free fences
2292 * no pending flips.
2293 *
2294 * This is propagated to atomic, but it uses
2295 * -EDEADLK to force a locking recovery, so
2296 * change the returned error to -EBUSY.
2297 */
2298 ret = -EBUSY;
2299 goto err_unpin;
2300 } else if (ret)
2301 goto err_unpin;
2302
2303 i915_gem_object_pin_fence(obj);
2304 }
2305
2306 intel_runtime_pm_put(dev_priv);
2307 return 0;
2308
2309 err_unpin:
2310 i915_gem_object_unpin_from_display_plane(obj, &view);
2311 err_pm:
2312 intel_runtime_pm_put(dev_priv);
2313 return ret;
2314 }
2315
2316 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2317 {
2318 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2319 struct i915_ggtt_view view;
2320
2321 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2322
2323 intel_fill_fb_ggtt_view(&view, fb, rotation);
2324
2325 if (view.type == I915_GGTT_VIEW_NORMAL)
2326 i915_gem_object_unpin_fence(obj);
2327
2328 i915_gem_object_unpin_from_display_plane(obj, &view);
2329 }
2330
2331 /*
2332 * Adjust the tile offset by moving the difference into
2333 * the x/y offsets.
2334 *
2335 * Input tile dimensions and pitch must already be
2336 * rotated to match x and y, and in pixel units.
2337 */
2338 static u32 intel_adjust_tile_offset(int *x, int *y,
2339 unsigned int tile_width,
2340 unsigned int tile_height,
2341 unsigned int tile_size,
2342 unsigned int pitch_tiles,
2343 u32 old_offset,
2344 u32 new_offset)
2345 {
2346 unsigned int tiles;
2347
2348 WARN_ON(old_offset & (tile_size - 1));
2349 WARN_ON(new_offset & (tile_size - 1));
2350 WARN_ON(new_offset > old_offset);
2351
2352 tiles = (old_offset - new_offset) / tile_size;
2353
2354 *y += tiles / pitch_tiles * tile_height;
2355 *x += tiles % pitch_tiles * tile_width;
2356
2357 return new_offset;
2358 }
2359
2360 /*
2361 * Computes the linear offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2363 *
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2367 */
2368 u32 intel_compute_tile_offset(int *x, int *y,
2369 const struct drm_framebuffer *fb, int plane,
2370 unsigned int pitch,
2371 unsigned int rotation)
2372 {
2373 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2374 uint64_t fb_modifier = fb->modifier[plane];
2375 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2376 u32 offset, offset_aligned, alignment;
2377
2378 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2379 if (alignment)
2380 alignment--;
2381
2382 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2383 unsigned int tile_size, tile_width, tile_height;
2384 unsigned int tile_rows, tiles, pitch_tiles;
2385
2386 tile_size = intel_tile_size(dev_priv);
2387 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2388 fb_modifier, cpp);
2389
2390 if (intel_rotation_90_or_270(rotation)) {
2391 pitch_tiles = pitch / tile_height;
2392 swap(tile_width, tile_height);
2393 } else {
2394 pitch_tiles = pitch / (tile_width * cpp);
2395 }
2396
2397 tile_rows = *y / tile_height;
2398 *y %= tile_height;
2399
2400 tiles = *x / tile_width;
2401 *x %= tile_width;
2402
2403 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2404 offset_aligned = offset & ~alignment;
2405
2406 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2407 tile_size, pitch_tiles,
2408 offset, offset_aligned);
2409 } else {
2410 offset = *y * pitch + *x * cpp;
2411 offset_aligned = offset & ~alignment;
2412
2413 *y = (offset & alignment) / pitch;
2414 *x = ((offset & alignment) - *y * pitch) / cpp;
2415 }
2416
2417 return offset_aligned;
2418 }
2419
2420 static int i9xx_format_to_fourcc(int format)
2421 {
2422 switch (format) {
2423 case DISPPLANE_8BPP:
2424 return DRM_FORMAT_C8;
2425 case DISPPLANE_BGRX555:
2426 return DRM_FORMAT_XRGB1555;
2427 case DISPPLANE_BGRX565:
2428 return DRM_FORMAT_RGB565;
2429 default:
2430 case DISPPLANE_BGRX888:
2431 return DRM_FORMAT_XRGB8888;
2432 case DISPPLANE_RGBX888:
2433 return DRM_FORMAT_XBGR8888;
2434 case DISPPLANE_BGRX101010:
2435 return DRM_FORMAT_XRGB2101010;
2436 case DISPPLANE_RGBX101010:
2437 return DRM_FORMAT_XBGR2101010;
2438 }
2439 }
2440
2441 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2442 {
2443 switch (format) {
2444 case PLANE_CTL_FORMAT_RGB_565:
2445 return DRM_FORMAT_RGB565;
2446 default:
2447 case PLANE_CTL_FORMAT_XRGB_8888:
2448 if (rgb_order) {
2449 if (alpha)
2450 return DRM_FORMAT_ABGR8888;
2451 else
2452 return DRM_FORMAT_XBGR8888;
2453 } else {
2454 if (alpha)
2455 return DRM_FORMAT_ARGB8888;
2456 else
2457 return DRM_FORMAT_XRGB8888;
2458 }
2459 case PLANE_CTL_FORMAT_XRGB_2101010:
2460 if (rgb_order)
2461 return DRM_FORMAT_XBGR2101010;
2462 else
2463 return DRM_FORMAT_XRGB2101010;
2464 }
2465 }
2466
2467 static bool
2468 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2469 struct intel_initial_plane_config *plane_config)
2470 {
2471 struct drm_device *dev = crtc->base.dev;
2472 struct drm_i915_private *dev_priv = to_i915(dev);
2473 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2474 struct drm_i915_gem_object *obj = NULL;
2475 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2476 struct drm_framebuffer *fb = &plane_config->fb->base;
2477 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2478 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2479 PAGE_SIZE);
2480
2481 size_aligned -= base_aligned;
2482
2483 if (plane_config->size == 0)
2484 return false;
2485
2486 /* If the FB is too big, just don't use it since fbdev is not very
2487 * important and we should probably use that space with FBC or other
2488 * features. */
2489 if (size_aligned * 2 > ggtt->stolen_usable_size)
2490 return false;
2491
2492 mutex_lock(&dev->struct_mutex);
2493
2494 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2495 base_aligned,
2496 base_aligned,
2497 size_aligned);
2498 if (!obj) {
2499 mutex_unlock(&dev->struct_mutex);
2500 return false;
2501 }
2502
2503 obj->tiling_mode = plane_config->tiling;
2504 if (obj->tiling_mode == I915_TILING_X)
2505 obj->stride = fb->pitches[0];
2506
2507 mode_cmd.pixel_format = fb->pixel_format;
2508 mode_cmd.width = fb->width;
2509 mode_cmd.height = fb->height;
2510 mode_cmd.pitches[0] = fb->pitches[0];
2511 mode_cmd.modifier[0] = fb->modifier[0];
2512 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2513
2514 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2515 &mode_cmd, obj)) {
2516 DRM_DEBUG_KMS("intel fb init failed\n");
2517 goto out_unref_obj;
2518 }
2519
2520 mutex_unlock(&dev->struct_mutex);
2521
2522 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2523 return true;
2524
2525 out_unref_obj:
2526 drm_gem_object_unreference(&obj->base);
2527 mutex_unlock(&dev->struct_mutex);
2528 return false;
2529 }
2530
2531 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2532 static void
2533 update_state_fb(struct drm_plane *plane)
2534 {
2535 if (plane->fb == plane->state->fb)
2536 return;
2537
2538 if (plane->state->fb)
2539 drm_framebuffer_unreference(plane->state->fb);
2540 plane->state->fb = plane->fb;
2541 if (plane->state->fb)
2542 drm_framebuffer_reference(plane->state->fb);
2543 }
2544
2545 static void
2546 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2547 struct intel_initial_plane_config *plane_config)
2548 {
2549 struct drm_device *dev = intel_crtc->base.dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 struct drm_crtc *c;
2552 struct intel_crtc *i;
2553 struct drm_i915_gem_object *obj;
2554 struct drm_plane *primary = intel_crtc->base.primary;
2555 struct drm_plane_state *plane_state = primary->state;
2556 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2557 struct intel_plane *intel_plane = to_intel_plane(primary);
2558 struct intel_plane_state *intel_state =
2559 to_intel_plane_state(plane_state);
2560 struct drm_framebuffer *fb;
2561
2562 if (!plane_config->fb)
2563 return;
2564
2565 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2566 fb = &plane_config->fb->base;
2567 goto valid_fb;
2568 }
2569
2570 kfree(plane_config->fb);
2571
2572 /*
2573 * Failed to alloc the obj, check to see if we should share
2574 * an fb with another CRTC instead
2575 */
2576 for_each_crtc(dev, c) {
2577 i = to_intel_crtc(c);
2578
2579 if (c == &intel_crtc->base)
2580 continue;
2581
2582 if (!i->active)
2583 continue;
2584
2585 fb = c->primary->fb;
2586 if (!fb)
2587 continue;
2588
2589 obj = intel_fb_obj(fb);
2590 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2591 drm_framebuffer_reference(fb);
2592 goto valid_fb;
2593 }
2594 }
2595
2596 /*
2597 * We've failed to reconstruct the BIOS FB. Current display state
2598 * indicates that the primary plane is visible, but has a NULL FB,
2599 * which will lead to problems later if we don't fix it up. The
2600 * simplest solution is to just disable the primary plane now and
2601 * pretend the BIOS never had it enabled.
2602 */
2603 to_intel_plane_state(plane_state)->visible = false;
2604 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2605 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2606 intel_plane->disable_plane(primary, &intel_crtc->base);
2607
2608 return;
2609
2610 valid_fb:
2611 plane_state->src_x = 0;
2612 plane_state->src_y = 0;
2613 plane_state->src_w = fb->width << 16;
2614 plane_state->src_h = fb->height << 16;
2615
2616 plane_state->crtc_x = 0;
2617 plane_state->crtc_y = 0;
2618 plane_state->crtc_w = fb->width;
2619 plane_state->crtc_h = fb->height;
2620
2621 intel_state->src.x1 = plane_state->src_x;
2622 intel_state->src.y1 = plane_state->src_y;
2623 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2624 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2625 intel_state->dst.x1 = plane_state->crtc_x;
2626 intel_state->dst.y1 = plane_state->crtc_y;
2627 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2628 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2629
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 drm_framebuffer_reference(fb);
2635 primary->fb = primary->state->fb = fb;
2636 primary->crtc = primary->state->crtc = &intel_crtc->base;
2637 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2638 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2639 }
2640
2641 static void i9xx_update_primary_plane(struct drm_plane *primary,
2642 const struct intel_crtc_state *crtc_state,
2643 const struct intel_plane_state *plane_state)
2644 {
2645 struct drm_device *dev = primary->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2648 struct drm_framebuffer *fb = plane_state->base.fb;
2649 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2650 int plane = intel_crtc->plane;
2651 u32 linear_offset;
2652 u32 dspcntr;
2653 i915_reg_t reg = DSPCNTR(plane);
2654 unsigned int rotation = plane_state->base.rotation;
2655 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2656 int x = plane_state->src.x1 >> 16;
2657 int y = plane_state->src.y1 >> 16;
2658
2659 dspcntr = DISPPLANE_GAMMA_ENABLE;
2660
2661 dspcntr |= DISPLAY_PLANE_ENABLE;
2662
2663 if (INTEL_INFO(dev)->gen < 4) {
2664 if (intel_crtc->pipe == PIPE_B)
2665 dspcntr |= DISPPLANE_SEL_PIPE_B;
2666
2667 /* pipesrc and dspsize control the size that is scaled from,
2668 * which should always be the user's requested size.
2669 */
2670 I915_WRITE(DSPSIZE(plane),
2671 ((crtc_state->pipe_src_h - 1) << 16) |
2672 (crtc_state->pipe_src_w - 1));
2673 I915_WRITE(DSPPOS(plane), 0);
2674 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2675 I915_WRITE(PRIMSIZE(plane),
2676 ((crtc_state->pipe_src_h - 1) << 16) |
2677 (crtc_state->pipe_src_w - 1));
2678 I915_WRITE(PRIMPOS(plane), 0);
2679 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2680 }
2681
2682 switch (fb->pixel_format) {
2683 case DRM_FORMAT_C8:
2684 dspcntr |= DISPPLANE_8BPP;
2685 break;
2686 case DRM_FORMAT_XRGB1555:
2687 dspcntr |= DISPPLANE_BGRX555;
2688 break;
2689 case DRM_FORMAT_RGB565:
2690 dspcntr |= DISPPLANE_BGRX565;
2691 break;
2692 case DRM_FORMAT_XRGB8888:
2693 dspcntr |= DISPPLANE_BGRX888;
2694 break;
2695 case DRM_FORMAT_XBGR8888:
2696 dspcntr |= DISPPLANE_RGBX888;
2697 break;
2698 case DRM_FORMAT_XRGB2101010:
2699 dspcntr |= DISPPLANE_BGRX101010;
2700 break;
2701 case DRM_FORMAT_XBGR2101010:
2702 dspcntr |= DISPPLANE_RGBX101010;
2703 break;
2704 default:
2705 BUG();
2706 }
2707
2708 if (INTEL_INFO(dev)->gen >= 4 &&
2709 obj->tiling_mode != I915_TILING_NONE)
2710 dspcntr |= DISPPLANE_TILED;
2711
2712 if (IS_G4X(dev))
2713 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2714
2715 linear_offset = y * fb->pitches[0] + x * cpp;
2716
2717 if (INTEL_INFO(dev)->gen >= 4) {
2718 intel_crtc->dspaddr_offset =
2719 intel_compute_tile_offset(&x, &y, fb, 0,
2720 fb->pitches[0], rotation);
2721 linear_offset -= intel_crtc->dspaddr_offset;
2722 } else {
2723 intel_crtc->dspaddr_offset = linear_offset;
2724 }
2725
2726 if (rotation == BIT(DRM_ROTATE_180)) {
2727 dspcntr |= DISPPLANE_ROTATE_180;
2728
2729 x += (crtc_state->pipe_src_w - 1);
2730 y += (crtc_state->pipe_src_h - 1);
2731
2732 /* Finding the last pixel of the last line of the display
2733 data and adding to linear_offset*/
2734 linear_offset +=
2735 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2736 (crtc_state->pipe_src_w - 1) * cpp;
2737 }
2738
2739 intel_crtc->adjusted_x = x;
2740 intel_crtc->adjusted_y = y;
2741
2742 I915_WRITE(reg, dspcntr);
2743
2744 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 I915_WRITE(DSPSURF(plane),
2747 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2748 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2749 I915_WRITE(DSPLINOFF(plane), linear_offset);
2750 } else
2751 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2752 POSTING_READ(reg);
2753 }
2754
2755 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2756 struct drm_crtc *crtc)
2757 {
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int plane = intel_crtc->plane;
2762
2763 I915_WRITE(DSPCNTR(plane), 0);
2764 if (INTEL_INFO(dev_priv)->gen >= 4)
2765 I915_WRITE(DSPSURF(plane), 0);
2766 else
2767 I915_WRITE(DSPADDR(plane), 0);
2768 POSTING_READ(DSPCNTR(plane));
2769 }
2770
2771 static void ironlake_update_primary_plane(struct drm_plane *primary,
2772 const struct intel_crtc_state *crtc_state,
2773 const struct intel_plane_state *plane_state)
2774 {
2775 struct drm_device *dev = primary->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2778 struct drm_framebuffer *fb = plane_state->base.fb;
2779 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2780 int plane = intel_crtc->plane;
2781 u32 linear_offset;
2782 u32 dspcntr;
2783 i915_reg_t reg = DSPCNTR(plane);
2784 unsigned int rotation = plane_state->base.rotation;
2785 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2786 int x = plane_state->src.x1 >> 16;
2787 int y = plane_state->src.y1 >> 16;
2788
2789 dspcntr = DISPPLANE_GAMMA_ENABLE;
2790 dspcntr |= DISPLAY_PLANE_ENABLE;
2791
2792 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2793 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2794
2795 switch (fb->pixel_format) {
2796 case DRM_FORMAT_C8:
2797 dspcntr |= DISPPLANE_8BPP;
2798 break;
2799 case DRM_FORMAT_RGB565:
2800 dspcntr |= DISPPLANE_BGRX565;
2801 break;
2802 case DRM_FORMAT_XRGB8888:
2803 dspcntr |= DISPPLANE_BGRX888;
2804 break;
2805 case DRM_FORMAT_XBGR8888:
2806 dspcntr |= DISPPLANE_RGBX888;
2807 break;
2808 case DRM_FORMAT_XRGB2101010:
2809 dspcntr |= DISPPLANE_BGRX101010;
2810 break;
2811 case DRM_FORMAT_XBGR2101010:
2812 dspcntr |= DISPPLANE_RGBX101010;
2813 break;
2814 default:
2815 BUG();
2816 }
2817
2818 if (obj->tiling_mode != I915_TILING_NONE)
2819 dspcntr |= DISPPLANE_TILED;
2820
2821 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2822 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2823
2824 linear_offset = y * fb->pitches[0] + x * cpp;
2825 intel_crtc->dspaddr_offset =
2826 intel_compute_tile_offset(&x, &y, fb, 0,
2827 fb->pitches[0], rotation);
2828 linear_offset -= intel_crtc->dspaddr_offset;
2829 if (rotation == BIT(DRM_ROTATE_180)) {
2830 dspcntr |= DISPPLANE_ROTATE_180;
2831
2832 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2833 x += (crtc_state->pipe_src_w - 1);
2834 y += (crtc_state->pipe_src_h - 1);
2835
2836 /* Finding the last pixel of the last line of the display
2837 data and adding to linear_offset*/
2838 linear_offset +=
2839 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2840 (crtc_state->pipe_src_w - 1) * cpp;
2841 }
2842 }
2843
2844 intel_crtc->adjusted_x = x;
2845 intel_crtc->adjusted_y = y;
2846
2847 I915_WRITE(reg, dspcntr);
2848
2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
2858 POSTING_READ(reg);
2859 }
2860
2861 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2862 uint64_t fb_modifier, uint32_t pixel_format)
2863 {
2864 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2865 return 64;
2866 } else {
2867 int cpp = drm_format_plane_cpp(pixel_format, 0);
2868
2869 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2870 }
2871 }
2872
2873 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2874 struct drm_i915_gem_object *obj,
2875 unsigned int plane)
2876 {
2877 struct i915_ggtt_view view;
2878 struct i915_vma *vma;
2879 u64 offset;
2880
2881 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2882 intel_plane->base.state->rotation);
2883
2884 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2885 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2886 view.type))
2887 return -1;
2888
2889 offset = vma->node.start;
2890
2891 if (plane == 1) {
2892 offset += vma->ggtt_view.params.rotated.uv_start_page *
2893 PAGE_SIZE;
2894 }
2895
2896 WARN_ON(upper_32_bits(offset));
2897
2898 return lower_32_bits(offset);
2899 }
2900
2901 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2902 {
2903 struct drm_device *dev = intel_crtc->base.dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2907 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2908 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2909 }
2910
2911 /*
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2913 */
2914 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2915 {
2916 struct intel_crtc_scaler_state *scaler_state;
2917 int i;
2918
2919 scaler_state = &intel_crtc->config->scaler_state;
2920
2921 /* loop through and disable scalers that aren't in use */
2922 for (i = 0; i < intel_crtc->num_scalers; i++) {
2923 if (!scaler_state->scalers[i].in_use)
2924 skl_detach_scaler(intel_crtc, i);
2925 }
2926 }
2927
2928 u32 skl_plane_ctl_format(uint32_t pixel_format)
2929 {
2930 switch (pixel_format) {
2931 case DRM_FORMAT_C8:
2932 return PLANE_CTL_FORMAT_INDEXED;
2933 case DRM_FORMAT_RGB565:
2934 return PLANE_CTL_FORMAT_RGB_565;
2935 case DRM_FORMAT_XBGR8888:
2936 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2937 case DRM_FORMAT_XRGB8888:
2938 return PLANE_CTL_FORMAT_XRGB_8888;
2939 /*
2940 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2941 * to be already pre-multiplied. We need to add a knob (or a different
2942 * DRM_FORMAT) for user-space to configure that.
2943 */
2944 case DRM_FORMAT_ABGR8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2947 case DRM_FORMAT_ARGB8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888 |
2949 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2950 case DRM_FORMAT_XRGB2101010:
2951 return PLANE_CTL_FORMAT_XRGB_2101010;
2952 case DRM_FORMAT_XBGR2101010:
2953 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2954 case DRM_FORMAT_YUYV:
2955 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2956 case DRM_FORMAT_YVYU:
2957 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2958 case DRM_FORMAT_UYVY:
2959 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2960 case DRM_FORMAT_VYUY:
2961 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2962 default:
2963 MISSING_CASE(pixel_format);
2964 }
2965
2966 return 0;
2967 }
2968
2969 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2970 {
2971 switch (fb_modifier) {
2972 case DRM_FORMAT_MOD_NONE:
2973 break;
2974 case I915_FORMAT_MOD_X_TILED:
2975 return PLANE_CTL_TILED_X;
2976 case I915_FORMAT_MOD_Y_TILED:
2977 return PLANE_CTL_TILED_Y;
2978 case I915_FORMAT_MOD_Yf_TILED:
2979 return PLANE_CTL_TILED_YF;
2980 default:
2981 MISSING_CASE(fb_modifier);
2982 }
2983
2984 return 0;
2985 }
2986
2987 u32 skl_plane_ctl_rotation(unsigned int rotation)
2988 {
2989 switch (rotation) {
2990 case BIT(DRM_ROTATE_0):
2991 break;
2992 /*
2993 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2994 * while i915 HW rotation is clockwise, thats why this swapping.
2995 */
2996 case BIT(DRM_ROTATE_90):
2997 return PLANE_CTL_ROTATE_270;
2998 case BIT(DRM_ROTATE_180):
2999 return PLANE_CTL_ROTATE_180;
3000 case BIT(DRM_ROTATE_270):
3001 return PLANE_CTL_ROTATE_90;
3002 default:
3003 MISSING_CASE(rotation);
3004 }
3005
3006 return 0;
3007 }
3008
3009 static void skylake_update_primary_plane(struct drm_plane *plane,
3010 const struct intel_crtc_state *crtc_state,
3011 const struct intel_plane_state *plane_state)
3012 {
3013 struct drm_device *dev = plane->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3016 struct drm_framebuffer *fb = plane_state->base.fb;
3017 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3018 int pipe = intel_crtc->pipe;
3019 u32 plane_ctl, stride_div, stride;
3020 u32 tile_height, plane_offset, plane_size;
3021 unsigned int rotation = plane_state->base.rotation;
3022 int x_offset, y_offset;
3023 u32 surf_addr;
3024 int scaler_id = plane_state->scaler_id;
3025 int src_x = plane_state->src.x1 >> 16;
3026 int src_y = plane_state->src.y1 >> 16;
3027 int src_w = drm_rect_width(&plane_state->src) >> 16;
3028 int src_h = drm_rect_height(&plane_state->src) >> 16;
3029 int dst_x = plane_state->dst.x1;
3030 int dst_y = plane_state->dst.y1;
3031 int dst_w = drm_rect_width(&plane_state->dst);
3032 int dst_h = drm_rect_height(&plane_state->dst);
3033
3034 plane_ctl = PLANE_CTL_ENABLE |
3035 PLANE_CTL_PIPE_GAMMA_ENABLE |
3036 PLANE_CTL_PIPE_CSC_ENABLE;
3037
3038 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3039 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3040 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3041 plane_ctl |= skl_plane_ctl_rotation(rotation);
3042
3043 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3044 fb->pixel_format);
3045 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3046
3047 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3048
3049 if (intel_rotation_90_or_270(rotation)) {
3050 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3051
3052 /* stride = Surface height in tiles */
3053 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3054 stride = DIV_ROUND_UP(fb->height, tile_height);
3055 x_offset = stride * tile_height - src_y - src_h;
3056 y_offset = src_x;
3057 plane_size = (src_w - 1) << 16 | (src_h - 1);
3058 } else {
3059 stride = fb->pitches[0] / stride_div;
3060 x_offset = src_x;
3061 y_offset = src_y;
3062 plane_size = (src_h - 1) << 16 | (src_w - 1);
3063 }
3064 plane_offset = y_offset << 16 | x_offset;
3065
3066 intel_crtc->adjusted_x = x_offset;
3067 intel_crtc->adjusted_y = y_offset;
3068
3069 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3070 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3071 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3072 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3073
3074 if (scaler_id >= 0) {
3075 uint32_t ps_ctrl = 0;
3076
3077 WARN_ON(!dst_w || !dst_h);
3078 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3079 crtc_state->scaler_state.scalers[scaler_id].mode;
3080 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3081 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3082 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3083 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3084 I915_WRITE(PLANE_POS(pipe, 0), 0);
3085 } else {
3086 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3087 }
3088
3089 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3090
3091 POSTING_READ(PLANE_SURF(pipe, 0));
3092 }
3093
3094 static void skylake_disable_primary_plane(struct drm_plane *primary,
3095 struct drm_crtc *crtc)
3096 {
3097 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 int pipe = to_intel_crtc(crtc)->pipe;
3100
3101 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3102 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3103 POSTING_READ(PLANE_SURF(pipe, 0));
3104 }
3105
3106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3107 static int
3108 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3109 int x, int y, enum mode_set_atomic state)
3110 {
3111 /* Support for kgdboc is disabled, this needs a major rework. */
3112 DRM_ERROR("legacy panic handler not supported any more.\n");
3113
3114 return -ENODEV;
3115 }
3116
3117 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3118 {
3119 struct intel_crtc *crtc;
3120
3121 for_each_intel_crtc(dev_priv->dev, crtc)
3122 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3123 }
3124
3125 static void intel_update_primary_planes(struct drm_device *dev)
3126 {
3127 struct drm_crtc *crtc;
3128
3129 for_each_crtc(dev, crtc) {
3130 struct intel_plane *plane = to_intel_plane(crtc->primary);
3131 struct intel_plane_state *plane_state;
3132
3133 drm_modeset_lock_crtc(crtc, &plane->base);
3134 plane_state = to_intel_plane_state(plane->base.state);
3135
3136 if (plane_state->visible)
3137 plane->update_plane(&plane->base,
3138 to_intel_crtc_state(crtc->state),
3139 plane_state);
3140
3141 drm_modeset_unlock_crtc(crtc);
3142 }
3143 }
3144
3145 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3146 {
3147 /* no reset support for gen2 */
3148 if (IS_GEN2(dev_priv))
3149 return;
3150
3151 /* reset doesn't touch the display */
3152 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3153 return;
3154
3155 drm_modeset_lock_all(dev_priv->dev);
3156 /*
3157 * Disabling the crtcs gracefully seems nicer. Also the
3158 * g33 docs say we should at least disable all the planes.
3159 */
3160 intel_display_suspend(dev_priv->dev);
3161 }
3162
3163 void intel_finish_reset(struct drm_i915_private *dev_priv)
3164 {
3165 /*
3166 * Flips in the rings will be nuked by the reset,
3167 * so complete all pending flips so that user space
3168 * will get its events and not get stuck.
3169 */
3170 intel_complete_page_flips(dev_priv);
3171
3172 /* no reset support for gen2 */
3173 if (IS_GEN2(dev_priv))
3174 return;
3175
3176 /* reset doesn't touch the display */
3177 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3178 /*
3179 * Flips in the rings have been nuked by the reset,
3180 * so update the base address of all primary
3181 * planes to the the last fb to make sure we're
3182 * showing the correct fb after a reset.
3183 *
3184 * FIXME: Atomic will make this obsolete since we won't schedule
3185 * CS-based flips (which might get lost in gpu resets) any more.
3186 */
3187 intel_update_primary_planes(dev_priv->dev);
3188 return;
3189 }
3190
3191 /*
3192 * The display has been reset as well,
3193 * so need a full re-initialization.
3194 */
3195 intel_runtime_pm_disable_interrupts(dev_priv);
3196 intel_runtime_pm_enable_interrupts(dev_priv);
3197
3198 intel_modeset_init_hw(dev_priv->dev);
3199
3200 spin_lock_irq(&dev_priv->irq_lock);
3201 if (dev_priv->display.hpd_irq_setup)
3202 dev_priv->display.hpd_irq_setup(dev_priv);
3203 spin_unlock_irq(&dev_priv->irq_lock);
3204
3205 intel_display_resume(dev_priv->dev);
3206
3207 intel_hpd_init(dev_priv);
3208
3209 drm_modeset_unlock_all(dev_priv->dev);
3210 }
3211
3212 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3213 {
3214 struct drm_device *dev = crtc->dev;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 unsigned reset_counter;
3217 bool pending;
3218
3219 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3220 if (intel_crtc->reset_counter != reset_counter)
3221 return false;
3222
3223 spin_lock_irq(&dev->event_lock);
3224 pending = to_intel_crtc(crtc)->flip_work != NULL;
3225 spin_unlock_irq(&dev->event_lock);
3226
3227 return pending;
3228 }
3229
3230 static void intel_update_pipe_config(struct intel_crtc *crtc,
3231 struct intel_crtc_state *old_crtc_state)
3232 {
3233 struct drm_device *dev = crtc->base.dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc_state *pipe_config =
3236 to_intel_crtc_state(crtc->base.state);
3237
3238 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3239 crtc->base.mode = crtc->base.state->mode;
3240
3241 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3242 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3243 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3244
3245 /*
3246 * Update pipe size and adjust fitter if needed: the reason for this is
3247 * that in compute_mode_changes we check the native mode (not the pfit
3248 * mode) to see if we can flip rather than do a full mode set. In the
3249 * fastboot case, we'll flip, but if we don't update the pipesrc and
3250 * pfit state, we'll end up with a big fb scanned out into the wrong
3251 * sized surface.
3252 */
3253
3254 I915_WRITE(PIPESRC(crtc->pipe),
3255 ((pipe_config->pipe_src_w - 1) << 16) |
3256 (pipe_config->pipe_src_h - 1));
3257
3258 /* on skylake this is done by detaching scalers */
3259 if (INTEL_INFO(dev)->gen >= 9) {
3260 skl_detach_scalers(crtc);
3261
3262 if (pipe_config->pch_pfit.enabled)
3263 skylake_pfit_enable(crtc);
3264 } else if (HAS_PCH_SPLIT(dev)) {
3265 if (pipe_config->pch_pfit.enabled)
3266 ironlake_pfit_enable(crtc);
3267 else if (old_crtc_state->pch_pfit.enabled)
3268 ironlake_pfit_disable(crtc, true);
3269 }
3270 }
3271
3272 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3273 {
3274 struct drm_device *dev = crtc->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277 int pipe = intel_crtc->pipe;
3278 i915_reg_t reg;
3279 u32 temp;
3280
3281 /* enable normal train */
3282 reg = FDI_TX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 if (IS_IVYBRIDGE(dev)) {
3285 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3286 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3287 } else {
3288 temp &= ~FDI_LINK_TRAIN_NONE;
3289 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3290 }
3291 I915_WRITE(reg, temp);
3292
3293 reg = FDI_RX_CTL(pipe);
3294 temp = I915_READ(reg);
3295 if (HAS_PCH_CPT(dev)) {
3296 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3297 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3298 } else {
3299 temp &= ~FDI_LINK_TRAIN_NONE;
3300 temp |= FDI_LINK_TRAIN_NONE;
3301 }
3302 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3303
3304 /* wait one idle pattern time */
3305 POSTING_READ(reg);
3306 udelay(1000);
3307
3308 /* IVB wants error correction enabled */
3309 if (IS_IVYBRIDGE(dev))
3310 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3311 FDI_FE_ERRC_ENABLE);
3312 }
3313
3314 /* The FDI link training functions for ILK/Ibexpeak. */
3315 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 int pipe = intel_crtc->pipe;
3321 i915_reg_t reg;
3322 u32 temp, tries;
3323
3324 /* FDI needs bits from pipe first */
3325 assert_pipe_enabled(dev_priv, pipe);
3326
3327 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3328 for train result */
3329 reg = FDI_RX_IMR(pipe);
3330 temp = I915_READ(reg);
3331 temp &= ~FDI_RX_SYMBOL_LOCK;
3332 temp &= ~FDI_RX_BIT_LOCK;
3333 I915_WRITE(reg, temp);
3334 I915_READ(reg);
3335 udelay(150);
3336
3337 /* enable CPU FDI TX and PCH FDI RX */
3338 reg = FDI_TX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3341 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3342 temp &= ~FDI_LINK_TRAIN_NONE;
3343 temp |= FDI_LINK_TRAIN_PATTERN_1;
3344 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3345
3346 reg = FDI_RX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~FDI_LINK_TRAIN_NONE;
3349 temp |= FDI_LINK_TRAIN_PATTERN_1;
3350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3351
3352 POSTING_READ(reg);
3353 udelay(150);
3354
3355 /* Ironlake workaround, enable clock pointer after FDI enable*/
3356 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3357 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3358 FDI_RX_PHASE_SYNC_POINTER_EN);
3359
3360 reg = FDI_RX_IIR(pipe);
3361 for (tries = 0; tries < 5; tries++) {
3362 temp = I915_READ(reg);
3363 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3364
3365 if ((temp & FDI_RX_BIT_LOCK)) {
3366 DRM_DEBUG_KMS("FDI train 1 done.\n");
3367 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3368 break;
3369 }
3370 }
3371 if (tries == 5)
3372 DRM_ERROR("FDI train 1 fail!\n");
3373
3374 /* Train 2 */
3375 reg = FDI_TX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 I915_WRITE(reg, temp);
3380
3381 reg = FDI_RX_CTL(pipe);
3382 temp = I915_READ(reg);
3383 temp &= ~FDI_LINK_TRAIN_NONE;
3384 temp |= FDI_LINK_TRAIN_PATTERN_2;
3385 I915_WRITE(reg, temp);
3386
3387 POSTING_READ(reg);
3388 udelay(150);
3389
3390 reg = FDI_RX_IIR(pipe);
3391 for (tries = 0; tries < 5; tries++) {
3392 temp = I915_READ(reg);
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3394
3395 if (temp & FDI_RX_SYMBOL_LOCK) {
3396 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3397 DRM_DEBUG_KMS("FDI train 2 done.\n");
3398 break;
3399 }
3400 }
3401 if (tries == 5)
3402 DRM_ERROR("FDI train 2 fail!\n");
3403
3404 DRM_DEBUG_KMS("FDI train done\n");
3405
3406 }
3407
3408 static const int snb_b_fdi_train_param[] = {
3409 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3410 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3411 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3412 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3413 };
3414
3415 /* The FDI link training functions for SNB/Cougarpoint. */
3416 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3417 {
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 i915_reg_t reg;
3423 u32 temp, i, retry;
3424
3425 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3426 for train result */
3427 reg = FDI_RX_IMR(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_RX_SYMBOL_LOCK;
3430 temp &= ~FDI_RX_BIT_LOCK;
3431 I915_WRITE(reg, temp);
3432
3433 POSTING_READ(reg);
3434 udelay(150);
3435
3436 /* enable CPU FDI TX and PCH FDI RX */
3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3440 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_1;
3443 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3444 /* SNB-B */
3445 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3447
3448 I915_WRITE(FDI_RX_MISC(pipe),
3449 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 if (HAS_PCH_CPT(dev)) {
3454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3456 } else {
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_1;
3459 }
3460 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3461
3462 POSTING_READ(reg);
3463 udelay(150);
3464
3465 for (i = 0; i < 4; i++) {
3466 reg = FDI_TX_CTL(pipe);
3467 temp = I915_READ(reg);
3468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3469 temp |= snb_b_fdi_train_param[i];
3470 I915_WRITE(reg, temp);
3471
3472 POSTING_READ(reg);
3473 udelay(500);
3474
3475 for (retry = 0; retry < 5; retry++) {
3476 reg = FDI_RX_IIR(pipe);
3477 temp = I915_READ(reg);
3478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3479 if (temp & FDI_RX_BIT_LOCK) {
3480 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3481 DRM_DEBUG_KMS("FDI train 1 done.\n");
3482 break;
3483 }
3484 udelay(50);
3485 }
3486 if (retry < 5)
3487 break;
3488 }
3489 if (i == 4)
3490 DRM_ERROR("FDI train 1 fail!\n");
3491
3492 /* Train 2 */
3493 reg = FDI_TX_CTL(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_LINK_TRAIN_NONE;
3496 temp |= FDI_LINK_TRAIN_PATTERN_2;
3497 if (IS_GEN6(dev)) {
3498 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3499 /* SNB-B */
3500 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3501 }
3502 I915_WRITE(reg, temp);
3503
3504 reg = FDI_RX_CTL(pipe);
3505 temp = I915_READ(reg);
3506 if (HAS_PCH_CPT(dev)) {
3507 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3508 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3509 } else {
3510 temp &= ~FDI_LINK_TRAIN_NONE;
3511 temp |= FDI_LINK_TRAIN_PATTERN_2;
3512 }
3513 I915_WRITE(reg, temp);
3514
3515 POSTING_READ(reg);
3516 udelay(150);
3517
3518 for (i = 0; i < 4; i++) {
3519 reg = FDI_TX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522 temp |= snb_b_fdi_train_param[i];
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(500);
3527
3528 for (retry = 0; retry < 5; retry++) {
3529 reg = FDI_RX_IIR(pipe);
3530 temp = I915_READ(reg);
3531 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3532 if (temp & FDI_RX_SYMBOL_LOCK) {
3533 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3534 DRM_DEBUG_KMS("FDI train 2 done.\n");
3535 break;
3536 }
3537 udelay(50);
3538 }
3539 if (retry < 5)
3540 break;
3541 }
3542 if (i == 4)
3543 DRM_ERROR("FDI train 2 fail!\n");
3544
3545 DRM_DEBUG_KMS("FDI train done.\n");
3546 }
3547
3548 /* Manual link training for Ivy Bridge A0 parts */
3549 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 int pipe = intel_crtc->pipe;
3555 i915_reg_t reg;
3556 u32 temp, i, j;
3557
3558 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3559 for train result */
3560 reg = FDI_RX_IMR(pipe);
3561 temp = I915_READ(reg);
3562 temp &= ~FDI_RX_SYMBOL_LOCK;
3563 temp &= ~FDI_RX_BIT_LOCK;
3564 I915_WRITE(reg, temp);
3565
3566 POSTING_READ(reg);
3567 udelay(150);
3568
3569 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3570 I915_READ(FDI_RX_IIR(pipe)));
3571
3572 /* Try each vswing and preemphasis setting twice before moving on */
3573 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3574 /* disable first in case we need to retry */
3575 reg = FDI_TX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3578 temp &= ~FDI_TX_ENABLE;
3579 I915_WRITE(reg, temp);
3580
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 temp &= ~FDI_LINK_TRAIN_AUTO;
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp &= ~FDI_RX_ENABLE;
3586 I915_WRITE(reg, temp);
3587
3588 /* enable CPU FDI TX and PCH FDI RX */
3589 reg = FDI_TX_CTL(pipe);
3590 temp = I915_READ(reg);
3591 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3592 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3593 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3595 temp |= snb_b_fdi_train_param[j/2];
3596 temp |= FDI_COMPOSITE_SYNC;
3597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3598
3599 I915_WRITE(FDI_RX_MISC(pipe),
3600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3601
3602 reg = FDI_RX_CTL(pipe);
3603 temp = I915_READ(reg);
3604 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3605 temp |= FDI_COMPOSITE_SYNC;
3606 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3607
3608 POSTING_READ(reg);
3609 udelay(1); /* should be 0.5us */
3610
3611 for (i = 0; i < 4; i++) {
3612 reg = FDI_RX_IIR(pipe);
3613 temp = I915_READ(reg);
3614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3615
3616 if (temp & FDI_RX_BIT_LOCK ||
3617 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3618 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3619 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3620 i);
3621 break;
3622 }
3623 udelay(1); /* should be 0.5us */
3624 }
3625 if (i == 4) {
3626 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3627 continue;
3628 }
3629
3630 /* Train 2 */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3634 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3635 I915_WRITE(reg, temp);
3636
3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3640 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3641 I915_WRITE(reg, temp);
3642
3643 POSTING_READ(reg);
3644 udelay(2); /* should be 1.5us */
3645
3646 for (i = 0; i < 4; i++) {
3647 reg = FDI_RX_IIR(pipe);
3648 temp = I915_READ(reg);
3649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3650
3651 if (temp & FDI_RX_SYMBOL_LOCK ||
3652 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3653 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3654 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3655 i);
3656 goto train_done;
3657 }
3658 udelay(2); /* should be 1.5us */
3659 }
3660 if (i == 4)
3661 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3662 }
3663
3664 train_done:
3665 DRM_DEBUG_KMS("FDI train done.\n");
3666 }
3667
3668 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3669 {
3670 struct drm_device *dev = intel_crtc->base.dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 int pipe = intel_crtc->pipe;
3673 i915_reg_t reg;
3674 u32 temp;
3675
3676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3682 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3683
3684 POSTING_READ(reg);
3685 udelay(200);
3686
3687 /* Switch from Rawclk to PCDclk */
3688 temp = I915_READ(reg);
3689 I915_WRITE(reg, temp | FDI_PCDCLK);
3690
3691 POSTING_READ(reg);
3692 udelay(200);
3693
3694 /* Enable CPU FDI TX PLL, always on for Ironlake */
3695 reg = FDI_TX_CTL(pipe);
3696 temp = I915_READ(reg);
3697 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3698 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3699
3700 POSTING_READ(reg);
3701 udelay(100);
3702 }
3703 }
3704
3705 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3706 {
3707 struct drm_device *dev = intel_crtc->base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 int pipe = intel_crtc->pipe;
3710 i915_reg_t reg;
3711 u32 temp;
3712
3713 /* Switch from PCDclk to Rawclk */
3714 reg = FDI_RX_CTL(pipe);
3715 temp = I915_READ(reg);
3716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3717
3718 /* Disable CPU FDI TX PLL */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3722
3723 POSTING_READ(reg);
3724 udelay(100);
3725
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3729
3730 /* Wait for the clocks to turn off. */
3731 POSTING_READ(reg);
3732 udelay(100);
3733 }
3734
3735 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3736 {
3737 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740 int pipe = intel_crtc->pipe;
3741 i915_reg_t reg;
3742 u32 temp;
3743
3744 /* disable CPU FDI tx and PCH FDI rx */
3745 reg = FDI_TX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3748 POSTING_READ(reg);
3749
3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~(0x7 << 16);
3753 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3754 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758
3759 /* Ironlake workaround, disable clock pointer after downing FDI */
3760 if (HAS_PCH_IBX(dev))
3761 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3762
3763 /* still set train pattern 1 */
3764 reg = FDI_TX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 temp &= ~FDI_LINK_TRAIN_NONE;
3767 temp |= FDI_LINK_TRAIN_PATTERN_1;
3768 I915_WRITE(reg, temp);
3769
3770 reg = FDI_RX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 if (HAS_PCH_CPT(dev)) {
3773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3775 } else {
3776 temp &= ~FDI_LINK_TRAIN_NONE;
3777 temp |= FDI_LINK_TRAIN_PATTERN_1;
3778 }
3779 /* BPC in FDI rx is consistent with that in PIPECONF */
3780 temp &= ~(0x07 << 16);
3781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3782 I915_WRITE(reg, temp);
3783
3784 POSTING_READ(reg);
3785 udelay(100);
3786 }
3787
3788 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3789 {
3790 struct intel_crtc *crtc;
3791
3792 /* Note that we don't need to be called with mode_config.lock here
3793 * as our list of CRTC objects is static for the lifetime of the
3794 * device and so cannot disappear as we iterate. Similarly, we can
3795 * happily treat the predicates as racy, atomic checks as userspace
3796 * cannot claim and pin a new fb without at least acquring the
3797 * struct_mutex and so serialising with us.
3798 */
3799 for_each_intel_crtc(dev, crtc) {
3800 if (atomic_read(&crtc->unpin_work_count) == 0)
3801 continue;
3802
3803 if (crtc->flip_work)
3804 intel_wait_for_vblank(dev, crtc->pipe);
3805
3806 return true;
3807 }
3808
3809 return false;
3810 }
3811
3812 static void page_flip_completed(struct intel_crtc *intel_crtc)
3813 {
3814 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3815 struct intel_flip_work *work = intel_crtc->flip_work;
3816
3817 intel_crtc->flip_work = NULL;
3818
3819 if (work->event)
3820 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3821
3822 drm_crtc_vblank_put(&intel_crtc->base);
3823
3824 wake_up_all(&dev_priv->pending_flip_queue);
3825 queue_work(dev_priv->wq, &work->unpin_work);
3826
3827 trace_i915_flip_complete(intel_crtc->plane,
3828 work->pending_flip_obj);
3829 }
3830
3831 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3832 {
3833 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 long ret;
3836
3837 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3838
3839 ret = wait_event_interruptible_timeout(
3840 dev_priv->pending_flip_queue,
3841 !intel_crtc_has_pending_flip(crtc),
3842 60*HZ);
3843
3844 if (ret < 0)
3845 return ret;
3846
3847 if (ret == 0) {
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 struct intel_flip_work *work;
3850
3851 spin_lock_irq(&dev->event_lock);
3852 work = intel_crtc->flip_work;
3853 if (work && !is_mmio_work(work)) {
3854 WARN_ONCE(1, "Removing stuck page flip\n");
3855 page_flip_completed(intel_crtc);
3856 }
3857 spin_unlock_irq(&dev->event_lock);
3858 }
3859
3860 return 0;
3861 }
3862
3863 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3864 {
3865 u32 temp;
3866
3867 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3868
3869 mutex_lock(&dev_priv->sb_lock);
3870
3871 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3872 temp |= SBI_SSCCTL_DISABLE;
3873 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3874
3875 mutex_unlock(&dev_priv->sb_lock);
3876 }
3877
3878 /* Program iCLKIP clock to the desired frequency */
3879 static void lpt_program_iclkip(struct drm_crtc *crtc)
3880 {
3881 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3882 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3883 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3884 u32 temp;
3885
3886 lpt_disable_iclkip(dev_priv);
3887
3888 /* The iCLK virtual clock root frequency is in MHz,
3889 * but the adjusted_mode->crtc_clock in in KHz. To get the
3890 * divisors, it is necessary to divide one by another, so we
3891 * convert the virtual clock precision to KHz here for higher
3892 * precision.
3893 */
3894 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3895 u32 iclk_virtual_root_freq = 172800 * 1000;
3896 u32 iclk_pi_range = 64;
3897 u32 desired_divisor;
3898
3899 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3900 clock << auxdiv);
3901 divsel = (desired_divisor / iclk_pi_range) - 2;
3902 phaseinc = desired_divisor % iclk_pi_range;
3903
3904 /*
3905 * Near 20MHz is a corner case which is
3906 * out of range for the 7-bit divisor
3907 */
3908 if (divsel <= 0x7f)
3909 break;
3910 }
3911
3912 /* This should not happen with any sane values */
3913 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3914 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3915 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3916 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3917
3918 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3919 clock,
3920 auxdiv,
3921 divsel,
3922 phasedir,
3923 phaseinc);
3924
3925 mutex_lock(&dev_priv->sb_lock);
3926
3927 /* Program SSCDIVINTPHASE6 */
3928 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3929 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3930 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3931 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3932 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3933 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3934 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3935 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3936
3937 /* Program SSCAUXDIV */
3938 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3939 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3940 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3941 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3942
3943 /* Enable modulator and associated divider */
3944 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3945 temp &= ~SBI_SSCCTL_DISABLE;
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3947
3948 mutex_unlock(&dev_priv->sb_lock);
3949
3950 /* Wait for initialization time */
3951 udelay(24);
3952
3953 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3954 }
3955
3956 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3957 {
3958 u32 divsel, phaseinc, auxdiv;
3959 u32 iclk_virtual_root_freq = 172800 * 1000;
3960 u32 iclk_pi_range = 64;
3961 u32 desired_divisor;
3962 u32 temp;
3963
3964 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3965 return 0;
3966
3967 mutex_lock(&dev_priv->sb_lock);
3968
3969 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3970 if (temp & SBI_SSCCTL_DISABLE) {
3971 mutex_unlock(&dev_priv->sb_lock);
3972 return 0;
3973 }
3974
3975 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3976 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3977 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3978 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3979 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3980
3981 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3982 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3983 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3984
3985 mutex_unlock(&dev_priv->sb_lock);
3986
3987 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3988
3989 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3990 desired_divisor << auxdiv);
3991 }
3992
3993 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3994 enum pipe pch_transcoder)
3995 {
3996 struct drm_device *dev = crtc->base.dev;
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3999
4000 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4001 I915_READ(HTOTAL(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4003 I915_READ(HBLANK(cpu_transcoder)));
4004 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4005 I915_READ(HSYNC(cpu_transcoder)));
4006
4007 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4008 I915_READ(VTOTAL(cpu_transcoder)));
4009 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4010 I915_READ(VBLANK(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4012 I915_READ(VSYNC(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4014 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4015 }
4016
4017 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4018 {
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 uint32_t temp;
4021
4022 temp = I915_READ(SOUTH_CHICKEN1);
4023 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4024 return;
4025
4026 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4027 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4028
4029 temp &= ~FDI_BC_BIFURCATION_SELECT;
4030 if (enable)
4031 temp |= FDI_BC_BIFURCATION_SELECT;
4032
4033 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4034 I915_WRITE(SOUTH_CHICKEN1, temp);
4035 POSTING_READ(SOUTH_CHICKEN1);
4036 }
4037
4038 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4039 {
4040 struct drm_device *dev = intel_crtc->base.dev;
4041
4042 switch (intel_crtc->pipe) {
4043 case PIPE_A:
4044 break;
4045 case PIPE_B:
4046 if (intel_crtc->config->fdi_lanes > 2)
4047 cpt_set_fdi_bc_bifurcation(dev, false);
4048 else
4049 cpt_set_fdi_bc_bifurcation(dev, true);
4050
4051 break;
4052 case PIPE_C:
4053 cpt_set_fdi_bc_bifurcation(dev, true);
4054
4055 break;
4056 default:
4057 BUG();
4058 }
4059 }
4060
4061 /* Return which DP Port should be selected for Transcoder DP control */
4062 static enum port
4063 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4064 {
4065 struct drm_device *dev = crtc->dev;
4066 struct intel_encoder *encoder;
4067
4068 for_each_encoder_on_crtc(dev, crtc, encoder) {
4069 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4070 encoder->type == INTEL_OUTPUT_EDP)
4071 return enc_to_dig_port(&encoder->base)->port;
4072 }
4073
4074 return -1;
4075 }
4076
4077 /*
4078 * Enable PCH resources required for PCH ports:
4079 * - PCH PLLs
4080 * - FDI training & RX/TX
4081 * - update transcoder timings
4082 * - DP transcoding bits
4083 * - transcoder
4084 */
4085 static void ironlake_pch_enable(struct drm_crtc *crtc)
4086 {
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4090 int pipe = intel_crtc->pipe;
4091 u32 temp;
4092
4093 assert_pch_transcoder_disabled(dev_priv, pipe);
4094
4095 if (IS_IVYBRIDGE(dev))
4096 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4097
4098 /* Write the TU size bits before fdi link training, so that error
4099 * detection works. */
4100 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4101 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4102
4103 /* For PCH output, training FDI link */
4104 dev_priv->display.fdi_link_train(crtc);
4105
4106 /* We need to program the right clock selection before writing the pixel
4107 * mutliplier into the DPLL. */
4108 if (HAS_PCH_CPT(dev)) {
4109 u32 sel;
4110
4111 temp = I915_READ(PCH_DPLL_SEL);
4112 temp |= TRANS_DPLL_ENABLE(pipe);
4113 sel = TRANS_DPLLB_SEL(pipe);
4114 if (intel_crtc->config->shared_dpll ==
4115 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4116 temp |= sel;
4117 else
4118 temp &= ~sel;
4119 I915_WRITE(PCH_DPLL_SEL, temp);
4120 }
4121
4122 /* XXX: pch pll's can be enabled any time before we enable the PCH
4123 * transcoder, and we actually should do this to not upset any PCH
4124 * transcoder that already use the clock when we share it.
4125 *
4126 * Note that enable_shared_dpll tries to do the right thing, but
4127 * get_shared_dpll unconditionally resets the pll - we need that to have
4128 * the right LVDS enable sequence. */
4129 intel_enable_shared_dpll(intel_crtc);
4130
4131 /* set transcoder timing, panel must allow it */
4132 assert_panel_unlocked(dev_priv, pipe);
4133 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4134
4135 intel_fdi_normal_train(crtc);
4136
4137 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4139 const struct drm_display_mode *adjusted_mode =
4140 &intel_crtc->config->base.adjusted_mode;
4141 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4142 i915_reg_t reg = TRANS_DP_CTL(pipe);
4143 temp = I915_READ(reg);
4144 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4145 TRANS_DP_SYNC_MASK |
4146 TRANS_DP_BPC_MASK);
4147 temp |= TRANS_DP_OUTPUT_ENABLE;
4148 temp |= bpc << 9; /* same format but at 11:9 */
4149
4150 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4151 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4152 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4153 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4154
4155 switch (intel_trans_dp_port_sel(crtc)) {
4156 case PORT_B:
4157 temp |= TRANS_DP_PORT_SEL_B;
4158 break;
4159 case PORT_C:
4160 temp |= TRANS_DP_PORT_SEL_C;
4161 break;
4162 case PORT_D:
4163 temp |= TRANS_DP_PORT_SEL_D;
4164 break;
4165 default:
4166 BUG();
4167 }
4168
4169 I915_WRITE(reg, temp);
4170 }
4171
4172 ironlake_enable_pch_transcoder(dev_priv, pipe);
4173 }
4174
4175 static void lpt_pch_enable(struct drm_crtc *crtc)
4176 {
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4181
4182 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4183
4184 lpt_program_iclkip(crtc);
4185
4186 /* Set transcoder timing. */
4187 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4188
4189 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4190 }
4191
4192 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4193 {
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 i915_reg_t dslreg = PIPEDSL(pipe);
4196 u32 temp;
4197
4198 temp = I915_READ(dslreg);
4199 udelay(500);
4200 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4201 if (wait_for(I915_READ(dslreg) != temp, 5))
4202 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4203 }
4204 }
4205
4206 static int
4207 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4208 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4209 int src_w, int src_h, int dst_w, int dst_h)
4210 {
4211 struct intel_crtc_scaler_state *scaler_state =
4212 &crtc_state->scaler_state;
4213 struct intel_crtc *intel_crtc =
4214 to_intel_crtc(crtc_state->base.crtc);
4215 int need_scaling;
4216
4217 need_scaling = intel_rotation_90_or_270(rotation) ?
4218 (src_h != dst_w || src_w != dst_h):
4219 (src_w != dst_w || src_h != dst_h);
4220
4221 /*
4222 * if plane is being disabled or scaler is no more required or force detach
4223 * - free scaler binded to this plane/crtc
4224 * - in order to do this, update crtc->scaler_usage
4225 *
4226 * Here scaler state in crtc_state is set free so that
4227 * scaler can be assigned to other user. Actual register
4228 * update to free the scaler is done in plane/panel-fit programming.
4229 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4230 */
4231 if (force_detach || !need_scaling) {
4232 if (*scaler_id >= 0) {
4233 scaler_state->scaler_users &= ~(1 << scaler_user);
4234 scaler_state->scalers[*scaler_id].in_use = 0;
4235
4236 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4237 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4238 intel_crtc->pipe, scaler_user, *scaler_id,
4239 scaler_state->scaler_users);
4240 *scaler_id = -1;
4241 }
4242 return 0;
4243 }
4244
4245 /* range checks */
4246 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4247 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4248
4249 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4250 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4251 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4252 "size is out of scaler range\n",
4253 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4254 return -EINVAL;
4255 }
4256
4257 /* mark this plane as a scaler user in crtc_state */
4258 scaler_state->scaler_users |= (1 << scaler_user);
4259 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4260 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4261 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4262 scaler_state->scaler_users);
4263
4264 return 0;
4265 }
4266
4267 /**
4268 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4269 *
4270 * @state: crtc's scaler state
4271 *
4272 * Return
4273 * 0 - scaler_usage updated successfully
4274 * error - requested scaling cannot be supported or other error condition
4275 */
4276 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4277 {
4278 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4279 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4280
4281 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4282 intel_crtc->base.base.id, intel_crtc->base.name,
4283 intel_crtc->pipe, SKL_CRTC_INDEX);
4284
4285 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4286 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4287 state->pipe_src_w, state->pipe_src_h,
4288 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4289 }
4290
4291 /**
4292 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4293 *
4294 * @state: crtc's scaler state
4295 * @plane_state: atomic plane state to update
4296 *
4297 * Return
4298 * 0 - scaler_usage updated successfully
4299 * error - requested scaling cannot be supported or other error condition
4300 */
4301 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4302 struct intel_plane_state *plane_state)
4303 {
4304
4305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4306 struct intel_plane *intel_plane =
4307 to_intel_plane(plane_state->base.plane);
4308 struct drm_framebuffer *fb = plane_state->base.fb;
4309 int ret;
4310
4311 bool force_detach = !fb || !plane_state->visible;
4312
4313 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4314 intel_plane->base.base.id, intel_plane->base.name,
4315 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4316
4317 ret = skl_update_scaler(crtc_state, force_detach,
4318 drm_plane_index(&intel_plane->base),
4319 &plane_state->scaler_id,
4320 plane_state->base.rotation,
4321 drm_rect_width(&plane_state->src) >> 16,
4322 drm_rect_height(&plane_state->src) >> 16,
4323 drm_rect_width(&plane_state->dst),
4324 drm_rect_height(&plane_state->dst));
4325
4326 if (ret || plane_state->scaler_id < 0)
4327 return ret;
4328
4329 /* check colorkey */
4330 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4331 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4332 intel_plane->base.base.id,
4333 intel_plane->base.name);
4334 return -EINVAL;
4335 }
4336
4337 /* Check src format */
4338 switch (fb->pixel_format) {
4339 case DRM_FORMAT_RGB565:
4340 case DRM_FORMAT_XBGR8888:
4341 case DRM_FORMAT_XRGB8888:
4342 case DRM_FORMAT_ABGR8888:
4343 case DRM_FORMAT_ARGB8888:
4344 case DRM_FORMAT_XRGB2101010:
4345 case DRM_FORMAT_XBGR2101010:
4346 case DRM_FORMAT_YUYV:
4347 case DRM_FORMAT_YVYU:
4348 case DRM_FORMAT_UYVY:
4349 case DRM_FORMAT_VYUY:
4350 break;
4351 default:
4352 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4353 intel_plane->base.base.id, intel_plane->base.name,
4354 fb->base.id, fb->pixel_format);
4355 return -EINVAL;
4356 }
4357
4358 return 0;
4359 }
4360
4361 static void skylake_scaler_disable(struct intel_crtc *crtc)
4362 {
4363 int i;
4364
4365 for (i = 0; i < crtc->num_scalers; i++)
4366 skl_detach_scaler(crtc, i);
4367 }
4368
4369 static void skylake_pfit_enable(struct intel_crtc *crtc)
4370 {
4371 struct drm_device *dev = crtc->base.dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 int pipe = crtc->pipe;
4374 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc->config->scaler_state;
4376
4377 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4378
4379 if (crtc->config->pch_pfit.enabled) {
4380 int id;
4381
4382 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4383 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4384 return;
4385 }
4386
4387 id = scaler_state->scaler_id;
4388 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4389 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4390 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4391 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4392
4393 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4394 }
4395 }
4396
4397 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4398 {
4399 struct drm_device *dev = crtc->base.dev;
4400 struct drm_i915_private *dev_priv = dev->dev_private;
4401 int pipe = crtc->pipe;
4402
4403 if (crtc->config->pch_pfit.enabled) {
4404 /* Force use of hard-coded filter coefficients
4405 * as some pre-programmed values are broken,
4406 * e.g. x201.
4407 */
4408 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4409 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4410 PF_PIPE_SEL_IVB(pipe));
4411 else
4412 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4413 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4414 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4415 }
4416 }
4417
4418 void hsw_enable_ips(struct intel_crtc *crtc)
4419 {
4420 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422
4423 if (!crtc->config->ips_enabled)
4424 return;
4425
4426 /*
4427 * We can only enable IPS after we enable a plane and wait for a vblank
4428 * This function is called from post_plane_update, which is run after
4429 * a vblank wait.
4430 */
4431
4432 assert_plane_enabled(dev_priv, crtc->plane);
4433 if (IS_BROADWELL(dev)) {
4434 mutex_lock(&dev_priv->rps.hw_lock);
4435 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4436 mutex_unlock(&dev_priv->rps.hw_lock);
4437 /* Quoting Art Runyan: "its not safe to expect any particular
4438 * value in IPS_CTL bit 31 after enabling IPS through the
4439 * mailbox." Moreover, the mailbox may return a bogus state,
4440 * so we need to just enable it and continue on.
4441 */
4442 } else {
4443 I915_WRITE(IPS_CTL, IPS_ENABLE);
4444 /* The bit only becomes 1 in the next vblank, so this wait here
4445 * is essentially intel_wait_for_vblank. If we don't have this
4446 * and don't wait for vblanks until the end of crtc_enable, then
4447 * the HW state readout code will complain that the expected
4448 * IPS_CTL value is not the one we read. */
4449 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4450 DRM_ERROR("Timed out waiting for IPS enable\n");
4451 }
4452 }
4453
4454 void hsw_disable_ips(struct intel_crtc *crtc)
4455 {
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458
4459 if (!crtc->config->ips_enabled)
4460 return;
4461
4462 assert_plane_enabled(dev_priv, crtc->plane);
4463 if (IS_BROADWELL(dev)) {
4464 mutex_lock(&dev_priv->rps.hw_lock);
4465 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4466 mutex_unlock(&dev_priv->rps.hw_lock);
4467 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4468 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4469 DRM_ERROR("Timed out waiting for IPS disable\n");
4470 } else {
4471 I915_WRITE(IPS_CTL, 0);
4472 POSTING_READ(IPS_CTL);
4473 }
4474
4475 /* We need to wait for a vblank before we can disable the plane. */
4476 intel_wait_for_vblank(dev, crtc->pipe);
4477 }
4478
4479 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4480 {
4481 if (intel_crtc->overlay) {
4482 struct drm_device *dev = intel_crtc->base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484
4485 mutex_lock(&dev->struct_mutex);
4486 dev_priv->mm.interruptible = false;
4487 (void) intel_overlay_switch_off(intel_crtc->overlay);
4488 dev_priv->mm.interruptible = true;
4489 mutex_unlock(&dev->struct_mutex);
4490 }
4491
4492 /* Let userspace switch the overlay on again. In most cases userspace
4493 * has to recompute where to put it anyway.
4494 */
4495 }
4496
4497 /**
4498 * intel_post_enable_primary - Perform operations after enabling primary plane
4499 * @crtc: the CRTC whose primary plane was just enabled
4500 *
4501 * Performs potentially sleeping operations that must be done after the primary
4502 * plane is enabled, such as updating FBC and IPS. Note that this may be
4503 * called due to an explicit primary plane update, or due to an implicit
4504 * re-enable that is caused when a sprite plane is updated to no longer
4505 * completely hide the primary plane.
4506 */
4507 static void
4508 intel_post_enable_primary(struct drm_crtc *crtc)
4509 {
4510 struct drm_device *dev = crtc->dev;
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4513 int pipe = intel_crtc->pipe;
4514
4515 /*
4516 * FIXME IPS should be fine as long as one plane is
4517 * enabled, but in practice it seems to have problems
4518 * when going from primary only to sprite only and vice
4519 * versa.
4520 */
4521 hsw_enable_ips(intel_crtc);
4522
4523 /*
4524 * Gen2 reports pipe underruns whenever all planes are disabled.
4525 * So don't enable underrun reporting before at least some planes
4526 * are enabled.
4527 * FIXME: Need to fix the logic to work when we turn off all planes
4528 * but leave the pipe running.
4529 */
4530 if (IS_GEN2(dev))
4531 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4532
4533 /* Underruns don't always raise interrupts, so check manually. */
4534 intel_check_cpu_fifo_underruns(dev_priv);
4535 intel_check_pch_fifo_underruns(dev_priv);
4536 }
4537
4538 /* FIXME move all this to pre_plane_update() with proper state tracking */
4539 static void
4540 intel_pre_disable_primary(struct drm_crtc *crtc)
4541 {
4542 struct drm_device *dev = crtc->dev;
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545 int pipe = intel_crtc->pipe;
4546
4547 /*
4548 * Gen2 reports pipe underruns whenever all planes are disabled.
4549 * So diasble underrun reporting before all the planes get disabled.
4550 * FIXME: Need to fix the logic to work when we turn off all planes
4551 * but leave the pipe running.
4552 */
4553 if (IS_GEN2(dev))
4554 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556 /*
4557 * FIXME IPS should be fine as long as one plane is
4558 * enabled, but in practice it seems to have problems
4559 * when going from primary only to sprite only and vice
4560 * versa.
4561 */
4562 hsw_disable_ips(intel_crtc);
4563 }
4564
4565 /* FIXME get rid of this and use pre_plane_update */
4566 static void
4567 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4568 {
4569 struct drm_device *dev = crtc->dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572 int pipe = intel_crtc->pipe;
4573
4574 intel_pre_disable_primary(crtc);
4575
4576 /*
4577 * Vblank time updates from the shadow to live plane control register
4578 * are blocked if the memory self-refresh mode is active at that
4579 * moment. So to make sure the plane gets truly disabled, disable
4580 * first the self-refresh mode. The self-refresh enable bit in turn
4581 * will be checked/applied by the HW only at the next frame start
4582 * event which is after the vblank start event, so we need to have a
4583 * wait-for-vblank between disabling the plane and the pipe.
4584 */
4585 if (HAS_GMCH_DISPLAY(dev)) {
4586 intel_set_memory_cxsr(dev_priv, false);
4587 dev_priv->wm.vlv.cxsr = false;
4588 intel_wait_for_vblank(dev, pipe);
4589 }
4590 }
4591
4592 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4593 {
4594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4595 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4596 struct intel_crtc_state *pipe_config =
4597 to_intel_crtc_state(crtc->base.state);
4598 struct drm_device *dev = crtc->base.dev;
4599 struct drm_plane *primary = crtc->base.primary;
4600 struct drm_plane_state *old_pri_state =
4601 drm_atomic_get_existing_plane_state(old_state, primary);
4602
4603 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4604
4605 crtc->wm.cxsr_allowed = true;
4606
4607 if (pipe_config->update_wm_post && pipe_config->base.active)
4608 intel_update_watermarks(&crtc->base);
4609
4610 if (old_pri_state) {
4611 struct intel_plane_state *primary_state =
4612 to_intel_plane_state(primary->state);
4613 struct intel_plane_state *old_primary_state =
4614 to_intel_plane_state(old_pri_state);
4615
4616 intel_fbc_post_update(crtc);
4617
4618 if (primary_state->visible &&
4619 (needs_modeset(&pipe_config->base) ||
4620 !old_primary_state->visible))
4621 intel_post_enable_primary(&crtc->base);
4622 }
4623 }
4624
4625 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4626 {
4627 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4628 struct drm_device *dev = crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_crtc_state *pipe_config =
4631 to_intel_crtc_state(crtc->base.state);
4632 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4633 struct drm_plane *primary = crtc->base.primary;
4634 struct drm_plane_state *old_pri_state =
4635 drm_atomic_get_existing_plane_state(old_state, primary);
4636 bool modeset = needs_modeset(&pipe_config->base);
4637
4638 if (old_pri_state) {
4639 struct intel_plane_state *primary_state =
4640 to_intel_plane_state(primary->state);
4641 struct intel_plane_state *old_primary_state =
4642 to_intel_plane_state(old_pri_state);
4643
4644 intel_fbc_pre_update(crtc);
4645
4646 if (old_primary_state->visible &&
4647 (modeset || !primary_state->visible))
4648 intel_pre_disable_primary(&crtc->base);
4649 }
4650
4651 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4652 crtc->wm.cxsr_allowed = false;
4653
4654 /*
4655 * Vblank time updates from the shadow to live plane control register
4656 * are blocked if the memory self-refresh mode is active at that
4657 * moment. So to make sure the plane gets truly disabled, disable
4658 * first the self-refresh mode. The self-refresh enable bit in turn
4659 * will be checked/applied by the HW only at the next frame start
4660 * event which is after the vblank start event, so we need to have a
4661 * wait-for-vblank between disabling the plane and the pipe.
4662 */
4663 if (old_crtc_state->base.active) {
4664 intel_set_memory_cxsr(dev_priv, false);
4665 dev_priv->wm.vlv.cxsr = false;
4666 intel_wait_for_vblank(dev, crtc->pipe);
4667 }
4668 }
4669
4670 /*
4671 * IVB workaround: must disable low power watermarks for at least
4672 * one frame before enabling scaling. LP watermarks can be re-enabled
4673 * when scaling is disabled.
4674 *
4675 * WaCxSRDisabledForSpriteScaling:ivb
4676 */
4677 if (pipe_config->disable_lp_wm) {
4678 ilk_disable_lp_wm(dev);
4679 intel_wait_for_vblank(dev, crtc->pipe);
4680 }
4681
4682 /*
4683 * If we're doing a modeset, we're done. No need to do any pre-vblank
4684 * watermark programming here.
4685 */
4686 if (needs_modeset(&pipe_config->base))
4687 return;
4688
4689 /*
4690 * For platforms that support atomic watermarks, program the
4691 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4692 * will be the intermediate values that are safe for both pre- and
4693 * post- vblank; when vblank happens, the 'active' values will be set
4694 * to the final 'target' values and we'll do this again to get the
4695 * optimal watermarks. For gen9+ platforms, the values we program here
4696 * will be the final target values which will get automatically latched
4697 * at vblank time; no further programming will be necessary.
4698 *
4699 * If a platform hasn't been transitioned to atomic watermarks yet,
4700 * we'll continue to update watermarks the old way, if flags tell
4701 * us to.
4702 */
4703 if (dev_priv->display.initial_watermarks != NULL)
4704 dev_priv->display.initial_watermarks(pipe_config);
4705 else if (pipe_config->update_wm_pre)
4706 intel_update_watermarks(&crtc->base);
4707 }
4708
4709 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4710 {
4711 struct drm_device *dev = crtc->dev;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct drm_plane *p;
4714 int pipe = intel_crtc->pipe;
4715
4716 intel_crtc_dpms_overlay_disable(intel_crtc);
4717
4718 drm_for_each_plane_mask(p, dev, plane_mask)
4719 to_intel_plane(p)->disable_plane(p, crtc);
4720
4721 /*
4722 * FIXME: Once we grow proper nuclear flip support out of this we need
4723 * to compute the mask of flip planes precisely. For the time being
4724 * consider this a flip to a NULL plane.
4725 */
4726 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4727 }
4728
4729 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4730 {
4731 struct drm_device *dev = crtc->dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 struct intel_encoder *encoder;
4735 int pipe = intel_crtc->pipe;
4736 struct intel_crtc_state *pipe_config =
4737 to_intel_crtc_state(crtc->state);
4738
4739 if (WARN_ON(intel_crtc->active))
4740 return;
4741
4742 /*
4743 * Sometimes spurious CPU pipe underruns happen during FDI
4744 * training, at least with VGA+HDMI cloning. Suppress them.
4745 *
4746 * On ILK we get an occasional spurious CPU pipe underruns
4747 * between eDP port A enable and vdd enable. Also PCH port
4748 * enable seems to result in the occasional CPU pipe underrun.
4749 *
4750 * Spurious PCH underruns also occur during PCH enabling.
4751 */
4752 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4753 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4754 if (intel_crtc->config->has_pch_encoder)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757 if (intel_crtc->config->has_pch_encoder)
4758 intel_prepare_shared_dpll(intel_crtc);
4759
4760 if (intel_crtc->config->has_dp_encoder)
4761 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763 intel_set_pipe_timings(intel_crtc);
4764 intel_set_pipe_src_size(intel_crtc);
4765
4766 if (intel_crtc->config->has_pch_encoder) {
4767 intel_cpu_transcoder_set_m_n(intel_crtc,
4768 &intel_crtc->config->fdi_m_n, NULL);
4769 }
4770
4771 ironlake_set_pipeconf(crtc);
4772
4773 intel_crtc->active = true;
4774
4775 for_each_encoder_on_crtc(dev, crtc, encoder)
4776 if (encoder->pre_enable)
4777 encoder->pre_enable(encoder);
4778
4779 if (intel_crtc->config->has_pch_encoder) {
4780 /* Note: FDI PLL enabling _must_ be done before we enable the
4781 * cpu pipes, hence this is separate from all the other fdi/pch
4782 * enabling. */
4783 ironlake_fdi_pll_enable(intel_crtc);
4784 } else {
4785 assert_fdi_tx_disabled(dev_priv, pipe);
4786 assert_fdi_rx_disabled(dev_priv, pipe);
4787 }
4788
4789 ironlake_pfit_enable(intel_crtc);
4790
4791 /*
4792 * On ILK+ LUT must be loaded before the pipe is running but with
4793 * clocks enabled
4794 */
4795 intel_color_load_luts(&pipe_config->base);
4796
4797 if (dev_priv->display.initial_watermarks != NULL)
4798 dev_priv->display.initial_watermarks(intel_crtc->config);
4799 intel_enable_pipe(intel_crtc);
4800
4801 if (intel_crtc->config->has_pch_encoder)
4802 ironlake_pch_enable(crtc);
4803
4804 assert_vblank_disabled(crtc);
4805 drm_crtc_vblank_on(crtc);
4806
4807 for_each_encoder_on_crtc(dev, crtc, encoder)
4808 encoder->enable(encoder);
4809
4810 if (HAS_PCH_CPT(dev))
4811 cpt_verify_modeset(dev, intel_crtc->pipe);
4812
4813 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4814 if (intel_crtc->config->has_pch_encoder)
4815 intel_wait_for_vblank(dev, pipe);
4816 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4817 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4818 }
4819
4820 /* IPS only exists on ULT machines and is tied to pipe A. */
4821 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4822 {
4823 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4824 }
4825
4826 static void haswell_crtc_enable(struct drm_crtc *crtc)
4827 {
4828 struct drm_device *dev = crtc->dev;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 struct intel_encoder *encoder;
4832 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4833 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4834 struct intel_crtc_state *pipe_config =
4835 to_intel_crtc_state(crtc->state);
4836
4837 if (WARN_ON(intel_crtc->active))
4838 return;
4839
4840 if (intel_crtc->config->has_pch_encoder)
4841 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4842 false);
4843
4844 for_each_encoder_on_crtc(dev, crtc, encoder)
4845 if (encoder->pre_pll_enable)
4846 encoder->pre_pll_enable(encoder);
4847
4848 if (intel_crtc->config->shared_dpll)
4849 intel_enable_shared_dpll(intel_crtc);
4850
4851 if (intel_crtc->config->has_dp_encoder)
4852 intel_dp_set_m_n(intel_crtc, M1_N1);
4853
4854 if (!intel_crtc->config->has_dsi_encoder)
4855 intel_set_pipe_timings(intel_crtc);
4856
4857 intel_set_pipe_src_size(intel_crtc);
4858
4859 if (cpu_transcoder != TRANSCODER_EDP &&
4860 !transcoder_is_dsi(cpu_transcoder)) {
4861 I915_WRITE(PIPE_MULT(cpu_transcoder),
4862 intel_crtc->config->pixel_multiplier - 1);
4863 }
4864
4865 if (intel_crtc->config->has_pch_encoder) {
4866 intel_cpu_transcoder_set_m_n(intel_crtc,
4867 &intel_crtc->config->fdi_m_n, NULL);
4868 }
4869
4870 if (!intel_crtc->config->has_dsi_encoder)
4871 haswell_set_pipeconf(crtc);
4872
4873 haswell_set_pipemisc(crtc);
4874
4875 intel_color_set_csc(&pipe_config->base);
4876
4877 intel_crtc->active = true;
4878
4879 if (intel_crtc->config->has_pch_encoder)
4880 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4881 else
4882 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4883
4884 for_each_encoder_on_crtc(dev, crtc, encoder) {
4885 if (encoder->pre_enable)
4886 encoder->pre_enable(encoder);
4887 }
4888
4889 if (intel_crtc->config->has_pch_encoder)
4890 dev_priv->display.fdi_link_train(crtc);
4891
4892 if (!intel_crtc->config->has_dsi_encoder)
4893 intel_ddi_enable_pipe_clock(intel_crtc);
4894
4895 if (INTEL_INFO(dev)->gen >= 9)
4896 skylake_pfit_enable(intel_crtc);
4897 else
4898 ironlake_pfit_enable(intel_crtc);
4899
4900 /*
4901 * On ILK+ LUT must be loaded before the pipe is running but with
4902 * clocks enabled
4903 */
4904 intel_color_load_luts(&pipe_config->base);
4905
4906 intel_ddi_set_pipe_settings(crtc);
4907 if (!intel_crtc->config->has_dsi_encoder)
4908 intel_ddi_enable_transcoder_func(crtc);
4909
4910 if (dev_priv->display.initial_watermarks != NULL)
4911 dev_priv->display.initial_watermarks(pipe_config);
4912 else
4913 intel_update_watermarks(crtc);
4914
4915 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4916 if (!intel_crtc->config->has_dsi_encoder)
4917 intel_enable_pipe(intel_crtc);
4918
4919 if (intel_crtc->config->has_pch_encoder)
4920 lpt_pch_enable(crtc);
4921
4922 if (intel_crtc->config->dp_encoder_is_mst)
4923 intel_ddi_set_vc_payload_alloc(crtc, true);
4924
4925 assert_vblank_disabled(crtc);
4926 drm_crtc_vblank_on(crtc);
4927
4928 for_each_encoder_on_crtc(dev, crtc, encoder) {
4929 encoder->enable(encoder);
4930 intel_opregion_notify_encoder(encoder, true);
4931 }
4932
4933 if (intel_crtc->config->has_pch_encoder) {
4934 intel_wait_for_vblank(dev, pipe);
4935 intel_wait_for_vblank(dev, pipe);
4936 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4937 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4938 true);
4939 }
4940
4941 /* If we change the relative order between pipe/planes enabling, we need
4942 * to change the workaround. */
4943 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4944 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4945 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4946 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4947 }
4948 }
4949
4950 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4951 {
4952 struct drm_device *dev = crtc->base.dev;
4953 struct drm_i915_private *dev_priv = dev->dev_private;
4954 int pipe = crtc->pipe;
4955
4956 /* To avoid upsetting the power well on haswell only disable the pfit if
4957 * it's in use. The hw state code will make sure we get this right. */
4958 if (force || crtc->config->pch_pfit.enabled) {
4959 I915_WRITE(PF_CTL(pipe), 0);
4960 I915_WRITE(PF_WIN_POS(pipe), 0);
4961 I915_WRITE(PF_WIN_SZ(pipe), 0);
4962 }
4963 }
4964
4965 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4966 {
4967 struct drm_device *dev = crtc->dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970 struct intel_encoder *encoder;
4971 int pipe = intel_crtc->pipe;
4972
4973 /*
4974 * Sometimes spurious CPU pipe underruns happen when the
4975 * pipe is already disabled, but FDI RX/TX is still enabled.
4976 * Happens at least with VGA+HDMI cloning. Suppress them.
4977 */
4978 if (intel_crtc->config->has_pch_encoder) {
4979 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4980 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4981 }
4982
4983 for_each_encoder_on_crtc(dev, crtc, encoder)
4984 encoder->disable(encoder);
4985
4986 drm_crtc_vblank_off(crtc);
4987 assert_vblank_disabled(crtc);
4988
4989 intel_disable_pipe(intel_crtc);
4990
4991 ironlake_pfit_disable(intel_crtc, false);
4992
4993 if (intel_crtc->config->has_pch_encoder)
4994 ironlake_fdi_disable(crtc);
4995
4996 for_each_encoder_on_crtc(dev, crtc, encoder)
4997 if (encoder->post_disable)
4998 encoder->post_disable(encoder);
4999
5000 if (intel_crtc->config->has_pch_encoder) {
5001 ironlake_disable_pch_transcoder(dev_priv, pipe);
5002
5003 if (HAS_PCH_CPT(dev)) {
5004 i915_reg_t reg;
5005 u32 temp;
5006
5007 /* disable TRANS_DP_CTL */
5008 reg = TRANS_DP_CTL(pipe);
5009 temp = I915_READ(reg);
5010 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5011 TRANS_DP_PORT_SEL_MASK);
5012 temp |= TRANS_DP_PORT_SEL_NONE;
5013 I915_WRITE(reg, temp);
5014
5015 /* disable DPLL_SEL */
5016 temp = I915_READ(PCH_DPLL_SEL);
5017 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5018 I915_WRITE(PCH_DPLL_SEL, temp);
5019 }
5020
5021 ironlake_fdi_pll_disable(intel_crtc);
5022 }
5023
5024 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5025 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5026 }
5027
5028 static void haswell_crtc_disable(struct drm_crtc *crtc)
5029 {
5030 struct drm_device *dev = crtc->dev;
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5033 struct intel_encoder *encoder;
5034 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5035
5036 if (intel_crtc->config->has_pch_encoder)
5037 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5038 false);
5039
5040 for_each_encoder_on_crtc(dev, crtc, encoder) {
5041 intel_opregion_notify_encoder(encoder, false);
5042 encoder->disable(encoder);
5043 }
5044
5045 drm_crtc_vblank_off(crtc);
5046 assert_vblank_disabled(crtc);
5047
5048 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5049 if (!intel_crtc->config->has_dsi_encoder)
5050 intel_disable_pipe(intel_crtc);
5051
5052 if (intel_crtc->config->dp_encoder_is_mst)
5053 intel_ddi_set_vc_payload_alloc(crtc, false);
5054
5055 if (!intel_crtc->config->has_dsi_encoder)
5056 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5057
5058 if (INTEL_INFO(dev)->gen >= 9)
5059 skylake_scaler_disable(intel_crtc);
5060 else
5061 ironlake_pfit_disable(intel_crtc, false);
5062
5063 if (!intel_crtc->config->has_dsi_encoder)
5064 intel_ddi_disable_pipe_clock(intel_crtc);
5065
5066 for_each_encoder_on_crtc(dev, crtc, encoder)
5067 if (encoder->post_disable)
5068 encoder->post_disable(encoder);
5069
5070 if (intel_crtc->config->has_pch_encoder) {
5071 lpt_disable_pch_transcoder(dev_priv);
5072 lpt_disable_iclkip(dev_priv);
5073 intel_ddi_fdi_disable(crtc);
5074
5075 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5076 true);
5077 }
5078 }
5079
5080 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5081 {
5082 struct drm_device *dev = crtc->base.dev;
5083 struct drm_i915_private *dev_priv = dev->dev_private;
5084 struct intel_crtc_state *pipe_config = crtc->config;
5085
5086 if (!pipe_config->gmch_pfit.control)
5087 return;
5088
5089 /*
5090 * The panel fitter should only be adjusted whilst the pipe is disabled,
5091 * according to register description and PRM.
5092 */
5093 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5094 assert_pipe_disabled(dev_priv, crtc->pipe);
5095
5096 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5097 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5098
5099 /* Border color in case we don't scale up to the full screen. Black by
5100 * default, change to something else for debugging. */
5101 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5102 }
5103
5104 static enum intel_display_power_domain port_to_power_domain(enum port port)
5105 {
5106 switch (port) {
5107 case PORT_A:
5108 return POWER_DOMAIN_PORT_DDI_A_LANES;
5109 case PORT_B:
5110 return POWER_DOMAIN_PORT_DDI_B_LANES;
5111 case PORT_C:
5112 return POWER_DOMAIN_PORT_DDI_C_LANES;
5113 case PORT_D:
5114 return POWER_DOMAIN_PORT_DDI_D_LANES;
5115 case PORT_E:
5116 return POWER_DOMAIN_PORT_DDI_E_LANES;
5117 default:
5118 MISSING_CASE(port);
5119 return POWER_DOMAIN_PORT_OTHER;
5120 }
5121 }
5122
5123 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5124 {
5125 switch (port) {
5126 case PORT_A:
5127 return POWER_DOMAIN_AUX_A;
5128 case PORT_B:
5129 return POWER_DOMAIN_AUX_B;
5130 case PORT_C:
5131 return POWER_DOMAIN_AUX_C;
5132 case PORT_D:
5133 return POWER_DOMAIN_AUX_D;
5134 case PORT_E:
5135 /* FIXME: Check VBT for actual wiring of PORT E */
5136 return POWER_DOMAIN_AUX_D;
5137 default:
5138 MISSING_CASE(port);
5139 return POWER_DOMAIN_AUX_A;
5140 }
5141 }
5142
5143 enum intel_display_power_domain
5144 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5145 {
5146 struct drm_device *dev = intel_encoder->base.dev;
5147 struct intel_digital_port *intel_dig_port;
5148
5149 switch (intel_encoder->type) {
5150 case INTEL_OUTPUT_UNKNOWN:
5151 /* Only DDI platforms should ever use this output type */
5152 WARN_ON_ONCE(!HAS_DDI(dev));
5153 case INTEL_OUTPUT_DISPLAYPORT:
5154 case INTEL_OUTPUT_HDMI:
5155 case INTEL_OUTPUT_EDP:
5156 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5157 return port_to_power_domain(intel_dig_port->port);
5158 case INTEL_OUTPUT_DP_MST:
5159 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5160 return port_to_power_domain(intel_dig_port->port);
5161 case INTEL_OUTPUT_ANALOG:
5162 return POWER_DOMAIN_PORT_CRT;
5163 case INTEL_OUTPUT_DSI:
5164 return POWER_DOMAIN_PORT_DSI;
5165 default:
5166 return POWER_DOMAIN_PORT_OTHER;
5167 }
5168 }
5169
5170 enum intel_display_power_domain
5171 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5172 {
5173 struct drm_device *dev = intel_encoder->base.dev;
5174 struct intel_digital_port *intel_dig_port;
5175
5176 switch (intel_encoder->type) {
5177 case INTEL_OUTPUT_UNKNOWN:
5178 case INTEL_OUTPUT_HDMI:
5179 /*
5180 * Only DDI platforms should ever use these output types.
5181 * We can get here after the HDMI detect code has already set
5182 * the type of the shared encoder. Since we can't be sure
5183 * what's the status of the given connectors, play safe and
5184 * run the DP detection too.
5185 */
5186 WARN_ON_ONCE(!HAS_DDI(dev));
5187 case INTEL_OUTPUT_DISPLAYPORT:
5188 case INTEL_OUTPUT_EDP:
5189 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5190 return port_to_aux_power_domain(intel_dig_port->port);
5191 case INTEL_OUTPUT_DP_MST:
5192 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5193 return port_to_aux_power_domain(intel_dig_port->port);
5194 default:
5195 MISSING_CASE(intel_encoder->type);
5196 return POWER_DOMAIN_AUX_A;
5197 }
5198 }
5199
5200 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5201 struct intel_crtc_state *crtc_state)
5202 {
5203 struct drm_device *dev = crtc->dev;
5204 struct drm_encoder *encoder;
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206 enum pipe pipe = intel_crtc->pipe;
5207 unsigned long mask;
5208 enum transcoder transcoder = crtc_state->cpu_transcoder;
5209
5210 if (!crtc_state->base.active)
5211 return 0;
5212
5213 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5214 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5215 if (crtc_state->pch_pfit.enabled ||
5216 crtc_state->pch_pfit.force_thru)
5217 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5218
5219 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5220 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5221
5222 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5223 }
5224
5225 if (crtc_state->shared_dpll)
5226 mask |= BIT(POWER_DOMAIN_PLLS);
5227
5228 return mask;
5229 }
5230
5231 static unsigned long
5232 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5233 struct intel_crtc_state *crtc_state)
5234 {
5235 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 enum intel_display_power_domain domain;
5238 unsigned long domains, new_domains, old_domains;
5239
5240 old_domains = intel_crtc->enabled_power_domains;
5241 intel_crtc->enabled_power_domains = new_domains =
5242 get_crtc_power_domains(crtc, crtc_state);
5243
5244 domains = new_domains & ~old_domains;
5245
5246 for_each_power_domain(domain, domains)
5247 intel_display_power_get(dev_priv, domain);
5248
5249 return old_domains & ~new_domains;
5250 }
5251
5252 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5253 unsigned long domains)
5254 {
5255 enum intel_display_power_domain domain;
5256
5257 for_each_power_domain(domain, domains)
5258 intel_display_power_put(dev_priv, domain);
5259 }
5260
5261 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5262 {
5263 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5264
5265 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5266 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5267 return max_cdclk_freq;
5268 else if (IS_CHERRYVIEW(dev_priv))
5269 return max_cdclk_freq*95/100;
5270 else if (INTEL_INFO(dev_priv)->gen < 4)
5271 return 2*max_cdclk_freq*90/100;
5272 else
5273 return max_cdclk_freq*90/100;
5274 }
5275
5276 static int skl_calc_cdclk(int max_pixclk, int vco);
5277
5278 static void intel_update_max_cdclk(struct drm_device *dev)
5279 {
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281
5282 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5283 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5284 int max_cdclk, vco;
5285
5286 vco = dev_priv->skl_preferred_vco_freq;
5287 WARN_ON(vco != 8100000 && vco != 8640000);
5288
5289 /*
5290 * Use the lower (vco 8640) cdclk values as a
5291 * first guess. skl_calc_cdclk() will correct it
5292 * if the preferred vco is 8100 instead.
5293 */
5294 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5295 max_cdclk = 617143;
5296 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5297 max_cdclk = 540000;
5298 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5299 max_cdclk = 432000;
5300 else
5301 max_cdclk = 308571;
5302
5303 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5304 } else if (IS_BROXTON(dev)) {
5305 dev_priv->max_cdclk_freq = 624000;
5306 } else if (IS_BROADWELL(dev)) {
5307 /*
5308 * FIXME with extra cooling we can allow
5309 * 540 MHz for ULX and 675 Mhz for ULT.
5310 * How can we know if extra cooling is
5311 * available? PCI ID, VTB, something else?
5312 */
5313 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5314 dev_priv->max_cdclk_freq = 450000;
5315 else if (IS_BDW_ULX(dev))
5316 dev_priv->max_cdclk_freq = 450000;
5317 else if (IS_BDW_ULT(dev))
5318 dev_priv->max_cdclk_freq = 540000;
5319 else
5320 dev_priv->max_cdclk_freq = 675000;
5321 } else if (IS_CHERRYVIEW(dev)) {
5322 dev_priv->max_cdclk_freq = 320000;
5323 } else if (IS_VALLEYVIEW(dev)) {
5324 dev_priv->max_cdclk_freq = 400000;
5325 } else {
5326 /* otherwise assume cdclk is fixed */
5327 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5328 }
5329
5330 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5331
5332 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5333 dev_priv->max_cdclk_freq);
5334
5335 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5336 dev_priv->max_dotclk_freq);
5337 }
5338
5339 static void intel_update_cdclk(struct drm_device *dev)
5340 {
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5344
5345 if (INTEL_GEN(dev_priv) >= 9)
5346 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5347 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5348 dev_priv->cdclk_pll.ref);
5349 else
5350 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5351 dev_priv->cdclk_freq);
5352
5353 /*
5354 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5355 * Programmng [sic] note: bit[9:2] should be programmed to the number
5356 * of cdclk that generates 4MHz reference clock freq which is used to
5357 * generate GMBus clock. This will vary with the cdclk freq.
5358 */
5359 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5360 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5361 }
5362
5363 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5364 static int skl_cdclk_decimal(int cdclk)
5365 {
5366 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5367 }
5368
5369 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5370 {
5371 int ratio;
5372
5373 if (cdclk == dev_priv->cdclk_pll.ref)
5374 return 0;
5375
5376 switch (cdclk) {
5377 default:
5378 MISSING_CASE(cdclk);
5379 case 144000:
5380 case 288000:
5381 case 384000:
5382 case 576000:
5383 ratio = 60;
5384 break;
5385 case 624000:
5386 ratio = 65;
5387 break;
5388 }
5389
5390 return dev_priv->cdclk_pll.ref * ratio;
5391 }
5392
5393 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5394 {
5395 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5396
5397 /* Timeout 200us */
5398 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5399 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5400
5401 dev_priv->cdclk_pll.vco = 0;
5402 }
5403
5404 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5405 {
5406 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5407 u32 val;
5408
5409 val = I915_READ(BXT_DE_PLL_CTL);
5410 val &= ~BXT_DE_PLL_RATIO_MASK;
5411 val |= BXT_DE_PLL_RATIO(ratio);
5412 I915_WRITE(BXT_DE_PLL_CTL, val);
5413
5414 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5415
5416 /* Timeout 200us */
5417 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5418 DRM_ERROR("timeout waiting for DE PLL lock\n");
5419
5420 dev_priv->cdclk_pll.vco = vco;
5421 }
5422
5423 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5424 {
5425 u32 val, divider;
5426 int vco, ret;
5427
5428 vco = bxt_de_pll_vco(dev_priv, cdclk);
5429
5430 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5431
5432 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5433 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5434 case 8:
5435 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5436 break;
5437 case 4:
5438 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5439 break;
5440 case 3:
5441 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5442 break;
5443 case 2:
5444 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5445 break;
5446 default:
5447 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5448 WARN_ON(vco != 0);
5449
5450 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5451 break;
5452 }
5453
5454 /* Inform power controller of upcoming frequency change */
5455 mutex_lock(&dev_priv->rps.hw_lock);
5456 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5457 0x80000000);
5458 mutex_unlock(&dev_priv->rps.hw_lock);
5459
5460 if (ret) {
5461 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5462 ret, cdclk);
5463 return;
5464 }
5465
5466 if (dev_priv->cdclk_pll.vco != 0 &&
5467 dev_priv->cdclk_pll.vco != vco)
5468 bxt_de_pll_disable(dev_priv);
5469
5470 if (dev_priv->cdclk_pll.vco != vco)
5471 bxt_de_pll_enable(dev_priv, vco);
5472
5473 val = divider | skl_cdclk_decimal(cdclk);
5474 /*
5475 * FIXME if only the cd2x divider needs changing, it could be done
5476 * without shutting off the pipe (if only one pipe is active).
5477 */
5478 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5479 /*
5480 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5481 * enable otherwise.
5482 */
5483 if (cdclk >= 500000)
5484 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5485 I915_WRITE(CDCLK_CTL, val);
5486
5487 mutex_lock(&dev_priv->rps.hw_lock);
5488 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5489 DIV_ROUND_UP(cdclk, 25000));
5490 mutex_unlock(&dev_priv->rps.hw_lock);
5491
5492 if (ret) {
5493 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5494 ret, cdclk);
5495 return;
5496 }
5497
5498 intel_update_cdclk(dev_priv->dev);
5499 }
5500
5501 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5502 {
5503 u32 cdctl, expected;
5504
5505 intel_update_cdclk(dev_priv->dev);
5506
5507 if (dev_priv->cdclk_pll.vco == 0 ||
5508 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5509 goto sanitize;
5510
5511 /* DPLL okay; verify the cdclock
5512 *
5513 * Some BIOS versions leave an incorrect decimal frequency value and
5514 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5515 * so sanitize this register.
5516 */
5517 cdctl = I915_READ(CDCLK_CTL);
5518 /*
5519 * Let's ignore the pipe field, since BIOS could have configured the
5520 * dividers both synching to an active pipe, or asynchronously
5521 * (PIPE_NONE).
5522 */
5523 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5524
5525 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5526 skl_cdclk_decimal(dev_priv->cdclk_freq);
5527 /*
5528 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5529 * enable otherwise.
5530 */
5531 if (dev_priv->cdclk_freq >= 500000)
5532 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5533
5534 if (cdctl == expected)
5535 /* All well; nothing to sanitize */
5536 return;
5537
5538 sanitize:
5539 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5540
5541 /* force cdclk programming */
5542 dev_priv->cdclk_freq = 0;
5543
5544 /* force full PLL disable + enable */
5545 dev_priv->cdclk_pll.vco = -1;
5546 }
5547
5548 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5549 {
5550 bxt_sanitize_cdclk(dev_priv);
5551
5552 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5553 return;
5554
5555 /*
5556 * FIXME:
5557 * - The initial CDCLK needs to be read from VBT.
5558 * Need to make this change after VBT has changes for BXT.
5559 */
5560 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5561 }
5562
5563 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5564 {
5565 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5566 }
5567
5568 static int skl_calc_cdclk(int max_pixclk, int vco)
5569 {
5570 if (vco == 8640000) {
5571 if (max_pixclk > 540000)
5572 return 617143;
5573 else if (max_pixclk > 432000)
5574 return 540000;
5575 else if (max_pixclk > 308571)
5576 return 432000;
5577 else
5578 return 308571;
5579 } else {
5580 if (max_pixclk > 540000)
5581 return 675000;
5582 else if (max_pixclk > 450000)
5583 return 540000;
5584 else if (max_pixclk > 337500)
5585 return 450000;
5586 else
5587 return 337500;
5588 }
5589 }
5590
5591 static void
5592 skl_dpll0_update(struct drm_i915_private *dev_priv)
5593 {
5594 u32 val;
5595
5596 dev_priv->cdclk_pll.ref = 24000;
5597 dev_priv->cdclk_pll.vco = 0;
5598
5599 val = I915_READ(LCPLL1_CTL);
5600 if ((val & LCPLL_PLL_ENABLE) == 0)
5601 return;
5602
5603 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5604 return;
5605
5606 val = I915_READ(DPLL_CTRL1);
5607
5608 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5609 DPLL_CTRL1_SSC(SKL_DPLL0) |
5610 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5611 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5612 return;
5613
5614 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5615 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5616 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5617 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5618 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5619 dev_priv->cdclk_pll.vco = 8100000;
5620 break;
5621 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5622 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5623 dev_priv->cdclk_pll.vco = 8640000;
5624 break;
5625 default:
5626 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5627 break;
5628 }
5629 }
5630
5631 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5632 {
5633 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5634
5635 dev_priv->skl_preferred_vco_freq = vco;
5636
5637 if (changed)
5638 intel_update_max_cdclk(dev_priv->dev);
5639 }
5640
5641 static void
5642 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5643 {
5644 int min_cdclk = skl_calc_cdclk(0, vco);
5645 u32 val;
5646
5647 WARN_ON(vco != 8100000 && vco != 8640000);
5648
5649 /* select the minimum CDCLK before enabling DPLL 0 */
5650 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5651 I915_WRITE(CDCLK_CTL, val);
5652 POSTING_READ(CDCLK_CTL);
5653
5654 /*
5655 * We always enable DPLL0 with the lowest link rate possible, but still
5656 * taking into account the VCO required to operate the eDP panel at the
5657 * desired frequency. The usual DP link rates operate with a VCO of
5658 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5659 * The modeset code is responsible for the selection of the exact link
5660 * rate later on, with the constraint of choosing a frequency that
5661 * works with vco.
5662 */
5663 val = I915_READ(DPLL_CTRL1);
5664
5665 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5666 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5667 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5668 if (vco == 8640000)
5669 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5670 SKL_DPLL0);
5671 else
5672 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5673 SKL_DPLL0);
5674
5675 I915_WRITE(DPLL_CTRL1, val);
5676 POSTING_READ(DPLL_CTRL1);
5677
5678 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5679
5680 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5681 DRM_ERROR("DPLL0 not locked\n");
5682
5683 dev_priv->cdclk_pll.vco = vco;
5684
5685 /* We'll want to keep using the current vco from now on. */
5686 skl_set_preferred_cdclk_vco(dev_priv, vco);
5687 }
5688
5689 static void
5690 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5691 {
5692 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5693 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5694 DRM_ERROR("Couldn't disable DPLL0\n");
5695
5696 dev_priv->cdclk_pll.vco = 0;
5697 }
5698
5699 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5700 {
5701 int ret;
5702 u32 val;
5703
5704 /* inform PCU we want to change CDCLK */
5705 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5706 mutex_lock(&dev_priv->rps.hw_lock);
5707 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5708 mutex_unlock(&dev_priv->rps.hw_lock);
5709
5710 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5711 }
5712
5713 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5714 {
5715 unsigned int i;
5716
5717 for (i = 0; i < 15; i++) {
5718 if (skl_cdclk_pcu_ready(dev_priv))
5719 return true;
5720 udelay(10);
5721 }
5722
5723 return false;
5724 }
5725
5726 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5727 {
5728 struct drm_device *dev = dev_priv->dev;
5729 u32 freq_select, pcu_ack;
5730
5731 WARN_ON((cdclk == 24000) != (vco == 0));
5732
5733 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5734
5735 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5736 DRM_ERROR("failed to inform PCU about cdclk change\n");
5737 return;
5738 }
5739
5740 /* set CDCLK_CTL */
5741 switch (cdclk) {
5742 case 450000:
5743 case 432000:
5744 freq_select = CDCLK_FREQ_450_432;
5745 pcu_ack = 1;
5746 break;
5747 case 540000:
5748 freq_select = CDCLK_FREQ_540;
5749 pcu_ack = 2;
5750 break;
5751 case 308571:
5752 case 337500:
5753 default:
5754 freq_select = CDCLK_FREQ_337_308;
5755 pcu_ack = 0;
5756 break;
5757 case 617143:
5758 case 675000:
5759 freq_select = CDCLK_FREQ_675_617;
5760 pcu_ack = 3;
5761 break;
5762 }
5763
5764 if (dev_priv->cdclk_pll.vco != 0 &&
5765 dev_priv->cdclk_pll.vco != vco)
5766 skl_dpll0_disable(dev_priv);
5767
5768 if (dev_priv->cdclk_pll.vco != vco)
5769 skl_dpll0_enable(dev_priv, vco);
5770
5771 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5772 POSTING_READ(CDCLK_CTL);
5773
5774 /* inform PCU of the change */
5775 mutex_lock(&dev_priv->rps.hw_lock);
5776 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5777 mutex_unlock(&dev_priv->rps.hw_lock);
5778
5779 intel_update_cdclk(dev);
5780 }
5781
5782 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5783
5784 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5785 {
5786 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5787 }
5788
5789 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5790 {
5791 int cdclk, vco;
5792
5793 skl_sanitize_cdclk(dev_priv);
5794
5795 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5796 /*
5797 * Use the current vco as our initial
5798 * guess as to what the preferred vco is.
5799 */
5800 if (dev_priv->skl_preferred_vco_freq == 0)
5801 skl_set_preferred_cdclk_vco(dev_priv,
5802 dev_priv->cdclk_pll.vco);
5803 return;
5804 }
5805
5806 vco = dev_priv->skl_preferred_vco_freq;
5807 if (vco == 0)
5808 vco = 8100000;
5809 cdclk = skl_calc_cdclk(0, vco);
5810
5811 skl_set_cdclk(dev_priv, cdclk, vco);
5812 }
5813
5814 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5815 {
5816 uint32_t cdctl, expected;
5817
5818 /*
5819 * check if the pre-os intialized the display
5820 * There is SWF18 scratchpad register defined which is set by the
5821 * pre-os which can be used by the OS drivers to check the status
5822 */
5823 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5824 goto sanitize;
5825
5826 intel_update_cdclk(dev_priv->dev);
5827 /* Is PLL enabled and locked ? */
5828 if (dev_priv->cdclk_pll.vco == 0 ||
5829 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5830 goto sanitize;
5831
5832 /* DPLL okay; verify the cdclock
5833 *
5834 * Noticed in some instances that the freq selection is correct but
5835 * decimal part is programmed wrong from BIOS where pre-os does not
5836 * enable display. Verify the same as well.
5837 */
5838 cdctl = I915_READ(CDCLK_CTL);
5839 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5840 skl_cdclk_decimal(dev_priv->cdclk_freq);
5841 if (cdctl == expected)
5842 /* All well; nothing to sanitize */
5843 return;
5844
5845 sanitize:
5846 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5847
5848 /* force cdclk programming */
5849 dev_priv->cdclk_freq = 0;
5850 /* force full PLL disable + enable */
5851 dev_priv->cdclk_pll.vco = -1;
5852 }
5853
5854 /* Adjust CDclk dividers to allow high res or save power if possible */
5855 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5856 {
5857 struct drm_i915_private *dev_priv = dev->dev_private;
5858 u32 val, cmd;
5859
5860 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5861 != dev_priv->cdclk_freq);
5862
5863 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5864 cmd = 2;
5865 else if (cdclk == 266667)
5866 cmd = 1;
5867 else
5868 cmd = 0;
5869
5870 mutex_lock(&dev_priv->rps.hw_lock);
5871 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5872 val &= ~DSPFREQGUAR_MASK;
5873 val |= (cmd << DSPFREQGUAR_SHIFT);
5874 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5875 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5876 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5877 50)) {
5878 DRM_ERROR("timed out waiting for CDclk change\n");
5879 }
5880 mutex_unlock(&dev_priv->rps.hw_lock);
5881
5882 mutex_lock(&dev_priv->sb_lock);
5883
5884 if (cdclk == 400000) {
5885 u32 divider;
5886
5887 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5888
5889 /* adjust cdclk divider */
5890 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5891 val &= ~CCK_FREQUENCY_VALUES;
5892 val |= divider;
5893 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5894
5895 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5896 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5897 50))
5898 DRM_ERROR("timed out waiting for CDclk change\n");
5899 }
5900
5901 /* adjust self-refresh exit latency value */
5902 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5903 val &= ~0x7f;
5904
5905 /*
5906 * For high bandwidth configs, we set a higher latency in the bunit
5907 * so that the core display fetch happens in time to avoid underruns.
5908 */
5909 if (cdclk == 400000)
5910 val |= 4500 / 250; /* 4.5 usec */
5911 else
5912 val |= 3000 / 250; /* 3.0 usec */
5913 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5914
5915 mutex_unlock(&dev_priv->sb_lock);
5916
5917 intel_update_cdclk(dev);
5918 }
5919
5920 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5921 {
5922 struct drm_i915_private *dev_priv = dev->dev_private;
5923 u32 val, cmd;
5924
5925 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5926 != dev_priv->cdclk_freq);
5927
5928 switch (cdclk) {
5929 case 333333:
5930 case 320000:
5931 case 266667:
5932 case 200000:
5933 break;
5934 default:
5935 MISSING_CASE(cdclk);
5936 return;
5937 }
5938
5939 /*
5940 * Specs are full of misinformation, but testing on actual
5941 * hardware has shown that we just need to write the desired
5942 * CCK divider into the Punit register.
5943 */
5944 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5945
5946 mutex_lock(&dev_priv->rps.hw_lock);
5947 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5948 val &= ~DSPFREQGUAR_MASK_CHV;
5949 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5950 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5951 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5952 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5953 50)) {
5954 DRM_ERROR("timed out waiting for CDclk change\n");
5955 }
5956 mutex_unlock(&dev_priv->rps.hw_lock);
5957
5958 intel_update_cdclk(dev);
5959 }
5960
5961 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5962 int max_pixclk)
5963 {
5964 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5965 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5966
5967 /*
5968 * Really only a few cases to deal with, as only 4 CDclks are supported:
5969 * 200MHz
5970 * 267MHz
5971 * 320/333MHz (depends on HPLL freq)
5972 * 400MHz (VLV only)
5973 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5974 * of the lower bin and adjust if needed.
5975 *
5976 * We seem to get an unstable or solid color picture at 200MHz.
5977 * Not sure what's wrong. For now use 200MHz only when all pipes
5978 * are off.
5979 */
5980 if (!IS_CHERRYVIEW(dev_priv) &&
5981 max_pixclk > freq_320*limit/100)
5982 return 400000;
5983 else if (max_pixclk > 266667*limit/100)
5984 return freq_320;
5985 else if (max_pixclk > 0)
5986 return 266667;
5987 else
5988 return 200000;
5989 }
5990
5991 static int bxt_calc_cdclk(int max_pixclk)
5992 {
5993 if (max_pixclk > 576000)
5994 return 624000;
5995 else if (max_pixclk > 384000)
5996 return 576000;
5997 else if (max_pixclk > 288000)
5998 return 384000;
5999 else if (max_pixclk > 144000)
6000 return 288000;
6001 else
6002 return 144000;
6003 }
6004
6005 /* Compute the max pixel clock for new configuration. */
6006 static int intel_mode_max_pixclk(struct drm_device *dev,
6007 struct drm_atomic_state *state)
6008 {
6009 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6010 struct drm_i915_private *dev_priv = dev->dev_private;
6011 struct drm_crtc *crtc;
6012 struct drm_crtc_state *crtc_state;
6013 unsigned max_pixclk = 0, i;
6014 enum pipe pipe;
6015
6016 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6017 sizeof(intel_state->min_pixclk));
6018
6019 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6020 int pixclk = 0;
6021
6022 if (crtc_state->enable)
6023 pixclk = crtc_state->adjusted_mode.crtc_clock;
6024
6025 intel_state->min_pixclk[i] = pixclk;
6026 }
6027
6028 for_each_pipe(dev_priv, pipe)
6029 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6030
6031 return max_pixclk;
6032 }
6033
6034 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6035 {
6036 struct drm_device *dev = state->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
6038 int max_pixclk = intel_mode_max_pixclk(dev, state);
6039 struct intel_atomic_state *intel_state =
6040 to_intel_atomic_state(state);
6041
6042 intel_state->cdclk = intel_state->dev_cdclk =
6043 valleyview_calc_cdclk(dev_priv, max_pixclk);
6044
6045 if (!intel_state->active_crtcs)
6046 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6047
6048 return 0;
6049 }
6050
6051 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6052 {
6053 int max_pixclk = ilk_max_pixel_rate(state);
6054 struct intel_atomic_state *intel_state =
6055 to_intel_atomic_state(state);
6056
6057 intel_state->cdclk = intel_state->dev_cdclk =
6058 bxt_calc_cdclk(max_pixclk);
6059
6060 if (!intel_state->active_crtcs)
6061 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6062
6063 return 0;
6064 }
6065
6066 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6067 {
6068 unsigned int credits, default_credits;
6069
6070 if (IS_CHERRYVIEW(dev_priv))
6071 default_credits = PFI_CREDIT(12);
6072 else
6073 default_credits = PFI_CREDIT(8);
6074
6075 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6076 /* CHV suggested value is 31 or 63 */
6077 if (IS_CHERRYVIEW(dev_priv))
6078 credits = PFI_CREDIT_63;
6079 else
6080 credits = PFI_CREDIT(15);
6081 } else {
6082 credits = default_credits;
6083 }
6084
6085 /*
6086 * WA - write default credits before re-programming
6087 * FIXME: should we also set the resend bit here?
6088 */
6089 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6090 default_credits);
6091
6092 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6093 credits | PFI_CREDIT_RESEND);
6094
6095 /*
6096 * FIXME is this guaranteed to clear
6097 * immediately or should we poll for it?
6098 */
6099 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6100 }
6101
6102 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6103 {
6104 struct drm_device *dev = old_state->dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106 struct intel_atomic_state *old_intel_state =
6107 to_intel_atomic_state(old_state);
6108 unsigned req_cdclk = old_intel_state->dev_cdclk;
6109
6110 /*
6111 * FIXME: We can end up here with all power domains off, yet
6112 * with a CDCLK frequency other than the minimum. To account
6113 * for this take the PIPE-A power domain, which covers the HW
6114 * blocks needed for the following programming. This can be
6115 * removed once it's guaranteed that we get here either with
6116 * the minimum CDCLK set, or the required power domains
6117 * enabled.
6118 */
6119 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6120
6121 if (IS_CHERRYVIEW(dev))
6122 cherryview_set_cdclk(dev, req_cdclk);
6123 else
6124 valleyview_set_cdclk(dev, req_cdclk);
6125
6126 vlv_program_pfi_credits(dev_priv);
6127
6128 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6129 }
6130
6131 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6132 {
6133 struct drm_device *dev = crtc->dev;
6134 struct drm_i915_private *dev_priv = to_i915(dev);
6135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6136 struct intel_encoder *encoder;
6137 struct intel_crtc_state *pipe_config =
6138 to_intel_crtc_state(crtc->state);
6139 int pipe = intel_crtc->pipe;
6140
6141 if (WARN_ON(intel_crtc->active))
6142 return;
6143
6144 if (intel_crtc->config->has_dp_encoder)
6145 intel_dp_set_m_n(intel_crtc, M1_N1);
6146
6147 intel_set_pipe_timings(intel_crtc);
6148 intel_set_pipe_src_size(intel_crtc);
6149
6150 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152
6153 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6154 I915_WRITE(CHV_CANVAS(pipe), 0);
6155 }
6156
6157 i9xx_set_pipeconf(intel_crtc);
6158
6159 intel_crtc->active = true;
6160
6161 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6162
6163 for_each_encoder_on_crtc(dev, crtc, encoder)
6164 if (encoder->pre_pll_enable)
6165 encoder->pre_pll_enable(encoder);
6166
6167 if (IS_CHERRYVIEW(dev)) {
6168 chv_prepare_pll(intel_crtc, intel_crtc->config);
6169 chv_enable_pll(intel_crtc, intel_crtc->config);
6170 } else {
6171 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6172 vlv_enable_pll(intel_crtc, intel_crtc->config);
6173 }
6174
6175 for_each_encoder_on_crtc(dev, crtc, encoder)
6176 if (encoder->pre_enable)
6177 encoder->pre_enable(encoder);
6178
6179 i9xx_pfit_enable(intel_crtc);
6180
6181 intel_color_load_luts(&pipe_config->base);
6182
6183 intel_update_watermarks(crtc);
6184 intel_enable_pipe(intel_crtc);
6185
6186 assert_vblank_disabled(crtc);
6187 drm_crtc_vblank_on(crtc);
6188
6189 for_each_encoder_on_crtc(dev, crtc, encoder)
6190 encoder->enable(encoder);
6191 }
6192
6193 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6194 {
6195 struct drm_device *dev = crtc->base.dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197
6198 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6199 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6200 }
6201
6202 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6203 {
6204 struct drm_device *dev = crtc->dev;
6205 struct drm_i915_private *dev_priv = to_i915(dev);
6206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207 struct intel_encoder *encoder;
6208 struct intel_crtc_state *pipe_config =
6209 to_intel_crtc_state(crtc->state);
6210 enum pipe pipe = intel_crtc->pipe;
6211
6212 if (WARN_ON(intel_crtc->active))
6213 return;
6214
6215 i9xx_set_pll_dividers(intel_crtc);
6216
6217 if (intel_crtc->config->has_dp_encoder)
6218 intel_dp_set_m_n(intel_crtc, M1_N1);
6219
6220 intel_set_pipe_timings(intel_crtc);
6221 intel_set_pipe_src_size(intel_crtc);
6222
6223 i9xx_set_pipeconf(intel_crtc);
6224
6225 intel_crtc->active = true;
6226
6227 if (!IS_GEN2(dev))
6228 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6229
6230 for_each_encoder_on_crtc(dev, crtc, encoder)
6231 if (encoder->pre_enable)
6232 encoder->pre_enable(encoder);
6233
6234 i9xx_enable_pll(intel_crtc);
6235
6236 i9xx_pfit_enable(intel_crtc);
6237
6238 intel_color_load_luts(&pipe_config->base);
6239
6240 intel_update_watermarks(crtc);
6241 intel_enable_pipe(intel_crtc);
6242
6243 assert_vblank_disabled(crtc);
6244 drm_crtc_vblank_on(crtc);
6245
6246 for_each_encoder_on_crtc(dev, crtc, encoder)
6247 encoder->enable(encoder);
6248 }
6249
6250 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6251 {
6252 struct drm_device *dev = crtc->base.dev;
6253 struct drm_i915_private *dev_priv = dev->dev_private;
6254
6255 if (!crtc->config->gmch_pfit.control)
6256 return;
6257
6258 assert_pipe_disabled(dev_priv, crtc->pipe);
6259
6260 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6261 I915_READ(PFIT_CONTROL));
6262 I915_WRITE(PFIT_CONTROL, 0);
6263 }
6264
6265 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6266 {
6267 struct drm_device *dev = crtc->dev;
6268 struct drm_i915_private *dev_priv = dev->dev_private;
6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270 struct intel_encoder *encoder;
6271 int pipe = intel_crtc->pipe;
6272
6273 /*
6274 * On gen2 planes are double buffered but the pipe isn't, so we must
6275 * wait for planes to fully turn off before disabling the pipe.
6276 */
6277 if (IS_GEN2(dev))
6278 intel_wait_for_vblank(dev, pipe);
6279
6280 for_each_encoder_on_crtc(dev, crtc, encoder)
6281 encoder->disable(encoder);
6282
6283 drm_crtc_vblank_off(crtc);
6284 assert_vblank_disabled(crtc);
6285
6286 intel_disable_pipe(intel_crtc);
6287
6288 i9xx_pfit_disable(intel_crtc);
6289
6290 for_each_encoder_on_crtc(dev, crtc, encoder)
6291 if (encoder->post_disable)
6292 encoder->post_disable(encoder);
6293
6294 if (!intel_crtc->config->has_dsi_encoder) {
6295 if (IS_CHERRYVIEW(dev))
6296 chv_disable_pll(dev_priv, pipe);
6297 else if (IS_VALLEYVIEW(dev))
6298 vlv_disable_pll(dev_priv, pipe);
6299 else
6300 i9xx_disable_pll(intel_crtc);
6301 }
6302
6303 for_each_encoder_on_crtc(dev, crtc, encoder)
6304 if (encoder->post_pll_disable)
6305 encoder->post_pll_disable(encoder);
6306
6307 if (!IS_GEN2(dev))
6308 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6309 }
6310
6311 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6312 {
6313 struct intel_encoder *encoder;
6314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6316 enum intel_display_power_domain domain;
6317 unsigned long domains;
6318
6319 if (!intel_crtc->active)
6320 return;
6321
6322 if (to_intel_plane_state(crtc->primary->state)->visible) {
6323 WARN_ON(intel_crtc->flip_work);
6324
6325 intel_pre_disable_primary_noatomic(crtc);
6326
6327 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6328 to_intel_plane_state(crtc->primary->state)->visible = false;
6329 }
6330
6331 dev_priv->display.crtc_disable(crtc);
6332
6333 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6334 crtc->base.id, crtc->name);
6335
6336 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6337 crtc->state->active = false;
6338 intel_crtc->active = false;
6339 crtc->enabled = false;
6340 crtc->state->connector_mask = 0;
6341 crtc->state->encoder_mask = 0;
6342
6343 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6344 encoder->base.crtc = NULL;
6345
6346 intel_fbc_disable(intel_crtc);
6347 intel_update_watermarks(crtc);
6348 intel_disable_shared_dpll(intel_crtc);
6349
6350 domains = intel_crtc->enabled_power_domains;
6351 for_each_power_domain(domain, domains)
6352 intel_display_power_put(dev_priv, domain);
6353 intel_crtc->enabled_power_domains = 0;
6354
6355 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6356 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6357 }
6358
6359 /*
6360 * turn all crtc's off, but do not adjust state
6361 * This has to be paired with a call to intel_modeset_setup_hw_state.
6362 */
6363 int intel_display_suspend(struct drm_device *dev)
6364 {
6365 struct drm_i915_private *dev_priv = to_i915(dev);
6366 struct drm_atomic_state *state;
6367 int ret;
6368
6369 state = drm_atomic_helper_suspend(dev);
6370 ret = PTR_ERR_OR_ZERO(state);
6371 if (ret)
6372 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6373 else
6374 dev_priv->modeset_restore_state = state;
6375 return ret;
6376 }
6377
6378 void intel_encoder_destroy(struct drm_encoder *encoder)
6379 {
6380 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6381
6382 drm_encoder_cleanup(encoder);
6383 kfree(intel_encoder);
6384 }
6385
6386 /* Cross check the actual hw state with our own modeset state tracking (and it's
6387 * internal consistency). */
6388 static void intel_connector_verify_state(struct intel_connector *connector)
6389 {
6390 struct drm_crtc *crtc = connector->base.state->crtc;
6391
6392 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6393 connector->base.base.id,
6394 connector->base.name);
6395
6396 if (connector->get_hw_state(connector)) {
6397 struct intel_encoder *encoder = connector->encoder;
6398 struct drm_connector_state *conn_state = connector->base.state;
6399
6400 I915_STATE_WARN(!crtc,
6401 "connector enabled without attached crtc\n");
6402
6403 if (!crtc)
6404 return;
6405
6406 I915_STATE_WARN(!crtc->state->active,
6407 "connector is active, but attached crtc isn't\n");
6408
6409 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6410 return;
6411
6412 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6413 "atomic encoder doesn't match attached encoder\n");
6414
6415 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6416 "attached encoder crtc differs from connector crtc\n");
6417 } else {
6418 I915_STATE_WARN(crtc && crtc->state->active,
6419 "attached crtc is active, but connector isn't\n");
6420 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6421 "best encoder set without crtc!\n");
6422 }
6423 }
6424
6425 int intel_connector_init(struct intel_connector *connector)
6426 {
6427 drm_atomic_helper_connector_reset(&connector->base);
6428
6429 if (!connector->base.state)
6430 return -ENOMEM;
6431
6432 return 0;
6433 }
6434
6435 struct intel_connector *intel_connector_alloc(void)
6436 {
6437 struct intel_connector *connector;
6438
6439 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6440 if (!connector)
6441 return NULL;
6442
6443 if (intel_connector_init(connector) < 0) {
6444 kfree(connector);
6445 return NULL;
6446 }
6447
6448 return connector;
6449 }
6450
6451 /* Simple connector->get_hw_state implementation for encoders that support only
6452 * one connector and no cloning and hence the encoder state determines the state
6453 * of the connector. */
6454 bool intel_connector_get_hw_state(struct intel_connector *connector)
6455 {
6456 enum pipe pipe = 0;
6457 struct intel_encoder *encoder = connector->encoder;
6458
6459 return encoder->get_hw_state(encoder, &pipe);
6460 }
6461
6462 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6463 {
6464 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6465 return crtc_state->fdi_lanes;
6466
6467 return 0;
6468 }
6469
6470 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6471 struct intel_crtc_state *pipe_config)
6472 {
6473 struct drm_atomic_state *state = pipe_config->base.state;
6474 struct intel_crtc *other_crtc;
6475 struct intel_crtc_state *other_crtc_state;
6476
6477 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6478 pipe_name(pipe), pipe_config->fdi_lanes);
6479 if (pipe_config->fdi_lanes > 4) {
6480 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6481 pipe_name(pipe), pipe_config->fdi_lanes);
6482 return -EINVAL;
6483 }
6484
6485 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6486 if (pipe_config->fdi_lanes > 2) {
6487 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6488 pipe_config->fdi_lanes);
6489 return -EINVAL;
6490 } else {
6491 return 0;
6492 }
6493 }
6494
6495 if (INTEL_INFO(dev)->num_pipes == 2)
6496 return 0;
6497
6498 /* Ivybridge 3 pipe is really complicated */
6499 switch (pipe) {
6500 case PIPE_A:
6501 return 0;
6502 case PIPE_B:
6503 if (pipe_config->fdi_lanes <= 2)
6504 return 0;
6505
6506 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6507 other_crtc_state =
6508 intel_atomic_get_crtc_state(state, other_crtc);
6509 if (IS_ERR(other_crtc_state))
6510 return PTR_ERR(other_crtc_state);
6511
6512 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6513 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6514 pipe_name(pipe), pipe_config->fdi_lanes);
6515 return -EINVAL;
6516 }
6517 return 0;
6518 case PIPE_C:
6519 if (pipe_config->fdi_lanes > 2) {
6520 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6521 pipe_name(pipe), pipe_config->fdi_lanes);
6522 return -EINVAL;
6523 }
6524
6525 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6526 other_crtc_state =
6527 intel_atomic_get_crtc_state(state, other_crtc);
6528 if (IS_ERR(other_crtc_state))
6529 return PTR_ERR(other_crtc_state);
6530
6531 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6532 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6533 return -EINVAL;
6534 }
6535 return 0;
6536 default:
6537 BUG();
6538 }
6539 }
6540
6541 #define RETRY 1
6542 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6543 struct intel_crtc_state *pipe_config)
6544 {
6545 struct drm_device *dev = intel_crtc->base.dev;
6546 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6547 int lane, link_bw, fdi_dotclock, ret;
6548 bool needs_recompute = false;
6549
6550 retry:
6551 /* FDI is a binary signal running at ~2.7GHz, encoding
6552 * each output octet as 10 bits. The actual frequency
6553 * is stored as a divider into a 100MHz clock, and the
6554 * mode pixel clock is stored in units of 1KHz.
6555 * Hence the bw of each lane in terms of the mode signal
6556 * is:
6557 */
6558 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6559
6560 fdi_dotclock = adjusted_mode->crtc_clock;
6561
6562 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6563 pipe_config->pipe_bpp);
6564
6565 pipe_config->fdi_lanes = lane;
6566
6567 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6568 link_bw, &pipe_config->fdi_m_n);
6569
6570 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6571 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6572 pipe_config->pipe_bpp -= 2*3;
6573 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6574 pipe_config->pipe_bpp);
6575 needs_recompute = true;
6576 pipe_config->bw_constrained = true;
6577
6578 goto retry;
6579 }
6580
6581 if (needs_recompute)
6582 return RETRY;
6583
6584 return ret;
6585 }
6586
6587 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6588 struct intel_crtc_state *pipe_config)
6589 {
6590 if (pipe_config->pipe_bpp > 24)
6591 return false;
6592
6593 /* HSW can handle pixel rate up to cdclk? */
6594 if (IS_HASWELL(dev_priv))
6595 return true;
6596
6597 /*
6598 * We compare against max which means we must take
6599 * the increased cdclk requirement into account when
6600 * calculating the new cdclk.
6601 *
6602 * Should measure whether using a lower cdclk w/o IPS
6603 */
6604 return ilk_pipe_pixel_rate(pipe_config) <=
6605 dev_priv->max_cdclk_freq * 95 / 100;
6606 }
6607
6608 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6609 struct intel_crtc_state *pipe_config)
6610 {
6611 struct drm_device *dev = crtc->base.dev;
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6613
6614 pipe_config->ips_enabled = i915.enable_ips &&
6615 hsw_crtc_supports_ips(crtc) &&
6616 pipe_config_supports_ips(dev_priv, pipe_config);
6617 }
6618
6619 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6620 {
6621 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6622
6623 /* GDG double wide on either pipe, otherwise pipe A only */
6624 return INTEL_INFO(dev_priv)->gen < 4 &&
6625 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6626 }
6627
6628 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6629 struct intel_crtc_state *pipe_config)
6630 {
6631 struct drm_device *dev = crtc->base.dev;
6632 struct drm_i915_private *dev_priv = dev->dev_private;
6633 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6634 int clock_limit = dev_priv->max_dotclk_freq;
6635
6636 if (INTEL_INFO(dev)->gen < 4) {
6637 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6638
6639 /*
6640 * Enable double wide mode when the dot clock
6641 * is > 90% of the (display) core speed.
6642 */
6643 if (intel_crtc_supports_double_wide(crtc) &&
6644 adjusted_mode->crtc_clock > clock_limit) {
6645 clock_limit = dev_priv->max_dotclk_freq;
6646 pipe_config->double_wide = true;
6647 }
6648 }
6649
6650 if (adjusted_mode->crtc_clock > clock_limit) {
6651 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6652 adjusted_mode->crtc_clock, clock_limit,
6653 yesno(pipe_config->double_wide));
6654 return -EINVAL;
6655 }
6656
6657 /*
6658 * Pipe horizontal size must be even in:
6659 * - DVO ganged mode
6660 * - LVDS dual channel mode
6661 * - Double wide pipe
6662 */
6663 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6664 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6665 pipe_config->pipe_src_w &= ~1;
6666
6667 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6668 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6669 */
6670 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6671 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6672 return -EINVAL;
6673
6674 if (HAS_IPS(dev))
6675 hsw_compute_ips_config(crtc, pipe_config);
6676
6677 if (pipe_config->has_pch_encoder)
6678 return ironlake_fdi_compute_config(crtc, pipe_config);
6679
6680 return 0;
6681 }
6682
6683 static int skylake_get_display_clock_speed(struct drm_device *dev)
6684 {
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686 uint32_t cdctl;
6687
6688 skl_dpll0_update(dev_priv);
6689
6690 if (dev_priv->cdclk_pll.vco == 0)
6691 return dev_priv->cdclk_pll.ref;
6692
6693 cdctl = I915_READ(CDCLK_CTL);
6694
6695 if (dev_priv->cdclk_pll.vco == 8640000) {
6696 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6697 case CDCLK_FREQ_450_432:
6698 return 432000;
6699 case CDCLK_FREQ_337_308:
6700 return 308571;
6701 case CDCLK_FREQ_540:
6702 return 540000;
6703 case CDCLK_FREQ_675_617:
6704 return 617143;
6705 default:
6706 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6707 }
6708 } else {
6709 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6710 case CDCLK_FREQ_450_432:
6711 return 450000;
6712 case CDCLK_FREQ_337_308:
6713 return 337500;
6714 case CDCLK_FREQ_540:
6715 return 540000;
6716 case CDCLK_FREQ_675_617:
6717 return 675000;
6718 default:
6719 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6720 }
6721 }
6722
6723 return dev_priv->cdclk_pll.ref;
6724 }
6725
6726 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6727 {
6728 u32 val;
6729
6730 dev_priv->cdclk_pll.ref = 19200;
6731 dev_priv->cdclk_pll.vco = 0;
6732
6733 val = I915_READ(BXT_DE_PLL_ENABLE);
6734 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6735 return;
6736
6737 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6738 return;
6739
6740 val = I915_READ(BXT_DE_PLL_CTL);
6741 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6742 dev_priv->cdclk_pll.ref;
6743 }
6744
6745 static int broxton_get_display_clock_speed(struct drm_device *dev)
6746 {
6747 struct drm_i915_private *dev_priv = to_i915(dev);
6748 u32 divider;
6749 int div, vco;
6750
6751 bxt_de_pll_update(dev_priv);
6752
6753 vco = dev_priv->cdclk_pll.vco;
6754 if (vco == 0)
6755 return dev_priv->cdclk_pll.ref;
6756
6757 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6758
6759 switch (divider) {
6760 case BXT_CDCLK_CD2X_DIV_SEL_1:
6761 div = 2;
6762 break;
6763 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6764 div = 3;
6765 break;
6766 case BXT_CDCLK_CD2X_DIV_SEL_2:
6767 div = 4;
6768 break;
6769 case BXT_CDCLK_CD2X_DIV_SEL_4:
6770 div = 8;
6771 break;
6772 default:
6773 MISSING_CASE(divider);
6774 return dev_priv->cdclk_pll.ref;
6775 }
6776
6777 return DIV_ROUND_CLOSEST(vco, div);
6778 }
6779
6780 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6781 {
6782 struct drm_i915_private *dev_priv = dev->dev_private;
6783 uint32_t lcpll = I915_READ(LCPLL_CTL);
6784 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6785
6786 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6787 return 800000;
6788 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6789 return 450000;
6790 else if (freq == LCPLL_CLK_FREQ_450)
6791 return 450000;
6792 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6793 return 540000;
6794 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6795 return 337500;
6796 else
6797 return 675000;
6798 }
6799
6800 static int haswell_get_display_clock_speed(struct drm_device *dev)
6801 {
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 uint32_t lcpll = I915_READ(LCPLL_CTL);
6804 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6805
6806 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6807 return 800000;
6808 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6809 return 450000;
6810 else if (freq == LCPLL_CLK_FREQ_450)
6811 return 450000;
6812 else if (IS_HSW_ULT(dev))
6813 return 337500;
6814 else
6815 return 540000;
6816 }
6817
6818 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6819 {
6820 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6821 CCK_DISPLAY_CLOCK_CONTROL);
6822 }
6823
6824 static int ilk_get_display_clock_speed(struct drm_device *dev)
6825 {
6826 return 450000;
6827 }
6828
6829 static int i945_get_display_clock_speed(struct drm_device *dev)
6830 {
6831 return 400000;
6832 }
6833
6834 static int i915_get_display_clock_speed(struct drm_device *dev)
6835 {
6836 return 333333;
6837 }
6838
6839 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6840 {
6841 return 200000;
6842 }
6843
6844 static int pnv_get_display_clock_speed(struct drm_device *dev)
6845 {
6846 u16 gcfgc = 0;
6847
6848 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6849
6850 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6851 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6852 return 266667;
6853 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6854 return 333333;
6855 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6856 return 444444;
6857 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6858 return 200000;
6859 default:
6860 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6861 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6862 return 133333;
6863 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6864 return 166667;
6865 }
6866 }
6867
6868 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6869 {
6870 u16 gcfgc = 0;
6871
6872 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6873
6874 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6875 return 133333;
6876 else {
6877 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6878 case GC_DISPLAY_CLOCK_333_MHZ:
6879 return 333333;
6880 default:
6881 case GC_DISPLAY_CLOCK_190_200_MHZ:
6882 return 190000;
6883 }
6884 }
6885 }
6886
6887 static int i865_get_display_clock_speed(struct drm_device *dev)
6888 {
6889 return 266667;
6890 }
6891
6892 static int i85x_get_display_clock_speed(struct drm_device *dev)
6893 {
6894 u16 hpllcc = 0;
6895
6896 /*
6897 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6898 * encoding is different :(
6899 * FIXME is this the right way to detect 852GM/852GMV?
6900 */
6901 if (dev->pdev->revision == 0x1)
6902 return 133333;
6903
6904 pci_bus_read_config_word(dev->pdev->bus,
6905 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6906
6907 /* Assume that the hardware is in the high speed state. This
6908 * should be the default.
6909 */
6910 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6911 case GC_CLOCK_133_200:
6912 case GC_CLOCK_133_200_2:
6913 case GC_CLOCK_100_200:
6914 return 200000;
6915 case GC_CLOCK_166_250:
6916 return 250000;
6917 case GC_CLOCK_100_133:
6918 return 133333;
6919 case GC_CLOCK_133_266:
6920 case GC_CLOCK_133_266_2:
6921 case GC_CLOCK_166_266:
6922 return 266667;
6923 }
6924
6925 /* Shouldn't happen */
6926 return 0;
6927 }
6928
6929 static int i830_get_display_clock_speed(struct drm_device *dev)
6930 {
6931 return 133333;
6932 }
6933
6934 static unsigned int intel_hpll_vco(struct drm_device *dev)
6935 {
6936 struct drm_i915_private *dev_priv = dev->dev_private;
6937 static const unsigned int blb_vco[8] = {
6938 [0] = 3200000,
6939 [1] = 4000000,
6940 [2] = 5333333,
6941 [3] = 4800000,
6942 [4] = 6400000,
6943 };
6944 static const unsigned int pnv_vco[8] = {
6945 [0] = 3200000,
6946 [1] = 4000000,
6947 [2] = 5333333,
6948 [3] = 4800000,
6949 [4] = 2666667,
6950 };
6951 static const unsigned int cl_vco[8] = {
6952 [0] = 3200000,
6953 [1] = 4000000,
6954 [2] = 5333333,
6955 [3] = 6400000,
6956 [4] = 3333333,
6957 [5] = 3566667,
6958 [6] = 4266667,
6959 };
6960 static const unsigned int elk_vco[8] = {
6961 [0] = 3200000,
6962 [1] = 4000000,
6963 [2] = 5333333,
6964 [3] = 4800000,
6965 };
6966 static const unsigned int ctg_vco[8] = {
6967 [0] = 3200000,
6968 [1] = 4000000,
6969 [2] = 5333333,
6970 [3] = 6400000,
6971 [4] = 2666667,
6972 [5] = 4266667,
6973 };
6974 const unsigned int *vco_table;
6975 unsigned int vco;
6976 uint8_t tmp = 0;
6977
6978 /* FIXME other chipsets? */
6979 if (IS_GM45(dev))
6980 vco_table = ctg_vco;
6981 else if (IS_G4X(dev))
6982 vco_table = elk_vco;
6983 else if (IS_CRESTLINE(dev))
6984 vco_table = cl_vco;
6985 else if (IS_PINEVIEW(dev))
6986 vco_table = pnv_vco;
6987 else if (IS_G33(dev))
6988 vco_table = blb_vco;
6989 else
6990 return 0;
6991
6992 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6993
6994 vco = vco_table[tmp & 0x7];
6995 if (vco == 0)
6996 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6997 else
6998 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6999
7000 return vco;
7001 }
7002
7003 static int gm45_get_display_clock_speed(struct drm_device *dev)
7004 {
7005 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7006 uint16_t tmp = 0;
7007
7008 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7009
7010 cdclk_sel = (tmp >> 12) & 0x1;
7011
7012 switch (vco) {
7013 case 2666667:
7014 case 4000000:
7015 case 5333333:
7016 return cdclk_sel ? 333333 : 222222;
7017 case 3200000:
7018 return cdclk_sel ? 320000 : 228571;
7019 default:
7020 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7021 return 222222;
7022 }
7023 }
7024
7025 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7026 {
7027 static const uint8_t div_3200[] = { 16, 10, 8 };
7028 static const uint8_t div_4000[] = { 20, 12, 10 };
7029 static const uint8_t div_5333[] = { 24, 16, 14 };
7030 const uint8_t *div_table;
7031 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7032 uint16_t tmp = 0;
7033
7034 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7035
7036 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7037
7038 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7039 goto fail;
7040
7041 switch (vco) {
7042 case 3200000:
7043 div_table = div_3200;
7044 break;
7045 case 4000000:
7046 div_table = div_4000;
7047 break;
7048 case 5333333:
7049 div_table = div_5333;
7050 break;
7051 default:
7052 goto fail;
7053 }
7054
7055 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7056
7057 fail:
7058 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7059 return 200000;
7060 }
7061
7062 static int g33_get_display_clock_speed(struct drm_device *dev)
7063 {
7064 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7065 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7066 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7067 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7068 const uint8_t *div_table;
7069 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7070 uint16_t tmp = 0;
7071
7072 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7073
7074 cdclk_sel = (tmp >> 4) & 0x7;
7075
7076 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7077 goto fail;
7078
7079 switch (vco) {
7080 case 3200000:
7081 div_table = div_3200;
7082 break;
7083 case 4000000:
7084 div_table = div_4000;
7085 break;
7086 case 4800000:
7087 div_table = div_4800;
7088 break;
7089 case 5333333:
7090 div_table = div_5333;
7091 break;
7092 default:
7093 goto fail;
7094 }
7095
7096 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7097
7098 fail:
7099 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7100 return 190476;
7101 }
7102
7103 static void
7104 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7105 {
7106 while (*num > DATA_LINK_M_N_MASK ||
7107 *den > DATA_LINK_M_N_MASK) {
7108 *num >>= 1;
7109 *den >>= 1;
7110 }
7111 }
7112
7113 static void compute_m_n(unsigned int m, unsigned int n,
7114 uint32_t *ret_m, uint32_t *ret_n)
7115 {
7116 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7117 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7118 intel_reduce_m_n_ratio(ret_m, ret_n);
7119 }
7120
7121 void
7122 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7123 int pixel_clock, int link_clock,
7124 struct intel_link_m_n *m_n)
7125 {
7126 m_n->tu = 64;
7127
7128 compute_m_n(bits_per_pixel * pixel_clock,
7129 link_clock * nlanes * 8,
7130 &m_n->gmch_m, &m_n->gmch_n);
7131
7132 compute_m_n(pixel_clock, link_clock,
7133 &m_n->link_m, &m_n->link_n);
7134 }
7135
7136 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7137 {
7138 if (i915.panel_use_ssc >= 0)
7139 return i915.panel_use_ssc != 0;
7140 return dev_priv->vbt.lvds_use_ssc
7141 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7142 }
7143
7144 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7145 {
7146 return (1 << dpll->n) << 16 | dpll->m2;
7147 }
7148
7149 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7150 {
7151 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7152 }
7153
7154 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7155 struct intel_crtc_state *crtc_state,
7156 struct dpll *reduced_clock)
7157 {
7158 struct drm_device *dev = crtc->base.dev;
7159 u32 fp, fp2 = 0;
7160
7161 if (IS_PINEVIEW(dev)) {
7162 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7163 if (reduced_clock)
7164 fp2 = pnv_dpll_compute_fp(reduced_clock);
7165 } else {
7166 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7167 if (reduced_clock)
7168 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7169 }
7170
7171 crtc_state->dpll_hw_state.fp0 = fp;
7172
7173 crtc->lowfreq_avail = false;
7174 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7175 reduced_clock) {
7176 crtc_state->dpll_hw_state.fp1 = fp2;
7177 crtc->lowfreq_avail = true;
7178 } else {
7179 crtc_state->dpll_hw_state.fp1 = fp;
7180 }
7181 }
7182
7183 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7184 pipe)
7185 {
7186 u32 reg_val;
7187
7188 /*
7189 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7190 * and set it to a reasonable value instead.
7191 */
7192 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7193 reg_val &= 0xffffff00;
7194 reg_val |= 0x00000030;
7195 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7196
7197 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7198 reg_val &= 0x8cffffff;
7199 reg_val = 0x8c000000;
7200 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7201
7202 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7203 reg_val &= 0xffffff00;
7204 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7205
7206 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7207 reg_val &= 0x00ffffff;
7208 reg_val |= 0xb0000000;
7209 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7210 }
7211
7212 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7213 struct intel_link_m_n *m_n)
7214 {
7215 struct drm_device *dev = crtc->base.dev;
7216 struct drm_i915_private *dev_priv = dev->dev_private;
7217 int pipe = crtc->pipe;
7218
7219 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7220 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7221 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7222 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7223 }
7224
7225 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7226 struct intel_link_m_n *m_n,
7227 struct intel_link_m_n *m2_n2)
7228 {
7229 struct drm_device *dev = crtc->base.dev;
7230 struct drm_i915_private *dev_priv = dev->dev_private;
7231 int pipe = crtc->pipe;
7232 enum transcoder transcoder = crtc->config->cpu_transcoder;
7233
7234 if (INTEL_INFO(dev)->gen >= 5) {
7235 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7236 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7237 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7238 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7239 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7240 * for gen < 8) and if DRRS is supported (to make sure the
7241 * registers are not unnecessarily accessed).
7242 */
7243 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7244 crtc->config->has_drrs) {
7245 I915_WRITE(PIPE_DATA_M2(transcoder),
7246 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7247 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7248 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7249 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7250 }
7251 } else {
7252 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7253 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7254 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7255 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7256 }
7257 }
7258
7259 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7260 {
7261 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7262
7263 if (m_n == M1_N1) {
7264 dp_m_n = &crtc->config->dp_m_n;
7265 dp_m2_n2 = &crtc->config->dp_m2_n2;
7266 } else if (m_n == M2_N2) {
7267
7268 /*
7269 * M2_N2 registers are not supported. Hence m2_n2 divider value
7270 * needs to be programmed into M1_N1.
7271 */
7272 dp_m_n = &crtc->config->dp_m2_n2;
7273 } else {
7274 DRM_ERROR("Unsupported divider value\n");
7275 return;
7276 }
7277
7278 if (crtc->config->has_pch_encoder)
7279 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7280 else
7281 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7282 }
7283
7284 static void vlv_compute_dpll(struct intel_crtc *crtc,
7285 struct intel_crtc_state *pipe_config)
7286 {
7287 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7288 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7289 if (crtc->pipe != PIPE_A)
7290 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7291
7292 /* DPLL not used with DSI, but still need the rest set up */
7293 if (!pipe_config->has_dsi_encoder)
7294 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7295 DPLL_EXT_BUFFER_ENABLE_VLV;
7296
7297 pipe_config->dpll_hw_state.dpll_md =
7298 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7299 }
7300
7301 static void chv_compute_dpll(struct intel_crtc *crtc,
7302 struct intel_crtc_state *pipe_config)
7303 {
7304 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7305 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7306 if (crtc->pipe != PIPE_A)
7307 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7308
7309 /* DPLL not used with DSI, but still need the rest set up */
7310 if (!pipe_config->has_dsi_encoder)
7311 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7312
7313 pipe_config->dpll_hw_state.dpll_md =
7314 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7315 }
7316
7317 static void vlv_prepare_pll(struct intel_crtc *crtc,
7318 const struct intel_crtc_state *pipe_config)
7319 {
7320 struct drm_device *dev = crtc->base.dev;
7321 struct drm_i915_private *dev_priv = dev->dev_private;
7322 enum pipe pipe = crtc->pipe;
7323 u32 mdiv;
7324 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7325 u32 coreclk, reg_val;
7326
7327 /* Enable Refclk */
7328 I915_WRITE(DPLL(pipe),
7329 pipe_config->dpll_hw_state.dpll &
7330 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7331
7332 /* No need to actually set up the DPLL with DSI */
7333 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7334 return;
7335
7336 mutex_lock(&dev_priv->sb_lock);
7337
7338 bestn = pipe_config->dpll.n;
7339 bestm1 = pipe_config->dpll.m1;
7340 bestm2 = pipe_config->dpll.m2;
7341 bestp1 = pipe_config->dpll.p1;
7342 bestp2 = pipe_config->dpll.p2;
7343
7344 /* See eDP HDMI DPIO driver vbios notes doc */
7345
7346 /* PLL B needs special handling */
7347 if (pipe == PIPE_B)
7348 vlv_pllb_recal_opamp(dev_priv, pipe);
7349
7350 /* Set up Tx target for periodic Rcomp update */
7351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7352
7353 /* Disable target IRef on PLL */
7354 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7355 reg_val &= 0x00ffffff;
7356 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7357
7358 /* Disable fast lock */
7359 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7360
7361 /* Set idtafcrecal before PLL is enabled */
7362 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7363 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7364 mdiv |= ((bestn << DPIO_N_SHIFT));
7365 mdiv |= (1 << DPIO_K_SHIFT);
7366
7367 /*
7368 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7369 * but we don't support that).
7370 * Note: don't use the DAC post divider as it seems unstable.
7371 */
7372 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7373 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7374
7375 mdiv |= DPIO_ENABLE_CALIBRATION;
7376 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7377
7378 /* Set HBR and RBR LPF coefficients */
7379 if (pipe_config->port_clock == 162000 ||
7380 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7381 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7383 0x009f0003);
7384 else
7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7386 0x00d0000f);
7387
7388 if (pipe_config->has_dp_encoder) {
7389 /* Use SSC source */
7390 if (pipe == PIPE_A)
7391 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7392 0x0df40000);
7393 else
7394 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7395 0x0df70000);
7396 } else { /* HDMI or VGA */
7397 /* Use bend source */
7398 if (pipe == PIPE_A)
7399 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7400 0x0df70000);
7401 else
7402 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7403 0x0df40000);
7404 }
7405
7406 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7407 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7409 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7410 coreclk |= 0x01000000;
7411 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7412
7413 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7414 mutex_unlock(&dev_priv->sb_lock);
7415 }
7416
7417 static void chv_prepare_pll(struct intel_crtc *crtc,
7418 const struct intel_crtc_state *pipe_config)
7419 {
7420 struct drm_device *dev = crtc->base.dev;
7421 struct drm_i915_private *dev_priv = dev->dev_private;
7422 enum pipe pipe = crtc->pipe;
7423 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7424 u32 loopfilter, tribuf_calcntr;
7425 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7426 u32 dpio_val;
7427 int vco;
7428
7429 /* Enable Refclk and SSC */
7430 I915_WRITE(DPLL(pipe),
7431 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7432
7433 /* No need to actually set up the DPLL with DSI */
7434 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7435 return;
7436
7437 bestn = pipe_config->dpll.n;
7438 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7439 bestm1 = pipe_config->dpll.m1;
7440 bestm2 = pipe_config->dpll.m2 >> 22;
7441 bestp1 = pipe_config->dpll.p1;
7442 bestp2 = pipe_config->dpll.p2;
7443 vco = pipe_config->dpll.vco;
7444 dpio_val = 0;
7445 loopfilter = 0;
7446
7447 mutex_lock(&dev_priv->sb_lock);
7448
7449 /* p1 and p2 divider */
7450 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7451 5 << DPIO_CHV_S1_DIV_SHIFT |
7452 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7453 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7454 1 << DPIO_CHV_K_DIV_SHIFT);
7455
7456 /* Feedback post-divider - m2 */
7457 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7458
7459 /* Feedback refclk divider - n and m1 */
7460 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7461 DPIO_CHV_M1_DIV_BY_2 |
7462 1 << DPIO_CHV_N_DIV_SHIFT);
7463
7464 /* M2 fraction division */
7465 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7466
7467 /* M2 fraction division enable */
7468 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7469 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7470 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7471 if (bestm2_frac)
7472 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7473 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7474
7475 /* Program digital lock detect threshold */
7476 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7477 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7478 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7479 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7480 if (!bestm2_frac)
7481 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7482 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7483
7484 /* Loop filter */
7485 if (vco == 5400000) {
7486 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7487 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7488 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7489 tribuf_calcntr = 0x9;
7490 } else if (vco <= 6200000) {
7491 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7492 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7493 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7494 tribuf_calcntr = 0x9;
7495 } else if (vco <= 6480000) {
7496 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7497 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7498 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7499 tribuf_calcntr = 0x8;
7500 } else {
7501 /* Not supported. Apply the same limits as in the max case */
7502 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7503 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7504 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7505 tribuf_calcntr = 0;
7506 }
7507 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7508
7509 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7510 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7511 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7512 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7513
7514 /* AFC Recal */
7515 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7516 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7517 DPIO_AFC_RECAL);
7518
7519 mutex_unlock(&dev_priv->sb_lock);
7520 }
7521
7522 /**
7523 * vlv_force_pll_on - forcibly enable just the PLL
7524 * @dev_priv: i915 private structure
7525 * @pipe: pipe PLL to enable
7526 * @dpll: PLL configuration
7527 *
7528 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7529 * in cases where we need the PLL enabled even when @pipe is not going to
7530 * be enabled.
7531 */
7532 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7533 const struct dpll *dpll)
7534 {
7535 struct intel_crtc *crtc =
7536 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7537 struct intel_crtc_state *pipe_config;
7538
7539 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7540 if (!pipe_config)
7541 return -ENOMEM;
7542
7543 pipe_config->base.crtc = &crtc->base;
7544 pipe_config->pixel_multiplier = 1;
7545 pipe_config->dpll = *dpll;
7546
7547 if (IS_CHERRYVIEW(dev)) {
7548 chv_compute_dpll(crtc, pipe_config);
7549 chv_prepare_pll(crtc, pipe_config);
7550 chv_enable_pll(crtc, pipe_config);
7551 } else {
7552 vlv_compute_dpll(crtc, pipe_config);
7553 vlv_prepare_pll(crtc, pipe_config);
7554 vlv_enable_pll(crtc, pipe_config);
7555 }
7556
7557 kfree(pipe_config);
7558
7559 return 0;
7560 }
7561
7562 /**
7563 * vlv_force_pll_off - forcibly disable just the PLL
7564 * @dev_priv: i915 private structure
7565 * @pipe: pipe PLL to disable
7566 *
7567 * Disable the PLL for @pipe. To be used in cases where we need
7568 * the PLL enabled even when @pipe is not going to be enabled.
7569 */
7570 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7571 {
7572 if (IS_CHERRYVIEW(dev))
7573 chv_disable_pll(to_i915(dev), pipe);
7574 else
7575 vlv_disable_pll(to_i915(dev), pipe);
7576 }
7577
7578 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7579 struct intel_crtc_state *crtc_state,
7580 struct dpll *reduced_clock)
7581 {
7582 struct drm_device *dev = crtc->base.dev;
7583 struct drm_i915_private *dev_priv = dev->dev_private;
7584 u32 dpll;
7585 bool is_sdvo;
7586 struct dpll *clock = &crtc_state->dpll;
7587
7588 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7589
7590 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7591 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7592
7593 dpll = DPLL_VGA_MODE_DIS;
7594
7595 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7596 dpll |= DPLLB_MODE_LVDS;
7597 else
7598 dpll |= DPLLB_MODE_DAC_SERIAL;
7599
7600 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7601 dpll |= (crtc_state->pixel_multiplier - 1)
7602 << SDVO_MULTIPLIER_SHIFT_HIRES;
7603 }
7604
7605 if (is_sdvo)
7606 dpll |= DPLL_SDVO_HIGH_SPEED;
7607
7608 if (crtc_state->has_dp_encoder)
7609 dpll |= DPLL_SDVO_HIGH_SPEED;
7610
7611 /* compute bitmask from p1 value */
7612 if (IS_PINEVIEW(dev))
7613 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7614 else {
7615 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7616 if (IS_G4X(dev) && reduced_clock)
7617 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7618 }
7619 switch (clock->p2) {
7620 case 5:
7621 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7622 break;
7623 case 7:
7624 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7625 break;
7626 case 10:
7627 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7628 break;
7629 case 14:
7630 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7631 break;
7632 }
7633 if (INTEL_INFO(dev)->gen >= 4)
7634 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7635
7636 if (crtc_state->sdvo_tv_clock)
7637 dpll |= PLL_REF_INPUT_TVCLKINBC;
7638 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7639 intel_panel_use_ssc(dev_priv))
7640 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7641 else
7642 dpll |= PLL_REF_INPUT_DREFCLK;
7643
7644 dpll |= DPLL_VCO_ENABLE;
7645 crtc_state->dpll_hw_state.dpll = dpll;
7646
7647 if (INTEL_INFO(dev)->gen >= 4) {
7648 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7649 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7650 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7651 }
7652 }
7653
7654 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7655 struct intel_crtc_state *crtc_state,
7656 struct dpll *reduced_clock)
7657 {
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private;
7660 u32 dpll;
7661 struct dpll *clock = &crtc_state->dpll;
7662
7663 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7664
7665 dpll = DPLL_VGA_MODE_DIS;
7666
7667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7669 } else {
7670 if (clock->p1 == 2)
7671 dpll |= PLL_P1_DIVIDE_BY_TWO;
7672 else
7673 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7674 if (clock->p2 == 4)
7675 dpll |= PLL_P2_DIVIDE_BY_4;
7676 }
7677
7678 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7679 dpll |= DPLL_DVO_2X_MODE;
7680
7681 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7682 intel_panel_use_ssc(dev_priv))
7683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7684 else
7685 dpll |= PLL_REF_INPUT_DREFCLK;
7686
7687 dpll |= DPLL_VCO_ENABLE;
7688 crtc_state->dpll_hw_state.dpll = dpll;
7689 }
7690
7691 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7692 {
7693 struct drm_device *dev = intel_crtc->base.dev;
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695 enum pipe pipe = intel_crtc->pipe;
7696 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7697 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7698 uint32_t crtc_vtotal, crtc_vblank_end;
7699 int vsyncshift = 0;
7700
7701 /* We need to be careful not to changed the adjusted mode, for otherwise
7702 * the hw state checker will get angry at the mismatch. */
7703 crtc_vtotal = adjusted_mode->crtc_vtotal;
7704 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7705
7706 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7707 /* the chip adds 2 halflines automatically */
7708 crtc_vtotal -= 1;
7709 crtc_vblank_end -= 1;
7710
7711 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7712 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7713 else
7714 vsyncshift = adjusted_mode->crtc_hsync_start -
7715 adjusted_mode->crtc_htotal / 2;
7716 if (vsyncshift < 0)
7717 vsyncshift += adjusted_mode->crtc_htotal;
7718 }
7719
7720 if (INTEL_INFO(dev)->gen > 3)
7721 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7722
7723 I915_WRITE(HTOTAL(cpu_transcoder),
7724 (adjusted_mode->crtc_hdisplay - 1) |
7725 ((adjusted_mode->crtc_htotal - 1) << 16));
7726 I915_WRITE(HBLANK(cpu_transcoder),
7727 (adjusted_mode->crtc_hblank_start - 1) |
7728 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7729 I915_WRITE(HSYNC(cpu_transcoder),
7730 (adjusted_mode->crtc_hsync_start - 1) |
7731 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7732
7733 I915_WRITE(VTOTAL(cpu_transcoder),
7734 (adjusted_mode->crtc_vdisplay - 1) |
7735 ((crtc_vtotal - 1) << 16));
7736 I915_WRITE(VBLANK(cpu_transcoder),
7737 (adjusted_mode->crtc_vblank_start - 1) |
7738 ((crtc_vblank_end - 1) << 16));
7739 I915_WRITE(VSYNC(cpu_transcoder),
7740 (adjusted_mode->crtc_vsync_start - 1) |
7741 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7742
7743 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7744 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7745 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7746 * bits. */
7747 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7748 (pipe == PIPE_B || pipe == PIPE_C))
7749 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7750
7751 }
7752
7753 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7754 {
7755 struct drm_device *dev = intel_crtc->base.dev;
7756 struct drm_i915_private *dev_priv = dev->dev_private;
7757 enum pipe pipe = intel_crtc->pipe;
7758
7759 /* pipesrc controls the size that is scaled from, which should
7760 * always be the user's requested size.
7761 */
7762 I915_WRITE(PIPESRC(pipe),
7763 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7764 (intel_crtc->config->pipe_src_h - 1));
7765 }
7766
7767 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7768 struct intel_crtc_state *pipe_config)
7769 {
7770 struct drm_device *dev = crtc->base.dev;
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7773 uint32_t tmp;
7774
7775 tmp = I915_READ(HTOTAL(cpu_transcoder));
7776 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7777 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7778 tmp = I915_READ(HBLANK(cpu_transcoder));
7779 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7780 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7781 tmp = I915_READ(HSYNC(cpu_transcoder));
7782 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7783 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7784
7785 tmp = I915_READ(VTOTAL(cpu_transcoder));
7786 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7787 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7788 tmp = I915_READ(VBLANK(cpu_transcoder));
7789 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7790 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7791 tmp = I915_READ(VSYNC(cpu_transcoder));
7792 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7793 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7794
7795 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7796 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7797 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7798 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7799 }
7800 }
7801
7802 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7803 struct intel_crtc_state *pipe_config)
7804 {
7805 struct drm_device *dev = crtc->base.dev;
7806 struct drm_i915_private *dev_priv = dev->dev_private;
7807 u32 tmp;
7808
7809 tmp = I915_READ(PIPESRC(crtc->pipe));
7810 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7811 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7812
7813 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7814 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7815 }
7816
7817 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7818 struct intel_crtc_state *pipe_config)
7819 {
7820 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7821 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7822 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7823 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7824
7825 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7826 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7827 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7828 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7829
7830 mode->flags = pipe_config->base.adjusted_mode.flags;
7831 mode->type = DRM_MODE_TYPE_DRIVER;
7832
7833 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7834 mode->flags |= pipe_config->base.adjusted_mode.flags;
7835
7836 mode->hsync = drm_mode_hsync(mode);
7837 mode->vrefresh = drm_mode_vrefresh(mode);
7838 drm_mode_set_name(mode);
7839 }
7840
7841 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7842 {
7843 struct drm_device *dev = intel_crtc->base.dev;
7844 struct drm_i915_private *dev_priv = dev->dev_private;
7845 uint32_t pipeconf;
7846
7847 pipeconf = 0;
7848
7849 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7850 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7851 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7852
7853 if (intel_crtc->config->double_wide)
7854 pipeconf |= PIPECONF_DOUBLE_WIDE;
7855
7856 /* only g4x and later have fancy bpc/dither controls */
7857 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7858 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7859 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7860 pipeconf |= PIPECONF_DITHER_EN |
7861 PIPECONF_DITHER_TYPE_SP;
7862
7863 switch (intel_crtc->config->pipe_bpp) {
7864 case 18:
7865 pipeconf |= PIPECONF_6BPC;
7866 break;
7867 case 24:
7868 pipeconf |= PIPECONF_8BPC;
7869 break;
7870 case 30:
7871 pipeconf |= PIPECONF_10BPC;
7872 break;
7873 default:
7874 /* Case prevented by intel_choose_pipe_bpp_dither. */
7875 BUG();
7876 }
7877 }
7878
7879 if (HAS_PIPE_CXSR(dev)) {
7880 if (intel_crtc->lowfreq_avail) {
7881 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7882 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7883 } else {
7884 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7885 }
7886 }
7887
7888 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7889 if (INTEL_INFO(dev)->gen < 4 ||
7890 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7891 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7892 else
7893 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7894 } else
7895 pipeconf |= PIPECONF_PROGRESSIVE;
7896
7897 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7898 intel_crtc->config->limited_color_range)
7899 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7900
7901 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7902 POSTING_READ(PIPECONF(intel_crtc->pipe));
7903 }
7904
7905 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7906 struct intel_crtc_state *crtc_state)
7907 {
7908 struct drm_device *dev = crtc->base.dev;
7909 struct drm_i915_private *dev_priv = dev->dev_private;
7910 const struct intel_limit *limit;
7911 int refclk = 48000;
7912
7913 memset(&crtc_state->dpll_hw_state, 0,
7914 sizeof(crtc_state->dpll_hw_state));
7915
7916 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7917 if (intel_panel_use_ssc(dev_priv)) {
7918 refclk = dev_priv->vbt.lvds_ssc_freq;
7919 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7920 }
7921
7922 limit = &intel_limits_i8xx_lvds;
7923 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7924 limit = &intel_limits_i8xx_dvo;
7925 } else {
7926 limit = &intel_limits_i8xx_dac;
7927 }
7928
7929 if (!crtc_state->clock_set &&
7930 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7931 refclk, NULL, &crtc_state->dpll)) {
7932 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7933 return -EINVAL;
7934 }
7935
7936 i8xx_compute_dpll(crtc, crtc_state, NULL);
7937
7938 return 0;
7939 }
7940
7941 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7942 struct intel_crtc_state *crtc_state)
7943 {
7944 struct drm_device *dev = crtc->base.dev;
7945 struct drm_i915_private *dev_priv = dev->dev_private;
7946 const struct intel_limit *limit;
7947 int refclk = 96000;
7948
7949 memset(&crtc_state->dpll_hw_state, 0,
7950 sizeof(crtc_state->dpll_hw_state));
7951
7952 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7953 if (intel_panel_use_ssc(dev_priv)) {
7954 refclk = dev_priv->vbt.lvds_ssc_freq;
7955 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7956 }
7957
7958 if (intel_is_dual_link_lvds(dev))
7959 limit = &intel_limits_g4x_dual_channel_lvds;
7960 else
7961 limit = &intel_limits_g4x_single_channel_lvds;
7962 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7963 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7964 limit = &intel_limits_g4x_hdmi;
7965 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7966 limit = &intel_limits_g4x_sdvo;
7967 } else {
7968 /* The option is for other outputs */
7969 limit = &intel_limits_i9xx_sdvo;
7970 }
7971
7972 if (!crtc_state->clock_set &&
7973 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7974 refclk, NULL, &crtc_state->dpll)) {
7975 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7976 return -EINVAL;
7977 }
7978
7979 i9xx_compute_dpll(crtc, crtc_state, NULL);
7980
7981 return 0;
7982 }
7983
7984 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7985 struct intel_crtc_state *crtc_state)
7986 {
7987 struct drm_device *dev = crtc->base.dev;
7988 struct drm_i915_private *dev_priv = dev->dev_private;
7989 const struct intel_limit *limit;
7990 int refclk = 96000;
7991
7992 memset(&crtc_state->dpll_hw_state, 0,
7993 sizeof(crtc_state->dpll_hw_state));
7994
7995 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7996 if (intel_panel_use_ssc(dev_priv)) {
7997 refclk = dev_priv->vbt.lvds_ssc_freq;
7998 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7999 }
8000
8001 limit = &intel_limits_pineview_lvds;
8002 } else {
8003 limit = &intel_limits_pineview_sdvo;
8004 }
8005
8006 if (!crtc_state->clock_set &&
8007 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8008 refclk, NULL, &crtc_state->dpll)) {
8009 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8010 return -EINVAL;
8011 }
8012
8013 i9xx_compute_dpll(crtc, crtc_state, NULL);
8014
8015 return 0;
8016 }
8017
8018 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8019 struct intel_crtc_state *crtc_state)
8020 {
8021 struct drm_device *dev = crtc->base.dev;
8022 struct drm_i915_private *dev_priv = dev->dev_private;
8023 const struct intel_limit *limit;
8024 int refclk = 96000;
8025
8026 memset(&crtc_state->dpll_hw_state, 0,
8027 sizeof(crtc_state->dpll_hw_state));
8028
8029 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8030 if (intel_panel_use_ssc(dev_priv)) {
8031 refclk = dev_priv->vbt.lvds_ssc_freq;
8032 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8033 }
8034
8035 limit = &intel_limits_i9xx_lvds;
8036 } else {
8037 limit = &intel_limits_i9xx_sdvo;
8038 }
8039
8040 if (!crtc_state->clock_set &&
8041 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8042 refclk, NULL, &crtc_state->dpll)) {
8043 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8044 return -EINVAL;
8045 }
8046
8047 i9xx_compute_dpll(crtc, crtc_state, NULL);
8048
8049 return 0;
8050 }
8051
8052 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8053 struct intel_crtc_state *crtc_state)
8054 {
8055 int refclk = 100000;
8056 const struct intel_limit *limit = &intel_limits_chv;
8057
8058 memset(&crtc_state->dpll_hw_state, 0,
8059 sizeof(crtc_state->dpll_hw_state));
8060
8061 if (!crtc_state->clock_set &&
8062 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8063 refclk, NULL, &crtc_state->dpll)) {
8064 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8065 return -EINVAL;
8066 }
8067
8068 chv_compute_dpll(crtc, crtc_state);
8069
8070 return 0;
8071 }
8072
8073 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8074 struct intel_crtc_state *crtc_state)
8075 {
8076 int refclk = 100000;
8077 const struct intel_limit *limit = &intel_limits_vlv;
8078
8079 memset(&crtc_state->dpll_hw_state, 0,
8080 sizeof(crtc_state->dpll_hw_state));
8081
8082 if (!crtc_state->clock_set &&
8083 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8084 refclk, NULL, &crtc_state->dpll)) {
8085 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8086 return -EINVAL;
8087 }
8088
8089 vlv_compute_dpll(crtc, crtc_state);
8090
8091 return 0;
8092 }
8093
8094 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8095 struct intel_crtc_state *pipe_config)
8096 {
8097 struct drm_device *dev = crtc->base.dev;
8098 struct drm_i915_private *dev_priv = dev->dev_private;
8099 uint32_t tmp;
8100
8101 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8102 return;
8103
8104 tmp = I915_READ(PFIT_CONTROL);
8105 if (!(tmp & PFIT_ENABLE))
8106 return;
8107
8108 /* Check whether the pfit is attached to our pipe. */
8109 if (INTEL_INFO(dev)->gen < 4) {
8110 if (crtc->pipe != PIPE_B)
8111 return;
8112 } else {
8113 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8114 return;
8115 }
8116
8117 pipe_config->gmch_pfit.control = tmp;
8118 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8119 }
8120
8121 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8122 struct intel_crtc_state *pipe_config)
8123 {
8124 struct drm_device *dev = crtc->base.dev;
8125 struct drm_i915_private *dev_priv = dev->dev_private;
8126 int pipe = pipe_config->cpu_transcoder;
8127 struct dpll clock;
8128 u32 mdiv;
8129 int refclk = 100000;
8130
8131 /* In case of DSI, DPLL will not be used */
8132 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8133 return;
8134
8135 mutex_lock(&dev_priv->sb_lock);
8136 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8137 mutex_unlock(&dev_priv->sb_lock);
8138
8139 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8140 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8141 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8142 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8143 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8144
8145 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8146 }
8147
8148 static void
8149 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8150 struct intel_initial_plane_config *plane_config)
8151 {
8152 struct drm_device *dev = crtc->base.dev;
8153 struct drm_i915_private *dev_priv = dev->dev_private;
8154 u32 val, base, offset;
8155 int pipe = crtc->pipe, plane = crtc->plane;
8156 int fourcc, pixel_format;
8157 unsigned int aligned_height;
8158 struct drm_framebuffer *fb;
8159 struct intel_framebuffer *intel_fb;
8160
8161 val = I915_READ(DSPCNTR(plane));
8162 if (!(val & DISPLAY_PLANE_ENABLE))
8163 return;
8164
8165 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8166 if (!intel_fb) {
8167 DRM_DEBUG_KMS("failed to alloc fb\n");
8168 return;
8169 }
8170
8171 fb = &intel_fb->base;
8172
8173 if (INTEL_INFO(dev)->gen >= 4) {
8174 if (val & DISPPLANE_TILED) {
8175 plane_config->tiling = I915_TILING_X;
8176 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8177 }
8178 }
8179
8180 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8181 fourcc = i9xx_format_to_fourcc(pixel_format);
8182 fb->pixel_format = fourcc;
8183 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8184
8185 if (INTEL_INFO(dev)->gen >= 4) {
8186 if (plane_config->tiling)
8187 offset = I915_READ(DSPTILEOFF(plane));
8188 else
8189 offset = I915_READ(DSPLINOFF(plane));
8190 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8191 } else {
8192 base = I915_READ(DSPADDR(plane));
8193 }
8194 plane_config->base = base;
8195
8196 val = I915_READ(PIPESRC(pipe));
8197 fb->width = ((val >> 16) & 0xfff) + 1;
8198 fb->height = ((val >> 0) & 0xfff) + 1;
8199
8200 val = I915_READ(DSPSTRIDE(pipe));
8201 fb->pitches[0] = val & 0xffffffc0;
8202
8203 aligned_height = intel_fb_align_height(dev, fb->height,
8204 fb->pixel_format,
8205 fb->modifier[0]);
8206
8207 plane_config->size = fb->pitches[0] * aligned_height;
8208
8209 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8210 pipe_name(pipe), plane, fb->width, fb->height,
8211 fb->bits_per_pixel, base, fb->pitches[0],
8212 plane_config->size);
8213
8214 plane_config->fb = intel_fb;
8215 }
8216
8217 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8218 struct intel_crtc_state *pipe_config)
8219 {
8220 struct drm_device *dev = crtc->base.dev;
8221 struct drm_i915_private *dev_priv = dev->dev_private;
8222 int pipe = pipe_config->cpu_transcoder;
8223 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8224 struct dpll clock;
8225 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8226 int refclk = 100000;
8227
8228 /* In case of DSI, DPLL will not be used */
8229 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8230 return;
8231
8232 mutex_lock(&dev_priv->sb_lock);
8233 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8234 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8235 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8236 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8237 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8238 mutex_unlock(&dev_priv->sb_lock);
8239
8240 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8241 clock.m2 = (pll_dw0 & 0xff) << 22;
8242 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8243 clock.m2 |= pll_dw2 & 0x3fffff;
8244 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8245 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8246 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8247
8248 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8249 }
8250
8251 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8252 struct intel_crtc_state *pipe_config)
8253 {
8254 struct drm_device *dev = crtc->base.dev;
8255 struct drm_i915_private *dev_priv = dev->dev_private;
8256 enum intel_display_power_domain power_domain;
8257 uint32_t tmp;
8258 bool ret;
8259
8260 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8261 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8262 return false;
8263
8264 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8265 pipe_config->shared_dpll = NULL;
8266
8267 ret = false;
8268
8269 tmp = I915_READ(PIPECONF(crtc->pipe));
8270 if (!(tmp & PIPECONF_ENABLE))
8271 goto out;
8272
8273 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8274 switch (tmp & PIPECONF_BPC_MASK) {
8275 case PIPECONF_6BPC:
8276 pipe_config->pipe_bpp = 18;
8277 break;
8278 case PIPECONF_8BPC:
8279 pipe_config->pipe_bpp = 24;
8280 break;
8281 case PIPECONF_10BPC:
8282 pipe_config->pipe_bpp = 30;
8283 break;
8284 default:
8285 break;
8286 }
8287 }
8288
8289 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8290 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8291 pipe_config->limited_color_range = true;
8292
8293 if (INTEL_INFO(dev)->gen < 4)
8294 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8295
8296 intel_get_pipe_timings(crtc, pipe_config);
8297 intel_get_pipe_src_size(crtc, pipe_config);
8298
8299 i9xx_get_pfit_config(crtc, pipe_config);
8300
8301 if (INTEL_INFO(dev)->gen >= 4) {
8302 /* No way to read it out on pipes B and C */
8303 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8304 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8305 else
8306 tmp = I915_READ(DPLL_MD(crtc->pipe));
8307 pipe_config->pixel_multiplier =
8308 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8309 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8310 pipe_config->dpll_hw_state.dpll_md = tmp;
8311 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8312 tmp = I915_READ(DPLL(crtc->pipe));
8313 pipe_config->pixel_multiplier =
8314 ((tmp & SDVO_MULTIPLIER_MASK)
8315 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8316 } else {
8317 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8318 * port and will be fixed up in the encoder->get_config
8319 * function. */
8320 pipe_config->pixel_multiplier = 1;
8321 }
8322 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8323 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8324 /*
8325 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8326 * on 830. Filter it out here so that we don't
8327 * report errors due to that.
8328 */
8329 if (IS_I830(dev))
8330 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8331
8332 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8333 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8334 } else {
8335 /* Mask out read-only status bits. */
8336 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8337 DPLL_PORTC_READY_MASK |
8338 DPLL_PORTB_READY_MASK);
8339 }
8340
8341 if (IS_CHERRYVIEW(dev))
8342 chv_crtc_clock_get(crtc, pipe_config);
8343 else if (IS_VALLEYVIEW(dev))
8344 vlv_crtc_clock_get(crtc, pipe_config);
8345 else
8346 i9xx_crtc_clock_get(crtc, pipe_config);
8347
8348 /*
8349 * Normally the dotclock is filled in by the encoder .get_config()
8350 * but in case the pipe is enabled w/o any ports we need a sane
8351 * default.
8352 */
8353 pipe_config->base.adjusted_mode.crtc_clock =
8354 pipe_config->port_clock / pipe_config->pixel_multiplier;
8355
8356 ret = true;
8357
8358 out:
8359 intel_display_power_put(dev_priv, power_domain);
8360
8361 return ret;
8362 }
8363
8364 static void ironlake_init_pch_refclk(struct drm_device *dev)
8365 {
8366 struct drm_i915_private *dev_priv = dev->dev_private;
8367 struct intel_encoder *encoder;
8368 u32 val, final;
8369 bool has_lvds = false;
8370 bool has_cpu_edp = false;
8371 bool has_panel = false;
8372 bool has_ck505 = false;
8373 bool can_ssc = false;
8374
8375 /* We need to take the global config into account */
8376 for_each_intel_encoder(dev, encoder) {
8377 switch (encoder->type) {
8378 case INTEL_OUTPUT_LVDS:
8379 has_panel = true;
8380 has_lvds = true;
8381 break;
8382 case INTEL_OUTPUT_EDP:
8383 has_panel = true;
8384 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8385 has_cpu_edp = true;
8386 break;
8387 default:
8388 break;
8389 }
8390 }
8391
8392 if (HAS_PCH_IBX(dev)) {
8393 has_ck505 = dev_priv->vbt.display_clock_mode;
8394 can_ssc = has_ck505;
8395 } else {
8396 has_ck505 = false;
8397 can_ssc = true;
8398 }
8399
8400 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8401 has_panel, has_lvds, has_ck505);
8402
8403 /* Ironlake: try to setup display ref clock before DPLL
8404 * enabling. This is only under driver's control after
8405 * PCH B stepping, previous chipset stepping should be
8406 * ignoring this setting.
8407 */
8408 val = I915_READ(PCH_DREF_CONTROL);
8409
8410 /* As we must carefully and slowly disable/enable each source in turn,
8411 * compute the final state we want first and check if we need to
8412 * make any changes at all.
8413 */
8414 final = val;
8415 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8416 if (has_ck505)
8417 final |= DREF_NONSPREAD_CK505_ENABLE;
8418 else
8419 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8420
8421 final &= ~DREF_SSC_SOURCE_MASK;
8422 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8423 final &= ~DREF_SSC1_ENABLE;
8424
8425 if (has_panel) {
8426 final |= DREF_SSC_SOURCE_ENABLE;
8427
8428 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8429 final |= DREF_SSC1_ENABLE;
8430
8431 if (has_cpu_edp) {
8432 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8433 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8434 else
8435 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8436 } else
8437 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8438 } else {
8439 final |= DREF_SSC_SOURCE_DISABLE;
8440 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8441 }
8442
8443 if (final == val)
8444 return;
8445
8446 /* Always enable nonspread source */
8447 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8448
8449 if (has_ck505)
8450 val |= DREF_NONSPREAD_CK505_ENABLE;
8451 else
8452 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8453
8454 if (has_panel) {
8455 val &= ~DREF_SSC_SOURCE_MASK;
8456 val |= DREF_SSC_SOURCE_ENABLE;
8457
8458 /* SSC must be turned on before enabling the CPU output */
8459 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8460 DRM_DEBUG_KMS("Using SSC on panel\n");
8461 val |= DREF_SSC1_ENABLE;
8462 } else
8463 val &= ~DREF_SSC1_ENABLE;
8464
8465 /* Get SSC going before enabling the outputs */
8466 I915_WRITE(PCH_DREF_CONTROL, val);
8467 POSTING_READ(PCH_DREF_CONTROL);
8468 udelay(200);
8469
8470 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8471
8472 /* Enable CPU source on CPU attached eDP */
8473 if (has_cpu_edp) {
8474 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8475 DRM_DEBUG_KMS("Using SSC on eDP\n");
8476 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8477 } else
8478 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8479 } else
8480 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8481
8482 I915_WRITE(PCH_DREF_CONTROL, val);
8483 POSTING_READ(PCH_DREF_CONTROL);
8484 udelay(200);
8485 } else {
8486 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8487
8488 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8489
8490 /* Turn off CPU output */
8491 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8492
8493 I915_WRITE(PCH_DREF_CONTROL, val);
8494 POSTING_READ(PCH_DREF_CONTROL);
8495 udelay(200);
8496
8497 /* Turn off the SSC source */
8498 val &= ~DREF_SSC_SOURCE_MASK;
8499 val |= DREF_SSC_SOURCE_DISABLE;
8500
8501 /* Turn off SSC1 */
8502 val &= ~DREF_SSC1_ENABLE;
8503
8504 I915_WRITE(PCH_DREF_CONTROL, val);
8505 POSTING_READ(PCH_DREF_CONTROL);
8506 udelay(200);
8507 }
8508
8509 BUG_ON(val != final);
8510 }
8511
8512 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8513 {
8514 uint32_t tmp;
8515
8516 tmp = I915_READ(SOUTH_CHICKEN2);
8517 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8518 I915_WRITE(SOUTH_CHICKEN2, tmp);
8519
8520 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8521 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8522 DRM_ERROR("FDI mPHY reset assert timeout\n");
8523
8524 tmp = I915_READ(SOUTH_CHICKEN2);
8525 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8526 I915_WRITE(SOUTH_CHICKEN2, tmp);
8527
8528 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8529 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8530 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8531 }
8532
8533 /* WaMPhyProgramming:hsw */
8534 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8535 {
8536 uint32_t tmp;
8537
8538 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8539 tmp &= ~(0xFF << 24);
8540 tmp |= (0x12 << 24);
8541 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8542
8543 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8544 tmp |= (1 << 11);
8545 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8546
8547 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8548 tmp |= (1 << 11);
8549 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8550
8551 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8552 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8553 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8554
8555 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8556 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8557 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8558
8559 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8560 tmp &= ~(7 << 13);
8561 tmp |= (5 << 13);
8562 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8563
8564 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8565 tmp &= ~(7 << 13);
8566 tmp |= (5 << 13);
8567 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8568
8569 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8570 tmp &= ~0xFF;
8571 tmp |= 0x1C;
8572 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8573
8574 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8575 tmp &= ~0xFF;
8576 tmp |= 0x1C;
8577 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8578
8579 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8580 tmp &= ~(0xFF << 16);
8581 tmp |= (0x1C << 16);
8582 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8583
8584 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8585 tmp &= ~(0xFF << 16);
8586 tmp |= (0x1C << 16);
8587 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8588
8589 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8590 tmp |= (1 << 27);
8591 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8592
8593 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8594 tmp |= (1 << 27);
8595 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8596
8597 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8598 tmp &= ~(0xF << 28);
8599 tmp |= (4 << 28);
8600 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8601
8602 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8603 tmp &= ~(0xF << 28);
8604 tmp |= (4 << 28);
8605 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8606 }
8607
8608 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8609 * Programming" based on the parameters passed:
8610 * - Sequence to enable CLKOUT_DP
8611 * - Sequence to enable CLKOUT_DP without spread
8612 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8613 */
8614 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8615 bool with_fdi)
8616 {
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8618 uint32_t reg, tmp;
8619
8620 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8621 with_spread = true;
8622 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8623 with_fdi = false;
8624
8625 mutex_lock(&dev_priv->sb_lock);
8626
8627 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8628 tmp &= ~SBI_SSCCTL_DISABLE;
8629 tmp |= SBI_SSCCTL_PATHALT;
8630 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8631
8632 udelay(24);
8633
8634 if (with_spread) {
8635 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8636 tmp &= ~SBI_SSCCTL_PATHALT;
8637 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8638
8639 if (with_fdi) {
8640 lpt_reset_fdi_mphy(dev_priv);
8641 lpt_program_fdi_mphy(dev_priv);
8642 }
8643 }
8644
8645 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8646 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8647 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8648 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8649
8650 mutex_unlock(&dev_priv->sb_lock);
8651 }
8652
8653 /* Sequence to disable CLKOUT_DP */
8654 static void lpt_disable_clkout_dp(struct drm_device *dev)
8655 {
8656 struct drm_i915_private *dev_priv = dev->dev_private;
8657 uint32_t reg, tmp;
8658
8659 mutex_lock(&dev_priv->sb_lock);
8660
8661 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8662 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8663 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8664 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8665
8666 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8667 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8668 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8669 tmp |= SBI_SSCCTL_PATHALT;
8670 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8671 udelay(32);
8672 }
8673 tmp |= SBI_SSCCTL_DISABLE;
8674 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8675 }
8676
8677 mutex_unlock(&dev_priv->sb_lock);
8678 }
8679
8680 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8681
8682 static const uint16_t sscdivintphase[] = {
8683 [BEND_IDX( 50)] = 0x3B23,
8684 [BEND_IDX( 45)] = 0x3B23,
8685 [BEND_IDX( 40)] = 0x3C23,
8686 [BEND_IDX( 35)] = 0x3C23,
8687 [BEND_IDX( 30)] = 0x3D23,
8688 [BEND_IDX( 25)] = 0x3D23,
8689 [BEND_IDX( 20)] = 0x3E23,
8690 [BEND_IDX( 15)] = 0x3E23,
8691 [BEND_IDX( 10)] = 0x3F23,
8692 [BEND_IDX( 5)] = 0x3F23,
8693 [BEND_IDX( 0)] = 0x0025,
8694 [BEND_IDX( -5)] = 0x0025,
8695 [BEND_IDX(-10)] = 0x0125,
8696 [BEND_IDX(-15)] = 0x0125,
8697 [BEND_IDX(-20)] = 0x0225,
8698 [BEND_IDX(-25)] = 0x0225,
8699 [BEND_IDX(-30)] = 0x0325,
8700 [BEND_IDX(-35)] = 0x0325,
8701 [BEND_IDX(-40)] = 0x0425,
8702 [BEND_IDX(-45)] = 0x0425,
8703 [BEND_IDX(-50)] = 0x0525,
8704 };
8705
8706 /*
8707 * Bend CLKOUT_DP
8708 * steps -50 to 50 inclusive, in steps of 5
8709 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8710 * change in clock period = -(steps / 10) * 5.787 ps
8711 */
8712 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8713 {
8714 uint32_t tmp;
8715 int idx = BEND_IDX(steps);
8716
8717 if (WARN_ON(steps % 5 != 0))
8718 return;
8719
8720 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8721 return;
8722
8723 mutex_lock(&dev_priv->sb_lock);
8724
8725 if (steps % 10 != 0)
8726 tmp = 0xAAAAAAAB;
8727 else
8728 tmp = 0x00000000;
8729 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8730
8731 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8732 tmp &= 0xffff0000;
8733 tmp |= sscdivintphase[idx];
8734 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8735
8736 mutex_unlock(&dev_priv->sb_lock);
8737 }
8738
8739 #undef BEND_IDX
8740
8741 static void lpt_init_pch_refclk(struct drm_device *dev)
8742 {
8743 struct intel_encoder *encoder;
8744 bool has_vga = false;
8745
8746 for_each_intel_encoder(dev, encoder) {
8747 switch (encoder->type) {
8748 case INTEL_OUTPUT_ANALOG:
8749 has_vga = true;
8750 break;
8751 default:
8752 break;
8753 }
8754 }
8755
8756 if (has_vga) {
8757 lpt_bend_clkout_dp(to_i915(dev), 0);
8758 lpt_enable_clkout_dp(dev, true, true);
8759 } else {
8760 lpt_disable_clkout_dp(dev);
8761 }
8762 }
8763
8764 /*
8765 * Initialize reference clocks when the driver loads
8766 */
8767 void intel_init_pch_refclk(struct drm_device *dev)
8768 {
8769 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8770 ironlake_init_pch_refclk(dev);
8771 else if (HAS_PCH_LPT(dev))
8772 lpt_init_pch_refclk(dev);
8773 }
8774
8775 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8776 {
8777 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8779 int pipe = intel_crtc->pipe;
8780 uint32_t val;
8781
8782 val = 0;
8783
8784 switch (intel_crtc->config->pipe_bpp) {
8785 case 18:
8786 val |= PIPECONF_6BPC;
8787 break;
8788 case 24:
8789 val |= PIPECONF_8BPC;
8790 break;
8791 case 30:
8792 val |= PIPECONF_10BPC;
8793 break;
8794 case 36:
8795 val |= PIPECONF_12BPC;
8796 break;
8797 default:
8798 /* Case prevented by intel_choose_pipe_bpp_dither. */
8799 BUG();
8800 }
8801
8802 if (intel_crtc->config->dither)
8803 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8804
8805 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8806 val |= PIPECONF_INTERLACED_ILK;
8807 else
8808 val |= PIPECONF_PROGRESSIVE;
8809
8810 if (intel_crtc->config->limited_color_range)
8811 val |= PIPECONF_COLOR_RANGE_SELECT;
8812
8813 I915_WRITE(PIPECONF(pipe), val);
8814 POSTING_READ(PIPECONF(pipe));
8815 }
8816
8817 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8818 {
8819 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8821 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8822 u32 val = 0;
8823
8824 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8825 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8826
8827 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8828 val |= PIPECONF_INTERLACED_ILK;
8829 else
8830 val |= PIPECONF_PROGRESSIVE;
8831
8832 I915_WRITE(PIPECONF(cpu_transcoder), val);
8833 POSTING_READ(PIPECONF(cpu_transcoder));
8834 }
8835
8836 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8837 {
8838 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8840
8841 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8842 u32 val = 0;
8843
8844 switch (intel_crtc->config->pipe_bpp) {
8845 case 18:
8846 val |= PIPEMISC_DITHER_6_BPC;
8847 break;
8848 case 24:
8849 val |= PIPEMISC_DITHER_8_BPC;
8850 break;
8851 case 30:
8852 val |= PIPEMISC_DITHER_10_BPC;
8853 break;
8854 case 36:
8855 val |= PIPEMISC_DITHER_12_BPC;
8856 break;
8857 default:
8858 /* Case prevented by pipe_config_set_bpp. */
8859 BUG();
8860 }
8861
8862 if (intel_crtc->config->dither)
8863 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8864
8865 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8866 }
8867 }
8868
8869 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8870 {
8871 /*
8872 * Account for spread spectrum to avoid
8873 * oversubscribing the link. Max center spread
8874 * is 2.5%; use 5% for safety's sake.
8875 */
8876 u32 bps = target_clock * bpp * 21 / 20;
8877 return DIV_ROUND_UP(bps, link_bw * 8);
8878 }
8879
8880 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8881 {
8882 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8883 }
8884
8885 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8886 struct intel_crtc_state *crtc_state,
8887 struct dpll *reduced_clock)
8888 {
8889 struct drm_crtc *crtc = &intel_crtc->base;
8890 struct drm_device *dev = crtc->dev;
8891 struct drm_i915_private *dev_priv = dev->dev_private;
8892 struct drm_atomic_state *state = crtc_state->base.state;
8893 struct drm_connector *connector;
8894 struct drm_connector_state *connector_state;
8895 struct intel_encoder *encoder;
8896 u32 dpll, fp, fp2;
8897 int factor, i;
8898 bool is_lvds = false, is_sdvo = false;
8899
8900 for_each_connector_in_state(state, connector, connector_state, i) {
8901 if (connector_state->crtc != crtc_state->base.crtc)
8902 continue;
8903
8904 encoder = to_intel_encoder(connector_state->best_encoder);
8905
8906 switch (encoder->type) {
8907 case INTEL_OUTPUT_LVDS:
8908 is_lvds = true;
8909 break;
8910 case INTEL_OUTPUT_SDVO:
8911 case INTEL_OUTPUT_HDMI:
8912 is_sdvo = true;
8913 break;
8914 default:
8915 break;
8916 }
8917 }
8918
8919 /* Enable autotuning of the PLL clock (if permissible) */
8920 factor = 21;
8921 if (is_lvds) {
8922 if ((intel_panel_use_ssc(dev_priv) &&
8923 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8924 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8925 factor = 25;
8926 } else if (crtc_state->sdvo_tv_clock)
8927 factor = 20;
8928
8929 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8930
8931 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8932 fp |= FP_CB_TUNE;
8933
8934 if (reduced_clock) {
8935 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8936
8937 if (reduced_clock->m < factor * reduced_clock->n)
8938 fp2 |= FP_CB_TUNE;
8939 } else {
8940 fp2 = fp;
8941 }
8942
8943 dpll = 0;
8944
8945 if (is_lvds)
8946 dpll |= DPLLB_MODE_LVDS;
8947 else
8948 dpll |= DPLLB_MODE_DAC_SERIAL;
8949
8950 dpll |= (crtc_state->pixel_multiplier - 1)
8951 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8952
8953 if (is_sdvo)
8954 dpll |= DPLL_SDVO_HIGH_SPEED;
8955 if (crtc_state->has_dp_encoder)
8956 dpll |= DPLL_SDVO_HIGH_SPEED;
8957
8958 /* compute bitmask from p1 value */
8959 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8960 /* also FPA1 */
8961 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8962
8963 switch (crtc_state->dpll.p2) {
8964 case 5:
8965 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8966 break;
8967 case 7:
8968 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8969 break;
8970 case 10:
8971 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8972 break;
8973 case 14:
8974 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8975 break;
8976 }
8977
8978 if (is_lvds && intel_panel_use_ssc(dev_priv))
8979 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8980 else
8981 dpll |= PLL_REF_INPUT_DREFCLK;
8982
8983 dpll |= DPLL_VCO_ENABLE;
8984
8985 crtc_state->dpll_hw_state.dpll = dpll;
8986 crtc_state->dpll_hw_state.fp0 = fp;
8987 crtc_state->dpll_hw_state.fp1 = fp2;
8988 }
8989
8990 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8991 struct intel_crtc_state *crtc_state)
8992 {
8993 struct drm_device *dev = crtc->base.dev;
8994 struct drm_i915_private *dev_priv = dev->dev_private;
8995 struct dpll reduced_clock;
8996 bool has_reduced_clock = false;
8997 struct intel_shared_dpll *pll;
8998 const struct intel_limit *limit;
8999 int refclk = 120000;
9000
9001 memset(&crtc_state->dpll_hw_state, 0,
9002 sizeof(crtc_state->dpll_hw_state));
9003
9004 crtc->lowfreq_avail = false;
9005
9006 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9007 if (!crtc_state->has_pch_encoder)
9008 return 0;
9009
9010 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9011 if (intel_panel_use_ssc(dev_priv)) {
9012 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9013 dev_priv->vbt.lvds_ssc_freq);
9014 refclk = dev_priv->vbt.lvds_ssc_freq;
9015 }
9016
9017 if (intel_is_dual_link_lvds(dev)) {
9018 if (refclk == 100000)
9019 limit = &intel_limits_ironlake_dual_lvds_100m;
9020 else
9021 limit = &intel_limits_ironlake_dual_lvds;
9022 } else {
9023 if (refclk == 100000)
9024 limit = &intel_limits_ironlake_single_lvds_100m;
9025 else
9026 limit = &intel_limits_ironlake_single_lvds;
9027 }
9028 } else {
9029 limit = &intel_limits_ironlake_dac;
9030 }
9031
9032 if (!crtc_state->clock_set &&
9033 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9034 refclk, NULL, &crtc_state->dpll)) {
9035 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9036 return -EINVAL;
9037 }
9038
9039 ironlake_compute_dpll(crtc, crtc_state,
9040 has_reduced_clock ? &reduced_clock : NULL);
9041
9042 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9043 if (pll == NULL) {
9044 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9045 pipe_name(crtc->pipe));
9046 return -EINVAL;
9047 }
9048
9049 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9050 has_reduced_clock)
9051 crtc->lowfreq_avail = true;
9052
9053 return 0;
9054 }
9055
9056 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9057 struct intel_link_m_n *m_n)
9058 {
9059 struct drm_device *dev = crtc->base.dev;
9060 struct drm_i915_private *dev_priv = dev->dev_private;
9061 enum pipe pipe = crtc->pipe;
9062
9063 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9064 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9065 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9066 & ~TU_SIZE_MASK;
9067 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9068 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9069 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9070 }
9071
9072 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9073 enum transcoder transcoder,
9074 struct intel_link_m_n *m_n,
9075 struct intel_link_m_n *m2_n2)
9076 {
9077 struct drm_device *dev = crtc->base.dev;
9078 struct drm_i915_private *dev_priv = dev->dev_private;
9079 enum pipe pipe = crtc->pipe;
9080
9081 if (INTEL_INFO(dev)->gen >= 5) {
9082 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9083 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9084 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9085 & ~TU_SIZE_MASK;
9086 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9087 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9088 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9089 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9090 * gen < 8) and if DRRS is supported (to make sure the
9091 * registers are not unnecessarily read).
9092 */
9093 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9094 crtc->config->has_drrs) {
9095 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9096 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9097 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9098 & ~TU_SIZE_MASK;
9099 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9100 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9101 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9102 }
9103 } else {
9104 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9105 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9106 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9107 & ~TU_SIZE_MASK;
9108 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9109 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9110 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9111 }
9112 }
9113
9114 void intel_dp_get_m_n(struct intel_crtc *crtc,
9115 struct intel_crtc_state *pipe_config)
9116 {
9117 if (pipe_config->has_pch_encoder)
9118 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9119 else
9120 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9121 &pipe_config->dp_m_n,
9122 &pipe_config->dp_m2_n2);
9123 }
9124
9125 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9126 struct intel_crtc_state *pipe_config)
9127 {
9128 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9129 &pipe_config->fdi_m_n, NULL);
9130 }
9131
9132 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9133 struct intel_crtc_state *pipe_config)
9134 {
9135 struct drm_device *dev = crtc->base.dev;
9136 struct drm_i915_private *dev_priv = dev->dev_private;
9137 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9138 uint32_t ps_ctrl = 0;
9139 int id = -1;
9140 int i;
9141
9142 /* find scaler attached to this pipe */
9143 for (i = 0; i < crtc->num_scalers; i++) {
9144 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9145 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9146 id = i;
9147 pipe_config->pch_pfit.enabled = true;
9148 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9149 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9150 break;
9151 }
9152 }
9153
9154 scaler_state->scaler_id = id;
9155 if (id >= 0) {
9156 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9157 } else {
9158 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9159 }
9160 }
9161
9162 static void
9163 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9164 struct intel_initial_plane_config *plane_config)
9165 {
9166 struct drm_device *dev = crtc->base.dev;
9167 struct drm_i915_private *dev_priv = dev->dev_private;
9168 u32 val, base, offset, stride_mult, tiling;
9169 int pipe = crtc->pipe;
9170 int fourcc, pixel_format;
9171 unsigned int aligned_height;
9172 struct drm_framebuffer *fb;
9173 struct intel_framebuffer *intel_fb;
9174
9175 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9176 if (!intel_fb) {
9177 DRM_DEBUG_KMS("failed to alloc fb\n");
9178 return;
9179 }
9180
9181 fb = &intel_fb->base;
9182
9183 val = I915_READ(PLANE_CTL(pipe, 0));
9184 if (!(val & PLANE_CTL_ENABLE))
9185 goto error;
9186
9187 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9188 fourcc = skl_format_to_fourcc(pixel_format,
9189 val & PLANE_CTL_ORDER_RGBX,
9190 val & PLANE_CTL_ALPHA_MASK);
9191 fb->pixel_format = fourcc;
9192 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9193
9194 tiling = val & PLANE_CTL_TILED_MASK;
9195 switch (tiling) {
9196 case PLANE_CTL_TILED_LINEAR:
9197 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9198 break;
9199 case PLANE_CTL_TILED_X:
9200 plane_config->tiling = I915_TILING_X;
9201 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9202 break;
9203 case PLANE_CTL_TILED_Y:
9204 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9205 break;
9206 case PLANE_CTL_TILED_YF:
9207 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9208 break;
9209 default:
9210 MISSING_CASE(tiling);
9211 goto error;
9212 }
9213
9214 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9215 plane_config->base = base;
9216
9217 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9218
9219 val = I915_READ(PLANE_SIZE(pipe, 0));
9220 fb->height = ((val >> 16) & 0xfff) + 1;
9221 fb->width = ((val >> 0) & 0x1fff) + 1;
9222
9223 val = I915_READ(PLANE_STRIDE(pipe, 0));
9224 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9225 fb->pixel_format);
9226 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9227
9228 aligned_height = intel_fb_align_height(dev, fb->height,
9229 fb->pixel_format,
9230 fb->modifier[0]);
9231
9232 plane_config->size = fb->pitches[0] * aligned_height;
9233
9234 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9235 pipe_name(pipe), fb->width, fb->height,
9236 fb->bits_per_pixel, base, fb->pitches[0],
9237 plane_config->size);
9238
9239 plane_config->fb = intel_fb;
9240 return;
9241
9242 error:
9243 kfree(fb);
9244 }
9245
9246 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9247 struct intel_crtc_state *pipe_config)
9248 {
9249 struct drm_device *dev = crtc->base.dev;
9250 struct drm_i915_private *dev_priv = dev->dev_private;
9251 uint32_t tmp;
9252
9253 tmp = I915_READ(PF_CTL(crtc->pipe));
9254
9255 if (tmp & PF_ENABLE) {
9256 pipe_config->pch_pfit.enabled = true;
9257 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9258 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9259
9260 /* We currently do not free assignements of panel fitters on
9261 * ivb/hsw (since we don't use the higher upscaling modes which
9262 * differentiates them) so just WARN about this case for now. */
9263 if (IS_GEN7(dev)) {
9264 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9265 PF_PIPE_SEL_IVB(crtc->pipe));
9266 }
9267 }
9268 }
9269
9270 static void
9271 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9272 struct intel_initial_plane_config *plane_config)
9273 {
9274 struct drm_device *dev = crtc->base.dev;
9275 struct drm_i915_private *dev_priv = dev->dev_private;
9276 u32 val, base, offset;
9277 int pipe = crtc->pipe;
9278 int fourcc, pixel_format;
9279 unsigned int aligned_height;
9280 struct drm_framebuffer *fb;
9281 struct intel_framebuffer *intel_fb;
9282
9283 val = I915_READ(DSPCNTR(pipe));
9284 if (!(val & DISPLAY_PLANE_ENABLE))
9285 return;
9286
9287 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9288 if (!intel_fb) {
9289 DRM_DEBUG_KMS("failed to alloc fb\n");
9290 return;
9291 }
9292
9293 fb = &intel_fb->base;
9294
9295 if (INTEL_INFO(dev)->gen >= 4) {
9296 if (val & DISPPLANE_TILED) {
9297 plane_config->tiling = I915_TILING_X;
9298 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9299 }
9300 }
9301
9302 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9303 fourcc = i9xx_format_to_fourcc(pixel_format);
9304 fb->pixel_format = fourcc;
9305 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9306
9307 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9308 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9309 offset = I915_READ(DSPOFFSET(pipe));
9310 } else {
9311 if (plane_config->tiling)
9312 offset = I915_READ(DSPTILEOFF(pipe));
9313 else
9314 offset = I915_READ(DSPLINOFF(pipe));
9315 }
9316 plane_config->base = base;
9317
9318 val = I915_READ(PIPESRC(pipe));
9319 fb->width = ((val >> 16) & 0xfff) + 1;
9320 fb->height = ((val >> 0) & 0xfff) + 1;
9321
9322 val = I915_READ(DSPSTRIDE(pipe));
9323 fb->pitches[0] = val & 0xffffffc0;
9324
9325 aligned_height = intel_fb_align_height(dev, fb->height,
9326 fb->pixel_format,
9327 fb->modifier[0]);
9328
9329 plane_config->size = fb->pitches[0] * aligned_height;
9330
9331 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9332 pipe_name(pipe), fb->width, fb->height,
9333 fb->bits_per_pixel, base, fb->pitches[0],
9334 plane_config->size);
9335
9336 plane_config->fb = intel_fb;
9337 }
9338
9339 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9340 struct intel_crtc_state *pipe_config)
9341 {
9342 struct drm_device *dev = crtc->base.dev;
9343 struct drm_i915_private *dev_priv = dev->dev_private;
9344 enum intel_display_power_domain power_domain;
9345 uint32_t tmp;
9346 bool ret;
9347
9348 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9349 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9350 return false;
9351
9352 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9353 pipe_config->shared_dpll = NULL;
9354
9355 ret = false;
9356 tmp = I915_READ(PIPECONF(crtc->pipe));
9357 if (!(tmp & PIPECONF_ENABLE))
9358 goto out;
9359
9360 switch (tmp & PIPECONF_BPC_MASK) {
9361 case PIPECONF_6BPC:
9362 pipe_config->pipe_bpp = 18;
9363 break;
9364 case PIPECONF_8BPC:
9365 pipe_config->pipe_bpp = 24;
9366 break;
9367 case PIPECONF_10BPC:
9368 pipe_config->pipe_bpp = 30;
9369 break;
9370 case PIPECONF_12BPC:
9371 pipe_config->pipe_bpp = 36;
9372 break;
9373 default:
9374 break;
9375 }
9376
9377 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9378 pipe_config->limited_color_range = true;
9379
9380 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9381 struct intel_shared_dpll *pll;
9382 enum intel_dpll_id pll_id;
9383
9384 pipe_config->has_pch_encoder = true;
9385
9386 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9387 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9388 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9389
9390 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9391
9392 if (HAS_PCH_IBX(dev_priv)) {
9393 /*
9394 * The pipe->pch transcoder and pch transcoder->pll
9395 * mapping is fixed.
9396 */
9397 pll_id = (enum intel_dpll_id) crtc->pipe;
9398 } else {
9399 tmp = I915_READ(PCH_DPLL_SEL);
9400 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9401 pll_id = DPLL_ID_PCH_PLL_B;
9402 else
9403 pll_id= DPLL_ID_PCH_PLL_A;
9404 }
9405
9406 pipe_config->shared_dpll =
9407 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9408 pll = pipe_config->shared_dpll;
9409
9410 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9411 &pipe_config->dpll_hw_state));
9412
9413 tmp = pipe_config->dpll_hw_state.dpll;
9414 pipe_config->pixel_multiplier =
9415 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9416 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9417
9418 ironlake_pch_clock_get(crtc, pipe_config);
9419 } else {
9420 pipe_config->pixel_multiplier = 1;
9421 }
9422
9423 intel_get_pipe_timings(crtc, pipe_config);
9424 intel_get_pipe_src_size(crtc, pipe_config);
9425
9426 ironlake_get_pfit_config(crtc, pipe_config);
9427
9428 ret = true;
9429
9430 out:
9431 intel_display_power_put(dev_priv, power_domain);
9432
9433 return ret;
9434 }
9435
9436 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9437 {
9438 struct drm_device *dev = dev_priv->dev;
9439 struct intel_crtc *crtc;
9440
9441 for_each_intel_crtc(dev, crtc)
9442 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9443 pipe_name(crtc->pipe));
9444
9445 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9446 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9447 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9448 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9449 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9450 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9451 "CPU PWM1 enabled\n");
9452 if (IS_HASWELL(dev))
9453 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9454 "CPU PWM2 enabled\n");
9455 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9456 "PCH PWM1 enabled\n");
9457 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9458 "Utility pin enabled\n");
9459 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9460
9461 /*
9462 * In theory we can still leave IRQs enabled, as long as only the HPD
9463 * interrupts remain enabled. We used to check for that, but since it's
9464 * gen-specific and since we only disable LCPLL after we fully disable
9465 * the interrupts, the check below should be enough.
9466 */
9467 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9468 }
9469
9470 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9471 {
9472 struct drm_device *dev = dev_priv->dev;
9473
9474 if (IS_HASWELL(dev))
9475 return I915_READ(D_COMP_HSW);
9476 else
9477 return I915_READ(D_COMP_BDW);
9478 }
9479
9480 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9481 {
9482 struct drm_device *dev = dev_priv->dev;
9483
9484 if (IS_HASWELL(dev)) {
9485 mutex_lock(&dev_priv->rps.hw_lock);
9486 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9487 val))
9488 DRM_ERROR("Failed to write to D_COMP\n");
9489 mutex_unlock(&dev_priv->rps.hw_lock);
9490 } else {
9491 I915_WRITE(D_COMP_BDW, val);
9492 POSTING_READ(D_COMP_BDW);
9493 }
9494 }
9495
9496 /*
9497 * This function implements pieces of two sequences from BSpec:
9498 * - Sequence for display software to disable LCPLL
9499 * - Sequence for display software to allow package C8+
9500 * The steps implemented here are just the steps that actually touch the LCPLL
9501 * register. Callers should take care of disabling all the display engine
9502 * functions, doing the mode unset, fixing interrupts, etc.
9503 */
9504 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9505 bool switch_to_fclk, bool allow_power_down)
9506 {
9507 uint32_t val;
9508
9509 assert_can_disable_lcpll(dev_priv);
9510
9511 val = I915_READ(LCPLL_CTL);
9512
9513 if (switch_to_fclk) {
9514 val |= LCPLL_CD_SOURCE_FCLK;
9515 I915_WRITE(LCPLL_CTL, val);
9516
9517 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9518 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9519 DRM_ERROR("Switching to FCLK failed\n");
9520
9521 val = I915_READ(LCPLL_CTL);
9522 }
9523
9524 val |= LCPLL_PLL_DISABLE;
9525 I915_WRITE(LCPLL_CTL, val);
9526 POSTING_READ(LCPLL_CTL);
9527
9528 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9529 DRM_ERROR("LCPLL still locked\n");
9530
9531 val = hsw_read_dcomp(dev_priv);
9532 val |= D_COMP_COMP_DISABLE;
9533 hsw_write_dcomp(dev_priv, val);
9534 ndelay(100);
9535
9536 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9537 1))
9538 DRM_ERROR("D_COMP RCOMP still in progress\n");
9539
9540 if (allow_power_down) {
9541 val = I915_READ(LCPLL_CTL);
9542 val |= LCPLL_POWER_DOWN_ALLOW;
9543 I915_WRITE(LCPLL_CTL, val);
9544 POSTING_READ(LCPLL_CTL);
9545 }
9546 }
9547
9548 /*
9549 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9550 * source.
9551 */
9552 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9553 {
9554 uint32_t val;
9555
9556 val = I915_READ(LCPLL_CTL);
9557
9558 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9559 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9560 return;
9561
9562 /*
9563 * Make sure we're not on PC8 state before disabling PC8, otherwise
9564 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9565 */
9566 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9567
9568 if (val & LCPLL_POWER_DOWN_ALLOW) {
9569 val &= ~LCPLL_POWER_DOWN_ALLOW;
9570 I915_WRITE(LCPLL_CTL, val);
9571 POSTING_READ(LCPLL_CTL);
9572 }
9573
9574 val = hsw_read_dcomp(dev_priv);
9575 val |= D_COMP_COMP_FORCE;
9576 val &= ~D_COMP_COMP_DISABLE;
9577 hsw_write_dcomp(dev_priv, val);
9578
9579 val = I915_READ(LCPLL_CTL);
9580 val &= ~LCPLL_PLL_DISABLE;
9581 I915_WRITE(LCPLL_CTL, val);
9582
9583 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9584 DRM_ERROR("LCPLL not locked yet\n");
9585
9586 if (val & LCPLL_CD_SOURCE_FCLK) {
9587 val = I915_READ(LCPLL_CTL);
9588 val &= ~LCPLL_CD_SOURCE_FCLK;
9589 I915_WRITE(LCPLL_CTL, val);
9590
9591 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9592 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9593 DRM_ERROR("Switching back to LCPLL failed\n");
9594 }
9595
9596 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9597 intel_update_cdclk(dev_priv->dev);
9598 }
9599
9600 /*
9601 * Package states C8 and deeper are really deep PC states that can only be
9602 * reached when all the devices on the system allow it, so even if the graphics
9603 * device allows PC8+, it doesn't mean the system will actually get to these
9604 * states. Our driver only allows PC8+ when going into runtime PM.
9605 *
9606 * The requirements for PC8+ are that all the outputs are disabled, the power
9607 * well is disabled and most interrupts are disabled, and these are also
9608 * requirements for runtime PM. When these conditions are met, we manually do
9609 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9610 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9611 * hang the machine.
9612 *
9613 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9614 * the state of some registers, so when we come back from PC8+ we need to
9615 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9616 * need to take care of the registers kept by RC6. Notice that this happens even
9617 * if we don't put the device in PCI D3 state (which is what currently happens
9618 * because of the runtime PM support).
9619 *
9620 * For more, read "Display Sequences for Package C8" on the hardware
9621 * documentation.
9622 */
9623 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9624 {
9625 struct drm_device *dev = dev_priv->dev;
9626 uint32_t val;
9627
9628 DRM_DEBUG_KMS("Enabling package C8+\n");
9629
9630 if (HAS_PCH_LPT_LP(dev)) {
9631 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9632 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9633 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9634 }
9635
9636 lpt_disable_clkout_dp(dev);
9637 hsw_disable_lcpll(dev_priv, true, true);
9638 }
9639
9640 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9641 {
9642 struct drm_device *dev = dev_priv->dev;
9643 uint32_t val;
9644
9645 DRM_DEBUG_KMS("Disabling package C8+\n");
9646
9647 hsw_restore_lcpll(dev_priv);
9648 lpt_init_pch_refclk(dev);
9649
9650 if (HAS_PCH_LPT_LP(dev)) {
9651 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9652 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9653 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9654 }
9655 }
9656
9657 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9658 {
9659 struct drm_device *dev = old_state->dev;
9660 struct intel_atomic_state *old_intel_state =
9661 to_intel_atomic_state(old_state);
9662 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9663
9664 bxt_set_cdclk(to_i915(dev), req_cdclk);
9665 }
9666
9667 /* compute the max rate for new configuration */
9668 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9669 {
9670 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9671 struct drm_i915_private *dev_priv = state->dev->dev_private;
9672 struct drm_crtc *crtc;
9673 struct drm_crtc_state *cstate;
9674 struct intel_crtc_state *crtc_state;
9675 unsigned max_pixel_rate = 0, i;
9676 enum pipe pipe;
9677
9678 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9679 sizeof(intel_state->min_pixclk));
9680
9681 for_each_crtc_in_state(state, crtc, cstate, i) {
9682 int pixel_rate;
9683
9684 crtc_state = to_intel_crtc_state(cstate);
9685 if (!crtc_state->base.enable) {
9686 intel_state->min_pixclk[i] = 0;
9687 continue;
9688 }
9689
9690 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9691
9692 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9693 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9694 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9695
9696 intel_state->min_pixclk[i] = pixel_rate;
9697 }
9698
9699 for_each_pipe(dev_priv, pipe)
9700 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9701
9702 return max_pixel_rate;
9703 }
9704
9705 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9706 {
9707 struct drm_i915_private *dev_priv = dev->dev_private;
9708 uint32_t val, data;
9709 int ret;
9710
9711 if (WARN((I915_READ(LCPLL_CTL) &
9712 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9713 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9714 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9715 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9716 "trying to change cdclk frequency with cdclk not enabled\n"))
9717 return;
9718
9719 mutex_lock(&dev_priv->rps.hw_lock);
9720 ret = sandybridge_pcode_write(dev_priv,
9721 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9722 mutex_unlock(&dev_priv->rps.hw_lock);
9723 if (ret) {
9724 DRM_ERROR("failed to inform pcode about cdclk change\n");
9725 return;
9726 }
9727
9728 val = I915_READ(LCPLL_CTL);
9729 val |= LCPLL_CD_SOURCE_FCLK;
9730 I915_WRITE(LCPLL_CTL, val);
9731
9732 if (wait_for_us(I915_READ(LCPLL_CTL) &
9733 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9734 DRM_ERROR("Switching to FCLK failed\n");
9735
9736 val = I915_READ(LCPLL_CTL);
9737 val &= ~LCPLL_CLK_FREQ_MASK;
9738
9739 switch (cdclk) {
9740 case 450000:
9741 val |= LCPLL_CLK_FREQ_450;
9742 data = 0;
9743 break;
9744 case 540000:
9745 val |= LCPLL_CLK_FREQ_54O_BDW;
9746 data = 1;
9747 break;
9748 case 337500:
9749 val |= LCPLL_CLK_FREQ_337_5_BDW;
9750 data = 2;
9751 break;
9752 case 675000:
9753 val |= LCPLL_CLK_FREQ_675_BDW;
9754 data = 3;
9755 break;
9756 default:
9757 WARN(1, "invalid cdclk frequency\n");
9758 return;
9759 }
9760
9761 I915_WRITE(LCPLL_CTL, val);
9762
9763 val = I915_READ(LCPLL_CTL);
9764 val &= ~LCPLL_CD_SOURCE_FCLK;
9765 I915_WRITE(LCPLL_CTL, val);
9766
9767 if (wait_for_us((I915_READ(LCPLL_CTL) &
9768 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9769 DRM_ERROR("Switching back to LCPLL failed\n");
9770
9771 mutex_lock(&dev_priv->rps.hw_lock);
9772 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9773 mutex_unlock(&dev_priv->rps.hw_lock);
9774
9775 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9776
9777 intel_update_cdclk(dev);
9778
9779 WARN(cdclk != dev_priv->cdclk_freq,
9780 "cdclk requested %d kHz but got %d kHz\n",
9781 cdclk, dev_priv->cdclk_freq);
9782 }
9783
9784 static int broadwell_calc_cdclk(int max_pixclk)
9785 {
9786 if (max_pixclk > 540000)
9787 return 675000;
9788 else if (max_pixclk > 450000)
9789 return 540000;
9790 else if (max_pixclk > 337500)
9791 return 450000;
9792 else
9793 return 337500;
9794 }
9795
9796 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9797 {
9798 struct drm_i915_private *dev_priv = to_i915(state->dev);
9799 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9800 int max_pixclk = ilk_max_pixel_rate(state);
9801 int cdclk;
9802
9803 /*
9804 * FIXME should also account for plane ratio
9805 * once 64bpp pixel formats are supported.
9806 */
9807 cdclk = broadwell_calc_cdclk(max_pixclk);
9808
9809 if (cdclk > dev_priv->max_cdclk_freq) {
9810 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9811 cdclk, dev_priv->max_cdclk_freq);
9812 return -EINVAL;
9813 }
9814
9815 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9816 if (!intel_state->active_crtcs)
9817 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9818
9819 return 0;
9820 }
9821
9822 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9823 {
9824 struct drm_device *dev = old_state->dev;
9825 struct intel_atomic_state *old_intel_state =
9826 to_intel_atomic_state(old_state);
9827 unsigned req_cdclk = old_intel_state->dev_cdclk;
9828
9829 broadwell_set_cdclk(dev, req_cdclk);
9830 }
9831
9832 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9833 {
9834 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9835 struct drm_i915_private *dev_priv = to_i915(state->dev);
9836 const int max_pixclk = ilk_max_pixel_rate(state);
9837 int vco = intel_state->cdclk_pll_vco;
9838 int cdclk;
9839
9840 /*
9841 * FIXME should also account for plane ratio
9842 * once 64bpp pixel formats are supported.
9843 */
9844 cdclk = skl_calc_cdclk(max_pixclk, vco);
9845
9846 /*
9847 * FIXME move the cdclk caclulation to
9848 * compute_config() so we can fail gracegully.
9849 */
9850 if (cdclk > dev_priv->max_cdclk_freq) {
9851 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9852 cdclk, dev_priv->max_cdclk_freq);
9853 cdclk = dev_priv->max_cdclk_freq;
9854 }
9855
9856 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9857 if (!intel_state->active_crtcs)
9858 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9859
9860 return 0;
9861 }
9862
9863 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9864 {
9865 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9866 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9867 unsigned int req_cdclk = intel_state->dev_cdclk;
9868 unsigned int req_vco = intel_state->cdclk_pll_vco;
9869
9870 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9871 }
9872
9873 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9874 struct intel_crtc_state *crtc_state)
9875 {
9876 struct intel_encoder *intel_encoder =
9877 intel_ddi_get_crtc_new_encoder(crtc_state);
9878
9879 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9880 if (!intel_ddi_pll_select(crtc, crtc_state))
9881 return -EINVAL;
9882 }
9883
9884 crtc->lowfreq_avail = false;
9885
9886 return 0;
9887 }
9888
9889 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9890 enum port port,
9891 struct intel_crtc_state *pipe_config)
9892 {
9893 enum intel_dpll_id id;
9894
9895 switch (port) {
9896 case PORT_A:
9897 pipe_config->ddi_pll_sel = SKL_DPLL0;
9898 id = DPLL_ID_SKL_DPLL0;
9899 break;
9900 case PORT_B:
9901 pipe_config->ddi_pll_sel = SKL_DPLL1;
9902 id = DPLL_ID_SKL_DPLL1;
9903 break;
9904 case PORT_C:
9905 pipe_config->ddi_pll_sel = SKL_DPLL2;
9906 id = DPLL_ID_SKL_DPLL2;
9907 break;
9908 default:
9909 DRM_ERROR("Incorrect port type\n");
9910 return;
9911 }
9912
9913 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9914 }
9915
9916 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9917 enum port port,
9918 struct intel_crtc_state *pipe_config)
9919 {
9920 enum intel_dpll_id id;
9921 u32 temp;
9922
9923 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9924 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9925
9926 switch (pipe_config->ddi_pll_sel) {
9927 case SKL_DPLL0:
9928 id = DPLL_ID_SKL_DPLL0;
9929 break;
9930 case SKL_DPLL1:
9931 id = DPLL_ID_SKL_DPLL1;
9932 break;
9933 case SKL_DPLL2:
9934 id = DPLL_ID_SKL_DPLL2;
9935 break;
9936 case SKL_DPLL3:
9937 id = DPLL_ID_SKL_DPLL3;
9938 break;
9939 default:
9940 MISSING_CASE(pipe_config->ddi_pll_sel);
9941 return;
9942 }
9943
9944 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9945 }
9946
9947 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9948 enum port port,
9949 struct intel_crtc_state *pipe_config)
9950 {
9951 enum intel_dpll_id id;
9952
9953 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9954
9955 switch (pipe_config->ddi_pll_sel) {
9956 case PORT_CLK_SEL_WRPLL1:
9957 id = DPLL_ID_WRPLL1;
9958 break;
9959 case PORT_CLK_SEL_WRPLL2:
9960 id = DPLL_ID_WRPLL2;
9961 break;
9962 case PORT_CLK_SEL_SPLL:
9963 id = DPLL_ID_SPLL;
9964 break;
9965 case PORT_CLK_SEL_LCPLL_810:
9966 id = DPLL_ID_LCPLL_810;
9967 break;
9968 case PORT_CLK_SEL_LCPLL_1350:
9969 id = DPLL_ID_LCPLL_1350;
9970 break;
9971 case PORT_CLK_SEL_LCPLL_2700:
9972 id = DPLL_ID_LCPLL_2700;
9973 break;
9974 default:
9975 MISSING_CASE(pipe_config->ddi_pll_sel);
9976 /* fall through */
9977 case PORT_CLK_SEL_NONE:
9978 return;
9979 }
9980
9981 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9982 }
9983
9984 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9985 struct intel_crtc_state *pipe_config,
9986 unsigned long *power_domain_mask)
9987 {
9988 struct drm_device *dev = crtc->base.dev;
9989 struct drm_i915_private *dev_priv = dev->dev_private;
9990 enum intel_display_power_domain power_domain;
9991 u32 tmp;
9992
9993 /*
9994 * The pipe->transcoder mapping is fixed with the exception of the eDP
9995 * transcoder handled below.
9996 */
9997 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9998
9999 /*
10000 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10001 * consistency and less surprising code; it's in always on power).
10002 */
10003 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10004 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10005 enum pipe trans_edp_pipe;
10006 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10007 default:
10008 WARN(1, "unknown pipe linked to edp transcoder\n");
10009 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10010 case TRANS_DDI_EDP_INPUT_A_ON:
10011 trans_edp_pipe = PIPE_A;
10012 break;
10013 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10014 trans_edp_pipe = PIPE_B;
10015 break;
10016 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10017 trans_edp_pipe = PIPE_C;
10018 break;
10019 }
10020
10021 if (trans_edp_pipe == crtc->pipe)
10022 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10023 }
10024
10025 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10026 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10027 return false;
10028 *power_domain_mask |= BIT(power_domain);
10029
10030 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10031
10032 return tmp & PIPECONF_ENABLE;
10033 }
10034
10035 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10036 struct intel_crtc_state *pipe_config,
10037 unsigned long *power_domain_mask)
10038 {
10039 struct drm_device *dev = crtc->base.dev;
10040 struct drm_i915_private *dev_priv = dev->dev_private;
10041 enum intel_display_power_domain power_domain;
10042 enum port port;
10043 enum transcoder cpu_transcoder;
10044 u32 tmp;
10045
10046 pipe_config->has_dsi_encoder = false;
10047
10048 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10049 if (port == PORT_A)
10050 cpu_transcoder = TRANSCODER_DSI_A;
10051 else
10052 cpu_transcoder = TRANSCODER_DSI_C;
10053
10054 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10055 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10056 continue;
10057 *power_domain_mask |= BIT(power_domain);
10058
10059 /*
10060 * The PLL needs to be enabled with a valid divider
10061 * configuration, otherwise accessing DSI registers will hang
10062 * the machine. See BSpec North Display Engine
10063 * registers/MIPI[BXT]. We can break out here early, since we
10064 * need the same DSI PLL to be enabled for both DSI ports.
10065 */
10066 if (!intel_dsi_pll_is_enabled(dev_priv))
10067 break;
10068
10069 /* XXX: this works for video mode only */
10070 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10071 if (!(tmp & DPI_ENABLE))
10072 continue;
10073
10074 tmp = I915_READ(MIPI_CTRL(port));
10075 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10076 continue;
10077
10078 pipe_config->cpu_transcoder = cpu_transcoder;
10079 pipe_config->has_dsi_encoder = true;
10080 break;
10081 }
10082
10083 return pipe_config->has_dsi_encoder;
10084 }
10085
10086 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10087 struct intel_crtc_state *pipe_config)
10088 {
10089 struct drm_device *dev = crtc->base.dev;
10090 struct drm_i915_private *dev_priv = dev->dev_private;
10091 struct intel_shared_dpll *pll;
10092 enum port port;
10093 uint32_t tmp;
10094
10095 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10096
10097 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10098
10099 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10100 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10101 else if (IS_BROXTON(dev))
10102 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10103 else
10104 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10105
10106 pll = pipe_config->shared_dpll;
10107 if (pll) {
10108 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10109 &pipe_config->dpll_hw_state));
10110 }
10111
10112 /*
10113 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10114 * DDI E. So just check whether this pipe is wired to DDI E and whether
10115 * the PCH transcoder is on.
10116 */
10117 if (INTEL_INFO(dev)->gen < 9 &&
10118 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10119 pipe_config->has_pch_encoder = true;
10120
10121 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10122 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10123 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10124
10125 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10126 }
10127 }
10128
10129 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10130 struct intel_crtc_state *pipe_config)
10131 {
10132 struct drm_device *dev = crtc->base.dev;
10133 struct drm_i915_private *dev_priv = dev->dev_private;
10134 enum intel_display_power_domain power_domain;
10135 unsigned long power_domain_mask;
10136 bool active;
10137
10138 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10139 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10140 return false;
10141 power_domain_mask = BIT(power_domain);
10142
10143 pipe_config->shared_dpll = NULL;
10144
10145 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10146
10147 if (IS_BROXTON(dev_priv)) {
10148 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10149 &power_domain_mask);
10150 WARN_ON(active && pipe_config->has_dsi_encoder);
10151 if (pipe_config->has_dsi_encoder)
10152 active = true;
10153 }
10154
10155 if (!active)
10156 goto out;
10157
10158 if (!pipe_config->has_dsi_encoder) {
10159 haswell_get_ddi_port_state(crtc, pipe_config);
10160 intel_get_pipe_timings(crtc, pipe_config);
10161 }
10162
10163 intel_get_pipe_src_size(crtc, pipe_config);
10164
10165 pipe_config->gamma_mode =
10166 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10167
10168 if (INTEL_INFO(dev)->gen >= 9) {
10169 skl_init_scalers(dev, crtc, pipe_config);
10170 }
10171
10172 if (INTEL_INFO(dev)->gen >= 9) {
10173 pipe_config->scaler_state.scaler_id = -1;
10174 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10175 }
10176
10177 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10178 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10179 power_domain_mask |= BIT(power_domain);
10180 if (INTEL_INFO(dev)->gen >= 9)
10181 skylake_get_pfit_config(crtc, pipe_config);
10182 else
10183 ironlake_get_pfit_config(crtc, pipe_config);
10184 }
10185
10186 if (IS_HASWELL(dev))
10187 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10188 (I915_READ(IPS_CTL) & IPS_ENABLE);
10189
10190 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10191 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10192 pipe_config->pixel_multiplier =
10193 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10194 } else {
10195 pipe_config->pixel_multiplier = 1;
10196 }
10197
10198 out:
10199 for_each_power_domain(power_domain, power_domain_mask)
10200 intel_display_power_put(dev_priv, power_domain);
10201
10202 return active;
10203 }
10204
10205 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10206 const struct intel_plane_state *plane_state)
10207 {
10208 struct drm_device *dev = crtc->dev;
10209 struct drm_i915_private *dev_priv = dev->dev_private;
10210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10211 uint32_t cntl = 0, size = 0;
10212
10213 if (plane_state && plane_state->visible) {
10214 unsigned int width = plane_state->base.crtc_w;
10215 unsigned int height = plane_state->base.crtc_h;
10216 unsigned int stride = roundup_pow_of_two(width) * 4;
10217
10218 switch (stride) {
10219 default:
10220 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10221 width, stride);
10222 stride = 256;
10223 /* fallthrough */
10224 case 256:
10225 case 512:
10226 case 1024:
10227 case 2048:
10228 break;
10229 }
10230
10231 cntl |= CURSOR_ENABLE |
10232 CURSOR_GAMMA_ENABLE |
10233 CURSOR_FORMAT_ARGB |
10234 CURSOR_STRIDE(stride);
10235
10236 size = (height << 12) | width;
10237 }
10238
10239 if (intel_crtc->cursor_cntl != 0 &&
10240 (intel_crtc->cursor_base != base ||
10241 intel_crtc->cursor_size != size ||
10242 intel_crtc->cursor_cntl != cntl)) {
10243 /* On these chipsets we can only modify the base/size/stride
10244 * whilst the cursor is disabled.
10245 */
10246 I915_WRITE(CURCNTR(PIPE_A), 0);
10247 POSTING_READ(CURCNTR(PIPE_A));
10248 intel_crtc->cursor_cntl = 0;
10249 }
10250
10251 if (intel_crtc->cursor_base != base) {
10252 I915_WRITE(CURBASE(PIPE_A), base);
10253 intel_crtc->cursor_base = base;
10254 }
10255
10256 if (intel_crtc->cursor_size != size) {
10257 I915_WRITE(CURSIZE, size);
10258 intel_crtc->cursor_size = size;
10259 }
10260
10261 if (intel_crtc->cursor_cntl != cntl) {
10262 I915_WRITE(CURCNTR(PIPE_A), cntl);
10263 POSTING_READ(CURCNTR(PIPE_A));
10264 intel_crtc->cursor_cntl = cntl;
10265 }
10266 }
10267
10268 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10269 const struct intel_plane_state *plane_state)
10270 {
10271 struct drm_device *dev = crtc->dev;
10272 struct drm_i915_private *dev_priv = dev->dev_private;
10273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10274 int pipe = intel_crtc->pipe;
10275 uint32_t cntl = 0;
10276
10277 if (plane_state && plane_state->visible) {
10278 cntl = MCURSOR_GAMMA_ENABLE;
10279 switch (plane_state->base.crtc_w) {
10280 case 64:
10281 cntl |= CURSOR_MODE_64_ARGB_AX;
10282 break;
10283 case 128:
10284 cntl |= CURSOR_MODE_128_ARGB_AX;
10285 break;
10286 case 256:
10287 cntl |= CURSOR_MODE_256_ARGB_AX;
10288 break;
10289 default:
10290 MISSING_CASE(plane_state->base.crtc_w);
10291 return;
10292 }
10293 cntl |= pipe << 28; /* Connect to correct pipe */
10294
10295 if (HAS_DDI(dev))
10296 cntl |= CURSOR_PIPE_CSC_ENABLE;
10297
10298 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10299 cntl |= CURSOR_ROTATE_180;
10300 }
10301
10302 if (intel_crtc->cursor_cntl != cntl) {
10303 I915_WRITE(CURCNTR(pipe), cntl);
10304 POSTING_READ(CURCNTR(pipe));
10305 intel_crtc->cursor_cntl = cntl;
10306 }
10307
10308 /* and commit changes on next vblank */
10309 I915_WRITE(CURBASE(pipe), base);
10310 POSTING_READ(CURBASE(pipe));
10311
10312 intel_crtc->cursor_base = base;
10313 }
10314
10315 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10316 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10317 const struct intel_plane_state *plane_state)
10318 {
10319 struct drm_device *dev = crtc->dev;
10320 struct drm_i915_private *dev_priv = dev->dev_private;
10321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10322 int pipe = intel_crtc->pipe;
10323 u32 base = intel_crtc->cursor_addr;
10324 u32 pos = 0;
10325
10326 if (plane_state) {
10327 int x = plane_state->base.crtc_x;
10328 int y = plane_state->base.crtc_y;
10329
10330 if (x < 0) {
10331 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10332 x = -x;
10333 }
10334 pos |= x << CURSOR_X_SHIFT;
10335
10336 if (y < 0) {
10337 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10338 y = -y;
10339 }
10340 pos |= y << CURSOR_Y_SHIFT;
10341
10342 /* ILK+ do this automagically */
10343 if (HAS_GMCH_DISPLAY(dev) &&
10344 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10345 base += (plane_state->base.crtc_h *
10346 plane_state->base.crtc_w - 1) * 4;
10347 }
10348 }
10349
10350 I915_WRITE(CURPOS(pipe), pos);
10351
10352 if (IS_845G(dev) || IS_I865G(dev))
10353 i845_update_cursor(crtc, base, plane_state);
10354 else
10355 i9xx_update_cursor(crtc, base, plane_state);
10356 }
10357
10358 static bool cursor_size_ok(struct drm_device *dev,
10359 uint32_t width, uint32_t height)
10360 {
10361 if (width == 0 || height == 0)
10362 return false;
10363
10364 /*
10365 * 845g/865g are special in that they are only limited by
10366 * the width of their cursors, the height is arbitrary up to
10367 * the precision of the register. Everything else requires
10368 * square cursors, limited to a few power-of-two sizes.
10369 */
10370 if (IS_845G(dev) || IS_I865G(dev)) {
10371 if ((width & 63) != 0)
10372 return false;
10373
10374 if (width > (IS_845G(dev) ? 64 : 512))
10375 return false;
10376
10377 if (height > 1023)
10378 return false;
10379 } else {
10380 switch (width | height) {
10381 case 256:
10382 case 128:
10383 if (IS_GEN2(dev))
10384 return false;
10385 case 64:
10386 break;
10387 default:
10388 return false;
10389 }
10390 }
10391
10392 return true;
10393 }
10394
10395 /* VESA 640x480x72Hz mode to set on the pipe */
10396 static struct drm_display_mode load_detect_mode = {
10397 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10398 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10399 };
10400
10401 struct drm_framebuffer *
10402 __intel_framebuffer_create(struct drm_device *dev,
10403 struct drm_mode_fb_cmd2 *mode_cmd,
10404 struct drm_i915_gem_object *obj)
10405 {
10406 struct intel_framebuffer *intel_fb;
10407 int ret;
10408
10409 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10410 if (!intel_fb)
10411 return ERR_PTR(-ENOMEM);
10412
10413 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10414 if (ret)
10415 goto err;
10416
10417 return &intel_fb->base;
10418
10419 err:
10420 kfree(intel_fb);
10421 return ERR_PTR(ret);
10422 }
10423
10424 static struct drm_framebuffer *
10425 intel_framebuffer_create(struct drm_device *dev,
10426 struct drm_mode_fb_cmd2 *mode_cmd,
10427 struct drm_i915_gem_object *obj)
10428 {
10429 struct drm_framebuffer *fb;
10430 int ret;
10431
10432 ret = i915_mutex_lock_interruptible(dev);
10433 if (ret)
10434 return ERR_PTR(ret);
10435 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10436 mutex_unlock(&dev->struct_mutex);
10437
10438 return fb;
10439 }
10440
10441 static u32
10442 intel_framebuffer_pitch_for_width(int width, int bpp)
10443 {
10444 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10445 return ALIGN(pitch, 64);
10446 }
10447
10448 static u32
10449 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10450 {
10451 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10452 return PAGE_ALIGN(pitch * mode->vdisplay);
10453 }
10454
10455 static struct drm_framebuffer *
10456 intel_framebuffer_create_for_mode(struct drm_device *dev,
10457 struct drm_display_mode *mode,
10458 int depth, int bpp)
10459 {
10460 struct drm_framebuffer *fb;
10461 struct drm_i915_gem_object *obj;
10462 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10463
10464 obj = i915_gem_object_create(dev,
10465 intel_framebuffer_size_for_mode(mode, bpp));
10466 if (IS_ERR(obj))
10467 return ERR_CAST(obj);
10468
10469 mode_cmd.width = mode->hdisplay;
10470 mode_cmd.height = mode->vdisplay;
10471 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10472 bpp);
10473 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10474
10475 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10476 if (IS_ERR(fb))
10477 drm_gem_object_unreference_unlocked(&obj->base);
10478
10479 return fb;
10480 }
10481
10482 static struct drm_framebuffer *
10483 mode_fits_in_fbdev(struct drm_device *dev,
10484 struct drm_display_mode *mode)
10485 {
10486 #ifdef CONFIG_DRM_FBDEV_EMULATION
10487 struct drm_i915_private *dev_priv = dev->dev_private;
10488 struct drm_i915_gem_object *obj;
10489 struct drm_framebuffer *fb;
10490
10491 if (!dev_priv->fbdev)
10492 return NULL;
10493
10494 if (!dev_priv->fbdev->fb)
10495 return NULL;
10496
10497 obj = dev_priv->fbdev->fb->obj;
10498 BUG_ON(!obj);
10499
10500 fb = &dev_priv->fbdev->fb->base;
10501 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10502 fb->bits_per_pixel))
10503 return NULL;
10504
10505 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10506 return NULL;
10507
10508 drm_framebuffer_reference(fb);
10509 return fb;
10510 #else
10511 return NULL;
10512 #endif
10513 }
10514
10515 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10516 struct drm_crtc *crtc,
10517 struct drm_display_mode *mode,
10518 struct drm_framebuffer *fb,
10519 int x, int y)
10520 {
10521 struct drm_plane_state *plane_state;
10522 int hdisplay, vdisplay;
10523 int ret;
10524
10525 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10526 if (IS_ERR(plane_state))
10527 return PTR_ERR(plane_state);
10528
10529 if (mode)
10530 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10531 else
10532 hdisplay = vdisplay = 0;
10533
10534 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10535 if (ret)
10536 return ret;
10537 drm_atomic_set_fb_for_plane(plane_state, fb);
10538 plane_state->crtc_x = 0;
10539 plane_state->crtc_y = 0;
10540 plane_state->crtc_w = hdisplay;
10541 plane_state->crtc_h = vdisplay;
10542 plane_state->src_x = x << 16;
10543 plane_state->src_y = y << 16;
10544 plane_state->src_w = hdisplay << 16;
10545 plane_state->src_h = vdisplay << 16;
10546
10547 return 0;
10548 }
10549
10550 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10551 struct drm_display_mode *mode,
10552 struct intel_load_detect_pipe *old,
10553 struct drm_modeset_acquire_ctx *ctx)
10554 {
10555 struct intel_crtc *intel_crtc;
10556 struct intel_encoder *intel_encoder =
10557 intel_attached_encoder(connector);
10558 struct drm_crtc *possible_crtc;
10559 struct drm_encoder *encoder = &intel_encoder->base;
10560 struct drm_crtc *crtc = NULL;
10561 struct drm_device *dev = encoder->dev;
10562 struct drm_framebuffer *fb;
10563 struct drm_mode_config *config = &dev->mode_config;
10564 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10565 struct drm_connector_state *connector_state;
10566 struct intel_crtc_state *crtc_state;
10567 int ret, i = -1;
10568
10569 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10570 connector->base.id, connector->name,
10571 encoder->base.id, encoder->name);
10572
10573 old->restore_state = NULL;
10574
10575 retry:
10576 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10577 if (ret)
10578 goto fail;
10579
10580 /*
10581 * Algorithm gets a little messy:
10582 *
10583 * - if the connector already has an assigned crtc, use it (but make
10584 * sure it's on first)
10585 *
10586 * - try to find the first unused crtc that can drive this connector,
10587 * and use that if we find one
10588 */
10589
10590 /* See if we already have a CRTC for this connector */
10591 if (connector->state->crtc) {
10592 crtc = connector->state->crtc;
10593
10594 ret = drm_modeset_lock(&crtc->mutex, ctx);
10595 if (ret)
10596 goto fail;
10597
10598 /* Make sure the crtc and connector are running */
10599 goto found;
10600 }
10601
10602 /* Find an unused one (if possible) */
10603 for_each_crtc(dev, possible_crtc) {
10604 i++;
10605 if (!(encoder->possible_crtcs & (1 << i)))
10606 continue;
10607
10608 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10609 if (ret)
10610 goto fail;
10611
10612 if (possible_crtc->state->enable) {
10613 drm_modeset_unlock(&possible_crtc->mutex);
10614 continue;
10615 }
10616
10617 crtc = possible_crtc;
10618 break;
10619 }
10620
10621 /*
10622 * If we didn't find an unused CRTC, don't use any.
10623 */
10624 if (!crtc) {
10625 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10626 goto fail;
10627 }
10628
10629 found:
10630 intel_crtc = to_intel_crtc(crtc);
10631
10632 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10633 if (ret)
10634 goto fail;
10635
10636 state = drm_atomic_state_alloc(dev);
10637 restore_state = drm_atomic_state_alloc(dev);
10638 if (!state || !restore_state) {
10639 ret = -ENOMEM;
10640 goto fail;
10641 }
10642
10643 state->acquire_ctx = ctx;
10644 restore_state->acquire_ctx = ctx;
10645
10646 connector_state = drm_atomic_get_connector_state(state, connector);
10647 if (IS_ERR(connector_state)) {
10648 ret = PTR_ERR(connector_state);
10649 goto fail;
10650 }
10651
10652 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10653 if (ret)
10654 goto fail;
10655
10656 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10657 if (IS_ERR(crtc_state)) {
10658 ret = PTR_ERR(crtc_state);
10659 goto fail;
10660 }
10661
10662 crtc_state->base.active = crtc_state->base.enable = true;
10663
10664 if (!mode)
10665 mode = &load_detect_mode;
10666
10667 /* We need a framebuffer large enough to accommodate all accesses
10668 * that the plane may generate whilst we perform load detection.
10669 * We can not rely on the fbcon either being present (we get called
10670 * during its initialisation to detect all boot displays, or it may
10671 * not even exist) or that it is large enough to satisfy the
10672 * requested mode.
10673 */
10674 fb = mode_fits_in_fbdev(dev, mode);
10675 if (fb == NULL) {
10676 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10677 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10678 } else
10679 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10680 if (IS_ERR(fb)) {
10681 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10682 goto fail;
10683 }
10684
10685 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10686 if (ret)
10687 goto fail;
10688
10689 drm_framebuffer_unreference(fb);
10690
10691 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10692 if (ret)
10693 goto fail;
10694
10695 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10696 if (!ret)
10697 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10698 if (!ret)
10699 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10700 if (ret) {
10701 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10702 goto fail;
10703 }
10704
10705 ret = drm_atomic_commit(state);
10706 if (ret) {
10707 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10708 goto fail;
10709 }
10710
10711 old->restore_state = restore_state;
10712
10713 /* let the connector get through one full cycle before testing */
10714 intel_wait_for_vblank(dev, intel_crtc->pipe);
10715 return true;
10716
10717 fail:
10718 drm_atomic_state_free(state);
10719 drm_atomic_state_free(restore_state);
10720 restore_state = state = NULL;
10721
10722 if (ret == -EDEADLK) {
10723 drm_modeset_backoff(ctx);
10724 goto retry;
10725 }
10726
10727 return false;
10728 }
10729
10730 void intel_release_load_detect_pipe(struct drm_connector *connector,
10731 struct intel_load_detect_pipe *old,
10732 struct drm_modeset_acquire_ctx *ctx)
10733 {
10734 struct intel_encoder *intel_encoder =
10735 intel_attached_encoder(connector);
10736 struct drm_encoder *encoder = &intel_encoder->base;
10737 struct drm_atomic_state *state = old->restore_state;
10738 int ret;
10739
10740 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10741 connector->base.id, connector->name,
10742 encoder->base.id, encoder->name);
10743
10744 if (!state)
10745 return;
10746
10747 ret = drm_atomic_commit(state);
10748 if (ret) {
10749 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10750 drm_atomic_state_free(state);
10751 }
10752 }
10753
10754 static int i9xx_pll_refclk(struct drm_device *dev,
10755 const struct intel_crtc_state *pipe_config)
10756 {
10757 struct drm_i915_private *dev_priv = dev->dev_private;
10758 u32 dpll = pipe_config->dpll_hw_state.dpll;
10759
10760 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10761 return dev_priv->vbt.lvds_ssc_freq;
10762 else if (HAS_PCH_SPLIT(dev))
10763 return 120000;
10764 else if (!IS_GEN2(dev))
10765 return 96000;
10766 else
10767 return 48000;
10768 }
10769
10770 /* Returns the clock of the currently programmed mode of the given pipe. */
10771 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10772 struct intel_crtc_state *pipe_config)
10773 {
10774 struct drm_device *dev = crtc->base.dev;
10775 struct drm_i915_private *dev_priv = dev->dev_private;
10776 int pipe = pipe_config->cpu_transcoder;
10777 u32 dpll = pipe_config->dpll_hw_state.dpll;
10778 u32 fp;
10779 struct dpll clock;
10780 int port_clock;
10781 int refclk = i9xx_pll_refclk(dev, pipe_config);
10782
10783 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10784 fp = pipe_config->dpll_hw_state.fp0;
10785 else
10786 fp = pipe_config->dpll_hw_state.fp1;
10787
10788 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10789 if (IS_PINEVIEW(dev)) {
10790 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10791 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10792 } else {
10793 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10794 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10795 }
10796
10797 if (!IS_GEN2(dev)) {
10798 if (IS_PINEVIEW(dev))
10799 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10800 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10801 else
10802 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10803 DPLL_FPA01_P1_POST_DIV_SHIFT);
10804
10805 switch (dpll & DPLL_MODE_MASK) {
10806 case DPLLB_MODE_DAC_SERIAL:
10807 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10808 5 : 10;
10809 break;
10810 case DPLLB_MODE_LVDS:
10811 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10812 7 : 14;
10813 break;
10814 default:
10815 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10816 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10817 return;
10818 }
10819
10820 if (IS_PINEVIEW(dev))
10821 port_clock = pnv_calc_dpll_params(refclk, &clock);
10822 else
10823 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10824 } else {
10825 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10826 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10827
10828 if (is_lvds) {
10829 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10830 DPLL_FPA01_P1_POST_DIV_SHIFT);
10831
10832 if (lvds & LVDS_CLKB_POWER_UP)
10833 clock.p2 = 7;
10834 else
10835 clock.p2 = 14;
10836 } else {
10837 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10838 clock.p1 = 2;
10839 else {
10840 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10841 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10842 }
10843 if (dpll & PLL_P2_DIVIDE_BY_4)
10844 clock.p2 = 4;
10845 else
10846 clock.p2 = 2;
10847 }
10848
10849 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10850 }
10851
10852 /*
10853 * This value includes pixel_multiplier. We will use
10854 * port_clock to compute adjusted_mode.crtc_clock in the
10855 * encoder's get_config() function.
10856 */
10857 pipe_config->port_clock = port_clock;
10858 }
10859
10860 int intel_dotclock_calculate(int link_freq,
10861 const struct intel_link_m_n *m_n)
10862 {
10863 /*
10864 * The calculation for the data clock is:
10865 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10866 * But we want to avoid losing precison if possible, so:
10867 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10868 *
10869 * and the link clock is simpler:
10870 * link_clock = (m * link_clock) / n
10871 */
10872
10873 if (!m_n->link_n)
10874 return 0;
10875
10876 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10877 }
10878
10879 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10880 struct intel_crtc_state *pipe_config)
10881 {
10882 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10883
10884 /* read out port_clock from the DPLL */
10885 i9xx_crtc_clock_get(crtc, pipe_config);
10886
10887 /*
10888 * In case there is an active pipe without active ports,
10889 * we may need some idea for the dotclock anyway.
10890 * Calculate one based on the FDI configuration.
10891 */
10892 pipe_config->base.adjusted_mode.crtc_clock =
10893 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10894 &pipe_config->fdi_m_n);
10895 }
10896
10897 /** Returns the currently programmed mode of the given pipe. */
10898 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10899 struct drm_crtc *crtc)
10900 {
10901 struct drm_i915_private *dev_priv = dev->dev_private;
10902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10903 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10904 struct drm_display_mode *mode;
10905 struct intel_crtc_state *pipe_config;
10906 int htot = I915_READ(HTOTAL(cpu_transcoder));
10907 int hsync = I915_READ(HSYNC(cpu_transcoder));
10908 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10909 int vsync = I915_READ(VSYNC(cpu_transcoder));
10910 enum pipe pipe = intel_crtc->pipe;
10911
10912 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10913 if (!mode)
10914 return NULL;
10915
10916 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10917 if (!pipe_config) {
10918 kfree(mode);
10919 return NULL;
10920 }
10921
10922 /*
10923 * Construct a pipe_config sufficient for getting the clock info
10924 * back out of crtc_clock_get.
10925 *
10926 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10927 * to use a real value here instead.
10928 */
10929 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10930 pipe_config->pixel_multiplier = 1;
10931 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10932 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10933 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10934 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10935
10936 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10937 mode->hdisplay = (htot & 0xffff) + 1;
10938 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10939 mode->hsync_start = (hsync & 0xffff) + 1;
10940 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10941 mode->vdisplay = (vtot & 0xffff) + 1;
10942 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10943 mode->vsync_start = (vsync & 0xffff) + 1;
10944 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10945
10946 drm_mode_set_name(mode);
10947
10948 kfree(pipe_config);
10949
10950 return mode;
10951 }
10952
10953 void intel_mark_busy(struct drm_i915_private *dev_priv)
10954 {
10955 if (dev_priv->mm.busy)
10956 return;
10957
10958 intel_runtime_pm_get(dev_priv);
10959 i915_update_gfx_val(dev_priv);
10960 if (INTEL_GEN(dev_priv) >= 6)
10961 gen6_rps_busy(dev_priv);
10962 dev_priv->mm.busy = true;
10963 }
10964
10965 void intel_mark_idle(struct drm_i915_private *dev_priv)
10966 {
10967 if (!dev_priv->mm.busy)
10968 return;
10969
10970 dev_priv->mm.busy = false;
10971
10972 if (INTEL_GEN(dev_priv) >= 6)
10973 gen6_rps_idle(dev_priv);
10974
10975 intel_runtime_pm_put(dev_priv);
10976 }
10977
10978 static void intel_crtc_destroy(struct drm_crtc *crtc)
10979 {
10980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10981 struct drm_device *dev = crtc->dev;
10982 struct intel_flip_work *work;
10983
10984 spin_lock_irq(&dev->event_lock);
10985 work = intel_crtc->flip_work;
10986 intel_crtc->flip_work = NULL;
10987 spin_unlock_irq(&dev->event_lock);
10988
10989 if (work) {
10990 cancel_work_sync(&work->mmio_work);
10991 cancel_work_sync(&work->unpin_work);
10992 kfree(work);
10993 }
10994
10995 drm_crtc_cleanup(crtc);
10996
10997 kfree(intel_crtc);
10998 }
10999
11000 static void intel_unpin_work_fn(struct work_struct *__work)
11001 {
11002 struct intel_flip_work *work =
11003 container_of(__work, struct intel_flip_work, unpin_work);
11004 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11005 struct drm_device *dev = crtc->base.dev;
11006 struct drm_plane *primary = crtc->base.primary;
11007
11008 if (is_mmio_work(work))
11009 flush_work(&work->mmio_work);
11010
11011 mutex_lock(&dev->struct_mutex);
11012 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11013 drm_gem_object_unreference(&work->pending_flip_obj->base);
11014
11015 if (work->flip_queued_req)
11016 i915_gem_request_assign(&work->flip_queued_req, NULL);
11017 mutex_unlock(&dev->struct_mutex);
11018
11019 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
11020 intel_fbc_post_update(crtc);
11021 drm_framebuffer_unreference(work->old_fb);
11022
11023 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11024 atomic_dec(&crtc->unpin_work_count);
11025
11026 kfree(work);
11027 }
11028
11029 /* Is 'a' after or equal to 'b'? */
11030 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11031 {
11032 return !((a - b) & 0x80000000);
11033 }
11034
11035 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11036 struct intel_flip_work *work)
11037 {
11038 struct drm_device *dev = crtc->base.dev;
11039 struct drm_i915_private *dev_priv = dev->dev_private;
11040 unsigned reset_counter;
11041
11042 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11043 if (crtc->reset_counter != reset_counter)
11044 return true;
11045
11046 /*
11047 * The relevant registers doen't exist on pre-ctg.
11048 * As the flip done interrupt doesn't trigger for mmio
11049 * flips on gmch platforms, a flip count check isn't
11050 * really needed there. But since ctg has the registers,
11051 * include it in the check anyway.
11052 */
11053 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11054 return true;
11055
11056 /*
11057 * BDW signals flip done immediately if the plane
11058 * is disabled, even if the plane enable is already
11059 * armed to occur at the next vblank :(
11060 */
11061
11062 /*
11063 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11064 * used the same base address. In that case the mmio flip might
11065 * have completed, but the CS hasn't even executed the flip yet.
11066 *
11067 * A flip count check isn't enough as the CS might have updated
11068 * the base address just after start of vblank, but before we
11069 * managed to process the interrupt. This means we'd complete the
11070 * CS flip too soon.
11071 *
11072 * Combining both checks should get us a good enough result. It may
11073 * still happen that the CS flip has been executed, but has not
11074 * yet actually completed. But in case the base address is the same
11075 * anyway, we don't really care.
11076 */
11077 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11078 crtc->flip_work->gtt_offset &&
11079 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11080 crtc->flip_work->flip_count);
11081 }
11082
11083 static bool
11084 __pageflip_finished_mmio(struct intel_crtc *crtc,
11085 struct intel_flip_work *work)
11086 {
11087 /*
11088 * MMIO work completes when vblank is different from
11089 * flip_queued_vblank.
11090 *
11091 * Reset counter value doesn't matter, this is handled by
11092 * i915_wait_request finishing early, so no need to handle
11093 * reset here.
11094 */
11095 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11096 }
11097
11098
11099 static bool pageflip_finished(struct intel_crtc *crtc,
11100 struct intel_flip_work *work)
11101 {
11102 if (!atomic_read(&work->pending))
11103 return false;
11104
11105 smp_rmb();
11106
11107 if (is_mmio_work(work))
11108 return __pageflip_finished_mmio(crtc, work);
11109 else
11110 return __pageflip_finished_cs(crtc, work);
11111 }
11112
11113 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11114 {
11115 struct drm_device *dev = dev_priv->dev;
11116 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11118 struct intel_flip_work *work;
11119 unsigned long flags;
11120
11121 /* Ignore early vblank irqs */
11122 if (!crtc)
11123 return;
11124
11125 /*
11126 * This is called both by irq handlers and the reset code (to complete
11127 * lost pageflips) so needs the full irqsave spinlocks.
11128 */
11129 spin_lock_irqsave(&dev->event_lock, flags);
11130 work = intel_crtc->flip_work;
11131
11132 if (work != NULL &&
11133 !is_mmio_work(work) &&
11134 pageflip_finished(intel_crtc, work))
11135 page_flip_completed(intel_crtc);
11136
11137 spin_unlock_irqrestore(&dev->event_lock, flags);
11138 }
11139
11140 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11141 {
11142 struct drm_device *dev = dev_priv->dev;
11143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11145 struct intel_flip_work *work;
11146 unsigned long flags;
11147
11148 /* Ignore early vblank irqs */
11149 if (!crtc)
11150 return;
11151
11152 /*
11153 * This is called both by irq handlers and the reset code (to complete
11154 * lost pageflips) so needs the full irqsave spinlocks.
11155 */
11156 spin_lock_irqsave(&dev->event_lock, flags);
11157 work = intel_crtc->flip_work;
11158
11159 if (work != NULL &&
11160 is_mmio_work(work) &&
11161 pageflip_finished(intel_crtc, work))
11162 page_flip_completed(intel_crtc);
11163
11164 spin_unlock_irqrestore(&dev->event_lock, flags);
11165 }
11166
11167 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11168 struct intel_flip_work *work)
11169 {
11170 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11171
11172 /* Ensure that the work item is consistent when activating it ... */
11173 smp_mb__before_atomic();
11174 atomic_set(&work->pending, 1);
11175 }
11176
11177 static int intel_gen2_queue_flip(struct drm_device *dev,
11178 struct drm_crtc *crtc,
11179 struct drm_framebuffer *fb,
11180 struct drm_i915_gem_object *obj,
11181 struct drm_i915_gem_request *req,
11182 uint32_t flags)
11183 {
11184 struct intel_engine_cs *engine = req->engine;
11185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11186 u32 flip_mask;
11187 int ret;
11188
11189 ret = intel_ring_begin(req, 6);
11190 if (ret)
11191 return ret;
11192
11193 /* Can't queue multiple flips, so wait for the previous
11194 * one to finish before executing the next.
11195 */
11196 if (intel_crtc->plane)
11197 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11198 else
11199 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11200 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11201 intel_ring_emit(engine, MI_NOOP);
11202 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11203 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11204 intel_ring_emit(engine, fb->pitches[0]);
11205 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11206 intel_ring_emit(engine, 0); /* aux display base address, unused */
11207
11208 return 0;
11209 }
11210
11211 static int intel_gen3_queue_flip(struct drm_device *dev,
11212 struct drm_crtc *crtc,
11213 struct drm_framebuffer *fb,
11214 struct drm_i915_gem_object *obj,
11215 struct drm_i915_gem_request *req,
11216 uint32_t flags)
11217 {
11218 struct intel_engine_cs *engine = req->engine;
11219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11220 u32 flip_mask;
11221 int ret;
11222
11223 ret = intel_ring_begin(req, 6);
11224 if (ret)
11225 return ret;
11226
11227 if (intel_crtc->plane)
11228 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11229 else
11230 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11231 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11232 intel_ring_emit(engine, MI_NOOP);
11233 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11234 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11235 intel_ring_emit(engine, fb->pitches[0]);
11236 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11237 intel_ring_emit(engine, MI_NOOP);
11238
11239 return 0;
11240 }
11241
11242 static int intel_gen4_queue_flip(struct drm_device *dev,
11243 struct drm_crtc *crtc,
11244 struct drm_framebuffer *fb,
11245 struct drm_i915_gem_object *obj,
11246 struct drm_i915_gem_request *req,
11247 uint32_t flags)
11248 {
11249 struct intel_engine_cs *engine = req->engine;
11250 struct drm_i915_private *dev_priv = dev->dev_private;
11251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11252 uint32_t pf, pipesrc;
11253 int ret;
11254
11255 ret = intel_ring_begin(req, 4);
11256 if (ret)
11257 return ret;
11258
11259 /* i965+ uses the linear or tiled offsets from the
11260 * Display Registers (which do not change across a page-flip)
11261 * so we need only reprogram the base address.
11262 */
11263 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11264 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11265 intel_ring_emit(engine, fb->pitches[0]);
11266 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11267 obj->tiling_mode);
11268
11269 /* XXX Enabling the panel-fitter across page-flip is so far
11270 * untested on non-native modes, so ignore it for now.
11271 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11272 */
11273 pf = 0;
11274 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11275 intel_ring_emit(engine, pf | pipesrc);
11276
11277 return 0;
11278 }
11279
11280 static int intel_gen6_queue_flip(struct drm_device *dev,
11281 struct drm_crtc *crtc,
11282 struct drm_framebuffer *fb,
11283 struct drm_i915_gem_object *obj,
11284 struct drm_i915_gem_request *req,
11285 uint32_t flags)
11286 {
11287 struct intel_engine_cs *engine = req->engine;
11288 struct drm_i915_private *dev_priv = dev->dev_private;
11289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11290 uint32_t pf, pipesrc;
11291 int ret;
11292
11293 ret = intel_ring_begin(req, 4);
11294 if (ret)
11295 return ret;
11296
11297 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11298 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11299 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11300 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11301
11302 /* Contrary to the suggestions in the documentation,
11303 * "Enable Panel Fitter" does not seem to be required when page
11304 * flipping with a non-native mode, and worse causes a normal
11305 * modeset to fail.
11306 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11307 */
11308 pf = 0;
11309 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11310 intel_ring_emit(engine, pf | pipesrc);
11311
11312 return 0;
11313 }
11314
11315 static int intel_gen7_queue_flip(struct drm_device *dev,
11316 struct drm_crtc *crtc,
11317 struct drm_framebuffer *fb,
11318 struct drm_i915_gem_object *obj,
11319 struct drm_i915_gem_request *req,
11320 uint32_t flags)
11321 {
11322 struct intel_engine_cs *engine = req->engine;
11323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11324 uint32_t plane_bit = 0;
11325 int len, ret;
11326
11327 switch (intel_crtc->plane) {
11328 case PLANE_A:
11329 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11330 break;
11331 case PLANE_B:
11332 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11333 break;
11334 case PLANE_C:
11335 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11336 break;
11337 default:
11338 WARN_ONCE(1, "unknown plane in flip command\n");
11339 return -ENODEV;
11340 }
11341
11342 len = 4;
11343 if (engine->id == RCS) {
11344 len += 6;
11345 /*
11346 * On Gen 8, SRM is now taking an extra dword to accommodate
11347 * 48bits addresses, and we need a NOOP for the batch size to
11348 * stay even.
11349 */
11350 if (IS_GEN8(dev))
11351 len += 2;
11352 }
11353
11354 /*
11355 * BSpec MI_DISPLAY_FLIP for IVB:
11356 * "The full packet must be contained within the same cache line."
11357 *
11358 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11359 * cacheline, if we ever start emitting more commands before
11360 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11361 * then do the cacheline alignment, and finally emit the
11362 * MI_DISPLAY_FLIP.
11363 */
11364 ret = intel_ring_cacheline_align(req);
11365 if (ret)
11366 return ret;
11367
11368 ret = intel_ring_begin(req, len);
11369 if (ret)
11370 return ret;
11371
11372 /* Unmask the flip-done completion message. Note that the bspec says that
11373 * we should do this for both the BCS and RCS, and that we must not unmask
11374 * more than one flip event at any time (or ensure that one flip message
11375 * can be sent by waiting for flip-done prior to queueing new flips).
11376 * Experimentation says that BCS works despite DERRMR masking all
11377 * flip-done completion events and that unmasking all planes at once
11378 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11379 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11380 */
11381 if (engine->id == RCS) {
11382 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11383 intel_ring_emit_reg(engine, DERRMR);
11384 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11385 DERRMR_PIPEB_PRI_FLIP_DONE |
11386 DERRMR_PIPEC_PRI_FLIP_DONE));
11387 if (IS_GEN8(dev))
11388 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11389 MI_SRM_LRM_GLOBAL_GTT);
11390 else
11391 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11392 MI_SRM_LRM_GLOBAL_GTT);
11393 intel_ring_emit_reg(engine, DERRMR);
11394 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11395 if (IS_GEN8(dev)) {
11396 intel_ring_emit(engine, 0);
11397 intel_ring_emit(engine, MI_NOOP);
11398 }
11399 }
11400
11401 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11402 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11403 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11404 intel_ring_emit(engine, (MI_NOOP));
11405
11406 return 0;
11407 }
11408
11409 static bool use_mmio_flip(struct intel_engine_cs *engine,
11410 struct drm_i915_gem_object *obj)
11411 {
11412 /*
11413 * This is not being used for older platforms, because
11414 * non-availability of flip done interrupt forces us to use
11415 * CS flips. Older platforms derive flip done using some clever
11416 * tricks involving the flip_pending status bits and vblank irqs.
11417 * So using MMIO flips there would disrupt this mechanism.
11418 */
11419
11420 if (engine == NULL)
11421 return true;
11422
11423 if (INTEL_GEN(engine->i915) < 5)
11424 return false;
11425
11426 if (i915.use_mmio_flip < 0)
11427 return false;
11428 else if (i915.use_mmio_flip > 0)
11429 return true;
11430 else if (i915.enable_execlists)
11431 return true;
11432 else if (obj->base.dma_buf &&
11433 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11434 false))
11435 return true;
11436 else
11437 return engine != i915_gem_request_get_engine(obj->last_write_req);
11438 }
11439
11440 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11441 unsigned int rotation,
11442 struct intel_flip_work *work)
11443 {
11444 struct drm_device *dev = intel_crtc->base.dev;
11445 struct drm_i915_private *dev_priv = dev->dev_private;
11446 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11447 const enum pipe pipe = intel_crtc->pipe;
11448 u32 ctl, stride, tile_height;
11449
11450 ctl = I915_READ(PLANE_CTL(pipe, 0));
11451 ctl &= ~PLANE_CTL_TILED_MASK;
11452 switch (fb->modifier[0]) {
11453 case DRM_FORMAT_MOD_NONE:
11454 break;
11455 case I915_FORMAT_MOD_X_TILED:
11456 ctl |= PLANE_CTL_TILED_X;
11457 break;
11458 case I915_FORMAT_MOD_Y_TILED:
11459 ctl |= PLANE_CTL_TILED_Y;
11460 break;
11461 case I915_FORMAT_MOD_Yf_TILED:
11462 ctl |= PLANE_CTL_TILED_YF;
11463 break;
11464 default:
11465 MISSING_CASE(fb->modifier[0]);
11466 }
11467
11468 /*
11469 * The stride is either expressed as a multiple of 64 bytes chunks for
11470 * linear buffers or in number of tiles for tiled buffers.
11471 */
11472 if (intel_rotation_90_or_270(rotation)) {
11473 /* stride = Surface height in tiles */
11474 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11475 stride = DIV_ROUND_UP(fb->height, tile_height);
11476 } else {
11477 stride = fb->pitches[0] /
11478 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11479 fb->pixel_format);
11480 }
11481
11482 /*
11483 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11484 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11485 */
11486 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11487 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11488
11489 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11490 POSTING_READ(PLANE_SURF(pipe, 0));
11491 }
11492
11493 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11494 struct intel_flip_work *work)
11495 {
11496 struct drm_device *dev = intel_crtc->base.dev;
11497 struct drm_i915_private *dev_priv = dev->dev_private;
11498 struct intel_framebuffer *intel_fb =
11499 to_intel_framebuffer(intel_crtc->base.primary->fb);
11500 struct drm_i915_gem_object *obj = intel_fb->obj;
11501 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11502 u32 dspcntr;
11503
11504 dspcntr = I915_READ(reg);
11505
11506 if (obj->tiling_mode != I915_TILING_NONE)
11507 dspcntr |= DISPPLANE_TILED;
11508 else
11509 dspcntr &= ~DISPPLANE_TILED;
11510
11511 I915_WRITE(reg, dspcntr);
11512
11513 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11514 POSTING_READ(DSPSURF(intel_crtc->plane));
11515 }
11516
11517 static void intel_mmio_flip_work_func(struct work_struct *w)
11518 {
11519 struct intel_flip_work *work =
11520 container_of(w, struct intel_flip_work, mmio_work);
11521 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11522 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11523 struct intel_framebuffer *intel_fb =
11524 to_intel_framebuffer(crtc->base.primary->fb);
11525 struct drm_i915_gem_object *obj = intel_fb->obj;
11526
11527 if (work->flip_queued_req)
11528 WARN_ON(__i915_wait_request(work->flip_queued_req,
11529 false, NULL,
11530 &dev_priv->rps.mmioflips));
11531
11532 /* For framebuffer backed by dmabuf, wait for fence */
11533 if (obj->base.dma_buf)
11534 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11535 false, false,
11536 MAX_SCHEDULE_TIMEOUT) < 0);
11537
11538 intel_pipe_update_start(crtc);
11539
11540 if (INTEL_GEN(dev_priv) >= 9)
11541 skl_do_mmio_flip(crtc, work->rotation, work);
11542 else
11543 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11544 ilk_do_mmio_flip(crtc, work);
11545
11546 intel_pipe_update_end(crtc, work);
11547 }
11548
11549 static int intel_default_queue_flip(struct drm_device *dev,
11550 struct drm_crtc *crtc,
11551 struct drm_framebuffer *fb,
11552 struct drm_i915_gem_object *obj,
11553 struct drm_i915_gem_request *req,
11554 uint32_t flags)
11555 {
11556 return -ENODEV;
11557 }
11558
11559 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11560 struct intel_crtc *intel_crtc,
11561 struct intel_flip_work *work)
11562 {
11563 u32 addr, vblank;
11564
11565 if (!atomic_read(&work->pending))
11566 return false;
11567
11568 smp_rmb();
11569
11570 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11571 if (work->flip_ready_vblank == 0) {
11572 if (work->flip_queued_req &&
11573 !i915_gem_request_completed(work->flip_queued_req, true))
11574 return false;
11575
11576 work->flip_ready_vblank = vblank;
11577 }
11578
11579 if (vblank - work->flip_ready_vblank < 3)
11580 return false;
11581
11582 /* Potential stall - if we see that the flip has happened,
11583 * assume a missed interrupt. */
11584 if (INTEL_GEN(dev_priv) >= 4)
11585 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11586 else
11587 addr = I915_READ(DSPADDR(intel_crtc->plane));
11588
11589 /* There is a potential issue here with a false positive after a flip
11590 * to the same address. We could address this by checking for a
11591 * non-incrementing frame counter.
11592 */
11593 return addr == work->gtt_offset;
11594 }
11595
11596 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11597 {
11598 struct drm_device *dev = dev_priv->dev;
11599 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11601 struct intel_flip_work *work;
11602
11603 WARN_ON(!in_interrupt());
11604
11605 if (crtc == NULL)
11606 return;
11607
11608 spin_lock(&dev->event_lock);
11609 work = intel_crtc->flip_work;
11610
11611 if (work != NULL && !is_mmio_work(work) &&
11612 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11613 WARN_ONCE(1,
11614 "Kicking stuck page flip: queued at %d, now %d\n",
11615 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11616 page_flip_completed(intel_crtc);
11617 work = NULL;
11618 }
11619
11620 if (work != NULL && !is_mmio_work(work) &&
11621 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11622 intel_queue_rps_boost_for_request(work->flip_queued_req);
11623 spin_unlock(&dev->event_lock);
11624 }
11625
11626 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11627 struct drm_framebuffer *fb,
11628 struct drm_pending_vblank_event *event,
11629 uint32_t page_flip_flags)
11630 {
11631 struct drm_device *dev = crtc->dev;
11632 struct drm_i915_private *dev_priv = dev->dev_private;
11633 struct drm_framebuffer *old_fb = crtc->primary->fb;
11634 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11636 struct drm_plane *primary = crtc->primary;
11637 enum pipe pipe = intel_crtc->pipe;
11638 struct intel_flip_work *work;
11639 struct intel_engine_cs *engine;
11640 bool mmio_flip;
11641 struct drm_i915_gem_request *request = NULL;
11642 int ret;
11643
11644 /*
11645 * drm_mode_page_flip_ioctl() should already catch this, but double
11646 * check to be safe. In the future we may enable pageflipping from
11647 * a disabled primary plane.
11648 */
11649 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11650 return -EBUSY;
11651
11652 /* Can't change pixel format via MI display flips. */
11653 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11654 return -EINVAL;
11655
11656 /*
11657 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11658 * Note that pitch changes could also affect these register.
11659 */
11660 if (INTEL_INFO(dev)->gen > 3 &&
11661 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11662 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11663 return -EINVAL;
11664
11665 if (i915_terminally_wedged(&dev_priv->gpu_error))
11666 goto out_hang;
11667
11668 work = kzalloc(sizeof(*work), GFP_KERNEL);
11669 if (work == NULL)
11670 return -ENOMEM;
11671
11672 work->event = event;
11673 work->crtc = crtc;
11674 work->old_fb = old_fb;
11675 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11676
11677 ret = drm_crtc_vblank_get(crtc);
11678 if (ret)
11679 goto free_work;
11680
11681 /* We borrow the event spin lock for protecting flip_work */
11682 spin_lock_irq(&dev->event_lock);
11683 if (intel_crtc->flip_work) {
11684 /* Before declaring the flip queue wedged, check if
11685 * the hardware completed the operation behind our backs.
11686 */
11687 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11688 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11689 page_flip_completed(intel_crtc);
11690 } else {
11691 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11692 spin_unlock_irq(&dev->event_lock);
11693
11694 drm_crtc_vblank_put(crtc);
11695 kfree(work);
11696 return -EBUSY;
11697 }
11698 }
11699 intel_crtc->flip_work = work;
11700 spin_unlock_irq(&dev->event_lock);
11701
11702 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11703 flush_workqueue(dev_priv->wq);
11704
11705 /* Reference the objects for the scheduled work. */
11706 drm_framebuffer_reference(work->old_fb);
11707 drm_gem_object_reference(&obj->base);
11708
11709 crtc->primary->fb = fb;
11710 update_state_fb(crtc->primary);
11711 intel_fbc_pre_update(intel_crtc);
11712
11713 work->pending_flip_obj = obj;
11714
11715 ret = i915_mutex_lock_interruptible(dev);
11716 if (ret)
11717 goto cleanup;
11718
11719 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11720 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11721 ret = -EIO;
11722 goto cleanup;
11723 }
11724
11725 atomic_inc(&intel_crtc->unpin_work_count);
11726
11727 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11728 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11729
11730 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11731 engine = &dev_priv->engine[BCS];
11732 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11733 /* vlv: DISPLAY_FLIP fails to change tiling */
11734 engine = NULL;
11735 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11736 engine = &dev_priv->engine[BCS];
11737 } else if (INTEL_INFO(dev)->gen >= 7) {
11738 engine = i915_gem_request_get_engine(obj->last_write_req);
11739 if (engine == NULL || engine->id != RCS)
11740 engine = &dev_priv->engine[BCS];
11741 } else {
11742 engine = &dev_priv->engine[RCS];
11743 }
11744
11745 mmio_flip = use_mmio_flip(engine, obj);
11746
11747 /* When using CS flips, we want to emit semaphores between rings.
11748 * However, when using mmio flips we will create a task to do the
11749 * synchronisation, so all we want here is to pin the framebuffer
11750 * into the display plane and skip any waits.
11751 */
11752 if (!mmio_flip) {
11753 ret = i915_gem_object_sync(obj, engine, &request);
11754 if (!ret && !request) {
11755 request = i915_gem_request_alloc(engine, NULL);
11756 ret = PTR_ERR_OR_ZERO(request);
11757 }
11758
11759 if (ret)
11760 goto cleanup_pending;
11761 }
11762
11763 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11764 if (ret)
11765 goto cleanup_pending;
11766
11767 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11768 obj, 0);
11769 work->gtt_offset += intel_crtc->dspaddr_offset;
11770 work->rotation = crtc->primary->state->rotation;
11771
11772 if (mmio_flip) {
11773 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11774
11775 i915_gem_request_assign(&work->flip_queued_req,
11776 obj->last_write_req);
11777
11778 schedule_work(&work->mmio_work);
11779 } else {
11780 i915_gem_request_assign(&work->flip_queued_req, request);
11781 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11782 page_flip_flags);
11783 if (ret)
11784 goto cleanup_unpin;
11785
11786 intel_mark_page_flip_active(intel_crtc, work);
11787
11788 i915_add_request_no_flush(request);
11789 }
11790
11791 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11792 to_intel_plane(primary)->frontbuffer_bit);
11793 mutex_unlock(&dev->struct_mutex);
11794
11795 intel_frontbuffer_flip_prepare(dev,
11796 to_intel_plane(primary)->frontbuffer_bit);
11797
11798 trace_i915_flip_request(intel_crtc->plane, obj);
11799
11800 return 0;
11801
11802 cleanup_unpin:
11803 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11804 cleanup_pending:
11805 if (!IS_ERR_OR_NULL(request))
11806 i915_add_request_no_flush(request);
11807 atomic_dec(&intel_crtc->unpin_work_count);
11808 mutex_unlock(&dev->struct_mutex);
11809 cleanup:
11810 crtc->primary->fb = old_fb;
11811 update_state_fb(crtc->primary);
11812
11813 drm_gem_object_unreference_unlocked(&obj->base);
11814 drm_framebuffer_unreference(work->old_fb);
11815
11816 spin_lock_irq(&dev->event_lock);
11817 intel_crtc->flip_work = NULL;
11818 spin_unlock_irq(&dev->event_lock);
11819
11820 drm_crtc_vblank_put(crtc);
11821 free_work:
11822 kfree(work);
11823
11824 if (ret == -EIO) {
11825 struct drm_atomic_state *state;
11826 struct drm_plane_state *plane_state;
11827
11828 out_hang:
11829 state = drm_atomic_state_alloc(dev);
11830 if (!state)
11831 return -ENOMEM;
11832 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11833
11834 retry:
11835 plane_state = drm_atomic_get_plane_state(state, primary);
11836 ret = PTR_ERR_OR_ZERO(plane_state);
11837 if (!ret) {
11838 drm_atomic_set_fb_for_plane(plane_state, fb);
11839
11840 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11841 if (!ret)
11842 ret = drm_atomic_commit(state);
11843 }
11844
11845 if (ret == -EDEADLK) {
11846 drm_modeset_backoff(state->acquire_ctx);
11847 drm_atomic_state_clear(state);
11848 goto retry;
11849 }
11850
11851 if (ret)
11852 drm_atomic_state_free(state);
11853
11854 if (ret == 0 && event) {
11855 spin_lock_irq(&dev->event_lock);
11856 drm_crtc_send_vblank_event(crtc, event);
11857 spin_unlock_irq(&dev->event_lock);
11858 }
11859 }
11860 return ret;
11861 }
11862
11863
11864 /**
11865 * intel_wm_need_update - Check whether watermarks need updating
11866 * @plane: drm plane
11867 * @state: new plane state
11868 *
11869 * Check current plane state versus the new one to determine whether
11870 * watermarks need to be recalculated.
11871 *
11872 * Returns true or false.
11873 */
11874 static bool intel_wm_need_update(struct drm_plane *plane,
11875 struct drm_plane_state *state)
11876 {
11877 struct intel_plane_state *new = to_intel_plane_state(state);
11878 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11879
11880 /* Update watermarks on tiling or size changes. */
11881 if (new->visible != cur->visible)
11882 return true;
11883
11884 if (!cur->base.fb || !new->base.fb)
11885 return false;
11886
11887 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11888 cur->base.rotation != new->base.rotation ||
11889 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11890 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11891 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11892 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11893 return true;
11894
11895 return false;
11896 }
11897
11898 static bool needs_scaling(struct intel_plane_state *state)
11899 {
11900 int src_w = drm_rect_width(&state->src) >> 16;
11901 int src_h = drm_rect_height(&state->src) >> 16;
11902 int dst_w = drm_rect_width(&state->dst);
11903 int dst_h = drm_rect_height(&state->dst);
11904
11905 return (src_w != dst_w || src_h != dst_h);
11906 }
11907
11908 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11909 struct drm_plane_state *plane_state)
11910 {
11911 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11912 struct drm_crtc *crtc = crtc_state->crtc;
11913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11914 struct drm_plane *plane = plane_state->plane;
11915 struct drm_device *dev = crtc->dev;
11916 struct drm_i915_private *dev_priv = to_i915(dev);
11917 struct intel_plane_state *old_plane_state =
11918 to_intel_plane_state(plane->state);
11919 bool mode_changed = needs_modeset(crtc_state);
11920 bool was_crtc_enabled = crtc->state->active;
11921 bool is_crtc_enabled = crtc_state->active;
11922 bool turn_off, turn_on, visible, was_visible;
11923 struct drm_framebuffer *fb = plane_state->fb;
11924 int ret;
11925
11926 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11927 plane->type != DRM_PLANE_TYPE_CURSOR) {
11928 ret = skl_update_scaler_plane(
11929 to_intel_crtc_state(crtc_state),
11930 to_intel_plane_state(plane_state));
11931 if (ret)
11932 return ret;
11933 }
11934
11935 was_visible = old_plane_state->visible;
11936 visible = to_intel_plane_state(plane_state)->visible;
11937
11938 if (!was_crtc_enabled && WARN_ON(was_visible))
11939 was_visible = false;
11940
11941 /*
11942 * Visibility is calculated as if the crtc was on, but
11943 * after scaler setup everything depends on it being off
11944 * when the crtc isn't active.
11945 *
11946 * FIXME this is wrong for watermarks. Watermarks should also
11947 * be computed as if the pipe would be active. Perhaps move
11948 * per-plane wm computation to the .check_plane() hook, and
11949 * only combine the results from all planes in the current place?
11950 */
11951 if (!is_crtc_enabled)
11952 to_intel_plane_state(plane_state)->visible = visible = false;
11953
11954 if (!was_visible && !visible)
11955 return 0;
11956
11957 if (fb != old_plane_state->base.fb)
11958 pipe_config->fb_changed = true;
11959
11960 turn_off = was_visible && (!visible || mode_changed);
11961 turn_on = visible && (!was_visible || mode_changed);
11962
11963 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11964 intel_crtc->base.base.id,
11965 intel_crtc->base.name,
11966 plane->base.id, plane->name,
11967 fb ? fb->base.id : -1);
11968
11969 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11970 plane->base.id, plane->name,
11971 was_visible, visible,
11972 turn_off, turn_on, mode_changed);
11973
11974 if (turn_on) {
11975 pipe_config->update_wm_pre = true;
11976
11977 /* must disable cxsr around plane enable/disable */
11978 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11979 pipe_config->disable_cxsr = true;
11980 } else if (turn_off) {
11981 pipe_config->update_wm_post = true;
11982
11983 /* must disable cxsr around plane enable/disable */
11984 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11985 pipe_config->disable_cxsr = true;
11986 } else if (intel_wm_need_update(plane, plane_state)) {
11987 /* FIXME bollocks */
11988 pipe_config->update_wm_pre = true;
11989 pipe_config->update_wm_post = true;
11990 }
11991
11992 /* Pre-gen9 platforms need two-step watermark updates */
11993 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11994 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11995 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11996
11997 if (visible || was_visible)
11998 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11999
12000 /*
12001 * WaCxSRDisabledForSpriteScaling:ivb
12002 *
12003 * cstate->update_wm was already set above, so this flag will
12004 * take effect when we commit and program watermarks.
12005 */
12006 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12007 needs_scaling(to_intel_plane_state(plane_state)) &&
12008 !needs_scaling(old_plane_state))
12009 pipe_config->disable_lp_wm = true;
12010
12011 return 0;
12012 }
12013
12014 static bool encoders_cloneable(const struct intel_encoder *a,
12015 const struct intel_encoder *b)
12016 {
12017 /* masks could be asymmetric, so check both ways */
12018 return a == b || (a->cloneable & (1 << b->type) &&
12019 b->cloneable & (1 << a->type));
12020 }
12021
12022 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12023 struct intel_crtc *crtc,
12024 struct intel_encoder *encoder)
12025 {
12026 struct intel_encoder *source_encoder;
12027 struct drm_connector *connector;
12028 struct drm_connector_state *connector_state;
12029 int i;
12030
12031 for_each_connector_in_state(state, connector, connector_state, i) {
12032 if (connector_state->crtc != &crtc->base)
12033 continue;
12034
12035 source_encoder =
12036 to_intel_encoder(connector_state->best_encoder);
12037 if (!encoders_cloneable(encoder, source_encoder))
12038 return false;
12039 }
12040
12041 return true;
12042 }
12043
12044 static bool check_encoder_cloning(struct drm_atomic_state *state,
12045 struct intel_crtc *crtc)
12046 {
12047 struct intel_encoder *encoder;
12048 struct drm_connector *connector;
12049 struct drm_connector_state *connector_state;
12050 int i;
12051
12052 for_each_connector_in_state(state, connector, connector_state, i) {
12053 if (connector_state->crtc != &crtc->base)
12054 continue;
12055
12056 encoder = to_intel_encoder(connector_state->best_encoder);
12057 if (!check_single_encoder_cloning(state, crtc, encoder))
12058 return false;
12059 }
12060
12061 return true;
12062 }
12063
12064 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12065 struct drm_crtc_state *crtc_state)
12066 {
12067 struct drm_device *dev = crtc->dev;
12068 struct drm_i915_private *dev_priv = dev->dev_private;
12069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12070 struct intel_crtc_state *pipe_config =
12071 to_intel_crtc_state(crtc_state);
12072 struct drm_atomic_state *state = crtc_state->state;
12073 int ret;
12074 bool mode_changed = needs_modeset(crtc_state);
12075
12076 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12077 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12078 return -EINVAL;
12079 }
12080
12081 if (mode_changed && !crtc_state->active)
12082 pipe_config->update_wm_post = true;
12083
12084 if (mode_changed && crtc_state->enable &&
12085 dev_priv->display.crtc_compute_clock &&
12086 !WARN_ON(pipe_config->shared_dpll)) {
12087 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12088 pipe_config);
12089 if (ret)
12090 return ret;
12091 }
12092
12093 if (crtc_state->color_mgmt_changed) {
12094 ret = intel_color_check(crtc, crtc_state);
12095 if (ret)
12096 return ret;
12097 }
12098
12099 ret = 0;
12100 if (dev_priv->display.compute_pipe_wm) {
12101 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12102 if (ret) {
12103 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12104 return ret;
12105 }
12106 }
12107
12108 if (dev_priv->display.compute_intermediate_wm &&
12109 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12110 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12111 return 0;
12112
12113 /*
12114 * Calculate 'intermediate' watermarks that satisfy both the
12115 * old state and the new state. We can program these
12116 * immediately.
12117 */
12118 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12119 intel_crtc,
12120 pipe_config);
12121 if (ret) {
12122 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12123 return ret;
12124 }
12125 } else if (dev_priv->display.compute_intermediate_wm) {
12126 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12127 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12128 }
12129
12130 if (INTEL_INFO(dev)->gen >= 9) {
12131 if (mode_changed)
12132 ret = skl_update_scaler_crtc(pipe_config);
12133
12134 if (!ret)
12135 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12136 pipe_config);
12137 }
12138
12139 return ret;
12140 }
12141
12142 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12143 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12144 .atomic_begin = intel_begin_crtc_commit,
12145 .atomic_flush = intel_finish_crtc_commit,
12146 .atomic_check = intel_crtc_atomic_check,
12147 };
12148
12149 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12150 {
12151 struct intel_connector *connector;
12152
12153 for_each_intel_connector(dev, connector) {
12154 if (connector->base.state->crtc)
12155 drm_connector_unreference(&connector->base);
12156
12157 if (connector->base.encoder) {
12158 connector->base.state->best_encoder =
12159 connector->base.encoder;
12160 connector->base.state->crtc =
12161 connector->base.encoder->crtc;
12162
12163 drm_connector_reference(&connector->base);
12164 } else {
12165 connector->base.state->best_encoder = NULL;
12166 connector->base.state->crtc = NULL;
12167 }
12168 }
12169 }
12170
12171 static void
12172 connected_sink_compute_bpp(struct intel_connector *connector,
12173 struct intel_crtc_state *pipe_config)
12174 {
12175 int bpp = pipe_config->pipe_bpp;
12176
12177 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12178 connector->base.base.id,
12179 connector->base.name);
12180
12181 /* Don't use an invalid EDID bpc value */
12182 if (connector->base.display_info.bpc &&
12183 connector->base.display_info.bpc * 3 < bpp) {
12184 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12185 bpp, connector->base.display_info.bpc*3);
12186 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12187 }
12188
12189 /* Clamp bpp to default limit on screens without EDID 1.4 */
12190 if (connector->base.display_info.bpc == 0) {
12191 int type = connector->base.connector_type;
12192 int clamp_bpp = 24;
12193
12194 /* Fall back to 18 bpp when DP sink capability is unknown. */
12195 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12196 type == DRM_MODE_CONNECTOR_eDP)
12197 clamp_bpp = 18;
12198
12199 if (bpp > clamp_bpp) {
12200 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12201 bpp, clamp_bpp);
12202 pipe_config->pipe_bpp = clamp_bpp;
12203 }
12204 }
12205 }
12206
12207 static int
12208 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12209 struct intel_crtc_state *pipe_config)
12210 {
12211 struct drm_device *dev = crtc->base.dev;
12212 struct drm_atomic_state *state;
12213 struct drm_connector *connector;
12214 struct drm_connector_state *connector_state;
12215 int bpp, i;
12216
12217 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12218 bpp = 10*3;
12219 else if (INTEL_INFO(dev)->gen >= 5)
12220 bpp = 12*3;
12221 else
12222 bpp = 8*3;
12223
12224
12225 pipe_config->pipe_bpp = bpp;
12226
12227 state = pipe_config->base.state;
12228
12229 /* Clamp display bpp to EDID value */
12230 for_each_connector_in_state(state, connector, connector_state, i) {
12231 if (connector_state->crtc != &crtc->base)
12232 continue;
12233
12234 connected_sink_compute_bpp(to_intel_connector(connector),
12235 pipe_config);
12236 }
12237
12238 return bpp;
12239 }
12240
12241 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12242 {
12243 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12244 "type: 0x%x flags: 0x%x\n",
12245 mode->crtc_clock,
12246 mode->crtc_hdisplay, mode->crtc_hsync_start,
12247 mode->crtc_hsync_end, mode->crtc_htotal,
12248 mode->crtc_vdisplay, mode->crtc_vsync_start,
12249 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12250 }
12251
12252 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12253 struct intel_crtc_state *pipe_config,
12254 const char *context)
12255 {
12256 struct drm_device *dev = crtc->base.dev;
12257 struct drm_plane *plane;
12258 struct intel_plane *intel_plane;
12259 struct intel_plane_state *state;
12260 struct drm_framebuffer *fb;
12261
12262 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12263 crtc->base.base.id, crtc->base.name,
12264 context, pipe_config, pipe_name(crtc->pipe));
12265
12266 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12267 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12268 pipe_config->pipe_bpp, pipe_config->dither);
12269 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12270 pipe_config->has_pch_encoder,
12271 pipe_config->fdi_lanes,
12272 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12273 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12274 pipe_config->fdi_m_n.tu);
12275 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12276 pipe_config->has_dp_encoder,
12277 pipe_config->lane_count,
12278 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12279 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12280 pipe_config->dp_m_n.tu);
12281
12282 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12283 pipe_config->has_dp_encoder,
12284 pipe_config->lane_count,
12285 pipe_config->dp_m2_n2.gmch_m,
12286 pipe_config->dp_m2_n2.gmch_n,
12287 pipe_config->dp_m2_n2.link_m,
12288 pipe_config->dp_m2_n2.link_n,
12289 pipe_config->dp_m2_n2.tu);
12290
12291 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12292 pipe_config->has_audio,
12293 pipe_config->has_infoframe);
12294
12295 DRM_DEBUG_KMS("requested mode:\n");
12296 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12297 DRM_DEBUG_KMS("adjusted mode:\n");
12298 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12299 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12300 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12301 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12302 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12303 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12304 crtc->num_scalers,
12305 pipe_config->scaler_state.scaler_users,
12306 pipe_config->scaler_state.scaler_id);
12307 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12308 pipe_config->gmch_pfit.control,
12309 pipe_config->gmch_pfit.pgm_ratios,
12310 pipe_config->gmch_pfit.lvds_border_bits);
12311 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12312 pipe_config->pch_pfit.pos,
12313 pipe_config->pch_pfit.size,
12314 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12315 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12316 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12317
12318 if (IS_BROXTON(dev)) {
12319 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12320 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12321 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12322 pipe_config->ddi_pll_sel,
12323 pipe_config->dpll_hw_state.ebb0,
12324 pipe_config->dpll_hw_state.ebb4,
12325 pipe_config->dpll_hw_state.pll0,
12326 pipe_config->dpll_hw_state.pll1,
12327 pipe_config->dpll_hw_state.pll2,
12328 pipe_config->dpll_hw_state.pll3,
12329 pipe_config->dpll_hw_state.pll6,
12330 pipe_config->dpll_hw_state.pll8,
12331 pipe_config->dpll_hw_state.pll9,
12332 pipe_config->dpll_hw_state.pll10,
12333 pipe_config->dpll_hw_state.pcsdw12);
12334 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12335 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12336 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12337 pipe_config->ddi_pll_sel,
12338 pipe_config->dpll_hw_state.ctrl1,
12339 pipe_config->dpll_hw_state.cfgcr1,
12340 pipe_config->dpll_hw_state.cfgcr2);
12341 } else if (HAS_DDI(dev)) {
12342 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12343 pipe_config->ddi_pll_sel,
12344 pipe_config->dpll_hw_state.wrpll,
12345 pipe_config->dpll_hw_state.spll);
12346 } else {
12347 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12348 "fp0: 0x%x, fp1: 0x%x\n",
12349 pipe_config->dpll_hw_state.dpll,
12350 pipe_config->dpll_hw_state.dpll_md,
12351 pipe_config->dpll_hw_state.fp0,
12352 pipe_config->dpll_hw_state.fp1);
12353 }
12354
12355 DRM_DEBUG_KMS("planes on this crtc\n");
12356 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12357 intel_plane = to_intel_plane(plane);
12358 if (intel_plane->pipe != crtc->pipe)
12359 continue;
12360
12361 state = to_intel_plane_state(plane->state);
12362 fb = state->base.fb;
12363 if (!fb) {
12364 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12365 plane->base.id, plane->name, state->scaler_id);
12366 continue;
12367 }
12368
12369 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12370 plane->base.id, plane->name);
12371 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12372 fb->base.id, fb->width, fb->height,
12373 drm_get_format_name(fb->pixel_format));
12374 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12375 state->scaler_id,
12376 state->src.x1 >> 16, state->src.y1 >> 16,
12377 drm_rect_width(&state->src) >> 16,
12378 drm_rect_height(&state->src) >> 16,
12379 state->dst.x1, state->dst.y1,
12380 drm_rect_width(&state->dst),
12381 drm_rect_height(&state->dst));
12382 }
12383 }
12384
12385 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12386 {
12387 struct drm_device *dev = state->dev;
12388 struct drm_connector *connector;
12389 unsigned int used_ports = 0;
12390
12391 /*
12392 * Walk the connector list instead of the encoder
12393 * list to detect the problem on ddi platforms
12394 * where there's just one encoder per digital port.
12395 */
12396 drm_for_each_connector(connector, dev) {
12397 struct drm_connector_state *connector_state;
12398 struct intel_encoder *encoder;
12399
12400 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12401 if (!connector_state)
12402 connector_state = connector->state;
12403
12404 if (!connector_state->best_encoder)
12405 continue;
12406
12407 encoder = to_intel_encoder(connector_state->best_encoder);
12408
12409 WARN_ON(!connector_state->crtc);
12410
12411 switch (encoder->type) {
12412 unsigned int port_mask;
12413 case INTEL_OUTPUT_UNKNOWN:
12414 if (WARN_ON(!HAS_DDI(dev)))
12415 break;
12416 case INTEL_OUTPUT_DISPLAYPORT:
12417 case INTEL_OUTPUT_HDMI:
12418 case INTEL_OUTPUT_EDP:
12419 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12420
12421 /* the same port mustn't appear more than once */
12422 if (used_ports & port_mask)
12423 return false;
12424
12425 used_ports |= port_mask;
12426 default:
12427 break;
12428 }
12429 }
12430
12431 return true;
12432 }
12433
12434 static void
12435 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12436 {
12437 struct drm_crtc_state tmp_state;
12438 struct intel_crtc_scaler_state scaler_state;
12439 struct intel_dpll_hw_state dpll_hw_state;
12440 struct intel_shared_dpll *shared_dpll;
12441 uint32_t ddi_pll_sel;
12442 bool force_thru;
12443
12444 /* FIXME: before the switch to atomic started, a new pipe_config was
12445 * kzalloc'd. Code that depends on any field being zero should be
12446 * fixed, so that the crtc_state can be safely duplicated. For now,
12447 * only fields that are know to not cause problems are preserved. */
12448
12449 tmp_state = crtc_state->base;
12450 scaler_state = crtc_state->scaler_state;
12451 shared_dpll = crtc_state->shared_dpll;
12452 dpll_hw_state = crtc_state->dpll_hw_state;
12453 ddi_pll_sel = crtc_state->ddi_pll_sel;
12454 force_thru = crtc_state->pch_pfit.force_thru;
12455
12456 memset(crtc_state, 0, sizeof *crtc_state);
12457
12458 crtc_state->base = tmp_state;
12459 crtc_state->scaler_state = scaler_state;
12460 crtc_state->shared_dpll = shared_dpll;
12461 crtc_state->dpll_hw_state = dpll_hw_state;
12462 crtc_state->ddi_pll_sel = ddi_pll_sel;
12463 crtc_state->pch_pfit.force_thru = force_thru;
12464 }
12465
12466 static int
12467 intel_modeset_pipe_config(struct drm_crtc *crtc,
12468 struct intel_crtc_state *pipe_config)
12469 {
12470 struct drm_atomic_state *state = pipe_config->base.state;
12471 struct intel_encoder *encoder;
12472 struct drm_connector *connector;
12473 struct drm_connector_state *connector_state;
12474 int base_bpp, ret = -EINVAL;
12475 int i;
12476 bool retry = true;
12477
12478 clear_intel_crtc_state(pipe_config);
12479
12480 pipe_config->cpu_transcoder =
12481 (enum transcoder) to_intel_crtc(crtc)->pipe;
12482
12483 /*
12484 * Sanitize sync polarity flags based on requested ones. If neither
12485 * positive or negative polarity is requested, treat this as meaning
12486 * negative polarity.
12487 */
12488 if (!(pipe_config->base.adjusted_mode.flags &
12489 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12490 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12491
12492 if (!(pipe_config->base.adjusted_mode.flags &
12493 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12494 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12495
12496 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12497 pipe_config);
12498 if (base_bpp < 0)
12499 goto fail;
12500
12501 /*
12502 * Determine the real pipe dimensions. Note that stereo modes can
12503 * increase the actual pipe size due to the frame doubling and
12504 * insertion of additional space for blanks between the frame. This
12505 * is stored in the crtc timings. We use the requested mode to do this
12506 * computation to clearly distinguish it from the adjusted mode, which
12507 * can be changed by the connectors in the below retry loop.
12508 */
12509 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12510 &pipe_config->pipe_src_w,
12511 &pipe_config->pipe_src_h);
12512
12513 encoder_retry:
12514 /* Ensure the port clock defaults are reset when retrying. */
12515 pipe_config->port_clock = 0;
12516 pipe_config->pixel_multiplier = 1;
12517
12518 /* Fill in default crtc timings, allow encoders to overwrite them. */
12519 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12520 CRTC_STEREO_DOUBLE);
12521
12522 /* Pass our mode to the connectors and the CRTC to give them a chance to
12523 * adjust it according to limitations or connector properties, and also
12524 * a chance to reject the mode entirely.
12525 */
12526 for_each_connector_in_state(state, connector, connector_state, i) {
12527 if (connector_state->crtc != crtc)
12528 continue;
12529
12530 encoder = to_intel_encoder(connector_state->best_encoder);
12531
12532 if (!(encoder->compute_config(encoder, pipe_config))) {
12533 DRM_DEBUG_KMS("Encoder config failure\n");
12534 goto fail;
12535 }
12536 }
12537
12538 /* Set default port clock if not overwritten by the encoder. Needs to be
12539 * done afterwards in case the encoder adjusts the mode. */
12540 if (!pipe_config->port_clock)
12541 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12542 * pipe_config->pixel_multiplier;
12543
12544 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12545 if (ret < 0) {
12546 DRM_DEBUG_KMS("CRTC fixup failed\n");
12547 goto fail;
12548 }
12549
12550 if (ret == RETRY) {
12551 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12552 ret = -EINVAL;
12553 goto fail;
12554 }
12555
12556 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12557 retry = false;
12558 goto encoder_retry;
12559 }
12560
12561 /* Dithering seems to not pass-through bits correctly when it should, so
12562 * only enable it on 6bpc panels. */
12563 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12564 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12565 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12566
12567 fail:
12568 return ret;
12569 }
12570
12571 static void
12572 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12573 {
12574 struct drm_crtc *crtc;
12575 struct drm_crtc_state *crtc_state;
12576 int i;
12577
12578 /* Double check state. */
12579 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12580 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12581
12582 /* Update hwmode for vblank functions */
12583 if (crtc->state->active)
12584 crtc->hwmode = crtc->state->adjusted_mode;
12585 else
12586 crtc->hwmode.crtc_clock = 0;
12587
12588 /*
12589 * Update legacy state to satisfy fbc code. This can
12590 * be removed when fbc uses the atomic state.
12591 */
12592 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12593 struct drm_plane_state *plane_state = crtc->primary->state;
12594
12595 crtc->primary->fb = plane_state->fb;
12596 crtc->x = plane_state->src_x >> 16;
12597 crtc->y = plane_state->src_y >> 16;
12598 }
12599 }
12600 }
12601
12602 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12603 {
12604 int diff;
12605
12606 if (clock1 == clock2)
12607 return true;
12608
12609 if (!clock1 || !clock2)
12610 return false;
12611
12612 diff = abs(clock1 - clock2);
12613
12614 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12615 return true;
12616
12617 return false;
12618 }
12619
12620 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12621 list_for_each_entry((intel_crtc), \
12622 &(dev)->mode_config.crtc_list, \
12623 base.head) \
12624 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12625
12626 static bool
12627 intel_compare_m_n(unsigned int m, unsigned int n,
12628 unsigned int m2, unsigned int n2,
12629 bool exact)
12630 {
12631 if (m == m2 && n == n2)
12632 return true;
12633
12634 if (exact || !m || !n || !m2 || !n2)
12635 return false;
12636
12637 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12638
12639 if (n > n2) {
12640 while (n > n2) {
12641 m2 <<= 1;
12642 n2 <<= 1;
12643 }
12644 } else if (n < n2) {
12645 while (n < n2) {
12646 m <<= 1;
12647 n <<= 1;
12648 }
12649 }
12650
12651 if (n != n2)
12652 return false;
12653
12654 return intel_fuzzy_clock_check(m, m2);
12655 }
12656
12657 static bool
12658 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12659 struct intel_link_m_n *m2_n2,
12660 bool adjust)
12661 {
12662 if (m_n->tu == m2_n2->tu &&
12663 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12664 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12665 intel_compare_m_n(m_n->link_m, m_n->link_n,
12666 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12667 if (adjust)
12668 *m2_n2 = *m_n;
12669
12670 return true;
12671 }
12672
12673 return false;
12674 }
12675
12676 static bool
12677 intel_pipe_config_compare(struct drm_device *dev,
12678 struct intel_crtc_state *current_config,
12679 struct intel_crtc_state *pipe_config,
12680 bool adjust)
12681 {
12682 bool ret = true;
12683
12684 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12685 do { \
12686 if (!adjust) \
12687 DRM_ERROR(fmt, ##__VA_ARGS__); \
12688 else \
12689 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12690 } while (0)
12691
12692 #define PIPE_CONF_CHECK_X(name) \
12693 if (current_config->name != pipe_config->name) { \
12694 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12695 "(expected 0x%08x, found 0x%08x)\n", \
12696 current_config->name, \
12697 pipe_config->name); \
12698 ret = false; \
12699 }
12700
12701 #define PIPE_CONF_CHECK_I(name) \
12702 if (current_config->name != pipe_config->name) { \
12703 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12704 "(expected %i, found %i)\n", \
12705 current_config->name, \
12706 pipe_config->name); \
12707 ret = false; \
12708 }
12709
12710 #define PIPE_CONF_CHECK_P(name) \
12711 if (current_config->name != pipe_config->name) { \
12712 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12713 "(expected %p, found %p)\n", \
12714 current_config->name, \
12715 pipe_config->name); \
12716 ret = false; \
12717 }
12718
12719 #define PIPE_CONF_CHECK_M_N(name) \
12720 if (!intel_compare_link_m_n(&current_config->name, \
12721 &pipe_config->name,\
12722 adjust)) { \
12723 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12724 "(expected tu %i gmch %i/%i link %i/%i, " \
12725 "found tu %i, gmch %i/%i link %i/%i)\n", \
12726 current_config->name.tu, \
12727 current_config->name.gmch_m, \
12728 current_config->name.gmch_n, \
12729 current_config->name.link_m, \
12730 current_config->name.link_n, \
12731 pipe_config->name.tu, \
12732 pipe_config->name.gmch_m, \
12733 pipe_config->name.gmch_n, \
12734 pipe_config->name.link_m, \
12735 pipe_config->name.link_n); \
12736 ret = false; \
12737 }
12738
12739 /* This is required for BDW+ where there is only one set of registers for
12740 * switching between high and low RR.
12741 * This macro can be used whenever a comparison has to be made between one
12742 * hw state and multiple sw state variables.
12743 */
12744 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12745 if (!intel_compare_link_m_n(&current_config->name, \
12746 &pipe_config->name, adjust) && \
12747 !intel_compare_link_m_n(&current_config->alt_name, \
12748 &pipe_config->name, adjust)) { \
12749 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12750 "(expected tu %i gmch %i/%i link %i/%i, " \
12751 "or tu %i gmch %i/%i link %i/%i, " \
12752 "found tu %i, gmch %i/%i link %i/%i)\n", \
12753 current_config->name.tu, \
12754 current_config->name.gmch_m, \
12755 current_config->name.gmch_n, \
12756 current_config->name.link_m, \
12757 current_config->name.link_n, \
12758 current_config->alt_name.tu, \
12759 current_config->alt_name.gmch_m, \
12760 current_config->alt_name.gmch_n, \
12761 current_config->alt_name.link_m, \
12762 current_config->alt_name.link_n, \
12763 pipe_config->name.tu, \
12764 pipe_config->name.gmch_m, \
12765 pipe_config->name.gmch_n, \
12766 pipe_config->name.link_m, \
12767 pipe_config->name.link_n); \
12768 ret = false; \
12769 }
12770
12771 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12772 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12773 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12774 "(expected %i, found %i)\n", \
12775 current_config->name & (mask), \
12776 pipe_config->name & (mask)); \
12777 ret = false; \
12778 }
12779
12780 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12781 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12782 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12783 "(expected %i, found %i)\n", \
12784 current_config->name, \
12785 pipe_config->name); \
12786 ret = false; \
12787 }
12788
12789 #define PIPE_CONF_QUIRK(quirk) \
12790 ((current_config->quirks | pipe_config->quirks) & (quirk))
12791
12792 PIPE_CONF_CHECK_I(cpu_transcoder);
12793
12794 PIPE_CONF_CHECK_I(has_pch_encoder);
12795 PIPE_CONF_CHECK_I(fdi_lanes);
12796 PIPE_CONF_CHECK_M_N(fdi_m_n);
12797
12798 PIPE_CONF_CHECK_I(has_dp_encoder);
12799 PIPE_CONF_CHECK_I(lane_count);
12800 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12801
12802 if (INTEL_INFO(dev)->gen < 8) {
12803 PIPE_CONF_CHECK_M_N(dp_m_n);
12804
12805 if (current_config->has_drrs)
12806 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12807 } else
12808 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12809
12810 PIPE_CONF_CHECK_I(has_dsi_encoder);
12811
12812 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12813 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12814 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12815 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12816 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12817 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12818
12819 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12820 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12821 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12822 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12823 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12824 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12825
12826 PIPE_CONF_CHECK_I(pixel_multiplier);
12827 PIPE_CONF_CHECK_I(has_hdmi_sink);
12828 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12829 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12830 PIPE_CONF_CHECK_I(limited_color_range);
12831 PIPE_CONF_CHECK_I(has_infoframe);
12832
12833 PIPE_CONF_CHECK_I(has_audio);
12834
12835 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12836 DRM_MODE_FLAG_INTERLACE);
12837
12838 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12839 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12840 DRM_MODE_FLAG_PHSYNC);
12841 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12842 DRM_MODE_FLAG_NHSYNC);
12843 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12844 DRM_MODE_FLAG_PVSYNC);
12845 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12846 DRM_MODE_FLAG_NVSYNC);
12847 }
12848
12849 PIPE_CONF_CHECK_X(gmch_pfit.control);
12850 /* pfit ratios are autocomputed by the hw on gen4+ */
12851 if (INTEL_INFO(dev)->gen < 4)
12852 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12853 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12854
12855 if (!adjust) {
12856 PIPE_CONF_CHECK_I(pipe_src_w);
12857 PIPE_CONF_CHECK_I(pipe_src_h);
12858
12859 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12860 if (current_config->pch_pfit.enabled) {
12861 PIPE_CONF_CHECK_X(pch_pfit.pos);
12862 PIPE_CONF_CHECK_X(pch_pfit.size);
12863 }
12864
12865 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12866 }
12867
12868 /* BDW+ don't expose a synchronous way to read the state */
12869 if (IS_HASWELL(dev))
12870 PIPE_CONF_CHECK_I(ips_enabled);
12871
12872 PIPE_CONF_CHECK_I(double_wide);
12873
12874 PIPE_CONF_CHECK_X(ddi_pll_sel);
12875
12876 PIPE_CONF_CHECK_P(shared_dpll);
12877 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12878 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12879 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12880 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12881 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12882 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12883 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12884 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12885 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12886
12887 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12888 PIPE_CONF_CHECK_X(dsi_pll.div);
12889
12890 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12891 PIPE_CONF_CHECK_I(pipe_bpp);
12892
12893 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12894 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12895
12896 #undef PIPE_CONF_CHECK_X
12897 #undef PIPE_CONF_CHECK_I
12898 #undef PIPE_CONF_CHECK_P
12899 #undef PIPE_CONF_CHECK_FLAGS
12900 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12901 #undef PIPE_CONF_QUIRK
12902 #undef INTEL_ERR_OR_DBG_KMS
12903
12904 return ret;
12905 }
12906
12907 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12908 const struct intel_crtc_state *pipe_config)
12909 {
12910 if (pipe_config->has_pch_encoder) {
12911 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12912 &pipe_config->fdi_m_n);
12913 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12914
12915 /*
12916 * FDI already provided one idea for the dotclock.
12917 * Yell if the encoder disagrees.
12918 */
12919 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12920 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12921 fdi_dotclock, dotclock);
12922 }
12923 }
12924
12925 static void verify_wm_state(struct drm_crtc *crtc,
12926 struct drm_crtc_state *new_state)
12927 {
12928 struct drm_device *dev = crtc->dev;
12929 struct drm_i915_private *dev_priv = dev->dev_private;
12930 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12931 struct skl_ddb_entry *hw_entry, *sw_entry;
12932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12933 const enum pipe pipe = intel_crtc->pipe;
12934 int plane;
12935
12936 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12937 return;
12938
12939 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12940 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12941
12942 /* planes */
12943 for_each_plane(dev_priv, pipe, plane) {
12944 hw_entry = &hw_ddb.plane[pipe][plane];
12945 sw_entry = &sw_ddb->plane[pipe][plane];
12946
12947 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12948 continue;
12949
12950 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12951 "(expected (%u,%u), found (%u,%u))\n",
12952 pipe_name(pipe), plane + 1,
12953 sw_entry->start, sw_entry->end,
12954 hw_entry->start, hw_entry->end);
12955 }
12956
12957 /* cursor */
12958 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12959 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12960
12961 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12962 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12963 "(expected (%u,%u), found (%u,%u))\n",
12964 pipe_name(pipe),
12965 sw_entry->start, sw_entry->end,
12966 hw_entry->start, hw_entry->end);
12967 }
12968 }
12969
12970 static void
12971 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12972 {
12973 struct drm_connector *connector;
12974
12975 drm_for_each_connector(connector, dev) {
12976 struct drm_encoder *encoder = connector->encoder;
12977 struct drm_connector_state *state = connector->state;
12978
12979 if (state->crtc != crtc)
12980 continue;
12981
12982 intel_connector_verify_state(to_intel_connector(connector));
12983
12984 I915_STATE_WARN(state->best_encoder != encoder,
12985 "connector's atomic encoder doesn't match legacy encoder\n");
12986 }
12987 }
12988
12989 static void
12990 verify_encoder_state(struct drm_device *dev)
12991 {
12992 struct intel_encoder *encoder;
12993 struct intel_connector *connector;
12994
12995 for_each_intel_encoder(dev, encoder) {
12996 bool enabled = false;
12997 enum pipe pipe;
12998
12999 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13000 encoder->base.base.id,
13001 encoder->base.name);
13002
13003 for_each_intel_connector(dev, connector) {
13004 if (connector->base.state->best_encoder != &encoder->base)
13005 continue;
13006 enabled = true;
13007
13008 I915_STATE_WARN(connector->base.state->crtc !=
13009 encoder->base.crtc,
13010 "connector's crtc doesn't match encoder crtc\n");
13011 }
13012
13013 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13014 "encoder's enabled state mismatch "
13015 "(expected %i, found %i)\n",
13016 !!encoder->base.crtc, enabled);
13017
13018 if (!encoder->base.crtc) {
13019 bool active;
13020
13021 active = encoder->get_hw_state(encoder, &pipe);
13022 I915_STATE_WARN(active,
13023 "encoder detached but still enabled on pipe %c.\n",
13024 pipe_name(pipe));
13025 }
13026 }
13027 }
13028
13029 static void
13030 verify_crtc_state(struct drm_crtc *crtc,
13031 struct drm_crtc_state *old_crtc_state,
13032 struct drm_crtc_state *new_crtc_state)
13033 {
13034 struct drm_device *dev = crtc->dev;
13035 struct drm_i915_private *dev_priv = dev->dev_private;
13036 struct intel_encoder *encoder;
13037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13038 struct intel_crtc_state *pipe_config, *sw_config;
13039 struct drm_atomic_state *old_state;
13040 bool active;
13041
13042 old_state = old_crtc_state->state;
13043 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13044 pipe_config = to_intel_crtc_state(old_crtc_state);
13045 memset(pipe_config, 0, sizeof(*pipe_config));
13046 pipe_config->base.crtc = crtc;
13047 pipe_config->base.state = old_state;
13048
13049 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13050
13051 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13052
13053 /* hw state is inconsistent with the pipe quirk */
13054 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13055 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13056 active = new_crtc_state->active;
13057
13058 I915_STATE_WARN(new_crtc_state->active != active,
13059 "crtc active state doesn't match with hw state "
13060 "(expected %i, found %i)\n", new_crtc_state->active, active);
13061
13062 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13063 "transitional active state does not match atomic hw state "
13064 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13065
13066 for_each_encoder_on_crtc(dev, crtc, encoder) {
13067 enum pipe pipe;
13068
13069 active = encoder->get_hw_state(encoder, &pipe);
13070 I915_STATE_WARN(active != new_crtc_state->active,
13071 "[ENCODER:%i] active %i with crtc active %i\n",
13072 encoder->base.base.id, active, new_crtc_state->active);
13073
13074 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13075 "Encoder connected to wrong pipe %c\n",
13076 pipe_name(pipe));
13077
13078 if (active)
13079 encoder->get_config(encoder, pipe_config);
13080 }
13081
13082 if (!new_crtc_state->active)
13083 return;
13084
13085 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13086
13087 sw_config = to_intel_crtc_state(crtc->state);
13088 if (!intel_pipe_config_compare(dev, sw_config,
13089 pipe_config, false)) {
13090 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13091 intel_dump_pipe_config(intel_crtc, pipe_config,
13092 "[hw state]");
13093 intel_dump_pipe_config(intel_crtc, sw_config,
13094 "[sw state]");
13095 }
13096 }
13097
13098 static void
13099 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13100 struct intel_shared_dpll *pll,
13101 struct drm_crtc *crtc,
13102 struct drm_crtc_state *new_state)
13103 {
13104 struct intel_dpll_hw_state dpll_hw_state;
13105 unsigned crtc_mask;
13106 bool active;
13107
13108 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13109
13110 DRM_DEBUG_KMS("%s\n", pll->name);
13111
13112 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13113
13114 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13115 I915_STATE_WARN(!pll->on && pll->active_mask,
13116 "pll in active use but not on in sw tracking\n");
13117 I915_STATE_WARN(pll->on && !pll->active_mask,
13118 "pll is on but not used by any active crtc\n");
13119 I915_STATE_WARN(pll->on != active,
13120 "pll on state mismatch (expected %i, found %i)\n",
13121 pll->on, active);
13122 }
13123
13124 if (!crtc) {
13125 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13126 "more active pll users than references: %x vs %x\n",
13127 pll->active_mask, pll->config.crtc_mask);
13128
13129 return;
13130 }
13131
13132 crtc_mask = 1 << drm_crtc_index(crtc);
13133
13134 if (new_state->active)
13135 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13136 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13137 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13138 else
13139 I915_STATE_WARN(pll->active_mask & crtc_mask,
13140 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13141 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13142
13143 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13144 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13145 crtc_mask, pll->config.crtc_mask);
13146
13147 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13148 &dpll_hw_state,
13149 sizeof(dpll_hw_state)),
13150 "pll hw state mismatch\n");
13151 }
13152
13153 static void
13154 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13155 struct drm_crtc_state *old_crtc_state,
13156 struct drm_crtc_state *new_crtc_state)
13157 {
13158 struct drm_i915_private *dev_priv = dev->dev_private;
13159 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13160 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13161
13162 if (new_state->shared_dpll)
13163 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13164
13165 if (old_state->shared_dpll &&
13166 old_state->shared_dpll != new_state->shared_dpll) {
13167 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13168 struct intel_shared_dpll *pll = old_state->shared_dpll;
13169
13170 I915_STATE_WARN(pll->active_mask & crtc_mask,
13171 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13172 pipe_name(drm_crtc_index(crtc)));
13173 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13174 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13175 pipe_name(drm_crtc_index(crtc)));
13176 }
13177 }
13178
13179 static void
13180 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13181 struct drm_crtc_state *old_state,
13182 struct drm_crtc_state *new_state)
13183 {
13184 if (!needs_modeset(new_state) &&
13185 !to_intel_crtc_state(new_state)->update_pipe)
13186 return;
13187
13188 verify_wm_state(crtc, new_state);
13189 verify_connector_state(crtc->dev, crtc);
13190 verify_crtc_state(crtc, old_state, new_state);
13191 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13192 }
13193
13194 static void
13195 verify_disabled_dpll_state(struct drm_device *dev)
13196 {
13197 struct drm_i915_private *dev_priv = dev->dev_private;
13198 int i;
13199
13200 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13201 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13202 }
13203
13204 static void
13205 intel_modeset_verify_disabled(struct drm_device *dev)
13206 {
13207 verify_encoder_state(dev);
13208 verify_connector_state(dev, NULL);
13209 verify_disabled_dpll_state(dev);
13210 }
13211
13212 static void update_scanline_offset(struct intel_crtc *crtc)
13213 {
13214 struct drm_device *dev = crtc->base.dev;
13215
13216 /*
13217 * The scanline counter increments at the leading edge of hsync.
13218 *
13219 * On most platforms it starts counting from vtotal-1 on the
13220 * first active line. That means the scanline counter value is
13221 * always one less than what we would expect. Ie. just after
13222 * start of vblank, which also occurs at start of hsync (on the
13223 * last active line), the scanline counter will read vblank_start-1.
13224 *
13225 * On gen2 the scanline counter starts counting from 1 instead
13226 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13227 * to keep the value positive), instead of adding one.
13228 *
13229 * On HSW+ the behaviour of the scanline counter depends on the output
13230 * type. For DP ports it behaves like most other platforms, but on HDMI
13231 * there's an extra 1 line difference. So we need to add two instead of
13232 * one to the value.
13233 */
13234 if (IS_GEN2(dev)) {
13235 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13236 int vtotal;
13237
13238 vtotal = adjusted_mode->crtc_vtotal;
13239 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13240 vtotal /= 2;
13241
13242 crtc->scanline_offset = vtotal - 1;
13243 } else if (HAS_DDI(dev) &&
13244 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13245 crtc->scanline_offset = 2;
13246 } else
13247 crtc->scanline_offset = 1;
13248 }
13249
13250 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13251 {
13252 struct drm_device *dev = state->dev;
13253 struct drm_i915_private *dev_priv = to_i915(dev);
13254 struct intel_shared_dpll_config *shared_dpll = NULL;
13255 struct drm_crtc *crtc;
13256 struct drm_crtc_state *crtc_state;
13257 int i;
13258
13259 if (!dev_priv->display.crtc_compute_clock)
13260 return;
13261
13262 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13264 struct intel_shared_dpll *old_dpll =
13265 to_intel_crtc_state(crtc->state)->shared_dpll;
13266
13267 if (!needs_modeset(crtc_state))
13268 continue;
13269
13270 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13271
13272 if (!old_dpll)
13273 continue;
13274
13275 if (!shared_dpll)
13276 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13277
13278 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13279 }
13280 }
13281
13282 /*
13283 * This implements the workaround described in the "notes" section of the mode
13284 * set sequence documentation. When going from no pipes or single pipe to
13285 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13286 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13287 */
13288 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13289 {
13290 struct drm_crtc_state *crtc_state;
13291 struct intel_crtc *intel_crtc;
13292 struct drm_crtc *crtc;
13293 struct intel_crtc_state *first_crtc_state = NULL;
13294 struct intel_crtc_state *other_crtc_state = NULL;
13295 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13296 int i;
13297
13298 /* look at all crtc's that are going to be enabled in during modeset */
13299 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13300 intel_crtc = to_intel_crtc(crtc);
13301
13302 if (!crtc_state->active || !needs_modeset(crtc_state))
13303 continue;
13304
13305 if (first_crtc_state) {
13306 other_crtc_state = to_intel_crtc_state(crtc_state);
13307 break;
13308 } else {
13309 first_crtc_state = to_intel_crtc_state(crtc_state);
13310 first_pipe = intel_crtc->pipe;
13311 }
13312 }
13313
13314 /* No workaround needed? */
13315 if (!first_crtc_state)
13316 return 0;
13317
13318 /* w/a possibly needed, check how many crtc's are already enabled. */
13319 for_each_intel_crtc(state->dev, intel_crtc) {
13320 struct intel_crtc_state *pipe_config;
13321
13322 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13323 if (IS_ERR(pipe_config))
13324 return PTR_ERR(pipe_config);
13325
13326 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13327
13328 if (!pipe_config->base.active ||
13329 needs_modeset(&pipe_config->base))
13330 continue;
13331
13332 /* 2 or more enabled crtcs means no need for w/a */
13333 if (enabled_pipe != INVALID_PIPE)
13334 return 0;
13335
13336 enabled_pipe = intel_crtc->pipe;
13337 }
13338
13339 if (enabled_pipe != INVALID_PIPE)
13340 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13341 else if (other_crtc_state)
13342 other_crtc_state->hsw_workaround_pipe = first_pipe;
13343
13344 return 0;
13345 }
13346
13347 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13348 {
13349 struct drm_crtc *crtc;
13350 struct drm_crtc_state *crtc_state;
13351 int ret = 0;
13352
13353 /* add all active pipes to the state */
13354 for_each_crtc(state->dev, crtc) {
13355 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13356 if (IS_ERR(crtc_state))
13357 return PTR_ERR(crtc_state);
13358
13359 if (!crtc_state->active || needs_modeset(crtc_state))
13360 continue;
13361
13362 crtc_state->mode_changed = true;
13363
13364 ret = drm_atomic_add_affected_connectors(state, crtc);
13365 if (ret)
13366 break;
13367
13368 ret = drm_atomic_add_affected_planes(state, crtc);
13369 if (ret)
13370 break;
13371 }
13372
13373 return ret;
13374 }
13375
13376 static int intel_modeset_checks(struct drm_atomic_state *state)
13377 {
13378 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13379 struct drm_i915_private *dev_priv = state->dev->dev_private;
13380 struct drm_crtc *crtc;
13381 struct drm_crtc_state *crtc_state;
13382 int ret = 0, i;
13383
13384 if (!check_digital_port_conflicts(state)) {
13385 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13386 return -EINVAL;
13387 }
13388
13389 intel_state->modeset = true;
13390 intel_state->active_crtcs = dev_priv->active_crtcs;
13391
13392 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13393 if (crtc_state->active)
13394 intel_state->active_crtcs |= 1 << i;
13395 else
13396 intel_state->active_crtcs &= ~(1 << i);
13397
13398 if (crtc_state->active != crtc->state->active)
13399 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13400 }
13401
13402 /*
13403 * See if the config requires any additional preparation, e.g.
13404 * to adjust global state with pipes off. We need to do this
13405 * here so we can get the modeset_pipe updated config for the new
13406 * mode set on this crtc. For other crtcs we need to use the
13407 * adjusted_mode bits in the crtc directly.
13408 */
13409 if (dev_priv->display.modeset_calc_cdclk) {
13410 if (!intel_state->cdclk_pll_vco)
13411 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13412 if (!intel_state->cdclk_pll_vco)
13413 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13414
13415 ret = dev_priv->display.modeset_calc_cdclk(state);
13416 if (ret < 0)
13417 return ret;
13418
13419 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13420 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13421 ret = intel_modeset_all_pipes(state);
13422
13423 if (ret < 0)
13424 return ret;
13425
13426 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13427 intel_state->cdclk, intel_state->dev_cdclk);
13428 } else
13429 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13430
13431 intel_modeset_clear_plls(state);
13432
13433 if (IS_HASWELL(dev_priv))
13434 return haswell_mode_set_planes_workaround(state);
13435
13436 return 0;
13437 }
13438
13439 /*
13440 * Handle calculation of various watermark data at the end of the atomic check
13441 * phase. The code here should be run after the per-crtc and per-plane 'check'
13442 * handlers to ensure that all derived state has been updated.
13443 */
13444 static int calc_watermark_data(struct drm_atomic_state *state)
13445 {
13446 struct drm_device *dev = state->dev;
13447 struct drm_i915_private *dev_priv = to_i915(dev);
13448
13449 /* Is there platform-specific watermark information to calculate? */
13450 if (dev_priv->display.compute_global_watermarks)
13451 return dev_priv->display.compute_global_watermarks(state);
13452
13453 return 0;
13454 }
13455
13456 /**
13457 * intel_atomic_check - validate state object
13458 * @dev: drm device
13459 * @state: state to validate
13460 */
13461 static int intel_atomic_check(struct drm_device *dev,
13462 struct drm_atomic_state *state)
13463 {
13464 struct drm_i915_private *dev_priv = to_i915(dev);
13465 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13466 struct drm_crtc *crtc;
13467 struct drm_crtc_state *crtc_state;
13468 int ret, i;
13469 bool any_ms = false;
13470
13471 ret = drm_atomic_helper_check_modeset(dev, state);
13472 if (ret)
13473 return ret;
13474
13475 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13476 struct intel_crtc_state *pipe_config =
13477 to_intel_crtc_state(crtc_state);
13478
13479 /* Catch I915_MODE_FLAG_INHERITED */
13480 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13481 crtc_state->mode_changed = true;
13482
13483 if (!needs_modeset(crtc_state))
13484 continue;
13485
13486 if (!crtc_state->enable) {
13487 any_ms = true;
13488 continue;
13489 }
13490
13491 /* FIXME: For only active_changed we shouldn't need to do any
13492 * state recomputation at all. */
13493
13494 ret = drm_atomic_add_affected_connectors(state, crtc);
13495 if (ret)
13496 return ret;
13497
13498 ret = intel_modeset_pipe_config(crtc, pipe_config);
13499 if (ret) {
13500 intel_dump_pipe_config(to_intel_crtc(crtc),
13501 pipe_config, "[failed]");
13502 return ret;
13503 }
13504
13505 if (i915.fastboot &&
13506 intel_pipe_config_compare(dev,
13507 to_intel_crtc_state(crtc->state),
13508 pipe_config, true)) {
13509 crtc_state->mode_changed = false;
13510 to_intel_crtc_state(crtc_state)->update_pipe = true;
13511 }
13512
13513 if (needs_modeset(crtc_state))
13514 any_ms = true;
13515
13516 ret = drm_atomic_add_affected_planes(state, crtc);
13517 if (ret)
13518 return ret;
13519
13520 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13521 needs_modeset(crtc_state) ?
13522 "[modeset]" : "[fastset]");
13523 }
13524
13525 if (any_ms) {
13526 ret = intel_modeset_checks(state);
13527
13528 if (ret)
13529 return ret;
13530 } else
13531 intel_state->cdclk = dev_priv->cdclk_freq;
13532
13533 ret = drm_atomic_helper_check_planes(dev, state);
13534 if (ret)
13535 return ret;
13536
13537 intel_fbc_choose_crtc(dev_priv, state);
13538 return calc_watermark_data(state);
13539 }
13540
13541 static int intel_atomic_prepare_commit(struct drm_device *dev,
13542 struct drm_atomic_state *state,
13543 bool nonblock)
13544 {
13545 struct drm_i915_private *dev_priv = dev->dev_private;
13546 struct drm_plane_state *plane_state;
13547 struct drm_crtc_state *crtc_state;
13548 struct drm_plane *plane;
13549 struct drm_crtc *crtc;
13550 int i, ret;
13551
13552 if (nonblock) {
13553 DRM_DEBUG_KMS("i915 does not yet support nonblocking commit\n");
13554 return -EINVAL;
13555 }
13556
13557 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13558 if (state->legacy_cursor_update)
13559 continue;
13560
13561 ret = intel_crtc_wait_for_pending_flips(crtc);
13562 if (ret)
13563 return ret;
13564
13565 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13566 flush_workqueue(dev_priv->wq);
13567 }
13568
13569 ret = mutex_lock_interruptible(&dev->struct_mutex);
13570 if (ret)
13571 return ret;
13572
13573 ret = drm_atomic_helper_prepare_planes(dev, state);
13574 mutex_unlock(&dev->struct_mutex);
13575
13576 if (!ret && !nonblock) {
13577 for_each_plane_in_state(state, plane, plane_state, i) {
13578 struct intel_plane_state *intel_plane_state =
13579 to_intel_plane_state(plane_state);
13580
13581 if (!intel_plane_state->wait_req)
13582 continue;
13583
13584 ret = __i915_wait_request(intel_plane_state->wait_req,
13585 true, NULL, NULL);
13586 if (ret) {
13587 /* Any hang should be swallowed by the wait */
13588 WARN_ON(ret == -EIO);
13589 mutex_lock(&dev->struct_mutex);
13590 drm_atomic_helper_cleanup_planes(dev, state);
13591 mutex_unlock(&dev->struct_mutex);
13592 break;
13593 }
13594 }
13595 }
13596
13597 return ret;
13598 }
13599
13600 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13601 {
13602 struct drm_device *dev = crtc->base.dev;
13603
13604 if (!dev->max_vblank_count)
13605 return drm_accurate_vblank_count(&crtc->base);
13606
13607 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13608 }
13609
13610 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13611 struct drm_i915_private *dev_priv,
13612 unsigned crtc_mask)
13613 {
13614 unsigned last_vblank_count[I915_MAX_PIPES];
13615 enum pipe pipe;
13616 int ret;
13617
13618 if (!crtc_mask)
13619 return;
13620
13621 for_each_pipe(dev_priv, pipe) {
13622 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13623
13624 if (!((1 << pipe) & crtc_mask))
13625 continue;
13626
13627 ret = drm_crtc_vblank_get(crtc);
13628 if (WARN_ON(ret != 0)) {
13629 crtc_mask &= ~(1 << pipe);
13630 continue;
13631 }
13632
13633 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13634 }
13635
13636 for_each_pipe(dev_priv, pipe) {
13637 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13638 long lret;
13639
13640 if (!((1 << pipe) & crtc_mask))
13641 continue;
13642
13643 lret = wait_event_timeout(dev->vblank[pipe].queue,
13644 last_vblank_count[pipe] !=
13645 drm_crtc_vblank_count(crtc),
13646 msecs_to_jiffies(50));
13647
13648 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13649
13650 drm_crtc_vblank_put(crtc);
13651 }
13652 }
13653
13654 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13655 {
13656 /* fb updated, need to unpin old fb */
13657 if (crtc_state->fb_changed)
13658 return true;
13659
13660 /* wm changes, need vblank before final wm's */
13661 if (crtc_state->update_wm_post)
13662 return true;
13663
13664 /*
13665 * cxsr is re-enabled after vblank.
13666 * This is already handled by crtc_state->update_wm_post,
13667 * but added for clarity.
13668 */
13669 if (crtc_state->disable_cxsr)
13670 return true;
13671
13672 return false;
13673 }
13674
13675 /**
13676 * intel_atomic_commit - commit validated state object
13677 * @dev: DRM device
13678 * @state: the top-level driver state object
13679 * @nonblock: nonblocking commit
13680 *
13681 * This function commits a top-level state object that has been validated
13682 * with drm_atomic_helper_check().
13683 *
13684 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13685 * we can only handle plane-related operations and do not yet support
13686 * nonblocking commit.
13687 *
13688 * RETURNS
13689 * Zero for success or -errno.
13690 */
13691 static int intel_atomic_commit(struct drm_device *dev,
13692 struct drm_atomic_state *state,
13693 bool nonblock)
13694 {
13695 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13696 struct drm_i915_private *dev_priv = dev->dev_private;
13697 struct drm_crtc_state *old_crtc_state;
13698 struct drm_crtc *crtc;
13699 struct intel_crtc_state *intel_cstate;
13700 int ret = 0, i;
13701 bool hw_check = intel_state->modeset;
13702 unsigned long put_domains[I915_MAX_PIPES] = {};
13703 unsigned crtc_vblank_mask = 0;
13704
13705 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13706 if (ret) {
13707 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13708 return ret;
13709 }
13710
13711 drm_atomic_helper_swap_state(dev, state);
13712 dev_priv->wm.distrust_bios_wm = false;
13713 dev_priv->wm.skl_results = intel_state->wm_results;
13714 intel_shared_dpll_commit(state);
13715
13716 if (intel_state->modeset) {
13717 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13718 sizeof(intel_state->min_pixclk));
13719 dev_priv->active_crtcs = intel_state->active_crtcs;
13720 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13721
13722 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13723 }
13724
13725 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13727
13728 if (needs_modeset(crtc->state) ||
13729 to_intel_crtc_state(crtc->state)->update_pipe) {
13730 hw_check = true;
13731
13732 put_domains[to_intel_crtc(crtc)->pipe] =
13733 modeset_get_crtc_power_domains(crtc,
13734 to_intel_crtc_state(crtc->state));
13735 }
13736
13737 if (!needs_modeset(crtc->state))
13738 continue;
13739
13740 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13741
13742 if (old_crtc_state->active) {
13743 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13744 dev_priv->display.crtc_disable(crtc);
13745 intel_crtc->active = false;
13746 intel_fbc_disable(intel_crtc);
13747 intel_disable_shared_dpll(intel_crtc);
13748
13749 /*
13750 * Underruns don't always raise
13751 * interrupts, so check manually.
13752 */
13753 intel_check_cpu_fifo_underruns(dev_priv);
13754 intel_check_pch_fifo_underruns(dev_priv);
13755
13756 if (!crtc->state->active)
13757 intel_update_watermarks(crtc);
13758 }
13759 }
13760
13761 /* Only after disabling all output pipelines that will be changed can we
13762 * update the the output configuration. */
13763 intel_modeset_update_crtc_state(state);
13764
13765 if (intel_state->modeset) {
13766 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13767
13768 if (dev_priv->display.modeset_commit_cdclk &&
13769 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13770 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13771 dev_priv->display.modeset_commit_cdclk(state);
13772
13773 intel_modeset_verify_disabled(dev);
13774 }
13775
13776 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13777 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13779 bool modeset = needs_modeset(crtc->state);
13780 struct intel_crtc_state *pipe_config =
13781 to_intel_crtc_state(crtc->state);
13782 bool update_pipe = !modeset && pipe_config->update_pipe;
13783
13784 if (modeset && crtc->state->active) {
13785 update_scanline_offset(to_intel_crtc(crtc));
13786 dev_priv->display.crtc_enable(crtc);
13787 }
13788
13789 if (!modeset)
13790 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13791
13792 if (crtc->state->active &&
13793 drm_atomic_get_existing_plane_state(state, crtc->primary))
13794 intel_fbc_enable(intel_crtc);
13795
13796 if (crtc->state->active &&
13797 (crtc->state->planes_changed || update_pipe))
13798 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13799
13800 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13801 crtc_vblank_mask |= 1 << i;
13802 }
13803
13804 /* FIXME: add subpixel order */
13805
13806 if (!state->legacy_cursor_update)
13807 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13808
13809 /*
13810 * Now that the vblank has passed, we can go ahead and program the
13811 * optimal watermarks on platforms that need two-step watermark
13812 * programming.
13813 *
13814 * TODO: Move this (and other cleanup) to an async worker eventually.
13815 */
13816 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13817 intel_cstate = to_intel_crtc_state(crtc->state);
13818
13819 if (dev_priv->display.optimize_watermarks)
13820 dev_priv->display.optimize_watermarks(intel_cstate);
13821 }
13822
13823 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13824 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13825
13826 if (put_domains[i])
13827 modeset_put_power_domains(dev_priv, put_domains[i]);
13828
13829 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13830 }
13831
13832 if (intel_state->modeset)
13833 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13834
13835 mutex_lock(&dev->struct_mutex);
13836 drm_atomic_helper_cleanup_planes(dev, state);
13837 mutex_unlock(&dev->struct_mutex);
13838
13839 drm_atomic_state_free(state);
13840
13841 /* As one of the primary mmio accessors, KMS has a high likelihood
13842 * of triggering bugs in unclaimed access. After we finish
13843 * modesetting, see if an error has been flagged, and if so
13844 * enable debugging for the next modeset - and hope we catch
13845 * the culprit.
13846 *
13847 * XXX note that we assume display power is on at this point.
13848 * This might hold true now but we need to add pm helper to check
13849 * unclaimed only when the hardware is on, as atomic commits
13850 * can happen also when the device is completely off.
13851 */
13852 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13853
13854 return 0;
13855 }
13856
13857 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13858 {
13859 struct drm_device *dev = crtc->dev;
13860 struct drm_atomic_state *state;
13861 struct drm_crtc_state *crtc_state;
13862 int ret;
13863
13864 state = drm_atomic_state_alloc(dev);
13865 if (!state) {
13866 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13867 crtc->base.id, crtc->name);
13868 return;
13869 }
13870
13871 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13872
13873 retry:
13874 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13875 ret = PTR_ERR_OR_ZERO(crtc_state);
13876 if (!ret) {
13877 if (!crtc_state->active)
13878 goto out;
13879
13880 crtc_state->mode_changed = true;
13881 ret = drm_atomic_commit(state);
13882 }
13883
13884 if (ret == -EDEADLK) {
13885 drm_atomic_state_clear(state);
13886 drm_modeset_backoff(state->acquire_ctx);
13887 goto retry;
13888 }
13889
13890 if (ret)
13891 out:
13892 drm_atomic_state_free(state);
13893 }
13894
13895 #undef for_each_intel_crtc_masked
13896
13897 static const struct drm_crtc_funcs intel_crtc_funcs = {
13898 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13899 .set_config = drm_atomic_helper_set_config,
13900 .set_property = drm_atomic_helper_crtc_set_property,
13901 .destroy = intel_crtc_destroy,
13902 .page_flip = intel_crtc_page_flip,
13903 .atomic_duplicate_state = intel_crtc_duplicate_state,
13904 .atomic_destroy_state = intel_crtc_destroy_state,
13905 };
13906
13907 /**
13908 * intel_prepare_plane_fb - Prepare fb for usage on plane
13909 * @plane: drm plane to prepare for
13910 * @fb: framebuffer to prepare for presentation
13911 *
13912 * Prepares a framebuffer for usage on a display plane. Generally this
13913 * involves pinning the underlying object and updating the frontbuffer tracking
13914 * bits. Some older platforms need special physical address handling for
13915 * cursor planes.
13916 *
13917 * Must be called with struct_mutex held.
13918 *
13919 * Returns 0 on success, negative error code on failure.
13920 */
13921 int
13922 intel_prepare_plane_fb(struct drm_plane *plane,
13923 const struct drm_plane_state *new_state)
13924 {
13925 struct drm_device *dev = plane->dev;
13926 struct drm_framebuffer *fb = new_state->fb;
13927 struct intel_plane *intel_plane = to_intel_plane(plane);
13928 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13929 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13930 int ret = 0;
13931
13932 if (!obj && !old_obj)
13933 return 0;
13934
13935 if (old_obj) {
13936 struct drm_crtc_state *crtc_state =
13937 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13938
13939 /* Big Hammer, we also need to ensure that any pending
13940 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13941 * current scanout is retired before unpinning the old
13942 * framebuffer. Note that we rely on userspace rendering
13943 * into the buffer attached to the pipe they are waiting
13944 * on. If not, userspace generates a GPU hang with IPEHR
13945 * point to the MI_WAIT_FOR_EVENT.
13946 *
13947 * This should only fail upon a hung GPU, in which case we
13948 * can safely continue.
13949 */
13950 if (needs_modeset(crtc_state))
13951 ret = i915_gem_object_wait_rendering(old_obj, true);
13952 if (ret) {
13953 /* GPU hangs should have been swallowed by the wait */
13954 WARN_ON(ret == -EIO);
13955 return ret;
13956 }
13957 }
13958
13959 /* For framebuffer backed by dmabuf, wait for fence */
13960 if (obj && obj->base.dma_buf) {
13961 long lret;
13962
13963 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13964 false, true,
13965 MAX_SCHEDULE_TIMEOUT);
13966 if (lret == -ERESTARTSYS)
13967 return lret;
13968
13969 WARN(lret < 0, "waiting returns %li\n", lret);
13970 }
13971
13972 if (!obj) {
13973 ret = 0;
13974 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13975 INTEL_INFO(dev)->cursor_needs_physical) {
13976 int align = IS_I830(dev) ? 16 * 1024 : 256;
13977 ret = i915_gem_object_attach_phys(obj, align);
13978 if (ret)
13979 DRM_DEBUG_KMS("failed to attach phys object\n");
13980 } else {
13981 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13982 }
13983
13984 if (ret == 0) {
13985 if (obj) {
13986 struct intel_plane_state *plane_state =
13987 to_intel_plane_state(new_state);
13988
13989 i915_gem_request_assign(&plane_state->wait_req,
13990 obj->last_write_req);
13991 }
13992
13993 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13994 }
13995
13996 return ret;
13997 }
13998
13999 /**
14000 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14001 * @plane: drm plane to clean up for
14002 * @fb: old framebuffer that was on plane
14003 *
14004 * Cleans up a framebuffer that has just been removed from a plane.
14005 *
14006 * Must be called with struct_mutex held.
14007 */
14008 void
14009 intel_cleanup_plane_fb(struct drm_plane *plane,
14010 const struct drm_plane_state *old_state)
14011 {
14012 struct drm_device *dev = plane->dev;
14013 struct intel_plane *intel_plane = to_intel_plane(plane);
14014 struct intel_plane_state *old_intel_state;
14015 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14016 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14017
14018 old_intel_state = to_intel_plane_state(old_state);
14019
14020 if (!obj && !old_obj)
14021 return;
14022
14023 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14024 !INTEL_INFO(dev)->cursor_needs_physical))
14025 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14026
14027 /* prepare_fb aborted? */
14028 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
14029 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
14030 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
14031
14032 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14033 }
14034
14035 int
14036 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14037 {
14038 int max_scale;
14039 struct drm_device *dev;
14040 struct drm_i915_private *dev_priv;
14041 int crtc_clock, cdclk;
14042
14043 if (!intel_crtc || !crtc_state->base.enable)
14044 return DRM_PLANE_HELPER_NO_SCALING;
14045
14046 dev = intel_crtc->base.dev;
14047 dev_priv = dev->dev_private;
14048 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14049 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14050
14051 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14052 return DRM_PLANE_HELPER_NO_SCALING;
14053
14054 /*
14055 * skl max scale is lower of:
14056 * close to 3 but not 3, -1 is for that purpose
14057 * or
14058 * cdclk/crtc_clock
14059 */
14060 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14061
14062 return max_scale;
14063 }
14064
14065 static int
14066 intel_check_primary_plane(struct drm_plane *plane,
14067 struct intel_crtc_state *crtc_state,
14068 struct intel_plane_state *state)
14069 {
14070 struct drm_crtc *crtc = state->base.crtc;
14071 struct drm_framebuffer *fb = state->base.fb;
14072 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14073 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14074 bool can_position = false;
14075
14076 if (INTEL_INFO(plane->dev)->gen >= 9) {
14077 /* use scaler when colorkey is not required */
14078 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14079 min_scale = 1;
14080 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14081 }
14082 can_position = true;
14083 }
14084
14085 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14086 &state->dst, &state->clip,
14087 min_scale, max_scale,
14088 can_position, true,
14089 &state->visible);
14090 }
14091
14092 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14093 struct drm_crtc_state *old_crtc_state)
14094 {
14095 struct drm_device *dev = crtc->dev;
14096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14097 struct intel_crtc_state *old_intel_state =
14098 to_intel_crtc_state(old_crtc_state);
14099 bool modeset = needs_modeset(crtc->state);
14100
14101 /* Perform vblank evasion around commit operation */
14102 intel_pipe_update_start(intel_crtc);
14103
14104 if (modeset)
14105 return;
14106
14107 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14108 intel_color_set_csc(crtc->state);
14109 intel_color_load_luts(crtc->state);
14110 }
14111
14112 if (to_intel_crtc_state(crtc->state)->update_pipe)
14113 intel_update_pipe_config(intel_crtc, old_intel_state);
14114 else if (INTEL_INFO(dev)->gen >= 9)
14115 skl_detach_scalers(intel_crtc);
14116 }
14117
14118 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14119 struct drm_crtc_state *old_crtc_state)
14120 {
14121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14122
14123 intel_pipe_update_end(intel_crtc, NULL);
14124 }
14125
14126 /**
14127 * intel_plane_destroy - destroy a plane
14128 * @plane: plane to destroy
14129 *
14130 * Common destruction function for all types of planes (primary, cursor,
14131 * sprite).
14132 */
14133 void intel_plane_destroy(struct drm_plane *plane)
14134 {
14135 if (!plane)
14136 return;
14137
14138 drm_plane_cleanup(plane);
14139 kfree(to_intel_plane(plane));
14140 }
14141
14142 const struct drm_plane_funcs intel_plane_funcs = {
14143 .update_plane = drm_atomic_helper_update_plane,
14144 .disable_plane = drm_atomic_helper_disable_plane,
14145 .destroy = intel_plane_destroy,
14146 .set_property = drm_atomic_helper_plane_set_property,
14147 .atomic_get_property = intel_plane_atomic_get_property,
14148 .atomic_set_property = intel_plane_atomic_set_property,
14149 .atomic_duplicate_state = intel_plane_duplicate_state,
14150 .atomic_destroy_state = intel_plane_destroy_state,
14151
14152 };
14153
14154 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14155 int pipe)
14156 {
14157 struct intel_plane *primary = NULL;
14158 struct intel_plane_state *state = NULL;
14159 const uint32_t *intel_primary_formats;
14160 unsigned int num_formats;
14161 int ret;
14162
14163 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14164 if (!primary)
14165 goto fail;
14166
14167 state = intel_create_plane_state(&primary->base);
14168 if (!state)
14169 goto fail;
14170 primary->base.state = &state->base;
14171
14172 primary->can_scale = false;
14173 primary->max_downscale = 1;
14174 if (INTEL_INFO(dev)->gen >= 9) {
14175 primary->can_scale = true;
14176 state->scaler_id = -1;
14177 }
14178 primary->pipe = pipe;
14179 primary->plane = pipe;
14180 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14181 primary->check_plane = intel_check_primary_plane;
14182 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14183 primary->plane = !pipe;
14184
14185 if (INTEL_INFO(dev)->gen >= 9) {
14186 intel_primary_formats = skl_primary_formats;
14187 num_formats = ARRAY_SIZE(skl_primary_formats);
14188
14189 primary->update_plane = skylake_update_primary_plane;
14190 primary->disable_plane = skylake_disable_primary_plane;
14191 } else if (HAS_PCH_SPLIT(dev)) {
14192 intel_primary_formats = i965_primary_formats;
14193 num_formats = ARRAY_SIZE(i965_primary_formats);
14194
14195 primary->update_plane = ironlake_update_primary_plane;
14196 primary->disable_plane = i9xx_disable_primary_plane;
14197 } else if (INTEL_INFO(dev)->gen >= 4) {
14198 intel_primary_formats = i965_primary_formats;
14199 num_formats = ARRAY_SIZE(i965_primary_formats);
14200
14201 primary->update_plane = i9xx_update_primary_plane;
14202 primary->disable_plane = i9xx_disable_primary_plane;
14203 } else {
14204 intel_primary_formats = i8xx_primary_formats;
14205 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14206
14207 primary->update_plane = i9xx_update_primary_plane;
14208 primary->disable_plane = i9xx_disable_primary_plane;
14209 }
14210
14211 if (INTEL_INFO(dev)->gen >= 9)
14212 ret = drm_universal_plane_init(dev, &primary->base, 0,
14213 &intel_plane_funcs,
14214 intel_primary_formats, num_formats,
14215 DRM_PLANE_TYPE_PRIMARY,
14216 "plane 1%c", pipe_name(pipe));
14217 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14218 ret = drm_universal_plane_init(dev, &primary->base, 0,
14219 &intel_plane_funcs,
14220 intel_primary_formats, num_formats,
14221 DRM_PLANE_TYPE_PRIMARY,
14222 "primary %c", pipe_name(pipe));
14223 else
14224 ret = drm_universal_plane_init(dev, &primary->base, 0,
14225 &intel_plane_funcs,
14226 intel_primary_formats, num_formats,
14227 DRM_PLANE_TYPE_PRIMARY,
14228 "plane %c", plane_name(primary->plane));
14229 if (ret)
14230 goto fail;
14231
14232 if (INTEL_INFO(dev)->gen >= 4)
14233 intel_create_rotation_property(dev, primary);
14234
14235 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14236
14237 return &primary->base;
14238
14239 fail:
14240 kfree(state);
14241 kfree(primary);
14242
14243 return NULL;
14244 }
14245
14246 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14247 {
14248 if (!dev->mode_config.rotation_property) {
14249 unsigned long flags = BIT(DRM_ROTATE_0) |
14250 BIT(DRM_ROTATE_180);
14251
14252 if (INTEL_INFO(dev)->gen >= 9)
14253 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14254
14255 dev->mode_config.rotation_property =
14256 drm_mode_create_rotation_property(dev, flags);
14257 }
14258 if (dev->mode_config.rotation_property)
14259 drm_object_attach_property(&plane->base.base,
14260 dev->mode_config.rotation_property,
14261 plane->base.state->rotation);
14262 }
14263
14264 static int
14265 intel_check_cursor_plane(struct drm_plane *plane,
14266 struct intel_crtc_state *crtc_state,
14267 struct intel_plane_state *state)
14268 {
14269 struct drm_crtc *crtc = crtc_state->base.crtc;
14270 struct drm_framebuffer *fb = state->base.fb;
14271 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14272 enum pipe pipe = to_intel_plane(plane)->pipe;
14273 unsigned stride;
14274 int ret;
14275
14276 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14277 &state->dst, &state->clip,
14278 DRM_PLANE_HELPER_NO_SCALING,
14279 DRM_PLANE_HELPER_NO_SCALING,
14280 true, true, &state->visible);
14281 if (ret)
14282 return ret;
14283
14284 /* if we want to turn off the cursor ignore width and height */
14285 if (!obj)
14286 return 0;
14287
14288 /* Check for which cursor types we support */
14289 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14290 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14291 state->base.crtc_w, state->base.crtc_h);
14292 return -EINVAL;
14293 }
14294
14295 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14296 if (obj->base.size < stride * state->base.crtc_h) {
14297 DRM_DEBUG_KMS("buffer is too small\n");
14298 return -ENOMEM;
14299 }
14300
14301 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14302 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14303 return -EINVAL;
14304 }
14305
14306 /*
14307 * There's something wrong with the cursor on CHV pipe C.
14308 * If it straddles the left edge of the screen then
14309 * moving it away from the edge or disabling it often
14310 * results in a pipe underrun, and often that can lead to
14311 * dead pipe (constant underrun reported, and it scans
14312 * out just a solid color). To recover from that, the
14313 * display power well must be turned off and on again.
14314 * Refuse the put the cursor into that compromised position.
14315 */
14316 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14317 state->visible && state->base.crtc_x < 0) {
14318 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14319 return -EINVAL;
14320 }
14321
14322 return 0;
14323 }
14324
14325 static void
14326 intel_disable_cursor_plane(struct drm_plane *plane,
14327 struct drm_crtc *crtc)
14328 {
14329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14330
14331 intel_crtc->cursor_addr = 0;
14332 intel_crtc_update_cursor(crtc, NULL);
14333 }
14334
14335 static void
14336 intel_update_cursor_plane(struct drm_plane *plane,
14337 const struct intel_crtc_state *crtc_state,
14338 const struct intel_plane_state *state)
14339 {
14340 struct drm_crtc *crtc = crtc_state->base.crtc;
14341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14342 struct drm_device *dev = plane->dev;
14343 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14344 uint32_t addr;
14345
14346 if (!obj)
14347 addr = 0;
14348 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14349 addr = i915_gem_obj_ggtt_offset(obj);
14350 else
14351 addr = obj->phys_handle->busaddr;
14352
14353 intel_crtc->cursor_addr = addr;
14354 intel_crtc_update_cursor(crtc, state);
14355 }
14356
14357 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14358 int pipe)
14359 {
14360 struct intel_plane *cursor = NULL;
14361 struct intel_plane_state *state = NULL;
14362 int ret;
14363
14364 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14365 if (!cursor)
14366 goto fail;
14367
14368 state = intel_create_plane_state(&cursor->base);
14369 if (!state)
14370 goto fail;
14371 cursor->base.state = &state->base;
14372
14373 cursor->can_scale = false;
14374 cursor->max_downscale = 1;
14375 cursor->pipe = pipe;
14376 cursor->plane = pipe;
14377 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14378 cursor->check_plane = intel_check_cursor_plane;
14379 cursor->update_plane = intel_update_cursor_plane;
14380 cursor->disable_plane = intel_disable_cursor_plane;
14381
14382 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14383 &intel_plane_funcs,
14384 intel_cursor_formats,
14385 ARRAY_SIZE(intel_cursor_formats),
14386 DRM_PLANE_TYPE_CURSOR,
14387 "cursor %c", pipe_name(pipe));
14388 if (ret)
14389 goto fail;
14390
14391 if (INTEL_INFO(dev)->gen >= 4) {
14392 if (!dev->mode_config.rotation_property)
14393 dev->mode_config.rotation_property =
14394 drm_mode_create_rotation_property(dev,
14395 BIT(DRM_ROTATE_0) |
14396 BIT(DRM_ROTATE_180));
14397 if (dev->mode_config.rotation_property)
14398 drm_object_attach_property(&cursor->base.base,
14399 dev->mode_config.rotation_property,
14400 state->base.rotation);
14401 }
14402
14403 if (INTEL_INFO(dev)->gen >=9)
14404 state->scaler_id = -1;
14405
14406 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14407
14408 return &cursor->base;
14409
14410 fail:
14411 kfree(state);
14412 kfree(cursor);
14413
14414 return NULL;
14415 }
14416
14417 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14418 struct intel_crtc_state *crtc_state)
14419 {
14420 int i;
14421 struct intel_scaler *intel_scaler;
14422 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14423
14424 for (i = 0; i < intel_crtc->num_scalers; i++) {
14425 intel_scaler = &scaler_state->scalers[i];
14426 intel_scaler->in_use = 0;
14427 intel_scaler->mode = PS_SCALER_MODE_DYN;
14428 }
14429
14430 scaler_state->scaler_id = -1;
14431 }
14432
14433 static void intel_crtc_init(struct drm_device *dev, int pipe)
14434 {
14435 struct drm_i915_private *dev_priv = dev->dev_private;
14436 struct intel_crtc *intel_crtc;
14437 struct intel_crtc_state *crtc_state = NULL;
14438 struct drm_plane *primary = NULL;
14439 struct drm_plane *cursor = NULL;
14440 int ret;
14441
14442 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14443 if (intel_crtc == NULL)
14444 return;
14445
14446 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14447 if (!crtc_state)
14448 goto fail;
14449 intel_crtc->config = crtc_state;
14450 intel_crtc->base.state = &crtc_state->base;
14451 crtc_state->base.crtc = &intel_crtc->base;
14452
14453 /* initialize shared scalers */
14454 if (INTEL_INFO(dev)->gen >= 9) {
14455 if (pipe == PIPE_C)
14456 intel_crtc->num_scalers = 1;
14457 else
14458 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14459
14460 skl_init_scalers(dev, intel_crtc, crtc_state);
14461 }
14462
14463 primary = intel_primary_plane_create(dev, pipe);
14464 if (!primary)
14465 goto fail;
14466
14467 cursor = intel_cursor_plane_create(dev, pipe);
14468 if (!cursor)
14469 goto fail;
14470
14471 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14472 cursor, &intel_crtc_funcs,
14473 "pipe %c", pipe_name(pipe));
14474 if (ret)
14475 goto fail;
14476
14477 /*
14478 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14479 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14480 */
14481 intel_crtc->pipe = pipe;
14482 intel_crtc->plane = pipe;
14483 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14484 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14485 intel_crtc->plane = !pipe;
14486 }
14487
14488 intel_crtc->cursor_base = ~0;
14489 intel_crtc->cursor_cntl = ~0;
14490 intel_crtc->cursor_size = ~0;
14491
14492 intel_crtc->wm.cxsr_allowed = true;
14493
14494 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14495 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14496 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14497 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14498
14499 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14500
14501 intel_color_init(&intel_crtc->base);
14502
14503 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14504 return;
14505
14506 fail:
14507 intel_plane_destroy(primary);
14508 intel_plane_destroy(cursor);
14509 kfree(crtc_state);
14510 kfree(intel_crtc);
14511 }
14512
14513 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14514 {
14515 struct drm_encoder *encoder = connector->base.encoder;
14516 struct drm_device *dev = connector->base.dev;
14517
14518 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14519
14520 if (!encoder || WARN_ON(!encoder->crtc))
14521 return INVALID_PIPE;
14522
14523 return to_intel_crtc(encoder->crtc)->pipe;
14524 }
14525
14526 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14527 struct drm_file *file)
14528 {
14529 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14530 struct drm_crtc *drmmode_crtc;
14531 struct intel_crtc *crtc;
14532
14533 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14534
14535 if (!drmmode_crtc) {
14536 DRM_ERROR("no such CRTC id\n");
14537 return -ENOENT;
14538 }
14539
14540 crtc = to_intel_crtc(drmmode_crtc);
14541 pipe_from_crtc_id->pipe = crtc->pipe;
14542
14543 return 0;
14544 }
14545
14546 static int intel_encoder_clones(struct intel_encoder *encoder)
14547 {
14548 struct drm_device *dev = encoder->base.dev;
14549 struct intel_encoder *source_encoder;
14550 int index_mask = 0;
14551 int entry = 0;
14552
14553 for_each_intel_encoder(dev, source_encoder) {
14554 if (encoders_cloneable(encoder, source_encoder))
14555 index_mask |= (1 << entry);
14556
14557 entry++;
14558 }
14559
14560 return index_mask;
14561 }
14562
14563 static bool has_edp_a(struct drm_device *dev)
14564 {
14565 struct drm_i915_private *dev_priv = dev->dev_private;
14566
14567 if (!IS_MOBILE(dev))
14568 return false;
14569
14570 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14571 return false;
14572
14573 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14574 return false;
14575
14576 return true;
14577 }
14578
14579 static bool intel_crt_present(struct drm_device *dev)
14580 {
14581 struct drm_i915_private *dev_priv = dev->dev_private;
14582
14583 if (INTEL_INFO(dev)->gen >= 9)
14584 return false;
14585
14586 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14587 return false;
14588
14589 if (IS_CHERRYVIEW(dev))
14590 return false;
14591
14592 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14593 return false;
14594
14595 /* DDI E can't be used if DDI A requires 4 lanes */
14596 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14597 return false;
14598
14599 if (!dev_priv->vbt.int_crt_support)
14600 return false;
14601
14602 return true;
14603 }
14604
14605 static void intel_setup_outputs(struct drm_device *dev)
14606 {
14607 struct drm_i915_private *dev_priv = dev->dev_private;
14608 struct intel_encoder *encoder;
14609 bool dpd_is_edp = false;
14610
14611 intel_lvds_init(dev);
14612
14613 if (intel_crt_present(dev))
14614 intel_crt_init(dev);
14615
14616 if (IS_BROXTON(dev)) {
14617 /*
14618 * FIXME: Broxton doesn't support port detection via the
14619 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14620 * detect the ports.
14621 */
14622 intel_ddi_init(dev, PORT_A);
14623 intel_ddi_init(dev, PORT_B);
14624 intel_ddi_init(dev, PORT_C);
14625
14626 intel_dsi_init(dev);
14627 } else if (HAS_DDI(dev)) {
14628 int found;
14629
14630 /*
14631 * Haswell uses DDI functions to detect digital outputs.
14632 * On SKL pre-D0 the strap isn't connected, so we assume
14633 * it's there.
14634 */
14635 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14636 /* WaIgnoreDDIAStrap: skl */
14637 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14638 intel_ddi_init(dev, PORT_A);
14639
14640 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14641 * register */
14642 found = I915_READ(SFUSE_STRAP);
14643
14644 if (found & SFUSE_STRAP_DDIB_DETECTED)
14645 intel_ddi_init(dev, PORT_B);
14646 if (found & SFUSE_STRAP_DDIC_DETECTED)
14647 intel_ddi_init(dev, PORT_C);
14648 if (found & SFUSE_STRAP_DDID_DETECTED)
14649 intel_ddi_init(dev, PORT_D);
14650 /*
14651 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14652 */
14653 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14654 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14655 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14656 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14657 intel_ddi_init(dev, PORT_E);
14658
14659 } else if (HAS_PCH_SPLIT(dev)) {
14660 int found;
14661 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14662
14663 if (has_edp_a(dev))
14664 intel_dp_init(dev, DP_A, PORT_A);
14665
14666 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14667 /* PCH SDVOB multiplex with HDMIB */
14668 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14669 if (!found)
14670 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14671 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14672 intel_dp_init(dev, PCH_DP_B, PORT_B);
14673 }
14674
14675 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14676 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14677
14678 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14679 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14680
14681 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14682 intel_dp_init(dev, PCH_DP_C, PORT_C);
14683
14684 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14685 intel_dp_init(dev, PCH_DP_D, PORT_D);
14686 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14687 bool has_edp, has_port;
14688
14689 /*
14690 * The DP_DETECTED bit is the latched state of the DDC
14691 * SDA pin at boot. However since eDP doesn't require DDC
14692 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14693 * eDP ports may have been muxed to an alternate function.
14694 * Thus we can't rely on the DP_DETECTED bit alone to detect
14695 * eDP ports. Consult the VBT as well as DP_DETECTED to
14696 * detect eDP ports.
14697 *
14698 * Sadly the straps seem to be missing sometimes even for HDMI
14699 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14700 * and VBT for the presence of the port. Additionally we can't
14701 * trust the port type the VBT declares as we've seen at least
14702 * HDMI ports that the VBT claim are DP or eDP.
14703 */
14704 has_edp = intel_dp_is_edp(dev, PORT_B);
14705 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14706 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14707 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14708 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14709 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14710
14711 has_edp = intel_dp_is_edp(dev, PORT_C);
14712 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14713 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14714 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14715 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14716 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14717
14718 if (IS_CHERRYVIEW(dev)) {
14719 /*
14720 * eDP not supported on port D,
14721 * so no need to worry about it
14722 */
14723 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14724 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14725 intel_dp_init(dev, CHV_DP_D, PORT_D);
14726 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14727 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14728 }
14729
14730 intel_dsi_init(dev);
14731 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14732 bool found = false;
14733
14734 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14735 DRM_DEBUG_KMS("probing SDVOB\n");
14736 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14737 if (!found && IS_G4X(dev)) {
14738 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14739 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14740 }
14741
14742 if (!found && IS_G4X(dev))
14743 intel_dp_init(dev, DP_B, PORT_B);
14744 }
14745
14746 /* Before G4X SDVOC doesn't have its own detect register */
14747
14748 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14749 DRM_DEBUG_KMS("probing SDVOC\n");
14750 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14751 }
14752
14753 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14754
14755 if (IS_G4X(dev)) {
14756 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14757 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14758 }
14759 if (IS_G4X(dev))
14760 intel_dp_init(dev, DP_C, PORT_C);
14761 }
14762
14763 if (IS_G4X(dev) &&
14764 (I915_READ(DP_D) & DP_DETECTED))
14765 intel_dp_init(dev, DP_D, PORT_D);
14766 } else if (IS_GEN2(dev))
14767 intel_dvo_init(dev);
14768
14769 if (SUPPORTS_TV(dev))
14770 intel_tv_init(dev);
14771
14772 intel_psr_init(dev);
14773
14774 for_each_intel_encoder(dev, encoder) {
14775 encoder->base.possible_crtcs = encoder->crtc_mask;
14776 encoder->base.possible_clones =
14777 intel_encoder_clones(encoder);
14778 }
14779
14780 intel_init_pch_refclk(dev);
14781
14782 drm_helper_move_panel_connectors_to_head(dev);
14783 }
14784
14785 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14786 {
14787 struct drm_device *dev = fb->dev;
14788 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14789
14790 drm_framebuffer_cleanup(fb);
14791 mutex_lock(&dev->struct_mutex);
14792 WARN_ON(!intel_fb->obj->framebuffer_references--);
14793 drm_gem_object_unreference(&intel_fb->obj->base);
14794 mutex_unlock(&dev->struct_mutex);
14795 kfree(intel_fb);
14796 }
14797
14798 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14799 struct drm_file *file,
14800 unsigned int *handle)
14801 {
14802 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14803 struct drm_i915_gem_object *obj = intel_fb->obj;
14804
14805 if (obj->userptr.mm) {
14806 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14807 return -EINVAL;
14808 }
14809
14810 return drm_gem_handle_create(file, &obj->base, handle);
14811 }
14812
14813 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14814 struct drm_file *file,
14815 unsigned flags, unsigned color,
14816 struct drm_clip_rect *clips,
14817 unsigned num_clips)
14818 {
14819 struct drm_device *dev = fb->dev;
14820 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14821 struct drm_i915_gem_object *obj = intel_fb->obj;
14822
14823 mutex_lock(&dev->struct_mutex);
14824 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14825 mutex_unlock(&dev->struct_mutex);
14826
14827 return 0;
14828 }
14829
14830 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14831 .destroy = intel_user_framebuffer_destroy,
14832 .create_handle = intel_user_framebuffer_create_handle,
14833 .dirty = intel_user_framebuffer_dirty,
14834 };
14835
14836 static
14837 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14838 uint32_t pixel_format)
14839 {
14840 u32 gen = INTEL_INFO(dev)->gen;
14841
14842 if (gen >= 9) {
14843 int cpp = drm_format_plane_cpp(pixel_format, 0);
14844
14845 /* "The stride in bytes must not exceed the of the size of 8K
14846 * pixels and 32K bytes."
14847 */
14848 return min(8192 * cpp, 32768);
14849 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14850 return 32*1024;
14851 } else if (gen >= 4) {
14852 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14853 return 16*1024;
14854 else
14855 return 32*1024;
14856 } else if (gen >= 3) {
14857 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14858 return 8*1024;
14859 else
14860 return 16*1024;
14861 } else {
14862 /* XXX DSPC is limited to 4k tiled */
14863 return 8*1024;
14864 }
14865 }
14866
14867 static int intel_framebuffer_init(struct drm_device *dev,
14868 struct intel_framebuffer *intel_fb,
14869 struct drm_mode_fb_cmd2 *mode_cmd,
14870 struct drm_i915_gem_object *obj)
14871 {
14872 struct drm_i915_private *dev_priv = to_i915(dev);
14873 unsigned int aligned_height;
14874 int ret;
14875 u32 pitch_limit, stride_alignment;
14876
14877 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14878
14879 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14880 /* Enforce that fb modifier and tiling mode match, but only for
14881 * X-tiled. This is needed for FBC. */
14882 if (!!(obj->tiling_mode == I915_TILING_X) !=
14883 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14884 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14885 return -EINVAL;
14886 }
14887 } else {
14888 if (obj->tiling_mode == I915_TILING_X)
14889 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14890 else if (obj->tiling_mode == I915_TILING_Y) {
14891 DRM_DEBUG("No Y tiling for legacy addfb\n");
14892 return -EINVAL;
14893 }
14894 }
14895
14896 /* Passed in modifier sanity checking. */
14897 switch (mode_cmd->modifier[0]) {
14898 case I915_FORMAT_MOD_Y_TILED:
14899 case I915_FORMAT_MOD_Yf_TILED:
14900 if (INTEL_INFO(dev)->gen < 9) {
14901 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14902 mode_cmd->modifier[0]);
14903 return -EINVAL;
14904 }
14905 case DRM_FORMAT_MOD_NONE:
14906 case I915_FORMAT_MOD_X_TILED:
14907 break;
14908 default:
14909 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14910 mode_cmd->modifier[0]);
14911 return -EINVAL;
14912 }
14913
14914 stride_alignment = intel_fb_stride_alignment(dev_priv,
14915 mode_cmd->modifier[0],
14916 mode_cmd->pixel_format);
14917 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14918 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14919 mode_cmd->pitches[0], stride_alignment);
14920 return -EINVAL;
14921 }
14922
14923 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14924 mode_cmd->pixel_format);
14925 if (mode_cmd->pitches[0] > pitch_limit) {
14926 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14927 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14928 "tiled" : "linear",
14929 mode_cmd->pitches[0], pitch_limit);
14930 return -EINVAL;
14931 }
14932
14933 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14934 mode_cmd->pitches[0] != obj->stride) {
14935 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14936 mode_cmd->pitches[0], obj->stride);
14937 return -EINVAL;
14938 }
14939
14940 /* Reject formats not supported by any plane early. */
14941 switch (mode_cmd->pixel_format) {
14942 case DRM_FORMAT_C8:
14943 case DRM_FORMAT_RGB565:
14944 case DRM_FORMAT_XRGB8888:
14945 case DRM_FORMAT_ARGB8888:
14946 break;
14947 case DRM_FORMAT_XRGB1555:
14948 if (INTEL_INFO(dev)->gen > 3) {
14949 DRM_DEBUG("unsupported pixel format: %s\n",
14950 drm_get_format_name(mode_cmd->pixel_format));
14951 return -EINVAL;
14952 }
14953 break;
14954 case DRM_FORMAT_ABGR8888:
14955 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14956 INTEL_INFO(dev)->gen < 9) {
14957 DRM_DEBUG("unsupported pixel format: %s\n",
14958 drm_get_format_name(mode_cmd->pixel_format));
14959 return -EINVAL;
14960 }
14961 break;
14962 case DRM_FORMAT_XBGR8888:
14963 case DRM_FORMAT_XRGB2101010:
14964 case DRM_FORMAT_XBGR2101010:
14965 if (INTEL_INFO(dev)->gen < 4) {
14966 DRM_DEBUG("unsupported pixel format: %s\n",
14967 drm_get_format_name(mode_cmd->pixel_format));
14968 return -EINVAL;
14969 }
14970 break;
14971 case DRM_FORMAT_ABGR2101010:
14972 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14973 DRM_DEBUG("unsupported pixel format: %s\n",
14974 drm_get_format_name(mode_cmd->pixel_format));
14975 return -EINVAL;
14976 }
14977 break;
14978 case DRM_FORMAT_YUYV:
14979 case DRM_FORMAT_UYVY:
14980 case DRM_FORMAT_YVYU:
14981 case DRM_FORMAT_VYUY:
14982 if (INTEL_INFO(dev)->gen < 5) {
14983 DRM_DEBUG("unsupported pixel format: %s\n",
14984 drm_get_format_name(mode_cmd->pixel_format));
14985 return -EINVAL;
14986 }
14987 break;
14988 default:
14989 DRM_DEBUG("unsupported pixel format: %s\n",
14990 drm_get_format_name(mode_cmd->pixel_format));
14991 return -EINVAL;
14992 }
14993
14994 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14995 if (mode_cmd->offsets[0] != 0)
14996 return -EINVAL;
14997
14998 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14999 mode_cmd->pixel_format,
15000 mode_cmd->modifier[0]);
15001 /* FIXME drm helper for size checks (especially planar formats)? */
15002 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15003 return -EINVAL;
15004
15005 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15006 intel_fb->obj = obj;
15007
15008 intel_fill_fb_info(dev_priv, &intel_fb->base);
15009
15010 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15011 if (ret) {
15012 DRM_ERROR("framebuffer init failed %d\n", ret);
15013 return ret;
15014 }
15015
15016 intel_fb->obj->framebuffer_references++;
15017
15018 return 0;
15019 }
15020
15021 static struct drm_framebuffer *
15022 intel_user_framebuffer_create(struct drm_device *dev,
15023 struct drm_file *filp,
15024 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15025 {
15026 struct drm_framebuffer *fb;
15027 struct drm_i915_gem_object *obj;
15028 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15029
15030 obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15031 if (&obj->base == NULL)
15032 return ERR_PTR(-ENOENT);
15033
15034 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15035 if (IS_ERR(fb))
15036 drm_gem_object_unreference_unlocked(&obj->base);
15037
15038 return fb;
15039 }
15040
15041 #ifndef CONFIG_DRM_FBDEV_EMULATION
15042 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15043 {
15044 }
15045 #endif
15046
15047 static const struct drm_mode_config_funcs intel_mode_funcs = {
15048 .fb_create = intel_user_framebuffer_create,
15049 .output_poll_changed = intel_fbdev_output_poll_changed,
15050 .atomic_check = intel_atomic_check,
15051 .atomic_commit = intel_atomic_commit,
15052 .atomic_state_alloc = intel_atomic_state_alloc,
15053 .atomic_state_clear = intel_atomic_state_clear,
15054 };
15055
15056 /**
15057 * intel_init_display_hooks - initialize the display modesetting hooks
15058 * @dev_priv: device private
15059 */
15060 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15061 {
15062 if (INTEL_INFO(dev_priv)->gen >= 9) {
15063 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15064 dev_priv->display.get_initial_plane_config =
15065 skylake_get_initial_plane_config;
15066 dev_priv->display.crtc_compute_clock =
15067 haswell_crtc_compute_clock;
15068 dev_priv->display.crtc_enable = haswell_crtc_enable;
15069 dev_priv->display.crtc_disable = haswell_crtc_disable;
15070 } else if (HAS_DDI(dev_priv)) {
15071 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15072 dev_priv->display.get_initial_plane_config =
15073 ironlake_get_initial_plane_config;
15074 dev_priv->display.crtc_compute_clock =
15075 haswell_crtc_compute_clock;
15076 dev_priv->display.crtc_enable = haswell_crtc_enable;
15077 dev_priv->display.crtc_disable = haswell_crtc_disable;
15078 } else if (HAS_PCH_SPLIT(dev_priv)) {
15079 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15080 dev_priv->display.get_initial_plane_config =
15081 ironlake_get_initial_plane_config;
15082 dev_priv->display.crtc_compute_clock =
15083 ironlake_crtc_compute_clock;
15084 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15085 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15086 } else if (IS_CHERRYVIEW(dev_priv)) {
15087 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15088 dev_priv->display.get_initial_plane_config =
15089 i9xx_get_initial_plane_config;
15090 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15091 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15092 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15093 } else if (IS_VALLEYVIEW(dev_priv)) {
15094 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15095 dev_priv->display.get_initial_plane_config =
15096 i9xx_get_initial_plane_config;
15097 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15098 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15099 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15100 } else if (IS_G4X(dev_priv)) {
15101 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15102 dev_priv->display.get_initial_plane_config =
15103 i9xx_get_initial_plane_config;
15104 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15105 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15106 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15107 } else if (IS_PINEVIEW(dev_priv)) {
15108 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15109 dev_priv->display.get_initial_plane_config =
15110 i9xx_get_initial_plane_config;
15111 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15112 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15113 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15114 } else if (!IS_GEN2(dev_priv)) {
15115 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15116 dev_priv->display.get_initial_plane_config =
15117 i9xx_get_initial_plane_config;
15118 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15119 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15120 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15121 } else {
15122 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15123 dev_priv->display.get_initial_plane_config =
15124 i9xx_get_initial_plane_config;
15125 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15126 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15127 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15128 }
15129
15130 /* Returns the core display clock speed */
15131 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15132 dev_priv->display.get_display_clock_speed =
15133 skylake_get_display_clock_speed;
15134 else if (IS_BROXTON(dev_priv))
15135 dev_priv->display.get_display_clock_speed =
15136 broxton_get_display_clock_speed;
15137 else if (IS_BROADWELL(dev_priv))
15138 dev_priv->display.get_display_clock_speed =
15139 broadwell_get_display_clock_speed;
15140 else if (IS_HASWELL(dev_priv))
15141 dev_priv->display.get_display_clock_speed =
15142 haswell_get_display_clock_speed;
15143 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15144 dev_priv->display.get_display_clock_speed =
15145 valleyview_get_display_clock_speed;
15146 else if (IS_GEN5(dev_priv))
15147 dev_priv->display.get_display_clock_speed =
15148 ilk_get_display_clock_speed;
15149 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15150 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15151 dev_priv->display.get_display_clock_speed =
15152 i945_get_display_clock_speed;
15153 else if (IS_GM45(dev_priv))
15154 dev_priv->display.get_display_clock_speed =
15155 gm45_get_display_clock_speed;
15156 else if (IS_CRESTLINE(dev_priv))
15157 dev_priv->display.get_display_clock_speed =
15158 i965gm_get_display_clock_speed;
15159 else if (IS_PINEVIEW(dev_priv))
15160 dev_priv->display.get_display_clock_speed =
15161 pnv_get_display_clock_speed;
15162 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15163 dev_priv->display.get_display_clock_speed =
15164 g33_get_display_clock_speed;
15165 else if (IS_I915G(dev_priv))
15166 dev_priv->display.get_display_clock_speed =
15167 i915_get_display_clock_speed;
15168 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15169 dev_priv->display.get_display_clock_speed =
15170 i9xx_misc_get_display_clock_speed;
15171 else if (IS_I915GM(dev_priv))
15172 dev_priv->display.get_display_clock_speed =
15173 i915gm_get_display_clock_speed;
15174 else if (IS_I865G(dev_priv))
15175 dev_priv->display.get_display_clock_speed =
15176 i865_get_display_clock_speed;
15177 else if (IS_I85X(dev_priv))
15178 dev_priv->display.get_display_clock_speed =
15179 i85x_get_display_clock_speed;
15180 else { /* 830 */
15181 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15182 dev_priv->display.get_display_clock_speed =
15183 i830_get_display_clock_speed;
15184 }
15185
15186 if (IS_GEN5(dev_priv)) {
15187 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15188 } else if (IS_GEN6(dev_priv)) {
15189 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15190 } else if (IS_IVYBRIDGE(dev_priv)) {
15191 /* FIXME: detect B0+ stepping and use auto training */
15192 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15193 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15194 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15195 }
15196
15197 if (IS_BROADWELL(dev_priv)) {
15198 dev_priv->display.modeset_commit_cdclk =
15199 broadwell_modeset_commit_cdclk;
15200 dev_priv->display.modeset_calc_cdclk =
15201 broadwell_modeset_calc_cdclk;
15202 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15203 dev_priv->display.modeset_commit_cdclk =
15204 valleyview_modeset_commit_cdclk;
15205 dev_priv->display.modeset_calc_cdclk =
15206 valleyview_modeset_calc_cdclk;
15207 } else if (IS_BROXTON(dev_priv)) {
15208 dev_priv->display.modeset_commit_cdclk =
15209 bxt_modeset_commit_cdclk;
15210 dev_priv->display.modeset_calc_cdclk =
15211 bxt_modeset_calc_cdclk;
15212 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15213 dev_priv->display.modeset_commit_cdclk =
15214 skl_modeset_commit_cdclk;
15215 dev_priv->display.modeset_calc_cdclk =
15216 skl_modeset_calc_cdclk;
15217 }
15218
15219 switch (INTEL_INFO(dev_priv)->gen) {
15220 case 2:
15221 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15222 break;
15223
15224 case 3:
15225 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15226 break;
15227
15228 case 4:
15229 case 5:
15230 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15231 break;
15232
15233 case 6:
15234 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15235 break;
15236 case 7:
15237 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15238 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15239 break;
15240 case 9:
15241 /* Drop through - unsupported since execlist only. */
15242 default:
15243 /* Default just returns -ENODEV to indicate unsupported */
15244 dev_priv->display.queue_flip = intel_default_queue_flip;
15245 }
15246 }
15247
15248 /*
15249 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15250 * resume, or other times. This quirk makes sure that's the case for
15251 * affected systems.
15252 */
15253 static void quirk_pipea_force(struct drm_device *dev)
15254 {
15255 struct drm_i915_private *dev_priv = dev->dev_private;
15256
15257 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15258 DRM_INFO("applying pipe a force quirk\n");
15259 }
15260
15261 static void quirk_pipeb_force(struct drm_device *dev)
15262 {
15263 struct drm_i915_private *dev_priv = dev->dev_private;
15264
15265 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15266 DRM_INFO("applying pipe b force quirk\n");
15267 }
15268
15269 /*
15270 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15271 */
15272 static void quirk_ssc_force_disable(struct drm_device *dev)
15273 {
15274 struct drm_i915_private *dev_priv = dev->dev_private;
15275 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15276 DRM_INFO("applying lvds SSC disable quirk\n");
15277 }
15278
15279 /*
15280 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15281 * brightness value
15282 */
15283 static void quirk_invert_brightness(struct drm_device *dev)
15284 {
15285 struct drm_i915_private *dev_priv = dev->dev_private;
15286 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15287 DRM_INFO("applying inverted panel brightness quirk\n");
15288 }
15289
15290 /* Some VBT's incorrectly indicate no backlight is present */
15291 static void quirk_backlight_present(struct drm_device *dev)
15292 {
15293 struct drm_i915_private *dev_priv = dev->dev_private;
15294 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15295 DRM_INFO("applying backlight present quirk\n");
15296 }
15297
15298 struct intel_quirk {
15299 int device;
15300 int subsystem_vendor;
15301 int subsystem_device;
15302 void (*hook)(struct drm_device *dev);
15303 };
15304
15305 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15306 struct intel_dmi_quirk {
15307 void (*hook)(struct drm_device *dev);
15308 const struct dmi_system_id (*dmi_id_list)[];
15309 };
15310
15311 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15312 {
15313 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15314 return 1;
15315 }
15316
15317 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15318 {
15319 .dmi_id_list = &(const struct dmi_system_id[]) {
15320 {
15321 .callback = intel_dmi_reverse_brightness,
15322 .ident = "NCR Corporation",
15323 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15324 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15325 },
15326 },
15327 { } /* terminating entry */
15328 },
15329 .hook = quirk_invert_brightness,
15330 },
15331 };
15332
15333 static struct intel_quirk intel_quirks[] = {
15334 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15335 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15336
15337 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15338 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15339
15340 /* 830 needs to leave pipe A & dpll A up */
15341 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15342
15343 /* 830 needs to leave pipe B & dpll B up */
15344 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15345
15346 /* Lenovo U160 cannot use SSC on LVDS */
15347 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15348
15349 /* Sony Vaio Y cannot use SSC on LVDS */
15350 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15351
15352 /* Acer Aspire 5734Z must invert backlight brightness */
15353 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15354
15355 /* Acer/eMachines G725 */
15356 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15357
15358 /* Acer/eMachines e725 */
15359 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15360
15361 /* Acer/Packard Bell NCL20 */
15362 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15363
15364 /* Acer Aspire 4736Z */
15365 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15366
15367 /* Acer Aspire 5336 */
15368 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15369
15370 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15371 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15372
15373 /* Acer C720 Chromebook (Core i3 4005U) */
15374 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15375
15376 /* Apple Macbook 2,1 (Core 2 T7400) */
15377 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15378
15379 /* Apple Macbook 4,1 */
15380 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15381
15382 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15383 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15384
15385 /* HP Chromebook 14 (Celeron 2955U) */
15386 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15387
15388 /* Dell Chromebook 11 */
15389 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15390
15391 /* Dell Chromebook 11 (2015 version) */
15392 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15393 };
15394
15395 static void intel_init_quirks(struct drm_device *dev)
15396 {
15397 struct pci_dev *d = dev->pdev;
15398 int i;
15399
15400 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15401 struct intel_quirk *q = &intel_quirks[i];
15402
15403 if (d->device == q->device &&
15404 (d->subsystem_vendor == q->subsystem_vendor ||
15405 q->subsystem_vendor == PCI_ANY_ID) &&
15406 (d->subsystem_device == q->subsystem_device ||
15407 q->subsystem_device == PCI_ANY_ID))
15408 q->hook(dev);
15409 }
15410 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15411 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15412 intel_dmi_quirks[i].hook(dev);
15413 }
15414 }
15415
15416 /* Disable the VGA plane that we never use */
15417 static void i915_disable_vga(struct drm_device *dev)
15418 {
15419 struct drm_i915_private *dev_priv = dev->dev_private;
15420 u8 sr1;
15421 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15422
15423 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15424 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15425 outb(SR01, VGA_SR_INDEX);
15426 sr1 = inb(VGA_SR_DATA);
15427 outb(sr1 | 1<<5, VGA_SR_DATA);
15428 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15429 udelay(300);
15430
15431 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15432 POSTING_READ(vga_reg);
15433 }
15434
15435 void intel_modeset_init_hw(struct drm_device *dev)
15436 {
15437 struct drm_i915_private *dev_priv = dev->dev_private;
15438
15439 intel_update_cdclk(dev);
15440
15441 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15442
15443 intel_init_clock_gating(dev);
15444 intel_enable_gt_powersave(dev_priv);
15445 }
15446
15447 /*
15448 * Calculate what we think the watermarks should be for the state we've read
15449 * out of the hardware and then immediately program those watermarks so that
15450 * we ensure the hardware settings match our internal state.
15451 *
15452 * We can calculate what we think WM's should be by creating a duplicate of the
15453 * current state (which was constructed during hardware readout) and running it
15454 * through the atomic check code to calculate new watermark values in the
15455 * state object.
15456 */
15457 static void sanitize_watermarks(struct drm_device *dev)
15458 {
15459 struct drm_i915_private *dev_priv = to_i915(dev);
15460 struct drm_atomic_state *state;
15461 struct drm_crtc *crtc;
15462 struct drm_crtc_state *cstate;
15463 struct drm_modeset_acquire_ctx ctx;
15464 int ret;
15465 int i;
15466
15467 /* Only supported on platforms that use atomic watermark design */
15468 if (!dev_priv->display.optimize_watermarks)
15469 return;
15470
15471 /*
15472 * We need to hold connection_mutex before calling duplicate_state so
15473 * that the connector loop is protected.
15474 */
15475 drm_modeset_acquire_init(&ctx, 0);
15476 retry:
15477 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15478 if (ret == -EDEADLK) {
15479 drm_modeset_backoff(&ctx);
15480 goto retry;
15481 } else if (WARN_ON(ret)) {
15482 goto fail;
15483 }
15484
15485 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15486 if (WARN_ON(IS_ERR(state)))
15487 goto fail;
15488
15489 /*
15490 * Hardware readout is the only time we don't want to calculate
15491 * intermediate watermarks (since we don't trust the current
15492 * watermarks).
15493 */
15494 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15495
15496 ret = intel_atomic_check(dev, state);
15497 if (ret) {
15498 /*
15499 * If we fail here, it means that the hardware appears to be
15500 * programmed in a way that shouldn't be possible, given our
15501 * understanding of watermark requirements. This might mean a
15502 * mistake in the hardware readout code or a mistake in the
15503 * watermark calculations for a given platform. Raise a WARN
15504 * so that this is noticeable.
15505 *
15506 * If this actually happens, we'll have to just leave the
15507 * BIOS-programmed watermarks untouched and hope for the best.
15508 */
15509 WARN(true, "Could not determine valid watermarks for inherited state\n");
15510 goto fail;
15511 }
15512
15513 /* Write calculated watermark values back */
15514 for_each_crtc_in_state(state, crtc, cstate, i) {
15515 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15516
15517 cs->wm.need_postvbl_update = true;
15518 dev_priv->display.optimize_watermarks(cs);
15519 }
15520
15521 drm_atomic_state_free(state);
15522 fail:
15523 drm_modeset_drop_locks(&ctx);
15524 drm_modeset_acquire_fini(&ctx);
15525 }
15526
15527 void intel_modeset_init(struct drm_device *dev)
15528 {
15529 struct drm_i915_private *dev_priv = to_i915(dev);
15530 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15531 int sprite, ret;
15532 enum pipe pipe;
15533 struct intel_crtc *crtc;
15534
15535 drm_mode_config_init(dev);
15536
15537 dev->mode_config.min_width = 0;
15538 dev->mode_config.min_height = 0;
15539
15540 dev->mode_config.preferred_depth = 24;
15541 dev->mode_config.prefer_shadow = 1;
15542
15543 dev->mode_config.allow_fb_modifiers = true;
15544
15545 dev->mode_config.funcs = &intel_mode_funcs;
15546
15547 intel_init_quirks(dev);
15548
15549 intel_init_pm(dev);
15550
15551 if (INTEL_INFO(dev)->num_pipes == 0)
15552 return;
15553
15554 /*
15555 * There may be no VBT; and if the BIOS enabled SSC we can
15556 * just keep using it to avoid unnecessary flicker. Whereas if the
15557 * BIOS isn't using it, don't assume it will work even if the VBT
15558 * indicates as much.
15559 */
15560 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15561 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15562 DREF_SSC1_ENABLE);
15563
15564 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15565 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15566 bios_lvds_use_ssc ? "en" : "dis",
15567 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15568 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15569 }
15570 }
15571
15572 if (IS_GEN2(dev)) {
15573 dev->mode_config.max_width = 2048;
15574 dev->mode_config.max_height = 2048;
15575 } else if (IS_GEN3(dev)) {
15576 dev->mode_config.max_width = 4096;
15577 dev->mode_config.max_height = 4096;
15578 } else {
15579 dev->mode_config.max_width = 8192;
15580 dev->mode_config.max_height = 8192;
15581 }
15582
15583 if (IS_845G(dev) || IS_I865G(dev)) {
15584 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15585 dev->mode_config.cursor_height = 1023;
15586 } else if (IS_GEN2(dev)) {
15587 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15588 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15589 } else {
15590 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15591 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15592 }
15593
15594 dev->mode_config.fb_base = ggtt->mappable_base;
15595
15596 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15597 INTEL_INFO(dev)->num_pipes,
15598 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15599
15600 for_each_pipe(dev_priv, pipe) {
15601 intel_crtc_init(dev, pipe);
15602 for_each_sprite(dev_priv, pipe, sprite) {
15603 ret = intel_plane_init(dev, pipe, sprite);
15604 if (ret)
15605 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15606 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15607 }
15608 }
15609
15610 intel_update_czclk(dev_priv);
15611 intel_update_cdclk(dev);
15612
15613 intel_shared_dpll_init(dev);
15614
15615 if (dev_priv->max_cdclk_freq == 0)
15616 intel_update_max_cdclk(dev);
15617
15618 /* Just disable it once at startup */
15619 i915_disable_vga(dev);
15620 intel_setup_outputs(dev);
15621
15622 drm_modeset_lock_all(dev);
15623 intel_modeset_setup_hw_state(dev);
15624 drm_modeset_unlock_all(dev);
15625
15626 for_each_intel_crtc(dev, crtc) {
15627 struct intel_initial_plane_config plane_config = {};
15628
15629 if (!crtc->active)
15630 continue;
15631
15632 /*
15633 * Note that reserving the BIOS fb up front prevents us
15634 * from stuffing other stolen allocations like the ring
15635 * on top. This prevents some ugliness at boot time, and
15636 * can even allow for smooth boot transitions if the BIOS
15637 * fb is large enough for the active pipe configuration.
15638 */
15639 dev_priv->display.get_initial_plane_config(crtc,
15640 &plane_config);
15641
15642 /*
15643 * If the fb is shared between multiple heads, we'll
15644 * just get the first one.
15645 */
15646 intel_find_initial_plane_obj(crtc, &plane_config);
15647 }
15648
15649 /*
15650 * Make sure hardware watermarks really match the state we read out.
15651 * Note that we need to do this after reconstructing the BIOS fb's
15652 * since the watermark calculation done here will use pstate->fb.
15653 */
15654 sanitize_watermarks(dev);
15655 }
15656
15657 static void intel_enable_pipe_a(struct drm_device *dev)
15658 {
15659 struct intel_connector *connector;
15660 struct drm_connector *crt = NULL;
15661 struct intel_load_detect_pipe load_detect_temp;
15662 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15663
15664 /* We can't just switch on the pipe A, we need to set things up with a
15665 * proper mode and output configuration. As a gross hack, enable pipe A
15666 * by enabling the load detect pipe once. */
15667 for_each_intel_connector(dev, connector) {
15668 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15669 crt = &connector->base;
15670 break;
15671 }
15672 }
15673
15674 if (!crt)
15675 return;
15676
15677 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15678 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15679 }
15680
15681 static bool
15682 intel_check_plane_mapping(struct intel_crtc *crtc)
15683 {
15684 struct drm_device *dev = crtc->base.dev;
15685 struct drm_i915_private *dev_priv = dev->dev_private;
15686 u32 val;
15687
15688 if (INTEL_INFO(dev)->num_pipes == 1)
15689 return true;
15690
15691 val = I915_READ(DSPCNTR(!crtc->plane));
15692
15693 if ((val & DISPLAY_PLANE_ENABLE) &&
15694 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15695 return false;
15696
15697 return true;
15698 }
15699
15700 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15701 {
15702 struct drm_device *dev = crtc->base.dev;
15703 struct intel_encoder *encoder;
15704
15705 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15706 return true;
15707
15708 return false;
15709 }
15710
15711 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15712 {
15713 struct drm_device *dev = encoder->base.dev;
15714 struct intel_connector *connector;
15715
15716 for_each_connector_on_encoder(dev, &encoder->base, connector)
15717 return true;
15718
15719 return false;
15720 }
15721
15722 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15723 {
15724 struct drm_device *dev = crtc->base.dev;
15725 struct drm_i915_private *dev_priv = dev->dev_private;
15726 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15727
15728 /* Clear any frame start delays used for debugging left by the BIOS */
15729 if (!transcoder_is_dsi(cpu_transcoder)) {
15730 i915_reg_t reg = PIPECONF(cpu_transcoder);
15731
15732 I915_WRITE(reg,
15733 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15734 }
15735
15736 /* restore vblank interrupts to correct state */
15737 drm_crtc_vblank_reset(&crtc->base);
15738 if (crtc->active) {
15739 struct intel_plane *plane;
15740
15741 drm_crtc_vblank_on(&crtc->base);
15742
15743 /* Disable everything but the primary plane */
15744 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15745 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15746 continue;
15747
15748 plane->disable_plane(&plane->base, &crtc->base);
15749 }
15750 }
15751
15752 /* We need to sanitize the plane -> pipe mapping first because this will
15753 * disable the crtc (and hence change the state) if it is wrong. Note
15754 * that gen4+ has a fixed plane -> pipe mapping. */
15755 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15756 bool plane;
15757
15758 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15759 crtc->base.base.id, crtc->base.name);
15760
15761 /* Pipe has the wrong plane attached and the plane is active.
15762 * Temporarily change the plane mapping and disable everything
15763 * ... */
15764 plane = crtc->plane;
15765 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15766 crtc->plane = !plane;
15767 intel_crtc_disable_noatomic(&crtc->base);
15768 crtc->plane = plane;
15769 }
15770
15771 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15772 crtc->pipe == PIPE_A && !crtc->active) {
15773 /* BIOS forgot to enable pipe A, this mostly happens after
15774 * resume. Force-enable the pipe to fix this, the update_dpms
15775 * call below we restore the pipe to the right state, but leave
15776 * the required bits on. */
15777 intel_enable_pipe_a(dev);
15778 }
15779
15780 /* Adjust the state of the output pipe according to whether we
15781 * have active connectors/encoders. */
15782 if (crtc->active && !intel_crtc_has_encoders(crtc))
15783 intel_crtc_disable_noatomic(&crtc->base);
15784
15785 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15786 /*
15787 * We start out with underrun reporting disabled to avoid races.
15788 * For correct bookkeeping mark this on active crtcs.
15789 *
15790 * Also on gmch platforms we dont have any hardware bits to
15791 * disable the underrun reporting. Which means we need to start
15792 * out with underrun reporting disabled also on inactive pipes,
15793 * since otherwise we'll complain about the garbage we read when
15794 * e.g. coming up after runtime pm.
15795 *
15796 * No protection against concurrent access is required - at
15797 * worst a fifo underrun happens which also sets this to false.
15798 */
15799 crtc->cpu_fifo_underrun_disabled = true;
15800 crtc->pch_fifo_underrun_disabled = true;
15801 }
15802 }
15803
15804 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15805 {
15806 struct intel_connector *connector;
15807 struct drm_device *dev = encoder->base.dev;
15808
15809 /* We need to check both for a crtc link (meaning that the
15810 * encoder is active and trying to read from a pipe) and the
15811 * pipe itself being active. */
15812 bool has_active_crtc = encoder->base.crtc &&
15813 to_intel_crtc(encoder->base.crtc)->active;
15814
15815 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15816 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15817 encoder->base.base.id,
15818 encoder->base.name);
15819
15820 /* Connector is active, but has no active pipe. This is
15821 * fallout from our resume register restoring. Disable
15822 * the encoder manually again. */
15823 if (encoder->base.crtc) {
15824 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15825 encoder->base.base.id,
15826 encoder->base.name);
15827 encoder->disable(encoder);
15828 if (encoder->post_disable)
15829 encoder->post_disable(encoder);
15830 }
15831 encoder->base.crtc = NULL;
15832
15833 /* Inconsistent output/port/pipe state happens presumably due to
15834 * a bug in one of the get_hw_state functions. Or someplace else
15835 * in our code, like the register restore mess on resume. Clamp
15836 * things to off as a safer default. */
15837 for_each_intel_connector(dev, connector) {
15838 if (connector->encoder != encoder)
15839 continue;
15840 connector->base.dpms = DRM_MODE_DPMS_OFF;
15841 connector->base.encoder = NULL;
15842 }
15843 }
15844 /* Enabled encoders without active connectors will be fixed in
15845 * the crtc fixup. */
15846 }
15847
15848 void i915_redisable_vga_power_on(struct drm_device *dev)
15849 {
15850 struct drm_i915_private *dev_priv = dev->dev_private;
15851 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15852
15853 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15854 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15855 i915_disable_vga(dev);
15856 }
15857 }
15858
15859 void i915_redisable_vga(struct drm_device *dev)
15860 {
15861 struct drm_i915_private *dev_priv = dev->dev_private;
15862
15863 /* This function can be called both from intel_modeset_setup_hw_state or
15864 * at a very early point in our resume sequence, where the power well
15865 * structures are not yet restored. Since this function is at a very
15866 * paranoid "someone might have enabled VGA while we were not looking"
15867 * level, just check if the power well is enabled instead of trying to
15868 * follow the "don't touch the power well if we don't need it" policy
15869 * the rest of the driver uses. */
15870 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15871 return;
15872
15873 i915_redisable_vga_power_on(dev);
15874
15875 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15876 }
15877
15878 static bool primary_get_hw_state(struct intel_plane *plane)
15879 {
15880 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15881
15882 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15883 }
15884
15885 /* FIXME read out full plane state for all planes */
15886 static void readout_plane_state(struct intel_crtc *crtc)
15887 {
15888 struct drm_plane *primary = crtc->base.primary;
15889 struct intel_plane_state *plane_state =
15890 to_intel_plane_state(primary->state);
15891
15892 plane_state->visible = crtc->active &&
15893 primary_get_hw_state(to_intel_plane(primary));
15894
15895 if (plane_state->visible)
15896 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15897 }
15898
15899 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15900 {
15901 struct drm_i915_private *dev_priv = dev->dev_private;
15902 enum pipe pipe;
15903 struct intel_crtc *crtc;
15904 struct intel_encoder *encoder;
15905 struct intel_connector *connector;
15906 int i;
15907
15908 dev_priv->active_crtcs = 0;
15909
15910 for_each_intel_crtc(dev, crtc) {
15911 struct intel_crtc_state *crtc_state = crtc->config;
15912 int pixclk = 0;
15913
15914 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15915 memset(crtc_state, 0, sizeof(*crtc_state));
15916 crtc_state->base.crtc = &crtc->base;
15917
15918 crtc_state->base.active = crtc_state->base.enable =
15919 dev_priv->display.get_pipe_config(crtc, crtc_state);
15920
15921 crtc->base.enabled = crtc_state->base.enable;
15922 crtc->active = crtc_state->base.active;
15923
15924 if (crtc_state->base.active) {
15925 dev_priv->active_crtcs |= 1 << crtc->pipe;
15926
15927 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15928 pixclk = ilk_pipe_pixel_rate(crtc_state);
15929 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15930 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15931 else
15932 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15933
15934 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15935 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15936 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15937 }
15938
15939 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15940
15941 readout_plane_state(crtc);
15942
15943 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15944 crtc->base.base.id, crtc->base.name,
15945 crtc->active ? "enabled" : "disabled");
15946 }
15947
15948 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15949 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15950
15951 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15952 &pll->config.hw_state);
15953 pll->config.crtc_mask = 0;
15954 for_each_intel_crtc(dev, crtc) {
15955 if (crtc->active && crtc->config->shared_dpll == pll)
15956 pll->config.crtc_mask |= 1 << crtc->pipe;
15957 }
15958 pll->active_mask = pll->config.crtc_mask;
15959
15960 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15961 pll->name, pll->config.crtc_mask, pll->on);
15962 }
15963
15964 for_each_intel_encoder(dev, encoder) {
15965 pipe = 0;
15966
15967 if (encoder->get_hw_state(encoder, &pipe)) {
15968 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15969 encoder->base.crtc = &crtc->base;
15970 encoder->get_config(encoder, crtc->config);
15971 } else {
15972 encoder->base.crtc = NULL;
15973 }
15974
15975 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15976 encoder->base.base.id,
15977 encoder->base.name,
15978 encoder->base.crtc ? "enabled" : "disabled",
15979 pipe_name(pipe));
15980 }
15981
15982 for_each_intel_connector(dev, connector) {
15983 if (connector->get_hw_state(connector)) {
15984 connector->base.dpms = DRM_MODE_DPMS_ON;
15985
15986 encoder = connector->encoder;
15987 connector->base.encoder = &encoder->base;
15988
15989 if (encoder->base.crtc &&
15990 encoder->base.crtc->state->active) {
15991 /*
15992 * This has to be done during hardware readout
15993 * because anything calling .crtc_disable may
15994 * rely on the connector_mask being accurate.
15995 */
15996 encoder->base.crtc->state->connector_mask |=
15997 1 << drm_connector_index(&connector->base);
15998 encoder->base.crtc->state->encoder_mask |=
15999 1 << drm_encoder_index(&encoder->base);
16000 }
16001
16002 } else {
16003 connector->base.dpms = DRM_MODE_DPMS_OFF;
16004 connector->base.encoder = NULL;
16005 }
16006 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16007 connector->base.base.id,
16008 connector->base.name,
16009 connector->base.encoder ? "enabled" : "disabled");
16010 }
16011
16012 for_each_intel_crtc(dev, crtc) {
16013 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16014
16015 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16016 if (crtc->base.state->active) {
16017 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16018 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16019 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16020
16021 /*
16022 * The initial mode needs to be set in order to keep
16023 * the atomic core happy. It wants a valid mode if the
16024 * crtc's enabled, so we do the above call.
16025 *
16026 * At this point some state updated by the connectors
16027 * in their ->detect() callback has not run yet, so
16028 * no recalculation can be done yet.
16029 *
16030 * Even if we could do a recalculation and modeset
16031 * right now it would cause a double modeset if
16032 * fbdev or userspace chooses a different initial mode.
16033 *
16034 * If that happens, someone indicated they wanted a
16035 * mode change, which means it's safe to do a full
16036 * recalculation.
16037 */
16038 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16039
16040 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16041 update_scanline_offset(crtc);
16042 }
16043
16044 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16045 }
16046 }
16047
16048 /* Scan out the current hw modeset state,
16049 * and sanitizes it to the current state
16050 */
16051 static void
16052 intel_modeset_setup_hw_state(struct drm_device *dev)
16053 {
16054 struct drm_i915_private *dev_priv = dev->dev_private;
16055 enum pipe pipe;
16056 struct intel_crtc *crtc;
16057 struct intel_encoder *encoder;
16058 int i;
16059
16060 intel_modeset_readout_hw_state(dev);
16061
16062 /* HW state is read out, now we need to sanitize this mess. */
16063 for_each_intel_encoder(dev, encoder) {
16064 intel_sanitize_encoder(encoder);
16065 }
16066
16067 for_each_pipe(dev_priv, pipe) {
16068 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16069 intel_sanitize_crtc(crtc);
16070 intel_dump_pipe_config(crtc, crtc->config,
16071 "[setup_hw_state]");
16072 }
16073
16074 intel_modeset_update_connector_atomic_state(dev);
16075
16076 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16077 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16078
16079 if (!pll->on || pll->active_mask)
16080 continue;
16081
16082 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16083
16084 pll->funcs.disable(dev_priv, pll);
16085 pll->on = false;
16086 }
16087
16088 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16089 vlv_wm_get_hw_state(dev);
16090 else if (IS_GEN9(dev))
16091 skl_wm_get_hw_state(dev);
16092 else if (HAS_PCH_SPLIT(dev))
16093 ilk_wm_get_hw_state(dev);
16094
16095 for_each_intel_crtc(dev, crtc) {
16096 unsigned long put_domains;
16097
16098 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16099 if (WARN_ON(put_domains))
16100 modeset_put_power_domains(dev_priv, put_domains);
16101 }
16102 intel_display_set_init_power(dev_priv, false);
16103
16104 intel_fbc_init_pipe_state(dev_priv);
16105 }
16106
16107 void intel_display_resume(struct drm_device *dev)
16108 {
16109 struct drm_i915_private *dev_priv = to_i915(dev);
16110 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16111 struct drm_modeset_acquire_ctx ctx;
16112 int ret;
16113 bool setup = false;
16114
16115 dev_priv->modeset_restore_state = NULL;
16116
16117 /*
16118 * This is a cludge because with real atomic modeset mode_config.mutex
16119 * won't be taken. Unfortunately some probed state like
16120 * audio_codec_enable is still protected by mode_config.mutex, so lock
16121 * it here for now.
16122 */
16123 mutex_lock(&dev->mode_config.mutex);
16124 drm_modeset_acquire_init(&ctx, 0);
16125
16126 retry:
16127 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16128
16129 if (ret == 0 && !setup) {
16130 setup = true;
16131
16132 intel_modeset_setup_hw_state(dev);
16133 i915_redisable_vga(dev);
16134 }
16135
16136 if (ret == 0 && state) {
16137 struct drm_crtc_state *crtc_state;
16138 struct drm_crtc *crtc;
16139 int i;
16140
16141 state->acquire_ctx = &ctx;
16142
16143 /* ignore any reset values/BIOS leftovers in the WM registers */
16144 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16145
16146 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16147 /*
16148 * Force recalculation even if we restore
16149 * current state. With fast modeset this may not result
16150 * in a modeset when the state is compatible.
16151 */
16152 crtc_state->mode_changed = true;
16153 }
16154
16155 ret = drm_atomic_commit(state);
16156 }
16157
16158 if (ret == -EDEADLK) {
16159 drm_modeset_backoff(&ctx);
16160 goto retry;
16161 }
16162
16163 drm_modeset_drop_locks(&ctx);
16164 drm_modeset_acquire_fini(&ctx);
16165 mutex_unlock(&dev->mode_config.mutex);
16166
16167 if (ret) {
16168 DRM_ERROR("Restoring old state failed with %i\n", ret);
16169 drm_atomic_state_free(state);
16170 }
16171 }
16172
16173 void intel_modeset_gem_init(struct drm_device *dev)
16174 {
16175 struct drm_i915_private *dev_priv = to_i915(dev);
16176 struct drm_crtc *c;
16177 struct drm_i915_gem_object *obj;
16178 int ret;
16179
16180 intel_init_gt_powersave(dev_priv);
16181
16182 intel_modeset_init_hw(dev);
16183
16184 intel_setup_overlay(dev_priv);
16185
16186 /*
16187 * Make sure any fbs we allocated at startup are properly
16188 * pinned & fenced. When we do the allocation it's too early
16189 * for this.
16190 */
16191 for_each_crtc(dev, c) {
16192 obj = intel_fb_obj(c->primary->fb);
16193 if (obj == NULL)
16194 continue;
16195
16196 mutex_lock(&dev->struct_mutex);
16197 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16198 c->primary->state->rotation);
16199 mutex_unlock(&dev->struct_mutex);
16200 if (ret) {
16201 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16202 to_intel_crtc(c)->pipe);
16203 drm_framebuffer_unreference(c->primary->fb);
16204 c->primary->fb = NULL;
16205 c->primary->crtc = c->primary->state->crtc = NULL;
16206 update_state_fb(c->primary);
16207 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16208 }
16209 }
16210
16211 intel_backlight_register(dev);
16212 }
16213
16214 void intel_connector_unregister(struct intel_connector *intel_connector)
16215 {
16216 struct drm_connector *connector = &intel_connector->base;
16217
16218 intel_panel_destroy_backlight(connector);
16219 drm_connector_unregister(connector);
16220 }
16221
16222 void intel_modeset_cleanup(struct drm_device *dev)
16223 {
16224 struct drm_i915_private *dev_priv = dev->dev_private;
16225 struct intel_connector *connector;
16226
16227 intel_disable_gt_powersave(dev_priv);
16228
16229 intel_backlight_unregister(dev);
16230
16231 /*
16232 * Interrupts and polling as the first thing to avoid creating havoc.
16233 * Too much stuff here (turning of connectors, ...) would
16234 * experience fancy races otherwise.
16235 */
16236 intel_irq_uninstall(dev_priv);
16237
16238 /*
16239 * Due to the hpd irq storm handling the hotplug work can re-arm the
16240 * poll handlers. Hence disable polling after hpd handling is shut down.
16241 */
16242 drm_kms_helper_poll_fini(dev);
16243
16244 intel_unregister_dsm_handler();
16245
16246 intel_fbc_global_disable(dev_priv);
16247
16248 /* flush any delayed tasks or pending work */
16249 flush_scheduled_work();
16250
16251 /* destroy the backlight and sysfs files before encoders/connectors */
16252 for_each_intel_connector(dev, connector)
16253 connector->unregister(connector);
16254
16255 drm_mode_config_cleanup(dev);
16256
16257 intel_cleanup_overlay(dev_priv);
16258
16259 intel_cleanup_gt_powersave(dev_priv);
16260
16261 intel_teardown_gmbus(dev);
16262 }
16263
16264 /*
16265 * Return which encoder is currently attached for connector.
16266 */
16267 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16268 {
16269 return &intel_attached_encoder(connector)->base;
16270 }
16271
16272 void intel_connector_attach_encoder(struct intel_connector *connector,
16273 struct intel_encoder *encoder)
16274 {
16275 connector->encoder = encoder;
16276 drm_mode_connector_attach_encoder(&connector->base,
16277 &encoder->base);
16278 }
16279
16280 /*
16281 * set vga decode state - true == enable VGA decode
16282 */
16283 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16284 {
16285 struct drm_i915_private *dev_priv = dev->dev_private;
16286 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16287 u16 gmch_ctrl;
16288
16289 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16290 DRM_ERROR("failed to read control word\n");
16291 return -EIO;
16292 }
16293
16294 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16295 return 0;
16296
16297 if (state)
16298 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16299 else
16300 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16301
16302 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16303 DRM_ERROR("failed to write control word\n");
16304 return -EIO;
16305 }
16306
16307 return 0;
16308 }
16309
16310 struct intel_display_error_state {
16311
16312 u32 power_well_driver;
16313
16314 int num_transcoders;
16315
16316 struct intel_cursor_error_state {
16317 u32 control;
16318 u32 position;
16319 u32 base;
16320 u32 size;
16321 } cursor[I915_MAX_PIPES];
16322
16323 struct intel_pipe_error_state {
16324 bool power_domain_on;
16325 u32 source;
16326 u32 stat;
16327 } pipe[I915_MAX_PIPES];
16328
16329 struct intel_plane_error_state {
16330 u32 control;
16331 u32 stride;
16332 u32 size;
16333 u32 pos;
16334 u32 addr;
16335 u32 surface;
16336 u32 tile_offset;
16337 } plane[I915_MAX_PIPES];
16338
16339 struct intel_transcoder_error_state {
16340 bool power_domain_on;
16341 enum transcoder cpu_transcoder;
16342
16343 u32 conf;
16344
16345 u32 htotal;
16346 u32 hblank;
16347 u32 hsync;
16348 u32 vtotal;
16349 u32 vblank;
16350 u32 vsync;
16351 } transcoder[4];
16352 };
16353
16354 struct intel_display_error_state *
16355 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16356 {
16357 struct intel_display_error_state *error;
16358 int transcoders[] = {
16359 TRANSCODER_A,
16360 TRANSCODER_B,
16361 TRANSCODER_C,
16362 TRANSCODER_EDP,
16363 };
16364 int i;
16365
16366 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16367 return NULL;
16368
16369 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16370 if (error == NULL)
16371 return NULL;
16372
16373 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16374 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16375
16376 for_each_pipe(dev_priv, i) {
16377 error->pipe[i].power_domain_on =
16378 __intel_display_power_is_enabled(dev_priv,
16379 POWER_DOMAIN_PIPE(i));
16380 if (!error->pipe[i].power_domain_on)
16381 continue;
16382
16383 error->cursor[i].control = I915_READ(CURCNTR(i));
16384 error->cursor[i].position = I915_READ(CURPOS(i));
16385 error->cursor[i].base = I915_READ(CURBASE(i));
16386
16387 error->plane[i].control = I915_READ(DSPCNTR(i));
16388 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16389 if (INTEL_GEN(dev_priv) <= 3) {
16390 error->plane[i].size = I915_READ(DSPSIZE(i));
16391 error->plane[i].pos = I915_READ(DSPPOS(i));
16392 }
16393 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16394 error->plane[i].addr = I915_READ(DSPADDR(i));
16395 if (INTEL_GEN(dev_priv) >= 4) {
16396 error->plane[i].surface = I915_READ(DSPSURF(i));
16397 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16398 }
16399
16400 error->pipe[i].source = I915_READ(PIPESRC(i));
16401
16402 if (HAS_GMCH_DISPLAY(dev_priv))
16403 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16404 }
16405
16406 /* Note: this does not include DSI transcoders. */
16407 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16408 if (HAS_DDI(dev_priv))
16409 error->num_transcoders++; /* Account for eDP. */
16410
16411 for (i = 0; i < error->num_transcoders; i++) {
16412 enum transcoder cpu_transcoder = transcoders[i];
16413
16414 error->transcoder[i].power_domain_on =
16415 __intel_display_power_is_enabled(dev_priv,
16416 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16417 if (!error->transcoder[i].power_domain_on)
16418 continue;
16419
16420 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16421
16422 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16423 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16424 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16425 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16426 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16427 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16428 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16429 }
16430
16431 return error;
16432 }
16433
16434 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16435
16436 void
16437 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16438 struct drm_device *dev,
16439 struct intel_display_error_state *error)
16440 {
16441 struct drm_i915_private *dev_priv = dev->dev_private;
16442 int i;
16443
16444 if (!error)
16445 return;
16446
16447 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16448 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16449 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16450 error->power_well_driver);
16451 for_each_pipe(dev_priv, i) {
16452 err_printf(m, "Pipe [%d]:\n", i);
16453 err_printf(m, " Power: %s\n",
16454 onoff(error->pipe[i].power_domain_on));
16455 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16456 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16457
16458 err_printf(m, "Plane [%d]:\n", i);
16459 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16460 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16461 if (INTEL_INFO(dev)->gen <= 3) {
16462 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16463 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16464 }
16465 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16466 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16467 if (INTEL_INFO(dev)->gen >= 4) {
16468 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16469 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16470 }
16471
16472 err_printf(m, "Cursor [%d]:\n", i);
16473 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16474 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16475 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16476 }
16477
16478 for (i = 0; i < error->num_transcoders; i++) {
16479 err_printf(m, "CPU transcoder: %s\n",
16480 transcoder_name(error->transcoder[i].cpu_transcoder));
16481 err_printf(m, " Power: %s\n",
16482 onoff(error->transcoder[i].power_domain_on));
16483 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16484 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16485 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16486 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16487 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16488 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16489 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16490 }
16491 }
Linux kernel - Deliverables
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