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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
80 };
81
82 /* FDI */
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
85 int
86 intel_pch_rawclk(struct drm_device *dev)
87 {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93 }
94
95 static bool
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99 static bool
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
103
104 static bool
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
111 {
112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
117 }
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
131 };
132
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
145 };
146
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
159 };
160
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
173 };
174
175
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
188 },
189 .find_pll = intel_g4x_find_best_PLL,
190 };
191
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
204 };
205
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
217 },
218 .find_pll = intel_g4x_find_best_PLL,
219 };
220
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
232 },
233 .find_pll = intel_g4x_find_best_PLL,
234 };
235
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
250 };
251
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
264 };
265
266 /* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
283 };
284
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
311 };
312
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
340 };
341
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354 };
355
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368 };
369
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382 };
383
384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385 {
386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
387
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
390 return 0;
391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
398 return 0;
399 }
400
401 return I915_READ(DPIO_DATA);
402 }
403
404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
405 {
406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
407
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
410 return;
411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
419 }
420
421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
423 {
424 struct drm_device *dev = crtc->dev;
425 const intel_limit_t *limit;
426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
439 } else
440 limit = &intel_limits_ironlake_dac;
441
442 return limit;
443 }
444
445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446 {
447 struct drm_device *dev = crtc->dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
453 else
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
462
463 return limit;
464 }
465
466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
467 {
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
478 else
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
494 limit = &intel_limits_i8xx_lvds;
495 else
496 limit = &intel_limits_i8xx_dvo;
497 }
498 return limit;
499 }
500
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk, intel_clock_t *clock)
503 {
504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508 }
509
510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511 {
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513 }
514
515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516 {
517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
519 return;
520 }
521 clock->m = i9xx_dpll_compute_m(clock);
522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525 }
526
527 /**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
531 {
532 struct drm_device *dev = crtc->dev;
533 struct intel_encoder *encoder;
534
535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
537 return true;
538
539 return false;
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock->p < limit->p.min || limit->p.max < clock->p)
555 INTELPllInvalid("p out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock->m < limit->m.min || limit->m.max < clock->m)
563 INTELPllInvalid("m out of range\n");
564 if (clock->n < limit->n.min || limit->n.max < clock->n)
565 INTELPllInvalid("n out of range\n");
566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
572 INTELPllInvalid("dot out of range\n");
573
574 return true;
575 }
576
577 static bool
578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
581
582 {
583 struct drm_device *dev = crtc->dev;
584 intel_clock_t clock;
585 int err = target;
586
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
588 /*
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
592 */
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
604 memset(best_clock, 0, sizeof(*best_clock));
605
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
617 int this_err;
618
619 intel_clock(dev, refclk, &clock);
620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
622 continue;
623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638 }
639
640 static bool
641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
644 {
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
647 int max_n;
648 bool found;
649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666 max_n = limit->n.max;
667 /* based on hardware requirement, prefer smaller n to precision */
668 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
669 /* based on hardware requirement, prefere larger m1,m2 */
670 for (clock.m1 = limit->m1.max;
671 clock.m1 >= limit->m1.min; clock.m1--) {
672 for (clock.m2 = limit->m2.max;
673 clock.m2 >= limit->m2.min; clock.m2--) {
674 for (clock.p1 = limit->p1.max;
675 clock.p1 >= limit->p1.min; clock.p1--) {
676 int this_err;
677
678 intel_clock(dev, refclk, &clock);
679 if (!intel_PLL_is_valid(dev, limit,
680 &clock))
681 continue;
682
683 this_err = abs(clock.dot - target);
684 if (this_err < err_most) {
685 *best_clock = clock;
686 err_most = this_err;
687 max_n = clock.n;
688 found = true;
689 }
690 }
691 }
692 }
693 }
694 return found;
695 }
696
697 static bool
698 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
701 {
702 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
703 u32 m, n, fastclk;
704 u32 updrate, minupdate, fracbits, p;
705 unsigned long bestppm, ppm, absppm;
706 int dotclk, flag;
707
708 flag = 0;
709 dotclk = target * 1000;
710 bestppm = 1000000;
711 ppm = absppm = 0;
712 fastclk = dotclk / (2*100);
713 updrate = 0;
714 minupdate = 19200;
715 fracbits = 1;
716 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
717 bestm1 = bestm2 = bestp1 = bestp2 = 0;
718
719 /* based on hardware requirement, prefer smaller n to precision */
720 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
721 updrate = refclk / n;
722 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
723 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
724 if (p2 > 10)
725 p2 = p2 - 1;
726 p = p1 * p2;
727 /* based on hardware requirement, prefer bigger m1,m2 values */
728 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
729 m2 = (((2*(fastclk * p * n / m1 )) +
730 refclk) / (2*refclk));
731 m = m1 * m2;
732 vco = updrate * m;
733 if (vco >= limit->vco.min && vco < limit->vco.max) {
734 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
735 absppm = (ppm > 0) ? ppm : (-ppm);
736 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
737 bestppm = 0;
738 flag = 1;
739 }
740 if (absppm < bestppm - 10) {
741 bestppm = absppm;
742 flag = 1;
743 }
744 if (flag) {
745 bestn = n;
746 bestm1 = m1;
747 bestm2 = m2;
748 bestp1 = p1;
749 bestp2 = p2;
750 flag = 0;
751 }
752 }
753 }
754 }
755 }
756 }
757 best_clock->n = bestn;
758 best_clock->m1 = bestm1;
759 best_clock->m2 = bestm2;
760 best_clock->p1 = bestp1;
761 best_clock->p2 = bestp2;
762
763 return true;
764 }
765
766 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
767 enum pipe pipe)
768 {
769 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
771
772 return intel_crtc->config.cpu_transcoder;
773 }
774
775 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
776 {
777 struct drm_i915_private *dev_priv = dev->dev_private;
778 u32 frame, frame_reg = PIPEFRAME(pipe);
779
780 frame = I915_READ(frame_reg);
781
782 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
783 DRM_DEBUG_KMS("vblank wait timed out\n");
784 }
785
786 /**
787 * intel_wait_for_vblank - wait for vblank on a given pipe
788 * @dev: drm device
789 * @pipe: pipe to wait for
790 *
791 * Wait for vblank to occur on a given pipe. Needed for various bits of
792 * mode setting code.
793 */
794 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
795 {
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 int pipestat_reg = PIPESTAT(pipe);
798
799 if (INTEL_INFO(dev)->gen >= 5) {
800 ironlake_wait_for_vblank(dev, pipe);
801 return;
802 }
803
804 /* Clear existing vblank status. Note this will clear any other
805 * sticky status fields as well.
806 *
807 * This races with i915_driver_irq_handler() with the result
808 * that either function could miss a vblank event. Here it is not
809 * fatal, as we will either wait upon the next vblank interrupt or
810 * timeout. Generally speaking intel_wait_for_vblank() is only
811 * called during modeset at which time the GPU should be idle and
812 * should *not* be performing page flips and thus not waiting on
813 * vblanks...
814 * Currently, the result of us stealing a vblank from the irq
815 * handler is that a single frame will be skipped during swapbuffers.
816 */
817 I915_WRITE(pipestat_reg,
818 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
819
820 /* Wait for vblank interrupt bit to set */
821 if (wait_for(I915_READ(pipestat_reg) &
822 PIPE_VBLANK_INTERRUPT_STATUS,
823 50))
824 DRM_DEBUG_KMS("vblank wait timed out\n");
825 }
826
827 /*
828 * intel_wait_for_pipe_off - wait for pipe to turn off
829 * @dev: drm device
830 * @pipe: pipe to wait for
831 *
832 * After disabling a pipe, we can't wait for vblank in the usual way,
833 * spinning on the vblank interrupt status bit, since we won't actually
834 * see an interrupt when the pipe is disabled.
835 *
836 * On Gen4 and above:
837 * wait for the pipe register state bit to turn off
838 *
839 * Otherwise:
840 * wait for the display line value to settle (it usually
841 * ends up stopping at the start of the next frame).
842 *
843 */
844 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
845 {
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
848 pipe);
849
850 if (INTEL_INFO(dev)->gen >= 4) {
851 int reg = PIPECONF(cpu_transcoder);
852
853 /* Wait for the Pipe State to go off */
854 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
855 100))
856 WARN(1, "pipe_off wait timed out\n");
857 } else {
858 u32 last_line, line_mask;
859 int reg = PIPEDSL(pipe);
860 unsigned long timeout = jiffies + msecs_to_jiffies(100);
861
862 if (IS_GEN2(dev))
863 line_mask = DSL_LINEMASK_GEN2;
864 else
865 line_mask = DSL_LINEMASK_GEN3;
866
867 /* Wait for the display line to settle */
868 do {
869 last_line = I915_READ(reg) & line_mask;
870 mdelay(5);
871 } while (((I915_READ(reg) & line_mask) != last_line) &&
872 time_after(timeout, jiffies));
873 if (time_after(jiffies, timeout))
874 WARN(1, "pipe_off wait timed out\n");
875 }
876 }
877
878 /*
879 * ibx_digital_port_connected - is the specified port connected?
880 * @dev_priv: i915 private structure
881 * @port: the port to test
882 *
883 * Returns true if @port is connected, false otherwise.
884 */
885 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
886 struct intel_digital_port *port)
887 {
888 u32 bit;
889
890 if (HAS_PCH_IBX(dev_priv->dev)) {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG;
900 break;
901 default:
902 return true;
903 }
904 } else {
905 switch(port->port) {
906 case PORT_B:
907 bit = SDE_PORTB_HOTPLUG_CPT;
908 break;
909 case PORT_C:
910 bit = SDE_PORTC_HOTPLUG_CPT;
911 break;
912 case PORT_D:
913 bit = SDE_PORTD_HOTPLUG_CPT;
914 break;
915 default:
916 return true;
917 }
918 }
919
920 return I915_READ(SDEISR) & bit;
921 }
922
923 static const char *state_string(bool enabled)
924 {
925 return enabled ? "on" : "off";
926 }
927
928 /* Only for pre-ILK configs */
929 static void assert_pll(struct drm_i915_private *dev_priv,
930 enum pipe pipe, bool state)
931 {
932 int reg;
933 u32 val;
934 bool cur_state;
935
936 reg = DPLL(pipe);
937 val = I915_READ(reg);
938 cur_state = !!(val & DPLL_VCO_ENABLE);
939 WARN(cur_state != state,
940 "PLL state assertion failure (expected %s, current %s)\n",
941 state_string(state), state_string(cur_state));
942 }
943 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
944 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
945
946 /* For ILK+ */
947 static void assert_pch_pll(struct drm_i915_private *dev_priv,
948 struct intel_pch_pll *pll,
949 struct intel_crtc *crtc,
950 bool state)
951 {
952 u32 val;
953 bool cur_state;
954
955 if (HAS_PCH_LPT(dev_priv->dev)) {
956 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 return;
958 }
959
960 if (WARN (!pll,
961 "asserting PCH PLL %s with no PLL\n", state_string(state)))
962 return;
963
964 val = I915_READ(pll->pll_reg);
965 cur_state = !!(val & DPLL_VCO_ENABLE);
966 WARN(cur_state != state,
967 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
968 pll->pll_reg, state_string(state), state_string(cur_state), val);
969
970 /* Make sure the selected PLL is correctly attached to the transcoder */
971 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
972 u32 pch_dpll;
973
974 pch_dpll = I915_READ(PCH_DPLL_SEL);
975 cur_state = pll->pll_reg == _PCH_DPLL_B;
976 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
977 "PLL[%d] not attached to this transcoder %c: %08x\n",
978 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
979 cur_state = !!(val >> (4*crtc->pipe + 3));
980 WARN(cur_state != state,
981 "PLL[%d] not %s on this transcoder %c: %08x\n",
982 pll->pll_reg == _PCH_DPLL_B,
983 state_string(state),
984 pipe_name(crtc->pipe),
985 val);
986 }
987 }
988 }
989 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
990 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
991
992 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994 {
995 int reg;
996 u32 val;
997 bool cur_state;
998 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
999 pipe);
1000
1001 if (HAS_DDI(dev_priv->dev)) {
1002 /* DDI does not have a specific FDI_TX register */
1003 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1004 val = I915_READ(reg);
1005 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1006 } else {
1007 reg = FDI_TX_CTL(pipe);
1008 val = I915_READ(reg);
1009 cur_state = !!(val & FDI_TX_ENABLE);
1010 }
1011 WARN(cur_state != state,
1012 "FDI TX state assertion failure (expected %s, current %s)\n",
1013 state_string(state), state_string(cur_state));
1014 }
1015 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1016 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1017
1018 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, bool state)
1020 {
1021 int reg;
1022 u32 val;
1023 bool cur_state;
1024
1025 reg = FDI_RX_CTL(pipe);
1026 val = I915_READ(reg);
1027 cur_state = !!(val & FDI_RX_ENABLE);
1028 WARN(cur_state != state,
1029 "FDI RX state assertion failure (expected %s, current %s)\n",
1030 state_string(state), state_string(cur_state));
1031 }
1032 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1033 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1034
1035 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1036 enum pipe pipe)
1037 {
1038 int reg;
1039 u32 val;
1040
1041 /* ILK FDI PLL is always enabled */
1042 if (dev_priv->info->gen == 5)
1043 return;
1044
1045 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1046 if (HAS_DDI(dev_priv->dev))
1047 return;
1048
1049 reg = FDI_TX_CTL(pipe);
1050 val = I915_READ(reg);
1051 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1052 }
1053
1054 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056 {
1057 int reg;
1058 u32 val;
1059
1060 reg = FDI_RX_CTL(pipe);
1061 val = I915_READ(reg);
1062 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1063 }
1064
1065 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1066 enum pipe pipe)
1067 {
1068 int pp_reg, lvds_reg;
1069 u32 val;
1070 enum pipe panel_pipe = PIPE_A;
1071 bool locked = true;
1072
1073 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1074 pp_reg = PCH_PP_CONTROL;
1075 lvds_reg = PCH_LVDS;
1076 } else {
1077 pp_reg = PP_CONTROL;
1078 lvds_reg = LVDS;
1079 }
1080
1081 val = I915_READ(pp_reg);
1082 if (!(val & PANEL_POWER_ON) ||
1083 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1084 locked = false;
1085
1086 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1087 panel_pipe = PIPE_B;
1088
1089 WARN(panel_pipe == pipe && locked,
1090 "panel assertion failure, pipe %c regs locked\n",
1091 pipe_name(pipe));
1092 }
1093
1094 void assert_pipe(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 int reg;
1098 u32 val;
1099 bool cur_state;
1100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1101 pipe);
1102
1103 /* if we need the pipe A quirk it must be always on */
1104 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1105 state = true;
1106
1107 if (!intel_display_power_enabled(dev_priv->dev,
1108 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1109 cur_state = false;
1110 } else {
1111 reg = PIPECONF(cpu_transcoder);
1112 val = I915_READ(reg);
1113 cur_state = !!(val & PIPECONF_ENABLE);
1114 }
1115
1116 WARN(cur_state != state,
1117 "pipe %c assertion failure (expected %s, current %s)\n",
1118 pipe_name(pipe), state_string(state), state_string(cur_state));
1119 }
1120
1121 static void assert_plane(struct drm_i915_private *dev_priv,
1122 enum plane plane, bool state)
1123 {
1124 int reg;
1125 u32 val;
1126 bool cur_state;
1127
1128 reg = DSPCNTR(plane);
1129 val = I915_READ(reg);
1130 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1131 WARN(cur_state != state,
1132 "plane %c assertion failure (expected %s, current %s)\n",
1133 plane_name(plane), state_string(state), state_string(cur_state));
1134 }
1135
1136 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1137 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1138
1139 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1140 enum pipe pipe)
1141 {
1142 int reg, i;
1143 u32 val;
1144 int cur_pipe;
1145
1146 /* Planes are fixed to pipes on ILK+ */
1147 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1148 reg = DSPCNTR(pipe);
1149 val = I915_READ(reg);
1150 WARN((val & DISPLAY_PLANE_ENABLE),
1151 "plane %c assertion failure, should be disabled but not\n",
1152 plane_name(pipe));
1153 return;
1154 }
1155
1156 /* Need to check both planes against the pipe */
1157 for (i = 0; i < 2; i++) {
1158 reg = DSPCNTR(i);
1159 val = I915_READ(reg);
1160 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1161 DISPPLANE_SEL_PIPE_SHIFT;
1162 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1163 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1164 plane_name(i), pipe_name(pipe));
1165 }
1166 }
1167
1168 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1169 enum pipe pipe)
1170 {
1171 int reg, i;
1172 u32 val;
1173
1174 if (!IS_VALLEYVIEW(dev_priv->dev))
1175 return;
1176
1177 /* Need to check both planes against the pipe */
1178 for (i = 0; i < dev_priv->num_plane; i++) {
1179 reg = SPCNTR(pipe, i);
1180 val = I915_READ(reg);
1181 WARN((val & SP_ENABLE),
1182 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1183 sprite_name(pipe, i), pipe_name(pipe));
1184 }
1185 }
1186
1187 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1188 {
1189 u32 val;
1190 bool enabled;
1191
1192 if (HAS_PCH_LPT(dev_priv->dev)) {
1193 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1194 return;
1195 }
1196
1197 val = I915_READ(PCH_DREF_CONTROL);
1198 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1199 DREF_SUPERSPREAD_SOURCE_MASK));
1200 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205 {
1206 int reg;
1207 u32 val;
1208 bool enabled;
1209
1210 reg = PCH_TRANSCONF(pipe);
1211 val = I915_READ(reg);
1212 enabled = !!(val & TRANS_ENABLE);
1213 WARN(enabled,
1214 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1215 pipe_name(pipe));
1216 }
1217
1218 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 port_sel, u32 val)
1220 {
1221 if ((val & DP_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1226 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1227 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1228 return false;
1229 } else {
1230 if ((val & DP_PIPE_MASK) != (pipe << 30))
1231 return false;
1232 }
1233 return true;
1234 }
1235
1236 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238 {
1239 if ((val & SDVO_ENABLE) == 0)
1240 return false;
1241
1242 if (HAS_PCH_CPT(dev_priv->dev)) {
1243 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1244 return false;
1245 } else {
1246 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1247 return false;
1248 }
1249 return true;
1250 }
1251
1252 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1254 {
1255 if ((val & LVDS_PORT_EN) == 0)
1256 return false;
1257
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
1259 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1260 return false;
1261 } else {
1262 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1263 return false;
1264 }
1265 return true;
1266 }
1267
1268 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1270 {
1271 if ((val & ADPA_DAC_ENABLE) == 0)
1272 return false;
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1275 return false;
1276 } else {
1277 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1278 return false;
1279 }
1280 return true;
1281 }
1282
1283 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1284 enum pipe pipe, int reg, u32 port_sel)
1285 {
1286 u32 val = I915_READ(reg);
1287 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1288 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1289 reg, pipe_name(pipe));
1290
1291 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1292 && (val & DP_PIPEB_SELECT),
1293 "IBX PCH dp port still using transcoder B\n");
1294 }
1295
1296 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, int reg)
1298 {
1299 u32 val = I915_READ(reg);
1300 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1301 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1302 reg, pipe_name(pipe));
1303
1304 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1305 && (val & SDVO_PIPE_B_SELECT),
1306 "IBX PCH hdmi port still using transcoder B\n");
1307 }
1308
1309 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311 {
1312 int reg;
1313 u32 val;
1314
1315 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1316 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1317 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1318
1319 reg = PCH_ADPA;
1320 val = I915_READ(reg);
1321 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1322 "PCH VGA enabled on transcoder %c, should be disabled\n",
1323 pipe_name(pipe));
1324
1325 reg = PCH_LVDS;
1326 val = I915_READ(reg);
1327 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1328 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1329 pipe_name(pipe));
1330
1331 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1332 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1333 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1334 }
1335
1336 /**
1337 * intel_enable_pll - enable a PLL
1338 * @dev_priv: i915 private structure
1339 * @pipe: pipe PLL to enable
1340 *
1341 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1342 * make sure the PLL reg is writable first though, since the panel write
1343 * protect mechanism may be enabled.
1344 *
1345 * Note! This is for pre-ILK only.
1346 *
1347 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1348 */
1349 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1350 {
1351 int reg;
1352 u32 val;
1353
1354 assert_pipe_disabled(dev_priv, pipe);
1355
1356 /* No really, not for ILK+ */
1357 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1358
1359 /* PLL is protected by panel, make sure we can write it */
1360 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1361 assert_panel_unlocked(dev_priv, pipe);
1362
1363 reg = DPLL(pipe);
1364 val = I915_READ(reg);
1365 val |= DPLL_VCO_ENABLE;
1366
1367 /* We do this three times for luck */
1368 I915_WRITE(reg, val);
1369 POSTING_READ(reg);
1370 udelay(150); /* wait for warmup */
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373 udelay(150); /* wait for warmup */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 }
1378
1379 /**
1380 * intel_disable_pll - disable a PLL
1381 * @dev_priv: i915 private structure
1382 * @pipe: pipe PLL to disable
1383 *
1384 * Disable the PLL for @pipe, making sure the pipe is off first.
1385 *
1386 * Note! This is for pre-ILK only.
1387 */
1388 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1389 {
1390 int reg;
1391 u32 val;
1392
1393 /* Don't disable pipe A or pipe A PLLs if needed */
1394 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1395 return;
1396
1397 /* Make sure the pipe isn't still relying on us */
1398 assert_pipe_disabled(dev_priv, pipe);
1399
1400 reg = DPLL(pipe);
1401 val = I915_READ(reg);
1402 val &= ~DPLL_VCO_ENABLE;
1403 I915_WRITE(reg, val);
1404 POSTING_READ(reg);
1405 }
1406
1407 /* SBI access */
1408 static void
1409 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1410 enum intel_sbi_destination destination)
1411 {
1412 u32 tmp;
1413
1414 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1415
1416 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1417 100)) {
1418 DRM_ERROR("timeout waiting for SBI to become ready\n");
1419 return;
1420 }
1421
1422 I915_WRITE(SBI_ADDR, (reg << 16));
1423 I915_WRITE(SBI_DATA, value);
1424
1425 if (destination == SBI_ICLK)
1426 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1427 else
1428 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1429 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1430
1431 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1432 100)) {
1433 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1434 return;
1435 }
1436 }
1437
1438 static u32
1439 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1440 enum intel_sbi_destination destination)
1441 {
1442 u32 value = 0;
1443 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1444
1445 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1446 100)) {
1447 DRM_ERROR("timeout waiting for SBI to become ready\n");
1448 return 0;
1449 }
1450
1451 I915_WRITE(SBI_ADDR, (reg << 16));
1452
1453 if (destination == SBI_ICLK)
1454 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1455 else
1456 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1457 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1458
1459 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1460 100)) {
1461 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1462 return 0;
1463 }
1464
1465 return I915_READ(SBI_DATA);
1466 }
1467
1468 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1469 {
1470 u32 port_mask;
1471
1472 if (!port)
1473 port_mask = DPLL_PORTB_READY_MASK;
1474 else
1475 port_mask = DPLL_PORTC_READY_MASK;
1476
1477 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1478 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479 'B' + port, I915_READ(DPLL(0)));
1480 }
1481
1482 /**
1483 * ironlake_enable_pch_pll - enable PCH PLL
1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to enable
1486 *
1487 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488 * drives the transcoder clock.
1489 */
1490 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1491 {
1492 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1493 struct intel_pch_pll *pll;
1494 int reg;
1495 u32 val;
1496
1497 /* PCH PLLs only available on ILK, SNB and IVB */
1498 BUG_ON(dev_priv->info->gen < 5);
1499 pll = intel_crtc->pch_pll;
1500 if (pll == NULL)
1501 return;
1502
1503 if (WARN_ON(pll->refcount == 0))
1504 return;
1505
1506 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1507 pll->pll_reg, pll->active, pll->on,
1508 intel_crtc->base.base.id);
1509
1510 /* PCH refclock must be enabled first */
1511 assert_pch_refclk_enabled(dev_priv);
1512
1513 if (pll->active++ && pll->on) {
1514 assert_pch_pll_enabled(dev_priv, pll, NULL);
1515 return;
1516 }
1517
1518 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1519
1520 reg = pll->pll_reg;
1521 val = I915_READ(reg);
1522 val |= DPLL_VCO_ENABLE;
1523 I915_WRITE(reg, val);
1524 POSTING_READ(reg);
1525 udelay(200);
1526
1527 pll->on = true;
1528 }
1529
1530 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1531 {
1532 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1533 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1534 int reg;
1535 u32 val;
1536
1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
1539 if (pll == NULL)
1540 return;
1541
1542 if (WARN_ON(pll->refcount == 0))
1543 return;
1544
1545 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1546 pll->pll_reg, pll->active, pll->on,
1547 intel_crtc->base.base.id);
1548
1549 if (WARN_ON(pll->active == 0)) {
1550 assert_pch_pll_disabled(dev_priv, pll, NULL);
1551 return;
1552 }
1553
1554 if (--pll->active) {
1555 assert_pch_pll_enabled(dev_priv, pll, NULL);
1556 return;
1557 }
1558
1559 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1560
1561 /* Make sure transcoder isn't still depending on us */
1562 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1563
1564 reg = pll->pll_reg;
1565 val = I915_READ(reg);
1566 val &= ~DPLL_VCO_ENABLE;
1567 I915_WRITE(reg, val);
1568 POSTING_READ(reg);
1569 udelay(200);
1570
1571 pll->on = false;
1572 }
1573
1574 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1575 enum pipe pipe)
1576 {
1577 struct drm_device *dev = dev_priv->dev;
1578 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1579 uint32_t reg, val, pipeconf_val;
1580
1581 /* PCH only available on ILK+ */
1582 BUG_ON(dev_priv->info->gen < 5);
1583
1584 /* Make sure PCH DPLL is enabled */
1585 assert_pch_pll_enabled(dev_priv,
1586 to_intel_crtc(crtc)->pch_pll,
1587 to_intel_crtc(crtc));
1588
1589 /* FDI must be feeding us bits for PCH ports */
1590 assert_fdi_tx_enabled(dev_priv, pipe);
1591 assert_fdi_rx_enabled(dev_priv, pipe);
1592
1593 if (HAS_PCH_CPT(dev)) {
1594 /* Workaround: Set the timing override bit before enabling the
1595 * pch transcoder. */
1596 reg = TRANS_CHICKEN2(pipe);
1597 val = I915_READ(reg);
1598 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1599 I915_WRITE(reg, val);
1600 }
1601
1602 reg = PCH_TRANSCONF(pipe);
1603 val = I915_READ(reg);
1604 pipeconf_val = I915_READ(PIPECONF(pipe));
1605
1606 if (HAS_PCH_IBX(dev_priv->dev)) {
1607 /*
1608 * make the BPC in transcoder be consistent with
1609 * that in pipeconf reg.
1610 */
1611 val &= ~PIPECONF_BPC_MASK;
1612 val |= pipeconf_val & PIPECONF_BPC_MASK;
1613 }
1614
1615 val &= ~TRANS_INTERLACE_MASK;
1616 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1617 if (HAS_PCH_IBX(dev_priv->dev) &&
1618 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1619 val |= TRANS_LEGACY_INTERLACED_ILK;
1620 else
1621 val |= TRANS_INTERLACED;
1622 else
1623 val |= TRANS_PROGRESSIVE;
1624
1625 I915_WRITE(reg, val | TRANS_ENABLE);
1626 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1627 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1628 }
1629
1630 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1631 enum transcoder cpu_transcoder)
1632 {
1633 u32 val, pipeconf_val;
1634
1635 /* PCH only available on ILK+ */
1636 BUG_ON(dev_priv->info->gen < 5);
1637
1638 /* FDI must be feeding us bits for PCH ports */
1639 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1640 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1641
1642 /* Workaround: set timing override bit. */
1643 val = I915_READ(_TRANSA_CHICKEN2);
1644 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1645 I915_WRITE(_TRANSA_CHICKEN2, val);
1646
1647 val = TRANS_ENABLE;
1648 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1649
1650 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1651 PIPECONF_INTERLACED_ILK)
1652 val |= TRANS_INTERLACED;
1653 else
1654 val |= TRANS_PROGRESSIVE;
1655
1656 I915_WRITE(LPT_TRANSCONF, val);
1657 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1658 DRM_ERROR("Failed to enable PCH transcoder\n");
1659 }
1660
1661 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663 {
1664 struct drm_device *dev = dev_priv->dev;
1665 uint32_t reg, val;
1666
1667 /* FDI relies on the transcoder */
1668 assert_fdi_tx_disabled(dev_priv, pipe);
1669 assert_fdi_rx_disabled(dev_priv, pipe);
1670
1671 /* Ports must be off as well */
1672 assert_pch_ports_disabled(dev_priv, pipe);
1673
1674 reg = PCH_TRANSCONF(pipe);
1675 val = I915_READ(reg);
1676 val &= ~TRANS_ENABLE;
1677 I915_WRITE(reg, val);
1678 /* wait for PCH transcoder off, transcoder state */
1679 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1680 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1681
1682 if (!HAS_PCH_IBX(dev)) {
1683 /* Workaround: Clear the timing override chicken bit again. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1688 }
1689 }
1690
1691 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1692 {
1693 u32 val;
1694
1695 val = I915_READ(LPT_TRANSCONF);
1696 val &= ~TRANS_ENABLE;
1697 I915_WRITE(LPT_TRANSCONF, val);
1698 /* wait for PCH transcoder off, transcoder state */
1699 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1700 DRM_ERROR("Failed to disable PCH transcoder\n");
1701
1702 /* Workaround: clear timing override bit. */
1703 val = I915_READ(_TRANSA_CHICKEN2);
1704 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1705 I915_WRITE(_TRANSA_CHICKEN2, val);
1706 }
1707
1708 /**
1709 * intel_enable_pipe - enable a pipe, asserting requirements
1710 * @dev_priv: i915 private structure
1711 * @pipe: pipe to enable
1712 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1713 *
1714 * Enable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1716 *
1717 * @pipe should be %PIPE_A or %PIPE_B.
1718 *
1719 * Will wait until the pipe is actually running (i.e. first vblank) before
1720 * returning.
1721 */
1722 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1723 bool pch_port)
1724 {
1725 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1726 pipe);
1727 enum pipe pch_transcoder;
1728 int reg;
1729 u32 val;
1730
1731 assert_planes_disabled(dev_priv, pipe);
1732 assert_sprites_disabled(dev_priv, pipe);
1733
1734 if (HAS_PCH_LPT(dev_priv->dev))
1735 pch_transcoder = TRANSCODER_A;
1736 else
1737 pch_transcoder = pipe;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1750 assert_fdi_tx_pll_enabled(dev_priv,
1751 (enum pipe) cpu_transcoder);
1752 }
1753 /* FIXME: assert CPU port conditions for SNB+ */
1754 }
1755
1756 reg = PIPECONF(cpu_transcoder);
1757 val = I915_READ(reg);
1758 if (val & PIPECONF_ENABLE)
1759 return;
1760
1761 I915_WRITE(reg, val | PIPECONF_ENABLE);
1762 intel_wait_for_vblank(dev_priv->dev, pipe);
1763 }
1764
1765 /**
1766 * intel_disable_pipe - disable a pipe, asserting requirements
1767 * @dev_priv: i915 private structure
1768 * @pipe: pipe to disable
1769 *
1770 * Disable @pipe, making sure that various hardware specific requirements
1771 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 *
1773 * @pipe should be %PIPE_A or %PIPE_B.
1774 *
1775 * Will wait until the pipe has shut down before returning.
1776 */
1777 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1778 enum pipe pipe)
1779 {
1780 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1781 pipe);
1782 int reg;
1783 u32 val;
1784
1785 /*
1786 * Make sure planes won't keep trying to pump pixels to us,
1787 * or we might hang the display.
1788 */
1789 assert_planes_disabled(dev_priv, pipe);
1790 assert_sprites_disabled(dev_priv, pipe);
1791
1792 /* Don't disable pipe A or pipe A PLLs if needed */
1793 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1794 return;
1795
1796 reg = PIPECONF(cpu_transcoder);
1797 val = I915_READ(reg);
1798 if ((val & PIPECONF_ENABLE) == 0)
1799 return;
1800
1801 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1802 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1803 }
1804
1805 /*
1806 * Plane regs are double buffered, going from enabled->disabled needs a
1807 * trigger in order to latch. The display address reg provides this.
1808 */
1809 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane)
1811 {
1812 if (dev_priv->info->gen >= 4)
1813 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1814 else
1815 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1816 }
1817
1818 /**
1819 * intel_enable_plane - enable a display plane on a given pipe
1820 * @dev_priv: i915 private structure
1821 * @plane: plane to enable
1822 * @pipe: pipe being fed
1823 *
1824 * Enable @plane on @pipe, making sure that @pipe is running first.
1825 */
1826 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1827 enum plane plane, enum pipe pipe)
1828 {
1829 int reg;
1830 u32 val;
1831
1832 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1833 assert_pipe_enabled(dev_priv, pipe);
1834
1835 reg = DSPCNTR(plane);
1836 val = I915_READ(reg);
1837 if (val & DISPLAY_PLANE_ENABLE)
1838 return;
1839
1840 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1841 intel_flush_display_plane(dev_priv, plane);
1842 intel_wait_for_vblank(dev_priv->dev, pipe);
1843 }
1844
1845 /**
1846 * intel_disable_plane - disable a display plane
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to disable
1849 * @pipe: pipe consuming the data
1850 *
1851 * Disable @plane; should be an independent operation.
1852 */
1853 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855 {
1856 int reg;
1857 u32 val;
1858
1859 reg = DSPCNTR(plane);
1860 val = I915_READ(reg);
1861 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1862 return;
1863
1864 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1865 intel_flush_display_plane(dev_priv, plane);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 static bool need_vtd_wa(struct drm_device *dev)
1870 {
1871 #ifdef CONFIG_INTEL_IOMMU
1872 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1873 return true;
1874 #endif
1875 return false;
1876 }
1877
1878 int
1879 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1880 struct drm_i915_gem_object *obj,
1881 struct intel_ring_buffer *pipelined)
1882 {
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 u32 alignment;
1885 int ret;
1886
1887 switch (obj->tiling_mode) {
1888 case I915_TILING_NONE:
1889 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1890 alignment = 128 * 1024;
1891 else if (INTEL_INFO(dev)->gen >= 4)
1892 alignment = 4 * 1024;
1893 else
1894 alignment = 64 * 1024;
1895 break;
1896 case I915_TILING_X:
1897 /* pin() will align the object as required by fence */
1898 alignment = 0;
1899 break;
1900 case I915_TILING_Y:
1901 /* Despite that we check this in framebuffer_init userspace can
1902 * screw us over and change the tiling after the fact. Only
1903 * pinned buffers can't change their tiling. */
1904 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1905 return -EINVAL;
1906 default:
1907 BUG();
1908 }
1909
1910 /* Note that the w/a also requires 64 PTE of padding following the
1911 * bo. We currently fill all unused PTE with the shadow page and so
1912 * we should always have valid PTE following the scanout preventing
1913 * the VT-d warning.
1914 */
1915 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1916 alignment = 256 * 1024;
1917
1918 dev_priv->mm.interruptible = false;
1919 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1920 if (ret)
1921 goto err_interruptible;
1922
1923 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1924 * fence, whereas 965+ only requires a fence if using
1925 * framebuffer compression. For simplicity, we always install
1926 * a fence as the cost is not that onerous.
1927 */
1928 ret = i915_gem_object_get_fence(obj);
1929 if (ret)
1930 goto err_unpin;
1931
1932 i915_gem_object_pin_fence(obj);
1933
1934 dev_priv->mm.interruptible = true;
1935 return 0;
1936
1937 err_unpin:
1938 i915_gem_object_unpin(obj);
1939 err_interruptible:
1940 dev_priv->mm.interruptible = true;
1941 return ret;
1942 }
1943
1944 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1945 {
1946 i915_gem_object_unpin_fence(obj);
1947 i915_gem_object_unpin(obj);
1948 }
1949
1950 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1951 * is assumed to be a power-of-two. */
1952 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1953 unsigned int tiling_mode,
1954 unsigned int cpp,
1955 unsigned int pitch)
1956 {
1957 if (tiling_mode != I915_TILING_NONE) {
1958 unsigned int tile_rows, tiles;
1959
1960 tile_rows = *y / 8;
1961 *y %= 8;
1962
1963 tiles = *x / (512/cpp);
1964 *x %= 512/cpp;
1965
1966 return tile_rows * pitch * 8 + tiles * 4096;
1967 } else {
1968 unsigned int offset;
1969
1970 offset = *y * pitch + *x * cpp;
1971 *y = 0;
1972 *x = (offset & 4095) / cpp;
1973 return offset & -4096;
1974 }
1975 }
1976
1977 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978 int x, int y)
1979 {
1980 struct drm_device *dev = crtc->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 struct intel_framebuffer *intel_fb;
1984 struct drm_i915_gem_object *obj;
1985 int plane = intel_crtc->plane;
1986 unsigned long linear_offset;
1987 u32 dspcntr;
1988 u32 reg;
1989
1990 switch (plane) {
1991 case 0:
1992 case 1:
1993 break;
1994 default:
1995 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1996 return -EINVAL;
1997 }
1998
1999 intel_fb = to_intel_framebuffer(fb);
2000 obj = intel_fb->obj;
2001
2002 reg = DSPCNTR(plane);
2003 dspcntr = I915_READ(reg);
2004 /* Mask out pixel format bits in case we change it */
2005 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2006 switch (fb->pixel_format) {
2007 case DRM_FORMAT_C8:
2008 dspcntr |= DISPPLANE_8BPP;
2009 break;
2010 case DRM_FORMAT_XRGB1555:
2011 case DRM_FORMAT_ARGB1555:
2012 dspcntr |= DISPPLANE_BGRX555;
2013 break;
2014 case DRM_FORMAT_RGB565:
2015 dspcntr |= DISPPLANE_BGRX565;
2016 break;
2017 case DRM_FORMAT_XRGB8888:
2018 case DRM_FORMAT_ARGB8888:
2019 dspcntr |= DISPPLANE_BGRX888;
2020 break;
2021 case DRM_FORMAT_XBGR8888:
2022 case DRM_FORMAT_ABGR8888:
2023 dspcntr |= DISPPLANE_RGBX888;
2024 break;
2025 case DRM_FORMAT_XRGB2101010:
2026 case DRM_FORMAT_ARGB2101010:
2027 dspcntr |= DISPPLANE_BGRX101010;
2028 break;
2029 case DRM_FORMAT_XBGR2101010:
2030 case DRM_FORMAT_ABGR2101010:
2031 dspcntr |= DISPPLANE_RGBX101010;
2032 break;
2033 default:
2034 BUG();
2035 }
2036
2037 if (INTEL_INFO(dev)->gen >= 4) {
2038 if (obj->tiling_mode != I915_TILING_NONE)
2039 dspcntr |= DISPPLANE_TILED;
2040 else
2041 dspcntr &= ~DISPPLANE_TILED;
2042 }
2043
2044 I915_WRITE(reg, dspcntr);
2045
2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2047
2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2052 fb->pitches[0]);
2053 linear_offset -= intel_crtc->dspaddr_offset;
2054 } else {
2055 intel_crtc->dspaddr_offset = linear_offset;
2056 }
2057
2058 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2059 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2060 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2061 if (INTEL_INFO(dev)->gen >= 4) {
2062 I915_MODIFY_DISPBASE(DSPSURF(plane),
2063 obj->gtt_offset + intel_crtc->dspaddr_offset);
2064 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2065 I915_WRITE(DSPLINOFF(plane), linear_offset);
2066 } else
2067 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2068 POSTING_READ(reg);
2069
2070 return 0;
2071 }
2072
2073 static int ironlake_update_plane(struct drm_crtc *crtc,
2074 struct drm_framebuffer *fb, int x, int y)
2075 {
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 struct intel_framebuffer *intel_fb;
2080 struct drm_i915_gem_object *obj;
2081 int plane = intel_crtc->plane;
2082 unsigned long linear_offset;
2083 u32 dspcntr;
2084 u32 reg;
2085
2086 switch (plane) {
2087 case 0:
2088 case 1:
2089 case 2:
2090 break;
2091 default:
2092 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2093 return -EINVAL;
2094 }
2095
2096 intel_fb = to_intel_framebuffer(fb);
2097 obj = intel_fb->obj;
2098
2099 reg = DSPCNTR(plane);
2100 dspcntr = I915_READ(reg);
2101 /* Mask out pixel format bits in case we change it */
2102 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2103 switch (fb->pixel_format) {
2104 case DRM_FORMAT_C8:
2105 dspcntr |= DISPPLANE_8BPP;
2106 break;
2107 case DRM_FORMAT_RGB565:
2108 dspcntr |= DISPPLANE_BGRX565;
2109 break;
2110 case DRM_FORMAT_XRGB8888:
2111 case DRM_FORMAT_ARGB8888:
2112 dspcntr |= DISPPLANE_BGRX888;
2113 break;
2114 case DRM_FORMAT_XBGR8888:
2115 case DRM_FORMAT_ABGR8888:
2116 dspcntr |= DISPPLANE_RGBX888;
2117 break;
2118 case DRM_FORMAT_XRGB2101010:
2119 case DRM_FORMAT_ARGB2101010:
2120 dspcntr |= DISPPLANE_BGRX101010;
2121 break;
2122 case DRM_FORMAT_XBGR2101010:
2123 case DRM_FORMAT_ABGR2101010:
2124 dspcntr |= DISPPLANE_RGBX101010;
2125 break;
2126 default:
2127 BUG();
2128 }
2129
2130 if (obj->tiling_mode != I915_TILING_NONE)
2131 dspcntr |= DISPPLANE_TILED;
2132 else
2133 dspcntr &= ~DISPPLANE_TILED;
2134
2135 /* must disable */
2136 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2137
2138 I915_WRITE(reg, dspcntr);
2139
2140 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2141 intel_crtc->dspaddr_offset =
2142 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2143 fb->bits_per_pixel / 8,
2144 fb->pitches[0]);
2145 linear_offset -= intel_crtc->dspaddr_offset;
2146
2147 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2148 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2149 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2150 I915_MODIFY_DISPBASE(DSPSURF(plane),
2151 obj->gtt_offset + intel_crtc->dspaddr_offset);
2152 if (IS_HASWELL(dev)) {
2153 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2154 } else {
2155 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2156 I915_WRITE(DSPLINOFF(plane), linear_offset);
2157 }
2158 POSTING_READ(reg);
2159
2160 return 0;
2161 }
2162
2163 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2164 static int
2165 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2166 int x, int y, enum mode_set_atomic state)
2167 {
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_i915_private *dev_priv = dev->dev_private;
2170
2171 if (dev_priv->display.disable_fbc)
2172 dev_priv->display.disable_fbc(dev);
2173 intel_increase_pllclock(crtc);
2174
2175 return dev_priv->display.update_plane(crtc, fb, x, y);
2176 }
2177
2178 void intel_display_handle_reset(struct drm_device *dev)
2179 {
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct drm_crtc *crtc;
2182
2183 /*
2184 * Flips in the rings have been nuked by the reset,
2185 * so complete all pending flips so that user space
2186 * will get its events and not get stuck.
2187 *
2188 * Also update the base address of all primary
2189 * planes to the the last fb to make sure we're
2190 * showing the correct fb after a reset.
2191 *
2192 * Need to make two loops over the crtcs so that we
2193 * don't try to grab a crtc mutex before the
2194 * pending_flip_queue really got woken up.
2195 */
2196
2197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 enum plane plane = intel_crtc->plane;
2200
2201 intel_prepare_page_flip(dev, plane);
2202 intel_finish_page_flip_plane(dev, plane);
2203 }
2204
2205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207
2208 mutex_lock(&crtc->mutex);
2209 if (intel_crtc->active)
2210 dev_priv->display.update_plane(crtc, crtc->fb,
2211 crtc->x, crtc->y);
2212 mutex_unlock(&crtc->mutex);
2213 }
2214 }
2215
2216 static int
2217 intel_finish_fb(struct drm_framebuffer *old_fb)
2218 {
2219 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2221 bool was_interruptible = dev_priv->mm.interruptible;
2222 int ret;
2223
2224 /* Big Hammer, we also need to ensure that any pending
2225 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2226 * current scanout is retired before unpinning the old
2227 * framebuffer.
2228 *
2229 * This should only fail upon a hung GPU, in which case we
2230 * can safely continue.
2231 */
2232 dev_priv->mm.interruptible = false;
2233 ret = i915_gem_object_finish_gpu(obj);
2234 dev_priv->mm.interruptible = was_interruptible;
2235
2236 return ret;
2237 }
2238
2239 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2240 {
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_master_private *master_priv;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244
2245 if (!dev->primary->master)
2246 return;
2247
2248 master_priv = dev->primary->master->driver_priv;
2249 if (!master_priv->sarea_priv)
2250 return;
2251
2252 switch (intel_crtc->pipe) {
2253 case 0:
2254 master_priv->sarea_priv->pipeA_x = x;
2255 master_priv->sarea_priv->pipeA_y = y;
2256 break;
2257 case 1:
2258 master_priv->sarea_priv->pipeB_x = x;
2259 master_priv->sarea_priv->pipeB_y = y;
2260 break;
2261 default:
2262 break;
2263 }
2264 }
2265
2266 static int
2267 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2268 struct drm_framebuffer *fb)
2269 {
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2273 struct drm_framebuffer *old_fb;
2274 int ret;
2275
2276 /* no fb bound */
2277 if (!fb) {
2278 DRM_ERROR("No FB bound\n");
2279 return 0;
2280 }
2281
2282 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2283 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2284 plane_name(intel_crtc->plane),
2285 INTEL_INFO(dev)->num_pipes);
2286 return -EINVAL;
2287 }
2288
2289 mutex_lock(&dev->struct_mutex);
2290 ret = intel_pin_and_fence_fb_obj(dev,
2291 to_intel_framebuffer(fb)->obj,
2292 NULL);
2293 if (ret != 0) {
2294 mutex_unlock(&dev->struct_mutex);
2295 DRM_ERROR("pin & fence failed\n");
2296 return ret;
2297 }
2298
2299 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2300 if (ret) {
2301 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2302 mutex_unlock(&dev->struct_mutex);
2303 DRM_ERROR("failed to update base address\n");
2304 return ret;
2305 }
2306
2307 old_fb = crtc->fb;
2308 crtc->fb = fb;
2309 crtc->x = x;
2310 crtc->y = y;
2311
2312 if (old_fb) {
2313 intel_wait_for_vblank(dev, intel_crtc->pipe);
2314 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2315 }
2316
2317 intel_update_fbc(dev);
2318 mutex_unlock(&dev->struct_mutex);
2319
2320 intel_crtc_update_sarea_pos(crtc, x, y);
2321
2322 return 0;
2323 }
2324
2325 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2326 {
2327 struct drm_device *dev = crtc->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2330 int pipe = intel_crtc->pipe;
2331 u32 reg, temp;
2332
2333 /* enable normal train */
2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
2336 if (IS_IVYBRIDGE(dev)) {
2337 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2338 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2339 } else {
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2342 }
2343 I915_WRITE(reg, temp);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 if (HAS_PCH_CPT(dev)) {
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2350 } else {
2351 temp &= ~FDI_LINK_TRAIN_NONE;
2352 temp |= FDI_LINK_TRAIN_NONE;
2353 }
2354 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2355
2356 /* wait one idle pattern time */
2357 POSTING_READ(reg);
2358 udelay(1000);
2359
2360 /* IVB wants error correction enabled */
2361 if (IS_IVYBRIDGE(dev))
2362 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2363 FDI_FE_ERRC_ENABLE);
2364 }
2365
2366 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2367 {
2368 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2369 }
2370
2371 static void ivb_modeset_global_resources(struct drm_device *dev)
2372 {
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *pipe_B_crtc =
2375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2376 struct intel_crtc *pipe_C_crtc =
2377 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2378 uint32_t temp;
2379
2380 /*
2381 * When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. Note that we don't care about enabled pipes without
2383 * an enabled pch encoder.
2384 */
2385 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2386 !pipe_has_enabled_pch(pipe_C_crtc)) {
2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2394 }
2395 }
2396
2397 /* The FDI link training functions for ILK/Ibexpeak. */
2398 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399 {
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 int plane = intel_crtc->plane;
2405 u32 reg, temp, tries;
2406
2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2410
2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
2417 I915_WRITE(reg, temp);
2418 I915_READ(reg);
2419 udelay(150);
2420
2421 /* enable CPU FDI TX and PCH FDI RX */
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2429
2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436 POSTING_READ(reg);
2437 udelay(150);
2438
2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
2443
2444 reg = FDI_RX_IIR(pipe);
2445 for (tries = 0; tries < 5; tries++) {
2446 temp = I915_READ(reg);
2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 break;
2453 }
2454 }
2455 if (tries == 5)
2456 DRM_ERROR("FDI train 1 fail!\n");
2457
2458 /* Train 2 */
2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
2463 I915_WRITE(reg, temp);
2464
2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2470
2471 POSTING_READ(reg);
2472 udelay(150);
2473
2474 reg = FDI_RX_IIR(pipe);
2475 for (tries = 0; tries < 5; tries++) {
2476 temp = I915_READ(reg);
2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2482 break;
2483 }
2484 }
2485 if (tries == 5)
2486 DRM_ERROR("FDI train 2 fail!\n");
2487
2488 DRM_DEBUG_KMS("FDI train done\n");
2489
2490 }
2491
2492 static const int snb_b_fdi_train_param[] = {
2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497 };
2498
2499 /* The FDI link training functions for SNB/Cougarpoint. */
2500 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501 {
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
2506 u32 reg, temp, i, retry;
2507
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
2517 udelay(150);
2518
2519 /* enable CPU FDI TX and PCH FDI RX */
2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2523 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 /* SNB-B */
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2530
2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
2546 udelay(150);
2547
2548 for (i = 0; i < 4; i++) {
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
2556 udelay(500);
2557
2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565 break;
2566 }
2567 udelay(50);
2568 }
2569 if (retry < 5)
2570 break;
2571 }
2572 if (i == 4)
2573 DRM_ERROR("FDI train 1 fail!\n");
2574
2575 /* Train 2 */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 if (IS_GEN6(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 }
2585 I915_WRITE(reg, temp);
2586
2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595 }
2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
2601 for (i = 0; i < 4; i++) {
2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618 break;
2619 }
2620 udelay(50);
2621 }
2622 if (retry < 5)
2623 break;
2624 }
2625 if (i == 4)
2626 DRM_ERROR("FDI train 2 fail!\n");
2627
2628 DRM_DEBUG_KMS("FDI train done.\n");
2629 }
2630
2631 /* Manual link training for Ivy Bridge A0 parts */
2632 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633 {
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2638 u32 reg, temp, i;
2639
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641 for train result */
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(150);
2650
2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2653
2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2674 temp |= FDI_COMPOSITE_SYNC;
2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677 POSTING_READ(reg);
2678 udelay(150);
2679
2680 for (i = 0; i < 4; i++) {
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(500);
2689
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2698 break;
2699 }
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 1 fail!\n");
2703
2704 /* Train 2 */
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2712
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2718
2719 POSTING_READ(reg);
2720 udelay(150);
2721
2722 for (i = 0; i < 4; i++) {
2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(500);
2731
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2739 break;
2740 }
2741 }
2742 if (i == 4)
2743 DRM_ERROR("FDI train 2 fail!\n");
2744
2745 DRM_DEBUG_KMS("FDI train done.\n");
2746 }
2747
2748 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2749 {
2750 struct drm_device *dev = intel_crtc->base.dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 int pipe = intel_crtc->pipe;
2753 u32 reg, temp;
2754
2755
2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2760 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764 POSTING_READ(reg);
2765 udelay(200);
2766
2767 /* Switch from Rawclk to PCDclk */
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771 POSTING_READ(reg);
2772 udelay(200);
2773
2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2779
2780 POSTING_READ(reg);
2781 udelay(100);
2782 }
2783 }
2784
2785 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786 {
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp;
2791
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
2803 udelay(100);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809 /* Wait for the clocks to turn off. */
2810 POSTING_READ(reg);
2811 udelay(100);
2812 }
2813
2814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815 {
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 POSTING_READ(reg);
2827
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834 POSTING_READ(reg);
2835 udelay(100);
2836
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2840 }
2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865 }
2866
2867 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868 {
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2872 unsigned long flags;
2873 bool pending;
2874
2875 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2877 return false;
2878
2879 spin_lock_irqsave(&dev->event_lock, flags);
2880 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881 spin_unlock_irqrestore(&dev->event_lock, flags);
2882
2883 return pending;
2884 }
2885
2886 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2887 {
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890
2891 if (crtc->fb == NULL)
2892 return;
2893
2894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2895
2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2898
2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 mutex_lock(&dev_priv->dpio_lock);
2913
2914 /* It is necessary to ungate the pixclk gate prior to programming
2915 * the divisors, and gate it back when it is done.
2916 */
2917 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2918
2919 /* Disable SSCCTL */
2920 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2921 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2922 SBI_SSCCTL_DISABLE,
2923 SBI_ICLK);
2924
2925 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2926 if (crtc->mode.clock == 20000) {
2927 auxdiv = 1;
2928 divsel = 0x41;
2929 phaseinc = 0x20;
2930 } else {
2931 /* The iCLK virtual clock root frequency is in MHz,
2932 * but the crtc->mode.clock in in KHz. To get the divisors,
2933 * it is necessary to divide one by another, so we
2934 * convert the virtual clock precision to KHz here for higher
2935 * precision.
2936 */
2937 u32 iclk_virtual_root_freq = 172800 * 1000;
2938 u32 iclk_pi_range = 64;
2939 u32 desired_divisor, msb_divisor_value, pi_value;
2940
2941 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2942 msb_divisor_value = desired_divisor / iclk_pi_range;
2943 pi_value = desired_divisor % iclk_pi_range;
2944
2945 auxdiv = 0;
2946 divsel = msb_divisor_value - 2;
2947 phaseinc = pi_value;
2948 }
2949
2950 /* This should not happen with any sane values */
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2952 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2953 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2954 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2955
2956 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2957 crtc->mode.clock,
2958 auxdiv,
2959 divsel,
2960 phasedir,
2961 phaseinc);
2962
2963 /* Program SSCDIVINTPHASE6 */
2964 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2965 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2967 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2968 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2969 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2970 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2971 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2978
2979 /* Enable modulator and associated divider */
2980 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2981 temp &= ~SBI_SSCCTL_DISABLE;
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2983
2984 /* Wait for initialization time */
2985 udelay(24);
2986
2987 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2988
2989 mutex_unlock(&dev_priv->dpio_lock);
2990 }
2991
2992 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2993 enum pipe pch_transcoder)
2994 {
2995 struct drm_device *dev = crtc->base.dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2998
2999 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3000 I915_READ(HTOTAL(cpu_transcoder)));
3001 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3002 I915_READ(HBLANK(cpu_transcoder)));
3003 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3004 I915_READ(HSYNC(cpu_transcoder)));
3005
3006 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3007 I915_READ(VTOTAL(cpu_transcoder)));
3008 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3009 I915_READ(VBLANK(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3011 I915_READ(VSYNC(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3013 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3014 }
3015
3016 /*
3017 * Enable PCH resources required for PCH ports:
3018 * - PCH PLLs
3019 * - FDI training & RX/TX
3020 * - update transcoder timings
3021 * - DP transcoding bits
3022 * - transcoder
3023 */
3024 static void ironlake_pch_enable(struct drm_crtc *crtc)
3025 {
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
3030 u32 reg, temp;
3031
3032 assert_pch_transcoder_disabled(dev_priv, pipe);
3033
3034 /* Write the TU size bits before fdi link training, so that error
3035 * detection works. */
3036 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3038
3039 /* For PCH output, training FDI link */
3040 dev_priv->display.fdi_link_train(crtc);
3041
3042 /* XXX: pch pll's can be enabled any time before we enable the PCH
3043 * transcoder, and we actually should do this to not upset any PCH
3044 * transcoder that already use the clock when we share it.
3045 *
3046 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047 * unconditionally resets the pll - we need that to have the right LVDS
3048 * enable sequence. */
3049 ironlake_enable_pch_pll(intel_crtc);
3050
3051 if (HAS_PCH_CPT(dev)) {
3052 u32 sel;
3053
3054 temp = I915_READ(PCH_DPLL_SEL);
3055 switch (pipe) {
3056 default:
3057 case 0:
3058 temp |= TRANSA_DPLL_ENABLE;
3059 sel = TRANSA_DPLLB_SEL;
3060 break;
3061 case 1:
3062 temp |= TRANSB_DPLL_ENABLE;
3063 sel = TRANSB_DPLLB_SEL;
3064 break;
3065 case 2:
3066 temp |= TRANSC_DPLL_ENABLE;
3067 sel = TRANSC_DPLLB_SEL;
3068 break;
3069 }
3070 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3071 temp |= sel;
3072 else
3073 temp &= ~sel;
3074 I915_WRITE(PCH_DPLL_SEL, temp);
3075 }
3076
3077 /* set transcoder timing, panel must allow it */
3078 assert_panel_unlocked(dev_priv, pipe);
3079 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3080
3081 intel_fdi_normal_train(crtc);
3082
3083 /* For PCH DP, enable TRANS_DP_CTL */
3084 if (HAS_PCH_CPT(dev) &&
3085 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3086 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3087 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3088 reg = TRANS_DP_CTL(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3091 TRANS_DP_SYNC_MASK |
3092 TRANS_DP_BPC_MASK);
3093 temp |= (TRANS_DP_OUTPUT_ENABLE |
3094 TRANS_DP_ENH_FRAMING);
3095 temp |= bpc << 9; /* same format but at 11:9 */
3096
3097 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3098 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3099 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3100 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3101
3102 switch (intel_trans_dp_port_sel(crtc)) {
3103 case PCH_DP_B:
3104 temp |= TRANS_DP_PORT_SEL_B;
3105 break;
3106 case PCH_DP_C:
3107 temp |= TRANS_DP_PORT_SEL_C;
3108 break;
3109 case PCH_DP_D:
3110 temp |= TRANS_DP_PORT_SEL_D;
3111 break;
3112 default:
3113 BUG();
3114 }
3115
3116 I915_WRITE(reg, temp);
3117 }
3118
3119 ironlake_enable_pch_transcoder(dev_priv, pipe);
3120 }
3121
3122 static void lpt_pch_enable(struct drm_crtc *crtc)
3123 {
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3128
3129 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3130
3131 lpt_program_iclkip(crtc);
3132
3133 /* Set transcoder timing. */
3134 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3135
3136 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3137 }
3138
3139 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3140 {
3141 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3142
3143 if (pll == NULL)
3144 return;
3145
3146 if (pll->refcount == 0) {
3147 WARN(1, "bad PCH PLL refcount\n");
3148 return;
3149 }
3150
3151 --pll->refcount;
3152 intel_crtc->pch_pll = NULL;
3153 }
3154
3155 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3156 {
3157 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3158 struct intel_pch_pll *pll;
3159 int i;
3160
3161 pll = intel_crtc->pch_pll;
3162 if (pll) {
3163 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto prepare;
3166 }
3167
3168 if (HAS_PCH_IBX(dev_priv->dev)) {
3169 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3170 i = intel_crtc->pipe;
3171 pll = &dev_priv->pch_plls[i];
3172
3173 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3174 intel_crtc->base.base.id, pll->pll_reg);
3175
3176 goto found;
3177 }
3178
3179 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3180 pll = &dev_priv->pch_plls[i];
3181
3182 /* Only want to check enabled timings first */
3183 if (pll->refcount == 0)
3184 continue;
3185
3186 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3187 fp == I915_READ(pll->fp0_reg)) {
3188 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3189 intel_crtc->base.base.id,
3190 pll->pll_reg, pll->refcount, pll->active);
3191
3192 goto found;
3193 }
3194 }
3195
3196 /* Ok no matching timings, maybe there's a free one? */
3197 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3198 pll = &dev_priv->pch_plls[i];
3199 if (pll->refcount == 0) {
3200 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3201 intel_crtc->base.base.id, pll->pll_reg);
3202 goto found;
3203 }
3204 }
3205
3206 return NULL;
3207
3208 found:
3209 intel_crtc->pch_pll = pll;
3210 pll->refcount++;
3211 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3212 prepare: /* separate function? */
3213 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3214
3215 /* Wait for the clocks to stabilize before rewriting the regs */
3216 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3217 POSTING_READ(pll->pll_reg);
3218 udelay(150);
3219
3220 I915_WRITE(pll->fp0_reg, fp);
3221 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3222 pll->on = false;
3223 return pll;
3224 }
3225
3226 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3227 {
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int dslreg = PIPEDSL(pipe);
3230 u32 temp;
3231
3232 temp = I915_READ(dslreg);
3233 udelay(500);
3234 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3235 if (wait_for(I915_READ(dslreg) != temp, 5))
3236 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3237 }
3238 }
3239
3240 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3241 {
3242 struct drm_device *dev = crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 int pipe = crtc->pipe;
3245
3246 if (crtc->config.pch_pfit.size) {
3247 /* Force use of hard-coded filter coefficients
3248 * as some pre-programmed values are broken,
3249 * e.g. x201.
3250 */
3251 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3253 PF_PIPE_SEL_IVB(pipe));
3254 else
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3256 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3257 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3258 }
3259 }
3260
3261 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3262 {
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3266 struct intel_encoder *encoder;
3267 int pipe = intel_crtc->pipe;
3268 int plane = intel_crtc->plane;
3269 u32 temp;
3270
3271 WARN_ON(!crtc->enabled);
3272
3273 if (intel_crtc->active)
3274 return;
3275
3276 intel_crtc->active = true;
3277
3278 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3279 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3280
3281 intel_update_watermarks(dev);
3282
3283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3284 temp = I915_READ(PCH_LVDS);
3285 if ((temp & LVDS_PORT_EN) == 0)
3286 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3287 }
3288
3289
3290 if (intel_crtc->config.has_pch_encoder) {
3291 /* Note: FDI PLL enabling _must_ be done before we enable the
3292 * cpu pipes, hence this is separate from all the other fdi/pch
3293 * enabling. */
3294 ironlake_fdi_pll_enable(intel_crtc);
3295 } else {
3296 assert_fdi_tx_disabled(dev_priv, pipe);
3297 assert_fdi_rx_disabled(dev_priv, pipe);
3298 }
3299
3300 for_each_encoder_on_crtc(dev, crtc, encoder)
3301 if (encoder->pre_enable)
3302 encoder->pre_enable(encoder);
3303
3304 /* Enable panel fitting for LVDS */
3305 ironlake_pfit_enable(intel_crtc);
3306
3307 /*
3308 * On ILK+ LUT must be loaded before the pipe is running but with
3309 * clocks enabled
3310 */
3311 intel_crtc_load_lut(crtc);
3312
3313 intel_enable_pipe(dev_priv, pipe,
3314 intel_crtc->config.has_pch_encoder);
3315 intel_enable_plane(dev_priv, plane, pipe);
3316
3317 if (intel_crtc->config.has_pch_encoder)
3318 ironlake_pch_enable(crtc);
3319
3320 mutex_lock(&dev->struct_mutex);
3321 intel_update_fbc(dev);
3322 mutex_unlock(&dev->struct_mutex);
3323
3324 intel_crtc_update_cursor(crtc, true);
3325
3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 encoder->enable(encoder);
3328
3329 if (HAS_PCH_CPT(dev))
3330 cpt_verify_modeset(dev, intel_crtc->pipe);
3331
3332 /*
3333 * There seems to be a race in PCH platform hw (at least on some
3334 * outputs) where an enabled pipe still completes any pageflip right
3335 * away (as if the pipe is off) instead of waiting for vblank. As soon
3336 * as the first vblank happend, everything works as expected. Hence just
3337 * wait for one vblank before returning to avoid strange things
3338 * happening.
3339 */
3340 intel_wait_for_vblank(dev, intel_crtc->pipe);
3341 }
3342
3343 static void haswell_crtc_enable(struct drm_crtc *crtc)
3344 {
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 struct intel_encoder *encoder;
3349 int pipe = intel_crtc->pipe;
3350 int plane = intel_crtc->plane;
3351
3352 WARN_ON(!crtc->enabled);
3353
3354 if (intel_crtc->active)
3355 return;
3356
3357 intel_crtc->active = true;
3358
3359 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3360 if (intel_crtc->config.has_pch_encoder)
3361 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3362
3363 intel_update_watermarks(dev);
3364
3365 if (intel_crtc->config.has_pch_encoder)
3366 dev_priv->display.fdi_link_train(crtc);
3367
3368 for_each_encoder_on_crtc(dev, crtc, encoder)
3369 if (encoder->pre_enable)
3370 encoder->pre_enable(encoder);
3371
3372 intel_ddi_enable_pipe_clock(intel_crtc);
3373
3374 /* Enable panel fitting for eDP */
3375 ironlake_pfit_enable(intel_crtc);
3376
3377 /*
3378 * On ILK+ LUT must be loaded before the pipe is running but with
3379 * clocks enabled
3380 */
3381 intel_crtc_load_lut(crtc);
3382
3383 intel_ddi_set_pipe_settings(crtc);
3384 intel_ddi_enable_transcoder_func(crtc);
3385
3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
3388 intel_enable_plane(dev_priv, plane, pipe);
3389
3390 if (intel_crtc->config.has_pch_encoder)
3391 lpt_pch_enable(crtc);
3392
3393 mutex_lock(&dev->struct_mutex);
3394 intel_update_fbc(dev);
3395 mutex_unlock(&dev->struct_mutex);
3396
3397 intel_crtc_update_cursor(crtc, true);
3398
3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 encoder->enable(encoder);
3401
3402 /*
3403 * There seems to be a race in PCH platform hw (at least on some
3404 * outputs) where an enabled pipe still completes any pageflip right
3405 * away (as if the pipe is off) instead of waiting for vblank. As soon
3406 * as the first vblank happend, everything works as expected. Hence just
3407 * wait for one vblank before returning to avoid strange things
3408 * happening.
3409 */
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3411 }
3412
3413 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3414 {
3415 struct drm_device *dev = crtc->base.dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 int pipe = crtc->pipe;
3418
3419 /* To avoid upsetting the power well on haswell only disable the pfit if
3420 * it's in use. The hw state code will make sure we get this right. */
3421 if (crtc->config.pch_pfit.size) {
3422 I915_WRITE(PF_CTL(pipe), 0);
3423 I915_WRITE(PF_WIN_POS(pipe), 0);
3424 I915_WRITE(PF_WIN_SZ(pipe), 0);
3425 }
3426 }
3427
3428 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3429 {
3430 struct drm_device *dev = crtc->dev;
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433 struct intel_encoder *encoder;
3434 int pipe = intel_crtc->pipe;
3435 int plane = intel_crtc->plane;
3436 u32 reg, temp;
3437
3438
3439 if (!intel_crtc->active)
3440 return;
3441
3442 for_each_encoder_on_crtc(dev, crtc, encoder)
3443 encoder->disable(encoder);
3444
3445 intel_crtc_wait_for_pending_flips(crtc);
3446 drm_vblank_off(dev, pipe);
3447 intel_crtc_update_cursor(crtc, false);
3448
3449 intel_disable_plane(dev_priv, plane, pipe);
3450
3451 if (dev_priv->cfb_plane == plane)
3452 intel_disable_fbc(dev);
3453
3454 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3455 intel_disable_pipe(dev_priv, pipe);
3456
3457 ironlake_pfit_disable(intel_crtc);
3458
3459 for_each_encoder_on_crtc(dev, crtc, encoder)
3460 if (encoder->post_disable)
3461 encoder->post_disable(encoder);
3462
3463 ironlake_fdi_disable(crtc);
3464
3465 ironlake_disable_pch_transcoder(dev_priv, pipe);
3466 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3467
3468 if (HAS_PCH_CPT(dev)) {
3469 /* disable TRANS_DP_CTL */
3470 reg = TRANS_DP_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3473 temp |= TRANS_DP_PORT_SEL_NONE;
3474 I915_WRITE(reg, temp);
3475
3476 /* disable DPLL_SEL */
3477 temp = I915_READ(PCH_DPLL_SEL);
3478 switch (pipe) {
3479 case 0:
3480 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3481 break;
3482 case 1:
3483 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3484 break;
3485 case 2:
3486 /* C shares PLL A or B */
3487 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3488 break;
3489 default:
3490 BUG(); /* wtf */
3491 }
3492 I915_WRITE(PCH_DPLL_SEL, temp);
3493 }
3494
3495 /* disable PCH DPLL */
3496 intel_disable_pch_pll(intel_crtc);
3497
3498 ironlake_fdi_pll_disable(intel_crtc);
3499
3500 intel_crtc->active = false;
3501 intel_update_watermarks(dev);
3502
3503 mutex_lock(&dev->struct_mutex);
3504 intel_update_fbc(dev);
3505 mutex_unlock(&dev->struct_mutex);
3506 }
3507
3508 static void haswell_crtc_disable(struct drm_crtc *crtc)
3509 {
3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513 struct intel_encoder *encoder;
3514 int pipe = intel_crtc->pipe;
3515 int plane = intel_crtc->plane;
3516 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3517
3518 if (!intel_crtc->active)
3519 return;
3520
3521 for_each_encoder_on_crtc(dev, crtc, encoder)
3522 encoder->disable(encoder);
3523
3524 intel_crtc_wait_for_pending_flips(crtc);
3525 drm_vblank_off(dev, pipe);
3526 intel_crtc_update_cursor(crtc, false);
3527
3528 /* FBC must be disabled before disabling the plane on HSW. */
3529 if (dev_priv->cfb_plane == plane)
3530 intel_disable_fbc(dev);
3531
3532 intel_disable_plane(dev_priv, plane, pipe);
3533
3534 if (intel_crtc->config.has_pch_encoder)
3535 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3536 intel_disable_pipe(dev_priv, pipe);
3537
3538 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3539
3540 ironlake_pfit_disable(intel_crtc);
3541
3542 intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
3548 if (intel_crtc->config.has_pch_encoder) {
3549 lpt_disable_pch_transcoder(dev_priv);
3550 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3551 intel_ddi_fdi_disable(crtc);
3552 }
3553
3554 intel_crtc->active = false;
3555 intel_update_watermarks(dev);
3556
3557 mutex_lock(&dev->struct_mutex);
3558 intel_update_fbc(dev);
3559 mutex_unlock(&dev->struct_mutex);
3560 }
3561
3562 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 {
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565 intel_put_pch_pll(intel_crtc);
3566 }
3567
3568 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 {
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571
3572 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3573 * start using it. */
3574 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3575
3576 intel_ddi_put_crtc_pll(crtc);
3577 }
3578
3579 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 {
3581 if (!enable && intel_crtc->overlay) {
3582 struct drm_device *dev = intel_crtc->base.dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585 mutex_lock(&dev->struct_mutex);
3586 dev_priv->mm.interruptible = false;
3587 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588 dev_priv->mm.interruptible = true;
3589 mutex_unlock(&dev->struct_mutex);
3590 }
3591
3592 /* Let userspace switch the overlay on again. In most cases userspace
3593 * has to recompute where to put it anyway.
3594 */
3595 }
3596
3597 /**
3598 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599 * cursor plane briefly if not already running after enabling the display
3600 * plane.
3601 * This workaround avoids occasional blank screens when self refresh is
3602 * enabled.
3603 */
3604 static void
3605 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606 {
3607 u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609 if ((cntl & CURSOR_MODE) == 0) {
3610 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614 intel_wait_for_vblank(dev_priv->dev, pipe);
3615 I915_WRITE(CURCNTR(pipe), cntl);
3616 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618 }
3619 }
3620
3621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622 {
3623 struct drm_device *dev = crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc_config *pipe_config = &crtc->config;
3626
3627 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3628 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3629 return;
3630
3631 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3632 assert_pipe_disabled(dev_priv, crtc->pipe);
3633
3634 /*
3635 * Enable automatic panel scaling so that non-native modes
3636 * fill the screen. The panel fitter should only be
3637 * adjusted whilst the pipe is disabled, according to
3638 * register description and PRM.
3639 */
3640 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3641 pipe_config->gmch_pfit.control,
3642 pipe_config->gmch_pfit.pgm_ratios);
3643
3644 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3645 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3646
3647 /* Border color in case we don't scale up to the full screen. Black by
3648 * default, change to something else for debugging. */
3649 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3650 }
3651
3652 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3653 {
3654 struct drm_device *dev = crtc->dev;
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657 struct intel_encoder *encoder;
3658 int pipe = intel_crtc->pipe;
3659 int plane = intel_crtc->plane;
3660
3661 WARN_ON(!crtc->enabled);
3662
3663 if (intel_crtc->active)
3664 return;
3665
3666 intel_crtc->active = true;
3667 intel_update_watermarks(dev);
3668
3669 mutex_lock(&dev_priv->dpio_lock);
3670
3671 for_each_encoder_on_crtc(dev, crtc, encoder)
3672 if (encoder->pre_pll_enable)
3673 encoder->pre_pll_enable(encoder);
3674
3675 intel_enable_pll(dev_priv, pipe);
3676
3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 if (encoder->pre_enable)
3679 encoder->pre_enable(encoder);
3680
3681 /* VLV wants encoder enabling _before_ the pipe is up. */
3682 for_each_encoder_on_crtc(dev, crtc, encoder)
3683 encoder->enable(encoder);
3684
3685 /* Enable panel fitting for eDP */
3686 i9xx_pfit_enable(intel_crtc);
3687
3688 intel_enable_pipe(dev_priv, pipe, false);
3689 intel_enable_plane(dev_priv, plane, pipe);
3690
3691 intel_crtc_load_lut(crtc);
3692 intel_update_fbc(dev);
3693
3694 /* Give the overlay scaler a chance to enable if it's on this pipe */
3695 intel_crtc_dpms_overlay(intel_crtc, true);
3696 intel_crtc_update_cursor(crtc, true);
3697
3698 mutex_unlock(&dev_priv->dpio_lock);
3699 }
3700
3701 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3702 {
3703 struct drm_device *dev = crtc->dev;
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3706 struct intel_encoder *encoder;
3707 int pipe = intel_crtc->pipe;
3708 int plane = intel_crtc->plane;
3709
3710 WARN_ON(!crtc->enabled);
3711
3712 if (intel_crtc->active)
3713 return;
3714
3715 intel_crtc->active = true;
3716 intel_update_watermarks(dev);
3717
3718 intel_enable_pll(dev_priv, pipe);
3719
3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->pre_enable)
3722 encoder->pre_enable(encoder);
3723
3724 /* Enable panel fitting for LVDS */
3725 i9xx_pfit_enable(intel_crtc);
3726
3727 intel_enable_pipe(dev_priv, pipe, false);
3728 intel_enable_plane(dev_priv, plane, pipe);
3729 if (IS_G4X(dev))
3730 g4x_fixup_plane(dev_priv, pipe);
3731
3732 intel_crtc_load_lut(crtc);
3733 intel_update_fbc(dev);
3734
3735 /* Give the overlay scaler a chance to enable if it's on this pipe */
3736 intel_crtc_dpms_overlay(intel_crtc, true);
3737 intel_crtc_update_cursor(crtc, true);
3738
3739 for_each_encoder_on_crtc(dev, crtc, encoder)
3740 encoder->enable(encoder);
3741 }
3742
3743 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3744 {
3745 struct drm_device *dev = crtc->base.dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 enum pipe pipe;
3748 uint32_t pctl = I915_READ(PFIT_CONTROL);
3749
3750 assert_pipe_disabled(dev_priv, crtc->pipe);
3751
3752 if (INTEL_INFO(dev)->gen >= 4)
3753 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3754 else
3755 pipe = PIPE_B;
3756
3757 if (pipe == crtc->pipe) {
3758 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3759 I915_WRITE(PFIT_CONTROL, 0);
3760 }
3761 }
3762
3763 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3764 {
3765 struct drm_device *dev = crtc->dev;
3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3768 struct intel_encoder *encoder;
3769 int pipe = intel_crtc->pipe;
3770 int plane = intel_crtc->plane;
3771
3772 if (!intel_crtc->active)
3773 return;
3774
3775 for_each_encoder_on_crtc(dev, crtc, encoder)
3776 encoder->disable(encoder);
3777
3778 /* Give the overlay scaler a chance to disable if it's on this pipe */
3779 intel_crtc_wait_for_pending_flips(crtc);
3780 drm_vblank_off(dev, pipe);
3781 intel_crtc_dpms_overlay(intel_crtc, false);
3782 intel_crtc_update_cursor(crtc, false);
3783
3784 if (dev_priv->cfb_plane == plane)
3785 intel_disable_fbc(dev);
3786
3787 intel_disable_plane(dev_priv, plane, pipe);
3788 intel_disable_pipe(dev_priv, pipe);
3789
3790 i9xx_pfit_disable(intel_crtc);
3791
3792 for_each_encoder_on_crtc(dev, crtc, encoder)
3793 if (encoder->post_disable)
3794 encoder->post_disable(encoder);
3795
3796 intel_disable_pll(dev_priv, pipe);
3797
3798 intel_crtc->active = false;
3799 intel_update_fbc(dev);
3800 intel_update_watermarks(dev);
3801 }
3802
3803 static void i9xx_crtc_off(struct drm_crtc *crtc)
3804 {
3805 }
3806
3807 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3808 bool enabled)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_master_private *master_priv;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814
3815 if (!dev->primary->master)
3816 return;
3817
3818 master_priv = dev->primary->master->driver_priv;
3819 if (!master_priv->sarea_priv)
3820 return;
3821
3822 switch (pipe) {
3823 case 0:
3824 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3825 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3826 break;
3827 case 1:
3828 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3829 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3830 break;
3831 default:
3832 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3833 break;
3834 }
3835 }
3836
3837 /**
3838 * Sets the power management mode of the pipe and plane.
3839 */
3840 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3841 {
3842 struct drm_device *dev = crtc->dev;
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 struct intel_encoder *intel_encoder;
3845 bool enable = false;
3846
3847 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3848 enable |= intel_encoder->connectors_active;
3849
3850 if (enable)
3851 dev_priv->display.crtc_enable(crtc);
3852 else
3853 dev_priv->display.crtc_disable(crtc);
3854
3855 intel_crtc_update_sarea(crtc, enable);
3856 }
3857
3858 static void intel_crtc_disable(struct drm_crtc *crtc)
3859 {
3860 struct drm_device *dev = crtc->dev;
3861 struct drm_connector *connector;
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3864
3865 /* crtc should still be enabled when we disable it. */
3866 WARN_ON(!crtc->enabled);
3867
3868 dev_priv->display.crtc_disable(crtc);
3869 intel_crtc->eld_vld = false;
3870 intel_crtc_update_sarea(crtc, false);
3871 dev_priv->display.off(crtc);
3872
3873 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3874 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3875
3876 if (crtc->fb) {
3877 mutex_lock(&dev->struct_mutex);
3878 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3879 mutex_unlock(&dev->struct_mutex);
3880 crtc->fb = NULL;
3881 }
3882
3883 /* Update computed state. */
3884 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3885 if (!connector->encoder || !connector->encoder->crtc)
3886 continue;
3887
3888 if (connector->encoder->crtc != crtc)
3889 continue;
3890
3891 connector->dpms = DRM_MODE_DPMS_OFF;
3892 to_intel_encoder(connector->encoder)->connectors_active = false;
3893 }
3894 }
3895
3896 void intel_modeset_disable(struct drm_device *dev)
3897 {
3898 struct drm_crtc *crtc;
3899
3900 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3901 if (crtc->enabled)
3902 intel_crtc_disable(crtc);
3903 }
3904 }
3905
3906 void intel_encoder_destroy(struct drm_encoder *encoder)
3907 {
3908 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3909
3910 drm_encoder_cleanup(encoder);
3911 kfree(intel_encoder);
3912 }
3913
3914 /* Simple dpms helper for encodres with just one connector, no cloning and only
3915 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3916 * state of the entire output pipe. */
3917 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3918 {
3919 if (mode == DRM_MODE_DPMS_ON) {
3920 encoder->connectors_active = true;
3921
3922 intel_crtc_update_dpms(encoder->base.crtc);
3923 } else {
3924 encoder->connectors_active = false;
3925
3926 intel_crtc_update_dpms(encoder->base.crtc);
3927 }
3928 }
3929
3930 /* Cross check the actual hw state with our own modeset state tracking (and it's
3931 * internal consistency). */
3932 static void intel_connector_check_state(struct intel_connector *connector)
3933 {
3934 if (connector->get_hw_state(connector)) {
3935 struct intel_encoder *encoder = connector->encoder;
3936 struct drm_crtc *crtc;
3937 bool encoder_enabled;
3938 enum pipe pipe;
3939
3940 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3941 connector->base.base.id,
3942 drm_get_connector_name(&connector->base));
3943
3944 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3945 "wrong connector dpms state\n");
3946 WARN(connector->base.encoder != &encoder->base,
3947 "active connector not linked to encoder\n");
3948 WARN(!encoder->connectors_active,
3949 "encoder->connectors_active not set\n");
3950
3951 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3952 WARN(!encoder_enabled, "encoder not enabled\n");
3953 if (WARN_ON(!encoder->base.crtc))
3954 return;
3955
3956 crtc = encoder->base.crtc;
3957
3958 WARN(!crtc->enabled, "crtc not enabled\n");
3959 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3960 WARN(pipe != to_intel_crtc(crtc)->pipe,
3961 "encoder active on the wrong pipe\n");
3962 }
3963 }
3964
3965 /* Even simpler default implementation, if there's really no special case to
3966 * consider. */
3967 void intel_connector_dpms(struct drm_connector *connector, int mode)
3968 {
3969 struct intel_encoder *encoder = intel_attached_encoder(connector);
3970
3971 /* All the simple cases only support two dpms states. */
3972 if (mode != DRM_MODE_DPMS_ON)
3973 mode = DRM_MODE_DPMS_OFF;
3974
3975 if (mode == connector->dpms)
3976 return;
3977
3978 connector->dpms = mode;
3979
3980 /* Only need to change hw state when actually enabled */
3981 if (encoder->base.crtc)
3982 intel_encoder_dpms(encoder, mode);
3983 else
3984 WARN_ON(encoder->connectors_active != false);
3985
3986 intel_modeset_check_state(connector->dev);
3987 }
3988
3989 /* Simple connector->get_hw_state implementation for encoders that support only
3990 * one connector and no cloning and hence the encoder state determines the state
3991 * of the connector. */
3992 bool intel_connector_get_hw_state(struct intel_connector *connector)
3993 {
3994 enum pipe pipe = 0;
3995 struct intel_encoder *encoder = connector->encoder;
3996
3997 return encoder->get_hw_state(encoder, &pipe);
3998 }
3999
4000 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4001 struct intel_crtc_config *pipe_config)
4002 {
4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004 struct intel_crtc *pipe_B_crtc =
4005 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4006
4007 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4008 pipe_name(pipe), pipe_config->fdi_lanes);
4009 if (pipe_config->fdi_lanes > 4) {
4010 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4011 pipe_name(pipe), pipe_config->fdi_lanes);
4012 return false;
4013 }
4014
4015 if (IS_HASWELL(dev)) {
4016 if (pipe_config->fdi_lanes > 2) {
4017 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4018 pipe_config->fdi_lanes);
4019 return false;
4020 } else {
4021 return true;
4022 }
4023 }
4024
4025 if (INTEL_INFO(dev)->num_pipes == 2)
4026 return true;
4027
4028 /* Ivybridge 3 pipe is really complicated */
4029 switch (pipe) {
4030 case PIPE_A:
4031 return true;
4032 case PIPE_B:
4033 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4034 pipe_config->fdi_lanes > 2) {
4035 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4036 pipe_name(pipe), pipe_config->fdi_lanes);
4037 return false;
4038 }
4039 return true;
4040 case PIPE_C:
4041 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4042 pipe_B_crtc->config.fdi_lanes <= 2) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4045 pipe_name(pipe), pipe_config->fdi_lanes);
4046 return false;
4047 }
4048 } else {
4049 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4050 return false;
4051 }
4052 return true;
4053 default:
4054 BUG();
4055 }
4056 }
4057
4058 #define RETRY 1
4059 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4060 struct intel_crtc_config *pipe_config)
4061 {
4062 struct drm_device *dev = intel_crtc->base.dev;
4063 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4064 int target_clock, lane, link_bw;
4065 bool setup_ok, needs_recompute = false;
4066
4067 retry:
4068 /* FDI is a binary signal running at ~2.7GHz, encoding
4069 * each output octet as 10 bits. The actual frequency
4070 * is stored as a divider into a 100MHz clock, and the
4071 * mode pixel clock is stored in units of 1KHz.
4072 * Hence the bw of each lane in terms of the mode signal
4073 * is:
4074 */
4075 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4076
4077 if (pipe_config->pixel_target_clock)
4078 target_clock = pipe_config->pixel_target_clock;
4079 else
4080 target_clock = adjusted_mode->clock;
4081
4082 lane = ironlake_get_lanes_required(target_clock, link_bw,
4083 pipe_config->pipe_bpp);
4084
4085 pipe_config->fdi_lanes = lane;
4086
4087 if (pipe_config->pixel_multiplier > 1)
4088 link_bw *= pipe_config->pixel_multiplier;
4089 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4090 link_bw, &pipe_config->fdi_m_n);
4091
4092 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4093 intel_crtc->pipe, pipe_config);
4094 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4095 pipe_config->pipe_bpp -= 2*3;
4096 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4097 pipe_config->pipe_bpp);
4098 needs_recompute = true;
4099 pipe_config->bw_constrained = true;
4100
4101 goto retry;
4102 }
4103
4104 if (needs_recompute)
4105 return RETRY;
4106
4107 return setup_ok ? 0 : -EINVAL;
4108 }
4109
4110 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4111 struct intel_crtc_config *pipe_config)
4112 {
4113 struct drm_device *dev = crtc->dev;
4114 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4115
4116 if (HAS_PCH_SPLIT(dev)) {
4117 /* FDI link clock is fixed at 2.7G */
4118 if (pipe_config->requested_mode.clock * 3
4119 > IRONLAKE_FDI_FREQ * 4)
4120 return -EINVAL;
4121 }
4122
4123 /* All interlaced capable intel hw wants timings in frames. Note though
4124 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4125 * timings, so we need to be careful not to clobber these.*/
4126 if (!pipe_config->timings_set)
4127 drm_mode_set_crtcinfo(adjusted_mode, 0);
4128
4129 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4130 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4131 */
4132 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4133 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4134 return -EINVAL;
4135
4136 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4137 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4138 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4139 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4140 * for lvds. */
4141 pipe_config->pipe_bpp = 8*3;
4142 }
4143
4144 if (pipe_config->has_pch_encoder)
4145 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4146
4147 return 0;
4148 }
4149
4150 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4151 {
4152 return 400000; /* FIXME */
4153 }
4154
4155 static int i945_get_display_clock_speed(struct drm_device *dev)
4156 {
4157 return 400000;
4158 }
4159
4160 static int i915_get_display_clock_speed(struct drm_device *dev)
4161 {
4162 return 333000;
4163 }
4164
4165 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4166 {
4167 return 200000;
4168 }
4169
4170 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4171 {
4172 u16 gcfgc = 0;
4173
4174 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4175
4176 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4177 return 133000;
4178 else {
4179 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4180 case GC_DISPLAY_CLOCK_333_MHZ:
4181 return 333000;
4182 default:
4183 case GC_DISPLAY_CLOCK_190_200_MHZ:
4184 return 190000;
4185 }
4186 }
4187 }
4188
4189 static int i865_get_display_clock_speed(struct drm_device *dev)
4190 {
4191 return 266000;
4192 }
4193
4194 static int i855_get_display_clock_speed(struct drm_device *dev)
4195 {
4196 u16 hpllcc = 0;
4197 /* Assume that the hardware is in the high speed state. This
4198 * should be the default.
4199 */
4200 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4201 case GC_CLOCK_133_200:
4202 case GC_CLOCK_100_200:
4203 return 200000;
4204 case GC_CLOCK_166_250:
4205 return 250000;
4206 case GC_CLOCK_100_133:
4207 return 133000;
4208 }
4209
4210 /* Shouldn't happen */
4211 return 0;
4212 }
4213
4214 static int i830_get_display_clock_speed(struct drm_device *dev)
4215 {
4216 return 133000;
4217 }
4218
4219 static void
4220 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4221 {
4222 while (*num > 0xffffff || *den > 0xffffff) {
4223 *num >>= 1;
4224 *den >>= 1;
4225 }
4226 }
4227
4228 void
4229 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4230 int pixel_clock, int link_clock,
4231 struct intel_link_m_n *m_n)
4232 {
4233 m_n->tu = 64;
4234 m_n->gmch_m = bits_per_pixel * pixel_clock;
4235 m_n->gmch_n = link_clock * nlanes * 8;
4236 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4237 m_n->link_m = pixel_clock;
4238 m_n->link_n = link_clock;
4239 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4240 }
4241
4242 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4243 {
4244 if (i915_panel_use_ssc >= 0)
4245 return i915_panel_use_ssc != 0;
4246 return dev_priv->vbt.lvds_use_ssc
4247 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4248 }
4249
4250 static int vlv_get_refclk(struct drm_crtc *crtc)
4251 {
4252 struct drm_device *dev = crtc->dev;
4253 struct drm_i915_private *dev_priv = dev->dev_private;
4254 int refclk = 27000; /* for DP & HDMI */
4255
4256 return 100000; /* only one validated so far */
4257
4258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4259 refclk = 96000;
4260 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4261 if (intel_panel_use_ssc(dev_priv))
4262 refclk = 100000;
4263 else
4264 refclk = 96000;
4265 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4266 refclk = 100000;
4267 }
4268
4269 return refclk;
4270 }
4271
4272 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4273 {
4274 struct drm_device *dev = crtc->dev;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276 int refclk;
4277
4278 if (IS_VALLEYVIEW(dev)) {
4279 refclk = vlv_get_refclk(crtc);
4280 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4281 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4282 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4283 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4284 refclk / 1000);
4285 } else if (!IS_GEN2(dev)) {
4286 refclk = 96000;
4287 } else {
4288 refclk = 48000;
4289 }
4290
4291 return refclk;
4292 }
4293
4294 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4295 {
4296 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4297 }
4298
4299 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4300 {
4301 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4302 }
4303
4304 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4305 intel_clock_t *reduced_clock)
4306 {
4307 struct drm_device *dev = crtc->base.dev;
4308 struct drm_i915_private *dev_priv = dev->dev_private;
4309 int pipe = crtc->pipe;
4310 u32 fp, fp2 = 0;
4311
4312 if (IS_PINEVIEW(dev)) {
4313 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4314 if (reduced_clock)
4315 fp2 = pnv_dpll_compute_fp(reduced_clock);
4316 } else {
4317 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4318 if (reduced_clock)
4319 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4320 }
4321
4322 I915_WRITE(FP0(pipe), fp);
4323
4324 crtc->lowfreq_avail = false;
4325 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4326 reduced_clock && i915_powersave) {
4327 I915_WRITE(FP1(pipe), fp2);
4328 crtc->lowfreq_avail = true;
4329 } else {
4330 I915_WRITE(FP1(pipe), fp);
4331 }
4332 }
4333
4334 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4335 {
4336 u32 reg_val;
4337
4338 /*
4339 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4340 * and set it to a reasonable value instead.
4341 */
4342 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4343 reg_val &= 0xffffff00;
4344 reg_val |= 0x00000030;
4345 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4346
4347 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4348 reg_val &= 0x8cffffff;
4349 reg_val = 0x8c000000;
4350 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4351
4352 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4353 reg_val &= 0xffffff00;
4354 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4355
4356 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4357 reg_val &= 0x00ffffff;
4358 reg_val |= 0xb0000000;
4359 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4360 }
4361
4362 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4363 struct intel_link_m_n *m_n)
4364 {
4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 int pipe = crtc->pipe;
4368
4369 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4370 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4371 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4372 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4373 }
4374
4375 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4376 struct intel_link_m_n *m_n)
4377 {
4378 struct drm_device *dev = crtc->base.dev;
4379 struct drm_i915_private *dev_priv = dev->dev_private;
4380 int pipe = crtc->pipe;
4381 enum transcoder transcoder = crtc->config.cpu_transcoder;
4382
4383 if (INTEL_INFO(dev)->gen >= 5) {
4384 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4385 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4386 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4387 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4388 } else {
4389 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4390 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4391 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4392 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4393 }
4394 }
4395
4396 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4397 {
4398 if (crtc->config.has_pch_encoder)
4399 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4400 else
4401 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4402 }
4403
4404 static void vlv_update_pll(struct intel_crtc *crtc)
4405 {
4406 struct drm_device *dev = crtc->base.dev;
4407 struct drm_i915_private *dev_priv = dev->dev_private;
4408 struct drm_display_mode *adjusted_mode =
4409 &crtc->config.adjusted_mode;
4410 struct intel_encoder *encoder;
4411 int pipe = crtc->pipe;
4412 u32 dpll, mdiv;
4413 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4414 bool is_hdmi;
4415 u32 coreclk, reg_val, dpll_md;
4416
4417 mutex_lock(&dev_priv->dpio_lock);
4418
4419 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4420
4421 bestn = crtc->config.dpll.n;
4422 bestm1 = crtc->config.dpll.m1;
4423 bestm2 = crtc->config.dpll.m2;
4424 bestp1 = crtc->config.dpll.p1;
4425 bestp2 = crtc->config.dpll.p2;
4426
4427 /* See eDP HDMI DPIO driver vbios notes doc */
4428
4429 /* PLL B needs special handling */
4430 if (pipe)
4431 vlv_pllb_recal_opamp(dev_priv);
4432
4433 /* Set up Tx target for periodic Rcomp update */
4434 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4435
4436 /* Disable target IRef on PLL */
4437 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4438 reg_val &= 0x00ffffff;
4439 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4440
4441 /* Disable fast lock */
4442 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4443
4444 /* Set idtafcrecal before PLL is enabled */
4445 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4446 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4447 mdiv |= ((bestn << DPIO_N_SHIFT));
4448 mdiv |= (1 << DPIO_K_SHIFT);
4449
4450 /*
4451 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4452 * but we don't support that).
4453 * Note: don't use the DAC post divider as it seems unstable.
4454 */
4455 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4456 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4457
4458 mdiv |= DPIO_ENABLE_CALIBRATION;
4459 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4460
4461 /* Set HBR and RBR LPF coefficients */
4462 if (adjusted_mode->clock == 162000 ||
4463 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4464 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4465 0x005f0021);
4466 else
4467 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4468 0x00d0000f);
4469
4470 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4471 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4472 /* Use SSC source */
4473 if (!pipe)
4474 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4475 0x0df40000);
4476 else
4477 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4478 0x0df70000);
4479 } else { /* HDMI or VGA */
4480 /* Use bend source */
4481 if (!pipe)
4482 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4483 0x0df70000);
4484 else
4485 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4486 0x0df40000);
4487 }
4488
4489 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4490 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4491 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4492 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4493 coreclk |= 0x01000000;
4494 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4495
4496 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4497
4498 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4499 if (encoder->pre_pll_enable)
4500 encoder->pre_pll_enable(encoder);
4501
4502 /* Enable DPIO clock input */
4503 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4504 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4505 if (pipe)
4506 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4507
4508 dpll |= DPLL_VCO_ENABLE;
4509 I915_WRITE(DPLL(pipe), dpll);
4510 POSTING_READ(DPLL(pipe));
4511 udelay(150);
4512
4513 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4514 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4515
4516 dpll_md = 0;
4517 if (crtc->config.pixel_multiplier > 1) {
4518 dpll_md = (crtc->config.pixel_multiplier - 1)
4519 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4520 }
4521 I915_WRITE(DPLL_MD(pipe), dpll_md);
4522 POSTING_READ(DPLL_MD(pipe));
4523
4524 if (crtc->config.has_dp_encoder)
4525 intel_dp_set_m_n(crtc);
4526
4527 mutex_unlock(&dev_priv->dpio_lock);
4528 }
4529
4530 static void i9xx_update_pll(struct intel_crtc *crtc,
4531 intel_clock_t *reduced_clock,
4532 int num_connectors)
4533 {
4534 struct drm_device *dev = crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 struct intel_encoder *encoder;
4537 int pipe = crtc->pipe;
4538 u32 dpll;
4539 bool is_sdvo;
4540 struct dpll *clock = &crtc->config.dpll;
4541
4542 i9xx_update_pll_dividers(crtc, reduced_clock);
4543
4544 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4545 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4546
4547 dpll = DPLL_VGA_MODE_DIS;
4548
4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4550 dpll |= DPLLB_MODE_LVDS;
4551 else
4552 dpll |= DPLLB_MODE_DAC_SERIAL;
4553
4554 if ((crtc->config.pixel_multiplier > 1) &&
4555 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4556 dpll |= (crtc->config.pixel_multiplier - 1)
4557 << SDVO_MULTIPLIER_SHIFT_HIRES;
4558 }
4559
4560 if (is_sdvo)
4561 dpll |= DPLL_DVO_HIGH_SPEED;
4562
4563 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4564 dpll |= DPLL_DVO_HIGH_SPEED;
4565
4566 /* compute bitmask from p1 value */
4567 if (IS_PINEVIEW(dev))
4568 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4569 else {
4570 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4571 if (IS_G4X(dev) && reduced_clock)
4572 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4573 }
4574 switch (clock->p2) {
4575 case 5:
4576 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4577 break;
4578 case 7:
4579 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4580 break;
4581 case 10:
4582 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4583 break;
4584 case 14:
4585 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4586 break;
4587 }
4588 if (INTEL_INFO(dev)->gen >= 4)
4589 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4590
4591 if (crtc->config.sdvo_tv_clock)
4592 dpll |= PLL_REF_INPUT_TVCLKINBC;
4593 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4594 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4595 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4596 else
4597 dpll |= PLL_REF_INPUT_DREFCLK;
4598
4599 dpll |= DPLL_VCO_ENABLE;
4600 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4601 POSTING_READ(DPLL(pipe));
4602 udelay(150);
4603
4604 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4605 if (encoder->pre_pll_enable)
4606 encoder->pre_pll_enable(encoder);
4607
4608 if (crtc->config.has_dp_encoder)
4609 intel_dp_set_m_n(crtc);
4610
4611 I915_WRITE(DPLL(pipe), dpll);
4612
4613 /* Wait for the clocks to stabilize. */
4614 POSTING_READ(DPLL(pipe));
4615 udelay(150);
4616
4617 if (INTEL_INFO(dev)->gen >= 4) {
4618 u32 dpll_md = 0;
4619 if (crtc->config.pixel_multiplier > 1) {
4620 dpll_md = (crtc->config.pixel_multiplier - 1)
4621 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4622 }
4623 I915_WRITE(DPLL_MD(pipe), dpll_md);
4624 } else {
4625 /* The pixel multiplier can only be updated once the
4626 * DPLL is enabled and the clocks are stable.
4627 *
4628 * So write it again.
4629 */
4630 I915_WRITE(DPLL(pipe), dpll);
4631 }
4632 }
4633
4634 static void i8xx_update_pll(struct intel_crtc *crtc,
4635 struct drm_display_mode *adjusted_mode,
4636 intel_clock_t *reduced_clock,
4637 int num_connectors)
4638 {
4639 struct drm_device *dev = crtc->base.dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 struct intel_encoder *encoder;
4642 int pipe = crtc->pipe;
4643 u32 dpll;
4644 struct dpll *clock = &crtc->config.dpll;
4645
4646 i9xx_update_pll_dividers(crtc, reduced_clock);
4647
4648 dpll = DPLL_VGA_MODE_DIS;
4649
4650 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4651 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4652 } else {
4653 if (clock->p1 == 2)
4654 dpll |= PLL_P1_DIVIDE_BY_TWO;
4655 else
4656 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4657 if (clock->p2 == 4)
4658 dpll |= PLL_P2_DIVIDE_BY_4;
4659 }
4660
4661 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4662 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4663 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4664 else
4665 dpll |= PLL_REF_INPUT_DREFCLK;
4666
4667 dpll |= DPLL_VCO_ENABLE;
4668 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4669 POSTING_READ(DPLL(pipe));
4670 udelay(150);
4671
4672 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4673 if (encoder->pre_pll_enable)
4674 encoder->pre_pll_enable(encoder);
4675
4676 I915_WRITE(DPLL(pipe), dpll);
4677
4678 /* Wait for the clocks to stabilize. */
4679 POSTING_READ(DPLL(pipe));
4680 udelay(150);
4681
4682 /* The pixel multiplier can only be updated once the
4683 * DPLL is enabled and the clocks are stable.
4684 *
4685 * So write it again.
4686 */
4687 I915_WRITE(DPLL(pipe), dpll);
4688 }
4689
4690 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4691 struct drm_display_mode *mode,
4692 struct drm_display_mode *adjusted_mode)
4693 {
4694 struct drm_device *dev = intel_crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum pipe pipe = intel_crtc->pipe;
4697 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4698 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4699
4700 /* We need to be careful not to changed the adjusted mode, for otherwise
4701 * the hw state checker will get angry at the mismatch. */
4702 crtc_vtotal = adjusted_mode->crtc_vtotal;
4703 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4704
4705 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4706 /* the chip adds 2 halflines automatically */
4707 crtc_vtotal -= 1;
4708 crtc_vblank_end -= 1;
4709 vsyncshift = adjusted_mode->crtc_hsync_start
4710 - adjusted_mode->crtc_htotal / 2;
4711 } else {
4712 vsyncshift = 0;
4713 }
4714
4715 if (INTEL_INFO(dev)->gen > 3)
4716 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4717
4718 I915_WRITE(HTOTAL(cpu_transcoder),
4719 (adjusted_mode->crtc_hdisplay - 1) |
4720 ((adjusted_mode->crtc_htotal - 1) << 16));
4721 I915_WRITE(HBLANK(cpu_transcoder),
4722 (adjusted_mode->crtc_hblank_start - 1) |
4723 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4724 I915_WRITE(HSYNC(cpu_transcoder),
4725 (adjusted_mode->crtc_hsync_start - 1) |
4726 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4727
4728 I915_WRITE(VTOTAL(cpu_transcoder),
4729 (adjusted_mode->crtc_vdisplay - 1) |
4730 ((crtc_vtotal - 1) << 16));
4731 I915_WRITE(VBLANK(cpu_transcoder),
4732 (adjusted_mode->crtc_vblank_start - 1) |
4733 ((crtc_vblank_end - 1) << 16));
4734 I915_WRITE(VSYNC(cpu_transcoder),
4735 (adjusted_mode->crtc_vsync_start - 1) |
4736 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4737
4738 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4739 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4740 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4741 * bits. */
4742 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4743 (pipe == PIPE_B || pipe == PIPE_C))
4744 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4745
4746 /* pipesrc controls the size that is scaled from, which should
4747 * always be the user's requested size.
4748 */
4749 I915_WRITE(PIPESRC(pipe),
4750 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4751 }
4752
4753 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4754 struct intel_crtc_config *pipe_config)
4755 {
4756 struct drm_device *dev = crtc->base.dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4759 uint32_t tmp;
4760
4761 tmp = I915_READ(HTOTAL(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4764 tmp = I915_READ(HBLANK(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4767 tmp = I915_READ(HSYNC(cpu_transcoder));
4768 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4769 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4770
4771 tmp = I915_READ(VTOTAL(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4774 tmp = I915_READ(VBLANK(cpu_transcoder));
4775 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4776 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4777 tmp = I915_READ(VSYNC(cpu_transcoder));
4778 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4779 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4780
4781 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4782 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4783 pipe_config->adjusted_mode.crtc_vtotal += 1;
4784 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4785 }
4786
4787 tmp = I915_READ(PIPESRC(crtc->pipe));
4788 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4789 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4790 }
4791
4792 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4793 {
4794 struct drm_device *dev = intel_crtc->base.dev;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 uint32_t pipeconf;
4797
4798 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4799
4800 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4801 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4802 * core speed.
4803 *
4804 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4805 * pipe == 0 check?
4806 */
4807 if (intel_crtc->config.requested_mode.clock >
4808 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4809 pipeconf |= PIPECONF_DOUBLE_WIDE;
4810 else
4811 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4812 }
4813
4814 /* only g4x and later have fancy bpc/dither controls */
4815 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4816 pipeconf &= ~(PIPECONF_BPC_MASK |
4817 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4818
4819 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4820 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4821 pipeconf |= PIPECONF_DITHER_EN |
4822 PIPECONF_DITHER_TYPE_SP;
4823
4824 switch (intel_crtc->config.pipe_bpp) {
4825 case 18:
4826 pipeconf |= PIPECONF_6BPC;
4827 break;
4828 case 24:
4829 pipeconf |= PIPECONF_8BPC;
4830 break;
4831 case 30:
4832 pipeconf |= PIPECONF_10BPC;
4833 break;
4834 default:
4835 /* Case prevented by intel_choose_pipe_bpp_dither. */
4836 BUG();
4837 }
4838 }
4839
4840 if (HAS_PIPE_CXSR(dev)) {
4841 if (intel_crtc->lowfreq_avail) {
4842 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4843 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4844 } else {
4845 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4846 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4847 }
4848 }
4849
4850 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4851 if (!IS_GEN2(dev) &&
4852 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4853 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4854 else
4855 pipeconf |= PIPECONF_PROGRESSIVE;
4856
4857 if (IS_VALLEYVIEW(dev)) {
4858 if (intel_crtc->config.limited_color_range)
4859 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4860 else
4861 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4862 }
4863
4864 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4865 POSTING_READ(PIPECONF(intel_crtc->pipe));
4866 }
4867
4868 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4869 int x, int y,
4870 struct drm_framebuffer *fb)
4871 {
4872 struct drm_device *dev = crtc->dev;
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875 struct drm_display_mode *adjusted_mode =
4876 &intel_crtc->config.adjusted_mode;
4877 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4878 int pipe = intel_crtc->pipe;
4879 int plane = intel_crtc->plane;
4880 int refclk, num_connectors = 0;
4881 intel_clock_t clock, reduced_clock;
4882 u32 dspcntr;
4883 bool ok, has_reduced_clock = false;
4884 bool is_lvds = false;
4885 struct intel_encoder *encoder;
4886 const intel_limit_t *limit;
4887 int ret;
4888
4889 for_each_encoder_on_crtc(dev, crtc, encoder) {
4890 switch (encoder->type) {
4891 case INTEL_OUTPUT_LVDS:
4892 is_lvds = true;
4893 break;
4894 }
4895
4896 num_connectors++;
4897 }
4898
4899 refclk = i9xx_get_refclk(crtc, num_connectors);
4900
4901 /*
4902 * Returns a set of divisors for the desired target clock with the given
4903 * refclk, or FALSE. The returned values represent the clock equation:
4904 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4905 */
4906 limit = intel_limit(crtc, refclk);
4907 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4908 &clock);
4909 if (!ok) {
4910 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4911 return -EINVAL;
4912 }
4913
4914 /* Ensure that the cursor is valid for the new mode before changing... */
4915 intel_crtc_update_cursor(crtc, true);
4916
4917 if (is_lvds && dev_priv->lvds_downclock_avail) {
4918 /*
4919 * Ensure we match the reduced clock's P to the target clock.
4920 * If the clocks don't match, we can't switch the display clock
4921 * by using the FP0/FP1. In such case we will disable the LVDS
4922 * downclock feature.
4923 */
4924 has_reduced_clock = limit->find_pll(limit, crtc,
4925 dev_priv->lvds_downclock,
4926 refclk,
4927 &clock,
4928 &reduced_clock);
4929 }
4930 /* Compat-code for transition, will disappear. */
4931 if (!intel_crtc->config.clock_set) {
4932 intel_crtc->config.dpll.n = clock.n;
4933 intel_crtc->config.dpll.m1 = clock.m1;
4934 intel_crtc->config.dpll.m2 = clock.m2;
4935 intel_crtc->config.dpll.p1 = clock.p1;
4936 intel_crtc->config.dpll.p2 = clock.p2;
4937 }
4938
4939 if (IS_GEN2(dev))
4940 i8xx_update_pll(intel_crtc, adjusted_mode,
4941 has_reduced_clock ? &reduced_clock : NULL,
4942 num_connectors);
4943 else if (IS_VALLEYVIEW(dev))
4944 vlv_update_pll(intel_crtc);
4945 else
4946 i9xx_update_pll(intel_crtc,
4947 has_reduced_clock ? &reduced_clock : NULL,
4948 num_connectors);
4949
4950 /* Set up the display plane register */
4951 dspcntr = DISPPLANE_GAMMA_ENABLE;
4952
4953 if (!IS_VALLEYVIEW(dev)) {
4954 if (pipe == 0)
4955 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4956 else
4957 dspcntr |= DISPPLANE_SEL_PIPE_B;
4958 }
4959
4960 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4961 drm_mode_debug_printmodeline(mode);
4962
4963 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4964
4965 /* pipesrc and dspsize control the size that is scaled from,
4966 * which should always be the user's requested size.
4967 */
4968 I915_WRITE(DSPSIZE(plane),
4969 ((mode->vdisplay - 1) << 16) |
4970 (mode->hdisplay - 1));
4971 I915_WRITE(DSPPOS(plane), 0);
4972
4973 i9xx_set_pipeconf(intel_crtc);
4974
4975 I915_WRITE(DSPCNTR(plane), dspcntr);
4976 POSTING_READ(DSPCNTR(plane));
4977
4978 ret = intel_pipe_set_base(crtc, x, y, fb);
4979
4980 intel_update_watermarks(dev);
4981
4982 return ret;
4983 }
4984
4985 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4986 struct intel_crtc_config *pipe_config)
4987 {
4988 struct drm_device *dev = crtc->base.dev;
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 uint32_t tmp;
4991
4992 tmp = I915_READ(PFIT_CONTROL);
4993
4994 if (INTEL_INFO(dev)->gen < 4) {
4995 if (crtc->pipe != PIPE_B)
4996 return;
4997
4998 /* gen2/3 store dither state in pfit control, needs to match */
4999 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
5000 } else {
5001 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5002 return;
5003 }
5004
5005 if (!(tmp & PFIT_ENABLE))
5006 return;
5007
5008 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
5009 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5010 if (INTEL_INFO(dev)->gen < 5)
5011 pipe_config->gmch_pfit.lvds_border_bits =
5012 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5013 }
5014
5015 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5016 struct intel_crtc_config *pipe_config)
5017 {
5018 struct drm_device *dev = crtc->base.dev;
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020 uint32_t tmp;
5021
5022 tmp = I915_READ(PIPECONF(crtc->pipe));
5023 if (!(tmp & PIPECONF_ENABLE))
5024 return false;
5025
5026 intel_get_pipe_timings(crtc, pipe_config);
5027
5028 i9xx_get_pfit_config(crtc, pipe_config);
5029
5030 return true;
5031 }
5032
5033 static void ironlake_init_pch_refclk(struct drm_device *dev)
5034 {
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 struct drm_mode_config *mode_config = &dev->mode_config;
5037 struct intel_encoder *encoder;
5038 u32 val, final;
5039 bool has_lvds = false;
5040 bool has_cpu_edp = false;
5041 bool has_panel = false;
5042 bool has_ck505 = false;
5043 bool can_ssc = false;
5044
5045 /* We need to take the global config into account */
5046 list_for_each_entry(encoder, &mode_config->encoder_list,
5047 base.head) {
5048 switch (encoder->type) {
5049 case INTEL_OUTPUT_LVDS:
5050 has_panel = true;
5051 has_lvds = true;
5052 break;
5053 case INTEL_OUTPUT_EDP:
5054 has_panel = true;
5055 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5056 has_cpu_edp = true;
5057 break;
5058 }
5059 }
5060
5061 if (HAS_PCH_IBX(dev)) {
5062 has_ck505 = dev_priv->vbt.display_clock_mode;
5063 can_ssc = has_ck505;
5064 } else {
5065 has_ck505 = false;
5066 can_ssc = true;
5067 }
5068
5069 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5070 has_panel, has_lvds, has_ck505);
5071
5072 /* Ironlake: try to setup display ref clock before DPLL
5073 * enabling. This is only under driver's control after
5074 * PCH B stepping, previous chipset stepping should be
5075 * ignoring this setting.
5076 */
5077 val = I915_READ(PCH_DREF_CONTROL);
5078
5079 /* As we must carefully and slowly disable/enable each source in turn,
5080 * compute the final state we want first and check if we need to
5081 * make any changes at all.
5082 */
5083 final = val;
5084 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5085 if (has_ck505)
5086 final |= DREF_NONSPREAD_CK505_ENABLE;
5087 else
5088 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5089
5090 final &= ~DREF_SSC_SOURCE_MASK;
5091 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5092 final &= ~DREF_SSC1_ENABLE;
5093
5094 if (has_panel) {
5095 final |= DREF_SSC_SOURCE_ENABLE;
5096
5097 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5098 final |= DREF_SSC1_ENABLE;
5099
5100 if (has_cpu_edp) {
5101 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5102 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5103 else
5104 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5105 } else
5106 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5107 } else {
5108 final |= DREF_SSC_SOURCE_DISABLE;
5109 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5110 }
5111
5112 if (final == val)
5113 return;
5114
5115 /* Always enable nonspread source */
5116 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5117
5118 if (has_ck505)
5119 val |= DREF_NONSPREAD_CK505_ENABLE;
5120 else
5121 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5122
5123 if (has_panel) {
5124 val &= ~DREF_SSC_SOURCE_MASK;
5125 val |= DREF_SSC_SOURCE_ENABLE;
5126
5127 /* SSC must be turned on before enabling the CPU output */
5128 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5129 DRM_DEBUG_KMS("Using SSC on panel\n");
5130 val |= DREF_SSC1_ENABLE;
5131 } else
5132 val &= ~DREF_SSC1_ENABLE;
5133
5134 /* Get SSC going before enabling the outputs */
5135 I915_WRITE(PCH_DREF_CONTROL, val);
5136 POSTING_READ(PCH_DREF_CONTROL);
5137 udelay(200);
5138
5139 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5140
5141 /* Enable CPU source on CPU attached eDP */
5142 if (has_cpu_edp) {
5143 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5144 DRM_DEBUG_KMS("Using SSC on eDP\n");
5145 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5146 }
5147 else
5148 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5149 } else
5150 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5151
5152 I915_WRITE(PCH_DREF_CONTROL, val);
5153 POSTING_READ(PCH_DREF_CONTROL);
5154 udelay(200);
5155 } else {
5156 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5157
5158 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5159
5160 /* Turn off CPU output */
5161 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5162
5163 I915_WRITE(PCH_DREF_CONTROL, val);
5164 POSTING_READ(PCH_DREF_CONTROL);
5165 udelay(200);
5166
5167 /* Turn off the SSC source */
5168 val &= ~DREF_SSC_SOURCE_MASK;
5169 val |= DREF_SSC_SOURCE_DISABLE;
5170
5171 /* Turn off SSC1 */
5172 val &= ~DREF_SSC1_ENABLE;
5173
5174 I915_WRITE(PCH_DREF_CONTROL, val);
5175 POSTING_READ(PCH_DREF_CONTROL);
5176 udelay(200);
5177 }
5178
5179 BUG_ON(val != final);
5180 }
5181
5182 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5183 static void lpt_init_pch_refclk(struct drm_device *dev)
5184 {
5185 struct drm_i915_private *dev_priv = dev->dev_private;
5186 struct drm_mode_config *mode_config = &dev->mode_config;
5187 struct intel_encoder *encoder;
5188 bool has_vga = false;
5189 bool is_sdv = false;
5190 u32 tmp;
5191
5192 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5193 switch (encoder->type) {
5194 case INTEL_OUTPUT_ANALOG:
5195 has_vga = true;
5196 break;
5197 }
5198 }
5199
5200 if (!has_vga)
5201 return;
5202
5203 mutex_lock(&dev_priv->dpio_lock);
5204
5205 /* XXX: Rip out SDV support once Haswell ships for real. */
5206 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5207 is_sdv = true;
5208
5209 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5210 tmp &= ~SBI_SSCCTL_DISABLE;
5211 tmp |= SBI_SSCCTL_PATHALT;
5212 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5213
5214 udelay(24);
5215
5216 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5217 tmp &= ~SBI_SSCCTL_PATHALT;
5218 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5219
5220 if (!is_sdv) {
5221 tmp = I915_READ(SOUTH_CHICKEN2);
5222 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5223 I915_WRITE(SOUTH_CHICKEN2, tmp);
5224
5225 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5226 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5227 DRM_ERROR("FDI mPHY reset assert timeout\n");
5228
5229 tmp = I915_READ(SOUTH_CHICKEN2);
5230 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5231 I915_WRITE(SOUTH_CHICKEN2, tmp);
5232
5233 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5234 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5235 100))
5236 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5237 }
5238
5239 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5240 tmp &= ~(0xFF << 24);
5241 tmp |= (0x12 << 24);
5242 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5243
5244 if (is_sdv) {
5245 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5246 tmp |= 0x7FFF;
5247 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5248 }
5249
5250 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5251 tmp |= (1 << 11);
5252 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5255 tmp |= (1 << 11);
5256 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5257
5258 if (is_sdv) {
5259 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5260 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5261 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5264 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5265 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5266
5267 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5268 tmp |= (0x3F << 8);
5269 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5270
5271 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5272 tmp |= (0x3F << 8);
5273 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5274 }
5275
5276 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5277 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5278 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5279
5280 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5281 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5282 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5283
5284 if (!is_sdv) {
5285 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5286 tmp &= ~(7 << 13);
5287 tmp |= (5 << 13);
5288 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5289
5290 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5291 tmp &= ~(7 << 13);
5292 tmp |= (5 << 13);
5293 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5294 }
5295
5296 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5297 tmp &= ~0xFF;
5298 tmp |= 0x1C;
5299 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5300
5301 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5302 tmp &= ~0xFF;
5303 tmp |= 0x1C;
5304 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5305
5306 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5307 tmp &= ~(0xFF << 16);
5308 tmp |= (0x1C << 16);
5309 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5310
5311 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5312 tmp &= ~(0xFF << 16);
5313 tmp |= (0x1C << 16);
5314 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5315
5316 if (!is_sdv) {
5317 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5318 tmp |= (1 << 27);
5319 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5320
5321 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5322 tmp |= (1 << 27);
5323 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5324
5325 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5326 tmp &= ~(0xF << 28);
5327 tmp |= (4 << 28);
5328 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5329
5330 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5331 tmp &= ~(0xF << 28);
5332 tmp |= (4 << 28);
5333 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5334 }
5335
5336 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5337 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5338 tmp |= SBI_DBUFF0_ENABLE;
5339 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5340
5341 mutex_unlock(&dev_priv->dpio_lock);
5342 }
5343
5344 /*
5345 * Initialize reference clocks when the driver loads
5346 */
5347 void intel_init_pch_refclk(struct drm_device *dev)
5348 {
5349 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5350 ironlake_init_pch_refclk(dev);
5351 else if (HAS_PCH_LPT(dev))
5352 lpt_init_pch_refclk(dev);
5353 }
5354
5355 static int ironlake_get_refclk(struct drm_crtc *crtc)
5356 {
5357 struct drm_device *dev = crtc->dev;
5358 struct drm_i915_private *dev_priv = dev->dev_private;
5359 struct intel_encoder *encoder;
5360 int num_connectors = 0;
5361 bool is_lvds = false;
5362
5363 for_each_encoder_on_crtc(dev, crtc, encoder) {
5364 switch (encoder->type) {
5365 case INTEL_OUTPUT_LVDS:
5366 is_lvds = true;
5367 break;
5368 }
5369 num_connectors++;
5370 }
5371
5372 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5373 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5374 dev_priv->vbt.lvds_ssc_freq);
5375 return dev_priv->vbt.lvds_ssc_freq * 1000;
5376 }
5377
5378 return 120000;
5379 }
5380
5381 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5382 {
5383 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5385 int pipe = intel_crtc->pipe;
5386 uint32_t val;
5387
5388 val = I915_READ(PIPECONF(pipe));
5389
5390 val &= ~PIPECONF_BPC_MASK;
5391 switch (intel_crtc->config.pipe_bpp) {
5392 case 18:
5393 val |= PIPECONF_6BPC;
5394 break;
5395 case 24:
5396 val |= PIPECONF_8BPC;
5397 break;
5398 case 30:
5399 val |= PIPECONF_10BPC;
5400 break;
5401 case 36:
5402 val |= PIPECONF_12BPC;
5403 break;
5404 default:
5405 /* Case prevented by intel_choose_pipe_bpp_dither. */
5406 BUG();
5407 }
5408
5409 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5410 if (intel_crtc->config.dither)
5411 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5412
5413 val &= ~PIPECONF_INTERLACE_MASK;
5414 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5415 val |= PIPECONF_INTERLACED_ILK;
5416 else
5417 val |= PIPECONF_PROGRESSIVE;
5418
5419 if (intel_crtc->config.limited_color_range)
5420 val |= PIPECONF_COLOR_RANGE_SELECT;
5421 else
5422 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5423
5424 I915_WRITE(PIPECONF(pipe), val);
5425 POSTING_READ(PIPECONF(pipe));
5426 }
5427
5428 /*
5429 * Set up the pipe CSC unit.
5430 *
5431 * Currently only full range RGB to limited range RGB conversion
5432 * is supported, but eventually this should handle various
5433 * RGB<->YCbCr scenarios as well.
5434 */
5435 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5436 {
5437 struct drm_device *dev = crtc->dev;
5438 struct drm_i915_private *dev_priv = dev->dev_private;
5439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5440 int pipe = intel_crtc->pipe;
5441 uint16_t coeff = 0x7800; /* 1.0 */
5442
5443 /*
5444 * TODO: Check what kind of values actually come out of the pipe
5445 * with these coeff/postoff values and adjust to get the best
5446 * accuracy. Perhaps we even need to take the bpc value into
5447 * consideration.
5448 */
5449
5450 if (intel_crtc->config.limited_color_range)
5451 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5452
5453 /*
5454 * GY/GU and RY/RU should be the other way around according
5455 * to BSpec, but reality doesn't agree. Just set them up in
5456 * a way that results in the correct picture.
5457 */
5458 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5459 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5460
5461 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5462 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5463
5464 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5465 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5466
5467 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5468 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5469 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5470
5471 if (INTEL_INFO(dev)->gen > 6) {
5472 uint16_t postoff = 0;
5473
5474 if (intel_crtc->config.limited_color_range)
5475 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5476
5477 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5478 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5479 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5480
5481 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5482 } else {
5483 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5484
5485 if (intel_crtc->config.limited_color_range)
5486 mode |= CSC_BLACK_SCREEN_OFFSET;
5487
5488 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5489 }
5490 }
5491
5492 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5493 {
5494 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5496 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5497 uint32_t val;
5498
5499 val = I915_READ(PIPECONF(cpu_transcoder));
5500
5501 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5502 if (intel_crtc->config.dither)
5503 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5504
5505 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5506 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5507 val |= PIPECONF_INTERLACED_ILK;
5508 else
5509 val |= PIPECONF_PROGRESSIVE;
5510
5511 I915_WRITE(PIPECONF(cpu_transcoder), val);
5512 POSTING_READ(PIPECONF(cpu_transcoder));
5513 }
5514
5515 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5516 struct drm_display_mode *adjusted_mode,
5517 intel_clock_t *clock,
5518 bool *has_reduced_clock,
5519 intel_clock_t *reduced_clock)
5520 {
5521 struct drm_device *dev = crtc->dev;
5522 struct drm_i915_private *dev_priv = dev->dev_private;
5523 struct intel_encoder *intel_encoder;
5524 int refclk;
5525 const intel_limit_t *limit;
5526 bool ret, is_lvds = false;
5527
5528 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5529 switch (intel_encoder->type) {
5530 case INTEL_OUTPUT_LVDS:
5531 is_lvds = true;
5532 break;
5533 }
5534 }
5535
5536 refclk = ironlake_get_refclk(crtc);
5537
5538 /*
5539 * Returns a set of divisors for the desired target clock with the given
5540 * refclk, or FALSE. The returned values represent the clock equation:
5541 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5542 */
5543 limit = intel_limit(crtc, refclk);
5544 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5545 clock);
5546 if (!ret)
5547 return false;
5548
5549 if (is_lvds && dev_priv->lvds_downclock_avail) {
5550 /*
5551 * Ensure we match the reduced clock's P to the target clock.
5552 * If the clocks don't match, we can't switch the display clock
5553 * by using the FP0/FP1. In such case we will disable the LVDS
5554 * downclock feature.
5555 */
5556 *has_reduced_clock = limit->find_pll(limit, crtc,
5557 dev_priv->lvds_downclock,
5558 refclk,
5559 clock,
5560 reduced_clock);
5561 }
5562
5563 return true;
5564 }
5565
5566 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5567 {
5568 struct drm_i915_private *dev_priv = dev->dev_private;
5569 uint32_t temp;
5570
5571 temp = I915_READ(SOUTH_CHICKEN1);
5572 if (temp & FDI_BC_BIFURCATION_SELECT)
5573 return;
5574
5575 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5576 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5577
5578 temp |= FDI_BC_BIFURCATION_SELECT;
5579 DRM_DEBUG_KMS("enabling fdi C rx\n");
5580 I915_WRITE(SOUTH_CHICKEN1, temp);
5581 POSTING_READ(SOUTH_CHICKEN1);
5582 }
5583
5584 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5585 {
5586 struct drm_device *dev = intel_crtc->base.dev;
5587 struct drm_i915_private *dev_priv = dev->dev_private;
5588
5589 switch (intel_crtc->pipe) {
5590 case PIPE_A:
5591 break;
5592 case PIPE_B:
5593 if (intel_crtc->config.fdi_lanes > 2)
5594 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5595 else
5596 cpt_enable_fdi_bc_bifurcation(dev);
5597
5598 break;
5599 case PIPE_C:
5600 cpt_enable_fdi_bc_bifurcation(dev);
5601
5602 break;
5603 default:
5604 BUG();
5605 }
5606 }
5607
5608 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5609 {
5610 /*
5611 * Account for spread spectrum to avoid
5612 * oversubscribing the link. Max center spread
5613 * is 2.5%; use 5% for safety's sake.
5614 */
5615 u32 bps = target_clock * bpp * 21 / 20;
5616 return bps / (link_bw * 8) + 1;
5617 }
5618
5619 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5620 {
5621 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5622 }
5623
5624 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5625 u32 *fp,
5626 intel_clock_t *reduced_clock, u32 *fp2)
5627 {
5628 struct drm_crtc *crtc = &intel_crtc->base;
5629 struct drm_device *dev = crtc->dev;
5630 struct drm_i915_private *dev_priv = dev->dev_private;
5631 struct intel_encoder *intel_encoder;
5632 uint32_t dpll;
5633 int factor, num_connectors = 0;
5634 bool is_lvds = false, is_sdvo = false;
5635
5636 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5637 switch (intel_encoder->type) {
5638 case INTEL_OUTPUT_LVDS:
5639 is_lvds = true;
5640 break;
5641 case INTEL_OUTPUT_SDVO:
5642 case INTEL_OUTPUT_HDMI:
5643 is_sdvo = true;
5644 break;
5645 }
5646
5647 num_connectors++;
5648 }
5649
5650 /* Enable autotuning of the PLL clock (if permissible) */
5651 factor = 21;
5652 if (is_lvds) {
5653 if ((intel_panel_use_ssc(dev_priv) &&
5654 dev_priv->vbt.lvds_ssc_freq == 100) ||
5655 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5656 factor = 25;
5657 } else if (intel_crtc->config.sdvo_tv_clock)
5658 factor = 20;
5659
5660 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5661 *fp |= FP_CB_TUNE;
5662
5663 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5664 *fp2 |= FP_CB_TUNE;
5665
5666 dpll = 0;
5667
5668 if (is_lvds)
5669 dpll |= DPLLB_MODE_LVDS;
5670 else
5671 dpll |= DPLLB_MODE_DAC_SERIAL;
5672
5673 if (intel_crtc->config.pixel_multiplier > 1) {
5674 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5675 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5676 }
5677
5678 if (is_sdvo)
5679 dpll |= DPLL_DVO_HIGH_SPEED;
5680 if (intel_crtc->config.has_dp_encoder)
5681 dpll |= DPLL_DVO_HIGH_SPEED;
5682
5683 /* compute bitmask from p1 value */
5684 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5685 /* also FPA1 */
5686 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5687
5688 switch (intel_crtc->config.dpll.p2) {
5689 case 5:
5690 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5691 break;
5692 case 7:
5693 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5694 break;
5695 case 10:
5696 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5697 break;
5698 case 14:
5699 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5700 break;
5701 }
5702
5703 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5704 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5705 else
5706 dpll |= PLL_REF_INPUT_DREFCLK;
5707
5708 return dpll;
5709 }
5710
5711 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5712 int x, int y,
5713 struct drm_framebuffer *fb)
5714 {
5715 struct drm_device *dev = crtc->dev;
5716 struct drm_i915_private *dev_priv = dev->dev_private;
5717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5718 struct drm_display_mode *adjusted_mode =
5719 &intel_crtc->config.adjusted_mode;
5720 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5721 int pipe = intel_crtc->pipe;
5722 int plane = intel_crtc->plane;
5723 int num_connectors = 0;
5724 intel_clock_t clock, reduced_clock;
5725 u32 dpll = 0, fp = 0, fp2 = 0;
5726 bool ok, has_reduced_clock = false;
5727 bool is_lvds = false;
5728 struct intel_encoder *encoder;
5729 int ret;
5730
5731 for_each_encoder_on_crtc(dev, crtc, encoder) {
5732 switch (encoder->type) {
5733 case INTEL_OUTPUT_LVDS:
5734 is_lvds = true;
5735 break;
5736 }
5737
5738 num_connectors++;
5739 }
5740
5741 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5742 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5743
5744 intel_crtc->config.cpu_transcoder = pipe;
5745
5746 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5747 &has_reduced_clock, &reduced_clock);
5748 if (!ok) {
5749 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5750 return -EINVAL;
5751 }
5752 /* Compat-code for transition, will disappear. */
5753 if (!intel_crtc->config.clock_set) {
5754 intel_crtc->config.dpll.n = clock.n;
5755 intel_crtc->config.dpll.m1 = clock.m1;
5756 intel_crtc->config.dpll.m2 = clock.m2;
5757 intel_crtc->config.dpll.p1 = clock.p1;
5758 intel_crtc->config.dpll.p2 = clock.p2;
5759 }
5760
5761 /* Ensure that the cursor is valid for the new mode before changing... */
5762 intel_crtc_update_cursor(crtc, true);
5763
5764 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5765 drm_mode_debug_printmodeline(mode);
5766
5767 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5768 if (intel_crtc->config.has_pch_encoder) {
5769 struct intel_pch_pll *pll;
5770
5771 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5772 if (has_reduced_clock)
5773 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5774
5775 dpll = ironlake_compute_dpll(intel_crtc,
5776 &fp, &reduced_clock,
5777 has_reduced_clock ? &fp2 : NULL);
5778
5779 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5780 if (pll == NULL) {
5781 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5782 pipe_name(pipe));
5783 return -EINVAL;
5784 }
5785 } else
5786 intel_put_pch_pll(intel_crtc);
5787
5788 if (intel_crtc->config.has_dp_encoder)
5789 intel_dp_set_m_n(intel_crtc);
5790
5791 for_each_encoder_on_crtc(dev, crtc, encoder)
5792 if (encoder->pre_pll_enable)
5793 encoder->pre_pll_enable(encoder);
5794
5795 if (intel_crtc->pch_pll) {
5796 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5797
5798 /* Wait for the clocks to stabilize. */
5799 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5800 udelay(150);
5801
5802 /* The pixel multiplier can only be updated once the
5803 * DPLL is enabled and the clocks are stable.
5804 *
5805 * So write it again.
5806 */
5807 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5808 }
5809
5810 intel_crtc->lowfreq_avail = false;
5811 if (intel_crtc->pch_pll) {
5812 if (is_lvds && has_reduced_clock && i915_powersave) {
5813 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5814 intel_crtc->lowfreq_avail = true;
5815 } else {
5816 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5817 }
5818 }
5819
5820 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5821
5822 if (intel_crtc->config.has_pch_encoder) {
5823 intel_cpu_transcoder_set_m_n(intel_crtc,
5824 &intel_crtc->config.fdi_m_n);
5825 }
5826
5827 if (IS_IVYBRIDGE(dev))
5828 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5829
5830 ironlake_set_pipeconf(crtc);
5831
5832 /* Set up the display plane register */
5833 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5834 POSTING_READ(DSPCNTR(plane));
5835
5836 ret = intel_pipe_set_base(crtc, x, y, fb);
5837
5838 intel_update_watermarks(dev);
5839
5840 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5841
5842 return ret;
5843 }
5844
5845 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5846 struct intel_crtc_config *pipe_config)
5847 {
5848 struct drm_device *dev = crtc->base.dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 enum transcoder transcoder = pipe_config->cpu_transcoder;
5851
5852 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5853 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5854 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5855 & ~TU_SIZE_MASK;
5856 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5857 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5858 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5859 }
5860
5861 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5862 struct intel_crtc_config *pipe_config)
5863 {
5864 struct drm_device *dev = crtc->base.dev;
5865 struct drm_i915_private *dev_priv = dev->dev_private;
5866 uint32_t tmp;
5867
5868 tmp = I915_READ(PF_CTL(crtc->pipe));
5869
5870 if (tmp & PF_ENABLE) {
5871 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5872 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5873 }
5874 }
5875
5876 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5877 struct intel_crtc_config *pipe_config)
5878 {
5879 struct drm_device *dev = crtc->base.dev;
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 uint32_t tmp;
5882
5883 tmp = I915_READ(PIPECONF(crtc->pipe));
5884 if (!(tmp & PIPECONF_ENABLE))
5885 return false;
5886
5887 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5888 pipe_config->has_pch_encoder = true;
5889
5890 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5891 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5892 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5893
5894 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5895 }
5896
5897 intel_get_pipe_timings(crtc, pipe_config);
5898
5899 ironlake_get_pfit_config(crtc, pipe_config);
5900
5901 return true;
5902 }
5903
5904 static void haswell_modeset_global_resources(struct drm_device *dev)
5905 {
5906 bool enable = false;
5907 struct intel_crtc *crtc;
5908 struct intel_encoder *encoder;
5909
5910 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5911 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5912 enable = true;
5913 /* XXX: Should check for edp transcoder here, but thanks to init
5914 * sequence that's not yet available. Just in case desktop eDP
5915 * on PORT D is possible on haswell, too. */
5916 /* Even the eDP panel fitter is outside the always-on well. */
5917 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5918 enable = true;
5919 }
5920
5921 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5922 base.head) {
5923 if (encoder->type != INTEL_OUTPUT_EDP &&
5924 encoder->connectors_active)
5925 enable = true;
5926 }
5927
5928 intel_set_power_well(dev, enable);
5929 }
5930
5931 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5932 int x, int y,
5933 struct drm_framebuffer *fb)
5934 {
5935 struct drm_device *dev = crtc->dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
5937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5938 struct drm_display_mode *adjusted_mode =
5939 &intel_crtc->config.adjusted_mode;
5940 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5941 int pipe = intel_crtc->pipe;
5942 int plane = intel_crtc->plane;
5943 int num_connectors = 0;
5944 bool is_cpu_edp = false;
5945 struct intel_encoder *encoder;
5946 int ret;
5947
5948 for_each_encoder_on_crtc(dev, crtc, encoder) {
5949 switch (encoder->type) {
5950 case INTEL_OUTPUT_EDP:
5951 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5952 is_cpu_edp = true;
5953 break;
5954 }
5955
5956 num_connectors++;
5957 }
5958
5959 if (is_cpu_edp)
5960 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5961 else
5962 intel_crtc->config.cpu_transcoder = pipe;
5963
5964 /* We are not sure yet this won't happen. */
5965 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5966 INTEL_PCH_TYPE(dev));
5967
5968 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5969 num_connectors, pipe_name(pipe));
5970
5971 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5972 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5973
5974 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5975
5976 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5977 return -EINVAL;
5978
5979 /* Ensure that the cursor is valid for the new mode before changing... */
5980 intel_crtc_update_cursor(crtc, true);
5981
5982 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5983 drm_mode_debug_printmodeline(mode);
5984
5985 if (intel_crtc->config.has_dp_encoder)
5986 intel_dp_set_m_n(intel_crtc);
5987
5988 intel_crtc->lowfreq_avail = false;
5989
5990 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5991
5992 if (intel_crtc->config.has_pch_encoder) {
5993 intel_cpu_transcoder_set_m_n(intel_crtc,
5994 &intel_crtc->config.fdi_m_n);
5995 }
5996
5997 haswell_set_pipeconf(crtc);
5998
5999 intel_set_pipe_csc(crtc);
6000
6001 /* Set up the display plane register */
6002 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6003 POSTING_READ(DSPCNTR(plane));
6004
6005 ret = intel_pipe_set_base(crtc, x, y, fb);
6006
6007 intel_update_watermarks(dev);
6008
6009 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6010
6011 return ret;
6012 }
6013
6014 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6015 struct intel_crtc_config *pipe_config)
6016 {
6017 struct drm_device *dev = crtc->base.dev;
6018 struct drm_i915_private *dev_priv = dev->dev_private;
6019 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6020 enum intel_display_power_domain pfit_domain;
6021 uint32_t tmp;
6022
6023 if (!intel_display_power_enabled(dev,
6024 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6025 return false;
6026
6027 tmp = I915_READ(PIPECONF(cpu_transcoder));
6028 if (!(tmp & PIPECONF_ENABLE))
6029 return false;
6030
6031 /*
6032 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6033 * DDI E. So just check whether this pipe is wired to DDI E and whether
6034 * the PCH transcoder is on.
6035 */
6036 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6037 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6038 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6039 pipe_config->has_pch_encoder = true;
6040
6041 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6042 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6043 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6044
6045 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6046 }
6047
6048 intel_get_pipe_timings(crtc, pipe_config);
6049
6050 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6051 if (intel_display_power_enabled(dev, pfit_domain))
6052 ironlake_get_pfit_config(crtc, pipe_config);
6053
6054 return true;
6055 }
6056
6057 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6058 int x, int y,
6059 struct drm_framebuffer *fb)
6060 {
6061 struct drm_device *dev = crtc->dev;
6062 struct drm_i915_private *dev_priv = dev->dev_private;
6063 struct drm_encoder_helper_funcs *encoder_funcs;
6064 struct intel_encoder *encoder;
6065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6066 struct drm_display_mode *adjusted_mode =
6067 &intel_crtc->config.adjusted_mode;
6068 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6069 int pipe = intel_crtc->pipe;
6070 int ret;
6071
6072 drm_vblank_pre_modeset(dev, pipe);
6073
6074 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6075
6076 drm_vblank_post_modeset(dev, pipe);
6077
6078 if (ret != 0)
6079 return ret;
6080
6081 for_each_encoder_on_crtc(dev, crtc, encoder) {
6082 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6083 encoder->base.base.id,
6084 drm_get_encoder_name(&encoder->base),
6085 mode->base.id, mode->name);
6086 if (encoder->mode_set) {
6087 encoder->mode_set(encoder);
6088 } else {
6089 encoder_funcs = encoder->base.helper_private;
6090 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6091 }
6092 }
6093
6094 return 0;
6095 }
6096
6097 static bool intel_eld_uptodate(struct drm_connector *connector,
6098 int reg_eldv, uint32_t bits_eldv,
6099 int reg_elda, uint32_t bits_elda,
6100 int reg_edid)
6101 {
6102 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6103 uint8_t *eld = connector->eld;
6104 uint32_t i;
6105
6106 i = I915_READ(reg_eldv);
6107 i &= bits_eldv;
6108
6109 if (!eld[0])
6110 return !i;
6111
6112 if (!i)
6113 return false;
6114
6115 i = I915_READ(reg_elda);
6116 i &= ~bits_elda;
6117 I915_WRITE(reg_elda, i);
6118
6119 for (i = 0; i < eld[2]; i++)
6120 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6121 return false;
6122
6123 return true;
6124 }
6125
6126 static void g4x_write_eld(struct drm_connector *connector,
6127 struct drm_crtc *crtc)
6128 {
6129 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6130 uint8_t *eld = connector->eld;
6131 uint32_t eldv;
6132 uint32_t len;
6133 uint32_t i;
6134
6135 i = I915_READ(G4X_AUD_VID_DID);
6136
6137 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6138 eldv = G4X_ELDV_DEVCL_DEVBLC;
6139 else
6140 eldv = G4X_ELDV_DEVCTG;
6141
6142 if (intel_eld_uptodate(connector,
6143 G4X_AUD_CNTL_ST, eldv,
6144 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6145 G4X_HDMIW_HDMIEDID))
6146 return;
6147
6148 i = I915_READ(G4X_AUD_CNTL_ST);
6149 i &= ~(eldv | G4X_ELD_ADDR);
6150 len = (i >> 9) & 0x1f; /* ELD buffer size */
6151 I915_WRITE(G4X_AUD_CNTL_ST, i);
6152
6153 if (!eld[0])
6154 return;
6155
6156 len = min_t(uint8_t, eld[2], len);
6157 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6158 for (i = 0; i < len; i++)
6159 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6160
6161 i = I915_READ(G4X_AUD_CNTL_ST);
6162 i |= eldv;
6163 I915_WRITE(G4X_AUD_CNTL_ST, i);
6164 }
6165
6166 static void haswell_write_eld(struct drm_connector *connector,
6167 struct drm_crtc *crtc)
6168 {
6169 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6170 uint8_t *eld = connector->eld;
6171 struct drm_device *dev = crtc->dev;
6172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6173 uint32_t eldv;
6174 uint32_t i;
6175 int len;
6176 int pipe = to_intel_crtc(crtc)->pipe;
6177 int tmp;
6178
6179 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6180 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6181 int aud_config = HSW_AUD_CFG(pipe);
6182 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6183
6184
6185 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6186
6187 /* Audio output enable */
6188 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6189 tmp = I915_READ(aud_cntrl_st2);
6190 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6191 I915_WRITE(aud_cntrl_st2, tmp);
6192
6193 /* Wait for 1 vertical blank */
6194 intel_wait_for_vblank(dev, pipe);
6195
6196 /* Set ELD valid state */
6197 tmp = I915_READ(aud_cntrl_st2);
6198 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6199 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6200 I915_WRITE(aud_cntrl_st2, tmp);
6201 tmp = I915_READ(aud_cntrl_st2);
6202 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6203
6204 /* Enable HDMI mode */
6205 tmp = I915_READ(aud_config);
6206 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6207 /* clear N_programing_enable and N_value_index */
6208 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6209 I915_WRITE(aud_config, tmp);
6210
6211 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6212
6213 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6214 intel_crtc->eld_vld = true;
6215
6216 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6217 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6218 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6219 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6220 } else
6221 I915_WRITE(aud_config, 0);
6222
6223 if (intel_eld_uptodate(connector,
6224 aud_cntrl_st2, eldv,
6225 aud_cntl_st, IBX_ELD_ADDRESS,
6226 hdmiw_hdmiedid))
6227 return;
6228
6229 i = I915_READ(aud_cntrl_st2);
6230 i &= ~eldv;
6231 I915_WRITE(aud_cntrl_st2, i);
6232
6233 if (!eld[0])
6234 return;
6235
6236 i = I915_READ(aud_cntl_st);
6237 i &= ~IBX_ELD_ADDRESS;
6238 I915_WRITE(aud_cntl_st, i);
6239 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6240 DRM_DEBUG_DRIVER("port num:%d\n", i);
6241
6242 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6243 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6244 for (i = 0; i < len; i++)
6245 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6246
6247 i = I915_READ(aud_cntrl_st2);
6248 i |= eldv;
6249 I915_WRITE(aud_cntrl_st2, i);
6250
6251 }
6252
6253 static void ironlake_write_eld(struct drm_connector *connector,
6254 struct drm_crtc *crtc)
6255 {
6256 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6257 uint8_t *eld = connector->eld;
6258 uint32_t eldv;
6259 uint32_t i;
6260 int len;
6261 int hdmiw_hdmiedid;
6262 int aud_config;
6263 int aud_cntl_st;
6264 int aud_cntrl_st2;
6265 int pipe = to_intel_crtc(crtc)->pipe;
6266
6267 if (HAS_PCH_IBX(connector->dev)) {
6268 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6269 aud_config = IBX_AUD_CFG(pipe);
6270 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6271 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6272 } else {
6273 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6274 aud_config = CPT_AUD_CFG(pipe);
6275 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6276 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6277 }
6278
6279 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6280
6281 i = I915_READ(aud_cntl_st);
6282 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6283 if (!i) {
6284 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6285 /* operate blindly on all ports */
6286 eldv = IBX_ELD_VALIDB;
6287 eldv |= IBX_ELD_VALIDB << 4;
6288 eldv |= IBX_ELD_VALIDB << 8;
6289 } else {
6290 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6291 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6292 }
6293
6294 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6295 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6296 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6297 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6298 } else
6299 I915_WRITE(aud_config, 0);
6300
6301 if (intel_eld_uptodate(connector,
6302 aud_cntrl_st2, eldv,
6303 aud_cntl_st, IBX_ELD_ADDRESS,
6304 hdmiw_hdmiedid))
6305 return;
6306
6307 i = I915_READ(aud_cntrl_st2);
6308 i &= ~eldv;
6309 I915_WRITE(aud_cntrl_st2, i);
6310
6311 if (!eld[0])
6312 return;
6313
6314 i = I915_READ(aud_cntl_st);
6315 i &= ~IBX_ELD_ADDRESS;
6316 I915_WRITE(aud_cntl_st, i);
6317
6318 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6319 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6320 for (i = 0; i < len; i++)
6321 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6322
6323 i = I915_READ(aud_cntrl_st2);
6324 i |= eldv;
6325 I915_WRITE(aud_cntrl_st2, i);
6326 }
6327
6328 void intel_write_eld(struct drm_encoder *encoder,
6329 struct drm_display_mode *mode)
6330 {
6331 struct drm_crtc *crtc = encoder->crtc;
6332 struct drm_connector *connector;
6333 struct drm_device *dev = encoder->dev;
6334 struct drm_i915_private *dev_priv = dev->dev_private;
6335
6336 connector = drm_select_eld(encoder, mode);
6337 if (!connector)
6338 return;
6339
6340 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6341 connector->base.id,
6342 drm_get_connector_name(connector),
6343 connector->encoder->base.id,
6344 drm_get_encoder_name(connector->encoder));
6345
6346 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6347
6348 if (dev_priv->display.write_eld)
6349 dev_priv->display.write_eld(connector, crtc);
6350 }
6351
6352 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6353 void intel_crtc_load_lut(struct drm_crtc *crtc)
6354 {
6355 struct drm_device *dev = crtc->dev;
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358 int palreg = PALETTE(intel_crtc->pipe);
6359 int i;
6360
6361 /* The clocks have to be on to load the palette. */
6362 if (!crtc->enabled || !intel_crtc->active)
6363 return;
6364
6365 /* use legacy palette for Ironlake */
6366 if (HAS_PCH_SPLIT(dev))
6367 palreg = LGC_PALETTE(intel_crtc->pipe);
6368
6369 for (i = 0; i < 256; i++) {
6370 I915_WRITE(palreg + 4 * i,
6371 (intel_crtc->lut_r[i] << 16) |
6372 (intel_crtc->lut_g[i] << 8) |
6373 intel_crtc->lut_b[i]);
6374 }
6375 }
6376
6377 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6378 {
6379 struct drm_device *dev = crtc->dev;
6380 struct drm_i915_private *dev_priv = dev->dev_private;
6381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382 bool visible = base != 0;
6383 u32 cntl;
6384
6385 if (intel_crtc->cursor_visible == visible)
6386 return;
6387
6388 cntl = I915_READ(_CURACNTR);
6389 if (visible) {
6390 /* On these chipsets we can only modify the base whilst
6391 * the cursor is disabled.
6392 */
6393 I915_WRITE(_CURABASE, base);
6394
6395 cntl &= ~(CURSOR_FORMAT_MASK);
6396 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6397 cntl |= CURSOR_ENABLE |
6398 CURSOR_GAMMA_ENABLE |
6399 CURSOR_FORMAT_ARGB;
6400 } else
6401 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6402 I915_WRITE(_CURACNTR, cntl);
6403
6404 intel_crtc->cursor_visible = visible;
6405 }
6406
6407 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6408 {
6409 struct drm_device *dev = crtc->dev;
6410 struct drm_i915_private *dev_priv = dev->dev_private;
6411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6412 int pipe = intel_crtc->pipe;
6413 bool visible = base != 0;
6414
6415 if (intel_crtc->cursor_visible != visible) {
6416 uint32_t cntl = I915_READ(CURCNTR(pipe));
6417 if (base) {
6418 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6419 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6420 cntl |= pipe << 28; /* Connect to correct pipe */
6421 } else {
6422 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6423 cntl |= CURSOR_MODE_DISABLE;
6424 }
6425 I915_WRITE(CURCNTR(pipe), cntl);
6426
6427 intel_crtc->cursor_visible = visible;
6428 }
6429 /* and commit changes on next vblank */
6430 I915_WRITE(CURBASE(pipe), base);
6431 }
6432
6433 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6434 {
6435 struct drm_device *dev = crtc->dev;
6436 struct drm_i915_private *dev_priv = dev->dev_private;
6437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6438 int pipe = intel_crtc->pipe;
6439 bool visible = base != 0;
6440
6441 if (intel_crtc->cursor_visible != visible) {
6442 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6443 if (base) {
6444 cntl &= ~CURSOR_MODE;
6445 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6446 } else {
6447 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6448 cntl |= CURSOR_MODE_DISABLE;
6449 }
6450 if (IS_HASWELL(dev))
6451 cntl |= CURSOR_PIPE_CSC_ENABLE;
6452 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6453
6454 intel_crtc->cursor_visible = visible;
6455 }
6456 /* and commit changes on next vblank */
6457 I915_WRITE(CURBASE_IVB(pipe), base);
6458 }
6459
6460 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6461 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6462 bool on)
6463 {
6464 struct drm_device *dev = crtc->dev;
6465 struct drm_i915_private *dev_priv = dev->dev_private;
6466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6467 int pipe = intel_crtc->pipe;
6468 int x = intel_crtc->cursor_x;
6469 int y = intel_crtc->cursor_y;
6470 u32 base, pos;
6471 bool visible;
6472
6473 pos = 0;
6474
6475 if (on && crtc->enabled && crtc->fb) {
6476 base = intel_crtc->cursor_addr;
6477 if (x > (int) crtc->fb->width)
6478 base = 0;
6479
6480 if (y > (int) crtc->fb->height)
6481 base = 0;
6482 } else
6483 base = 0;
6484
6485 if (x < 0) {
6486 if (x + intel_crtc->cursor_width < 0)
6487 base = 0;
6488
6489 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6490 x = -x;
6491 }
6492 pos |= x << CURSOR_X_SHIFT;
6493
6494 if (y < 0) {
6495 if (y + intel_crtc->cursor_height < 0)
6496 base = 0;
6497
6498 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6499 y = -y;
6500 }
6501 pos |= y << CURSOR_Y_SHIFT;
6502
6503 visible = base != 0;
6504 if (!visible && !intel_crtc->cursor_visible)
6505 return;
6506
6507 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6508 I915_WRITE(CURPOS_IVB(pipe), pos);
6509 ivb_update_cursor(crtc, base);
6510 } else {
6511 I915_WRITE(CURPOS(pipe), pos);
6512 if (IS_845G(dev) || IS_I865G(dev))
6513 i845_update_cursor(crtc, base);
6514 else
6515 i9xx_update_cursor(crtc, base);
6516 }
6517 }
6518
6519 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6520 struct drm_file *file,
6521 uint32_t handle,
6522 uint32_t width, uint32_t height)
6523 {
6524 struct drm_device *dev = crtc->dev;
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6527 struct drm_i915_gem_object *obj;
6528 uint32_t addr;
6529 int ret;
6530
6531 /* if we want to turn off the cursor ignore width and height */
6532 if (!handle) {
6533 DRM_DEBUG_KMS("cursor off\n");
6534 addr = 0;
6535 obj = NULL;
6536 mutex_lock(&dev->struct_mutex);
6537 goto finish;
6538 }
6539
6540 /* Currently we only support 64x64 cursors */
6541 if (width != 64 || height != 64) {
6542 DRM_ERROR("we currently only support 64x64 cursors\n");
6543 return -EINVAL;
6544 }
6545
6546 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6547 if (&obj->base == NULL)
6548 return -ENOENT;
6549
6550 if (obj->base.size < width * height * 4) {
6551 DRM_ERROR("buffer is to small\n");
6552 ret = -ENOMEM;
6553 goto fail;
6554 }
6555
6556 /* we only need to pin inside GTT if cursor is non-phy */
6557 mutex_lock(&dev->struct_mutex);
6558 if (!dev_priv->info->cursor_needs_physical) {
6559 unsigned alignment;
6560
6561 if (obj->tiling_mode) {
6562 DRM_ERROR("cursor cannot be tiled\n");
6563 ret = -EINVAL;
6564 goto fail_locked;
6565 }
6566
6567 /* Note that the w/a also requires 2 PTE of padding following
6568 * the bo. We currently fill all unused PTE with the shadow
6569 * page and so we should always have valid PTE following the
6570 * cursor preventing the VT-d warning.
6571 */
6572 alignment = 0;
6573 if (need_vtd_wa(dev))
6574 alignment = 64*1024;
6575
6576 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6577 if (ret) {
6578 DRM_ERROR("failed to move cursor bo into the GTT\n");
6579 goto fail_locked;
6580 }
6581
6582 ret = i915_gem_object_put_fence(obj);
6583 if (ret) {
6584 DRM_ERROR("failed to release fence for cursor");
6585 goto fail_unpin;
6586 }
6587
6588 addr = obj->gtt_offset;
6589 } else {
6590 int align = IS_I830(dev) ? 16 * 1024 : 256;
6591 ret = i915_gem_attach_phys_object(dev, obj,
6592 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6593 align);
6594 if (ret) {
6595 DRM_ERROR("failed to attach phys object\n");
6596 goto fail_locked;
6597 }
6598 addr = obj->phys_obj->handle->busaddr;
6599 }
6600
6601 if (IS_GEN2(dev))
6602 I915_WRITE(CURSIZE, (height << 12) | width);
6603
6604 finish:
6605 if (intel_crtc->cursor_bo) {
6606 if (dev_priv->info->cursor_needs_physical) {
6607 if (intel_crtc->cursor_bo != obj)
6608 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6609 } else
6610 i915_gem_object_unpin(intel_crtc->cursor_bo);
6611 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6612 }
6613
6614 mutex_unlock(&dev->struct_mutex);
6615
6616 intel_crtc->cursor_addr = addr;
6617 intel_crtc->cursor_bo = obj;
6618 intel_crtc->cursor_width = width;
6619 intel_crtc->cursor_height = height;
6620
6621 intel_crtc_update_cursor(crtc, true);
6622
6623 return 0;
6624 fail_unpin:
6625 i915_gem_object_unpin(obj);
6626 fail_locked:
6627 mutex_unlock(&dev->struct_mutex);
6628 fail:
6629 drm_gem_object_unreference_unlocked(&obj->base);
6630 return ret;
6631 }
6632
6633 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6634 {
6635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6636
6637 intel_crtc->cursor_x = x;
6638 intel_crtc->cursor_y = y;
6639
6640 intel_crtc_update_cursor(crtc, true);
6641
6642 return 0;
6643 }
6644
6645 /** Sets the color ramps on behalf of RandR */
6646 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6647 u16 blue, int regno)
6648 {
6649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650
6651 intel_crtc->lut_r[regno] = red >> 8;
6652 intel_crtc->lut_g[regno] = green >> 8;
6653 intel_crtc->lut_b[regno] = blue >> 8;
6654 }
6655
6656 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6657 u16 *blue, int regno)
6658 {
6659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6660
6661 *red = intel_crtc->lut_r[regno] << 8;
6662 *green = intel_crtc->lut_g[regno] << 8;
6663 *blue = intel_crtc->lut_b[regno] << 8;
6664 }
6665
6666 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6667 u16 *blue, uint32_t start, uint32_t size)
6668 {
6669 int end = (start + size > 256) ? 256 : start + size, i;
6670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6671
6672 for (i = start; i < end; i++) {
6673 intel_crtc->lut_r[i] = red[i] >> 8;
6674 intel_crtc->lut_g[i] = green[i] >> 8;
6675 intel_crtc->lut_b[i] = blue[i] >> 8;
6676 }
6677
6678 intel_crtc_load_lut(crtc);
6679 }
6680
6681 /* VESA 640x480x72Hz mode to set on the pipe */
6682 static struct drm_display_mode load_detect_mode = {
6683 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6684 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6685 };
6686
6687 static struct drm_framebuffer *
6688 intel_framebuffer_create(struct drm_device *dev,
6689 struct drm_mode_fb_cmd2 *mode_cmd,
6690 struct drm_i915_gem_object *obj)
6691 {
6692 struct intel_framebuffer *intel_fb;
6693 int ret;
6694
6695 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6696 if (!intel_fb) {
6697 drm_gem_object_unreference_unlocked(&obj->base);
6698 return ERR_PTR(-ENOMEM);
6699 }
6700
6701 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6702 if (ret) {
6703 drm_gem_object_unreference_unlocked(&obj->base);
6704 kfree(intel_fb);
6705 return ERR_PTR(ret);
6706 }
6707
6708 return &intel_fb->base;
6709 }
6710
6711 static u32
6712 intel_framebuffer_pitch_for_width(int width, int bpp)
6713 {
6714 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6715 return ALIGN(pitch, 64);
6716 }
6717
6718 static u32
6719 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6720 {
6721 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6722 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6723 }
6724
6725 static struct drm_framebuffer *
6726 intel_framebuffer_create_for_mode(struct drm_device *dev,
6727 struct drm_display_mode *mode,
6728 int depth, int bpp)
6729 {
6730 struct drm_i915_gem_object *obj;
6731 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6732
6733 obj = i915_gem_alloc_object(dev,
6734 intel_framebuffer_size_for_mode(mode, bpp));
6735 if (obj == NULL)
6736 return ERR_PTR(-ENOMEM);
6737
6738 mode_cmd.width = mode->hdisplay;
6739 mode_cmd.height = mode->vdisplay;
6740 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6741 bpp);
6742 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6743
6744 return intel_framebuffer_create(dev, &mode_cmd, obj);
6745 }
6746
6747 static struct drm_framebuffer *
6748 mode_fits_in_fbdev(struct drm_device *dev,
6749 struct drm_display_mode *mode)
6750 {
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 struct drm_i915_gem_object *obj;
6753 struct drm_framebuffer *fb;
6754
6755 if (dev_priv->fbdev == NULL)
6756 return NULL;
6757
6758 obj = dev_priv->fbdev->ifb.obj;
6759 if (obj == NULL)
6760 return NULL;
6761
6762 fb = &dev_priv->fbdev->ifb.base;
6763 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6764 fb->bits_per_pixel))
6765 return NULL;
6766
6767 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6768 return NULL;
6769
6770 return fb;
6771 }
6772
6773 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6774 struct drm_display_mode *mode,
6775 struct intel_load_detect_pipe *old)
6776 {
6777 struct intel_crtc *intel_crtc;
6778 struct intel_encoder *intel_encoder =
6779 intel_attached_encoder(connector);
6780 struct drm_crtc *possible_crtc;
6781 struct drm_encoder *encoder = &intel_encoder->base;
6782 struct drm_crtc *crtc = NULL;
6783 struct drm_device *dev = encoder->dev;
6784 struct drm_framebuffer *fb;
6785 int i = -1;
6786
6787 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6788 connector->base.id, drm_get_connector_name(connector),
6789 encoder->base.id, drm_get_encoder_name(encoder));
6790
6791 /*
6792 * Algorithm gets a little messy:
6793 *
6794 * - if the connector already has an assigned crtc, use it (but make
6795 * sure it's on first)
6796 *
6797 * - try to find the first unused crtc that can drive this connector,
6798 * and use that if we find one
6799 */
6800
6801 /* See if we already have a CRTC for this connector */
6802 if (encoder->crtc) {
6803 crtc = encoder->crtc;
6804
6805 mutex_lock(&crtc->mutex);
6806
6807 old->dpms_mode = connector->dpms;
6808 old->load_detect_temp = false;
6809
6810 /* Make sure the crtc and connector are running */
6811 if (connector->dpms != DRM_MODE_DPMS_ON)
6812 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6813
6814 return true;
6815 }
6816
6817 /* Find an unused one (if possible) */
6818 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6819 i++;
6820 if (!(encoder->possible_crtcs & (1 << i)))
6821 continue;
6822 if (!possible_crtc->enabled) {
6823 crtc = possible_crtc;
6824 break;
6825 }
6826 }
6827
6828 /*
6829 * If we didn't find an unused CRTC, don't use any.
6830 */
6831 if (!crtc) {
6832 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6833 return false;
6834 }
6835
6836 mutex_lock(&crtc->mutex);
6837 intel_encoder->new_crtc = to_intel_crtc(crtc);
6838 to_intel_connector(connector)->new_encoder = intel_encoder;
6839
6840 intel_crtc = to_intel_crtc(crtc);
6841 old->dpms_mode = connector->dpms;
6842 old->load_detect_temp = true;
6843 old->release_fb = NULL;
6844
6845 if (!mode)
6846 mode = &load_detect_mode;
6847
6848 /* We need a framebuffer large enough to accommodate all accesses
6849 * that the plane may generate whilst we perform load detection.
6850 * We can not rely on the fbcon either being present (we get called
6851 * during its initialisation to detect all boot displays, or it may
6852 * not even exist) or that it is large enough to satisfy the
6853 * requested mode.
6854 */
6855 fb = mode_fits_in_fbdev(dev, mode);
6856 if (fb == NULL) {
6857 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6858 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6859 old->release_fb = fb;
6860 } else
6861 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6862 if (IS_ERR(fb)) {
6863 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6864 mutex_unlock(&crtc->mutex);
6865 return false;
6866 }
6867
6868 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6869 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6870 if (old->release_fb)
6871 old->release_fb->funcs->destroy(old->release_fb);
6872 mutex_unlock(&crtc->mutex);
6873 return false;
6874 }
6875
6876 /* let the connector get through one full cycle before testing */
6877 intel_wait_for_vblank(dev, intel_crtc->pipe);
6878 return true;
6879 }
6880
6881 void intel_release_load_detect_pipe(struct drm_connector *connector,
6882 struct intel_load_detect_pipe *old)
6883 {
6884 struct intel_encoder *intel_encoder =
6885 intel_attached_encoder(connector);
6886 struct drm_encoder *encoder = &intel_encoder->base;
6887 struct drm_crtc *crtc = encoder->crtc;
6888
6889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6890 connector->base.id, drm_get_connector_name(connector),
6891 encoder->base.id, drm_get_encoder_name(encoder));
6892
6893 if (old->load_detect_temp) {
6894 to_intel_connector(connector)->new_encoder = NULL;
6895 intel_encoder->new_crtc = NULL;
6896 intel_set_mode(crtc, NULL, 0, 0, NULL);
6897
6898 if (old->release_fb) {
6899 drm_framebuffer_unregister_private(old->release_fb);
6900 drm_framebuffer_unreference(old->release_fb);
6901 }
6902
6903 mutex_unlock(&crtc->mutex);
6904 return;
6905 }
6906
6907 /* Switch crtc and encoder back off if necessary */
6908 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6909 connector->funcs->dpms(connector, old->dpms_mode);
6910
6911 mutex_unlock(&crtc->mutex);
6912 }
6913
6914 /* Returns the clock of the currently programmed mode of the given pipe. */
6915 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6916 {
6917 struct drm_i915_private *dev_priv = dev->dev_private;
6918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6919 int pipe = intel_crtc->pipe;
6920 u32 dpll = I915_READ(DPLL(pipe));
6921 u32 fp;
6922 intel_clock_t clock;
6923
6924 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6925 fp = I915_READ(FP0(pipe));
6926 else
6927 fp = I915_READ(FP1(pipe));
6928
6929 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6930 if (IS_PINEVIEW(dev)) {
6931 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6932 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6933 } else {
6934 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6935 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6936 }
6937
6938 if (!IS_GEN2(dev)) {
6939 if (IS_PINEVIEW(dev))
6940 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6941 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6942 else
6943 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6944 DPLL_FPA01_P1_POST_DIV_SHIFT);
6945
6946 switch (dpll & DPLL_MODE_MASK) {
6947 case DPLLB_MODE_DAC_SERIAL:
6948 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6949 5 : 10;
6950 break;
6951 case DPLLB_MODE_LVDS:
6952 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6953 7 : 14;
6954 break;
6955 default:
6956 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6957 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6958 return 0;
6959 }
6960
6961 /* XXX: Handle the 100Mhz refclk */
6962 intel_clock(dev, 96000, &clock);
6963 } else {
6964 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6965
6966 if (is_lvds) {
6967 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6968 DPLL_FPA01_P1_POST_DIV_SHIFT);
6969 clock.p2 = 14;
6970
6971 if ((dpll & PLL_REF_INPUT_MASK) ==
6972 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6973 /* XXX: might not be 66MHz */
6974 intel_clock(dev, 66000, &clock);
6975 } else
6976 intel_clock(dev, 48000, &clock);
6977 } else {
6978 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6979 clock.p1 = 2;
6980 else {
6981 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6982 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6983 }
6984 if (dpll & PLL_P2_DIVIDE_BY_4)
6985 clock.p2 = 4;
6986 else
6987 clock.p2 = 2;
6988
6989 intel_clock(dev, 48000, &clock);
6990 }
6991 }
6992
6993 /* XXX: It would be nice to validate the clocks, but we can't reuse
6994 * i830PllIsValid() because it relies on the xf86_config connector
6995 * configuration being accurate, which it isn't necessarily.
6996 */
6997
6998 return clock.dot;
6999 }
7000
7001 /** Returns the currently programmed mode of the given pipe. */
7002 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7003 struct drm_crtc *crtc)
7004 {
7005 struct drm_i915_private *dev_priv = dev->dev_private;
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7008 struct drm_display_mode *mode;
7009 int htot = I915_READ(HTOTAL(cpu_transcoder));
7010 int hsync = I915_READ(HSYNC(cpu_transcoder));
7011 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7012 int vsync = I915_READ(VSYNC(cpu_transcoder));
7013
7014 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7015 if (!mode)
7016 return NULL;
7017
7018 mode->clock = intel_crtc_clock_get(dev, crtc);
7019 mode->hdisplay = (htot & 0xffff) + 1;
7020 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7021 mode->hsync_start = (hsync & 0xffff) + 1;
7022 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7023 mode->vdisplay = (vtot & 0xffff) + 1;
7024 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7025 mode->vsync_start = (vsync & 0xffff) + 1;
7026 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7027
7028 drm_mode_set_name(mode);
7029
7030 return mode;
7031 }
7032
7033 static void intel_increase_pllclock(struct drm_crtc *crtc)
7034 {
7035 struct drm_device *dev = crtc->dev;
7036 drm_i915_private_t *dev_priv = dev->dev_private;
7037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7038 int pipe = intel_crtc->pipe;
7039 int dpll_reg = DPLL(pipe);
7040 int dpll;
7041
7042 if (HAS_PCH_SPLIT(dev))
7043 return;
7044
7045 if (!dev_priv->lvds_downclock_avail)
7046 return;
7047
7048 dpll = I915_READ(dpll_reg);
7049 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7050 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7051
7052 assert_panel_unlocked(dev_priv, pipe);
7053
7054 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7055 I915_WRITE(dpll_reg, dpll);
7056 intel_wait_for_vblank(dev, pipe);
7057
7058 dpll = I915_READ(dpll_reg);
7059 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7060 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7061 }
7062 }
7063
7064 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7065 {
7066 struct drm_device *dev = crtc->dev;
7067 drm_i915_private_t *dev_priv = dev->dev_private;
7068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7069
7070 if (HAS_PCH_SPLIT(dev))
7071 return;
7072
7073 if (!dev_priv->lvds_downclock_avail)
7074 return;
7075
7076 /*
7077 * Since this is called by a timer, we should never get here in
7078 * the manual case.
7079 */
7080 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7081 int pipe = intel_crtc->pipe;
7082 int dpll_reg = DPLL(pipe);
7083 int dpll;
7084
7085 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7086
7087 assert_panel_unlocked(dev_priv, pipe);
7088
7089 dpll = I915_READ(dpll_reg);
7090 dpll |= DISPLAY_RATE_SELECT_FPA1;
7091 I915_WRITE(dpll_reg, dpll);
7092 intel_wait_for_vblank(dev, pipe);
7093 dpll = I915_READ(dpll_reg);
7094 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7095 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7096 }
7097
7098 }
7099
7100 void intel_mark_busy(struct drm_device *dev)
7101 {
7102 i915_update_gfx_val(dev->dev_private);
7103 }
7104
7105 void intel_mark_idle(struct drm_device *dev)
7106 {
7107 struct drm_crtc *crtc;
7108
7109 if (!i915_powersave)
7110 return;
7111
7112 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7113 if (!crtc->fb)
7114 continue;
7115
7116 intel_decrease_pllclock(crtc);
7117 }
7118 }
7119
7120 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7121 {
7122 struct drm_device *dev = obj->base.dev;
7123 struct drm_crtc *crtc;
7124
7125 if (!i915_powersave)
7126 return;
7127
7128 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7129 if (!crtc->fb)
7130 continue;
7131
7132 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7133 intel_increase_pllclock(crtc);
7134 }
7135 }
7136
7137 static void intel_crtc_destroy(struct drm_crtc *crtc)
7138 {
7139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140 struct drm_device *dev = crtc->dev;
7141 struct intel_unpin_work *work;
7142 unsigned long flags;
7143
7144 spin_lock_irqsave(&dev->event_lock, flags);
7145 work = intel_crtc->unpin_work;
7146 intel_crtc->unpin_work = NULL;
7147 spin_unlock_irqrestore(&dev->event_lock, flags);
7148
7149 if (work) {
7150 cancel_work_sync(&work->work);
7151 kfree(work);
7152 }
7153
7154 drm_crtc_cleanup(crtc);
7155
7156 kfree(intel_crtc);
7157 }
7158
7159 static void intel_unpin_work_fn(struct work_struct *__work)
7160 {
7161 struct intel_unpin_work *work =
7162 container_of(__work, struct intel_unpin_work, work);
7163 struct drm_device *dev = work->crtc->dev;
7164
7165 mutex_lock(&dev->struct_mutex);
7166 intel_unpin_fb_obj(work->old_fb_obj);
7167 drm_gem_object_unreference(&work->pending_flip_obj->base);
7168 drm_gem_object_unreference(&work->old_fb_obj->base);
7169
7170 intel_update_fbc(dev);
7171 mutex_unlock(&dev->struct_mutex);
7172
7173 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7174 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7175
7176 kfree(work);
7177 }
7178
7179 static void do_intel_finish_page_flip(struct drm_device *dev,
7180 struct drm_crtc *crtc)
7181 {
7182 drm_i915_private_t *dev_priv = dev->dev_private;
7183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7184 struct intel_unpin_work *work;
7185 unsigned long flags;
7186
7187 /* Ignore early vblank irqs */
7188 if (intel_crtc == NULL)
7189 return;
7190
7191 spin_lock_irqsave(&dev->event_lock, flags);
7192 work = intel_crtc->unpin_work;
7193
7194 /* Ensure we don't miss a work->pending update ... */
7195 smp_rmb();
7196
7197 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7198 spin_unlock_irqrestore(&dev->event_lock, flags);
7199 return;
7200 }
7201
7202 /* and that the unpin work is consistent wrt ->pending. */
7203 smp_rmb();
7204
7205 intel_crtc->unpin_work = NULL;
7206
7207 if (work->event)
7208 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7209
7210 drm_vblank_put(dev, intel_crtc->pipe);
7211
7212 spin_unlock_irqrestore(&dev->event_lock, flags);
7213
7214 wake_up_all(&dev_priv->pending_flip_queue);
7215
7216 queue_work(dev_priv->wq, &work->work);
7217
7218 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7219 }
7220
7221 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7222 {
7223 drm_i915_private_t *dev_priv = dev->dev_private;
7224 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7225
7226 do_intel_finish_page_flip(dev, crtc);
7227 }
7228
7229 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7230 {
7231 drm_i915_private_t *dev_priv = dev->dev_private;
7232 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7233
7234 do_intel_finish_page_flip(dev, crtc);
7235 }
7236
7237 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7238 {
7239 drm_i915_private_t *dev_priv = dev->dev_private;
7240 struct intel_crtc *intel_crtc =
7241 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7242 unsigned long flags;
7243
7244 /* NB: An MMIO update of the plane base pointer will also
7245 * generate a page-flip completion irq, i.e. every modeset
7246 * is also accompanied by a spurious intel_prepare_page_flip().
7247 */
7248 spin_lock_irqsave(&dev->event_lock, flags);
7249 if (intel_crtc->unpin_work)
7250 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7251 spin_unlock_irqrestore(&dev->event_lock, flags);
7252 }
7253
7254 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7255 {
7256 /* Ensure that the work item is consistent when activating it ... */
7257 smp_wmb();
7258 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7259 /* and that it is marked active as soon as the irq could fire. */
7260 smp_wmb();
7261 }
7262
7263 static int intel_gen2_queue_flip(struct drm_device *dev,
7264 struct drm_crtc *crtc,
7265 struct drm_framebuffer *fb,
7266 struct drm_i915_gem_object *obj)
7267 {
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270 u32 flip_mask;
7271 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7272 int ret;
7273
7274 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7275 if (ret)
7276 goto err;
7277
7278 ret = intel_ring_begin(ring, 6);
7279 if (ret)
7280 goto err_unpin;
7281
7282 /* Can't queue multiple flips, so wait for the previous
7283 * one to finish before executing the next.
7284 */
7285 if (intel_crtc->plane)
7286 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7287 else
7288 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7289 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7290 intel_ring_emit(ring, MI_NOOP);
7291 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7292 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7293 intel_ring_emit(ring, fb->pitches[0]);
7294 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7295 intel_ring_emit(ring, 0); /* aux display base address, unused */
7296
7297 intel_mark_page_flip_active(intel_crtc);
7298 intel_ring_advance(ring);
7299 return 0;
7300
7301 err_unpin:
7302 intel_unpin_fb_obj(obj);
7303 err:
7304 return ret;
7305 }
7306
7307 static int intel_gen3_queue_flip(struct drm_device *dev,
7308 struct drm_crtc *crtc,
7309 struct drm_framebuffer *fb,
7310 struct drm_i915_gem_object *obj)
7311 {
7312 struct drm_i915_private *dev_priv = dev->dev_private;
7313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314 u32 flip_mask;
7315 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7316 int ret;
7317
7318 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7319 if (ret)
7320 goto err;
7321
7322 ret = intel_ring_begin(ring, 6);
7323 if (ret)
7324 goto err_unpin;
7325
7326 if (intel_crtc->plane)
7327 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7328 else
7329 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7330 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7331 intel_ring_emit(ring, MI_NOOP);
7332 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7333 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7334 intel_ring_emit(ring, fb->pitches[0]);
7335 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7336 intel_ring_emit(ring, MI_NOOP);
7337
7338 intel_mark_page_flip_active(intel_crtc);
7339 intel_ring_advance(ring);
7340 return 0;
7341
7342 err_unpin:
7343 intel_unpin_fb_obj(obj);
7344 err:
7345 return ret;
7346 }
7347
7348 static int intel_gen4_queue_flip(struct drm_device *dev,
7349 struct drm_crtc *crtc,
7350 struct drm_framebuffer *fb,
7351 struct drm_i915_gem_object *obj)
7352 {
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7355 uint32_t pf, pipesrc;
7356 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7357 int ret;
7358
7359 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7360 if (ret)
7361 goto err;
7362
7363 ret = intel_ring_begin(ring, 4);
7364 if (ret)
7365 goto err_unpin;
7366
7367 /* i965+ uses the linear or tiled offsets from the
7368 * Display Registers (which do not change across a page-flip)
7369 * so we need only reprogram the base address.
7370 */
7371 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7372 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7373 intel_ring_emit(ring, fb->pitches[0]);
7374 intel_ring_emit(ring,
7375 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7376 obj->tiling_mode);
7377
7378 /* XXX Enabling the panel-fitter across page-flip is so far
7379 * untested on non-native modes, so ignore it for now.
7380 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7381 */
7382 pf = 0;
7383 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7384 intel_ring_emit(ring, pf | pipesrc);
7385
7386 intel_mark_page_flip_active(intel_crtc);
7387 intel_ring_advance(ring);
7388 return 0;
7389
7390 err_unpin:
7391 intel_unpin_fb_obj(obj);
7392 err:
7393 return ret;
7394 }
7395
7396 static int intel_gen6_queue_flip(struct drm_device *dev,
7397 struct drm_crtc *crtc,
7398 struct drm_framebuffer *fb,
7399 struct drm_i915_gem_object *obj)
7400 {
7401 struct drm_i915_private *dev_priv = dev->dev_private;
7402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7403 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7404 uint32_t pf, pipesrc;
7405 int ret;
7406
7407 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7408 if (ret)
7409 goto err;
7410
7411 ret = intel_ring_begin(ring, 4);
7412 if (ret)
7413 goto err_unpin;
7414
7415 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7416 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7417 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7418 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7419
7420 /* Contrary to the suggestions in the documentation,
7421 * "Enable Panel Fitter" does not seem to be required when page
7422 * flipping with a non-native mode, and worse causes a normal
7423 * modeset to fail.
7424 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7425 */
7426 pf = 0;
7427 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7428 intel_ring_emit(ring, pf | pipesrc);
7429
7430 intel_mark_page_flip_active(intel_crtc);
7431 intel_ring_advance(ring);
7432 return 0;
7433
7434 err_unpin:
7435 intel_unpin_fb_obj(obj);
7436 err:
7437 return ret;
7438 }
7439
7440 /*
7441 * On gen7 we currently use the blit ring because (in early silicon at least)
7442 * the render ring doesn't give us interrpts for page flip completion, which
7443 * means clients will hang after the first flip is queued. Fortunately the
7444 * blit ring generates interrupts properly, so use it instead.
7445 */
7446 static int intel_gen7_queue_flip(struct drm_device *dev,
7447 struct drm_crtc *crtc,
7448 struct drm_framebuffer *fb,
7449 struct drm_i915_gem_object *obj)
7450 {
7451 struct drm_i915_private *dev_priv = dev->dev_private;
7452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7453 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7454 uint32_t plane_bit = 0;
7455 int ret;
7456
7457 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7458 if (ret)
7459 goto err;
7460
7461 switch(intel_crtc->plane) {
7462 case PLANE_A:
7463 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7464 break;
7465 case PLANE_B:
7466 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7467 break;
7468 case PLANE_C:
7469 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7470 break;
7471 default:
7472 WARN_ONCE(1, "unknown plane in flip command\n");
7473 ret = -ENODEV;
7474 goto err_unpin;
7475 }
7476
7477 ret = intel_ring_begin(ring, 4);
7478 if (ret)
7479 goto err_unpin;
7480
7481 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7482 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7483 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7484 intel_ring_emit(ring, (MI_NOOP));
7485
7486 intel_mark_page_flip_active(intel_crtc);
7487 intel_ring_advance(ring);
7488 return 0;
7489
7490 err_unpin:
7491 intel_unpin_fb_obj(obj);
7492 err:
7493 return ret;
7494 }
7495
7496 static int intel_default_queue_flip(struct drm_device *dev,
7497 struct drm_crtc *crtc,
7498 struct drm_framebuffer *fb,
7499 struct drm_i915_gem_object *obj)
7500 {
7501 return -ENODEV;
7502 }
7503
7504 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7505 struct drm_framebuffer *fb,
7506 struct drm_pending_vblank_event *event)
7507 {
7508 struct drm_device *dev = crtc->dev;
7509 struct drm_i915_private *dev_priv = dev->dev_private;
7510 struct drm_framebuffer *old_fb = crtc->fb;
7511 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7513 struct intel_unpin_work *work;
7514 unsigned long flags;
7515 int ret;
7516
7517 /* Can't change pixel format via MI display flips. */
7518 if (fb->pixel_format != crtc->fb->pixel_format)
7519 return -EINVAL;
7520
7521 /*
7522 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7523 * Note that pitch changes could also affect these register.
7524 */
7525 if (INTEL_INFO(dev)->gen > 3 &&
7526 (fb->offsets[0] != crtc->fb->offsets[0] ||
7527 fb->pitches[0] != crtc->fb->pitches[0]))
7528 return -EINVAL;
7529
7530 work = kzalloc(sizeof *work, GFP_KERNEL);
7531 if (work == NULL)
7532 return -ENOMEM;
7533
7534 work->event = event;
7535 work->crtc = crtc;
7536 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7537 INIT_WORK(&work->work, intel_unpin_work_fn);
7538
7539 ret = drm_vblank_get(dev, intel_crtc->pipe);
7540 if (ret)
7541 goto free_work;
7542
7543 /* We borrow the event spin lock for protecting unpin_work */
7544 spin_lock_irqsave(&dev->event_lock, flags);
7545 if (intel_crtc->unpin_work) {
7546 spin_unlock_irqrestore(&dev->event_lock, flags);
7547 kfree(work);
7548 drm_vblank_put(dev, intel_crtc->pipe);
7549
7550 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7551 return -EBUSY;
7552 }
7553 intel_crtc->unpin_work = work;
7554 spin_unlock_irqrestore(&dev->event_lock, flags);
7555
7556 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7557 flush_workqueue(dev_priv->wq);
7558
7559 ret = i915_mutex_lock_interruptible(dev);
7560 if (ret)
7561 goto cleanup;
7562
7563 /* Reference the objects for the scheduled work. */
7564 drm_gem_object_reference(&work->old_fb_obj->base);
7565 drm_gem_object_reference(&obj->base);
7566
7567 crtc->fb = fb;
7568
7569 work->pending_flip_obj = obj;
7570
7571 work->enable_stall_check = true;
7572
7573 atomic_inc(&intel_crtc->unpin_work_count);
7574 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7575
7576 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7577 if (ret)
7578 goto cleanup_pending;
7579
7580 intel_disable_fbc(dev);
7581 intel_mark_fb_busy(obj);
7582 mutex_unlock(&dev->struct_mutex);
7583
7584 trace_i915_flip_request(intel_crtc->plane, obj);
7585
7586 return 0;
7587
7588 cleanup_pending:
7589 atomic_dec(&intel_crtc->unpin_work_count);
7590 crtc->fb = old_fb;
7591 drm_gem_object_unreference(&work->old_fb_obj->base);
7592 drm_gem_object_unreference(&obj->base);
7593 mutex_unlock(&dev->struct_mutex);
7594
7595 cleanup:
7596 spin_lock_irqsave(&dev->event_lock, flags);
7597 intel_crtc->unpin_work = NULL;
7598 spin_unlock_irqrestore(&dev->event_lock, flags);
7599
7600 drm_vblank_put(dev, intel_crtc->pipe);
7601 free_work:
7602 kfree(work);
7603
7604 return ret;
7605 }
7606
7607 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7608 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7609 .load_lut = intel_crtc_load_lut,
7610 };
7611
7612 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7613 {
7614 struct intel_encoder *other_encoder;
7615 struct drm_crtc *crtc = &encoder->new_crtc->base;
7616
7617 if (WARN_ON(!crtc))
7618 return false;
7619
7620 list_for_each_entry(other_encoder,
7621 &crtc->dev->mode_config.encoder_list,
7622 base.head) {
7623
7624 if (&other_encoder->new_crtc->base != crtc ||
7625 encoder == other_encoder)
7626 continue;
7627 else
7628 return true;
7629 }
7630
7631 return false;
7632 }
7633
7634 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7635 struct drm_crtc *crtc)
7636 {
7637 struct drm_device *dev;
7638 struct drm_crtc *tmp;
7639 int crtc_mask = 1;
7640
7641 WARN(!crtc, "checking null crtc?\n");
7642
7643 dev = crtc->dev;
7644
7645 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7646 if (tmp == crtc)
7647 break;
7648 crtc_mask <<= 1;
7649 }
7650
7651 if (encoder->possible_crtcs & crtc_mask)
7652 return true;
7653 return false;
7654 }
7655
7656 /**
7657 * intel_modeset_update_staged_output_state
7658 *
7659 * Updates the staged output configuration state, e.g. after we've read out the
7660 * current hw state.
7661 */
7662 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7663 {
7664 struct intel_encoder *encoder;
7665 struct intel_connector *connector;
7666
7667 list_for_each_entry(connector, &dev->mode_config.connector_list,
7668 base.head) {
7669 connector->new_encoder =
7670 to_intel_encoder(connector->base.encoder);
7671 }
7672
7673 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7674 base.head) {
7675 encoder->new_crtc =
7676 to_intel_crtc(encoder->base.crtc);
7677 }
7678 }
7679
7680 /**
7681 * intel_modeset_commit_output_state
7682 *
7683 * This function copies the stage display pipe configuration to the real one.
7684 */
7685 static void intel_modeset_commit_output_state(struct drm_device *dev)
7686 {
7687 struct intel_encoder *encoder;
7688 struct intel_connector *connector;
7689
7690 list_for_each_entry(connector, &dev->mode_config.connector_list,
7691 base.head) {
7692 connector->base.encoder = &connector->new_encoder->base;
7693 }
7694
7695 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7696 base.head) {
7697 encoder->base.crtc = &encoder->new_crtc->base;
7698 }
7699 }
7700
7701 static int
7702 pipe_config_set_bpp(struct drm_crtc *crtc,
7703 struct drm_framebuffer *fb,
7704 struct intel_crtc_config *pipe_config)
7705 {
7706 struct drm_device *dev = crtc->dev;
7707 struct drm_connector *connector;
7708 int bpp;
7709
7710 switch (fb->pixel_format) {
7711 case DRM_FORMAT_C8:
7712 bpp = 8*3; /* since we go through a colormap */
7713 break;
7714 case DRM_FORMAT_XRGB1555:
7715 case DRM_FORMAT_ARGB1555:
7716 /* checked in intel_framebuffer_init already */
7717 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7718 return -EINVAL;
7719 case DRM_FORMAT_RGB565:
7720 bpp = 6*3; /* min is 18bpp */
7721 break;
7722 case DRM_FORMAT_XBGR8888:
7723 case DRM_FORMAT_ABGR8888:
7724 /* checked in intel_framebuffer_init already */
7725 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7726 return -EINVAL;
7727 case DRM_FORMAT_XRGB8888:
7728 case DRM_FORMAT_ARGB8888:
7729 bpp = 8*3;
7730 break;
7731 case DRM_FORMAT_XRGB2101010:
7732 case DRM_FORMAT_ARGB2101010:
7733 case DRM_FORMAT_XBGR2101010:
7734 case DRM_FORMAT_ABGR2101010:
7735 /* checked in intel_framebuffer_init already */
7736 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7737 return -EINVAL;
7738 bpp = 10*3;
7739 break;
7740 /* TODO: gen4+ supports 16 bpc floating point, too. */
7741 default:
7742 DRM_DEBUG_KMS("unsupported depth\n");
7743 return -EINVAL;
7744 }
7745
7746 pipe_config->pipe_bpp = bpp;
7747
7748 /* Clamp display bpp to EDID value */
7749 list_for_each_entry(connector, &dev->mode_config.connector_list,
7750 head) {
7751 if (connector->encoder && connector->encoder->crtc != crtc)
7752 continue;
7753
7754 /* Don't use an invalid EDID bpc value */
7755 if (connector->display_info.bpc &&
7756 connector->display_info.bpc * 3 < bpp) {
7757 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7758 bpp, connector->display_info.bpc*3);
7759 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7760 }
7761
7762 /* Clamp bpp to 8 on screens without EDID 1.4 */
7763 if (connector->display_info.bpc == 0 && bpp > 24) {
7764 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7765 bpp);
7766 pipe_config->pipe_bpp = 24;
7767 }
7768 }
7769
7770 return bpp;
7771 }
7772
7773 static struct intel_crtc_config *
7774 intel_modeset_pipe_config(struct drm_crtc *crtc,
7775 struct drm_framebuffer *fb,
7776 struct drm_display_mode *mode)
7777 {
7778 struct drm_device *dev = crtc->dev;
7779 struct drm_encoder_helper_funcs *encoder_funcs;
7780 struct intel_encoder *encoder;
7781 struct intel_crtc_config *pipe_config;
7782 int plane_bpp, ret = -EINVAL;
7783 bool retry = true;
7784
7785 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7786 if (!pipe_config)
7787 return ERR_PTR(-ENOMEM);
7788
7789 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7790 drm_mode_copy(&pipe_config->requested_mode, mode);
7791
7792 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7793 if (plane_bpp < 0)
7794 goto fail;
7795
7796 encoder_retry:
7797 /* Pass our mode to the connectors and the CRTC to give them a chance to
7798 * adjust it according to limitations or connector properties, and also
7799 * a chance to reject the mode entirely.
7800 */
7801 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7802 base.head) {
7803
7804 if (&encoder->new_crtc->base != crtc)
7805 continue;
7806
7807 if (encoder->compute_config) {
7808 if (!(encoder->compute_config(encoder, pipe_config))) {
7809 DRM_DEBUG_KMS("Encoder config failure\n");
7810 goto fail;
7811 }
7812
7813 continue;
7814 }
7815
7816 encoder_funcs = encoder->base.helper_private;
7817 if (!(encoder_funcs->mode_fixup(&encoder->base,
7818 &pipe_config->requested_mode,
7819 &pipe_config->adjusted_mode))) {
7820 DRM_DEBUG_KMS("Encoder fixup failed\n");
7821 goto fail;
7822 }
7823 }
7824
7825 ret = intel_crtc_compute_config(crtc, pipe_config);
7826 if (ret < 0) {
7827 DRM_DEBUG_KMS("CRTC fixup failed\n");
7828 goto fail;
7829 }
7830
7831 if (ret == RETRY) {
7832 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7833 ret = -EINVAL;
7834 goto fail;
7835 }
7836
7837 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7838 retry = false;
7839 goto encoder_retry;
7840 }
7841
7842 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7843
7844 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7845 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7846 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7847
7848 return pipe_config;
7849 fail:
7850 kfree(pipe_config);
7851 return ERR_PTR(ret);
7852 }
7853
7854 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7855 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7856 static void
7857 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7858 unsigned *prepare_pipes, unsigned *disable_pipes)
7859 {
7860 struct intel_crtc *intel_crtc;
7861 struct drm_device *dev = crtc->dev;
7862 struct intel_encoder *encoder;
7863 struct intel_connector *connector;
7864 struct drm_crtc *tmp_crtc;
7865
7866 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7867
7868 /* Check which crtcs have changed outputs connected to them, these need
7869 * to be part of the prepare_pipes mask. We don't (yet) support global
7870 * modeset across multiple crtcs, so modeset_pipes will only have one
7871 * bit set at most. */
7872 list_for_each_entry(connector, &dev->mode_config.connector_list,
7873 base.head) {
7874 if (connector->base.encoder == &connector->new_encoder->base)
7875 continue;
7876
7877 if (connector->base.encoder) {
7878 tmp_crtc = connector->base.encoder->crtc;
7879
7880 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7881 }
7882
7883 if (connector->new_encoder)
7884 *prepare_pipes |=
7885 1 << connector->new_encoder->new_crtc->pipe;
7886 }
7887
7888 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7889 base.head) {
7890 if (encoder->base.crtc == &encoder->new_crtc->base)
7891 continue;
7892
7893 if (encoder->base.crtc) {
7894 tmp_crtc = encoder->base.crtc;
7895
7896 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7897 }
7898
7899 if (encoder->new_crtc)
7900 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7901 }
7902
7903 /* Check for any pipes that will be fully disabled ... */
7904 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7905 base.head) {
7906 bool used = false;
7907
7908 /* Don't try to disable disabled crtcs. */
7909 if (!intel_crtc->base.enabled)
7910 continue;
7911
7912 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7913 base.head) {
7914 if (encoder->new_crtc == intel_crtc)
7915 used = true;
7916 }
7917
7918 if (!used)
7919 *disable_pipes |= 1 << intel_crtc->pipe;
7920 }
7921
7922
7923 /* set_mode is also used to update properties on life display pipes. */
7924 intel_crtc = to_intel_crtc(crtc);
7925 if (crtc->enabled)
7926 *prepare_pipes |= 1 << intel_crtc->pipe;
7927
7928 /*
7929 * For simplicity do a full modeset on any pipe where the output routing
7930 * changed. We could be more clever, but that would require us to be
7931 * more careful with calling the relevant encoder->mode_set functions.
7932 */
7933 if (*prepare_pipes)
7934 *modeset_pipes = *prepare_pipes;
7935
7936 /* ... and mask these out. */
7937 *modeset_pipes &= ~(*disable_pipes);
7938 *prepare_pipes &= ~(*disable_pipes);
7939
7940 /*
7941 * HACK: We don't (yet) fully support global modesets. intel_set_config
7942 * obies this rule, but the modeset restore mode of
7943 * intel_modeset_setup_hw_state does not.
7944 */
7945 *modeset_pipes &= 1 << intel_crtc->pipe;
7946 *prepare_pipes &= 1 << intel_crtc->pipe;
7947
7948 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7949 *modeset_pipes, *prepare_pipes, *disable_pipes);
7950 }
7951
7952 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7953 {
7954 struct drm_encoder *encoder;
7955 struct drm_device *dev = crtc->dev;
7956
7957 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7958 if (encoder->crtc == crtc)
7959 return true;
7960
7961 return false;
7962 }
7963
7964 static void
7965 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7966 {
7967 struct intel_encoder *intel_encoder;
7968 struct intel_crtc *intel_crtc;
7969 struct drm_connector *connector;
7970
7971 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7972 base.head) {
7973 if (!intel_encoder->base.crtc)
7974 continue;
7975
7976 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7977
7978 if (prepare_pipes & (1 << intel_crtc->pipe))
7979 intel_encoder->connectors_active = false;
7980 }
7981
7982 intel_modeset_commit_output_state(dev);
7983
7984 /* Update computed state. */
7985 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7986 base.head) {
7987 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7988 }
7989
7990 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7991 if (!connector->encoder || !connector->encoder->crtc)
7992 continue;
7993
7994 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7995
7996 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7997 struct drm_property *dpms_property =
7998 dev->mode_config.dpms_property;
7999
8000 connector->dpms = DRM_MODE_DPMS_ON;
8001 drm_object_property_set_value(&connector->base,
8002 dpms_property,
8003 DRM_MODE_DPMS_ON);
8004
8005 intel_encoder = to_intel_encoder(connector->encoder);
8006 intel_encoder->connectors_active = true;
8007 }
8008 }
8009
8010 }
8011
8012 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8013 list_for_each_entry((intel_crtc), \
8014 &(dev)->mode_config.crtc_list, \
8015 base.head) \
8016 if (mask & (1 <<(intel_crtc)->pipe))
8017
8018 static bool
8019 intel_pipe_config_compare(struct drm_device *dev,
8020 struct intel_crtc_config *current_config,
8021 struct intel_crtc_config *pipe_config)
8022 {
8023 #define PIPE_CONF_CHECK_I(name) \
8024 if (current_config->name != pipe_config->name) { \
8025 DRM_ERROR("mismatch in " #name " " \
8026 "(expected %i, found %i)\n", \
8027 current_config->name, \
8028 pipe_config->name); \
8029 return false; \
8030 }
8031
8032 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8033 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8034 DRM_ERROR("mismatch in " #name " " \
8035 "(expected %i, found %i)\n", \
8036 current_config->name & (mask), \
8037 pipe_config->name & (mask)); \
8038 return false; \
8039 }
8040
8041 PIPE_CONF_CHECK_I(has_pch_encoder);
8042 PIPE_CONF_CHECK_I(fdi_lanes);
8043 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8044 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8045 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8046 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8047 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8048
8049 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8050 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8051 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8052 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8055
8056 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8057 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8059 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8060 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8061 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8062
8063 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8064 DRM_MODE_FLAG_INTERLACE);
8065
8066 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8067 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8068
8069 PIPE_CONF_CHECK_I(gmch_pfit.control);
8070 /* pfit ratios are autocomputed by the hw on gen4+ */
8071 if (INTEL_INFO(dev)->gen < 4)
8072 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8073 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8074 PIPE_CONF_CHECK_I(pch_pfit.pos);
8075 PIPE_CONF_CHECK_I(pch_pfit.size);
8076
8077 #undef PIPE_CONF_CHECK_I
8078 #undef PIPE_CONF_CHECK_FLAGS
8079
8080 return true;
8081 }
8082
8083 void
8084 intel_modeset_check_state(struct drm_device *dev)
8085 {
8086 drm_i915_private_t *dev_priv = dev->dev_private;
8087 struct intel_crtc *crtc;
8088 struct intel_encoder *encoder;
8089 struct intel_connector *connector;
8090 struct intel_crtc_config pipe_config;
8091
8092 list_for_each_entry(connector, &dev->mode_config.connector_list,
8093 base.head) {
8094 /* This also checks the encoder/connector hw state with the
8095 * ->get_hw_state callbacks. */
8096 intel_connector_check_state(connector);
8097
8098 WARN(&connector->new_encoder->base != connector->base.encoder,
8099 "connector's staged encoder doesn't match current encoder\n");
8100 }
8101
8102 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8103 base.head) {
8104 bool enabled = false;
8105 bool active = false;
8106 enum pipe pipe, tracked_pipe;
8107
8108 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8109 encoder->base.base.id,
8110 drm_get_encoder_name(&encoder->base));
8111
8112 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8113 "encoder's stage crtc doesn't match current crtc\n");
8114 WARN(encoder->connectors_active && !encoder->base.crtc,
8115 "encoder's active_connectors set, but no crtc\n");
8116
8117 list_for_each_entry(connector, &dev->mode_config.connector_list,
8118 base.head) {
8119 if (connector->base.encoder != &encoder->base)
8120 continue;
8121 enabled = true;
8122 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8123 active = true;
8124 }
8125 WARN(!!encoder->base.crtc != enabled,
8126 "encoder's enabled state mismatch "
8127 "(expected %i, found %i)\n",
8128 !!encoder->base.crtc, enabled);
8129 WARN(active && !encoder->base.crtc,
8130 "active encoder with no crtc\n");
8131
8132 WARN(encoder->connectors_active != active,
8133 "encoder's computed active state doesn't match tracked active state "
8134 "(expected %i, found %i)\n", active, encoder->connectors_active);
8135
8136 active = encoder->get_hw_state(encoder, &pipe);
8137 WARN(active != encoder->connectors_active,
8138 "encoder's hw state doesn't match sw tracking "
8139 "(expected %i, found %i)\n",
8140 encoder->connectors_active, active);
8141
8142 if (!encoder->base.crtc)
8143 continue;
8144
8145 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8146 WARN(active && pipe != tracked_pipe,
8147 "active encoder's pipe doesn't match"
8148 "(expected %i, found %i)\n",
8149 tracked_pipe, pipe);
8150
8151 }
8152
8153 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8154 base.head) {
8155 bool enabled = false;
8156 bool active = false;
8157
8158 DRM_DEBUG_KMS("[CRTC:%d]\n",
8159 crtc->base.base.id);
8160
8161 WARN(crtc->active && !crtc->base.enabled,
8162 "active crtc, but not enabled in sw tracking\n");
8163
8164 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8165 base.head) {
8166 if (encoder->base.crtc != &crtc->base)
8167 continue;
8168 enabled = true;
8169 if (encoder->connectors_active)
8170 active = true;
8171 }
8172 WARN(active != crtc->active,
8173 "crtc's computed active state doesn't match tracked active state "
8174 "(expected %i, found %i)\n", active, crtc->active);
8175 WARN(enabled != crtc->base.enabled,
8176 "crtc's computed enabled state doesn't match tracked enabled state "
8177 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8178
8179 memset(&pipe_config, 0, sizeof(pipe_config));
8180 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8181 active = dev_priv->display.get_pipe_config(crtc,
8182 &pipe_config);
8183 WARN(crtc->active != active,
8184 "crtc active state doesn't match with hw state "
8185 "(expected %i, found %i)\n", crtc->active, active);
8186
8187 WARN(active &&
8188 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config),
8189 "pipe state doesn't match!\n");
8190 }
8191 }
8192
8193 static int __intel_set_mode(struct drm_crtc *crtc,
8194 struct drm_display_mode *mode,
8195 int x, int y, struct drm_framebuffer *fb)
8196 {
8197 struct drm_device *dev = crtc->dev;
8198 drm_i915_private_t *dev_priv = dev->dev_private;
8199 struct drm_display_mode *saved_mode, *saved_hwmode;
8200 struct intel_crtc_config *pipe_config = NULL;
8201 struct intel_crtc *intel_crtc;
8202 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8203 int ret = 0;
8204
8205 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8206 if (!saved_mode)
8207 return -ENOMEM;
8208 saved_hwmode = saved_mode + 1;
8209
8210 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8211 &prepare_pipes, &disable_pipes);
8212
8213 *saved_hwmode = crtc->hwmode;
8214 *saved_mode = crtc->mode;
8215
8216 /* Hack: Because we don't (yet) support global modeset on multiple
8217 * crtcs, we don't keep track of the new mode for more than one crtc.
8218 * Hence simply check whether any bit is set in modeset_pipes in all the
8219 * pieces of code that are not yet converted to deal with mutliple crtcs
8220 * changing their mode at the same time. */
8221 if (modeset_pipes) {
8222 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8223 if (IS_ERR(pipe_config)) {
8224 ret = PTR_ERR(pipe_config);
8225 pipe_config = NULL;
8226
8227 goto out;
8228 }
8229 }
8230
8231 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8232 intel_crtc_disable(&intel_crtc->base);
8233
8234 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8235 if (intel_crtc->base.enabled)
8236 dev_priv->display.crtc_disable(&intel_crtc->base);
8237 }
8238
8239 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8240 * to set it here already despite that we pass it down the callchain.
8241 */
8242 if (modeset_pipes) {
8243 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8244 crtc->mode = *mode;
8245 /* mode_set/enable/disable functions rely on a correct pipe
8246 * config. */
8247 to_intel_crtc(crtc)->config = *pipe_config;
8248 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8249 }
8250
8251 /* Only after disabling all output pipelines that will be changed can we
8252 * update the the output configuration. */
8253 intel_modeset_update_state(dev, prepare_pipes);
8254
8255 if (dev_priv->display.modeset_global_resources)
8256 dev_priv->display.modeset_global_resources(dev);
8257
8258 /* Set up the DPLL and any encoders state that needs to adjust or depend
8259 * on the DPLL.
8260 */
8261 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8262 ret = intel_crtc_mode_set(&intel_crtc->base,
8263 x, y, fb);
8264 if (ret)
8265 goto done;
8266 }
8267
8268 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8269 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8270 dev_priv->display.crtc_enable(&intel_crtc->base);
8271
8272 if (modeset_pipes) {
8273 /* Store real post-adjustment hardware mode. */
8274 crtc->hwmode = pipe_config->adjusted_mode;
8275
8276 /* Calculate and store various constants which
8277 * are later needed by vblank and swap-completion
8278 * timestamping. They are derived from true hwmode.
8279 */
8280 drm_calc_timestamping_constants(crtc);
8281 }
8282
8283 /* FIXME: add subpixel order */
8284 done:
8285 if (ret && crtc->enabled) {
8286 crtc->hwmode = *saved_hwmode;
8287 crtc->mode = *saved_mode;
8288 }
8289
8290 out:
8291 kfree(pipe_config);
8292 kfree(saved_mode);
8293 return ret;
8294 }
8295
8296 int intel_set_mode(struct drm_crtc *crtc,
8297 struct drm_display_mode *mode,
8298 int x, int y, struct drm_framebuffer *fb)
8299 {
8300 int ret;
8301
8302 ret = __intel_set_mode(crtc, mode, x, y, fb);
8303
8304 if (ret == 0)
8305 intel_modeset_check_state(crtc->dev);
8306
8307 return ret;
8308 }
8309
8310 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8311 {
8312 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8313 }
8314
8315 #undef for_each_intel_crtc_masked
8316
8317 static void intel_set_config_free(struct intel_set_config *config)
8318 {
8319 if (!config)
8320 return;
8321
8322 kfree(config->save_connector_encoders);
8323 kfree(config->save_encoder_crtcs);
8324 kfree(config);
8325 }
8326
8327 static int intel_set_config_save_state(struct drm_device *dev,
8328 struct intel_set_config *config)
8329 {
8330 struct drm_encoder *encoder;
8331 struct drm_connector *connector;
8332 int count;
8333
8334 config->save_encoder_crtcs =
8335 kcalloc(dev->mode_config.num_encoder,
8336 sizeof(struct drm_crtc *), GFP_KERNEL);
8337 if (!config->save_encoder_crtcs)
8338 return -ENOMEM;
8339
8340 config->save_connector_encoders =
8341 kcalloc(dev->mode_config.num_connector,
8342 sizeof(struct drm_encoder *), GFP_KERNEL);
8343 if (!config->save_connector_encoders)
8344 return -ENOMEM;
8345
8346 /* Copy data. Note that driver private data is not affected.
8347 * Should anything bad happen only the expected state is
8348 * restored, not the drivers personal bookkeeping.
8349 */
8350 count = 0;
8351 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8352 config->save_encoder_crtcs[count++] = encoder->crtc;
8353 }
8354
8355 count = 0;
8356 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8357 config->save_connector_encoders[count++] = connector->encoder;
8358 }
8359
8360 return 0;
8361 }
8362
8363 static void intel_set_config_restore_state(struct drm_device *dev,
8364 struct intel_set_config *config)
8365 {
8366 struct intel_encoder *encoder;
8367 struct intel_connector *connector;
8368 int count;
8369
8370 count = 0;
8371 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8372 encoder->new_crtc =
8373 to_intel_crtc(config->save_encoder_crtcs[count++]);
8374 }
8375
8376 count = 0;
8377 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8378 connector->new_encoder =
8379 to_intel_encoder(config->save_connector_encoders[count++]);
8380 }
8381 }
8382
8383 static void
8384 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8385 struct intel_set_config *config)
8386 {
8387
8388 /* We should be able to check here if the fb has the same properties
8389 * and then just flip_or_move it */
8390 if (set->crtc->fb != set->fb) {
8391 /* If we have no fb then treat it as a full mode set */
8392 if (set->crtc->fb == NULL) {
8393 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8394 config->mode_changed = true;
8395 } else if (set->fb == NULL) {
8396 config->mode_changed = true;
8397 } else if (set->fb->pixel_format !=
8398 set->crtc->fb->pixel_format) {
8399 config->mode_changed = true;
8400 } else
8401 config->fb_changed = true;
8402 }
8403
8404 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8405 config->fb_changed = true;
8406
8407 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8408 DRM_DEBUG_KMS("modes are different, full mode set\n");
8409 drm_mode_debug_printmodeline(&set->crtc->mode);
8410 drm_mode_debug_printmodeline(set->mode);
8411 config->mode_changed = true;
8412 }
8413 }
8414
8415 static int
8416 intel_modeset_stage_output_state(struct drm_device *dev,
8417 struct drm_mode_set *set,
8418 struct intel_set_config *config)
8419 {
8420 struct drm_crtc *new_crtc;
8421 struct intel_connector *connector;
8422 struct intel_encoder *encoder;
8423 int count, ro;
8424
8425 /* The upper layers ensure that we either disable a crtc or have a list
8426 * of connectors. For paranoia, double-check this. */
8427 WARN_ON(!set->fb && (set->num_connectors != 0));
8428 WARN_ON(set->fb && (set->num_connectors == 0));
8429
8430 count = 0;
8431 list_for_each_entry(connector, &dev->mode_config.connector_list,
8432 base.head) {
8433 /* Otherwise traverse passed in connector list and get encoders
8434 * for them. */
8435 for (ro = 0; ro < set->num_connectors; ro++) {
8436 if (set->connectors[ro] == &connector->base) {
8437 connector->new_encoder = connector->encoder;
8438 break;
8439 }
8440 }
8441
8442 /* If we disable the crtc, disable all its connectors. Also, if
8443 * the connector is on the changing crtc but not on the new
8444 * connector list, disable it. */
8445 if ((!set->fb || ro == set->num_connectors) &&
8446 connector->base.encoder &&
8447 connector->base.encoder->crtc == set->crtc) {
8448 connector->new_encoder = NULL;
8449
8450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8451 connector->base.base.id,
8452 drm_get_connector_name(&connector->base));
8453 }
8454
8455
8456 if (&connector->new_encoder->base != connector->base.encoder) {
8457 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8458 config->mode_changed = true;
8459 }
8460 }
8461 /* connector->new_encoder is now updated for all connectors. */
8462
8463 /* Update crtc of enabled connectors. */
8464 count = 0;
8465 list_for_each_entry(connector, &dev->mode_config.connector_list,
8466 base.head) {
8467 if (!connector->new_encoder)
8468 continue;
8469
8470 new_crtc = connector->new_encoder->base.crtc;
8471
8472 for (ro = 0; ro < set->num_connectors; ro++) {
8473 if (set->connectors[ro] == &connector->base)
8474 new_crtc = set->crtc;
8475 }
8476
8477 /* Make sure the new CRTC will work with the encoder */
8478 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8479 new_crtc)) {
8480 return -EINVAL;
8481 }
8482 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8483
8484 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8485 connector->base.base.id,
8486 drm_get_connector_name(&connector->base),
8487 new_crtc->base.id);
8488 }
8489
8490 /* Check for any encoders that needs to be disabled. */
8491 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8492 base.head) {
8493 list_for_each_entry(connector,
8494 &dev->mode_config.connector_list,
8495 base.head) {
8496 if (connector->new_encoder == encoder) {
8497 WARN_ON(!connector->new_encoder->new_crtc);
8498
8499 goto next_encoder;
8500 }
8501 }
8502 encoder->new_crtc = NULL;
8503 next_encoder:
8504 /* Only now check for crtc changes so we don't miss encoders
8505 * that will be disabled. */
8506 if (&encoder->new_crtc->base != encoder->base.crtc) {
8507 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8508 config->mode_changed = true;
8509 }
8510 }
8511 /* Now we've also updated encoder->new_crtc for all encoders. */
8512
8513 return 0;
8514 }
8515
8516 static int intel_crtc_set_config(struct drm_mode_set *set)
8517 {
8518 struct drm_device *dev;
8519 struct drm_mode_set save_set;
8520 struct intel_set_config *config;
8521 int ret;
8522
8523 BUG_ON(!set);
8524 BUG_ON(!set->crtc);
8525 BUG_ON(!set->crtc->helper_private);
8526
8527 /* Enforce sane interface api - has been abused by the fb helper. */
8528 BUG_ON(!set->mode && set->fb);
8529 BUG_ON(set->fb && set->num_connectors == 0);
8530
8531 if (set->fb) {
8532 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8533 set->crtc->base.id, set->fb->base.id,
8534 (int)set->num_connectors, set->x, set->y);
8535 } else {
8536 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8537 }
8538
8539 dev = set->crtc->dev;
8540
8541 ret = -ENOMEM;
8542 config = kzalloc(sizeof(*config), GFP_KERNEL);
8543 if (!config)
8544 goto out_config;
8545
8546 ret = intel_set_config_save_state(dev, config);
8547 if (ret)
8548 goto out_config;
8549
8550 save_set.crtc = set->crtc;
8551 save_set.mode = &set->crtc->mode;
8552 save_set.x = set->crtc->x;
8553 save_set.y = set->crtc->y;
8554 save_set.fb = set->crtc->fb;
8555
8556 /* Compute whether we need a full modeset, only an fb base update or no
8557 * change at all. In the future we might also check whether only the
8558 * mode changed, e.g. for LVDS where we only change the panel fitter in
8559 * such cases. */
8560 intel_set_config_compute_mode_changes(set, config);
8561
8562 ret = intel_modeset_stage_output_state(dev, set, config);
8563 if (ret)
8564 goto fail;
8565
8566 if (config->mode_changed) {
8567 if (set->mode) {
8568 DRM_DEBUG_KMS("attempting to set mode from"
8569 " userspace\n");
8570 drm_mode_debug_printmodeline(set->mode);
8571 }
8572
8573 ret = intel_set_mode(set->crtc, set->mode,
8574 set->x, set->y, set->fb);
8575 if (ret) {
8576 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8577 set->crtc->base.id, ret);
8578 goto fail;
8579 }
8580 } else if (config->fb_changed) {
8581 intel_crtc_wait_for_pending_flips(set->crtc);
8582
8583 ret = intel_pipe_set_base(set->crtc,
8584 set->x, set->y, set->fb);
8585 }
8586
8587 intel_set_config_free(config);
8588
8589 return 0;
8590
8591 fail:
8592 intel_set_config_restore_state(dev, config);
8593
8594 /* Try to restore the config */
8595 if (config->mode_changed &&
8596 intel_set_mode(save_set.crtc, save_set.mode,
8597 save_set.x, save_set.y, save_set.fb))
8598 DRM_ERROR("failed to restore config after modeset failure\n");
8599
8600 out_config:
8601 intel_set_config_free(config);
8602 return ret;
8603 }
8604
8605 static const struct drm_crtc_funcs intel_crtc_funcs = {
8606 .cursor_set = intel_crtc_cursor_set,
8607 .cursor_move = intel_crtc_cursor_move,
8608 .gamma_set = intel_crtc_gamma_set,
8609 .set_config = intel_crtc_set_config,
8610 .destroy = intel_crtc_destroy,
8611 .page_flip = intel_crtc_page_flip,
8612 };
8613
8614 static void intel_cpu_pll_init(struct drm_device *dev)
8615 {
8616 if (HAS_DDI(dev))
8617 intel_ddi_pll_init(dev);
8618 }
8619
8620 static void intel_pch_pll_init(struct drm_device *dev)
8621 {
8622 drm_i915_private_t *dev_priv = dev->dev_private;
8623 int i;
8624
8625 if (dev_priv->num_pch_pll == 0) {
8626 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8627 return;
8628 }
8629
8630 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8631 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8632 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8633 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8634 }
8635 }
8636
8637 static void intel_crtc_init(struct drm_device *dev, int pipe)
8638 {
8639 drm_i915_private_t *dev_priv = dev->dev_private;
8640 struct intel_crtc *intel_crtc;
8641 int i;
8642
8643 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8644 if (intel_crtc == NULL)
8645 return;
8646
8647 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8648
8649 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8650 for (i = 0; i < 256; i++) {
8651 intel_crtc->lut_r[i] = i;
8652 intel_crtc->lut_g[i] = i;
8653 intel_crtc->lut_b[i] = i;
8654 }
8655
8656 /* Swap pipes & planes for FBC on pre-965 */
8657 intel_crtc->pipe = pipe;
8658 intel_crtc->plane = pipe;
8659 intel_crtc->config.cpu_transcoder = pipe;
8660 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8661 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8662 intel_crtc->plane = !pipe;
8663 }
8664
8665 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8666 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8667 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8668 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8669
8670 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8671 }
8672
8673 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8674 struct drm_file *file)
8675 {
8676 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8677 struct drm_mode_object *drmmode_obj;
8678 struct intel_crtc *crtc;
8679
8680 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8681 return -ENODEV;
8682
8683 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8684 DRM_MODE_OBJECT_CRTC);
8685
8686 if (!drmmode_obj) {
8687 DRM_ERROR("no such CRTC id\n");
8688 return -EINVAL;
8689 }
8690
8691 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8692 pipe_from_crtc_id->pipe = crtc->pipe;
8693
8694 return 0;
8695 }
8696
8697 static int intel_encoder_clones(struct intel_encoder *encoder)
8698 {
8699 struct drm_device *dev = encoder->base.dev;
8700 struct intel_encoder *source_encoder;
8701 int index_mask = 0;
8702 int entry = 0;
8703
8704 list_for_each_entry(source_encoder,
8705 &dev->mode_config.encoder_list, base.head) {
8706
8707 if (encoder == source_encoder)
8708 index_mask |= (1 << entry);
8709
8710 /* Intel hw has only one MUX where enocoders could be cloned. */
8711 if (encoder->cloneable && source_encoder->cloneable)
8712 index_mask |= (1 << entry);
8713
8714 entry++;
8715 }
8716
8717 return index_mask;
8718 }
8719
8720 static bool has_edp_a(struct drm_device *dev)
8721 {
8722 struct drm_i915_private *dev_priv = dev->dev_private;
8723
8724 if (!IS_MOBILE(dev))
8725 return false;
8726
8727 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8728 return false;
8729
8730 if (IS_GEN5(dev) &&
8731 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8732 return false;
8733
8734 return true;
8735 }
8736
8737 static void intel_setup_outputs(struct drm_device *dev)
8738 {
8739 struct drm_i915_private *dev_priv = dev->dev_private;
8740 struct intel_encoder *encoder;
8741 bool dpd_is_edp = false;
8742 bool has_lvds;
8743
8744 has_lvds = intel_lvds_init(dev);
8745 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8746 /* disable the panel fitter on everything but LVDS */
8747 I915_WRITE(PFIT_CONTROL, 0);
8748 }
8749
8750 if (!IS_ULT(dev))
8751 intel_crt_init(dev);
8752
8753 if (HAS_DDI(dev)) {
8754 int found;
8755
8756 /* Haswell uses DDI functions to detect digital outputs */
8757 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8758 /* DDI A only supports eDP */
8759 if (found)
8760 intel_ddi_init(dev, PORT_A);
8761
8762 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8763 * register */
8764 found = I915_READ(SFUSE_STRAP);
8765
8766 if (found & SFUSE_STRAP_DDIB_DETECTED)
8767 intel_ddi_init(dev, PORT_B);
8768 if (found & SFUSE_STRAP_DDIC_DETECTED)
8769 intel_ddi_init(dev, PORT_C);
8770 if (found & SFUSE_STRAP_DDID_DETECTED)
8771 intel_ddi_init(dev, PORT_D);
8772 } else if (HAS_PCH_SPLIT(dev)) {
8773 int found;
8774 dpd_is_edp = intel_dpd_is_edp(dev);
8775
8776 if (has_edp_a(dev))
8777 intel_dp_init(dev, DP_A, PORT_A);
8778
8779 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8780 /* PCH SDVOB multiplex with HDMIB */
8781 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8782 if (!found)
8783 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8784 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8785 intel_dp_init(dev, PCH_DP_B, PORT_B);
8786 }
8787
8788 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8789 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8790
8791 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8792 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8793
8794 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8795 intel_dp_init(dev, PCH_DP_C, PORT_C);
8796
8797 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8798 intel_dp_init(dev, PCH_DP_D, PORT_D);
8799 } else if (IS_VALLEYVIEW(dev)) {
8800 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8801 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8802 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8803
8804 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8805 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8806 PORT_B);
8807 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8808 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8809 }
8810 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8811 bool found = false;
8812
8813 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8814 DRM_DEBUG_KMS("probing SDVOB\n");
8815 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8816 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8817 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8818 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8819 }
8820
8821 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8822 intel_dp_init(dev, DP_B, PORT_B);
8823 }
8824
8825 /* Before G4X SDVOC doesn't have its own detect register */
8826
8827 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8828 DRM_DEBUG_KMS("probing SDVOC\n");
8829 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8830 }
8831
8832 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8833
8834 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8835 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8836 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8837 }
8838 if (SUPPORTS_INTEGRATED_DP(dev))
8839 intel_dp_init(dev, DP_C, PORT_C);
8840 }
8841
8842 if (SUPPORTS_INTEGRATED_DP(dev) &&
8843 (I915_READ(DP_D) & DP_DETECTED))
8844 intel_dp_init(dev, DP_D, PORT_D);
8845 } else if (IS_GEN2(dev))
8846 intel_dvo_init(dev);
8847
8848 if (SUPPORTS_TV(dev))
8849 intel_tv_init(dev);
8850
8851 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8852 encoder->base.possible_crtcs = encoder->crtc_mask;
8853 encoder->base.possible_clones =
8854 intel_encoder_clones(encoder);
8855 }
8856
8857 intel_init_pch_refclk(dev);
8858
8859 drm_helper_move_panel_connectors_to_head(dev);
8860 }
8861
8862 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8863 {
8864 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8865
8866 drm_framebuffer_cleanup(fb);
8867 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8868
8869 kfree(intel_fb);
8870 }
8871
8872 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8873 struct drm_file *file,
8874 unsigned int *handle)
8875 {
8876 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8877 struct drm_i915_gem_object *obj = intel_fb->obj;
8878
8879 return drm_gem_handle_create(file, &obj->base, handle);
8880 }
8881
8882 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8883 .destroy = intel_user_framebuffer_destroy,
8884 .create_handle = intel_user_framebuffer_create_handle,
8885 };
8886
8887 int intel_framebuffer_init(struct drm_device *dev,
8888 struct intel_framebuffer *intel_fb,
8889 struct drm_mode_fb_cmd2 *mode_cmd,
8890 struct drm_i915_gem_object *obj)
8891 {
8892 int ret;
8893
8894 if (obj->tiling_mode == I915_TILING_Y) {
8895 DRM_DEBUG("hardware does not support tiling Y\n");
8896 return -EINVAL;
8897 }
8898
8899 if (mode_cmd->pitches[0] & 63) {
8900 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8901 mode_cmd->pitches[0]);
8902 return -EINVAL;
8903 }
8904
8905 /* FIXME <= Gen4 stride limits are bit unclear */
8906 if (mode_cmd->pitches[0] > 32768) {
8907 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8908 mode_cmd->pitches[0]);
8909 return -EINVAL;
8910 }
8911
8912 if (obj->tiling_mode != I915_TILING_NONE &&
8913 mode_cmd->pitches[0] != obj->stride) {
8914 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8915 mode_cmd->pitches[0], obj->stride);
8916 return -EINVAL;
8917 }
8918
8919 /* Reject formats not supported by any plane early. */
8920 switch (mode_cmd->pixel_format) {
8921 case DRM_FORMAT_C8:
8922 case DRM_FORMAT_RGB565:
8923 case DRM_FORMAT_XRGB8888:
8924 case DRM_FORMAT_ARGB8888:
8925 break;
8926 case DRM_FORMAT_XRGB1555:
8927 case DRM_FORMAT_ARGB1555:
8928 if (INTEL_INFO(dev)->gen > 3) {
8929 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8930 return -EINVAL;
8931 }
8932 break;
8933 case DRM_FORMAT_XBGR8888:
8934 case DRM_FORMAT_ABGR8888:
8935 case DRM_FORMAT_XRGB2101010:
8936 case DRM_FORMAT_ARGB2101010:
8937 case DRM_FORMAT_XBGR2101010:
8938 case DRM_FORMAT_ABGR2101010:
8939 if (INTEL_INFO(dev)->gen < 4) {
8940 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8941 return -EINVAL;
8942 }
8943 break;
8944 case DRM_FORMAT_YUYV:
8945 case DRM_FORMAT_UYVY:
8946 case DRM_FORMAT_YVYU:
8947 case DRM_FORMAT_VYUY:
8948 if (INTEL_INFO(dev)->gen < 5) {
8949 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8950 return -EINVAL;
8951 }
8952 break;
8953 default:
8954 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8955 return -EINVAL;
8956 }
8957
8958 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8959 if (mode_cmd->offsets[0] != 0)
8960 return -EINVAL;
8961
8962 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8963 intel_fb->obj = obj;
8964
8965 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8966 if (ret) {
8967 DRM_ERROR("framebuffer init failed %d\n", ret);
8968 return ret;
8969 }
8970
8971 return 0;
8972 }
8973
8974 static struct drm_framebuffer *
8975 intel_user_framebuffer_create(struct drm_device *dev,
8976 struct drm_file *filp,
8977 struct drm_mode_fb_cmd2 *mode_cmd)
8978 {
8979 struct drm_i915_gem_object *obj;
8980
8981 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8982 mode_cmd->handles[0]));
8983 if (&obj->base == NULL)
8984 return ERR_PTR(-ENOENT);
8985
8986 return intel_framebuffer_create(dev, mode_cmd, obj);
8987 }
8988
8989 static const struct drm_mode_config_funcs intel_mode_funcs = {
8990 .fb_create = intel_user_framebuffer_create,
8991 .output_poll_changed = intel_fb_output_poll_changed,
8992 };
8993
8994 /* Set up chip specific display functions */
8995 static void intel_init_display(struct drm_device *dev)
8996 {
8997 struct drm_i915_private *dev_priv = dev->dev_private;
8998
8999 if (HAS_DDI(dev)) {
9000 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9001 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9002 dev_priv->display.crtc_enable = haswell_crtc_enable;
9003 dev_priv->display.crtc_disable = haswell_crtc_disable;
9004 dev_priv->display.off = haswell_crtc_off;
9005 dev_priv->display.update_plane = ironlake_update_plane;
9006 } else if (HAS_PCH_SPLIT(dev)) {
9007 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9008 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9009 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9010 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9011 dev_priv->display.off = ironlake_crtc_off;
9012 dev_priv->display.update_plane = ironlake_update_plane;
9013 } else if (IS_VALLEYVIEW(dev)) {
9014 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9015 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9016 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9017 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9018 dev_priv->display.off = i9xx_crtc_off;
9019 dev_priv->display.update_plane = i9xx_update_plane;
9020 } else {
9021 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9022 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9023 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9024 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9025 dev_priv->display.off = i9xx_crtc_off;
9026 dev_priv->display.update_plane = i9xx_update_plane;
9027 }
9028
9029 /* Returns the core display clock speed */
9030 if (IS_VALLEYVIEW(dev))
9031 dev_priv->display.get_display_clock_speed =
9032 valleyview_get_display_clock_speed;
9033 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9034 dev_priv->display.get_display_clock_speed =
9035 i945_get_display_clock_speed;
9036 else if (IS_I915G(dev))
9037 dev_priv->display.get_display_clock_speed =
9038 i915_get_display_clock_speed;
9039 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9040 dev_priv->display.get_display_clock_speed =
9041 i9xx_misc_get_display_clock_speed;
9042 else if (IS_I915GM(dev))
9043 dev_priv->display.get_display_clock_speed =
9044 i915gm_get_display_clock_speed;
9045 else if (IS_I865G(dev))
9046 dev_priv->display.get_display_clock_speed =
9047 i865_get_display_clock_speed;
9048 else if (IS_I85X(dev))
9049 dev_priv->display.get_display_clock_speed =
9050 i855_get_display_clock_speed;
9051 else /* 852, 830 */
9052 dev_priv->display.get_display_clock_speed =
9053 i830_get_display_clock_speed;
9054
9055 if (HAS_PCH_SPLIT(dev)) {
9056 if (IS_GEN5(dev)) {
9057 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9058 dev_priv->display.write_eld = ironlake_write_eld;
9059 } else if (IS_GEN6(dev)) {
9060 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9061 dev_priv->display.write_eld = ironlake_write_eld;
9062 } else if (IS_IVYBRIDGE(dev)) {
9063 /* FIXME: detect B0+ stepping and use auto training */
9064 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9065 dev_priv->display.write_eld = ironlake_write_eld;
9066 dev_priv->display.modeset_global_resources =
9067 ivb_modeset_global_resources;
9068 } else if (IS_HASWELL(dev)) {
9069 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9070 dev_priv->display.write_eld = haswell_write_eld;
9071 dev_priv->display.modeset_global_resources =
9072 haswell_modeset_global_resources;
9073 }
9074 } else if (IS_G4X(dev)) {
9075 dev_priv->display.write_eld = g4x_write_eld;
9076 }
9077
9078 /* Default just returns -ENODEV to indicate unsupported */
9079 dev_priv->display.queue_flip = intel_default_queue_flip;
9080
9081 switch (INTEL_INFO(dev)->gen) {
9082 case 2:
9083 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9084 break;
9085
9086 case 3:
9087 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9088 break;
9089
9090 case 4:
9091 case 5:
9092 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9093 break;
9094
9095 case 6:
9096 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9097 break;
9098 case 7:
9099 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9100 break;
9101 }
9102 }
9103
9104 /*
9105 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9106 * resume, or other times. This quirk makes sure that's the case for
9107 * affected systems.
9108 */
9109 static void quirk_pipea_force(struct drm_device *dev)
9110 {
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112
9113 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9114 DRM_INFO("applying pipe a force quirk\n");
9115 }
9116
9117 /*
9118 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9119 */
9120 static void quirk_ssc_force_disable(struct drm_device *dev)
9121 {
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9123 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9124 DRM_INFO("applying lvds SSC disable quirk\n");
9125 }
9126
9127 /*
9128 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9129 * brightness value
9130 */
9131 static void quirk_invert_brightness(struct drm_device *dev)
9132 {
9133 struct drm_i915_private *dev_priv = dev->dev_private;
9134 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9135 DRM_INFO("applying inverted panel brightness quirk\n");
9136 }
9137
9138 struct intel_quirk {
9139 int device;
9140 int subsystem_vendor;
9141 int subsystem_device;
9142 void (*hook)(struct drm_device *dev);
9143 };
9144
9145 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9146 struct intel_dmi_quirk {
9147 void (*hook)(struct drm_device *dev);
9148 const struct dmi_system_id (*dmi_id_list)[];
9149 };
9150
9151 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9152 {
9153 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9154 return 1;
9155 }
9156
9157 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9158 {
9159 .dmi_id_list = &(const struct dmi_system_id[]) {
9160 {
9161 .callback = intel_dmi_reverse_brightness,
9162 .ident = "NCR Corporation",
9163 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9164 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9165 },
9166 },
9167 { } /* terminating entry */
9168 },
9169 .hook = quirk_invert_brightness,
9170 },
9171 };
9172
9173 static struct intel_quirk intel_quirks[] = {
9174 /* HP Mini needs pipe A force quirk (LP: #322104) */
9175 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9176
9177 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9178 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9179
9180 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9181 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9182
9183 /* 830/845 need to leave pipe A & dpll A up */
9184 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9185 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9186
9187 /* Lenovo U160 cannot use SSC on LVDS */
9188 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9189
9190 /* Sony Vaio Y cannot use SSC on LVDS */
9191 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9192
9193 /* Acer Aspire 5734Z must invert backlight brightness */
9194 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9195
9196 /* Acer/eMachines G725 */
9197 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9198
9199 /* Acer/eMachines e725 */
9200 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9201
9202 /* Acer/Packard Bell NCL20 */
9203 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9204
9205 /* Acer Aspire 4736Z */
9206 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9207 };
9208
9209 static void intel_init_quirks(struct drm_device *dev)
9210 {
9211 struct pci_dev *d = dev->pdev;
9212 int i;
9213
9214 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9215 struct intel_quirk *q = &intel_quirks[i];
9216
9217 if (d->device == q->device &&
9218 (d->subsystem_vendor == q->subsystem_vendor ||
9219 q->subsystem_vendor == PCI_ANY_ID) &&
9220 (d->subsystem_device == q->subsystem_device ||
9221 q->subsystem_device == PCI_ANY_ID))
9222 q->hook(dev);
9223 }
9224 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9225 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9226 intel_dmi_quirks[i].hook(dev);
9227 }
9228 }
9229
9230 /* Disable the VGA plane that we never use */
9231 static void i915_disable_vga(struct drm_device *dev)
9232 {
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234 u8 sr1;
9235 u32 vga_reg = i915_vgacntrl_reg(dev);
9236
9237 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9238 outb(SR01, VGA_SR_INDEX);
9239 sr1 = inb(VGA_SR_DATA);
9240 outb(sr1 | 1<<5, VGA_SR_DATA);
9241 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9242 udelay(300);
9243
9244 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9245 POSTING_READ(vga_reg);
9246 }
9247
9248 void intel_modeset_init_hw(struct drm_device *dev)
9249 {
9250 intel_init_power_well(dev);
9251
9252 intel_prepare_ddi(dev);
9253
9254 intel_init_clock_gating(dev);
9255
9256 mutex_lock(&dev->struct_mutex);
9257 intel_enable_gt_powersave(dev);
9258 mutex_unlock(&dev->struct_mutex);
9259 }
9260
9261 void intel_modeset_suspend_hw(struct drm_device *dev)
9262 {
9263 intel_suspend_hw(dev);
9264 }
9265
9266 void intel_modeset_init(struct drm_device *dev)
9267 {
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269 int i, j, ret;
9270
9271 drm_mode_config_init(dev);
9272
9273 dev->mode_config.min_width = 0;
9274 dev->mode_config.min_height = 0;
9275
9276 dev->mode_config.preferred_depth = 24;
9277 dev->mode_config.prefer_shadow = 1;
9278
9279 dev->mode_config.funcs = &intel_mode_funcs;
9280
9281 intel_init_quirks(dev);
9282
9283 intel_init_pm(dev);
9284
9285 if (INTEL_INFO(dev)->num_pipes == 0)
9286 return;
9287
9288 intel_init_display(dev);
9289
9290 if (IS_GEN2(dev)) {
9291 dev->mode_config.max_width = 2048;
9292 dev->mode_config.max_height = 2048;
9293 } else if (IS_GEN3(dev)) {
9294 dev->mode_config.max_width = 4096;
9295 dev->mode_config.max_height = 4096;
9296 } else {
9297 dev->mode_config.max_width = 8192;
9298 dev->mode_config.max_height = 8192;
9299 }
9300 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9301
9302 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9303 INTEL_INFO(dev)->num_pipes,
9304 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9305
9306 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9307 intel_crtc_init(dev, i);
9308 for (j = 0; j < dev_priv->num_plane; j++) {
9309 ret = intel_plane_init(dev, i, j);
9310 if (ret)
9311 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9312 pipe_name(i), sprite_name(i, j), ret);
9313 }
9314 }
9315
9316 intel_cpu_pll_init(dev);
9317 intel_pch_pll_init(dev);
9318
9319 /* Just disable it once at startup */
9320 i915_disable_vga(dev);
9321 intel_setup_outputs(dev);
9322
9323 /* Just in case the BIOS is doing something questionable. */
9324 intel_disable_fbc(dev);
9325 }
9326
9327 static void
9328 intel_connector_break_all_links(struct intel_connector *connector)
9329 {
9330 connector->base.dpms = DRM_MODE_DPMS_OFF;
9331 connector->base.encoder = NULL;
9332 connector->encoder->connectors_active = false;
9333 connector->encoder->base.crtc = NULL;
9334 }
9335
9336 static void intel_enable_pipe_a(struct drm_device *dev)
9337 {
9338 struct intel_connector *connector;
9339 struct drm_connector *crt = NULL;
9340 struct intel_load_detect_pipe load_detect_temp;
9341
9342 /* We can't just switch on the pipe A, we need to set things up with a
9343 * proper mode and output configuration. As a gross hack, enable pipe A
9344 * by enabling the load detect pipe once. */
9345 list_for_each_entry(connector,
9346 &dev->mode_config.connector_list,
9347 base.head) {
9348 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9349 crt = &connector->base;
9350 break;
9351 }
9352 }
9353
9354 if (!crt)
9355 return;
9356
9357 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9358 intel_release_load_detect_pipe(crt, &load_detect_temp);
9359
9360
9361 }
9362
9363 static bool
9364 intel_check_plane_mapping(struct intel_crtc *crtc)
9365 {
9366 struct drm_device *dev = crtc->base.dev;
9367 struct drm_i915_private *dev_priv = dev->dev_private;
9368 u32 reg, val;
9369
9370 if (INTEL_INFO(dev)->num_pipes == 1)
9371 return true;
9372
9373 reg = DSPCNTR(!crtc->plane);
9374 val = I915_READ(reg);
9375
9376 if ((val & DISPLAY_PLANE_ENABLE) &&
9377 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9378 return false;
9379
9380 return true;
9381 }
9382
9383 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9384 {
9385 struct drm_device *dev = crtc->base.dev;
9386 struct drm_i915_private *dev_priv = dev->dev_private;
9387 u32 reg;
9388
9389 /* Clear any frame start delays used for debugging left by the BIOS */
9390 reg = PIPECONF(crtc->config.cpu_transcoder);
9391 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9392
9393 /* We need to sanitize the plane -> pipe mapping first because this will
9394 * disable the crtc (and hence change the state) if it is wrong. Note
9395 * that gen4+ has a fixed plane -> pipe mapping. */
9396 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9397 struct intel_connector *connector;
9398 bool plane;
9399
9400 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9401 crtc->base.base.id);
9402
9403 /* Pipe has the wrong plane attached and the plane is active.
9404 * Temporarily change the plane mapping and disable everything
9405 * ... */
9406 plane = crtc->plane;
9407 crtc->plane = !plane;
9408 dev_priv->display.crtc_disable(&crtc->base);
9409 crtc->plane = plane;
9410
9411 /* ... and break all links. */
9412 list_for_each_entry(connector, &dev->mode_config.connector_list,
9413 base.head) {
9414 if (connector->encoder->base.crtc != &crtc->base)
9415 continue;
9416
9417 intel_connector_break_all_links(connector);
9418 }
9419
9420 WARN_ON(crtc->active);
9421 crtc->base.enabled = false;
9422 }
9423
9424 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9425 crtc->pipe == PIPE_A && !crtc->active) {
9426 /* BIOS forgot to enable pipe A, this mostly happens after
9427 * resume. Force-enable the pipe to fix this, the update_dpms
9428 * call below we restore the pipe to the right state, but leave
9429 * the required bits on. */
9430 intel_enable_pipe_a(dev);
9431 }
9432
9433 /* Adjust the state of the output pipe according to whether we
9434 * have active connectors/encoders. */
9435 intel_crtc_update_dpms(&crtc->base);
9436
9437 if (crtc->active != crtc->base.enabled) {
9438 struct intel_encoder *encoder;
9439
9440 /* This can happen either due to bugs in the get_hw_state
9441 * functions or because the pipe is force-enabled due to the
9442 * pipe A quirk. */
9443 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9444 crtc->base.base.id,
9445 crtc->base.enabled ? "enabled" : "disabled",
9446 crtc->active ? "enabled" : "disabled");
9447
9448 crtc->base.enabled = crtc->active;
9449
9450 /* Because we only establish the connector -> encoder ->
9451 * crtc links if something is active, this means the
9452 * crtc is now deactivated. Break the links. connector
9453 * -> encoder links are only establish when things are
9454 * actually up, hence no need to break them. */
9455 WARN_ON(crtc->active);
9456
9457 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9458 WARN_ON(encoder->connectors_active);
9459 encoder->base.crtc = NULL;
9460 }
9461 }
9462 }
9463
9464 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9465 {
9466 struct intel_connector *connector;
9467 struct drm_device *dev = encoder->base.dev;
9468
9469 /* We need to check both for a crtc link (meaning that the
9470 * encoder is active and trying to read from a pipe) and the
9471 * pipe itself being active. */
9472 bool has_active_crtc = encoder->base.crtc &&
9473 to_intel_crtc(encoder->base.crtc)->active;
9474
9475 if (encoder->connectors_active && !has_active_crtc) {
9476 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9477 encoder->base.base.id,
9478 drm_get_encoder_name(&encoder->base));
9479
9480 /* Connector is active, but has no active pipe. This is
9481 * fallout from our resume register restoring. Disable
9482 * the encoder manually again. */
9483 if (encoder->base.crtc) {
9484 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9485 encoder->base.base.id,
9486 drm_get_encoder_name(&encoder->base));
9487 encoder->disable(encoder);
9488 }
9489
9490 /* Inconsistent output/port/pipe state happens presumably due to
9491 * a bug in one of the get_hw_state functions. Or someplace else
9492 * in our code, like the register restore mess on resume. Clamp
9493 * things to off as a safer default. */
9494 list_for_each_entry(connector,
9495 &dev->mode_config.connector_list,
9496 base.head) {
9497 if (connector->encoder != encoder)
9498 continue;
9499
9500 intel_connector_break_all_links(connector);
9501 }
9502 }
9503 /* Enabled encoders without active connectors will be fixed in
9504 * the crtc fixup. */
9505 }
9506
9507 void i915_redisable_vga(struct drm_device *dev)
9508 {
9509 struct drm_i915_private *dev_priv = dev->dev_private;
9510 u32 vga_reg = i915_vgacntrl_reg(dev);
9511
9512 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9513 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9514 i915_disable_vga(dev);
9515 }
9516 }
9517
9518 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9519 * and i915 state tracking structures. */
9520 void intel_modeset_setup_hw_state(struct drm_device *dev,
9521 bool force_restore)
9522 {
9523 struct drm_i915_private *dev_priv = dev->dev_private;
9524 enum pipe pipe;
9525 u32 tmp;
9526 struct drm_plane *plane;
9527 struct intel_crtc *crtc;
9528 struct intel_encoder *encoder;
9529 struct intel_connector *connector;
9530
9531 if (HAS_DDI(dev)) {
9532 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9533
9534 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9535 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9536 case TRANS_DDI_EDP_INPUT_A_ON:
9537 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9538 pipe = PIPE_A;
9539 break;
9540 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9541 pipe = PIPE_B;
9542 break;
9543 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9544 pipe = PIPE_C;
9545 break;
9546 default:
9547 /* A bogus value has been programmed, disable
9548 * the transcoder */
9549 WARN(1, "Bogus eDP source %08x\n", tmp);
9550 intel_ddi_disable_transcoder_func(dev_priv,
9551 TRANSCODER_EDP);
9552 goto setup_pipes;
9553 }
9554
9555 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9556 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9557
9558 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9559 pipe_name(pipe));
9560 }
9561 }
9562
9563 setup_pipes:
9564 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9565 base.head) {
9566 enum transcoder tmp = crtc->config.cpu_transcoder;
9567 memset(&crtc->config, 0, sizeof(crtc->config));
9568 crtc->config.cpu_transcoder = tmp;
9569
9570 crtc->active = dev_priv->display.get_pipe_config(crtc,
9571 &crtc->config);
9572
9573 crtc->base.enabled = crtc->active;
9574
9575 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9576 crtc->base.base.id,
9577 crtc->active ? "enabled" : "disabled");
9578 }
9579
9580 if (HAS_DDI(dev))
9581 intel_ddi_setup_hw_pll_state(dev);
9582
9583 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9584 base.head) {
9585 pipe = 0;
9586
9587 if (encoder->get_hw_state(encoder, &pipe)) {
9588 encoder->base.crtc =
9589 dev_priv->pipe_to_crtc_mapping[pipe];
9590 } else {
9591 encoder->base.crtc = NULL;
9592 }
9593
9594 encoder->connectors_active = false;
9595 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9596 encoder->base.base.id,
9597 drm_get_encoder_name(&encoder->base),
9598 encoder->base.crtc ? "enabled" : "disabled",
9599 pipe);
9600 }
9601
9602 list_for_each_entry(connector, &dev->mode_config.connector_list,
9603 base.head) {
9604 if (connector->get_hw_state(connector)) {
9605 connector->base.dpms = DRM_MODE_DPMS_ON;
9606 connector->encoder->connectors_active = true;
9607 connector->base.encoder = &connector->encoder->base;
9608 } else {
9609 connector->base.dpms = DRM_MODE_DPMS_OFF;
9610 connector->base.encoder = NULL;
9611 }
9612 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9613 connector->base.base.id,
9614 drm_get_connector_name(&connector->base),
9615 connector->base.encoder ? "enabled" : "disabled");
9616 }
9617
9618 /* HW state is read out, now we need to sanitize this mess. */
9619 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9620 base.head) {
9621 intel_sanitize_encoder(encoder);
9622 }
9623
9624 for_each_pipe(pipe) {
9625 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9626 intel_sanitize_crtc(crtc);
9627 }
9628
9629 if (force_restore) {
9630 /*
9631 * We need to use raw interfaces for restoring state to avoid
9632 * checking (bogus) intermediate states.
9633 */
9634 for_each_pipe(pipe) {
9635 struct drm_crtc *crtc =
9636 dev_priv->pipe_to_crtc_mapping[pipe];
9637
9638 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9639 crtc->fb);
9640 }
9641 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9642 intel_plane_restore(plane);
9643
9644 i915_redisable_vga(dev);
9645 } else {
9646 intel_modeset_update_staged_output_state(dev);
9647 }
9648
9649 intel_modeset_check_state(dev);
9650
9651 drm_mode_config_reset(dev);
9652 }
9653
9654 void intel_modeset_gem_init(struct drm_device *dev)
9655 {
9656 intel_modeset_init_hw(dev);
9657
9658 intel_setup_overlay(dev);
9659
9660 intel_modeset_setup_hw_state(dev, false);
9661 }
9662
9663 void intel_modeset_cleanup(struct drm_device *dev)
9664 {
9665 struct drm_i915_private *dev_priv = dev->dev_private;
9666 struct drm_crtc *crtc;
9667 struct intel_crtc *intel_crtc;
9668
9669 /*
9670 * Interrupts and polling as the first thing to avoid creating havoc.
9671 * Too much stuff here (turning of rps, connectors, ...) would
9672 * experience fancy races otherwise.
9673 */
9674 drm_irq_uninstall(dev);
9675 cancel_work_sync(&dev_priv->hotplug_work);
9676 /*
9677 * Due to the hpd irq storm handling the hotplug work can re-arm the
9678 * poll handlers. Hence disable polling after hpd handling is shut down.
9679 */
9680 drm_kms_helper_poll_fini(dev);
9681
9682 mutex_lock(&dev->struct_mutex);
9683
9684 intel_unregister_dsm_handler();
9685
9686 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9687 /* Skip inactive CRTCs */
9688 if (!crtc->fb)
9689 continue;
9690
9691 intel_crtc = to_intel_crtc(crtc);
9692 intel_increase_pllclock(crtc);
9693 }
9694
9695 intel_disable_fbc(dev);
9696
9697 intel_disable_gt_powersave(dev);
9698
9699 ironlake_teardown_rc6(dev);
9700
9701 mutex_unlock(&dev->struct_mutex);
9702
9703 /* flush any delayed tasks or pending work */
9704 flush_scheduled_work();
9705
9706 /* destroy backlight, if any, before the connectors */
9707 intel_panel_destroy_backlight(dev);
9708
9709 drm_mode_config_cleanup(dev);
9710
9711 intel_cleanup_overlay(dev);
9712 }
9713
9714 /*
9715 * Return which encoder is currently attached for connector.
9716 */
9717 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9718 {
9719 return &intel_attached_encoder(connector)->base;
9720 }
9721
9722 void intel_connector_attach_encoder(struct intel_connector *connector,
9723 struct intel_encoder *encoder)
9724 {
9725 connector->encoder = encoder;
9726 drm_mode_connector_attach_encoder(&connector->base,
9727 &encoder->base);
9728 }
9729
9730 /*
9731 * set vga decode state - true == enable VGA decode
9732 */
9733 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9734 {
9735 struct drm_i915_private *dev_priv = dev->dev_private;
9736 u16 gmch_ctrl;
9737
9738 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9739 if (state)
9740 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9741 else
9742 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9743 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9744 return 0;
9745 }
9746
9747 #ifdef CONFIG_DEBUG_FS
9748 #include <linux/seq_file.h>
9749
9750 struct intel_display_error_state {
9751
9752 u32 power_well_driver;
9753
9754 struct intel_cursor_error_state {
9755 u32 control;
9756 u32 position;
9757 u32 base;
9758 u32 size;
9759 } cursor[I915_MAX_PIPES];
9760
9761 struct intel_pipe_error_state {
9762 enum transcoder cpu_transcoder;
9763 u32 conf;
9764 u32 source;
9765
9766 u32 htotal;
9767 u32 hblank;
9768 u32 hsync;
9769 u32 vtotal;
9770 u32 vblank;
9771 u32 vsync;
9772 } pipe[I915_MAX_PIPES];
9773
9774 struct intel_plane_error_state {
9775 u32 control;
9776 u32 stride;
9777 u32 size;
9778 u32 pos;
9779 u32 addr;
9780 u32 surface;
9781 u32 tile_offset;
9782 } plane[I915_MAX_PIPES];
9783 };
9784
9785 struct intel_display_error_state *
9786 intel_display_capture_error_state(struct drm_device *dev)
9787 {
9788 drm_i915_private_t *dev_priv = dev->dev_private;
9789 struct intel_display_error_state *error;
9790 enum transcoder cpu_transcoder;
9791 int i;
9792
9793 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9794 if (error == NULL)
9795 return NULL;
9796
9797 if (HAS_POWER_WELL(dev))
9798 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9799
9800 for_each_pipe(i) {
9801 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9802 error->pipe[i].cpu_transcoder = cpu_transcoder;
9803
9804 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9805 error->cursor[i].control = I915_READ(CURCNTR(i));
9806 error->cursor[i].position = I915_READ(CURPOS(i));
9807 error->cursor[i].base = I915_READ(CURBASE(i));
9808 } else {
9809 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9810 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9811 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9812 }
9813
9814 error->plane[i].control = I915_READ(DSPCNTR(i));
9815 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9816 if (INTEL_INFO(dev)->gen <= 3) {
9817 error->plane[i].size = I915_READ(DSPSIZE(i));
9818 error->plane[i].pos = I915_READ(DSPPOS(i));
9819 }
9820 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9821 error->plane[i].addr = I915_READ(DSPADDR(i));
9822 if (INTEL_INFO(dev)->gen >= 4) {
9823 error->plane[i].surface = I915_READ(DSPSURF(i));
9824 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9825 }
9826
9827 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9828 error->pipe[i].source = I915_READ(PIPESRC(i));
9829 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9830 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9831 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9832 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9833 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9834 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9835 }
9836
9837 /* In the code above we read the registers without checking if the power
9838 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9839 * prevent the next I915_WRITE from detecting it and printing an error
9840 * message. */
9841 if (HAS_POWER_WELL(dev))
9842 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9843
9844 return error;
9845 }
9846
9847 void
9848 intel_display_print_error_state(struct seq_file *m,
9849 struct drm_device *dev,
9850 struct intel_display_error_state *error)
9851 {
9852 int i;
9853
9854 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9855 if (HAS_POWER_WELL(dev))
9856 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9857 error->power_well_driver);
9858 for_each_pipe(i) {
9859 seq_printf(m, "Pipe [%d]:\n", i);
9860 seq_printf(m, " CPU transcoder: %c\n",
9861 transcoder_name(error->pipe[i].cpu_transcoder));
9862 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9863 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9864 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9865 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9866 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9867 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9868 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9869 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9870
9871 seq_printf(m, "Plane [%d]:\n", i);
9872 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9873 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9874 if (INTEL_INFO(dev)->gen <= 3) {
9875 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9876 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9877 }
9878 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9879 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9880 if (INTEL_INFO(dev)->gen >= 4) {
9881 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9882 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9883 }
9884
9885 seq_printf(m, "Cursor [%d]:\n", i);
9886 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9887 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9888 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9889 }
9890 }
9891 #endif
Linux kernel - Deliverables
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