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drm/i915: correctly program the VSYNCSHIFT register
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
61 } intel_clock_t;
62
63 typedef struct {
64 int min, max;
65 } intel_range_t;
66
67 typedef struct {
68 int dot_limit;
69 int p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
88 static bool
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92
93 static bool
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
97 static bool
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
101
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
104 {
105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
110 }
111
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
123 .find_pll = intel_find_best_PLL,
124 };
125
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
137 .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
181 },
182 .find_pll = intel_g4x_find_best_PLL,
183 };
184
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
196 .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
210 },
211 .find_pll = intel_g4x_find_best_PLL,
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
225 },
226 .find_pll = intel_g4x_find_best_PLL,
227 };
228
229 static const intel_limit_t intel_limits_g4x_display_port = {
230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
239 .p2_slow = 10, .p2_fast = 10 },
240 .find_pll = intel_find_pll_g4x_dp,
241 };
242
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
246 /* Pineview's Ncounter is a ring counter */
247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
249 /* Pineview only has one combined m divider, which we treat as m2. */
250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
256 .find_pll = intel_find_best_PLL,
257 };
258
259 static const intel_limit_t intel_limits_pineview_lvds = {
260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
270 .find_pll = intel_find_best_PLL,
271 };
272
273 /* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
278 static const intel_limit_t intel_limits_ironlake_dac = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
289 .find_pll = intel_g4x_find_best_PLL,
290 };
291
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
303 .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
329 .p1 = { .min = 2, .max = 8 },
330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
332 .find_pll = intel_g4x_find_best_PLL,
333 };
334
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
343 .p1 = { .min = 2, .max = 6 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
346 .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
359 .p2_slow = 10, .p2_fast = 10 },
360 .find_pll = intel_find_pll_ironlake_dp,
361 };
362
363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
365 {
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 const intel_limit_t *limit;
369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
379 if (refclk == 100000)
380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
387 else
388 limit = &intel_limits_ironlake_dac;
389
390 return limit;
391 }
392
393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394 {
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_dual_channel_lvds;
404 else
405 /* LVDS with dual channel */
406 limit = &intel_limits_g4x_single_channel_lvds;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
409 limit = &intel_limits_g4x_hdmi;
410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
411 limit = &intel_limits_g4x_sdvo;
412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
413 limit = &intel_limits_g4x_display_port;
414 } else /* The option is for other outputs */
415 limit = &intel_limits_i9xx_sdvo;
416
417 return limit;
418 }
419
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
421 {
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
425 if (HAS_PCH_SPLIT(dev))
426 limit = intel_ironlake_limit(crtc, refclk);
427 else if (IS_G4X(dev)) {
428 limit = intel_g4x_limit(crtc);
429 } else if (IS_PINEVIEW(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_pineview_lvds;
432 else
433 limit = &intel_limits_pineview_sdvo;
434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
441 limit = &intel_limits_i8xx_lvds;
442 else
443 limit = &intel_limits_i8xx_dvo;
444 }
445 return limit;
446 }
447
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk, intel_clock_t *clock)
450 {
451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455 }
456
457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458 {
459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
461 return;
462 }
463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467 }
468
469 /**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
473 {
474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
483 }
484
485 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
486 /**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
491 static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
494 {
495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
496 INTELPllInvalid("p1 out of range\n");
497 if (clock->p < limit->p.min || limit->p.max < clock->p)
498 INTELPllInvalid("p out of range\n");
499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
500 INTELPllInvalid("m2 out of range\n");
501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
502 INTELPllInvalid("m1 out of range\n");
503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504 INTELPllInvalid("m1 <= m2\n");
505 if (clock->m < limit->m.min || limit->m.max < clock->m)
506 INTELPllInvalid("m out of range\n");
507 if (clock->n < limit->n.min || limit->n.max < clock->n)
508 INTELPllInvalid("n out of range\n");
509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
510 INTELPllInvalid("vco out of range\n");
511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515 INTELPllInvalid("dot out of range\n");
516
517 return true;
518 }
519
520 static bool
521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
524
525 {
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
529 int err = target;
530
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532 (I915_READ(LVDS)) != 0) {
533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
551 memset(best_clock, 0, sizeof(*best_clock));
552
553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
564 int this_err;
565
566 intel_clock(dev, refclk, &clock);
567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
569 continue;
570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585 }
586
587 static bool
588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
591 {
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
602 int lvds_reg;
603
604 if (HAS_PCH_SPLIT(dev))
605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
622 /* based on hardware requirement, prefer smaller n to precision */
623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624 /* based on hardware requirement, prefere larger m1,m2 */
625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
633 intel_clock(dev, refclk, &clock);
634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
636 continue;
637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
640
641 this_err = abs(clock.dot - target);
642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
652 return found;
653 }
654
655 static bool
656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
659 {
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
662
663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679 }
680
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
682 static bool
683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
686 {
687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
707 }
708
709 /**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
718 {
719 struct drm_i915_private *dev_priv = dev->dev_private;
720 int pipestat_reg = PIPESTAT(pipe);
721
722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
738 /* Wait for vblank interrupt bit to set */
739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
742 DRM_DEBUG_KMS("vblank wait timed out\n");
743 }
744
745 /*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
760 *
761 */
762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
763 {
764 struct drm_i915_private *dev_priv = dev->dev_private;
765
766 if (INTEL_INFO(dev)->gen >= 4) {
767 int reg = PIPECONF(pipe);
768
769 /* Wait for the Pipe State to go off */
770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
775 int reg = PIPEDSL(pipe);
776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
780 last_line = I915_READ(reg) & DSL_LINEMASK;
781 mdelay(5);
782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
787 }
788
789 static const char *state_string(bool enabled)
790 {
791 return enabled ? "on" : "off";
792 }
793
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797 {
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808 }
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
812 /* For ILK+ */
813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815 {
816 int reg;
817 u32 val;
818 bool cur_state;
819
820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839 }
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845 {
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856 }
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862 {
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873 }
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890 }
891
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894 {
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901 }
902
903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905 {
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
909 bool locked = true;
910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
929 pipe_name(pipe));
930 }
931
932 void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
934 {
935 int reg;
936 u32 val;
937 bool cur_state;
938
939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
948 pipe_name(pipe), state_string(state), state_string(cur_state));
949 }
950
951 static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
953 {
954 int reg;
955 u32 val;
956 bool cur_state;
957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
964 }
965
966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971 {
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
976 /* Planes are fixed to pipes on ILK+ */
977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
983 return;
984 }
985
986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
995 }
996 }
997
998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999 {
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011 {
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044 {
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060 {
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076 {
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, int reg, u32 port_sel)
1091 {
1092 u32 val = I915_READ(reg);
1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095 reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100 {
1101 u32 val = I915_READ(reg);
1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104 reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109 {
1110 int reg;
1111 u32 val;
1112
1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
1121 pipe_name(pipe));
1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127 pipe_name(pipe));
1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199 }
1200
1201 /**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211 {
1212 int reg;
1213 u32 val;
1214
1215 if (pipe > 1)
1216 return;
1217
1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 int reg;
1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239 if (pipe > 1)
1240 return;
1241
1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 int reg;
1269 u32 val;
1270
1271 /* PCH only available on ILK+ */
1272 BUG_ON(dev_priv->info->gen < 5);
1273
1274 /* Make sure PCH DPLL is enabled */
1275 assert_pch_pll_enabled(dev_priv, pipe);
1276
1277 /* FDI must be feeding us bits for PCH ports */
1278 assert_fdi_tx_enabled(dev_priv, pipe);
1279 assert_fdi_rx_enabled(dev_priv, pipe);
1280
1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
1283
1284 if (HAS_PCH_IBX(dev_priv->dev)) {
1285 /*
1286 * make the BPC in transcoder be consistent with
1287 * that in pipeconf reg.
1288 */
1289 val &= ~PIPE_BPC_MASK;
1290 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1291 }
1292 I915_WRITE(reg, val | TRANS_ENABLE);
1293 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1294 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1295 }
1296
1297 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299 {
1300 int reg;
1301 u32 val;
1302
1303 /* FDI relies on the transcoder */
1304 assert_fdi_tx_disabled(dev_priv, pipe);
1305 assert_fdi_rx_disabled(dev_priv, pipe);
1306
1307 /* Ports must be off as well */
1308 assert_pch_ports_disabled(dev_priv, pipe);
1309
1310 reg = TRANSCONF(pipe);
1311 val = I915_READ(reg);
1312 val &= ~TRANS_ENABLE;
1313 I915_WRITE(reg, val);
1314 /* wait for PCH transcoder off, transcoder state */
1315 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1316 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1317 }
1318
1319 /**
1320 * intel_enable_pipe - enable a pipe, asserting requirements
1321 * @dev_priv: i915 private structure
1322 * @pipe: pipe to enable
1323 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1324 *
1325 * Enable @pipe, making sure that various hardware specific requirements
1326 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1327 *
1328 * @pipe should be %PIPE_A or %PIPE_B.
1329 *
1330 * Will wait until the pipe is actually running (i.e. first vblank) before
1331 * returning.
1332 */
1333 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1334 bool pch_port)
1335 {
1336 int reg;
1337 u32 val;
1338
1339 /*
1340 * A pipe without a PLL won't actually be able to drive bits from
1341 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1342 * need the check.
1343 */
1344 if (!HAS_PCH_SPLIT(dev_priv->dev))
1345 assert_pll_enabled(dev_priv, pipe);
1346 else {
1347 if (pch_port) {
1348 /* if driving the PCH, we need FDI enabled */
1349 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1350 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1351 }
1352 /* FIXME: assert CPU port conditions for SNB+ */
1353 }
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
1357 if (val & PIPECONF_ENABLE)
1358 return;
1359
1360 I915_WRITE(reg, val | PIPECONF_ENABLE);
1361 intel_wait_for_vblank(dev_priv->dev, pipe);
1362 }
1363
1364 /**
1365 * intel_disable_pipe - disable a pipe, asserting requirements
1366 * @dev_priv: i915 private structure
1367 * @pipe: pipe to disable
1368 *
1369 * Disable @pipe, making sure that various hardware specific requirements
1370 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1371 *
1372 * @pipe should be %PIPE_A or %PIPE_B.
1373 *
1374 * Will wait until the pipe has shut down before returning.
1375 */
1376 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1377 enum pipe pipe)
1378 {
1379 int reg;
1380 u32 val;
1381
1382 /*
1383 * Make sure planes won't keep trying to pump pixels to us,
1384 * or we might hang the display.
1385 */
1386 assert_planes_disabled(dev_priv, pipe);
1387
1388 /* Don't disable pipe A or pipe A PLLs if needed */
1389 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1390 return;
1391
1392 reg = PIPECONF(pipe);
1393 val = I915_READ(reg);
1394 if ((val & PIPECONF_ENABLE) == 0)
1395 return;
1396
1397 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1398 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1399 }
1400
1401 /*
1402 * Plane regs are double buffered, going from enabled->disabled needs a
1403 * trigger in order to latch. The display address reg provides this.
1404 */
1405 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1406 enum plane plane)
1407 {
1408 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1409 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1410 }
1411
1412 /**
1413 * intel_enable_plane - enable a display plane on a given pipe
1414 * @dev_priv: i915 private structure
1415 * @plane: plane to enable
1416 * @pipe: pipe being fed
1417 *
1418 * Enable @plane on @pipe, making sure that @pipe is running first.
1419 */
1420 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1421 enum plane plane, enum pipe pipe)
1422 {
1423 int reg;
1424 u32 val;
1425
1426 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1427 assert_pipe_enabled(dev_priv, pipe);
1428
1429 reg = DSPCNTR(plane);
1430 val = I915_READ(reg);
1431 if (val & DISPLAY_PLANE_ENABLE)
1432 return;
1433
1434 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1435 intel_flush_display_plane(dev_priv, plane);
1436 intel_wait_for_vblank(dev_priv->dev, pipe);
1437 }
1438
1439 /**
1440 * intel_disable_plane - disable a display plane
1441 * @dev_priv: i915 private structure
1442 * @plane: plane to disable
1443 * @pipe: pipe consuming the data
1444 *
1445 * Disable @plane; should be an independent operation.
1446 */
1447 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1448 enum plane plane, enum pipe pipe)
1449 {
1450 int reg;
1451 u32 val;
1452
1453 reg = DSPCNTR(plane);
1454 val = I915_READ(reg);
1455 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1456 return;
1457
1458 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1459 intel_flush_display_plane(dev_priv, plane);
1460 intel_wait_for_vblank(dev_priv->dev, pipe);
1461 }
1462
1463 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, int reg, u32 port_sel)
1465 {
1466 u32 val = I915_READ(reg);
1467 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1468 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1469 I915_WRITE(reg, val & ~DP_PORT_EN);
1470 }
1471 }
1472
1473 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, int reg)
1475 {
1476 u32 val = I915_READ(reg);
1477 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1478 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1479 reg, pipe);
1480 I915_WRITE(reg, val & ~PORT_ENABLE);
1481 }
1482 }
1483
1484 /* Disable any ports connected to this transcoder */
1485 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487 {
1488 u32 reg, val;
1489
1490 val = I915_READ(PCH_PP_CONTROL);
1491 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1492
1493 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1494 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1495 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1496
1497 reg = PCH_ADPA;
1498 val = I915_READ(reg);
1499 if (adpa_pipe_enabled(dev_priv, val, pipe))
1500 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1501
1502 reg = PCH_LVDS;
1503 val = I915_READ(reg);
1504 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1505 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1506 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1507 POSTING_READ(reg);
1508 udelay(100);
1509 }
1510
1511 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1512 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1513 disable_pch_hdmi(dev_priv, pipe, HDMID);
1514 }
1515
1516 static void i8xx_disable_fbc(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 u32 fbc_ctl;
1520
1521 /* Disable compression */
1522 fbc_ctl = I915_READ(FBC_CONTROL);
1523 if ((fbc_ctl & FBC_CTL_EN) == 0)
1524 return;
1525
1526 fbc_ctl &= ~FBC_CTL_EN;
1527 I915_WRITE(FBC_CONTROL, fbc_ctl);
1528
1529 /* Wait for compressing bit to clear */
1530 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1531 DRM_DEBUG_KMS("FBC idle timed out\n");
1532 return;
1533 }
1534
1535 DRM_DEBUG_KMS("disabled FBC\n");
1536 }
1537
1538 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1539 {
1540 struct drm_device *dev = crtc->dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_framebuffer *fb = crtc->fb;
1543 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1544 struct drm_i915_gem_object *obj = intel_fb->obj;
1545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1546 int cfb_pitch;
1547 int plane, i;
1548 u32 fbc_ctl, fbc_ctl2;
1549
1550 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1551 if (fb->pitches[0] < cfb_pitch)
1552 cfb_pitch = fb->pitches[0];
1553
1554 /* FBC_CTL wants 64B units */
1555 cfb_pitch = (cfb_pitch / 64) - 1;
1556 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1557
1558 /* Clear old tags */
1559 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1560 I915_WRITE(FBC_TAG + (i * 4), 0);
1561
1562 /* Set it up... */
1563 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1564 fbc_ctl2 |= plane;
1565 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1566 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1567
1568 /* enable it... */
1569 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1570 if (IS_I945GM(dev))
1571 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1572 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1573 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1574 fbc_ctl |= obj->fence_reg;
1575 I915_WRITE(FBC_CONTROL, fbc_ctl);
1576
1577 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1578 cfb_pitch, crtc->y, intel_crtc->plane);
1579 }
1580
1581 static bool i8xx_fbc_enabled(struct drm_device *dev)
1582 {
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1586 }
1587
1588 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1589 {
1590 struct drm_device *dev = crtc->dev;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592 struct drm_framebuffer *fb = crtc->fb;
1593 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1594 struct drm_i915_gem_object *obj = intel_fb->obj;
1595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1596 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1597 unsigned long stall_watermark = 200;
1598 u32 dpfc_ctl;
1599
1600 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1601 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1602 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1603
1604 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1605 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1606 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1607 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1608
1609 /* enable it... */
1610 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1611
1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613 }
1614
1615 static void g4x_disable_fbc(struct drm_device *dev)
1616 {
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(DPFC_CONTROL);
1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1625
1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
1628 }
1629
1630 static bool g4x_fbc_enabled(struct drm_device *dev)
1631 {
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1635 }
1636
1637 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1638 {
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640 u32 blt_ecoskpd;
1641
1642 /* Make sure blitter notifies FBC of writes */
1643 gen6_gt_force_wake_get(dev_priv);
1644 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1645 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1646 GEN6_BLITTER_LOCK_SHIFT;
1647 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1648 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1649 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1650 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1651 GEN6_BLITTER_LOCK_SHIFT);
1652 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1653 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1654 gen6_gt_force_wake_put(dev_priv);
1655 }
1656
1657 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1658 {
1659 struct drm_device *dev = crtc->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 struct drm_framebuffer *fb = crtc->fb;
1662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1663 struct drm_i915_gem_object *obj = intel_fb->obj;
1664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1665 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1666 unsigned long stall_watermark = 200;
1667 u32 dpfc_ctl;
1668
1669 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1670 dpfc_ctl &= DPFC_RESERVED;
1671 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1672 /* Set persistent mode for front-buffer rendering, ala X. */
1673 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1674 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1675 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1676
1677 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1678 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1679 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1680 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1681 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1682 /* enable it... */
1683 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1684
1685 if (IS_GEN6(dev)) {
1686 I915_WRITE(SNB_DPFC_CTL_SA,
1687 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1688 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1689 sandybridge_blit_fbc_update(dev);
1690 }
1691
1692 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1693 }
1694
1695 static void ironlake_disable_fbc(struct drm_device *dev)
1696 {
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 u32 dpfc_ctl;
1699
1700 /* Disable compression */
1701 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1702 if (dpfc_ctl & DPFC_CTL_EN) {
1703 dpfc_ctl &= ~DPFC_CTL_EN;
1704 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1705
1706 DRM_DEBUG_KMS("disabled FBC\n");
1707 }
1708 }
1709
1710 static bool ironlake_fbc_enabled(struct drm_device *dev)
1711 {
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713
1714 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1715 }
1716
1717 bool intel_fbc_enabled(struct drm_device *dev)
1718 {
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
1721 if (!dev_priv->display.fbc_enabled)
1722 return false;
1723
1724 return dev_priv->display.fbc_enabled(dev);
1725 }
1726
1727 static void intel_fbc_work_fn(struct work_struct *__work)
1728 {
1729 struct intel_fbc_work *work =
1730 container_of(to_delayed_work(__work),
1731 struct intel_fbc_work, work);
1732 struct drm_device *dev = work->crtc->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734
1735 mutex_lock(&dev->struct_mutex);
1736 if (work == dev_priv->fbc_work) {
1737 /* Double check that we haven't switched fb without cancelling
1738 * the prior work.
1739 */
1740 if (work->crtc->fb == work->fb) {
1741 dev_priv->display.enable_fbc(work->crtc,
1742 work->interval);
1743
1744 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1745 dev_priv->cfb_fb = work->crtc->fb->base.id;
1746 dev_priv->cfb_y = work->crtc->y;
1747 }
1748
1749 dev_priv->fbc_work = NULL;
1750 }
1751 mutex_unlock(&dev->struct_mutex);
1752
1753 kfree(work);
1754 }
1755
1756 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1757 {
1758 if (dev_priv->fbc_work == NULL)
1759 return;
1760
1761 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1762
1763 /* Synchronisation is provided by struct_mutex and checking of
1764 * dev_priv->fbc_work, so we can perform the cancellation
1765 * entirely asynchronously.
1766 */
1767 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1768 /* tasklet was killed before being run, clean up */
1769 kfree(dev_priv->fbc_work);
1770
1771 /* Mark the work as no longer wanted so that if it does
1772 * wake-up (because the work was already running and waiting
1773 * for our mutex), it will discover that is no longer
1774 * necessary to run.
1775 */
1776 dev_priv->fbc_work = NULL;
1777 }
1778
1779 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1780 {
1781 struct intel_fbc_work *work;
1782 struct drm_device *dev = crtc->dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784
1785 if (!dev_priv->display.enable_fbc)
1786 return;
1787
1788 intel_cancel_fbc_work(dev_priv);
1789
1790 work = kzalloc(sizeof *work, GFP_KERNEL);
1791 if (work == NULL) {
1792 dev_priv->display.enable_fbc(crtc, interval);
1793 return;
1794 }
1795
1796 work->crtc = crtc;
1797 work->fb = crtc->fb;
1798 work->interval = interval;
1799 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1800
1801 dev_priv->fbc_work = work;
1802
1803 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1804
1805 /* Delay the actual enabling to let pageflipping cease and the
1806 * display to settle before starting the compression. Note that
1807 * this delay also serves a second purpose: it allows for a
1808 * vblank to pass after disabling the FBC before we attempt
1809 * to modify the control registers.
1810 *
1811 * A more complicated solution would involve tracking vblanks
1812 * following the termination of the page-flipping sequence
1813 * and indeed performing the enable as a co-routine and not
1814 * waiting synchronously upon the vblank.
1815 */
1816 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1817 }
1818
1819 void intel_disable_fbc(struct drm_device *dev)
1820 {
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822
1823 intel_cancel_fbc_work(dev_priv);
1824
1825 if (!dev_priv->display.disable_fbc)
1826 return;
1827
1828 dev_priv->display.disable_fbc(dev);
1829 dev_priv->cfb_plane = -1;
1830 }
1831
1832 /**
1833 * intel_update_fbc - enable/disable FBC as needed
1834 * @dev: the drm_device
1835 *
1836 * Set up the framebuffer compression hardware at mode set time. We
1837 * enable it if possible:
1838 * - plane A only (on pre-965)
1839 * - no pixel mulitply/line duplication
1840 * - no alpha buffer discard
1841 * - no dual wide
1842 * - framebuffer <= 2048 in width, 1536 in height
1843 *
1844 * We can't assume that any compression will take place (worst case),
1845 * so the compressed buffer has to be the same size as the uncompressed
1846 * one. It also must reside (along with the line length buffer) in
1847 * stolen memory.
1848 *
1849 * We need to enable/disable FBC on a global basis.
1850 */
1851 static void intel_update_fbc(struct drm_device *dev)
1852 {
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854 struct drm_crtc *crtc = NULL, *tmp_crtc;
1855 struct intel_crtc *intel_crtc;
1856 struct drm_framebuffer *fb;
1857 struct intel_framebuffer *intel_fb;
1858 struct drm_i915_gem_object *obj;
1859 int enable_fbc;
1860
1861 DRM_DEBUG_KMS("\n");
1862
1863 if (!i915_powersave)
1864 return;
1865
1866 if (!I915_HAS_FBC(dev))
1867 return;
1868
1869 /*
1870 * If FBC is already on, we just have to verify that we can
1871 * keep it that way...
1872 * Need to disable if:
1873 * - more than one pipe is active
1874 * - changing FBC params (stride, fence, mode)
1875 * - new fb is too large to fit in compressed buffer
1876 * - going to an unsupported config (interlace, pixel multiply, etc.)
1877 */
1878 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1879 if (tmp_crtc->enabled && tmp_crtc->fb) {
1880 if (crtc) {
1881 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1882 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1883 goto out_disable;
1884 }
1885 crtc = tmp_crtc;
1886 }
1887 }
1888
1889 if (!crtc || crtc->fb == NULL) {
1890 DRM_DEBUG_KMS("no output, disabling\n");
1891 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1892 goto out_disable;
1893 }
1894
1895 intel_crtc = to_intel_crtc(crtc);
1896 fb = crtc->fb;
1897 intel_fb = to_intel_framebuffer(fb);
1898 obj = intel_fb->obj;
1899
1900 enable_fbc = i915_enable_fbc;
1901 if (enable_fbc < 0) {
1902 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1903 enable_fbc = 1;
1904 if (INTEL_INFO(dev)->gen <= 6)
1905 enable_fbc = 0;
1906 }
1907 if (!enable_fbc) {
1908 DRM_DEBUG_KMS("fbc disabled per module param\n");
1909 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1910 goto out_disable;
1911 }
1912 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1913 DRM_DEBUG_KMS("framebuffer too large, disabling "
1914 "compression\n");
1915 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1916 goto out_disable;
1917 }
1918 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1919 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1920 DRM_DEBUG_KMS("mode incompatible with compression, "
1921 "disabling\n");
1922 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1923 goto out_disable;
1924 }
1925 if ((crtc->mode.hdisplay > 2048) ||
1926 (crtc->mode.vdisplay > 1536)) {
1927 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1928 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1929 goto out_disable;
1930 }
1931 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1932 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1933 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1934 goto out_disable;
1935 }
1936
1937 /* The use of a CPU fence is mandatory in order to detect writes
1938 * by the CPU to the scanout and trigger updates to the FBC.
1939 */
1940 if (obj->tiling_mode != I915_TILING_X ||
1941 obj->fence_reg == I915_FENCE_REG_NONE) {
1942 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1943 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1944 goto out_disable;
1945 }
1946
1947 /* If the kernel debugger is active, always disable compression */
1948 if (in_dbg_master())
1949 goto out_disable;
1950
1951 /* If the scanout has not changed, don't modify the FBC settings.
1952 * Note that we make the fundamental assumption that the fb->obj
1953 * cannot be unpinned (and have its GTT offset and fence revoked)
1954 * without first being decoupled from the scanout and FBC disabled.
1955 */
1956 if (dev_priv->cfb_plane == intel_crtc->plane &&
1957 dev_priv->cfb_fb == fb->base.id &&
1958 dev_priv->cfb_y == crtc->y)
1959 return;
1960
1961 if (intel_fbc_enabled(dev)) {
1962 /* We update FBC along two paths, after changing fb/crtc
1963 * configuration (modeswitching) and after page-flipping
1964 * finishes. For the latter, we know that not only did
1965 * we disable the FBC at the start of the page-flip
1966 * sequence, but also more than one vblank has passed.
1967 *
1968 * For the former case of modeswitching, it is possible
1969 * to switch between two FBC valid configurations
1970 * instantaneously so we do need to disable the FBC
1971 * before we can modify its control registers. We also
1972 * have to wait for the next vblank for that to take
1973 * effect. However, since we delay enabling FBC we can
1974 * assume that a vblank has passed since disabling and
1975 * that we can safely alter the registers in the deferred
1976 * callback.
1977 *
1978 * In the scenario that we go from a valid to invalid
1979 * and then back to valid FBC configuration we have
1980 * no strict enforcement that a vblank occurred since
1981 * disabling the FBC. However, along all current pipe
1982 * disabling paths we do need to wait for a vblank at
1983 * some point. And we wait before enabling FBC anyway.
1984 */
1985 DRM_DEBUG_KMS("disabling active FBC for update\n");
1986 intel_disable_fbc(dev);
1987 }
1988
1989 intel_enable_fbc(crtc, 500);
1990 return;
1991
1992 out_disable:
1993 /* Multiple disables should be harmless */
1994 if (intel_fbc_enabled(dev)) {
1995 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1996 intel_disable_fbc(dev);
1997 }
1998 }
1999
2000 int
2001 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2002 struct drm_i915_gem_object *obj,
2003 struct intel_ring_buffer *pipelined)
2004 {
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 u32 alignment;
2007 int ret;
2008
2009 switch (obj->tiling_mode) {
2010 case I915_TILING_NONE:
2011 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2012 alignment = 128 * 1024;
2013 else if (INTEL_INFO(dev)->gen >= 4)
2014 alignment = 4 * 1024;
2015 else
2016 alignment = 64 * 1024;
2017 break;
2018 case I915_TILING_X:
2019 /* pin() will align the object as required by fence */
2020 alignment = 0;
2021 break;
2022 case I915_TILING_Y:
2023 /* FIXME: Is this true? */
2024 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2025 return -EINVAL;
2026 default:
2027 BUG();
2028 }
2029
2030 dev_priv->mm.interruptible = false;
2031 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2032 if (ret)
2033 goto err_interruptible;
2034
2035 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2036 * fence, whereas 965+ only requires a fence if using
2037 * framebuffer compression. For simplicity, we always install
2038 * a fence as the cost is not that onerous.
2039 */
2040 if (obj->tiling_mode != I915_TILING_NONE) {
2041 ret = i915_gem_object_get_fence(obj, pipelined);
2042 if (ret)
2043 goto err_unpin;
2044
2045 i915_gem_object_pin_fence(obj);
2046 }
2047
2048 dev_priv->mm.interruptible = true;
2049 return 0;
2050
2051 err_unpin:
2052 i915_gem_object_unpin(obj);
2053 err_interruptible:
2054 dev_priv->mm.interruptible = true;
2055 return ret;
2056 }
2057
2058 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2059 {
2060 i915_gem_object_unpin_fence(obj);
2061 i915_gem_object_unpin(obj);
2062 }
2063
2064 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2065 int x, int y)
2066 {
2067 struct drm_device *dev = crtc->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2070 struct intel_framebuffer *intel_fb;
2071 struct drm_i915_gem_object *obj;
2072 int plane = intel_crtc->plane;
2073 unsigned long Start, Offset;
2074 u32 dspcntr;
2075 u32 reg;
2076
2077 switch (plane) {
2078 case 0:
2079 case 1:
2080 break;
2081 default:
2082 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2083 return -EINVAL;
2084 }
2085
2086 intel_fb = to_intel_framebuffer(fb);
2087 obj = intel_fb->obj;
2088
2089 reg = DSPCNTR(plane);
2090 dspcntr = I915_READ(reg);
2091 /* Mask out pixel format bits in case we change it */
2092 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2093 switch (fb->bits_per_pixel) {
2094 case 8:
2095 dspcntr |= DISPPLANE_8BPP;
2096 break;
2097 case 16:
2098 if (fb->depth == 15)
2099 dspcntr |= DISPPLANE_15_16BPP;
2100 else
2101 dspcntr |= DISPPLANE_16BPP;
2102 break;
2103 case 24:
2104 case 32:
2105 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2106 break;
2107 default:
2108 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2109 return -EINVAL;
2110 }
2111 if (INTEL_INFO(dev)->gen >= 4) {
2112 if (obj->tiling_mode != I915_TILING_NONE)
2113 dspcntr |= DISPPLANE_TILED;
2114 else
2115 dspcntr &= ~DISPPLANE_TILED;
2116 }
2117
2118 I915_WRITE(reg, dspcntr);
2119
2120 Start = obj->gtt_offset;
2121 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2122
2123 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2124 Start, Offset, x, y, fb->pitches[0]);
2125 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2126 if (INTEL_INFO(dev)->gen >= 4) {
2127 I915_WRITE(DSPSURF(plane), Start);
2128 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129 I915_WRITE(DSPADDR(plane), Offset);
2130 } else
2131 I915_WRITE(DSPADDR(plane), Start + Offset);
2132 POSTING_READ(reg);
2133
2134 return 0;
2135 }
2136
2137 static int ironlake_update_plane(struct drm_crtc *crtc,
2138 struct drm_framebuffer *fb, int x, int y)
2139 {
2140 struct drm_device *dev = crtc->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143 struct intel_framebuffer *intel_fb;
2144 struct drm_i915_gem_object *obj;
2145 int plane = intel_crtc->plane;
2146 unsigned long Start, Offset;
2147 u32 dspcntr;
2148 u32 reg;
2149
2150 switch (plane) {
2151 case 0:
2152 case 1:
2153 case 2:
2154 break;
2155 default:
2156 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2157 return -EINVAL;
2158 }
2159
2160 intel_fb = to_intel_framebuffer(fb);
2161 obj = intel_fb->obj;
2162
2163 reg = DSPCNTR(plane);
2164 dspcntr = I915_READ(reg);
2165 /* Mask out pixel format bits in case we change it */
2166 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2167 switch (fb->bits_per_pixel) {
2168 case 8:
2169 dspcntr |= DISPPLANE_8BPP;
2170 break;
2171 case 16:
2172 if (fb->depth != 16)
2173 return -EINVAL;
2174
2175 dspcntr |= DISPPLANE_16BPP;
2176 break;
2177 case 24:
2178 case 32:
2179 if (fb->depth == 24)
2180 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2181 else if (fb->depth == 30)
2182 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2183 else
2184 return -EINVAL;
2185 break;
2186 default:
2187 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2188 return -EINVAL;
2189 }
2190
2191 if (obj->tiling_mode != I915_TILING_NONE)
2192 dspcntr |= DISPPLANE_TILED;
2193 else
2194 dspcntr &= ~DISPPLANE_TILED;
2195
2196 /* must disable */
2197 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2198
2199 I915_WRITE(reg, dspcntr);
2200
2201 Start = obj->gtt_offset;
2202 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2203
2204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205 Start, Offset, x, y, fb->pitches[0]);
2206 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2207 I915_WRITE(DSPSURF(plane), Start);
2208 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2209 I915_WRITE(DSPADDR(plane), Offset);
2210 POSTING_READ(reg);
2211
2212 return 0;
2213 }
2214
2215 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2216 static int
2217 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2218 int x, int y, enum mode_set_atomic state)
2219 {
2220 struct drm_device *dev = crtc->dev;
2221 struct drm_i915_private *dev_priv = dev->dev_private;
2222 int ret;
2223
2224 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2225 if (ret)
2226 return ret;
2227
2228 intel_update_fbc(dev);
2229 intel_increase_pllclock(crtc);
2230
2231 return 0;
2232 }
2233
2234 static int
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236 struct drm_framebuffer *old_fb)
2237 {
2238 struct drm_device *dev = crtc->dev;
2239 struct drm_i915_master_private *master_priv;
2240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241 int ret;
2242
2243 /* no fb bound */
2244 if (!crtc->fb) {
2245 DRM_ERROR("No FB bound\n");
2246 return 0;
2247 }
2248
2249 switch (intel_crtc->plane) {
2250 case 0:
2251 case 1:
2252 break;
2253 case 2:
2254 if (IS_IVYBRIDGE(dev))
2255 break;
2256 /* fall through otherwise */
2257 default:
2258 DRM_ERROR("no plane for crtc\n");
2259 return -EINVAL;
2260 }
2261
2262 mutex_lock(&dev->struct_mutex);
2263 ret = intel_pin_and_fence_fb_obj(dev,
2264 to_intel_framebuffer(crtc->fb)->obj,
2265 NULL);
2266 if (ret != 0) {
2267 mutex_unlock(&dev->struct_mutex);
2268 DRM_ERROR("pin & fence failed\n");
2269 return ret;
2270 }
2271
2272 if (old_fb) {
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2275
2276 wait_event(dev_priv->pending_flip_queue,
2277 atomic_read(&dev_priv->mm.wedged) ||
2278 atomic_read(&obj->pending_flip) == 0);
2279
2280 /* Big Hammer, we also need to ensure that any pending
2281 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2282 * current scanout is retired before unpinning the old
2283 * framebuffer.
2284 *
2285 * This should only fail upon a hung GPU, in which case we
2286 * can safely continue.
2287 */
2288 ret = i915_gem_object_finish_gpu(obj);
2289 (void) ret;
2290 }
2291
2292 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2293 LEAVE_ATOMIC_MODE_SET);
2294 if (ret) {
2295 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2296 mutex_unlock(&dev->struct_mutex);
2297 DRM_ERROR("failed to update base address\n");
2298 return ret;
2299 }
2300
2301 if (old_fb) {
2302 intel_wait_for_vblank(dev, intel_crtc->pipe);
2303 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2304 }
2305
2306 mutex_unlock(&dev->struct_mutex);
2307
2308 if (!dev->primary->master)
2309 return 0;
2310
2311 master_priv = dev->primary->master->driver_priv;
2312 if (!master_priv->sarea_priv)
2313 return 0;
2314
2315 if (intel_crtc->pipe) {
2316 master_priv->sarea_priv->pipeB_x = x;
2317 master_priv->sarea_priv->pipeB_y = y;
2318 } else {
2319 master_priv->sarea_priv->pipeA_x = x;
2320 master_priv->sarea_priv->pipeA_y = y;
2321 }
2322
2323 return 0;
2324 }
2325
2326 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2327 {
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 u32 dpa_ctl;
2331
2332 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2333 dpa_ctl = I915_READ(DP_A);
2334 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2335
2336 if (clock < 200000) {
2337 u32 temp;
2338 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2339 /* workaround for 160Mhz:
2340 1) program 0x4600c bits 15:0 = 0x8124
2341 2) program 0x46010 bit 0 = 1
2342 3) program 0x46034 bit 24 = 1
2343 4) program 0x64000 bit 14 = 1
2344 */
2345 temp = I915_READ(0x4600c);
2346 temp &= 0xffff0000;
2347 I915_WRITE(0x4600c, temp | 0x8124);
2348
2349 temp = I915_READ(0x46010);
2350 I915_WRITE(0x46010, temp | 1);
2351
2352 temp = I915_READ(0x46034);
2353 I915_WRITE(0x46034, temp | (1 << 24));
2354 } else {
2355 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2356 }
2357 I915_WRITE(DP_A, dpa_ctl);
2358
2359 POSTING_READ(DP_A);
2360 udelay(500);
2361 }
2362
2363 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2364 {
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 u32 reg, temp;
2370
2371 /* enable normal train */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 if (IS_IVYBRIDGE(dev)) {
2375 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2376 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2377 } else {
2378 temp &= ~FDI_LINK_TRAIN_NONE;
2379 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2380 }
2381 I915_WRITE(reg, temp);
2382
2383 reg = FDI_RX_CTL(pipe);
2384 temp = I915_READ(reg);
2385 if (HAS_PCH_CPT(dev)) {
2386 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2387 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2388 } else {
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_NONE;
2391 }
2392 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2393
2394 /* wait one idle pattern time */
2395 POSTING_READ(reg);
2396 udelay(1000);
2397
2398 /* IVB wants error correction enabled */
2399 if (IS_IVYBRIDGE(dev))
2400 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2401 FDI_FE_ERRC_ENABLE);
2402 }
2403
2404 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2405 {
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 u32 flags = I915_READ(SOUTH_CHICKEN1);
2408
2409 flags |= FDI_PHASE_SYNC_OVR(pipe);
2410 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2411 flags |= FDI_PHASE_SYNC_EN(pipe);
2412 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2413 POSTING_READ(SOUTH_CHICKEN1);
2414 }
2415
2416 /* The FDI link training functions for ILK/Ibexpeak. */
2417 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2418 {
2419 struct drm_device *dev = crtc->dev;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422 int pipe = intel_crtc->pipe;
2423 int plane = intel_crtc->plane;
2424 u32 reg, temp, tries;
2425
2426 /* FDI needs bits from pipe & plane first */
2427 assert_pipe_enabled(dev_priv, pipe);
2428 assert_plane_enabled(dev_priv, plane);
2429
2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
2436 I915_WRITE(reg, temp);
2437 I915_READ(reg);
2438 udelay(150);
2439
2440 /* enable CPU FDI TX and PCH FDI RX */
2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
2443 temp &= ~(7 << 19);
2444 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2448
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_1;
2453 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2454
2455 POSTING_READ(reg);
2456 udelay(150);
2457
2458 /* Ironlake workaround, enable clock pointer after FDI enable*/
2459 if (HAS_PCH_IBX(dev)) {
2460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2462 FDI_RX_PHASE_SYNC_POINTER_EN);
2463 }
2464
2465 reg = FDI_RX_IIR(pipe);
2466 for (tries = 0; tries < 5; tries++) {
2467 temp = I915_READ(reg);
2468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2469
2470 if ((temp & FDI_RX_BIT_LOCK)) {
2471 DRM_DEBUG_KMS("FDI train 1 done.\n");
2472 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2473 break;
2474 }
2475 }
2476 if (tries == 5)
2477 DRM_ERROR("FDI train 1 fail!\n");
2478
2479 /* Train 2 */
2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_2;
2484 I915_WRITE(reg, temp);
2485
2486 reg = FDI_RX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_2;
2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
2493 udelay(150);
2494
2495 reg = FDI_RX_IIR(pipe);
2496 for (tries = 0; tries < 5; tries++) {
2497 temp = I915_READ(reg);
2498 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2499
2500 if (temp & FDI_RX_SYMBOL_LOCK) {
2501 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2502 DRM_DEBUG_KMS("FDI train 2 done.\n");
2503 break;
2504 }
2505 }
2506 if (tries == 5)
2507 DRM_ERROR("FDI train 2 fail!\n");
2508
2509 DRM_DEBUG_KMS("FDI train done\n");
2510
2511 }
2512
2513 static const int snb_b_fdi_train_param[] = {
2514 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2515 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2516 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2517 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2518 };
2519
2520 /* The FDI link training functions for SNB/Cougarpoint. */
2521 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2522 {
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 int pipe = intel_crtc->pipe;
2527 u32 reg, temp, i;
2528
2529 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2530 for train result */
2531 reg = FDI_RX_IMR(pipe);
2532 temp = I915_READ(reg);
2533 temp &= ~FDI_RX_SYMBOL_LOCK;
2534 temp &= ~FDI_RX_BIT_LOCK;
2535 I915_WRITE(reg, temp);
2536
2537 POSTING_READ(reg);
2538 udelay(150);
2539
2540 /* enable CPU FDI TX and PCH FDI RX */
2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~(7 << 19);
2544 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_1;
2547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2548 /* SNB-B */
2549 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2550 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2551
2552 reg = FDI_RX_CTL(pipe);
2553 temp = I915_READ(reg);
2554 if (HAS_PCH_CPT(dev)) {
2555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2557 } else {
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_1;
2560 }
2561 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2562
2563 POSTING_READ(reg);
2564 udelay(150);
2565
2566 if (HAS_PCH_CPT(dev))
2567 cpt_phase_pointer_enable(dev, pipe);
2568
2569 for (i = 0; i < 4; i++) {
2570 reg = FDI_TX_CTL(pipe);
2571 temp = I915_READ(reg);
2572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2573 temp |= snb_b_fdi_train_param[i];
2574 I915_WRITE(reg, temp);
2575
2576 POSTING_READ(reg);
2577 udelay(500);
2578
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582
2583 if (temp & FDI_RX_BIT_LOCK) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585 DRM_DEBUG_KMS("FDI train 1 done.\n");
2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2;
2597 if (IS_GEN6(dev)) {
2598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2599 /* SNB-B */
2600 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2601 }
2602 I915_WRITE(reg, temp);
2603
2604 reg = FDI_RX_CTL(pipe);
2605 temp = I915_READ(reg);
2606 if (HAS_PCH_CPT(dev)) {
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2609 } else {
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2;
2612 }
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 for (i = 0; i < 4; i++) {
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(500);
2627
2628 reg = FDI_RX_IIR(pipe);
2629 temp = I915_READ(reg);
2630 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2631
2632 if (temp & FDI_RX_SYMBOL_LOCK) {
2633 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2634 DRM_DEBUG_KMS("FDI train 2 done.\n");
2635 break;
2636 }
2637 }
2638 if (i == 4)
2639 DRM_ERROR("FDI train 2 fail!\n");
2640
2641 DRM_DEBUG_KMS("FDI train done.\n");
2642 }
2643
2644 /* Manual link training for Ivy Bridge A0 parts */
2645 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2646 {
2647 struct drm_device *dev = crtc->dev;
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650 int pipe = intel_crtc->pipe;
2651 u32 reg, temp, i;
2652
2653 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2654 for train result */
2655 reg = FDI_RX_IMR(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_RX_SYMBOL_LOCK;
2658 temp &= ~FDI_RX_BIT_LOCK;
2659 I915_WRITE(reg, temp);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
2664 /* enable CPU FDI TX and PCH FDI RX */
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~(7 << 19);
2668 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2669 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2670 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2673 temp |= FDI_COMPOSITE_SYNC;
2674 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2675
2676 reg = FDI_RX_CTL(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_LINK_TRAIN_AUTO;
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2681 temp |= FDI_COMPOSITE_SYNC;
2682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
2687 if (HAS_PCH_CPT(dev))
2688 cpt_phase_pointer_enable(dev, pipe);
2689
2690 for (i = 0; i < 4; i++) {
2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= snb_b_fdi_train_param[i];
2695 I915_WRITE(reg, temp);
2696
2697 POSTING_READ(reg);
2698 udelay(500);
2699
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done.\n");
2708 break;
2709 }
2710 }
2711 if (i == 4)
2712 DRM_ERROR("FDI train 1 fail!\n");
2713
2714 /* Train 2 */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2718 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2721 I915_WRITE(reg, temp);
2722
2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(150);
2731
2732 for (i = 0; i < 4; i++) {
2733 reg = FDI_TX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= snb_b_fdi_train_param[i];
2737 I915_WRITE(reg, temp);
2738
2739 POSTING_READ(reg);
2740 udelay(500);
2741
2742 reg = FDI_RX_IIR(pipe);
2743 temp = I915_READ(reg);
2744 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2745
2746 if (temp & FDI_RX_SYMBOL_LOCK) {
2747 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2748 DRM_DEBUG_KMS("FDI train 2 done.\n");
2749 break;
2750 }
2751 }
2752 if (i == 4)
2753 DRM_ERROR("FDI train 2 fail!\n");
2754
2755 DRM_DEBUG_KMS("FDI train done.\n");
2756 }
2757
2758 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2759 {
2760 struct drm_device *dev = crtc->dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763 int pipe = intel_crtc->pipe;
2764 u32 reg, temp;
2765
2766 /* Write the TU size bits so error detection works */
2767 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2768 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2769
2770 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2771 reg = FDI_RX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~((0x7 << 19) | (0x7 << 16));
2774 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2775 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2776 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2777
2778 POSTING_READ(reg);
2779 udelay(200);
2780
2781 /* Switch from Rawclk to PCDclk */
2782 temp = I915_READ(reg);
2783 I915_WRITE(reg, temp | FDI_PCDCLK);
2784
2785 POSTING_READ(reg);
2786 udelay(200);
2787
2788 /* Enable CPU FDI TX PLL, always on for Ironlake */
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2792 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2793
2794 POSTING_READ(reg);
2795 udelay(100);
2796 }
2797 }
2798
2799 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2800 {
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 u32 flags = I915_READ(SOUTH_CHICKEN1);
2803
2804 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2805 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2806 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2807 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2808 POSTING_READ(SOUTH_CHICKEN1);
2809 }
2810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2811 {
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 int pipe = intel_crtc->pipe;
2816 u32 reg, temp;
2817
2818 /* disable CPU FDI tx and PCH FDI rx */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2822 POSTING_READ(reg);
2823
2824 reg = FDI_RX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~(0x7 << 16);
2827 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2829
2830 POSTING_READ(reg);
2831 udelay(100);
2832
2833 /* Ironlake workaround, disable clock pointer after downing FDI */
2834 if (HAS_PCH_IBX(dev)) {
2835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2836 I915_WRITE(FDI_RX_CHICKEN(pipe),
2837 I915_READ(FDI_RX_CHICKEN(pipe) &
2838 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2839 } else if (HAS_PCH_CPT(dev)) {
2840 cpt_phase_pointer_disable(dev, pipe);
2841 }
2842
2843 /* still set train pattern 1 */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 I915_WRITE(reg, temp);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if (HAS_PCH_CPT(dev)) {
2853 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 } else {
2856 temp &= ~FDI_LINK_TRAIN_NONE;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 }
2859 /* BPC in FDI rx is consistent with that in PIPECONF */
2860 temp &= ~(0x07 << 16);
2861 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2862 I915_WRITE(reg, temp);
2863
2864 POSTING_READ(reg);
2865 udelay(100);
2866 }
2867
2868 /*
2869 * When we disable a pipe, we need to clear any pending scanline wait events
2870 * to avoid hanging the ring, which we assume we are waiting on.
2871 */
2872 static void intel_clear_scanline_wait(struct drm_device *dev)
2873 {
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 struct intel_ring_buffer *ring;
2876 u32 tmp;
2877
2878 if (IS_GEN2(dev))
2879 /* Can't break the hang on i8xx */
2880 return;
2881
2882 ring = LP_RING(dev_priv);
2883 tmp = I915_READ_CTL(ring);
2884 if (tmp & RING_WAIT)
2885 I915_WRITE_CTL(ring, tmp);
2886 }
2887
2888 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2889 {
2890 struct drm_i915_gem_object *obj;
2891 struct drm_i915_private *dev_priv;
2892
2893 if (crtc->fb == NULL)
2894 return;
2895
2896 obj = to_intel_framebuffer(crtc->fb)->obj;
2897 dev_priv = crtc->dev->dev_private;
2898 wait_event(dev_priv->pending_flip_queue,
2899 atomic_read(&obj->pending_flip) == 0);
2900 }
2901
2902 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2903 {
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_mode_config *mode_config = &dev->mode_config;
2906 struct intel_encoder *encoder;
2907
2908 /*
2909 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2910 * must be driven by its own crtc; no sharing is possible.
2911 */
2912 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2913 if (encoder->base.crtc != crtc)
2914 continue;
2915
2916 switch (encoder->type) {
2917 case INTEL_OUTPUT_EDP:
2918 if (!intel_encoder_is_pch_edp(&encoder->base))
2919 return false;
2920 continue;
2921 }
2922 }
2923
2924 return true;
2925 }
2926
2927 /*
2928 * Enable PCH resources required for PCH ports:
2929 * - PCH PLLs
2930 * - FDI training & RX/TX
2931 * - update transcoder timings
2932 * - DP transcoding bits
2933 * - transcoder
2934 */
2935 static void ironlake_pch_enable(struct drm_crtc *crtc)
2936 {
2937 struct drm_device *dev = crtc->dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2940 int pipe = intel_crtc->pipe;
2941 u32 reg, temp, transc_sel;
2942
2943 /* For PCH output, training FDI link */
2944 dev_priv->display.fdi_link_train(crtc);
2945
2946 intel_enable_pch_pll(dev_priv, pipe);
2947
2948 if (HAS_PCH_CPT(dev)) {
2949 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2950 TRANSC_DPLLB_SEL;
2951
2952 /* Be sure PCH DPLL SEL is set */
2953 temp = I915_READ(PCH_DPLL_SEL);
2954 if (pipe == 0) {
2955 temp &= ~(TRANSA_DPLLB_SEL);
2956 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2957 } else if (pipe == 1) {
2958 temp &= ~(TRANSB_DPLLB_SEL);
2959 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2960 } else if (pipe == 2) {
2961 temp &= ~(TRANSC_DPLLB_SEL);
2962 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2963 }
2964 I915_WRITE(PCH_DPLL_SEL, temp);
2965 }
2966
2967 /* set transcoder timing, panel must allow it */
2968 assert_panel_unlocked(dev_priv, pipe);
2969 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2970 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2971 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2972
2973 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2974 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2975 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2976 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2977
2978 intel_fdi_normal_train(crtc);
2979
2980 /* For PCH DP, enable TRANS_DP_CTL */
2981 if (HAS_PCH_CPT(dev) &&
2982 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2983 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2984 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2985 reg = TRANS_DP_CTL(pipe);
2986 temp = I915_READ(reg);
2987 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2988 TRANS_DP_SYNC_MASK |
2989 TRANS_DP_BPC_MASK);
2990 temp |= (TRANS_DP_OUTPUT_ENABLE |
2991 TRANS_DP_ENH_FRAMING);
2992 temp |= bpc << 9; /* same format but at 11:9 */
2993
2994 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2995 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2996 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2997 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2998
2999 switch (intel_trans_dp_port_sel(crtc)) {
3000 case PCH_DP_B:
3001 temp |= TRANS_DP_PORT_SEL_B;
3002 break;
3003 case PCH_DP_C:
3004 temp |= TRANS_DP_PORT_SEL_C;
3005 break;
3006 case PCH_DP_D:
3007 temp |= TRANS_DP_PORT_SEL_D;
3008 break;
3009 default:
3010 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3011 temp |= TRANS_DP_PORT_SEL_B;
3012 break;
3013 }
3014
3015 I915_WRITE(reg, temp);
3016 }
3017
3018 intel_enable_transcoder(dev_priv, pipe);
3019 }
3020
3021 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3022 {
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3025 u32 temp;
3026
3027 temp = I915_READ(dslreg);
3028 udelay(500);
3029 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3030 /* Without this, mode sets may fail silently on FDI */
3031 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3032 udelay(250);
3033 I915_WRITE(tc2reg, 0);
3034 if (wait_for(I915_READ(dslreg) != temp, 5))
3035 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3036 }
3037 }
3038
3039 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3040 {
3041 struct drm_device *dev = crtc->dev;
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3044 int pipe = intel_crtc->pipe;
3045 int plane = intel_crtc->plane;
3046 u32 temp;
3047 bool is_pch_port;
3048
3049 if (intel_crtc->active)
3050 return;
3051
3052 intel_crtc->active = true;
3053 intel_update_watermarks(dev);
3054
3055 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3056 temp = I915_READ(PCH_LVDS);
3057 if ((temp & LVDS_PORT_EN) == 0)
3058 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3059 }
3060
3061 is_pch_port = intel_crtc_driving_pch(crtc);
3062
3063 if (is_pch_port)
3064 ironlake_fdi_pll_enable(crtc);
3065 else
3066 ironlake_fdi_disable(crtc);
3067
3068 /* Enable panel fitting for LVDS */
3069 if (dev_priv->pch_pf_size &&
3070 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3071 /* Force use of hard-coded filter coefficients
3072 * as some pre-programmed values are broken,
3073 * e.g. x201.
3074 */
3075 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3076 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3077 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3078 }
3079
3080 /*
3081 * On ILK+ LUT must be loaded before the pipe is running but with
3082 * clocks enabled
3083 */
3084 intel_crtc_load_lut(crtc);
3085
3086 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3087 intel_enable_plane(dev_priv, plane, pipe);
3088
3089 if (is_pch_port)
3090 ironlake_pch_enable(crtc);
3091
3092 mutex_lock(&dev->struct_mutex);
3093 intel_update_fbc(dev);
3094 mutex_unlock(&dev->struct_mutex);
3095
3096 intel_crtc_update_cursor(crtc, true);
3097 }
3098
3099 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3100 {
3101 struct drm_device *dev = crtc->dev;
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104 int pipe = intel_crtc->pipe;
3105 int plane = intel_crtc->plane;
3106 u32 reg, temp;
3107
3108 if (!intel_crtc->active)
3109 return;
3110
3111 intel_crtc_wait_for_pending_flips(crtc);
3112 drm_vblank_off(dev, pipe);
3113 intel_crtc_update_cursor(crtc, false);
3114
3115 intel_disable_plane(dev_priv, plane, pipe);
3116
3117 if (dev_priv->cfb_plane == plane)
3118 intel_disable_fbc(dev);
3119
3120 intel_disable_pipe(dev_priv, pipe);
3121
3122 /* Disable PF */
3123 I915_WRITE(PF_CTL(pipe), 0);
3124 I915_WRITE(PF_WIN_SZ(pipe), 0);
3125
3126 ironlake_fdi_disable(crtc);
3127
3128 /* This is a horrible layering violation; we should be doing this in
3129 * the connector/encoder ->prepare instead, but we don't always have
3130 * enough information there about the config to know whether it will
3131 * actually be necessary or just cause undesired flicker.
3132 */
3133 intel_disable_pch_ports(dev_priv, pipe);
3134
3135 intel_disable_transcoder(dev_priv, pipe);
3136
3137 if (HAS_PCH_CPT(dev)) {
3138 /* disable TRANS_DP_CTL */
3139 reg = TRANS_DP_CTL(pipe);
3140 temp = I915_READ(reg);
3141 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3142 temp |= TRANS_DP_PORT_SEL_NONE;
3143 I915_WRITE(reg, temp);
3144
3145 /* disable DPLL_SEL */
3146 temp = I915_READ(PCH_DPLL_SEL);
3147 switch (pipe) {
3148 case 0:
3149 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3150 break;
3151 case 1:
3152 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3153 break;
3154 case 2:
3155 /* C shares PLL A or B */
3156 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3157 break;
3158 default:
3159 BUG(); /* wtf */
3160 }
3161 I915_WRITE(PCH_DPLL_SEL, temp);
3162 }
3163
3164 /* disable PCH DPLL */
3165 if (!intel_crtc->no_pll)
3166 intel_disable_pch_pll(dev_priv, pipe);
3167
3168 /* Switch from PCDclk to Rawclk */
3169 reg = FDI_RX_CTL(pipe);
3170 temp = I915_READ(reg);
3171 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3172
3173 /* Disable CPU FDI TX PLL */
3174 reg = FDI_TX_CTL(pipe);
3175 temp = I915_READ(reg);
3176 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3177
3178 POSTING_READ(reg);
3179 udelay(100);
3180
3181 reg = FDI_RX_CTL(pipe);
3182 temp = I915_READ(reg);
3183 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3184
3185 /* Wait for the clocks to turn off. */
3186 POSTING_READ(reg);
3187 udelay(100);
3188
3189 intel_crtc->active = false;
3190 intel_update_watermarks(dev);
3191
3192 mutex_lock(&dev->struct_mutex);
3193 intel_update_fbc(dev);
3194 intel_clear_scanline_wait(dev);
3195 mutex_unlock(&dev->struct_mutex);
3196 }
3197
3198 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3199 {
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201 int pipe = intel_crtc->pipe;
3202 int plane = intel_crtc->plane;
3203
3204 /* XXX: When our outputs are all unaware of DPMS modes other than off
3205 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3206 */
3207 switch (mode) {
3208 case DRM_MODE_DPMS_ON:
3209 case DRM_MODE_DPMS_STANDBY:
3210 case DRM_MODE_DPMS_SUSPEND:
3211 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3212 ironlake_crtc_enable(crtc);
3213 break;
3214
3215 case DRM_MODE_DPMS_OFF:
3216 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3217 ironlake_crtc_disable(crtc);
3218 break;
3219 }
3220 }
3221
3222 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3223 {
3224 if (!enable && intel_crtc->overlay) {
3225 struct drm_device *dev = intel_crtc->base.dev;
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227
3228 mutex_lock(&dev->struct_mutex);
3229 dev_priv->mm.interruptible = false;
3230 (void) intel_overlay_switch_off(intel_crtc->overlay);
3231 dev_priv->mm.interruptible = true;
3232 mutex_unlock(&dev->struct_mutex);
3233 }
3234
3235 /* Let userspace switch the overlay on again. In most cases userspace
3236 * has to recompute where to put it anyway.
3237 */
3238 }
3239
3240 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3241 {
3242 struct drm_device *dev = crtc->dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3245 int pipe = intel_crtc->pipe;
3246 int plane = intel_crtc->plane;
3247
3248 if (intel_crtc->active)
3249 return;
3250
3251 intel_crtc->active = true;
3252 intel_update_watermarks(dev);
3253
3254 intel_enable_pll(dev_priv, pipe);
3255 intel_enable_pipe(dev_priv, pipe, false);
3256 intel_enable_plane(dev_priv, plane, pipe);
3257
3258 intel_crtc_load_lut(crtc);
3259 intel_update_fbc(dev);
3260
3261 /* Give the overlay scaler a chance to enable if it's on this pipe */
3262 intel_crtc_dpms_overlay(intel_crtc, true);
3263 intel_crtc_update_cursor(crtc, true);
3264 }
3265
3266 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3267 {
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 int pipe = intel_crtc->pipe;
3272 int plane = intel_crtc->plane;
3273
3274 if (!intel_crtc->active)
3275 return;
3276
3277 /* Give the overlay scaler a chance to disable if it's on this pipe */
3278 intel_crtc_wait_for_pending_flips(crtc);
3279 drm_vblank_off(dev, pipe);
3280 intel_crtc_dpms_overlay(intel_crtc, false);
3281 intel_crtc_update_cursor(crtc, false);
3282
3283 if (dev_priv->cfb_plane == plane)
3284 intel_disable_fbc(dev);
3285
3286 intel_disable_plane(dev_priv, plane, pipe);
3287 intel_disable_pipe(dev_priv, pipe);
3288 intel_disable_pll(dev_priv, pipe);
3289
3290 intel_crtc->active = false;
3291 intel_update_fbc(dev);
3292 intel_update_watermarks(dev);
3293 intel_clear_scanline_wait(dev);
3294 }
3295
3296 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3297 {
3298 /* XXX: When our outputs are all unaware of DPMS modes other than off
3299 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3300 */
3301 switch (mode) {
3302 case DRM_MODE_DPMS_ON:
3303 case DRM_MODE_DPMS_STANDBY:
3304 case DRM_MODE_DPMS_SUSPEND:
3305 i9xx_crtc_enable(crtc);
3306 break;
3307 case DRM_MODE_DPMS_OFF:
3308 i9xx_crtc_disable(crtc);
3309 break;
3310 }
3311 }
3312
3313 /**
3314 * Sets the power management mode of the pipe and plane.
3315 */
3316 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3317 {
3318 struct drm_device *dev = crtc->dev;
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320 struct drm_i915_master_private *master_priv;
3321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3322 int pipe = intel_crtc->pipe;
3323 bool enabled;
3324
3325 if (intel_crtc->dpms_mode == mode)
3326 return;
3327
3328 intel_crtc->dpms_mode = mode;
3329
3330 dev_priv->display.dpms(crtc, mode);
3331
3332 if (!dev->primary->master)
3333 return;
3334
3335 master_priv = dev->primary->master->driver_priv;
3336 if (!master_priv->sarea_priv)
3337 return;
3338
3339 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3340
3341 switch (pipe) {
3342 case 0:
3343 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3344 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3345 break;
3346 case 1:
3347 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3348 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3349 break;
3350 default:
3351 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3352 break;
3353 }
3354 }
3355
3356 static void intel_crtc_disable(struct drm_crtc *crtc)
3357 {
3358 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3359 struct drm_device *dev = crtc->dev;
3360
3361 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3362 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3363 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3364
3365 if (crtc->fb) {
3366 mutex_lock(&dev->struct_mutex);
3367 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3368 mutex_unlock(&dev->struct_mutex);
3369 }
3370 }
3371
3372 /* Prepare for a mode set.
3373 *
3374 * Note we could be a lot smarter here. We need to figure out which outputs
3375 * will be enabled, which disabled (in short, how the config will changes)
3376 * and perform the minimum necessary steps to accomplish that, e.g. updating
3377 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3378 * panel fitting is in the proper state, etc.
3379 */
3380 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3381 {
3382 i9xx_crtc_disable(crtc);
3383 }
3384
3385 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3386 {
3387 i9xx_crtc_enable(crtc);
3388 }
3389
3390 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3391 {
3392 ironlake_crtc_disable(crtc);
3393 }
3394
3395 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3396 {
3397 ironlake_crtc_enable(crtc);
3398 }
3399
3400 void intel_encoder_prepare(struct drm_encoder *encoder)
3401 {
3402 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3403 /* lvds has its own version of prepare see intel_lvds_prepare */
3404 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3405 }
3406
3407 void intel_encoder_commit(struct drm_encoder *encoder)
3408 {
3409 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3410 struct drm_device *dev = encoder->dev;
3411 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3412 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3413
3414 /* lvds has its own version of commit see intel_lvds_commit */
3415 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3416
3417 if (HAS_PCH_CPT(dev))
3418 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3419 }
3420
3421 void intel_encoder_destroy(struct drm_encoder *encoder)
3422 {
3423 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3424
3425 drm_encoder_cleanup(encoder);
3426 kfree(intel_encoder);
3427 }
3428
3429 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3430 struct drm_display_mode *mode,
3431 struct drm_display_mode *adjusted_mode)
3432 {
3433 struct drm_device *dev = crtc->dev;
3434
3435 if (HAS_PCH_SPLIT(dev)) {
3436 /* FDI link clock is fixed at 2.7G */
3437 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3438 return false;
3439 }
3440
3441 /* All interlaced capable intel hw wants timings in frames. */
3442 drm_mode_set_crtcinfo(adjusted_mode, 0);
3443
3444 return true;
3445 }
3446
3447 static int i945_get_display_clock_speed(struct drm_device *dev)
3448 {
3449 return 400000;
3450 }
3451
3452 static int i915_get_display_clock_speed(struct drm_device *dev)
3453 {
3454 return 333000;
3455 }
3456
3457 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3458 {
3459 return 200000;
3460 }
3461
3462 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3463 {
3464 u16 gcfgc = 0;
3465
3466 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3467
3468 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3469 return 133000;
3470 else {
3471 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3472 case GC_DISPLAY_CLOCK_333_MHZ:
3473 return 333000;
3474 default:
3475 case GC_DISPLAY_CLOCK_190_200_MHZ:
3476 return 190000;
3477 }
3478 }
3479 }
3480
3481 static int i865_get_display_clock_speed(struct drm_device *dev)
3482 {
3483 return 266000;
3484 }
3485
3486 static int i855_get_display_clock_speed(struct drm_device *dev)
3487 {
3488 u16 hpllcc = 0;
3489 /* Assume that the hardware is in the high speed state. This
3490 * should be the default.
3491 */
3492 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3493 case GC_CLOCK_133_200:
3494 case GC_CLOCK_100_200:
3495 return 200000;
3496 case GC_CLOCK_166_250:
3497 return 250000;
3498 case GC_CLOCK_100_133:
3499 return 133000;
3500 }
3501
3502 /* Shouldn't happen */
3503 return 0;
3504 }
3505
3506 static int i830_get_display_clock_speed(struct drm_device *dev)
3507 {
3508 return 133000;
3509 }
3510
3511 struct fdi_m_n {
3512 u32 tu;
3513 u32 gmch_m;
3514 u32 gmch_n;
3515 u32 link_m;
3516 u32 link_n;
3517 };
3518
3519 static void
3520 fdi_reduce_ratio(u32 *num, u32 *den)
3521 {
3522 while (*num > 0xffffff || *den > 0xffffff) {
3523 *num >>= 1;
3524 *den >>= 1;
3525 }
3526 }
3527
3528 static void
3529 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3530 int link_clock, struct fdi_m_n *m_n)
3531 {
3532 m_n->tu = 64; /* default size */
3533
3534 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3535 m_n->gmch_m = bits_per_pixel * pixel_clock;
3536 m_n->gmch_n = link_clock * nlanes * 8;
3537 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3538
3539 m_n->link_m = pixel_clock;
3540 m_n->link_n = link_clock;
3541 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3542 }
3543
3544
3545 struct intel_watermark_params {
3546 unsigned long fifo_size;
3547 unsigned long max_wm;
3548 unsigned long default_wm;
3549 unsigned long guard_size;
3550 unsigned long cacheline_size;
3551 };
3552
3553 /* Pineview has different values for various configs */
3554 static const struct intel_watermark_params pineview_display_wm = {
3555 PINEVIEW_DISPLAY_FIFO,
3556 PINEVIEW_MAX_WM,
3557 PINEVIEW_DFT_WM,
3558 PINEVIEW_GUARD_WM,
3559 PINEVIEW_FIFO_LINE_SIZE
3560 };
3561 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3562 PINEVIEW_DISPLAY_FIFO,
3563 PINEVIEW_MAX_WM,
3564 PINEVIEW_DFT_HPLLOFF_WM,
3565 PINEVIEW_GUARD_WM,
3566 PINEVIEW_FIFO_LINE_SIZE
3567 };
3568 static const struct intel_watermark_params pineview_cursor_wm = {
3569 PINEVIEW_CURSOR_FIFO,
3570 PINEVIEW_CURSOR_MAX_WM,
3571 PINEVIEW_CURSOR_DFT_WM,
3572 PINEVIEW_CURSOR_GUARD_WM,
3573 PINEVIEW_FIFO_LINE_SIZE,
3574 };
3575 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3576 PINEVIEW_CURSOR_FIFO,
3577 PINEVIEW_CURSOR_MAX_WM,
3578 PINEVIEW_CURSOR_DFT_WM,
3579 PINEVIEW_CURSOR_GUARD_WM,
3580 PINEVIEW_FIFO_LINE_SIZE
3581 };
3582 static const struct intel_watermark_params g4x_wm_info = {
3583 G4X_FIFO_SIZE,
3584 G4X_MAX_WM,
3585 G4X_MAX_WM,
3586 2,
3587 G4X_FIFO_LINE_SIZE,
3588 };
3589 static const struct intel_watermark_params g4x_cursor_wm_info = {
3590 I965_CURSOR_FIFO,
3591 I965_CURSOR_MAX_WM,
3592 I965_CURSOR_DFT_WM,
3593 2,
3594 G4X_FIFO_LINE_SIZE,
3595 };
3596 static const struct intel_watermark_params i965_cursor_wm_info = {
3597 I965_CURSOR_FIFO,
3598 I965_CURSOR_MAX_WM,
3599 I965_CURSOR_DFT_WM,
3600 2,
3601 I915_FIFO_LINE_SIZE,
3602 };
3603 static const struct intel_watermark_params i945_wm_info = {
3604 I945_FIFO_SIZE,
3605 I915_MAX_WM,
3606 1,
3607 2,
3608 I915_FIFO_LINE_SIZE
3609 };
3610 static const struct intel_watermark_params i915_wm_info = {
3611 I915_FIFO_SIZE,
3612 I915_MAX_WM,
3613 1,
3614 2,
3615 I915_FIFO_LINE_SIZE
3616 };
3617 static const struct intel_watermark_params i855_wm_info = {
3618 I855GM_FIFO_SIZE,
3619 I915_MAX_WM,
3620 1,
3621 2,
3622 I830_FIFO_LINE_SIZE
3623 };
3624 static const struct intel_watermark_params i830_wm_info = {
3625 I830_FIFO_SIZE,
3626 I915_MAX_WM,
3627 1,
3628 2,
3629 I830_FIFO_LINE_SIZE
3630 };
3631
3632 static const struct intel_watermark_params ironlake_display_wm_info = {
3633 ILK_DISPLAY_FIFO,
3634 ILK_DISPLAY_MAXWM,
3635 ILK_DISPLAY_DFTWM,
3636 2,
3637 ILK_FIFO_LINE_SIZE
3638 };
3639 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3640 ILK_CURSOR_FIFO,
3641 ILK_CURSOR_MAXWM,
3642 ILK_CURSOR_DFTWM,
3643 2,
3644 ILK_FIFO_LINE_SIZE
3645 };
3646 static const struct intel_watermark_params ironlake_display_srwm_info = {
3647 ILK_DISPLAY_SR_FIFO,
3648 ILK_DISPLAY_MAX_SRWM,
3649 ILK_DISPLAY_DFT_SRWM,
3650 2,
3651 ILK_FIFO_LINE_SIZE
3652 };
3653 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3654 ILK_CURSOR_SR_FIFO,
3655 ILK_CURSOR_MAX_SRWM,
3656 ILK_CURSOR_DFT_SRWM,
3657 2,
3658 ILK_FIFO_LINE_SIZE
3659 };
3660
3661 static const struct intel_watermark_params sandybridge_display_wm_info = {
3662 SNB_DISPLAY_FIFO,
3663 SNB_DISPLAY_MAXWM,
3664 SNB_DISPLAY_DFTWM,
3665 2,
3666 SNB_FIFO_LINE_SIZE
3667 };
3668 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3669 SNB_CURSOR_FIFO,
3670 SNB_CURSOR_MAXWM,
3671 SNB_CURSOR_DFTWM,
3672 2,
3673 SNB_FIFO_LINE_SIZE
3674 };
3675 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3676 SNB_DISPLAY_SR_FIFO,
3677 SNB_DISPLAY_MAX_SRWM,
3678 SNB_DISPLAY_DFT_SRWM,
3679 2,
3680 SNB_FIFO_LINE_SIZE
3681 };
3682 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3683 SNB_CURSOR_SR_FIFO,
3684 SNB_CURSOR_MAX_SRWM,
3685 SNB_CURSOR_DFT_SRWM,
3686 2,
3687 SNB_FIFO_LINE_SIZE
3688 };
3689
3690
3691 /**
3692 * intel_calculate_wm - calculate watermark level
3693 * @clock_in_khz: pixel clock
3694 * @wm: chip FIFO params
3695 * @pixel_size: display pixel size
3696 * @latency_ns: memory latency for the platform
3697 *
3698 * Calculate the watermark level (the level at which the display plane will
3699 * start fetching from memory again). Each chip has a different display
3700 * FIFO size and allocation, so the caller needs to figure that out and pass
3701 * in the correct intel_watermark_params structure.
3702 *
3703 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3704 * on the pixel size. When it reaches the watermark level, it'll start
3705 * fetching FIFO line sized based chunks from memory until the FIFO fills
3706 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3707 * will occur, and a display engine hang could result.
3708 */
3709 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3710 const struct intel_watermark_params *wm,
3711 int fifo_size,
3712 int pixel_size,
3713 unsigned long latency_ns)
3714 {
3715 long entries_required, wm_size;
3716
3717 /*
3718 * Note: we need to make sure we don't overflow for various clock &
3719 * latency values.
3720 * clocks go from a few thousand to several hundred thousand.
3721 * latency is usually a few thousand
3722 */
3723 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3724 1000;
3725 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3726
3727 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3728
3729 wm_size = fifo_size - (entries_required + wm->guard_size);
3730
3731 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3732
3733 /* Don't promote wm_size to unsigned... */
3734 if (wm_size > (long)wm->max_wm)
3735 wm_size = wm->max_wm;
3736 if (wm_size <= 0)
3737 wm_size = wm->default_wm;
3738 return wm_size;
3739 }
3740
3741 struct cxsr_latency {
3742 int is_desktop;
3743 int is_ddr3;
3744 unsigned long fsb_freq;
3745 unsigned long mem_freq;
3746 unsigned long display_sr;
3747 unsigned long display_hpll_disable;
3748 unsigned long cursor_sr;
3749 unsigned long cursor_hpll_disable;
3750 };
3751
3752 static const struct cxsr_latency cxsr_latency_table[] = {
3753 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3754 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3755 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3756 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3757 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3758
3759 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3760 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3761 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3762 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3763 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3764
3765 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3766 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3767 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3768 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3769 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3770
3771 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3772 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3773 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3774 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3775 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3776
3777 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3778 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3779 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3780 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3781 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3782
3783 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3784 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3785 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3786 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3787 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3788 };
3789
3790 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3791 int is_ddr3,
3792 int fsb,
3793 int mem)
3794 {
3795 const struct cxsr_latency *latency;
3796 int i;
3797
3798 if (fsb == 0 || mem == 0)
3799 return NULL;
3800
3801 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3802 latency = &cxsr_latency_table[i];
3803 if (is_desktop == latency->is_desktop &&
3804 is_ddr3 == latency->is_ddr3 &&
3805 fsb == latency->fsb_freq && mem == latency->mem_freq)
3806 return latency;
3807 }
3808
3809 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3810
3811 return NULL;
3812 }
3813
3814 static void pineview_disable_cxsr(struct drm_device *dev)
3815 {
3816 struct drm_i915_private *dev_priv = dev->dev_private;
3817
3818 /* deactivate cxsr */
3819 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3820 }
3821
3822 /*
3823 * Latency for FIFO fetches is dependent on several factors:
3824 * - memory configuration (speed, channels)
3825 * - chipset
3826 * - current MCH state
3827 * It can be fairly high in some situations, so here we assume a fairly
3828 * pessimal value. It's a tradeoff between extra memory fetches (if we
3829 * set this value too high, the FIFO will fetch frequently to stay full)
3830 * and power consumption (set it too low to save power and we might see
3831 * FIFO underruns and display "flicker").
3832 *
3833 * A value of 5us seems to be a good balance; safe for very low end
3834 * platforms but not overly aggressive on lower latency configs.
3835 */
3836 static const int latency_ns = 5000;
3837
3838 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3839 {
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 uint32_t dsparb = I915_READ(DSPARB);
3842 int size;
3843
3844 size = dsparb & 0x7f;
3845 if (plane)
3846 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3847
3848 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3849 plane ? "B" : "A", size);
3850
3851 return size;
3852 }
3853
3854 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3855 {
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857 uint32_t dsparb = I915_READ(DSPARB);
3858 int size;
3859
3860 size = dsparb & 0x1ff;
3861 if (plane)
3862 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3863 size >>= 1; /* Convert to cachelines */
3864
3865 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3866 plane ? "B" : "A", size);
3867
3868 return size;
3869 }
3870
3871 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3872 {
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 uint32_t dsparb = I915_READ(DSPARB);
3875 int size;
3876
3877 size = dsparb & 0x7f;
3878 size >>= 2; /* Convert to cachelines */
3879
3880 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3881 plane ? "B" : "A",
3882 size);
3883
3884 return size;
3885 }
3886
3887 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3888 {
3889 struct drm_i915_private *dev_priv = dev->dev_private;
3890 uint32_t dsparb = I915_READ(DSPARB);
3891 int size;
3892
3893 size = dsparb & 0x7f;
3894 size >>= 1; /* Convert to cachelines */
3895
3896 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3897 plane ? "B" : "A", size);
3898
3899 return size;
3900 }
3901
3902 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3903 {
3904 struct drm_crtc *crtc, *enabled = NULL;
3905
3906 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3907 if (crtc->enabled && crtc->fb) {
3908 if (enabled)
3909 return NULL;
3910 enabled = crtc;
3911 }
3912 }
3913
3914 return enabled;
3915 }
3916
3917 static void pineview_update_wm(struct drm_device *dev)
3918 {
3919 struct drm_i915_private *dev_priv = dev->dev_private;
3920 struct drm_crtc *crtc;
3921 const struct cxsr_latency *latency;
3922 u32 reg;
3923 unsigned long wm;
3924
3925 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3926 dev_priv->fsb_freq, dev_priv->mem_freq);
3927 if (!latency) {
3928 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3929 pineview_disable_cxsr(dev);
3930 return;
3931 }
3932
3933 crtc = single_enabled_crtc(dev);
3934 if (crtc) {
3935 int clock = crtc->mode.clock;
3936 int pixel_size = crtc->fb->bits_per_pixel / 8;
3937
3938 /* Display SR */
3939 wm = intel_calculate_wm(clock, &pineview_display_wm,
3940 pineview_display_wm.fifo_size,
3941 pixel_size, latency->display_sr);
3942 reg = I915_READ(DSPFW1);
3943 reg &= ~DSPFW_SR_MASK;
3944 reg |= wm << DSPFW_SR_SHIFT;
3945 I915_WRITE(DSPFW1, reg);
3946 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3947
3948 /* cursor SR */
3949 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3950 pineview_display_wm.fifo_size,
3951 pixel_size, latency->cursor_sr);
3952 reg = I915_READ(DSPFW3);
3953 reg &= ~DSPFW_CURSOR_SR_MASK;
3954 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3955 I915_WRITE(DSPFW3, reg);
3956
3957 /* Display HPLL off SR */
3958 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3959 pineview_display_hplloff_wm.fifo_size,
3960 pixel_size, latency->display_hpll_disable);
3961 reg = I915_READ(DSPFW3);
3962 reg &= ~DSPFW_HPLL_SR_MASK;
3963 reg |= wm & DSPFW_HPLL_SR_MASK;
3964 I915_WRITE(DSPFW3, reg);
3965
3966 /* cursor HPLL off SR */
3967 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3968 pineview_display_hplloff_wm.fifo_size,
3969 pixel_size, latency->cursor_hpll_disable);
3970 reg = I915_READ(DSPFW3);
3971 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3972 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3973 I915_WRITE(DSPFW3, reg);
3974 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3975
3976 /* activate cxsr */
3977 I915_WRITE(DSPFW3,
3978 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3979 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3980 } else {
3981 pineview_disable_cxsr(dev);
3982 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3983 }
3984 }
3985
3986 static bool g4x_compute_wm0(struct drm_device *dev,
3987 int plane,
3988 const struct intel_watermark_params *display,
3989 int display_latency_ns,
3990 const struct intel_watermark_params *cursor,
3991 int cursor_latency_ns,
3992 int *plane_wm,
3993 int *cursor_wm)
3994 {
3995 struct drm_crtc *crtc;
3996 int htotal, hdisplay, clock, pixel_size;
3997 int line_time_us, line_count;
3998 int entries, tlb_miss;
3999
4000 crtc = intel_get_crtc_for_plane(dev, plane);
4001 if (crtc->fb == NULL || !crtc->enabled) {
4002 *cursor_wm = cursor->guard_size;
4003 *plane_wm = display->guard_size;
4004 return false;
4005 }
4006
4007 htotal = crtc->mode.htotal;
4008 hdisplay = crtc->mode.hdisplay;
4009 clock = crtc->mode.clock;
4010 pixel_size = crtc->fb->bits_per_pixel / 8;
4011
4012 /* Use the small buffer method to calculate plane watermark */
4013 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4014 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4015 if (tlb_miss > 0)
4016 entries += tlb_miss;
4017 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4018 *plane_wm = entries + display->guard_size;
4019 if (*plane_wm > (int)display->max_wm)
4020 *plane_wm = display->max_wm;
4021
4022 /* Use the large buffer method to calculate cursor watermark */
4023 line_time_us = ((htotal * 1000) / clock);
4024 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4025 entries = line_count * 64 * pixel_size;
4026 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4027 if (tlb_miss > 0)
4028 entries += tlb_miss;
4029 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4030 *cursor_wm = entries + cursor->guard_size;
4031 if (*cursor_wm > (int)cursor->max_wm)
4032 *cursor_wm = (int)cursor->max_wm;
4033
4034 return true;
4035 }
4036
4037 /*
4038 * Check the wm result.
4039 *
4040 * If any calculated watermark values is larger than the maximum value that
4041 * can be programmed into the associated watermark register, that watermark
4042 * must be disabled.
4043 */
4044 static bool g4x_check_srwm(struct drm_device *dev,
4045 int display_wm, int cursor_wm,
4046 const struct intel_watermark_params *display,
4047 const struct intel_watermark_params *cursor)
4048 {
4049 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4050 display_wm, cursor_wm);
4051
4052 if (display_wm > display->max_wm) {
4053 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4054 display_wm, display->max_wm);
4055 return false;
4056 }
4057
4058 if (cursor_wm > cursor->max_wm) {
4059 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4060 cursor_wm, cursor->max_wm);
4061 return false;
4062 }
4063
4064 if (!(display_wm || cursor_wm)) {
4065 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4066 return false;
4067 }
4068
4069 return true;
4070 }
4071
4072 static bool g4x_compute_srwm(struct drm_device *dev,
4073 int plane,
4074 int latency_ns,
4075 const struct intel_watermark_params *display,
4076 const struct intel_watermark_params *cursor,
4077 int *display_wm, int *cursor_wm)
4078 {
4079 struct drm_crtc *crtc;
4080 int hdisplay, htotal, pixel_size, clock;
4081 unsigned long line_time_us;
4082 int line_count, line_size;
4083 int small, large;
4084 int entries;
4085
4086 if (!latency_ns) {
4087 *display_wm = *cursor_wm = 0;
4088 return false;
4089 }
4090
4091 crtc = intel_get_crtc_for_plane(dev, plane);
4092 hdisplay = crtc->mode.hdisplay;
4093 htotal = crtc->mode.htotal;
4094 clock = crtc->mode.clock;
4095 pixel_size = crtc->fb->bits_per_pixel / 8;
4096
4097 line_time_us = (htotal * 1000) / clock;
4098 line_count = (latency_ns / line_time_us + 1000) / 1000;
4099 line_size = hdisplay * pixel_size;
4100
4101 /* Use the minimum of the small and large buffer method for primary */
4102 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4103 large = line_count * line_size;
4104
4105 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4106 *display_wm = entries + display->guard_size;
4107
4108 /* calculate the self-refresh watermark for display cursor */
4109 entries = line_count * pixel_size * 64;
4110 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4111 *cursor_wm = entries + cursor->guard_size;
4112
4113 return g4x_check_srwm(dev,
4114 *display_wm, *cursor_wm,
4115 display, cursor);
4116 }
4117
4118 #define single_plane_enabled(mask) is_power_of_2(mask)
4119
4120 static void g4x_update_wm(struct drm_device *dev)
4121 {
4122 static const int sr_latency_ns = 12000;
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4125 int plane_sr, cursor_sr;
4126 unsigned int enabled = 0;
4127
4128 if (g4x_compute_wm0(dev, 0,
4129 &g4x_wm_info, latency_ns,
4130 &g4x_cursor_wm_info, latency_ns,
4131 &planea_wm, &cursora_wm))
4132 enabled |= 1;
4133
4134 if (g4x_compute_wm0(dev, 1,
4135 &g4x_wm_info, latency_ns,
4136 &g4x_cursor_wm_info, latency_ns,
4137 &planeb_wm, &cursorb_wm))
4138 enabled |= 2;
4139
4140 plane_sr = cursor_sr = 0;
4141 if (single_plane_enabled(enabled) &&
4142 g4x_compute_srwm(dev, ffs(enabled) - 1,
4143 sr_latency_ns,
4144 &g4x_wm_info,
4145 &g4x_cursor_wm_info,
4146 &plane_sr, &cursor_sr))
4147 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4148 else
4149 I915_WRITE(FW_BLC_SELF,
4150 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4151
4152 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4153 planea_wm, cursora_wm,
4154 planeb_wm, cursorb_wm,
4155 plane_sr, cursor_sr);
4156
4157 I915_WRITE(DSPFW1,
4158 (plane_sr << DSPFW_SR_SHIFT) |
4159 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4160 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4161 planea_wm);
4162 I915_WRITE(DSPFW2,
4163 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4164 (cursora_wm << DSPFW_CURSORA_SHIFT));
4165 /* HPLL off in SR has some issues on G4x... disable it */
4166 I915_WRITE(DSPFW3,
4167 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4168 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4169 }
4170
4171 static void i965_update_wm(struct drm_device *dev)
4172 {
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct drm_crtc *crtc;
4175 int srwm = 1;
4176 int cursor_sr = 16;
4177
4178 /* Calc sr entries for one plane configs */
4179 crtc = single_enabled_crtc(dev);
4180 if (crtc) {
4181 /* self-refresh has much higher latency */
4182 static const int sr_latency_ns = 12000;
4183 int clock = crtc->mode.clock;
4184 int htotal = crtc->mode.htotal;
4185 int hdisplay = crtc->mode.hdisplay;
4186 int pixel_size = crtc->fb->bits_per_pixel / 8;
4187 unsigned long line_time_us;
4188 int entries;
4189
4190 line_time_us = ((htotal * 1000) / clock);
4191
4192 /* Use ns/us then divide to preserve precision */
4193 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4194 pixel_size * hdisplay;
4195 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4196 srwm = I965_FIFO_SIZE - entries;
4197 if (srwm < 0)
4198 srwm = 1;
4199 srwm &= 0x1ff;
4200 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4201 entries, srwm);
4202
4203 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4204 pixel_size * 64;
4205 entries = DIV_ROUND_UP(entries,
4206 i965_cursor_wm_info.cacheline_size);
4207 cursor_sr = i965_cursor_wm_info.fifo_size -
4208 (entries + i965_cursor_wm_info.guard_size);
4209
4210 if (cursor_sr > i965_cursor_wm_info.max_wm)
4211 cursor_sr = i965_cursor_wm_info.max_wm;
4212
4213 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4214 "cursor %d\n", srwm, cursor_sr);
4215
4216 if (IS_CRESTLINE(dev))
4217 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4218 } else {
4219 /* Turn off self refresh if both pipes are enabled */
4220 if (IS_CRESTLINE(dev))
4221 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4222 & ~FW_BLC_SELF_EN);
4223 }
4224
4225 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4226 srwm);
4227
4228 /* 965 has limitations... */
4229 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4230 (8 << 16) | (8 << 8) | (8 << 0));
4231 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4232 /* update cursor SR watermark */
4233 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4234 }
4235
4236 static void i9xx_update_wm(struct drm_device *dev)
4237 {
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 const struct intel_watermark_params *wm_info;
4240 uint32_t fwater_lo;
4241 uint32_t fwater_hi;
4242 int cwm, srwm = 1;
4243 int fifo_size;
4244 int planea_wm, planeb_wm;
4245 struct drm_crtc *crtc, *enabled = NULL;
4246
4247 if (IS_I945GM(dev))
4248 wm_info = &i945_wm_info;
4249 else if (!IS_GEN2(dev))
4250 wm_info = &i915_wm_info;
4251 else
4252 wm_info = &i855_wm_info;
4253
4254 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4255 crtc = intel_get_crtc_for_plane(dev, 0);
4256 if (crtc->enabled && crtc->fb) {
4257 planea_wm = intel_calculate_wm(crtc->mode.clock,
4258 wm_info, fifo_size,
4259 crtc->fb->bits_per_pixel / 8,
4260 latency_ns);
4261 enabled = crtc;
4262 } else
4263 planea_wm = fifo_size - wm_info->guard_size;
4264
4265 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4266 crtc = intel_get_crtc_for_plane(dev, 1);
4267 if (crtc->enabled && crtc->fb) {
4268 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4269 wm_info, fifo_size,
4270 crtc->fb->bits_per_pixel / 8,
4271 latency_ns);
4272 if (enabled == NULL)
4273 enabled = crtc;
4274 else
4275 enabled = NULL;
4276 } else
4277 planeb_wm = fifo_size - wm_info->guard_size;
4278
4279 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4280
4281 /*
4282 * Overlay gets an aggressive default since video jitter is bad.
4283 */
4284 cwm = 2;
4285
4286 /* Play safe and disable self-refresh before adjusting watermarks. */
4287 if (IS_I945G(dev) || IS_I945GM(dev))
4288 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4289 else if (IS_I915GM(dev))
4290 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4291
4292 /* Calc sr entries for one plane configs */
4293 if (HAS_FW_BLC(dev) && enabled) {
4294 /* self-refresh has much higher latency */
4295 static const int sr_latency_ns = 6000;
4296 int clock = enabled->mode.clock;
4297 int htotal = enabled->mode.htotal;
4298 int hdisplay = enabled->mode.hdisplay;
4299 int pixel_size = enabled->fb->bits_per_pixel / 8;
4300 unsigned long line_time_us;
4301 int entries;
4302
4303 line_time_us = (htotal * 1000) / clock;
4304
4305 /* Use ns/us then divide to preserve precision */
4306 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4307 pixel_size * hdisplay;
4308 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4309 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4310 srwm = wm_info->fifo_size - entries;
4311 if (srwm < 0)
4312 srwm = 1;
4313
4314 if (IS_I945G(dev) || IS_I945GM(dev))
4315 I915_WRITE(FW_BLC_SELF,
4316 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4317 else if (IS_I915GM(dev))
4318 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4319 }
4320
4321 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4322 planea_wm, planeb_wm, cwm, srwm);
4323
4324 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4325 fwater_hi = (cwm & 0x1f);
4326
4327 /* Set request length to 8 cachelines per fetch */
4328 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4329 fwater_hi = fwater_hi | (1 << 8);
4330
4331 I915_WRITE(FW_BLC, fwater_lo);
4332 I915_WRITE(FW_BLC2, fwater_hi);
4333
4334 if (HAS_FW_BLC(dev)) {
4335 if (enabled) {
4336 if (IS_I945G(dev) || IS_I945GM(dev))
4337 I915_WRITE(FW_BLC_SELF,
4338 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4339 else if (IS_I915GM(dev))
4340 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4341 DRM_DEBUG_KMS("memory self refresh enabled\n");
4342 } else
4343 DRM_DEBUG_KMS("memory self refresh disabled\n");
4344 }
4345 }
4346
4347 static void i830_update_wm(struct drm_device *dev)
4348 {
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350 struct drm_crtc *crtc;
4351 uint32_t fwater_lo;
4352 int planea_wm;
4353
4354 crtc = single_enabled_crtc(dev);
4355 if (crtc == NULL)
4356 return;
4357
4358 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4359 dev_priv->display.get_fifo_size(dev, 0),
4360 crtc->fb->bits_per_pixel / 8,
4361 latency_ns);
4362 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4363 fwater_lo |= (3<<8) | planea_wm;
4364
4365 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4366
4367 I915_WRITE(FW_BLC, fwater_lo);
4368 }
4369
4370 #define ILK_LP0_PLANE_LATENCY 700
4371 #define ILK_LP0_CURSOR_LATENCY 1300
4372
4373 /*
4374 * Check the wm result.
4375 *
4376 * If any calculated watermark values is larger than the maximum value that
4377 * can be programmed into the associated watermark register, that watermark
4378 * must be disabled.
4379 */
4380 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4381 int fbc_wm, int display_wm, int cursor_wm,
4382 const struct intel_watermark_params *display,
4383 const struct intel_watermark_params *cursor)
4384 {
4385 struct drm_i915_private *dev_priv = dev->dev_private;
4386
4387 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4388 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4389
4390 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4391 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4392 fbc_wm, SNB_FBC_MAX_SRWM, level);
4393
4394 /* fbc has it's own way to disable FBC WM */
4395 I915_WRITE(DISP_ARB_CTL,
4396 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4397 return false;
4398 }
4399
4400 if (display_wm > display->max_wm) {
4401 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4402 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4403 return false;
4404 }
4405
4406 if (cursor_wm > cursor->max_wm) {
4407 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4408 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4409 return false;
4410 }
4411
4412 if (!(fbc_wm || display_wm || cursor_wm)) {
4413 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4414 return false;
4415 }
4416
4417 return true;
4418 }
4419
4420 /*
4421 * Compute watermark values of WM[1-3],
4422 */
4423 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4424 int latency_ns,
4425 const struct intel_watermark_params *display,
4426 const struct intel_watermark_params *cursor,
4427 int *fbc_wm, int *display_wm, int *cursor_wm)
4428 {
4429 struct drm_crtc *crtc;
4430 unsigned long line_time_us;
4431 int hdisplay, htotal, pixel_size, clock;
4432 int line_count, line_size;
4433 int small, large;
4434 int entries;
4435
4436 if (!latency_ns) {
4437 *fbc_wm = *display_wm = *cursor_wm = 0;
4438 return false;
4439 }
4440
4441 crtc = intel_get_crtc_for_plane(dev, plane);
4442 hdisplay = crtc->mode.hdisplay;
4443 htotal = crtc->mode.htotal;
4444 clock = crtc->mode.clock;
4445 pixel_size = crtc->fb->bits_per_pixel / 8;
4446
4447 line_time_us = (htotal * 1000) / clock;
4448 line_count = (latency_ns / line_time_us + 1000) / 1000;
4449 line_size = hdisplay * pixel_size;
4450
4451 /* Use the minimum of the small and large buffer method for primary */
4452 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4453 large = line_count * line_size;
4454
4455 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4456 *display_wm = entries + display->guard_size;
4457
4458 /*
4459 * Spec says:
4460 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4461 */
4462 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4463
4464 /* calculate the self-refresh watermark for display cursor */
4465 entries = line_count * pixel_size * 64;
4466 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4467 *cursor_wm = entries + cursor->guard_size;
4468
4469 return ironlake_check_srwm(dev, level,
4470 *fbc_wm, *display_wm, *cursor_wm,
4471 display, cursor);
4472 }
4473
4474 static void ironlake_update_wm(struct drm_device *dev)
4475 {
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 int fbc_wm, plane_wm, cursor_wm;
4478 unsigned int enabled;
4479
4480 enabled = 0;
4481 if (g4x_compute_wm0(dev, 0,
4482 &ironlake_display_wm_info,
4483 ILK_LP0_PLANE_LATENCY,
4484 &ironlake_cursor_wm_info,
4485 ILK_LP0_CURSOR_LATENCY,
4486 &plane_wm, &cursor_wm)) {
4487 I915_WRITE(WM0_PIPEA_ILK,
4488 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4489 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4490 " plane %d, " "cursor: %d\n",
4491 plane_wm, cursor_wm);
4492 enabled |= 1;
4493 }
4494
4495 if (g4x_compute_wm0(dev, 1,
4496 &ironlake_display_wm_info,
4497 ILK_LP0_PLANE_LATENCY,
4498 &ironlake_cursor_wm_info,
4499 ILK_LP0_CURSOR_LATENCY,
4500 &plane_wm, &cursor_wm)) {
4501 I915_WRITE(WM0_PIPEB_ILK,
4502 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4503 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4504 " plane %d, cursor: %d\n",
4505 plane_wm, cursor_wm);
4506 enabled |= 2;
4507 }
4508
4509 /*
4510 * Calculate and update the self-refresh watermark only when one
4511 * display plane is used.
4512 */
4513 I915_WRITE(WM3_LP_ILK, 0);
4514 I915_WRITE(WM2_LP_ILK, 0);
4515 I915_WRITE(WM1_LP_ILK, 0);
4516
4517 if (!single_plane_enabled(enabled))
4518 return;
4519 enabled = ffs(enabled) - 1;
4520
4521 /* WM1 */
4522 if (!ironlake_compute_srwm(dev, 1, enabled,
4523 ILK_READ_WM1_LATENCY() * 500,
4524 &ironlake_display_srwm_info,
4525 &ironlake_cursor_srwm_info,
4526 &fbc_wm, &plane_wm, &cursor_wm))
4527 return;
4528
4529 I915_WRITE(WM1_LP_ILK,
4530 WM1_LP_SR_EN |
4531 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4532 (fbc_wm << WM1_LP_FBC_SHIFT) |
4533 (plane_wm << WM1_LP_SR_SHIFT) |
4534 cursor_wm);
4535
4536 /* WM2 */
4537 if (!ironlake_compute_srwm(dev, 2, enabled,
4538 ILK_READ_WM2_LATENCY() * 500,
4539 &ironlake_display_srwm_info,
4540 &ironlake_cursor_srwm_info,
4541 &fbc_wm, &plane_wm, &cursor_wm))
4542 return;
4543
4544 I915_WRITE(WM2_LP_ILK,
4545 WM2_LP_EN |
4546 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4547 (fbc_wm << WM1_LP_FBC_SHIFT) |
4548 (plane_wm << WM1_LP_SR_SHIFT) |
4549 cursor_wm);
4550
4551 /*
4552 * WM3 is unsupported on ILK, probably because we don't have latency
4553 * data for that power state
4554 */
4555 }
4556
4557 void sandybridge_update_wm(struct drm_device *dev)
4558 {
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4561 u32 val;
4562 int fbc_wm, plane_wm, cursor_wm;
4563 unsigned int enabled;
4564
4565 enabled = 0;
4566 if (g4x_compute_wm0(dev, 0,
4567 &sandybridge_display_wm_info, latency,
4568 &sandybridge_cursor_wm_info, latency,
4569 &plane_wm, &cursor_wm)) {
4570 val = I915_READ(WM0_PIPEA_ILK);
4571 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4572 I915_WRITE(WM0_PIPEA_ILK, val |
4573 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4574 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4575 " plane %d, " "cursor: %d\n",
4576 plane_wm, cursor_wm);
4577 enabled |= 1;
4578 }
4579
4580 if (g4x_compute_wm0(dev, 1,
4581 &sandybridge_display_wm_info, latency,
4582 &sandybridge_cursor_wm_info, latency,
4583 &plane_wm, &cursor_wm)) {
4584 val = I915_READ(WM0_PIPEB_ILK);
4585 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4586 I915_WRITE(WM0_PIPEB_ILK, val |
4587 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4588 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4589 " plane %d, cursor: %d\n",
4590 plane_wm, cursor_wm);
4591 enabled |= 2;
4592 }
4593
4594 /* IVB has 3 pipes */
4595 if (IS_IVYBRIDGE(dev) &&
4596 g4x_compute_wm0(dev, 2,
4597 &sandybridge_display_wm_info, latency,
4598 &sandybridge_cursor_wm_info, latency,
4599 &plane_wm, &cursor_wm)) {
4600 val = I915_READ(WM0_PIPEC_IVB);
4601 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4602 I915_WRITE(WM0_PIPEC_IVB, val |
4603 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4604 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4605 " plane %d, cursor: %d\n",
4606 plane_wm, cursor_wm);
4607 enabled |= 3;
4608 }
4609
4610 /*
4611 * Calculate and update the self-refresh watermark only when one
4612 * display plane is used.
4613 *
4614 * SNB support 3 levels of watermark.
4615 *
4616 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4617 * and disabled in the descending order
4618 *
4619 */
4620 I915_WRITE(WM3_LP_ILK, 0);
4621 I915_WRITE(WM2_LP_ILK, 0);
4622 I915_WRITE(WM1_LP_ILK, 0);
4623
4624 if (!single_plane_enabled(enabled) ||
4625 dev_priv->sprite_scaling_enabled)
4626 return;
4627 enabled = ffs(enabled) - 1;
4628
4629 /* WM1 */
4630 if (!ironlake_compute_srwm(dev, 1, enabled,
4631 SNB_READ_WM1_LATENCY() * 500,
4632 &sandybridge_display_srwm_info,
4633 &sandybridge_cursor_srwm_info,
4634 &fbc_wm, &plane_wm, &cursor_wm))
4635 return;
4636
4637 I915_WRITE(WM1_LP_ILK,
4638 WM1_LP_SR_EN |
4639 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4640 (fbc_wm << WM1_LP_FBC_SHIFT) |
4641 (plane_wm << WM1_LP_SR_SHIFT) |
4642 cursor_wm);
4643
4644 /* WM2 */
4645 if (!ironlake_compute_srwm(dev, 2, enabled,
4646 SNB_READ_WM2_LATENCY() * 500,
4647 &sandybridge_display_srwm_info,
4648 &sandybridge_cursor_srwm_info,
4649 &fbc_wm, &plane_wm, &cursor_wm))
4650 return;
4651
4652 I915_WRITE(WM2_LP_ILK,
4653 WM2_LP_EN |
4654 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4655 (fbc_wm << WM1_LP_FBC_SHIFT) |
4656 (plane_wm << WM1_LP_SR_SHIFT) |
4657 cursor_wm);
4658
4659 /* WM3 */
4660 if (!ironlake_compute_srwm(dev, 3, enabled,
4661 SNB_READ_WM3_LATENCY() * 500,
4662 &sandybridge_display_srwm_info,
4663 &sandybridge_cursor_srwm_info,
4664 &fbc_wm, &plane_wm, &cursor_wm))
4665 return;
4666
4667 I915_WRITE(WM3_LP_ILK,
4668 WM3_LP_EN |
4669 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4670 (fbc_wm << WM1_LP_FBC_SHIFT) |
4671 (plane_wm << WM1_LP_SR_SHIFT) |
4672 cursor_wm);
4673 }
4674
4675 static bool
4676 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4677 uint32_t sprite_width, int pixel_size,
4678 const struct intel_watermark_params *display,
4679 int display_latency_ns, int *sprite_wm)
4680 {
4681 struct drm_crtc *crtc;
4682 int clock;
4683 int entries, tlb_miss;
4684
4685 crtc = intel_get_crtc_for_plane(dev, plane);
4686 if (crtc->fb == NULL || !crtc->enabled) {
4687 *sprite_wm = display->guard_size;
4688 return false;
4689 }
4690
4691 clock = crtc->mode.clock;
4692
4693 /* Use the small buffer method to calculate the sprite watermark */
4694 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4695 tlb_miss = display->fifo_size*display->cacheline_size -
4696 sprite_width * 8;
4697 if (tlb_miss > 0)
4698 entries += tlb_miss;
4699 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4700 *sprite_wm = entries + display->guard_size;
4701 if (*sprite_wm > (int)display->max_wm)
4702 *sprite_wm = display->max_wm;
4703
4704 return true;
4705 }
4706
4707 static bool
4708 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4709 uint32_t sprite_width, int pixel_size,
4710 const struct intel_watermark_params *display,
4711 int latency_ns, int *sprite_wm)
4712 {
4713 struct drm_crtc *crtc;
4714 unsigned long line_time_us;
4715 int clock;
4716 int line_count, line_size;
4717 int small, large;
4718 int entries;
4719
4720 if (!latency_ns) {
4721 *sprite_wm = 0;
4722 return false;
4723 }
4724
4725 crtc = intel_get_crtc_for_plane(dev, plane);
4726 clock = crtc->mode.clock;
4727
4728 line_time_us = (sprite_width * 1000) / clock;
4729 line_count = (latency_ns / line_time_us + 1000) / 1000;
4730 line_size = sprite_width * pixel_size;
4731
4732 /* Use the minimum of the small and large buffer method for primary */
4733 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4734 large = line_count * line_size;
4735
4736 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4737 *sprite_wm = entries + display->guard_size;
4738
4739 return *sprite_wm > 0x3ff ? false : true;
4740 }
4741
4742 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4743 uint32_t sprite_width, int pixel_size)
4744 {
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4747 u32 val;
4748 int sprite_wm, reg;
4749 int ret;
4750
4751 switch (pipe) {
4752 case 0:
4753 reg = WM0_PIPEA_ILK;
4754 break;
4755 case 1:
4756 reg = WM0_PIPEB_ILK;
4757 break;
4758 case 2:
4759 reg = WM0_PIPEC_IVB;
4760 break;
4761 default:
4762 return; /* bad pipe */
4763 }
4764
4765 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4766 &sandybridge_display_wm_info,
4767 latency, &sprite_wm);
4768 if (!ret) {
4769 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4770 pipe);
4771 return;
4772 }
4773
4774 val = I915_READ(reg);
4775 val &= ~WM0_PIPE_SPRITE_MASK;
4776 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4777 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4778
4779
4780 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4781 pixel_size,
4782 &sandybridge_display_srwm_info,
4783 SNB_READ_WM1_LATENCY() * 500,
4784 &sprite_wm);
4785 if (!ret) {
4786 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4787 pipe);
4788 return;
4789 }
4790 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4791
4792 /* Only IVB has two more LP watermarks for sprite */
4793 if (!IS_IVYBRIDGE(dev))
4794 return;
4795
4796 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4797 pixel_size,
4798 &sandybridge_display_srwm_info,
4799 SNB_READ_WM2_LATENCY() * 500,
4800 &sprite_wm);
4801 if (!ret) {
4802 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4803 pipe);
4804 return;
4805 }
4806 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4807
4808 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4809 pixel_size,
4810 &sandybridge_display_srwm_info,
4811 SNB_READ_WM3_LATENCY() * 500,
4812 &sprite_wm);
4813 if (!ret) {
4814 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4815 pipe);
4816 return;
4817 }
4818 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4819 }
4820
4821 /**
4822 * intel_update_watermarks - update FIFO watermark values based on current modes
4823 *
4824 * Calculate watermark values for the various WM regs based on current mode
4825 * and plane configuration.
4826 *
4827 * There are several cases to deal with here:
4828 * - normal (i.e. non-self-refresh)
4829 * - self-refresh (SR) mode
4830 * - lines are large relative to FIFO size (buffer can hold up to 2)
4831 * - lines are small relative to FIFO size (buffer can hold more than 2
4832 * lines), so need to account for TLB latency
4833 *
4834 * The normal calculation is:
4835 * watermark = dotclock * bytes per pixel * latency
4836 * where latency is platform & configuration dependent (we assume pessimal
4837 * values here).
4838 *
4839 * The SR calculation is:
4840 * watermark = (trunc(latency/line time)+1) * surface width *
4841 * bytes per pixel
4842 * where
4843 * line time = htotal / dotclock
4844 * surface width = hdisplay for normal plane and 64 for cursor
4845 * and latency is assumed to be high, as above.
4846 *
4847 * The final value programmed to the register should always be rounded up,
4848 * and include an extra 2 entries to account for clock crossings.
4849 *
4850 * We don't use the sprite, so we can ignore that. And on Crestline we have
4851 * to set the non-SR watermarks to 8.
4852 */
4853 static void intel_update_watermarks(struct drm_device *dev)
4854 {
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856
4857 if (dev_priv->display.update_wm)
4858 dev_priv->display.update_wm(dev);
4859 }
4860
4861 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4862 uint32_t sprite_width, int pixel_size)
4863 {
4864 struct drm_i915_private *dev_priv = dev->dev_private;
4865
4866 if (dev_priv->display.update_sprite_wm)
4867 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4868 pixel_size);
4869 }
4870
4871 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4872 {
4873 if (i915_panel_use_ssc >= 0)
4874 return i915_panel_use_ssc != 0;
4875 return dev_priv->lvds_use_ssc
4876 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4877 }
4878
4879 /**
4880 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4881 * @crtc: CRTC structure
4882 * @mode: requested mode
4883 *
4884 * A pipe may be connected to one or more outputs. Based on the depth of the
4885 * attached framebuffer, choose a good color depth to use on the pipe.
4886 *
4887 * If possible, match the pipe depth to the fb depth. In some cases, this
4888 * isn't ideal, because the connected output supports a lesser or restricted
4889 * set of depths. Resolve that here:
4890 * LVDS typically supports only 6bpc, so clamp down in that case
4891 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4892 * Displays may support a restricted set as well, check EDID and clamp as
4893 * appropriate.
4894 * DP may want to dither down to 6bpc to fit larger modes
4895 *
4896 * RETURNS:
4897 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4898 * true if they don't match).
4899 */
4900 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4901 unsigned int *pipe_bpp,
4902 struct drm_display_mode *mode)
4903 {
4904 struct drm_device *dev = crtc->dev;
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906 struct drm_encoder *encoder;
4907 struct drm_connector *connector;
4908 unsigned int display_bpc = UINT_MAX, bpc;
4909
4910 /* Walk the encoders & connectors on this crtc, get min bpc */
4911 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4912 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4913
4914 if (encoder->crtc != crtc)
4915 continue;
4916
4917 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4918 unsigned int lvds_bpc;
4919
4920 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4921 LVDS_A3_POWER_UP)
4922 lvds_bpc = 8;
4923 else
4924 lvds_bpc = 6;
4925
4926 if (lvds_bpc < display_bpc) {
4927 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4928 display_bpc = lvds_bpc;
4929 }
4930 continue;
4931 }
4932
4933 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4934 /* Use VBT settings if we have an eDP panel */
4935 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4936
4937 if (edp_bpc < display_bpc) {
4938 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4939 display_bpc = edp_bpc;
4940 }
4941 continue;
4942 }
4943
4944 /* Not one of the known troublemakers, check the EDID */
4945 list_for_each_entry(connector, &dev->mode_config.connector_list,
4946 head) {
4947 if (connector->encoder != encoder)
4948 continue;
4949
4950 /* Don't use an invalid EDID bpc value */
4951 if (connector->display_info.bpc &&
4952 connector->display_info.bpc < display_bpc) {
4953 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4954 display_bpc = connector->display_info.bpc;
4955 }
4956 }
4957
4958 /*
4959 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4960 * through, clamp it down. (Note: >12bpc will be caught below.)
4961 */
4962 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4963 if (display_bpc > 8 && display_bpc < 12) {
4964 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4965 display_bpc = 12;
4966 } else {
4967 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4968 display_bpc = 8;
4969 }
4970 }
4971 }
4972
4973 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4974 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4975 display_bpc = 6;
4976 }
4977
4978 /*
4979 * We could just drive the pipe at the highest bpc all the time and
4980 * enable dithering as needed, but that costs bandwidth. So choose
4981 * the minimum value that expresses the full color range of the fb but
4982 * also stays within the max display bpc discovered above.
4983 */
4984
4985 switch (crtc->fb->depth) {
4986 case 8:
4987 bpc = 8; /* since we go through a colormap */
4988 break;
4989 case 15:
4990 case 16:
4991 bpc = 6; /* min is 18bpp */
4992 break;
4993 case 24:
4994 bpc = 8;
4995 break;
4996 case 30:
4997 bpc = 10;
4998 break;
4999 case 48:
5000 bpc = 12;
5001 break;
5002 default:
5003 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5004 bpc = min((unsigned int)8, display_bpc);
5005 break;
5006 }
5007
5008 display_bpc = min(display_bpc, bpc);
5009
5010 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5011 bpc, display_bpc);
5012
5013 *pipe_bpp = display_bpc * 3;
5014
5015 return display_bpc != bpc;
5016 }
5017
5018 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5019 {
5020 struct drm_device *dev = crtc->dev;
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 int refclk;
5023
5024 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5025 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5026 refclk = dev_priv->lvds_ssc_freq * 1000;
5027 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5028 refclk / 1000);
5029 } else if (!IS_GEN2(dev)) {
5030 refclk = 96000;
5031 } else {
5032 refclk = 48000;
5033 }
5034
5035 return refclk;
5036 }
5037
5038 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5039 intel_clock_t *clock)
5040 {
5041 /* SDVO TV has fixed PLL values depend on its clock range,
5042 this mirrors vbios setting. */
5043 if (adjusted_mode->clock >= 100000
5044 && adjusted_mode->clock < 140500) {
5045 clock->p1 = 2;
5046 clock->p2 = 10;
5047 clock->n = 3;
5048 clock->m1 = 16;
5049 clock->m2 = 8;
5050 } else if (adjusted_mode->clock >= 140500
5051 && adjusted_mode->clock <= 200000) {
5052 clock->p1 = 1;
5053 clock->p2 = 10;
5054 clock->n = 6;
5055 clock->m1 = 12;
5056 clock->m2 = 8;
5057 }
5058 }
5059
5060 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5061 intel_clock_t *clock,
5062 intel_clock_t *reduced_clock)
5063 {
5064 struct drm_device *dev = crtc->dev;
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5067 int pipe = intel_crtc->pipe;
5068 u32 fp, fp2 = 0;
5069
5070 if (IS_PINEVIEW(dev)) {
5071 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5072 if (reduced_clock)
5073 fp2 = (1 << reduced_clock->n) << 16 |
5074 reduced_clock->m1 << 8 | reduced_clock->m2;
5075 } else {
5076 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5077 if (reduced_clock)
5078 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5079 reduced_clock->m2;
5080 }
5081
5082 I915_WRITE(FP0(pipe), fp);
5083
5084 intel_crtc->lowfreq_avail = false;
5085 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5086 reduced_clock && i915_powersave) {
5087 I915_WRITE(FP1(pipe), fp2);
5088 intel_crtc->lowfreq_avail = true;
5089 } else {
5090 I915_WRITE(FP1(pipe), fp);
5091 }
5092 }
5093
5094 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5095 struct drm_display_mode *mode,
5096 struct drm_display_mode *adjusted_mode,
5097 int x, int y,
5098 struct drm_framebuffer *old_fb)
5099 {
5100 struct drm_device *dev = crtc->dev;
5101 struct drm_i915_private *dev_priv = dev->dev_private;
5102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5103 int pipe = intel_crtc->pipe;
5104 int plane = intel_crtc->plane;
5105 int refclk, num_connectors = 0;
5106 intel_clock_t clock, reduced_clock;
5107 u32 dpll, dspcntr, pipeconf, vsyncshift;
5108 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5109 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5110 struct drm_mode_config *mode_config = &dev->mode_config;
5111 struct intel_encoder *encoder;
5112 const intel_limit_t *limit;
5113 int ret;
5114 u32 temp;
5115 u32 lvds_sync = 0;
5116
5117 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5118 if (encoder->base.crtc != crtc)
5119 continue;
5120
5121 switch (encoder->type) {
5122 case INTEL_OUTPUT_LVDS:
5123 is_lvds = true;
5124 break;
5125 case INTEL_OUTPUT_SDVO:
5126 case INTEL_OUTPUT_HDMI:
5127 is_sdvo = true;
5128 if (encoder->needs_tv_clock)
5129 is_tv = true;
5130 break;
5131 case INTEL_OUTPUT_DVO:
5132 is_dvo = true;
5133 break;
5134 case INTEL_OUTPUT_TVOUT:
5135 is_tv = true;
5136 break;
5137 case INTEL_OUTPUT_ANALOG:
5138 is_crt = true;
5139 break;
5140 case INTEL_OUTPUT_DISPLAYPORT:
5141 is_dp = true;
5142 break;
5143 }
5144
5145 num_connectors++;
5146 }
5147
5148 refclk = i9xx_get_refclk(crtc, num_connectors);
5149
5150 /*
5151 * Returns a set of divisors for the desired target clock with the given
5152 * refclk, or FALSE. The returned values represent the clock equation:
5153 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5154 */
5155 limit = intel_limit(crtc, refclk);
5156 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5157 &clock);
5158 if (!ok) {
5159 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5160 return -EINVAL;
5161 }
5162
5163 /* Ensure that the cursor is valid for the new mode before changing... */
5164 intel_crtc_update_cursor(crtc, true);
5165
5166 if (is_lvds && dev_priv->lvds_downclock_avail) {
5167 /*
5168 * Ensure we match the reduced clock's P to the target clock.
5169 * If the clocks don't match, we can't switch the display clock
5170 * by using the FP0/FP1. In such case we will disable the LVDS
5171 * downclock feature.
5172 */
5173 has_reduced_clock = limit->find_pll(limit, crtc,
5174 dev_priv->lvds_downclock,
5175 refclk,
5176 &clock,
5177 &reduced_clock);
5178 }
5179
5180 if (is_sdvo && is_tv)
5181 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5182
5183 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5184 &reduced_clock : NULL);
5185
5186 dpll = DPLL_VGA_MODE_DIS;
5187
5188 if (!IS_GEN2(dev)) {
5189 if (is_lvds)
5190 dpll |= DPLLB_MODE_LVDS;
5191 else
5192 dpll |= DPLLB_MODE_DAC_SERIAL;
5193 if (is_sdvo) {
5194 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5195 if (pixel_multiplier > 1) {
5196 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5197 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5198 }
5199 dpll |= DPLL_DVO_HIGH_SPEED;
5200 }
5201 if (is_dp)
5202 dpll |= DPLL_DVO_HIGH_SPEED;
5203
5204 /* compute bitmask from p1 value */
5205 if (IS_PINEVIEW(dev))
5206 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5207 else {
5208 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5209 if (IS_G4X(dev) && has_reduced_clock)
5210 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5211 }
5212 switch (clock.p2) {
5213 case 5:
5214 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5215 break;
5216 case 7:
5217 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5218 break;
5219 case 10:
5220 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5221 break;
5222 case 14:
5223 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5224 break;
5225 }
5226 if (INTEL_INFO(dev)->gen >= 4)
5227 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5228 } else {
5229 if (is_lvds) {
5230 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5231 } else {
5232 if (clock.p1 == 2)
5233 dpll |= PLL_P1_DIVIDE_BY_TWO;
5234 else
5235 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5236 if (clock.p2 == 4)
5237 dpll |= PLL_P2_DIVIDE_BY_4;
5238 }
5239 }
5240
5241 if (is_sdvo && is_tv)
5242 dpll |= PLL_REF_INPUT_TVCLKINBC;
5243 else if (is_tv)
5244 /* XXX: just matching BIOS for now */
5245 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5246 dpll |= 3;
5247 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5248 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5249 else
5250 dpll |= PLL_REF_INPUT_DREFCLK;
5251
5252 /* setup pipeconf */
5253 pipeconf = I915_READ(PIPECONF(pipe));
5254
5255 /* Set up the display plane register */
5256 dspcntr = DISPPLANE_GAMMA_ENABLE;
5257
5258 if (pipe == 0)
5259 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5260 else
5261 dspcntr |= DISPPLANE_SEL_PIPE_B;
5262
5263 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5264 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5265 * core speed.
5266 *
5267 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5268 * pipe == 0 check?
5269 */
5270 if (mode->clock >
5271 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5272 pipeconf |= PIPECONF_DOUBLE_WIDE;
5273 else
5274 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5275 }
5276
5277 /* default to 8bpc */
5278 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5279 if (is_dp) {
5280 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5281 pipeconf |= PIPECONF_BPP_6 |
5282 PIPECONF_DITHER_EN |
5283 PIPECONF_DITHER_TYPE_SP;
5284 }
5285 }
5286
5287 dpll |= DPLL_VCO_ENABLE;
5288
5289 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5290 drm_mode_debug_printmodeline(mode);
5291
5292 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5293
5294 POSTING_READ(DPLL(pipe));
5295 udelay(150);
5296
5297 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5298 * This is an exception to the general rule that mode_set doesn't turn
5299 * things on.
5300 */
5301 if (is_lvds) {
5302 temp = I915_READ(LVDS);
5303 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5304 if (pipe == 1) {
5305 temp |= LVDS_PIPEB_SELECT;
5306 } else {
5307 temp &= ~LVDS_PIPEB_SELECT;
5308 }
5309 /* set the corresponsding LVDS_BORDER bit */
5310 temp |= dev_priv->lvds_border_bits;
5311 /* Set the B0-B3 data pairs corresponding to whether we're going to
5312 * set the DPLLs for dual-channel mode or not.
5313 */
5314 if (clock.p2 == 7)
5315 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5316 else
5317 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5318
5319 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5320 * appropriately here, but we need to look more thoroughly into how
5321 * panels behave in the two modes.
5322 */
5323 /* set the dithering flag on LVDS as needed */
5324 if (INTEL_INFO(dev)->gen >= 4) {
5325 if (dev_priv->lvds_dither)
5326 temp |= LVDS_ENABLE_DITHER;
5327 else
5328 temp &= ~LVDS_ENABLE_DITHER;
5329 }
5330 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5331 lvds_sync |= LVDS_HSYNC_POLARITY;
5332 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5333 lvds_sync |= LVDS_VSYNC_POLARITY;
5334 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5335 != lvds_sync) {
5336 char flags[2] = "-+";
5337 DRM_INFO("Changing LVDS panel from "
5338 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5339 flags[!(temp & LVDS_HSYNC_POLARITY)],
5340 flags[!(temp & LVDS_VSYNC_POLARITY)],
5341 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5342 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5343 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5344 temp |= lvds_sync;
5345 }
5346 I915_WRITE(LVDS, temp);
5347 }
5348
5349 if (is_dp) {
5350 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5351 }
5352
5353 I915_WRITE(DPLL(pipe), dpll);
5354
5355 /* Wait for the clocks to stabilize. */
5356 POSTING_READ(DPLL(pipe));
5357 udelay(150);
5358
5359 if (INTEL_INFO(dev)->gen >= 4) {
5360 temp = 0;
5361 if (is_sdvo) {
5362 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5363 if (temp > 1)
5364 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5365 else
5366 temp = 0;
5367 }
5368 I915_WRITE(DPLL_MD(pipe), temp);
5369 } else {
5370 /* The pixel multiplier can only be updated once the
5371 * DPLL is enabled and the clocks are stable.
5372 *
5373 * So write it again.
5374 */
5375 I915_WRITE(DPLL(pipe), dpll);
5376 }
5377
5378 if (HAS_PIPE_CXSR(dev)) {
5379 if (intel_crtc->lowfreq_avail) {
5380 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5381 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5382 } else {
5383 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5384 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5385 }
5386 }
5387
5388 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5389 if (!IS_GEN2(dev) &&
5390 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5391 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5392 /* the chip adds 2 halflines automatically */
5393 adjusted_mode->crtc_vtotal -= 1;
5394 adjusted_mode->crtc_vblank_end -= 1;
5395 vsyncshift = adjusted_mode->crtc_hsync_start
5396 - adjusted_mode->crtc_htotal/2;
5397 } else {
5398 pipeconf |= PIPECONF_PROGRESSIVE;
5399 vsyncshift = 0;
5400 }
5401
5402 if (!IS_GEN3(dev))
5403 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5404
5405 I915_WRITE(HTOTAL(pipe),
5406 (adjusted_mode->crtc_hdisplay - 1) |
5407 ((adjusted_mode->crtc_htotal - 1) << 16));
5408 I915_WRITE(HBLANK(pipe),
5409 (adjusted_mode->crtc_hblank_start - 1) |
5410 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5411 I915_WRITE(HSYNC(pipe),
5412 (adjusted_mode->crtc_hsync_start - 1) |
5413 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5414
5415 I915_WRITE(VTOTAL(pipe),
5416 (adjusted_mode->crtc_vdisplay - 1) |
5417 ((adjusted_mode->crtc_vtotal - 1) << 16));
5418 I915_WRITE(VBLANK(pipe),
5419 (adjusted_mode->crtc_vblank_start - 1) |
5420 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5421 I915_WRITE(VSYNC(pipe),
5422 (adjusted_mode->crtc_vsync_start - 1) |
5423 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5424
5425 /* pipesrc and dspsize control the size that is scaled from,
5426 * which should always be the user's requested size.
5427 */
5428 I915_WRITE(DSPSIZE(plane),
5429 ((mode->vdisplay - 1) << 16) |
5430 (mode->hdisplay - 1));
5431 I915_WRITE(DSPPOS(plane), 0);
5432 I915_WRITE(PIPESRC(pipe),
5433 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5434
5435 I915_WRITE(PIPECONF(pipe), pipeconf);
5436 POSTING_READ(PIPECONF(pipe));
5437 intel_enable_pipe(dev_priv, pipe, false);
5438
5439 intel_wait_for_vblank(dev, pipe);
5440
5441 I915_WRITE(DSPCNTR(plane), dspcntr);
5442 POSTING_READ(DSPCNTR(plane));
5443 intel_enable_plane(dev_priv, plane, pipe);
5444
5445 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5446
5447 intel_update_watermarks(dev);
5448
5449 return ret;
5450 }
5451
5452 /*
5453 * Initialize reference clocks when the driver loads
5454 */
5455 void ironlake_init_pch_refclk(struct drm_device *dev)
5456 {
5457 struct drm_i915_private *dev_priv = dev->dev_private;
5458 struct drm_mode_config *mode_config = &dev->mode_config;
5459 struct intel_encoder *encoder;
5460 u32 temp;
5461 bool has_lvds = false;
5462 bool has_cpu_edp = false;
5463 bool has_pch_edp = false;
5464 bool has_panel = false;
5465 bool has_ck505 = false;
5466 bool can_ssc = false;
5467
5468 /* We need to take the global config into account */
5469 list_for_each_entry(encoder, &mode_config->encoder_list,
5470 base.head) {
5471 switch (encoder->type) {
5472 case INTEL_OUTPUT_LVDS:
5473 has_panel = true;
5474 has_lvds = true;
5475 break;
5476 case INTEL_OUTPUT_EDP:
5477 has_panel = true;
5478 if (intel_encoder_is_pch_edp(&encoder->base))
5479 has_pch_edp = true;
5480 else
5481 has_cpu_edp = true;
5482 break;
5483 }
5484 }
5485
5486 if (HAS_PCH_IBX(dev)) {
5487 has_ck505 = dev_priv->display_clock_mode;
5488 can_ssc = has_ck505;
5489 } else {
5490 has_ck505 = false;
5491 can_ssc = true;
5492 }
5493
5494 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5495 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5496 has_ck505);
5497
5498 /* Ironlake: try to setup display ref clock before DPLL
5499 * enabling. This is only under driver's control after
5500 * PCH B stepping, previous chipset stepping should be
5501 * ignoring this setting.
5502 */
5503 temp = I915_READ(PCH_DREF_CONTROL);
5504 /* Always enable nonspread source */
5505 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5506
5507 if (has_ck505)
5508 temp |= DREF_NONSPREAD_CK505_ENABLE;
5509 else
5510 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5511
5512 if (has_panel) {
5513 temp &= ~DREF_SSC_SOURCE_MASK;
5514 temp |= DREF_SSC_SOURCE_ENABLE;
5515
5516 /* SSC must be turned on before enabling the CPU output */
5517 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5518 DRM_DEBUG_KMS("Using SSC on panel\n");
5519 temp |= DREF_SSC1_ENABLE;
5520 }
5521
5522 /* Get SSC going before enabling the outputs */
5523 I915_WRITE(PCH_DREF_CONTROL, temp);
5524 POSTING_READ(PCH_DREF_CONTROL);
5525 udelay(200);
5526
5527 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5528
5529 /* Enable CPU source on CPU attached eDP */
5530 if (has_cpu_edp) {
5531 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5532 DRM_DEBUG_KMS("Using SSC on eDP\n");
5533 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5534 }
5535 else
5536 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5537 } else
5538 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5539
5540 I915_WRITE(PCH_DREF_CONTROL, temp);
5541 POSTING_READ(PCH_DREF_CONTROL);
5542 udelay(200);
5543 } else {
5544 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5545
5546 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5547
5548 /* Turn off CPU output */
5549 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5550
5551 I915_WRITE(PCH_DREF_CONTROL, temp);
5552 POSTING_READ(PCH_DREF_CONTROL);
5553 udelay(200);
5554
5555 /* Turn off the SSC source */
5556 temp &= ~DREF_SSC_SOURCE_MASK;
5557 temp |= DREF_SSC_SOURCE_DISABLE;
5558
5559 /* Turn off SSC1 */
5560 temp &= ~ DREF_SSC1_ENABLE;
5561
5562 I915_WRITE(PCH_DREF_CONTROL, temp);
5563 POSTING_READ(PCH_DREF_CONTROL);
5564 udelay(200);
5565 }
5566 }
5567
5568 static int ironlake_get_refclk(struct drm_crtc *crtc)
5569 {
5570 struct drm_device *dev = crtc->dev;
5571 struct drm_i915_private *dev_priv = dev->dev_private;
5572 struct intel_encoder *encoder;
5573 struct drm_mode_config *mode_config = &dev->mode_config;
5574 struct intel_encoder *edp_encoder = NULL;
5575 int num_connectors = 0;
5576 bool is_lvds = false;
5577
5578 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5579 if (encoder->base.crtc != crtc)
5580 continue;
5581
5582 switch (encoder->type) {
5583 case INTEL_OUTPUT_LVDS:
5584 is_lvds = true;
5585 break;
5586 case INTEL_OUTPUT_EDP:
5587 edp_encoder = encoder;
5588 break;
5589 }
5590 num_connectors++;
5591 }
5592
5593 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5594 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5595 dev_priv->lvds_ssc_freq);
5596 return dev_priv->lvds_ssc_freq * 1000;
5597 }
5598
5599 return 120000;
5600 }
5601
5602 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5603 struct drm_display_mode *mode,
5604 struct drm_display_mode *adjusted_mode,
5605 int x, int y,
5606 struct drm_framebuffer *old_fb)
5607 {
5608 struct drm_device *dev = crtc->dev;
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5611 int pipe = intel_crtc->pipe;
5612 int plane = intel_crtc->plane;
5613 int refclk, num_connectors = 0;
5614 intel_clock_t clock, reduced_clock;
5615 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5616 bool ok, has_reduced_clock = false, is_sdvo = false;
5617 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5618 struct intel_encoder *has_edp_encoder = NULL;
5619 struct drm_mode_config *mode_config = &dev->mode_config;
5620 struct intel_encoder *encoder;
5621 const intel_limit_t *limit;
5622 int ret;
5623 struct fdi_m_n m_n = {0};
5624 u32 temp;
5625 u32 lvds_sync = 0;
5626 int target_clock, pixel_multiplier, lane, link_bw, factor;
5627 unsigned int pipe_bpp;
5628 bool dither;
5629
5630 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5631 if (encoder->base.crtc != crtc)
5632 continue;
5633
5634 switch (encoder->type) {
5635 case INTEL_OUTPUT_LVDS:
5636 is_lvds = true;
5637 break;
5638 case INTEL_OUTPUT_SDVO:
5639 case INTEL_OUTPUT_HDMI:
5640 is_sdvo = true;
5641 if (encoder->needs_tv_clock)
5642 is_tv = true;
5643 break;
5644 case INTEL_OUTPUT_TVOUT:
5645 is_tv = true;
5646 break;
5647 case INTEL_OUTPUT_ANALOG:
5648 is_crt = true;
5649 break;
5650 case INTEL_OUTPUT_DISPLAYPORT:
5651 is_dp = true;
5652 break;
5653 case INTEL_OUTPUT_EDP:
5654 has_edp_encoder = encoder;
5655 break;
5656 }
5657
5658 num_connectors++;
5659 }
5660
5661 refclk = ironlake_get_refclk(crtc);
5662
5663 /*
5664 * Returns a set of divisors for the desired target clock with the given
5665 * refclk, or FALSE. The returned values represent the clock equation:
5666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5667 */
5668 limit = intel_limit(crtc, refclk);
5669 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5670 &clock);
5671 if (!ok) {
5672 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5673 return -EINVAL;
5674 }
5675
5676 /* Ensure that the cursor is valid for the new mode before changing... */
5677 intel_crtc_update_cursor(crtc, true);
5678
5679 if (is_lvds && dev_priv->lvds_downclock_avail) {
5680 /*
5681 * Ensure we match the reduced clock's P to the target clock.
5682 * If the clocks don't match, we can't switch the display clock
5683 * by using the FP0/FP1. In such case we will disable the LVDS
5684 * downclock feature.
5685 */
5686 has_reduced_clock = limit->find_pll(limit, crtc,
5687 dev_priv->lvds_downclock,
5688 refclk,
5689 &clock,
5690 &reduced_clock);
5691 }
5692 /* SDVO TV has fixed PLL values depend on its clock range,
5693 this mirrors vbios setting. */
5694 if (is_sdvo && is_tv) {
5695 if (adjusted_mode->clock >= 100000
5696 && adjusted_mode->clock < 140500) {
5697 clock.p1 = 2;
5698 clock.p2 = 10;
5699 clock.n = 3;
5700 clock.m1 = 16;
5701 clock.m2 = 8;
5702 } else if (adjusted_mode->clock >= 140500
5703 && adjusted_mode->clock <= 200000) {
5704 clock.p1 = 1;
5705 clock.p2 = 10;
5706 clock.n = 6;
5707 clock.m1 = 12;
5708 clock.m2 = 8;
5709 }
5710 }
5711
5712 /* FDI link */
5713 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5714 lane = 0;
5715 /* CPU eDP doesn't require FDI link, so just set DP M/N
5716 according to current link config */
5717 if (has_edp_encoder &&
5718 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5719 target_clock = mode->clock;
5720 intel_edp_link_config(has_edp_encoder,
5721 &lane, &link_bw);
5722 } else {
5723 /* [e]DP over FDI requires target mode clock
5724 instead of link clock */
5725 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5726 target_clock = mode->clock;
5727 else
5728 target_clock = adjusted_mode->clock;
5729
5730 /* FDI is a binary signal running at ~2.7GHz, encoding
5731 * each output octet as 10 bits. The actual frequency
5732 * is stored as a divider into a 100MHz clock, and the
5733 * mode pixel clock is stored in units of 1KHz.
5734 * Hence the bw of each lane in terms of the mode signal
5735 * is:
5736 */
5737 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5738 }
5739
5740 /* determine panel color depth */
5741 temp = I915_READ(PIPECONF(pipe));
5742 temp &= ~PIPE_BPC_MASK;
5743 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5744 switch (pipe_bpp) {
5745 case 18:
5746 temp |= PIPE_6BPC;
5747 break;
5748 case 24:
5749 temp |= PIPE_8BPC;
5750 break;
5751 case 30:
5752 temp |= PIPE_10BPC;
5753 break;
5754 case 36:
5755 temp |= PIPE_12BPC;
5756 break;
5757 default:
5758 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5759 pipe_bpp);
5760 temp |= PIPE_8BPC;
5761 pipe_bpp = 24;
5762 break;
5763 }
5764
5765 intel_crtc->bpp = pipe_bpp;
5766 I915_WRITE(PIPECONF(pipe), temp);
5767
5768 if (!lane) {
5769 /*
5770 * Account for spread spectrum to avoid
5771 * oversubscribing the link. Max center spread
5772 * is 2.5%; use 5% for safety's sake.
5773 */
5774 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5775 lane = bps / (link_bw * 8) + 1;
5776 }
5777
5778 intel_crtc->fdi_lanes = lane;
5779
5780 if (pixel_multiplier > 1)
5781 link_bw *= pixel_multiplier;
5782 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5783 &m_n);
5784
5785 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5786 if (has_reduced_clock)
5787 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5788 reduced_clock.m2;
5789
5790 /* Enable autotuning of the PLL clock (if permissible) */
5791 factor = 21;
5792 if (is_lvds) {
5793 if ((intel_panel_use_ssc(dev_priv) &&
5794 dev_priv->lvds_ssc_freq == 100) ||
5795 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5796 factor = 25;
5797 } else if (is_sdvo && is_tv)
5798 factor = 20;
5799
5800 if (clock.m < factor * clock.n)
5801 fp |= FP_CB_TUNE;
5802
5803 dpll = 0;
5804
5805 if (is_lvds)
5806 dpll |= DPLLB_MODE_LVDS;
5807 else
5808 dpll |= DPLLB_MODE_DAC_SERIAL;
5809 if (is_sdvo) {
5810 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5811 if (pixel_multiplier > 1) {
5812 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5813 }
5814 dpll |= DPLL_DVO_HIGH_SPEED;
5815 }
5816 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5817 dpll |= DPLL_DVO_HIGH_SPEED;
5818
5819 /* compute bitmask from p1 value */
5820 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5821 /* also FPA1 */
5822 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5823
5824 switch (clock.p2) {
5825 case 5:
5826 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5827 break;
5828 case 7:
5829 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5830 break;
5831 case 10:
5832 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5833 break;
5834 case 14:
5835 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5836 break;
5837 }
5838
5839 if (is_sdvo && is_tv)
5840 dpll |= PLL_REF_INPUT_TVCLKINBC;
5841 else if (is_tv)
5842 /* XXX: just matching BIOS for now */
5843 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5844 dpll |= 3;
5845 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5846 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5847 else
5848 dpll |= PLL_REF_INPUT_DREFCLK;
5849
5850 /* setup pipeconf */
5851 pipeconf = I915_READ(PIPECONF(pipe));
5852
5853 /* Set up the display plane register */
5854 dspcntr = DISPPLANE_GAMMA_ENABLE;
5855
5856 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5857 drm_mode_debug_printmodeline(mode);
5858
5859 /* PCH eDP needs FDI, but CPU eDP does not */
5860 if (!intel_crtc->no_pll) {
5861 if (!has_edp_encoder ||
5862 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5863 I915_WRITE(PCH_FP0(pipe), fp);
5864 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5865
5866 POSTING_READ(PCH_DPLL(pipe));
5867 udelay(150);
5868 }
5869 } else {
5870 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5871 fp == I915_READ(PCH_FP0(0))) {
5872 intel_crtc->use_pll_a = true;
5873 DRM_DEBUG_KMS("using pipe a dpll\n");
5874 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5875 fp == I915_READ(PCH_FP0(1))) {
5876 intel_crtc->use_pll_a = false;
5877 DRM_DEBUG_KMS("using pipe b dpll\n");
5878 } else {
5879 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5880 return -EINVAL;
5881 }
5882 }
5883
5884 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5885 * This is an exception to the general rule that mode_set doesn't turn
5886 * things on.
5887 */
5888 if (is_lvds) {
5889 temp = I915_READ(PCH_LVDS);
5890 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5891 if (HAS_PCH_CPT(dev)) {
5892 temp &= ~PORT_TRANS_SEL_MASK;
5893 temp |= PORT_TRANS_SEL_CPT(pipe);
5894 } else {
5895 if (pipe == 1)
5896 temp |= LVDS_PIPEB_SELECT;
5897 else
5898 temp &= ~LVDS_PIPEB_SELECT;
5899 }
5900
5901 /* set the corresponsding LVDS_BORDER bit */
5902 temp |= dev_priv->lvds_border_bits;
5903 /* Set the B0-B3 data pairs corresponding to whether we're going to
5904 * set the DPLLs for dual-channel mode or not.
5905 */
5906 if (clock.p2 == 7)
5907 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5908 else
5909 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5910
5911 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5912 * appropriately here, but we need to look more thoroughly into how
5913 * panels behave in the two modes.
5914 */
5915 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5916 lvds_sync |= LVDS_HSYNC_POLARITY;
5917 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5918 lvds_sync |= LVDS_VSYNC_POLARITY;
5919 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5920 != lvds_sync) {
5921 char flags[2] = "-+";
5922 DRM_INFO("Changing LVDS panel from "
5923 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5924 flags[!(temp & LVDS_HSYNC_POLARITY)],
5925 flags[!(temp & LVDS_VSYNC_POLARITY)],
5926 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5927 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5928 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5929 temp |= lvds_sync;
5930 }
5931 I915_WRITE(PCH_LVDS, temp);
5932 }
5933
5934 pipeconf &= ~PIPECONF_DITHER_EN;
5935 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5936 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5937 pipeconf |= PIPECONF_DITHER_EN;
5938 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5939 }
5940 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5941 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5942 } else {
5943 /* For non-DP output, clear any trans DP clock recovery setting.*/
5944 I915_WRITE(TRANSDATA_M1(pipe), 0);
5945 I915_WRITE(TRANSDATA_N1(pipe), 0);
5946 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5947 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5948 }
5949
5950 if (!intel_crtc->no_pll &&
5951 (!has_edp_encoder ||
5952 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5953 I915_WRITE(PCH_DPLL(pipe), dpll);
5954
5955 /* Wait for the clocks to stabilize. */
5956 POSTING_READ(PCH_DPLL(pipe));
5957 udelay(150);
5958
5959 /* The pixel multiplier can only be updated once the
5960 * DPLL is enabled and the clocks are stable.
5961 *
5962 * So write it again.
5963 */
5964 I915_WRITE(PCH_DPLL(pipe), dpll);
5965 }
5966
5967 intel_crtc->lowfreq_avail = false;
5968 if (!intel_crtc->no_pll) {
5969 if (is_lvds && has_reduced_clock && i915_powersave) {
5970 I915_WRITE(PCH_FP1(pipe), fp2);
5971 intel_crtc->lowfreq_avail = true;
5972 if (HAS_PIPE_CXSR(dev)) {
5973 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5974 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5975 }
5976 } else {
5977 I915_WRITE(PCH_FP1(pipe), fp);
5978 if (HAS_PIPE_CXSR(dev)) {
5979 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5980 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5981 }
5982 }
5983 }
5984
5985 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5986 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5987 pipeconf |= PIPECONF_INTERLACED_ILK;
5988 /* the chip adds 2 halflines automatically */
5989 adjusted_mode->crtc_vtotal -= 1;
5990 adjusted_mode->crtc_vblank_end -= 1;
5991 I915_WRITE(VSYNCSHIFT(pipe),
5992 adjusted_mode->crtc_hsync_start
5993 - adjusted_mode->crtc_htotal/2);
5994 } else {
5995 pipeconf |= PIPECONF_PROGRESSIVE;
5996 I915_WRITE(VSYNCSHIFT(pipe), 0);
5997 }
5998
5999 I915_WRITE(HTOTAL(pipe),
6000 (adjusted_mode->crtc_hdisplay - 1) |
6001 ((adjusted_mode->crtc_htotal - 1) << 16));
6002 I915_WRITE(HBLANK(pipe),
6003 (adjusted_mode->crtc_hblank_start - 1) |
6004 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6005 I915_WRITE(HSYNC(pipe),
6006 (adjusted_mode->crtc_hsync_start - 1) |
6007 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6008
6009 I915_WRITE(VTOTAL(pipe),
6010 (adjusted_mode->crtc_vdisplay - 1) |
6011 ((adjusted_mode->crtc_vtotal - 1) << 16));
6012 I915_WRITE(VBLANK(pipe),
6013 (adjusted_mode->crtc_vblank_start - 1) |
6014 ((adjusted_mode->crtc_vblank_end - 1) << 16));
6015 I915_WRITE(VSYNC(pipe),
6016 (adjusted_mode->crtc_vsync_start - 1) |
6017 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6018
6019 /* pipesrc controls the size that is scaled from, which should
6020 * always be the user's requested size.
6021 */
6022 I915_WRITE(PIPESRC(pipe),
6023 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6024
6025 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6026 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6027 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6028 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6029
6030 if (has_edp_encoder &&
6031 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6032 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6033 }
6034
6035 I915_WRITE(PIPECONF(pipe), pipeconf);
6036 POSTING_READ(PIPECONF(pipe));
6037
6038 intel_wait_for_vblank(dev, pipe);
6039
6040 I915_WRITE(DSPCNTR(plane), dspcntr);
6041 POSTING_READ(DSPCNTR(plane));
6042
6043 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6044
6045 intel_update_watermarks(dev);
6046
6047 return ret;
6048 }
6049
6050 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6051 struct drm_display_mode *mode,
6052 struct drm_display_mode *adjusted_mode,
6053 int x, int y,
6054 struct drm_framebuffer *old_fb)
6055 {
6056 struct drm_device *dev = crtc->dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059 int pipe = intel_crtc->pipe;
6060 int ret;
6061
6062 drm_vblank_pre_modeset(dev, pipe);
6063
6064 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6065 x, y, old_fb);
6066 drm_vblank_post_modeset(dev, pipe);
6067
6068 if (ret)
6069 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6070 else
6071 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6072
6073 return ret;
6074 }
6075
6076 static bool intel_eld_uptodate(struct drm_connector *connector,
6077 int reg_eldv, uint32_t bits_eldv,
6078 int reg_elda, uint32_t bits_elda,
6079 int reg_edid)
6080 {
6081 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6082 uint8_t *eld = connector->eld;
6083 uint32_t i;
6084
6085 i = I915_READ(reg_eldv);
6086 i &= bits_eldv;
6087
6088 if (!eld[0])
6089 return !i;
6090
6091 if (!i)
6092 return false;
6093
6094 i = I915_READ(reg_elda);
6095 i &= ~bits_elda;
6096 I915_WRITE(reg_elda, i);
6097
6098 for (i = 0; i < eld[2]; i++)
6099 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6100 return false;
6101
6102 return true;
6103 }
6104
6105 static void g4x_write_eld(struct drm_connector *connector,
6106 struct drm_crtc *crtc)
6107 {
6108 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6109 uint8_t *eld = connector->eld;
6110 uint32_t eldv;
6111 uint32_t len;
6112 uint32_t i;
6113
6114 i = I915_READ(G4X_AUD_VID_DID);
6115
6116 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6117 eldv = G4X_ELDV_DEVCL_DEVBLC;
6118 else
6119 eldv = G4X_ELDV_DEVCTG;
6120
6121 if (intel_eld_uptodate(connector,
6122 G4X_AUD_CNTL_ST, eldv,
6123 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6124 G4X_HDMIW_HDMIEDID))
6125 return;
6126
6127 i = I915_READ(G4X_AUD_CNTL_ST);
6128 i &= ~(eldv | G4X_ELD_ADDR);
6129 len = (i >> 9) & 0x1f; /* ELD buffer size */
6130 I915_WRITE(G4X_AUD_CNTL_ST, i);
6131
6132 if (!eld[0])
6133 return;
6134
6135 len = min_t(uint8_t, eld[2], len);
6136 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6137 for (i = 0; i < len; i++)
6138 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6139
6140 i = I915_READ(G4X_AUD_CNTL_ST);
6141 i |= eldv;
6142 I915_WRITE(G4X_AUD_CNTL_ST, i);
6143 }
6144
6145 static void ironlake_write_eld(struct drm_connector *connector,
6146 struct drm_crtc *crtc)
6147 {
6148 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6149 uint8_t *eld = connector->eld;
6150 uint32_t eldv;
6151 uint32_t i;
6152 int len;
6153 int hdmiw_hdmiedid;
6154 int aud_config;
6155 int aud_cntl_st;
6156 int aud_cntrl_st2;
6157
6158 if (HAS_PCH_IBX(connector->dev)) {
6159 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6160 aud_config = IBX_AUD_CONFIG_A;
6161 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6162 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6163 } else {
6164 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6165 aud_config = CPT_AUD_CONFIG_A;
6166 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6167 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6168 }
6169
6170 i = to_intel_crtc(crtc)->pipe;
6171 hdmiw_hdmiedid += i * 0x100;
6172 aud_cntl_st += i * 0x100;
6173 aud_config += i * 0x100;
6174
6175 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6176
6177 i = I915_READ(aud_cntl_st);
6178 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6179 if (!i) {
6180 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6181 /* operate blindly on all ports */
6182 eldv = IBX_ELD_VALIDB;
6183 eldv |= IBX_ELD_VALIDB << 4;
6184 eldv |= IBX_ELD_VALIDB << 8;
6185 } else {
6186 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6187 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6188 }
6189
6190 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6191 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6192 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6193 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6194 } else
6195 I915_WRITE(aud_config, 0);
6196
6197 if (intel_eld_uptodate(connector,
6198 aud_cntrl_st2, eldv,
6199 aud_cntl_st, IBX_ELD_ADDRESS,
6200 hdmiw_hdmiedid))
6201 return;
6202
6203 i = I915_READ(aud_cntrl_st2);
6204 i &= ~eldv;
6205 I915_WRITE(aud_cntrl_st2, i);
6206
6207 if (!eld[0])
6208 return;
6209
6210 i = I915_READ(aud_cntl_st);
6211 i &= ~IBX_ELD_ADDRESS;
6212 I915_WRITE(aud_cntl_st, i);
6213
6214 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6215 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6216 for (i = 0; i < len; i++)
6217 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6218
6219 i = I915_READ(aud_cntrl_st2);
6220 i |= eldv;
6221 I915_WRITE(aud_cntrl_st2, i);
6222 }
6223
6224 void intel_write_eld(struct drm_encoder *encoder,
6225 struct drm_display_mode *mode)
6226 {
6227 struct drm_crtc *crtc = encoder->crtc;
6228 struct drm_connector *connector;
6229 struct drm_device *dev = encoder->dev;
6230 struct drm_i915_private *dev_priv = dev->dev_private;
6231
6232 connector = drm_select_eld(encoder, mode);
6233 if (!connector)
6234 return;
6235
6236 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6237 connector->base.id,
6238 drm_get_connector_name(connector),
6239 connector->encoder->base.id,
6240 drm_get_encoder_name(connector->encoder));
6241
6242 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6243
6244 if (dev_priv->display.write_eld)
6245 dev_priv->display.write_eld(connector, crtc);
6246 }
6247
6248 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6249 void intel_crtc_load_lut(struct drm_crtc *crtc)
6250 {
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254 int palreg = PALETTE(intel_crtc->pipe);
6255 int i;
6256
6257 /* The clocks have to be on to load the palette. */
6258 if (!crtc->enabled)
6259 return;
6260
6261 /* use legacy palette for Ironlake */
6262 if (HAS_PCH_SPLIT(dev))
6263 palreg = LGC_PALETTE(intel_crtc->pipe);
6264
6265 for (i = 0; i < 256; i++) {
6266 I915_WRITE(palreg + 4 * i,
6267 (intel_crtc->lut_r[i] << 16) |
6268 (intel_crtc->lut_g[i] << 8) |
6269 intel_crtc->lut_b[i]);
6270 }
6271 }
6272
6273 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6274 {
6275 struct drm_device *dev = crtc->dev;
6276 struct drm_i915_private *dev_priv = dev->dev_private;
6277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6278 bool visible = base != 0;
6279 u32 cntl;
6280
6281 if (intel_crtc->cursor_visible == visible)
6282 return;
6283
6284 cntl = I915_READ(_CURACNTR);
6285 if (visible) {
6286 /* On these chipsets we can only modify the base whilst
6287 * the cursor is disabled.
6288 */
6289 I915_WRITE(_CURABASE, base);
6290
6291 cntl &= ~(CURSOR_FORMAT_MASK);
6292 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6293 cntl |= CURSOR_ENABLE |
6294 CURSOR_GAMMA_ENABLE |
6295 CURSOR_FORMAT_ARGB;
6296 } else
6297 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6298 I915_WRITE(_CURACNTR, cntl);
6299
6300 intel_crtc->cursor_visible = visible;
6301 }
6302
6303 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6304 {
6305 struct drm_device *dev = crtc->dev;
6306 struct drm_i915_private *dev_priv = dev->dev_private;
6307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6308 int pipe = intel_crtc->pipe;
6309 bool visible = base != 0;
6310
6311 if (intel_crtc->cursor_visible != visible) {
6312 uint32_t cntl = I915_READ(CURCNTR(pipe));
6313 if (base) {
6314 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6315 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6316 cntl |= pipe << 28; /* Connect to correct pipe */
6317 } else {
6318 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6319 cntl |= CURSOR_MODE_DISABLE;
6320 }
6321 I915_WRITE(CURCNTR(pipe), cntl);
6322
6323 intel_crtc->cursor_visible = visible;
6324 }
6325 /* and commit changes on next vblank */
6326 I915_WRITE(CURBASE(pipe), base);
6327 }
6328
6329 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6330 {
6331 struct drm_device *dev = crtc->dev;
6332 struct drm_i915_private *dev_priv = dev->dev_private;
6333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334 int pipe = intel_crtc->pipe;
6335 bool visible = base != 0;
6336
6337 if (intel_crtc->cursor_visible != visible) {
6338 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6339 if (base) {
6340 cntl &= ~CURSOR_MODE;
6341 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6342 } else {
6343 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6344 cntl |= CURSOR_MODE_DISABLE;
6345 }
6346 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6347
6348 intel_crtc->cursor_visible = visible;
6349 }
6350 /* and commit changes on next vblank */
6351 I915_WRITE(CURBASE_IVB(pipe), base);
6352 }
6353
6354 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6355 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6356 bool on)
6357 {
6358 struct drm_device *dev = crtc->dev;
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 int pipe = intel_crtc->pipe;
6362 int x = intel_crtc->cursor_x;
6363 int y = intel_crtc->cursor_y;
6364 u32 base, pos;
6365 bool visible;
6366
6367 pos = 0;
6368
6369 if (on && crtc->enabled && crtc->fb) {
6370 base = intel_crtc->cursor_addr;
6371 if (x > (int) crtc->fb->width)
6372 base = 0;
6373
6374 if (y > (int) crtc->fb->height)
6375 base = 0;
6376 } else
6377 base = 0;
6378
6379 if (x < 0) {
6380 if (x + intel_crtc->cursor_width < 0)
6381 base = 0;
6382
6383 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6384 x = -x;
6385 }
6386 pos |= x << CURSOR_X_SHIFT;
6387
6388 if (y < 0) {
6389 if (y + intel_crtc->cursor_height < 0)
6390 base = 0;
6391
6392 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6393 y = -y;
6394 }
6395 pos |= y << CURSOR_Y_SHIFT;
6396
6397 visible = base != 0;
6398 if (!visible && !intel_crtc->cursor_visible)
6399 return;
6400
6401 if (IS_IVYBRIDGE(dev)) {
6402 I915_WRITE(CURPOS_IVB(pipe), pos);
6403 ivb_update_cursor(crtc, base);
6404 } else {
6405 I915_WRITE(CURPOS(pipe), pos);
6406 if (IS_845G(dev) || IS_I865G(dev))
6407 i845_update_cursor(crtc, base);
6408 else
6409 i9xx_update_cursor(crtc, base);
6410 }
6411
6412 if (visible)
6413 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6414 }
6415
6416 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6417 struct drm_file *file,
6418 uint32_t handle,
6419 uint32_t width, uint32_t height)
6420 {
6421 struct drm_device *dev = crtc->dev;
6422 struct drm_i915_private *dev_priv = dev->dev_private;
6423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6424 struct drm_i915_gem_object *obj;
6425 uint32_t addr;
6426 int ret;
6427
6428 DRM_DEBUG_KMS("\n");
6429
6430 /* if we want to turn off the cursor ignore width and height */
6431 if (!handle) {
6432 DRM_DEBUG_KMS("cursor off\n");
6433 addr = 0;
6434 obj = NULL;
6435 mutex_lock(&dev->struct_mutex);
6436 goto finish;
6437 }
6438
6439 /* Currently we only support 64x64 cursors */
6440 if (width != 64 || height != 64) {
6441 DRM_ERROR("we currently only support 64x64 cursors\n");
6442 return -EINVAL;
6443 }
6444
6445 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6446 if (&obj->base == NULL)
6447 return -ENOENT;
6448
6449 if (obj->base.size < width * height * 4) {
6450 DRM_ERROR("buffer is to small\n");
6451 ret = -ENOMEM;
6452 goto fail;
6453 }
6454
6455 /* we only need to pin inside GTT if cursor is non-phy */
6456 mutex_lock(&dev->struct_mutex);
6457 if (!dev_priv->info->cursor_needs_physical) {
6458 if (obj->tiling_mode) {
6459 DRM_ERROR("cursor cannot be tiled\n");
6460 ret = -EINVAL;
6461 goto fail_locked;
6462 }
6463
6464 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6465 if (ret) {
6466 DRM_ERROR("failed to move cursor bo into the GTT\n");
6467 goto fail_locked;
6468 }
6469
6470 ret = i915_gem_object_put_fence(obj);
6471 if (ret) {
6472 DRM_ERROR("failed to release fence for cursor");
6473 goto fail_unpin;
6474 }
6475
6476 addr = obj->gtt_offset;
6477 } else {
6478 int align = IS_I830(dev) ? 16 * 1024 : 256;
6479 ret = i915_gem_attach_phys_object(dev, obj,
6480 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6481 align);
6482 if (ret) {
6483 DRM_ERROR("failed to attach phys object\n");
6484 goto fail_locked;
6485 }
6486 addr = obj->phys_obj->handle->busaddr;
6487 }
6488
6489 if (IS_GEN2(dev))
6490 I915_WRITE(CURSIZE, (height << 12) | width);
6491
6492 finish:
6493 if (intel_crtc->cursor_bo) {
6494 if (dev_priv->info->cursor_needs_physical) {
6495 if (intel_crtc->cursor_bo != obj)
6496 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6497 } else
6498 i915_gem_object_unpin(intel_crtc->cursor_bo);
6499 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6500 }
6501
6502 mutex_unlock(&dev->struct_mutex);
6503
6504 intel_crtc->cursor_addr = addr;
6505 intel_crtc->cursor_bo = obj;
6506 intel_crtc->cursor_width = width;
6507 intel_crtc->cursor_height = height;
6508
6509 intel_crtc_update_cursor(crtc, true);
6510
6511 return 0;
6512 fail_unpin:
6513 i915_gem_object_unpin(obj);
6514 fail_locked:
6515 mutex_unlock(&dev->struct_mutex);
6516 fail:
6517 drm_gem_object_unreference_unlocked(&obj->base);
6518 return ret;
6519 }
6520
6521 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6522 {
6523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6524
6525 intel_crtc->cursor_x = x;
6526 intel_crtc->cursor_y = y;
6527
6528 intel_crtc_update_cursor(crtc, true);
6529
6530 return 0;
6531 }
6532
6533 /** Sets the color ramps on behalf of RandR */
6534 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6535 u16 blue, int regno)
6536 {
6537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6538
6539 intel_crtc->lut_r[regno] = red >> 8;
6540 intel_crtc->lut_g[regno] = green >> 8;
6541 intel_crtc->lut_b[regno] = blue >> 8;
6542 }
6543
6544 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6545 u16 *blue, int regno)
6546 {
6547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6548
6549 *red = intel_crtc->lut_r[regno] << 8;
6550 *green = intel_crtc->lut_g[regno] << 8;
6551 *blue = intel_crtc->lut_b[regno] << 8;
6552 }
6553
6554 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6555 u16 *blue, uint32_t start, uint32_t size)
6556 {
6557 int end = (start + size > 256) ? 256 : start + size, i;
6558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6559
6560 for (i = start; i < end; i++) {
6561 intel_crtc->lut_r[i] = red[i] >> 8;
6562 intel_crtc->lut_g[i] = green[i] >> 8;
6563 intel_crtc->lut_b[i] = blue[i] >> 8;
6564 }
6565
6566 intel_crtc_load_lut(crtc);
6567 }
6568
6569 /**
6570 * Get a pipe with a simple mode set on it for doing load-based monitor
6571 * detection.
6572 *
6573 * It will be up to the load-detect code to adjust the pipe as appropriate for
6574 * its requirements. The pipe will be connected to no other encoders.
6575 *
6576 * Currently this code will only succeed if there is a pipe with no encoders
6577 * configured for it. In the future, it could choose to temporarily disable
6578 * some outputs to free up a pipe for its use.
6579 *
6580 * \return crtc, or NULL if no pipes are available.
6581 */
6582
6583 /* VESA 640x480x72Hz mode to set on the pipe */
6584 static struct drm_display_mode load_detect_mode = {
6585 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6586 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6587 };
6588
6589 static struct drm_framebuffer *
6590 intel_framebuffer_create(struct drm_device *dev,
6591 struct drm_mode_fb_cmd2 *mode_cmd,
6592 struct drm_i915_gem_object *obj)
6593 {
6594 struct intel_framebuffer *intel_fb;
6595 int ret;
6596
6597 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6598 if (!intel_fb) {
6599 drm_gem_object_unreference_unlocked(&obj->base);
6600 return ERR_PTR(-ENOMEM);
6601 }
6602
6603 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6604 if (ret) {
6605 drm_gem_object_unreference_unlocked(&obj->base);
6606 kfree(intel_fb);
6607 return ERR_PTR(ret);
6608 }
6609
6610 return &intel_fb->base;
6611 }
6612
6613 static u32
6614 intel_framebuffer_pitch_for_width(int width, int bpp)
6615 {
6616 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6617 return ALIGN(pitch, 64);
6618 }
6619
6620 static u32
6621 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6622 {
6623 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6624 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6625 }
6626
6627 static struct drm_framebuffer *
6628 intel_framebuffer_create_for_mode(struct drm_device *dev,
6629 struct drm_display_mode *mode,
6630 int depth, int bpp)
6631 {
6632 struct drm_i915_gem_object *obj;
6633 struct drm_mode_fb_cmd2 mode_cmd;
6634
6635 obj = i915_gem_alloc_object(dev,
6636 intel_framebuffer_size_for_mode(mode, bpp));
6637 if (obj == NULL)
6638 return ERR_PTR(-ENOMEM);
6639
6640 mode_cmd.width = mode->hdisplay;
6641 mode_cmd.height = mode->vdisplay;
6642 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6643 bpp);
6644 mode_cmd.pixel_format = 0;
6645
6646 return intel_framebuffer_create(dev, &mode_cmd, obj);
6647 }
6648
6649 static struct drm_framebuffer *
6650 mode_fits_in_fbdev(struct drm_device *dev,
6651 struct drm_display_mode *mode)
6652 {
6653 struct drm_i915_private *dev_priv = dev->dev_private;
6654 struct drm_i915_gem_object *obj;
6655 struct drm_framebuffer *fb;
6656
6657 if (dev_priv->fbdev == NULL)
6658 return NULL;
6659
6660 obj = dev_priv->fbdev->ifb.obj;
6661 if (obj == NULL)
6662 return NULL;
6663
6664 fb = &dev_priv->fbdev->ifb.base;
6665 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6666 fb->bits_per_pixel))
6667 return NULL;
6668
6669 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6670 return NULL;
6671
6672 return fb;
6673 }
6674
6675 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6676 struct drm_connector *connector,
6677 struct drm_display_mode *mode,
6678 struct intel_load_detect_pipe *old)
6679 {
6680 struct intel_crtc *intel_crtc;
6681 struct drm_crtc *possible_crtc;
6682 struct drm_encoder *encoder = &intel_encoder->base;
6683 struct drm_crtc *crtc = NULL;
6684 struct drm_device *dev = encoder->dev;
6685 struct drm_framebuffer *old_fb;
6686 int i = -1;
6687
6688 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6689 connector->base.id, drm_get_connector_name(connector),
6690 encoder->base.id, drm_get_encoder_name(encoder));
6691
6692 /*
6693 * Algorithm gets a little messy:
6694 *
6695 * - if the connector already has an assigned crtc, use it (but make
6696 * sure it's on first)
6697 *
6698 * - try to find the first unused crtc that can drive this connector,
6699 * and use that if we find one
6700 */
6701
6702 /* See if we already have a CRTC for this connector */
6703 if (encoder->crtc) {
6704 crtc = encoder->crtc;
6705
6706 intel_crtc = to_intel_crtc(crtc);
6707 old->dpms_mode = intel_crtc->dpms_mode;
6708 old->load_detect_temp = false;
6709
6710 /* Make sure the crtc and connector are running */
6711 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6712 struct drm_encoder_helper_funcs *encoder_funcs;
6713 struct drm_crtc_helper_funcs *crtc_funcs;
6714
6715 crtc_funcs = crtc->helper_private;
6716 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6717
6718 encoder_funcs = encoder->helper_private;
6719 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6720 }
6721
6722 return true;
6723 }
6724
6725 /* Find an unused one (if possible) */
6726 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6727 i++;
6728 if (!(encoder->possible_crtcs & (1 << i)))
6729 continue;
6730 if (!possible_crtc->enabled) {
6731 crtc = possible_crtc;
6732 break;
6733 }
6734 }
6735
6736 /*
6737 * If we didn't find an unused CRTC, don't use any.
6738 */
6739 if (!crtc) {
6740 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6741 return false;
6742 }
6743
6744 encoder->crtc = crtc;
6745 connector->encoder = encoder;
6746
6747 intel_crtc = to_intel_crtc(crtc);
6748 old->dpms_mode = intel_crtc->dpms_mode;
6749 old->load_detect_temp = true;
6750 old->release_fb = NULL;
6751
6752 if (!mode)
6753 mode = &load_detect_mode;
6754
6755 old_fb = crtc->fb;
6756
6757 /* We need a framebuffer large enough to accommodate all accesses
6758 * that the plane may generate whilst we perform load detection.
6759 * We can not rely on the fbcon either being present (we get called
6760 * during its initialisation to detect all boot displays, or it may
6761 * not even exist) or that it is large enough to satisfy the
6762 * requested mode.
6763 */
6764 crtc->fb = mode_fits_in_fbdev(dev, mode);
6765 if (crtc->fb == NULL) {
6766 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6767 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6768 old->release_fb = crtc->fb;
6769 } else
6770 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6771 if (IS_ERR(crtc->fb)) {
6772 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6773 crtc->fb = old_fb;
6774 return false;
6775 }
6776
6777 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6778 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6779 if (old->release_fb)
6780 old->release_fb->funcs->destroy(old->release_fb);
6781 crtc->fb = old_fb;
6782 return false;
6783 }
6784
6785 /* let the connector get through one full cycle before testing */
6786 intel_wait_for_vblank(dev, intel_crtc->pipe);
6787
6788 return true;
6789 }
6790
6791 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6792 struct drm_connector *connector,
6793 struct intel_load_detect_pipe *old)
6794 {
6795 struct drm_encoder *encoder = &intel_encoder->base;
6796 struct drm_device *dev = encoder->dev;
6797 struct drm_crtc *crtc = encoder->crtc;
6798 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6799 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6800
6801 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6802 connector->base.id, drm_get_connector_name(connector),
6803 encoder->base.id, drm_get_encoder_name(encoder));
6804
6805 if (old->load_detect_temp) {
6806 connector->encoder = NULL;
6807 drm_helper_disable_unused_functions(dev);
6808
6809 if (old->release_fb)
6810 old->release_fb->funcs->destroy(old->release_fb);
6811
6812 return;
6813 }
6814
6815 /* Switch crtc and encoder back off if necessary */
6816 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6817 encoder_funcs->dpms(encoder, old->dpms_mode);
6818 crtc_funcs->dpms(crtc, old->dpms_mode);
6819 }
6820 }
6821
6822 /* Returns the clock of the currently programmed mode of the given pipe. */
6823 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6824 {
6825 struct drm_i915_private *dev_priv = dev->dev_private;
6826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6827 int pipe = intel_crtc->pipe;
6828 u32 dpll = I915_READ(DPLL(pipe));
6829 u32 fp;
6830 intel_clock_t clock;
6831
6832 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6833 fp = I915_READ(FP0(pipe));
6834 else
6835 fp = I915_READ(FP1(pipe));
6836
6837 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6838 if (IS_PINEVIEW(dev)) {
6839 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6840 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6841 } else {
6842 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6843 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6844 }
6845
6846 if (!IS_GEN2(dev)) {
6847 if (IS_PINEVIEW(dev))
6848 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6849 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6850 else
6851 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6852 DPLL_FPA01_P1_POST_DIV_SHIFT);
6853
6854 switch (dpll & DPLL_MODE_MASK) {
6855 case DPLLB_MODE_DAC_SERIAL:
6856 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6857 5 : 10;
6858 break;
6859 case DPLLB_MODE_LVDS:
6860 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6861 7 : 14;
6862 break;
6863 default:
6864 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6865 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6866 return 0;
6867 }
6868
6869 /* XXX: Handle the 100Mhz refclk */
6870 intel_clock(dev, 96000, &clock);
6871 } else {
6872 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6873
6874 if (is_lvds) {
6875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6876 DPLL_FPA01_P1_POST_DIV_SHIFT);
6877 clock.p2 = 14;
6878
6879 if ((dpll & PLL_REF_INPUT_MASK) ==
6880 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6881 /* XXX: might not be 66MHz */
6882 intel_clock(dev, 66000, &clock);
6883 } else
6884 intel_clock(dev, 48000, &clock);
6885 } else {
6886 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6887 clock.p1 = 2;
6888 else {
6889 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6890 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6891 }
6892 if (dpll & PLL_P2_DIVIDE_BY_4)
6893 clock.p2 = 4;
6894 else
6895 clock.p2 = 2;
6896
6897 intel_clock(dev, 48000, &clock);
6898 }
6899 }
6900
6901 /* XXX: It would be nice to validate the clocks, but we can't reuse
6902 * i830PllIsValid() because it relies on the xf86_config connector
6903 * configuration being accurate, which it isn't necessarily.
6904 */
6905
6906 return clock.dot;
6907 }
6908
6909 /** Returns the currently programmed mode of the given pipe. */
6910 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6911 struct drm_crtc *crtc)
6912 {
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6915 int pipe = intel_crtc->pipe;
6916 struct drm_display_mode *mode;
6917 int htot = I915_READ(HTOTAL(pipe));
6918 int hsync = I915_READ(HSYNC(pipe));
6919 int vtot = I915_READ(VTOTAL(pipe));
6920 int vsync = I915_READ(VSYNC(pipe));
6921
6922 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6923 if (!mode)
6924 return NULL;
6925
6926 mode->clock = intel_crtc_clock_get(dev, crtc);
6927 mode->hdisplay = (htot & 0xffff) + 1;
6928 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6929 mode->hsync_start = (hsync & 0xffff) + 1;
6930 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6931 mode->vdisplay = (vtot & 0xffff) + 1;
6932 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6933 mode->vsync_start = (vsync & 0xffff) + 1;
6934 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6935
6936 drm_mode_set_name(mode);
6937 drm_mode_set_crtcinfo(mode, 0);
6938
6939 return mode;
6940 }
6941
6942 #define GPU_IDLE_TIMEOUT 500 /* ms */
6943
6944 /* When this timer fires, we've been idle for awhile */
6945 static void intel_gpu_idle_timer(unsigned long arg)
6946 {
6947 struct drm_device *dev = (struct drm_device *)arg;
6948 drm_i915_private_t *dev_priv = dev->dev_private;
6949
6950 if (!list_empty(&dev_priv->mm.active_list)) {
6951 /* Still processing requests, so just re-arm the timer. */
6952 mod_timer(&dev_priv->idle_timer, jiffies +
6953 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6954 return;
6955 }
6956
6957 dev_priv->busy = false;
6958 queue_work(dev_priv->wq, &dev_priv->idle_work);
6959 }
6960
6961 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6962
6963 static void intel_crtc_idle_timer(unsigned long arg)
6964 {
6965 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6966 struct drm_crtc *crtc = &intel_crtc->base;
6967 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6968 struct intel_framebuffer *intel_fb;
6969
6970 intel_fb = to_intel_framebuffer(crtc->fb);
6971 if (intel_fb && intel_fb->obj->active) {
6972 /* The framebuffer is still being accessed by the GPU. */
6973 mod_timer(&intel_crtc->idle_timer, jiffies +
6974 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6975 return;
6976 }
6977
6978 intel_crtc->busy = false;
6979 queue_work(dev_priv->wq, &dev_priv->idle_work);
6980 }
6981
6982 static void intel_increase_pllclock(struct drm_crtc *crtc)
6983 {
6984 struct drm_device *dev = crtc->dev;
6985 drm_i915_private_t *dev_priv = dev->dev_private;
6986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6987 int pipe = intel_crtc->pipe;
6988 int dpll_reg = DPLL(pipe);
6989 int dpll;
6990
6991 if (HAS_PCH_SPLIT(dev))
6992 return;
6993
6994 if (!dev_priv->lvds_downclock_avail)
6995 return;
6996
6997 dpll = I915_READ(dpll_reg);
6998 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6999 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7000
7001 /* Unlock panel regs */
7002 I915_WRITE(PP_CONTROL,
7003 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
7004
7005 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7006 I915_WRITE(dpll_reg, dpll);
7007 intel_wait_for_vblank(dev, pipe);
7008
7009 dpll = I915_READ(dpll_reg);
7010 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7011 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7012
7013 /* ...and lock them again */
7014 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7015 }
7016
7017 /* Schedule downclock */
7018 mod_timer(&intel_crtc->idle_timer, jiffies +
7019 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7020 }
7021
7022 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7023 {
7024 struct drm_device *dev = crtc->dev;
7025 drm_i915_private_t *dev_priv = dev->dev_private;
7026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7027 int pipe = intel_crtc->pipe;
7028 int dpll_reg = DPLL(pipe);
7029 int dpll = I915_READ(dpll_reg);
7030
7031 if (HAS_PCH_SPLIT(dev))
7032 return;
7033
7034 if (!dev_priv->lvds_downclock_avail)
7035 return;
7036
7037 /*
7038 * Since this is called by a timer, we should never get here in
7039 * the manual case.
7040 */
7041 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7042 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7043
7044 /* Unlock panel regs */
7045 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7046 PANEL_UNLOCK_REGS);
7047
7048 dpll |= DISPLAY_RATE_SELECT_FPA1;
7049 I915_WRITE(dpll_reg, dpll);
7050 intel_wait_for_vblank(dev, pipe);
7051 dpll = I915_READ(dpll_reg);
7052 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7053 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7054
7055 /* ...and lock them again */
7056 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7057 }
7058
7059 }
7060
7061 /**
7062 * intel_idle_update - adjust clocks for idleness
7063 * @work: work struct
7064 *
7065 * Either the GPU or display (or both) went idle. Check the busy status
7066 * here and adjust the CRTC and GPU clocks as necessary.
7067 */
7068 static void intel_idle_update(struct work_struct *work)
7069 {
7070 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7071 idle_work);
7072 struct drm_device *dev = dev_priv->dev;
7073 struct drm_crtc *crtc;
7074 struct intel_crtc *intel_crtc;
7075
7076 if (!i915_powersave)
7077 return;
7078
7079 mutex_lock(&dev->struct_mutex);
7080
7081 i915_update_gfx_val(dev_priv);
7082
7083 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7084 /* Skip inactive CRTCs */
7085 if (!crtc->fb)
7086 continue;
7087
7088 intel_crtc = to_intel_crtc(crtc);
7089 if (!intel_crtc->busy)
7090 intel_decrease_pllclock(crtc);
7091 }
7092
7093
7094 mutex_unlock(&dev->struct_mutex);
7095 }
7096
7097 /**
7098 * intel_mark_busy - mark the GPU and possibly the display busy
7099 * @dev: drm device
7100 * @obj: object we're operating on
7101 *
7102 * Callers can use this function to indicate that the GPU is busy processing
7103 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7104 * buffer), we'll also mark the display as busy, so we know to increase its
7105 * clock frequency.
7106 */
7107 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7108 {
7109 drm_i915_private_t *dev_priv = dev->dev_private;
7110 struct drm_crtc *crtc = NULL;
7111 struct intel_framebuffer *intel_fb;
7112 struct intel_crtc *intel_crtc;
7113
7114 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7115 return;
7116
7117 if (!dev_priv->busy)
7118 dev_priv->busy = true;
7119 else
7120 mod_timer(&dev_priv->idle_timer, jiffies +
7121 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7122
7123 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7124 if (!crtc->fb)
7125 continue;
7126
7127 intel_crtc = to_intel_crtc(crtc);
7128 intel_fb = to_intel_framebuffer(crtc->fb);
7129 if (intel_fb->obj == obj) {
7130 if (!intel_crtc->busy) {
7131 /* Non-busy -> busy, upclock */
7132 intel_increase_pllclock(crtc);
7133 intel_crtc->busy = true;
7134 } else {
7135 /* Busy -> busy, put off timer */
7136 mod_timer(&intel_crtc->idle_timer, jiffies +
7137 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7138 }
7139 }
7140 }
7141 }
7142
7143 static void intel_crtc_destroy(struct drm_crtc *crtc)
7144 {
7145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7146 struct drm_device *dev = crtc->dev;
7147 struct intel_unpin_work *work;
7148 unsigned long flags;
7149
7150 spin_lock_irqsave(&dev->event_lock, flags);
7151 work = intel_crtc->unpin_work;
7152 intel_crtc->unpin_work = NULL;
7153 spin_unlock_irqrestore(&dev->event_lock, flags);
7154
7155 if (work) {
7156 cancel_work_sync(&work->work);
7157 kfree(work);
7158 }
7159
7160 drm_crtc_cleanup(crtc);
7161
7162 kfree(intel_crtc);
7163 }
7164
7165 static void intel_unpin_work_fn(struct work_struct *__work)
7166 {
7167 struct intel_unpin_work *work =
7168 container_of(__work, struct intel_unpin_work, work);
7169
7170 mutex_lock(&work->dev->struct_mutex);
7171 intel_unpin_fb_obj(work->old_fb_obj);
7172 drm_gem_object_unreference(&work->pending_flip_obj->base);
7173 drm_gem_object_unreference(&work->old_fb_obj->base);
7174
7175 intel_update_fbc(work->dev);
7176 mutex_unlock(&work->dev->struct_mutex);
7177 kfree(work);
7178 }
7179
7180 static void do_intel_finish_page_flip(struct drm_device *dev,
7181 struct drm_crtc *crtc)
7182 {
7183 drm_i915_private_t *dev_priv = dev->dev_private;
7184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7185 struct intel_unpin_work *work;
7186 struct drm_i915_gem_object *obj;
7187 struct drm_pending_vblank_event *e;
7188 struct timeval tnow, tvbl;
7189 unsigned long flags;
7190
7191 /* Ignore early vblank irqs */
7192 if (intel_crtc == NULL)
7193 return;
7194
7195 do_gettimeofday(&tnow);
7196
7197 spin_lock_irqsave(&dev->event_lock, flags);
7198 work = intel_crtc->unpin_work;
7199 if (work == NULL || !work->pending) {
7200 spin_unlock_irqrestore(&dev->event_lock, flags);
7201 return;
7202 }
7203
7204 intel_crtc->unpin_work = NULL;
7205
7206 if (work->event) {
7207 e = work->event;
7208 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7209
7210 /* Called before vblank count and timestamps have
7211 * been updated for the vblank interval of flip
7212 * completion? Need to increment vblank count and
7213 * add one videorefresh duration to returned timestamp
7214 * to account for this. We assume this happened if we
7215 * get called over 0.9 frame durations after the last
7216 * timestamped vblank.
7217 *
7218 * This calculation can not be used with vrefresh rates
7219 * below 5Hz (10Hz to be on the safe side) without
7220 * promoting to 64 integers.
7221 */
7222 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7223 9 * crtc->framedur_ns) {
7224 e->event.sequence++;
7225 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7226 crtc->framedur_ns);
7227 }
7228
7229 e->event.tv_sec = tvbl.tv_sec;
7230 e->event.tv_usec = tvbl.tv_usec;
7231
7232 list_add_tail(&e->base.link,
7233 &e->base.file_priv->event_list);
7234 wake_up_interruptible(&e->base.file_priv->event_wait);
7235 }
7236
7237 drm_vblank_put(dev, intel_crtc->pipe);
7238
7239 spin_unlock_irqrestore(&dev->event_lock, flags);
7240
7241 obj = work->old_fb_obj;
7242
7243 atomic_clear_mask(1 << intel_crtc->plane,
7244 &obj->pending_flip.counter);
7245 if (atomic_read(&obj->pending_flip) == 0)
7246 wake_up(&dev_priv->pending_flip_queue);
7247
7248 schedule_work(&work->work);
7249
7250 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7251 }
7252
7253 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7254 {
7255 drm_i915_private_t *dev_priv = dev->dev_private;
7256 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7257
7258 do_intel_finish_page_flip(dev, crtc);
7259 }
7260
7261 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7262 {
7263 drm_i915_private_t *dev_priv = dev->dev_private;
7264 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7265
7266 do_intel_finish_page_flip(dev, crtc);
7267 }
7268
7269 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7270 {
7271 drm_i915_private_t *dev_priv = dev->dev_private;
7272 struct intel_crtc *intel_crtc =
7273 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7274 unsigned long flags;
7275
7276 spin_lock_irqsave(&dev->event_lock, flags);
7277 if (intel_crtc->unpin_work) {
7278 if ((++intel_crtc->unpin_work->pending) > 1)
7279 DRM_ERROR("Prepared flip multiple times\n");
7280 } else {
7281 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7282 }
7283 spin_unlock_irqrestore(&dev->event_lock, flags);
7284 }
7285
7286 static int intel_gen2_queue_flip(struct drm_device *dev,
7287 struct drm_crtc *crtc,
7288 struct drm_framebuffer *fb,
7289 struct drm_i915_gem_object *obj)
7290 {
7291 struct drm_i915_private *dev_priv = dev->dev_private;
7292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7293 unsigned long offset;
7294 u32 flip_mask;
7295 int ret;
7296
7297 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7298 if (ret)
7299 goto out;
7300
7301 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7302 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7303
7304 ret = BEGIN_LP_RING(6);
7305 if (ret)
7306 goto out;
7307
7308 /* Can't queue multiple flips, so wait for the previous
7309 * one to finish before executing the next.
7310 */
7311 if (intel_crtc->plane)
7312 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7313 else
7314 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7315 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7316 OUT_RING(MI_NOOP);
7317 OUT_RING(MI_DISPLAY_FLIP |
7318 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7319 OUT_RING(fb->pitches[0]);
7320 OUT_RING(obj->gtt_offset + offset);
7321 OUT_RING(0); /* aux display base address, unused */
7322 ADVANCE_LP_RING();
7323 out:
7324 return ret;
7325 }
7326
7327 static int intel_gen3_queue_flip(struct drm_device *dev,
7328 struct drm_crtc *crtc,
7329 struct drm_framebuffer *fb,
7330 struct drm_i915_gem_object *obj)
7331 {
7332 struct drm_i915_private *dev_priv = dev->dev_private;
7333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7334 unsigned long offset;
7335 u32 flip_mask;
7336 int ret;
7337
7338 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7339 if (ret)
7340 goto out;
7341
7342 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7343 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7344
7345 ret = BEGIN_LP_RING(6);
7346 if (ret)
7347 goto out;
7348
7349 if (intel_crtc->plane)
7350 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7351 else
7352 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7353 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7354 OUT_RING(MI_NOOP);
7355 OUT_RING(MI_DISPLAY_FLIP_I915 |
7356 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7357 OUT_RING(fb->pitches[0]);
7358 OUT_RING(obj->gtt_offset + offset);
7359 OUT_RING(MI_NOOP);
7360
7361 ADVANCE_LP_RING();
7362 out:
7363 return ret;
7364 }
7365
7366 static int intel_gen4_queue_flip(struct drm_device *dev,
7367 struct drm_crtc *crtc,
7368 struct drm_framebuffer *fb,
7369 struct drm_i915_gem_object *obj)
7370 {
7371 struct drm_i915_private *dev_priv = dev->dev_private;
7372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7373 uint32_t pf, pipesrc;
7374 int ret;
7375
7376 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7377 if (ret)
7378 goto out;
7379
7380 ret = BEGIN_LP_RING(4);
7381 if (ret)
7382 goto out;
7383
7384 /* i965+ uses the linear or tiled offsets from the
7385 * Display Registers (which do not change across a page-flip)
7386 * so we need only reprogram the base address.
7387 */
7388 OUT_RING(MI_DISPLAY_FLIP |
7389 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7390 OUT_RING(fb->pitches[0]);
7391 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7392
7393 /* XXX Enabling the panel-fitter across page-flip is so far
7394 * untested on non-native modes, so ignore it for now.
7395 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7396 */
7397 pf = 0;
7398 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7399 OUT_RING(pf | pipesrc);
7400 ADVANCE_LP_RING();
7401 out:
7402 return ret;
7403 }
7404
7405 static int intel_gen6_queue_flip(struct drm_device *dev,
7406 struct drm_crtc *crtc,
7407 struct drm_framebuffer *fb,
7408 struct drm_i915_gem_object *obj)
7409 {
7410 struct drm_i915_private *dev_priv = dev->dev_private;
7411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7412 uint32_t pf, pipesrc;
7413 int ret;
7414
7415 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7416 if (ret)
7417 goto out;
7418
7419 ret = BEGIN_LP_RING(4);
7420 if (ret)
7421 goto out;
7422
7423 OUT_RING(MI_DISPLAY_FLIP |
7424 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7425 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7426 OUT_RING(obj->gtt_offset);
7427
7428 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7429 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7430 OUT_RING(pf | pipesrc);
7431 ADVANCE_LP_RING();
7432 out:
7433 return ret;
7434 }
7435
7436 /*
7437 * On gen7 we currently use the blit ring because (in early silicon at least)
7438 * the render ring doesn't give us interrpts for page flip completion, which
7439 * means clients will hang after the first flip is queued. Fortunately the
7440 * blit ring generates interrupts properly, so use it instead.
7441 */
7442 static int intel_gen7_queue_flip(struct drm_device *dev,
7443 struct drm_crtc *crtc,
7444 struct drm_framebuffer *fb,
7445 struct drm_i915_gem_object *obj)
7446 {
7447 struct drm_i915_private *dev_priv = dev->dev_private;
7448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7449 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7450 int ret;
7451
7452 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7453 if (ret)
7454 goto out;
7455
7456 ret = intel_ring_begin(ring, 4);
7457 if (ret)
7458 goto out;
7459
7460 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7461 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7462 intel_ring_emit(ring, (obj->gtt_offset));
7463 intel_ring_emit(ring, (MI_NOOP));
7464 intel_ring_advance(ring);
7465 out:
7466 return ret;
7467 }
7468
7469 static int intel_default_queue_flip(struct drm_device *dev,
7470 struct drm_crtc *crtc,
7471 struct drm_framebuffer *fb,
7472 struct drm_i915_gem_object *obj)
7473 {
7474 return -ENODEV;
7475 }
7476
7477 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7478 struct drm_framebuffer *fb,
7479 struct drm_pending_vblank_event *event)
7480 {
7481 struct drm_device *dev = crtc->dev;
7482 struct drm_i915_private *dev_priv = dev->dev_private;
7483 struct intel_framebuffer *intel_fb;
7484 struct drm_i915_gem_object *obj;
7485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7486 struct intel_unpin_work *work;
7487 unsigned long flags;
7488 int ret;
7489
7490 work = kzalloc(sizeof *work, GFP_KERNEL);
7491 if (work == NULL)
7492 return -ENOMEM;
7493
7494 work->event = event;
7495 work->dev = crtc->dev;
7496 intel_fb = to_intel_framebuffer(crtc->fb);
7497 work->old_fb_obj = intel_fb->obj;
7498 INIT_WORK(&work->work, intel_unpin_work_fn);
7499
7500 ret = drm_vblank_get(dev, intel_crtc->pipe);
7501 if (ret)
7502 goto free_work;
7503
7504 /* We borrow the event spin lock for protecting unpin_work */
7505 spin_lock_irqsave(&dev->event_lock, flags);
7506 if (intel_crtc->unpin_work) {
7507 spin_unlock_irqrestore(&dev->event_lock, flags);
7508 kfree(work);
7509 drm_vblank_put(dev, intel_crtc->pipe);
7510
7511 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7512 return -EBUSY;
7513 }
7514 intel_crtc->unpin_work = work;
7515 spin_unlock_irqrestore(&dev->event_lock, flags);
7516
7517 intel_fb = to_intel_framebuffer(fb);
7518 obj = intel_fb->obj;
7519
7520 mutex_lock(&dev->struct_mutex);
7521
7522 /* Reference the objects for the scheduled work. */
7523 drm_gem_object_reference(&work->old_fb_obj->base);
7524 drm_gem_object_reference(&obj->base);
7525
7526 crtc->fb = fb;
7527
7528 work->pending_flip_obj = obj;
7529
7530 work->enable_stall_check = true;
7531
7532 /* Block clients from rendering to the new back buffer until
7533 * the flip occurs and the object is no longer visible.
7534 */
7535 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7536
7537 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7538 if (ret)
7539 goto cleanup_pending;
7540
7541 intel_disable_fbc(dev);
7542 mutex_unlock(&dev->struct_mutex);
7543
7544 trace_i915_flip_request(intel_crtc->plane, obj);
7545
7546 return 0;
7547
7548 cleanup_pending:
7549 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7550 drm_gem_object_unreference(&work->old_fb_obj->base);
7551 drm_gem_object_unreference(&obj->base);
7552 mutex_unlock(&dev->struct_mutex);
7553
7554 spin_lock_irqsave(&dev->event_lock, flags);
7555 intel_crtc->unpin_work = NULL;
7556 spin_unlock_irqrestore(&dev->event_lock, flags);
7557
7558 drm_vblank_put(dev, intel_crtc->pipe);
7559 free_work:
7560 kfree(work);
7561
7562 return ret;
7563 }
7564
7565 static void intel_sanitize_modesetting(struct drm_device *dev,
7566 int pipe, int plane)
7567 {
7568 struct drm_i915_private *dev_priv = dev->dev_private;
7569 u32 reg, val;
7570
7571 if (HAS_PCH_SPLIT(dev))
7572 return;
7573
7574 /* Who knows what state these registers were left in by the BIOS or
7575 * grub?
7576 *
7577 * If we leave the registers in a conflicting state (e.g. with the
7578 * display plane reading from the other pipe than the one we intend
7579 * to use) then when we attempt to teardown the active mode, we will
7580 * not disable the pipes and planes in the correct order -- leaving
7581 * a plane reading from a disabled pipe and possibly leading to
7582 * undefined behaviour.
7583 */
7584
7585 reg = DSPCNTR(plane);
7586 val = I915_READ(reg);
7587
7588 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7589 return;
7590 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7591 return;
7592
7593 /* This display plane is active and attached to the other CPU pipe. */
7594 pipe = !pipe;
7595
7596 /* Disable the plane and wait for it to stop reading from the pipe. */
7597 intel_disable_plane(dev_priv, plane, pipe);
7598 intel_disable_pipe(dev_priv, pipe);
7599 }
7600
7601 static void intel_crtc_reset(struct drm_crtc *crtc)
7602 {
7603 struct drm_device *dev = crtc->dev;
7604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7605
7606 /* Reset flags back to the 'unknown' status so that they
7607 * will be correctly set on the initial modeset.
7608 */
7609 intel_crtc->dpms_mode = -1;
7610
7611 /* We need to fix up any BIOS configuration that conflicts with
7612 * our expectations.
7613 */
7614 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7615 }
7616
7617 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7618 .dpms = intel_crtc_dpms,
7619 .mode_fixup = intel_crtc_mode_fixup,
7620 .mode_set = intel_crtc_mode_set,
7621 .mode_set_base = intel_pipe_set_base,
7622 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7623 .load_lut = intel_crtc_load_lut,
7624 .disable = intel_crtc_disable,
7625 };
7626
7627 static const struct drm_crtc_funcs intel_crtc_funcs = {
7628 .reset = intel_crtc_reset,
7629 .cursor_set = intel_crtc_cursor_set,
7630 .cursor_move = intel_crtc_cursor_move,
7631 .gamma_set = intel_crtc_gamma_set,
7632 .set_config = drm_crtc_helper_set_config,
7633 .destroy = intel_crtc_destroy,
7634 .page_flip = intel_crtc_page_flip,
7635 };
7636
7637 static void intel_crtc_init(struct drm_device *dev, int pipe)
7638 {
7639 drm_i915_private_t *dev_priv = dev->dev_private;
7640 struct intel_crtc *intel_crtc;
7641 int i;
7642
7643 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7644 if (intel_crtc == NULL)
7645 return;
7646
7647 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7648
7649 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7650 for (i = 0; i < 256; i++) {
7651 intel_crtc->lut_r[i] = i;
7652 intel_crtc->lut_g[i] = i;
7653 intel_crtc->lut_b[i] = i;
7654 }
7655
7656 /* Swap pipes & planes for FBC on pre-965 */
7657 intel_crtc->pipe = pipe;
7658 intel_crtc->plane = pipe;
7659 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7660 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7661 intel_crtc->plane = !pipe;
7662 }
7663
7664 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7665 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7666 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7667 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7668
7669 intel_crtc_reset(&intel_crtc->base);
7670 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7671 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7672
7673 if (HAS_PCH_SPLIT(dev)) {
7674 if (pipe == 2 && IS_IVYBRIDGE(dev))
7675 intel_crtc->no_pll = true;
7676 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7677 intel_helper_funcs.commit = ironlake_crtc_commit;
7678 } else {
7679 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7680 intel_helper_funcs.commit = i9xx_crtc_commit;
7681 }
7682
7683 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7684
7685 intel_crtc->busy = false;
7686
7687 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7688 (unsigned long)intel_crtc);
7689 }
7690
7691 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7692 struct drm_file *file)
7693 {
7694 drm_i915_private_t *dev_priv = dev->dev_private;
7695 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7696 struct drm_mode_object *drmmode_obj;
7697 struct intel_crtc *crtc;
7698
7699 if (!dev_priv) {
7700 DRM_ERROR("called with no initialization\n");
7701 return -EINVAL;
7702 }
7703
7704 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7705 DRM_MODE_OBJECT_CRTC);
7706
7707 if (!drmmode_obj) {
7708 DRM_ERROR("no such CRTC id\n");
7709 return -EINVAL;
7710 }
7711
7712 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7713 pipe_from_crtc_id->pipe = crtc->pipe;
7714
7715 return 0;
7716 }
7717
7718 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7719 {
7720 struct intel_encoder *encoder;
7721 int index_mask = 0;
7722 int entry = 0;
7723
7724 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7725 if (type_mask & encoder->clone_mask)
7726 index_mask |= (1 << entry);
7727 entry++;
7728 }
7729
7730 return index_mask;
7731 }
7732
7733 static bool has_edp_a(struct drm_device *dev)
7734 {
7735 struct drm_i915_private *dev_priv = dev->dev_private;
7736
7737 if (!IS_MOBILE(dev))
7738 return false;
7739
7740 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7741 return false;
7742
7743 if (IS_GEN5(dev) &&
7744 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7745 return false;
7746
7747 return true;
7748 }
7749
7750 static void intel_setup_outputs(struct drm_device *dev)
7751 {
7752 struct drm_i915_private *dev_priv = dev->dev_private;
7753 struct intel_encoder *encoder;
7754 bool dpd_is_edp = false;
7755 bool has_lvds = false;
7756
7757 if (IS_MOBILE(dev) && !IS_I830(dev))
7758 has_lvds = intel_lvds_init(dev);
7759 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7760 /* disable the panel fitter on everything but LVDS */
7761 I915_WRITE(PFIT_CONTROL, 0);
7762 }
7763
7764 if (HAS_PCH_SPLIT(dev)) {
7765 dpd_is_edp = intel_dpd_is_edp(dev);
7766
7767 if (has_edp_a(dev))
7768 intel_dp_init(dev, DP_A);
7769
7770 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7771 intel_dp_init(dev, PCH_DP_D);
7772 }
7773
7774 intel_crt_init(dev);
7775
7776 if (HAS_PCH_SPLIT(dev)) {
7777 int found;
7778
7779 if (I915_READ(HDMIB) & PORT_DETECTED) {
7780 /* PCH SDVOB multiplex with HDMIB */
7781 found = intel_sdvo_init(dev, PCH_SDVOB);
7782 if (!found)
7783 intel_hdmi_init(dev, HDMIB);
7784 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7785 intel_dp_init(dev, PCH_DP_B);
7786 }
7787
7788 if (I915_READ(HDMIC) & PORT_DETECTED)
7789 intel_hdmi_init(dev, HDMIC);
7790
7791 if (I915_READ(HDMID) & PORT_DETECTED)
7792 intel_hdmi_init(dev, HDMID);
7793
7794 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7795 intel_dp_init(dev, PCH_DP_C);
7796
7797 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7798 intel_dp_init(dev, PCH_DP_D);
7799
7800 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7801 bool found = false;
7802
7803 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7804 DRM_DEBUG_KMS("probing SDVOB\n");
7805 found = intel_sdvo_init(dev, SDVOB);
7806 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7807 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7808 intel_hdmi_init(dev, SDVOB);
7809 }
7810
7811 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7812 DRM_DEBUG_KMS("probing DP_B\n");
7813 intel_dp_init(dev, DP_B);
7814 }
7815 }
7816
7817 /* Before G4X SDVOC doesn't have its own detect register */
7818
7819 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7820 DRM_DEBUG_KMS("probing SDVOC\n");
7821 found = intel_sdvo_init(dev, SDVOC);
7822 }
7823
7824 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7825
7826 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7827 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7828 intel_hdmi_init(dev, SDVOC);
7829 }
7830 if (SUPPORTS_INTEGRATED_DP(dev)) {
7831 DRM_DEBUG_KMS("probing DP_C\n");
7832 intel_dp_init(dev, DP_C);
7833 }
7834 }
7835
7836 if (SUPPORTS_INTEGRATED_DP(dev) &&
7837 (I915_READ(DP_D) & DP_DETECTED)) {
7838 DRM_DEBUG_KMS("probing DP_D\n");
7839 intel_dp_init(dev, DP_D);
7840 }
7841 } else if (IS_GEN2(dev))
7842 intel_dvo_init(dev);
7843
7844 if (SUPPORTS_TV(dev))
7845 intel_tv_init(dev);
7846
7847 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7848 encoder->base.possible_crtcs = encoder->crtc_mask;
7849 encoder->base.possible_clones =
7850 intel_encoder_clones(dev, encoder->clone_mask);
7851 }
7852
7853 /* disable all the possible outputs/crtcs before entering KMS mode */
7854 drm_helper_disable_unused_functions(dev);
7855
7856 if (HAS_PCH_SPLIT(dev))
7857 ironlake_init_pch_refclk(dev);
7858 }
7859
7860 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7861 {
7862 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7863
7864 drm_framebuffer_cleanup(fb);
7865 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7866
7867 kfree(intel_fb);
7868 }
7869
7870 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7871 struct drm_file *file,
7872 unsigned int *handle)
7873 {
7874 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7875 struct drm_i915_gem_object *obj = intel_fb->obj;
7876
7877 return drm_gem_handle_create(file, &obj->base, handle);
7878 }
7879
7880 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7881 .destroy = intel_user_framebuffer_destroy,
7882 .create_handle = intel_user_framebuffer_create_handle,
7883 };
7884
7885 int intel_framebuffer_init(struct drm_device *dev,
7886 struct intel_framebuffer *intel_fb,
7887 struct drm_mode_fb_cmd2 *mode_cmd,
7888 struct drm_i915_gem_object *obj)
7889 {
7890 int ret;
7891
7892 if (obj->tiling_mode == I915_TILING_Y)
7893 return -EINVAL;
7894
7895 if (mode_cmd->pitches[0] & 63)
7896 return -EINVAL;
7897
7898 switch (mode_cmd->pixel_format) {
7899 case DRM_FORMAT_RGB332:
7900 case DRM_FORMAT_RGB565:
7901 case DRM_FORMAT_XRGB8888:
7902 case DRM_FORMAT_ARGB8888:
7903 case DRM_FORMAT_XRGB2101010:
7904 case DRM_FORMAT_ARGB2101010:
7905 /* RGB formats are common across chipsets */
7906 break;
7907 case DRM_FORMAT_YUYV:
7908 case DRM_FORMAT_UYVY:
7909 case DRM_FORMAT_YVYU:
7910 case DRM_FORMAT_VYUY:
7911 break;
7912 default:
7913 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7914 mode_cmd->pixel_format);
7915 return -EINVAL;
7916 }
7917
7918 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7919 if (ret) {
7920 DRM_ERROR("framebuffer init failed %d\n", ret);
7921 return ret;
7922 }
7923
7924 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7925 intel_fb->obj = obj;
7926 return 0;
7927 }
7928
7929 static struct drm_framebuffer *
7930 intel_user_framebuffer_create(struct drm_device *dev,
7931 struct drm_file *filp,
7932 struct drm_mode_fb_cmd2 *mode_cmd)
7933 {
7934 struct drm_i915_gem_object *obj;
7935
7936 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7937 mode_cmd->handles[0]));
7938 if (&obj->base == NULL)
7939 return ERR_PTR(-ENOENT);
7940
7941 return intel_framebuffer_create(dev, mode_cmd, obj);
7942 }
7943
7944 static const struct drm_mode_config_funcs intel_mode_funcs = {
7945 .fb_create = intel_user_framebuffer_create,
7946 .output_poll_changed = intel_fb_output_poll_changed,
7947 };
7948
7949 static struct drm_i915_gem_object *
7950 intel_alloc_context_page(struct drm_device *dev)
7951 {
7952 struct drm_i915_gem_object *ctx;
7953 int ret;
7954
7955 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7956
7957 ctx = i915_gem_alloc_object(dev, 4096);
7958 if (!ctx) {
7959 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7960 return NULL;
7961 }
7962
7963 ret = i915_gem_object_pin(ctx, 4096, true);
7964 if (ret) {
7965 DRM_ERROR("failed to pin power context: %d\n", ret);
7966 goto err_unref;
7967 }
7968
7969 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7970 if (ret) {
7971 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7972 goto err_unpin;
7973 }
7974
7975 return ctx;
7976
7977 err_unpin:
7978 i915_gem_object_unpin(ctx);
7979 err_unref:
7980 drm_gem_object_unreference(&ctx->base);
7981 mutex_unlock(&dev->struct_mutex);
7982 return NULL;
7983 }
7984
7985 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7986 {
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 u16 rgvswctl;
7989
7990 rgvswctl = I915_READ16(MEMSWCTL);
7991 if (rgvswctl & MEMCTL_CMD_STS) {
7992 DRM_DEBUG("gpu busy, RCS change rejected\n");
7993 return false; /* still busy with another command */
7994 }
7995
7996 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7997 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7998 I915_WRITE16(MEMSWCTL, rgvswctl);
7999 POSTING_READ16(MEMSWCTL);
8000
8001 rgvswctl |= MEMCTL_CMD_STS;
8002 I915_WRITE16(MEMSWCTL, rgvswctl);
8003
8004 return true;
8005 }
8006
8007 void ironlake_enable_drps(struct drm_device *dev)
8008 {
8009 struct drm_i915_private *dev_priv = dev->dev_private;
8010 u32 rgvmodectl = I915_READ(MEMMODECTL);
8011 u8 fmax, fmin, fstart, vstart;
8012
8013 /* Enable temp reporting */
8014 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8015 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8016
8017 /* 100ms RC evaluation intervals */
8018 I915_WRITE(RCUPEI, 100000);
8019 I915_WRITE(RCDNEI, 100000);
8020
8021 /* Set max/min thresholds to 90ms and 80ms respectively */
8022 I915_WRITE(RCBMAXAVG, 90000);
8023 I915_WRITE(RCBMINAVG, 80000);
8024
8025 I915_WRITE(MEMIHYST, 1);
8026
8027 /* Set up min, max, and cur for interrupt handling */
8028 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8029 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8030 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8031 MEMMODE_FSTART_SHIFT;
8032
8033 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8034 PXVFREQ_PX_SHIFT;
8035
8036 dev_priv->fmax = fmax; /* IPS callback will increase this */
8037 dev_priv->fstart = fstart;
8038
8039 dev_priv->max_delay = fstart;
8040 dev_priv->min_delay = fmin;
8041 dev_priv->cur_delay = fstart;
8042
8043 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8044 fmax, fmin, fstart);
8045
8046 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8047
8048 /*
8049 * Interrupts will be enabled in ironlake_irq_postinstall
8050 */
8051
8052 I915_WRITE(VIDSTART, vstart);
8053 POSTING_READ(VIDSTART);
8054
8055 rgvmodectl |= MEMMODE_SWMODE_EN;
8056 I915_WRITE(MEMMODECTL, rgvmodectl);
8057
8058 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8059 DRM_ERROR("stuck trying to change perf mode\n");
8060 msleep(1);
8061
8062 ironlake_set_drps(dev, fstart);
8063
8064 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8065 I915_READ(0x112e0);
8066 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8067 dev_priv->last_count2 = I915_READ(0x112f4);
8068 getrawmonotonic(&dev_priv->last_time2);
8069 }
8070
8071 void ironlake_disable_drps(struct drm_device *dev)
8072 {
8073 struct drm_i915_private *dev_priv = dev->dev_private;
8074 u16 rgvswctl = I915_READ16(MEMSWCTL);
8075
8076 /* Ack interrupts, disable EFC interrupt */
8077 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8078 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8079 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8080 I915_WRITE(DEIIR, DE_PCU_EVENT);
8081 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8082
8083 /* Go back to the starting frequency */
8084 ironlake_set_drps(dev, dev_priv->fstart);
8085 msleep(1);
8086 rgvswctl |= MEMCTL_CMD_STS;
8087 I915_WRITE(MEMSWCTL, rgvswctl);
8088 msleep(1);
8089
8090 }
8091
8092 void gen6_set_rps(struct drm_device *dev, u8 val)
8093 {
8094 struct drm_i915_private *dev_priv = dev->dev_private;
8095 u32 swreq;
8096
8097 swreq = (val & 0x3ff) << 25;
8098 I915_WRITE(GEN6_RPNSWREQ, swreq);
8099 }
8100
8101 void gen6_disable_rps(struct drm_device *dev)
8102 {
8103 struct drm_i915_private *dev_priv = dev->dev_private;
8104
8105 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8106 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8107 I915_WRITE(GEN6_PMIER, 0);
8108 /* Complete PM interrupt masking here doesn't race with the rps work
8109 * item again unmasking PM interrupts because that is using a different
8110 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8111 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8112
8113 spin_lock_irq(&dev_priv->rps_lock);
8114 dev_priv->pm_iir = 0;
8115 spin_unlock_irq(&dev_priv->rps_lock);
8116
8117 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8118 }
8119
8120 static unsigned long intel_pxfreq(u32 vidfreq)
8121 {
8122 unsigned long freq;
8123 int div = (vidfreq & 0x3f0000) >> 16;
8124 int post = (vidfreq & 0x3000) >> 12;
8125 int pre = (vidfreq & 0x7);
8126
8127 if (!pre)
8128 return 0;
8129
8130 freq = ((div * 133333) / ((1<<post) * pre));
8131
8132 return freq;
8133 }
8134
8135 void intel_init_emon(struct drm_device *dev)
8136 {
8137 struct drm_i915_private *dev_priv = dev->dev_private;
8138 u32 lcfuse;
8139 u8 pxw[16];
8140 int i;
8141
8142 /* Disable to program */
8143 I915_WRITE(ECR, 0);
8144 POSTING_READ(ECR);
8145
8146 /* Program energy weights for various events */
8147 I915_WRITE(SDEW, 0x15040d00);
8148 I915_WRITE(CSIEW0, 0x007f0000);
8149 I915_WRITE(CSIEW1, 0x1e220004);
8150 I915_WRITE(CSIEW2, 0x04000004);
8151
8152 for (i = 0; i < 5; i++)
8153 I915_WRITE(PEW + (i * 4), 0);
8154 for (i = 0; i < 3; i++)
8155 I915_WRITE(DEW + (i * 4), 0);
8156
8157 /* Program P-state weights to account for frequency power adjustment */
8158 for (i = 0; i < 16; i++) {
8159 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8160 unsigned long freq = intel_pxfreq(pxvidfreq);
8161 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8162 PXVFREQ_PX_SHIFT;
8163 unsigned long val;
8164
8165 val = vid * vid;
8166 val *= (freq / 1000);
8167 val *= 255;
8168 val /= (127*127*900);
8169 if (val > 0xff)
8170 DRM_ERROR("bad pxval: %ld\n", val);
8171 pxw[i] = val;
8172 }
8173 /* Render standby states get 0 weight */
8174 pxw[14] = 0;
8175 pxw[15] = 0;
8176
8177 for (i = 0; i < 4; i++) {
8178 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8179 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8180 I915_WRITE(PXW + (i * 4), val);
8181 }
8182
8183 /* Adjust magic regs to magic values (more experimental results) */
8184 I915_WRITE(OGW0, 0);
8185 I915_WRITE(OGW1, 0);
8186 I915_WRITE(EG0, 0x00007f00);
8187 I915_WRITE(EG1, 0x0000000e);
8188 I915_WRITE(EG2, 0x000e0000);
8189 I915_WRITE(EG3, 0x68000300);
8190 I915_WRITE(EG4, 0x42000000);
8191 I915_WRITE(EG5, 0x00140031);
8192 I915_WRITE(EG6, 0);
8193 I915_WRITE(EG7, 0);
8194
8195 for (i = 0; i < 8; i++)
8196 I915_WRITE(PXWL + (i * 4), 0);
8197
8198 /* Enable PMON + select events */
8199 I915_WRITE(ECR, 0x80000019);
8200
8201 lcfuse = I915_READ(LCFUSE02);
8202
8203 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8204 }
8205
8206 static bool intel_enable_rc6(struct drm_device *dev)
8207 {
8208 /*
8209 * Respect the kernel parameter if it is set
8210 */
8211 if (i915_enable_rc6 >= 0)
8212 return i915_enable_rc6;
8213
8214 /*
8215 * Disable RC6 on Ironlake
8216 */
8217 if (INTEL_INFO(dev)->gen == 5)
8218 return 0;
8219
8220 /*
8221 * Disable rc6 on Sandybridge
8222 */
8223 if (INTEL_INFO(dev)->gen == 6) {
8224 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8225 return 0;
8226 }
8227 DRM_DEBUG_DRIVER("RC6 enabled\n");
8228 return 1;
8229 }
8230
8231 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8232 {
8233 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8234 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8235 u32 pcu_mbox, rc6_mask = 0;
8236 int cur_freq, min_freq, max_freq;
8237 int i;
8238
8239 /* Here begins a magic sequence of register writes to enable
8240 * auto-downclocking.
8241 *
8242 * Perhaps there might be some value in exposing these to
8243 * userspace...
8244 */
8245 I915_WRITE(GEN6_RC_STATE, 0);
8246 mutex_lock(&dev_priv->dev->struct_mutex);
8247 gen6_gt_force_wake_get(dev_priv);
8248
8249 /* disable the counters and set deterministic thresholds */
8250 I915_WRITE(GEN6_RC_CONTROL, 0);
8251
8252 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8253 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8254 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8255 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8256 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8257
8258 for (i = 0; i < I915_NUM_RINGS; i++)
8259 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8260
8261 I915_WRITE(GEN6_RC_SLEEP, 0);
8262 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8263 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8264 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8265 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8266
8267 if (intel_enable_rc6(dev_priv->dev))
8268 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8269 GEN6_RC_CTL_RC6_ENABLE;
8270
8271 I915_WRITE(GEN6_RC_CONTROL,
8272 rc6_mask |
8273 GEN6_RC_CTL_EI_MODE(1) |
8274 GEN6_RC_CTL_HW_ENABLE);
8275
8276 I915_WRITE(GEN6_RPNSWREQ,
8277 GEN6_FREQUENCY(10) |
8278 GEN6_OFFSET(0) |
8279 GEN6_AGGRESSIVE_TURBO);
8280 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8281 GEN6_FREQUENCY(12));
8282
8283 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8284 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8285 18 << 24 |
8286 6 << 16);
8287 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8288 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8289 I915_WRITE(GEN6_RP_UP_EI, 100000);
8290 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8291 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8292 I915_WRITE(GEN6_RP_CONTROL,
8293 GEN6_RP_MEDIA_TURBO |
8294 GEN6_RP_MEDIA_HW_MODE |
8295 GEN6_RP_MEDIA_IS_GFX |
8296 GEN6_RP_ENABLE |
8297 GEN6_RP_UP_BUSY_AVG |
8298 GEN6_RP_DOWN_IDLE_CONT);
8299
8300 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8301 500))
8302 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8303
8304 I915_WRITE(GEN6_PCODE_DATA, 0);
8305 I915_WRITE(GEN6_PCODE_MAILBOX,
8306 GEN6_PCODE_READY |
8307 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8308 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8309 500))
8310 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8311
8312 min_freq = (rp_state_cap & 0xff0000) >> 16;
8313 max_freq = rp_state_cap & 0xff;
8314 cur_freq = (gt_perf_status & 0xff00) >> 8;
8315
8316 /* Check for overclock support */
8317 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8318 500))
8319 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8320 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8321 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8322 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8323 500))
8324 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8325 if (pcu_mbox & (1<<31)) { /* OC supported */
8326 max_freq = pcu_mbox & 0xff;
8327 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8328 }
8329
8330 /* In units of 100MHz */
8331 dev_priv->max_delay = max_freq;
8332 dev_priv->min_delay = min_freq;
8333 dev_priv->cur_delay = cur_freq;
8334
8335 /* requires MSI enabled */
8336 I915_WRITE(GEN6_PMIER,
8337 GEN6_PM_MBOX_EVENT |
8338 GEN6_PM_THERMAL_EVENT |
8339 GEN6_PM_RP_DOWN_TIMEOUT |
8340 GEN6_PM_RP_UP_THRESHOLD |
8341 GEN6_PM_RP_DOWN_THRESHOLD |
8342 GEN6_PM_RP_UP_EI_EXPIRED |
8343 GEN6_PM_RP_DOWN_EI_EXPIRED);
8344 spin_lock_irq(&dev_priv->rps_lock);
8345 WARN_ON(dev_priv->pm_iir != 0);
8346 I915_WRITE(GEN6_PMIMR, 0);
8347 spin_unlock_irq(&dev_priv->rps_lock);
8348 /* enable all PM interrupts */
8349 I915_WRITE(GEN6_PMINTRMSK, 0);
8350
8351 gen6_gt_force_wake_put(dev_priv);
8352 mutex_unlock(&dev_priv->dev->struct_mutex);
8353 }
8354
8355 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8356 {
8357 int min_freq = 15;
8358 int gpu_freq, ia_freq, max_ia_freq;
8359 int scaling_factor = 180;
8360
8361 max_ia_freq = cpufreq_quick_get_max(0);
8362 /*
8363 * Default to measured freq if none found, PCU will ensure we don't go
8364 * over
8365 */
8366 if (!max_ia_freq)
8367 max_ia_freq = tsc_khz;
8368
8369 /* Convert from kHz to MHz */
8370 max_ia_freq /= 1000;
8371
8372 mutex_lock(&dev_priv->dev->struct_mutex);
8373
8374 /*
8375 * For each potential GPU frequency, load a ring frequency we'd like
8376 * to use for memory access. We do this by specifying the IA frequency
8377 * the PCU should use as a reference to determine the ring frequency.
8378 */
8379 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8380 gpu_freq--) {
8381 int diff = dev_priv->max_delay - gpu_freq;
8382
8383 /*
8384 * For GPU frequencies less than 750MHz, just use the lowest
8385 * ring freq.
8386 */
8387 if (gpu_freq < min_freq)
8388 ia_freq = 800;
8389 else
8390 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8391 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8392
8393 I915_WRITE(GEN6_PCODE_DATA,
8394 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8395 gpu_freq);
8396 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8397 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8398 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8399 GEN6_PCODE_READY) == 0, 10)) {
8400 DRM_ERROR("pcode write of freq table timed out\n");
8401 continue;
8402 }
8403 }
8404
8405 mutex_unlock(&dev_priv->dev->struct_mutex);
8406 }
8407
8408 static void ironlake_init_clock_gating(struct drm_device *dev)
8409 {
8410 struct drm_i915_private *dev_priv = dev->dev_private;
8411 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8412
8413 /* Required for FBC */
8414 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8415 DPFCRUNIT_CLOCK_GATE_DISABLE |
8416 DPFDUNIT_CLOCK_GATE_DISABLE;
8417 /* Required for CxSR */
8418 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8419
8420 I915_WRITE(PCH_3DCGDIS0,
8421 MARIUNIT_CLOCK_GATE_DISABLE |
8422 SVSMUNIT_CLOCK_GATE_DISABLE);
8423 I915_WRITE(PCH_3DCGDIS1,
8424 VFMUNIT_CLOCK_GATE_DISABLE);
8425
8426 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8427
8428 /*
8429 * According to the spec the following bits should be set in
8430 * order to enable memory self-refresh
8431 * The bit 22/21 of 0x42004
8432 * The bit 5 of 0x42020
8433 * The bit 15 of 0x45000
8434 */
8435 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8436 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8437 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8438 I915_WRITE(ILK_DSPCLK_GATE,
8439 (I915_READ(ILK_DSPCLK_GATE) |
8440 ILK_DPARB_CLK_GATE));
8441 I915_WRITE(DISP_ARB_CTL,
8442 (I915_READ(DISP_ARB_CTL) |
8443 DISP_FBC_WM_DIS));
8444 I915_WRITE(WM3_LP_ILK, 0);
8445 I915_WRITE(WM2_LP_ILK, 0);
8446 I915_WRITE(WM1_LP_ILK, 0);
8447
8448 /*
8449 * Based on the document from hardware guys the following bits
8450 * should be set unconditionally in order to enable FBC.
8451 * The bit 22 of 0x42000
8452 * The bit 22 of 0x42004
8453 * The bit 7,8,9 of 0x42020.
8454 */
8455 if (IS_IRONLAKE_M(dev)) {
8456 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8457 I915_READ(ILK_DISPLAY_CHICKEN1) |
8458 ILK_FBCQ_DIS);
8459 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8460 I915_READ(ILK_DISPLAY_CHICKEN2) |
8461 ILK_DPARB_GATE);
8462 I915_WRITE(ILK_DSPCLK_GATE,
8463 I915_READ(ILK_DSPCLK_GATE) |
8464 ILK_DPFC_DIS1 |
8465 ILK_DPFC_DIS2 |
8466 ILK_CLK_FBC);
8467 }
8468
8469 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8470 I915_READ(ILK_DISPLAY_CHICKEN2) |
8471 ILK_ELPIN_409_SELECT);
8472 I915_WRITE(_3D_CHICKEN2,
8473 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8474 _3D_CHICKEN2_WM_READ_PIPELINED);
8475 }
8476
8477 static void gen6_init_clock_gating(struct drm_device *dev)
8478 {
8479 struct drm_i915_private *dev_priv = dev->dev_private;
8480 int pipe;
8481 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8482
8483 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8484
8485 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8486 I915_READ(ILK_DISPLAY_CHICKEN2) |
8487 ILK_ELPIN_409_SELECT);
8488
8489 I915_WRITE(WM3_LP_ILK, 0);
8490 I915_WRITE(WM2_LP_ILK, 0);
8491 I915_WRITE(WM1_LP_ILK, 0);
8492
8493 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8494 * gating disable must be set. Failure to set it results in
8495 * flickering pixels due to Z write ordering failures after
8496 * some amount of runtime in the Mesa "fire" demo, and Unigine
8497 * Sanctuary and Tropics, and apparently anything else with
8498 * alpha test or pixel discard.
8499 *
8500 * According to the spec, bit 11 (RCCUNIT) must also be set,
8501 * but we didn't debug actual testcases to find it out.
8502 */
8503 I915_WRITE(GEN6_UCGCTL2,
8504 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8505 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8506
8507 /*
8508 * According to the spec the following bits should be
8509 * set in order to enable memory self-refresh and fbc:
8510 * The bit21 and bit22 of 0x42000
8511 * The bit21 and bit22 of 0x42004
8512 * The bit5 and bit7 of 0x42020
8513 * The bit14 of 0x70180
8514 * The bit14 of 0x71180
8515 */
8516 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8517 I915_READ(ILK_DISPLAY_CHICKEN1) |
8518 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8519 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8520 I915_READ(ILK_DISPLAY_CHICKEN2) |
8521 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8522 I915_WRITE(ILK_DSPCLK_GATE,
8523 I915_READ(ILK_DSPCLK_GATE) |
8524 ILK_DPARB_CLK_GATE |
8525 ILK_DPFD_CLK_GATE);
8526
8527 for_each_pipe(pipe) {
8528 I915_WRITE(DSPCNTR(pipe),
8529 I915_READ(DSPCNTR(pipe)) |
8530 DISPPLANE_TRICKLE_FEED_DISABLE);
8531 intel_flush_display_plane(dev_priv, pipe);
8532 }
8533 }
8534
8535 static void ivybridge_init_clock_gating(struct drm_device *dev)
8536 {
8537 struct drm_i915_private *dev_priv = dev->dev_private;
8538 int pipe;
8539 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8540
8541 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8542
8543 I915_WRITE(WM3_LP_ILK, 0);
8544 I915_WRITE(WM2_LP_ILK, 0);
8545 I915_WRITE(WM1_LP_ILK, 0);
8546
8547 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8548
8549 I915_WRITE(IVB_CHICKEN3,
8550 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8551 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8552
8553 for_each_pipe(pipe) {
8554 I915_WRITE(DSPCNTR(pipe),
8555 I915_READ(DSPCNTR(pipe)) |
8556 DISPPLANE_TRICKLE_FEED_DISABLE);
8557 intel_flush_display_plane(dev_priv, pipe);
8558 }
8559 }
8560
8561 static void g4x_init_clock_gating(struct drm_device *dev)
8562 {
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 uint32_t dspclk_gate;
8565
8566 I915_WRITE(RENCLK_GATE_D1, 0);
8567 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8568 GS_UNIT_CLOCK_GATE_DISABLE |
8569 CL_UNIT_CLOCK_GATE_DISABLE);
8570 I915_WRITE(RAMCLK_GATE_D, 0);
8571 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8572 OVRUNIT_CLOCK_GATE_DISABLE |
8573 OVCUNIT_CLOCK_GATE_DISABLE;
8574 if (IS_GM45(dev))
8575 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8576 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8577 }
8578
8579 static void crestline_init_clock_gating(struct drm_device *dev)
8580 {
8581 struct drm_i915_private *dev_priv = dev->dev_private;
8582
8583 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8584 I915_WRITE(RENCLK_GATE_D2, 0);
8585 I915_WRITE(DSPCLK_GATE_D, 0);
8586 I915_WRITE(RAMCLK_GATE_D, 0);
8587 I915_WRITE16(DEUC, 0);
8588 }
8589
8590 static void broadwater_init_clock_gating(struct drm_device *dev)
8591 {
8592 struct drm_i915_private *dev_priv = dev->dev_private;
8593
8594 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8595 I965_RCC_CLOCK_GATE_DISABLE |
8596 I965_RCPB_CLOCK_GATE_DISABLE |
8597 I965_ISC_CLOCK_GATE_DISABLE |
8598 I965_FBC_CLOCK_GATE_DISABLE);
8599 I915_WRITE(RENCLK_GATE_D2, 0);
8600 }
8601
8602 static void gen3_init_clock_gating(struct drm_device *dev)
8603 {
8604 struct drm_i915_private *dev_priv = dev->dev_private;
8605 u32 dstate = I915_READ(D_STATE);
8606
8607 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8608 DSTATE_DOT_CLOCK_GATING;
8609 I915_WRITE(D_STATE, dstate);
8610 }
8611
8612 static void i85x_init_clock_gating(struct drm_device *dev)
8613 {
8614 struct drm_i915_private *dev_priv = dev->dev_private;
8615
8616 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8617 }
8618
8619 static void i830_init_clock_gating(struct drm_device *dev)
8620 {
8621 struct drm_i915_private *dev_priv = dev->dev_private;
8622
8623 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8624 }
8625
8626 static void ibx_init_clock_gating(struct drm_device *dev)
8627 {
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8629
8630 /*
8631 * On Ibex Peak and Cougar Point, we need to disable clock
8632 * gating for the panel power sequencer or it will fail to
8633 * start up when no ports are active.
8634 */
8635 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8636 }
8637
8638 static void cpt_init_clock_gating(struct drm_device *dev)
8639 {
8640 struct drm_i915_private *dev_priv = dev->dev_private;
8641 int pipe;
8642
8643 /*
8644 * On Ibex Peak and Cougar Point, we need to disable clock
8645 * gating for the panel power sequencer or it will fail to
8646 * start up when no ports are active.
8647 */
8648 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8649 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8650 DPLS_EDP_PPS_FIX_DIS);
8651 /* Without this, mode sets may fail silently on FDI */
8652 for_each_pipe(pipe)
8653 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8654 }
8655
8656 static void ironlake_teardown_rc6(struct drm_device *dev)
8657 {
8658 struct drm_i915_private *dev_priv = dev->dev_private;
8659
8660 if (dev_priv->renderctx) {
8661 i915_gem_object_unpin(dev_priv->renderctx);
8662 drm_gem_object_unreference(&dev_priv->renderctx->base);
8663 dev_priv->renderctx = NULL;
8664 }
8665
8666 if (dev_priv->pwrctx) {
8667 i915_gem_object_unpin(dev_priv->pwrctx);
8668 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8669 dev_priv->pwrctx = NULL;
8670 }
8671 }
8672
8673 static void ironlake_disable_rc6(struct drm_device *dev)
8674 {
8675 struct drm_i915_private *dev_priv = dev->dev_private;
8676
8677 if (I915_READ(PWRCTXA)) {
8678 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8679 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8680 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8681 50);
8682
8683 I915_WRITE(PWRCTXA, 0);
8684 POSTING_READ(PWRCTXA);
8685
8686 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8687 POSTING_READ(RSTDBYCTL);
8688 }
8689
8690 ironlake_teardown_rc6(dev);
8691 }
8692
8693 static int ironlake_setup_rc6(struct drm_device *dev)
8694 {
8695 struct drm_i915_private *dev_priv = dev->dev_private;
8696
8697 if (dev_priv->renderctx == NULL)
8698 dev_priv->renderctx = intel_alloc_context_page(dev);
8699 if (!dev_priv->renderctx)
8700 return -ENOMEM;
8701
8702 if (dev_priv->pwrctx == NULL)
8703 dev_priv->pwrctx = intel_alloc_context_page(dev);
8704 if (!dev_priv->pwrctx) {
8705 ironlake_teardown_rc6(dev);
8706 return -ENOMEM;
8707 }
8708
8709 return 0;
8710 }
8711
8712 void ironlake_enable_rc6(struct drm_device *dev)
8713 {
8714 struct drm_i915_private *dev_priv = dev->dev_private;
8715 int ret;
8716
8717 /* rc6 disabled by default due to repeated reports of hanging during
8718 * boot and resume.
8719 */
8720 if (!intel_enable_rc6(dev))
8721 return;
8722
8723 mutex_lock(&dev->struct_mutex);
8724 ret = ironlake_setup_rc6(dev);
8725 if (ret) {
8726 mutex_unlock(&dev->struct_mutex);
8727 return;
8728 }
8729
8730 /*
8731 * GPU can automatically power down the render unit if given a page
8732 * to save state.
8733 */
8734 ret = BEGIN_LP_RING(6);
8735 if (ret) {
8736 ironlake_teardown_rc6(dev);
8737 mutex_unlock(&dev->struct_mutex);
8738 return;
8739 }
8740
8741 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8742 OUT_RING(MI_SET_CONTEXT);
8743 OUT_RING(dev_priv->renderctx->gtt_offset |
8744 MI_MM_SPACE_GTT |
8745 MI_SAVE_EXT_STATE_EN |
8746 MI_RESTORE_EXT_STATE_EN |
8747 MI_RESTORE_INHIBIT);
8748 OUT_RING(MI_SUSPEND_FLUSH);
8749 OUT_RING(MI_NOOP);
8750 OUT_RING(MI_FLUSH);
8751 ADVANCE_LP_RING();
8752
8753 /*
8754 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8755 * does an implicit flush, combined with MI_FLUSH above, it should be
8756 * safe to assume that renderctx is valid
8757 */
8758 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8759 if (ret) {
8760 DRM_ERROR("failed to enable ironlake power power savings\n");
8761 ironlake_teardown_rc6(dev);
8762 mutex_unlock(&dev->struct_mutex);
8763 return;
8764 }
8765
8766 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8767 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8768 mutex_unlock(&dev->struct_mutex);
8769 }
8770
8771 void intel_init_clock_gating(struct drm_device *dev)
8772 {
8773 struct drm_i915_private *dev_priv = dev->dev_private;
8774
8775 dev_priv->display.init_clock_gating(dev);
8776
8777 if (dev_priv->display.init_pch_clock_gating)
8778 dev_priv->display.init_pch_clock_gating(dev);
8779 }
8780
8781 /* Set up chip specific display functions */
8782 static void intel_init_display(struct drm_device *dev)
8783 {
8784 struct drm_i915_private *dev_priv = dev->dev_private;
8785
8786 /* We always want a DPMS function */
8787 if (HAS_PCH_SPLIT(dev)) {
8788 dev_priv->display.dpms = ironlake_crtc_dpms;
8789 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8790 dev_priv->display.update_plane = ironlake_update_plane;
8791 } else {
8792 dev_priv->display.dpms = i9xx_crtc_dpms;
8793 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8794 dev_priv->display.update_plane = i9xx_update_plane;
8795 }
8796
8797 if (I915_HAS_FBC(dev)) {
8798 if (HAS_PCH_SPLIT(dev)) {
8799 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8800 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8801 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8802 } else if (IS_GM45(dev)) {
8803 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8804 dev_priv->display.enable_fbc = g4x_enable_fbc;
8805 dev_priv->display.disable_fbc = g4x_disable_fbc;
8806 } else if (IS_CRESTLINE(dev)) {
8807 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8808 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8809 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8810 }
8811 /* 855GM needs testing */
8812 }
8813
8814 /* Returns the core display clock speed */
8815 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8816 dev_priv->display.get_display_clock_speed =
8817 i945_get_display_clock_speed;
8818 else if (IS_I915G(dev))
8819 dev_priv->display.get_display_clock_speed =
8820 i915_get_display_clock_speed;
8821 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8822 dev_priv->display.get_display_clock_speed =
8823 i9xx_misc_get_display_clock_speed;
8824 else if (IS_I915GM(dev))
8825 dev_priv->display.get_display_clock_speed =
8826 i915gm_get_display_clock_speed;
8827 else if (IS_I865G(dev))
8828 dev_priv->display.get_display_clock_speed =
8829 i865_get_display_clock_speed;
8830 else if (IS_I85X(dev))
8831 dev_priv->display.get_display_clock_speed =
8832 i855_get_display_clock_speed;
8833 else /* 852, 830 */
8834 dev_priv->display.get_display_clock_speed =
8835 i830_get_display_clock_speed;
8836
8837 /* For FIFO watermark updates */
8838 if (HAS_PCH_SPLIT(dev)) {
8839 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8840 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8841
8842 /* IVB configs may use multi-threaded forcewake */
8843 if (IS_IVYBRIDGE(dev)) {
8844 u32 ecobus;
8845
8846 /* A small trick here - if the bios hasn't configured MT forcewake,
8847 * and if the device is in RC6, then force_wake_mt_get will not wake
8848 * the device and the ECOBUS read will return zero. Which will be
8849 * (correctly) interpreted by the test below as MT forcewake being
8850 * disabled.
8851 */
8852 mutex_lock(&dev->struct_mutex);
8853 __gen6_gt_force_wake_mt_get(dev_priv);
8854 ecobus = I915_READ_NOTRACE(ECOBUS);
8855 __gen6_gt_force_wake_mt_put(dev_priv);
8856 mutex_unlock(&dev->struct_mutex);
8857
8858 if (ecobus & FORCEWAKE_MT_ENABLE) {
8859 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8860 dev_priv->display.force_wake_get =
8861 __gen6_gt_force_wake_mt_get;
8862 dev_priv->display.force_wake_put =
8863 __gen6_gt_force_wake_mt_put;
8864 }
8865 }
8866
8867 if (HAS_PCH_IBX(dev))
8868 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8869 else if (HAS_PCH_CPT(dev))
8870 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8871
8872 if (IS_GEN5(dev)) {
8873 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8874 dev_priv->display.update_wm = ironlake_update_wm;
8875 else {
8876 DRM_DEBUG_KMS("Failed to get proper latency. "
8877 "Disable CxSR\n");
8878 dev_priv->display.update_wm = NULL;
8879 }
8880 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8881 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8882 dev_priv->display.write_eld = ironlake_write_eld;
8883 } else if (IS_GEN6(dev)) {
8884 if (SNB_READ_WM0_LATENCY()) {
8885 dev_priv->display.update_wm = sandybridge_update_wm;
8886 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8887 } else {
8888 DRM_DEBUG_KMS("Failed to read display plane latency. "
8889 "Disable CxSR\n");
8890 dev_priv->display.update_wm = NULL;
8891 }
8892 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8893 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8894 dev_priv->display.write_eld = ironlake_write_eld;
8895 } else if (IS_IVYBRIDGE(dev)) {
8896 /* FIXME: detect B0+ stepping and use auto training */
8897 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8898 if (SNB_READ_WM0_LATENCY()) {
8899 dev_priv->display.update_wm = sandybridge_update_wm;
8900 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8901 } else {
8902 DRM_DEBUG_KMS("Failed to read display plane latency. "
8903 "Disable CxSR\n");
8904 dev_priv->display.update_wm = NULL;
8905 }
8906 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8907 dev_priv->display.write_eld = ironlake_write_eld;
8908 } else
8909 dev_priv->display.update_wm = NULL;
8910 } else if (IS_PINEVIEW(dev)) {
8911 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8912 dev_priv->is_ddr3,
8913 dev_priv->fsb_freq,
8914 dev_priv->mem_freq)) {
8915 DRM_INFO("failed to find known CxSR latency "
8916 "(found ddr%s fsb freq %d, mem freq %d), "
8917 "disabling CxSR\n",
8918 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8919 dev_priv->fsb_freq, dev_priv->mem_freq);
8920 /* Disable CxSR and never update its watermark again */
8921 pineview_disable_cxsr(dev);
8922 dev_priv->display.update_wm = NULL;
8923 } else
8924 dev_priv->display.update_wm = pineview_update_wm;
8925 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8926 } else if (IS_G4X(dev)) {
8927 dev_priv->display.write_eld = g4x_write_eld;
8928 dev_priv->display.update_wm = g4x_update_wm;
8929 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8930 } else if (IS_GEN4(dev)) {
8931 dev_priv->display.update_wm = i965_update_wm;
8932 if (IS_CRESTLINE(dev))
8933 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8934 else if (IS_BROADWATER(dev))
8935 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8936 } else if (IS_GEN3(dev)) {
8937 dev_priv->display.update_wm = i9xx_update_wm;
8938 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8939 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8940 } else if (IS_I865G(dev)) {
8941 dev_priv->display.update_wm = i830_update_wm;
8942 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8943 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8944 } else if (IS_I85X(dev)) {
8945 dev_priv->display.update_wm = i9xx_update_wm;
8946 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8947 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8948 } else {
8949 dev_priv->display.update_wm = i830_update_wm;
8950 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8951 if (IS_845G(dev))
8952 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8953 else
8954 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8955 }
8956
8957 /* Default just returns -ENODEV to indicate unsupported */
8958 dev_priv->display.queue_flip = intel_default_queue_flip;
8959
8960 switch (INTEL_INFO(dev)->gen) {
8961 case 2:
8962 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8963 break;
8964
8965 case 3:
8966 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8967 break;
8968
8969 case 4:
8970 case 5:
8971 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8972 break;
8973
8974 case 6:
8975 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8976 break;
8977 case 7:
8978 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8979 break;
8980 }
8981 }
8982
8983 /*
8984 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8985 * resume, or other times. This quirk makes sure that's the case for
8986 * affected systems.
8987 */
8988 static void quirk_pipea_force(struct drm_device *dev)
8989 {
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8991
8992 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8993 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8994 }
8995
8996 /*
8997 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8998 */
8999 static void quirk_ssc_force_disable(struct drm_device *dev)
9000 {
9001 struct drm_i915_private *dev_priv = dev->dev_private;
9002 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9003 }
9004
9005 struct intel_quirk {
9006 int device;
9007 int subsystem_vendor;
9008 int subsystem_device;
9009 void (*hook)(struct drm_device *dev);
9010 };
9011
9012 struct intel_quirk intel_quirks[] = {
9013 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
9014 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
9015 /* HP Mini needs pipe A force quirk (LP: #322104) */
9016 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9017
9018 /* Thinkpad R31 needs pipe A force quirk */
9019 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9020 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9021 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9022
9023 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9024 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9025 /* ThinkPad X40 needs pipe A force quirk */
9026
9027 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9028 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9029
9030 /* 855 & before need to leave pipe A & dpll A up */
9031 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9032 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9033
9034 /* Lenovo U160 cannot use SSC on LVDS */
9035 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9036
9037 /* Sony Vaio Y cannot use SSC on LVDS */
9038 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9039 };
9040
9041 static void intel_init_quirks(struct drm_device *dev)
9042 {
9043 struct pci_dev *d = dev->pdev;
9044 int i;
9045
9046 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9047 struct intel_quirk *q = &intel_quirks[i];
9048
9049 if (d->device == q->device &&
9050 (d->subsystem_vendor == q->subsystem_vendor ||
9051 q->subsystem_vendor == PCI_ANY_ID) &&
9052 (d->subsystem_device == q->subsystem_device ||
9053 q->subsystem_device == PCI_ANY_ID))
9054 q->hook(dev);
9055 }
9056 }
9057
9058 /* Disable the VGA plane that we never use */
9059 static void i915_disable_vga(struct drm_device *dev)
9060 {
9061 struct drm_i915_private *dev_priv = dev->dev_private;
9062 u8 sr1;
9063 u32 vga_reg;
9064
9065 if (HAS_PCH_SPLIT(dev))
9066 vga_reg = CPU_VGACNTRL;
9067 else
9068 vga_reg = VGACNTRL;
9069
9070 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9071 outb(1, VGA_SR_INDEX);
9072 sr1 = inb(VGA_SR_DATA);
9073 outb(sr1 | 1<<5, VGA_SR_DATA);
9074 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9075 udelay(300);
9076
9077 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9078 POSTING_READ(vga_reg);
9079 }
9080
9081 void intel_modeset_init(struct drm_device *dev)
9082 {
9083 struct drm_i915_private *dev_priv = dev->dev_private;
9084 int i, ret;
9085
9086 drm_mode_config_init(dev);
9087
9088 dev->mode_config.min_width = 0;
9089 dev->mode_config.min_height = 0;
9090
9091 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9092
9093 intel_init_quirks(dev);
9094
9095 intel_init_display(dev);
9096
9097 if (IS_GEN2(dev)) {
9098 dev->mode_config.max_width = 2048;
9099 dev->mode_config.max_height = 2048;
9100 } else if (IS_GEN3(dev)) {
9101 dev->mode_config.max_width = 4096;
9102 dev->mode_config.max_height = 4096;
9103 } else {
9104 dev->mode_config.max_width = 8192;
9105 dev->mode_config.max_height = 8192;
9106 }
9107 dev->mode_config.fb_base = dev->agp->base;
9108
9109 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9110 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9111
9112 for (i = 0; i < dev_priv->num_pipe; i++) {
9113 intel_crtc_init(dev, i);
9114 ret = intel_plane_init(dev, i);
9115 if (ret)
9116 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9117 }
9118
9119 /* Just disable it once at startup */
9120 i915_disable_vga(dev);
9121 intel_setup_outputs(dev);
9122
9123 intel_init_clock_gating(dev);
9124
9125 if (IS_IRONLAKE_M(dev)) {
9126 ironlake_enable_drps(dev);
9127 intel_init_emon(dev);
9128 }
9129
9130 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9131 gen6_enable_rps(dev_priv);
9132 gen6_update_ring_freq(dev_priv);
9133 }
9134
9135 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9136 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9137 (unsigned long)dev);
9138 }
9139
9140 void intel_modeset_gem_init(struct drm_device *dev)
9141 {
9142 if (IS_IRONLAKE_M(dev))
9143 ironlake_enable_rc6(dev);
9144
9145 intel_setup_overlay(dev);
9146 }
9147
9148 void intel_modeset_cleanup(struct drm_device *dev)
9149 {
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151 struct drm_crtc *crtc;
9152 struct intel_crtc *intel_crtc;
9153
9154 drm_kms_helper_poll_fini(dev);
9155 mutex_lock(&dev->struct_mutex);
9156
9157 intel_unregister_dsm_handler();
9158
9159
9160 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9161 /* Skip inactive CRTCs */
9162 if (!crtc->fb)
9163 continue;
9164
9165 intel_crtc = to_intel_crtc(crtc);
9166 intel_increase_pllclock(crtc);
9167 }
9168
9169 intel_disable_fbc(dev);
9170
9171 if (IS_IRONLAKE_M(dev))
9172 ironlake_disable_drps(dev);
9173 if (IS_GEN6(dev) || IS_GEN7(dev))
9174 gen6_disable_rps(dev);
9175
9176 if (IS_IRONLAKE_M(dev))
9177 ironlake_disable_rc6(dev);
9178
9179 mutex_unlock(&dev->struct_mutex);
9180
9181 /* Disable the irq before mode object teardown, for the irq might
9182 * enqueue unpin/hotplug work. */
9183 drm_irq_uninstall(dev);
9184 cancel_work_sync(&dev_priv->hotplug_work);
9185 cancel_work_sync(&dev_priv->rps_work);
9186
9187 /* flush any delayed tasks or pending work */
9188 flush_scheduled_work();
9189
9190 /* Shut off idle work before the crtcs get freed. */
9191 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9192 intel_crtc = to_intel_crtc(crtc);
9193 del_timer_sync(&intel_crtc->idle_timer);
9194 }
9195 del_timer_sync(&dev_priv->idle_timer);
9196 cancel_work_sync(&dev_priv->idle_work);
9197
9198 drm_mode_config_cleanup(dev);
9199 }
9200
9201 /*
9202 * Return which encoder is currently attached for connector.
9203 */
9204 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9205 {
9206 return &intel_attached_encoder(connector)->base;
9207 }
9208
9209 void intel_connector_attach_encoder(struct intel_connector *connector,
9210 struct intel_encoder *encoder)
9211 {
9212 connector->encoder = encoder;
9213 drm_mode_connector_attach_encoder(&connector->base,
9214 &encoder->base);
9215 }
9216
9217 /*
9218 * set vga decode state - true == enable VGA decode
9219 */
9220 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9221 {
9222 struct drm_i915_private *dev_priv = dev->dev_private;
9223 u16 gmch_ctrl;
9224
9225 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9226 if (state)
9227 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9228 else
9229 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9230 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9231 return 0;
9232 }
9233
9234 #ifdef CONFIG_DEBUG_FS
9235 #include <linux/seq_file.h>
9236
9237 struct intel_display_error_state {
9238 struct intel_cursor_error_state {
9239 u32 control;
9240 u32 position;
9241 u32 base;
9242 u32 size;
9243 } cursor[2];
9244
9245 struct intel_pipe_error_state {
9246 u32 conf;
9247 u32 source;
9248
9249 u32 htotal;
9250 u32 hblank;
9251 u32 hsync;
9252 u32 vtotal;
9253 u32 vblank;
9254 u32 vsync;
9255 } pipe[2];
9256
9257 struct intel_plane_error_state {
9258 u32 control;
9259 u32 stride;
9260 u32 size;
9261 u32 pos;
9262 u32 addr;
9263 u32 surface;
9264 u32 tile_offset;
9265 } plane[2];
9266 };
9267
9268 struct intel_display_error_state *
9269 intel_display_capture_error_state(struct drm_device *dev)
9270 {
9271 drm_i915_private_t *dev_priv = dev->dev_private;
9272 struct intel_display_error_state *error;
9273 int i;
9274
9275 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9276 if (error == NULL)
9277 return NULL;
9278
9279 for (i = 0; i < 2; i++) {
9280 error->cursor[i].control = I915_READ(CURCNTR(i));
9281 error->cursor[i].position = I915_READ(CURPOS(i));
9282 error->cursor[i].base = I915_READ(CURBASE(i));
9283
9284 error->plane[i].control = I915_READ(DSPCNTR(i));
9285 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9286 error->plane[i].size = I915_READ(DSPSIZE(i));
9287 error->plane[i].pos = I915_READ(DSPPOS(i));
9288 error->plane[i].addr = I915_READ(DSPADDR(i));
9289 if (INTEL_INFO(dev)->gen >= 4) {
9290 error->plane[i].surface = I915_READ(DSPSURF(i));
9291 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9292 }
9293
9294 error->pipe[i].conf = I915_READ(PIPECONF(i));
9295 error->pipe[i].source = I915_READ(PIPESRC(i));
9296 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9297 error->pipe[i].hblank = I915_READ(HBLANK(i));
9298 error->pipe[i].hsync = I915_READ(HSYNC(i));
9299 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9300 error->pipe[i].vblank = I915_READ(VBLANK(i));
9301 error->pipe[i].vsync = I915_READ(VSYNC(i));
9302 }
9303
9304 return error;
9305 }
9306
9307 void
9308 intel_display_print_error_state(struct seq_file *m,
9309 struct drm_device *dev,
9310 struct intel_display_error_state *error)
9311 {
9312 int i;
9313
9314 for (i = 0; i < 2; i++) {
9315 seq_printf(m, "Pipe [%d]:\n", i);
9316 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9317 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9318 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9319 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9320 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9321 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9322 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9323 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9324
9325 seq_printf(m, "Plane [%d]:\n", i);
9326 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9327 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9328 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9329 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9330 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9331 if (INTEL_INFO(dev)->gen >= 4) {
9332 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9333 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9334 }
9335
9336 seq_printf(m, "Cursor [%d]:\n", i);
9337 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9338 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9339 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9340 }
9341 }
9342 #endif
Linux kernel - Deliverables
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