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drm/i915: Update queue_flip() to take a request structure
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112
113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114 {
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119 }
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 int
137 intel_pch_rawclk(struct drm_device *dev)
138 {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144 }
145
146 static inline u32 /* units of 100MHz */
147 intel_fdi_link_freq(struct drm_device *dev)
148 {
149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
154 }
155
156 static const intel_limit_t intel_limits_i8xx_dac = {
157 .dot = { .min = 25000, .max = 350000 },
158 .vco = { .min = 908000, .max = 1512000 },
159 .n = { .min = 2, .max = 16 },
160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
167 };
168
169 static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
171 .vco = { .min = 908000, .max = 1512000 },
172 .n = { .min = 2, .max = 16 },
173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180 };
181
182 static const intel_limit_t intel_limits_i8xx_lvds = {
183 .dot = { .min = 25000, .max = 350000 },
184 .vco = { .min = 908000, .max = 1512000 },
185 .n = { .min = 2, .max = 16 },
186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
193 };
194
195 static const intel_limit_t intel_limits_i9xx_sdvo = {
196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
206 };
207
208 static const intel_limit_t intel_limits_i9xx_lvds = {
209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
219 };
220
221
222 static const intel_limit_t intel_limits_g4x_sdvo = {
223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
234 },
235 };
236
237 static const intel_limit_t intel_limits_g4x_hdmi = {
238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
248 };
249
250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
261 },
262 };
263
264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
275 },
276 };
277
278 static const intel_limit_t intel_limits_pineview_sdvo = {
279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
281 /* Pineview's Ncounter is a ring counter */
282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
284 /* Pineview only has one combined m divider, which we treat as m2. */
285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
291 };
292
293 static const intel_limit_t intel_limits_pineview_lvds = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
304 };
305
306 /* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
311 static const intel_limit_t intel_limits_ironlake_dac = {
312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
322 };
323
324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
335 };
336
337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
348 };
349
350 /* LVDS 100mhz refclk limits. */
351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
362 };
363
364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
372 .p1 = { .min = 2, .max = 6 },
373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
375 };
376
377 static const intel_limit_t intel_limits_vlv = {
378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
385 .vco = { .min = 4000000, .max = 6000000 },
386 .n = { .min = 1, .max = 7 },
387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
391 };
392
393 static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
401 .vco = { .min = 4800000, .max = 6480000 },
402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407 };
408
409 static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419 };
420
421 static void vlv_clock(int refclk, intel_clock_t *clock)
422 {
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
429 }
430
431 static bool
432 needs_modeset(struct drm_crtc_state *state)
433 {
434 return state->mode_changed || state->active_changed;
435 }
436
437 /**
438 * Returns whether any output on the specified pipe is of the specified type
439 */
440 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
441 {
442 struct drm_device *dev = crtc->base.dev;
443 struct intel_encoder *encoder;
444
445 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
446 if (encoder->type == type)
447 return true;
448
449 return false;
450 }
451
452 /**
453 * Returns whether any output on the specified pipe will have the specified
454 * type after a staged modeset is complete, i.e., the same as
455 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
456 * encoder->crtc.
457 */
458 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
459 int type)
460 {
461 struct drm_atomic_state *state = crtc_state->base.state;
462 struct drm_connector *connector;
463 struct drm_connector_state *connector_state;
464 struct intel_encoder *encoder;
465 int i, num_connectors = 0;
466
467 for_each_connector_in_state(state, connector, connector_state, i) {
468 if (connector_state->crtc != crtc_state->base.crtc)
469 continue;
470
471 num_connectors++;
472
473 encoder = to_intel_encoder(connector_state->best_encoder);
474 if (encoder->type == type)
475 return true;
476 }
477
478 WARN_ON(num_connectors == 0);
479
480 return false;
481 }
482
483 static const intel_limit_t *
484 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
485 {
486 struct drm_device *dev = crtc_state->base.crtc->dev;
487 const intel_limit_t *limit;
488
489 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
490 if (intel_is_dual_link_lvds(dev)) {
491 if (refclk == 100000)
492 limit = &intel_limits_ironlake_dual_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_dual_lvds;
495 } else {
496 if (refclk == 100000)
497 limit = &intel_limits_ironlake_single_lvds_100m;
498 else
499 limit = &intel_limits_ironlake_single_lvds;
500 }
501 } else
502 limit = &intel_limits_ironlake_dac;
503
504 return limit;
505 }
506
507 static const intel_limit_t *
508 intel_g4x_limit(struct intel_crtc_state *crtc_state)
509 {
510 struct drm_device *dev = crtc_state->base.crtc->dev;
511 const intel_limit_t *limit;
512
513 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
514 if (intel_is_dual_link_lvds(dev))
515 limit = &intel_limits_g4x_dual_channel_lvds;
516 else
517 limit = &intel_limits_g4x_single_channel_lvds;
518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
519 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
520 limit = &intel_limits_g4x_hdmi;
521 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
522 limit = &intel_limits_g4x_sdvo;
523 } else /* The option is for other outputs */
524 limit = &intel_limits_i9xx_sdvo;
525
526 return limit;
527 }
528
529 static const intel_limit_t *
530 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
531 {
532 struct drm_device *dev = crtc_state->base.crtc->dev;
533 const intel_limit_t *limit;
534
535 if (IS_BROXTON(dev))
536 limit = &intel_limits_bxt;
537 else if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc_state, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc_state);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
544 else
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_CHERRYVIEW(dev)) {
547 limit = &intel_limits_chv;
548 } else if (IS_VALLEYVIEW(dev)) {
549 limit = &intel_limits_vlv;
550 } else if (!IS_GEN2(dev)) {
551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
552 limit = &intel_limits_i9xx_lvds;
553 else
554 limit = &intel_limits_i9xx_sdvo;
555 } else {
556 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
557 limit = &intel_limits_i8xx_lvds;
558 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
559 limit = &intel_limits_i8xx_dvo;
560 else
561 limit = &intel_limits_i8xx_dac;
562 }
563 return limit;
564 }
565
566 /* m1 is reserved as 0 in Pineview, n is a ring counter */
567 static void pineview_clock(int refclk, intel_clock_t *clock)
568 {
569 clock->m = clock->m2 + 2;
570 clock->p = clock->p1 * clock->p2;
571 if (WARN_ON(clock->n == 0 || clock->p == 0))
572 return;
573 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
574 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
575 }
576
577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578 {
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580 }
581
582 static void i9xx_clock(int refclk, intel_clock_t *clock)
583 {
584 clock->m = i9xx_dpll_compute_m(clock);
585 clock->p = clock->p1 * clock->p2;
586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
587 return;
588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 }
591
592 static void chv_clock(int refclk, intel_clock_t *clock)
593 {
594 clock->m = clock->m1 * clock->m2;
595 clock->p = clock->p1 * clock->p2;
596 if (WARN_ON(clock->n == 0 || clock->p == 0))
597 return;
598 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
599 clock->n << 22);
600 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604 /**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
612 {
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
616 INTELPllInvalid("p1 out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621
622 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
623 if (clock->m1 <= clock->m2)
624 INTELPllInvalid("m1 <= m2\n");
625
626 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
627 if (clock->p < limit->p.min || limit->p.max < clock->p)
628 INTELPllInvalid("p out of range\n");
629 if (clock->m < limit->m.min || limit->m.max < clock->m)
630 INTELPllInvalid("m out of range\n");
631 }
632
633 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
634 INTELPllInvalid("vco out of range\n");
635 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
636 * connector, etc., rather than just a single range.
637 */
638 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
639 INTELPllInvalid("dot out of range\n");
640
641 return true;
642 }
643
644 static int
645 i9xx_select_p2_div(const intel_limit_t *limit,
646 const struct intel_crtc_state *crtc_state,
647 int target)
648 {
649 struct drm_device *dev = crtc_state->base.crtc->dev;
650
651 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
652 /*
653 * For LVDS just rely on its current settings for dual-channel.
654 * We haven't figured out how to reliably set up different
655 * single/dual channel state, if we even can.
656 */
657 if (intel_is_dual_link_lvds(dev))
658 return limit->p2.p2_fast;
659 else
660 return limit->p2.p2_slow;
661 } else {
662 if (target < limit->p2.dot_limit)
663 return limit->p2.p2_slow;
664 else
665 return limit->p2.p2_fast;
666 }
667 }
668
669 static bool
670 i9xx_find_best_dpll(const intel_limit_t *limit,
671 struct intel_crtc_state *crtc_state,
672 int target, int refclk, intel_clock_t *match_clock,
673 intel_clock_t *best_clock)
674 {
675 struct drm_device *dev = crtc_state->base.crtc->dev;
676 intel_clock_t clock;
677 int err = target;
678
679 memset(best_clock, 0, sizeof(*best_clock));
680
681 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
682
683 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
684 clock.m1++) {
685 for (clock.m2 = limit->m2.min;
686 clock.m2 <= limit->m2.max; clock.m2++) {
687 if (clock.m2 >= clock.m1)
688 break;
689 for (clock.n = limit->n.min;
690 clock.n <= limit->n.max; clock.n++) {
691 for (clock.p1 = limit->p1.min;
692 clock.p1 <= limit->p1.max; clock.p1++) {
693 int this_err;
694
695 i9xx_clock(refclk, &clock);
696 if (!intel_PLL_is_valid(dev, limit,
697 &clock))
698 continue;
699 if (match_clock &&
700 clock.p != match_clock->p)
701 continue;
702
703 this_err = abs(clock.dot - target);
704 if (this_err < err) {
705 *best_clock = clock;
706 err = this_err;
707 }
708 }
709 }
710 }
711 }
712
713 return (err != target);
714 }
715
716 static bool
717 pnv_find_best_dpll(const intel_limit_t *limit,
718 struct intel_crtc_state *crtc_state,
719 int target, int refclk, intel_clock_t *match_clock,
720 intel_clock_t *best_clock)
721 {
722 struct drm_device *dev = crtc_state->base.crtc->dev;
723 intel_clock_t clock;
724 int err = target;
725
726 memset(best_clock, 0, sizeof(*best_clock));
727
728 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 static bool
762 g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
766 {
767 struct drm_device *dev = crtc_state->base.crtc->dev;
768 intel_clock_t clock;
769 int max_n;
770 bool found = false;
771 /* approximately equals target * 0.00585 */
772 int err_most = (target >> 8) + (target >> 9);
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 max_n = limit->n.max;
779 /* based on hardware requirement, prefer smaller n to precision */
780 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
781 /* based on hardware requirement, prefere larger m1,m2 */
782 for (clock.m1 = limit->m1.max;
783 clock.m1 >= limit->m1.min; clock.m1--) {
784 for (clock.m2 = limit->m2.max;
785 clock.m2 >= limit->m2.min; clock.m2--) {
786 for (clock.p1 = limit->p1.max;
787 clock.p1 >= limit->p1.min; clock.p1--) {
788 int this_err;
789
790 i9xx_clock(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 this_err = abs(clock.dot - target);
796 if (this_err < err_most) {
797 *best_clock = clock;
798 err_most = this_err;
799 max_n = clock.n;
800 found = true;
801 }
802 }
803 }
804 }
805 }
806 return found;
807 }
808
809 /*
810 * Check if the calculated PLL configuration is more optimal compared to the
811 * best configuration and error found so far. Return the calculated error.
812 */
813 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
814 const intel_clock_t *calculated_clock,
815 const intel_clock_t *best_clock,
816 unsigned int best_error_ppm,
817 unsigned int *error_ppm)
818 {
819 /*
820 * For CHV ignore the error and consider only the P value.
821 * Prefer a bigger P value based on HW requirements.
822 */
823 if (IS_CHERRYVIEW(dev)) {
824 *error_ppm = 0;
825
826 return calculated_clock->p > best_clock->p;
827 }
828
829 if (WARN_ON_ONCE(!target_freq))
830 return false;
831
832 *error_ppm = div_u64(1000000ULL *
833 abs(target_freq - calculated_clock->dot),
834 target_freq);
835 /*
836 * Prefer a better P value over a better (smaller) error if the error
837 * is small. Ensure this preference for future configurations too by
838 * setting the error to 0.
839 */
840 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
841 *error_ppm = 0;
842
843 return true;
844 }
845
846 return *error_ppm + 10 < best_error_ppm;
847 }
848
849 static bool
850 vlv_find_best_dpll(const intel_limit_t *limit,
851 struct intel_crtc_state *crtc_state,
852 int target, int refclk, intel_clock_t *match_clock,
853 intel_clock_t *best_clock)
854 {
855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
856 struct drm_device *dev = crtc->base.dev;
857 intel_clock_t clock;
858 unsigned int bestppm = 1000000;
859 /* min update 19.2 MHz */
860 int max_n = min(limit->n.max, refclk / 19200);
861 bool found = false;
862
863 target *= 5; /* fast clock */
864
865 memset(best_clock, 0, sizeof(*best_clock));
866
867 /* based on hardware requirement, prefer smaller n to precision */
868 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
869 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
870 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
871 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
872 clock.p = clock.p1 * clock.p2;
873 /* based on hardware requirement, prefer bigger m1,m2 values */
874 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
875 unsigned int ppm;
876
877 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
878 refclk * clock.m1);
879
880 vlv_clock(refclk, &clock);
881
882 if (!intel_PLL_is_valid(dev, limit,
883 &clock))
884 continue;
885
886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
891
892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
895 }
896 }
897 }
898 }
899
900 return found;
901 }
902
903 static bool
904 chv_find_best_dpll(const intel_limit_t *limit,
905 struct intel_crtc_state *crtc_state,
906 int target, int refclk, intel_clock_t *match_clock,
907 intel_clock_t *best_clock)
908 {
909 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
910 struct drm_device *dev = crtc->base.dev;
911 unsigned int best_error_ppm;
912 intel_clock_t clock;
913 uint64_t m2;
914 int found = false;
915
916 memset(best_clock, 0, sizeof(*best_clock));
917 best_error_ppm = 1000000;
918
919 /*
920 * Based on hardware doc, the n always set to 1, and m1 always
921 * set to 2. If requires to support 200Mhz refclk, we need to
922 * revisit this because n may not 1 anymore.
923 */
924 clock.n = 1, clock.m1 = 2;
925 target *= 5; /* fast clock */
926
927 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
928 for (clock.p2 = limit->p2.p2_fast;
929 clock.p2 >= limit->p2.p2_slow;
930 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
931 unsigned int error_ppm;
932
933 clock.p = clock.p1 * clock.p2;
934
935 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
936 clock.n) << 22, refclk * clock.m1);
937
938 if (m2 > INT_MAX/clock.m1)
939 continue;
940
941 clock.m2 = m2;
942
943 chv_clock(refclk, &clock);
944
945 if (!intel_PLL_is_valid(dev, limit, &clock))
946 continue;
947
948 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
949 best_error_ppm, &error_ppm))
950 continue;
951
952 *best_clock = clock;
953 best_error_ppm = error_ppm;
954 found = true;
955 }
956 }
957
958 return found;
959 }
960
961 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
962 intel_clock_t *best_clock)
963 {
964 int refclk = i9xx_get_refclk(crtc_state, 0);
965
966 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
967 target_clock, refclk, NULL, best_clock);
968 }
969
970 bool intel_crtc_active(struct drm_crtc *crtc)
971 {
972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
973
974 /* Be paranoid as we can arrive here with only partial
975 * state retrieved from the hardware during setup.
976 *
977 * We can ditch the adjusted_mode.crtc_clock check as soon
978 * as Haswell has gained clock readout/fastboot support.
979 *
980 * We can ditch the crtc->primary->fb check as soon as we can
981 * properly reconstruct framebuffers.
982 *
983 * FIXME: The intel_crtc->active here should be switched to
984 * crtc->state->active once we have proper CRTC states wired up
985 * for atomic.
986 */
987 return intel_crtc->active && crtc->primary->state->fb &&
988 intel_crtc->config->base.adjusted_mode.crtc_clock;
989 }
990
991 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993 {
994 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
996
997 return intel_crtc->config->cpu_transcoder;
998 }
999
1000 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1001 {
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 u32 reg = PIPEDSL(pipe);
1004 u32 line1, line2;
1005 u32 line_mask;
1006
1007 if (IS_GEN2(dev))
1008 line_mask = DSL_LINEMASK_GEN2;
1009 else
1010 line_mask = DSL_LINEMASK_GEN3;
1011
1012 line1 = I915_READ(reg) & line_mask;
1013 mdelay(5);
1014 line2 = I915_READ(reg) & line_mask;
1015
1016 return line1 == line2;
1017 }
1018
1019 /*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
1021 * @crtc: crtc whose pipe to wait for
1022 *
1023 * After disabling a pipe, we can't wait for vblank in the usual way,
1024 * spinning on the vblank interrupt status bit, since we won't actually
1025 * see an interrupt when the pipe is disabled.
1026 *
1027 * On Gen4 and above:
1028 * wait for the pipe register state bit to turn off
1029 *
1030 * Otherwise:
1031 * wait for the display line value to settle (it usually
1032 * ends up stopping at the start of the next frame).
1033 *
1034 */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037 struct drm_device *dev = crtc->base.dev;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1040 enum pipe pipe = crtc->pipe;
1041
1042 if (INTEL_INFO(dev)->gen >= 4) {
1043 int reg = PIPECONF(cpu_transcoder);
1044
1045 /* Wait for the Pipe State to go off */
1046 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1047 100))
1048 WARN(1, "pipe_off wait timed out\n");
1049 } else {
1050 /* Wait for the display line to settle */
1051 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1052 WARN(1, "pipe_off wait timed out\n");
1053 }
1054 }
1055
1056 /*
1057 * ibx_digital_port_connected - is the specified port connected?
1058 * @dev_priv: i915 private structure
1059 * @port: the port to test
1060 *
1061 * Returns true if @port is connected, false otherwise.
1062 */
1063 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1064 struct intel_digital_port *port)
1065 {
1066 u32 bit;
1067
1068 if (HAS_PCH_IBX(dev_priv->dev)) {
1069 switch (port->port) {
1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG;
1078 break;
1079 default:
1080 return true;
1081 }
1082 } else {
1083 switch (port->port) {
1084 case PORT_B:
1085 bit = SDE_PORTB_HOTPLUG_CPT;
1086 break;
1087 case PORT_C:
1088 bit = SDE_PORTC_HOTPLUG_CPT;
1089 break;
1090 case PORT_D:
1091 bit = SDE_PORTD_HOTPLUG_CPT;
1092 break;
1093 default:
1094 return true;
1095 }
1096 }
1097
1098 return I915_READ(SDEISR) & bit;
1099 }
1100
1101 static const char *state_string(bool enabled)
1102 {
1103 return enabled ? "on" : "off";
1104 }
1105
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = DPLL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & DPLL_VCO_ENABLE);
1117 I915_STATE_WARN(cur_state != state,
1118 "PLL state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121
1122 /* XXX: the dsi pll is shared between MIPI DSI ports */
1123 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124 {
1125 u32 val;
1126 bool cur_state;
1127
1128 mutex_lock(&dev_priv->sb_lock);
1129 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1130 mutex_unlock(&dev_priv->sb_lock);
1131
1132 cur_state = val & DSI_PLL_VCO_EN;
1133 I915_STATE_WARN(cur_state != state,
1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136 }
1137 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
1140 struct intel_shared_dpll *
1141 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142 {
1143 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
1145 if (crtc->config->shared_dpll < 0)
1146 return NULL;
1147
1148 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1149 }
1150
1151 /* For ILK+ */
1152 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153 struct intel_shared_dpll *pll,
1154 bool state)
1155 {
1156 bool cur_state;
1157 struct intel_dpll_hw_state hw_state;
1158
1159 if (WARN (!pll,
1160 "asserting DPLL %s with no DPLL\n", state_string(state)))
1161 return;
1162
1163 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1164 I915_STATE_WARN(cur_state != state,
1165 "%s assertion failure (expected %s, current %s)\n",
1166 pll->name, state_string(state), state_string(cur_state));
1167 }
1168
1169 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171 {
1172 int reg;
1173 u32 val;
1174 bool cur_state;
1175 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176 pipe);
1177
1178 if (HAS_DDI(dev_priv->dev)) {
1179 /* DDI does not have a specific FDI_TX register */
1180 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1181 val = I915_READ(reg);
1182 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1183 } else {
1184 reg = FDI_TX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_TX_ENABLE);
1187 }
1188 I915_STATE_WARN(cur_state != state,
1189 "FDI TX state assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191 }
1192 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197 {
1198 int reg;
1199 u32 val;
1200 bool cur_state;
1201
1202 reg = FDI_RX_CTL(pipe);
1203 val = I915_READ(reg);
1204 cur_state = !!(val & FDI_RX_ENABLE);
1205 I915_STATE_WARN(cur_state != state,
1206 "FDI RX state assertion failure (expected %s, current %s)\n",
1207 state_string(state), state_string(cur_state));
1208 }
1209 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214 {
1215 int reg;
1216 u32 val;
1217
1218 /* ILK FDI PLL is always enabled */
1219 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1220 return;
1221
1222 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1223 if (HAS_DDI(dev_priv->dev))
1224 return;
1225
1226 reg = FDI_TX_CTL(pipe);
1227 val = I915_READ(reg);
1228 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1229 }
1230
1231 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
1233 {
1234 int reg;
1235 u32 val;
1236 bool cur_state;
1237
1238 reg = FDI_RX_CTL(pipe);
1239 val = I915_READ(reg);
1240 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1241 I915_STATE_WARN(cur_state != state,
1242 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243 state_string(state), state_string(cur_state));
1244 }
1245
1246 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 struct drm_device *dev = dev_priv->dev;
1250 int pp_reg;
1251 u32 val;
1252 enum pipe panel_pipe = PIPE_A;
1253 bool locked = true;
1254
1255 if (WARN_ON(HAS_DDI(dev)))
1256 return;
1257
1258 if (HAS_PCH_SPLIT(dev)) {
1259 u32 port_sel;
1260
1261 pp_reg = PCH_PP_CONTROL;
1262 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266 panel_pipe = PIPE_B;
1267 /* XXX: else fix for eDP */
1268 } else if (IS_VALLEYVIEW(dev)) {
1269 /* presumably write lock depends on pipe, not port select */
1270 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271 panel_pipe = pipe;
1272 } else {
1273 pp_reg = PP_CONTROL;
1274 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275 panel_pipe = PIPE_B;
1276 }
1277
1278 val = I915_READ(pp_reg);
1279 if (!(val & PANEL_POWER_ON) ||
1280 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1281 locked = false;
1282
1283 I915_STATE_WARN(panel_pipe == pipe && locked,
1284 "panel assertion failure, pipe %c regs locked\n",
1285 pipe_name(pipe));
1286 }
1287
1288 static void assert_cursor(struct drm_i915_private *dev_priv,
1289 enum pipe pipe, bool state)
1290 {
1291 struct drm_device *dev = dev_priv->dev;
1292 bool cur_state;
1293
1294 if (IS_845G(dev) || IS_I865G(dev))
1295 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1296 else
1297 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1298
1299 I915_STATE_WARN(cur_state != state,
1300 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301 pipe_name(pipe), state_string(state), state_string(cur_state));
1302 }
1303 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
1306 void assert_pipe(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, bool state)
1308 {
1309 int reg;
1310 u32 val;
1311 bool cur_state;
1312 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313 pipe);
1314
1315 /* if we need the pipe quirk it must be always on */
1316 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1318 state = true;
1319
1320 if (!intel_display_power_is_enabled(dev_priv,
1321 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1322 cur_state = false;
1323 } else {
1324 reg = PIPECONF(cpu_transcoder);
1325 val = I915_READ(reg);
1326 cur_state = !!(val & PIPECONF_ENABLE);
1327 }
1328
1329 I915_STATE_WARN(cur_state != state,
1330 "pipe %c assertion failure (expected %s, current %s)\n",
1331 pipe_name(pipe), state_string(state), state_string(cur_state));
1332 }
1333
1334 static void assert_plane(struct drm_i915_private *dev_priv,
1335 enum plane plane, bool state)
1336 {
1337 int reg;
1338 u32 val;
1339 bool cur_state;
1340
1341 reg = DSPCNTR(plane);
1342 val = I915_READ(reg);
1343 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1344 I915_STATE_WARN(cur_state != state,
1345 "plane %c assertion failure (expected %s, current %s)\n",
1346 plane_name(plane), state_string(state), state_string(cur_state));
1347 }
1348
1349 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
1352 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe pipe)
1354 {
1355 struct drm_device *dev = dev_priv->dev;
1356 int reg, i;
1357 u32 val;
1358 int cur_pipe;
1359
1360 /* Primary planes are fixed to pipes on gen4+ */
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 reg = DSPCNTR(pipe);
1363 val = I915_READ(reg);
1364 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1365 "plane %c assertion failure, should be disabled but not\n",
1366 plane_name(pipe));
1367 return;
1368 }
1369
1370 /* Need to check both planes against the pipe */
1371 for_each_pipe(dev_priv, i) {
1372 reg = DSPCNTR(i);
1373 val = I915_READ(reg);
1374 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375 DISPPLANE_SEL_PIPE_SHIFT;
1376 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1377 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378 plane_name(i), pipe_name(pipe));
1379 }
1380 }
1381
1382 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe)
1384 {
1385 struct drm_device *dev = dev_priv->dev;
1386 int reg, sprite;
1387 u32 val;
1388
1389 if (INTEL_INFO(dev)->gen >= 9) {
1390 for_each_sprite(dev_priv, pipe, sprite) {
1391 val = I915_READ(PLANE_CTL(pipe, sprite));
1392 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1393 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394 sprite, pipe_name(pipe));
1395 }
1396 } else if (IS_VALLEYVIEW(dev)) {
1397 for_each_sprite(dev_priv, pipe, sprite) {
1398 reg = SPCNTR(pipe, sprite);
1399 val = I915_READ(reg);
1400 I915_STATE_WARN(val & SP_ENABLE,
1401 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1402 sprite_name(pipe, sprite), pipe_name(pipe));
1403 }
1404 } else if (INTEL_INFO(dev)->gen >= 7) {
1405 reg = SPRCTL(pipe);
1406 val = I915_READ(reg);
1407 I915_STATE_WARN(val & SPRITE_ENABLE,
1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1409 plane_name(pipe), pipe_name(pipe));
1410 } else if (INTEL_INFO(dev)->gen >= 5) {
1411 reg = DVSCNTR(pipe);
1412 val = I915_READ(reg);
1413 I915_STATE_WARN(val & DVS_ENABLE,
1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415 plane_name(pipe), pipe_name(pipe));
1416 }
1417 }
1418
1419 static void assert_vblank_disabled(struct drm_crtc *crtc)
1420 {
1421 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1422 drm_crtc_vblank_put(crtc);
1423 }
1424
1425 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1426 {
1427 u32 val;
1428 bool enabled;
1429
1430 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1431
1432 val = I915_READ(PCH_DREF_CONTROL);
1433 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434 DREF_SUPERSPREAD_SOURCE_MASK));
1435 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1436 }
1437
1438 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
1440 {
1441 int reg;
1442 u32 val;
1443 bool enabled;
1444
1445 reg = PCH_TRANSCONF(pipe);
1446 val = I915_READ(reg);
1447 enabled = !!(val & TRANS_ENABLE);
1448 I915_STATE_WARN(enabled,
1449 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450 pipe_name(pipe));
1451 }
1452
1453 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, u32 port_sel, u32 val)
1455 {
1456 if ((val & DP_PORT_EN) == 0)
1457 return false;
1458
1459 if (HAS_PCH_CPT(dev_priv->dev)) {
1460 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463 return false;
1464 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466 return false;
1467 } else {
1468 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469 return false;
1470 }
1471 return true;
1472 }
1473
1474 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 val)
1476 {
1477 if ((val & SDVO_ENABLE) == 0)
1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
1481 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1482 return false;
1483 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485 return false;
1486 } else {
1487 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1488 return false;
1489 }
1490 return true;
1491 }
1492
1493 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe, u32 val)
1495 {
1496 if ((val & LVDS_PORT_EN) == 0)
1497 return false;
1498
1499 if (HAS_PCH_CPT(dev_priv->dev)) {
1500 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501 return false;
1502 } else {
1503 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504 return false;
1505 }
1506 return true;
1507 }
1508
1509 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511 {
1512 if ((val & ADPA_DAC_ENABLE) == 0)
1513 return false;
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519 return false;
1520 }
1521 return true;
1522 }
1523
1524 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, int reg, u32 port_sel)
1526 {
1527 u32 val = I915_READ(reg);
1528 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1529 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1530 reg, pipe_name(pipe));
1531
1532 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1533 && (val & DP_PIPEB_SELECT),
1534 "IBX PCH dp port still using transcoder B\n");
1535 }
1536
1537 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538 enum pipe pipe, int reg)
1539 {
1540 u32 val = I915_READ(reg);
1541 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1542 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1543 reg, pipe_name(pipe));
1544
1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1546 && (val & SDVO_PIPE_B_SELECT),
1547 "IBX PCH hdmi port still using transcoder B\n");
1548 }
1549
1550 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe)
1552 {
1553 int reg;
1554 u32 val;
1555
1556 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1559
1560 reg = PCH_ADPA;
1561 val = I915_READ(reg);
1562 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1563 "PCH VGA enabled on transcoder %c, should be disabled\n",
1564 pipe_name(pipe));
1565
1566 reg = PCH_LVDS;
1567 val = I915_READ(reg);
1568 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1570 pipe_name(pipe));
1571
1572 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1575 }
1576
1577 static void intel_init_dpio(struct drm_device *dev)
1578 {
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581 if (!IS_VALLEYVIEW(dev))
1582 return;
1583
1584 /*
1585 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1586 * CHV x1 PHY (DP/HDMI D)
1587 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1588 */
1589 if (IS_CHERRYVIEW(dev)) {
1590 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1591 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1592 } else {
1593 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1594 }
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
1731
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
1777 I915_WRITE(DPLL(pipe), 0);
1778 POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783 u32 val = 0;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
1792 if (pipe == PIPE_B)
1793 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1794 I915_WRITE(DPLL(pipe), val);
1795 POSTING_READ(DPLL(pipe));
1796
1797 }
1798
1799 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1800 {
1801 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1802 u32 val;
1803
1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
1806
1807 /* Set PLL en = 0 */
1808 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1809 if (pipe != PIPE_A)
1810 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1811 I915_WRITE(DPLL(pipe), val);
1812 POSTING_READ(DPLL(pipe));
1813
1814 mutex_lock(&dev_priv->sb_lock);
1815
1816 /* Disable 10bit clock to display controller */
1817 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1818 val &= ~DPIO_DCLKP_EN;
1819 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1820
1821 /* disable left/right clock distribution */
1822 if (pipe != PIPE_B) {
1823 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1824 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1825 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1826 } else {
1827 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1828 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1829 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1830 }
1831
1832 mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
1838 {
1839 u32 port_mask;
1840 int dpll_reg;
1841
1842 switch (dport->port) {
1843 case PORT_B:
1844 port_mask = DPLL_PORTB_READY_MASK;
1845 dpll_reg = DPLL(0);
1846 break;
1847 case PORT_C:
1848 port_mask = DPLL_PORTC_READY_MASK;
1849 dpll_reg = DPLL(0);
1850 expected_mask <<= 4;
1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
1855 break;
1856 default:
1857 BUG();
1858 }
1859
1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871 if (WARN_ON(pll == NULL))
1872 return;
1873
1874 WARN_ON(!pll->config.crtc_mask);
1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882 }
1883
1884 /**
1885 * intel_enable_shared_dpll - enable PCH PLL
1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898 if (WARN_ON(pll == NULL))
1899 return;
1900
1901 if (WARN_ON(pll->config.crtc_mask == 0))
1902 return;
1903
1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905 pll->name, pll->active, pll->on,
1906 crtc->base.base.id);
1907
1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
1910 assert_shared_dpll_enabled(dev_priv, pll);
1911 return;
1912 }
1913 WARN_ON(pll->on);
1914
1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918 pll->enable(dev_priv, pll);
1919 pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928 /* PCH only available on ILK+ */
1929 BUG_ON(INTEL_INFO(dev)->gen < 5);
1930 if (pll == NULL)
1931 return;
1932
1933 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1934 return;
1935
1936 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1937 pll->name, pll->active, pll->on,
1938 crtc->base.base.id);
1939
1940 if (WARN_ON(pll->active == 0)) {
1941 assert_shared_dpll_disabled(dev_priv, pll);
1942 return;
1943 }
1944
1945 assert_shared_dpll_enabled(dev_priv, pll);
1946 WARN_ON(!pll->on);
1947 if (--pll->active)
1948 return;
1949
1950 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1951 pll->disable(dev_priv, pll);
1952 pll->on = false;
1953
1954 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1955 }
1956
1957 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1958 enum pipe pipe)
1959 {
1960 struct drm_device *dev = dev_priv->dev;
1961 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1963 uint32_t reg, val, pipeconf_val;
1964
1965 /* PCH only available on ILK+ */
1966 BUG_ON(!HAS_PCH_SPLIT(dev));
1967
1968 /* Make sure PCH DPLL is enabled */
1969 assert_shared_dpll_enabled(dev_priv,
1970 intel_crtc_to_shared_dpll(intel_crtc));
1971
1972 /* FDI must be feeding us bits for PCH ports */
1973 assert_fdi_tx_enabled(dev_priv, pipe);
1974 assert_fdi_rx_enabled(dev_priv, pipe);
1975
1976 if (HAS_PCH_CPT(dev)) {
1977 /* Workaround: Set the timing override bit before enabling the
1978 * pch transcoder. */
1979 reg = TRANS_CHICKEN2(pipe);
1980 val = I915_READ(reg);
1981 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982 I915_WRITE(reg, val);
1983 }
1984
1985 reg = PCH_TRANSCONF(pipe);
1986 val = I915_READ(reg);
1987 pipeconf_val = I915_READ(PIPECONF(pipe));
1988
1989 if (HAS_PCH_IBX(dev_priv->dev)) {
1990 /*
1991 * Make the BPC in transcoder be consistent with
1992 * that in pipeconf reg. For HDMI we must use 8bpc
1993 * here for both 8bpc and 12bpc.
1994 */
1995 val &= ~PIPECONF_BPC_MASK;
1996 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997 val |= PIPECONF_8BPC;
1998 else
1999 val |= pipeconf_val & PIPECONF_BPC_MASK;
2000 }
2001
2002 val &= ~TRANS_INTERLACE_MASK;
2003 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2004 if (HAS_PCH_IBX(dev_priv->dev) &&
2005 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2006 val |= TRANS_LEGACY_INTERLACED_ILK;
2007 else
2008 val |= TRANS_INTERLACED;
2009 else
2010 val |= TRANS_PROGRESSIVE;
2011
2012 I915_WRITE(reg, val | TRANS_ENABLE);
2013 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2014 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2015 }
2016
2017 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2018 enum transcoder cpu_transcoder)
2019 {
2020 u32 val, pipeconf_val;
2021
2022 /* PCH only available on ILK+ */
2023 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2024
2025 /* FDI must be feeding us bits for PCH ports */
2026 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2027 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2028
2029 /* Workaround: set timing override bit. */
2030 val = I915_READ(_TRANSA_CHICKEN2);
2031 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2032 I915_WRITE(_TRANSA_CHICKEN2, val);
2033
2034 val = TRANS_ENABLE;
2035 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2036
2037 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038 PIPECONF_INTERLACED_ILK)
2039 val |= TRANS_INTERLACED;
2040 else
2041 val |= TRANS_PROGRESSIVE;
2042
2043 I915_WRITE(LPT_TRANSCONF, val);
2044 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2045 DRM_ERROR("Failed to enable PCH transcoder\n");
2046 }
2047
2048 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049 enum pipe pipe)
2050 {
2051 struct drm_device *dev = dev_priv->dev;
2052 uint32_t reg, val;
2053
2054 /* FDI relies on the transcoder */
2055 assert_fdi_tx_disabled(dev_priv, pipe);
2056 assert_fdi_rx_disabled(dev_priv, pipe);
2057
2058 /* Ports must be off as well */
2059 assert_pch_ports_disabled(dev_priv, pipe);
2060
2061 reg = PCH_TRANSCONF(pipe);
2062 val = I915_READ(reg);
2063 val &= ~TRANS_ENABLE;
2064 I915_WRITE(reg, val);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2067 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2068
2069 if (!HAS_PCH_IBX(dev)) {
2070 /* Workaround: Clear the timing override chicken bit again. */
2071 reg = TRANS_CHICKEN2(pipe);
2072 val = I915_READ(reg);
2073 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2074 I915_WRITE(reg, val);
2075 }
2076 }
2077
2078 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2079 {
2080 u32 val;
2081
2082 val = I915_READ(LPT_TRANSCONF);
2083 val &= ~TRANS_ENABLE;
2084 I915_WRITE(LPT_TRANSCONF, val);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2087 DRM_ERROR("Failed to disable PCH transcoder\n");
2088
2089 /* Workaround: clear timing override bit. */
2090 val = I915_READ(_TRANSA_CHICKEN2);
2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092 I915_WRITE(_TRANSA_CHICKEN2, val);
2093 }
2094
2095 /**
2096 * intel_enable_pipe - enable a pipe, asserting requirements
2097 * @crtc: crtc responsible for the pipe
2098 *
2099 * Enable @crtc's pipe, making sure that various hardware specific requirements
2100 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2101 */
2102 static void intel_enable_pipe(struct intel_crtc *crtc)
2103 {
2104 struct drm_device *dev = crtc->base.dev;
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 enum pipe pipe = crtc->pipe;
2107 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2108 pipe);
2109 enum pipe pch_transcoder;
2110 int reg;
2111 u32 val;
2112
2113 assert_planes_disabled(dev_priv, pipe);
2114 assert_cursor_disabled(dev_priv, pipe);
2115 assert_sprites_disabled(dev_priv, pipe);
2116
2117 if (HAS_PCH_LPT(dev_priv->dev))
2118 pch_transcoder = TRANSCODER_A;
2119 else
2120 pch_transcoder = pipe;
2121
2122 /*
2123 * A pipe without a PLL won't actually be able to drive bits from
2124 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2125 * need the check.
2126 */
2127 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2129 assert_dsi_pll_enabled(dev_priv);
2130 else
2131 assert_pll_enabled(dev_priv, pipe);
2132 else {
2133 if (crtc->config->has_pch_encoder) {
2134 /* if driving the PCH, we need FDI enabled */
2135 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2136 assert_fdi_tx_pll_enabled(dev_priv,
2137 (enum pipe) cpu_transcoder);
2138 }
2139 /* FIXME: assert CPU port conditions for SNB+ */
2140 }
2141
2142 reg = PIPECONF(cpu_transcoder);
2143 val = I915_READ(reg);
2144 if (val & PIPECONF_ENABLE) {
2145 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2146 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2147 return;
2148 }
2149
2150 I915_WRITE(reg, val | PIPECONF_ENABLE);
2151 POSTING_READ(reg);
2152 }
2153
2154 /**
2155 * intel_disable_pipe - disable a pipe, asserting requirements
2156 * @crtc: crtc whose pipes is to be disabled
2157 *
2158 * Disable the pipe of @crtc, making sure that various hardware
2159 * specific requirements are met, if applicable, e.g. plane
2160 * disabled, panel fitter off, etc.
2161 *
2162 * Will wait until the pipe has shut down before returning.
2163 */
2164 static void intel_disable_pipe(struct intel_crtc *crtc)
2165 {
2166 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2167 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2168 enum pipe pipe = crtc->pipe;
2169 int reg;
2170 u32 val;
2171
2172 /*
2173 * Make sure planes won't keep trying to pump pixels to us,
2174 * or we might hang the display.
2175 */
2176 assert_planes_disabled(dev_priv, pipe);
2177 assert_cursor_disabled(dev_priv, pipe);
2178 assert_sprites_disabled(dev_priv, pipe);
2179
2180 reg = PIPECONF(cpu_transcoder);
2181 val = I915_READ(reg);
2182 if ((val & PIPECONF_ENABLE) == 0)
2183 return;
2184
2185 /*
2186 * Double wide has implications for planes
2187 * so best keep it disabled when not needed.
2188 */
2189 if (crtc->config->double_wide)
2190 val &= ~PIPECONF_DOUBLE_WIDE;
2191
2192 /* Don't disable pipe or pipe PLLs if needed */
2193 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2194 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2195 val &= ~PIPECONF_ENABLE;
2196
2197 I915_WRITE(reg, val);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 intel_wait_for_pipe_off(crtc);
2200 }
2201
2202 static bool need_vtd_wa(struct drm_device *dev)
2203 {
2204 #ifdef CONFIG_INTEL_IOMMU
2205 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2206 return true;
2207 #endif
2208 return false;
2209 }
2210
2211 unsigned int
2212 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2213 uint64_t fb_format_modifier)
2214 {
2215 unsigned int tile_height;
2216 uint32_t pixel_bytes;
2217
2218 switch (fb_format_modifier) {
2219 case DRM_FORMAT_MOD_NONE:
2220 tile_height = 1;
2221 break;
2222 case I915_FORMAT_MOD_X_TILED:
2223 tile_height = IS_GEN2(dev) ? 16 : 8;
2224 break;
2225 case I915_FORMAT_MOD_Y_TILED:
2226 tile_height = 32;
2227 break;
2228 case I915_FORMAT_MOD_Yf_TILED:
2229 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2230 switch (pixel_bytes) {
2231 default:
2232 case 1:
2233 tile_height = 64;
2234 break;
2235 case 2:
2236 case 4:
2237 tile_height = 32;
2238 break;
2239 case 8:
2240 tile_height = 16;
2241 break;
2242 case 16:
2243 WARN_ONCE(1,
2244 "128-bit pixels are not supported for display!");
2245 tile_height = 16;
2246 break;
2247 }
2248 break;
2249 default:
2250 MISSING_CASE(fb_format_modifier);
2251 tile_height = 1;
2252 break;
2253 }
2254
2255 return tile_height;
2256 }
2257
2258 unsigned int
2259 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2260 uint32_t pixel_format, uint64_t fb_format_modifier)
2261 {
2262 return ALIGN(height, intel_tile_height(dev, pixel_format,
2263 fb_format_modifier));
2264 }
2265
2266 static int
2267 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2268 const struct drm_plane_state *plane_state)
2269 {
2270 struct intel_rotation_info *info = &view->rotation_info;
2271
2272 *view = i915_ggtt_view_normal;
2273
2274 if (!plane_state)
2275 return 0;
2276
2277 if (!intel_rotation_90_or_270(plane_state->rotation))
2278 return 0;
2279
2280 *view = i915_ggtt_view_rotated;
2281
2282 info->height = fb->height;
2283 info->pixel_format = fb->pixel_format;
2284 info->pitch = fb->pitches[0];
2285 info->fb_modifier = fb->modifier[0];
2286
2287 return 0;
2288 }
2289
2290 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2291 {
2292 if (INTEL_INFO(dev_priv)->gen >= 9)
2293 return 256 * 1024;
2294 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2295 IS_VALLEYVIEW(dev_priv))
2296 return 128 * 1024;
2297 else if (INTEL_INFO(dev_priv)->gen >= 4)
2298 return 4 * 1024;
2299 else
2300 return 0;
2301 }
2302
2303 int
2304 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2305 struct drm_framebuffer *fb,
2306 const struct drm_plane_state *plane_state,
2307 struct intel_engine_cs *pipelined,
2308 struct drm_i915_gem_request **pipelined_request)
2309 {
2310 struct drm_device *dev = fb->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2313 struct i915_ggtt_view view;
2314 u32 alignment;
2315 int ret;
2316
2317 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2318
2319 switch (fb->modifier[0]) {
2320 case DRM_FORMAT_MOD_NONE:
2321 alignment = intel_linear_alignment(dev_priv);
2322 break;
2323 case I915_FORMAT_MOD_X_TILED:
2324 if (INTEL_INFO(dev)->gen >= 9)
2325 alignment = 256 * 1024;
2326 else {
2327 /* pin() will align the object as required by fence */
2328 alignment = 0;
2329 }
2330 break;
2331 case I915_FORMAT_MOD_Y_TILED:
2332 case I915_FORMAT_MOD_Yf_TILED:
2333 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2334 "Y tiling bo slipped through, driver bug!\n"))
2335 return -EINVAL;
2336 alignment = 1 * 1024 * 1024;
2337 break;
2338 default:
2339 MISSING_CASE(fb->modifier[0]);
2340 return -EINVAL;
2341 }
2342
2343 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2344 if (ret)
2345 return ret;
2346
2347 /* Note that the w/a also requires 64 PTE of padding following the
2348 * bo. We currently fill all unused PTE with the shadow page and so
2349 * we should always have valid PTE following the scanout preventing
2350 * the VT-d warning.
2351 */
2352 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2353 alignment = 256 * 1024;
2354
2355 /*
2356 * Global gtt pte registers are special registers which actually forward
2357 * writes to a chunk of system memory. Which means that there is no risk
2358 * that the register values disappear as soon as we call
2359 * intel_runtime_pm_put(), so it is correct to wrap only the
2360 * pin/unpin/fence and not more.
2361 */
2362 intel_runtime_pm_get(dev_priv);
2363
2364 dev_priv->mm.interruptible = false;
2365 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2366 pipelined_request, &view);
2367 if (ret)
2368 goto err_interruptible;
2369
2370 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2371 * fence, whereas 965+ only requires a fence if using
2372 * framebuffer compression. For simplicity, we always install
2373 * a fence as the cost is not that onerous.
2374 */
2375 ret = i915_gem_object_get_fence(obj);
2376 if (ret)
2377 goto err_unpin;
2378
2379 i915_gem_object_pin_fence(obj);
2380
2381 dev_priv->mm.interruptible = true;
2382 intel_runtime_pm_put(dev_priv);
2383 return 0;
2384
2385 err_unpin:
2386 i915_gem_object_unpin_from_display_plane(obj, &view);
2387 err_interruptible:
2388 dev_priv->mm.interruptible = true;
2389 intel_runtime_pm_put(dev_priv);
2390 return ret;
2391 }
2392
2393 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2394 const struct drm_plane_state *plane_state)
2395 {
2396 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2397 struct i915_ggtt_view view;
2398 int ret;
2399
2400 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2401
2402 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2403 WARN_ONCE(ret, "Couldn't get view from plane state!");
2404
2405 i915_gem_object_unpin_fence(obj);
2406 i915_gem_object_unpin_from_display_plane(obj, &view);
2407 }
2408
2409 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2410 * is assumed to be a power-of-two. */
2411 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2412 int *x, int *y,
2413 unsigned int tiling_mode,
2414 unsigned int cpp,
2415 unsigned int pitch)
2416 {
2417 if (tiling_mode != I915_TILING_NONE) {
2418 unsigned int tile_rows, tiles;
2419
2420 tile_rows = *y / 8;
2421 *y %= 8;
2422
2423 tiles = *x / (512/cpp);
2424 *x %= 512/cpp;
2425
2426 return tile_rows * pitch * 8 + tiles * 4096;
2427 } else {
2428 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2429 unsigned int offset;
2430
2431 offset = *y * pitch + *x * cpp;
2432 *y = (offset & alignment) / pitch;
2433 *x = ((offset & alignment) - *y * pitch) / cpp;
2434 return offset & ~alignment;
2435 }
2436 }
2437
2438 static int i9xx_format_to_fourcc(int format)
2439 {
2440 switch (format) {
2441 case DISPPLANE_8BPP:
2442 return DRM_FORMAT_C8;
2443 case DISPPLANE_BGRX555:
2444 return DRM_FORMAT_XRGB1555;
2445 case DISPPLANE_BGRX565:
2446 return DRM_FORMAT_RGB565;
2447 default:
2448 case DISPPLANE_BGRX888:
2449 return DRM_FORMAT_XRGB8888;
2450 case DISPPLANE_RGBX888:
2451 return DRM_FORMAT_XBGR8888;
2452 case DISPPLANE_BGRX101010:
2453 return DRM_FORMAT_XRGB2101010;
2454 case DISPPLANE_RGBX101010:
2455 return DRM_FORMAT_XBGR2101010;
2456 }
2457 }
2458
2459 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2460 {
2461 switch (format) {
2462 case PLANE_CTL_FORMAT_RGB_565:
2463 return DRM_FORMAT_RGB565;
2464 default:
2465 case PLANE_CTL_FORMAT_XRGB_8888:
2466 if (rgb_order) {
2467 if (alpha)
2468 return DRM_FORMAT_ABGR8888;
2469 else
2470 return DRM_FORMAT_XBGR8888;
2471 } else {
2472 if (alpha)
2473 return DRM_FORMAT_ARGB8888;
2474 else
2475 return DRM_FORMAT_XRGB8888;
2476 }
2477 case PLANE_CTL_FORMAT_XRGB_2101010:
2478 if (rgb_order)
2479 return DRM_FORMAT_XBGR2101010;
2480 else
2481 return DRM_FORMAT_XRGB2101010;
2482 }
2483 }
2484
2485 static bool
2486 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2487 struct intel_initial_plane_config *plane_config)
2488 {
2489 struct drm_device *dev = crtc->base.dev;
2490 struct drm_i915_gem_object *obj = NULL;
2491 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2492 struct drm_framebuffer *fb = &plane_config->fb->base;
2493 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2494 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2495 PAGE_SIZE);
2496
2497 size_aligned -= base_aligned;
2498
2499 if (plane_config->size == 0)
2500 return false;
2501
2502 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2503 base_aligned,
2504 base_aligned,
2505 size_aligned);
2506 if (!obj)
2507 return false;
2508
2509 obj->tiling_mode = plane_config->tiling;
2510 if (obj->tiling_mode == I915_TILING_X)
2511 obj->stride = fb->pitches[0];
2512
2513 mode_cmd.pixel_format = fb->pixel_format;
2514 mode_cmd.width = fb->width;
2515 mode_cmd.height = fb->height;
2516 mode_cmd.pitches[0] = fb->pitches[0];
2517 mode_cmd.modifier[0] = fb->modifier[0];
2518 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2519
2520 mutex_lock(&dev->struct_mutex);
2521 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2522 &mode_cmd, obj)) {
2523 DRM_DEBUG_KMS("intel fb init failed\n");
2524 goto out_unref_obj;
2525 }
2526 mutex_unlock(&dev->struct_mutex);
2527
2528 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2529 return true;
2530
2531 out_unref_obj:
2532 drm_gem_object_unreference(&obj->base);
2533 mutex_unlock(&dev->struct_mutex);
2534 return false;
2535 }
2536
2537 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2538 static void
2539 update_state_fb(struct drm_plane *plane)
2540 {
2541 if (plane->fb == plane->state->fb)
2542 return;
2543
2544 if (plane->state->fb)
2545 drm_framebuffer_unreference(plane->state->fb);
2546 plane->state->fb = plane->fb;
2547 if (plane->state->fb)
2548 drm_framebuffer_reference(plane->state->fb);
2549 }
2550
2551 static void
2552 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2553 struct intel_initial_plane_config *plane_config)
2554 {
2555 struct drm_device *dev = intel_crtc->base.dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct drm_crtc *c;
2558 struct intel_crtc *i;
2559 struct drm_i915_gem_object *obj;
2560 struct drm_plane *primary = intel_crtc->base.primary;
2561 struct drm_framebuffer *fb;
2562
2563 if (!plane_config->fb)
2564 return;
2565
2566 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2567 fb = &plane_config->fb->base;
2568 goto valid_fb;
2569 }
2570
2571 kfree(plane_config->fb);
2572
2573 /*
2574 * Failed to alloc the obj, check to see if we should share
2575 * an fb with another CRTC instead
2576 */
2577 for_each_crtc(dev, c) {
2578 i = to_intel_crtc(c);
2579
2580 if (c == &intel_crtc->base)
2581 continue;
2582
2583 if (!i->active)
2584 continue;
2585
2586 fb = c->primary->fb;
2587 if (!fb)
2588 continue;
2589
2590 obj = intel_fb_obj(fb);
2591 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2592 drm_framebuffer_reference(fb);
2593 goto valid_fb;
2594 }
2595 }
2596
2597 return;
2598
2599 valid_fb:
2600 obj = intel_fb_obj(fb);
2601 if (obj->tiling_mode != I915_TILING_NONE)
2602 dev_priv->preserve_bios_swizzle = true;
2603
2604 primary->fb = fb;
2605 primary->crtc = primary->state->crtc = &intel_crtc->base;
2606 update_state_fb(primary);
2607 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2608 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2609 }
2610
2611 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2612 struct drm_framebuffer *fb,
2613 int x, int y)
2614 {
2615 struct drm_device *dev = crtc->dev;
2616 struct drm_i915_private *dev_priv = dev->dev_private;
2617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618 struct drm_plane *primary = crtc->primary;
2619 bool visible = to_intel_plane_state(primary->state)->visible;
2620 struct drm_i915_gem_object *obj;
2621 int plane = intel_crtc->plane;
2622 unsigned long linear_offset;
2623 u32 dspcntr;
2624 u32 reg = DSPCNTR(plane);
2625 int pixel_size;
2626
2627 if (!visible || !fb) {
2628 I915_WRITE(reg, 0);
2629 if (INTEL_INFO(dev)->gen >= 4)
2630 I915_WRITE(DSPSURF(plane), 0);
2631 else
2632 I915_WRITE(DSPADDR(plane), 0);
2633 POSTING_READ(reg);
2634 return;
2635 }
2636
2637 obj = intel_fb_obj(fb);
2638 if (WARN_ON(obj == NULL))
2639 return;
2640
2641 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2642
2643 dspcntr = DISPPLANE_GAMMA_ENABLE;
2644
2645 dspcntr |= DISPLAY_PLANE_ENABLE;
2646
2647 if (INTEL_INFO(dev)->gen < 4) {
2648 if (intel_crtc->pipe == PIPE_B)
2649 dspcntr |= DISPPLANE_SEL_PIPE_B;
2650
2651 /* pipesrc and dspsize control the size that is scaled from,
2652 * which should always be the user's requested size.
2653 */
2654 I915_WRITE(DSPSIZE(plane),
2655 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2656 (intel_crtc->config->pipe_src_w - 1));
2657 I915_WRITE(DSPPOS(plane), 0);
2658 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2659 I915_WRITE(PRIMSIZE(plane),
2660 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2661 (intel_crtc->config->pipe_src_w - 1));
2662 I915_WRITE(PRIMPOS(plane), 0);
2663 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2664 }
2665
2666 switch (fb->pixel_format) {
2667 case DRM_FORMAT_C8:
2668 dspcntr |= DISPPLANE_8BPP;
2669 break;
2670 case DRM_FORMAT_XRGB1555:
2671 dspcntr |= DISPPLANE_BGRX555;
2672 break;
2673 case DRM_FORMAT_RGB565:
2674 dspcntr |= DISPPLANE_BGRX565;
2675 break;
2676 case DRM_FORMAT_XRGB8888:
2677 dspcntr |= DISPPLANE_BGRX888;
2678 break;
2679 case DRM_FORMAT_XBGR8888:
2680 dspcntr |= DISPPLANE_RGBX888;
2681 break;
2682 case DRM_FORMAT_XRGB2101010:
2683 dspcntr |= DISPPLANE_BGRX101010;
2684 break;
2685 case DRM_FORMAT_XBGR2101010:
2686 dspcntr |= DISPPLANE_RGBX101010;
2687 break;
2688 default:
2689 BUG();
2690 }
2691
2692 if (INTEL_INFO(dev)->gen >= 4 &&
2693 obj->tiling_mode != I915_TILING_NONE)
2694 dspcntr |= DISPPLANE_TILED;
2695
2696 if (IS_G4X(dev))
2697 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2698
2699 linear_offset = y * fb->pitches[0] + x * pixel_size;
2700
2701 if (INTEL_INFO(dev)->gen >= 4) {
2702 intel_crtc->dspaddr_offset =
2703 intel_gen4_compute_page_offset(dev_priv,
2704 &x, &y, obj->tiling_mode,
2705 pixel_size,
2706 fb->pitches[0]);
2707 linear_offset -= intel_crtc->dspaddr_offset;
2708 } else {
2709 intel_crtc->dspaddr_offset = linear_offset;
2710 }
2711
2712 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2713 dspcntr |= DISPPLANE_ROTATE_180;
2714
2715 x += (intel_crtc->config->pipe_src_w - 1);
2716 y += (intel_crtc->config->pipe_src_h - 1);
2717
2718 /* Finding the last pixel of the last line of the display
2719 data and adding to linear_offset*/
2720 linear_offset +=
2721 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2722 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2723 }
2724
2725 I915_WRITE(reg, dspcntr);
2726
2727 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2728 if (INTEL_INFO(dev)->gen >= 4) {
2729 I915_WRITE(DSPSURF(plane),
2730 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2731 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2732 I915_WRITE(DSPLINOFF(plane), linear_offset);
2733 } else
2734 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2735 POSTING_READ(reg);
2736 }
2737
2738 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2739 struct drm_framebuffer *fb,
2740 int x, int y)
2741 {
2742 struct drm_device *dev = crtc->dev;
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2745 struct drm_plane *primary = crtc->primary;
2746 bool visible = to_intel_plane_state(primary->state)->visible;
2747 struct drm_i915_gem_object *obj;
2748 int plane = intel_crtc->plane;
2749 unsigned long linear_offset;
2750 u32 dspcntr;
2751 u32 reg = DSPCNTR(plane);
2752 int pixel_size;
2753
2754 if (!visible || !fb) {
2755 I915_WRITE(reg, 0);
2756 I915_WRITE(DSPSURF(plane), 0);
2757 POSTING_READ(reg);
2758 return;
2759 }
2760
2761 obj = intel_fb_obj(fb);
2762 if (WARN_ON(obj == NULL))
2763 return;
2764
2765 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2766
2767 dspcntr = DISPPLANE_GAMMA_ENABLE;
2768
2769 dspcntr |= DISPLAY_PLANE_ENABLE;
2770
2771 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2772 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2773
2774 switch (fb->pixel_format) {
2775 case DRM_FORMAT_C8:
2776 dspcntr |= DISPPLANE_8BPP;
2777 break;
2778 case DRM_FORMAT_RGB565:
2779 dspcntr |= DISPPLANE_BGRX565;
2780 break;
2781 case DRM_FORMAT_XRGB8888:
2782 dspcntr |= DISPPLANE_BGRX888;
2783 break;
2784 case DRM_FORMAT_XBGR8888:
2785 dspcntr |= DISPPLANE_RGBX888;
2786 break;
2787 case DRM_FORMAT_XRGB2101010:
2788 dspcntr |= DISPPLANE_BGRX101010;
2789 break;
2790 case DRM_FORMAT_XBGR2101010:
2791 dspcntr |= DISPPLANE_RGBX101010;
2792 break;
2793 default:
2794 BUG();
2795 }
2796
2797 if (obj->tiling_mode != I915_TILING_NONE)
2798 dspcntr |= DISPPLANE_TILED;
2799
2800 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2801 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2802
2803 linear_offset = y * fb->pitches[0] + x * pixel_size;
2804 intel_crtc->dspaddr_offset =
2805 intel_gen4_compute_page_offset(dev_priv,
2806 &x, &y, obj->tiling_mode,
2807 pixel_size,
2808 fb->pitches[0]);
2809 linear_offset -= intel_crtc->dspaddr_offset;
2810 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2811 dspcntr |= DISPPLANE_ROTATE_180;
2812
2813 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2814 x += (intel_crtc->config->pipe_src_w - 1);
2815 y += (intel_crtc->config->pipe_src_h - 1);
2816
2817 /* Finding the last pixel of the last line of the display
2818 data and adding to linear_offset*/
2819 linear_offset +=
2820 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2821 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2822 }
2823 }
2824
2825 I915_WRITE(reg, dspcntr);
2826
2827 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2828 I915_WRITE(DSPSURF(plane),
2829 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2830 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2831 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2832 } else {
2833 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2834 I915_WRITE(DSPLINOFF(plane), linear_offset);
2835 }
2836 POSTING_READ(reg);
2837 }
2838
2839 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2840 uint32_t pixel_format)
2841 {
2842 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2843
2844 /*
2845 * The stride is either expressed as a multiple of 64 bytes
2846 * chunks for linear buffers or in number of tiles for tiled
2847 * buffers.
2848 */
2849 switch (fb_modifier) {
2850 case DRM_FORMAT_MOD_NONE:
2851 return 64;
2852 case I915_FORMAT_MOD_X_TILED:
2853 if (INTEL_INFO(dev)->gen == 2)
2854 return 128;
2855 return 512;
2856 case I915_FORMAT_MOD_Y_TILED:
2857 /* No need to check for old gens and Y tiling since this is
2858 * about the display engine and those will be blocked before
2859 * we get here.
2860 */
2861 return 128;
2862 case I915_FORMAT_MOD_Yf_TILED:
2863 if (bits_per_pixel == 8)
2864 return 64;
2865 else
2866 return 128;
2867 default:
2868 MISSING_CASE(fb_modifier);
2869 return 64;
2870 }
2871 }
2872
2873 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2874 struct drm_i915_gem_object *obj)
2875 {
2876 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2877
2878 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2879 view = &i915_ggtt_view_rotated;
2880
2881 return i915_gem_obj_ggtt_offset_view(obj, view);
2882 }
2883
2884 /*
2885 * This function detaches (aka. unbinds) unused scalers in hardware
2886 */
2887 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2888 {
2889 struct drm_device *dev;
2890 struct drm_i915_private *dev_priv;
2891 struct intel_crtc_scaler_state *scaler_state;
2892 int i;
2893
2894 dev = intel_crtc->base.dev;
2895 dev_priv = dev->dev_private;
2896 scaler_state = &intel_crtc->config->scaler_state;
2897
2898 /* loop through and disable scalers that aren't in use */
2899 for (i = 0; i < intel_crtc->num_scalers; i++) {
2900 if (!scaler_state->scalers[i].in_use) {
2901 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2902 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2903 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2904 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2905 intel_crtc->base.base.id, intel_crtc->pipe, i);
2906 }
2907 }
2908 }
2909
2910 u32 skl_plane_ctl_format(uint32_t pixel_format)
2911 {
2912 switch (pixel_format) {
2913 case DRM_FORMAT_C8:
2914 return PLANE_CTL_FORMAT_INDEXED;
2915 case DRM_FORMAT_RGB565:
2916 return PLANE_CTL_FORMAT_RGB_565;
2917 case DRM_FORMAT_XBGR8888:
2918 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2919 case DRM_FORMAT_XRGB8888:
2920 return PLANE_CTL_FORMAT_XRGB_8888;
2921 /*
2922 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2923 * to be already pre-multiplied. We need to add a knob (or a different
2924 * DRM_FORMAT) for user-space to configure that.
2925 */
2926 case DRM_FORMAT_ABGR8888:
2927 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2928 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2929 case DRM_FORMAT_ARGB8888:
2930 return PLANE_CTL_FORMAT_XRGB_8888 |
2931 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2932 case DRM_FORMAT_XRGB2101010:
2933 return PLANE_CTL_FORMAT_XRGB_2101010;
2934 case DRM_FORMAT_XBGR2101010:
2935 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2936 case DRM_FORMAT_YUYV:
2937 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2938 case DRM_FORMAT_YVYU:
2939 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2940 case DRM_FORMAT_UYVY:
2941 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2942 case DRM_FORMAT_VYUY:
2943 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2944 default:
2945 MISSING_CASE(pixel_format);
2946 }
2947
2948 return 0;
2949 }
2950
2951 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2952 {
2953 switch (fb_modifier) {
2954 case DRM_FORMAT_MOD_NONE:
2955 break;
2956 case I915_FORMAT_MOD_X_TILED:
2957 return PLANE_CTL_TILED_X;
2958 case I915_FORMAT_MOD_Y_TILED:
2959 return PLANE_CTL_TILED_Y;
2960 case I915_FORMAT_MOD_Yf_TILED:
2961 return PLANE_CTL_TILED_YF;
2962 default:
2963 MISSING_CASE(fb_modifier);
2964 }
2965
2966 return 0;
2967 }
2968
2969 u32 skl_plane_ctl_rotation(unsigned int rotation)
2970 {
2971 switch (rotation) {
2972 case BIT(DRM_ROTATE_0):
2973 break;
2974 /*
2975 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2976 * while i915 HW rotation is clockwise, thats why this swapping.
2977 */
2978 case BIT(DRM_ROTATE_90):
2979 return PLANE_CTL_ROTATE_270;
2980 case BIT(DRM_ROTATE_180):
2981 return PLANE_CTL_ROTATE_180;
2982 case BIT(DRM_ROTATE_270):
2983 return PLANE_CTL_ROTATE_90;
2984 default:
2985 MISSING_CASE(rotation);
2986 }
2987
2988 return 0;
2989 }
2990
2991 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2992 struct drm_framebuffer *fb,
2993 int x, int y)
2994 {
2995 struct drm_device *dev = crtc->dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998 struct drm_plane *plane = crtc->primary;
2999 bool visible = to_intel_plane_state(plane->state)->visible;
3000 struct drm_i915_gem_object *obj;
3001 int pipe = intel_crtc->pipe;
3002 u32 plane_ctl, stride_div, stride;
3003 u32 tile_height, plane_offset, plane_size;
3004 unsigned int rotation;
3005 int x_offset, y_offset;
3006 unsigned long surf_addr;
3007 struct intel_crtc_state *crtc_state = intel_crtc->config;
3008 struct intel_plane_state *plane_state;
3009 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3010 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3011 int scaler_id = -1;
3012
3013 plane_state = to_intel_plane_state(plane->state);
3014
3015 if (!visible || !fb) {
3016 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3017 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3018 POSTING_READ(PLANE_CTL(pipe, 0));
3019 return;
3020 }
3021
3022 plane_ctl = PLANE_CTL_ENABLE |
3023 PLANE_CTL_PIPE_GAMMA_ENABLE |
3024 PLANE_CTL_PIPE_CSC_ENABLE;
3025
3026 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3027 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3028 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3029
3030 rotation = plane->state->rotation;
3031 plane_ctl |= skl_plane_ctl_rotation(rotation);
3032
3033 obj = intel_fb_obj(fb);
3034 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3035 fb->pixel_format);
3036 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3037
3038 /*
3039 * FIXME: intel_plane_state->src, dst aren't set when transitional
3040 * update_plane helpers are called from legacy paths.
3041 * Once full atomic crtc is available, below check can be avoided.
3042 */
3043 if (drm_rect_width(&plane_state->src)) {
3044 scaler_id = plane_state->scaler_id;
3045 src_x = plane_state->src.x1 >> 16;
3046 src_y = plane_state->src.y1 >> 16;
3047 src_w = drm_rect_width(&plane_state->src) >> 16;
3048 src_h = drm_rect_height(&plane_state->src) >> 16;
3049 dst_x = plane_state->dst.x1;
3050 dst_y = plane_state->dst.y1;
3051 dst_w = drm_rect_width(&plane_state->dst);
3052 dst_h = drm_rect_height(&plane_state->dst);
3053
3054 WARN_ON(x != src_x || y != src_y);
3055 } else {
3056 src_w = intel_crtc->config->pipe_src_w;
3057 src_h = intel_crtc->config->pipe_src_h;
3058 }
3059
3060 if (intel_rotation_90_or_270(rotation)) {
3061 /* stride = Surface height in tiles */
3062 tile_height = intel_tile_height(dev, fb->pixel_format,
3063 fb->modifier[0]);
3064 stride = DIV_ROUND_UP(fb->height, tile_height);
3065 x_offset = stride * tile_height - y - src_h;
3066 y_offset = x;
3067 plane_size = (src_w - 1) << 16 | (src_h - 1);
3068 } else {
3069 stride = fb->pitches[0] / stride_div;
3070 x_offset = x;
3071 y_offset = y;
3072 plane_size = (src_h - 1) << 16 | (src_w - 1);
3073 }
3074 plane_offset = y_offset << 16 | x_offset;
3075
3076 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3077 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3078 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3079 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3080
3081 if (scaler_id >= 0) {
3082 uint32_t ps_ctrl = 0;
3083
3084 WARN_ON(!dst_w || !dst_h);
3085 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3086 crtc_state->scaler_state.scalers[scaler_id].mode;
3087 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3088 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3089 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3090 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3091 I915_WRITE(PLANE_POS(pipe, 0), 0);
3092 } else {
3093 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3094 }
3095
3096 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3097
3098 POSTING_READ(PLANE_SURF(pipe, 0));
3099 }
3100
3101 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3102 static int
3103 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3104 int x, int y, enum mode_set_atomic state)
3105 {
3106 struct drm_device *dev = crtc->dev;
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108
3109 if (dev_priv->display.disable_fbc)
3110 dev_priv->display.disable_fbc(dev);
3111
3112 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3113
3114 return 0;
3115 }
3116
3117 static void intel_complete_page_flips(struct drm_device *dev)
3118 {
3119 struct drm_crtc *crtc;
3120
3121 for_each_crtc(dev, crtc) {
3122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3123 enum plane plane = intel_crtc->plane;
3124
3125 intel_prepare_page_flip(dev, plane);
3126 intel_finish_page_flip_plane(dev, plane);
3127 }
3128 }
3129
3130 static void intel_update_primary_planes(struct drm_device *dev)
3131 {
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133 struct drm_crtc *crtc;
3134
3135 for_each_crtc(dev, crtc) {
3136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3137
3138 drm_modeset_lock(&crtc->mutex, NULL);
3139 /*
3140 * FIXME: Once we have proper support for primary planes (and
3141 * disabling them without disabling the entire crtc) allow again
3142 * a NULL crtc->primary->fb.
3143 */
3144 if (intel_crtc->active && crtc->primary->fb)
3145 dev_priv->display.update_primary_plane(crtc,
3146 crtc->primary->fb,
3147 crtc->x,
3148 crtc->y);
3149 drm_modeset_unlock(&crtc->mutex);
3150 }
3151 }
3152
3153 void intel_prepare_reset(struct drm_device *dev)
3154 {
3155 /* no reset support for gen2 */
3156 if (IS_GEN2(dev))
3157 return;
3158
3159 /* reset doesn't touch the display */
3160 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3161 return;
3162
3163 drm_modeset_lock_all(dev);
3164 /*
3165 * Disabling the crtcs gracefully seems nicer. Also the
3166 * g33 docs say we should at least disable all the planes.
3167 */
3168 intel_display_suspend(dev);
3169 }
3170
3171 void intel_finish_reset(struct drm_device *dev)
3172 {
3173 struct drm_i915_private *dev_priv = to_i915(dev);
3174
3175 /*
3176 * Flips in the rings will be nuked by the reset,
3177 * so complete all pending flips so that user space
3178 * will get its events and not get stuck.
3179 */
3180 intel_complete_page_flips(dev);
3181
3182 /* no reset support for gen2 */
3183 if (IS_GEN2(dev))
3184 return;
3185
3186 /* reset doesn't touch the display */
3187 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3188 /*
3189 * Flips in the rings have been nuked by the reset,
3190 * so update the base address of all primary
3191 * planes to the the last fb to make sure we're
3192 * showing the correct fb after a reset.
3193 */
3194 intel_update_primary_planes(dev);
3195 return;
3196 }
3197
3198 /*
3199 * The display has been reset as well,
3200 * so need a full re-initialization.
3201 */
3202 intel_runtime_pm_disable_interrupts(dev_priv);
3203 intel_runtime_pm_enable_interrupts(dev_priv);
3204
3205 intel_modeset_init_hw(dev);
3206
3207 spin_lock_irq(&dev_priv->irq_lock);
3208 if (dev_priv->display.hpd_irq_setup)
3209 dev_priv->display.hpd_irq_setup(dev);
3210 spin_unlock_irq(&dev_priv->irq_lock);
3211
3212 intel_modeset_setup_hw_state(dev, true);
3213
3214 intel_hpd_init(dev_priv);
3215
3216 drm_modeset_unlock_all(dev);
3217 }
3218
3219 static void
3220 intel_finish_fb(struct drm_framebuffer *old_fb)
3221 {
3222 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3223 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3224 bool was_interruptible = dev_priv->mm.interruptible;
3225 int ret;
3226
3227 /* Big Hammer, we also need to ensure that any pending
3228 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3229 * current scanout is retired before unpinning the old
3230 * framebuffer. Note that we rely on userspace rendering
3231 * into the buffer attached to the pipe they are waiting
3232 * on. If not, userspace generates a GPU hang with IPEHR
3233 * point to the MI_WAIT_FOR_EVENT.
3234 *
3235 * This should only fail upon a hung GPU, in which case we
3236 * can safely continue.
3237 */
3238 dev_priv->mm.interruptible = false;
3239 ret = i915_gem_object_wait_rendering(obj, true);
3240 dev_priv->mm.interruptible = was_interruptible;
3241
3242 WARN_ON(ret);
3243 }
3244
3245 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3246 {
3247 struct drm_device *dev = crtc->dev;
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3250 bool pending;
3251
3252 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3253 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3254 return false;
3255
3256 spin_lock_irq(&dev->event_lock);
3257 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3258 spin_unlock_irq(&dev->event_lock);
3259
3260 return pending;
3261 }
3262
3263 static void intel_update_pipe_size(struct intel_crtc *crtc)
3264 {
3265 struct drm_device *dev = crtc->base.dev;
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267 const struct drm_display_mode *adjusted_mode;
3268
3269 if (!i915.fastboot)
3270 return;
3271
3272 /*
3273 * Update pipe size and adjust fitter if needed: the reason for this is
3274 * that in compute_mode_changes we check the native mode (not the pfit
3275 * mode) to see if we can flip rather than do a full mode set. In the
3276 * fastboot case, we'll flip, but if we don't update the pipesrc and
3277 * pfit state, we'll end up with a big fb scanned out into the wrong
3278 * sized surface.
3279 *
3280 * To fix this properly, we need to hoist the checks up into
3281 * compute_mode_changes (or above), check the actual pfit state and
3282 * whether the platform allows pfit disable with pipe active, and only
3283 * then update the pipesrc and pfit state, even on the flip path.
3284 */
3285
3286 adjusted_mode = &crtc->config->base.adjusted_mode;
3287
3288 I915_WRITE(PIPESRC(crtc->pipe),
3289 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3290 (adjusted_mode->crtc_vdisplay - 1));
3291 if (!crtc->config->pch_pfit.enabled &&
3292 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3293 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3294 I915_WRITE(PF_CTL(crtc->pipe), 0);
3295 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3296 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3297 }
3298 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3299 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3300 }
3301
3302 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3303 {
3304 struct drm_device *dev = crtc->dev;
3305 struct drm_i915_private *dev_priv = dev->dev_private;
3306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3307 int pipe = intel_crtc->pipe;
3308 u32 reg, temp;
3309
3310 /* enable normal train */
3311 reg = FDI_TX_CTL(pipe);
3312 temp = I915_READ(reg);
3313 if (IS_IVYBRIDGE(dev)) {
3314 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3315 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3316 } else {
3317 temp &= ~FDI_LINK_TRAIN_NONE;
3318 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3319 }
3320 I915_WRITE(reg, temp);
3321
3322 reg = FDI_RX_CTL(pipe);
3323 temp = I915_READ(reg);
3324 if (HAS_PCH_CPT(dev)) {
3325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3326 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3327 } else {
3328 temp &= ~FDI_LINK_TRAIN_NONE;
3329 temp |= FDI_LINK_TRAIN_NONE;
3330 }
3331 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3332
3333 /* wait one idle pattern time */
3334 POSTING_READ(reg);
3335 udelay(1000);
3336
3337 /* IVB wants error correction enabled */
3338 if (IS_IVYBRIDGE(dev))
3339 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3340 FDI_FE_ERRC_ENABLE);
3341 }
3342
3343 /* The FDI link training functions for ILK/Ibexpeak. */
3344 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3345 {
3346 struct drm_device *dev = crtc->dev;
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3349 int pipe = intel_crtc->pipe;
3350 u32 reg, temp, tries;
3351
3352 /* FDI needs bits from pipe first */
3353 assert_pipe_enabled(dev_priv, pipe);
3354
3355 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3356 for train result */
3357 reg = FDI_RX_IMR(pipe);
3358 temp = I915_READ(reg);
3359 temp &= ~FDI_RX_SYMBOL_LOCK;
3360 temp &= ~FDI_RX_BIT_LOCK;
3361 I915_WRITE(reg, temp);
3362 I915_READ(reg);
3363 udelay(150);
3364
3365 /* enable CPU FDI TX and PCH FDI RX */
3366 reg = FDI_TX_CTL(pipe);
3367 temp = I915_READ(reg);
3368 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3369 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3370 temp &= ~FDI_LINK_TRAIN_NONE;
3371 temp |= FDI_LINK_TRAIN_PATTERN_1;
3372 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3373
3374 reg = FDI_RX_CTL(pipe);
3375 temp = I915_READ(reg);
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_PATTERN_1;
3378 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3379
3380 POSTING_READ(reg);
3381 udelay(150);
3382
3383 /* Ironlake workaround, enable clock pointer after FDI enable*/
3384 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3385 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3386 FDI_RX_PHASE_SYNC_POINTER_EN);
3387
3388 reg = FDI_RX_IIR(pipe);
3389 for (tries = 0; tries < 5; tries++) {
3390 temp = I915_READ(reg);
3391 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3392
3393 if ((temp & FDI_RX_BIT_LOCK)) {
3394 DRM_DEBUG_KMS("FDI train 1 done.\n");
3395 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3396 break;
3397 }
3398 }
3399 if (tries == 5)
3400 DRM_ERROR("FDI train 1 fail!\n");
3401
3402 /* Train 2 */
3403 reg = FDI_TX_CTL(pipe);
3404 temp = I915_READ(reg);
3405 temp &= ~FDI_LINK_TRAIN_NONE;
3406 temp |= FDI_LINK_TRAIN_PATTERN_2;
3407 I915_WRITE(reg, temp);
3408
3409 reg = FDI_RX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 temp &= ~FDI_LINK_TRAIN_NONE;
3412 temp |= FDI_LINK_TRAIN_PATTERN_2;
3413 I915_WRITE(reg, temp);
3414
3415 POSTING_READ(reg);
3416 udelay(150);
3417
3418 reg = FDI_RX_IIR(pipe);
3419 for (tries = 0; tries < 5; tries++) {
3420 temp = I915_READ(reg);
3421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3422
3423 if (temp & FDI_RX_SYMBOL_LOCK) {
3424 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3425 DRM_DEBUG_KMS("FDI train 2 done.\n");
3426 break;
3427 }
3428 }
3429 if (tries == 5)
3430 DRM_ERROR("FDI train 2 fail!\n");
3431
3432 DRM_DEBUG_KMS("FDI train done\n");
3433
3434 }
3435
3436 static const int snb_b_fdi_train_param[] = {
3437 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3438 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3439 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3440 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3441 };
3442
3443 /* The FDI link training functions for SNB/Cougarpoint. */
3444 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3445 {
3446 struct drm_device *dev = crtc->dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449 int pipe = intel_crtc->pipe;
3450 u32 reg, temp, i, retry;
3451
3452 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453 for train result */
3454 reg = FDI_RX_IMR(pipe);
3455 temp = I915_READ(reg);
3456 temp &= ~FDI_RX_SYMBOL_LOCK;
3457 temp &= ~FDI_RX_BIT_LOCK;
3458 I915_WRITE(reg, temp);
3459
3460 POSTING_READ(reg);
3461 udelay(150);
3462
3463 /* enable CPU FDI TX and PCH FDI RX */
3464 reg = FDI_TX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3467 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3468 temp &= ~FDI_LINK_TRAIN_NONE;
3469 temp |= FDI_LINK_TRAIN_PATTERN_1;
3470 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3471 /* SNB-B */
3472 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3473 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3474
3475 I915_WRITE(FDI_RX_MISC(pipe),
3476 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3477
3478 reg = FDI_RX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 if (HAS_PCH_CPT(dev)) {
3481 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3482 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3483 } else {
3484 temp &= ~FDI_LINK_TRAIN_NONE;
3485 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486 }
3487 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3488
3489 POSTING_READ(reg);
3490 udelay(150);
3491
3492 for (i = 0; i < 4; i++) {
3493 reg = FDI_TX_CTL(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3496 temp |= snb_b_fdi_train_param[i];
3497 I915_WRITE(reg, temp);
3498
3499 POSTING_READ(reg);
3500 udelay(500);
3501
3502 for (retry = 0; retry < 5; retry++) {
3503 reg = FDI_RX_IIR(pipe);
3504 temp = I915_READ(reg);
3505 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3506 if (temp & FDI_RX_BIT_LOCK) {
3507 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3508 DRM_DEBUG_KMS("FDI train 1 done.\n");
3509 break;
3510 }
3511 udelay(50);
3512 }
3513 if (retry < 5)
3514 break;
3515 }
3516 if (i == 4)
3517 DRM_ERROR("FDI train 1 fail!\n");
3518
3519 /* Train 2 */
3520 reg = FDI_TX_CTL(pipe);
3521 temp = I915_READ(reg);
3522 temp &= ~FDI_LINK_TRAIN_NONE;
3523 temp |= FDI_LINK_TRAIN_PATTERN_2;
3524 if (IS_GEN6(dev)) {
3525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526 /* SNB-B */
3527 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3528 }
3529 I915_WRITE(reg, temp);
3530
3531 reg = FDI_RX_CTL(pipe);
3532 temp = I915_READ(reg);
3533 if (HAS_PCH_CPT(dev)) {
3534 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3535 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3536 } else {
3537 temp &= ~FDI_LINK_TRAIN_NONE;
3538 temp |= FDI_LINK_TRAIN_PATTERN_2;
3539 }
3540 I915_WRITE(reg, temp);
3541
3542 POSTING_READ(reg);
3543 udelay(150);
3544
3545 for (i = 0; i < 4; i++) {
3546 reg = FDI_TX_CTL(pipe);
3547 temp = I915_READ(reg);
3548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3549 temp |= snb_b_fdi_train_param[i];
3550 I915_WRITE(reg, temp);
3551
3552 POSTING_READ(reg);
3553 udelay(500);
3554
3555 for (retry = 0; retry < 5; retry++) {
3556 reg = FDI_RX_IIR(pipe);
3557 temp = I915_READ(reg);
3558 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3559 if (temp & FDI_RX_SYMBOL_LOCK) {
3560 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3561 DRM_DEBUG_KMS("FDI train 2 done.\n");
3562 break;
3563 }
3564 udelay(50);
3565 }
3566 if (retry < 5)
3567 break;
3568 }
3569 if (i == 4)
3570 DRM_ERROR("FDI train 2 fail!\n");
3571
3572 DRM_DEBUG_KMS("FDI train done.\n");
3573 }
3574
3575 /* Manual link training for Ivy Bridge A0 parts */
3576 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3577 {
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581 int pipe = intel_crtc->pipe;
3582 u32 reg, temp, i, j;
3583
3584 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3585 for train result */
3586 reg = FDI_RX_IMR(pipe);
3587 temp = I915_READ(reg);
3588 temp &= ~FDI_RX_SYMBOL_LOCK;
3589 temp &= ~FDI_RX_BIT_LOCK;
3590 I915_WRITE(reg, temp);
3591
3592 POSTING_READ(reg);
3593 udelay(150);
3594
3595 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3596 I915_READ(FDI_RX_IIR(pipe)));
3597
3598 /* Try each vswing and preemphasis setting twice before moving on */
3599 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3600 /* disable first in case we need to retry */
3601 reg = FDI_TX_CTL(pipe);
3602 temp = I915_READ(reg);
3603 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3604 temp &= ~FDI_TX_ENABLE;
3605 I915_WRITE(reg, temp);
3606
3607 reg = FDI_RX_CTL(pipe);
3608 temp = I915_READ(reg);
3609 temp &= ~FDI_LINK_TRAIN_AUTO;
3610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3611 temp &= ~FDI_RX_ENABLE;
3612 I915_WRITE(reg, temp);
3613
3614 /* enable CPU FDI TX and PCH FDI RX */
3615 reg = FDI_TX_CTL(pipe);
3616 temp = I915_READ(reg);
3617 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3618 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3619 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3621 temp |= snb_b_fdi_train_param[j/2];
3622 temp |= FDI_COMPOSITE_SYNC;
3623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3624
3625 I915_WRITE(FDI_RX_MISC(pipe),
3626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3627
3628 reg = FDI_RX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3631 temp |= FDI_COMPOSITE_SYNC;
3632 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3633
3634 POSTING_READ(reg);
3635 udelay(1); /* should be 0.5us */
3636
3637 for (i = 0; i < 4; i++) {
3638 reg = FDI_RX_IIR(pipe);
3639 temp = I915_READ(reg);
3640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3641
3642 if (temp & FDI_RX_BIT_LOCK ||
3643 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3644 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3645 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3646 i);
3647 break;
3648 }
3649 udelay(1); /* should be 0.5us */
3650 }
3651 if (i == 4) {
3652 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3653 continue;
3654 }
3655
3656 /* Train 2 */
3657 reg = FDI_TX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3660 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3661 I915_WRITE(reg, temp);
3662
3663 reg = FDI_RX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3666 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3667 I915_WRITE(reg, temp);
3668
3669 POSTING_READ(reg);
3670 udelay(2); /* should be 1.5us */
3671
3672 for (i = 0; i < 4; i++) {
3673 reg = FDI_RX_IIR(pipe);
3674 temp = I915_READ(reg);
3675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3676
3677 if (temp & FDI_RX_SYMBOL_LOCK ||
3678 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3679 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3680 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3681 i);
3682 goto train_done;
3683 }
3684 udelay(2); /* should be 1.5us */
3685 }
3686 if (i == 4)
3687 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3688 }
3689
3690 train_done:
3691 DRM_DEBUG_KMS("FDI train done.\n");
3692 }
3693
3694 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3695 {
3696 struct drm_device *dev = intel_crtc->base.dev;
3697 struct drm_i915_private *dev_priv = dev->dev_private;
3698 int pipe = intel_crtc->pipe;
3699 u32 reg, temp;
3700
3701
3702 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3703 reg = FDI_RX_CTL(pipe);
3704 temp = I915_READ(reg);
3705 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3706 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3707 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3708 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3709
3710 POSTING_READ(reg);
3711 udelay(200);
3712
3713 /* Switch from Rawclk to PCDclk */
3714 temp = I915_READ(reg);
3715 I915_WRITE(reg, temp | FDI_PCDCLK);
3716
3717 POSTING_READ(reg);
3718 udelay(200);
3719
3720 /* Enable CPU FDI TX PLL, always on for Ironlake */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3724 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3725
3726 POSTING_READ(reg);
3727 udelay(100);
3728 }
3729 }
3730
3731 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3732 {
3733 struct drm_device *dev = intel_crtc->base.dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 int pipe = intel_crtc->pipe;
3736 u32 reg, temp;
3737
3738 /* Switch from PCDclk to Rawclk */
3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3742
3743 /* Disable CPU FDI TX PLL */
3744 reg = FDI_TX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3747
3748 POSTING_READ(reg);
3749 udelay(100);
3750
3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3754
3755 /* Wait for the clocks to turn off. */
3756 POSTING_READ(reg);
3757 udelay(100);
3758 }
3759
3760 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3761 {
3762 struct drm_device *dev = crtc->dev;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3765 int pipe = intel_crtc->pipe;
3766 u32 reg, temp;
3767
3768 /* disable CPU FDI tx and PCH FDI rx */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3772 POSTING_READ(reg);
3773
3774 reg = FDI_RX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 temp &= ~(0x7 << 16);
3777 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3778 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3779
3780 POSTING_READ(reg);
3781 udelay(100);
3782
3783 /* Ironlake workaround, disable clock pointer after downing FDI */
3784 if (HAS_PCH_IBX(dev))
3785 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3786
3787 /* still set train pattern 1 */
3788 reg = FDI_TX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 temp &= ~FDI_LINK_TRAIN_NONE;
3791 temp |= FDI_LINK_TRAIN_PATTERN_1;
3792 I915_WRITE(reg, temp);
3793
3794 reg = FDI_RX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 if (HAS_PCH_CPT(dev)) {
3797 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3798 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3799 } else {
3800 temp &= ~FDI_LINK_TRAIN_NONE;
3801 temp |= FDI_LINK_TRAIN_PATTERN_1;
3802 }
3803 /* BPC in FDI rx is consistent with that in PIPECONF */
3804 temp &= ~(0x07 << 16);
3805 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3806 I915_WRITE(reg, temp);
3807
3808 POSTING_READ(reg);
3809 udelay(100);
3810 }
3811
3812 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3813 {
3814 struct intel_crtc *crtc;
3815
3816 /* Note that we don't need to be called with mode_config.lock here
3817 * as our list of CRTC objects is static for the lifetime of the
3818 * device and so cannot disappear as we iterate. Similarly, we can
3819 * happily treat the predicates as racy, atomic checks as userspace
3820 * cannot claim and pin a new fb without at least acquring the
3821 * struct_mutex and so serialising with us.
3822 */
3823 for_each_intel_crtc(dev, crtc) {
3824 if (atomic_read(&crtc->unpin_work_count) == 0)
3825 continue;
3826
3827 if (crtc->unpin_work)
3828 intel_wait_for_vblank(dev, crtc->pipe);
3829
3830 return true;
3831 }
3832
3833 return false;
3834 }
3835
3836 static void page_flip_completed(struct intel_crtc *intel_crtc)
3837 {
3838 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3839 struct intel_unpin_work *work = intel_crtc->unpin_work;
3840
3841 /* ensure that the unpin work is consistent wrt ->pending. */
3842 smp_rmb();
3843 intel_crtc->unpin_work = NULL;
3844
3845 if (work->event)
3846 drm_send_vblank_event(intel_crtc->base.dev,
3847 intel_crtc->pipe,
3848 work->event);
3849
3850 drm_crtc_vblank_put(&intel_crtc->base);
3851
3852 wake_up_all(&dev_priv->pending_flip_queue);
3853 queue_work(dev_priv->wq, &work->work);
3854
3855 trace_i915_flip_complete(intel_crtc->plane,
3856 work->pending_flip_obj);
3857 }
3858
3859 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3860 {
3861 struct drm_device *dev = crtc->dev;
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863
3864 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3865 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3866 !intel_crtc_has_pending_flip(crtc),
3867 60*HZ) == 0)) {
3868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3869
3870 spin_lock_irq(&dev->event_lock);
3871 if (intel_crtc->unpin_work) {
3872 WARN_ONCE(1, "Removing stuck page flip\n");
3873 page_flip_completed(intel_crtc);
3874 }
3875 spin_unlock_irq(&dev->event_lock);
3876 }
3877
3878 if (crtc->primary->fb) {
3879 mutex_lock(&dev->struct_mutex);
3880 intel_finish_fb(crtc->primary->fb);
3881 mutex_unlock(&dev->struct_mutex);
3882 }
3883 }
3884
3885 /* Program iCLKIP clock to the desired frequency */
3886 static void lpt_program_iclkip(struct drm_crtc *crtc)
3887 {
3888 struct drm_device *dev = crtc->dev;
3889 struct drm_i915_private *dev_priv = dev->dev_private;
3890 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3891 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3892 u32 temp;
3893
3894 mutex_lock(&dev_priv->sb_lock);
3895
3896 /* It is necessary to ungate the pixclk gate prior to programming
3897 * the divisors, and gate it back when it is done.
3898 */
3899 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3900
3901 /* Disable SSCCTL */
3902 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3903 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3904 SBI_SSCCTL_DISABLE,
3905 SBI_ICLK);
3906
3907 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3908 if (clock == 20000) {
3909 auxdiv = 1;
3910 divsel = 0x41;
3911 phaseinc = 0x20;
3912 } else {
3913 /* The iCLK virtual clock root frequency is in MHz,
3914 * but the adjusted_mode->crtc_clock in in KHz. To get the
3915 * divisors, it is necessary to divide one by another, so we
3916 * convert the virtual clock precision to KHz here for higher
3917 * precision.
3918 */
3919 u32 iclk_virtual_root_freq = 172800 * 1000;
3920 u32 iclk_pi_range = 64;
3921 u32 desired_divisor, msb_divisor_value, pi_value;
3922
3923 desired_divisor = (iclk_virtual_root_freq / clock);
3924 msb_divisor_value = desired_divisor / iclk_pi_range;
3925 pi_value = desired_divisor % iclk_pi_range;
3926
3927 auxdiv = 0;
3928 divsel = msb_divisor_value - 2;
3929 phaseinc = pi_value;
3930 }
3931
3932 /* This should not happen with any sane values */
3933 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3934 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3935 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3936 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3937
3938 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3939 clock,
3940 auxdiv,
3941 divsel,
3942 phasedir,
3943 phaseinc);
3944
3945 /* Program SSCDIVINTPHASE6 */
3946 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3947 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3948 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3949 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3950 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3951 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3952 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3953 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3954
3955 /* Program SSCAUXDIV */
3956 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3957 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3958 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3959 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3960
3961 /* Enable modulator and associated divider */
3962 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3963 temp &= ~SBI_SSCCTL_DISABLE;
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3965
3966 /* Wait for initialization time */
3967 udelay(24);
3968
3969 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3970
3971 mutex_unlock(&dev_priv->sb_lock);
3972 }
3973
3974 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3975 enum pipe pch_transcoder)
3976 {
3977 struct drm_device *dev = crtc->base.dev;
3978 struct drm_i915_private *dev_priv = dev->dev_private;
3979 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3980
3981 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3982 I915_READ(HTOTAL(cpu_transcoder)));
3983 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3984 I915_READ(HBLANK(cpu_transcoder)));
3985 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3986 I915_READ(HSYNC(cpu_transcoder)));
3987
3988 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3989 I915_READ(VTOTAL(cpu_transcoder)));
3990 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3991 I915_READ(VBLANK(cpu_transcoder)));
3992 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3993 I915_READ(VSYNC(cpu_transcoder)));
3994 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3995 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3996 }
3997
3998 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3999 {
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001 uint32_t temp;
4002
4003 temp = I915_READ(SOUTH_CHICKEN1);
4004 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4005 return;
4006
4007 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4008 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4009
4010 temp &= ~FDI_BC_BIFURCATION_SELECT;
4011 if (enable)
4012 temp |= FDI_BC_BIFURCATION_SELECT;
4013
4014 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4015 I915_WRITE(SOUTH_CHICKEN1, temp);
4016 POSTING_READ(SOUTH_CHICKEN1);
4017 }
4018
4019 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4020 {
4021 struct drm_device *dev = intel_crtc->base.dev;
4022
4023 switch (intel_crtc->pipe) {
4024 case PIPE_A:
4025 break;
4026 case PIPE_B:
4027 if (intel_crtc->config->fdi_lanes > 2)
4028 cpt_set_fdi_bc_bifurcation(dev, false);
4029 else
4030 cpt_set_fdi_bc_bifurcation(dev, true);
4031
4032 break;
4033 case PIPE_C:
4034 cpt_set_fdi_bc_bifurcation(dev, true);
4035
4036 break;
4037 default:
4038 BUG();
4039 }
4040 }
4041
4042 /*
4043 * Enable PCH resources required for PCH ports:
4044 * - PCH PLLs
4045 * - FDI training & RX/TX
4046 * - update transcoder timings
4047 * - DP transcoding bits
4048 * - transcoder
4049 */
4050 static void ironlake_pch_enable(struct drm_crtc *crtc)
4051 {
4052 struct drm_device *dev = crtc->dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4055 int pipe = intel_crtc->pipe;
4056 u32 reg, temp;
4057
4058 assert_pch_transcoder_disabled(dev_priv, pipe);
4059
4060 if (IS_IVYBRIDGE(dev))
4061 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4062
4063 /* Write the TU size bits before fdi link training, so that error
4064 * detection works. */
4065 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4066 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4067
4068 /* For PCH output, training FDI link */
4069 dev_priv->display.fdi_link_train(crtc);
4070
4071 /* We need to program the right clock selection before writing the pixel
4072 * mutliplier into the DPLL. */
4073 if (HAS_PCH_CPT(dev)) {
4074 u32 sel;
4075
4076 temp = I915_READ(PCH_DPLL_SEL);
4077 temp |= TRANS_DPLL_ENABLE(pipe);
4078 sel = TRANS_DPLLB_SEL(pipe);
4079 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4080 temp |= sel;
4081 else
4082 temp &= ~sel;
4083 I915_WRITE(PCH_DPLL_SEL, temp);
4084 }
4085
4086 /* XXX: pch pll's can be enabled any time before we enable the PCH
4087 * transcoder, and we actually should do this to not upset any PCH
4088 * transcoder that already use the clock when we share it.
4089 *
4090 * Note that enable_shared_dpll tries to do the right thing, but
4091 * get_shared_dpll unconditionally resets the pll - we need that to have
4092 * the right LVDS enable sequence. */
4093 intel_enable_shared_dpll(intel_crtc);
4094
4095 /* set transcoder timing, panel must allow it */
4096 assert_panel_unlocked(dev_priv, pipe);
4097 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4098
4099 intel_fdi_normal_train(crtc);
4100
4101 /* For PCH DP, enable TRANS_DP_CTL */
4102 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4103 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4104 reg = TRANS_DP_CTL(pipe);
4105 temp = I915_READ(reg);
4106 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4107 TRANS_DP_SYNC_MASK |
4108 TRANS_DP_BPC_MASK);
4109 temp |= TRANS_DP_OUTPUT_ENABLE;
4110 temp |= bpc << 9; /* same format but at 11:9 */
4111
4112 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4113 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4114 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4115 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4116
4117 switch (intel_trans_dp_port_sel(crtc)) {
4118 case PCH_DP_B:
4119 temp |= TRANS_DP_PORT_SEL_B;
4120 break;
4121 case PCH_DP_C:
4122 temp |= TRANS_DP_PORT_SEL_C;
4123 break;
4124 case PCH_DP_D:
4125 temp |= TRANS_DP_PORT_SEL_D;
4126 break;
4127 default:
4128 BUG();
4129 }
4130
4131 I915_WRITE(reg, temp);
4132 }
4133
4134 ironlake_enable_pch_transcoder(dev_priv, pipe);
4135 }
4136
4137 static void lpt_pch_enable(struct drm_crtc *crtc)
4138 {
4139 struct drm_device *dev = crtc->dev;
4140 struct drm_i915_private *dev_priv = dev->dev_private;
4141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4142 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4143
4144 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4145
4146 lpt_program_iclkip(crtc);
4147
4148 /* Set transcoder timing. */
4149 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4150
4151 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4152 }
4153
4154 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4155 struct intel_crtc_state *crtc_state)
4156 {
4157 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4158 struct intel_shared_dpll *pll;
4159 struct intel_shared_dpll_config *shared_dpll;
4160 enum intel_dpll_id i;
4161
4162 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4163
4164 if (HAS_PCH_IBX(dev_priv->dev)) {
4165 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4166 i = (enum intel_dpll_id) crtc->pipe;
4167 pll = &dev_priv->shared_dplls[i];
4168
4169 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4170 crtc->base.base.id, pll->name);
4171
4172 WARN_ON(shared_dpll[i].crtc_mask);
4173
4174 goto found;
4175 }
4176
4177 if (IS_BROXTON(dev_priv->dev)) {
4178 /* PLL is attached to port in bxt */
4179 struct intel_encoder *encoder;
4180 struct intel_digital_port *intel_dig_port;
4181
4182 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4183 if (WARN_ON(!encoder))
4184 return NULL;
4185
4186 intel_dig_port = enc_to_dig_port(&encoder->base);
4187 /* 1:1 mapping between ports and PLLs */
4188 i = (enum intel_dpll_id)intel_dig_port->port;
4189 pll = &dev_priv->shared_dplls[i];
4190 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4191 crtc->base.base.id, pll->name);
4192 WARN_ON(shared_dpll[i].crtc_mask);
4193
4194 goto found;
4195 }
4196
4197 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4198 pll = &dev_priv->shared_dplls[i];
4199
4200 /* Only want to check enabled timings first */
4201 if (shared_dpll[i].crtc_mask == 0)
4202 continue;
4203
4204 if (memcmp(&crtc_state->dpll_hw_state,
4205 &shared_dpll[i].hw_state,
4206 sizeof(crtc_state->dpll_hw_state)) == 0) {
4207 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4208 crtc->base.base.id, pll->name,
4209 shared_dpll[i].crtc_mask,
4210 pll->active);
4211 goto found;
4212 }
4213 }
4214
4215 /* Ok no matching timings, maybe there's a free one? */
4216 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4217 pll = &dev_priv->shared_dplls[i];
4218 if (shared_dpll[i].crtc_mask == 0) {
4219 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4220 crtc->base.base.id, pll->name);
4221 goto found;
4222 }
4223 }
4224
4225 return NULL;
4226
4227 found:
4228 if (shared_dpll[i].crtc_mask == 0)
4229 shared_dpll[i].hw_state =
4230 crtc_state->dpll_hw_state;
4231
4232 crtc_state->shared_dpll = i;
4233 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4234 pipe_name(crtc->pipe));
4235
4236 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4237
4238 return pll;
4239 }
4240
4241 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4242 {
4243 struct drm_i915_private *dev_priv = to_i915(state->dev);
4244 struct intel_shared_dpll_config *shared_dpll;
4245 struct intel_shared_dpll *pll;
4246 enum intel_dpll_id i;
4247
4248 if (!to_intel_atomic_state(state)->dpll_set)
4249 return;
4250
4251 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4252 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4253 pll = &dev_priv->shared_dplls[i];
4254 pll->config = shared_dpll[i];
4255 }
4256 }
4257
4258 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4259 {
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 int dslreg = PIPEDSL(pipe);
4262 u32 temp;
4263
4264 temp = I915_READ(dslreg);
4265 udelay(500);
4266 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4267 if (wait_for(I915_READ(dslreg) != temp, 5))
4268 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4269 }
4270 }
4271
4272 static int
4273 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4274 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4275 int src_w, int src_h, int dst_w, int dst_h)
4276 {
4277 struct intel_crtc_scaler_state *scaler_state =
4278 &crtc_state->scaler_state;
4279 struct intel_crtc *intel_crtc =
4280 to_intel_crtc(crtc_state->base.crtc);
4281 int need_scaling;
4282
4283 need_scaling = intel_rotation_90_or_270(rotation) ?
4284 (src_h != dst_w || src_w != dst_h):
4285 (src_w != dst_w || src_h != dst_h);
4286
4287 /*
4288 * if plane is being disabled or scaler is no more required or force detach
4289 * - free scaler binded to this plane/crtc
4290 * - in order to do this, update crtc->scaler_usage
4291 *
4292 * Here scaler state in crtc_state is set free so that
4293 * scaler can be assigned to other user. Actual register
4294 * update to free the scaler is done in plane/panel-fit programming.
4295 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4296 */
4297 if (force_detach || !need_scaling) {
4298 if (*scaler_id >= 0) {
4299 scaler_state->scaler_users &= ~(1 << scaler_user);
4300 scaler_state->scalers[*scaler_id].in_use = 0;
4301
4302 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4303 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4304 intel_crtc->pipe, scaler_user, *scaler_id,
4305 scaler_state->scaler_users);
4306 *scaler_id = -1;
4307 }
4308 return 0;
4309 }
4310
4311 /* range checks */
4312 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4313 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4314
4315 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4316 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4317 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4318 "size is out of scaler range\n",
4319 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4320 return -EINVAL;
4321 }
4322
4323 /* mark this plane as a scaler user in crtc_state */
4324 scaler_state->scaler_users |= (1 << scaler_user);
4325 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4326 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4327 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4328 scaler_state->scaler_users);
4329
4330 return 0;
4331 }
4332
4333 /**
4334 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4335 *
4336 * @state: crtc's scaler state
4337 * @force_detach: whether to forcibly disable scaler
4338 *
4339 * Return
4340 * 0 - scaler_usage updated successfully
4341 * error - requested scaling cannot be supported or other error condition
4342 */
4343 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4344 {
4345 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4346 struct drm_display_mode *adjusted_mode =
4347 &state->base.adjusted_mode;
4348
4349 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4350 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4351
4352 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4353 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4354 state->pipe_src_w, state->pipe_src_h,
4355 adjusted_mode->hdisplay, adjusted_mode->hdisplay);
4356 }
4357
4358 /**
4359 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4360 *
4361 * @state: crtc's scaler state
4362 * @plane_state: atomic plane state to update
4363 *
4364 * Return
4365 * 0 - scaler_usage updated successfully
4366 * error - requested scaling cannot be supported or other error condition
4367 */
4368 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4369 struct intel_plane_state *plane_state)
4370 {
4371
4372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4373 struct intel_plane *intel_plane =
4374 to_intel_plane(plane_state->base.plane);
4375 struct drm_framebuffer *fb = plane_state->base.fb;
4376 int ret;
4377
4378 bool force_detach = !fb || !plane_state->visible;
4379
4380 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4381 intel_plane->base.base.id, intel_crtc->pipe,
4382 drm_plane_index(&intel_plane->base));
4383
4384 ret = skl_update_scaler(crtc_state, force_detach,
4385 drm_plane_index(&intel_plane->base),
4386 &plane_state->scaler_id,
4387 plane_state->base.rotation,
4388 drm_rect_width(&plane_state->src) >> 16,
4389 drm_rect_height(&plane_state->src) >> 16,
4390 drm_rect_width(&plane_state->dst),
4391 drm_rect_height(&plane_state->dst));
4392
4393 if (ret || plane_state->scaler_id < 0)
4394 return ret;
4395
4396 /* check colorkey */
4397 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4398 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4399 intel_plane->base.base.id);
4400 return -EINVAL;
4401 }
4402
4403 /* Check src format */
4404 switch (fb->pixel_format) {
4405 case DRM_FORMAT_RGB565:
4406 case DRM_FORMAT_XBGR8888:
4407 case DRM_FORMAT_XRGB8888:
4408 case DRM_FORMAT_ABGR8888:
4409 case DRM_FORMAT_ARGB8888:
4410 case DRM_FORMAT_XRGB2101010:
4411 case DRM_FORMAT_XBGR2101010:
4412 case DRM_FORMAT_YUYV:
4413 case DRM_FORMAT_YVYU:
4414 case DRM_FORMAT_UYVY:
4415 case DRM_FORMAT_VYUY:
4416 break;
4417 default:
4418 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4419 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4420 return -EINVAL;
4421 }
4422
4423 return 0;
4424 }
4425
4426 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4427 {
4428 struct drm_device *dev = crtc->base.dev;
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430 int pipe = crtc->pipe;
4431 struct intel_crtc_scaler_state *scaler_state =
4432 &crtc->config->scaler_state;
4433
4434 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4435
4436 /* To update pfit, first update scaler state */
4437 skl_update_scaler_crtc(crtc->config, !enable);
4438 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4439 skl_detach_scalers(crtc);
4440 if (!enable)
4441 return;
4442
4443 if (crtc->config->pch_pfit.enabled) {
4444 int id;
4445
4446 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4447 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4448 return;
4449 }
4450
4451 id = scaler_state->scaler_id;
4452 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4453 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4454 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4455 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4456
4457 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4458 }
4459 }
4460
4461 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4462 {
4463 struct drm_device *dev = crtc->base.dev;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
4465 int pipe = crtc->pipe;
4466
4467 if (crtc->config->pch_pfit.enabled) {
4468 /* Force use of hard-coded filter coefficients
4469 * as some pre-programmed values are broken,
4470 * e.g. x201.
4471 */
4472 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4473 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4474 PF_PIPE_SEL_IVB(pipe));
4475 else
4476 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4477 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4478 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4479 }
4480 }
4481
4482 void hsw_enable_ips(struct intel_crtc *crtc)
4483 {
4484 struct drm_device *dev = crtc->base.dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486
4487 if (!crtc->config->ips_enabled)
4488 return;
4489
4490 /* We can only enable IPS after we enable a plane and wait for a vblank */
4491 intel_wait_for_vblank(dev, crtc->pipe);
4492
4493 assert_plane_enabled(dev_priv, crtc->plane);
4494 if (IS_BROADWELL(dev)) {
4495 mutex_lock(&dev_priv->rps.hw_lock);
4496 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4497 mutex_unlock(&dev_priv->rps.hw_lock);
4498 /* Quoting Art Runyan: "its not safe to expect any particular
4499 * value in IPS_CTL bit 31 after enabling IPS through the
4500 * mailbox." Moreover, the mailbox may return a bogus state,
4501 * so we need to just enable it and continue on.
4502 */
4503 } else {
4504 I915_WRITE(IPS_CTL, IPS_ENABLE);
4505 /* The bit only becomes 1 in the next vblank, so this wait here
4506 * is essentially intel_wait_for_vblank. If we don't have this
4507 * and don't wait for vblanks until the end of crtc_enable, then
4508 * the HW state readout code will complain that the expected
4509 * IPS_CTL value is not the one we read. */
4510 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4511 DRM_ERROR("Timed out waiting for IPS enable\n");
4512 }
4513 }
4514
4515 void hsw_disable_ips(struct intel_crtc *crtc)
4516 {
4517 struct drm_device *dev = crtc->base.dev;
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519
4520 if (!crtc->config->ips_enabled)
4521 return;
4522
4523 assert_plane_enabled(dev_priv, crtc->plane);
4524 if (IS_BROADWELL(dev)) {
4525 mutex_lock(&dev_priv->rps.hw_lock);
4526 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4527 mutex_unlock(&dev_priv->rps.hw_lock);
4528 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4529 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4530 DRM_ERROR("Timed out waiting for IPS disable\n");
4531 } else {
4532 I915_WRITE(IPS_CTL, 0);
4533 POSTING_READ(IPS_CTL);
4534 }
4535
4536 /* We need to wait for a vblank before we can disable the plane. */
4537 intel_wait_for_vblank(dev, crtc->pipe);
4538 }
4539
4540 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4541 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4542 {
4543 struct drm_device *dev = crtc->dev;
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4546 enum pipe pipe = intel_crtc->pipe;
4547 int palreg = PALETTE(pipe);
4548 int i;
4549 bool reenable_ips = false;
4550
4551 /* The clocks have to be on to load the palette. */
4552 if (!crtc->state->active)
4553 return;
4554
4555 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4556 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4557 assert_dsi_pll_enabled(dev_priv);
4558 else
4559 assert_pll_enabled(dev_priv, pipe);
4560 }
4561
4562 /* use legacy palette for Ironlake */
4563 if (!HAS_GMCH_DISPLAY(dev))
4564 palreg = LGC_PALETTE(pipe);
4565
4566 /* Workaround : Do not read or write the pipe palette/gamma data while
4567 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4568 */
4569 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4570 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4571 GAMMA_MODE_MODE_SPLIT)) {
4572 hsw_disable_ips(intel_crtc);
4573 reenable_ips = true;
4574 }
4575
4576 for (i = 0; i < 256; i++) {
4577 I915_WRITE(palreg + 4 * i,
4578 (intel_crtc->lut_r[i] << 16) |
4579 (intel_crtc->lut_g[i] << 8) |
4580 intel_crtc->lut_b[i]);
4581 }
4582
4583 if (reenable_ips)
4584 hsw_enable_ips(intel_crtc);
4585 }
4586
4587 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4588 {
4589 if (intel_crtc->overlay) {
4590 struct drm_device *dev = intel_crtc->base.dev;
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592
4593 mutex_lock(&dev->struct_mutex);
4594 dev_priv->mm.interruptible = false;
4595 (void) intel_overlay_switch_off(intel_crtc->overlay);
4596 dev_priv->mm.interruptible = true;
4597 mutex_unlock(&dev->struct_mutex);
4598 }
4599
4600 /* Let userspace switch the overlay on again. In most cases userspace
4601 * has to recompute where to put it anyway.
4602 */
4603 }
4604
4605 /**
4606 * intel_post_enable_primary - Perform operations after enabling primary plane
4607 * @crtc: the CRTC whose primary plane was just enabled
4608 *
4609 * Performs potentially sleeping operations that must be done after the primary
4610 * plane is enabled, such as updating FBC and IPS. Note that this may be
4611 * called due to an explicit primary plane update, or due to an implicit
4612 * re-enable that is caused when a sprite plane is updated to no longer
4613 * completely hide the primary plane.
4614 */
4615 static void
4616 intel_post_enable_primary(struct drm_crtc *crtc)
4617 {
4618 struct drm_device *dev = crtc->dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4621 int pipe = intel_crtc->pipe;
4622
4623 /*
4624 * BDW signals flip done immediately if the plane
4625 * is disabled, even if the plane enable is already
4626 * armed to occur at the next vblank :(
4627 */
4628 if (IS_BROADWELL(dev))
4629 intel_wait_for_vblank(dev, pipe);
4630
4631 /*
4632 * FIXME IPS should be fine as long as one plane is
4633 * enabled, but in practice it seems to have problems
4634 * when going from primary only to sprite only and vice
4635 * versa.
4636 */
4637 hsw_enable_ips(intel_crtc);
4638
4639 /*
4640 * Gen2 reports pipe underruns whenever all planes are disabled.
4641 * So don't enable underrun reporting before at least some planes
4642 * are enabled.
4643 * FIXME: Need to fix the logic to work when we turn off all planes
4644 * but leave the pipe running.
4645 */
4646 if (IS_GEN2(dev))
4647 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4648
4649 /* Underruns don't raise interrupts, so check manually. */
4650 if (HAS_GMCH_DISPLAY(dev))
4651 i9xx_check_fifo_underruns(dev_priv);
4652 }
4653
4654 /**
4655 * intel_pre_disable_primary - Perform operations before disabling primary plane
4656 * @crtc: the CRTC whose primary plane is to be disabled
4657 *
4658 * Performs potentially sleeping operations that must be done before the
4659 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4660 * be called due to an explicit primary plane update, or due to an implicit
4661 * disable that is caused when a sprite plane completely hides the primary
4662 * plane.
4663 */
4664 static void
4665 intel_pre_disable_primary(struct drm_crtc *crtc)
4666 {
4667 struct drm_device *dev = crtc->dev;
4668 struct drm_i915_private *dev_priv = dev->dev_private;
4669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4670 int pipe = intel_crtc->pipe;
4671
4672 /*
4673 * Gen2 reports pipe underruns whenever all planes are disabled.
4674 * So diasble underrun reporting before all the planes get disabled.
4675 * FIXME: Need to fix the logic to work when we turn off all planes
4676 * but leave the pipe running.
4677 */
4678 if (IS_GEN2(dev))
4679 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4680
4681 /*
4682 * Vblank time updates from the shadow to live plane control register
4683 * are blocked if the memory self-refresh mode is active at that
4684 * moment. So to make sure the plane gets truly disabled, disable
4685 * first the self-refresh mode. The self-refresh enable bit in turn
4686 * will be checked/applied by the HW only at the next frame start
4687 * event which is after the vblank start event, so we need to have a
4688 * wait-for-vblank between disabling the plane and the pipe.
4689 */
4690 if (HAS_GMCH_DISPLAY(dev))
4691 intel_set_memory_cxsr(dev_priv, false);
4692
4693 /*
4694 * FIXME IPS should be fine as long as one plane is
4695 * enabled, but in practice it seems to have problems
4696 * when going from primary only to sprite only and vice
4697 * versa.
4698 */
4699 hsw_disable_ips(intel_crtc);
4700 }
4701
4702 static void intel_post_plane_update(struct intel_crtc *crtc)
4703 {
4704 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4705 struct drm_device *dev = crtc->base.dev;
4706 struct drm_plane *plane;
4707
4708 if (atomic->wait_vblank)
4709 intel_wait_for_vblank(dev, crtc->pipe);
4710
4711 intel_frontbuffer_flip(dev, atomic->fb_bits);
4712
4713 if (atomic->update_fbc) {
4714 mutex_lock(&dev->struct_mutex);
4715 intel_fbc_update(dev);
4716 mutex_unlock(&dev->struct_mutex);
4717 }
4718
4719 if (atomic->post_enable_primary)
4720 intel_post_enable_primary(&crtc->base);
4721
4722 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4723 intel_update_sprite_watermarks(plane, &crtc->base,
4724 0, 0, 0, false, false);
4725
4726 memset(atomic, 0, sizeof(*atomic));
4727 }
4728
4729 static void intel_pre_plane_update(struct intel_crtc *crtc)
4730 {
4731 struct drm_device *dev = crtc->base.dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4734 struct drm_plane *p;
4735
4736 /* Track fb's for any planes being disabled */
4737
4738 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4739 struct intel_plane *plane = to_intel_plane(p);
4740 unsigned fb_bits = 0;
4741
4742 switch (p->type) {
4743 case DRM_PLANE_TYPE_PRIMARY:
4744 fb_bits = INTEL_FRONTBUFFER_PRIMARY(plane->pipe);
4745 break;
4746 case DRM_PLANE_TYPE_CURSOR:
4747 fb_bits = INTEL_FRONTBUFFER_CURSOR(plane->pipe);
4748 break;
4749 case DRM_PLANE_TYPE_OVERLAY:
4750 fb_bits = INTEL_FRONTBUFFER_SPRITE(plane->pipe);
4751 break;
4752 }
4753
4754 mutex_lock(&dev->struct_mutex);
4755 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, fb_bits);
4756 mutex_unlock(&dev->struct_mutex);
4757 }
4758
4759 if (atomic->wait_for_flips)
4760 intel_crtc_wait_for_pending_flips(&crtc->base);
4761
4762 if (atomic->disable_fbc &&
4763 dev_priv->fbc.crtc == crtc) {
4764 mutex_lock(&dev->struct_mutex);
4765 if (dev_priv->fbc.crtc == crtc)
4766 intel_fbc_disable(dev);
4767 mutex_unlock(&dev->struct_mutex);
4768 }
4769
4770 if (atomic->pre_disable_primary)
4771 intel_pre_disable_primary(&crtc->base);
4772 }
4773
4774 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4775 {
4776 struct drm_device *dev = crtc->dev;
4777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778 struct drm_plane *p;
4779 int pipe = intel_crtc->pipe;
4780
4781 intel_crtc_dpms_overlay_disable(intel_crtc);
4782
4783 drm_for_each_plane_mask(p, dev, plane_mask)
4784 to_intel_plane(p)->disable_plane(p, crtc);
4785
4786 /*
4787 * FIXME: Once we grow proper nuclear flip support out of this we need
4788 * to compute the mask of flip planes precisely. For the time being
4789 * consider this a flip to a NULL plane.
4790 */
4791 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4792 }
4793
4794 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4795 {
4796 struct drm_device *dev = crtc->dev;
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4799 struct intel_encoder *encoder;
4800 int pipe = intel_crtc->pipe;
4801
4802 if (WARN_ON(intel_crtc->active))
4803 return;
4804
4805 if (intel_crtc->config->has_pch_encoder)
4806 intel_prepare_shared_dpll(intel_crtc);
4807
4808 if (intel_crtc->config->has_dp_encoder)
4809 intel_dp_set_m_n(intel_crtc, M1_N1);
4810
4811 intel_set_pipe_timings(intel_crtc);
4812
4813 if (intel_crtc->config->has_pch_encoder) {
4814 intel_cpu_transcoder_set_m_n(intel_crtc,
4815 &intel_crtc->config->fdi_m_n, NULL);
4816 }
4817
4818 ironlake_set_pipeconf(crtc);
4819
4820 intel_crtc->active = true;
4821
4822 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4823 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4824
4825 for_each_encoder_on_crtc(dev, crtc, encoder)
4826 if (encoder->pre_enable)
4827 encoder->pre_enable(encoder);
4828
4829 if (intel_crtc->config->has_pch_encoder) {
4830 /* Note: FDI PLL enabling _must_ be done before we enable the
4831 * cpu pipes, hence this is separate from all the other fdi/pch
4832 * enabling. */
4833 ironlake_fdi_pll_enable(intel_crtc);
4834 } else {
4835 assert_fdi_tx_disabled(dev_priv, pipe);
4836 assert_fdi_rx_disabled(dev_priv, pipe);
4837 }
4838
4839 ironlake_pfit_enable(intel_crtc);
4840
4841 /*
4842 * On ILK+ LUT must be loaded before the pipe is running but with
4843 * clocks enabled
4844 */
4845 intel_crtc_load_lut(crtc);
4846
4847 intel_update_watermarks(crtc);
4848 intel_enable_pipe(intel_crtc);
4849
4850 if (intel_crtc->config->has_pch_encoder)
4851 ironlake_pch_enable(crtc);
4852
4853 assert_vblank_disabled(crtc);
4854 drm_crtc_vblank_on(crtc);
4855
4856 for_each_encoder_on_crtc(dev, crtc, encoder)
4857 encoder->enable(encoder);
4858
4859 if (HAS_PCH_CPT(dev))
4860 cpt_verify_modeset(dev, intel_crtc->pipe);
4861 }
4862
4863 /* IPS only exists on ULT machines and is tied to pipe A. */
4864 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4865 {
4866 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4867 }
4868
4869 static void haswell_crtc_enable(struct drm_crtc *crtc)
4870 {
4871 struct drm_device *dev = crtc->dev;
4872 struct drm_i915_private *dev_priv = dev->dev_private;
4873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4874 struct intel_encoder *encoder;
4875 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4876 struct intel_crtc_state *pipe_config =
4877 to_intel_crtc_state(crtc->state);
4878
4879 if (WARN_ON(intel_crtc->active))
4880 return;
4881
4882 if (intel_crtc_to_shared_dpll(intel_crtc))
4883 intel_enable_shared_dpll(intel_crtc);
4884
4885 if (intel_crtc->config->has_dp_encoder)
4886 intel_dp_set_m_n(intel_crtc, M1_N1);
4887
4888 intel_set_pipe_timings(intel_crtc);
4889
4890 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4891 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4892 intel_crtc->config->pixel_multiplier - 1);
4893 }
4894
4895 if (intel_crtc->config->has_pch_encoder) {
4896 intel_cpu_transcoder_set_m_n(intel_crtc,
4897 &intel_crtc->config->fdi_m_n, NULL);
4898 }
4899
4900 haswell_set_pipeconf(crtc);
4901
4902 intel_set_pipe_csc(crtc);
4903
4904 intel_crtc->active = true;
4905
4906 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4907 for_each_encoder_on_crtc(dev, crtc, encoder)
4908 if (encoder->pre_enable)
4909 encoder->pre_enable(encoder);
4910
4911 if (intel_crtc->config->has_pch_encoder) {
4912 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4913 true);
4914 dev_priv->display.fdi_link_train(crtc);
4915 }
4916
4917 intel_ddi_enable_pipe_clock(intel_crtc);
4918
4919 if (INTEL_INFO(dev)->gen == 9)
4920 skylake_pfit_update(intel_crtc, 1);
4921 else if (INTEL_INFO(dev)->gen < 9)
4922 ironlake_pfit_enable(intel_crtc);
4923 else
4924 MISSING_CASE(INTEL_INFO(dev)->gen);
4925
4926 /*
4927 * On ILK+ LUT must be loaded before the pipe is running but with
4928 * clocks enabled
4929 */
4930 intel_crtc_load_lut(crtc);
4931
4932 intel_ddi_set_pipe_settings(crtc);
4933 intel_ddi_enable_transcoder_func(crtc);
4934
4935 intel_update_watermarks(crtc);
4936 intel_enable_pipe(intel_crtc);
4937
4938 if (intel_crtc->config->has_pch_encoder)
4939 lpt_pch_enable(crtc);
4940
4941 if (intel_crtc->config->dp_encoder_is_mst)
4942 intel_ddi_set_vc_payload_alloc(crtc, true);
4943
4944 assert_vblank_disabled(crtc);
4945 drm_crtc_vblank_on(crtc);
4946
4947 for_each_encoder_on_crtc(dev, crtc, encoder) {
4948 encoder->enable(encoder);
4949 intel_opregion_notify_encoder(encoder, true);
4950 }
4951
4952 /* If we change the relative order between pipe/planes enabling, we need
4953 * to change the workaround. */
4954 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4955 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4956 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4957 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4958 }
4959 }
4960
4961 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4962 {
4963 struct drm_device *dev = crtc->base.dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 int pipe = crtc->pipe;
4966
4967 /* To avoid upsetting the power well on haswell only disable the pfit if
4968 * it's in use. The hw state code will make sure we get this right. */
4969 if (crtc->config->pch_pfit.enabled) {
4970 I915_WRITE(PF_CTL(pipe), 0);
4971 I915_WRITE(PF_WIN_POS(pipe), 0);
4972 I915_WRITE(PF_WIN_SZ(pipe), 0);
4973 }
4974 }
4975
4976 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4977 {
4978 struct drm_device *dev = crtc->dev;
4979 struct drm_i915_private *dev_priv = dev->dev_private;
4980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4981 struct intel_encoder *encoder;
4982 int pipe = intel_crtc->pipe;
4983 u32 reg, temp;
4984
4985 for_each_encoder_on_crtc(dev, crtc, encoder)
4986 encoder->disable(encoder);
4987
4988 drm_crtc_vblank_off(crtc);
4989 assert_vblank_disabled(crtc);
4990
4991 if (intel_crtc->config->has_pch_encoder)
4992 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4993
4994 intel_disable_pipe(intel_crtc);
4995
4996 ironlake_pfit_disable(intel_crtc);
4997
4998 if (intel_crtc->config->has_pch_encoder)
4999 ironlake_fdi_disable(crtc);
5000
5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 if (encoder->post_disable)
5003 encoder->post_disable(encoder);
5004
5005 if (intel_crtc->config->has_pch_encoder) {
5006 ironlake_disable_pch_transcoder(dev_priv, pipe);
5007
5008 if (HAS_PCH_CPT(dev)) {
5009 /* disable TRANS_DP_CTL */
5010 reg = TRANS_DP_CTL(pipe);
5011 temp = I915_READ(reg);
5012 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5013 TRANS_DP_PORT_SEL_MASK);
5014 temp |= TRANS_DP_PORT_SEL_NONE;
5015 I915_WRITE(reg, temp);
5016
5017 /* disable DPLL_SEL */
5018 temp = I915_READ(PCH_DPLL_SEL);
5019 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5020 I915_WRITE(PCH_DPLL_SEL, temp);
5021 }
5022
5023 ironlake_fdi_pll_disable(intel_crtc);
5024 }
5025 }
5026
5027 static void haswell_crtc_disable(struct drm_crtc *crtc)
5028 {
5029 struct drm_device *dev = crtc->dev;
5030 struct drm_i915_private *dev_priv = dev->dev_private;
5031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5032 struct intel_encoder *encoder;
5033 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5034
5035 for_each_encoder_on_crtc(dev, crtc, encoder) {
5036 intel_opregion_notify_encoder(encoder, false);
5037 encoder->disable(encoder);
5038 }
5039
5040 drm_crtc_vblank_off(crtc);
5041 assert_vblank_disabled(crtc);
5042
5043 if (intel_crtc->config->has_pch_encoder)
5044 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5045 false);
5046 intel_disable_pipe(intel_crtc);
5047
5048 if (intel_crtc->config->dp_encoder_is_mst)
5049 intel_ddi_set_vc_payload_alloc(crtc, false);
5050
5051 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5052
5053 if (INTEL_INFO(dev)->gen == 9)
5054 skylake_pfit_update(intel_crtc, 0);
5055 else if (INTEL_INFO(dev)->gen < 9)
5056 ironlake_pfit_disable(intel_crtc);
5057 else
5058 MISSING_CASE(INTEL_INFO(dev)->gen);
5059
5060 intel_ddi_disable_pipe_clock(intel_crtc);
5061
5062 if (intel_crtc->config->has_pch_encoder) {
5063 lpt_disable_pch_transcoder(dev_priv);
5064 intel_ddi_fdi_disable(crtc);
5065 }
5066
5067 for_each_encoder_on_crtc(dev, crtc, encoder)
5068 if (encoder->post_disable)
5069 encoder->post_disable(encoder);
5070 }
5071
5072 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5073 {
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 struct intel_crtc_state *pipe_config = crtc->config;
5077
5078 if (!pipe_config->gmch_pfit.control)
5079 return;
5080
5081 /*
5082 * The panel fitter should only be adjusted whilst the pipe is disabled,
5083 * according to register description and PRM.
5084 */
5085 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5086 assert_pipe_disabled(dev_priv, crtc->pipe);
5087
5088 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5089 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5090
5091 /* Border color in case we don't scale up to the full screen. Black by
5092 * default, change to something else for debugging. */
5093 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5094 }
5095
5096 static enum intel_display_power_domain port_to_power_domain(enum port port)
5097 {
5098 switch (port) {
5099 case PORT_A:
5100 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5101 case PORT_B:
5102 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5103 case PORT_C:
5104 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5105 case PORT_D:
5106 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5107 default:
5108 WARN_ON_ONCE(1);
5109 return POWER_DOMAIN_PORT_OTHER;
5110 }
5111 }
5112
5113 #define for_each_power_domain(domain, mask) \
5114 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5115 if ((1 << (domain)) & (mask))
5116
5117 enum intel_display_power_domain
5118 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5119 {
5120 struct drm_device *dev = intel_encoder->base.dev;
5121 struct intel_digital_port *intel_dig_port;
5122
5123 switch (intel_encoder->type) {
5124 case INTEL_OUTPUT_UNKNOWN:
5125 /* Only DDI platforms should ever use this output type */
5126 WARN_ON_ONCE(!HAS_DDI(dev));
5127 case INTEL_OUTPUT_DISPLAYPORT:
5128 case INTEL_OUTPUT_HDMI:
5129 case INTEL_OUTPUT_EDP:
5130 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5131 return port_to_power_domain(intel_dig_port->port);
5132 case INTEL_OUTPUT_DP_MST:
5133 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5134 return port_to_power_domain(intel_dig_port->port);
5135 case INTEL_OUTPUT_ANALOG:
5136 return POWER_DOMAIN_PORT_CRT;
5137 case INTEL_OUTPUT_DSI:
5138 return POWER_DOMAIN_PORT_DSI;
5139 default:
5140 return POWER_DOMAIN_PORT_OTHER;
5141 }
5142 }
5143
5144 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5145 {
5146 struct drm_device *dev = crtc->dev;
5147 struct intel_encoder *intel_encoder;
5148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5149 enum pipe pipe = intel_crtc->pipe;
5150 unsigned long mask;
5151 enum transcoder transcoder;
5152
5153 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5154
5155 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5156 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5157 if (intel_crtc->config->pch_pfit.enabled ||
5158 intel_crtc->config->pch_pfit.force_thru)
5159 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5160
5161 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5162 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5163
5164 return mask;
5165 }
5166
5167 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5168 {
5169 struct drm_device *dev = state->dev;
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5172 struct intel_crtc *crtc;
5173
5174 /*
5175 * First get all needed power domains, then put all unneeded, to avoid
5176 * any unnecessary toggling of the power wells.
5177 */
5178 for_each_intel_crtc(dev, crtc) {
5179 enum intel_display_power_domain domain;
5180
5181 if (!crtc->base.state->enable)
5182 continue;
5183
5184 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5185
5186 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5187 intel_display_power_get(dev_priv, domain);
5188 }
5189
5190 if (dev_priv->display.modeset_commit_cdclk) {
5191 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5192
5193 if (cdclk != dev_priv->cdclk_freq &&
5194 !WARN_ON(!state->allow_modeset))
5195 dev_priv->display.modeset_commit_cdclk(state);
5196 }
5197
5198 for_each_intel_crtc(dev, crtc) {
5199 enum intel_display_power_domain domain;
5200
5201 for_each_power_domain(domain, crtc->enabled_power_domains)
5202 intel_display_power_put(dev_priv, domain);
5203
5204 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5205 }
5206
5207 intel_display_set_init_power(dev_priv, false);
5208 }
5209
5210 static void intel_update_max_cdclk(struct drm_device *dev)
5211 {
5212 struct drm_i915_private *dev_priv = dev->dev_private;
5213
5214 if (IS_SKYLAKE(dev)) {
5215 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5216
5217 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5218 dev_priv->max_cdclk_freq = 675000;
5219 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5220 dev_priv->max_cdclk_freq = 540000;
5221 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5222 dev_priv->max_cdclk_freq = 450000;
5223 else
5224 dev_priv->max_cdclk_freq = 337500;
5225 } else if (IS_BROADWELL(dev)) {
5226 /*
5227 * FIXME with extra cooling we can allow
5228 * 540 MHz for ULX and 675 Mhz for ULT.
5229 * How can we know if extra cooling is
5230 * available? PCI ID, VTB, something else?
5231 */
5232 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5233 dev_priv->max_cdclk_freq = 450000;
5234 else if (IS_BDW_ULX(dev))
5235 dev_priv->max_cdclk_freq = 450000;
5236 else if (IS_BDW_ULT(dev))
5237 dev_priv->max_cdclk_freq = 540000;
5238 else
5239 dev_priv->max_cdclk_freq = 675000;
5240 } else if (IS_CHERRYVIEW(dev)) {
5241 dev_priv->max_cdclk_freq = 320000;
5242 } else if (IS_VALLEYVIEW(dev)) {
5243 dev_priv->max_cdclk_freq = 400000;
5244 } else {
5245 /* otherwise assume cdclk is fixed */
5246 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5247 }
5248
5249 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5250 dev_priv->max_cdclk_freq);
5251 }
5252
5253 static void intel_update_cdclk(struct drm_device *dev)
5254 {
5255 struct drm_i915_private *dev_priv = dev->dev_private;
5256
5257 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5258 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5259 dev_priv->cdclk_freq);
5260
5261 /*
5262 * Program the gmbus_freq based on the cdclk frequency.
5263 * BSpec erroneously claims we should aim for 4MHz, but
5264 * in fact 1MHz is the correct frequency.
5265 */
5266 if (IS_VALLEYVIEW(dev)) {
5267 /*
5268 * Program the gmbus_freq based on the cdclk frequency.
5269 * BSpec erroneously claims we should aim for 4MHz, but
5270 * in fact 1MHz is the correct frequency.
5271 */
5272 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5273 }
5274
5275 if (dev_priv->max_cdclk_freq == 0)
5276 intel_update_max_cdclk(dev);
5277 }
5278
5279 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5280 {
5281 struct drm_i915_private *dev_priv = dev->dev_private;
5282 uint32_t divider;
5283 uint32_t ratio;
5284 uint32_t current_freq;
5285 int ret;
5286
5287 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5288 switch (frequency) {
5289 case 144000:
5290 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5291 ratio = BXT_DE_PLL_RATIO(60);
5292 break;
5293 case 288000:
5294 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5295 ratio = BXT_DE_PLL_RATIO(60);
5296 break;
5297 case 384000:
5298 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5299 ratio = BXT_DE_PLL_RATIO(60);
5300 break;
5301 case 576000:
5302 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5303 ratio = BXT_DE_PLL_RATIO(60);
5304 break;
5305 case 624000:
5306 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5307 ratio = BXT_DE_PLL_RATIO(65);
5308 break;
5309 case 19200:
5310 /*
5311 * Bypass frequency with DE PLL disabled. Init ratio, divider
5312 * to suppress GCC warning.
5313 */
5314 ratio = 0;
5315 divider = 0;
5316 break;
5317 default:
5318 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5319
5320 return;
5321 }
5322
5323 mutex_lock(&dev_priv->rps.hw_lock);
5324 /* Inform power controller of upcoming frequency change */
5325 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5326 0x80000000);
5327 mutex_unlock(&dev_priv->rps.hw_lock);
5328
5329 if (ret) {
5330 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5331 ret, frequency);
5332 return;
5333 }
5334
5335 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5336 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5337 current_freq = current_freq * 500 + 1000;
5338
5339 /*
5340 * DE PLL has to be disabled when
5341 * - setting to 19.2MHz (bypass, PLL isn't used)
5342 * - before setting to 624MHz (PLL needs toggling)
5343 * - before setting to any frequency from 624MHz (PLL needs toggling)
5344 */
5345 if (frequency == 19200 || frequency == 624000 ||
5346 current_freq == 624000) {
5347 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5348 /* Timeout 200us */
5349 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5350 1))
5351 DRM_ERROR("timout waiting for DE PLL unlock\n");
5352 }
5353
5354 if (frequency != 19200) {
5355 uint32_t val;
5356
5357 val = I915_READ(BXT_DE_PLL_CTL);
5358 val &= ~BXT_DE_PLL_RATIO_MASK;
5359 val |= ratio;
5360 I915_WRITE(BXT_DE_PLL_CTL, val);
5361
5362 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5363 /* Timeout 200us */
5364 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5365 DRM_ERROR("timeout waiting for DE PLL lock\n");
5366
5367 val = I915_READ(CDCLK_CTL);
5368 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5369 val |= divider;
5370 /*
5371 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5372 * enable otherwise.
5373 */
5374 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5375 if (frequency >= 500000)
5376 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5377
5378 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5379 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5380 val |= (frequency - 1000) / 500;
5381 I915_WRITE(CDCLK_CTL, val);
5382 }
5383
5384 mutex_lock(&dev_priv->rps.hw_lock);
5385 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5386 DIV_ROUND_UP(frequency, 25000));
5387 mutex_unlock(&dev_priv->rps.hw_lock);
5388
5389 if (ret) {
5390 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5391 ret, frequency);
5392 return;
5393 }
5394
5395 intel_update_cdclk(dev);
5396 }
5397
5398 void broxton_init_cdclk(struct drm_device *dev)
5399 {
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 uint32_t val;
5402
5403 /*
5404 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5405 * or else the reset will hang because there is no PCH to respond.
5406 * Move the handshake programming to initialization sequence.
5407 * Previously was left up to BIOS.
5408 */
5409 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5410 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5411 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5412
5413 /* Enable PG1 for cdclk */
5414 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5415
5416 /* check if cd clock is enabled */
5417 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5418 DRM_DEBUG_KMS("Display already initialized\n");
5419 return;
5420 }
5421
5422 /*
5423 * FIXME:
5424 * - The initial CDCLK needs to be read from VBT.
5425 * Need to make this change after VBT has changes for BXT.
5426 * - check if setting the max (or any) cdclk freq is really necessary
5427 * here, it belongs to modeset time
5428 */
5429 broxton_set_cdclk(dev, 624000);
5430
5431 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5432 POSTING_READ(DBUF_CTL);
5433
5434 udelay(10);
5435
5436 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5437 DRM_ERROR("DBuf power enable timeout!\n");
5438 }
5439
5440 void broxton_uninit_cdclk(struct drm_device *dev)
5441 {
5442 struct drm_i915_private *dev_priv = dev->dev_private;
5443
5444 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5445 POSTING_READ(DBUF_CTL);
5446
5447 udelay(10);
5448
5449 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5450 DRM_ERROR("DBuf power disable timeout!\n");
5451
5452 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5453 broxton_set_cdclk(dev, 19200);
5454
5455 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5456 }
5457
5458 static const struct skl_cdclk_entry {
5459 unsigned int freq;
5460 unsigned int vco;
5461 } skl_cdclk_frequencies[] = {
5462 { .freq = 308570, .vco = 8640 },
5463 { .freq = 337500, .vco = 8100 },
5464 { .freq = 432000, .vco = 8640 },
5465 { .freq = 450000, .vco = 8100 },
5466 { .freq = 540000, .vco = 8100 },
5467 { .freq = 617140, .vco = 8640 },
5468 { .freq = 675000, .vco = 8100 },
5469 };
5470
5471 static unsigned int skl_cdclk_decimal(unsigned int freq)
5472 {
5473 return (freq - 1000) / 500;
5474 }
5475
5476 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5477 {
5478 unsigned int i;
5479
5480 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5481 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5482
5483 if (e->freq == freq)
5484 return e->vco;
5485 }
5486
5487 return 8100;
5488 }
5489
5490 static void
5491 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5492 {
5493 unsigned int min_freq;
5494 u32 val;
5495
5496 /* select the minimum CDCLK before enabling DPLL 0 */
5497 val = I915_READ(CDCLK_CTL);
5498 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5499 val |= CDCLK_FREQ_337_308;
5500
5501 if (required_vco == 8640)
5502 min_freq = 308570;
5503 else
5504 min_freq = 337500;
5505
5506 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5507
5508 I915_WRITE(CDCLK_CTL, val);
5509 POSTING_READ(CDCLK_CTL);
5510
5511 /*
5512 * We always enable DPLL0 with the lowest link rate possible, but still
5513 * taking into account the VCO required to operate the eDP panel at the
5514 * desired frequency. The usual DP link rates operate with a VCO of
5515 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5516 * The modeset code is responsible for the selection of the exact link
5517 * rate later on, with the constraint of choosing a frequency that
5518 * works with required_vco.
5519 */
5520 val = I915_READ(DPLL_CTRL1);
5521
5522 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5523 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5524 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5525 if (required_vco == 8640)
5526 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5527 SKL_DPLL0);
5528 else
5529 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5530 SKL_DPLL0);
5531
5532 I915_WRITE(DPLL_CTRL1, val);
5533 POSTING_READ(DPLL_CTRL1);
5534
5535 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5536
5537 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5538 DRM_ERROR("DPLL0 not locked\n");
5539 }
5540
5541 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5542 {
5543 int ret;
5544 u32 val;
5545
5546 /* inform PCU we want to change CDCLK */
5547 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5548 mutex_lock(&dev_priv->rps.hw_lock);
5549 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5550 mutex_unlock(&dev_priv->rps.hw_lock);
5551
5552 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5553 }
5554
5555 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5556 {
5557 unsigned int i;
5558
5559 for (i = 0; i < 15; i++) {
5560 if (skl_cdclk_pcu_ready(dev_priv))
5561 return true;
5562 udelay(10);
5563 }
5564
5565 return false;
5566 }
5567
5568 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5569 {
5570 struct drm_device *dev = dev_priv->dev;
5571 u32 freq_select, pcu_ack;
5572
5573 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5574
5575 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5576 DRM_ERROR("failed to inform PCU about cdclk change\n");
5577 return;
5578 }
5579
5580 /* set CDCLK_CTL */
5581 switch(freq) {
5582 case 450000:
5583 case 432000:
5584 freq_select = CDCLK_FREQ_450_432;
5585 pcu_ack = 1;
5586 break;
5587 case 540000:
5588 freq_select = CDCLK_FREQ_540;
5589 pcu_ack = 2;
5590 break;
5591 case 308570:
5592 case 337500:
5593 default:
5594 freq_select = CDCLK_FREQ_337_308;
5595 pcu_ack = 0;
5596 break;
5597 case 617140:
5598 case 675000:
5599 freq_select = CDCLK_FREQ_675_617;
5600 pcu_ack = 3;
5601 break;
5602 }
5603
5604 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5605 POSTING_READ(CDCLK_CTL);
5606
5607 /* inform PCU of the change */
5608 mutex_lock(&dev_priv->rps.hw_lock);
5609 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5610 mutex_unlock(&dev_priv->rps.hw_lock);
5611
5612 intel_update_cdclk(dev);
5613 }
5614
5615 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5616 {
5617 /* disable DBUF power */
5618 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5619 POSTING_READ(DBUF_CTL);
5620
5621 udelay(10);
5622
5623 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5624 DRM_ERROR("DBuf power disable timeout\n");
5625
5626 /* disable DPLL0 */
5627 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5628 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5629 DRM_ERROR("Couldn't disable DPLL0\n");
5630
5631 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5632 }
5633
5634 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5635 {
5636 u32 val;
5637 unsigned int required_vco;
5638
5639 /* enable PCH reset handshake */
5640 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5641 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5642
5643 /* enable PG1 and Misc I/O */
5644 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5645
5646 /* DPLL0 already enabed !? */
5647 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5648 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5649 return;
5650 }
5651
5652 /* enable DPLL0 */
5653 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5654 skl_dpll0_enable(dev_priv, required_vco);
5655
5656 /* set CDCLK to the frequency the BIOS chose */
5657 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5658
5659 /* enable DBUF power */
5660 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5661 POSTING_READ(DBUF_CTL);
5662
5663 udelay(10);
5664
5665 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5666 DRM_ERROR("DBuf power enable timeout\n");
5667 }
5668
5669 /* returns HPLL frequency in kHz */
5670 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5671 {
5672 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5673
5674 /* Obtain SKU information */
5675 mutex_lock(&dev_priv->sb_lock);
5676 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5677 CCK_FUSE_HPLL_FREQ_MASK;
5678 mutex_unlock(&dev_priv->sb_lock);
5679
5680 return vco_freq[hpll_freq] * 1000;
5681 }
5682
5683 /* Adjust CDclk dividers to allow high res or save power if possible */
5684 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5685 {
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 u32 val, cmd;
5688
5689 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5690 != dev_priv->cdclk_freq);
5691
5692 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5693 cmd = 2;
5694 else if (cdclk == 266667)
5695 cmd = 1;
5696 else
5697 cmd = 0;
5698
5699 mutex_lock(&dev_priv->rps.hw_lock);
5700 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5701 val &= ~DSPFREQGUAR_MASK;
5702 val |= (cmd << DSPFREQGUAR_SHIFT);
5703 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5704 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5705 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5706 50)) {
5707 DRM_ERROR("timed out waiting for CDclk change\n");
5708 }
5709 mutex_unlock(&dev_priv->rps.hw_lock);
5710
5711 mutex_lock(&dev_priv->sb_lock);
5712
5713 if (cdclk == 400000) {
5714 u32 divider;
5715
5716 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5717
5718 /* adjust cdclk divider */
5719 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5720 val &= ~DISPLAY_FREQUENCY_VALUES;
5721 val |= divider;
5722 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5723
5724 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5725 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5726 50))
5727 DRM_ERROR("timed out waiting for CDclk change\n");
5728 }
5729
5730 /* adjust self-refresh exit latency value */
5731 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5732 val &= ~0x7f;
5733
5734 /*
5735 * For high bandwidth configs, we set a higher latency in the bunit
5736 * so that the core display fetch happens in time to avoid underruns.
5737 */
5738 if (cdclk == 400000)
5739 val |= 4500 / 250; /* 4.5 usec */
5740 else
5741 val |= 3000 / 250; /* 3.0 usec */
5742 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5743
5744 mutex_unlock(&dev_priv->sb_lock);
5745
5746 intel_update_cdclk(dev);
5747 }
5748
5749 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5750 {
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 u32 val, cmd;
5753
5754 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5755 != dev_priv->cdclk_freq);
5756
5757 switch (cdclk) {
5758 case 333333:
5759 case 320000:
5760 case 266667:
5761 case 200000:
5762 break;
5763 default:
5764 MISSING_CASE(cdclk);
5765 return;
5766 }
5767
5768 /*
5769 * Specs are full of misinformation, but testing on actual
5770 * hardware has shown that we just need to write the desired
5771 * CCK divider into the Punit register.
5772 */
5773 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5774
5775 mutex_lock(&dev_priv->rps.hw_lock);
5776 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5777 val &= ~DSPFREQGUAR_MASK_CHV;
5778 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5779 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5780 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5781 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5782 50)) {
5783 DRM_ERROR("timed out waiting for CDclk change\n");
5784 }
5785 mutex_unlock(&dev_priv->rps.hw_lock);
5786
5787 intel_update_cdclk(dev);
5788 }
5789
5790 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5791 int max_pixclk)
5792 {
5793 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5794 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5795
5796 /*
5797 * Really only a few cases to deal with, as only 4 CDclks are supported:
5798 * 200MHz
5799 * 267MHz
5800 * 320/333MHz (depends on HPLL freq)
5801 * 400MHz (VLV only)
5802 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5803 * of the lower bin and adjust if needed.
5804 *
5805 * We seem to get an unstable or solid color picture at 200MHz.
5806 * Not sure what's wrong. For now use 200MHz only when all pipes
5807 * are off.
5808 */
5809 if (!IS_CHERRYVIEW(dev_priv) &&
5810 max_pixclk > freq_320*limit/100)
5811 return 400000;
5812 else if (max_pixclk > 266667*limit/100)
5813 return freq_320;
5814 else if (max_pixclk > 0)
5815 return 266667;
5816 else
5817 return 200000;
5818 }
5819
5820 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5821 int max_pixclk)
5822 {
5823 /*
5824 * FIXME:
5825 * - remove the guardband, it's not needed on BXT
5826 * - set 19.2MHz bypass frequency if there are no active pipes
5827 */
5828 if (max_pixclk > 576000*9/10)
5829 return 624000;
5830 else if (max_pixclk > 384000*9/10)
5831 return 576000;
5832 else if (max_pixclk > 288000*9/10)
5833 return 384000;
5834 else if (max_pixclk > 144000*9/10)
5835 return 288000;
5836 else
5837 return 144000;
5838 }
5839
5840 /* Compute the max pixel clock for new configuration. Uses atomic state if
5841 * that's non-NULL, look at current state otherwise. */
5842 static int intel_mode_max_pixclk(struct drm_device *dev,
5843 struct drm_atomic_state *state)
5844 {
5845 struct intel_crtc *intel_crtc;
5846 struct intel_crtc_state *crtc_state;
5847 int max_pixclk = 0;
5848
5849 for_each_intel_crtc(dev, intel_crtc) {
5850 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5851 if (IS_ERR(crtc_state))
5852 return PTR_ERR(crtc_state);
5853
5854 if (!crtc_state->base.enable)
5855 continue;
5856
5857 max_pixclk = max(max_pixclk,
5858 crtc_state->base.adjusted_mode.crtc_clock);
5859 }
5860
5861 return max_pixclk;
5862 }
5863
5864 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5865 {
5866 struct drm_device *dev = state->dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 int max_pixclk = intel_mode_max_pixclk(dev, state);
5869
5870 if (max_pixclk < 0)
5871 return max_pixclk;
5872
5873 to_intel_atomic_state(state)->cdclk =
5874 valleyview_calc_cdclk(dev_priv, max_pixclk);
5875
5876 return 0;
5877 }
5878
5879 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5880 {
5881 struct drm_device *dev = state->dev;
5882 struct drm_i915_private *dev_priv = dev->dev_private;
5883 int max_pixclk = intel_mode_max_pixclk(dev, state);
5884
5885 if (max_pixclk < 0)
5886 return max_pixclk;
5887
5888 to_intel_atomic_state(state)->cdclk =
5889 broxton_calc_cdclk(dev_priv, max_pixclk);
5890
5891 return 0;
5892 }
5893
5894 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5895 {
5896 unsigned int credits, default_credits;
5897
5898 if (IS_CHERRYVIEW(dev_priv))
5899 default_credits = PFI_CREDIT(12);
5900 else
5901 default_credits = PFI_CREDIT(8);
5902
5903 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5904 /* CHV suggested value is 31 or 63 */
5905 if (IS_CHERRYVIEW(dev_priv))
5906 credits = PFI_CREDIT_63;
5907 else
5908 credits = PFI_CREDIT(15);
5909 } else {
5910 credits = default_credits;
5911 }
5912
5913 /*
5914 * WA - write default credits before re-programming
5915 * FIXME: should we also set the resend bit here?
5916 */
5917 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5918 default_credits);
5919
5920 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5921 credits | PFI_CREDIT_RESEND);
5922
5923 /*
5924 * FIXME is this guaranteed to clear
5925 * immediately or should we poll for it?
5926 */
5927 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5928 }
5929
5930 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5931 {
5932 struct drm_device *dev = old_state->dev;
5933 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935
5936 /*
5937 * FIXME: We can end up here with all power domains off, yet
5938 * with a CDCLK frequency other than the minimum. To account
5939 * for this take the PIPE-A power domain, which covers the HW
5940 * blocks needed for the following programming. This can be
5941 * removed once it's guaranteed that we get here either with
5942 * the minimum CDCLK set, or the required power domains
5943 * enabled.
5944 */
5945 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5946
5947 if (IS_CHERRYVIEW(dev))
5948 cherryview_set_cdclk(dev, req_cdclk);
5949 else
5950 valleyview_set_cdclk(dev, req_cdclk);
5951
5952 vlv_program_pfi_credits(dev_priv);
5953
5954 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5955 }
5956
5957 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5958 {
5959 struct drm_device *dev = crtc->dev;
5960 struct drm_i915_private *dev_priv = to_i915(dev);
5961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5962 struct intel_encoder *encoder;
5963 int pipe = intel_crtc->pipe;
5964 bool is_dsi;
5965
5966 if (WARN_ON(intel_crtc->active))
5967 return;
5968
5969 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5970
5971 if (!is_dsi) {
5972 if (IS_CHERRYVIEW(dev))
5973 chv_prepare_pll(intel_crtc, intel_crtc->config);
5974 else
5975 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5976 }
5977
5978 if (intel_crtc->config->has_dp_encoder)
5979 intel_dp_set_m_n(intel_crtc, M1_N1);
5980
5981 intel_set_pipe_timings(intel_crtc);
5982
5983 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5984 struct drm_i915_private *dev_priv = dev->dev_private;
5985
5986 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5987 I915_WRITE(CHV_CANVAS(pipe), 0);
5988 }
5989
5990 i9xx_set_pipeconf(intel_crtc);
5991
5992 intel_crtc->active = true;
5993
5994 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5995
5996 for_each_encoder_on_crtc(dev, crtc, encoder)
5997 if (encoder->pre_pll_enable)
5998 encoder->pre_pll_enable(encoder);
5999
6000 if (!is_dsi) {
6001 if (IS_CHERRYVIEW(dev))
6002 chv_enable_pll(intel_crtc, intel_crtc->config);
6003 else
6004 vlv_enable_pll(intel_crtc, intel_crtc->config);
6005 }
6006
6007 for_each_encoder_on_crtc(dev, crtc, encoder)
6008 if (encoder->pre_enable)
6009 encoder->pre_enable(encoder);
6010
6011 i9xx_pfit_enable(intel_crtc);
6012
6013 intel_crtc_load_lut(crtc);
6014
6015 intel_update_watermarks(crtc);
6016 intel_enable_pipe(intel_crtc);
6017
6018 assert_vblank_disabled(crtc);
6019 drm_crtc_vblank_on(crtc);
6020
6021 for_each_encoder_on_crtc(dev, crtc, encoder)
6022 encoder->enable(encoder);
6023 }
6024
6025 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6026 {
6027 struct drm_device *dev = crtc->base.dev;
6028 struct drm_i915_private *dev_priv = dev->dev_private;
6029
6030 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6031 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6032 }
6033
6034 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6035 {
6036 struct drm_device *dev = crtc->dev;
6037 struct drm_i915_private *dev_priv = to_i915(dev);
6038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6039 struct intel_encoder *encoder;
6040 int pipe = intel_crtc->pipe;
6041
6042 if (WARN_ON(intel_crtc->active))
6043 return;
6044
6045 i9xx_set_pll_dividers(intel_crtc);
6046
6047 if (intel_crtc->config->has_dp_encoder)
6048 intel_dp_set_m_n(intel_crtc, M1_N1);
6049
6050 intel_set_pipe_timings(intel_crtc);
6051
6052 i9xx_set_pipeconf(intel_crtc);
6053
6054 intel_crtc->active = true;
6055
6056 if (!IS_GEN2(dev))
6057 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6058
6059 for_each_encoder_on_crtc(dev, crtc, encoder)
6060 if (encoder->pre_enable)
6061 encoder->pre_enable(encoder);
6062
6063 i9xx_enable_pll(intel_crtc);
6064
6065 i9xx_pfit_enable(intel_crtc);
6066
6067 intel_crtc_load_lut(crtc);
6068
6069 intel_update_watermarks(crtc);
6070 intel_enable_pipe(intel_crtc);
6071
6072 assert_vblank_disabled(crtc);
6073 drm_crtc_vblank_on(crtc);
6074
6075 for_each_encoder_on_crtc(dev, crtc, encoder)
6076 encoder->enable(encoder);
6077 }
6078
6079 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6080 {
6081 struct drm_device *dev = crtc->base.dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083
6084 if (!crtc->config->gmch_pfit.control)
6085 return;
6086
6087 assert_pipe_disabled(dev_priv, crtc->pipe);
6088
6089 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6090 I915_READ(PFIT_CONTROL));
6091 I915_WRITE(PFIT_CONTROL, 0);
6092 }
6093
6094 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6095 {
6096 struct drm_device *dev = crtc->dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6099 struct intel_encoder *encoder;
6100 int pipe = intel_crtc->pipe;
6101
6102 /*
6103 * On gen2 planes are double buffered but the pipe isn't, so we must
6104 * wait for planes to fully turn off before disabling the pipe.
6105 * We also need to wait on all gmch platforms because of the
6106 * self-refresh mode constraint explained above.
6107 */
6108 intel_wait_for_vblank(dev, pipe);
6109
6110 for_each_encoder_on_crtc(dev, crtc, encoder)
6111 encoder->disable(encoder);
6112
6113 drm_crtc_vblank_off(crtc);
6114 assert_vblank_disabled(crtc);
6115
6116 intel_disable_pipe(intel_crtc);
6117
6118 i9xx_pfit_disable(intel_crtc);
6119
6120 for_each_encoder_on_crtc(dev, crtc, encoder)
6121 if (encoder->post_disable)
6122 encoder->post_disable(encoder);
6123
6124 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6125 if (IS_CHERRYVIEW(dev))
6126 chv_disable_pll(dev_priv, pipe);
6127 else if (IS_VALLEYVIEW(dev))
6128 vlv_disable_pll(dev_priv, pipe);
6129 else
6130 i9xx_disable_pll(intel_crtc);
6131 }
6132
6133 if (!IS_GEN2(dev))
6134 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6135 }
6136
6137 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6138 {
6139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6140 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6141 enum intel_display_power_domain domain;
6142 unsigned long domains;
6143
6144 if (!intel_crtc->active)
6145 return;
6146
6147 if (to_intel_plane_state(crtc->primary->state)->visible) {
6148 intel_crtc_wait_for_pending_flips(crtc);
6149 intel_pre_disable_primary(crtc);
6150 }
6151
6152 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6153 dev_priv->display.crtc_disable(crtc);
6154
6155 domains = intel_crtc->enabled_power_domains;
6156 for_each_power_domain(domain, domains)
6157 intel_display_power_put(dev_priv, domain);
6158 intel_crtc->enabled_power_domains = 0;
6159 }
6160
6161 /*
6162 * turn all crtc's off, but do not adjust state
6163 * This has to be paired with a call to intel_modeset_setup_hw_state.
6164 */
6165 void intel_display_suspend(struct drm_device *dev)
6166 {
6167 struct drm_crtc *crtc;
6168
6169 for_each_crtc(dev, crtc)
6170 intel_crtc_disable_noatomic(crtc);
6171 }
6172
6173 /* Master function to enable/disable CRTC and corresponding power wells */
6174 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6175 {
6176 struct drm_device *dev = crtc->dev;
6177 struct drm_mode_config *config = &dev->mode_config;
6178 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 struct intel_crtc_state *pipe_config;
6181 struct drm_atomic_state *state;
6182 int ret;
6183
6184 if (enable == intel_crtc->active)
6185 return 0;
6186
6187 if (enable && !crtc->state->enable)
6188 return 0;
6189
6190 /* this function should be called with drm_modeset_lock_all for now */
6191 if (WARN_ON(!ctx))
6192 return -EIO;
6193 lockdep_assert_held(&ctx->ww_ctx);
6194
6195 state = drm_atomic_state_alloc(dev);
6196 if (WARN_ON(!state))
6197 return -ENOMEM;
6198
6199 state->acquire_ctx = ctx;
6200 state->allow_modeset = true;
6201
6202 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6203 if (IS_ERR(pipe_config)) {
6204 ret = PTR_ERR(pipe_config);
6205 goto err;
6206 }
6207 pipe_config->base.active = enable;
6208
6209 ret = intel_set_mode(state);
6210 if (!ret)
6211 return ret;
6212
6213 err:
6214 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6215 drm_atomic_state_free(state);
6216 return ret;
6217 }
6218
6219 /**
6220 * Sets the power management mode of the pipe and plane.
6221 */
6222 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6223 {
6224 struct drm_device *dev = crtc->dev;
6225 struct intel_encoder *intel_encoder;
6226 bool enable = false;
6227
6228 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6229 enable |= intel_encoder->connectors_active;
6230
6231 intel_crtc_control(crtc, enable);
6232 }
6233
6234 void intel_encoder_destroy(struct drm_encoder *encoder)
6235 {
6236 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6237
6238 drm_encoder_cleanup(encoder);
6239 kfree(intel_encoder);
6240 }
6241
6242 /* Simple dpms helper for encoders with just one connector, no cloning and only
6243 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6244 * state of the entire output pipe. */
6245 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6246 {
6247 if (mode == DRM_MODE_DPMS_ON) {
6248 encoder->connectors_active = true;
6249
6250 intel_crtc_update_dpms(encoder->base.crtc);
6251 } else {
6252 encoder->connectors_active = false;
6253
6254 intel_crtc_update_dpms(encoder->base.crtc);
6255 }
6256 }
6257
6258 /* Cross check the actual hw state with our own modeset state tracking (and it's
6259 * internal consistency). */
6260 static void intel_connector_check_state(struct intel_connector *connector)
6261 {
6262 if (connector->get_hw_state(connector)) {
6263 struct intel_encoder *encoder = connector->encoder;
6264 struct drm_crtc *crtc;
6265 bool encoder_enabled;
6266 enum pipe pipe;
6267
6268 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6269 connector->base.base.id,
6270 connector->base.name);
6271
6272 /* there is no real hw state for MST connectors */
6273 if (connector->mst_port)
6274 return;
6275
6276 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6277 "wrong connector dpms state\n");
6278 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6279 "active connector not linked to encoder\n");
6280
6281 if (encoder) {
6282 I915_STATE_WARN(!encoder->connectors_active,
6283 "encoder->connectors_active not set\n");
6284
6285 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6286 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6287 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6288 return;
6289
6290 crtc = encoder->base.crtc;
6291
6292 I915_STATE_WARN(!crtc->state->enable,
6293 "crtc not enabled\n");
6294 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6295 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6296 "encoder active on the wrong pipe\n");
6297 }
6298 }
6299 }
6300
6301 int intel_connector_init(struct intel_connector *connector)
6302 {
6303 struct drm_connector_state *connector_state;
6304
6305 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6306 if (!connector_state)
6307 return -ENOMEM;
6308
6309 connector->base.state = connector_state;
6310 return 0;
6311 }
6312
6313 struct intel_connector *intel_connector_alloc(void)
6314 {
6315 struct intel_connector *connector;
6316
6317 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6318 if (!connector)
6319 return NULL;
6320
6321 if (intel_connector_init(connector) < 0) {
6322 kfree(connector);
6323 return NULL;
6324 }
6325
6326 return connector;
6327 }
6328
6329 /* Even simpler default implementation, if there's really no special case to
6330 * consider. */
6331 void intel_connector_dpms(struct drm_connector *connector, int mode)
6332 {
6333 /* All the simple cases only support two dpms states. */
6334 if (mode != DRM_MODE_DPMS_ON)
6335 mode = DRM_MODE_DPMS_OFF;
6336
6337 if (mode == connector->dpms)
6338 return;
6339
6340 connector->dpms = mode;
6341
6342 /* Only need to change hw state when actually enabled */
6343 if (connector->encoder)
6344 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6345
6346 intel_modeset_check_state(connector->dev);
6347 }
6348
6349 /* Simple connector->get_hw_state implementation for encoders that support only
6350 * one connector and no cloning and hence the encoder state determines the state
6351 * of the connector. */
6352 bool intel_connector_get_hw_state(struct intel_connector *connector)
6353 {
6354 enum pipe pipe = 0;
6355 struct intel_encoder *encoder = connector->encoder;
6356
6357 return encoder->get_hw_state(encoder, &pipe);
6358 }
6359
6360 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6361 {
6362 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6363 return crtc_state->fdi_lanes;
6364
6365 return 0;
6366 }
6367
6368 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6369 struct intel_crtc_state *pipe_config)
6370 {
6371 struct drm_atomic_state *state = pipe_config->base.state;
6372 struct intel_crtc *other_crtc;
6373 struct intel_crtc_state *other_crtc_state;
6374
6375 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6376 pipe_name(pipe), pipe_config->fdi_lanes);
6377 if (pipe_config->fdi_lanes > 4) {
6378 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6379 pipe_name(pipe), pipe_config->fdi_lanes);
6380 return -EINVAL;
6381 }
6382
6383 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6384 if (pipe_config->fdi_lanes > 2) {
6385 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6386 pipe_config->fdi_lanes);
6387 return -EINVAL;
6388 } else {
6389 return 0;
6390 }
6391 }
6392
6393 if (INTEL_INFO(dev)->num_pipes == 2)
6394 return 0;
6395
6396 /* Ivybridge 3 pipe is really complicated */
6397 switch (pipe) {
6398 case PIPE_A:
6399 return 0;
6400 case PIPE_B:
6401 if (pipe_config->fdi_lanes <= 2)
6402 return 0;
6403
6404 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6405 other_crtc_state =
6406 intel_atomic_get_crtc_state(state, other_crtc);
6407 if (IS_ERR(other_crtc_state))
6408 return PTR_ERR(other_crtc_state);
6409
6410 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6411 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6412 pipe_name(pipe), pipe_config->fdi_lanes);
6413 return -EINVAL;
6414 }
6415 return 0;
6416 case PIPE_C:
6417 if (pipe_config->fdi_lanes > 2) {
6418 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6419 pipe_name(pipe), pipe_config->fdi_lanes);
6420 return -EINVAL;
6421 }
6422
6423 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6424 other_crtc_state =
6425 intel_atomic_get_crtc_state(state, other_crtc);
6426 if (IS_ERR(other_crtc_state))
6427 return PTR_ERR(other_crtc_state);
6428
6429 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6430 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6431 return -EINVAL;
6432 }
6433 return 0;
6434 default:
6435 BUG();
6436 }
6437 }
6438
6439 #define RETRY 1
6440 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6441 struct intel_crtc_state *pipe_config)
6442 {
6443 struct drm_device *dev = intel_crtc->base.dev;
6444 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6445 int lane, link_bw, fdi_dotclock, ret;
6446 bool needs_recompute = false;
6447
6448 retry:
6449 /* FDI is a binary signal running at ~2.7GHz, encoding
6450 * each output octet as 10 bits. The actual frequency
6451 * is stored as a divider into a 100MHz clock, and the
6452 * mode pixel clock is stored in units of 1KHz.
6453 * Hence the bw of each lane in terms of the mode signal
6454 * is:
6455 */
6456 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6457
6458 fdi_dotclock = adjusted_mode->crtc_clock;
6459
6460 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6461 pipe_config->pipe_bpp);
6462
6463 pipe_config->fdi_lanes = lane;
6464
6465 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6466 link_bw, &pipe_config->fdi_m_n);
6467
6468 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6469 intel_crtc->pipe, pipe_config);
6470 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6471 pipe_config->pipe_bpp -= 2*3;
6472 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6473 pipe_config->pipe_bpp);
6474 needs_recompute = true;
6475 pipe_config->bw_constrained = true;
6476
6477 goto retry;
6478 }
6479
6480 if (needs_recompute)
6481 return RETRY;
6482
6483 return ret;
6484 }
6485
6486 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6487 struct intel_crtc_state *pipe_config)
6488 {
6489 if (pipe_config->pipe_bpp > 24)
6490 return false;
6491
6492 /* HSW can handle pixel rate up to cdclk? */
6493 if (IS_HASWELL(dev_priv->dev))
6494 return true;
6495
6496 /*
6497 * We compare against max which means we must take
6498 * the increased cdclk requirement into account when
6499 * calculating the new cdclk.
6500 *
6501 * Should measure whether using a lower cdclk w/o IPS
6502 */
6503 return ilk_pipe_pixel_rate(pipe_config) <=
6504 dev_priv->max_cdclk_freq * 95 / 100;
6505 }
6506
6507 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6508 struct intel_crtc_state *pipe_config)
6509 {
6510 struct drm_device *dev = crtc->base.dev;
6511 struct drm_i915_private *dev_priv = dev->dev_private;
6512
6513 pipe_config->ips_enabled = i915.enable_ips &&
6514 hsw_crtc_supports_ips(crtc) &&
6515 pipe_config_supports_ips(dev_priv, pipe_config);
6516 }
6517
6518 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6519 struct intel_crtc_state *pipe_config)
6520 {
6521 struct drm_device *dev = crtc->base.dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6524
6525 /* FIXME should check pixel clock limits on all platforms */
6526 if (INTEL_INFO(dev)->gen < 4) {
6527 int clock_limit = dev_priv->max_cdclk_freq;
6528
6529 /*
6530 * Enable pixel doubling when the dot clock
6531 * is > 90% of the (display) core speed.
6532 *
6533 * GDG double wide on either pipe,
6534 * otherwise pipe A only.
6535 */
6536 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6537 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6538 clock_limit *= 2;
6539 pipe_config->double_wide = true;
6540 }
6541
6542 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6543 return -EINVAL;
6544 }
6545
6546 /*
6547 * Pipe horizontal size must be even in:
6548 * - DVO ganged mode
6549 * - LVDS dual channel mode
6550 * - Double wide pipe
6551 */
6552 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6553 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6554 pipe_config->pipe_src_w &= ~1;
6555
6556 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6557 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6558 */
6559 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6560 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6561 return -EINVAL;
6562
6563 if (HAS_IPS(dev))
6564 hsw_compute_ips_config(crtc, pipe_config);
6565
6566 if (pipe_config->has_pch_encoder)
6567 return ironlake_fdi_compute_config(crtc, pipe_config);
6568
6569 return 0;
6570 }
6571
6572 static int skylake_get_display_clock_speed(struct drm_device *dev)
6573 {
6574 struct drm_i915_private *dev_priv = to_i915(dev);
6575 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6576 uint32_t cdctl = I915_READ(CDCLK_CTL);
6577 uint32_t linkrate;
6578
6579 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6580 return 24000; /* 24MHz is the cd freq with NSSC ref */
6581
6582 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6583 return 540000;
6584
6585 linkrate = (I915_READ(DPLL_CTRL1) &
6586 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6587
6588 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6589 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6590 /* vco 8640 */
6591 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6592 case CDCLK_FREQ_450_432:
6593 return 432000;
6594 case CDCLK_FREQ_337_308:
6595 return 308570;
6596 case CDCLK_FREQ_675_617:
6597 return 617140;
6598 default:
6599 WARN(1, "Unknown cd freq selection\n");
6600 }
6601 } else {
6602 /* vco 8100 */
6603 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6604 case CDCLK_FREQ_450_432:
6605 return 450000;
6606 case CDCLK_FREQ_337_308:
6607 return 337500;
6608 case CDCLK_FREQ_675_617:
6609 return 675000;
6610 default:
6611 WARN(1, "Unknown cd freq selection\n");
6612 }
6613 }
6614
6615 /* error case, do as if DPLL0 isn't enabled */
6616 return 24000;
6617 }
6618
6619 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6620 {
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 uint32_t lcpll = I915_READ(LCPLL_CTL);
6623 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6624
6625 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6626 return 800000;
6627 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6628 return 450000;
6629 else if (freq == LCPLL_CLK_FREQ_450)
6630 return 450000;
6631 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6632 return 540000;
6633 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6634 return 337500;
6635 else
6636 return 675000;
6637 }
6638
6639 static int haswell_get_display_clock_speed(struct drm_device *dev)
6640 {
6641 struct drm_i915_private *dev_priv = dev->dev_private;
6642 uint32_t lcpll = I915_READ(LCPLL_CTL);
6643 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6644
6645 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6646 return 800000;
6647 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6648 return 450000;
6649 else if (freq == LCPLL_CLK_FREQ_450)
6650 return 450000;
6651 else if (IS_HSW_ULT(dev))
6652 return 337500;
6653 else
6654 return 540000;
6655 }
6656
6657 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6658 {
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6660 u32 val;
6661 int divider;
6662
6663 if (dev_priv->hpll_freq == 0)
6664 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6665
6666 mutex_lock(&dev_priv->sb_lock);
6667 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6668 mutex_unlock(&dev_priv->sb_lock);
6669
6670 divider = val & DISPLAY_FREQUENCY_VALUES;
6671
6672 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6673 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6674 "cdclk change in progress\n");
6675
6676 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6677 }
6678
6679 static int ilk_get_display_clock_speed(struct drm_device *dev)
6680 {
6681 return 450000;
6682 }
6683
6684 static int i945_get_display_clock_speed(struct drm_device *dev)
6685 {
6686 return 400000;
6687 }
6688
6689 static int i915_get_display_clock_speed(struct drm_device *dev)
6690 {
6691 return 333333;
6692 }
6693
6694 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6695 {
6696 return 200000;
6697 }
6698
6699 static int pnv_get_display_clock_speed(struct drm_device *dev)
6700 {
6701 u16 gcfgc = 0;
6702
6703 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6704
6705 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6706 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6707 return 266667;
6708 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6709 return 333333;
6710 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6711 return 444444;
6712 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6713 return 200000;
6714 default:
6715 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6716 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6717 return 133333;
6718 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6719 return 166667;
6720 }
6721 }
6722
6723 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6724 {
6725 u16 gcfgc = 0;
6726
6727 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6728
6729 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6730 return 133333;
6731 else {
6732 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6733 case GC_DISPLAY_CLOCK_333_MHZ:
6734 return 333333;
6735 default:
6736 case GC_DISPLAY_CLOCK_190_200_MHZ:
6737 return 190000;
6738 }
6739 }
6740 }
6741
6742 static int i865_get_display_clock_speed(struct drm_device *dev)
6743 {
6744 return 266667;
6745 }
6746
6747 static int i85x_get_display_clock_speed(struct drm_device *dev)
6748 {
6749 u16 hpllcc = 0;
6750
6751 /*
6752 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6753 * encoding is different :(
6754 * FIXME is this the right way to detect 852GM/852GMV?
6755 */
6756 if (dev->pdev->revision == 0x1)
6757 return 133333;
6758
6759 pci_bus_read_config_word(dev->pdev->bus,
6760 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6761
6762 /* Assume that the hardware is in the high speed state. This
6763 * should be the default.
6764 */
6765 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6766 case GC_CLOCK_133_200:
6767 case GC_CLOCK_133_200_2:
6768 case GC_CLOCK_100_200:
6769 return 200000;
6770 case GC_CLOCK_166_250:
6771 return 250000;
6772 case GC_CLOCK_100_133:
6773 return 133333;
6774 case GC_CLOCK_133_266:
6775 case GC_CLOCK_133_266_2:
6776 case GC_CLOCK_166_266:
6777 return 266667;
6778 }
6779
6780 /* Shouldn't happen */
6781 return 0;
6782 }
6783
6784 static int i830_get_display_clock_speed(struct drm_device *dev)
6785 {
6786 return 133333;
6787 }
6788
6789 static unsigned int intel_hpll_vco(struct drm_device *dev)
6790 {
6791 struct drm_i915_private *dev_priv = dev->dev_private;
6792 static const unsigned int blb_vco[8] = {
6793 [0] = 3200000,
6794 [1] = 4000000,
6795 [2] = 5333333,
6796 [3] = 4800000,
6797 [4] = 6400000,
6798 };
6799 static const unsigned int pnv_vco[8] = {
6800 [0] = 3200000,
6801 [1] = 4000000,
6802 [2] = 5333333,
6803 [3] = 4800000,
6804 [4] = 2666667,
6805 };
6806 static const unsigned int cl_vco[8] = {
6807 [0] = 3200000,
6808 [1] = 4000000,
6809 [2] = 5333333,
6810 [3] = 6400000,
6811 [4] = 3333333,
6812 [5] = 3566667,
6813 [6] = 4266667,
6814 };
6815 static const unsigned int elk_vco[8] = {
6816 [0] = 3200000,
6817 [1] = 4000000,
6818 [2] = 5333333,
6819 [3] = 4800000,
6820 };
6821 static const unsigned int ctg_vco[8] = {
6822 [0] = 3200000,
6823 [1] = 4000000,
6824 [2] = 5333333,
6825 [3] = 6400000,
6826 [4] = 2666667,
6827 [5] = 4266667,
6828 };
6829 const unsigned int *vco_table;
6830 unsigned int vco;
6831 uint8_t tmp = 0;
6832
6833 /* FIXME other chipsets? */
6834 if (IS_GM45(dev))
6835 vco_table = ctg_vco;
6836 else if (IS_G4X(dev))
6837 vco_table = elk_vco;
6838 else if (IS_CRESTLINE(dev))
6839 vco_table = cl_vco;
6840 else if (IS_PINEVIEW(dev))
6841 vco_table = pnv_vco;
6842 else if (IS_G33(dev))
6843 vco_table = blb_vco;
6844 else
6845 return 0;
6846
6847 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6848
6849 vco = vco_table[tmp & 0x7];
6850 if (vco == 0)
6851 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6852 else
6853 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6854
6855 return vco;
6856 }
6857
6858 static int gm45_get_display_clock_speed(struct drm_device *dev)
6859 {
6860 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6861 uint16_t tmp = 0;
6862
6863 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6864
6865 cdclk_sel = (tmp >> 12) & 0x1;
6866
6867 switch (vco) {
6868 case 2666667:
6869 case 4000000:
6870 case 5333333:
6871 return cdclk_sel ? 333333 : 222222;
6872 case 3200000:
6873 return cdclk_sel ? 320000 : 228571;
6874 default:
6875 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6876 return 222222;
6877 }
6878 }
6879
6880 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6881 {
6882 static const uint8_t div_3200[] = { 16, 10, 8 };
6883 static const uint8_t div_4000[] = { 20, 12, 10 };
6884 static const uint8_t div_5333[] = { 24, 16, 14 };
6885 const uint8_t *div_table;
6886 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6887 uint16_t tmp = 0;
6888
6889 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6890
6891 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6892
6893 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6894 goto fail;
6895
6896 switch (vco) {
6897 case 3200000:
6898 div_table = div_3200;
6899 break;
6900 case 4000000:
6901 div_table = div_4000;
6902 break;
6903 case 5333333:
6904 div_table = div_5333;
6905 break;
6906 default:
6907 goto fail;
6908 }
6909
6910 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6911
6912 fail:
6913 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6914 return 200000;
6915 }
6916
6917 static int g33_get_display_clock_speed(struct drm_device *dev)
6918 {
6919 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6920 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6921 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6922 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6923 const uint8_t *div_table;
6924 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6925 uint16_t tmp = 0;
6926
6927 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6928
6929 cdclk_sel = (tmp >> 4) & 0x7;
6930
6931 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6932 goto fail;
6933
6934 switch (vco) {
6935 case 3200000:
6936 div_table = div_3200;
6937 break;
6938 case 4000000:
6939 div_table = div_4000;
6940 break;
6941 case 4800000:
6942 div_table = div_4800;
6943 break;
6944 case 5333333:
6945 div_table = div_5333;
6946 break;
6947 default:
6948 goto fail;
6949 }
6950
6951 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6952
6953 fail:
6954 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6955 return 190476;
6956 }
6957
6958 static void
6959 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6960 {
6961 while (*num > DATA_LINK_M_N_MASK ||
6962 *den > DATA_LINK_M_N_MASK) {
6963 *num >>= 1;
6964 *den >>= 1;
6965 }
6966 }
6967
6968 static void compute_m_n(unsigned int m, unsigned int n,
6969 uint32_t *ret_m, uint32_t *ret_n)
6970 {
6971 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6972 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6973 intel_reduce_m_n_ratio(ret_m, ret_n);
6974 }
6975
6976 void
6977 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6978 int pixel_clock, int link_clock,
6979 struct intel_link_m_n *m_n)
6980 {
6981 m_n->tu = 64;
6982
6983 compute_m_n(bits_per_pixel * pixel_clock,
6984 link_clock * nlanes * 8,
6985 &m_n->gmch_m, &m_n->gmch_n);
6986
6987 compute_m_n(pixel_clock, link_clock,
6988 &m_n->link_m, &m_n->link_n);
6989 }
6990
6991 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6992 {
6993 if (i915.panel_use_ssc >= 0)
6994 return i915.panel_use_ssc != 0;
6995 return dev_priv->vbt.lvds_use_ssc
6996 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6997 }
6998
6999 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7000 int num_connectors)
7001 {
7002 struct drm_device *dev = crtc_state->base.crtc->dev;
7003 struct drm_i915_private *dev_priv = dev->dev_private;
7004 int refclk;
7005
7006 WARN_ON(!crtc_state->base.state);
7007
7008 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7009 refclk = 100000;
7010 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7011 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7012 refclk = dev_priv->vbt.lvds_ssc_freq;
7013 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7014 } else if (!IS_GEN2(dev)) {
7015 refclk = 96000;
7016 } else {
7017 refclk = 48000;
7018 }
7019
7020 return refclk;
7021 }
7022
7023 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7024 {
7025 return (1 << dpll->n) << 16 | dpll->m2;
7026 }
7027
7028 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7029 {
7030 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7031 }
7032
7033 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7034 struct intel_crtc_state *crtc_state,
7035 intel_clock_t *reduced_clock)
7036 {
7037 struct drm_device *dev = crtc->base.dev;
7038 u32 fp, fp2 = 0;
7039
7040 if (IS_PINEVIEW(dev)) {
7041 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7042 if (reduced_clock)
7043 fp2 = pnv_dpll_compute_fp(reduced_clock);
7044 } else {
7045 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7046 if (reduced_clock)
7047 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7048 }
7049
7050 crtc_state->dpll_hw_state.fp0 = fp;
7051
7052 crtc->lowfreq_avail = false;
7053 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7054 reduced_clock) {
7055 crtc_state->dpll_hw_state.fp1 = fp2;
7056 crtc->lowfreq_avail = true;
7057 } else {
7058 crtc_state->dpll_hw_state.fp1 = fp;
7059 }
7060 }
7061
7062 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7063 pipe)
7064 {
7065 u32 reg_val;
7066
7067 /*
7068 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7069 * and set it to a reasonable value instead.
7070 */
7071 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7072 reg_val &= 0xffffff00;
7073 reg_val |= 0x00000030;
7074 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7075
7076 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7077 reg_val &= 0x8cffffff;
7078 reg_val = 0x8c000000;
7079 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7080
7081 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7082 reg_val &= 0xffffff00;
7083 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7084
7085 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7086 reg_val &= 0x00ffffff;
7087 reg_val |= 0xb0000000;
7088 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7089 }
7090
7091 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7092 struct intel_link_m_n *m_n)
7093 {
7094 struct drm_device *dev = crtc->base.dev;
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096 int pipe = crtc->pipe;
7097
7098 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7099 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7100 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7101 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7102 }
7103
7104 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7105 struct intel_link_m_n *m_n,
7106 struct intel_link_m_n *m2_n2)
7107 {
7108 struct drm_device *dev = crtc->base.dev;
7109 struct drm_i915_private *dev_priv = dev->dev_private;
7110 int pipe = crtc->pipe;
7111 enum transcoder transcoder = crtc->config->cpu_transcoder;
7112
7113 if (INTEL_INFO(dev)->gen >= 5) {
7114 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7115 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7116 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7117 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7118 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7119 * for gen < 8) and if DRRS is supported (to make sure the
7120 * registers are not unnecessarily accessed).
7121 */
7122 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7123 crtc->config->has_drrs) {
7124 I915_WRITE(PIPE_DATA_M2(transcoder),
7125 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7126 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7127 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7128 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7129 }
7130 } else {
7131 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7132 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7133 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7134 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7135 }
7136 }
7137
7138 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7139 {
7140 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7141
7142 if (m_n == M1_N1) {
7143 dp_m_n = &crtc->config->dp_m_n;
7144 dp_m2_n2 = &crtc->config->dp_m2_n2;
7145 } else if (m_n == M2_N2) {
7146
7147 /*
7148 * M2_N2 registers are not supported. Hence m2_n2 divider value
7149 * needs to be programmed into M1_N1.
7150 */
7151 dp_m_n = &crtc->config->dp_m2_n2;
7152 } else {
7153 DRM_ERROR("Unsupported divider value\n");
7154 return;
7155 }
7156
7157 if (crtc->config->has_pch_encoder)
7158 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7159 else
7160 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7161 }
7162
7163 static void vlv_update_pll(struct intel_crtc *crtc,
7164 struct intel_crtc_state *pipe_config)
7165 {
7166 u32 dpll, dpll_md;
7167
7168 /*
7169 * Enable DPIO clock input. We should never disable the reference
7170 * clock for pipe B, since VGA hotplug / manual detection depends
7171 * on it.
7172 */
7173 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7174 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7175 /* We should never disable this, set it here for state tracking */
7176 if (crtc->pipe == PIPE_B)
7177 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7178 dpll |= DPLL_VCO_ENABLE;
7179 pipe_config->dpll_hw_state.dpll = dpll;
7180
7181 dpll_md = (pipe_config->pixel_multiplier - 1)
7182 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7183 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7184 }
7185
7186 static void vlv_prepare_pll(struct intel_crtc *crtc,
7187 const struct intel_crtc_state *pipe_config)
7188 {
7189 struct drm_device *dev = crtc->base.dev;
7190 struct drm_i915_private *dev_priv = dev->dev_private;
7191 int pipe = crtc->pipe;
7192 u32 mdiv;
7193 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7194 u32 coreclk, reg_val;
7195
7196 mutex_lock(&dev_priv->sb_lock);
7197
7198 bestn = pipe_config->dpll.n;
7199 bestm1 = pipe_config->dpll.m1;
7200 bestm2 = pipe_config->dpll.m2;
7201 bestp1 = pipe_config->dpll.p1;
7202 bestp2 = pipe_config->dpll.p2;
7203
7204 /* See eDP HDMI DPIO driver vbios notes doc */
7205
7206 /* PLL B needs special handling */
7207 if (pipe == PIPE_B)
7208 vlv_pllb_recal_opamp(dev_priv, pipe);
7209
7210 /* Set up Tx target for periodic Rcomp update */
7211 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7212
7213 /* Disable target IRef on PLL */
7214 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7215 reg_val &= 0x00ffffff;
7216 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7217
7218 /* Disable fast lock */
7219 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7220
7221 /* Set idtafcrecal before PLL is enabled */
7222 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7223 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7224 mdiv |= ((bestn << DPIO_N_SHIFT));
7225 mdiv |= (1 << DPIO_K_SHIFT);
7226
7227 /*
7228 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7229 * but we don't support that).
7230 * Note: don't use the DAC post divider as it seems unstable.
7231 */
7232 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7233 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7234
7235 mdiv |= DPIO_ENABLE_CALIBRATION;
7236 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7237
7238 /* Set HBR and RBR LPF coefficients */
7239 if (pipe_config->port_clock == 162000 ||
7240 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7241 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7242 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7243 0x009f0003);
7244 else
7245 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7246 0x00d0000f);
7247
7248 if (pipe_config->has_dp_encoder) {
7249 /* Use SSC source */
7250 if (pipe == PIPE_A)
7251 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7252 0x0df40000);
7253 else
7254 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7255 0x0df70000);
7256 } else { /* HDMI or VGA */
7257 /* Use bend source */
7258 if (pipe == PIPE_A)
7259 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7260 0x0df70000);
7261 else
7262 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7263 0x0df40000);
7264 }
7265
7266 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7267 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7268 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7269 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7270 coreclk |= 0x01000000;
7271 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7272
7273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7274 mutex_unlock(&dev_priv->sb_lock);
7275 }
7276
7277 static void chv_update_pll(struct intel_crtc *crtc,
7278 struct intel_crtc_state *pipe_config)
7279 {
7280 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7281 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7282 DPLL_VCO_ENABLE;
7283 if (crtc->pipe != PIPE_A)
7284 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7285
7286 pipe_config->dpll_hw_state.dpll_md =
7287 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7288 }
7289
7290 static void chv_prepare_pll(struct intel_crtc *crtc,
7291 const struct intel_crtc_state *pipe_config)
7292 {
7293 struct drm_device *dev = crtc->base.dev;
7294 struct drm_i915_private *dev_priv = dev->dev_private;
7295 int pipe = crtc->pipe;
7296 int dpll_reg = DPLL(crtc->pipe);
7297 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7298 u32 loopfilter, tribuf_calcntr;
7299 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7300 u32 dpio_val;
7301 int vco;
7302
7303 bestn = pipe_config->dpll.n;
7304 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7305 bestm1 = pipe_config->dpll.m1;
7306 bestm2 = pipe_config->dpll.m2 >> 22;
7307 bestp1 = pipe_config->dpll.p1;
7308 bestp2 = pipe_config->dpll.p2;
7309 vco = pipe_config->dpll.vco;
7310 dpio_val = 0;
7311 loopfilter = 0;
7312
7313 /*
7314 * Enable Refclk and SSC
7315 */
7316 I915_WRITE(dpll_reg,
7317 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7318
7319 mutex_lock(&dev_priv->sb_lock);
7320
7321 /* p1 and p2 divider */
7322 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7323 5 << DPIO_CHV_S1_DIV_SHIFT |
7324 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7325 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7326 1 << DPIO_CHV_K_DIV_SHIFT);
7327
7328 /* Feedback post-divider - m2 */
7329 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7330
7331 /* Feedback refclk divider - n and m1 */
7332 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7333 DPIO_CHV_M1_DIV_BY_2 |
7334 1 << DPIO_CHV_N_DIV_SHIFT);
7335
7336 /* M2 fraction division */
7337 if (bestm2_frac)
7338 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7339
7340 /* M2 fraction division enable */
7341 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7342 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7343 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7344 if (bestm2_frac)
7345 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7346 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7347
7348 /* Program digital lock detect threshold */
7349 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7350 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7351 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7352 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7353 if (!bestm2_frac)
7354 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7355 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7356
7357 /* Loop filter */
7358 if (vco == 5400000) {
7359 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7360 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7361 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7362 tribuf_calcntr = 0x9;
7363 } else if (vco <= 6200000) {
7364 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7365 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7366 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7367 tribuf_calcntr = 0x9;
7368 } else if (vco <= 6480000) {
7369 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7370 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7371 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7372 tribuf_calcntr = 0x8;
7373 } else {
7374 /* Not supported. Apply the same limits as in the max case */
7375 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7376 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7377 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7378 tribuf_calcntr = 0;
7379 }
7380 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7381
7382 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7383 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7384 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7385 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7386
7387 /* AFC Recal */
7388 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7389 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7390 DPIO_AFC_RECAL);
7391
7392 mutex_unlock(&dev_priv->sb_lock);
7393 }
7394
7395 /**
7396 * vlv_force_pll_on - forcibly enable just the PLL
7397 * @dev_priv: i915 private structure
7398 * @pipe: pipe PLL to enable
7399 * @dpll: PLL configuration
7400 *
7401 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7402 * in cases where we need the PLL enabled even when @pipe is not going to
7403 * be enabled.
7404 */
7405 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7406 const struct dpll *dpll)
7407 {
7408 struct intel_crtc *crtc =
7409 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7410 struct intel_crtc_state pipe_config = {
7411 .base.crtc = &crtc->base,
7412 .pixel_multiplier = 1,
7413 .dpll = *dpll,
7414 };
7415
7416 if (IS_CHERRYVIEW(dev)) {
7417 chv_update_pll(crtc, &pipe_config);
7418 chv_prepare_pll(crtc, &pipe_config);
7419 chv_enable_pll(crtc, &pipe_config);
7420 } else {
7421 vlv_update_pll(crtc, &pipe_config);
7422 vlv_prepare_pll(crtc, &pipe_config);
7423 vlv_enable_pll(crtc, &pipe_config);
7424 }
7425 }
7426
7427 /**
7428 * vlv_force_pll_off - forcibly disable just the PLL
7429 * @dev_priv: i915 private structure
7430 * @pipe: pipe PLL to disable
7431 *
7432 * Disable the PLL for @pipe. To be used in cases where we need
7433 * the PLL enabled even when @pipe is not going to be enabled.
7434 */
7435 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7436 {
7437 if (IS_CHERRYVIEW(dev))
7438 chv_disable_pll(to_i915(dev), pipe);
7439 else
7440 vlv_disable_pll(to_i915(dev), pipe);
7441 }
7442
7443 static void i9xx_update_pll(struct intel_crtc *crtc,
7444 struct intel_crtc_state *crtc_state,
7445 intel_clock_t *reduced_clock,
7446 int num_connectors)
7447 {
7448 struct drm_device *dev = crtc->base.dev;
7449 struct drm_i915_private *dev_priv = dev->dev_private;
7450 u32 dpll;
7451 bool is_sdvo;
7452 struct dpll *clock = &crtc_state->dpll;
7453
7454 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7455
7456 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7457 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7458
7459 dpll = DPLL_VGA_MODE_DIS;
7460
7461 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7462 dpll |= DPLLB_MODE_LVDS;
7463 else
7464 dpll |= DPLLB_MODE_DAC_SERIAL;
7465
7466 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7467 dpll |= (crtc_state->pixel_multiplier - 1)
7468 << SDVO_MULTIPLIER_SHIFT_HIRES;
7469 }
7470
7471 if (is_sdvo)
7472 dpll |= DPLL_SDVO_HIGH_SPEED;
7473
7474 if (crtc_state->has_dp_encoder)
7475 dpll |= DPLL_SDVO_HIGH_SPEED;
7476
7477 /* compute bitmask from p1 value */
7478 if (IS_PINEVIEW(dev))
7479 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7480 else {
7481 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7482 if (IS_G4X(dev) && reduced_clock)
7483 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7484 }
7485 switch (clock->p2) {
7486 case 5:
7487 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7488 break;
7489 case 7:
7490 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7491 break;
7492 case 10:
7493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7494 break;
7495 case 14:
7496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7497 break;
7498 }
7499 if (INTEL_INFO(dev)->gen >= 4)
7500 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7501
7502 if (crtc_state->sdvo_tv_clock)
7503 dpll |= PLL_REF_INPUT_TVCLKINBC;
7504 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7505 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7506 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7507 else
7508 dpll |= PLL_REF_INPUT_DREFCLK;
7509
7510 dpll |= DPLL_VCO_ENABLE;
7511 crtc_state->dpll_hw_state.dpll = dpll;
7512
7513 if (INTEL_INFO(dev)->gen >= 4) {
7514 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7515 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7516 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7517 }
7518 }
7519
7520 static void i8xx_update_pll(struct intel_crtc *crtc,
7521 struct intel_crtc_state *crtc_state,
7522 intel_clock_t *reduced_clock,
7523 int num_connectors)
7524 {
7525 struct drm_device *dev = crtc->base.dev;
7526 struct drm_i915_private *dev_priv = dev->dev_private;
7527 u32 dpll;
7528 struct dpll *clock = &crtc_state->dpll;
7529
7530 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7531
7532 dpll = DPLL_VGA_MODE_DIS;
7533
7534 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7535 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7536 } else {
7537 if (clock->p1 == 2)
7538 dpll |= PLL_P1_DIVIDE_BY_TWO;
7539 else
7540 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7541 if (clock->p2 == 4)
7542 dpll |= PLL_P2_DIVIDE_BY_4;
7543 }
7544
7545 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7546 dpll |= DPLL_DVO_2X_MODE;
7547
7548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7549 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7550 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7551 else
7552 dpll |= PLL_REF_INPUT_DREFCLK;
7553
7554 dpll |= DPLL_VCO_ENABLE;
7555 crtc_state->dpll_hw_state.dpll = dpll;
7556 }
7557
7558 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7559 {
7560 struct drm_device *dev = intel_crtc->base.dev;
7561 struct drm_i915_private *dev_priv = dev->dev_private;
7562 enum pipe pipe = intel_crtc->pipe;
7563 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7564 struct drm_display_mode *adjusted_mode =
7565 &intel_crtc->config->base.adjusted_mode;
7566 uint32_t crtc_vtotal, crtc_vblank_end;
7567 int vsyncshift = 0;
7568
7569 /* We need to be careful not to changed the adjusted mode, for otherwise
7570 * the hw state checker will get angry at the mismatch. */
7571 crtc_vtotal = adjusted_mode->crtc_vtotal;
7572 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7573
7574 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7575 /* the chip adds 2 halflines automatically */
7576 crtc_vtotal -= 1;
7577 crtc_vblank_end -= 1;
7578
7579 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7580 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7581 else
7582 vsyncshift = adjusted_mode->crtc_hsync_start -
7583 adjusted_mode->crtc_htotal / 2;
7584 if (vsyncshift < 0)
7585 vsyncshift += adjusted_mode->crtc_htotal;
7586 }
7587
7588 if (INTEL_INFO(dev)->gen > 3)
7589 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7590
7591 I915_WRITE(HTOTAL(cpu_transcoder),
7592 (adjusted_mode->crtc_hdisplay - 1) |
7593 ((adjusted_mode->crtc_htotal - 1) << 16));
7594 I915_WRITE(HBLANK(cpu_transcoder),
7595 (adjusted_mode->crtc_hblank_start - 1) |
7596 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7597 I915_WRITE(HSYNC(cpu_transcoder),
7598 (adjusted_mode->crtc_hsync_start - 1) |
7599 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7600
7601 I915_WRITE(VTOTAL(cpu_transcoder),
7602 (adjusted_mode->crtc_vdisplay - 1) |
7603 ((crtc_vtotal - 1) << 16));
7604 I915_WRITE(VBLANK(cpu_transcoder),
7605 (adjusted_mode->crtc_vblank_start - 1) |
7606 ((crtc_vblank_end - 1) << 16));
7607 I915_WRITE(VSYNC(cpu_transcoder),
7608 (adjusted_mode->crtc_vsync_start - 1) |
7609 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7610
7611 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7612 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7613 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7614 * bits. */
7615 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7616 (pipe == PIPE_B || pipe == PIPE_C))
7617 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7618
7619 /* pipesrc controls the size that is scaled from, which should
7620 * always be the user's requested size.
7621 */
7622 I915_WRITE(PIPESRC(pipe),
7623 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7624 (intel_crtc->config->pipe_src_h - 1));
7625 }
7626
7627 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7628 struct intel_crtc_state *pipe_config)
7629 {
7630 struct drm_device *dev = crtc->base.dev;
7631 struct drm_i915_private *dev_priv = dev->dev_private;
7632 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7633 uint32_t tmp;
7634
7635 tmp = I915_READ(HTOTAL(cpu_transcoder));
7636 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7637 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7638 tmp = I915_READ(HBLANK(cpu_transcoder));
7639 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7640 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7641 tmp = I915_READ(HSYNC(cpu_transcoder));
7642 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7643 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7644
7645 tmp = I915_READ(VTOTAL(cpu_transcoder));
7646 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7647 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7648 tmp = I915_READ(VBLANK(cpu_transcoder));
7649 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7650 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7651 tmp = I915_READ(VSYNC(cpu_transcoder));
7652 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7653 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7654
7655 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7656 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7657 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7658 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7659 }
7660
7661 tmp = I915_READ(PIPESRC(crtc->pipe));
7662 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7663 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7664
7665 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7666 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7667 }
7668
7669 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7670 struct intel_crtc_state *pipe_config)
7671 {
7672 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7673 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7674 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7675 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7676
7677 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7678 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7679 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7680 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7681
7682 mode->flags = pipe_config->base.adjusted_mode.flags;
7683
7684 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7685 mode->flags |= pipe_config->base.adjusted_mode.flags;
7686 }
7687
7688 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7689 {
7690 struct drm_device *dev = intel_crtc->base.dev;
7691 struct drm_i915_private *dev_priv = dev->dev_private;
7692 uint32_t pipeconf;
7693
7694 pipeconf = 0;
7695
7696 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7697 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7698 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7699
7700 if (intel_crtc->config->double_wide)
7701 pipeconf |= PIPECONF_DOUBLE_WIDE;
7702
7703 /* only g4x and later have fancy bpc/dither controls */
7704 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7705 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7706 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7707 pipeconf |= PIPECONF_DITHER_EN |
7708 PIPECONF_DITHER_TYPE_SP;
7709
7710 switch (intel_crtc->config->pipe_bpp) {
7711 case 18:
7712 pipeconf |= PIPECONF_6BPC;
7713 break;
7714 case 24:
7715 pipeconf |= PIPECONF_8BPC;
7716 break;
7717 case 30:
7718 pipeconf |= PIPECONF_10BPC;
7719 break;
7720 default:
7721 /* Case prevented by intel_choose_pipe_bpp_dither. */
7722 BUG();
7723 }
7724 }
7725
7726 if (HAS_PIPE_CXSR(dev)) {
7727 if (intel_crtc->lowfreq_avail) {
7728 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7729 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7730 } else {
7731 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7732 }
7733 }
7734
7735 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7736 if (INTEL_INFO(dev)->gen < 4 ||
7737 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7738 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7739 else
7740 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7741 } else
7742 pipeconf |= PIPECONF_PROGRESSIVE;
7743
7744 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7745 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7746
7747 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7748 POSTING_READ(PIPECONF(intel_crtc->pipe));
7749 }
7750
7751 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7752 struct intel_crtc_state *crtc_state)
7753 {
7754 struct drm_device *dev = crtc->base.dev;
7755 struct drm_i915_private *dev_priv = dev->dev_private;
7756 int refclk, num_connectors = 0;
7757 intel_clock_t clock, reduced_clock;
7758 bool ok, has_reduced_clock = false;
7759 bool is_lvds = false, is_dsi = false;
7760 struct intel_encoder *encoder;
7761 const intel_limit_t *limit;
7762 struct drm_atomic_state *state = crtc_state->base.state;
7763 struct drm_connector *connector;
7764 struct drm_connector_state *connector_state;
7765 int i;
7766
7767 memset(&crtc_state->dpll_hw_state, 0,
7768 sizeof(crtc_state->dpll_hw_state));
7769
7770 for_each_connector_in_state(state, connector, connector_state, i) {
7771 if (connector_state->crtc != &crtc->base)
7772 continue;
7773
7774 encoder = to_intel_encoder(connector_state->best_encoder);
7775
7776 switch (encoder->type) {
7777 case INTEL_OUTPUT_LVDS:
7778 is_lvds = true;
7779 break;
7780 case INTEL_OUTPUT_DSI:
7781 is_dsi = true;
7782 break;
7783 default:
7784 break;
7785 }
7786
7787 num_connectors++;
7788 }
7789
7790 if (is_dsi)
7791 return 0;
7792
7793 if (!crtc_state->clock_set) {
7794 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7795
7796 /*
7797 * Returns a set of divisors for the desired target clock with
7798 * the given refclk, or FALSE. The returned values represent
7799 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7800 * 2) / p1 / p2.
7801 */
7802 limit = intel_limit(crtc_state, refclk);
7803 ok = dev_priv->display.find_dpll(limit, crtc_state,
7804 crtc_state->port_clock,
7805 refclk, NULL, &clock);
7806 if (!ok) {
7807 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7808 return -EINVAL;
7809 }
7810
7811 if (is_lvds && dev_priv->lvds_downclock_avail) {
7812 /*
7813 * Ensure we match the reduced clock's P to the target
7814 * clock. If the clocks don't match, we can't switch
7815 * the display clock by using the FP0/FP1. In such case
7816 * we will disable the LVDS downclock feature.
7817 */
7818 has_reduced_clock =
7819 dev_priv->display.find_dpll(limit, crtc_state,
7820 dev_priv->lvds_downclock,
7821 refclk, &clock,
7822 &reduced_clock);
7823 }
7824 /* Compat-code for transition, will disappear. */
7825 crtc_state->dpll.n = clock.n;
7826 crtc_state->dpll.m1 = clock.m1;
7827 crtc_state->dpll.m2 = clock.m2;
7828 crtc_state->dpll.p1 = clock.p1;
7829 crtc_state->dpll.p2 = clock.p2;
7830 }
7831
7832 if (IS_GEN2(dev)) {
7833 i8xx_update_pll(crtc, crtc_state,
7834 has_reduced_clock ? &reduced_clock : NULL,
7835 num_connectors);
7836 } else if (IS_CHERRYVIEW(dev)) {
7837 chv_update_pll(crtc, crtc_state);
7838 } else if (IS_VALLEYVIEW(dev)) {
7839 vlv_update_pll(crtc, crtc_state);
7840 } else {
7841 i9xx_update_pll(crtc, crtc_state,
7842 has_reduced_clock ? &reduced_clock : NULL,
7843 num_connectors);
7844 }
7845
7846 return 0;
7847 }
7848
7849 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7850 struct intel_crtc_state *pipe_config)
7851 {
7852 struct drm_device *dev = crtc->base.dev;
7853 struct drm_i915_private *dev_priv = dev->dev_private;
7854 uint32_t tmp;
7855
7856 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7857 return;
7858
7859 tmp = I915_READ(PFIT_CONTROL);
7860 if (!(tmp & PFIT_ENABLE))
7861 return;
7862
7863 /* Check whether the pfit is attached to our pipe. */
7864 if (INTEL_INFO(dev)->gen < 4) {
7865 if (crtc->pipe != PIPE_B)
7866 return;
7867 } else {
7868 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7869 return;
7870 }
7871
7872 pipe_config->gmch_pfit.control = tmp;
7873 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7874 if (INTEL_INFO(dev)->gen < 5)
7875 pipe_config->gmch_pfit.lvds_border_bits =
7876 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7877 }
7878
7879 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7880 struct intel_crtc_state *pipe_config)
7881 {
7882 struct drm_device *dev = crtc->base.dev;
7883 struct drm_i915_private *dev_priv = dev->dev_private;
7884 int pipe = pipe_config->cpu_transcoder;
7885 intel_clock_t clock;
7886 u32 mdiv;
7887 int refclk = 100000;
7888
7889 /* In case of MIPI DPLL will not even be used */
7890 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7891 return;
7892
7893 mutex_lock(&dev_priv->sb_lock);
7894 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7895 mutex_unlock(&dev_priv->sb_lock);
7896
7897 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7898 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7899 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7900 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7901 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7902
7903 vlv_clock(refclk, &clock);
7904
7905 /* clock.dot is the fast clock */
7906 pipe_config->port_clock = clock.dot / 5;
7907 }
7908
7909 static void
7910 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7911 struct intel_initial_plane_config *plane_config)
7912 {
7913 struct drm_device *dev = crtc->base.dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 u32 val, base, offset;
7916 int pipe = crtc->pipe, plane = crtc->plane;
7917 int fourcc, pixel_format;
7918 unsigned int aligned_height;
7919 struct drm_framebuffer *fb;
7920 struct intel_framebuffer *intel_fb;
7921
7922 val = I915_READ(DSPCNTR(plane));
7923 if (!(val & DISPLAY_PLANE_ENABLE))
7924 return;
7925
7926 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7927 if (!intel_fb) {
7928 DRM_DEBUG_KMS("failed to alloc fb\n");
7929 return;
7930 }
7931
7932 fb = &intel_fb->base;
7933
7934 if (INTEL_INFO(dev)->gen >= 4) {
7935 if (val & DISPPLANE_TILED) {
7936 plane_config->tiling = I915_TILING_X;
7937 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7938 }
7939 }
7940
7941 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7942 fourcc = i9xx_format_to_fourcc(pixel_format);
7943 fb->pixel_format = fourcc;
7944 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7945
7946 if (INTEL_INFO(dev)->gen >= 4) {
7947 if (plane_config->tiling)
7948 offset = I915_READ(DSPTILEOFF(plane));
7949 else
7950 offset = I915_READ(DSPLINOFF(plane));
7951 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7952 } else {
7953 base = I915_READ(DSPADDR(plane));
7954 }
7955 plane_config->base = base;
7956
7957 val = I915_READ(PIPESRC(pipe));
7958 fb->width = ((val >> 16) & 0xfff) + 1;
7959 fb->height = ((val >> 0) & 0xfff) + 1;
7960
7961 val = I915_READ(DSPSTRIDE(pipe));
7962 fb->pitches[0] = val & 0xffffffc0;
7963
7964 aligned_height = intel_fb_align_height(dev, fb->height,
7965 fb->pixel_format,
7966 fb->modifier[0]);
7967
7968 plane_config->size = fb->pitches[0] * aligned_height;
7969
7970 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7971 pipe_name(pipe), plane, fb->width, fb->height,
7972 fb->bits_per_pixel, base, fb->pitches[0],
7973 plane_config->size);
7974
7975 plane_config->fb = intel_fb;
7976 }
7977
7978 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7979 struct intel_crtc_state *pipe_config)
7980 {
7981 struct drm_device *dev = crtc->base.dev;
7982 struct drm_i915_private *dev_priv = dev->dev_private;
7983 int pipe = pipe_config->cpu_transcoder;
7984 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7985 intel_clock_t clock;
7986 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7987 int refclk = 100000;
7988
7989 mutex_lock(&dev_priv->sb_lock);
7990 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7991 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7992 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7993 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7994 mutex_unlock(&dev_priv->sb_lock);
7995
7996 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7997 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7998 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7999 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8000 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8001
8002 chv_clock(refclk, &clock);
8003
8004 /* clock.dot is the fast clock */
8005 pipe_config->port_clock = clock.dot / 5;
8006 }
8007
8008 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8009 struct intel_crtc_state *pipe_config)
8010 {
8011 struct drm_device *dev = crtc->base.dev;
8012 struct drm_i915_private *dev_priv = dev->dev_private;
8013 uint32_t tmp;
8014
8015 if (!intel_display_power_is_enabled(dev_priv,
8016 POWER_DOMAIN_PIPE(crtc->pipe)))
8017 return false;
8018
8019 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8020 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8021
8022 tmp = I915_READ(PIPECONF(crtc->pipe));
8023 if (!(tmp & PIPECONF_ENABLE))
8024 return false;
8025
8026 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8027 switch (tmp & PIPECONF_BPC_MASK) {
8028 case PIPECONF_6BPC:
8029 pipe_config->pipe_bpp = 18;
8030 break;
8031 case PIPECONF_8BPC:
8032 pipe_config->pipe_bpp = 24;
8033 break;
8034 case PIPECONF_10BPC:
8035 pipe_config->pipe_bpp = 30;
8036 break;
8037 default:
8038 break;
8039 }
8040 }
8041
8042 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8043 pipe_config->limited_color_range = true;
8044
8045 if (INTEL_INFO(dev)->gen < 4)
8046 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8047
8048 intel_get_pipe_timings(crtc, pipe_config);
8049
8050 i9xx_get_pfit_config(crtc, pipe_config);
8051
8052 if (INTEL_INFO(dev)->gen >= 4) {
8053 tmp = I915_READ(DPLL_MD(crtc->pipe));
8054 pipe_config->pixel_multiplier =
8055 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8056 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8057 pipe_config->dpll_hw_state.dpll_md = tmp;
8058 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8059 tmp = I915_READ(DPLL(crtc->pipe));
8060 pipe_config->pixel_multiplier =
8061 ((tmp & SDVO_MULTIPLIER_MASK)
8062 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8063 } else {
8064 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8065 * port and will be fixed up in the encoder->get_config
8066 * function. */
8067 pipe_config->pixel_multiplier = 1;
8068 }
8069 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8070 if (!IS_VALLEYVIEW(dev)) {
8071 /*
8072 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8073 * on 830. Filter it out here so that we don't
8074 * report errors due to that.
8075 */
8076 if (IS_I830(dev))
8077 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8078
8079 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8080 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8081 } else {
8082 /* Mask out read-only status bits. */
8083 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8084 DPLL_PORTC_READY_MASK |
8085 DPLL_PORTB_READY_MASK);
8086 }
8087
8088 if (IS_CHERRYVIEW(dev))
8089 chv_crtc_clock_get(crtc, pipe_config);
8090 else if (IS_VALLEYVIEW(dev))
8091 vlv_crtc_clock_get(crtc, pipe_config);
8092 else
8093 i9xx_crtc_clock_get(crtc, pipe_config);
8094
8095 return true;
8096 }
8097
8098 static void ironlake_init_pch_refclk(struct drm_device *dev)
8099 {
8100 struct drm_i915_private *dev_priv = dev->dev_private;
8101 struct intel_encoder *encoder;
8102 u32 val, final;
8103 bool has_lvds = false;
8104 bool has_cpu_edp = false;
8105 bool has_panel = false;
8106 bool has_ck505 = false;
8107 bool can_ssc = false;
8108
8109 /* We need to take the global config into account */
8110 for_each_intel_encoder(dev, encoder) {
8111 switch (encoder->type) {
8112 case INTEL_OUTPUT_LVDS:
8113 has_panel = true;
8114 has_lvds = true;
8115 break;
8116 case INTEL_OUTPUT_EDP:
8117 has_panel = true;
8118 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8119 has_cpu_edp = true;
8120 break;
8121 default:
8122 break;
8123 }
8124 }
8125
8126 if (HAS_PCH_IBX(dev)) {
8127 has_ck505 = dev_priv->vbt.display_clock_mode;
8128 can_ssc = has_ck505;
8129 } else {
8130 has_ck505 = false;
8131 can_ssc = true;
8132 }
8133
8134 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8135 has_panel, has_lvds, has_ck505);
8136
8137 /* Ironlake: try to setup display ref clock before DPLL
8138 * enabling. This is only under driver's control after
8139 * PCH B stepping, previous chipset stepping should be
8140 * ignoring this setting.
8141 */
8142 val = I915_READ(PCH_DREF_CONTROL);
8143
8144 /* As we must carefully and slowly disable/enable each source in turn,
8145 * compute the final state we want first and check if we need to
8146 * make any changes at all.
8147 */
8148 final = val;
8149 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8150 if (has_ck505)
8151 final |= DREF_NONSPREAD_CK505_ENABLE;
8152 else
8153 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8154
8155 final &= ~DREF_SSC_SOURCE_MASK;
8156 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8157 final &= ~DREF_SSC1_ENABLE;
8158
8159 if (has_panel) {
8160 final |= DREF_SSC_SOURCE_ENABLE;
8161
8162 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8163 final |= DREF_SSC1_ENABLE;
8164
8165 if (has_cpu_edp) {
8166 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8167 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8168 else
8169 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8170 } else
8171 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8172 } else {
8173 final |= DREF_SSC_SOURCE_DISABLE;
8174 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8175 }
8176
8177 if (final == val)
8178 return;
8179
8180 /* Always enable nonspread source */
8181 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8182
8183 if (has_ck505)
8184 val |= DREF_NONSPREAD_CK505_ENABLE;
8185 else
8186 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8187
8188 if (has_panel) {
8189 val &= ~DREF_SSC_SOURCE_MASK;
8190 val |= DREF_SSC_SOURCE_ENABLE;
8191
8192 /* SSC must be turned on before enabling the CPU output */
8193 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8194 DRM_DEBUG_KMS("Using SSC on panel\n");
8195 val |= DREF_SSC1_ENABLE;
8196 } else
8197 val &= ~DREF_SSC1_ENABLE;
8198
8199 /* Get SSC going before enabling the outputs */
8200 I915_WRITE(PCH_DREF_CONTROL, val);
8201 POSTING_READ(PCH_DREF_CONTROL);
8202 udelay(200);
8203
8204 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8205
8206 /* Enable CPU source on CPU attached eDP */
8207 if (has_cpu_edp) {
8208 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8209 DRM_DEBUG_KMS("Using SSC on eDP\n");
8210 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8211 } else
8212 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8213 } else
8214 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8215
8216 I915_WRITE(PCH_DREF_CONTROL, val);
8217 POSTING_READ(PCH_DREF_CONTROL);
8218 udelay(200);
8219 } else {
8220 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8221
8222 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8223
8224 /* Turn off CPU output */
8225 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8226
8227 I915_WRITE(PCH_DREF_CONTROL, val);
8228 POSTING_READ(PCH_DREF_CONTROL);
8229 udelay(200);
8230
8231 /* Turn off the SSC source */
8232 val &= ~DREF_SSC_SOURCE_MASK;
8233 val |= DREF_SSC_SOURCE_DISABLE;
8234
8235 /* Turn off SSC1 */
8236 val &= ~DREF_SSC1_ENABLE;
8237
8238 I915_WRITE(PCH_DREF_CONTROL, val);
8239 POSTING_READ(PCH_DREF_CONTROL);
8240 udelay(200);
8241 }
8242
8243 BUG_ON(val != final);
8244 }
8245
8246 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8247 {
8248 uint32_t tmp;
8249
8250 tmp = I915_READ(SOUTH_CHICKEN2);
8251 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8252 I915_WRITE(SOUTH_CHICKEN2, tmp);
8253
8254 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8255 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8256 DRM_ERROR("FDI mPHY reset assert timeout\n");
8257
8258 tmp = I915_READ(SOUTH_CHICKEN2);
8259 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8260 I915_WRITE(SOUTH_CHICKEN2, tmp);
8261
8262 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8263 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8264 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8265 }
8266
8267 /* WaMPhyProgramming:hsw */
8268 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8269 {
8270 uint32_t tmp;
8271
8272 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8273 tmp &= ~(0xFF << 24);
8274 tmp |= (0x12 << 24);
8275 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8276
8277 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8278 tmp |= (1 << 11);
8279 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8280
8281 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8282 tmp |= (1 << 11);
8283 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8284
8285 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8286 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8287 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8288
8289 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8290 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8291 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8292
8293 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8294 tmp &= ~(7 << 13);
8295 tmp |= (5 << 13);
8296 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8297
8298 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8299 tmp &= ~(7 << 13);
8300 tmp |= (5 << 13);
8301 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8302
8303 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8304 tmp &= ~0xFF;
8305 tmp |= 0x1C;
8306 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8307
8308 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8309 tmp &= ~0xFF;
8310 tmp |= 0x1C;
8311 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8312
8313 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8314 tmp &= ~(0xFF << 16);
8315 tmp |= (0x1C << 16);
8316 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8319 tmp &= ~(0xFF << 16);
8320 tmp |= (0x1C << 16);
8321 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8322
8323 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8324 tmp |= (1 << 27);
8325 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8328 tmp |= (1 << 27);
8329 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8330
8331 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8332 tmp &= ~(0xF << 28);
8333 tmp |= (4 << 28);
8334 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8335
8336 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8337 tmp &= ~(0xF << 28);
8338 tmp |= (4 << 28);
8339 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8340 }
8341
8342 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8343 * Programming" based on the parameters passed:
8344 * - Sequence to enable CLKOUT_DP
8345 * - Sequence to enable CLKOUT_DP without spread
8346 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8347 */
8348 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8349 bool with_fdi)
8350 {
8351 struct drm_i915_private *dev_priv = dev->dev_private;
8352 uint32_t reg, tmp;
8353
8354 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8355 with_spread = true;
8356 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8357 with_fdi, "LP PCH doesn't have FDI\n"))
8358 with_fdi = false;
8359
8360 mutex_lock(&dev_priv->sb_lock);
8361
8362 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8363 tmp &= ~SBI_SSCCTL_DISABLE;
8364 tmp |= SBI_SSCCTL_PATHALT;
8365 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8366
8367 udelay(24);
8368
8369 if (with_spread) {
8370 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8371 tmp &= ~SBI_SSCCTL_PATHALT;
8372 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8373
8374 if (with_fdi) {
8375 lpt_reset_fdi_mphy(dev_priv);
8376 lpt_program_fdi_mphy(dev_priv);
8377 }
8378 }
8379
8380 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8381 SBI_GEN0 : SBI_DBUFF0;
8382 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8383 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8384 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8385
8386 mutex_unlock(&dev_priv->sb_lock);
8387 }
8388
8389 /* Sequence to disable CLKOUT_DP */
8390 static void lpt_disable_clkout_dp(struct drm_device *dev)
8391 {
8392 struct drm_i915_private *dev_priv = dev->dev_private;
8393 uint32_t reg, tmp;
8394
8395 mutex_lock(&dev_priv->sb_lock);
8396
8397 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8398 SBI_GEN0 : SBI_DBUFF0;
8399 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8400 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8401 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8402
8403 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8404 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8405 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8406 tmp |= SBI_SSCCTL_PATHALT;
8407 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8408 udelay(32);
8409 }
8410 tmp |= SBI_SSCCTL_DISABLE;
8411 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8412 }
8413
8414 mutex_unlock(&dev_priv->sb_lock);
8415 }
8416
8417 static void lpt_init_pch_refclk(struct drm_device *dev)
8418 {
8419 struct intel_encoder *encoder;
8420 bool has_vga = false;
8421
8422 for_each_intel_encoder(dev, encoder) {
8423 switch (encoder->type) {
8424 case INTEL_OUTPUT_ANALOG:
8425 has_vga = true;
8426 break;
8427 default:
8428 break;
8429 }
8430 }
8431
8432 if (has_vga)
8433 lpt_enable_clkout_dp(dev, true, true);
8434 else
8435 lpt_disable_clkout_dp(dev);
8436 }
8437
8438 /*
8439 * Initialize reference clocks when the driver loads
8440 */
8441 void intel_init_pch_refclk(struct drm_device *dev)
8442 {
8443 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8444 ironlake_init_pch_refclk(dev);
8445 else if (HAS_PCH_LPT(dev))
8446 lpt_init_pch_refclk(dev);
8447 }
8448
8449 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8450 {
8451 struct drm_device *dev = crtc_state->base.crtc->dev;
8452 struct drm_i915_private *dev_priv = dev->dev_private;
8453 struct drm_atomic_state *state = crtc_state->base.state;
8454 struct drm_connector *connector;
8455 struct drm_connector_state *connector_state;
8456 struct intel_encoder *encoder;
8457 int num_connectors = 0, i;
8458 bool is_lvds = false;
8459
8460 for_each_connector_in_state(state, connector, connector_state, i) {
8461 if (connector_state->crtc != crtc_state->base.crtc)
8462 continue;
8463
8464 encoder = to_intel_encoder(connector_state->best_encoder);
8465
8466 switch (encoder->type) {
8467 case INTEL_OUTPUT_LVDS:
8468 is_lvds = true;
8469 break;
8470 default:
8471 break;
8472 }
8473 num_connectors++;
8474 }
8475
8476 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8477 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8478 dev_priv->vbt.lvds_ssc_freq);
8479 return dev_priv->vbt.lvds_ssc_freq;
8480 }
8481
8482 return 120000;
8483 }
8484
8485 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8486 {
8487 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8489 int pipe = intel_crtc->pipe;
8490 uint32_t val;
8491
8492 val = 0;
8493
8494 switch (intel_crtc->config->pipe_bpp) {
8495 case 18:
8496 val |= PIPECONF_6BPC;
8497 break;
8498 case 24:
8499 val |= PIPECONF_8BPC;
8500 break;
8501 case 30:
8502 val |= PIPECONF_10BPC;
8503 break;
8504 case 36:
8505 val |= PIPECONF_12BPC;
8506 break;
8507 default:
8508 /* Case prevented by intel_choose_pipe_bpp_dither. */
8509 BUG();
8510 }
8511
8512 if (intel_crtc->config->dither)
8513 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8514
8515 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8516 val |= PIPECONF_INTERLACED_ILK;
8517 else
8518 val |= PIPECONF_PROGRESSIVE;
8519
8520 if (intel_crtc->config->limited_color_range)
8521 val |= PIPECONF_COLOR_RANGE_SELECT;
8522
8523 I915_WRITE(PIPECONF(pipe), val);
8524 POSTING_READ(PIPECONF(pipe));
8525 }
8526
8527 /*
8528 * Set up the pipe CSC unit.
8529 *
8530 * Currently only full range RGB to limited range RGB conversion
8531 * is supported, but eventually this should handle various
8532 * RGB<->YCbCr scenarios as well.
8533 */
8534 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8535 {
8536 struct drm_device *dev = crtc->dev;
8537 struct drm_i915_private *dev_priv = dev->dev_private;
8538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8539 int pipe = intel_crtc->pipe;
8540 uint16_t coeff = 0x7800; /* 1.0 */
8541
8542 /*
8543 * TODO: Check what kind of values actually come out of the pipe
8544 * with these coeff/postoff values and adjust to get the best
8545 * accuracy. Perhaps we even need to take the bpc value into
8546 * consideration.
8547 */
8548
8549 if (intel_crtc->config->limited_color_range)
8550 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8551
8552 /*
8553 * GY/GU and RY/RU should be the other way around according
8554 * to BSpec, but reality doesn't agree. Just set them up in
8555 * a way that results in the correct picture.
8556 */
8557 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8558 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8559
8560 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8561 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8562
8563 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8564 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8565
8566 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8567 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8568 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8569
8570 if (INTEL_INFO(dev)->gen > 6) {
8571 uint16_t postoff = 0;
8572
8573 if (intel_crtc->config->limited_color_range)
8574 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8575
8576 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8577 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8578 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8579
8580 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8581 } else {
8582 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8583
8584 if (intel_crtc->config->limited_color_range)
8585 mode |= CSC_BLACK_SCREEN_OFFSET;
8586
8587 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8588 }
8589 }
8590
8591 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8592 {
8593 struct drm_device *dev = crtc->dev;
8594 struct drm_i915_private *dev_priv = dev->dev_private;
8595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8596 enum pipe pipe = intel_crtc->pipe;
8597 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8598 uint32_t val;
8599
8600 val = 0;
8601
8602 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8603 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8604
8605 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8606 val |= PIPECONF_INTERLACED_ILK;
8607 else
8608 val |= PIPECONF_PROGRESSIVE;
8609
8610 I915_WRITE(PIPECONF(cpu_transcoder), val);
8611 POSTING_READ(PIPECONF(cpu_transcoder));
8612
8613 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8614 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8615
8616 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8617 val = 0;
8618
8619 switch (intel_crtc->config->pipe_bpp) {
8620 case 18:
8621 val |= PIPEMISC_DITHER_6_BPC;
8622 break;
8623 case 24:
8624 val |= PIPEMISC_DITHER_8_BPC;
8625 break;
8626 case 30:
8627 val |= PIPEMISC_DITHER_10_BPC;
8628 break;
8629 case 36:
8630 val |= PIPEMISC_DITHER_12_BPC;
8631 break;
8632 default:
8633 /* Case prevented by pipe_config_set_bpp. */
8634 BUG();
8635 }
8636
8637 if (intel_crtc->config->dither)
8638 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8639
8640 I915_WRITE(PIPEMISC(pipe), val);
8641 }
8642 }
8643
8644 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8645 struct intel_crtc_state *crtc_state,
8646 intel_clock_t *clock,
8647 bool *has_reduced_clock,
8648 intel_clock_t *reduced_clock)
8649 {
8650 struct drm_device *dev = crtc->dev;
8651 struct drm_i915_private *dev_priv = dev->dev_private;
8652 int refclk;
8653 const intel_limit_t *limit;
8654 bool ret, is_lvds = false;
8655
8656 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8657
8658 refclk = ironlake_get_refclk(crtc_state);
8659
8660 /*
8661 * Returns a set of divisors for the desired target clock with the given
8662 * refclk, or FALSE. The returned values represent the clock equation:
8663 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8664 */
8665 limit = intel_limit(crtc_state, refclk);
8666 ret = dev_priv->display.find_dpll(limit, crtc_state,
8667 crtc_state->port_clock,
8668 refclk, NULL, clock);
8669 if (!ret)
8670 return false;
8671
8672 if (is_lvds && dev_priv->lvds_downclock_avail) {
8673 /*
8674 * Ensure we match the reduced clock's P to the target clock.
8675 * If the clocks don't match, we can't switch the display clock
8676 * by using the FP0/FP1. In such case we will disable the LVDS
8677 * downclock feature.
8678 */
8679 *has_reduced_clock =
8680 dev_priv->display.find_dpll(limit, crtc_state,
8681 dev_priv->lvds_downclock,
8682 refclk, clock,
8683 reduced_clock);
8684 }
8685
8686 return true;
8687 }
8688
8689 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8690 {
8691 /*
8692 * Account for spread spectrum to avoid
8693 * oversubscribing the link. Max center spread
8694 * is 2.5%; use 5% for safety's sake.
8695 */
8696 u32 bps = target_clock * bpp * 21 / 20;
8697 return DIV_ROUND_UP(bps, link_bw * 8);
8698 }
8699
8700 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8701 {
8702 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8703 }
8704
8705 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8706 struct intel_crtc_state *crtc_state,
8707 u32 *fp,
8708 intel_clock_t *reduced_clock, u32 *fp2)
8709 {
8710 struct drm_crtc *crtc = &intel_crtc->base;
8711 struct drm_device *dev = crtc->dev;
8712 struct drm_i915_private *dev_priv = dev->dev_private;
8713 struct drm_atomic_state *state = crtc_state->base.state;
8714 struct drm_connector *connector;
8715 struct drm_connector_state *connector_state;
8716 struct intel_encoder *encoder;
8717 uint32_t dpll;
8718 int factor, num_connectors = 0, i;
8719 bool is_lvds = false, is_sdvo = false;
8720
8721 for_each_connector_in_state(state, connector, connector_state, i) {
8722 if (connector_state->crtc != crtc_state->base.crtc)
8723 continue;
8724
8725 encoder = to_intel_encoder(connector_state->best_encoder);
8726
8727 switch (encoder->type) {
8728 case INTEL_OUTPUT_LVDS:
8729 is_lvds = true;
8730 break;
8731 case INTEL_OUTPUT_SDVO:
8732 case INTEL_OUTPUT_HDMI:
8733 is_sdvo = true;
8734 break;
8735 default:
8736 break;
8737 }
8738
8739 num_connectors++;
8740 }
8741
8742 /* Enable autotuning of the PLL clock (if permissible) */
8743 factor = 21;
8744 if (is_lvds) {
8745 if ((intel_panel_use_ssc(dev_priv) &&
8746 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8747 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8748 factor = 25;
8749 } else if (crtc_state->sdvo_tv_clock)
8750 factor = 20;
8751
8752 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8753 *fp |= FP_CB_TUNE;
8754
8755 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8756 *fp2 |= FP_CB_TUNE;
8757
8758 dpll = 0;
8759
8760 if (is_lvds)
8761 dpll |= DPLLB_MODE_LVDS;
8762 else
8763 dpll |= DPLLB_MODE_DAC_SERIAL;
8764
8765 dpll |= (crtc_state->pixel_multiplier - 1)
8766 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8767
8768 if (is_sdvo)
8769 dpll |= DPLL_SDVO_HIGH_SPEED;
8770 if (crtc_state->has_dp_encoder)
8771 dpll |= DPLL_SDVO_HIGH_SPEED;
8772
8773 /* compute bitmask from p1 value */
8774 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8775 /* also FPA1 */
8776 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8777
8778 switch (crtc_state->dpll.p2) {
8779 case 5:
8780 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8781 break;
8782 case 7:
8783 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8784 break;
8785 case 10:
8786 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8787 break;
8788 case 14:
8789 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8790 break;
8791 }
8792
8793 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8794 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8795 else
8796 dpll |= PLL_REF_INPUT_DREFCLK;
8797
8798 return dpll | DPLL_VCO_ENABLE;
8799 }
8800
8801 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8802 struct intel_crtc_state *crtc_state)
8803 {
8804 struct drm_device *dev = crtc->base.dev;
8805 intel_clock_t clock, reduced_clock;
8806 u32 dpll = 0, fp = 0, fp2 = 0;
8807 bool ok, has_reduced_clock = false;
8808 bool is_lvds = false;
8809 struct intel_shared_dpll *pll;
8810
8811 memset(&crtc_state->dpll_hw_state, 0,
8812 sizeof(crtc_state->dpll_hw_state));
8813
8814 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8815
8816 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8817 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8818
8819 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8820 &has_reduced_clock, &reduced_clock);
8821 if (!ok && !crtc_state->clock_set) {
8822 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8823 return -EINVAL;
8824 }
8825 /* Compat-code for transition, will disappear. */
8826 if (!crtc_state->clock_set) {
8827 crtc_state->dpll.n = clock.n;
8828 crtc_state->dpll.m1 = clock.m1;
8829 crtc_state->dpll.m2 = clock.m2;
8830 crtc_state->dpll.p1 = clock.p1;
8831 crtc_state->dpll.p2 = clock.p2;
8832 }
8833
8834 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8835 if (crtc_state->has_pch_encoder) {
8836 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8837 if (has_reduced_clock)
8838 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8839
8840 dpll = ironlake_compute_dpll(crtc, crtc_state,
8841 &fp, &reduced_clock,
8842 has_reduced_clock ? &fp2 : NULL);
8843
8844 crtc_state->dpll_hw_state.dpll = dpll;
8845 crtc_state->dpll_hw_state.fp0 = fp;
8846 if (has_reduced_clock)
8847 crtc_state->dpll_hw_state.fp1 = fp2;
8848 else
8849 crtc_state->dpll_hw_state.fp1 = fp;
8850
8851 pll = intel_get_shared_dpll(crtc, crtc_state);
8852 if (pll == NULL) {
8853 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8854 pipe_name(crtc->pipe));
8855 return -EINVAL;
8856 }
8857 }
8858
8859 if (is_lvds && has_reduced_clock)
8860 crtc->lowfreq_avail = true;
8861 else
8862 crtc->lowfreq_avail = false;
8863
8864 return 0;
8865 }
8866
8867 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8868 struct intel_link_m_n *m_n)
8869 {
8870 struct drm_device *dev = crtc->base.dev;
8871 struct drm_i915_private *dev_priv = dev->dev_private;
8872 enum pipe pipe = crtc->pipe;
8873
8874 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8875 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8876 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8877 & ~TU_SIZE_MASK;
8878 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8879 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8880 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8881 }
8882
8883 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8884 enum transcoder transcoder,
8885 struct intel_link_m_n *m_n,
8886 struct intel_link_m_n *m2_n2)
8887 {
8888 struct drm_device *dev = crtc->base.dev;
8889 struct drm_i915_private *dev_priv = dev->dev_private;
8890 enum pipe pipe = crtc->pipe;
8891
8892 if (INTEL_INFO(dev)->gen >= 5) {
8893 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8894 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8895 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8896 & ~TU_SIZE_MASK;
8897 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8898 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8899 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8900 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8901 * gen < 8) and if DRRS is supported (to make sure the
8902 * registers are not unnecessarily read).
8903 */
8904 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8905 crtc->config->has_drrs) {
8906 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8907 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8908 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8909 & ~TU_SIZE_MASK;
8910 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8911 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8912 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8913 }
8914 } else {
8915 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8916 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8917 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8918 & ~TU_SIZE_MASK;
8919 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8920 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8921 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8922 }
8923 }
8924
8925 void intel_dp_get_m_n(struct intel_crtc *crtc,
8926 struct intel_crtc_state *pipe_config)
8927 {
8928 if (pipe_config->has_pch_encoder)
8929 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8930 else
8931 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8932 &pipe_config->dp_m_n,
8933 &pipe_config->dp_m2_n2);
8934 }
8935
8936 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8937 struct intel_crtc_state *pipe_config)
8938 {
8939 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8940 &pipe_config->fdi_m_n, NULL);
8941 }
8942
8943 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8944 struct intel_crtc_state *pipe_config)
8945 {
8946 struct drm_device *dev = crtc->base.dev;
8947 struct drm_i915_private *dev_priv = dev->dev_private;
8948 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8949 uint32_t ps_ctrl = 0;
8950 int id = -1;
8951 int i;
8952
8953 /* find scaler attached to this pipe */
8954 for (i = 0; i < crtc->num_scalers; i++) {
8955 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8956 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8957 id = i;
8958 pipe_config->pch_pfit.enabled = true;
8959 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8960 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8961 break;
8962 }
8963 }
8964
8965 scaler_state->scaler_id = id;
8966 if (id >= 0) {
8967 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8968 } else {
8969 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8970 }
8971 }
8972
8973 static void
8974 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8975 struct intel_initial_plane_config *plane_config)
8976 {
8977 struct drm_device *dev = crtc->base.dev;
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 u32 val, base, offset, stride_mult, tiling;
8980 int pipe = crtc->pipe;
8981 int fourcc, pixel_format;
8982 unsigned int aligned_height;
8983 struct drm_framebuffer *fb;
8984 struct intel_framebuffer *intel_fb;
8985
8986 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8987 if (!intel_fb) {
8988 DRM_DEBUG_KMS("failed to alloc fb\n");
8989 return;
8990 }
8991
8992 fb = &intel_fb->base;
8993
8994 val = I915_READ(PLANE_CTL(pipe, 0));
8995 if (!(val & PLANE_CTL_ENABLE))
8996 goto error;
8997
8998 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8999 fourcc = skl_format_to_fourcc(pixel_format,
9000 val & PLANE_CTL_ORDER_RGBX,
9001 val & PLANE_CTL_ALPHA_MASK);
9002 fb->pixel_format = fourcc;
9003 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9004
9005 tiling = val & PLANE_CTL_TILED_MASK;
9006 switch (tiling) {
9007 case PLANE_CTL_TILED_LINEAR:
9008 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9009 break;
9010 case PLANE_CTL_TILED_X:
9011 plane_config->tiling = I915_TILING_X;
9012 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9013 break;
9014 case PLANE_CTL_TILED_Y:
9015 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9016 break;
9017 case PLANE_CTL_TILED_YF:
9018 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9019 break;
9020 default:
9021 MISSING_CASE(tiling);
9022 goto error;
9023 }
9024
9025 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9026 plane_config->base = base;
9027
9028 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9029
9030 val = I915_READ(PLANE_SIZE(pipe, 0));
9031 fb->height = ((val >> 16) & 0xfff) + 1;
9032 fb->width = ((val >> 0) & 0x1fff) + 1;
9033
9034 val = I915_READ(PLANE_STRIDE(pipe, 0));
9035 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9036 fb->pixel_format);
9037 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9038
9039 aligned_height = intel_fb_align_height(dev, fb->height,
9040 fb->pixel_format,
9041 fb->modifier[0]);
9042
9043 plane_config->size = fb->pitches[0] * aligned_height;
9044
9045 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9046 pipe_name(pipe), fb->width, fb->height,
9047 fb->bits_per_pixel, base, fb->pitches[0],
9048 plane_config->size);
9049
9050 plane_config->fb = intel_fb;
9051 return;
9052
9053 error:
9054 kfree(fb);
9055 }
9056
9057 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9058 struct intel_crtc_state *pipe_config)
9059 {
9060 struct drm_device *dev = crtc->base.dev;
9061 struct drm_i915_private *dev_priv = dev->dev_private;
9062 uint32_t tmp;
9063
9064 tmp = I915_READ(PF_CTL(crtc->pipe));
9065
9066 if (tmp & PF_ENABLE) {
9067 pipe_config->pch_pfit.enabled = true;
9068 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9069 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9070
9071 /* We currently do not free assignements of panel fitters on
9072 * ivb/hsw (since we don't use the higher upscaling modes which
9073 * differentiates them) so just WARN about this case for now. */
9074 if (IS_GEN7(dev)) {
9075 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9076 PF_PIPE_SEL_IVB(crtc->pipe));
9077 }
9078 }
9079 }
9080
9081 static void
9082 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9083 struct intel_initial_plane_config *plane_config)
9084 {
9085 struct drm_device *dev = crtc->base.dev;
9086 struct drm_i915_private *dev_priv = dev->dev_private;
9087 u32 val, base, offset;
9088 int pipe = crtc->pipe;
9089 int fourcc, pixel_format;
9090 unsigned int aligned_height;
9091 struct drm_framebuffer *fb;
9092 struct intel_framebuffer *intel_fb;
9093
9094 val = I915_READ(DSPCNTR(pipe));
9095 if (!(val & DISPLAY_PLANE_ENABLE))
9096 return;
9097
9098 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9099 if (!intel_fb) {
9100 DRM_DEBUG_KMS("failed to alloc fb\n");
9101 return;
9102 }
9103
9104 fb = &intel_fb->base;
9105
9106 if (INTEL_INFO(dev)->gen >= 4) {
9107 if (val & DISPPLANE_TILED) {
9108 plane_config->tiling = I915_TILING_X;
9109 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9110 }
9111 }
9112
9113 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9114 fourcc = i9xx_format_to_fourcc(pixel_format);
9115 fb->pixel_format = fourcc;
9116 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9117
9118 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9119 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9120 offset = I915_READ(DSPOFFSET(pipe));
9121 } else {
9122 if (plane_config->tiling)
9123 offset = I915_READ(DSPTILEOFF(pipe));
9124 else
9125 offset = I915_READ(DSPLINOFF(pipe));
9126 }
9127 plane_config->base = base;
9128
9129 val = I915_READ(PIPESRC(pipe));
9130 fb->width = ((val >> 16) & 0xfff) + 1;
9131 fb->height = ((val >> 0) & 0xfff) + 1;
9132
9133 val = I915_READ(DSPSTRIDE(pipe));
9134 fb->pitches[0] = val & 0xffffffc0;
9135
9136 aligned_height = intel_fb_align_height(dev, fb->height,
9137 fb->pixel_format,
9138 fb->modifier[0]);
9139
9140 plane_config->size = fb->pitches[0] * aligned_height;
9141
9142 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9143 pipe_name(pipe), fb->width, fb->height,
9144 fb->bits_per_pixel, base, fb->pitches[0],
9145 plane_config->size);
9146
9147 plane_config->fb = intel_fb;
9148 }
9149
9150 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9151 struct intel_crtc_state *pipe_config)
9152 {
9153 struct drm_device *dev = crtc->base.dev;
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9155 uint32_t tmp;
9156
9157 if (!intel_display_power_is_enabled(dev_priv,
9158 POWER_DOMAIN_PIPE(crtc->pipe)))
9159 return false;
9160
9161 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9162 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9163
9164 tmp = I915_READ(PIPECONF(crtc->pipe));
9165 if (!(tmp & PIPECONF_ENABLE))
9166 return false;
9167
9168 switch (tmp & PIPECONF_BPC_MASK) {
9169 case PIPECONF_6BPC:
9170 pipe_config->pipe_bpp = 18;
9171 break;
9172 case PIPECONF_8BPC:
9173 pipe_config->pipe_bpp = 24;
9174 break;
9175 case PIPECONF_10BPC:
9176 pipe_config->pipe_bpp = 30;
9177 break;
9178 case PIPECONF_12BPC:
9179 pipe_config->pipe_bpp = 36;
9180 break;
9181 default:
9182 break;
9183 }
9184
9185 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9186 pipe_config->limited_color_range = true;
9187
9188 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9189 struct intel_shared_dpll *pll;
9190
9191 pipe_config->has_pch_encoder = true;
9192
9193 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9194 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9195 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9196
9197 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9198
9199 if (HAS_PCH_IBX(dev_priv->dev)) {
9200 pipe_config->shared_dpll =
9201 (enum intel_dpll_id) crtc->pipe;
9202 } else {
9203 tmp = I915_READ(PCH_DPLL_SEL);
9204 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9205 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9206 else
9207 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9208 }
9209
9210 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9211
9212 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9213 &pipe_config->dpll_hw_state));
9214
9215 tmp = pipe_config->dpll_hw_state.dpll;
9216 pipe_config->pixel_multiplier =
9217 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9218 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9219
9220 ironlake_pch_clock_get(crtc, pipe_config);
9221 } else {
9222 pipe_config->pixel_multiplier = 1;
9223 }
9224
9225 intel_get_pipe_timings(crtc, pipe_config);
9226
9227 ironlake_get_pfit_config(crtc, pipe_config);
9228
9229 return true;
9230 }
9231
9232 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9233 {
9234 struct drm_device *dev = dev_priv->dev;
9235 struct intel_crtc *crtc;
9236
9237 for_each_intel_crtc(dev, crtc)
9238 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9239 pipe_name(crtc->pipe));
9240
9241 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9242 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9243 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9244 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9245 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9246 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9247 "CPU PWM1 enabled\n");
9248 if (IS_HASWELL(dev))
9249 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9250 "CPU PWM2 enabled\n");
9251 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9252 "PCH PWM1 enabled\n");
9253 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9254 "Utility pin enabled\n");
9255 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9256
9257 /*
9258 * In theory we can still leave IRQs enabled, as long as only the HPD
9259 * interrupts remain enabled. We used to check for that, but since it's
9260 * gen-specific and since we only disable LCPLL after we fully disable
9261 * the interrupts, the check below should be enough.
9262 */
9263 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9264 }
9265
9266 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9267 {
9268 struct drm_device *dev = dev_priv->dev;
9269
9270 if (IS_HASWELL(dev))
9271 return I915_READ(D_COMP_HSW);
9272 else
9273 return I915_READ(D_COMP_BDW);
9274 }
9275
9276 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9277 {
9278 struct drm_device *dev = dev_priv->dev;
9279
9280 if (IS_HASWELL(dev)) {
9281 mutex_lock(&dev_priv->rps.hw_lock);
9282 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9283 val))
9284 DRM_ERROR("Failed to write to D_COMP\n");
9285 mutex_unlock(&dev_priv->rps.hw_lock);
9286 } else {
9287 I915_WRITE(D_COMP_BDW, val);
9288 POSTING_READ(D_COMP_BDW);
9289 }
9290 }
9291
9292 /*
9293 * This function implements pieces of two sequences from BSpec:
9294 * - Sequence for display software to disable LCPLL
9295 * - Sequence for display software to allow package C8+
9296 * The steps implemented here are just the steps that actually touch the LCPLL
9297 * register. Callers should take care of disabling all the display engine
9298 * functions, doing the mode unset, fixing interrupts, etc.
9299 */
9300 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9301 bool switch_to_fclk, bool allow_power_down)
9302 {
9303 uint32_t val;
9304
9305 assert_can_disable_lcpll(dev_priv);
9306
9307 val = I915_READ(LCPLL_CTL);
9308
9309 if (switch_to_fclk) {
9310 val |= LCPLL_CD_SOURCE_FCLK;
9311 I915_WRITE(LCPLL_CTL, val);
9312
9313 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9314 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9315 DRM_ERROR("Switching to FCLK failed\n");
9316
9317 val = I915_READ(LCPLL_CTL);
9318 }
9319
9320 val |= LCPLL_PLL_DISABLE;
9321 I915_WRITE(LCPLL_CTL, val);
9322 POSTING_READ(LCPLL_CTL);
9323
9324 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9325 DRM_ERROR("LCPLL still locked\n");
9326
9327 val = hsw_read_dcomp(dev_priv);
9328 val |= D_COMP_COMP_DISABLE;
9329 hsw_write_dcomp(dev_priv, val);
9330 ndelay(100);
9331
9332 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9333 1))
9334 DRM_ERROR("D_COMP RCOMP still in progress\n");
9335
9336 if (allow_power_down) {
9337 val = I915_READ(LCPLL_CTL);
9338 val |= LCPLL_POWER_DOWN_ALLOW;
9339 I915_WRITE(LCPLL_CTL, val);
9340 POSTING_READ(LCPLL_CTL);
9341 }
9342 }
9343
9344 /*
9345 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9346 * source.
9347 */
9348 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9349 {
9350 uint32_t val;
9351
9352 val = I915_READ(LCPLL_CTL);
9353
9354 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9355 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9356 return;
9357
9358 /*
9359 * Make sure we're not on PC8 state before disabling PC8, otherwise
9360 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9361 */
9362 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9363
9364 if (val & LCPLL_POWER_DOWN_ALLOW) {
9365 val &= ~LCPLL_POWER_DOWN_ALLOW;
9366 I915_WRITE(LCPLL_CTL, val);
9367 POSTING_READ(LCPLL_CTL);
9368 }
9369
9370 val = hsw_read_dcomp(dev_priv);
9371 val |= D_COMP_COMP_FORCE;
9372 val &= ~D_COMP_COMP_DISABLE;
9373 hsw_write_dcomp(dev_priv, val);
9374
9375 val = I915_READ(LCPLL_CTL);
9376 val &= ~LCPLL_PLL_DISABLE;
9377 I915_WRITE(LCPLL_CTL, val);
9378
9379 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9380 DRM_ERROR("LCPLL not locked yet\n");
9381
9382 if (val & LCPLL_CD_SOURCE_FCLK) {
9383 val = I915_READ(LCPLL_CTL);
9384 val &= ~LCPLL_CD_SOURCE_FCLK;
9385 I915_WRITE(LCPLL_CTL, val);
9386
9387 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9388 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9389 DRM_ERROR("Switching back to LCPLL failed\n");
9390 }
9391
9392 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9393 intel_update_cdclk(dev_priv->dev);
9394 }
9395
9396 /*
9397 * Package states C8 and deeper are really deep PC states that can only be
9398 * reached when all the devices on the system allow it, so even if the graphics
9399 * device allows PC8+, it doesn't mean the system will actually get to these
9400 * states. Our driver only allows PC8+ when going into runtime PM.
9401 *
9402 * The requirements for PC8+ are that all the outputs are disabled, the power
9403 * well is disabled and most interrupts are disabled, and these are also
9404 * requirements for runtime PM. When these conditions are met, we manually do
9405 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9406 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9407 * hang the machine.
9408 *
9409 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9410 * the state of some registers, so when we come back from PC8+ we need to
9411 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9412 * need to take care of the registers kept by RC6. Notice that this happens even
9413 * if we don't put the device in PCI D3 state (which is what currently happens
9414 * because of the runtime PM support).
9415 *
9416 * For more, read "Display Sequences for Package C8" on the hardware
9417 * documentation.
9418 */
9419 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9420 {
9421 struct drm_device *dev = dev_priv->dev;
9422 uint32_t val;
9423
9424 DRM_DEBUG_KMS("Enabling package C8+\n");
9425
9426 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9427 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9428 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9429 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9430 }
9431
9432 lpt_disable_clkout_dp(dev);
9433 hsw_disable_lcpll(dev_priv, true, true);
9434 }
9435
9436 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9437 {
9438 struct drm_device *dev = dev_priv->dev;
9439 uint32_t val;
9440
9441 DRM_DEBUG_KMS("Disabling package C8+\n");
9442
9443 hsw_restore_lcpll(dev_priv);
9444 lpt_init_pch_refclk(dev);
9445
9446 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9447 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9448 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9449 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9450 }
9451
9452 intel_prepare_ddi(dev);
9453 }
9454
9455 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9456 {
9457 struct drm_device *dev = old_state->dev;
9458 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9459
9460 broxton_set_cdclk(dev, req_cdclk);
9461 }
9462
9463 /* compute the max rate for new configuration */
9464 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9465 {
9466 struct intel_crtc *intel_crtc;
9467 struct intel_crtc_state *crtc_state;
9468 int max_pixel_rate = 0;
9469
9470 for_each_intel_crtc(state->dev, intel_crtc) {
9471 int pixel_rate;
9472
9473 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9474 if (IS_ERR(crtc_state))
9475 return PTR_ERR(crtc_state);
9476
9477 if (!crtc_state->base.enable)
9478 continue;
9479
9480 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9481
9482 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9483 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9484 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9485
9486 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9487 }
9488
9489 return max_pixel_rate;
9490 }
9491
9492 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9493 {
9494 struct drm_i915_private *dev_priv = dev->dev_private;
9495 uint32_t val, data;
9496 int ret;
9497
9498 if (WARN((I915_READ(LCPLL_CTL) &
9499 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9500 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9501 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9502 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9503 "trying to change cdclk frequency with cdclk not enabled\n"))
9504 return;
9505
9506 mutex_lock(&dev_priv->rps.hw_lock);
9507 ret = sandybridge_pcode_write(dev_priv,
9508 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9509 mutex_unlock(&dev_priv->rps.hw_lock);
9510 if (ret) {
9511 DRM_ERROR("failed to inform pcode about cdclk change\n");
9512 return;
9513 }
9514
9515 val = I915_READ(LCPLL_CTL);
9516 val |= LCPLL_CD_SOURCE_FCLK;
9517 I915_WRITE(LCPLL_CTL, val);
9518
9519 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9520 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9521 DRM_ERROR("Switching to FCLK failed\n");
9522
9523 val = I915_READ(LCPLL_CTL);
9524 val &= ~LCPLL_CLK_FREQ_MASK;
9525
9526 switch (cdclk) {
9527 case 450000:
9528 val |= LCPLL_CLK_FREQ_450;
9529 data = 0;
9530 break;
9531 case 540000:
9532 val |= LCPLL_CLK_FREQ_54O_BDW;
9533 data = 1;
9534 break;
9535 case 337500:
9536 val |= LCPLL_CLK_FREQ_337_5_BDW;
9537 data = 2;
9538 break;
9539 case 675000:
9540 val |= LCPLL_CLK_FREQ_675_BDW;
9541 data = 3;
9542 break;
9543 default:
9544 WARN(1, "invalid cdclk frequency\n");
9545 return;
9546 }
9547
9548 I915_WRITE(LCPLL_CTL, val);
9549
9550 val = I915_READ(LCPLL_CTL);
9551 val &= ~LCPLL_CD_SOURCE_FCLK;
9552 I915_WRITE(LCPLL_CTL, val);
9553
9554 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9555 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9556 DRM_ERROR("Switching back to LCPLL failed\n");
9557
9558 mutex_lock(&dev_priv->rps.hw_lock);
9559 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9560 mutex_unlock(&dev_priv->rps.hw_lock);
9561
9562 intel_update_cdclk(dev);
9563
9564 WARN(cdclk != dev_priv->cdclk_freq,
9565 "cdclk requested %d kHz but got %d kHz\n",
9566 cdclk, dev_priv->cdclk_freq);
9567 }
9568
9569 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9570 {
9571 struct drm_i915_private *dev_priv = to_i915(state->dev);
9572 int max_pixclk = ilk_max_pixel_rate(state);
9573 int cdclk;
9574
9575 /*
9576 * FIXME should also account for plane ratio
9577 * once 64bpp pixel formats are supported.
9578 */
9579 if (max_pixclk > 540000)
9580 cdclk = 675000;
9581 else if (max_pixclk > 450000)
9582 cdclk = 540000;
9583 else if (max_pixclk > 337500)
9584 cdclk = 450000;
9585 else
9586 cdclk = 337500;
9587
9588 /*
9589 * FIXME move the cdclk caclulation to
9590 * compute_config() so we can fail gracegully.
9591 */
9592 if (cdclk > dev_priv->max_cdclk_freq) {
9593 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9594 cdclk, dev_priv->max_cdclk_freq);
9595 cdclk = dev_priv->max_cdclk_freq;
9596 }
9597
9598 to_intel_atomic_state(state)->cdclk = cdclk;
9599
9600 return 0;
9601 }
9602
9603 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9604 {
9605 struct drm_device *dev = old_state->dev;
9606 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9607
9608 broadwell_set_cdclk(dev, req_cdclk);
9609 }
9610
9611 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9612 struct intel_crtc_state *crtc_state)
9613 {
9614 if (!intel_ddi_pll_select(crtc, crtc_state))
9615 return -EINVAL;
9616
9617 crtc->lowfreq_avail = false;
9618
9619 return 0;
9620 }
9621
9622 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9623 enum port port,
9624 struct intel_crtc_state *pipe_config)
9625 {
9626 switch (port) {
9627 case PORT_A:
9628 pipe_config->ddi_pll_sel = SKL_DPLL0;
9629 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9630 break;
9631 case PORT_B:
9632 pipe_config->ddi_pll_sel = SKL_DPLL1;
9633 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9634 break;
9635 case PORT_C:
9636 pipe_config->ddi_pll_sel = SKL_DPLL2;
9637 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9638 break;
9639 default:
9640 DRM_ERROR("Incorrect port type\n");
9641 }
9642 }
9643
9644 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9645 enum port port,
9646 struct intel_crtc_state *pipe_config)
9647 {
9648 u32 temp, dpll_ctl1;
9649
9650 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9651 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9652
9653 switch (pipe_config->ddi_pll_sel) {
9654 case SKL_DPLL0:
9655 /*
9656 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9657 * of the shared DPLL framework and thus needs to be read out
9658 * separately
9659 */
9660 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9661 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9662 break;
9663 case SKL_DPLL1:
9664 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9665 break;
9666 case SKL_DPLL2:
9667 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9668 break;
9669 case SKL_DPLL3:
9670 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9671 break;
9672 }
9673 }
9674
9675 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9676 enum port port,
9677 struct intel_crtc_state *pipe_config)
9678 {
9679 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9680
9681 switch (pipe_config->ddi_pll_sel) {
9682 case PORT_CLK_SEL_WRPLL1:
9683 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9684 break;
9685 case PORT_CLK_SEL_WRPLL2:
9686 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9687 break;
9688 }
9689 }
9690
9691 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9692 struct intel_crtc_state *pipe_config)
9693 {
9694 struct drm_device *dev = crtc->base.dev;
9695 struct drm_i915_private *dev_priv = dev->dev_private;
9696 struct intel_shared_dpll *pll;
9697 enum port port;
9698 uint32_t tmp;
9699
9700 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9701
9702 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9703
9704 if (IS_SKYLAKE(dev))
9705 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9706 else if (IS_BROXTON(dev))
9707 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9708 else
9709 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9710
9711 if (pipe_config->shared_dpll >= 0) {
9712 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9713
9714 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9715 &pipe_config->dpll_hw_state));
9716 }
9717
9718 /*
9719 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9720 * DDI E. So just check whether this pipe is wired to DDI E and whether
9721 * the PCH transcoder is on.
9722 */
9723 if (INTEL_INFO(dev)->gen < 9 &&
9724 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9725 pipe_config->has_pch_encoder = true;
9726
9727 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9728 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9729 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9730
9731 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9732 }
9733 }
9734
9735 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9736 struct intel_crtc_state *pipe_config)
9737 {
9738 struct drm_device *dev = crtc->base.dev;
9739 struct drm_i915_private *dev_priv = dev->dev_private;
9740 enum intel_display_power_domain pfit_domain;
9741 uint32_t tmp;
9742
9743 if (!intel_display_power_is_enabled(dev_priv,
9744 POWER_DOMAIN_PIPE(crtc->pipe)))
9745 return false;
9746
9747 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9748 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9749
9750 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9751 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9752 enum pipe trans_edp_pipe;
9753 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9754 default:
9755 WARN(1, "unknown pipe linked to edp transcoder\n");
9756 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9757 case TRANS_DDI_EDP_INPUT_A_ON:
9758 trans_edp_pipe = PIPE_A;
9759 break;
9760 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9761 trans_edp_pipe = PIPE_B;
9762 break;
9763 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9764 trans_edp_pipe = PIPE_C;
9765 break;
9766 }
9767
9768 if (trans_edp_pipe == crtc->pipe)
9769 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9770 }
9771
9772 if (!intel_display_power_is_enabled(dev_priv,
9773 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9774 return false;
9775
9776 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9777 if (!(tmp & PIPECONF_ENABLE))
9778 return false;
9779
9780 haswell_get_ddi_port_state(crtc, pipe_config);
9781
9782 intel_get_pipe_timings(crtc, pipe_config);
9783
9784 if (INTEL_INFO(dev)->gen >= 9) {
9785 skl_init_scalers(dev, crtc, pipe_config);
9786 }
9787
9788 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9789
9790 if (INTEL_INFO(dev)->gen >= 9) {
9791 pipe_config->scaler_state.scaler_id = -1;
9792 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9793 }
9794
9795 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9796 if (INTEL_INFO(dev)->gen == 9)
9797 skylake_get_pfit_config(crtc, pipe_config);
9798 else if (INTEL_INFO(dev)->gen < 9)
9799 ironlake_get_pfit_config(crtc, pipe_config);
9800 else
9801 MISSING_CASE(INTEL_INFO(dev)->gen);
9802 }
9803
9804 if (IS_HASWELL(dev))
9805 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9806 (I915_READ(IPS_CTL) & IPS_ENABLE);
9807
9808 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9809 pipe_config->pixel_multiplier =
9810 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9811 } else {
9812 pipe_config->pixel_multiplier = 1;
9813 }
9814
9815 return true;
9816 }
9817
9818 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9819 {
9820 struct drm_device *dev = crtc->dev;
9821 struct drm_i915_private *dev_priv = dev->dev_private;
9822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9823 uint32_t cntl = 0, size = 0;
9824
9825 if (base) {
9826 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9827 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9828 unsigned int stride = roundup_pow_of_two(width) * 4;
9829
9830 switch (stride) {
9831 default:
9832 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9833 width, stride);
9834 stride = 256;
9835 /* fallthrough */
9836 case 256:
9837 case 512:
9838 case 1024:
9839 case 2048:
9840 break;
9841 }
9842
9843 cntl |= CURSOR_ENABLE |
9844 CURSOR_GAMMA_ENABLE |
9845 CURSOR_FORMAT_ARGB |
9846 CURSOR_STRIDE(stride);
9847
9848 size = (height << 12) | width;
9849 }
9850
9851 if (intel_crtc->cursor_cntl != 0 &&
9852 (intel_crtc->cursor_base != base ||
9853 intel_crtc->cursor_size != size ||
9854 intel_crtc->cursor_cntl != cntl)) {
9855 /* On these chipsets we can only modify the base/size/stride
9856 * whilst the cursor is disabled.
9857 */
9858 I915_WRITE(_CURACNTR, 0);
9859 POSTING_READ(_CURACNTR);
9860 intel_crtc->cursor_cntl = 0;
9861 }
9862
9863 if (intel_crtc->cursor_base != base) {
9864 I915_WRITE(_CURABASE, base);
9865 intel_crtc->cursor_base = base;
9866 }
9867
9868 if (intel_crtc->cursor_size != size) {
9869 I915_WRITE(CURSIZE, size);
9870 intel_crtc->cursor_size = size;
9871 }
9872
9873 if (intel_crtc->cursor_cntl != cntl) {
9874 I915_WRITE(_CURACNTR, cntl);
9875 POSTING_READ(_CURACNTR);
9876 intel_crtc->cursor_cntl = cntl;
9877 }
9878 }
9879
9880 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9881 {
9882 struct drm_device *dev = crtc->dev;
9883 struct drm_i915_private *dev_priv = dev->dev_private;
9884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9885 int pipe = intel_crtc->pipe;
9886 uint32_t cntl;
9887
9888 cntl = 0;
9889 if (base) {
9890 cntl = MCURSOR_GAMMA_ENABLE;
9891 switch (intel_crtc->base.cursor->state->crtc_w) {
9892 case 64:
9893 cntl |= CURSOR_MODE_64_ARGB_AX;
9894 break;
9895 case 128:
9896 cntl |= CURSOR_MODE_128_ARGB_AX;
9897 break;
9898 case 256:
9899 cntl |= CURSOR_MODE_256_ARGB_AX;
9900 break;
9901 default:
9902 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9903 return;
9904 }
9905 cntl |= pipe << 28; /* Connect to correct pipe */
9906
9907 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9908 cntl |= CURSOR_PIPE_CSC_ENABLE;
9909 }
9910
9911 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9912 cntl |= CURSOR_ROTATE_180;
9913
9914 if (intel_crtc->cursor_cntl != cntl) {
9915 I915_WRITE(CURCNTR(pipe), cntl);
9916 POSTING_READ(CURCNTR(pipe));
9917 intel_crtc->cursor_cntl = cntl;
9918 }
9919
9920 /* and commit changes on next vblank */
9921 I915_WRITE(CURBASE(pipe), base);
9922 POSTING_READ(CURBASE(pipe));
9923
9924 intel_crtc->cursor_base = base;
9925 }
9926
9927 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9928 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9929 bool on)
9930 {
9931 struct drm_device *dev = crtc->dev;
9932 struct drm_i915_private *dev_priv = dev->dev_private;
9933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9934 int pipe = intel_crtc->pipe;
9935 int x = crtc->cursor_x;
9936 int y = crtc->cursor_y;
9937 u32 base = 0, pos = 0;
9938
9939 if (on)
9940 base = intel_crtc->cursor_addr;
9941
9942 if (x >= intel_crtc->config->pipe_src_w)
9943 base = 0;
9944
9945 if (y >= intel_crtc->config->pipe_src_h)
9946 base = 0;
9947
9948 if (x < 0) {
9949 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9950 base = 0;
9951
9952 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9953 x = -x;
9954 }
9955 pos |= x << CURSOR_X_SHIFT;
9956
9957 if (y < 0) {
9958 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9959 base = 0;
9960
9961 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9962 y = -y;
9963 }
9964 pos |= y << CURSOR_Y_SHIFT;
9965
9966 if (base == 0 && intel_crtc->cursor_base == 0)
9967 return;
9968
9969 I915_WRITE(CURPOS(pipe), pos);
9970
9971 /* ILK+ do this automagically */
9972 if (HAS_GMCH_DISPLAY(dev) &&
9973 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9974 base += (intel_crtc->base.cursor->state->crtc_h *
9975 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9976 }
9977
9978 if (IS_845G(dev) || IS_I865G(dev))
9979 i845_update_cursor(crtc, base);
9980 else
9981 i9xx_update_cursor(crtc, base);
9982 }
9983
9984 static bool cursor_size_ok(struct drm_device *dev,
9985 uint32_t width, uint32_t height)
9986 {
9987 if (width == 0 || height == 0)
9988 return false;
9989
9990 /*
9991 * 845g/865g are special in that they are only limited by
9992 * the width of their cursors, the height is arbitrary up to
9993 * the precision of the register. Everything else requires
9994 * square cursors, limited to a few power-of-two sizes.
9995 */
9996 if (IS_845G(dev) || IS_I865G(dev)) {
9997 if ((width & 63) != 0)
9998 return false;
9999
10000 if (width > (IS_845G(dev) ? 64 : 512))
10001 return false;
10002
10003 if (height > 1023)
10004 return false;
10005 } else {
10006 switch (width | height) {
10007 case 256:
10008 case 128:
10009 if (IS_GEN2(dev))
10010 return false;
10011 case 64:
10012 break;
10013 default:
10014 return false;
10015 }
10016 }
10017
10018 return true;
10019 }
10020
10021 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10022 u16 *blue, uint32_t start, uint32_t size)
10023 {
10024 int end = (start + size > 256) ? 256 : start + size, i;
10025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10026
10027 for (i = start; i < end; i++) {
10028 intel_crtc->lut_r[i] = red[i] >> 8;
10029 intel_crtc->lut_g[i] = green[i] >> 8;
10030 intel_crtc->lut_b[i] = blue[i] >> 8;
10031 }
10032
10033 intel_crtc_load_lut(crtc);
10034 }
10035
10036 /* VESA 640x480x72Hz mode to set on the pipe */
10037 static struct drm_display_mode load_detect_mode = {
10038 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10039 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10040 };
10041
10042 struct drm_framebuffer *
10043 __intel_framebuffer_create(struct drm_device *dev,
10044 struct drm_mode_fb_cmd2 *mode_cmd,
10045 struct drm_i915_gem_object *obj)
10046 {
10047 struct intel_framebuffer *intel_fb;
10048 int ret;
10049
10050 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10051 if (!intel_fb) {
10052 drm_gem_object_unreference(&obj->base);
10053 return ERR_PTR(-ENOMEM);
10054 }
10055
10056 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10057 if (ret)
10058 goto err;
10059
10060 return &intel_fb->base;
10061 err:
10062 drm_gem_object_unreference(&obj->base);
10063 kfree(intel_fb);
10064
10065 return ERR_PTR(ret);
10066 }
10067
10068 static struct drm_framebuffer *
10069 intel_framebuffer_create(struct drm_device *dev,
10070 struct drm_mode_fb_cmd2 *mode_cmd,
10071 struct drm_i915_gem_object *obj)
10072 {
10073 struct drm_framebuffer *fb;
10074 int ret;
10075
10076 ret = i915_mutex_lock_interruptible(dev);
10077 if (ret)
10078 return ERR_PTR(ret);
10079 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10080 mutex_unlock(&dev->struct_mutex);
10081
10082 return fb;
10083 }
10084
10085 static u32
10086 intel_framebuffer_pitch_for_width(int width, int bpp)
10087 {
10088 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10089 return ALIGN(pitch, 64);
10090 }
10091
10092 static u32
10093 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10094 {
10095 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10096 return PAGE_ALIGN(pitch * mode->vdisplay);
10097 }
10098
10099 static struct drm_framebuffer *
10100 intel_framebuffer_create_for_mode(struct drm_device *dev,
10101 struct drm_display_mode *mode,
10102 int depth, int bpp)
10103 {
10104 struct drm_i915_gem_object *obj;
10105 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10106
10107 obj = i915_gem_alloc_object(dev,
10108 intel_framebuffer_size_for_mode(mode, bpp));
10109 if (obj == NULL)
10110 return ERR_PTR(-ENOMEM);
10111
10112 mode_cmd.width = mode->hdisplay;
10113 mode_cmd.height = mode->vdisplay;
10114 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10115 bpp);
10116 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10117
10118 return intel_framebuffer_create(dev, &mode_cmd, obj);
10119 }
10120
10121 static struct drm_framebuffer *
10122 mode_fits_in_fbdev(struct drm_device *dev,
10123 struct drm_display_mode *mode)
10124 {
10125 #ifdef CONFIG_DRM_I915_FBDEV
10126 struct drm_i915_private *dev_priv = dev->dev_private;
10127 struct drm_i915_gem_object *obj;
10128 struct drm_framebuffer *fb;
10129
10130 if (!dev_priv->fbdev)
10131 return NULL;
10132
10133 if (!dev_priv->fbdev->fb)
10134 return NULL;
10135
10136 obj = dev_priv->fbdev->fb->obj;
10137 BUG_ON(!obj);
10138
10139 fb = &dev_priv->fbdev->fb->base;
10140 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10141 fb->bits_per_pixel))
10142 return NULL;
10143
10144 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10145 return NULL;
10146
10147 return fb;
10148 #else
10149 return NULL;
10150 #endif
10151 }
10152
10153 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10154 struct drm_crtc *crtc,
10155 struct drm_display_mode *mode,
10156 struct drm_framebuffer *fb,
10157 int x, int y)
10158 {
10159 struct drm_plane_state *plane_state;
10160 int hdisplay, vdisplay;
10161 int ret;
10162
10163 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10164 if (IS_ERR(plane_state))
10165 return PTR_ERR(plane_state);
10166
10167 if (mode)
10168 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10169 else
10170 hdisplay = vdisplay = 0;
10171
10172 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10173 if (ret)
10174 return ret;
10175 drm_atomic_set_fb_for_plane(plane_state, fb);
10176 plane_state->crtc_x = 0;
10177 plane_state->crtc_y = 0;
10178 plane_state->crtc_w = hdisplay;
10179 plane_state->crtc_h = vdisplay;
10180 plane_state->src_x = x << 16;
10181 plane_state->src_y = y << 16;
10182 plane_state->src_w = hdisplay << 16;
10183 plane_state->src_h = vdisplay << 16;
10184
10185 return 0;
10186 }
10187
10188 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10189 struct drm_display_mode *mode,
10190 struct intel_load_detect_pipe *old,
10191 struct drm_modeset_acquire_ctx *ctx)
10192 {
10193 struct intel_crtc *intel_crtc;
10194 struct intel_encoder *intel_encoder =
10195 intel_attached_encoder(connector);
10196 struct drm_crtc *possible_crtc;
10197 struct drm_encoder *encoder = &intel_encoder->base;
10198 struct drm_crtc *crtc = NULL;
10199 struct drm_device *dev = encoder->dev;
10200 struct drm_framebuffer *fb;
10201 struct drm_mode_config *config = &dev->mode_config;
10202 struct drm_atomic_state *state = NULL;
10203 struct drm_connector_state *connector_state;
10204 struct intel_crtc_state *crtc_state;
10205 int ret, i = -1;
10206
10207 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10208 connector->base.id, connector->name,
10209 encoder->base.id, encoder->name);
10210
10211 retry:
10212 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10213 if (ret)
10214 goto fail_unlock;
10215
10216 /*
10217 * Algorithm gets a little messy:
10218 *
10219 * - if the connector already has an assigned crtc, use it (but make
10220 * sure it's on first)
10221 *
10222 * - try to find the first unused crtc that can drive this connector,
10223 * and use that if we find one
10224 */
10225
10226 /* See if we already have a CRTC for this connector */
10227 if (encoder->crtc) {
10228 crtc = encoder->crtc;
10229
10230 ret = drm_modeset_lock(&crtc->mutex, ctx);
10231 if (ret)
10232 goto fail_unlock;
10233 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10234 if (ret)
10235 goto fail_unlock;
10236
10237 old->dpms_mode = connector->dpms;
10238 old->load_detect_temp = false;
10239
10240 /* Make sure the crtc and connector are running */
10241 if (connector->dpms != DRM_MODE_DPMS_ON)
10242 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10243
10244 return true;
10245 }
10246
10247 /* Find an unused one (if possible) */
10248 for_each_crtc(dev, possible_crtc) {
10249 i++;
10250 if (!(encoder->possible_crtcs & (1 << i)))
10251 continue;
10252 if (possible_crtc->state->enable)
10253 continue;
10254 /* This can occur when applying the pipe A quirk on resume. */
10255 if (to_intel_crtc(possible_crtc)->new_enabled)
10256 continue;
10257
10258 crtc = possible_crtc;
10259 break;
10260 }
10261
10262 /*
10263 * If we didn't find an unused CRTC, don't use any.
10264 */
10265 if (!crtc) {
10266 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10267 goto fail_unlock;
10268 }
10269
10270 ret = drm_modeset_lock(&crtc->mutex, ctx);
10271 if (ret)
10272 goto fail_unlock;
10273 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10274 if (ret)
10275 goto fail_unlock;
10276 intel_encoder->new_crtc = to_intel_crtc(crtc);
10277 to_intel_connector(connector)->new_encoder = intel_encoder;
10278
10279 intel_crtc = to_intel_crtc(crtc);
10280 intel_crtc->new_enabled = true;
10281 old->dpms_mode = connector->dpms;
10282 old->load_detect_temp = true;
10283 old->release_fb = NULL;
10284
10285 state = drm_atomic_state_alloc(dev);
10286 if (!state)
10287 return false;
10288
10289 state->acquire_ctx = ctx;
10290
10291 connector_state = drm_atomic_get_connector_state(state, connector);
10292 if (IS_ERR(connector_state)) {
10293 ret = PTR_ERR(connector_state);
10294 goto fail;
10295 }
10296
10297 connector_state->crtc = crtc;
10298 connector_state->best_encoder = &intel_encoder->base;
10299
10300 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10301 if (IS_ERR(crtc_state)) {
10302 ret = PTR_ERR(crtc_state);
10303 goto fail;
10304 }
10305
10306 crtc_state->base.active = crtc_state->base.enable = true;
10307
10308 if (!mode)
10309 mode = &load_detect_mode;
10310
10311 /* We need a framebuffer large enough to accommodate all accesses
10312 * that the plane may generate whilst we perform load detection.
10313 * We can not rely on the fbcon either being present (we get called
10314 * during its initialisation to detect all boot displays, or it may
10315 * not even exist) or that it is large enough to satisfy the
10316 * requested mode.
10317 */
10318 fb = mode_fits_in_fbdev(dev, mode);
10319 if (fb == NULL) {
10320 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10321 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10322 old->release_fb = fb;
10323 } else
10324 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10325 if (IS_ERR(fb)) {
10326 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10327 goto fail;
10328 }
10329
10330 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10331 if (ret)
10332 goto fail;
10333
10334 drm_mode_copy(&crtc_state->base.mode, mode);
10335
10336 if (intel_set_mode(state)) {
10337 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10338 if (old->release_fb)
10339 old->release_fb->funcs->destroy(old->release_fb);
10340 goto fail;
10341 }
10342 crtc->primary->crtc = crtc;
10343
10344 /* let the connector get through one full cycle before testing */
10345 intel_wait_for_vblank(dev, intel_crtc->pipe);
10346 return true;
10347
10348 fail:
10349 intel_crtc->new_enabled = crtc->state->enable;
10350 fail_unlock:
10351 drm_atomic_state_free(state);
10352 state = NULL;
10353
10354 if (ret == -EDEADLK) {
10355 drm_modeset_backoff(ctx);
10356 goto retry;
10357 }
10358
10359 return false;
10360 }
10361
10362 void intel_release_load_detect_pipe(struct drm_connector *connector,
10363 struct intel_load_detect_pipe *old,
10364 struct drm_modeset_acquire_ctx *ctx)
10365 {
10366 struct drm_device *dev = connector->dev;
10367 struct intel_encoder *intel_encoder =
10368 intel_attached_encoder(connector);
10369 struct drm_encoder *encoder = &intel_encoder->base;
10370 struct drm_crtc *crtc = encoder->crtc;
10371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10372 struct drm_atomic_state *state;
10373 struct drm_connector_state *connector_state;
10374 struct intel_crtc_state *crtc_state;
10375 int ret;
10376
10377 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10378 connector->base.id, connector->name,
10379 encoder->base.id, encoder->name);
10380
10381 if (old->load_detect_temp) {
10382 state = drm_atomic_state_alloc(dev);
10383 if (!state)
10384 goto fail;
10385
10386 state->acquire_ctx = ctx;
10387
10388 connector_state = drm_atomic_get_connector_state(state, connector);
10389 if (IS_ERR(connector_state))
10390 goto fail;
10391
10392 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10393 if (IS_ERR(crtc_state))
10394 goto fail;
10395
10396 to_intel_connector(connector)->new_encoder = NULL;
10397 intel_encoder->new_crtc = NULL;
10398 intel_crtc->new_enabled = false;
10399
10400 connector_state->best_encoder = NULL;
10401 connector_state->crtc = NULL;
10402
10403 crtc_state->base.enable = crtc_state->base.active = false;
10404
10405 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10406 0, 0);
10407 if (ret)
10408 goto fail;
10409
10410 ret = intel_set_mode(state);
10411 if (ret)
10412 goto fail;
10413
10414 if (old->release_fb) {
10415 drm_framebuffer_unregister_private(old->release_fb);
10416 drm_framebuffer_unreference(old->release_fb);
10417 }
10418
10419 return;
10420 }
10421
10422 /* Switch crtc and encoder back off if necessary */
10423 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10424 connector->funcs->dpms(connector, old->dpms_mode);
10425
10426 return;
10427 fail:
10428 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10429 drm_atomic_state_free(state);
10430 }
10431
10432 static int i9xx_pll_refclk(struct drm_device *dev,
10433 const struct intel_crtc_state *pipe_config)
10434 {
10435 struct drm_i915_private *dev_priv = dev->dev_private;
10436 u32 dpll = pipe_config->dpll_hw_state.dpll;
10437
10438 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10439 return dev_priv->vbt.lvds_ssc_freq;
10440 else if (HAS_PCH_SPLIT(dev))
10441 return 120000;
10442 else if (!IS_GEN2(dev))
10443 return 96000;
10444 else
10445 return 48000;
10446 }
10447
10448 /* Returns the clock of the currently programmed mode of the given pipe. */
10449 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10450 struct intel_crtc_state *pipe_config)
10451 {
10452 struct drm_device *dev = crtc->base.dev;
10453 struct drm_i915_private *dev_priv = dev->dev_private;
10454 int pipe = pipe_config->cpu_transcoder;
10455 u32 dpll = pipe_config->dpll_hw_state.dpll;
10456 u32 fp;
10457 intel_clock_t clock;
10458 int refclk = i9xx_pll_refclk(dev, pipe_config);
10459
10460 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10461 fp = pipe_config->dpll_hw_state.fp0;
10462 else
10463 fp = pipe_config->dpll_hw_state.fp1;
10464
10465 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10466 if (IS_PINEVIEW(dev)) {
10467 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10468 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10469 } else {
10470 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10471 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10472 }
10473
10474 if (!IS_GEN2(dev)) {
10475 if (IS_PINEVIEW(dev))
10476 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10477 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10478 else
10479 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10480 DPLL_FPA01_P1_POST_DIV_SHIFT);
10481
10482 switch (dpll & DPLL_MODE_MASK) {
10483 case DPLLB_MODE_DAC_SERIAL:
10484 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10485 5 : 10;
10486 break;
10487 case DPLLB_MODE_LVDS:
10488 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10489 7 : 14;
10490 break;
10491 default:
10492 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10493 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10494 return;
10495 }
10496
10497 if (IS_PINEVIEW(dev))
10498 pineview_clock(refclk, &clock);
10499 else
10500 i9xx_clock(refclk, &clock);
10501 } else {
10502 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10503 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10504
10505 if (is_lvds) {
10506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10507 DPLL_FPA01_P1_POST_DIV_SHIFT);
10508
10509 if (lvds & LVDS_CLKB_POWER_UP)
10510 clock.p2 = 7;
10511 else
10512 clock.p2 = 14;
10513 } else {
10514 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10515 clock.p1 = 2;
10516 else {
10517 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10518 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10519 }
10520 if (dpll & PLL_P2_DIVIDE_BY_4)
10521 clock.p2 = 4;
10522 else
10523 clock.p2 = 2;
10524 }
10525
10526 i9xx_clock(refclk, &clock);
10527 }
10528
10529 /*
10530 * This value includes pixel_multiplier. We will use
10531 * port_clock to compute adjusted_mode.crtc_clock in the
10532 * encoder's get_config() function.
10533 */
10534 pipe_config->port_clock = clock.dot;
10535 }
10536
10537 int intel_dotclock_calculate(int link_freq,
10538 const struct intel_link_m_n *m_n)
10539 {
10540 /*
10541 * The calculation for the data clock is:
10542 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10543 * But we want to avoid losing precison if possible, so:
10544 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10545 *
10546 * and the link clock is simpler:
10547 * link_clock = (m * link_clock) / n
10548 */
10549
10550 if (!m_n->link_n)
10551 return 0;
10552
10553 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10554 }
10555
10556 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10557 struct intel_crtc_state *pipe_config)
10558 {
10559 struct drm_device *dev = crtc->base.dev;
10560
10561 /* read out port_clock from the DPLL */
10562 i9xx_crtc_clock_get(crtc, pipe_config);
10563
10564 /*
10565 * This value does not include pixel_multiplier.
10566 * We will check that port_clock and adjusted_mode.crtc_clock
10567 * agree once we know their relationship in the encoder's
10568 * get_config() function.
10569 */
10570 pipe_config->base.adjusted_mode.crtc_clock =
10571 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10572 &pipe_config->fdi_m_n);
10573 }
10574
10575 /** Returns the currently programmed mode of the given pipe. */
10576 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10577 struct drm_crtc *crtc)
10578 {
10579 struct drm_i915_private *dev_priv = dev->dev_private;
10580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10581 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10582 struct drm_display_mode *mode;
10583 struct intel_crtc_state pipe_config;
10584 int htot = I915_READ(HTOTAL(cpu_transcoder));
10585 int hsync = I915_READ(HSYNC(cpu_transcoder));
10586 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10587 int vsync = I915_READ(VSYNC(cpu_transcoder));
10588 enum pipe pipe = intel_crtc->pipe;
10589
10590 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10591 if (!mode)
10592 return NULL;
10593
10594 /*
10595 * Construct a pipe_config sufficient for getting the clock info
10596 * back out of crtc_clock_get.
10597 *
10598 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10599 * to use a real value here instead.
10600 */
10601 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10602 pipe_config.pixel_multiplier = 1;
10603 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10604 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10605 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10606 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10607
10608 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10609 mode->hdisplay = (htot & 0xffff) + 1;
10610 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10611 mode->hsync_start = (hsync & 0xffff) + 1;
10612 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10613 mode->vdisplay = (vtot & 0xffff) + 1;
10614 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10615 mode->vsync_start = (vsync & 0xffff) + 1;
10616 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10617
10618 drm_mode_set_name(mode);
10619
10620 return mode;
10621 }
10622
10623 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10624 {
10625 struct drm_device *dev = crtc->dev;
10626 struct drm_i915_private *dev_priv = dev->dev_private;
10627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10628
10629 if (!HAS_GMCH_DISPLAY(dev))
10630 return;
10631
10632 if (!dev_priv->lvds_downclock_avail)
10633 return;
10634
10635 /*
10636 * Since this is called by a timer, we should never get here in
10637 * the manual case.
10638 */
10639 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10640 int pipe = intel_crtc->pipe;
10641 int dpll_reg = DPLL(pipe);
10642 int dpll;
10643
10644 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10645
10646 assert_panel_unlocked(dev_priv, pipe);
10647
10648 dpll = I915_READ(dpll_reg);
10649 dpll |= DISPLAY_RATE_SELECT_FPA1;
10650 I915_WRITE(dpll_reg, dpll);
10651 intel_wait_for_vblank(dev, pipe);
10652 dpll = I915_READ(dpll_reg);
10653 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10654 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10655 }
10656
10657 }
10658
10659 void intel_mark_busy(struct drm_device *dev)
10660 {
10661 struct drm_i915_private *dev_priv = dev->dev_private;
10662
10663 if (dev_priv->mm.busy)
10664 return;
10665
10666 intel_runtime_pm_get(dev_priv);
10667 i915_update_gfx_val(dev_priv);
10668 if (INTEL_INFO(dev)->gen >= 6)
10669 gen6_rps_busy(dev_priv);
10670 dev_priv->mm.busy = true;
10671 }
10672
10673 void intel_mark_idle(struct drm_device *dev)
10674 {
10675 struct drm_i915_private *dev_priv = dev->dev_private;
10676 struct drm_crtc *crtc;
10677
10678 if (!dev_priv->mm.busy)
10679 return;
10680
10681 dev_priv->mm.busy = false;
10682
10683 for_each_crtc(dev, crtc) {
10684 if (!crtc->primary->fb)
10685 continue;
10686
10687 intel_decrease_pllclock(crtc);
10688 }
10689
10690 if (INTEL_INFO(dev)->gen >= 6)
10691 gen6_rps_idle(dev->dev_private);
10692
10693 intel_runtime_pm_put(dev_priv);
10694 }
10695
10696 static void intel_crtc_destroy(struct drm_crtc *crtc)
10697 {
10698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10699 struct drm_device *dev = crtc->dev;
10700 struct intel_unpin_work *work;
10701
10702 spin_lock_irq(&dev->event_lock);
10703 work = intel_crtc->unpin_work;
10704 intel_crtc->unpin_work = NULL;
10705 spin_unlock_irq(&dev->event_lock);
10706
10707 if (work) {
10708 cancel_work_sync(&work->work);
10709 kfree(work);
10710 }
10711
10712 drm_crtc_cleanup(crtc);
10713
10714 kfree(intel_crtc);
10715 }
10716
10717 static void intel_unpin_work_fn(struct work_struct *__work)
10718 {
10719 struct intel_unpin_work *work =
10720 container_of(__work, struct intel_unpin_work, work);
10721 struct drm_device *dev = work->crtc->dev;
10722 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10723
10724 mutex_lock(&dev->struct_mutex);
10725 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10726 drm_gem_object_unreference(&work->pending_flip_obj->base);
10727
10728 intel_fbc_update(dev);
10729
10730 if (work->flip_queued_req)
10731 i915_gem_request_assign(&work->flip_queued_req, NULL);
10732 mutex_unlock(&dev->struct_mutex);
10733
10734 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10735 drm_framebuffer_unreference(work->old_fb);
10736
10737 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10738 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10739
10740 kfree(work);
10741 }
10742
10743 static void do_intel_finish_page_flip(struct drm_device *dev,
10744 struct drm_crtc *crtc)
10745 {
10746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10747 struct intel_unpin_work *work;
10748 unsigned long flags;
10749
10750 /* Ignore early vblank irqs */
10751 if (intel_crtc == NULL)
10752 return;
10753
10754 /*
10755 * This is called both by irq handlers and the reset code (to complete
10756 * lost pageflips) so needs the full irqsave spinlocks.
10757 */
10758 spin_lock_irqsave(&dev->event_lock, flags);
10759 work = intel_crtc->unpin_work;
10760
10761 /* Ensure we don't miss a work->pending update ... */
10762 smp_rmb();
10763
10764 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10765 spin_unlock_irqrestore(&dev->event_lock, flags);
10766 return;
10767 }
10768
10769 page_flip_completed(intel_crtc);
10770
10771 spin_unlock_irqrestore(&dev->event_lock, flags);
10772 }
10773
10774 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10775 {
10776 struct drm_i915_private *dev_priv = dev->dev_private;
10777 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10778
10779 do_intel_finish_page_flip(dev, crtc);
10780 }
10781
10782 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10783 {
10784 struct drm_i915_private *dev_priv = dev->dev_private;
10785 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10786
10787 do_intel_finish_page_flip(dev, crtc);
10788 }
10789
10790 /* Is 'a' after or equal to 'b'? */
10791 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10792 {
10793 return !((a - b) & 0x80000000);
10794 }
10795
10796 static bool page_flip_finished(struct intel_crtc *crtc)
10797 {
10798 struct drm_device *dev = crtc->base.dev;
10799 struct drm_i915_private *dev_priv = dev->dev_private;
10800
10801 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10802 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10803 return true;
10804
10805 /*
10806 * The relevant registers doen't exist on pre-ctg.
10807 * As the flip done interrupt doesn't trigger for mmio
10808 * flips on gmch platforms, a flip count check isn't
10809 * really needed there. But since ctg has the registers,
10810 * include it in the check anyway.
10811 */
10812 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10813 return true;
10814
10815 /*
10816 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10817 * used the same base address. In that case the mmio flip might
10818 * have completed, but the CS hasn't even executed the flip yet.
10819 *
10820 * A flip count check isn't enough as the CS might have updated
10821 * the base address just after start of vblank, but before we
10822 * managed to process the interrupt. This means we'd complete the
10823 * CS flip too soon.
10824 *
10825 * Combining both checks should get us a good enough result. It may
10826 * still happen that the CS flip has been executed, but has not
10827 * yet actually completed. But in case the base address is the same
10828 * anyway, we don't really care.
10829 */
10830 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10831 crtc->unpin_work->gtt_offset &&
10832 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10833 crtc->unpin_work->flip_count);
10834 }
10835
10836 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10837 {
10838 struct drm_i915_private *dev_priv = dev->dev_private;
10839 struct intel_crtc *intel_crtc =
10840 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10841 unsigned long flags;
10842
10843
10844 /*
10845 * This is called both by irq handlers and the reset code (to complete
10846 * lost pageflips) so needs the full irqsave spinlocks.
10847 *
10848 * NB: An MMIO update of the plane base pointer will also
10849 * generate a page-flip completion irq, i.e. every modeset
10850 * is also accompanied by a spurious intel_prepare_page_flip().
10851 */
10852 spin_lock_irqsave(&dev->event_lock, flags);
10853 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10854 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10855 spin_unlock_irqrestore(&dev->event_lock, flags);
10856 }
10857
10858 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10859 {
10860 /* Ensure that the work item is consistent when activating it ... */
10861 smp_wmb();
10862 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10863 /* and that it is marked active as soon as the irq could fire. */
10864 smp_wmb();
10865 }
10866
10867 static int intel_gen2_queue_flip(struct drm_device *dev,
10868 struct drm_crtc *crtc,
10869 struct drm_framebuffer *fb,
10870 struct drm_i915_gem_object *obj,
10871 struct drm_i915_gem_request *req,
10872 uint32_t flags)
10873 {
10874 struct intel_engine_cs *ring = req->ring;
10875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10876 u32 flip_mask;
10877 int ret;
10878
10879 ret = intel_ring_begin(ring, 6);
10880 if (ret)
10881 return ret;
10882
10883 /* Can't queue multiple flips, so wait for the previous
10884 * one to finish before executing the next.
10885 */
10886 if (intel_crtc->plane)
10887 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10888 else
10889 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10890 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10891 intel_ring_emit(ring, MI_NOOP);
10892 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10893 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10894 intel_ring_emit(ring, fb->pitches[0]);
10895 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10896 intel_ring_emit(ring, 0); /* aux display base address, unused */
10897
10898 intel_mark_page_flip_active(intel_crtc);
10899 return 0;
10900 }
10901
10902 static int intel_gen3_queue_flip(struct drm_device *dev,
10903 struct drm_crtc *crtc,
10904 struct drm_framebuffer *fb,
10905 struct drm_i915_gem_object *obj,
10906 struct drm_i915_gem_request *req,
10907 uint32_t flags)
10908 {
10909 struct intel_engine_cs *ring = req->ring;
10910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10911 u32 flip_mask;
10912 int ret;
10913
10914 ret = intel_ring_begin(ring, 6);
10915 if (ret)
10916 return ret;
10917
10918 if (intel_crtc->plane)
10919 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10920 else
10921 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10922 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10923 intel_ring_emit(ring, MI_NOOP);
10924 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10925 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10926 intel_ring_emit(ring, fb->pitches[0]);
10927 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10928 intel_ring_emit(ring, MI_NOOP);
10929
10930 intel_mark_page_flip_active(intel_crtc);
10931 return 0;
10932 }
10933
10934 static int intel_gen4_queue_flip(struct drm_device *dev,
10935 struct drm_crtc *crtc,
10936 struct drm_framebuffer *fb,
10937 struct drm_i915_gem_object *obj,
10938 struct drm_i915_gem_request *req,
10939 uint32_t flags)
10940 {
10941 struct intel_engine_cs *ring = req->ring;
10942 struct drm_i915_private *dev_priv = dev->dev_private;
10943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10944 uint32_t pf, pipesrc;
10945 int ret;
10946
10947 ret = intel_ring_begin(ring, 4);
10948 if (ret)
10949 return ret;
10950
10951 /* i965+ uses the linear or tiled offsets from the
10952 * Display Registers (which do not change across a page-flip)
10953 * so we need only reprogram the base address.
10954 */
10955 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10956 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10957 intel_ring_emit(ring, fb->pitches[0]);
10958 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10959 obj->tiling_mode);
10960
10961 /* XXX Enabling the panel-fitter across page-flip is so far
10962 * untested on non-native modes, so ignore it for now.
10963 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10964 */
10965 pf = 0;
10966 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10967 intel_ring_emit(ring, pf | pipesrc);
10968
10969 intel_mark_page_flip_active(intel_crtc);
10970 return 0;
10971 }
10972
10973 static int intel_gen6_queue_flip(struct drm_device *dev,
10974 struct drm_crtc *crtc,
10975 struct drm_framebuffer *fb,
10976 struct drm_i915_gem_object *obj,
10977 struct drm_i915_gem_request *req,
10978 uint32_t flags)
10979 {
10980 struct intel_engine_cs *ring = req->ring;
10981 struct drm_i915_private *dev_priv = dev->dev_private;
10982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10983 uint32_t pf, pipesrc;
10984 int ret;
10985
10986 ret = intel_ring_begin(ring, 4);
10987 if (ret)
10988 return ret;
10989
10990 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10991 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10992 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10993 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10994
10995 /* Contrary to the suggestions in the documentation,
10996 * "Enable Panel Fitter" does not seem to be required when page
10997 * flipping with a non-native mode, and worse causes a normal
10998 * modeset to fail.
10999 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11000 */
11001 pf = 0;
11002 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11003 intel_ring_emit(ring, pf | pipesrc);
11004
11005 intel_mark_page_flip_active(intel_crtc);
11006 return 0;
11007 }
11008
11009 static int intel_gen7_queue_flip(struct drm_device *dev,
11010 struct drm_crtc *crtc,
11011 struct drm_framebuffer *fb,
11012 struct drm_i915_gem_object *obj,
11013 struct drm_i915_gem_request *req,
11014 uint32_t flags)
11015 {
11016 struct intel_engine_cs *ring = req->ring;
11017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11018 uint32_t plane_bit = 0;
11019 int len, ret;
11020
11021 switch (intel_crtc->plane) {
11022 case PLANE_A:
11023 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11024 break;
11025 case PLANE_B:
11026 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11027 break;
11028 case PLANE_C:
11029 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11030 break;
11031 default:
11032 WARN_ONCE(1, "unknown plane in flip command\n");
11033 return -ENODEV;
11034 }
11035
11036 len = 4;
11037 if (ring->id == RCS) {
11038 len += 6;
11039 /*
11040 * On Gen 8, SRM is now taking an extra dword to accommodate
11041 * 48bits addresses, and we need a NOOP for the batch size to
11042 * stay even.
11043 */
11044 if (IS_GEN8(dev))
11045 len += 2;
11046 }
11047
11048 /*
11049 * BSpec MI_DISPLAY_FLIP for IVB:
11050 * "The full packet must be contained within the same cache line."
11051 *
11052 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11053 * cacheline, if we ever start emitting more commands before
11054 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11055 * then do the cacheline alignment, and finally emit the
11056 * MI_DISPLAY_FLIP.
11057 */
11058 ret = intel_ring_cacheline_align(ring);
11059 if (ret)
11060 return ret;
11061
11062 ret = intel_ring_begin(ring, len);
11063 if (ret)
11064 return ret;
11065
11066 /* Unmask the flip-done completion message. Note that the bspec says that
11067 * we should do this for both the BCS and RCS, and that we must not unmask
11068 * more than one flip event at any time (or ensure that one flip message
11069 * can be sent by waiting for flip-done prior to queueing new flips).
11070 * Experimentation says that BCS works despite DERRMR masking all
11071 * flip-done completion events and that unmasking all planes at once
11072 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11073 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11074 */
11075 if (ring->id == RCS) {
11076 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11077 intel_ring_emit(ring, DERRMR);
11078 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11079 DERRMR_PIPEB_PRI_FLIP_DONE |
11080 DERRMR_PIPEC_PRI_FLIP_DONE));
11081 if (IS_GEN8(dev))
11082 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11083 MI_SRM_LRM_GLOBAL_GTT);
11084 else
11085 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11086 MI_SRM_LRM_GLOBAL_GTT);
11087 intel_ring_emit(ring, DERRMR);
11088 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11089 if (IS_GEN8(dev)) {
11090 intel_ring_emit(ring, 0);
11091 intel_ring_emit(ring, MI_NOOP);
11092 }
11093 }
11094
11095 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11096 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11097 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11098 intel_ring_emit(ring, (MI_NOOP));
11099
11100 intel_mark_page_flip_active(intel_crtc);
11101 return 0;
11102 }
11103
11104 static bool use_mmio_flip(struct intel_engine_cs *ring,
11105 struct drm_i915_gem_object *obj)
11106 {
11107 /*
11108 * This is not being used for older platforms, because
11109 * non-availability of flip done interrupt forces us to use
11110 * CS flips. Older platforms derive flip done using some clever
11111 * tricks involving the flip_pending status bits and vblank irqs.
11112 * So using MMIO flips there would disrupt this mechanism.
11113 */
11114
11115 if (ring == NULL)
11116 return true;
11117
11118 if (INTEL_INFO(ring->dev)->gen < 5)
11119 return false;
11120
11121 if (i915.use_mmio_flip < 0)
11122 return false;
11123 else if (i915.use_mmio_flip > 0)
11124 return true;
11125 else if (i915.enable_execlists)
11126 return true;
11127 else
11128 return ring != i915_gem_request_get_ring(obj->last_write_req);
11129 }
11130
11131 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11132 {
11133 struct drm_device *dev = intel_crtc->base.dev;
11134 struct drm_i915_private *dev_priv = dev->dev_private;
11135 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11136 const enum pipe pipe = intel_crtc->pipe;
11137 u32 ctl, stride;
11138
11139 ctl = I915_READ(PLANE_CTL(pipe, 0));
11140 ctl &= ~PLANE_CTL_TILED_MASK;
11141 switch (fb->modifier[0]) {
11142 case DRM_FORMAT_MOD_NONE:
11143 break;
11144 case I915_FORMAT_MOD_X_TILED:
11145 ctl |= PLANE_CTL_TILED_X;
11146 break;
11147 case I915_FORMAT_MOD_Y_TILED:
11148 ctl |= PLANE_CTL_TILED_Y;
11149 break;
11150 case I915_FORMAT_MOD_Yf_TILED:
11151 ctl |= PLANE_CTL_TILED_YF;
11152 break;
11153 default:
11154 MISSING_CASE(fb->modifier[0]);
11155 }
11156
11157 /*
11158 * The stride is either expressed as a multiple of 64 bytes chunks for
11159 * linear buffers or in number of tiles for tiled buffers.
11160 */
11161 stride = fb->pitches[0] /
11162 intel_fb_stride_alignment(dev, fb->modifier[0],
11163 fb->pixel_format);
11164
11165 /*
11166 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11167 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11168 */
11169 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11170 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11171
11172 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11173 POSTING_READ(PLANE_SURF(pipe, 0));
11174 }
11175
11176 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11177 {
11178 struct drm_device *dev = intel_crtc->base.dev;
11179 struct drm_i915_private *dev_priv = dev->dev_private;
11180 struct intel_framebuffer *intel_fb =
11181 to_intel_framebuffer(intel_crtc->base.primary->fb);
11182 struct drm_i915_gem_object *obj = intel_fb->obj;
11183 u32 dspcntr;
11184 u32 reg;
11185
11186 reg = DSPCNTR(intel_crtc->plane);
11187 dspcntr = I915_READ(reg);
11188
11189 if (obj->tiling_mode != I915_TILING_NONE)
11190 dspcntr |= DISPPLANE_TILED;
11191 else
11192 dspcntr &= ~DISPPLANE_TILED;
11193
11194 I915_WRITE(reg, dspcntr);
11195
11196 I915_WRITE(DSPSURF(intel_crtc->plane),
11197 intel_crtc->unpin_work->gtt_offset);
11198 POSTING_READ(DSPSURF(intel_crtc->plane));
11199
11200 }
11201
11202 /*
11203 * XXX: This is the temporary way to update the plane registers until we get
11204 * around to using the usual plane update functions for MMIO flips
11205 */
11206 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11207 {
11208 struct drm_device *dev = intel_crtc->base.dev;
11209 bool atomic_update;
11210 u32 start_vbl_count;
11211
11212 intel_mark_page_flip_active(intel_crtc);
11213
11214 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11215
11216 if (INTEL_INFO(dev)->gen >= 9)
11217 skl_do_mmio_flip(intel_crtc);
11218 else
11219 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11220 ilk_do_mmio_flip(intel_crtc);
11221
11222 if (atomic_update)
11223 intel_pipe_update_end(intel_crtc, start_vbl_count);
11224 }
11225
11226 static void intel_mmio_flip_work_func(struct work_struct *work)
11227 {
11228 struct intel_mmio_flip *mmio_flip =
11229 container_of(work, struct intel_mmio_flip, work);
11230
11231 if (mmio_flip->req)
11232 WARN_ON(__i915_wait_request(mmio_flip->req,
11233 mmio_flip->crtc->reset_counter,
11234 false, NULL,
11235 &mmio_flip->i915->rps.mmioflips));
11236
11237 intel_do_mmio_flip(mmio_flip->crtc);
11238
11239 i915_gem_request_unreference__unlocked(mmio_flip->req);
11240 kfree(mmio_flip);
11241 }
11242
11243 static int intel_queue_mmio_flip(struct drm_device *dev,
11244 struct drm_crtc *crtc,
11245 struct drm_framebuffer *fb,
11246 struct drm_i915_gem_object *obj,
11247 struct intel_engine_cs *ring,
11248 uint32_t flags)
11249 {
11250 struct intel_mmio_flip *mmio_flip;
11251
11252 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11253 if (mmio_flip == NULL)
11254 return -ENOMEM;
11255
11256 mmio_flip->i915 = to_i915(dev);
11257 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11258 mmio_flip->crtc = to_intel_crtc(crtc);
11259
11260 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11261 schedule_work(&mmio_flip->work);
11262
11263 return 0;
11264 }
11265
11266 static int intel_default_queue_flip(struct drm_device *dev,
11267 struct drm_crtc *crtc,
11268 struct drm_framebuffer *fb,
11269 struct drm_i915_gem_object *obj,
11270 struct drm_i915_gem_request *req,
11271 uint32_t flags)
11272 {
11273 return -ENODEV;
11274 }
11275
11276 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11277 struct drm_crtc *crtc)
11278 {
11279 struct drm_i915_private *dev_priv = dev->dev_private;
11280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11281 struct intel_unpin_work *work = intel_crtc->unpin_work;
11282 u32 addr;
11283
11284 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11285 return true;
11286
11287 if (!work->enable_stall_check)
11288 return false;
11289
11290 if (work->flip_ready_vblank == 0) {
11291 if (work->flip_queued_req &&
11292 !i915_gem_request_completed(work->flip_queued_req, true))
11293 return false;
11294
11295 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11296 }
11297
11298 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11299 return false;
11300
11301 /* Potential stall - if we see that the flip has happened,
11302 * assume a missed interrupt. */
11303 if (INTEL_INFO(dev)->gen >= 4)
11304 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11305 else
11306 addr = I915_READ(DSPADDR(intel_crtc->plane));
11307
11308 /* There is a potential issue here with a false positive after a flip
11309 * to the same address. We could address this by checking for a
11310 * non-incrementing frame counter.
11311 */
11312 return addr == work->gtt_offset;
11313 }
11314
11315 void intel_check_page_flip(struct drm_device *dev, int pipe)
11316 {
11317 struct drm_i915_private *dev_priv = dev->dev_private;
11318 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11320 struct intel_unpin_work *work;
11321
11322 WARN_ON(!in_interrupt());
11323
11324 if (crtc == NULL)
11325 return;
11326
11327 spin_lock(&dev->event_lock);
11328 work = intel_crtc->unpin_work;
11329 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11330 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11331 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11332 page_flip_completed(intel_crtc);
11333 work = NULL;
11334 }
11335 if (work != NULL &&
11336 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11337 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11338 spin_unlock(&dev->event_lock);
11339 }
11340
11341 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11342 struct drm_framebuffer *fb,
11343 struct drm_pending_vblank_event *event,
11344 uint32_t page_flip_flags)
11345 {
11346 struct drm_device *dev = crtc->dev;
11347 struct drm_i915_private *dev_priv = dev->dev_private;
11348 struct drm_framebuffer *old_fb = crtc->primary->fb;
11349 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11351 struct drm_plane *primary = crtc->primary;
11352 enum pipe pipe = intel_crtc->pipe;
11353 struct intel_unpin_work *work;
11354 struct intel_engine_cs *ring;
11355 bool mmio_flip;
11356 struct drm_i915_gem_request *request = NULL;
11357 int ret;
11358
11359 /*
11360 * drm_mode_page_flip_ioctl() should already catch this, but double
11361 * check to be safe. In the future we may enable pageflipping from
11362 * a disabled primary plane.
11363 */
11364 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11365 return -EBUSY;
11366
11367 /* Can't change pixel format via MI display flips. */
11368 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11369 return -EINVAL;
11370
11371 /*
11372 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11373 * Note that pitch changes could also affect these register.
11374 */
11375 if (INTEL_INFO(dev)->gen > 3 &&
11376 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11377 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11378 return -EINVAL;
11379
11380 if (i915_terminally_wedged(&dev_priv->gpu_error))
11381 goto out_hang;
11382
11383 work = kzalloc(sizeof(*work), GFP_KERNEL);
11384 if (work == NULL)
11385 return -ENOMEM;
11386
11387 work->event = event;
11388 work->crtc = crtc;
11389 work->old_fb = old_fb;
11390 INIT_WORK(&work->work, intel_unpin_work_fn);
11391
11392 ret = drm_crtc_vblank_get(crtc);
11393 if (ret)
11394 goto free_work;
11395
11396 /* We borrow the event spin lock for protecting unpin_work */
11397 spin_lock_irq(&dev->event_lock);
11398 if (intel_crtc->unpin_work) {
11399 /* Before declaring the flip queue wedged, check if
11400 * the hardware completed the operation behind our backs.
11401 */
11402 if (__intel_pageflip_stall_check(dev, crtc)) {
11403 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11404 page_flip_completed(intel_crtc);
11405 } else {
11406 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11407 spin_unlock_irq(&dev->event_lock);
11408
11409 drm_crtc_vblank_put(crtc);
11410 kfree(work);
11411 return -EBUSY;
11412 }
11413 }
11414 intel_crtc->unpin_work = work;
11415 spin_unlock_irq(&dev->event_lock);
11416
11417 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11418 flush_workqueue(dev_priv->wq);
11419
11420 /* Reference the objects for the scheduled work. */
11421 drm_framebuffer_reference(work->old_fb);
11422 drm_gem_object_reference(&obj->base);
11423
11424 crtc->primary->fb = fb;
11425 update_state_fb(crtc->primary);
11426
11427 work->pending_flip_obj = obj;
11428
11429 ret = i915_mutex_lock_interruptible(dev);
11430 if (ret)
11431 goto cleanup;
11432
11433 atomic_inc(&intel_crtc->unpin_work_count);
11434 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11435
11436 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11437 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11438
11439 if (IS_VALLEYVIEW(dev)) {
11440 ring = &dev_priv->ring[BCS];
11441 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11442 /* vlv: DISPLAY_FLIP fails to change tiling */
11443 ring = NULL;
11444 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11445 ring = &dev_priv->ring[BCS];
11446 } else if (INTEL_INFO(dev)->gen >= 7) {
11447 ring = i915_gem_request_get_ring(obj->last_write_req);
11448 if (ring == NULL || ring->id != RCS)
11449 ring = &dev_priv->ring[BCS];
11450 } else {
11451 ring = &dev_priv->ring[RCS];
11452 }
11453
11454 mmio_flip = use_mmio_flip(ring, obj);
11455
11456 /* When using CS flips, we want to emit semaphores between rings.
11457 * However, when using mmio flips we will create a task to do the
11458 * synchronisation, so all we want here is to pin the framebuffer
11459 * into the display plane and skip any waits.
11460 */
11461 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11462 crtc->primary->state,
11463 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11464 if (ret)
11465 goto cleanup_pending;
11466
11467 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11468 + intel_crtc->dspaddr_offset;
11469
11470 if (mmio_flip) {
11471 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11472 page_flip_flags);
11473 if (ret)
11474 goto cleanup_unpin;
11475
11476 i915_gem_request_assign(&work->flip_queued_req,
11477 obj->last_write_req);
11478 } else {
11479 if (obj->last_write_req) {
11480 ret = i915_gem_check_olr(obj->last_write_req);
11481 if (ret)
11482 goto cleanup_unpin;
11483 }
11484
11485 if (!request) {
11486 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11487 if (ret)
11488 goto cleanup_unpin;
11489 }
11490
11491 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11492 page_flip_flags);
11493 if (ret)
11494 goto cleanup_unpin;
11495
11496 i915_gem_request_assign(&work->flip_queued_req, request);
11497 }
11498
11499 if (request)
11500 i915_add_request_no_flush(request->ring);
11501
11502 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11503 work->enable_stall_check = true;
11504
11505 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11506 INTEL_FRONTBUFFER_PRIMARY(pipe));
11507
11508 intel_fbc_disable(dev);
11509 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11510 mutex_unlock(&dev->struct_mutex);
11511
11512 trace_i915_flip_request(intel_crtc->plane, obj);
11513
11514 return 0;
11515
11516 cleanup_unpin:
11517 intel_unpin_fb_obj(fb, crtc->primary->state);
11518 cleanup_pending:
11519 if (request)
11520 i915_gem_request_cancel(request);
11521 atomic_dec(&intel_crtc->unpin_work_count);
11522 mutex_unlock(&dev->struct_mutex);
11523 cleanup:
11524 crtc->primary->fb = old_fb;
11525 update_state_fb(crtc->primary);
11526
11527 drm_gem_object_unreference_unlocked(&obj->base);
11528 drm_framebuffer_unreference(work->old_fb);
11529
11530 spin_lock_irq(&dev->event_lock);
11531 intel_crtc->unpin_work = NULL;
11532 spin_unlock_irq(&dev->event_lock);
11533
11534 drm_crtc_vblank_put(crtc);
11535 free_work:
11536 kfree(work);
11537
11538 if (ret == -EIO) {
11539 struct drm_atomic_state *state;
11540 struct drm_plane_state *plane_state;
11541
11542 out_hang:
11543 state = drm_atomic_state_alloc(dev);
11544 if (!state)
11545 return -ENOMEM;
11546 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11547
11548 retry:
11549 plane_state = drm_atomic_get_plane_state(state, primary);
11550 ret = PTR_ERR_OR_ZERO(plane_state);
11551 if (!ret) {
11552 drm_atomic_set_fb_for_plane(plane_state, fb);
11553
11554 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11555 if (!ret)
11556 ret = drm_atomic_commit(state);
11557 }
11558
11559 if (ret == -EDEADLK) {
11560 drm_modeset_backoff(state->acquire_ctx);
11561 drm_atomic_state_clear(state);
11562 goto retry;
11563 }
11564
11565 if (ret)
11566 drm_atomic_state_free(state);
11567
11568 if (ret == 0 && event) {
11569 spin_lock_irq(&dev->event_lock);
11570 drm_send_vblank_event(dev, pipe, event);
11571 spin_unlock_irq(&dev->event_lock);
11572 }
11573 }
11574 return ret;
11575 }
11576
11577
11578 /**
11579 * intel_wm_need_update - Check whether watermarks need updating
11580 * @plane: drm plane
11581 * @state: new plane state
11582 *
11583 * Check current plane state versus the new one to determine whether
11584 * watermarks need to be recalculated.
11585 *
11586 * Returns true or false.
11587 */
11588 static bool intel_wm_need_update(struct drm_plane *plane,
11589 struct drm_plane_state *state)
11590 {
11591 /* Update watermarks on tiling changes. */
11592 if (!plane->state->fb || !state->fb ||
11593 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11594 plane->state->rotation != state->rotation)
11595 return true;
11596
11597 if (plane->state->crtc_w != state->crtc_w)
11598 return true;
11599
11600 return false;
11601 }
11602
11603 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11604 struct drm_plane_state *plane_state)
11605 {
11606 struct drm_crtc *crtc = crtc_state->crtc;
11607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11608 struct drm_plane *plane = plane_state->plane;
11609 struct drm_device *dev = crtc->dev;
11610 struct drm_i915_private *dev_priv = dev->dev_private;
11611 struct intel_plane_state *old_plane_state =
11612 to_intel_plane_state(plane->state);
11613 int idx = intel_crtc->base.base.id, ret;
11614 int i = drm_plane_index(plane);
11615 bool mode_changed = needs_modeset(crtc_state);
11616 bool was_crtc_enabled = crtc->state->active;
11617 bool is_crtc_enabled = crtc_state->active;
11618
11619 bool turn_off, turn_on, visible, was_visible;
11620 struct drm_framebuffer *fb = plane_state->fb;
11621
11622 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11623 plane->type != DRM_PLANE_TYPE_CURSOR) {
11624 ret = skl_update_scaler_plane(
11625 to_intel_crtc_state(crtc_state),
11626 to_intel_plane_state(plane_state));
11627 if (ret)
11628 return ret;
11629 }
11630
11631 /*
11632 * Disabling a plane is always okay; we just need to update
11633 * fb tracking in a special way since cleanup_fb() won't
11634 * get called by the plane helpers.
11635 */
11636 if (old_plane_state->base.fb && !fb)
11637 intel_crtc->atomic.disabled_planes |= 1 << i;
11638
11639 was_visible = old_plane_state->visible;
11640 visible = to_intel_plane_state(plane_state)->visible;
11641
11642 if (!was_crtc_enabled && WARN_ON(was_visible))
11643 was_visible = false;
11644
11645 if (!is_crtc_enabled && WARN_ON(visible))
11646 visible = false;
11647
11648 if (!was_visible && !visible)
11649 return 0;
11650
11651 turn_off = was_visible && (!visible || mode_changed);
11652 turn_on = visible && (!was_visible || mode_changed);
11653
11654 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11655 plane->base.id, fb ? fb->base.id : -1);
11656
11657 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11658 plane->base.id, was_visible, visible,
11659 turn_off, turn_on, mode_changed);
11660
11661 if (intel_wm_need_update(plane, plane_state))
11662 intel_crtc->atomic.update_wm = true;
11663
11664 switch (plane->type) {
11665 case DRM_PLANE_TYPE_PRIMARY:
11666 if (visible)
11667 intel_crtc->atomic.fb_bits |=
11668 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11669
11670 intel_crtc->atomic.wait_for_flips = true;
11671 intel_crtc->atomic.pre_disable_primary = turn_off;
11672 intel_crtc->atomic.post_enable_primary = turn_on;
11673
11674 if (turn_off)
11675 intel_crtc->atomic.disable_fbc = true;
11676
11677 /*
11678 * FBC does not work on some platforms for rotated
11679 * planes, so disable it when rotation is not 0 and
11680 * update it when rotation is set back to 0.
11681 *
11682 * FIXME: This is redundant with the fbc update done in
11683 * the primary plane enable function except that that
11684 * one is done too late. We eventually need to unify
11685 * this.
11686 */
11687
11688 if (visible &&
11689 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11690 dev_priv->fbc.crtc == intel_crtc &&
11691 plane_state->rotation != BIT(DRM_ROTATE_0))
11692 intel_crtc->atomic.disable_fbc = true;
11693
11694 /*
11695 * BDW signals flip done immediately if the plane
11696 * is disabled, even if the plane enable is already
11697 * armed to occur at the next vblank :(
11698 */
11699 if (turn_on && IS_BROADWELL(dev))
11700 intel_crtc->atomic.wait_vblank = true;
11701
11702 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11703 break;
11704 case DRM_PLANE_TYPE_CURSOR:
11705 if (visible)
11706 intel_crtc->atomic.fb_bits |=
11707 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
11708 break;
11709 case DRM_PLANE_TYPE_OVERLAY:
11710 /*
11711 * 'prepare' is never called when plane is being disabled, so
11712 * we need to handle frontbuffer tracking as a special case
11713 */
11714 if (visible)
11715 intel_crtc->atomic.fb_bits |=
11716 INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
11717
11718 if (turn_off && !mode_changed) {
11719 intel_crtc->atomic.wait_vblank = true;
11720 intel_crtc->atomic.update_sprite_watermarks |=
11721 1 << i;
11722 }
11723 break;
11724 }
11725 return 0;
11726 }
11727
11728 static bool encoders_cloneable(const struct intel_encoder *a,
11729 const struct intel_encoder *b)
11730 {
11731 /* masks could be asymmetric, so check both ways */
11732 return a == b || (a->cloneable & (1 << b->type) &&
11733 b->cloneable & (1 << a->type));
11734 }
11735
11736 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11737 struct intel_crtc *crtc,
11738 struct intel_encoder *encoder)
11739 {
11740 struct intel_encoder *source_encoder;
11741 struct drm_connector *connector;
11742 struct drm_connector_state *connector_state;
11743 int i;
11744
11745 for_each_connector_in_state(state, connector, connector_state, i) {
11746 if (connector_state->crtc != &crtc->base)
11747 continue;
11748
11749 source_encoder =
11750 to_intel_encoder(connector_state->best_encoder);
11751 if (!encoders_cloneable(encoder, source_encoder))
11752 return false;
11753 }
11754
11755 return true;
11756 }
11757
11758 static bool check_encoder_cloning(struct drm_atomic_state *state,
11759 struct intel_crtc *crtc)
11760 {
11761 struct intel_encoder *encoder;
11762 struct drm_connector *connector;
11763 struct drm_connector_state *connector_state;
11764 int i;
11765
11766 for_each_connector_in_state(state, connector, connector_state, i) {
11767 if (connector_state->crtc != &crtc->base)
11768 continue;
11769
11770 encoder = to_intel_encoder(connector_state->best_encoder);
11771 if (!check_single_encoder_cloning(state, crtc, encoder))
11772 return false;
11773 }
11774
11775 return true;
11776 }
11777
11778 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11779 struct drm_crtc_state *crtc_state)
11780 {
11781 struct intel_crtc_state *pipe_config =
11782 to_intel_crtc_state(crtc_state);
11783 struct drm_plane *p;
11784 unsigned visible_mask = 0;
11785
11786 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11787 struct drm_plane_state *plane_state =
11788 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11789
11790 if (WARN_ON(!plane_state))
11791 continue;
11792
11793 if (!plane_state->fb)
11794 crtc_state->plane_mask &=
11795 ~(1 << drm_plane_index(p));
11796 else if (to_intel_plane_state(plane_state)->visible)
11797 visible_mask |= 1 << drm_plane_index(p);
11798 }
11799
11800 if (!visible_mask)
11801 return;
11802
11803 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11804 }
11805
11806 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11807 struct drm_crtc_state *crtc_state)
11808 {
11809 struct drm_device *dev = crtc->dev;
11810 struct drm_i915_private *dev_priv = dev->dev_private;
11811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11812 struct intel_crtc_state *pipe_config =
11813 to_intel_crtc_state(crtc_state);
11814 struct drm_atomic_state *state = crtc_state->state;
11815 int ret, idx = crtc->base.id;
11816 bool mode_changed = needs_modeset(crtc_state);
11817
11818 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11819 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11820 return -EINVAL;
11821 }
11822
11823 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11824 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11825 idx, crtc->state->active, intel_crtc->active);
11826
11827 /* plane mask is fixed up after all initial planes are calculated */
11828 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11829 intel_crtc_check_initial_planes(crtc, crtc_state);
11830
11831 if (mode_changed)
11832 intel_crtc->atomic.update_wm = !crtc_state->active;
11833
11834 if (mode_changed && crtc_state->enable &&
11835 dev_priv->display.crtc_compute_clock &&
11836 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11837 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11838 pipe_config);
11839 if (ret)
11840 return ret;
11841 }
11842
11843 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11844 }
11845
11846 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11847 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11848 .load_lut = intel_crtc_load_lut,
11849 .atomic_begin = intel_begin_crtc_commit,
11850 .atomic_flush = intel_finish_crtc_commit,
11851 .atomic_check = intel_crtc_atomic_check,
11852 };
11853
11854 /**
11855 * intel_modeset_update_staged_output_state
11856 *
11857 * Updates the staged output configuration state, e.g. after we've read out the
11858 * current hw state.
11859 */
11860 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11861 {
11862 struct intel_crtc *crtc;
11863 struct intel_encoder *encoder;
11864 struct intel_connector *connector;
11865
11866 for_each_intel_connector(dev, connector) {
11867 connector->new_encoder =
11868 to_intel_encoder(connector->base.encoder);
11869 }
11870
11871 for_each_intel_encoder(dev, encoder) {
11872 encoder->new_crtc =
11873 to_intel_crtc(encoder->base.crtc);
11874 }
11875
11876 for_each_intel_crtc(dev, crtc) {
11877 crtc->new_enabled = crtc->base.state->enable;
11878 }
11879 }
11880
11881 /* Transitional helper to copy current connector/encoder state to
11882 * connector->state. This is needed so that code that is partially
11883 * converted to atomic does the right thing.
11884 */
11885 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11886 {
11887 struct intel_connector *connector;
11888
11889 for_each_intel_connector(dev, connector) {
11890 if (connector->base.encoder) {
11891 connector->base.state->best_encoder =
11892 connector->base.encoder;
11893 connector->base.state->crtc =
11894 connector->base.encoder->crtc;
11895 } else {
11896 connector->base.state->best_encoder = NULL;
11897 connector->base.state->crtc = NULL;
11898 }
11899 }
11900 }
11901
11902 static void
11903 connected_sink_compute_bpp(struct intel_connector *connector,
11904 struct intel_crtc_state *pipe_config)
11905 {
11906 int bpp = pipe_config->pipe_bpp;
11907
11908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11909 connector->base.base.id,
11910 connector->base.name);
11911
11912 /* Don't use an invalid EDID bpc value */
11913 if (connector->base.display_info.bpc &&
11914 connector->base.display_info.bpc * 3 < bpp) {
11915 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11916 bpp, connector->base.display_info.bpc*3);
11917 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11918 }
11919
11920 /* Clamp bpp to 8 on screens without EDID 1.4 */
11921 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11922 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11923 bpp);
11924 pipe_config->pipe_bpp = 24;
11925 }
11926 }
11927
11928 static int
11929 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11930 struct intel_crtc_state *pipe_config)
11931 {
11932 struct drm_device *dev = crtc->base.dev;
11933 struct drm_atomic_state *state;
11934 struct drm_connector *connector;
11935 struct drm_connector_state *connector_state;
11936 int bpp, i;
11937
11938 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11939 bpp = 10*3;
11940 else if (INTEL_INFO(dev)->gen >= 5)
11941 bpp = 12*3;
11942 else
11943 bpp = 8*3;
11944
11945
11946 pipe_config->pipe_bpp = bpp;
11947
11948 state = pipe_config->base.state;
11949
11950 /* Clamp display bpp to EDID value */
11951 for_each_connector_in_state(state, connector, connector_state, i) {
11952 if (connector_state->crtc != &crtc->base)
11953 continue;
11954
11955 connected_sink_compute_bpp(to_intel_connector(connector),
11956 pipe_config);
11957 }
11958
11959 return bpp;
11960 }
11961
11962 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11963 {
11964 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11965 "type: 0x%x flags: 0x%x\n",
11966 mode->crtc_clock,
11967 mode->crtc_hdisplay, mode->crtc_hsync_start,
11968 mode->crtc_hsync_end, mode->crtc_htotal,
11969 mode->crtc_vdisplay, mode->crtc_vsync_start,
11970 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11971 }
11972
11973 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11974 struct intel_crtc_state *pipe_config,
11975 const char *context)
11976 {
11977 struct drm_device *dev = crtc->base.dev;
11978 struct drm_plane *plane;
11979 struct intel_plane *intel_plane;
11980 struct intel_plane_state *state;
11981 struct drm_framebuffer *fb;
11982
11983 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11984 context, pipe_config, pipe_name(crtc->pipe));
11985
11986 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11987 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11988 pipe_config->pipe_bpp, pipe_config->dither);
11989 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11990 pipe_config->has_pch_encoder,
11991 pipe_config->fdi_lanes,
11992 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11993 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11994 pipe_config->fdi_m_n.tu);
11995 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11996 pipe_config->has_dp_encoder,
11997 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11998 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11999 pipe_config->dp_m_n.tu);
12000
12001 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12002 pipe_config->has_dp_encoder,
12003 pipe_config->dp_m2_n2.gmch_m,
12004 pipe_config->dp_m2_n2.gmch_n,
12005 pipe_config->dp_m2_n2.link_m,
12006 pipe_config->dp_m2_n2.link_n,
12007 pipe_config->dp_m2_n2.tu);
12008
12009 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12010 pipe_config->has_audio,
12011 pipe_config->has_infoframe);
12012
12013 DRM_DEBUG_KMS("requested mode:\n");
12014 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12015 DRM_DEBUG_KMS("adjusted mode:\n");
12016 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12017 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12018 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12019 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12020 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12021 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12022 crtc->num_scalers,
12023 pipe_config->scaler_state.scaler_users,
12024 pipe_config->scaler_state.scaler_id);
12025 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12026 pipe_config->gmch_pfit.control,
12027 pipe_config->gmch_pfit.pgm_ratios,
12028 pipe_config->gmch_pfit.lvds_border_bits);
12029 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12030 pipe_config->pch_pfit.pos,
12031 pipe_config->pch_pfit.size,
12032 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12033 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12034 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12035
12036 if (IS_BROXTON(dev)) {
12037 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
12038 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12039 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
12040 pipe_config->ddi_pll_sel,
12041 pipe_config->dpll_hw_state.ebb0,
12042 pipe_config->dpll_hw_state.pll0,
12043 pipe_config->dpll_hw_state.pll1,
12044 pipe_config->dpll_hw_state.pll2,
12045 pipe_config->dpll_hw_state.pll3,
12046 pipe_config->dpll_hw_state.pll6,
12047 pipe_config->dpll_hw_state.pll8,
12048 pipe_config->dpll_hw_state.pcsdw12);
12049 } else if (IS_SKYLAKE(dev)) {
12050 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12051 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12052 pipe_config->ddi_pll_sel,
12053 pipe_config->dpll_hw_state.ctrl1,
12054 pipe_config->dpll_hw_state.cfgcr1,
12055 pipe_config->dpll_hw_state.cfgcr2);
12056 } else if (HAS_DDI(dev)) {
12057 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12058 pipe_config->ddi_pll_sel,
12059 pipe_config->dpll_hw_state.wrpll);
12060 } else {
12061 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12062 "fp0: 0x%x, fp1: 0x%x\n",
12063 pipe_config->dpll_hw_state.dpll,
12064 pipe_config->dpll_hw_state.dpll_md,
12065 pipe_config->dpll_hw_state.fp0,
12066 pipe_config->dpll_hw_state.fp1);
12067 }
12068
12069 DRM_DEBUG_KMS("planes on this crtc\n");
12070 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12071 intel_plane = to_intel_plane(plane);
12072 if (intel_plane->pipe != crtc->pipe)
12073 continue;
12074
12075 state = to_intel_plane_state(plane->state);
12076 fb = state->base.fb;
12077 if (!fb) {
12078 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12079 "disabled, scaler_id = %d\n",
12080 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12081 plane->base.id, intel_plane->pipe,
12082 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12083 drm_plane_index(plane), state->scaler_id);
12084 continue;
12085 }
12086
12087 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12088 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12089 plane->base.id, intel_plane->pipe,
12090 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12091 drm_plane_index(plane));
12092 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12093 fb->base.id, fb->width, fb->height, fb->pixel_format);
12094 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12095 state->scaler_id,
12096 state->src.x1 >> 16, state->src.y1 >> 16,
12097 drm_rect_width(&state->src) >> 16,
12098 drm_rect_height(&state->src) >> 16,
12099 state->dst.x1, state->dst.y1,
12100 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12101 }
12102 }
12103
12104 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12105 {
12106 struct drm_device *dev = state->dev;
12107 struct intel_encoder *encoder;
12108 struct drm_connector *connector;
12109 struct drm_connector_state *connector_state;
12110 unsigned int used_ports = 0;
12111 int i;
12112
12113 /*
12114 * Walk the connector list instead of the encoder
12115 * list to detect the problem on ddi platforms
12116 * where there's just one encoder per digital port.
12117 */
12118 for_each_connector_in_state(state, connector, connector_state, i) {
12119 if (!connector_state->best_encoder)
12120 continue;
12121
12122 encoder = to_intel_encoder(connector_state->best_encoder);
12123
12124 WARN_ON(!connector_state->crtc);
12125
12126 switch (encoder->type) {
12127 unsigned int port_mask;
12128 case INTEL_OUTPUT_UNKNOWN:
12129 if (WARN_ON(!HAS_DDI(dev)))
12130 break;
12131 case INTEL_OUTPUT_DISPLAYPORT:
12132 case INTEL_OUTPUT_HDMI:
12133 case INTEL_OUTPUT_EDP:
12134 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12135
12136 /* the same port mustn't appear more than once */
12137 if (used_ports & port_mask)
12138 return false;
12139
12140 used_ports |= port_mask;
12141 default:
12142 break;
12143 }
12144 }
12145
12146 return true;
12147 }
12148
12149 static void
12150 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12151 {
12152 struct drm_crtc_state tmp_state;
12153 struct intel_crtc_scaler_state scaler_state;
12154 struct intel_dpll_hw_state dpll_hw_state;
12155 enum intel_dpll_id shared_dpll;
12156 uint32_t ddi_pll_sel;
12157
12158 /* FIXME: before the switch to atomic started, a new pipe_config was
12159 * kzalloc'd. Code that depends on any field being zero should be
12160 * fixed, so that the crtc_state can be safely duplicated. For now,
12161 * only fields that are know to not cause problems are preserved. */
12162
12163 tmp_state = crtc_state->base;
12164 scaler_state = crtc_state->scaler_state;
12165 shared_dpll = crtc_state->shared_dpll;
12166 dpll_hw_state = crtc_state->dpll_hw_state;
12167 ddi_pll_sel = crtc_state->ddi_pll_sel;
12168
12169 memset(crtc_state, 0, sizeof *crtc_state);
12170
12171 crtc_state->base = tmp_state;
12172 crtc_state->scaler_state = scaler_state;
12173 crtc_state->shared_dpll = shared_dpll;
12174 crtc_state->dpll_hw_state = dpll_hw_state;
12175 crtc_state->ddi_pll_sel = ddi_pll_sel;
12176 }
12177
12178 static int
12179 intel_modeset_pipe_config(struct drm_crtc *crtc,
12180 struct intel_crtc_state *pipe_config)
12181 {
12182 struct drm_atomic_state *state = pipe_config->base.state;
12183 struct intel_encoder *encoder;
12184 struct drm_connector *connector;
12185 struct drm_connector_state *connector_state;
12186 int base_bpp, ret = -EINVAL;
12187 int i;
12188 bool retry = true;
12189
12190 clear_intel_crtc_state(pipe_config);
12191
12192 pipe_config->cpu_transcoder =
12193 (enum transcoder) to_intel_crtc(crtc)->pipe;
12194
12195 /*
12196 * Sanitize sync polarity flags based on requested ones. If neither
12197 * positive or negative polarity is requested, treat this as meaning
12198 * negative polarity.
12199 */
12200 if (!(pipe_config->base.adjusted_mode.flags &
12201 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12202 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12203
12204 if (!(pipe_config->base.adjusted_mode.flags &
12205 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12206 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12207
12208 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12209 * plane pixel format and any sink constraints into account. Returns the
12210 * source plane bpp so that dithering can be selected on mismatches
12211 * after encoders and crtc also have had their say. */
12212 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12213 pipe_config);
12214 if (base_bpp < 0)
12215 goto fail;
12216
12217 /*
12218 * Determine the real pipe dimensions. Note that stereo modes can
12219 * increase the actual pipe size due to the frame doubling and
12220 * insertion of additional space for blanks between the frame. This
12221 * is stored in the crtc timings. We use the requested mode to do this
12222 * computation to clearly distinguish it from the adjusted mode, which
12223 * can be changed by the connectors in the below retry loop.
12224 */
12225 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12226 &pipe_config->pipe_src_w,
12227 &pipe_config->pipe_src_h);
12228
12229 encoder_retry:
12230 /* Ensure the port clock defaults are reset when retrying. */
12231 pipe_config->port_clock = 0;
12232 pipe_config->pixel_multiplier = 1;
12233
12234 /* Fill in default crtc timings, allow encoders to overwrite them. */
12235 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12236 CRTC_STEREO_DOUBLE);
12237
12238 /* Pass our mode to the connectors and the CRTC to give them a chance to
12239 * adjust it according to limitations or connector properties, and also
12240 * a chance to reject the mode entirely.
12241 */
12242 for_each_connector_in_state(state, connector, connector_state, i) {
12243 if (connector_state->crtc != crtc)
12244 continue;
12245
12246 encoder = to_intel_encoder(connector_state->best_encoder);
12247
12248 if (!(encoder->compute_config(encoder, pipe_config))) {
12249 DRM_DEBUG_KMS("Encoder config failure\n");
12250 goto fail;
12251 }
12252 }
12253
12254 /* Set default port clock if not overwritten by the encoder. Needs to be
12255 * done afterwards in case the encoder adjusts the mode. */
12256 if (!pipe_config->port_clock)
12257 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12258 * pipe_config->pixel_multiplier;
12259
12260 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12261 if (ret < 0) {
12262 DRM_DEBUG_KMS("CRTC fixup failed\n");
12263 goto fail;
12264 }
12265
12266 if (ret == RETRY) {
12267 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12268 ret = -EINVAL;
12269 goto fail;
12270 }
12271
12272 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12273 retry = false;
12274 goto encoder_retry;
12275 }
12276
12277 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12278 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12279 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12280
12281 /* Check if we need to force a modeset */
12282 if (pipe_config->has_audio !=
12283 to_intel_crtc_state(crtc->state)->has_audio) {
12284 pipe_config->base.mode_changed = true;
12285 ret = drm_atomic_add_affected_planes(state, crtc);
12286 }
12287
12288 /*
12289 * Note we have an issue here with infoframes: current code
12290 * only updates them on the full mode set path per hw
12291 * requirements. So here we should be checking for any
12292 * required changes and forcing a mode set.
12293 */
12294 fail:
12295 return ret;
12296 }
12297
12298 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12299 {
12300 struct drm_encoder *encoder;
12301 struct drm_device *dev = crtc->dev;
12302
12303 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12304 if (encoder->crtc == crtc)
12305 return true;
12306
12307 return false;
12308 }
12309
12310 static void
12311 intel_modeset_update_state(struct drm_atomic_state *state)
12312 {
12313 struct drm_device *dev = state->dev;
12314 struct intel_encoder *intel_encoder;
12315 struct drm_crtc *crtc;
12316 struct drm_crtc_state *crtc_state;
12317 struct drm_connector *connector;
12318
12319 intel_shared_dpll_commit(state);
12320
12321 for_each_intel_encoder(dev, intel_encoder) {
12322 if (!intel_encoder->base.crtc)
12323 continue;
12324
12325 crtc = intel_encoder->base.crtc;
12326 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12327 if (!crtc_state || !needs_modeset(crtc->state))
12328 continue;
12329
12330 intel_encoder->connectors_active = false;
12331 }
12332
12333 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12334 intel_modeset_update_staged_output_state(state->dev);
12335
12336 /* Double check state. */
12337 for_each_crtc(dev, crtc) {
12338 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12339
12340 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12341
12342 /* Update hwmode for vblank functions */
12343 if (crtc->state->active)
12344 crtc->hwmode = crtc->state->adjusted_mode;
12345 else
12346 crtc->hwmode.crtc_clock = 0;
12347 }
12348
12349 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12350 if (!connector->encoder || !connector->encoder->crtc)
12351 continue;
12352
12353 crtc = connector->encoder->crtc;
12354 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12355 if (!crtc_state || !needs_modeset(crtc->state))
12356 continue;
12357
12358 if (crtc->state->active) {
12359 struct drm_property *dpms_property =
12360 dev->mode_config.dpms_property;
12361
12362 connector->dpms = DRM_MODE_DPMS_ON;
12363 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12364
12365 intel_encoder = to_intel_encoder(connector->encoder);
12366 intel_encoder->connectors_active = true;
12367 } else
12368 connector->dpms = DRM_MODE_DPMS_OFF;
12369 }
12370 }
12371
12372 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12373 {
12374 int diff;
12375
12376 if (clock1 == clock2)
12377 return true;
12378
12379 if (!clock1 || !clock2)
12380 return false;
12381
12382 diff = abs(clock1 - clock2);
12383
12384 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12385 return true;
12386
12387 return false;
12388 }
12389
12390 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12391 list_for_each_entry((intel_crtc), \
12392 &(dev)->mode_config.crtc_list, \
12393 base.head) \
12394 if (mask & (1 <<(intel_crtc)->pipe))
12395
12396 static bool
12397 intel_pipe_config_compare(struct drm_device *dev,
12398 struct intel_crtc_state *current_config,
12399 struct intel_crtc_state *pipe_config)
12400 {
12401 #define PIPE_CONF_CHECK_X(name) \
12402 if (current_config->name != pipe_config->name) { \
12403 DRM_ERROR("mismatch in " #name " " \
12404 "(expected 0x%08x, found 0x%08x)\n", \
12405 current_config->name, \
12406 pipe_config->name); \
12407 return false; \
12408 }
12409
12410 #define PIPE_CONF_CHECK_I(name) \
12411 if (current_config->name != pipe_config->name) { \
12412 DRM_ERROR("mismatch in " #name " " \
12413 "(expected %i, found %i)\n", \
12414 current_config->name, \
12415 pipe_config->name); \
12416 return false; \
12417 }
12418
12419 /* This is required for BDW+ where there is only one set of registers for
12420 * switching between high and low RR.
12421 * This macro can be used whenever a comparison has to be made between one
12422 * hw state and multiple sw state variables.
12423 */
12424 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12425 if ((current_config->name != pipe_config->name) && \
12426 (current_config->alt_name != pipe_config->name)) { \
12427 DRM_ERROR("mismatch in " #name " " \
12428 "(expected %i or %i, found %i)\n", \
12429 current_config->name, \
12430 current_config->alt_name, \
12431 pipe_config->name); \
12432 return false; \
12433 }
12434
12435 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12436 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12437 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12438 "(expected %i, found %i)\n", \
12439 current_config->name & (mask), \
12440 pipe_config->name & (mask)); \
12441 return false; \
12442 }
12443
12444 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12445 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12446 DRM_ERROR("mismatch in " #name " " \
12447 "(expected %i, found %i)\n", \
12448 current_config->name, \
12449 pipe_config->name); \
12450 return false; \
12451 }
12452
12453 #define PIPE_CONF_QUIRK(quirk) \
12454 ((current_config->quirks | pipe_config->quirks) & (quirk))
12455
12456 PIPE_CONF_CHECK_I(cpu_transcoder);
12457
12458 PIPE_CONF_CHECK_I(has_pch_encoder);
12459 PIPE_CONF_CHECK_I(fdi_lanes);
12460 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12461 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12462 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12463 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12464 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12465
12466 PIPE_CONF_CHECK_I(has_dp_encoder);
12467
12468 if (INTEL_INFO(dev)->gen < 8) {
12469 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12470 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12471 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12472 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12473 PIPE_CONF_CHECK_I(dp_m_n.tu);
12474
12475 if (current_config->has_drrs) {
12476 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12477 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12478 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12479 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12480 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12481 }
12482 } else {
12483 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12484 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12485 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12486 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12487 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12488 }
12489
12490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12491 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12493 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12494 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12495 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12496
12497 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12498 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12499 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12500 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12501 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12502 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12503
12504 PIPE_CONF_CHECK_I(pixel_multiplier);
12505 PIPE_CONF_CHECK_I(has_hdmi_sink);
12506 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12507 IS_VALLEYVIEW(dev))
12508 PIPE_CONF_CHECK_I(limited_color_range);
12509 PIPE_CONF_CHECK_I(has_infoframe);
12510
12511 PIPE_CONF_CHECK_I(has_audio);
12512
12513 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12514 DRM_MODE_FLAG_INTERLACE);
12515
12516 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12517 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12518 DRM_MODE_FLAG_PHSYNC);
12519 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12520 DRM_MODE_FLAG_NHSYNC);
12521 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12522 DRM_MODE_FLAG_PVSYNC);
12523 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12524 DRM_MODE_FLAG_NVSYNC);
12525 }
12526
12527 PIPE_CONF_CHECK_I(pipe_src_w);
12528 PIPE_CONF_CHECK_I(pipe_src_h);
12529
12530 /*
12531 * FIXME: BIOS likes to set up a cloned config with lvds+external
12532 * screen. Since we don't yet re-compute the pipe config when moving
12533 * just the lvds port away to another pipe the sw tracking won't match.
12534 *
12535 * Proper atomic modesets with recomputed global state will fix this.
12536 * Until then just don't check gmch state for inherited modes.
12537 */
12538 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12539 PIPE_CONF_CHECK_I(gmch_pfit.control);
12540 /* pfit ratios are autocomputed by the hw on gen4+ */
12541 if (INTEL_INFO(dev)->gen < 4)
12542 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12543 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12544 }
12545
12546 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12547 if (current_config->pch_pfit.enabled) {
12548 PIPE_CONF_CHECK_I(pch_pfit.pos);
12549 PIPE_CONF_CHECK_I(pch_pfit.size);
12550 }
12551
12552 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12553
12554 /* BDW+ don't expose a synchronous way to read the state */
12555 if (IS_HASWELL(dev))
12556 PIPE_CONF_CHECK_I(ips_enabled);
12557
12558 PIPE_CONF_CHECK_I(double_wide);
12559
12560 PIPE_CONF_CHECK_X(ddi_pll_sel);
12561
12562 PIPE_CONF_CHECK_I(shared_dpll);
12563 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12564 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12565 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12566 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12567 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12568 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12569 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12570 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12571
12572 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12573 PIPE_CONF_CHECK_I(pipe_bpp);
12574
12575 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12576 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12577
12578 #undef PIPE_CONF_CHECK_X
12579 #undef PIPE_CONF_CHECK_I
12580 #undef PIPE_CONF_CHECK_I_ALT
12581 #undef PIPE_CONF_CHECK_FLAGS
12582 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12583 #undef PIPE_CONF_QUIRK
12584
12585 return true;
12586 }
12587
12588 static void check_wm_state(struct drm_device *dev)
12589 {
12590 struct drm_i915_private *dev_priv = dev->dev_private;
12591 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12592 struct intel_crtc *intel_crtc;
12593 int plane;
12594
12595 if (INTEL_INFO(dev)->gen < 9)
12596 return;
12597
12598 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12599 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12600
12601 for_each_intel_crtc(dev, intel_crtc) {
12602 struct skl_ddb_entry *hw_entry, *sw_entry;
12603 const enum pipe pipe = intel_crtc->pipe;
12604
12605 if (!intel_crtc->active)
12606 continue;
12607
12608 /* planes */
12609 for_each_plane(dev_priv, pipe, plane) {
12610 hw_entry = &hw_ddb.plane[pipe][plane];
12611 sw_entry = &sw_ddb->plane[pipe][plane];
12612
12613 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12614 continue;
12615
12616 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12617 "(expected (%u,%u), found (%u,%u))\n",
12618 pipe_name(pipe), plane + 1,
12619 sw_entry->start, sw_entry->end,
12620 hw_entry->start, hw_entry->end);
12621 }
12622
12623 /* cursor */
12624 hw_entry = &hw_ddb.cursor[pipe];
12625 sw_entry = &sw_ddb->cursor[pipe];
12626
12627 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12628 continue;
12629
12630 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12631 "(expected (%u,%u), found (%u,%u))\n",
12632 pipe_name(pipe),
12633 sw_entry->start, sw_entry->end,
12634 hw_entry->start, hw_entry->end);
12635 }
12636 }
12637
12638 static void
12639 check_connector_state(struct drm_device *dev)
12640 {
12641 struct intel_connector *connector;
12642
12643 for_each_intel_connector(dev, connector) {
12644 /* This also checks the encoder/connector hw state with the
12645 * ->get_hw_state callbacks. */
12646 intel_connector_check_state(connector);
12647
12648 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12649 "connector's staged encoder doesn't match current encoder\n");
12650 }
12651 }
12652
12653 static void
12654 check_encoder_state(struct drm_device *dev)
12655 {
12656 struct intel_encoder *encoder;
12657 struct intel_connector *connector;
12658
12659 for_each_intel_encoder(dev, encoder) {
12660 bool enabled = false;
12661 bool active = false;
12662 enum pipe pipe, tracked_pipe;
12663
12664 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12665 encoder->base.base.id,
12666 encoder->base.name);
12667
12668 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12669 "encoder's stage crtc doesn't match current crtc\n");
12670 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12671 "encoder's active_connectors set, but no crtc\n");
12672
12673 for_each_intel_connector(dev, connector) {
12674 if (connector->base.encoder != &encoder->base)
12675 continue;
12676 enabled = true;
12677 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12678 active = true;
12679 }
12680 /*
12681 * for MST connectors if we unplug the connector is gone
12682 * away but the encoder is still connected to a crtc
12683 * until a modeset happens in response to the hotplug.
12684 */
12685 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12686 continue;
12687
12688 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12689 "encoder's enabled state mismatch "
12690 "(expected %i, found %i)\n",
12691 !!encoder->base.crtc, enabled);
12692 I915_STATE_WARN(active && !encoder->base.crtc,
12693 "active encoder with no crtc\n");
12694
12695 I915_STATE_WARN(encoder->connectors_active != active,
12696 "encoder's computed active state doesn't match tracked active state "
12697 "(expected %i, found %i)\n", active, encoder->connectors_active);
12698
12699 active = encoder->get_hw_state(encoder, &pipe);
12700 I915_STATE_WARN(active != encoder->connectors_active,
12701 "encoder's hw state doesn't match sw tracking "
12702 "(expected %i, found %i)\n",
12703 encoder->connectors_active, active);
12704
12705 if (!encoder->base.crtc)
12706 continue;
12707
12708 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12709 I915_STATE_WARN(active && pipe != tracked_pipe,
12710 "active encoder's pipe doesn't match"
12711 "(expected %i, found %i)\n",
12712 tracked_pipe, pipe);
12713
12714 }
12715 }
12716
12717 static void
12718 check_crtc_state(struct drm_device *dev)
12719 {
12720 struct drm_i915_private *dev_priv = dev->dev_private;
12721 struct intel_crtc *crtc;
12722 struct intel_encoder *encoder;
12723 struct intel_crtc_state pipe_config;
12724
12725 for_each_intel_crtc(dev, crtc) {
12726 bool enabled = false;
12727 bool active = false;
12728
12729 memset(&pipe_config, 0, sizeof(pipe_config));
12730
12731 DRM_DEBUG_KMS("[CRTC:%d]\n",
12732 crtc->base.base.id);
12733
12734 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12735 "active crtc, but not enabled in sw tracking\n");
12736
12737 for_each_intel_encoder(dev, encoder) {
12738 if (encoder->base.crtc != &crtc->base)
12739 continue;
12740 enabled = true;
12741 if (encoder->connectors_active)
12742 active = true;
12743 }
12744
12745 I915_STATE_WARN(active != crtc->active,
12746 "crtc's computed active state doesn't match tracked active state "
12747 "(expected %i, found %i)\n", active, crtc->active);
12748 I915_STATE_WARN(enabled != crtc->base.state->enable,
12749 "crtc's computed enabled state doesn't match tracked enabled state "
12750 "(expected %i, found %i)\n", enabled,
12751 crtc->base.state->enable);
12752
12753 active = dev_priv->display.get_pipe_config(crtc,
12754 &pipe_config);
12755
12756 /* hw state is inconsistent with the pipe quirk */
12757 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12758 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12759 active = crtc->active;
12760
12761 for_each_intel_encoder(dev, encoder) {
12762 enum pipe pipe;
12763 if (encoder->base.crtc != &crtc->base)
12764 continue;
12765 if (encoder->get_hw_state(encoder, &pipe))
12766 encoder->get_config(encoder, &pipe_config);
12767 }
12768
12769 I915_STATE_WARN(crtc->active != active,
12770 "crtc active state doesn't match with hw state "
12771 "(expected %i, found %i)\n", crtc->active, active);
12772
12773 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12774 "transitional active state does not match atomic hw state "
12775 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12776
12777 if (active &&
12778 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12779 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12780 intel_dump_pipe_config(crtc, &pipe_config,
12781 "[hw state]");
12782 intel_dump_pipe_config(crtc, crtc->config,
12783 "[sw state]");
12784 }
12785 }
12786 }
12787
12788 static void
12789 check_shared_dpll_state(struct drm_device *dev)
12790 {
12791 struct drm_i915_private *dev_priv = dev->dev_private;
12792 struct intel_crtc *crtc;
12793 struct intel_dpll_hw_state dpll_hw_state;
12794 int i;
12795
12796 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12797 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12798 int enabled_crtcs = 0, active_crtcs = 0;
12799 bool active;
12800
12801 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12802
12803 DRM_DEBUG_KMS("%s\n", pll->name);
12804
12805 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12806
12807 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12808 "more active pll users than references: %i vs %i\n",
12809 pll->active, hweight32(pll->config.crtc_mask));
12810 I915_STATE_WARN(pll->active && !pll->on,
12811 "pll in active use but not on in sw tracking\n");
12812 I915_STATE_WARN(pll->on && !pll->active,
12813 "pll in on but not on in use in sw tracking\n");
12814 I915_STATE_WARN(pll->on != active,
12815 "pll on state mismatch (expected %i, found %i)\n",
12816 pll->on, active);
12817
12818 for_each_intel_crtc(dev, crtc) {
12819 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12820 enabled_crtcs++;
12821 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12822 active_crtcs++;
12823 }
12824 I915_STATE_WARN(pll->active != active_crtcs,
12825 "pll active crtcs mismatch (expected %i, found %i)\n",
12826 pll->active, active_crtcs);
12827 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12828 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12829 hweight32(pll->config.crtc_mask), enabled_crtcs);
12830
12831 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12832 sizeof(dpll_hw_state)),
12833 "pll hw state mismatch\n");
12834 }
12835 }
12836
12837 void
12838 intel_modeset_check_state(struct drm_device *dev)
12839 {
12840 check_wm_state(dev);
12841 check_connector_state(dev);
12842 check_encoder_state(dev);
12843 check_crtc_state(dev);
12844 check_shared_dpll_state(dev);
12845 }
12846
12847 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12848 int dotclock)
12849 {
12850 /*
12851 * FDI already provided one idea for the dotclock.
12852 * Yell if the encoder disagrees.
12853 */
12854 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12855 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12856 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12857 }
12858
12859 static void update_scanline_offset(struct intel_crtc *crtc)
12860 {
12861 struct drm_device *dev = crtc->base.dev;
12862
12863 /*
12864 * The scanline counter increments at the leading edge of hsync.
12865 *
12866 * On most platforms it starts counting from vtotal-1 on the
12867 * first active line. That means the scanline counter value is
12868 * always one less than what we would expect. Ie. just after
12869 * start of vblank, which also occurs at start of hsync (on the
12870 * last active line), the scanline counter will read vblank_start-1.
12871 *
12872 * On gen2 the scanline counter starts counting from 1 instead
12873 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12874 * to keep the value positive), instead of adding one.
12875 *
12876 * On HSW+ the behaviour of the scanline counter depends on the output
12877 * type. For DP ports it behaves like most other platforms, but on HDMI
12878 * there's an extra 1 line difference. So we need to add two instead of
12879 * one to the value.
12880 */
12881 if (IS_GEN2(dev)) {
12882 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12883 int vtotal;
12884
12885 vtotal = mode->crtc_vtotal;
12886 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12887 vtotal /= 2;
12888
12889 crtc->scanline_offset = vtotal - 1;
12890 } else if (HAS_DDI(dev) &&
12891 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12892 crtc->scanline_offset = 2;
12893 } else
12894 crtc->scanline_offset = 1;
12895 }
12896
12897 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12898 {
12899 struct drm_device *dev = state->dev;
12900 struct drm_i915_private *dev_priv = to_i915(dev);
12901 struct intel_shared_dpll_config *shared_dpll = NULL;
12902 struct intel_crtc *intel_crtc;
12903 struct intel_crtc_state *intel_crtc_state;
12904 struct drm_crtc *crtc;
12905 struct drm_crtc_state *crtc_state;
12906 int i;
12907
12908 if (!dev_priv->display.crtc_compute_clock)
12909 return;
12910
12911 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12912 int dpll;
12913
12914 intel_crtc = to_intel_crtc(crtc);
12915 intel_crtc_state = to_intel_crtc_state(crtc_state);
12916 dpll = intel_crtc_state->shared_dpll;
12917
12918 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12919 continue;
12920
12921 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12922
12923 if (!shared_dpll)
12924 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12925
12926 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12927 }
12928 }
12929
12930 /*
12931 * This implements the workaround described in the "notes" section of the mode
12932 * set sequence documentation. When going from no pipes or single pipe to
12933 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12934 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12935 */
12936 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12937 {
12938 struct drm_crtc_state *crtc_state;
12939 struct intel_crtc *intel_crtc;
12940 struct drm_crtc *crtc;
12941 struct intel_crtc_state *first_crtc_state = NULL;
12942 struct intel_crtc_state *other_crtc_state = NULL;
12943 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12944 int i;
12945
12946 /* look at all crtc's that are going to be enabled in during modeset */
12947 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12948 intel_crtc = to_intel_crtc(crtc);
12949
12950 if (!crtc_state->active || !needs_modeset(crtc_state))
12951 continue;
12952
12953 if (first_crtc_state) {
12954 other_crtc_state = to_intel_crtc_state(crtc_state);
12955 break;
12956 } else {
12957 first_crtc_state = to_intel_crtc_state(crtc_state);
12958 first_pipe = intel_crtc->pipe;
12959 }
12960 }
12961
12962 /* No workaround needed? */
12963 if (!first_crtc_state)
12964 return 0;
12965
12966 /* w/a possibly needed, check how many crtc's are already enabled. */
12967 for_each_intel_crtc(state->dev, intel_crtc) {
12968 struct intel_crtc_state *pipe_config;
12969
12970 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12971 if (IS_ERR(pipe_config))
12972 return PTR_ERR(pipe_config);
12973
12974 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12975
12976 if (!pipe_config->base.active ||
12977 needs_modeset(&pipe_config->base))
12978 continue;
12979
12980 /* 2 or more enabled crtcs means no need for w/a */
12981 if (enabled_pipe != INVALID_PIPE)
12982 return 0;
12983
12984 enabled_pipe = intel_crtc->pipe;
12985 }
12986
12987 if (enabled_pipe != INVALID_PIPE)
12988 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12989 else if (other_crtc_state)
12990 other_crtc_state->hsw_workaround_pipe = first_pipe;
12991
12992 return 0;
12993 }
12994
12995 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12996 {
12997 struct drm_crtc *crtc;
12998 struct drm_crtc_state *crtc_state;
12999 int ret = 0;
13000
13001 /* add all active pipes to the state */
13002 for_each_crtc(state->dev, crtc) {
13003 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13004 if (IS_ERR(crtc_state))
13005 return PTR_ERR(crtc_state);
13006
13007 if (!crtc_state->active || needs_modeset(crtc_state))
13008 continue;
13009
13010 crtc_state->mode_changed = true;
13011
13012 ret = drm_atomic_add_affected_connectors(state, crtc);
13013 if (ret)
13014 break;
13015
13016 ret = drm_atomic_add_affected_planes(state, crtc);
13017 if (ret)
13018 break;
13019 }
13020
13021 return ret;
13022 }
13023
13024
13025 /* Code that should eventually be part of atomic_check() */
13026 static int intel_modeset_checks(struct drm_atomic_state *state)
13027 {
13028 struct drm_device *dev = state->dev;
13029 struct drm_i915_private *dev_priv = dev->dev_private;
13030 int ret;
13031
13032 if (!check_digital_port_conflicts(state)) {
13033 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13034 return -EINVAL;
13035 }
13036
13037 /*
13038 * See if the config requires any additional preparation, e.g.
13039 * to adjust global state with pipes off. We need to do this
13040 * here so we can get the modeset_pipe updated config for the new
13041 * mode set on this crtc. For other crtcs we need to use the
13042 * adjusted_mode bits in the crtc directly.
13043 */
13044 if (dev_priv->display.modeset_calc_cdclk) {
13045 unsigned int cdclk;
13046
13047 ret = dev_priv->display.modeset_calc_cdclk(state);
13048
13049 cdclk = to_intel_atomic_state(state)->cdclk;
13050 if (!ret && cdclk != dev_priv->cdclk_freq)
13051 ret = intel_modeset_all_pipes(state);
13052
13053 if (ret < 0)
13054 return ret;
13055 } else
13056 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13057
13058 intel_modeset_clear_plls(state);
13059
13060 if (IS_HASWELL(dev))
13061 return haswell_mode_set_planes_workaround(state);
13062
13063 return 0;
13064 }
13065
13066 static int
13067 intel_modeset_compute_config(struct drm_atomic_state *state)
13068 {
13069 struct drm_crtc *crtc;
13070 struct drm_crtc_state *crtc_state;
13071 int ret, i;
13072 bool any_ms = false;
13073
13074 ret = drm_atomic_helper_check_modeset(state->dev, state);
13075 if (ret)
13076 return ret;
13077
13078 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13079 if (!crtc_state->enable) {
13080 if (needs_modeset(crtc_state))
13081 any_ms = true;
13082 continue;
13083 }
13084
13085 if (to_intel_crtc_state(crtc_state)->quirks &
13086 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13087 ret = drm_atomic_add_affected_planes(state, crtc);
13088 if (ret)
13089 return ret;
13090
13091 /*
13092 * We ought to handle i915.fastboot here.
13093 * If no modeset is required and the primary plane has
13094 * a fb, update the members of crtc_state as needed,
13095 * and run the necessary updates during vblank evasion.
13096 */
13097 }
13098
13099 if (!needs_modeset(crtc_state)) {
13100 ret = drm_atomic_add_affected_connectors(state, crtc);
13101 if (ret)
13102 return ret;
13103 }
13104
13105 ret = intel_modeset_pipe_config(crtc,
13106 to_intel_crtc_state(crtc_state));
13107 if (ret)
13108 return ret;
13109
13110 if (needs_modeset(crtc_state))
13111 any_ms = true;
13112
13113 intel_dump_pipe_config(to_intel_crtc(crtc),
13114 to_intel_crtc_state(crtc_state),
13115 "[modeset]");
13116 }
13117
13118 if (any_ms) {
13119 ret = intel_modeset_checks(state);
13120
13121 if (ret)
13122 return ret;
13123 } else
13124 to_intel_atomic_state(state)->cdclk =
13125 to_i915(state->dev)->cdclk_freq;
13126
13127 return drm_atomic_helper_check_planes(state->dev, state);
13128 }
13129
13130 static int __intel_set_mode(struct drm_atomic_state *state)
13131 {
13132 struct drm_device *dev = state->dev;
13133 struct drm_i915_private *dev_priv = dev->dev_private;
13134 struct drm_crtc *crtc;
13135 struct drm_crtc_state *crtc_state;
13136 int ret = 0;
13137 int i;
13138 bool any_ms = false;
13139
13140 ret = drm_atomic_helper_prepare_planes(dev, state);
13141 if (ret)
13142 return ret;
13143
13144 drm_atomic_helper_swap_state(dev, state);
13145
13146 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13148
13149 if (!needs_modeset(crtc->state))
13150 continue;
13151
13152 any_ms = true;
13153 intel_pre_plane_update(intel_crtc);
13154
13155 if (crtc_state->active) {
13156 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13157 dev_priv->display.crtc_disable(crtc);
13158 intel_crtc->active = false;
13159 intel_disable_shared_dpll(intel_crtc);
13160 }
13161 }
13162
13163 /* Only after disabling all output pipelines that will be changed can we
13164 * update the the output configuration. */
13165 intel_modeset_update_state(state);
13166
13167 /* The state has been swaped above, so state actually contains the
13168 * old state now. */
13169 if (any_ms)
13170 modeset_update_crtc_power_domains(state);
13171
13172 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13173 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13174 if (needs_modeset(crtc->state) && crtc->state->active) {
13175 update_scanline_offset(to_intel_crtc(crtc));
13176 dev_priv->display.crtc_enable(crtc);
13177 }
13178
13179 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13180 }
13181
13182 /* FIXME: add subpixel order */
13183
13184 drm_atomic_helper_cleanup_planes(dev, state);
13185
13186 drm_atomic_state_free(state);
13187
13188 return 0;
13189 }
13190
13191 static int intel_set_mode_checked(struct drm_atomic_state *state)
13192 {
13193 struct drm_device *dev = state->dev;
13194 int ret;
13195
13196 ret = __intel_set_mode(state);
13197 if (ret == 0)
13198 intel_modeset_check_state(dev);
13199
13200 return ret;
13201 }
13202
13203 static int intel_set_mode(struct drm_atomic_state *state)
13204 {
13205 int ret;
13206
13207 ret = intel_modeset_compute_config(state);
13208 if (ret)
13209 return ret;
13210
13211 return intel_set_mode_checked(state);
13212 }
13213
13214 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13215 {
13216 struct drm_device *dev = crtc->dev;
13217 struct drm_atomic_state *state;
13218 struct intel_encoder *encoder;
13219 struct intel_connector *connector;
13220 struct drm_connector_state *connector_state;
13221 struct intel_crtc_state *crtc_state;
13222 int ret;
13223
13224 state = drm_atomic_state_alloc(dev);
13225 if (!state) {
13226 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13227 crtc->base.id);
13228 return;
13229 }
13230
13231 state->acquire_ctx = dev->mode_config.acquire_ctx;
13232
13233 /* The force restore path in the HW readout code relies on the staged
13234 * config still keeping the user requested config while the actual
13235 * state has been overwritten by the configuration read from HW. We
13236 * need to copy the staged config to the atomic state, otherwise the
13237 * mode set will just reapply the state the HW is already in. */
13238 for_each_intel_encoder(dev, encoder) {
13239 if (&encoder->new_crtc->base != crtc)
13240 continue;
13241
13242 for_each_intel_connector(dev, connector) {
13243 if (connector->new_encoder != encoder)
13244 continue;
13245
13246 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13247 if (IS_ERR(connector_state)) {
13248 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13249 connector->base.base.id,
13250 connector->base.name,
13251 PTR_ERR(connector_state));
13252 continue;
13253 }
13254
13255 connector_state->crtc = crtc;
13256 connector_state->best_encoder = &encoder->base;
13257 }
13258 }
13259
13260 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13261 if (IS_ERR(crtc_state)) {
13262 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13263 crtc->base.id, PTR_ERR(crtc_state));
13264 drm_atomic_state_free(state);
13265 return;
13266 }
13267
13268 crtc_state->base.active = crtc_state->base.enable =
13269 to_intel_crtc(crtc)->new_enabled;
13270
13271 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13272
13273 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13274 crtc->primary->fb, crtc->x, crtc->y);
13275
13276 ret = intel_set_mode(state);
13277 if (ret)
13278 drm_atomic_state_free(state);
13279 }
13280
13281 #undef for_each_intel_crtc_masked
13282
13283 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13284 struct drm_mode_set *set)
13285 {
13286 int ro;
13287
13288 for (ro = 0; ro < set->num_connectors; ro++)
13289 if (set->connectors[ro] == &connector->base)
13290 return true;
13291
13292 return false;
13293 }
13294
13295 static int
13296 intel_modeset_stage_output_state(struct drm_device *dev,
13297 struct drm_mode_set *set,
13298 struct drm_atomic_state *state)
13299 {
13300 struct intel_connector *connector;
13301 struct drm_connector *drm_connector;
13302 struct drm_connector_state *connector_state;
13303 struct drm_crtc *crtc;
13304 struct drm_crtc_state *crtc_state;
13305 int i, ret;
13306
13307 /* The upper layers ensure that we either disable a crtc or have a list
13308 * of connectors. For paranoia, double-check this. */
13309 WARN_ON(!set->fb && (set->num_connectors != 0));
13310 WARN_ON(set->fb && (set->num_connectors == 0));
13311
13312 for_each_intel_connector(dev, connector) {
13313 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13314
13315 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13316 continue;
13317
13318 connector_state =
13319 drm_atomic_get_connector_state(state, &connector->base);
13320 if (IS_ERR(connector_state))
13321 return PTR_ERR(connector_state);
13322
13323 if (in_mode_set) {
13324 int pipe = to_intel_crtc(set->crtc)->pipe;
13325 connector_state->best_encoder =
13326 &intel_find_encoder(connector, pipe)->base;
13327 }
13328
13329 if (connector->base.state->crtc != set->crtc)
13330 continue;
13331
13332 /* If we disable the crtc, disable all its connectors. Also, if
13333 * the connector is on the changing crtc but not on the new
13334 * connector list, disable it. */
13335 if (!set->fb || !in_mode_set) {
13336 connector_state->best_encoder = NULL;
13337
13338 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13339 connector->base.base.id,
13340 connector->base.name);
13341 }
13342 }
13343 /* connector->new_encoder is now updated for all connectors. */
13344
13345 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13346 connector = to_intel_connector(drm_connector);
13347
13348 if (!connector_state->best_encoder) {
13349 ret = drm_atomic_set_crtc_for_connector(connector_state,
13350 NULL);
13351 if (ret)
13352 return ret;
13353
13354 continue;
13355 }
13356
13357 if (intel_connector_in_mode_set(connector, set)) {
13358 struct drm_crtc *crtc = connector->base.state->crtc;
13359
13360 /* If this connector was in a previous crtc, add it
13361 * to the state. We might need to disable it. */
13362 if (crtc) {
13363 crtc_state =
13364 drm_atomic_get_crtc_state(state, crtc);
13365 if (IS_ERR(crtc_state))
13366 return PTR_ERR(crtc_state);
13367 }
13368
13369 ret = drm_atomic_set_crtc_for_connector(connector_state,
13370 set->crtc);
13371 if (ret)
13372 return ret;
13373 }
13374
13375 /* Make sure the new CRTC will work with the encoder */
13376 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13377 connector_state->crtc)) {
13378 return -EINVAL;
13379 }
13380
13381 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13382 connector->base.base.id,
13383 connector->base.name,
13384 connector_state->crtc->base.id);
13385
13386 if (connector_state->best_encoder != &connector->encoder->base)
13387 connector->encoder =
13388 to_intel_encoder(connector_state->best_encoder);
13389 }
13390
13391 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13392 bool has_connectors;
13393
13394 ret = drm_atomic_add_affected_connectors(state, crtc);
13395 if (ret)
13396 return ret;
13397
13398 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13399 if (has_connectors != crtc_state->enable)
13400 crtc_state->enable =
13401 crtc_state->active = has_connectors;
13402 }
13403
13404 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13405 set->fb, set->x, set->y);
13406 if (ret)
13407 return ret;
13408
13409 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13410 if (IS_ERR(crtc_state))
13411 return PTR_ERR(crtc_state);
13412
13413 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13414 if (ret)
13415 return ret;
13416
13417 if (set->num_connectors)
13418 crtc_state->active = true;
13419
13420 return 0;
13421 }
13422
13423 static int intel_crtc_set_config(struct drm_mode_set *set)
13424 {
13425 struct drm_device *dev;
13426 struct drm_atomic_state *state = NULL;
13427 int ret;
13428
13429 BUG_ON(!set);
13430 BUG_ON(!set->crtc);
13431 BUG_ON(!set->crtc->helper_private);
13432
13433 /* Enforce sane interface api - has been abused by the fb helper. */
13434 BUG_ON(!set->mode && set->fb);
13435 BUG_ON(set->fb && set->num_connectors == 0);
13436
13437 if (set->fb) {
13438 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13439 set->crtc->base.id, set->fb->base.id,
13440 (int)set->num_connectors, set->x, set->y);
13441 } else {
13442 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13443 }
13444
13445 dev = set->crtc->dev;
13446
13447 state = drm_atomic_state_alloc(dev);
13448 if (!state)
13449 return -ENOMEM;
13450
13451 state->acquire_ctx = dev->mode_config.acquire_ctx;
13452
13453 ret = intel_modeset_stage_output_state(dev, set, state);
13454 if (ret)
13455 goto out;
13456
13457 ret = intel_modeset_compute_config(state);
13458 if (ret)
13459 goto out;
13460
13461 intel_update_pipe_size(to_intel_crtc(set->crtc));
13462
13463 ret = intel_set_mode_checked(state);
13464 if (ret) {
13465 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13466 set->crtc->base.id, ret);
13467 }
13468
13469 out:
13470 if (ret)
13471 drm_atomic_state_free(state);
13472 return ret;
13473 }
13474
13475 static const struct drm_crtc_funcs intel_crtc_funcs = {
13476 .gamma_set = intel_crtc_gamma_set,
13477 .set_config = intel_crtc_set_config,
13478 .destroy = intel_crtc_destroy,
13479 .page_flip = intel_crtc_page_flip,
13480 .atomic_duplicate_state = intel_crtc_duplicate_state,
13481 .atomic_destroy_state = intel_crtc_destroy_state,
13482 };
13483
13484 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13485 struct intel_shared_dpll *pll,
13486 struct intel_dpll_hw_state *hw_state)
13487 {
13488 uint32_t val;
13489
13490 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13491 return false;
13492
13493 val = I915_READ(PCH_DPLL(pll->id));
13494 hw_state->dpll = val;
13495 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13496 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13497
13498 return val & DPLL_VCO_ENABLE;
13499 }
13500
13501 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13502 struct intel_shared_dpll *pll)
13503 {
13504 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13505 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13506 }
13507
13508 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13509 struct intel_shared_dpll *pll)
13510 {
13511 /* PCH refclock must be enabled first */
13512 ibx_assert_pch_refclk_enabled(dev_priv);
13513
13514 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13515
13516 /* Wait for the clocks to stabilize. */
13517 POSTING_READ(PCH_DPLL(pll->id));
13518 udelay(150);
13519
13520 /* The pixel multiplier can only be updated once the
13521 * DPLL is enabled and the clocks are stable.
13522 *
13523 * So write it again.
13524 */
13525 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13526 POSTING_READ(PCH_DPLL(pll->id));
13527 udelay(200);
13528 }
13529
13530 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13531 struct intel_shared_dpll *pll)
13532 {
13533 struct drm_device *dev = dev_priv->dev;
13534 struct intel_crtc *crtc;
13535
13536 /* Make sure no transcoder isn't still depending on us. */
13537 for_each_intel_crtc(dev, crtc) {
13538 if (intel_crtc_to_shared_dpll(crtc) == pll)
13539 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13540 }
13541
13542 I915_WRITE(PCH_DPLL(pll->id), 0);
13543 POSTING_READ(PCH_DPLL(pll->id));
13544 udelay(200);
13545 }
13546
13547 static char *ibx_pch_dpll_names[] = {
13548 "PCH DPLL A",
13549 "PCH DPLL B",
13550 };
13551
13552 static void ibx_pch_dpll_init(struct drm_device *dev)
13553 {
13554 struct drm_i915_private *dev_priv = dev->dev_private;
13555 int i;
13556
13557 dev_priv->num_shared_dpll = 2;
13558
13559 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13560 dev_priv->shared_dplls[i].id = i;
13561 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13562 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13563 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13564 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13565 dev_priv->shared_dplls[i].get_hw_state =
13566 ibx_pch_dpll_get_hw_state;
13567 }
13568 }
13569
13570 static void intel_shared_dpll_init(struct drm_device *dev)
13571 {
13572 struct drm_i915_private *dev_priv = dev->dev_private;
13573
13574 intel_update_cdclk(dev);
13575
13576 if (HAS_DDI(dev))
13577 intel_ddi_pll_init(dev);
13578 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13579 ibx_pch_dpll_init(dev);
13580 else
13581 dev_priv->num_shared_dpll = 0;
13582
13583 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13584 }
13585
13586 /**
13587 * intel_prepare_plane_fb - Prepare fb for usage on plane
13588 * @plane: drm plane to prepare for
13589 * @fb: framebuffer to prepare for presentation
13590 *
13591 * Prepares a framebuffer for usage on a display plane. Generally this
13592 * involves pinning the underlying object and updating the frontbuffer tracking
13593 * bits. Some older platforms need special physical address handling for
13594 * cursor planes.
13595 *
13596 * Returns 0 on success, negative error code on failure.
13597 */
13598 int
13599 intel_prepare_plane_fb(struct drm_plane *plane,
13600 struct drm_framebuffer *fb,
13601 const struct drm_plane_state *new_state)
13602 {
13603 struct drm_device *dev = plane->dev;
13604 struct intel_plane *intel_plane = to_intel_plane(plane);
13605 enum pipe pipe = intel_plane->pipe;
13606 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13607 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13608 unsigned frontbuffer_bits = 0;
13609 int ret = 0;
13610
13611 if (!obj)
13612 return 0;
13613
13614 switch (plane->type) {
13615 case DRM_PLANE_TYPE_PRIMARY:
13616 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13617 break;
13618 case DRM_PLANE_TYPE_CURSOR:
13619 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13620 break;
13621 case DRM_PLANE_TYPE_OVERLAY:
13622 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13623 break;
13624 }
13625
13626 mutex_lock(&dev->struct_mutex);
13627
13628 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13629 INTEL_INFO(dev)->cursor_needs_physical) {
13630 int align = IS_I830(dev) ? 16 * 1024 : 256;
13631 ret = i915_gem_object_attach_phys(obj, align);
13632 if (ret)
13633 DRM_DEBUG_KMS("failed to attach phys object\n");
13634 } else {
13635 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13636 }
13637
13638 if (ret == 0)
13639 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13640
13641 mutex_unlock(&dev->struct_mutex);
13642
13643 return ret;
13644 }
13645
13646 /**
13647 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13648 * @plane: drm plane to clean up for
13649 * @fb: old framebuffer that was on plane
13650 *
13651 * Cleans up a framebuffer that has just been removed from a plane.
13652 */
13653 void
13654 intel_cleanup_plane_fb(struct drm_plane *plane,
13655 struct drm_framebuffer *fb,
13656 const struct drm_plane_state *old_state)
13657 {
13658 struct drm_device *dev = plane->dev;
13659 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13660
13661 if (WARN_ON(!obj))
13662 return;
13663
13664 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13665 !INTEL_INFO(dev)->cursor_needs_physical) {
13666 mutex_lock(&dev->struct_mutex);
13667 intel_unpin_fb_obj(fb, old_state);
13668 mutex_unlock(&dev->struct_mutex);
13669 }
13670 }
13671
13672 int
13673 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13674 {
13675 int max_scale;
13676 struct drm_device *dev;
13677 struct drm_i915_private *dev_priv;
13678 int crtc_clock, cdclk;
13679
13680 if (!intel_crtc || !crtc_state)
13681 return DRM_PLANE_HELPER_NO_SCALING;
13682
13683 dev = intel_crtc->base.dev;
13684 dev_priv = dev->dev_private;
13685 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13686 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13687
13688 if (!crtc_clock || !cdclk)
13689 return DRM_PLANE_HELPER_NO_SCALING;
13690
13691 /*
13692 * skl max scale is lower of:
13693 * close to 3 but not 3, -1 is for that purpose
13694 * or
13695 * cdclk/crtc_clock
13696 */
13697 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13698
13699 return max_scale;
13700 }
13701
13702 static int
13703 intel_check_primary_plane(struct drm_plane *plane,
13704 struct intel_crtc_state *crtc_state,
13705 struct intel_plane_state *state)
13706 {
13707 struct drm_crtc *crtc = state->base.crtc;
13708 struct drm_framebuffer *fb = state->base.fb;
13709 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13710 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13711 bool can_position = false;
13712
13713 /* use scaler when colorkey is not required */
13714 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13715 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13716 min_scale = 1;
13717 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13718 can_position = true;
13719 }
13720
13721 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13722 &state->dst, &state->clip,
13723 min_scale, max_scale,
13724 can_position, true,
13725 &state->visible);
13726 }
13727
13728 static void
13729 intel_commit_primary_plane(struct drm_plane *plane,
13730 struct intel_plane_state *state)
13731 {
13732 struct drm_crtc *crtc = state->base.crtc;
13733 struct drm_framebuffer *fb = state->base.fb;
13734 struct drm_device *dev = plane->dev;
13735 struct drm_i915_private *dev_priv = dev->dev_private;
13736 struct intel_crtc *intel_crtc;
13737 struct drm_rect *src = &state->src;
13738
13739 crtc = crtc ? crtc : plane->crtc;
13740 intel_crtc = to_intel_crtc(crtc);
13741
13742 plane->fb = fb;
13743 crtc->x = src->x1 >> 16;
13744 crtc->y = src->y1 >> 16;
13745
13746 if (!crtc->state->active)
13747 return;
13748
13749 if (state->visible)
13750 /* FIXME: kill this fastboot hack */
13751 intel_update_pipe_size(intel_crtc);
13752
13753 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13754 }
13755
13756 static void
13757 intel_disable_primary_plane(struct drm_plane *plane,
13758 struct drm_crtc *crtc)
13759 {
13760 struct drm_device *dev = plane->dev;
13761 struct drm_i915_private *dev_priv = dev->dev_private;
13762
13763 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13764 }
13765
13766 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13767 {
13768 struct drm_device *dev = crtc->dev;
13769 struct drm_i915_private *dev_priv = dev->dev_private;
13770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13771
13772 if (!needs_modeset(crtc->state))
13773 intel_pre_plane_update(intel_crtc);
13774
13775 if (intel_crtc->atomic.update_wm)
13776 intel_update_watermarks(crtc);
13777
13778 intel_runtime_pm_get(dev_priv);
13779
13780 /* Perform vblank evasion around commit operation */
13781 if (crtc->state->active)
13782 intel_crtc->atomic.evade =
13783 intel_pipe_update_start(intel_crtc,
13784 &intel_crtc->atomic.start_vbl_count);
13785
13786 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13787 skl_detach_scalers(intel_crtc);
13788 }
13789
13790 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13791 {
13792 struct drm_device *dev = crtc->dev;
13793 struct drm_i915_private *dev_priv = dev->dev_private;
13794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13795
13796 if (intel_crtc->atomic.evade)
13797 intel_pipe_update_end(intel_crtc,
13798 intel_crtc->atomic.start_vbl_count);
13799
13800 intel_runtime_pm_put(dev_priv);
13801
13802 intel_post_plane_update(intel_crtc);
13803 }
13804
13805 /**
13806 * intel_plane_destroy - destroy a plane
13807 * @plane: plane to destroy
13808 *
13809 * Common destruction function for all types of planes (primary, cursor,
13810 * sprite).
13811 */
13812 void intel_plane_destroy(struct drm_plane *plane)
13813 {
13814 struct intel_plane *intel_plane = to_intel_plane(plane);
13815 drm_plane_cleanup(plane);
13816 kfree(intel_plane);
13817 }
13818
13819 const struct drm_plane_funcs intel_plane_funcs = {
13820 .update_plane = drm_atomic_helper_update_plane,
13821 .disable_plane = drm_atomic_helper_disable_plane,
13822 .destroy = intel_plane_destroy,
13823 .set_property = drm_atomic_helper_plane_set_property,
13824 .atomic_get_property = intel_plane_atomic_get_property,
13825 .atomic_set_property = intel_plane_atomic_set_property,
13826 .atomic_duplicate_state = intel_plane_duplicate_state,
13827 .atomic_destroy_state = intel_plane_destroy_state,
13828
13829 };
13830
13831 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13832 int pipe)
13833 {
13834 struct intel_plane *primary;
13835 struct intel_plane_state *state;
13836 const uint32_t *intel_primary_formats;
13837 int num_formats;
13838
13839 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13840 if (primary == NULL)
13841 return NULL;
13842
13843 state = intel_create_plane_state(&primary->base);
13844 if (!state) {
13845 kfree(primary);
13846 return NULL;
13847 }
13848 primary->base.state = &state->base;
13849
13850 primary->can_scale = false;
13851 primary->max_downscale = 1;
13852 if (INTEL_INFO(dev)->gen >= 9) {
13853 primary->can_scale = true;
13854 state->scaler_id = -1;
13855 }
13856 primary->pipe = pipe;
13857 primary->plane = pipe;
13858 primary->check_plane = intel_check_primary_plane;
13859 primary->commit_plane = intel_commit_primary_plane;
13860 primary->disable_plane = intel_disable_primary_plane;
13861 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13862 primary->plane = !pipe;
13863
13864 if (INTEL_INFO(dev)->gen >= 9) {
13865 intel_primary_formats = skl_primary_formats;
13866 num_formats = ARRAY_SIZE(skl_primary_formats);
13867 } else if (INTEL_INFO(dev)->gen >= 4) {
13868 intel_primary_formats = i965_primary_formats;
13869 num_formats = ARRAY_SIZE(i965_primary_formats);
13870 } else {
13871 intel_primary_formats = i8xx_primary_formats;
13872 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13873 }
13874
13875 drm_universal_plane_init(dev, &primary->base, 0,
13876 &intel_plane_funcs,
13877 intel_primary_formats, num_formats,
13878 DRM_PLANE_TYPE_PRIMARY);
13879
13880 if (INTEL_INFO(dev)->gen >= 4)
13881 intel_create_rotation_property(dev, primary);
13882
13883 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13884
13885 return &primary->base;
13886 }
13887
13888 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13889 {
13890 if (!dev->mode_config.rotation_property) {
13891 unsigned long flags = BIT(DRM_ROTATE_0) |
13892 BIT(DRM_ROTATE_180);
13893
13894 if (INTEL_INFO(dev)->gen >= 9)
13895 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13896
13897 dev->mode_config.rotation_property =
13898 drm_mode_create_rotation_property(dev, flags);
13899 }
13900 if (dev->mode_config.rotation_property)
13901 drm_object_attach_property(&plane->base.base,
13902 dev->mode_config.rotation_property,
13903 plane->base.state->rotation);
13904 }
13905
13906 static int
13907 intel_check_cursor_plane(struct drm_plane *plane,
13908 struct intel_crtc_state *crtc_state,
13909 struct intel_plane_state *state)
13910 {
13911 struct drm_crtc *crtc = crtc_state->base.crtc;
13912 struct drm_framebuffer *fb = state->base.fb;
13913 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13914 unsigned stride;
13915 int ret;
13916
13917 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13918 &state->dst, &state->clip,
13919 DRM_PLANE_HELPER_NO_SCALING,
13920 DRM_PLANE_HELPER_NO_SCALING,
13921 true, true, &state->visible);
13922 if (ret)
13923 return ret;
13924
13925 /* if we want to turn off the cursor ignore width and height */
13926 if (!obj)
13927 return 0;
13928
13929 /* Check for which cursor types we support */
13930 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13931 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13932 state->base.crtc_w, state->base.crtc_h);
13933 return -EINVAL;
13934 }
13935
13936 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13937 if (obj->base.size < stride * state->base.crtc_h) {
13938 DRM_DEBUG_KMS("buffer is too small\n");
13939 return -ENOMEM;
13940 }
13941
13942 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13943 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13944 return -EINVAL;
13945 }
13946
13947 return 0;
13948 }
13949
13950 static void
13951 intel_disable_cursor_plane(struct drm_plane *plane,
13952 struct drm_crtc *crtc)
13953 {
13954 intel_crtc_update_cursor(crtc, false);
13955 }
13956
13957 static void
13958 intel_commit_cursor_plane(struct drm_plane *plane,
13959 struct intel_plane_state *state)
13960 {
13961 struct drm_crtc *crtc = state->base.crtc;
13962 struct drm_device *dev = plane->dev;
13963 struct intel_crtc *intel_crtc;
13964 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13965 uint32_t addr;
13966
13967 crtc = crtc ? crtc : plane->crtc;
13968 intel_crtc = to_intel_crtc(crtc);
13969
13970 plane->fb = state->base.fb;
13971 crtc->cursor_x = state->base.crtc_x;
13972 crtc->cursor_y = state->base.crtc_y;
13973
13974 if (intel_crtc->cursor_bo == obj)
13975 goto update;
13976
13977 if (!obj)
13978 addr = 0;
13979 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13980 addr = i915_gem_obj_ggtt_offset(obj);
13981 else
13982 addr = obj->phys_handle->busaddr;
13983
13984 intel_crtc->cursor_addr = addr;
13985 intel_crtc->cursor_bo = obj;
13986
13987 update:
13988 if (crtc->state->active)
13989 intel_crtc_update_cursor(crtc, state->visible);
13990 }
13991
13992 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13993 int pipe)
13994 {
13995 struct intel_plane *cursor;
13996 struct intel_plane_state *state;
13997
13998 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13999 if (cursor == NULL)
14000 return NULL;
14001
14002 state = intel_create_plane_state(&cursor->base);
14003 if (!state) {
14004 kfree(cursor);
14005 return NULL;
14006 }
14007 cursor->base.state = &state->base;
14008
14009 cursor->can_scale = false;
14010 cursor->max_downscale = 1;
14011 cursor->pipe = pipe;
14012 cursor->plane = pipe;
14013 cursor->check_plane = intel_check_cursor_plane;
14014 cursor->commit_plane = intel_commit_cursor_plane;
14015 cursor->disable_plane = intel_disable_cursor_plane;
14016
14017 drm_universal_plane_init(dev, &cursor->base, 0,
14018 &intel_plane_funcs,
14019 intel_cursor_formats,
14020 ARRAY_SIZE(intel_cursor_formats),
14021 DRM_PLANE_TYPE_CURSOR);
14022
14023 if (INTEL_INFO(dev)->gen >= 4) {
14024 if (!dev->mode_config.rotation_property)
14025 dev->mode_config.rotation_property =
14026 drm_mode_create_rotation_property(dev,
14027 BIT(DRM_ROTATE_0) |
14028 BIT(DRM_ROTATE_180));
14029 if (dev->mode_config.rotation_property)
14030 drm_object_attach_property(&cursor->base.base,
14031 dev->mode_config.rotation_property,
14032 state->base.rotation);
14033 }
14034
14035 if (INTEL_INFO(dev)->gen >=9)
14036 state->scaler_id = -1;
14037
14038 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14039
14040 return &cursor->base;
14041 }
14042
14043 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14044 struct intel_crtc_state *crtc_state)
14045 {
14046 int i;
14047 struct intel_scaler *intel_scaler;
14048 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14049
14050 for (i = 0; i < intel_crtc->num_scalers; i++) {
14051 intel_scaler = &scaler_state->scalers[i];
14052 intel_scaler->in_use = 0;
14053 intel_scaler->mode = PS_SCALER_MODE_DYN;
14054 }
14055
14056 scaler_state->scaler_id = -1;
14057 }
14058
14059 static void intel_crtc_init(struct drm_device *dev, int pipe)
14060 {
14061 struct drm_i915_private *dev_priv = dev->dev_private;
14062 struct intel_crtc *intel_crtc;
14063 struct intel_crtc_state *crtc_state = NULL;
14064 struct drm_plane *primary = NULL;
14065 struct drm_plane *cursor = NULL;
14066 int i, ret;
14067
14068 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14069 if (intel_crtc == NULL)
14070 return;
14071
14072 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14073 if (!crtc_state)
14074 goto fail;
14075 intel_crtc->config = crtc_state;
14076 intel_crtc->base.state = &crtc_state->base;
14077 crtc_state->base.crtc = &intel_crtc->base;
14078
14079 /* initialize shared scalers */
14080 if (INTEL_INFO(dev)->gen >= 9) {
14081 if (pipe == PIPE_C)
14082 intel_crtc->num_scalers = 1;
14083 else
14084 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14085
14086 skl_init_scalers(dev, intel_crtc, crtc_state);
14087 }
14088
14089 primary = intel_primary_plane_create(dev, pipe);
14090 if (!primary)
14091 goto fail;
14092
14093 cursor = intel_cursor_plane_create(dev, pipe);
14094 if (!cursor)
14095 goto fail;
14096
14097 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14098 cursor, &intel_crtc_funcs);
14099 if (ret)
14100 goto fail;
14101
14102 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14103 for (i = 0; i < 256; i++) {
14104 intel_crtc->lut_r[i] = i;
14105 intel_crtc->lut_g[i] = i;
14106 intel_crtc->lut_b[i] = i;
14107 }
14108
14109 /*
14110 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14111 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14112 */
14113 intel_crtc->pipe = pipe;
14114 intel_crtc->plane = pipe;
14115 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14116 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14117 intel_crtc->plane = !pipe;
14118 }
14119
14120 intel_crtc->cursor_base = ~0;
14121 intel_crtc->cursor_cntl = ~0;
14122 intel_crtc->cursor_size = ~0;
14123
14124 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14125 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14126 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14127 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14128
14129 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14130
14131 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14132 return;
14133
14134 fail:
14135 if (primary)
14136 drm_plane_cleanup(primary);
14137 if (cursor)
14138 drm_plane_cleanup(cursor);
14139 kfree(crtc_state);
14140 kfree(intel_crtc);
14141 }
14142
14143 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14144 {
14145 struct drm_encoder *encoder = connector->base.encoder;
14146 struct drm_device *dev = connector->base.dev;
14147
14148 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14149
14150 if (!encoder || WARN_ON(!encoder->crtc))
14151 return INVALID_PIPE;
14152
14153 return to_intel_crtc(encoder->crtc)->pipe;
14154 }
14155
14156 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14157 struct drm_file *file)
14158 {
14159 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14160 struct drm_crtc *drmmode_crtc;
14161 struct intel_crtc *crtc;
14162
14163 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14164
14165 if (!drmmode_crtc) {
14166 DRM_ERROR("no such CRTC id\n");
14167 return -ENOENT;
14168 }
14169
14170 crtc = to_intel_crtc(drmmode_crtc);
14171 pipe_from_crtc_id->pipe = crtc->pipe;
14172
14173 return 0;
14174 }
14175
14176 static int intel_encoder_clones(struct intel_encoder *encoder)
14177 {
14178 struct drm_device *dev = encoder->base.dev;
14179 struct intel_encoder *source_encoder;
14180 int index_mask = 0;
14181 int entry = 0;
14182
14183 for_each_intel_encoder(dev, source_encoder) {
14184 if (encoders_cloneable(encoder, source_encoder))
14185 index_mask |= (1 << entry);
14186
14187 entry++;
14188 }
14189
14190 return index_mask;
14191 }
14192
14193 static bool has_edp_a(struct drm_device *dev)
14194 {
14195 struct drm_i915_private *dev_priv = dev->dev_private;
14196
14197 if (!IS_MOBILE(dev))
14198 return false;
14199
14200 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14201 return false;
14202
14203 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14204 return false;
14205
14206 return true;
14207 }
14208
14209 static bool intel_crt_present(struct drm_device *dev)
14210 {
14211 struct drm_i915_private *dev_priv = dev->dev_private;
14212
14213 if (INTEL_INFO(dev)->gen >= 9)
14214 return false;
14215
14216 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14217 return false;
14218
14219 if (IS_CHERRYVIEW(dev))
14220 return false;
14221
14222 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14223 return false;
14224
14225 return true;
14226 }
14227
14228 static void intel_setup_outputs(struct drm_device *dev)
14229 {
14230 struct drm_i915_private *dev_priv = dev->dev_private;
14231 struct intel_encoder *encoder;
14232 bool dpd_is_edp = false;
14233
14234 intel_lvds_init(dev);
14235
14236 if (intel_crt_present(dev))
14237 intel_crt_init(dev);
14238
14239 if (IS_BROXTON(dev)) {
14240 /*
14241 * FIXME: Broxton doesn't support port detection via the
14242 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14243 * detect the ports.
14244 */
14245 intel_ddi_init(dev, PORT_A);
14246 intel_ddi_init(dev, PORT_B);
14247 intel_ddi_init(dev, PORT_C);
14248 } else if (HAS_DDI(dev)) {
14249 int found;
14250
14251 /*
14252 * Haswell uses DDI functions to detect digital outputs.
14253 * On SKL pre-D0 the strap isn't connected, so we assume
14254 * it's there.
14255 */
14256 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14257 /* WaIgnoreDDIAStrap: skl */
14258 if (found ||
14259 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14260 intel_ddi_init(dev, PORT_A);
14261
14262 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14263 * register */
14264 found = I915_READ(SFUSE_STRAP);
14265
14266 if (found & SFUSE_STRAP_DDIB_DETECTED)
14267 intel_ddi_init(dev, PORT_B);
14268 if (found & SFUSE_STRAP_DDIC_DETECTED)
14269 intel_ddi_init(dev, PORT_C);
14270 if (found & SFUSE_STRAP_DDID_DETECTED)
14271 intel_ddi_init(dev, PORT_D);
14272 } else if (HAS_PCH_SPLIT(dev)) {
14273 int found;
14274 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14275
14276 if (has_edp_a(dev))
14277 intel_dp_init(dev, DP_A, PORT_A);
14278
14279 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14280 /* PCH SDVOB multiplex with HDMIB */
14281 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14282 if (!found)
14283 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14284 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14285 intel_dp_init(dev, PCH_DP_B, PORT_B);
14286 }
14287
14288 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14289 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14290
14291 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14292 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14293
14294 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14295 intel_dp_init(dev, PCH_DP_C, PORT_C);
14296
14297 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14298 intel_dp_init(dev, PCH_DP_D, PORT_D);
14299 } else if (IS_VALLEYVIEW(dev)) {
14300 /*
14301 * The DP_DETECTED bit is the latched state of the DDC
14302 * SDA pin at boot. However since eDP doesn't require DDC
14303 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14304 * eDP ports may have been muxed to an alternate function.
14305 * Thus we can't rely on the DP_DETECTED bit alone to detect
14306 * eDP ports. Consult the VBT as well as DP_DETECTED to
14307 * detect eDP ports.
14308 */
14309 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14310 !intel_dp_is_edp(dev, PORT_B))
14311 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14312 PORT_B);
14313 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14314 intel_dp_is_edp(dev, PORT_B))
14315 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14316
14317 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14318 !intel_dp_is_edp(dev, PORT_C))
14319 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14320 PORT_C);
14321 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14322 intel_dp_is_edp(dev, PORT_C))
14323 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14324
14325 if (IS_CHERRYVIEW(dev)) {
14326 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14327 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14328 PORT_D);
14329 /* eDP not supported on port D, so don't check VBT */
14330 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14331 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14332 }
14333
14334 intel_dsi_init(dev);
14335 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14336 bool found = false;
14337
14338 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14339 DRM_DEBUG_KMS("probing SDVOB\n");
14340 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14341 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14342 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14343 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14344 }
14345
14346 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14347 intel_dp_init(dev, DP_B, PORT_B);
14348 }
14349
14350 /* Before G4X SDVOC doesn't have its own detect register */
14351
14352 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14353 DRM_DEBUG_KMS("probing SDVOC\n");
14354 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14355 }
14356
14357 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14358
14359 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14360 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14361 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14362 }
14363 if (SUPPORTS_INTEGRATED_DP(dev))
14364 intel_dp_init(dev, DP_C, PORT_C);
14365 }
14366
14367 if (SUPPORTS_INTEGRATED_DP(dev) &&
14368 (I915_READ(DP_D) & DP_DETECTED))
14369 intel_dp_init(dev, DP_D, PORT_D);
14370 } else if (IS_GEN2(dev))
14371 intel_dvo_init(dev);
14372
14373 if (SUPPORTS_TV(dev))
14374 intel_tv_init(dev);
14375
14376 intel_psr_init(dev);
14377
14378 for_each_intel_encoder(dev, encoder) {
14379 encoder->base.possible_crtcs = encoder->crtc_mask;
14380 encoder->base.possible_clones =
14381 intel_encoder_clones(encoder);
14382 }
14383
14384 intel_init_pch_refclk(dev);
14385
14386 drm_helper_move_panel_connectors_to_head(dev);
14387 }
14388
14389 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14390 {
14391 struct drm_device *dev = fb->dev;
14392 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14393
14394 drm_framebuffer_cleanup(fb);
14395 mutex_lock(&dev->struct_mutex);
14396 WARN_ON(!intel_fb->obj->framebuffer_references--);
14397 drm_gem_object_unreference(&intel_fb->obj->base);
14398 mutex_unlock(&dev->struct_mutex);
14399 kfree(intel_fb);
14400 }
14401
14402 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14403 struct drm_file *file,
14404 unsigned int *handle)
14405 {
14406 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14407 struct drm_i915_gem_object *obj = intel_fb->obj;
14408
14409 return drm_gem_handle_create(file, &obj->base, handle);
14410 }
14411
14412 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14413 .destroy = intel_user_framebuffer_destroy,
14414 .create_handle = intel_user_framebuffer_create_handle,
14415 };
14416
14417 static
14418 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14419 uint32_t pixel_format)
14420 {
14421 u32 gen = INTEL_INFO(dev)->gen;
14422
14423 if (gen >= 9) {
14424 /* "The stride in bytes must not exceed the of the size of 8K
14425 * pixels and 32K bytes."
14426 */
14427 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14428 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14429 return 32*1024;
14430 } else if (gen >= 4) {
14431 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14432 return 16*1024;
14433 else
14434 return 32*1024;
14435 } else if (gen >= 3) {
14436 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14437 return 8*1024;
14438 else
14439 return 16*1024;
14440 } else {
14441 /* XXX DSPC is limited to 4k tiled */
14442 return 8*1024;
14443 }
14444 }
14445
14446 static int intel_framebuffer_init(struct drm_device *dev,
14447 struct intel_framebuffer *intel_fb,
14448 struct drm_mode_fb_cmd2 *mode_cmd,
14449 struct drm_i915_gem_object *obj)
14450 {
14451 unsigned int aligned_height;
14452 int ret;
14453 u32 pitch_limit, stride_alignment;
14454
14455 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14456
14457 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14458 /* Enforce that fb modifier and tiling mode match, but only for
14459 * X-tiled. This is needed for FBC. */
14460 if (!!(obj->tiling_mode == I915_TILING_X) !=
14461 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14462 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14463 return -EINVAL;
14464 }
14465 } else {
14466 if (obj->tiling_mode == I915_TILING_X)
14467 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14468 else if (obj->tiling_mode == I915_TILING_Y) {
14469 DRM_DEBUG("No Y tiling for legacy addfb\n");
14470 return -EINVAL;
14471 }
14472 }
14473
14474 /* Passed in modifier sanity checking. */
14475 switch (mode_cmd->modifier[0]) {
14476 case I915_FORMAT_MOD_Y_TILED:
14477 case I915_FORMAT_MOD_Yf_TILED:
14478 if (INTEL_INFO(dev)->gen < 9) {
14479 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14480 mode_cmd->modifier[0]);
14481 return -EINVAL;
14482 }
14483 case DRM_FORMAT_MOD_NONE:
14484 case I915_FORMAT_MOD_X_TILED:
14485 break;
14486 default:
14487 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14488 mode_cmd->modifier[0]);
14489 return -EINVAL;
14490 }
14491
14492 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14493 mode_cmd->pixel_format);
14494 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14495 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14496 mode_cmd->pitches[0], stride_alignment);
14497 return -EINVAL;
14498 }
14499
14500 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14501 mode_cmd->pixel_format);
14502 if (mode_cmd->pitches[0] > pitch_limit) {
14503 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14504 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14505 "tiled" : "linear",
14506 mode_cmd->pitches[0], pitch_limit);
14507 return -EINVAL;
14508 }
14509
14510 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14511 mode_cmd->pitches[0] != obj->stride) {
14512 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14513 mode_cmd->pitches[0], obj->stride);
14514 return -EINVAL;
14515 }
14516
14517 /* Reject formats not supported by any plane early. */
14518 switch (mode_cmd->pixel_format) {
14519 case DRM_FORMAT_C8:
14520 case DRM_FORMAT_RGB565:
14521 case DRM_FORMAT_XRGB8888:
14522 case DRM_FORMAT_ARGB8888:
14523 break;
14524 case DRM_FORMAT_XRGB1555:
14525 if (INTEL_INFO(dev)->gen > 3) {
14526 DRM_DEBUG("unsupported pixel format: %s\n",
14527 drm_get_format_name(mode_cmd->pixel_format));
14528 return -EINVAL;
14529 }
14530 break;
14531 case DRM_FORMAT_ABGR8888:
14532 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14533 DRM_DEBUG("unsupported pixel format: %s\n",
14534 drm_get_format_name(mode_cmd->pixel_format));
14535 return -EINVAL;
14536 }
14537 break;
14538 case DRM_FORMAT_XBGR8888:
14539 case DRM_FORMAT_XRGB2101010:
14540 case DRM_FORMAT_XBGR2101010:
14541 if (INTEL_INFO(dev)->gen < 4) {
14542 DRM_DEBUG("unsupported pixel format: %s\n",
14543 drm_get_format_name(mode_cmd->pixel_format));
14544 return -EINVAL;
14545 }
14546 break;
14547 case DRM_FORMAT_ABGR2101010:
14548 if (!IS_VALLEYVIEW(dev)) {
14549 DRM_DEBUG("unsupported pixel format: %s\n",
14550 drm_get_format_name(mode_cmd->pixel_format));
14551 return -EINVAL;
14552 }
14553 break;
14554 case DRM_FORMAT_YUYV:
14555 case DRM_FORMAT_UYVY:
14556 case DRM_FORMAT_YVYU:
14557 case DRM_FORMAT_VYUY:
14558 if (INTEL_INFO(dev)->gen < 5) {
14559 DRM_DEBUG("unsupported pixel format: %s\n",
14560 drm_get_format_name(mode_cmd->pixel_format));
14561 return -EINVAL;
14562 }
14563 break;
14564 default:
14565 DRM_DEBUG("unsupported pixel format: %s\n",
14566 drm_get_format_name(mode_cmd->pixel_format));
14567 return -EINVAL;
14568 }
14569
14570 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14571 if (mode_cmd->offsets[0] != 0)
14572 return -EINVAL;
14573
14574 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14575 mode_cmd->pixel_format,
14576 mode_cmd->modifier[0]);
14577 /* FIXME drm helper for size checks (especially planar formats)? */
14578 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14579 return -EINVAL;
14580
14581 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14582 intel_fb->obj = obj;
14583 intel_fb->obj->framebuffer_references++;
14584
14585 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14586 if (ret) {
14587 DRM_ERROR("framebuffer init failed %d\n", ret);
14588 return ret;
14589 }
14590
14591 return 0;
14592 }
14593
14594 static struct drm_framebuffer *
14595 intel_user_framebuffer_create(struct drm_device *dev,
14596 struct drm_file *filp,
14597 struct drm_mode_fb_cmd2 *mode_cmd)
14598 {
14599 struct drm_i915_gem_object *obj;
14600
14601 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14602 mode_cmd->handles[0]));
14603 if (&obj->base == NULL)
14604 return ERR_PTR(-ENOENT);
14605
14606 return intel_framebuffer_create(dev, mode_cmd, obj);
14607 }
14608
14609 #ifndef CONFIG_DRM_I915_FBDEV
14610 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14611 {
14612 }
14613 #endif
14614
14615 static const struct drm_mode_config_funcs intel_mode_funcs = {
14616 .fb_create = intel_user_framebuffer_create,
14617 .output_poll_changed = intel_fbdev_output_poll_changed,
14618 .atomic_check = intel_atomic_check,
14619 .atomic_commit = intel_atomic_commit,
14620 .atomic_state_alloc = intel_atomic_state_alloc,
14621 .atomic_state_clear = intel_atomic_state_clear,
14622 };
14623
14624 /* Set up chip specific display functions */
14625 static void intel_init_display(struct drm_device *dev)
14626 {
14627 struct drm_i915_private *dev_priv = dev->dev_private;
14628
14629 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14630 dev_priv->display.find_dpll = g4x_find_best_dpll;
14631 else if (IS_CHERRYVIEW(dev))
14632 dev_priv->display.find_dpll = chv_find_best_dpll;
14633 else if (IS_VALLEYVIEW(dev))
14634 dev_priv->display.find_dpll = vlv_find_best_dpll;
14635 else if (IS_PINEVIEW(dev))
14636 dev_priv->display.find_dpll = pnv_find_best_dpll;
14637 else
14638 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14639
14640 if (INTEL_INFO(dev)->gen >= 9) {
14641 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14642 dev_priv->display.get_initial_plane_config =
14643 skylake_get_initial_plane_config;
14644 dev_priv->display.crtc_compute_clock =
14645 haswell_crtc_compute_clock;
14646 dev_priv->display.crtc_enable = haswell_crtc_enable;
14647 dev_priv->display.crtc_disable = haswell_crtc_disable;
14648 dev_priv->display.update_primary_plane =
14649 skylake_update_primary_plane;
14650 } else if (HAS_DDI(dev)) {
14651 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14652 dev_priv->display.get_initial_plane_config =
14653 ironlake_get_initial_plane_config;
14654 dev_priv->display.crtc_compute_clock =
14655 haswell_crtc_compute_clock;
14656 dev_priv->display.crtc_enable = haswell_crtc_enable;
14657 dev_priv->display.crtc_disable = haswell_crtc_disable;
14658 dev_priv->display.update_primary_plane =
14659 ironlake_update_primary_plane;
14660 } else if (HAS_PCH_SPLIT(dev)) {
14661 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14662 dev_priv->display.get_initial_plane_config =
14663 ironlake_get_initial_plane_config;
14664 dev_priv->display.crtc_compute_clock =
14665 ironlake_crtc_compute_clock;
14666 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14667 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14668 dev_priv->display.update_primary_plane =
14669 ironlake_update_primary_plane;
14670 } else if (IS_VALLEYVIEW(dev)) {
14671 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14672 dev_priv->display.get_initial_plane_config =
14673 i9xx_get_initial_plane_config;
14674 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14675 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14676 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14677 dev_priv->display.update_primary_plane =
14678 i9xx_update_primary_plane;
14679 } else {
14680 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14681 dev_priv->display.get_initial_plane_config =
14682 i9xx_get_initial_plane_config;
14683 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14684 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14685 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14686 dev_priv->display.update_primary_plane =
14687 i9xx_update_primary_plane;
14688 }
14689
14690 /* Returns the core display clock speed */
14691 if (IS_SKYLAKE(dev))
14692 dev_priv->display.get_display_clock_speed =
14693 skylake_get_display_clock_speed;
14694 else if (IS_BROADWELL(dev))
14695 dev_priv->display.get_display_clock_speed =
14696 broadwell_get_display_clock_speed;
14697 else if (IS_HASWELL(dev))
14698 dev_priv->display.get_display_clock_speed =
14699 haswell_get_display_clock_speed;
14700 else if (IS_VALLEYVIEW(dev))
14701 dev_priv->display.get_display_clock_speed =
14702 valleyview_get_display_clock_speed;
14703 else if (IS_GEN5(dev))
14704 dev_priv->display.get_display_clock_speed =
14705 ilk_get_display_clock_speed;
14706 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14707 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14708 dev_priv->display.get_display_clock_speed =
14709 i945_get_display_clock_speed;
14710 else if (IS_GM45(dev))
14711 dev_priv->display.get_display_clock_speed =
14712 gm45_get_display_clock_speed;
14713 else if (IS_CRESTLINE(dev))
14714 dev_priv->display.get_display_clock_speed =
14715 i965gm_get_display_clock_speed;
14716 else if (IS_PINEVIEW(dev))
14717 dev_priv->display.get_display_clock_speed =
14718 pnv_get_display_clock_speed;
14719 else if (IS_G33(dev) || IS_G4X(dev))
14720 dev_priv->display.get_display_clock_speed =
14721 g33_get_display_clock_speed;
14722 else if (IS_I915G(dev))
14723 dev_priv->display.get_display_clock_speed =
14724 i915_get_display_clock_speed;
14725 else if (IS_I945GM(dev) || IS_845G(dev))
14726 dev_priv->display.get_display_clock_speed =
14727 i9xx_misc_get_display_clock_speed;
14728 else if (IS_PINEVIEW(dev))
14729 dev_priv->display.get_display_clock_speed =
14730 pnv_get_display_clock_speed;
14731 else if (IS_I915GM(dev))
14732 dev_priv->display.get_display_clock_speed =
14733 i915gm_get_display_clock_speed;
14734 else if (IS_I865G(dev))
14735 dev_priv->display.get_display_clock_speed =
14736 i865_get_display_clock_speed;
14737 else if (IS_I85X(dev))
14738 dev_priv->display.get_display_clock_speed =
14739 i85x_get_display_clock_speed;
14740 else { /* 830 */
14741 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14742 dev_priv->display.get_display_clock_speed =
14743 i830_get_display_clock_speed;
14744 }
14745
14746 if (IS_GEN5(dev)) {
14747 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14748 } else if (IS_GEN6(dev)) {
14749 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14750 } else if (IS_IVYBRIDGE(dev)) {
14751 /* FIXME: detect B0+ stepping and use auto training */
14752 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14753 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14754 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14755 if (IS_BROADWELL(dev)) {
14756 dev_priv->display.modeset_commit_cdclk =
14757 broadwell_modeset_commit_cdclk;
14758 dev_priv->display.modeset_calc_cdclk =
14759 broadwell_modeset_calc_cdclk;
14760 }
14761 } else if (IS_VALLEYVIEW(dev)) {
14762 dev_priv->display.modeset_commit_cdclk =
14763 valleyview_modeset_commit_cdclk;
14764 dev_priv->display.modeset_calc_cdclk =
14765 valleyview_modeset_calc_cdclk;
14766 } else if (IS_BROXTON(dev)) {
14767 dev_priv->display.modeset_commit_cdclk =
14768 broxton_modeset_commit_cdclk;
14769 dev_priv->display.modeset_calc_cdclk =
14770 broxton_modeset_calc_cdclk;
14771 }
14772
14773 switch (INTEL_INFO(dev)->gen) {
14774 case 2:
14775 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14776 break;
14777
14778 case 3:
14779 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14780 break;
14781
14782 case 4:
14783 case 5:
14784 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14785 break;
14786
14787 case 6:
14788 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14789 break;
14790 case 7:
14791 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14792 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14793 break;
14794 case 9:
14795 /* Drop through - unsupported since execlist only. */
14796 default:
14797 /* Default just returns -ENODEV to indicate unsupported */
14798 dev_priv->display.queue_flip = intel_default_queue_flip;
14799 }
14800
14801 intel_panel_init_backlight_funcs(dev);
14802
14803 mutex_init(&dev_priv->pps_mutex);
14804 }
14805
14806 /*
14807 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14808 * resume, or other times. This quirk makes sure that's the case for
14809 * affected systems.
14810 */
14811 static void quirk_pipea_force(struct drm_device *dev)
14812 {
14813 struct drm_i915_private *dev_priv = dev->dev_private;
14814
14815 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14816 DRM_INFO("applying pipe a force quirk\n");
14817 }
14818
14819 static void quirk_pipeb_force(struct drm_device *dev)
14820 {
14821 struct drm_i915_private *dev_priv = dev->dev_private;
14822
14823 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14824 DRM_INFO("applying pipe b force quirk\n");
14825 }
14826
14827 /*
14828 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14829 */
14830 static void quirk_ssc_force_disable(struct drm_device *dev)
14831 {
14832 struct drm_i915_private *dev_priv = dev->dev_private;
14833 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14834 DRM_INFO("applying lvds SSC disable quirk\n");
14835 }
14836
14837 /*
14838 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14839 * brightness value
14840 */
14841 static void quirk_invert_brightness(struct drm_device *dev)
14842 {
14843 struct drm_i915_private *dev_priv = dev->dev_private;
14844 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14845 DRM_INFO("applying inverted panel brightness quirk\n");
14846 }
14847
14848 /* Some VBT's incorrectly indicate no backlight is present */
14849 static void quirk_backlight_present(struct drm_device *dev)
14850 {
14851 struct drm_i915_private *dev_priv = dev->dev_private;
14852 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14853 DRM_INFO("applying backlight present quirk\n");
14854 }
14855
14856 struct intel_quirk {
14857 int device;
14858 int subsystem_vendor;
14859 int subsystem_device;
14860 void (*hook)(struct drm_device *dev);
14861 };
14862
14863 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14864 struct intel_dmi_quirk {
14865 void (*hook)(struct drm_device *dev);
14866 const struct dmi_system_id (*dmi_id_list)[];
14867 };
14868
14869 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14870 {
14871 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14872 return 1;
14873 }
14874
14875 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14876 {
14877 .dmi_id_list = &(const struct dmi_system_id[]) {
14878 {
14879 .callback = intel_dmi_reverse_brightness,
14880 .ident = "NCR Corporation",
14881 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14882 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14883 },
14884 },
14885 { } /* terminating entry */
14886 },
14887 .hook = quirk_invert_brightness,
14888 },
14889 };
14890
14891 static struct intel_quirk intel_quirks[] = {
14892 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14893 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14894
14895 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14896 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14897
14898 /* 830 needs to leave pipe A & dpll A up */
14899 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14900
14901 /* 830 needs to leave pipe B & dpll B up */
14902 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14903
14904 /* Lenovo U160 cannot use SSC on LVDS */
14905 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14906
14907 /* Sony Vaio Y cannot use SSC on LVDS */
14908 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14909
14910 /* Acer Aspire 5734Z must invert backlight brightness */
14911 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14912
14913 /* Acer/eMachines G725 */
14914 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14915
14916 /* Acer/eMachines e725 */
14917 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14918
14919 /* Acer/Packard Bell NCL20 */
14920 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14921
14922 /* Acer Aspire 4736Z */
14923 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14924
14925 /* Acer Aspire 5336 */
14926 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14927
14928 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14929 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14930
14931 /* Acer C720 Chromebook (Core i3 4005U) */
14932 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14933
14934 /* Apple Macbook 2,1 (Core 2 T7400) */
14935 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14936
14937 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14938 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14939
14940 /* HP Chromebook 14 (Celeron 2955U) */
14941 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14942
14943 /* Dell Chromebook 11 */
14944 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14945 };
14946
14947 static void intel_init_quirks(struct drm_device *dev)
14948 {
14949 struct pci_dev *d = dev->pdev;
14950 int i;
14951
14952 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14953 struct intel_quirk *q = &intel_quirks[i];
14954
14955 if (d->device == q->device &&
14956 (d->subsystem_vendor == q->subsystem_vendor ||
14957 q->subsystem_vendor == PCI_ANY_ID) &&
14958 (d->subsystem_device == q->subsystem_device ||
14959 q->subsystem_device == PCI_ANY_ID))
14960 q->hook(dev);
14961 }
14962 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14963 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14964 intel_dmi_quirks[i].hook(dev);
14965 }
14966 }
14967
14968 /* Disable the VGA plane that we never use */
14969 static void i915_disable_vga(struct drm_device *dev)
14970 {
14971 struct drm_i915_private *dev_priv = dev->dev_private;
14972 u8 sr1;
14973 u32 vga_reg = i915_vgacntrl_reg(dev);
14974
14975 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14976 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14977 outb(SR01, VGA_SR_INDEX);
14978 sr1 = inb(VGA_SR_DATA);
14979 outb(sr1 | 1<<5, VGA_SR_DATA);
14980 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14981 udelay(300);
14982
14983 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14984 POSTING_READ(vga_reg);
14985 }
14986
14987 void intel_modeset_init_hw(struct drm_device *dev)
14988 {
14989 intel_update_cdclk(dev);
14990 intel_prepare_ddi(dev);
14991 intel_init_clock_gating(dev);
14992 intel_enable_gt_powersave(dev);
14993 }
14994
14995 void intel_modeset_init(struct drm_device *dev)
14996 {
14997 struct drm_i915_private *dev_priv = dev->dev_private;
14998 int sprite, ret;
14999 enum pipe pipe;
15000 struct intel_crtc *crtc;
15001
15002 drm_mode_config_init(dev);
15003
15004 dev->mode_config.min_width = 0;
15005 dev->mode_config.min_height = 0;
15006
15007 dev->mode_config.preferred_depth = 24;
15008 dev->mode_config.prefer_shadow = 1;
15009
15010 dev->mode_config.allow_fb_modifiers = true;
15011
15012 dev->mode_config.funcs = &intel_mode_funcs;
15013
15014 intel_init_quirks(dev);
15015
15016 intel_init_pm(dev);
15017
15018 if (INTEL_INFO(dev)->num_pipes == 0)
15019 return;
15020
15021 intel_init_display(dev);
15022 intel_init_audio(dev);
15023
15024 if (IS_GEN2(dev)) {
15025 dev->mode_config.max_width = 2048;
15026 dev->mode_config.max_height = 2048;
15027 } else if (IS_GEN3(dev)) {
15028 dev->mode_config.max_width = 4096;
15029 dev->mode_config.max_height = 4096;
15030 } else {
15031 dev->mode_config.max_width = 8192;
15032 dev->mode_config.max_height = 8192;
15033 }
15034
15035 if (IS_845G(dev) || IS_I865G(dev)) {
15036 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15037 dev->mode_config.cursor_height = 1023;
15038 } else if (IS_GEN2(dev)) {
15039 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15040 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15041 } else {
15042 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15043 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15044 }
15045
15046 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15047
15048 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15049 INTEL_INFO(dev)->num_pipes,
15050 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15051
15052 for_each_pipe(dev_priv, pipe) {
15053 intel_crtc_init(dev, pipe);
15054 for_each_sprite(dev_priv, pipe, sprite) {
15055 ret = intel_plane_init(dev, pipe, sprite);
15056 if (ret)
15057 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15058 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15059 }
15060 }
15061
15062 intel_init_dpio(dev);
15063
15064 intel_shared_dpll_init(dev);
15065
15066 /* Just disable it once at startup */
15067 i915_disable_vga(dev);
15068 intel_setup_outputs(dev);
15069
15070 /* Just in case the BIOS is doing something questionable. */
15071 intel_fbc_disable(dev);
15072
15073 drm_modeset_lock_all(dev);
15074 intel_modeset_setup_hw_state(dev, false);
15075 drm_modeset_unlock_all(dev);
15076
15077 for_each_intel_crtc(dev, crtc) {
15078 if (!crtc->active)
15079 continue;
15080
15081 /*
15082 * Note that reserving the BIOS fb up front prevents us
15083 * from stuffing other stolen allocations like the ring
15084 * on top. This prevents some ugliness at boot time, and
15085 * can even allow for smooth boot transitions if the BIOS
15086 * fb is large enough for the active pipe configuration.
15087 */
15088 if (dev_priv->display.get_initial_plane_config) {
15089 dev_priv->display.get_initial_plane_config(crtc,
15090 &crtc->plane_config);
15091 /*
15092 * If the fb is shared between multiple heads, we'll
15093 * just get the first one.
15094 */
15095 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15096 }
15097 }
15098 }
15099
15100 static void intel_enable_pipe_a(struct drm_device *dev)
15101 {
15102 struct intel_connector *connector;
15103 struct drm_connector *crt = NULL;
15104 struct intel_load_detect_pipe load_detect_temp;
15105 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15106
15107 /* We can't just switch on the pipe A, we need to set things up with a
15108 * proper mode and output configuration. As a gross hack, enable pipe A
15109 * by enabling the load detect pipe once. */
15110 for_each_intel_connector(dev, connector) {
15111 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15112 crt = &connector->base;
15113 break;
15114 }
15115 }
15116
15117 if (!crt)
15118 return;
15119
15120 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15121 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15122 }
15123
15124 static bool
15125 intel_check_plane_mapping(struct intel_crtc *crtc)
15126 {
15127 struct drm_device *dev = crtc->base.dev;
15128 struct drm_i915_private *dev_priv = dev->dev_private;
15129 u32 reg, val;
15130
15131 if (INTEL_INFO(dev)->num_pipes == 1)
15132 return true;
15133
15134 reg = DSPCNTR(!crtc->plane);
15135 val = I915_READ(reg);
15136
15137 if ((val & DISPLAY_PLANE_ENABLE) &&
15138 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15139 return false;
15140
15141 return true;
15142 }
15143
15144 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15145 {
15146 struct drm_device *dev = crtc->base.dev;
15147 struct drm_i915_private *dev_priv = dev->dev_private;
15148 struct intel_encoder *encoder;
15149 u32 reg;
15150 bool enable;
15151
15152 /* Clear any frame start delays used for debugging left by the BIOS */
15153 reg = PIPECONF(crtc->config->cpu_transcoder);
15154 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15155
15156 /* restore vblank interrupts to correct state */
15157 drm_crtc_vblank_reset(&crtc->base);
15158 if (crtc->active) {
15159 update_scanline_offset(crtc);
15160 drm_crtc_vblank_on(&crtc->base);
15161 }
15162
15163 /* We need to sanitize the plane -> pipe mapping first because this will
15164 * disable the crtc (and hence change the state) if it is wrong. Note
15165 * that gen4+ has a fixed plane -> pipe mapping. */
15166 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15167 bool plane;
15168
15169 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15170 crtc->base.base.id);
15171
15172 /* Pipe has the wrong plane attached and the plane is active.
15173 * Temporarily change the plane mapping and disable everything
15174 * ... */
15175 plane = crtc->plane;
15176 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15177 crtc->plane = !plane;
15178 intel_crtc_disable_noatomic(&crtc->base);
15179 crtc->plane = plane;
15180 }
15181
15182 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15183 crtc->pipe == PIPE_A && !crtc->active) {
15184 /* BIOS forgot to enable pipe A, this mostly happens after
15185 * resume. Force-enable the pipe to fix this, the update_dpms
15186 * call below we restore the pipe to the right state, but leave
15187 * the required bits on. */
15188 intel_enable_pipe_a(dev);
15189 }
15190
15191 /* Adjust the state of the output pipe according to whether we
15192 * have active connectors/encoders. */
15193 enable = false;
15194 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15195 enable |= encoder->connectors_active;
15196
15197 if (!enable)
15198 intel_crtc_disable_noatomic(&crtc->base);
15199
15200 if (crtc->active != crtc->base.state->active) {
15201
15202 /* This can happen either due to bugs in the get_hw_state
15203 * functions or because of calls to intel_crtc_disable_noatomic,
15204 * or because the pipe is force-enabled due to the
15205 * pipe A quirk. */
15206 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15207 crtc->base.base.id,
15208 crtc->base.state->enable ? "enabled" : "disabled",
15209 crtc->active ? "enabled" : "disabled");
15210
15211 crtc->base.state->enable = crtc->active;
15212 crtc->base.state->active = crtc->active;
15213 crtc->base.enabled = crtc->active;
15214
15215 /* Because we only establish the connector -> encoder ->
15216 * crtc links if something is active, this means the
15217 * crtc is now deactivated. Break the links. connector
15218 * -> encoder links are only establish when things are
15219 * actually up, hence no need to break them. */
15220 WARN_ON(crtc->active);
15221
15222 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15223 WARN_ON(encoder->connectors_active);
15224 encoder->base.crtc = NULL;
15225 }
15226 }
15227
15228 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15229 /*
15230 * We start out with underrun reporting disabled to avoid races.
15231 * For correct bookkeeping mark this on active crtcs.
15232 *
15233 * Also on gmch platforms we dont have any hardware bits to
15234 * disable the underrun reporting. Which means we need to start
15235 * out with underrun reporting disabled also on inactive pipes,
15236 * since otherwise we'll complain about the garbage we read when
15237 * e.g. coming up after runtime pm.
15238 *
15239 * No protection against concurrent access is required - at
15240 * worst a fifo underrun happens which also sets this to false.
15241 */
15242 crtc->cpu_fifo_underrun_disabled = true;
15243 crtc->pch_fifo_underrun_disabled = true;
15244 }
15245 }
15246
15247 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15248 {
15249 struct intel_connector *connector;
15250 struct drm_device *dev = encoder->base.dev;
15251
15252 /* We need to check both for a crtc link (meaning that the
15253 * encoder is active and trying to read from a pipe) and the
15254 * pipe itself being active. */
15255 bool has_active_crtc = encoder->base.crtc &&
15256 to_intel_crtc(encoder->base.crtc)->active;
15257
15258 if (encoder->connectors_active && !has_active_crtc) {
15259 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15260 encoder->base.base.id,
15261 encoder->base.name);
15262
15263 /* Connector is active, but has no active pipe. This is
15264 * fallout from our resume register restoring. Disable
15265 * the encoder manually again. */
15266 if (encoder->base.crtc) {
15267 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15268 encoder->base.base.id,
15269 encoder->base.name);
15270 encoder->disable(encoder);
15271 if (encoder->post_disable)
15272 encoder->post_disable(encoder);
15273 }
15274 encoder->base.crtc = NULL;
15275 encoder->connectors_active = false;
15276
15277 /* Inconsistent output/port/pipe state happens presumably due to
15278 * a bug in one of the get_hw_state functions. Or someplace else
15279 * in our code, like the register restore mess on resume. Clamp
15280 * things to off as a safer default. */
15281 for_each_intel_connector(dev, connector) {
15282 if (connector->encoder != encoder)
15283 continue;
15284 connector->base.dpms = DRM_MODE_DPMS_OFF;
15285 connector->base.encoder = NULL;
15286 }
15287 }
15288 /* Enabled encoders without active connectors will be fixed in
15289 * the crtc fixup. */
15290 }
15291
15292 void i915_redisable_vga_power_on(struct drm_device *dev)
15293 {
15294 struct drm_i915_private *dev_priv = dev->dev_private;
15295 u32 vga_reg = i915_vgacntrl_reg(dev);
15296
15297 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15298 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15299 i915_disable_vga(dev);
15300 }
15301 }
15302
15303 void i915_redisable_vga(struct drm_device *dev)
15304 {
15305 struct drm_i915_private *dev_priv = dev->dev_private;
15306
15307 /* This function can be called both from intel_modeset_setup_hw_state or
15308 * at a very early point in our resume sequence, where the power well
15309 * structures are not yet restored. Since this function is at a very
15310 * paranoid "someone might have enabled VGA while we were not looking"
15311 * level, just check if the power well is enabled instead of trying to
15312 * follow the "don't touch the power well if we don't need it" policy
15313 * the rest of the driver uses. */
15314 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15315 return;
15316
15317 i915_redisable_vga_power_on(dev);
15318 }
15319
15320 static bool primary_get_hw_state(struct intel_crtc *crtc)
15321 {
15322 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15323
15324 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15325 }
15326
15327 static void readout_plane_state(struct intel_crtc *crtc,
15328 struct intel_crtc_state *crtc_state)
15329 {
15330 struct intel_plane *p;
15331 struct drm_plane_state *drm_plane_state;
15332 bool active = crtc_state->base.active;
15333
15334 if (active) {
15335 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15336
15337 /* apply to previous sw state too */
15338 to_intel_crtc_state(crtc->base.state)->quirks |=
15339 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15340 }
15341
15342 for_each_intel_plane(crtc->base.dev, p) {
15343 bool visible = active;
15344
15345 if (crtc->pipe != p->pipe)
15346 continue;
15347
15348 drm_plane_state = p->base.state;
15349 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15350 visible = primary_get_hw_state(crtc);
15351 to_intel_plane_state(drm_plane_state)->visible = visible;
15352 } else {
15353 /*
15354 * unknown state, assume it's off to force a transition
15355 * to on when calculating state changes.
15356 */
15357 to_intel_plane_state(drm_plane_state)->visible = false;
15358 }
15359
15360 if (visible) {
15361 crtc_state->base.plane_mask |=
15362 1 << drm_plane_index(&p->base);
15363 } else if (crtc_state->base.state) {
15364 /* Make this unconditional for atomic hw readout. */
15365 crtc_state->base.plane_mask &=
15366 ~(1 << drm_plane_index(&p->base));
15367 }
15368 }
15369 }
15370
15371 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15372 {
15373 struct drm_i915_private *dev_priv = dev->dev_private;
15374 enum pipe pipe;
15375 struct intel_crtc *crtc;
15376 struct intel_encoder *encoder;
15377 struct intel_connector *connector;
15378 int i;
15379
15380 for_each_intel_crtc(dev, crtc) {
15381 memset(crtc->config, 0, sizeof(*crtc->config));
15382 crtc->config->base.crtc = &crtc->base;
15383
15384 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15385
15386 crtc->active = dev_priv->display.get_pipe_config(crtc,
15387 crtc->config);
15388
15389 crtc->base.state->enable = crtc->active;
15390 crtc->base.state->active = crtc->active;
15391 crtc->base.enabled = crtc->active;
15392 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15393
15394 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15395
15396 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15397 crtc->base.base.id,
15398 crtc->active ? "enabled" : "disabled");
15399 }
15400
15401 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15402 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15403
15404 pll->on = pll->get_hw_state(dev_priv, pll,
15405 &pll->config.hw_state);
15406 pll->active = 0;
15407 pll->config.crtc_mask = 0;
15408 for_each_intel_crtc(dev, crtc) {
15409 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15410 pll->active++;
15411 pll->config.crtc_mask |= 1 << crtc->pipe;
15412 }
15413 }
15414
15415 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15416 pll->name, pll->config.crtc_mask, pll->on);
15417
15418 if (pll->config.crtc_mask)
15419 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15420 }
15421
15422 for_each_intel_encoder(dev, encoder) {
15423 pipe = 0;
15424
15425 if (encoder->get_hw_state(encoder, &pipe)) {
15426 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15427 encoder->base.crtc = &crtc->base;
15428 encoder->get_config(encoder, crtc->config);
15429 } else {
15430 encoder->base.crtc = NULL;
15431 }
15432
15433 encoder->connectors_active = false;
15434 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15435 encoder->base.base.id,
15436 encoder->base.name,
15437 encoder->base.crtc ? "enabled" : "disabled",
15438 pipe_name(pipe));
15439 }
15440
15441 for_each_intel_connector(dev, connector) {
15442 if (connector->get_hw_state(connector)) {
15443 connector->base.dpms = DRM_MODE_DPMS_ON;
15444 connector->encoder->connectors_active = true;
15445 connector->base.encoder = &connector->encoder->base;
15446 } else {
15447 connector->base.dpms = DRM_MODE_DPMS_OFF;
15448 connector->base.encoder = NULL;
15449 }
15450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15451 connector->base.base.id,
15452 connector->base.name,
15453 connector->base.encoder ? "enabled" : "disabled");
15454 }
15455 }
15456
15457 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15458 * and i915 state tracking structures. */
15459 void intel_modeset_setup_hw_state(struct drm_device *dev,
15460 bool force_restore)
15461 {
15462 struct drm_i915_private *dev_priv = dev->dev_private;
15463 enum pipe pipe;
15464 struct intel_crtc *crtc;
15465 struct intel_encoder *encoder;
15466 int i;
15467
15468 intel_modeset_readout_hw_state(dev);
15469
15470 /*
15471 * Now that we have the config, copy it to each CRTC struct
15472 * Note that this could go away if we move to using crtc_config
15473 * checking everywhere.
15474 */
15475 for_each_intel_crtc(dev, crtc) {
15476 if (crtc->active && i915.fastboot) {
15477 intel_mode_from_pipe_config(&crtc->base.mode,
15478 crtc->config);
15479 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15480 crtc->base.base.id);
15481 drm_mode_debug_printmodeline(&crtc->base.mode);
15482 }
15483 }
15484
15485 /* HW state is read out, now we need to sanitize this mess. */
15486 for_each_intel_encoder(dev, encoder) {
15487 intel_sanitize_encoder(encoder);
15488 }
15489
15490 for_each_pipe(dev_priv, pipe) {
15491 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15492 intel_sanitize_crtc(crtc);
15493 intel_dump_pipe_config(crtc, crtc->config,
15494 "[setup_hw_state]");
15495 }
15496
15497 intel_modeset_update_connector_atomic_state(dev);
15498
15499 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15500 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15501
15502 if (!pll->on || pll->active)
15503 continue;
15504
15505 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15506
15507 pll->disable(dev_priv, pll);
15508 pll->on = false;
15509 }
15510
15511 if (IS_GEN9(dev))
15512 skl_wm_get_hw_state(dev);
15513 else if (HAS_PCH_SPLIT(dev))
15514 ilk_wm_get_hw_state(dev);
15515
15516 if (force_restore) {
15517 i915_redisable_vga(dev);
15518
15519 /*
15520 * We need to use raw interfaces for restoring state to avoid
15521 * checking (bogus) intermediate states.
15522 */
15523 for_each_pipe(dev_priv, pipe) {
15524 struct drm_crtc *crtc =
15525 dev_priv->pipe_to_crtc_mapping[pipe];
15526
15527 intel_crtc_restore_mode(crtc);
15528 }
15529 } else {
15530 intel_modeset_update_staged_output_state(dev);
15531 }
15532
15533 intel_modeset_check_state(dev);
15534 }
15535
15536 void intel_modeset_gem_init(struct drm_device *dev)
15537 {
15538 struct drm_i915_private *dev_priv = dev->dev_private;
15539 struct drm_crtc *c;
15540 struct drm_i915_gem_object *obj;
15541 int ret;
15542
15543 mutex_lock(&dev->struct_mutex);
15544 intel_init_gt_powersave(dev);
15545 mutex_unlock(&dev->struct_mutex);
15546
15547 /*
15548 * There may be no VBT; and if the BIOS enabled SSC we can
15549 * just keep using it to avoid unnecessary flicker. Whereas if the
15550 * BIOS isn't using it, don't assume it will work even if the VBT
15551 * indicates as much.
15552 */
15553 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15554 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15555 DREF_SSC1_ENABLE);
15556
15557 intel_modeset_init_hw(dev);
15558
15559 intel_setup_overlay(dev);
15560
15561 /*
15562 * Make sure any fbs we allocated at startup are properly
15563 * pinned & fenced. When we do the allocation it's too early
15564 * for this.
15565 */
15566 for_each_crtc(dev, c) {
15567 obj = intel_fb_obj(c->primary->fb);
15568 if (obj == NULL)
15569 continue;
15570
15571 mutex_lock(&dev->struct_mutex);
15572 ret = intel_pin_and_fence_fb_obj(c->primary,
15573 c->primary->fb,
15574 c->primary->state,
15575 NULL, NULL);
15576 mutex_unlock(&dev->struct_mutex);
15577 if (ret) {
15578 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15579 to_intel_crtc(c)->pipe);
15580 drm_framebuffer_unreference(c->primary->fb);
15581 c->primary->fb = NULL;
15582 c->primary->crtc = c->primary->state->crtc = NULL;
15583 update_state_fb(c->primary);
15584 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15585 }
15586 }
15587
15588 intel_backlight_register(dev);
15589 }
15590
15591 void intel_connector_unregister(struct intel_connector *intel_connector)
15592 {
15593 struct drm_connector *connector = &intel_connector->base;
15594
15595 intel_panel_destroy_backlight(connector);
15596 drm_connector_unregister(connector);
15597 }
15598
15599 void intel_modeset_cleanup(struct drm_device *dev)
15600 {
15601 struct drm_i915_private *dev_priv = dev->dev_private;
15602 struct drm_connector *connector;
15603
15604 intel_disable_gt_powersave(dev);
15605
15606 intel_backlight_unregister(dev);
15607
15608 /*
15609 * Interrupts and polling as the first thing to avoid creating havoc.
15610 * Too much stuff here (turning of connectors, ...) would
15611 * experience fancy races otherwise.
15612 */
15613 intel_irq_uninstall(dev_priv);
15614
15615 /*
15616 * Due to the hpd irq storm handling the hotplug work can re-arm the
15617 * poll handlers. Hence disable polling after hpd handling is shut down.
15618 */
15619 drm_kms_helper_poll_fini(dev);
15620
15621 mutex_lock(&dev->struct_mutex);
15622
15623 intel_unregister_dsm_handler();
15624
15625 intel_fbc_disable(dev);
15626
15627 mutex_unlock(&dev->struct_mutex);
15628
15629 /* flush any delayed tasks or pending work */
15630 flush_scheduled_work();
15631
15632 /* destroy the backlight and sysfs files before encoders/connectors */
15633 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15634 struct intel_connector *intel_connector;
15635
15636 intel_connector = to_intel_connector(connector);
15637 intel_connector->unregister(intel_connector);
15638 }
15639
15640 drm_mode_config_cleanup(dev);
15641
15642 intel_cleanup_overlay(dev);
15643
15644 mutex_lock(&dev->struct_mutex);
15645 intel_cleanup_gt_powersave(dev);
15646 mutex_unlock(&dev->struct_mutex);
15647 }
15648
15649 /*
15650 * Return which encoder is currently attached for connector.
15651 */
15652 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15653 {
15654 return &intel_attached_encoder(connector)->base;
15655 }
15656
15657 void intel_connector_attach_encoder(struct intel_connector *connector,
15658 struct intel_encoder *encoder)
15659 {
15660 connector->encoder = encoder;
15661 drm_mode_connector_attach_encoder(&connector->base,
15662 &encoder->base);
15663 }
15664
15665 /*
15666 * set vga decode state - true == enable VGA decode
15667 */
15668 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15669 {
15670 struct drm_i915_private *dev_priv = dev->dev_private;
15671 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15672 u16 gmch_ctrl;
15673
15674 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15675 DRM_ERROR("failed to read control word\n");
15676 return -EIO;
15677 }
15678
15679 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15680 return 0;
15681
15682 if (state)
15683 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15684 else
15685 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15686
15687 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15688 DRM_ERROR("failed to write control word\n");
15689 return -EIO;
15690 }
15691
15692 return 0;
15693 }
15694
15695 struct intel_display_error_state {
15696
15697 u32 power_well_driver;
15698
15699 int num_transcoders;
15700
15701 struct intel_cursor_error_state {
15702 u32 control;
15703 u32 position;
15704 u32 base;
15705 u32 size;
15706 } cursor[I915_MAX_PIPES];
15707
15708 struct intel_pipe_error_state {
15709 bool power_domain_on;
15710 u32 source;
15711 u32 stat;
15712 } pipe[I915_MAX_PIPES];
15713
15714 struct intel_plane_error_state {
15715 u32 control;
15716 u32 stride;
15717 u32 size;
15718 u32 pos;
15719 u32 addr;
15720 u32 surface;
15721 u32 tile_offset;
15722 } plane[I915_MAX_PIPES];
15723
15724 struct intel_transcoder_error_state {
15725 bool power_domain_on;
15726 enum transcoder cpu_transcoder;
15727
15728 u32 conf;
15729
15730 u32 htotal;
15731 u32 hblank;
15732 u32 hsync;
15733 u32 vtotal;
15734 u32 vblank;
15735 u32 vsync;
15736 } transcoder[4];
15737 };
15738
15739 struct intel_display_error_state *
15740 intel_display_capture_error_state(struct drm_device *dev)
15741 {
15742 struct drm_i915_private *dev_priv = dev->dev_private;
15743 struct intel_display_error_state *error;
15744 int transcoders[] = {
15745 TRANSCODER_A,
15746 TRANSCODER_B,
15747 TRANSCODER_C,
15748 TRANSCODER_EDP,
15749 };
15750 int i;
15751
15752 if (INTEL_INFO(dev)->num_pipes == 0)
15753 return NULL;
15754
15755 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15756 if (error == NULL)
15757 return NULL;
15758
15759 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15760 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15761
15762 for_each_pipe(dev_priv, i) {
15763 error->pipe[i].power_domain_on =
15764 __intel_display_power_is_enabled(dev_priv,
15765 POWER_DOMAIN_PIPE(i));
15766 if (!error->pipe[i].power_domain_on)
15767 continue;
15768
15769 error->cursor[i].control = I915_READ(CURCNTR(i));
15770 error->cursor[i].position = I915_READ(CURPOS(i));
15771 error->cursor[i].base = I915_READ(CURBASE(i));
15772
15773 error->plane[i].control = I915_READ(DSPCNTR(i));
15774 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15775 if (INTEL_INFO(dev)->gen <= 3) {
15776 error->plane[i].size = I915_READ(DSPSIZE(i));
15777 error->plane[i].pos = I915_READ(DSPPOS(i));
15778 }
15779 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15780 error->plane[i].addr = I915_READ(DSPADDR(i));
15781 if (INTEL_INFO(dev)->gen >= 4) {
15782 error->plane[i].surface = I915_READ(DSPSURF(i));
15783 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15784 }
15785
15786 error->pipe[i].source = I915_READ(PIPESRC(i));
15787
15788 if (HAS_GMCH_DISPLAY(dev))
15789 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15790 }
15791
15792 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15793 if (HAS_DDI(dev_priv->dev))
15794 error->num_transcoders++; /* Account for eDP. */
15795
15796 for (i = 0; i < error->num_transcoders; i++) {
15797 enum transcoder cpu_transcoder = transcoders[i];
15798
15799 error->transcoder[i].power_domain_on =
15800 __intel_display_power_is_enabled(dev_priv,
15801 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15802 if (!error->transcoder[i].power_domain_on)
15803 continue;
15804
15805 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15806
15807 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15808 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15809 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15810 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15811 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15812 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15813 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15814 }
15815
15816 return error;
15817 }
15818
15819 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15820
15821 void
15822 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15823 struct drm_device *dev,
15824 struct intel_display_error_state *error)
15825 {
15826 struct drm_i915_private *dev_priv = dev->dev_private;
15827 int i;
15828
15829 if (!error)
15830 return;
15831
15832 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15833 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15834 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15835 error->power_well_driver);
15836 for_each_pipe(dev_priv, i) {
15837 err_printf(m, "Pipe [%d]:\n", i);
15838 err_printf(m, " Power: %s\n",
15839 error->pipe[i].power_domain_on ? "on" : "off");
15840 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15841 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15842
15843 err_printf(m, "Plane [%d]:\n", i);
15844 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15845 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15846 if (INTEL_INFO(dev)->gen <= 3) {
15847 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15848 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15849 }
15850 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15851 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15852 if (INTEL_INFO(dev)->gen >= 4) {
15853 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15854 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15855 }
15856
15857 err_printf(m, "Cursor [%d]:\n", i);
15858 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15859 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15860 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15861 }
15862
15863 for (i = 0; i < error->num_transcoders; i++) {
15864 err_printf(m, "CPU transcoder: %c\n",
15865 transcoder_name(error->transcoder[i].cpu_transcoder));
15866 err_printf(m, " Power: %s\n",
15867 error->transcoder[i].power_domain_on ? "on" : "off");
15868 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15869 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15870 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15871 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15872 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15873 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15874 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15875 }
15876 }
15877
15878 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15879 {
15880 struct intel_crtc *crtc;
15881
15882 for_each_intel_crtc(dev, crtc) {
15883 struct intel_unpin_work *work;
15884
15885 spin_lock_irq(&dev->event_lock);
15886
15887 work = crtc->unpin_work;
15888
15889 if (work && work->event &&
15890 work->event->base.file_priv == file) {
15891 kfree(work->event);
15892 work->event = NULL;
15893 }
15894
15895 spin_unlock_irq(&dev->event_lock);
15896 }
15897 }
Linux kernel - Deliverables
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