2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
48 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
49 struct intel_crtc_config
*pipe_config
);
50 static void ironlake_crtc_clock_get(struct intel_crtc
*crtc
,
51 struct intel_crtc_config
*pipe_config
);
53 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
54 int x
, int y
, struct drm_framebuffer
*old_fb
);
66 typedef struct intel_limit intel_limit_t
;
68 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
73 intel_pch_rawclk(struct drm_device
*dev
)
75 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
77 WARN_ON(!HAS_PCH_SPLIT(dev
));
79 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
82 static inline u32
/* units of 100MHz */
83 intel_fdi_link_freq(struct drm_device
*dev
)
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
87 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
92 static const intel_limit_t intel_limits_i8xx_dac
= {
93 .dot
= { .min
= 25000, .max
= 350000 },
94 .vco
= { .min
= 930000, .max
= 1400000 },
95 .n
= { .min
= 3, .max
= 16 },
96 .m
= { .min
= 96, .max
= 140 },
97 .m1
= { .min
= 18, .max
= 26 },
98 .m2
= { .min
= 6, .max
= 16 },
99 .p
= { .min
= 4, .max
= 128 },
100 .p1
= { .min
= 2, .max
= 33 },
101 .p2
= { .dot_limit
= 165000,
102 .p2_slow
= 4, .p2_fast
= 2 },
105 static const intel_limit_t intel_limits_i8xx_dvo
= {
106 .dot
= { .min
= 25000, .max
= 350000 },
107 .vco
= { .min
= 930000, .max
= 1400000 },
108 .n
= { .min
= 3, .max
= 16 },
109 .m
= { .min
= 96, .max
= 140 },
110 .m1
= { .min
= 18, .max
= 26 },
111 .m2
= { .min
= 6, .max
= 16 },
112 .p
= { .min
= 4, .max
= 128 },
113 .p1
= { .min
= 2, .max
= 33 },
114 .p2
= { .dot_limit
= 165000,
115 .p2_slow
= 4, .p2_fast
= 4 },
118 static const intel_limit_t intel_limits_i8xx_lvds
= {
119 .dot
= { .min
= 25000, .max
= 350000 },
120 .vco
= { .min
= 930000, .max
= 1400000 },
121 .n
= { .min
= 3, .max
= 16 },
122 .m
= { .min
= 96, .max
= 140 },
123 .m1
= { .min
= 18, .max
= 26 },
124 .m2
= { .min
= 6, .max
= 16 },
125 .p
= { .min
= 4, .max
= 128 },
126 .p1
= { .min
= 1, .max
= 6 },
127 .p2
= { .dot_limit
= 165000,
128 .p2_slow
= 14, .p2_fast
= 7 },
131 static const intel_limit_t intel_limits_i9xx_sdvo
= {
132 .dot
= { .min
= 20000, .max
= 400000 },
133 .vco
= { .min
= 1400000, .max
= 2800000 },
134 .n
= { .min
= 1, .max
= 6 },
135 .m
= { .min
= 70, .max
= 120 },
136 .m1
= { .min
= 8, .max
= 18 },
137 .m2
= { .min
= 3, .max
= 7 },
138 .p
= { .min
= 5, .max
= 80 },
139 .p1
= { .min
= 1, .max
= 8 },
140 .p2
= { .dot_limit
= 200000,
141 .p2_slow
= 10, .p2_fast
= 5 },
144 static const intel_limit_t intel_limits_i9xx_lvds
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 8, .max
= 18 },
150 .m2
= { .min
= 3, .max
= 7 },
151 .p
= { .min
= 7, .max
= 98 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 112000,
154 .p2_slow
= 14, .p2_fast
= 7 },
158 static const intel_limit_t intel_limits_g4x_sdvo
= {
159 .dot
= { .min
= 25000, .max
= 270000 },
160 .vco
= { .min
= 1750000, .max
= 3500000},
161 .n
= { .min
= 1, .max
= 4 },
162 .m
= { .min
= 104, .max
= 138 },
163 .m1
= { .min
= 17, .max
= 23 },
164 .m2
= { .min
= 5, .max
= 11 },
165 .p
= { .min
= 10, .max
= 30 },
166 .p1
= { .min
= 1, .max
= 3},
167 .p2
= { .dot_limit
= 270000,
173 static const intel_limit_t intel_limits_g4x_hdmi
= {
174 .dot
= { .min
= 22000, .max
= 400000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 16, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 5, .max
= 80 },
181 .p1
= { .min
= 1, .max
= 8},
182 .p2
= { .dot_limit
= 165000,
183 .p2_slow
= 10, .p2_fast
= 5 },
186 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
187 .dot
= { .min
= 20000, .max
= 115000 },
188 .vco
= { .min
= 1750000, .max
= 3500000 },
189 .n
= { .min
= 1, .max
= 3 },
190 .m
= { .min
= 104, .max
= 138 },
191 .m1
= { .min
= 17, .max
= 23 },
192 .m2
= { .min
= 5, .max
= 11 },
193 .p
= { .min
= 28, .max
= 112 },
194 .p1
= { .min
= 2, .max
= 8 },
195 .p2
= { .dot_limit
= 0,
196 .p2_slow
= 14, .p2_fast
= 14
200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
201 .dot
= { .min
= 80000, .max
= 224000 },
202 .vco
= { .min
= 1750000, .max
= 3500000 },
203 .n
= { .min
= 1, .max
= 3 },
204 .m
= { .min
= 104, .max
= 138 },
205 .m1
= { .min
= 17, .max
= 23 },
206 .m2
= { .min
= 5, .max
= 11 },
207 .p
= { .min
= 14, .max
= 42 },
208 .p1
= { .min
= 2, .max
= 6 },
209 .p2
= { .dot_limit
= 0,
210 .p2_slow
= 7, .p2_fast
= 7
214 static const intel_limit_t intel_limits_pineview_sdvo
= {
215 .dot
= { .min
= 20000, .max
= 400000},
216 .vco
= { .min
= 1700000, .max
= 3500000 },
217 /* Pineview's Ncounter is a ring counter */
218 .n
= { .min
= 3, .max
= 6 },
219 .m
= { .min
= 2, .max
= 256 },
220 /* Pineview only has one combined m divider, which we treat as m2. */
221 .m1
= { .min
= 0, .max
= 0 },
222 .m2
= { .min
= 0, .max
= 254 },
223 .p
= { .min
= 5, .max
= 80 },
224 .p1
= { .min
= 1, .max
= 8 },
225 .p2
= { .dot_limit
= 200000,
226 .p2_slow
= 10, .p2_fast
= 5 },
229 static const intel_limit_t intel_limits_pineview_lvds
= {
230 .dot
= { .min
= 20000, .max
= 400000 },
231 .vco
= { .min
= 1700000, .max
= 3500000 },
232 .n
= { .min
= 3, .max
= 6 },
233 .m
= { .min
= 2, .max
= 256 },
234 .m1
= { .min
= 0, .max
= 0 },
235 .m2
= { .min
= 0, .max
= 254 },
236 .p
= { .min
= 7, .max
= 112 },
237 .p1
= { .min
= 1, .max
= 8 },
238 .p2
= { .dot_limit
= 112000,
239 .p2_slow
= 14, .p2_fast
= 14 },
242 /* Ironlake / Sandybridge
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
247 static const intel_limit_t intel_limits_ironlake_dac
= {
248 .dot
= { .min
= 25000, .max
= 350000 },
249 .vco
= { .min
= 1760000, .max
= 3510000 },
250 .n
= { .min
= 1, .max
= 5 },
251 .m
= { .min
= 79, .max
= 127 },
252 .m1
= { .min
= 12, .max
= 22 },
253 .m2
= { .min
= 5, .max
= 9 },
254 .p
= { .min
= 5, .max
= 80 },
255 .p1
= { .min
= 1, .max
= 8 },
256 .p2
= { .dot_limit
= 225000,
257 .p2_slow
= 10, .p2_fast
= 5 },
260 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
261 .dot
= { .min
= 25000, .max
= 350000 },
262 .vco
= { .min
= 1760000, .max
= 3510000 },
263 .n
= { .min
= 1, .max
= 3 },
264 .m
= { .min
= 79, .max
= 118 },
265 .m1
= { .min
= 12, .max
= 22 },
266 .m2
= { .min
= 5, .max
= 9 },
267 .p
= { .min
= 28, .max
= 112 },
268 .p1
= { .min
= 2, .max
= 8 },
269 .p2
= { .dot_limit
= 225000,
270 .p2_slow
= 14, .p2_fast
= 14 },
273 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
274 .dot
= { .min
= 25000, .max
= 350000 },
275 .vco
= { .min
= 1760000, .max
= 3510000 },
276 .n
= { .min
= 1, .max
= 3 },
277 .m
= { .min
= 79, .max
= 127 },
278 .m1
= { .min
= 12, .max
= 22 },
279 .m2
= { .min
= 5, .max
= 9 },
280 .p
= { .min
= 14, .max
= 56 },
281 .p1
= { .min
= 2, .max
= 8 },
282 .p2
= { .dot_limit
= 225000,
283 .p2_slow
= 7, .p2_fast
= 7 },
286 /* LVDS 100mhz refclk limits. */
287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
288 .dot
= { .min
= 25000, .max
= 350000 },
289 .vco
= { .min
= 1760000, .max
= 3510000 },
290 .n
= { .min
= 1, .max
= 2 },
291 .m
= { .min
= 79, .max
= 126 },
292 .m1
= { .min
= 12, .max
= 22 },
293 .m2
= { .min
= 5, .max
= 9 },
294 .p
= { .min
= 28, .max
= 112 },
295 .p1
= { .min
= 2, .max
= 8 },
296 .p2
= { .dot_limit
= 225000,
297 .p2_slow
= 14, .p2_fast
= 14 },
300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 3 },
304 .m
= { .min
= 79, .max
= 126 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 14, .max
= 42 },
308 .p1
= { .min
= 2, .max
= 6 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 7, .p2_fast
= 7 },
313 static const intel_limit_t intel_limits_vlv_dac
= {
314 .dot
= { .min
= 25000, .max
= 270000 },
315 .vco
= { .min
= 4000000, .max
= 6000000 },
316 .n
= { .min
= 1, .max
= 7 },
317 .m
= { .min
= 22, .max
= 450 }, /* guess */
318 .m1
= { .min
= 2, .max
= 3 },
319 .m2
= { .min
= 11, .max
= 156 },
320 .p
= { .min
= 10, .max
= 30 },
321 .p1
= { .min
= 1, .max
= 3 },
322 .p2
= { .dot_limit
= 270000,
323 .p2_slow
= 2, .p2_fast
= 20 },
326 static const intel_limit_t intel_limits_vlv_hdmi
= {
327 .dot
= { .min
= 25000, .max
= 270000 },
328 .vco
= { .min
= 4000000, .max
= 6000000 },
329 .n
= { .min
= 1, .max
= 7 },
330 .m
= { .min
= 60, .max
= 300 }, /* guess */
331 .m1
= { .min
= 2, .max
= 3 },
332 .m2
= { .min
= 11, .max
= 156 },
333 .p
= { .min
= 10, .max
= 30 },
334 .p1
= { .min
= 2, .max
= 3 },
335 .p2
= { .dot_limit
= 270000,
336 .p2_slow
= 2, .p2_fast
= 20 },
339 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
342 struct drm_device
*dev
= crtc
->dev
;
343 const intel_limit_t
*limit
;
345 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
346 if (intel_is_dual_link_lvds(dev
)) {
347 if (refclk
== 100000)
348 limit
= &intel_limits_ironlake_dual_lvds_100m
;
350 limit
= &intel_limits_ironlake_dual_lvds
;
352 if (refclk
== 100000)
353 limit
= &intel_limits_ironlake_single_lvds_100m
;
355 limit
= &intel_limits_ironlake_single_lvds
;
358 limit
= &intel_limits_ironlake_dac
;
363 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
365 struct drm_device
*dev
= crtc
->dev
;
366 const intel_limit_t
*limit
;
368 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
369 if (intel_is_dual_link_lvds(dev
))
370 limit
= &intel_limits_g4x_dual_channel_lvds
;
372 limit
= &intel_limits_g4x_single_channel_lvds
;
373 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
374 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
375 limit
= &intel_limits_g4x_hdmi
;
376 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
377 limit
= &intel_limits_g4x_sdvo
;
378 } else /* The option is for other outputs */
379 limit
= &intel_limits_i9xx_sdvo
;
384 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
386 struct drm_device
*dev
= crtc
->dev
;
387 const intel_limit_t
*limit
;
389 if (HAS_PCH_SPLIT(dev
))
390 limit
= intel_ironlake_limit(crtc
, refclk
);
391 else if (IS_G4X(dev
)) {
392 limit
= intel_g4x_limit(crtc
);
393 } else if (IS_PINEVIEW(dev
)) {
394 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
395 limit
= &intel_limits_pineview_lvds
;
397 limit
= &intel_limits_pineview_sdvo
;
398 } else if (IS_VALLEYVIEW(dev
)) {
399 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
400 limit
= &intel_limits_vlv_dac
;
402 limit
= &intel_limits_vlv_hdmi
;
403 } else if (!IS_GEN2(dev
)) {
404 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
405 limit
= &intel_limits_i9xx_lvds
;
407 limit
= &intel_limits_i9xx_sdvo
;
409 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
410 limit
= &intel_limits_i8xx_lvds
;
411 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
412 limit
= &intel_limits_i8xx_dvo
;
414 limit
= &intel_limits_i8xx_dac
;
419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
420 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
422 clock
->m
= clock
->m2
+ 2;
423 clock
->p
= clock
->p1
* clock
->p2
;
424 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
425 clock
->dot
= clock
->vco
/ clock
->p
;
428 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
430 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
433 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
435 clock
->m
= i9xx_dpll_compute_m(clock
);
436 clock
->p
= clock
->p1
* clock
->p2
;
437 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
438 clock
->dot
= clock
->vco
/ clock
->p
;
442 * Returns whether any output on the specified pipe is of the specified type
444 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
446 struct drm_device
*dev
= crtc
->dev
;
447 struct intel_encoder
*encoder
;
449 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
450 if (encoder
->type
== type
)
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device
*dev
,
463 const intel_limit_t
*limit
,
464 const intel_clock_t
*clock
)
466 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
467 INTELPllInvalid("p1 out of range\n");
468 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
469 INTELPllInvalid("p out of range\n");
470 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
473 INTELPllInvalid("m1 out of range\n");
474 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
475 INTELPllInvalid("m1 <= m2\n");
476 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
477 INTELPllInvalid("m out of range\n");
478 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
479 INTELPllInvalid("n out of range\n");
480 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
493 int target
, int refclk
, intel_clock_t
*match_clock
,
494 intel_clock_t
*best_clock
)
496 struct drm_device
*dev
= crtc
->dev
;
500 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev
))
507 clock
.p2
= limit
->p2
.p2_fast
;
509 clock
.p2
= limit
->p2
.p2_slow
;
511 if (target
< limit
->p2
.dot_limit
)
512 clock
.p2
= limit
->p2
.p2_slow
;
514 clock
.p2
= limit
->p2
.p2_fast
;
517 memset(best_clock
, 0, sizeof(*best_clock
));
519 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
521 for (clock
.m2
= limit
->m2
.min
;
522 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
523 if (clock
.m2
>= clock
.m1
)
525 for (clock
.n
= limit
->n
.min
;
526 clock
.n
<= limit
->n
.max
; clock
.n
++) {
527 for (clock
.p1
= limit
->p1
.min
;
528 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
531 i9xx_clock(refclk
, &clock
);
532 if (!intel_PLL_is_valid(dev
, limit
,
536 clock
.p
!= match_clock
->p
)
539 this_err
= abs(clock
.dot
- target
);
540 if (this_err
< err
) {
549 return (err
!= target
);
553 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
554 int target
, int refclk
, intel_clock_t
*match_clock
,
555 intel_clock_t
*best_clock
)
557 struct drm_device
*dev
= crtc
->dev
;
561 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev
))
568 clock
.p2
= limit
->p2
.p2_fast
;
570 clock
.p2
= limit
->p2
.p2_slow
;
572 if (target
< limit
->p2
.dot_limit
)
573 clock
.p2
= limit
->p2
.p2_slow
;
575 clock
.p2
= limit
->p2
.p2_fast
;
578 memset(best_clock
, 0, sizeof(*best_clock
));
580 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
582 for (clock
.m2
= limit
->m2
.min
;
583 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
584 for (clock
.n
= limit
->n
.min
;
585 clock
.n
<= limit
->n
.max
; clock
.n
++) {
586 for (clock
.p1
= limit
->p1
.min
;
587 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
590 pineview_clock(refclk
, &clock
);
591 if (!intel_PLL_is_valid(dev
, limit
,
595 clock
.p
!= match_clock
->p
)
598 this_err
= abs(clock
.dot
- target
);
599 if (this_err
< err
) {
608 return (err
!= target
);
612 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
613 int target
, int refclk
, intel_clock_t
*match_clock
,
614 intel_clock_t
*best_clock
)
616 struct drm_device
*dev
= crtc
->dev
;
620 /* approximately equals target * 0.00585 */
621 int err_most
= (target
>> 8) + (target
>> 9);
624 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
625 if (intel_is_dual_link_lvds(dev
))
626 clock
.p2
= limit
->p2
.p2_fast
;
628 clock
.p2
= limit
->p2
.p2_slow
;
630 if (target
< limit
->p2
.dot_limit
)
631 clock
.p2
= limit
->p2
.p2_slow
;
633 clock
.p2
= limit
->p2
.p2_fast
;
636 memset(best_clock
, 0, sizeof(*best_clock
));
637 max_n
= limit
->n
.max
;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock
.m1
= limit
->m1
.max
;
642 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
643 for (clock
.m2
= limit
->m2
.max
;
644 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
645 for (clock
.p1
= limit
->p1
.max
;
646 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
649 i9xx_clock(refclk
, &clock
);
650 if (!intel_PLL_is_valid(dev
, limit
,
654 this_err
= abs(clock
.dot
- target
);
655 if (this_err
< err_most
) {
669 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
670 int target
, int refclk
, intel_clock_t
*match_clock
,
671 intel_clock_t
*best_clock
)
673 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
675 u32 updrate
, minupdate
, p
;
676 unsigned long bestppm
, ppm
, absppm
;
680 dotclk
= target
* 1000;
683 fastclk
= dotclk
/ (2*100);
686 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
687 bestm1
= bestm2
= bestp1
= bestp2
= 0;
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
691 updrate
= refclk
/ n
;
692 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
693 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
699 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
700 refclk
) / (2*refclk
));
703 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
704 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
705 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
706 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
710 if (absppm
< bestppm
- 10) {
727 best_clock
->n
= bestn
;
728 best_clock
->m1
= bestm1
;
729 best_clock
->m2
= bestm2
;
730 best_clock
->p1
= bestp1
;
731 best_clock
->p2
= bestp2
;
736 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
739 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
740 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
742 return intel_crtc
->config
.cpu_transcoder
;
745 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
748 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
750 frame
= I915_READ(frame_reg
);
752 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
753 DRM_DEBUG_KMS("vblank wait timed out\n");
757 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @pipe: pipe to wait for
761 * Wait for vblank to occur on a given pipe. Needed for various bits of
764 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
767 int pipestat_reg
= PIPESTAT(pipe
);
769 if (INTEL_INFO(dev
)->gen
>= 5) {
770 ironlake_wait_for_vblank(dev
, pipe
);
774 /* Clear existing vblank status. Note this will clear any other
775 * sticky status fields as well.
777 * This races with i915_driver_irq_handler() with the result
778 * that either function could miss a vblank event. Here it is not
779 * fatal, as we will either wait upon the next vblank interrupt or
780 * timeout. Generally speaking intel_wait_for_vblank() is only
781 * called during modeset at which time the GPU should be idle and
782 * should *not* be performing page flips and thus not waiting on
784 * Currently, the result of us stealing a vblank from the irq
785 * handler is that a single frame will be skipped during swapbuffers.
787 I915_WRITE(pipestat_reg
,
788 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
790 /* Wait for vblank interrupt bit to set */
791 if (wait_for(I915_READ(pipestat_reg
) &
792 PIPE_VBLANK_INTERRUPT_STATUS
,
794 DRM_DEBUG_KMS("vblank wait timed out\n");
798 * intel_wait_for_pipe_off - wait for pipe to turn off
800 * @pipe: pipe to wait for
802 * After disabling a pipe, we can't wait for vblank in the usual way,
803 * spinning on the vblank interrupt status bit, since we won't actually
804 * see an interrupt when the pipe is disabled.
807 * wait for the pipe register state bit to turn off
810 * wait for the display line value to settle (it usually
811 * ends up stopping at the start of the next frame).
814 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
817 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
820 if (INTEL_INFO(dev
)->gen
>= 4) {
821 int reg
= PIPECONF(cpu_transcoder
);
823 /* Wait for the Pipe State to go off */
824 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
826 WARN(1, "pipe_off wait timed out\n");
828 u32 last_line
, line_mask
;
829 int reg
= PIPEDSL(pipe
);
830 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
833 line_mask
= DSL_LINEMASK_GEN2
;
835 line_mask
= DSL_LINEMASK_GEN3
;
837 /* Wait for the display line to settle */
839 last_line
= I915_READ(reg
) & line_mask
;
841 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
842 time_after(timeout
, jiffies
));
843 if (time_after(jiffies
, timeout
))
844 WARN(1, "pipe_off wait timed out\n");
849 * ibx_digital_port_connected - is the specified port connected?
850 * @dev_priv: i915 private structure
851 * @port: the port to test
853 * Returns true if @port is connected, false otherwise.
855 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
856 struct intel_digital_port
*port
)
860 if (HAS_PCH_IBX(dev_priv
->dev
)) {
863 bit
= SDE_PORTB_HOTPLUG
;
866 bit
= SDE_PORTC_HOTPLUG
;
869 bit
= SDE_PORTD_HOTPLUG
;
877 bit
= SDE_PORTB_HOTPLUG_CPT
;
880 bit
= SDE_PORTC_HOTPLUG_CPT
;
883 bit
= SDE_PORTD_HOTPLUG_CPT
;
890 return I915_READ(SDEISR
) & bit
;
893 static const char *state_string(bool enabled
)
895 return enabled
? "on" : "off";
898 /* Only for pre-ILK configs */
899 void assert_pll(struct drm_i915_private
*dev_priv
,
900 enum pipe pipe
, bool state
)
907 val
= I915_READ(reg
);
908 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
909 WARN(cur_state
!= state
,
910 "PLL state assertion failure (expected %s, current %s)\n",
911 state_string(state
), state_string(cur_state
));
914 /* XXX: the dsi pll is shared between MIPI DSI ports */
915 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
920 mutex_lock(&dev_priv
->dpio_lock
);
921 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
922 mutex_unlock(&dev_priv
->dpio_lock
);
924 cur_state
= val
& DSI_PLL_VCO_EN
;
925 WARN(cur_state
!= state
,
926 "DSI PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state
), state_string(cur_state
));
929 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
930 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
932 struct intel_shared_dpll
*
933 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
935 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
937 if (crtc
->config
.shared_dpll
< 0)
940 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
944 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
945 struct intel_shared_dpll
*pll
,
949 struct intel_dpll_hw_state hw_state
;
951 if (HAS_PCH_LPT(dev_priv
->dev
)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 "asserting DPLL %s with no DPLL\n", state_string(state
)))
960 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
961 WARN(cur_state
!= state
,
962 "%s assertion failure (expected %s, current %s)\n",
963 pll
->name
, state_string(state
), state_string(cur_state
));
966 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
967 enum pipe pipe
, bool state
)
972 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
975 if (HAS_DDI(dev_priv
->dev
)) {
976 /* DDI does not have a specific FDI_TX register */
977 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
978 val
= I915_READ(reg
);
979 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
981 reg
= FDI_TX_CTL(pipe
);
982 val
= I915_READ(reg
);
983 cur_state
= !!(val
& FDI_TX_ENABLE
);
985 WARN(cur_state
!= state
,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state
), state_string(cur_state
));
989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
992 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
993 enum pipe pipe
, bool state
)
999 reg
= FDI_RX_CTL(pipe
);
1000 val
= I915_READ(reg
);
1001 cur_state
= !!(val
& FDI_RX_ENABLE
);
1002 WARN(cur_state
!= state
,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state
), state_string(cur_state
));
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv
->info
->gen
== 5)
1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020 if (HAS_DDI(dev_priv
->dev
))
1023 reg
= FDI_TX_CTL(pipe
);
1024 val
= I915_READ(reg
);
1025 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1028 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1029 enum pipe pipe
, bool state
)
1035 reg
= FDI_RX_CTL(pipe
);
1036 val
= I915_READ(reg
);
1037 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1038 WARN(cur_state
!= state
,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state
), state_string(cur_state
));
1043 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1046 int pp_reg
, lvds_reg
;
1048 enum pipe panel_pipe
= PIPE_A
;
1051 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1052 pp_reg
= PCH_PP_CONTROL
;
1053 lvds_reg
= PCH_LVDS
;
1055 pp_reg
= PP_CONTROL
;
1059 val
= I915_READ(pp_reg
);
1060 if (!(val
& PANEL_POWER_ON
) ||
1061 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1064 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1065 panel_pipe
= PIPE_B
;
1067 WARN(panel_pipe
== pipe
&& locked
,
1068 "panel assertion failure, pipe %c regs locked\n",
1072 void assert_pipe(struct drm_i915_private
*dev_priv
,
1073 enum pipe pipe
, bool state
)
1078 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1085 if (!intel_display_power_enabled(dev_priv
->dev
,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1089 reg
= PIPECONF(cpu_transcoder
);
1090 val
= I915_READ(reg
);
1091 cur_state
= !!(val
& PIPECONF_ENABLE
);
1094 WARN(cur_state
!= state
,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
1096 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1099 static void assert_plane(struct drm_i915_private
*dev_priv
,
1100 enum plane plane
, bool state
)
1106 reg
= DSPCNTR(plane
);
1107 val
= I915_READ(reg
);
1108 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1109 WARN(cur_state
!= state
,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane
), state_string(state
), state_string(cur_state
));
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1117 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1120 struct drm_device
*dev
= dev_priv
->dev
;
1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev
)->gen
>= 4) {
1127 reg
= DSPCNTR(pipe
);
1128 val
= I915_READ(reg
);
1129 WARN((val
& DISPLAY_PLANE_ENABLE
),
1130 "plane %c assertion failure, should be disabled but not\n",
1135 /* Need to check both planes against the pipe */
1138 val
= I915_READ(reg
);
1139 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1140 DISPPLANE_SEL_PIPE_SHIFT
;
1141 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i
), pipe_name(pipe
));
1147 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1150 struct drm_device
*dev
= dev_priv
->dev
;
1154 if (IS_VALLEYVIEW(dev
)) {
1155 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1156 reg
= SPCNTR(pipe
, i
);
1157 val
= I915_READ(reg
);
1158 WARN((val
& SP_ENABLE
),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe
, i
), pipe_name(pipe
));
1162 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1164 val
= I915_READ(reg
);
1165 WARN((val
& SPRITE_ENABLE
),
1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167 plane_name(pipe
), pipe_name(pipe
));
1168 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1169 reg
= DVSCNTR(pipe
);
1170 val
= I915_READ(reg
);
1171 WARN((val
& DVS_ENABLE
),
1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173 plane_name(pipe
), pipe_name(pipe
));
1177 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1182 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1187 val
= I915_READ(PCH_DREF_CONTROL
);
1188 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1189 DREF_SUPERSPREAD_SOURCE_MASK
));
1190 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1193 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1200 reg
= PCH_TRANSCONF(pipe
);
1201 val
= I915_READ(reg
);
1202 enabled
= !!(val
& TRANS_ENABLE
);
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1208 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1209 enum pipe pipe
, u32 port_sel
, u32 val
)
1211 if ((val
& DP_PORT_EN
) == 0)
1214 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1215 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1216 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1217 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1220 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1226 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1227 enum pipe pipe
, u32 val
)
1229 if ((val
& SDVO_ENABLE
) == 0)
1232 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1233 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1236 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1242 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1243 enum pipe pipe
, u32 val
)
1245 if ((val
& LVDS_PORT_EN
) == 0)
1248 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1249 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1252 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1258 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1259 enum pipe pipe
, u32 val
)
1261 if ((val
& ADPA_DAC_ENABLE
) == 0)
1263 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1264 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1267 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1273 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1274 enum pipe pipe
, int reg
, u32 port_sel
)
1276 u32 val
= I915_READ(reg
);
1277 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279 reg
, pipe_name(pipe
));
1281 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1282 && (val
& DP_PIPEB_SELECT
),
1283 "IBX PCH dp port still using transcoder B\n");
1286 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1287 enum pipe pipe
, int reg
)
1289 u32 val
= I915_READ(reg
);
1290 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292 reg
, pipe_name(pipe
));
1294 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1295 && (val
& SDVO_PIPE_B_SELECT
),
1296 "IBX PCH hdmi port still using transcoder B\n");
1299 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1305 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1306 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1307 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1310 val
= I915_READ(reg
);
1311 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
1316 val
= I915_READ(reg
);
1317 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1321 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1322 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1323 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1326 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1328 struct drm_device
*dev
= crtc
->base
.dev
;
1329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1330 int reg
= DPLL(crtc
->pipe
);
1331 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1333 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1340 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1342 I915_WRITE(reg
, dpll
);
1346 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1349 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1350 POSTING_READ(DPLL_MD(crtc
->pipe
));
1352 /* We do this three times for luck */
1353 I915_WRITE(reg
, dpll
);
1355 udelay(150); /* wait for warmup */
1356 I915_WRITE(reg
, dpll
);
1358 udelay(150); /* wait for warmup */
1359 I915_WRITE(reg
, dpll
);
1361 udelay(150); /* wait for warmup */
1364 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1366 struct drm_device
*dev
= crtc
->base
.dev
;
1367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1368 int reg
= DPLL(crtc
->pipe
);
1369 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1371 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1373 /* No really, not for ILK+ */
1374 BUG_ON(dev_priv
->info
->gen
>= 5);
1376 /* PLL is protected by panel, make sure we can write it */
1377 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1378 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1380 I915_WRITE(reg
, dpll
);
1382 /* Wait for the clocks to stabilize. */
1386 if (INTEL_INFO(dev
)->gen
>= 4) {
1387 I915_WRITE(DPLL_MD(crtc
->pipe
),
1388 crtc
->config
.dpll_hw_state
.dpll_md
);
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1393 * So write it again.
1395 I915_WRITE(reg
, dpll
);
1398 /* We do this three times for luck */
1399 I915_WRITE(reg
, dpll
);
1401 udelay(150); /* wait for warmup */
1402 I915_WRITE(reg
, dpll
);
1404 udelay(150); /* wait for warmup */
1405 I915_WRITE(reg
, dpll
);
1407 udelay(150); /* wait for warmup */
1411 * i9xx_disable_pll - disable a PLL
1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1417 * Note! This is for pre-ILK only.
1419 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv
, pipe
);
1428 I915_WRITE(DPLL(pipe
), 0);
1429 POSTING_READ(DPLL(pipe
));
1432 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1437 port_mask
= DPLL_PORTB_READY_MASK
;
1439 port_mask
= DPLL_PORTC_READY_MASK
;
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port
, I915_READ(DPLL(0)));
1447 * ironlake_enable_shared_dpll - enable PCH PLL
1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1454 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1456 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1457 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1459 /* PCH PLLs only available on ILK, SNB and IVB */
1460 BUG_ON(dev_priv
->info
->gen
< 5);
1461 if (WARN_ON(pll
== NULL
))
1464 if (WARN_ON(pll
->refcount
== 0))
1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll
->name
, pll
->active
, pll
->on
,
1469 crtc
->base
.base
.id
);
1471 if (pll
->active
++) {
1473 assert_shared_dpll_enabled(dev_priv
, pll
);
1478 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1479 pll
->enable(dev_priv
, pll
);
1483 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1485 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1486 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv
->info
->gen
< 5);
1490 if (WARN_ON(pll
== NULL
))
1493 if (WARN_ON(pll
->refcount
== 0))
1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll
->name
, pll
->active
, pll
->on
,
1498 crtc
->base
.base
.id
);
1500 if (WARN_ON(pll
->active
== 0)) {
1501 assert_shared_dpll_disabled(dev_priv
, pll
);
1505 assert_shared_dpll_enabled(dev_priv
, pll
);
1510 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1511 pll
->disable(dev_priv
, pll
);
1515 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1518 struct drm_device
*dev
= dev_priv
->dev
;
1519 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1520 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1521 uint32_t reg
, val
, pipeconf_val
;
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv
->info
->gen
< 5);
1526 /* Make sure PCH DPLL is enabled */
1527 assert_shared_dpll_enabled(dev_priv
,
1528 intel_crtc_to_shared_dpll(intel_crtc
));
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv
, pipe
);
1532 assert_fdi_rx_enabled(dev_priv
, pipe
);
1534 if (HAS_PCH_CPT(dev
)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg
= TRANS_CHICKEN2(pipe
);
1538 val
= I915_READ(reg
);
1539 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1540 I915_WRITE(reg
, val
);
1543 reg
= PCH_TRANSCONF(pipe
);
1544 val
= I915_READ(reg
);
1545 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1547 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1552 val
&= ~PIPECONF_BPC_MASK
;
1553 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1556 val
&= ~TRANS_INTERLACE_MASK
;
1557 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1558 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1559 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1560 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1562 val
|= TRANS_INTERLACED
;
1564 val
|= TRANS_PROGRESSIVE
;
1566 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1567 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1571 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1572 enum transcoder cpu_transcoder
)
1574 u32 val
, pipeconf_val
;
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv
->info
->gen
< 5);
1579 /* FDI must be feeding us bits for PCH ports */
1580 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1581 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1583 /* Workaround: set timing override bit. */
1584 val
= I915_READ(_TRANSA_CHICKEN2
);
1585 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1586 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1589 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1591 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1592 PIPECONF_INTERLACED_ILK
)
1593 val
|= TRANS_INTERLACED
;
1595 val
|= TRANS_PROGRESSIVE
;
1597 I915_WRITE(LPT_TRANSCONF
, val
);
1598 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1599 DRM_ERROR("Failed to enable PCH transcoder\n");
1602 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1605 struct drm_device
*dev
= dev_priv
->dev
;
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv
, pipe
);
1610 assert_fdi_rx_disabled(dev_priv
, pipe
);
1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv
, pipe
);
1615 reg
= PCH_TRANSCONF(pipe
);
1616 val
= I915_READ(reg
);
1617 val
&= ~TRANS_ENABLE
;
1618 I915_WRITE(reg
, val
);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1623 if (!HAS_PCH_IBX(dev
)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg
= TRANS_CHICKEN2(pipe
);
1626 val
= I915_READ(reg
);
1627 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1628 I915_WRITE(reg
, val
);
1632 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1636 val
= I915_READ(LPT_TRANSCONF
);
1637 val
&= ~TRANS_ENABLE
;
1638 I915_WRITE(LPT_TRANSCONF
, val
);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1641 DRM_ERROR("Failed to disable PCH transcoder\n");
1643 /* Workaround: clear timing override bit. */
1644 val
= I915_READ(_TRANSA_CHICKEN2
);
1645 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1646 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1650 * intel_enable_pipe - enable a pipe, asserting requirements
1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1658 * @pipe should be %PIPE_A or %PIPE_B.
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1663 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1664 bool pch_port
, bool dsi
)
1666 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1668 enum pipe pch_transcoder
;
1672 assert_planes_disabled(dev_priv
, pipe
);
1673 assert_sprites_disabled(dev_priv
, pipe
);
1675 if (HAS_PCH_LPT(dev_priv
->dev
))
1676 pch_transcoder
= TRANSCODER_A
;
1678 pch_transcoder
= pipe
;
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1685 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1687 assert_dsi_pll_enabled(dev_priv
);
1689 assert_pll_enabled(dev_priv
, pipe
);
1692 /* if driving the PCH, we need FDI enabled */
1693 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1694 assert_fdi_tx_pll_enabled(dev_priv
,
1695 (enum pipe
) cpu_transcoder
);
1697 /* FIXME: assert CPU port conditions for SNB+ */
1700 reg
= PIPECONF(cpu_transcoder
);
1701 val
= I915_READ(reg
);
1702 if (val
& PIPECONF_ENABLE
)
1705 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1706 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1710 * intel_disable_pipe - disable a pipe, asserting requirements
1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe to disable
1714 * Disable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1717 * @pipe should be %PIPE_A or %PIPE_B.
1719 * Will wait until the pipe has shut down before returning.
1721 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1724 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1730 * Make sure planes won't keep trying to pump pixels to us,
1731 * or we might hang the display.
1733 assert_planes_disabled(dev_priv
, pipe
);
1734 assert_sprites_disabled(dev_priv
, pipe
);
1736 /* Don't disable pipe A or pipe A PLLs if needed */
1737 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1740 reg
= PIPECONF(cpu_transcoder
);
1741 val
= I915_READ(reg
);
1742 if ((val
& PIPECONF_ENABLE
) == 0)
1745 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1746 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1750 * Plane regs are double buffered, going from enabled->disabled needs a
1751 * trigger in order to latch. The display address reg provides this.
1753 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1756 if (dev_priv
->info
->gen
>= 4)
1757 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1759 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1763 * intel_enable_plane - enable a display plane on a given pipe
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to enable
1766 * @pipe: pipe being fed
1768 * Enable @plane on @pipe, making sure that @pipe is running first.
1770 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1771 enum plane plane
, enum pipe pipe
)
1776 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1777 assert_pipe_enabled(dev_priv
, pipe
);
1779 reg
= DSPCNTR(plane
);
1780 val
= I915_READ(reg
);
1781 if (val
& DISPLAY_PLANE_ENABLE
)
1784 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1785 intel_flush_display_plane(dev_priv
, plane
);
1786 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1790 * intel_disable_plane - disable a display plane
1791 * @dev_priv: i915 private structure
1792 * @plane: plane to disable
1793 * @pipe: pipe consuming the data
1795 * Disable @plane; should be an independent operation.
1797 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1798 enum plane plane
, enum pipe pipe
)
1803 reg
= DSPCNTR(plane
);
1804 val
= I915_READ(reg
);
1805 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1808 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1809 intel_flush_display_plane(dev_priv
, plane
);
1810 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1813 static bool need_vtd_wa(struct drm_device
*dev
)
1815 #ifdef CONFIG_INTEL_IOMMU
1816 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1823 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1824 struct drm_i915_gem_object
*obj
,
1825 struct intel_ring_buffer
*pipelined
)
1827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1831 switch (obj
->tiling_mode
) {
1832 case I915_TILING_NONE
:
1833 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1834 alignment
= 128 * 1024;
1835 else if (INTEL_INFO(dev
)->gen
>= 4)
1836 alignment
= 4 * 1024;
1838 alignment
= 64 * 1024;
1841 /* pin() will align the object as required by fence */
1845 /* Despite that we check this in framebuffer_init userspace can
1846 * screw us over and change the tiling after the fact. Only
1847 * pinned buffers can't change their tiling. */
1848 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1854 /* Note that the w/a also requires 64 PTE of padding following the
1855 * bo. We currently fill all unused PTE with the shadow page and so
1856 * we should always have valid PTE following the scanout preventing
1859 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1860 alignment
= 256 * 1024;
1862 dev_priv
->mm
.interruptible
= false;
1863 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1865 goto err_interruptible
;
1867 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1868 * fence, whereas 965+ only requires a fence if using
1869 * framebuffer compression. For simplicity, we always install
1870 * a fence as the cost is not that onerous.
1872 ret
= i915_gem_object_get_fence(obj
);
1876 i915_gem_object_pin_fence(obj
);
1878 dev_priv
->mm
.interruptible
= true;
1882 i915_gem_object_unpin_from_display_plane(obj
);
1884 dev_priv
->mm
.interruptible
= true;
1888 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1890 i915_gem_object_unpin_fence(obj
);
1891 i915_gem_object_unpin_from_display_plane(obj
);
1894 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1895 * is assumed to be a power-of-two. */
1896 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1897 unsigned int tiling_mode
,
1901 if (tiling_mode
!= I915_TILING_NONE
) {
1902 unsigned int tile_rows
, tiles
;
1907 tiles
= *x
/ (512/cpp
);
1910 return tile_rows
* pitch
* 8 + tiles
* 4096;
1912 unsigned int offset
;
1914 offset
= *y
* pitch
+ *x
* cpp
;
1916 *x
= (offset
& 4095) / cpp
;
1917 return offset
& -4096;
1921 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1924 struct drm_device
*dev
= crtc
->dev
;
1925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1927 struct intel_framebuffer
*intel_fb
;
1928 struct drm_i915_gem_object
*obj
;
1929 int plane
= intel_crtc
->plane
;
1930 unsigned long linear_offset
;
1939 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1943 intel_fb
= to_intel_framebuffer(fb
);
1944 obj
= intel_fb
->obj
;
1946 reg
= DSPCNTR(plane
);
1947 dspcntr
= I915_READ(reg
);
1948 /* Mask out pixel format bits in case we change it */
1949 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1950 switch (fb
->pixel_format
) {
1952 dspcntr
|= DISPPLANE_8BPP
;
1954 case DRM_FORMAT_XRGB1555
:
1955 case DRM_FORMAT_ARGB1555
:
1956 dspcntr
|= DISPPLANE_BGRX555
;
1958 case DRM_FORMAT_RGB565
:
1959 dspcntr
|= DISPPLANE_BGRX565
;
1961 case DRM_FORMAT_XRGB8888
:
1962 case DRM_FORMAT_ARGB8888
:
1963 dspcntr
|= DISPPLANE_BGRX888
;
1965 case DRM_FORMAT_XBGR8888
:
1966 case DRM_FORMAT_ABGR8888
:
1967 dspcntr
|= DISPPLANE_RGBX888
;
1969 case DRM_FORMAT_XRGB2101010
:
1970 case DRM_FORMAT_ARGB2101010
:
1971 dspcntr
|= DISPPLANE_BGRX101010
;
1973 case DRM_FORMAT_XBGR2101010
:
1974 case DRM_FORMAT_ABGR2101010
:
1975 dspcntr
|= DISPPLANE_RGBX101010
;
1981 if (INTEL_INFO(dev
)->gen
>= 4) {
1982 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1983 dspcntr
|= DISPPLANE_TILED
;
1985 dspcntr
&= ~DISPPLANE_TILED
;
1989 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1991 I915_WRITE(reg
, dspcntr
);
1993 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1995 if (INTEL_INFO(dev
)->gen
>= 4) {
1996 intel_crtc
->dspaddr_offset
=
1997 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
1998 fb
->bits_per_pixel
/ 8,
2000 linear_offset
-= intel_crtc
->dspaddr_offset
;
2002 intel_crtc
->dspaddr_offset
= linear_offset
;
2005 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2006 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2008 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2009 if (INTEL_INFO(dev
)->gen
>= 4) {
2010 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2011 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2012 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2013 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2015 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2021 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2022 struct drm_framebuffer
*fb
, int x
, int y
)
2024 struct drm_device
*dev
= crtc
->dev
;
2025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2026 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2027 struct intel_framebuffer
*intel_fb
;
2028 struct drm_i915_gem_object
*obj
;
2029 int plane
= intel_crtc
->plane
;
2030 unsigned long linear_offset
;
2040 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2044 intel_fb
= to_intel_framebuffer(fb
);
2045 obj
= intel_fb
->obj
;
2047 reg
= DSPCNTR(plane
);
2048 dspcntr
= I915_READ(reg
);
2049 /* Mask out pixel format bits in case we change it */
2050 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2051 switch (fb
->pixel_format
) {
2053 dspcntr
|= DISPPLANE_8BPP
;
2055 case DRM_FORMAT_RGB565
:
2056 dspcntr
|= DISPPLANE_BGRX565
;
2058 case DRM_FORMAT_XRGB8888
:
2059 case DRM_FORMAT_ARGB8888
:
2060 dspcntr
|= DISPPLANE_BGRX888
;
2062 case DRM_FORMAT_XBGR8888
:
2063 case DRM_FORMAT_ABGR8888
:
2064 dspcntr
|= DISPPLANE_RGBX888
;
2066 case DRM_FORMAT_XRGB2101010
:
2067 case DRM_FORMAT_ARGB2101010
:
2068 dspcntr
|= DISPPLANE_BGRX101010
;
2070 case DRM_FORMAT_XBGR2101010
:
2071 case DRM_FORMAT_ABGR2101010
:
2072 dspcntr
|= DISPPLANE_RGBX101010
;
2078 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2079 dspcntr
|= DISPPLANE_TILED
;
2081 dspcntr
&= ~DISPPLANE_TILED
;
2083 if (IS_HASWELL(dev
))
2084 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2086 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2088 I915_WRITE(reg
, dspcntr
);
2090 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2091 intel_crtc
->dspaddr_offset
=
2092 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2093 fb
->bits_per_pixel
/ 8,
2095 linear_offset
-= intel_crtc
->dspaddr_offset
;
2097 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2098 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2100 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2101 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2102 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2103 if (IS_HASWELL(dev
)) {
2104 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2106 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2107 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2114 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2116 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2117 int x
, int y
, enum mode_set_atomic state
)
2119 struct drm_device
*dev
= crtc
->dev
;
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2122 if (dev_priv
->display
.disable_fbc
)
2123 dev_priv
->display
.disable_fbc(dev
);
2124 intel_increase_pllclock(crtc
);
2126 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2129 void intel_display_handle_reset(struct drm_device
*dev
)
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2132 struct drm_crtc
*crtc
;
2135 * Flips in the rings have been nuked by the reset,
2136 * so complete all pending flips so that user space
2137 * will get its events and not get stuck.
2139 * Also update the base address of all primary
2140 * planes to the the last fb to make sure we're
2141 * showing the correct fb after a reset.
2143 * Need to make two loops over the crtcs so that we
2144 * don't try to grab a crtc mutex before the
2145 * pending_flip_queue really got woken up.
2148 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2149 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2150 enum plane plane
= intel_crtc
->plane
;
2152 intel_prepare_page_flip(dev
, plane
);
2153 intel_finish_page_flip_plane(dev
, plane
);
2156 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2157 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2159 mutex_lock(&crtc
->mutex
);
2160 if (intel_crtc
->active
)
2161 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2163 mutex_unlock(&crtc
->mutex
);
2168 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2170 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2171 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2172 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2175 /* Big Hammer, we also need to ensure that any pending
2176 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2177 * current scanout is retired before unpinning the old
2180 * This should only fail upon a hung GPU, in which case we
2181 * can safely continue.
2183 dev_priv
->mm
.interruptible
= false;
2184 ret
= i915_gem_object_finish_gpu(obj
);
2185 dev_priv
->mm
.interruptible
= was_interruptible
;
2190 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2192 struct drm_device
*dev
= crtc
->dev
;
2193 struct drm_i915_master_private
*master_priv
;
2194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2196 if (!dev
->primary
->master
)
2199 master_priv
= dev
->primary
->master
->driver_priv
;
2200 if (!master_priv
->sarea_priv
)
2203 switch (intel_crtc
->pipe
) {
2205 master_priv
->sarea_priv
->pipeA_x
= x
;
2206 master_priv
->sarea_priv
->pipeA_y
= y
;
2209 master_priv
->sarea_priv
->pipeB_x
= x
;
2210 master_priv
->sarea_priv
->pipeB_y
= y
;
2218 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2219 struct drm_framebuffer
*fb
)
2221 struct drm_device
*dev
= crtc
->dev
;
2222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2223 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2224 struct drm_framebuffer
*old_fb
;
2229 DRM_ERROR("No FB bound\n");
2233 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2234 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2235 plane_name(intel_crtc
->plane
),
2236 INTEL_INFO(dev
)->num_pipes
);
2240 mutex_lock(&dev
->struct_mutex
);
2241 ret
= intel_pin_and_fence_fb_obj(dev
,
2242 to_intel_framebuffer(fb
)->obj
,
2245 mutex_unlock(&dev
->struct_mutex
);
2246 DRM_ERROR("pin & fence failed\n");
2250 /* Update pipe size and adjust fitter if needed */
2251 if (i915_fastboot
) {
2252 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2253 ((crtc
->mode
.hdisplay
- 1) << 16) |
2254 (crtc
->mode
.vdisplay
- 1));
2255 if (!intel_crtc
->config
.pch_pfit
.size
&&
2256 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2257 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2258 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2259 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2260 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2264 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2266 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2267 mutex_unlock(&dev
->struct_mutex
);
2268 DRM_ERROR("failed to update base address\n");
2278 if (intel_crtc
->active
&& old_fb
!= fb
)
2279 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2280 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2283 intel_update_fbc(dev
);
2284 intel_edp_psr_update(dev
);
2285 mutex_unlock(&dev
->struct_mutex
);
2287 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2292 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2294 struct drm_device
*dev
= crtc
->dev
;
2295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2296 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2297 int pipe
= intel_crtc
->pipe
;
2300 /* enable normal train */
2301 reg
= FDI_TX_CTL(pipe
);
2302 temp
= I915_READ(reg
);
2303 if (IS_IVYBRIDGE(dev
)) {
2304 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2305 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2307 temp
&= ~FDI_LINK_TRAIN_NONE
;
2308 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2310 I915_WRITE(reg
, temp
);
2312 reg
= FDI_RX_CTL(pipe
);
2313 temp
= I915_READ(reg
);
2314 if (HAS_PCH_CPT(dev
)) {
2315 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2316 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2318 temp
&= ~FDI_LINK_TRAIN_NONE
;
2319 temp
|= FDI_LINK_TRAIN_NONE
;
2321 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2323 /* wait one idle pattern time */
2327 /* IVB wants error correction enabled */
2328 if (IS_IVYBRIDGE(dev
))
2329 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2330 FDI_FE_ERRC_ENABLE
);
2333 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2335 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2338 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2341 struct intel_crtc
*pipe_B_crtc
=
2342 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2343 struct intel_crtc
*pipe_C_crtc
=
2344 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2348 * When everything is off disable fdi C so that we could enable fdi B
2349 * with all lanes. Note that we don't care about enabled pipes without
2350 * an enabled pch encoder.
2352 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2353 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2354 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2355 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2357 temp
= I915_READ(SOUTH_CHICKEN1
);
2358 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2359 DRM_DEBUG_KMS("disabling fdi C rx\n");
2360 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2364 /* The FDI link training functions for ILK/Ibexpeak. */
2365 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2367 struct drm_device
*dev
= crtc
->dev
;
2368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2370 int pipe
= intel_crtc
->pipe
;
2371 int plane
= intel_crtc
->plane
;
2372 u32 reg
, temp
, tries
;
2374 /* FDI needs bits from pipe & plane first */
2375 assert_pipe_enabled(dev_priv
, pipe
);
2376 assert_plane_enabled(dev_priv
, plane
);
2378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2380 reg
= FDI_RX_IMR(pipe
);
2381 temp
= I915_READ(reg
);
2382 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2383 temp
&= ~FDI_RX_BIT_LOCK
;
2384 I915_WRITE(reg
, temp
);
2388 /* enable CPU FDI TX and PCH FDI RX */
2389 reg
= FDI_TX_CTL(pipe
);
2390 temp
= I915_READ(reg
);
2391 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2392 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2393 temp
&= ~FDI_LINK_TRAIN_NONE
;
2394 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2395 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2397 reg
= FDI_RX_CTL(pipe
);
2398 temp
= I915_READ(reg
);
2399 temp
&= ~FDI_LINK_TRAIN_NONE
;
2400 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2401 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2406 /* Ironlake workaround, enable clock pointer after FDI enable*/
2407 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2408 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2409 FDI_RX_PHASE_SYNC_POINTER_EN
);
2411 reg
= FDI_RX_IIR(pipe
);
2412 for (tries
= 0; tries
< 5; tries
++) {
2413 temp
= I915_READ(reg
);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2416 if ((temp
& FDI_RX_BIT_LOCK
)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2423 DRM_ERROR("FDI train 1 fail!\n");
2426 reg
= FDI_TX_CTL(pipe
);
2427 temp
= I915_READ(reg
);
2428 temp
&= ~FDI_LINK_TRAIN_NONE
;
2429 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2430 I915_WRITE(reg
, temp
);
2432 reg
= FDI_RX_CTL(pipe
);
2433 temp
= I915_READ(reg
);
2434 temp
&= ~FDI_LINK_TRAIN_NONE
;
2435 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2436 I915_WRITE(reg
, temp
);
2441 reg
= FDI_RX_IIR(pipe
);
2442 for (tries
= 0; tries
< 5; tries
++) {
2443 temp
= I915_READ(reg
);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2446 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2447 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2453 DRM_ERROR("FDI train 2 fail!\n");
2455 DRM_DEBUG_KMS("FDI train done\n");
2459 static const int snb_b_fdi_train_param
[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2469 struct drm_device
*dev
= crtc
->dev
;
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2472 int pipe
= intel_crtc
->pipe
;
2473 u32 reg
, temp
, i
, retry
;
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477 reg
= FDI_RX_IMR(pipe
);
2478 temp
= I915_READ(reg
);
2479 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2480 temp
&= ~FDI_RX_BIT_LOCK
;
2481 I915_WRITE(reg
, temp
);
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg
= FDI_TX_CTL(pipe
);
2488 temp
= I915_READ(reg
);
2489 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2490 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2491 temp
&= ~FDI_LINK_TRAIN_NONE
;
2492 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2493 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2495 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2496 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2498 I915_WRITE(FDI_RX_MISC(pipe
),
2499 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2501 reg
= FDI_RX_CTL(pipe
);
2502 temp
= I915_READ(reg
);
2503 if (HAS_PCH_CPT(dev
)) {
2504 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2505 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2507 temp
&= ~FDI_LINK_TRAIN_NONE
;
2508 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2510 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2515 for (i
= 0; i
< 4; i
++) {
2516 reg
= FDI_TX_CTL(pipe
);
2517 temp
= I915_READ(reg
);
2518 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2519 temp
|= snb_b_fdi_train_param
[i
];
2520 I915_WRITE(reg
, temp
);
2525 for (retry
= 0; retry
< 5; retry
++) {
2526 reg
= FDI_RX_IIR(pipe
);
2527 temp
= I915_READ(reg
);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2529 if (temp
& FDI_RX_BIT_LOCK
) {
2530 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2540 DRM_ERROR("FDI train 1 fail!\n");
2543 reg
= FDI_TX_CTL(pipe
);
2544 temp
= I915_READ(reg
);
2545 temp
&= ~FDI_LINK_TRAIN_NONE
;
2546 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2548 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2550 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2552 I915_WRITE(reg
, temp
);
2554 reg
= FDI_RX_CTL(pipe
);
2555 temp
= I915_READ(reg
);
2556 if (HAS_PCH_CPT(dev
)) {
2557 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2558 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2560 temp
&= ~FDI_LINK_TRAIN_NONE
;
2561 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2563 I915_WRITE(reg
, temp
);
2568 for (i
= 0; i
< 4; i
++) {
2569 reg
= FDI_TX_CTL(pipe
);
2570 temp
= I915_READ(reg
);
2571 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2572 temp
|= snb_b_fdi_train_param
[i
];
2573 I915_WRITE(reg
, temp
);
2578 for (retry
= 0; retry
< 5; retry
++) {
2579 reg
= FDI_RX_IIR(pipe
);
2580 temp
= I915_READ(reg
);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2582 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2583 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2593 DRM_ERROR("FDI train 2 fail!\n");
2595 DRM_DEBUG_KMS("FDI train done.\n");
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2601 struct drm_device
*dev
= crtc
->dev
;
2602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2603 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2604 int pipe
= intel_crtc
->pipe
;
2605 u32 reg
, temp
, i
, j
;
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 reg
= FDI_RX_IMR(pipe
);
2610 temp
= I915_READ(reg
);
2611 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2612 temp
&= ~FDI_RX_BIT_LOCK
;
2613 I915_WRITE(reg
, temp
);
2618 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2619 I915_READ(FDI_RX_IIR(pipe
)));
2621 /* Try each vswing and preemphasis setting twice before moving on */
2622 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2623 /* disable first in case we need to retry */
2624 reg
= FDI_TX_CTL(pipe
);
2625 temp
= I915_READ(reg
);
2626 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2627 temp
&= ~FDI_TX_ENABLE
;
2628 I915_WRITE(reg
, temp
);
2630 reg
= FDI_RX_CTL(pipe
);
2631 temp
= I915_READ(reg
);
2632 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2633 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2634 temp
&= ~FDI_RX_ENABLE
;
2635 I915_WRITE(reg
, temp
);
2637 /* enable CPU FDI TX and PCH FDI RX */
2638 reg
= FDI_TX_CTL(pipe
);
2639 temp
= I915_READ(reg
);
2640 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2641 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2642 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2643 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2644 temp
|= snb_b_fdi_train_param
[j
/2];
2645 temp
|= FDI_COMPOSITE_SYNC
;
2646 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2648 I915_WRITE(FDI_RX_MISC(pipe
),
2649 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2651 reg
= FDI_RX_CTL(pipe
);
2652 temp
= I915_READ(reg
);
2653 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2654 temp
|= FDI_COMPOSITE_SYNC
;
2655 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2658 udelay(1); /* should be 0.5us */
2660 for (i
= 0; i
< 4; i
++) {
2661 reg
= FDI_RX_IIR(pipe
);
2662 temp
= I915_READ(reg
);
2663 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2665 if (temp
& FDI_RX_BIT_LOCK
||
2666 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2667 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2668 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2672 udelay(1); /* should be 0.5us */
2675 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2680 reg
= FDI_TX_CTL(pipe
);
2681 temp
= I915_READ(reg
);
2682 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2683 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2684 I915_WRITE(reg
, temp
);
2686 reg
= FDI_RX_CTL(pipe
);
2687 temp
= I915_READ(reg
);
2688 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2689 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2690 I915_WRITE(reg
, temp
);
2693 udelay(2); /* should be 1.5us */
2695 for (i
= 0; i
< 4; i
++) {
2696 reg
= FDI_RX_IIR(pipe
);
2697 temp
= I915_READ(reg
);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2700 if (temp
& FDI_RX_SYMBOL_LOCK
||
2701 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2702 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2703 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2707 udelay(2); /* should be 1.5us */
2710 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2714 DRM_DEBUG_KMS("FDI train done.\n");
2717 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2719 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2721 int pipe
= intel_crtc
->pipe
;
2725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2726 reg
= FDI_RX_CTL(pipe
);
2727 temp
= I915_READ(reg
);
2728 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2729 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2730 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2731 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2736 /* Switch from Rawclk to PCDclk */
2737 temp
= I915_READ(reg
);
2738 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
2744 reg
= FDI_TX_CTL(pipe
);
2745 temp
= I915_READ(reg
);
2746 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2747 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2754 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2756 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2758 int pipe
= intel_crtc
->pipe
;
2761 /* Switch from PCDclk to Rawclk */
2762 reg
= FDI_RX_CTL(pipe
);
2763 temp
= I915_READ(reg
);
2764 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2766 /* Disable CPU FDI TX PLL */
2767 reg
= FDI_TX_CTL(pipe
);
2768 temp
= I915_READ(reg
);
2769 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2774 reg
= FDI_RX_CTL(pipe
);
2775 temp
= I915_READ(reg
);
2776 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2778 /* Wait for the clocks to turn off. */
2783 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2785 struct drm_device
*dev
= crtc
->dev
;
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2788 int pipe
= intel_crtc
->pipe
;
2791 /* disable CPU FDI tx and PCH FDI rx */
2792 reg
= FDI_TX_CTL(pipe
);
2793 temp
= I915_READ(reg
);
2794 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2797 reg
= FDI_RX_CTL(pipe
);
2798 temp
= I915_READ(reg
);
2799 temp
&= ~(0x7 << 16);
2800 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2801 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2806 /* Ironlake workaround, disable clock pointer after downing FDI */
2807 if (HAS_PCH_IBX(dev
)) {
2808 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2811 /* still set train pattern 1 */
2812 reg
= FDI_TX_CTL(pipe
);
2813 temp
= I915_READ(reg
);
2814 temp
&= ~FDI_LINK_TRAIN_NONE
;
2815 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2816 I915_WRITE(reg
, temp
);
2818 reg
= FDI_RX_CTL(pipe
);
2819 temp
= I915_READ(reg
);
2820 if (HAS_PCH_CPT(dev
)) {
2821 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2822 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2824 temp
&= ~FDI_LINK_TRAIN_NONE
;
2825 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2827 /* BPC in FDI rx is consistent with that in PIPECONF */
2828 temp
&= ~(0x07 << 16);
2829 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2830 I915_WRITE(reg
, temp
);
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2838 struct drm_device
*dev
= crtc
->dev
;
2839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2840 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2841 unsigned long flags
;
2844 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2845 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2848 spin_lock_irqsave(&dev
->event_lock
, flags
);
2849 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2850 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2855 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2857 struct drm_device
*dev
= crtc
->dev
;
2858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2860 if (crtc
->fb
== NULL
)
2863 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2865 wait_event(dev_priv
->pending_flip_queue
,
2866 !intel_crtc_has_pending_flip(crtc
));
2868 mutex_lock(&dev
->struct_mutex
);
2869 intel_finish_fb(crtc
->fb
);
2870 mutex_unlock(&dev
->struct_mutex
);
2873 /* Program iCLKIP clock to the desired frequency */
2874 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2876 struct drm_device
*dev
= crtc
->dev
;
2877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2878 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2881 mutex_lock(&dev_priv
->dpio_lock
);
2883 /* It is necessary to ungate the pixclk gate prior to programming
2884 * the divisors, and gate it back when it is done.
2886 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2888 /* Disable SSCCTL */
2889 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2890 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2894 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2895 if (crtc
->mode
.clock
== 20000) {
2900 /* The iCLK virtual clock root frequency is in MHz,
2901 * but the crtc->mode.clock in in KHz. To get the divisors,
2902 * it is necessary to divide one by another, so we
2903 * convert the virtual clock precision to KHz here for higher
2906 u32 iclk_virtual_root_freq
= 172800 * 1000;
2907 u32 iclk_pi_range
= 64;
2908 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2910 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2911 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2912 pi_value
= desired_divisor
% iclk_pi_range
;
2915 divsel
= msb_divisor_value
- 2;
2916 phaseinc
= pi_value
;
2919 /* This should not happen with any sane values */
2920 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2921 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2922 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2923 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2925 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2932 /* Program SSCDIVINTPHASE6 */
2933 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2934 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2935 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2936 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2937 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2938 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2939 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2940 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2942 /* Program SSCAUXDIV */
2943 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2944 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2945 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2946 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2948 /* Enable modulator and associated divider */
2949 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2950 temp
&= ~SBI_SSCCTL_DISABLE
;
2951 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2953 /* Wait for initialization time */
2956 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2958 mutex_unlock(&dev_priv
->dpio_lock
);
2961 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
2962 enum pipe pch_transcoder
)
2964 struct drm_device
*dev
= crtc
->base
.dev
;
2965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2966 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2968 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
2969 I915_READ(HTOTAL(cpu_transcoder
)));
2970 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
2971 I915_READ(HBLANK(cpu_transcoder
)));
2972 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
2973 I915_READ(HSYNC(cpu_transcoder
)));
2975 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
2976 I915_READ(VTOTAL(cpu_transcoder
)));
2977 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
2978 I915_READ(VBLANK(cpu_transcoder
)));
2979 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
2980 I915_READ(VSYNC(cpu_transcoder
)));
2981 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
2982 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
2986 * Enable PCH resources required for PCH ports:
2988 * - FDI training & RX/TX
2989 * - update transcoder timings
2990 * - DP transcoding bits
2993 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2995 struct drm_device
*dev
= crtc
->dev
;
2996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2997 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2998 int pipe
= intel_crtc
->pipe
;
3001 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3003 /* Write the TU size bits before fdi link training, so that error
3004 * detection works. */
3005 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3006 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3008 /* For PCH output, training FDI link */
3009 dev_priv
->display
.fdi_link_train(crtc
);
3011 /* We need to program the right clock selection before writing the pixel
3012 * mutliplier into the DPLL. */
3013 if (HAS_PCH_CPT(dev
)) {
3016 temp
= I915_READ(PCH_DPLL_SEL
);
3017 temp
|= TRANS_DPLL_ENABLE(pipe
);
3018 sel
= TRANS_DPLLB_SEL(pipe
);
3019 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3023 I915_WRITE(PCH_DPLL_SEL
, temp
);
3026 /* XXX: pch pll's can be enabled any time before we enable the PCH
3027 * transcoder, and we actually should do this to not upset any PCH
3028 * transcoder that already use the clock when we share it.
3030 * Note that enable_shared_dpll tries to do the right thing, but
3031 * get_shared_dpll unconditionally resets the pll - we need that to have
3032 * the right LVDS enable sequence. */
3033 ironlake_enable_shared_dpll(intel_crtc
);
3035 /* set transcoder timing, panel must allow it */
3036 assert_panel_unlocked(dev_priv
, pipe
);
3037 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3039 intel_fdi_normal_train(crtc
);
3041 /* For PCH DP, enable TRANS_DP_CTL */
3042 if (HAS_PCH_CPT(dev
) &&
3043 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3044 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3045 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3046 reg
= TRANS_DP_CTL(pipe
);
3047 temp
= I915_READ(reg
);
3048 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3049 TRANS_DP_SYNC_MASK
|
3051 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3052 TRANS_DP_ENH_FRAMING
);
3053 temp
|= bpc
<< 9; /* same format but at 11:9 */
3055 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3056 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3057 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3058 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3060 switch (intel_trans_dp_port_sel(crtc
)) {
3062 temp
|= TRANS_DP_PORT_SEL_B
;
3065 temp
|= TRANS_DP_PORT_SEL_C
;
3068 temp
|= TRANS_DP_PORT_SEL_D
;
3074 I915_WRITE(reg
, temp
);
3077 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3080 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3082 struct drm_device
*dev
= crtc
->dev
;
3083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3084 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3085 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3087 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3089 lpt_program_iclkip(crtc
);
3091 /* Set transcoder timing. */
3092 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3094 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3097 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3099 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3104 if (pll
->refcount
== 0) {
3105 WARN(1, "bad %s refcount\n", pll
->name
);
3109 if (--pll
->refcount
== 0) {
3111 WARN_ON(pll
->active
);
3114 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3117 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3119 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3120 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3121 enum intel_dpll_id i
;
3124 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3125 crtc
->base
.base
.id
, pll
->name
);
3126 intel_put_shared_dpll(crtc
);
3129 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3130 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3131 i
= (enum intel_dpll_id
) crtc
->pipe
;
3132 pll
= &dev_priv
->shared_dplls
[i
];
3134 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3135 crtc
->base
.base
.id
, pll
->name
);
3140 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3141 pll
= &dev_priv
->shared_dplls
[i
];
3143 /* Only want to check enabled timings first */
3144 if (pll
->refcount
== 0)
3147 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3148 sizeof(pll
->hw_state
)) == 0) {
3149 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3151 pll
->name
, pll
->refcount
, pll
->active
);
3157 /* Ok no matching timings, maybe there's a free one? */
3158 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3159 pll
= &dev_priv
->shared_dplls
[i
];
3160 if (pll
->refcount
== 0) {
3161 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3162 crtc
->base
.base
.id
, pll
->name
);
3170 crtc
->config
.shared_dpll
= i
;
3171 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3172 pipe_name(crtc
->pipe
));
3174 if (pll
->active
== 0) {
3175 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3176 sizeof(pll
->hw_state
));
3178 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3180 assert_shared_dpll_disabled(dev_priv
, pll
);
3182 pll
->mode_set(dev_priv
, pll
);
3189 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3192 int dslreg
= PIPEDSL(pipe
);
3195 temp
= I915_READ(dslreg
);
3197 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3198 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3199 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3203 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3205 struct drm_device
*dev
= crtc
->base
.dev
;
3206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3207 int pipe
= crtc
->pipe
;
3209 if (crtc
->config
.pch_pfit
.size
) {
3210 /* Force use of hard-coded filter coefficients
3211 * as some pre-programmed values are broken,
3214 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3215 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3216 PF_PIPE_SEL_IVB(pipe
));
3218 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3219 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3220 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3224 static void intel_enable_planes(struct drm_crtc
*crtc
)
3226 struct drm_device
*dev
= crtc
->dev
;
3227 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3228 struct intel_plane
*intel_plane
;
3230 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3231 if (intel_plane
->pipe
== pipe
)
3232 intel_plane_restore(&intel_plane
->base
);
3235 static void intel_disable_planes(struct drm_crtc
*crtc
)
3237 struct drm_device
*dev
= crtc
->dev
;
3238 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3239 struct intel_plane
*intel_plane
;
3241 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3242 if (intel_plane
->pipe
== pipe
)
3243 intel_plane_disable(&intel_plane
->base
);
3246 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3248 struct drm_device
*dev
= crtc
->dev
;
3249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3250 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3251 struct intel_encoder
*encoder
;
3252 int pipe
= intel_crtc
->pipe
;
3253 int plane
= intel_crtc
->plane
;
3255 WARN_ON(!crtc
->enabled
);
3257 if (intel_crtc
->active
)
3260 intel_crtc
->active
= true;
3262 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3263 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3265 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3266 if (encoder
->pre_enable
)
3267 encoder
->pre_enable(encoder
);
3269 if (intel_crtc
->config
.has_pch_encoder
) {
3270 /* Note: FDI PLL enabling _must_ be done before we enable the
3271 * cpu pipes, hence this is separate from all the other fdi/pch
3273 ironlake_fdi_pll_enable(intel_crtc
);
3275 assert_fdi_tx_disabled(dev_priv
, pipe
);
3276 assert_fdi_rx_disabled(dev_priv
, pipe
);
3279 ironlake_pfit_enable(intel_crtc
);
3282 * On ILK+ LUT must be loaded before the pipe is running but with
3285 intel_crtc_load_lut(crtc
);
3287 intel_update_watermarks(crtc
);
3288 intel_enable_pipe(dev_priv
, pipe
,
3289 intel_crtc
->config
.has_pch_encoder
, false);
3290 intel_enable_plane(dev_priv
, plane
, pipe
);
3291 intel_enable_planes(crtc
);
3292 intel_crtc_update_cursor(crtc
, true);
3294 if (intel_crtc
->config
.has_pch_encoder
)
3295 ironlake_pch_enable(crtc
);
3297 mutex_lock(&dev
->struct_mutex
);
3298 intel_update_fbc(dev
);
3299 mutex_unlock(&dev
->struct_mutex
);
3301 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3302 encoder
->enable(encoder
);
3304 if (HAS_PCH_CPT(dev
))
3305 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3308 * There seems to be a race in PCH platform hw (at least on some
3309 * outputs) where an enabled pipe still completes any pageflip right
3310 * away (as if the pipe is off) instead of waiting for vblank. As soon
3311 * as the first vblank happend, everything works as expected. Hence just
3312 * wait for one vblank before returning to avoid strange things
3315 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3318 /* IPS only exists on ULT machines and is tied to pipe A. */
3319 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3321 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3324 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3326 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3328 if (!crtc
->config
.ips_enabled
)
3331 /* We can only enable IPS after we enable a plane and wait for a vblank.
3332 * We guarantee that the plane is enabled by calling intel_enable_ips
3333 * only after intel_enable_plane. And intel_enable_plane already waits
3334 * for a vblank, so all we need to do here is to enable the IPS bit. */
3335 assert_plane_enabled(dev_priv
, crtc
->plane
);
3336 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3339 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3341 struct drm_device
*dev
= crtc
->base
.dev
;
3342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3344 if (!crtc
->config
.ips_enabled
)
3347 assert_plane_enabled(dev_priv
, crtc
->plane
);
3348 I915_WRITE(IPS_CTL
, 0);
3350 /* We need to wait for a vblank before we can disable the plane. */
3351 intel_wait_for_vblank(dev
, crtc
->pipe
);
3354 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3356 struct drm_device
*dev
= crtc
->dev
;
3357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3358 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3359 struct intel_encoder
*encoder
;
3360 int pipe
= intel_crtc
->pipe
;
3361 int plane
= intel_crtc
->plane
;
3363 WARN_ON(!crtc
->enabled
);
3365 if (intel_crtc
->active
)
3368 intel_crtc
->active
= true;
3370 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3371 if (intel_crtc
->config
.has_pch_encoder
)
3372 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3374 if (intel_crtc
->config
.has_pch_encoder
)
3375 dev_priv
->display
.fdi_link_train(crtc
);
3377 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3378 if (encoder
->pre_enable
)
3379 encoder
->pre_enable(encoder
);
3381 intel_ddi_enable_pipe_clock(intel_crtc
);
3383 ironlake_pfit_enable(intel_crtc
);
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3389 intel_crtc_load_lut(crtc
);
3391 intel_ddi_set_pipe_settings(crtc
);
3392 intel_ddi_enable_transcoder_func(crtc
);
3394 intel_update_watermarks(crtc
);
3395 intel_enable_pipe(dev_priv
, pipe
,
3396 intel_crtc
->config
.has_pch_encoder
, false);
3397 intel_enable_plane(dev_priv
, plane
, pipe
);
3398 intel_enable_planes(crtc
);
3399 intel_crtc_update_cursor(crtc
, true);
3401 hsw_enable_ips(intel_crtc
);
3403 if (intel_crtc
->config
.has_pch_encoder
)
3404 lpt_pch_enable(crtc
);
3406 mutex_lock(&dev
->struct_mutex
);
3407 intel_update_fbc(dev
);
3408 mutex_unlock(&dev
->struct_mutex
);
3410 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3411 encoder
->enable(encoder
);
3412 intel_opregion_notify_encoder(encoder
, true);
3416 * There seems to be a race in PCH platform hw (at least on some
3417 * outputs) where an enabled pipe still completes any pageflip right
3418 * away (as if the pipe is off) instead of waiting for vblank. As soon
3419 * as the first vblank happend, everything works as expected. Hence just
3420 * wait for one vblank before returning to avoid strange things
3423 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3426 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3428 struct drm_device
*dev
= crtc
->base
.dev
;
3429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3430 int pipe
= crtc
->pipe
;
3432 /* To avoid upsetting the power well on haswell only disable the pfit if
3433 * it's in use. The hw state code will make sure we get this right. */
3434 if (crtc
->config
.pch_pfit
.size
) {
3435 I915_WRITE(PF_CTL(pipe
), 0);
3436 I915_WRITE(PF_WIN_POS(pipe
), 0);
3437 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3441 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3443 struct drm_device
*dev
= crtc
->dev
;
3444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3446 struct intel_encoder
*encoder
;
3447 int pipe
= intel_crtc
->pipe
;
3448 int plane
= intel_crtc
->plane
;
3452 if (!intel_crtc
->active
)
3455 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3456 encoder
->disable(encoder
);
3458 intel_crtc_wait_for_pending_flips(crtc
);
3459 drm_vblank_off(dev
, pipe
);
3461 if (dev_priv
->fbc
.plane
== plane
)
3462 intel_disable_fbc(dev
);
3464 intel_crtc_update_cursor(crtc
, false);
3465 intel_disable_planes(crtc
);
3466 intel_disable_plane(dev_priv
, plane
, pipe
);
3468 if (intel_crtc
->config
.has_pch_encoder
)
3469 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3471 intel_disable_pipe(dev_priv
, pipe
);
3473 ironlake_pfit_disable(intel_crtc
);
3475 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3476 if (encoder
->post_disable
)
3477 encoder
->post_disable(encoder
);
3479 if (intel_crtc
->config
.has_pch_encoder
) {
3480 ironlake_fdi_disable(crtc
);
3482 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3483 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3485 if (HAS_PCH_CPT(dev
)) {
3486 /* disable TRANS_DP_CTL */
3487 reg
= TRANS_DP_CTL(pipe
);
3488 temp
= I915_READ(reg
);
3489 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3490 TRANS_DP_PORT_SEL_MASK
);
3491 temp
|= TRANS_DP_PORT_SEL_NONE
;
3492 I915_WRITE(reg
, temp
);
3494 /* disable DPLL_SEL */
3495 temp
= I915_READ(PCH_DPLL_SEL
);
3496 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3497 I915_WRITE(PCH_DPLL_SEL
, temp
);
3500 /* disable PCH DPLL */
3501 intel_disable_shared_dpll(intel_crtc
);
3503 ironlake_fdi_pll_disable(intel_crtc
);
3506 intel_crtc
->active
= false;
3507 intel_update_watermarks(crtc
);
3509 mutex_lock(&dev
->struct_mutex
);
3510 intel_update_fbc(dev
);
3511 mutex_unlock(&dev
->struct_mutex
);
3514 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3516 struct drm_device
*dev
= crtc
->dev
;
3517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3518 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3519 struct intel_encoder
*encoder
;
3520 int pipe
= intel_crtc
->pipe
;
3521 int plane
= intel_crtc
->plane
;
3522 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3524 if (!intel_crtc
->active
)
3527 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3528 intel_opregion_notify_encoder(encoder
, false);
3529 encoder
->disable(encoder
);
3532 intel_crtc_wait_for_pending_flips(crtc
);
3533 drm_vblank_off(dev
, pipe
);
3535 /* FBC must be disabled before disabling the plane on HSW. */
3536 if (dev_priv
->fbc
.plane
== plane
)
3537 intel_disable_fbc(dev
);
3539 hsw_disable_ips(intel_crtc
);
3541 intel_crtc_update_cursor(crtc
, false);
3542 intel_disable_planes(crtc
);
3543 intel_disable_plane(dev_priv
, plane
, pipe
);
3545 if (intel_crtc
->config
.has_pch_encoder
)
3546 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3547 intel_disable_pipe(dev_priv
, pipe
);
3549 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3551 ironlake_pfit_disable(intel_crtc
);
3553 intel_ddi_disable_pipe_clock(intel_crtc
);
3555 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3556 if (encoder
->post_disable
)
3557 encoder
->post_disable(encoder
);
3559 if (intel_crtc
->config
.has_pch_encoder
) {
3560 lpt_disable_pch_transcoder(dev_priv
);
3561 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3562 intel_ddi_fdi_disable(crtc
);
3565 intel_crtc
->active
= false;
3566 intel_update_watermarks(crtc
);
3568 mutex_lock(&dev
->struct_mutex
);
3569 intel_update_fbc(dev
);
3570 mutex_unlock(&dev
->struct_mutex
);
3573 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3575 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3576 intel_put_shared_dpll(intel_crtc
);
3579 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3581 intel_ddi_put_crtc_pll(crtc
);
3584 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3586 if (!enable
&& intel_crtc
->overlay
) {
3587 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3590 mutex_lock(&dev
->struct_mutex
);
3591 dev_priv
->mm
.interruptible
= false;
3592 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3593 dev_priv
->mm
.interruptible
= true;
3594 mutex_unlock(&dev
->struct_mutex
);
3597 /* Let userspace switch the overlay on again. In most cases userspace
3598 * has to recompute where to put it anyway.
3603 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3604 * cursor plane briefly if not already running after enabling the display
3606 * This workaround avoids occasional blank screens when self refresh is
3610 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3612 u32 cntl
= I915_READ(CURCNTR(pipe
));
3614 if ((cntl
& CURSOR_MODE
) == 0) {
3615 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3617 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3618 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3619 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3620 I915_WRITE(CURCNTR(pipe
), cntl
);
3621 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3622 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3626 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3628 struct drm_device
*dev
= crtc
->base
.dev
;
3629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3630 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3632 if (!crtc
->config
.gmch_pfit
.control
)
3636 * The panel fitter should only be adjusted whilst the pipe is disabled,
3637 * according to register description and PRM.
3639 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3640 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3642 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3643 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3645 /* Border color in case we don't scale up to the full screen. Black by
3646 * default, change to something else for debugging. */
3647 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3650 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3652 struct drm_device
*dev
= crtc
->dev
;
3653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3654 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3655 struct intel_encoder
*encoder
;
3656 int pipe
= intel_crtc
->pipe
;
3657 int plane
= intel_crtc
->plane
;
3660 WARN_ON(!crtc
->enabled
);
3662 if (intel_crtc
->active
)
3665 intel_crtc
->active
= true;
3667 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3668 if (encoder
->pre_pll_enable
)
3669 encoder
->pre_pll_enable(encoder
);
3671 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3674 vlv_enable_pll(intel_crtc
);
3676 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3677 if (encoder
->pre_enable
)
3678 encoder
->pre_enable(encoder
);
3680 i9xx_pfit_enable(intel_crtc
);
3682 intel_crtc_load_lut(crtc
);
3684 intel_update_watermarks(crtc
);
3685 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3686 intel_enable_plane(dev_priv
, plane
, pipe
);
3687 intel_enable_planes(crtc
);
3688 intel_crtc_update_cursor(crtc
, true);
3690 intel_update_fbc(dev
);
3692 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3693 encoder
->enable(encoder
);
3696 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3698 struct drm_device
*dev
= crtc
->dev
;
3699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3700 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3701 struct intel_encoder
*encoder
;
3702 int pipe
= intel_crtc
->pipe
;
3703 int plane
= intel_crtc
->plane
;
3705 WARN_ON(!crtc
->enabled
);
3707 if (intel_crtc
->active
)
3710 intel_crtc
->active
= true;
3712 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3713 if (encoder
->pre_enable
)
3714 encoder
->pre_enable(encoder
);
3716 i9xx_enable_pll(intel_crtc
);
3718 i9xx_pfit_enable(intel_crtc
);
3720 intel_crtc_load_lut(crtc
);
3722 intel_update_watermarks(crtc
);
3723 intel_enable_pipe(dev_priv
, pipe
, false, false);
3724 intel_enable_plane(dev_priv
, plane
, pipe
);
3725 intel_enable_planes(crtc
);
3726 /* The fixup needs to happen before cursor is enabled */
3728 g4x_fixup_plane(dev_priv
, pipe
);
3729 intel_crtc_update_cursor(crtc
, true);
3731 /* Give the overlay scaler a chance to enable if it's on this pipe */
3732 intel_crtc_dpms_overlay(intel_crtc
, true);
3734 intel_update_fbc(dev
);
3736 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3737 encoder
->enable(encoder
);
3740 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3742 struct drm_device
*dev
= crtc
->base
.dev
;
3743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3745 if (!crtc
->config
.gmch_pfit
.control
)
3748 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3750 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3751 I915_READ(PFIT_CONTROL
));
3752 I915_WRITE(PFIT_CONTROL
, 0);
3755 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3757 struct drm_device
*dev
= crtc
->dev
;
3758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3759 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3760 struct intel_encoder
*encoder
;
3761 int pipe
= intel_crtc
->pipe
;
3762 int plane
= intel_crtc
->plane
;
3764 if (!intel_crtc
->active
)
3767 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3768 encoder
->disable(encoder
);
3770 /* Give the overlay scaler a chance to disable if it's on this pipe */
3771 intel_crtc_wait_for_pending_flips(crtc
);
3772 drm_vblank_off(dev
, pipe
);
3774 if (dev_priv
->fbc
.plane
== plane
)
3775 intel_disable_fbc(dev
);
3777 intel_crtc_dpms_overlay(intel_crtc
, false);
3778 intel_crtc_update_cursor(crtc
, false);
3779 intel_disable_planes(crtc
);
3780 intel_disable_plane(dev_priv
, plane
, pipe
);
3782 intel_disable_pipe(dev_priv
, pipe
);
3784 i9xx_pfit_disable(intel_crtc
);
3786 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3787 if (encoder
->post_disable
)
3788 encoder
->post_disable(encoder
);
3790 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3791 i9xx_disable_pll(dev_priv
, pipe
);
3793 intel_crtc
->active
= false;
3794 intel_update_watermarks(crtc
);
3796 intel_update_fbc(dev
);
3799 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3803 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3806 struct drm_device
*dev
= crtc
->dev
;
3807 struct drm_i915_master_private
*master_priv
;
3808 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3809 int pipe
= intel_crtc
->pipe
;
3811 if (!dev
->primary
->master
)
3814 master_priv
= dev
->primary
->master
->driver_priv
;
3815 if (!master_priv
->sarea_priv
)
3820 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3821 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3824 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3825 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3828 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3834 * Sets the power management mode of the pipe and plane.
3836 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3838 struct drm_device
*dev
= crtc
->dev
;
3839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3840 struct intel_encoder
*intel_encoder
;
3841 bool enable
= false;
3843 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3844 enable
|= intel_encoder
->connectors_active
;
3847 dev_priv
->display
.crtc_enable(crtc
);
3849 dev_priv
->display
.crtc_disable(crtc
);
3851 intel_crtc_update_sarea(crtc
, enable
);
3854 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3856 struct drm_device
*dev
= crtc
->dev
;
3857 struct drm_connector
*connector
;
3858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3861 /* crtc should still be enabled when we disable it. */
3862 WARN_ON(!crtc
->enabled
);
3864 dev_priv
->display
.crtc_disable(crtc
);
3865 intel_crtc
->eld_vld
= false;
3866 intel_crtc_update_sarea(crtc
, false);
3867 dev_priv
->display
.off(crtc
);
3869 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3870 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3873 mutex_lock(&dev
->struct_mutex
);
3874 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3875 mutex_unlock(&dev
->struct_mutex
);
3879 /* Update computed state. */
3880 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3881 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3884 if (connector
->encoder
->crtc
!= crtc
)
3887 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3888 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3892 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3894 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3896 drm_encoder_cleanup(encoder
);
3897 kfree(intel_encoder
);
3900 /* Simple dpms helper for encoders with just one connector, no cloning and only
3901 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3902 * state of the entire output pipe. */
3903 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3905 if (mode
== DRM_MODE_DPMS_ON
) {
3906 encoder
->connectors_active
= true;
3908 intel_crtc_update_dpms(encoder
->base
.crtc
);
3910 encoder
->connectors_active
= false;
3912 intel_crtc_update_dpms(encoder
->base
.crtc
);
3916 /* Cross check the actual hw state with our own modeset state tracking (and it's
3917 * internal consistency). */
3918 static void intel_connector_check_state(struct intel_connector
*connector
)
3920 if (connector
->get_hw_state(connector
)) {
3921 struct intel_encoder
*encoder
= connector
->encoder
;
3922 struct drm_crtc
*crtc
;
3923 bool encoder_enabled
;
3926 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3927 connector
->base
.base
.id
,
3928 drm_get_connector_name(&connector
->base
));
3930 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3931 "wrong connector dpms state\n");
3932 WARN(connector
->base
.encoder
!= &encoder
->base
,
3933 "active connector not linked to encoder\n");
3934 WARN(!encoder
->connectors_active
,
3935 "encoder->connectors_active not set\n");
3937 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3938 WARN(!encoder_enabled
, "encoder not enabled\n");
3939 if (WARN_ON(!encoder
->base
.crtc
))
3942 crtc
= encoder
->base
.crtc
;
3944 WARN(!crtc
->enabled
, "crtc not enabled\n");
3945 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3946 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3947 "encoder active on the wrong pipe\n");
3951 /* Even simpler default implementation, if there's really no special case to
3953 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3955 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3957 /* All the simple cases only support two dpms states. */
3958 if (mode
!= DRM_MODE_DPMS_ON
)
3959 mode
= DRM_MODE_DPMS_OFF
;
3961 if (mode
== connector
->dpms
)
3964 connector
->dpms
= mode
;
3966 /* Only need to change hw state when actually enabled */
3967 if (encoder
->base
.crtc
)
3968 intel_encoder_dpms(encoder
, mode
);
3970 WARN_ON(encoder
->connectors_active
!= false);
3972 intel_modeset_check_state(connector
->dev
);
3975 /* Simple connector->get_hw_state implementation for encoders that support only
3976 * one connector and no cloning and hence the encoder state determines the state
3977 * of the connector. */
3978 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3981 struct intel_encoder
*encoder
= connector
->encoder
;
3983 return encoder
->get_hw_state(encoder
, &pipe
);
3986 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
3987 struct intel_crtc_config
*pipe_config
)
3989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3990 struct intel_crtc
*pipe_B_crtc
=
3991 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3993 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3994 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3995 if (pipe_config
->fdi_lanes
> 4) {
3996 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3997 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4001 if (IS_HASWELL(dev
)) {
4002 if (pipe_config
->fdi_lanes
> 2) {
4003 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4004 pipe_config
->fdi_lanes
);
4011 if (INTEL_INFO(dev
)->num_pipes
== 2)
4014 /* Ivybridge 3 pipe is really complicated */
4019 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4020 pipe_config
->fdi_lanes
> 2) {
4021 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4022 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4027 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4028 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4029 if (pipe_config
->fdi_lanes
> 2) {
4030 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4031 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4035 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4045 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4046 struct intel_crtc_config
*pipe_config
)
4048 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4049 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4050 int lane
, link_bw
, fdi_dotclock
;
4051 bool setup_ok
, needs_recompute
= false;
4054 /* FDI is a binary signal running at ~2.7GHz, encoding
4055 * each output octet as 10 bits. The actual frequency
4056 * is stored as a divider into a 100MHz clock, and the
4057 * mode pixel clock is stored in units of 1KHz.
4058 * Hence the bw of each lane in terms of the mode signal
4061 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4063 fdi_dotclock
= adjusted_mode
->clock
;
4064 fdi_dotclock
/= pipe_config
->pixel_multiplier
;
4066 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4067 pipe_config
->pipe_bpp
);
4069 pipe_config
->fdi_lanes
= lane
;
4071 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4072 link_bw
, &pipe_config
->fdi_m_n
);
4074 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4075 intel_crtc
->pipe
, pipe_config
);
4076 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4077 pipe_config
->pipe_bpp
-= 2*3;
4078 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4079 pipe_config
->pipe_bpp
);
4080 needs_recompute
= true;
4081 pipe_config
->bw_constrained
= true;
4086 if (needs_recompute
)
4089 return setup_ok
? 0 : -EINVAL
;
4092 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4093 struct intel_crtc_config
*pipe_config
)
4095 pipe_config
->ips_enabled
= i915_enable_ips
&&
4096 hsw_crtc_supports_ips(crtc
) &&
4097 pipe_config
->pipe_bpp
<= 24;
4100 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4101 struct intel_crtc_config
*pipe_config
)
4103 struct drm_device
*dev
= crtc
->base
.dev
;
4104 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4106 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4107 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4109 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4110 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4113 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4114 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4115 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4116 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4118 pipe_config
->pipe_bpp
= 8*3;
4122 hsw_compute_ips_config(crtc
, pipe_config
);
4124 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4125 * clock survives for now. */
4126 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4127 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4129 if (pipe_config
->has_pch_encoder
)
4130 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4135 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4137 return 400000; /* FIXME */
4140 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4145 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4150 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4155 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4159 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4161 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4162 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4164 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4166 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4168 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4171 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4172 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4174 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4179 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4183 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4185 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4188 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4189 case GC_DISPLAY_CLOCK_333_MHZ
:
4192 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4198 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4203 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4206 /* Assume that the hardware is in the high speed state. This
4207 * should be the default.
4209 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4210 case GC_CLOCK_133_200
:
4211 case GC_CLOCK_100_200
:
4213 case GC_CLOCK_166_250
:
4215 case GC_CLOCK_100_133
:
4219 /* Shouldn't happen */
4223 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4229 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4231 while (*num
> DATA_LINK_M_N_MASK
||
4232 *den
> DATA_LINK_M_N_MASK
) {
4238 static void compute_m_n(unsigned int m
, unsigned int n
,
4239 uint32_t *ret_m
, uint32_t *ret_n
)
4241 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4242 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4243 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4247 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4248 int pixel_clock
, int link_clock
,
4249 struct intel_link_m_n
*m_n
)
4253 compute_m_n(bits_per_pixel
* pixel_clock
,
4254 link_clock
* nlanes
* 8,
4255 &m_n
->gmch_m
, &m_n
->gmch_n
);
4257 compute_m_n(pixel_clock
, link_clock
,
4258 &m_n
->link_m
, &m_n
->link_n
);
4261 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4263 if (i915_panel_use_ssc
>= 0)
4264 return i915_panel_use_ssc
!= 0;
4265 return dev_priv
->vbt
.lvds_use_ssc
4266 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4269 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4271 struct drm_device
*dev
= crtc
->dev
;
4272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4273 int refclk
= 27000; /* for DP & HDMI */
4275 return 100000; /* only one validated so far */
4277 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4279 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4280 if (intel_panel_use_ssc(dev_priv
))
4284 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4291 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4293 struct drm_device
*dev
= crtc
->dev
;
4294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4297 if (IS_VALLEYVIEW(dev
)) {
4298 refclk
= vlv_get_refclk(crtc
);
4299 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4300 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4301 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4302 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4304 } else if (!IS_GEN2(dev
)) {
4313 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4315 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4318 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4320 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4323 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4324 intel_clock_t
*reduced_clock
)
4326 struct drm_device
*dev
= crtc
->base
.dev
;
4327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4328 int pipe
= crtc
->pipe
;
4331 if (IS_PINEVIEW(dev
)) {
4332 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4334 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4336 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4338 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4341 I915_WRITE(FP0(pipe
), fp
);
4342 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4344 crtc
->lowfreq_avail
= false;
4345 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4346 reduced_clock
&& i915_powersave
) {
4347 I915_WRITE(FP1(pipe
), fp2
);
4348 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4349 crtc
->lowfreq_avail
= true;
4351 I915_WRITE(FP1(pipe
), fp
);
4352 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4356 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4362 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4363 * and set it to a reasonable value instead.
4365 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4366 reg_val
&= 0xffffff00;
4367 reg_val
|= 0x00000030;
4368 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4370 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4371 reg_val
&= 0x8cffffff;
4372 reg_val
= 0x8c000000;
4373 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4375 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4376 reg_val
&= 0xffffff00;
4377 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4379 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4380 reg_val
&= 0x00ffffff;
4381 reg_val
|= 0xb0000000;
4382 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4385 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4386 struct intel_link_m_n
*m_n
)
4388 struct drm_device
*dev
= crtc
->base
.dev
;
4389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4390 int pipe
= crtc
->pipe
;
4392 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4393 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4394 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4395 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4398 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4399 struct intel_link_m_n
*m_n
)
4401 struct drm_device
*dev
= crtc
->base
.dev
;
4402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4403 int pipe
= crtc
->pipe
;
4404 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4406 if (INTEL_INFO(dev
)->gen
>= 5) {
4407 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4408 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4409 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4410 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4412 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4413 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4414 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4415 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4419 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4421 if (crtc
->config
.has_pch_encoder
)
4422 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4424 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4427 static void vlv_update_pll(struct intel_crtc
*crtc
)
4429 struct drm_device
*dev
= crtc
->base
.dev
;
4430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4431 int pipe
= crtc
->pipe
;
4433 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4434 u32 coreclk
, reg_val
, dpll_md
;
4436 mutex_lock(&dev_priv
->dpio_lock
);
4438 bestn
= crtc
->config
.dpll
.n
;
4439 bestm1
= crtc
->config
.dpll
.m1
;
4440 bestm2
= crtc
->config
.dpll
.m2
;
4441 bestp1
= crtc
->config
.dpll
.p1
;
4442 bestp2
= crtc
->config
.dpll
.p2
;
4444 /* See eDP HDMI DPIO driver vbios notes doc */
4446 /* PLL B needs special handling */
4448 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4450 /* Set up Tx target for periodic Rcomp update */
4451 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4453 /* Disable target IRef on PLL */
4454 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4455 reg_val
&= 0x00ffffff;
4456 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4458 /* Disable fast lock */
4459 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4461 /* Set idtafcrecal before PLL is enabled */
4462 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4463 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4464 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4465 mdiv
|= (1 << DPIO_K_SHIFT
);
4468 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4469 * but we don't support that).
4470 * Note: don't use the DAC post divider as it seems unstable.
4472 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4473 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4475 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4476 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4478 /* Set HBR and RBR LPF coefficients */
4479 if (crtc
->config
.port_clock
== 162000 ||
4480 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4481 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4482 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4485 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4488 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4489 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4490 /* Use SSC source */
4492 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4495 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4497 } else { /* HDMI or VGA */
4498 /* Use bend source */
4500 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4503 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4507 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4508 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4509 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4510 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4511 coreclk
|= 0x01000000;
4512 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4514 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4516 /* Enable DPIO clock input */
4517 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4518 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4520 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4522 dpll
|= DPLL_VCO_ENABLE
;
4523 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4525 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4526 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4527 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4529 if (crtc
->config
.has_dp_encoder
)
4530 intel_dp_set_m_n(crtc
);
4532 mutex_unlock(&dev_priv
->dpio_lock
);
4535 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4536 intel_clock_t
*reduced_clock
,
4539 struct drm_device
*dev
= crtc
->base
.dev
;
4540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4543 struct dpll
*clock
= &crtc
->config
.dpll
;
4545 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4547 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4548 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4550 dpll
= DPLL_VGA_MODE_DIS
;
4552 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4553 dpll
|= DPLLB_MODE_LVDS
;
4555 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4557 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4558 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4559 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4563 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4565 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4566 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4568 /* compute bitmask from p1 value */
4569 if (IS_PINEVIEW(dev
))
4570 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4572 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4573 if (IS_G4X(dev
) && reduced_clock
)
4574 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4576 switch (clock
->p2
) {
4578 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4581 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4584 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4587 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4590 if (INTEL_INFO(dev
)->gen
>= 4)
4591 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4593 if (crtc
->config
.sdvo_tv_clock
)
4594 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4595 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4596 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4597 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4599 dpll
|= PLL_REF_INPUT_DREFCLK
;
4601 dpll
|= DPLL_VCO_ENABLE
;
4602 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4604 if (INTEL_INFO(dev
)->gen
>= 4) {
4605 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4606 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4607 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4610 if (crtc
->config
.has_dp_encoder
)
4611 intel_dp_set_m_n(crtc
);
4614 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4615 intel_clock_t
*reduced_clock
,
4618 struct drm_device
*dev
= crtc
->base
.dev
;
4619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4621 struct dpll
*clock
= &crtc
->config
.dpll
;
4623 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4625 dpll
= DPLL_VGA_MODE_DIS
;
4627 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4628 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4631 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4633 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4635 dpll
|= PLL_P2_DIVIDE_BY_4
;
4638 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4639 dpll
|= DPLL_DVO_2X_MODE
;
4641 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4642 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4643 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4645 dpll
|= PLL_REF_INPUT_DREFCLK
;
4647 dpll
|= DPLL_VCO_ENABLE
;
4648 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4651 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4653 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4655 enum pipe pipe
= intel_crtc
->pipe
;
4656 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4657 struct drm_display_mode
*adjusted_mode
=
4658 &intel_crtc
->config
.adjusted_mode
;
4659 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4660 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4662 /* We need to be careful not to changed the adjusted mode, for otherwise
4663 * the hw state checker will get angry at the mismatch. */
4664 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4665 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4667 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4668 /* the chip adds 2 halflines automatically */
4670 crtc_vblank_end
-= 1;
4671 vsyncshift
= adjusted_mode
->crtc_hsync_start
4672 - adjusted_mode
->crtc_htotal
/ 2;
4677 if (INTEL_INFO(dev
)->gen
> 3)
4678 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4680 I915_WRITE(HTOTAL(cpu_transcoder
),
4681 (adjusted_mode
->crtc_hdisplay
- 1) |
4682 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4683 I915_WRITE(HBLANK(cpu_transcoder
),
4684 (adjusted_mode
->crtc_hblank_start
- 1) |
4685 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4686 I915_WRITE(HSYNC(cpu_transcoder
),
4687 (adjusted_mode
->crtc_hsync_start
- 1) |
4688 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4690 I915_WRITE(VTOTAL(cpu_transcoder
),
4691 (adjusted_mode
->crtc_vdisplay
- 1) |
4692 ((crtc_vtotal
- 1) << 16));
4693 I915_WRITE(VBLANK(cpu_transcoder
),
4694 (adjusted_mode
->crtc_vblank_start
- 1) |
4695 ((crtc_vblank_end
- 1) << 16));
4696 I915_WRITE(VSYNC(cpu_transcoder
),
4697 (adjusted_mode
->crtc_vsync_start
- 1) |
4698 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4700 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4701 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4702 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4704 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4705 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4706 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4708 /* pipesrc controls the size that is scaled from, which should
4709 * always be the user's requested size.
4711 I915_WRITE(PIPESRC(pipe
),
4712 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4715 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4716 struct intel_crtc_config
*pipe_config
)
4718 struct drm_device
*dev
= crtc
->base
.dev
;
4719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4720 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4723 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4724 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4725 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4726 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4727 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4728 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4729 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4730 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4731 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4733 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4734 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4735 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4736 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4737 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4738 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4739 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4740 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4741 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4743 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4744 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4745 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4746 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4749 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4750 pipe_config
->requested_mode
.vdisplay
= (tmp
& 0xffff) + 1;
4751 pipe_config
->requested_mode
.hdisplay
= ((tmp
>> 16) & 0xffff) + 1;
4754 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4755 struct intel_crtc_config
*pipe_config
)
4757 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4759 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4760 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4761 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4762 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4764 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4765 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4766 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4767 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4769 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4771 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.clock
;
4772 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4775 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4777 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4783 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4784 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4787 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4790 if (intel_crtc
->config
.requested_mode
.clock
>
4791 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4792 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4795 /* only g4x and later have fancy bpc/dither controls */
4796 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4797 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4798 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4799 pipeconf
|= PIPECONF_DITHER_EN
|
4800 PIPECONF_DITHER_TYPE_SP
;
4802 switch (intel_crtc
->config
.pipe_bpp
) {
4804 pipeconf
|= PIPECONF_6BPC
;
4807 pipeconf
|= PIPECONF_8BPC
;
4810 pipeconf
|= PIPECONF_10BPC
;
4813 /* Case prevented by intel_choose_pipe_bpp_dither. */
4818 if (HAS_PIPE_CXSR(dev
)) {
4819 if (intel_crtc
->lowfreq_avail
) {
4820 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4821 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4823 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4827 if (!IS_GEN2(dev
) &&
4828 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4829 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4831 pipeconf
|= PIPECONF_PROGRESSIVE
;
4833 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4834 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4836 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4837 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4840 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4842 struct drm_framebuffer
*fb
)
4844 struct drm_device
*dev
= crtc
->dev
;
4845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4847 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4848 int pipe
= intel_crtc
->pipe
;
4849 int plane
= intel_crtc
->plane
;
4850 int refclk
, num_connectors
= 0;
4851 intel_clock_t clock
, reduced_clock
;
4853 bool ok
, has_reduced_clock
= false;
4854 bool is_lvds
= false, is_dsi
= false;
4855 struct intel_encoder
*encoder
;
4856 const intel_limit_t
*limit
;
4859 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4860 switch (encoder
->type
) {
4861 case INTEL_OUTPUT_LVDS
:
4864 case INTEL_OUTPUT_DSI
:
4872 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4874 if (!is_dsi
&& !intel_crtc
->config
.clock_set
) {
4876 * Returns a set of divisors for the desired target clock with
4877 * the given refclk, or FALSE. The returned values represent
4878 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4881 limit
= intel_limit(crtc
, refclk
);
4882 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4883 intel_crtc
->config
.port_clock
,
4884 refclk
, NULL
, &clock
);
4885 if (!ok
&& !intel_crtc
->config
.clock_set
) {
4886 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4891 /* Ensure that the cursor is valid for the new mode before changing... */
4892 intel_crtc_update_cursor(crtc
, true);
4894 if (!is_dsi
&& is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4896 * Ensure we match the reduced clock's P to the target clock.
4897 * If the clocks don't match, we can't switch the display clock
4898 * by using the FP0/FP1. In such case we will disable the LVDS
4899 * downclock feature.
4901 limit
= intel_limit(crtc
, refclk
);
4903 dev_priv
->display
.find_dpll(limit
, crtc
,
4904 dev_priv
->lvds_downclock
,
4908 /* Compat-code for transition, will disappear. */
4909 if (!intel_crtc
->config
.clock_set
) {
4910 intel_crtc
->config
.dpll
.n
= clock
.n
;
4911 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4912 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4913 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4914 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4918 i8xx_update_pll(intel_crtc
,
4919 has_reduced_clock
? &reduced_clock
: NULL
,
4921 } else if (IS_VALLEYVIEW(dev
)) {
4923 vlv_update_pll(intel_crtc
);
4925 i9xx_update_pll(intel_crtc
,
4926 has_reduced_clock
? &reduced_clock
: NULL
,
4930 /* Set up the display plane register */
4931 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4933 if (!IS_VALLEYVIEW(dev
)) {
4935 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4937 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4940 intel_set_pipe_timings(intel_crtc
);
4942 /* pipesrc and dspsize control the size that is scaled from,
4943 * which should always be the user's requested size.
4945 I915_WRITE(DSPSIZE(plane
),
4946 ((mode
->vdisplay
- 1) << 16) |
4947 (mode
->hdisplay
- 1));
4948 I915_WRITE(DSPPOS(plane
), 0);
4950 i9xx_set_pipeconf(intel_crtc
);
4952 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4953 POSTING_READ(DSPCNTR(plane
));
4955 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4960 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
4961 struct intel_crtc_config
*pipe_config
)
4963 struct drm_device
*dev
= crtc
->base
.dev
;
4964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4967 tmp
= I915_READ(PFIT_CONTROL
);
4968 if (!(tmp
& PFIT_ENABLE
))
4971 /* Check whether the pfit is attached to our pipe. */
4972 if (INTEL_INFO(dev
)->gen
< 4) {
4973 if (crtc
->pipe
!= PIPE_B
)
4976 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
4980 pipe_config
->gmch_pfit
.control
= tmp
;
4981 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
4982 if (INTEL_INFO(dev
)->gen
< 5)
4983 pipe_config
->gmch_pfit
.lvds_border_bits
=
4984 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
4987 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4988 struct intel_crtc_config
*pipe_config
)
4990 struct drm_device
*dev
= crtc
->base
.dev
;
4991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4994 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
4995 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
4997 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4998 if (!(tmp
& PIPECONF_ENABLE
))
5001 intel_get_pipe_timings(crtc
, pipe_config
);
5003 i9xx_get_pfit_config(crtc
, pipe_config
);
5005 if (INTEL_INFO(dev
)->gen
>= 4) {
5006 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5007 pipe_config
->pixel_multiplier
=
5008 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5009 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5010 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5011 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5012 tmp
= I915_READ(DPLL(crtc
->pipe
));
5013 pipe_config
->pixel_multiplier
=
5014 ((tmp
& SDVO_MULTIPLIER_MASK
)
5015 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5017 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5018 * port and will be fixed up in the encoder->get_config
5020 pipe_config
->pixel_multiplier
= 1;
5022 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5023 if (!IS_VALLEYVIEW(dev
)) {
5024 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5025 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5027 /* Mask out read-only status bits. */
5028 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5029 DPLL_PORTC_READY_MASK
|
5030 DPLL_PORTB_READY_MASK
);
5036 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5039 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5040 struct intel_encoder
*encoder
;
5042 bool has_lvds
= false;
5043 bool has_cpu_edp
= false;
5044 bool has_panel
= false;
5045 bool has_ck505
= false;
5046 bool can_ssc
= false;
5048 /* We need to take the global config into account */
5049 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5051 switch (encoder
->type
) {
5052 case INTEL_OUTPUT_LVDS
:
5056 case INTEL_OUTPUT_EDP
:
5058 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5064 if (HAS_PCH_IBX(dev
)) {
5065 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5066 can_ssc
= has_ck505
;
5072 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5073 has_panel
, has_lvds
, has_ck505
);
5075 /* Ironlake: try to setup display ref clock before DPLL
5076 * enabling. This is only under driver's control after
5077 * PCH B stepping, previous chipset stepping should be
5078 * ignoring this setting.
5080 val
= I915_READ(PCH_DREF_CONTROL
);
5082 /* As we must carefully and slowly disable/enable each source in turn,
5083 * compute the final state we want first and check if we need to
5084 * make any changes at all.
5087 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5089 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5091 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5093 final
&= ~DREF_SSC_SOURCE_MASK
;
5094 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5095 final
&= ~DREF_SSC1_ENABLE
;
5098 final
|= DREF_SSC_SOURCE_ENABLE
;
5100 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5101 final
|= DREF_SSC1_ENABLE
;
5104 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5105 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5107 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5109 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5111 final
|= DREF_SSC_SOURCE_DISABLE
;
5112 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5118 /* Always enable nonspread source */
5119 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5122 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5124 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5127 val
&= ~DREF_SSC_SOURCE_MASK
;
5128 val
|= DREF_SSC_SOURCE_ENABLE
;
5130 /* SSC must be turned on before enabling the CPU output */
5131 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5132 DRM_DEBUG_KMS("Using SSC on panel\n");
5133 val
|= DREF_SSC1_ENABLE
;
5135 val
&= ~DREF_SSC1_ENABLE
;
5137 /* Get SSC going before enabling the outputs */
5138 I915_WRITE(PCH_DREF_CONTROL
, val
);
5139 POSTING_READ(PCH_DREF_CONTROL
);
5142 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5144 /* Enable CPU source on CPU attached eDP */
5146 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5147 DRM_DEBUG_KMS("Using SSC on eDP\n");
5148 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5151 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5153 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5155 I915_WRITE(PCH_DREF_CONTROL
, val
);
5156 POSTING_READ(PCH_DREF_CONTROL
);
5159 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5161 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5163 /* Turn off CPU output */
5164 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5166 I915_WRITE(PCH_DREF_CONTROL
, val
);
5167 POSTING_READ(PCH_DREF_CONTROL
);
5170 /* Turn off the SSC source */
5171 val
&= ~DREF_SSC_SOURCE_MASK
;
5172 val
|= DREF_SSC_SOURCE_DISABLE
;
5175 val
&= ~DREF_SSC1_ENABLE
;
5177 I915_WRITE(PCH_DREF_CONTROL
, val
);
5178 POSTING_READ(PCH_DREF_CONTROL
);
5182 BUG_ON(val
!= final
);
5185 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5189 tmp
= I915_READ(SOUTH_CHICKEN2
);
5190 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5191 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5193 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5194 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5195 DRM_ERROR("FDI mPHY reset assert timeout\n");
5197 tmp
= I915_READ(SOUTH_CHICKEN2
);
5198 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5199 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5201 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5202 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5203 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5206 /* WaMPhyProgramming:hsw */
5207 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5211 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5212 tmp
&= ~(0xFF << 24);
5213 tmp
|= (0x12 << 24);
5214 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5216 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5218 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5220 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5222 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5224 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5225 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5226 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5228 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5229 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5230 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5232 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5235 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5237 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5240 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5242 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5245 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5247 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5250 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5252 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5253 tmp
&= ~(0xFF << 16);
5254 tmp
|= (0x1C << 16);
5255 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5257 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5258 tmp
&= ~(0xFF << 16);
5259 tmp
|= (0x1C << 16);
5260 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5262 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5264 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5266 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5268 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5270 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5271 tmp
&= ~(0xF << 28);
5273 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5275 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5276 tmp
&= ~(0xF << 28);
5278 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5281 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5282 * Programming" based on the parameters passed:
5283 * - Sequence to enable CLKOUT_DP
5284 * - Sequence to enable CLKOUT_DP without spread
5285 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5287 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5293 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5295 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5296 with_fdi
, "LP PCH doesn't have FDI\n"))
5299 mutex_lock(&dev_priv
->dpio_lock
);
5301 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5302 tmp
&= ~SBI_SSCCTL_DISABLE
;
5303 tmp
|= SBI_SSCCTL_PATHALT
;
5304 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5309 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5310 tmp
&= ~SBI_SSCCTL_PATHALT
;
5311 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5314 lpt_reset_fdi_mphy(dev_priv
);
5315 lpt_program_fdi_mphy(dev_priv
);
5319 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5320 SBI_GEN0
: SBI_DBUFF0
;
5321 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5322 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5323 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5325 mutex_unlock(&dev_priv
->dpio_lock
);
5328 /* Sequence to disable CLKOUT_DP */
5329 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5334 mutex_lock(&dev_priv
->dpio_lock
);
5336 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5337 SBI_GEN0
: SBI_DBUFF0
;
5338 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5339 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5340 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5342 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5343 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5344 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5345 tmp
|= SBI_SSCCTL_PATHALT
;
5346 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5349 tmp
|= SBI_SSCCTL_DISABLE
;
5350 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5353 mutex_unlock(&dev_priv
->dpio_lock
);
5356 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5358 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5359 struct intel_encoder
*encoder
;
5360 bool has_vga
= false;
5362 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5363 switch (encoder
->type
) {
5364 case INTEL_OUTPUT_ANALOG
:
5371 lpt_enable_clkout_dp(dev
, true, true);
5373 lpt_disable_clkout_dp(dev
);
5377 * Initialize reference clocks when the driver loads
5379 void intel_init_pch_refclk(struct drm_device
*dev
)
5381 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5382 ironlake_init_pch_refclk(dev
);
5383 else if (HAS_PCH_LPT(dev
))
5384 lpt_init_pch_refclk(dev
);
5387 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5389 struct drm_device
*dev
= crtc
->dev
;
5390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5391 struct intel_encoder
*encoder
;
5392 int num_connectors
= 0;
5393 bool is_lvds
= false;
5395 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5396 switch (encoder
->type
) {
5397 case INTEL_OUTPUT_LVDS
:
5404 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5405 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5406 dev_priv
->vbt
.lvds_ssc_freq
);
5407 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5413 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5415 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5416 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5417 int pipe
= intel_crtc
->pipe
;
5422 switch (intel_crtc
->config
.pipe_bpp
) {
5424 val
|= PIPECONF_6BPC
;
5427 val
|= PIPECONF_8BPC
;
5430 val
|= PIPECONF_10BPC
;
5433 val
|= PIPECONF_12BPC
;
5436 /* Case prevented by intel_choose_pipe_bpp_dither. */
5440 if (intel_crtc
->config
.dither
)
5441 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5443 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5444 val
|= PIPECONF_INTERLACED_ILK
;
5446 val
|= PIPECONF_PROGRESSIVE
;
5448 if (intel_crtc
->config
.limited_color_range
)
5449 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5451 I915_WRITE(PIPECONF(pipe
), val
);
5452 POSTING_READ(PIPECONF(pipe
));
5456 * Set up the pipe CSC unit.
5458 * Currently only full range RGB to limited range RGB conversion
5459 * is supported, but eventually this should handle various
5460 * RGB<->YCbCr scenarios as well.
5462 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5464 struct drm_device
*dev
= crtc
->dev
;
5465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5466 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5467 int pipe
= intel_crtc
->pipe
;
5468 uint16_t coeff
= 0x7800; /* 1.0 */
5471 * TODO: Check what kind of values actually come out of the pipe
5472 * with these coeff/postoff values and adjust to get the best
5473 * accuracy. Perhaps we even need to take the bpc value into
5477 if (intel_crtc
->config
.limited_color_range
)
5478 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5481 * GY/GU and RY/RU should be the other way around according
5482 * to BSpec, but reality doesn't agree. Just set them up in
5483 * a way that results in the correct picture.
5485 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5486 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5488 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5489 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5491 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5492 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5494 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5495 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5496 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5498 if (INTEL_INFO(dev
)->gen
> 6) {
5499 uint16_t postoff
= 0;
5501 if (intel_crtc
->config
.limited_color_range
)
5502 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5504 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5505 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5506 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5508 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5510 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5512 if (intel_crtc
->config
.limited_color_range
)
5513 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5515 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5519 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5521 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5522 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5523 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5528 if (intel_crtc
->config
.dither
)
5529 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5531 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5532 val
|= PIPECONF_INTERLACED_ILK
;
5534 val
|= PIPECONF_PROGRESSIVE
;
5536 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5537 POSTING_READ(PIPECONF(cpu_transcoder
));
5539 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5540 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5543 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5544 intel_clock_t
*clock
,
5545 bool *has_reduced_clock
,
5546 intel_clock_t
*reduced_clock
)
5548 struct drm_device
*dev
= crtc
->dev
;
5549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5550 struct intel_encoder
*intel_encoder
;
5552 const intel_limit_t
*limit
;
5553 bool ret
, is_lvds
= false;
5555 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5556 switch (intel_encoder
->type
) {
5557 case INTEL_OUTPUT_LVDS
:
5563 refclk
= ironlake_get_refclk(crtc
);
5566 * Returns a set of divisors for the desired target clock with the given
5567 * refclk, or FALSE. The returned values represent the clock equation:
5568 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5570 limit
= intel_limit(crtc
, refclk
);
5571 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5572 to_intel_crtc(crtc
)->config
.port_clock
,
5573 refclk
, NULL
, clock
);
5577 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5579 * Ensure we match the reduced clock's P to the target clock.
5580 * If the clocks don't match, we can't switch the display clock
5581 * by using the FP0/FP1. In such case we will disable the LVDS
5582 * downclock feature.
5584 *has_reduced_clock
=
5585 dev_priv
->display
.find_dpll(limit
, crtc
,
5586 dev_priv
->lvds_downclock
,
5594 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5599 temp
= I915_READ(SOUTH_CHICKEN1
);
5600 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5603 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5604 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5606 temp
|= FDI_BC_BIFURCATION_SELECT
;
5607 DRM_DEBUG_KMS("enabling fdi C rx\n");
5608 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5609 POSTING_READ(SOUTH_CHICKEN1
);
5612 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5614 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5617 switch (intel_crtc
->pipe
) {
5621 if (intel_crtc
->config
.fdi_lanes
> 2)
5622 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5624 cpt_enable_fdi_bc_bifurcation(dev
);
5628 cpt_enable_fdi_bc_bifurcation(dev
);
5636 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5639 * Account for spread spectrum to avoid
5640 * oversubscribing the link. Max center spread
5641 * is 2.5%; use 5% for safety's sake.
5643 u32 bps
= target_clock
* bpp
* 21 / 20;
5644 return bps
/ (link_bw
* 8) + 1;
5647 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5649 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5652 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5654 intel_clock_t
*reduced_clock
, u32
*fp2
)
5656 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5657 struct drm_device
*dev
= crtc
->dev
;
5658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5659 struct intel_encoder
*intel_encoder
;
5661 int factor
, num_connectors
= 0;
5662 bool is_lvds
= false, is_sdvo
= false;
5664 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5665 switch (intel_encoder
->type
) {
5666 case INTEL_OUTPUT_LVDS
:
5669 case INTEL_OUTPUT_SDVO
:
5670 case INTEL_OUTPUT_HDMI
:
5678 /* Enable autotuning of the PLL clock (if permissible) */
5681 if ((intel_panel_use_ssc(dev_priv
) &&
5682 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5683 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5685 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5688 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5691 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5697 dpll
|= DPLLB_MODE_LVDS
;
5699 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5701 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5702 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5705 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5706 if (intel_crtc
->config
.has_dp_encoder
)
5707 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5709 /* compute bitmask from p1 value */
5710 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5712 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5714 switch (intel_crtc
->config
.dpll
.p2
) {
5716 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5719 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5722 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5725 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5729 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5730 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5732 dpll
|= PLL_REF_INPUT_DREFCLK
;
5734 return dpll
| DPLL_VCO_ENABLE
;
5737 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5739 struct drm_framebuffer
*fb
)
5741 struct drm_device
*dev
= crtc
->dev
;
5742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5743 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5744 int pipe
= intel_crtc
->pipe
;
5745 int plane
= intel_crtc
->plane
;
5746 int num_connectors
= 0;
5747 intel_clock_t clock
, reduced_clock
;
5748 u32 dpll
= 0, fp
= 0, fp2
= 0;
5749 bool ok
, has_reduced_clock
= false;
5750 bool is_lvds
= false;
5751 struct intel_encoder
*encoder
;
5752 struct intel_shared_dpll
*pll
;
5755 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5756 switch (encoder
->type
) {
5757 case INTEL_OUTPUT_LVDS
:
5765 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5766 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5768 ok
= ironlake_compute_clocks(crtc
, &clock
,
5769 &has_reduced_clock
, &reduced_clock
);
5770 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5771 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5774 /* Compat-code for transition, will disappear. */
5775 if (!intel_crtc
->config
.clock_set
) {
5776 intel_crtc
->config
.dpll
.n
= clock
.n
;
5777 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5778 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5779 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5780 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5783 /* Ensure that the cursor is valid for the new mode before changing... */
5784 intel_crtc_update_cursor(crtc
, true);
5786 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5787 if (intel_crtc
->config
.has_pch_encoder
) {
5788 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5789 if (has_reduced_clock
)
5790 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5792 dpll
= ironlake_compute_dpll(intel_crtc
,
5793 &fp
, &reduced_clock
,
5794 has_reduced_clock
? &fp2
: NULL
);
5796 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5797 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5798 if (has_reduced_clock
)
5799 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5801 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5803 pll
= intel_get_shared_dpll(intel_crtc
);
5805 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5810 intel_put_shared_dpll(intel_crtc
);
5812 if (intel_crtc
->config
.has_dp_encoder
)
5813 intel_dp_set_m_n(intel_crtc
);
5815 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5816 intel_crtc
->lowfreq_avail
= true;
5818 intel_crtc
->lowfreq_avail
= false;
5820 if (intel_crtc
->config
.has_pch_encoder
) {
5821 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5825 intel_set_pipe_timings(intel_crtc
);
5827 if (intel_crtc
->config
.has_pch_encoder
) {
5828 intel_cpu_transcoder_set_m_n(intel_crtc
,
5829 &intel_crtc
->config
.fdi_m_n
);
5832 if (IS_IVYBRIDGE(dev
))
5833 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5835 ironlake_set_pipeconf(crtc
);
5837 /* Set up the display plane register */
5838 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5839 POSTING_READ(DSPCNTR(plane
));
5841 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5846 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
5847 struct intel_crtc_config
*pipe_config
)
5849 struct drm_device
*dev
= crtc
->base
.dev
;
5850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5851 enum transcoder transcoder
= pipe_config
->cpu_transcoder
;
5853 pipe_config
->fdi_m_n
.link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
5854 pipe_config
->fdi_m_n
.link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
5855 pipe_config
->fdi_m_n
.gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
5857 pipe_config
->fdi_m_n
.gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
5858 pipe_config
->fdi_m_n
.tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
5859 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5862 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
5863 struct intel_crtc_config
*pipe_config
)
5865 struct drm_device
*dev
= crtc
->base
.dev
;
5866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5869 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
5871 if (tmp
& PF_ENABLE
) {
5872 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
5873 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
5875 /* We currently do not free assignements of panel fitters on
5876 * ivb/hsw (since we don't use the higher upscaling modes which
5877 * differentiates them) so just WARN about this case for now. */
5879 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
5880 PF_PIPE_SEL_IVB(crtc
->pipe
));
5885 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5886 struct intel_crtc_config
*pipe_config
)
5888 struct drm_device
*dev
= crtc
->base
.dev
;
5889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5892 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5893 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5895 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5896 if (!(tmp
& PIPECONF_ENABLE
))
5899 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
5900 struct intel_shared_dpll
*pll
;
5902 pipe_config
->has_pch_encoder
= true;
5904 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
5905 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
5906 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
5908 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
5910 if (HAS_PCH_IBX(dev_priv
->dev
)) {
5911 pipe_config
->shared_dpll
=
5912 (enum intel_dpll_id
) crtc
->pipe
;
5914 tmp
= I915_READ(PCH_DPLL_SEL
);
5915 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
5916 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
5918 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
5921 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
5923 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
5924 &pipe_config
->dpll_hw_state
));
5926 tmp
= pipe_config
->dpll_hw_state
.dpll
;
5927 pipe_config
->pixel_multiplier
=
5928 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
5929 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
5931 pipe_config
->pixel_multiplier
= 1;
5934 intel_get_pipe_timings(crtc
, pipe_config
);
5936 ironlake_get_pfit_config(crtc
, pipe_config
);
5941 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
5943 struct drm_device
*dev
= dev_priv
->dev
;
5944 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
5945 struct intel_crtc
*crtc
;
5946 unsigned long irqflags
;
5949 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
5950 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
5951 pipe_name(crtc
->pipe
));
5953 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
5954 WARN(plls
->spll_refcount
, "SPLL enabled\n");
5955 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
5956 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
5957 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
5958 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
5959 "CPU PWM1 enabled\n");
5960 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
5961 "CPU PWM2 enabled\n");
5962 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
5963 "PCH PWM1 enabled\n");
5964 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
5965 "Utility pin enabled\n");
5966 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
5968 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
5969 val
= I915_READ(DEIMR
);
5970 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
5971 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
5972 val
= I915_READ(SDEIMR
);
5973 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
5974 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
5975 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
5979 * This function implements pieces of two sequences from BSpec:
5980 * - Sequence for display software to disable LCPLL
5981 * - Sequence for display software to allow package C8+
5982 * The steps implemented here are just the steps that actually touch the LCPLL
5983 * register. Callers should take care of disabling all the display engine
5984 * functions, doing the mode unset, fixing interrupts, etc.
5986 void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
5987 bool switch_to_fclk
, bool allow_power_down
)
5991 assert_can_disable_lcpll(dev_priv
);
5993 val
= I915_READ(LCPLL_CTL
);
5995 if (switch_to_fclk
) {
5996 val
|= LCPLL_CD_SOURCE_FCLK
;
5997 I915_WRITE(LCPLL_CTL
, val
);
5999 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6000 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6001 DRM_ERROR("Switching to FCLK failed\n");
6003 val
= I915_READ(LCPLL_CTL
);
6006 val
|= LCPLL_PLL_DISABLE
;
6007 I915_WRITE(LCPLL_CTL
, val
);
6008 POSTING_READ(LCPLL_CTL
);
6010 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6011 DRM_ERROR("LCPLL still locked\n");
6013 val
= I915_READ(D_COMP
);
6014 val
|= D_COMP_COMP_DISABLE
;
6015 I915_WRITE(D_COMP
, val
);
6016 POSTING_READ(D_COMP
);
6019 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6020 DRM_ERROR("D_COMP RCOMP still in progress\n");
6022 if (allow_power_down
) {
6023 val
= I915_READ(LCPLL_CTL
);
6024 val
|= LCPLL_POWER_DOWN_ALLOW
;
6025 I915_WRITE(LCPLL_CTL
, val
);
6026 POSTING_READ(LCPLL_CTL
);
6031 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6034 void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6038 val
= I915_READ(LCPLL_CTL
);
6040 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6041 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6044 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6045 * we'll hang the machine! */
6046 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6048 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6049 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6050 I915_WRITE(LCPLL_CTL
, val
);
6051 POSTING_READ(LCPLL_CTL
);
6054 val
= I915_READ(D_COMP
);
6055 val
|= D_COMP_COMP_FORCE
;
6056 val
&= ~D_COMP_COMP_DISABLE
;
6057 I915_WRITE(D_COMP
, val
);
6058 POSTING_READ(D_COMP
);
6060 val
= I915_READ(LCPLL_CTL
);
6061 val
&= ~LCPLL_PLL_DISABLE
;
6062 I915_WRITE(LCPLL_CTL
, val
);
6064 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6065 DRM_ERROR("LCPLL not locked yet\n");
6067 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6068 val
= I915_READ(LCPLL_CTL
);
6069 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6070 I915_WRITE(LCPLL_CTL
, val
);
6072 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6073 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6074 DRM_ERROR("Switching back to LCPLL failed\n");
6077 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6080 void hsw_enable_pc8_work(struct work_struct
*__work
)
6082 struct drm_i915_private
*dev_priv
=
6083 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6085 struct drm_device
*dev
= dev_priv
->dev
;
6088 if (dev_priv
->pc8
.enabled
)
6091 DRM_DEBUG_KMS("Enabling package C8+\n");
6093 dev_priv
->pc8
.enabled
= true;
6095 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6096 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6097 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6098 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6101 lpt_disable_clkout_dp(dev
);
6102 hsw_pc8_disable_interrupts(dev
);
6103 hsw_disable_lcpll(dev_priv
, true, true);
6106 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6108 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6109 WARN(dev_priv
->pc8
.disable_count
< 1,
6110 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6112 dev_priv
->pc8
.disable_count
--;
6113 if (dev_priv
->pc8
.disable_count
!= 0)
6116 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6117 msecs_to_jiffies(i915_pc8_timeout
));
6120 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6122 struct drm_device
*dev
= dev_priv
->dev
;
6125 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6126 WARN(dev_priv
->pc8
.disable_count
< 0,
6127 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6129 dev_priv
->pc8
.disable_count
++;
6130 if (dev_priv
->pc8
.disable_count
!= 1)
6133 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6134 if (!dev_priv
->pc8
.enabled
)
6137 DRM_DEBUG_KMS("Disabling package C8+\n");
6139 hsw_restore_lcpll(dev_priv
);
6140 hsw_pc8_restore_interrupts(dev
);
6141 lpt_init_pch_refclk(dev
);
6143 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6144 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6145 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6146 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6149 intel_prepare_ddi(dev
);
6150 i915_gem_init_swizzling(dev
);
6151 mutex_lock(&dev_priv
->rps
.hw_lock
);
6152 gen6_update_ring_freq(dev
);
6153 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6154 dev_priv
->pc8
.enabled
= false;
6157 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6159 mutex_lock(&dev_priv
->pc8
.lock
);
6160 __hsw_enable_package_c8(dev_priv
);
6161 mutex_unlock(&dev_priv
->pc8
.lock
);
6164 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6166 mutex_lock(&dev_priv
->pc8
.lock
);
6167 __hsw_disable_package_c8(dev_priv
);
6168 mutex_unlock(&dev_priv
->pc8
.lock
);
6171 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6173 struct drm_device
*dev
= dev_priv
->dev
;
6174 struct intel_crtc
*crtc
;
6177 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6178 if (crtc
->base
.enabled
)
6181 /* This case is still possible since we have the i915.disable_power_well
6182 * parameter and also the KVMr or something else might be requesting the
6184 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6186 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6193 /* Since we're called from modeset_global_resources there's no way to
6194 * symmetrically increase and decrease the refcount, so we use
6195 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6198 static void hsw_update_package_c8(struct drm_device
*dev
)
6200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6203 if (!i915_enable_pc8
)
6206 mutex_lock(&dev_priv
->pc8
.lock
);
6208 allow
= hsw_can_enable_package_c8(dev_priv
);
6210 if (allow
== dev_priv
->pc8
.requirements_met
)
6213 dev_priv
->pc8
.requirements_met
= allow
;
6216 __hsw_enable_package_c8(dev_priv
);
6218 __hsw_disable_package_c8(dev_priv
);
6221 mutex_unlock(&dev_priv
->pc8
.lock
);
6224 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6226 if (!dev_priv
->pc8
.gpu_idle
) {
6227 dev_priv
->pc8
.gpu_idle
= true;
6228 hsw_enable_package_c8(dev_priv
);
6232 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6234 if (dev_priv
->pc8
.gpu_idle
) {
6235 dev_priv
->pc8
.gpu_idle
= false;
6236 hsw_disable_package_c8(dev_priv
);
6240 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6242 bool enable
= false;
6243 struct intel_crtc
*crtc
;
6245 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6246 if (!crtc
->base
.enabled
)
6249 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.size
||
6250 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6254 intel_set_power_well(dev
, enable
);
6256 hsw_update_package_c8(dev
);
6259 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6261 struct drm_framebuffer
*fb
)
6263 struct drm_device
*dev
= crtc
->dev
;
6264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6265 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6266 int plane
= intel_crtc
->plane
;
6269 if (!intel_ddi_pll_mode_set(crtc
))
6272 /* Ensure that the cursor is valid for the new mode before changing... */
6273 intel_crtc_update_cursor(crtc
, true);
6275 if (intel_crtc
->config
.has_dp_encoder
)
6276 intel_dp_set_m_n(intel_crtc
);
6278 intel_crtc
->lowfreq_avail
= false;
6280 intel_set_pipe_timings(intel_crtc
);
6282 if (intel_crtc
->config
.has_pch_encoder
) {
6283 intel_cpu_transcoder_set_m_n(intel_crtc
,
6284 &intel_crtc
->config
.fdi_m_n
);
6287 haswell_set_pipeconf(crtc
);
6289 intel_set_pipe_csc(crtc
);
6291 /* Set up the display plane register */
6292 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6293 POSTING_READ(DSPCNTR(plane
));
6295 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6300 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6301 struct intel_crtc_config
*pipe_config
)
6303 struct drm_device
*dev
= crtc
->base
.dev
;
6304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6305 enum intel_display_power_domain pfit_domain
;
6308 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6309 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6311 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6312 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6313 enum pipe trans_edp_pipe
;
6314 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6316 WARN(1, "unknown pipe linked to edp transcoder\n");
6317 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6318 case TRANS_DDI_EDP_INPUT_A_ON
:
6319 trans_edp_pipe
= PIPE_A
;
6321 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6322 trans_edp_pipe
= PIPE_B
;
6324 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6325 trans_edp_pipe
= PIPE_C
;
6329 if (trans_edp_pipe
== crtc
->pipe
)
6330 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6333 if (!intel_display_power_enabled(dev
,
6334 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6337 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6338 if (!(tmp
& PIPECONF_ENABLE
))
6342 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6343 * DDI E. So just check whether this pipe is wired to DDI E and whether
6344 * the PCH transcoder is on.
6346 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6347 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6348 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6349 pipe_config
->has_pch_encoder
= true;
6351 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6352 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6353 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6355 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6358 intel_get_pipe_timings(crtc
, pipe_config
);
6360 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6361 if (intel_display_power_enabled(dev
, pfit_domain
))
6362 ironlake_get_pfit_config(crtc
, pipe_config
);
6364 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6365 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6367 pipe_config
->pixel_multiplier
= 1;
6372 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6374 struct drm_framebuffer
*fb
)
6376 struct drm_device
*dev
= crtc
->dev
;
6377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6378 struct intel_encoder
*encoder
;
6379 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6380 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6381 int pipe
= intel_crtc
->pipe
;
6384 drm_vblank_pre_modeset(dev
, pipe
);
6386 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6388 drm_vblank_post_modeset(dev
, pipe
);
6393 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6394 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6395 encoder
->base
.base
.id
,
6396 drm_get_encoder_name(&encoder
->base
),
6397 mode
->base
.id
, mode
->name
);
6398 encoder
->mode_set(encoder
);
6404 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6405 int reg_eldv
, uint32_t bits_eldv
,
6406 int reg_elda
, uint32_t bits_elda
,
6409 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6410 uint8_t *eld
= connector
->eld
;
6413 i
= I915_READ(reg_eldv
);
6422 i
= I915_READ(reg_elda
);
6424 I915_WRITE(reg_elda
, i
);
6426 for (i
= 0; i
< eld
[2]; i
++)
6427 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6433 static void g4x_write_eld(struct drm_connector
*connector
,
6434 struct drm_crtc
*crtc
)
6436 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6437 uint8_t *eld
= connector
->eld
;
6442 i
= I915_READ(G4X_AUD_VID_DID
);
6444 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6445 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6447 eldv
= G4X_ELDV_DEVCTG
;
6449 if (intel_eld_uptodate(connector
,
6450 G4X_AUD_CNTL_ST
, eldv
,
6451 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6452 G4X_HDMIW_HDMIEDID
))
6455 i
= I915_READ(G4X_AUD_CNTL_ST
);
6456 i
&= ~(eldv
| G4X_ELD_ADDR
);
6457 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6458 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6463 len
= min_t(uint8_t, eld
[2], len
);
6464 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6465 for (i
= 0; i
< len
; i
++)
6466 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6468 i
= I915_READ(G4X_AUD_CNTL_ST
);
6470 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6473 static void haswell_write_eld(struct drm_connector
*connector
,
6474 struct drm_crtc
*crtc
)
6476 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6477 uint8_t *eld
= connector
->eld
;
6478 struct drm_device
*dev
= crtc
->dev
;
6479 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6483 int pipe
= to_intel_crtc(crtc
)->pipe
;
6486 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6487 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6488 int aud_config
= HSW_AUD_CFG(pipe
);
6489 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6492 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6494 /* Audio output enable */
6495 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6496 tmp
= I915_READ(aud_cntrl_st2
);
6497 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6498 I915_WRITE(aud_cntrl_st2
, tmp
);
6500 /* Wait for 1 vertical blank */
6501 intel_wait_for_vblank(dev
, pipe
);
6503 /* Set ELD valid state */
6504 tmp
= I915_READ(aud_cntrl_st2
);
6505 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6506 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6507 I915_WRITE(aud_cntrl_st2
, tmp
);
6508 tmp
= I915_READ(aud_cntrl_st2
);
6509 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6511 /* Enable HDMI mode */
6512 tmp
= I915_READ(aud_config
);
6513 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6514 /* clear N_programing_enable and N_value_index */
6515 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6516 I915_WRITE(aud_config
, tmp
);
6518 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6520 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6521 intel_crtc
->eld_vld
= true;
6523 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6524 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6525 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6526 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6528 I915_WRITE(aud_config
, 0);
6530 if (intel_eld_uptodate(connector
,
6531 aud_cntrl_st2
, eldv
,
6532 aud_cntl_st
, IBX_ELD_ADDRESS
,
6536 i
= I915_READ(aud_cntrl_st2
);
6538 I915_WRITE(aud_cntrl_st2
, i
);
6543 i
= I915_READ(aud_cntl_st
);
6544 i
&= ~IBX_ELD_ADDRESS
;
6545 I915_WRITE(aud_cntl_st
, i
);
6546 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6547 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6549 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6550 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6551 for (i
= 0; i
< len
; i
++)
6552 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6554 i
= I915_READ(aud_cntrl_st2
);
6556 I915_WRITE(aud_cntrl_st2
, i
);
6560 static void ironlake_write_eld(struct drm_connector
*connector
,
6561 struct drm_crtc
*crtc
)
6563 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6564 uint8_t *eld
= connector
->eld
;
6572 int pipe
= to_intel_crtc(crtc
)->pipe
;
6574 if (HAS_PCH_IBX(connector
->dev
)) {
6575 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6576 aud_config
= IBX_AUD_CFG(pipe
);
6577 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6578 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6580 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6581 aud_config
= CPT_AUD_CFG(pipe
);
6582 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6583 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6586 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6588 i
= I915_READ(aud_cntl_st
);
6589 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6591 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6592 /* operate blindly on all ports */
6593 eldv
= IBX_ELD_VALIDB
;
6594 eldv
|= IBX_ELD_VALIDB
<< 4;
6595 eldv
|= IBX_ELD_VALIDB
<< 8;
6597 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6598 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6601 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6602 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6603 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6604 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6606 I915_WRITE(aud_config
, 0);
6608 if (intel_eld_uptodate(connector
,
6609 aud_cntrl_st2
, eldv
,
6610 aud_cntl_st
, IBX_ELD_ADDRESS
,
6614 i
= I915_READ(aud_cntrl_st2
);
6616 I915_WRITE(aud_cntrl_st2
, i
);
6621 i
= I915_READ(aud_cntl_st
);
6622 i
&= ~IBX_ELD_ADDRESS
;
6623 I915_WRITE(aud_cntl_st
, i
);
6625 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6626 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6627 for (i
= 0; i
< len
; i
++)
6628 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6630 i
= I915_READ(aud_cntrl_st2
);
6632 I915_WRITE(aud_cntrl_st2
, i
);
6635 void intel_write_eld(struct drm_encoder
*encoder
,
6636 struct drm_display_mode
*mode
)
6638 struct drm_crtc
*crtc
= encoder
->crtc
;
6639 struct drm_connector
*connector
;
6640 struct drm_device
*dev
= encoder
->dev
;
6641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6643 connector
= drm_select_eld(encoder
, mode
);
6647 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6649 drm_get_connector_name(connector
),
6650 connector
->encoder
->base
.id
,
6651 drm_get_encoder_name(connector
->encoder
));
6653 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6655 if (dev_priv
->display
.write_eld
)
6656 dev_priv
->display
.write_eld(connector
, crtc
);
6659 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6660 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6662 struct drm_device
*dev
= crtc
->dev
;
6663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6664 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6665 enum pipe pipe
= intel_crtc
->pipe
;
6666 int palreg
= PALETTE(pipe
);
6668 bool reenable_ips
= false;
6670 /* The clocks have to be on to load the palette. */
6671 if (!crtc
->enabled
|| !intel_crtc
->active
)
6674 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
6675 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
6676 assert_dsi_pll_enabled(dev_priv
);
6678 assert_pll_enabled(dev_priv
, pipe
);
6681 /* use legacy palette for Ironlake */
6682 if (HAS_PCH_SPLIT(dev
))
6683 palreg
= LGC_PALETTE(pipe
);
6685 /* Workaround : Do not read or write the pipe palette/gamma data while
6686 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6688 if (intel_crtc
->config
.ips_enabled
&&
6689 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
6690 GAMMA_MODE_MODE_SPLIT
)) {
6691 hsw_disable_ips(intel_crtc
);
6692 reenable_ips
= true;
6695 for (i
= 0; i
< 256; i
++) {
6696 I915_WRITE(palreg
+ 4 * i
,
6697 (intel_crtc
->lut_r
[i
] << 16) |
6698 (intel_crtc
->lut_g
[i
] << 8) |
6699 intel_crtc
->lut_b
[i
]);
6703 hsw_enable_ips(intel_crtc
);
6706 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6708 struct drm_device
*dev
= crtc
->dev
;
6709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6710 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6711 bool visible
= base
!= 0;
6714 if (intel_crtc
->cursor_visible
== visible
)
6717 cntl
= I915_READ(_CURACNTR
);
6719 /* On these chipsets we can only modify the base whilst
6720 * the cursor is disabled.
6722 I915_WRITE(_CURABASE
, base
);
6724 cntl
&= ~(CURSOR_FORMAT_MASK
);
6725 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6726 cntl
|= CURSOR_ENABLE
|
6727 CURSOR_GAMMA_ENABLE
|
6730 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6731 I915_WRITE(_CURACNTR
, cntl
);
6733 intel_crtc
->cursor_visible
= visible
;
6736 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6738 struct drm_device
*dev
= crtc
->dev
;
6739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6740 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6741 int pipe
= intel_crtc
->pipe
;
6742 bool visible
= base
!= 0;
6744 if (intel_crtc
->cursor_visible
!= visible
) {
6745 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6747 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6748 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6749 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6751 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6752 cntl
|= CURSOR_MODE_DISABLE
;
6754 I915_WRITE(CURCNTR(pipe
), cntl
);
6756 intel_crtc
->cursor_visible
= visible
;
6758 /* and commit changes on next vblank */
6759 I915_WRITE(CURBASE(pipe
), base
);
6762 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6764 struct drm_device
*dev
= crtc
->dev
;
6765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6766 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6767 int pipe
= intel_crtc
->pipe
;
6768 bool visible
= base
!= 0;
6770 if (intel_crtc
->cursor_visible
!= visible
) {
6771 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6773 cntl
&= ~CURSOR_MODE
;
6774 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6776 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6777 cntl
|= CURSOR_MODE_DISABLE
;
6779 if (IS_HASWELL(dev
)) {
6780 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6781 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
6783 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6785 intel_crtc
->cursor_visible
= visible
;
6787 /* and commit changes on next vblank */
6788 I915_WRITE(CURBASE_IVB(pipe
), base
);
6791 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6792 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6795 struct drm_device
*dev
= crtc
->dev
;
6796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6797 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6798 int pipe
= intel_crtc
->pipe
;
6799 int x
= intel_crtc
->cursor_x
;
6800 int y
= intel_crtc
->cursor_y
;
6806 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6807 base
= intel_crtc
->cursor_addr
;
6808 if (x
> (int) crtc
->fb
->width
)
6811 if (y
> (int) crtc
->fb
->height
)
6817 if (x
+ intel_crtc
->cursor_width
< 0)
6820 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6823 pos
|= x
<< CURSOR_X_SHIFT
;
6826 if (y
+ intel_crtc
->cursor_height
< 0)
6829 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6832 pos
|= y
<< CURSOR_Y_SHIFT
;
6834 visible
= base
!= 0;
6835 if (!visible
&& !intel_crtc
->cursor_visible
)
6838 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6839 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6840 ivb_update_cursor(crtc
, base
);
6842 I915_WRITE(CURPOS(pipe
), pos
);
6843 if (IS_845G(dev
) || IS_I865G(dev
))
6844 i845_update_cursor(crtc
, base
);
6846 i9xx_update_cursor(crtc
, base
);
6850 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6851 struct drm_file
*file
,
6853 uint32_t width
, uint32_t height
)
6855 struct drm_device
*dev
= crtc
->dev
;
6856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6858 struct drm_i915_gem_object
*obj
;
6862 /* if we want to turn off the cursor ignore width and height */
6864 DRM_DEBUG_KMS("cursor off\n");
6867 mutex_lock(&dev
->struct_mutex
);
6871 /* Currently we only support 64x64 cursors */
6872 if (width
!= 64 || height
!= 64) {
6873 DRM_ERROR("we currently only support 64x64 cursors\n");
6877 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6878 if (&obj
->base
== NULL
)
6881 if (obj
->base
.size
< width
* height
* 4) {
6882 DRM_ERROR("buffer is to small\n");
6887 /* we only need to pin inside GTT if cursor is non-phy */
6888 mutex_lock(&dev
->struct_mutex
);
6889 if (!dev_priv
->info
->cursor_needs_physical
) {
6892 if (obj
->tiling_mode
) {
6893 DRM_ERROR("cursor cannot be tiled\n");
6898 /* Note that the w/a also requires 2 PTE of padding following
6899 * the bo. We currently fill all unused PTE with the shadow
6900 * page and so we should always have valid PTE following the
6901 * cursor preventing the VT-d warning.
6904 if (need_vtd_wa(dev
))
6905 alignment
= 64*1024;
6907 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6909 DRM_ERROR("failed to move cursor bo into the GTT\n");
6913 ret
= i915_gem_object_put_fence(obj
);
6915 DRM_ERROR("failed to release fence for cursor");
6919 addr
= i915_gem_obj_ggtt_offset(obj
);
6921 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6922 ret
= i915_gem_attach_phys_object(dev
, obj
,
6923 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6926 DRM_ERROR("failed to attach phys object\n");
6929 addr
= obj
->phys_obj
->handle
->busaddr
;
6933 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6936 if (intel_crtc
->cursor_bo
) {
6937 if (dev_priv
->info
->cursor_needs_physical
) {
6938 if (intel_crtc
->cursor_bo
!= obj
)
6939 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6941 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
6942 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6945 mutex_unlock(&dev
->struct_mutex
);
6947 intel_crtc
->cursor_addr
= addr
;
6948 intel_crtc
->cursor_bo
= obj
;
6949 intel_crtc
->cursor_width
= width
;
6950 intel_crtc
->cursor_height
= height
;
6952 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6956 i915_gem_object_unpin_from_display_plane(obj
);
6958 mutex_unlock(&dev
->struct_mutex
);
6960 drm_gem_object_unreference_unlocked(&obj
->base
);
6964 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6966 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6968 intel_crtc
->cursor_x
= x
;
6969 intel_crtc
->cursor_y
= y
;
6971 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6976 /** Sets the color ramps on behalf of RandR */
6977 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6978 u16 blue
, int regno
)
6980 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6982 intel_crtc
->lut_r
[regno
] = red
>> 8;
6983 intel_crtc
->lut_g
[regno
] = green
>> 8;
6984 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6987 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6988 u16
*blue
, int regno
)
6990 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6992 *red
= intel_crtc
->lut_r
[regno
] << 8;
6993 *green
= intel_crtc
->lut_g
[regno
] << 8;
6994 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6997 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6998 u16
*blue
, uint32_t start
, uint32_t size
)
7000 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7001 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7003 for (i
= start
; i
< end
; i
++) {
7004 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7005 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7006 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7009 intel_crtc_load_lut(crtc
);
7012 /* VESA 640x480x72Hz mode to set on the pipe */
7013 static struct drm_display_mode load_detect_mode
= {
7014 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7015 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7018 static struct drm_framebuffer
*
7019 intel_framebuffer_create(struct drm_device
*dev
,
7020 struct drm_mode_fb_cmd2
*mode_cmd
,
7021 struct drm_i915_gem_object
*obj
)
7023 struct intel_framebuffer
*intel_fb
;
7026 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7028 drm_gem_object_unreference_unlocked(&obj
->base
);
7029 return ERR_PTR(-ENOMEM
);
7032 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7034 drm_gem_object_unreference_unlocked(&obj
->base
);
7036 return ERR_PTR(ret
);
7039 return &intel_fb
->base
;
7043 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7045 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7046 return ALIGN(pitch
, 64);
7050 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7052 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7053 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7056 static struct drm_framebuffer
*
7057 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7058 struct drm_display_mode
*mode
,
7061 struct drm_i915_gem_object
*obj
;
7062 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7064 obj
= i915_gem_alloc_object(dev
,
7065 intel_framebuffer_size_for_mode(mode
, bpp
));
7067 return ERR_PTR(-ENOMEM
);
7069 mode_cmd
.width
= mode
->hdisplay
;
7070 mode_cmd
.height
= mode
->vdisplay
;
7071 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7073 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7075 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7078 static struct drm_framebuffer
*
7079 mode_fits_in_fbdev(struct drm_device
*dev
,
7080 struct drm_display_mode
*mode
)
7082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7083 struct drm_i915_gem_object
*obj
;
7084 struct drm_framebuffer
*fb
;
7086 if (dev_priv
->fbdev
== NULL
)
7089 obj
= dev_priv
->fbdev
->ifb
.obj
;
7093 fb
= &dev_priv
->fbdev
->ifb
.base
;
7094 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7095 fb
->bits_per_pixel
))
7098 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7104 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7105 struct drm_display_mode
*mode
,
7106 struct intel_load_detect_pipe
*old
)
7108 struct intel_crtc
*intel_crtc
;
7109 struct intel_encoder
*intel_encoder
=
7110 intel_attached_encoder(connector
);
7111 struct drm_crtc
*possible_crtc
;
7112 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7113 struct drm_crtc
*crtc
= NULL
;
7114 struct drm_device
*dev
= encoder
->dev
;
7115 struct drm_framebuffer
*fb
;
7118 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7119 connector
->base
.id
, drm_get_connector_name(connector
),
7120 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7123 * Algorithm gets a little messy:
7125 * - if the connector already has an assigned crtc, use it (but make
7126 * sure it's on first)
7128 * - try to find the first unused crtc that can drive this connector,
7129 * and use that if we find one
7132 /* See if we already have a CRTC for this connector */
7133 if (encoder
->crtc
) {
7134 crtc
= encoder
->crtc
;
7136 mutex_lock(&crtc
->mutex
);
7138 old
->dpms_mode
= connector
->dpms
;
7139 old
->load_detect_temp
= false;
7141 /* Make sure the crtc and connector are running */
7142 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7143 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7148 /* Find an unused one (if possible) */
7149 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7151 if (!(encoder
->possible_crtcs
& (1 << i
)))
7153 if (!possible_crtc
->enabled
) {
7154 crtc
= possible_crtc
;
7160 * If we didn't find an unused CRTC, don't use any.
7163 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7167 mutex_lock(&crtc
->mutex
);
7168 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7169 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7171 intel_crtc
= to_intel_crtc(crtc
);
7172 old
->dpms_mode
= connector
->dpms
;
7173 old
->load_detect_temp
= true;
7174 old
->release_fb
= NULL
;
7177 mode
= &load_detect_mode
;
7179 /* We need a framebuffer large enough to accommodate all accesses
7180 * that the plane may generate whilst we perform load detection.
7181 * We can not rely on the fbcon either being present (we get called
7182 * during its initialisation to detect all boot displays, or it may
7183 * not even exist) or that it is large enough to satisfy the
7186 fb
= mode_fits_in_fbdev(dev
, mode
);
7188 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7189 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7190 old
->release_fb
= fb
;
7192 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7194 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7195 mutex_unlock(&crtc
->mutex
);
7199 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7200 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7201 if (old
->release_fb
)
7202 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7203 mutex_unlock(&crtc
->mutex
);
7207 /* let the connector get through one full cycle before testing */
7208 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7212 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7213 struct intel_load_detect_pipe
*old
)
7215 struct intel_encoder
*intel_encoder
=
7216 intel_attached_encoder(connector
);
7217 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7218 struct drm_crtc
*crtc
= encoder
->crtc
;
7220 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7221 connector
->base
.id
, drm_get_connector_name(connector
),
7222 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7224 if (old
->load_detect_temp
) {
7225 to_intel_connector(connector
)->new_encoder
= NULL
;
7226 intel_encoder
->new_crtc
= NULL
;
7227 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7229 if (old
->release_fb
) {
7230 drm_framebuffer_unregister_private(old
->release_fb
);
7231 drm_framebuffer_unreference(old
->release_fb
);
7234 mutex_unlock(&crtc
->mutex
);
7238 /* Switch crtc and encoder back off if necessary */
7239 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7240 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7242 mutex_unlock(&crtc
->mutex
);
7245 /* Returns the clock of the currently programmed mode of the given pipe. */
7246 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7247 struct intel_crtc_config
*pipe_config
)
7249 struct drm_device
*dev
= crtc
->base
.dev
;
7250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7251 int pipe
= pipe_config
->cpu_transcoder
;
7252 u32 dpll
= I915_READ(DPLL(pipe
));
7254 intel_clock_t clock
;
7256 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7257 fp
= I915_READ(FP0(pipe
));
7259 fp
= I915_READ(FP1(pipe
));
7261 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7262 if (IS_PINEVIEW(dev
)) {
7263 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7264 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7266 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7267 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7270 if (!IS_GEN2(dev
)) {
7271 if (IS_PINEVIEW(dev
))
7272 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7273 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7275 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7276 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7278 switch (dpll
& DPLL_MODE_MASK
) {
7279 case DPLLB_MODE_DAC_SERIAL
:
7280 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7283 case DPLLB_MODE_LVDS
:
7284 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7288 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7289 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7290 pipe_config
->adjusted_mode
.clock
= 0;
7294 if (IS_PINEVIEW(dev
))
7295 pineview_clock(96000, &clock
);
7297 i9xx_clock(96000, &clock
);
7299 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7302 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7303 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7306 if ((dpll
& PLL_REF_INPUT_MASK
) ==
7307 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
7308 /* XXX: might not be 66MHz */
7309 i9xx_clock(66000, &clock
);
7311 i9xx_clock(48000, &clock
);
7313 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7316 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7317 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7319 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7324 i9xx_clock(48000, &clock
);
7328 pipe_config
->adjusted_mode
.clock
= clock
.dot
;
7331 static void ironlake_crtc_clock_get(struct intel_crtc
*crtc
,
7332 struct intel_crtc_config
*pipe_config
)
7334 struct drm_device
*dev
= crtc
->base
.dev
;
7335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7336 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7337 int link_freq
, repeat
;
7341 repeat
= pipe_config
->pixel_multiplier
;
7344 * The calculation for the data clock is:
7345 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7346 * But we want to avoid losing precison if possible, so:
7347 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7349 * and the link clock is simpler:
7350 * link_clock = (m * link_clock * repeat) / n
7354 * We need to get the FDI or DP link clock here to derive
7357 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7358 * For DP, it's either 1.62GHz or 2.7GHz.
7359 * We do our calculations in 10*MHz since we don't need much precison.
7361 if (pipe_config
->has_pch_encoder
)
7362 link_freq
= intel_fdi_link_freq(dev
) * 10000;
7364 link_freq
= pipe_config
->port_clock
;
7366 link_m
= I915_READ(PIPE_LINK_M1(cpu_transcoder
));
7367 link_n
= I915_READ(PIPE_LINK_N1(cpu_transcoder
));
7369 if (!link_m
|| !link_n
)
7372 clock
= ((u64
)link_m
* (u64
)link_freq
* (u64
)repeat
);
7373 do_div(clock
, link_n
);
7375 pipe_config
->adjusted_mode
.clock
= clock
;
7378 /** Returns the currently programmed mode of the given pipe. */
7379 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7380 struct drm_crtc
*crtc
)
7382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7383 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7384 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7385 struct drm_display_mode
*mode
;
7386 struct intel_crtc_config pipe_config
;
7387 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7388 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7389 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7390 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7392 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7397 * Construct a pipe_config sufficient for getting the clock info
7398 * back out of crtc_clock_get.
7400 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7401 * to use a real value here instead.
7403 pipe_config
.cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
7404 pipe_config
.pixel_multiplier
= 1;
7405 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7407 mode
->clock
= pipe_config
.adjusted_mode
.clock
;
7408 mode
->hdisplay
= (htot
& 0xffff) + 1;
7409 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7410 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7411 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7412 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7413 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7414 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7415 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7417 drm_mode_set_name(mode
);
7422 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7424 struct drm_device
*dev
= crtc
->dev
;
7425 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7427 int pipe
= intel_crtc
->pipe
;
7428 int dpll_reg
= DPLL(pipe
);
7431 if (HAS_PCH_SPLIT(dev
))
7434 if (!dev_priv
->lvds_downclock_avail
)
7437 dpll
= I915_READ(dpll_reg
);
7438 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7439 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7441 assert_panel_unlocked(dev_priv
, pipe
);
7443 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7444 I915_WRITE(dpll_reg
, dpll
);
7445 intel_wait_for_vblank(dev
, pipe
);
7447 dpll
= I915_READ(dpll_reg
);
7448 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7449 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7453 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7455 struct drm_device
*dev
= crtc
->dev
;
7456 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7457 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7459 if (HAS_PCH_SPLIT(dev
))
7462 if (!dev_priv
->lvds_downclock_avail
)
7466 * Since this is called by a timer, we should never get here in
7469 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7470 int pipe
= intel_crtc
->pipe
;
7471 int dpll_reg
= DPLL(pipe
);
7474 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7476 assert_panel_unlocked(dev_priv
, pipe
);
7478 dpll
= I915_READ(dpll_reg
);
7479 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7480 I915_WRITE(dpll_reg
, dpll
);
7481 intel_wait_for_vblank(dev
, pipe
);
7482 dpll
= I915_READ(dpll_reg
);
7483 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7484 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7489 void intel_mark_busy(struct drm_device
*dev
)
7491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7493 hsw_package_c8_gpu_busy(dev_priv
);
7494 i915_update_gfx_val(dev_priv
);
7497 void intel_mark_idle(struct drm_device
*dev
)
7499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7500 struct drm_crtc
*crtc
;
7502 hsw_package_c8_gpu_idle(dev_priv
);
7504 if (!i915_powersave
)
7507 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7511 intel_decrease_pllclock(crtc
);
7515 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7516 struct intel_ring_buffer
*ring
)
7518 struct drm_device
*dev
= obj
->base
.dev
;
7519 struct drm_crtc
*crtc
;
7521 if (!i915_powersave
)
7524 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7528 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7531 intel_increase_pllclock(crtc
);
7532 if (ring
&& intel_fbc_enabled(dev
))
7533 ring
->fbc_dirty
= true;
7537 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7539 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7540 struct drm_device
*dev
= crtc
->dev
;
7541 struct intel_unpin_work
*work
;
7542 unsigned long flags
;
7544 spin_lock_irqsave(&dev
->event_lock
, flags
);
7545 work
= intel_crtc
->unpin_work
;
7546 intel_crtc
->unpin_work
= NULL
;
7547 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7550 cancel_work_sync(&work
->work
);
7554 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7556 drm_crtc_cleanup(crtc
);
7561 static void intel_unpin_work_fn(struct work_struct
*__work
)
7563 struct intel_unpin_work
*work
=
7564 container_of(__work
, struct intel_unpin_work
, work
);
7565 struct drm_device
*dev
= work
->crtc
->dev
;
7567 mutex_lock(&dev
->struct_mutex
);
7568 intel_unpin_fb_obj(work
->old_fb_obj
);
7569 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7570 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7572 intel_update_fbc(dev
);
7573 mutex_unlock(&dev
->struct_mutex
);
7575 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7576 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7581 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7582 struct drm_crtc
*crtc
)
7584 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7585 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7586 struct intel_unpin_work
*work
;
7587 unsigned long flags
;
7589 /* Ignore early vblank irqs */
7590 if (intel_crtc
== NULL
)
7593 spin_lock_irqsave(&dev
->event_lock
, flags
);
7594 work
= intel_crtc
->unpin_work
;
7596 /* Ensure we don't miss a work->pending update ... */
7599 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7600 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7604 /* and that the unpin work is consistent wrt ->pending. */
7607 intel_crtc
->unpin_work
= NULL
;
7610 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7612 drm_vblank_put(dev
, intel_crtc
->pipe
);
7614 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7616 wake_up_all(&dev_priv
->pending_flip_queue
);
7618 queue_work(dev_priv
->wq
, &work
->work
);
7620 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7623 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7625 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7626 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7628 do_intel_finish_page_flip(dev
, crtc
);
7631 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7633 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7634 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7636 do_intel_finish_page_flip(dev
, crtc
);
7639 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7641 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7642 struct intel_crtc
*intel_crtc
=
7643 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7644 unsigned long flags
;
7646 /* NB: An MMIO update of the plane base pointer will also
7647 * generate a page-flip completion irq, i.e. every modeset
7648 * is also accompanied by a spurious intel_prepare_page_flip().
7650 spin_lock_irqsave(&dev
->event_lock
, flags
);
7651 if (intel_crtc
->unpin_work
)
7652 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7653 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7656 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7658 /* Ensure that the work item is consistent when activating it ... */
7660 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7661 /* and that it is marked active as soon as the irq could fire. */
7665 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7666 struct drm_crtc
*crtc
,
7667 struct drm_framebuffer
*fb
,
7668 struct drm_i915_gem_object
*obj
,
7671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7674 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7677 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7681 ret
= intel_ring_begin(ring
, 6);
7685 /* Can't queue multiple flips, so wait for the previous
7686 * one to finish before executing the next.
7688 if (intel_crtc
->plane
)
7689 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7691 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7692 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7693 intel_ring_emit(ring
, MI_NOOP
);
7694 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7695 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7696 intel_ring_emit(ring
, fb
->pitches
[0]);
7697 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7698 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7700 intel_mark_page_flip_active(intel_crtc
);
7701 __intel_ring_advance(ring
);
7705 intel_unpin_fb_obj(obj
);
7710 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7711 struct drm_crtc
*crtc
,
7712 struct drm_framebuffer
*fb
,
7713 struct drm_i915_gem_object
*obj
,
7716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7717 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7719 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7722 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7726 ret
= intel_ring_begin(ring
, 6);
7730 if (intel_crtc
->plane
)
7731 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7733 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7734 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7735 intel_ring_emit(ring
, MI_NOOP
);
7736 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7737 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7738 intel_ring_emit(ring
, fb
->pitches
[0]);
7739 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7740 intel_ring_emit(ring
, MI_NOOP
);
7742 intel_mark_page_flip_active(intel_crtc
);
7743 __intel_ring_advance(ring
);
7747 intel_unpin_fb_obj(obj
);
7752 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7753 struct drm_crtc
*crtc
,
7754 struct drm_framebuffer
*fb
,
7755 struct drm_i915_gem_object
*obj
,
7758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7759 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7760 uint32_t pf
, pipesrc
;
7761 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7764 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7768 ret
= intel_ring_begin(ring
, 4);
7772 /* i965+ uses the linear or tiled offsets from the
7773 * Display Registers (which do not change across a page-flip)
7774 * so we need only reprogram the base address.
7776 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7777 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7778 intel_ring_emit(ring
, fb
->pitches
[0]);
7779 intel_ring_emit(ring
,
7780 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
7783 /* XXX Enabling the panel-fitter across page-flip is so far
7784 * untested on non-native modes, so ignore it for now.
7785 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7788 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7789 intel_ring_emit(ring
, pf
| pipesrc
);
7791 intel_mark_page_flip_active(intel_crtc
);
7792 __intel_ring_advance(ring
);
7796 intel_unpin_fb_obj(obj
);
7801 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7802 struct drm_crtc
*crtc
,
7803 struct drm_framebuffer
*fb
,
7804 struct drm_i915_gem_object
*obj
,
7807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7808 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7809 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7810 uint32_t pf
, pipesrc
;
7813 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7817 ret
= intel_ring_begin(ring
, 4);
7821 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7822 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7823 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7824 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7826 /* Contrary to the suggestions in the documentation,
7827 * "Enable Panel Fitter" does not seem to be required when page
7828 * flipping with a non-native mode, and worse causes a normal
7830 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7833 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7834 intel_ring_emit(ring
, pf
| pipesrc
);
7836 intel_mark_page_flip_active(intel_crtc
);
7837 __intel_ring_advance(ring
);
7841 intel_unpin_fb_obj(obj
);
7846 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7847 struct drm_crtc
*crtc
,
7848 struct drm_framebuffer
*fb
,
7849 struct drm_i915_gem_object
*obj
,
7852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7854 struct intel_ring_buffer
*ring
;
7855 uint32_t plane_bit
= 0;
7859 if (ring
== NULL
|| ring
->id
!= RCS
)
7860 ring
= &dev_priv
->ring
[BCS
];
7862 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7866 switch(intel_crtc
->plane
) {
7868 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7871 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7874 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7877 WARN_ONCE(1, "unknown plane in flip command\n");
7883 if (ring
->id
== RCS
)
7886 ret
= intel_ring_begin(ring
, len
);
7890 /* Unmask the flip-done completion message. Note that the bspec says that
7891 * we should do this for both the BCS and RCS, and that we must not unmask
7892 * more than one flip event at any time (or ensure that one flip message
7893 * can be sent by waiting for flip-done prior to queueing new flips).
7894 * Experimentation says that BCS works despite DERRMR masking all
7895 * flip-done completion events and that unmasking all planes at once
7896 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7897 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7899 if (ring
->id
== RCS
) {
7900 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
7901 intel_ring_emit(ring
, DERRMR
);
7902 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
7903 DERRMR_PIPEB_PRI_FLIP_DONE
|
7904 DERRMR_PIPEC_PRI_FLIP_DONE
));
7905 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
7906 intel_ring_emit(ring
, DERRMR
);
7907 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
7910 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7911 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7912 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7913 intel_ring_emit(ring
, (MI_NOOP
));
7915 intel_mark_page_flip_active(intel_crtc
);
7916 __intel_ring_advance(ring
);
7920 intel_unpin_fb_obj(obj
);
7925 static int intel_default_queue_flip(struct drm_device
*dev
,
7926 struct drm_crtc
*crtc
,
7927 struct drm_framebuffer
*fb
,
7928 struct drm_i915_gem_object
*obj
,
7934 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7935 struct drm_framebuffer
*fb
,
7936 struct drm_pending_vblank_event
*event
,
7937 uint32_t page_flip_flags
)
7939 struct drm_device
*dev
= crtc
->dev
;
7940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7941 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7942 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7944 struct intel_unpin_work
*work
;
7945 unsigned long flags
;
7948 /* Can't change pixel format via MI display flips. */
7949 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7953 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7954 * Note that pitch changes could also affect these register.
7956 if (INTEL_INFO(dev
)->gen
> 3 &&
7957 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7958 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7961 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7965 work
->event
= event
;
7967 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7968 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7970 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7974 /* We borrow the event spin lock for protecting unpin_work */
7975 spin_lock_irqsave(&dev
->event_lock
, flags
);
7976 if (intel_crtc
->unpin_work
) {
7977 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7979 drm_vblank_put(dev
, intel_crtc
->pipe
);
7981 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7984 intel_crtc
->unpin_work
= work
;
7985 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7987 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7988 flush_workqueue(dev_priv
->wq
);
7990 ret
= i915_mutex_lock_interruptible(dev
);
7994 /* Reference the objects for the scheduled work. */
7995 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7996 drm_gem_object_reference(&obj
->base
);
8000 work
->pending_flip_obj
= obj
;
8002 work
->enable_stall_check
= true;
8004 atomic_inc(&intel_crtc
->unpin_work_count
);
8005 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8007 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8009 goto cleanup_pending
;
8011 intel_disable_fbc(dev
);
8012 intel_mark_fb_busy(obj
, NULL
);
8013 mutex_unlock(&dev
->struct_mutex
);
8015 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8020 atomic_dec(&intel_crtc
->unpin_work_count
);
8022 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8023 drm_gem_object_unreference(&obj
->base
);
8024 mutex_unlock(&dev
->struct_mutex
);
8027 spin_lock_irqsave(&dev
->event_lock
, flags
);
8028 intel_crtc
->unpin_work
= NULL
;
8029 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8031 drm_vblank_put(dev
, intel_crtc
->pipe
);
8038 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8039 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8040 .load_lut
= intel_crtc_load_lut
,
8043 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8044 struct drm_crtc
*crtc
)
8046 struct drm_device
*dev
;
8047 struct drm_crtc
*tmp
;
8050 WARN(!crtc
, "checking null crtc?\n");
8054 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8060 if (encoder
->possible_crtcs
& crtc_mask
)
8066 * intel_modeset_update_staged_output_state
8068 * Updates the staged output configuration state, e.g. after we've read out the
8071 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8073 struct intel_encoder
*encoder
;
8074 struct intel_connector
*connector
;
8076 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8078 connector
->new_encoder
=
8079 to_intel_encoder(connector
->base
.encoder
);
8082 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8085 to_intel_crtc(encoder
->base
.crtc
);
8090 * intel_modeset_commit_output_state
8092 * This function copies the stage display pipe configuration to the real one.
8094 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8096 struct intel_encoder
*encoder
;
8097 struct intel_connector
*connector
;
8099 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8101 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8104 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8106 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8111 connected_sink_compute_bpp(struct intel_connector
* connector
,
8112 struct intel_crtc_config
*pipe_config
)
8114 int bpp
= pipe_config
->pipe_bpp
;
8116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8117 connector
->base
.base
.id
,
8118 drm_get_connector_name(&connector
->base
));
8120 /* Don't use an invalid EDID bpc value */
8121 if (connector
->base
.display_info
.bpc
&&
8122 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8123 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8124 bpp
, connector
->base
.display_info
.bpc
*3);
8125 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8128 /* Clamp bpp to 8 on screens without EDID 1.4 */
8129 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8130 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8132 pipe_config
->pipe_bpp
= 24;
8137 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8138 struct drm_framebuffer
*fb
,
8139 struct intel_crtc_config
*pipe_config
)
8141 struct drm_device
*dev
= crtc
->base
.dev
;
8142 struct intel_connector
*connector
;
8145 switch (fb
->pixel_format
) {
8147 bpp
= 8*3; /* since we go through a colormap */
8149 case DRM_FORMAT_XRGB1555
:
8150 case DRM_FORMAT_ARGB1555
:
8151 /* checked in intel_framebuffer_init already */
8152 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8154 case DRM_FORMAT_RGB565
:
8155 bpp
= 6*3; /* min is 18bpp */
8157 case DRM_FORMAT_XBGR8888
:
8158 case DRM_FORMAT_ABGR8888
:
8159 /* checked in intel_framebuffer_init already */
8160 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8162 case DRM_FORMAT_XRGB8888
:
8163 case DRM_FORMAT_ARGB8888
:
8166 case DRM_FORMAT_XRGB2101010
:
8167 case DRM_FORMAT_ARGB2101010
:
8168 case DRM_FORMAT_XBGR2101010
:
8169 case DRM_FORMAT_ABGR2101010
:
8170 /* checked in intel_framebuffer_init already */
8171 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8175 /* TODO: gen4+ supports 16 bpc floating point, too. */
8177 DRM_DEBUG_KMS("unsupported depth\n");
8181 pipe_config
->pipe_bpp
= bpp
;
8183 /* Clamp display bpp to EDID value */
8184 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8186 if (!connector
->new_encoder
||
8187 connector
->new_encoder
->new_crtc
!= crtc
)
8190 connected_sink_compute_bpp(connector
, pipe_config
);
8196 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8197 struct intel_crtc_config
*pipe_config
,
8198 const char *context
)
8200 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8201 context
, pipe_name(crtc
->pipe
));
8203 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8204 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8205 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8206 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8207 pipe_config
->has_pch_encoder
,
8208 pipe_config
->fdi_lanes
,
8209 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8210 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8211 pipe_config
->fdi_m_n
.tu
);
8212 DRM_DEBUG_KMS("requested mode:\n");
8213 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8214 DRM_DEBUG_KMS("adjusted mode:\n");
8215 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8216 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8217 pipe_config
->gmch_pfit
.control
,
8218 pipe_config
->gmch_pfit
.pgm_ratios
,
8219 pipe_config
->gmch_pfit
.lvds_border_bits
);
8220 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8221 pipe_config
->pch_pfit
.pos
,
8222 pipe_config
->pch_pfit
.size
);
8223 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8226 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8228 int num_encoders
= 0;
8229 bool uncloneable_encoders
= false;
8230 struct intel_encoder
*encoder
;
8232 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8234 if (&encoder
->new_crtc
->base
!= crtc
)
8238 if (!encoder
->cloneable
)
8239 uncloneable_encoders
= true;
8242 return !(num_encoders
> 1 && uncloneable_encoders
);
8245 static struct intel_crtc_config
*
8246 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8247 struct drm_framebuffer
*fb
,
8248 struct drm_display_mode
*mode
)
8250 struct drm_device
*dev
= crtc
->dev
;
8251 struct intel_encoder
*encoder
;
8252 struct intel_crtc_config
*pipe_config
;
8253 int plane_bpp
, ret
= -EINVAL
;
8256 if (!check_encoder_cloning(crtc
)) {
8257 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8258 return ERR_PTR(-EINVAL
);
8261 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8263 return ERR_PTR(-ENOMEM
);
8265 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8266 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8267 pipe_config
->cpu_transcoder
=
8268 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8269 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8272 * Sanitize sync polarity flags based on requested ones. If neither
8273 * positive or negative polarity is requested, treat this as meaning
8274 * negative polarity.
8276 if (!(pipe_config
->adjusted_mode
.flags
&
8277 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8278 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8280 if (!(pipe_config
->adjusted_mode
.flags
&
8281 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8282 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8284 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8285 * plane pixel format and any sink constraints into account. Returns the
8286 * source plane bpp so that dithering can be selected on mismatches
8287 * after encoders and crtc also have had their say. */
8288 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8294 /* Ensure the port clock defaults are reset when retrying. */
8295 pipe_config
->port_clock
= 0;
8296 pipe_config
->pixel_multiplier
= 1;
8298 /* Fill in default crtc timings, allow encoders to overwrite them. */
8299 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, 0);
8301 /* Pass our mode to the connectors and the CRTC to give them a chance to
8302 * adjust it according to limitations or connector properties, and also
8303 * a chance to reject the mode entirely.
8305 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8308 if (&encoder
->new_crtc
->base
!= crtc
)
8311 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8312 DRM_DEBUG_KMS("Encoder config failure\n");
8317 /* Set default port clock if not overwritten by the encoder. Needs to be
8318 * done afterwards in case the encoder adjusts the mode. */
8319 if (!pipe_config
->port_clock
)
8320 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.clock
;
8322 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8324 DRM_DEBUG_KMS("CRTC fixup failed\n");
8329 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8334 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8339 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8340 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8341 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8346 return ERR_PTR(ret
);
8349 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8350 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8352 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8353 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8355 struct intel_crtc
*intel_crtc
;
8356 struct drm_device
*dev
= crtc
->dev
;
8357 struct intel_encoder
*encoder
;
8358 struct intel_connector
*connector
;
8359 struct drm_crtc
*tmp_crtc
;
8361 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8363 /* Check which crtcs have changed outputs connected to them, these need
8364 * to be part of the prepare_pipes mask. We don't (yet) support global
8365 * modeset across multiple crtcs, so modeset_pipes will only have one
8366 * bit set at most. */
8367 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8369 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8372 if (connector
->base
.encoder
) {
8373 tmp_crtc
= connector
->base
.encoder
->crtc
;
8375 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8378 if (connector
->new_encoder
)
8380 1 << connector
->new_encoder
->new_crtc
->pipe
;
8383 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8385 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8388 if (encoder
->base
.crtc
) {
8389 tmp_crtc
= encoder
->base
.crtc
;
8391 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8394 if (encoder
->new_crtc
)
8395 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8398 /* Check for any pipes that will be fully disabled ... */
8399 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8403 /* Don't try to disable disabled crtcs. */
8404 if (!intel_crtc
->base
.enabled
)
8407 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8409 if (encoder
->new_crtc
== intel_crtc
)
8414 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8418 /* set_mode is also used to update properties on life display pipes. */
8419 intel_crtc
= to_intel_crtc(crtc
);
8421 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8424 * For simplicity do a full modeset on any pipe where the output routing
8425 * changed. We could be more clever, but that would require us to be
8426 * more careful with calling the relevant encoder->mode_set functions.
8429 *modeset_pipes
= *prepare_pipes
;
8431 /* ... and mask these out. */
8432 *modeset_pipes
&= ~(*disable_pipes
);
8433 *prepare_pipes
&= ~(*disable_pipes
);
8436 * HACK: We don't (yet) fully support global modesets. intel_set_config
8437 * obies this rule, but the modeset restore mode of
8438 * intel_modeset_setup_hw_state does not.
8440 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8441 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8443 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8444 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8447 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8449 struct drm_encoder
*encoder
;
8450 struct drm_device
*dev
= crtc
->dev
;
8452 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8453 if (encoder
->crtc
== crtc
)
8460 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8462 struct intel_encoder
*intel_encoder
;
8463 struct intel_crtc
*intel_crtc
;
8464 struct drm_connector
*connector
;
8466 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8468 if (!intel_encoder
->base
.crtc
)
8471 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8473 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8474 intel_encoder
->connectors_active
= false;
8477 intel_modeset_commit_output_state(dev
);
8479 /* Update computed state. */
8480 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8482 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8485 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8486 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8489 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8491 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8492 struct drm_property
*dpms_property
=
8493 dev
->mode_config
.dpms_property
;
8495 connector
->dpms
= DRM_MODE_DPMS_ON
;
8496 drm_object_property_set_value(&connector
->base
,
8500 intel_encoder
= to_intel_encoder(connector
->encoder
);
8501 intel_encoder
->connectors_active
= true;
8507 static bool intel_fuzzy_clock_check(struct intel_crtc_config
*cur
,
8508 struct intel_crtc_config
*new)
8510 int clock1
, clock2
, diff
;
8512 clock1
= cur
->adjusted_mode
.clock
;
8513 clock2
= new->adjusted_mode
.clock
;
8515 if (clock1
== clock2
)
8518 if (!clock1
|| !clock2
)
8521 diff
= abs(clock1
- clock2
);
8523 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8529 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8530 list_for_each_entry((intel_crtc), \
8531 &(dev)->mode_config.crtc_list, \
8533 if (mask & (1 <<(intel_crtc)->pipe))
8536 intel_pipe_config_compare(struct drm_device
*dev
,
8537 struct intel_crtc_config
*current_config
,
8538 struct intel_crtc_config
*pipe_config
)
8540 #define PIPE_CONF_CHECK_X(name) \
8541 if (current_config->name != pipe_config->name) { \
8542 DRM_ERROR("mismatch in " #name " " \
8543 "(expected 0x%08x, found 0x%08x)\n", \
8544 current_config->name, \
8545 pipe_config->name); \
8549 #define PIPE_CONF_CHECK_I(name) \
8550 if (current_config->name != pipe_config->name) { \
8551 DRM_ERROR("mismatch in " #name " " \
8552 "(expected %i, found %i)\n", \
8553 current_config->name, \
8554 pipe_config->name); \
8558 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8559 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8560 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8561 "(expected %i, found %i)\n", \
8562 current_config->name & (mask), \
8563 pipe_config->name & (mask)); \
8567 #define PIPE_CONF_QUIRK(quirk) \
8568 ((current_config->quirks | pipe_config->quirks) & (quirk))
8570 PIPE_CONF_CHECK_I(cpu_transcoder
);
8572 PIPE_CONF_CHECK_I(has_pch_encoder
);
8573 PIPE_CONF_CHECK_I(fdi_lanes
);
8574 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8575 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8576 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8577 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8578 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8580 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8581 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8582 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8583 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8584 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8585 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8587 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8588 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8589 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8590 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8591 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8592 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8594 PIPE_CONF_CHECK_I(pixel_multiplier
);
8596 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8597 DRM_MODE_FLAG_INTERLACE
);
8599 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8600 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8601 DRM_MODE_FLAG_PHSYNC
);
8602 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8603 DRM_MODE_FLAG_NHSYNC
);
8604 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8605 DRM_MODE_FLAG_PVSYNC
);
8606 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8607 DRM_MODE_FLAG_NVSYNC
);
8610 PIPE_CONF_CHECK_I(requested_mode
.hdisplay
);
8611 PIPE_CONF_CHECK_I(requested_mode
.vdisplay
);
8613 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8614 /* pfit ratios are autocomputed by the hw on gen4+ */
8615 if (INTEL_INFO(dev
)->gen
< 4)
8616 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8617 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8618 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8619 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8621 PIPE_CONF_CHECK_I(ips_enabled
);
8623 PIPE_CONF_CHECK_I(shared_dpll
);
8624 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8625 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8626 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8627 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8629 #undef PIPE_CONF_CHECK_X
8630 #undef PIPE_CONF_CHECK_I
8631 #undef PIPE_CONF_CHECK_FLAGS
8632 #undef PIPE_CONF_QUIRK
8634 if (!IS_HASWELL(dev
)) {
8635 if (!intel_fuzzy_clock_check(current_config
, pipe_config
)) {
8636 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8637 current_config
->adjusted_mode
.clock
,
8638 pipe_config
->adjusted_mode
.clock
);
8647 check_connector_state(struct drm_device
*dev
)
8649 struct intel_connector
*connector
;
8651 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8653 /* This also checks the encoder/connector hw state with the
8654 * ->get_hw_state callbacks. */
8655 intel_connector_check_state(connector
);
8657 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8658 "connector's staged encoder doesn't match current encoder\n");
8663 check_encoder_state(struct drm_device
*dev
)
8665 struct intel_encoder
*encoder
;
8666 struct intel_connector
*connector
;
8668 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8670 bool enabled
= false;
8671 bool active
= false;
8672 enum pipe pipe
, tracked_pipe
;
8674 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8675 encoder
->base
.base
.id
,
8676 drm_get_encoder_name(&encoder
->base
));
8678 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8679 "encoder's stage crtc doesn't match current crtc\n");
8680 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8681 "encoder's active_connectors set, but no crtc\n");
8683 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8685 if (connector
->base
.encoder
!= &encoder
->base
)
8688 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8691 WARN(!!encoder
->base
.crtc
!= enabled
,
8692 "encoder's enabled state mismatch "
8693 "(expected %i, found %i)\n",
8694 !!encoder
->base
.crtc
, enabled
);
8695 WARN(active
&& !encoder
->base
.crtc
,
8696 "active encoder with no crtc\n");
8698 WARN(encoder
->connectors_active
!= active
,
8699 "encoder's computed active state doesn't match tracked active state "
8700 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8702 active
= encoder
->get_hw_state(encoder
, &pipe
);
8703 WARN(active
!= encoder
->connectors_active
,
8704 "encoder's hw state doesn't match sw tracking "
8705 "(expected %i, found %i)\n",
8706 encoder
->connectors_active
, active
);
8708 if (!encoder
->base
.crtc
)
8711 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8712 WARN(active
&& pipe
!= tracked_pipe
,
8713 "active encoder's pipe doesn't match"
8714 "(expected %i, found %i)\n",
8715 tracked_pipe
, pipe
);
8721 check_crtc_state(struct drm_device
*dev
)
8723 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8724 struct intel_crtc
*crtc
;
8725 struct intel_encoder
*encoder
;
8726 struct intel_crtc_config pipe_config
;
8728 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8730 bool enabled
= false;
8731 bool active
= false;
8733 memset(&pipe_config
, 0, sizeof(pipe_config
));
8735 DRM_DEBUG_KMS("[CRTC:%d]\n",
8736 crtc
->base
.base
.id
);
8738 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8739 "active crtc, but not enabled in sw tracking\n");
8741 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8743 if (encoder
->base
.crtc
!= &crtc
->base
)
8746 if (encoder
->connectors_active
)
8750 WARN(active
!= crtc
->active
,
8751 "crtc's computed active state doesn't match tracked active state "
8752 "(expected %i, found %i)\n", active
, crtc
->active
);
8753 WARN(enabled
!= crtc
->base
.enabled
,
8754 "crtc's computed enabled state doesn't match tracked enabled state "
8755 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8757 active
= dev_priv
->display
.get_pipe_config(crtc
,
8760 /* hw state is inconsistent with the pipe A quirk */
8761 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8762 active
= crtc
->active
;
8764 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8767 if (encoder
->base
.crtc
!= &crtc
->base
)
8769 if (encoder
->get_config
&&
8770 encoder
->get_hw_state(encoder
, &pipe
))
8771 encoder
->get_config(encoder
, &pipe_config
);
8774 if (dev_priv
->display
.get_clock
)
8775 dev_priv
->display
.get_clock(crtc
, &pipe_config
);
8777 WARN(crtc
->active
!= active
,
8778 "crtc active state doesn't match with hw state "
8779 "(expected %i, found %i)\n", crtc
->active
, active
);
8782 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8783 WARN(1, "pipe state doesn't match!\n");
8784 intel_dump_pipe_config(crtc
, &pipe_config
,
8786 intel_dump_pipe_config(crtc
, &crtc
->config
,
8793 check_shared_dpll_state(struct drm_device
*dev
)
8795 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8796 struct intel_crtc
*crtc
;
8797 struct intel_dpll_hw_state dpll_hw_state
;
8800 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8801 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8802 int enabled_crtcs
= 0, active_crtcs
= 0;
8805 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8807 DRM_DEBUG_KMS("%s\n", pll
->name
);
8809 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
8811 WARN(pll
->active
> pll
->refcount
,
8812 "more active pll users than references: %i vs %i\n",
8813 pll
->active
, pll
->refcount
);
8814 WARN(pll
->active
&& !pll
->on
,
8815 "pll in active use but not on in sw tracking\n");
8816 WARN(pll
->on
&& !pll
->active
,
8817 "pll in on but not on in use in sw tracking\n");
8818 WARN(pll
->on
!= active
,
8819 "pll on state mismatch (expected %i, found %i)\n",
8822 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8824 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8826 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8829 WARN(pll
->active
!= active_crtcs
,
8830 "pll active crtcs mismatch (expected %i, found %i)\n",
8831 pll
->active
, active_crtcs
);
8832 WARN(pll
->refcount
!= enabled_crtcs
,
8833 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8834 pll
->refcount
, enabled_crtcs
);
8836 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
8837 sizeof(dpll_hw_state
)),
8838 "pll hw state mismatch\n");
8843 intel_modeset_check_state(struct drm_device
*dev
)
8845 check_connector_state(dev
);
8846 check_encoder_state(dev
);
8847 check_crtc_state(dev
);
8848 check_shared_dpll_state(dev
);
8851 static int __intel_set_mode(struct drm_crtc
*crtc
,
8852 struct drm_display_mode
*mode
,
8853 int x
, int y
, struct drm_framebuffer
*fb
)
8855 struct drm_device
*dev
= crtc
->dev
;
8856 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8857 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
8858 struct intel_crtc_config
*pipe_config
= NULL
;
8859 struct intel_crtc
*intel_crtc
;
8860 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
8863 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
8866 saved_hwmode
= saved_mode
+ 1;
8868 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
8869 &prepare_pipes
, &disable_pipes
);
8871 *saved_hwmode
= crtc
->hwmode
;
8872 *saved_mode
= crtc
->mode
;
8874 /* Hack: Because we don't (yet) support global modeset on multiple
8875 * crtcs, we don't keep track of the new mode for more than one crtc.
8876 * Hence simply check whether any bit is set in modeset_pipes in all the
8877 * pieces of code that are not yet converted to deal with mutliple crtcs
8878 * changing their mode at the same time. */
8879 if (modeset_pipes
) {
8880 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
8881 if (IS_ERR(pipe_config
)) {
8882 ret
= PTR_ERR(pipe_config
);
8887 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
8891 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
8892 intel_crtc_disable(&intel_crtc
->base
);
8894 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
8895 if (intel_crtc
->base
.enabled
)
8896 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
8899 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8900 * to set it here already despite that we pass it down the callchain.
8902 if (modeset_pipes
) {
8904 /* mode_set/enable/disable functions rely on a correct pipe
8906 to_intel_crtc(crtc
)->config
= *pipe_config
;
8909 /* Only after disabling all output pipelines that will be changed can we
8910 * update the the output configuration. */
8911 intel_modeset_update_state(dev
, prepare_pipes
);
8913 if (dev_priv
->display
.modeset_global_resources
)
8914 dev_priv
->display
.modeset_global_resources(dev
);
8916 /* Set up the DPLL and any encoders state that needs to adjust or depend
8919 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8920 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8926 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8927 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8928 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8930 if (modeset_pipes
) {
8931 /* Store real post-adjustment hardware mode. */
8932 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8934 /* Calculate and store various constants which
8935 * are later needed by vblank and swap-completion
8936 * timestamping. They are derived from true hwmode.
8938 drm_calc_timestamping_constants(crtc
);
8941 /* FIXME: add subpixel order */
8943 if (ret
&& crtc
->enabled
) {
8944 crtc
->hwmode
= *saved_hwmode
;
8945 crtc
->mode
= *saved_mode
;
8954 static int intel_set_mode(struct drm_crtc
*crtc
,
8955 struct drm_display_mode
*mode
,
8956 int x
, int y
, struct drm_framebuffer
*fb
)
8960 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8963 intel_modeset_check_state(crtc
->dev
);
8968 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8970 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8973 #undef for_each_intel_crtc_masked
8975 static void intel_set_config_free(struct intel_set_config
*config
)
8980 kfree(config
->save_connector_encoders
);
8981 kfree(config
->save_encoder_crtcs
);
8985 static int intel_set_config_save_state(struct drm_device
*dev
,
8986 struct intel_set_config
*config
)
8988 struct drm_encoder
*encoder
;
8989 struct drm_connector
*connector
;
8992 config
->save_encoder_crtcs
=
8993 kcalloc(dev
->mode_config
.num_encoder
,
8994 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8995 if (!config
->save_encoder_crtcs
)
8998 config
->save_connector_encoders
=
8999 kcalloc(dev
->mode_config
.num_connector
,
9000 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9001 if (!config
->save_connector_encoders
)
9004 /* Copy data. Note that driver private data is not affected.
9005 * Should anything bad happen only the expected state is
9006 * restored, not the drivers personal bookkeeping.
9009 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9010 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9014 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9015 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9021 static void intel_set_config_restore_state(struct drm_device
*dev
,
9022 struct intel_set_config
*config
)
9024 struct intel_encoder
*encoder
;
9025 struct intel_connector
*connector
;
9029 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9031 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9035 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9036 connector
->new_encoder
=
9037 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9042 is_crtc_connector_off(struct drm_mode_set
*set
)
9046 if (set
->num_connectors
== 0)
9049 if (WARN_ON(set
->connectors
== NULL
))
9052 for (i
= 0; i
< set
->num_connectors
; i
++)
9053 if (set
->connectors
[i
]->encoder
&&
9054 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9055 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9062 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9063 struct intel_set_config
*config
)
9066 /* We should be able to check here if the fb has the same properties
9067 * and then just flip_or_move it */
9068 if (is_crtc_connector_off(set
)) {
9069 config
->mode_changed
= true;
9070 } else if (set
->crtc
->fb
!= set
->fb
) {
9071 /* If we have no fb then treat it as a full mode set */
9072 if (set
->crtc
->fb
== NULL
) {
9073 struct intel_crtc
*intel_crtc
=
9074 to_intel_crtc(set
->crtc
);
9076 if (intel_crtc
->active
&& i915_fastboot
) {
9077 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9078 config
->fb_changed
= true;
9080 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9081 config
->mode_changed
= true;
9083 } else if (set
->fb
== NULL
) {
9084 config
->mode_changed
= true;
9085 } else if (set
->fb
->pixel_format
!=
9086 set
->crtc
->fb
->pixel_format
) {
9087 config
->mode_changed
= true;
9089 config
->fb_changed
= true;
9093 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9094 config
->fb_changed
= true;
9096 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9097 DRM_DEBUG_KMS("modes are different, full mode set\n");
9098 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9099 drm_mode_debug_printmodeline(set
->mode
);
9100 config
->mode_changed
= true;
9103 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9104 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9108 intel_modeset_stage_output_state(struct drm_device
*dev
,
9109 struct drm_mode_set
*set
,
9110 struct intel_set_config
*config
)
9112 struct drm_crtc
*new_crtc
;
9113 struct intel_connector
*connector
;
9114 struct intel_encoder
*encoder
;
9117 /* The upper layers ensure that we either disable a crtc or have a list
9118 * of connectors. For paranoia, double-check this. */
9119 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9120 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9122 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9124 /* Otherwise traverse passed in connector list and get encoders
9126 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9127 if (set
->connectors
[ro
] == &connector
->base
) {
9128 connector
->new_encoder
= connector
->encoder
;
9133 /* If we disable the crtc, disable all its connectors. Also, if
9134 * the connector is on the changing crtc but not on the new
9135 * connector list, disable it. */
9136 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9137 connector
->base
.encoder
&&
9138 connector
->base
.encoder
->crtc
== set
->crtc
) {
9139 connector
->new_encoder
= NULL
;
9141 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9142 connector
->base
.base
.id
,
9143 drm_get_connector_name(&connector
->base
));
9147 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9148 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9149 config
->mode_changed
= true;
9152 /* connector->new_encoder is now updated for all connectors. */
9154 /* Update crtc of enabled connectors. */
9155 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9157 if (!connector
->new_encoder
)
9160 new_crtc
= connector
->new_encoder
->base
.crtc
;
9162 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9163 if (set
->connectors
[ro
] == &connector
->base
)
9164 new_crtc
= set
->crtc
;
9167 /* Make sure the new CRTC will work with the encoder */
9168 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9172 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9174 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9175 connector
->base
.base
.id
,
9176 drm_get_connector_name(&connector
->base
),
9180 /* Check for any encoders that needs to be disabled. */
9181 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9183 list_for_each_entry(connector
,
9184 &dev
->mode_config
.connector_list
,
9186 if (connector
->new_encoder
== encoder
) {
9187 WARN_ON(!connector
->new_encoder
->new_crtc
);
9192 encoder
->new_crtc
= NULL
;
9194 /* Only now check for crtc changes so we don't miss encoders
9195 * that will be disabled. */
9196 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9197 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9198 config
->mode_changed
= true;
9201 /* Now we've also updated encoder->new_crtc for all encoders. */
9206 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9208 struct drm_device
*dev
;
9209 struct drm_mode_set save_set
;
9210 struct intel_set_config
*config
;
9215 BUG_ON(!set
->crtc
->helper_private
);
9217 /* Enforce sane interface api - has been abused by the fb helper. */
9218 BUG_ON(!set
->mode
&& set
->fb
);
9219 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9222 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9223 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9224 (int)set
->num_connectors
, set
->x
, set
->y
);
9226 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9229 dev
= set
->crtc
->dev
;
9232 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9236 ret
= intel_set_config_save_state(dev
, config
);
9240 save_set
.crtc
= set
->crtc
;
9241 save_set
.mode
= &set
->crtc
->mode
;
9242 save_set
.x
= set
->crtc
->x
;
9243 save_set
.y
= set
->crtc
->y
;
9244 save_set
.fb
= set
->crtc
->fb
;
9246 /* Compute whether we need a full modeset, only an fb base update or no
9247 * change at all. In the future we might also check whether only the
9248 * mode changed, e.g. for LVDS where we only change the panel fitter in
9250 intel_set_config_compute_mode_changes(set
, config
);
9252 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9256 if (config
->mode_changed
) {
9257 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9258 set
->x
, set
->y
, set
->fb
);
9259 } else if (config
->fb_changed
) {
9260 intel_crtc_wait_for_pending_flips(set
->crtc
);
9262 ret
= intel_pipe_set_base(set
->crtc
,
9263 set
->x
, set
->y
, set
->fb
);
9267 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9268 set
->crtc
->base
.id
, ret
);
9270 intel_set_config_restore_state(dev
, config
);
9272 /* Try to restore the config */
9273 if (config
->mode_changed
&&
9274 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9275 save_set
.x
, save_set
.y
, save_set
.fb
))
9276 DRM_ERROR("failed to restore config after modeset failure\n");
9280 intel_set_config_free(config
);
9284 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9285 .cursor_set
= intel_crtc_cursor_set
,
9286 .cursor_move
= intel_crtc_cursor_move
,
9287 .gamma_set
= intel_crtc_gamma_set
,
9288 .set_config
= intel_crtc_set_config
,
9289 .destroy
= intel_crtc_destroy
,
9290 .page_flip
= intel_crtc_page_flip
,
9293 static void intel_cpu_pll_init(struct drm_device
*dev
)
9296 intel_ddi_pll_init(dev
);
9299 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9300 struct intel_shared_dpll
*pll
,
9301 struct intel_dpll_hw_state
*hw_state
)
9305 val
= I915_READ(PCH_DPLL(pll
->id
));
9306 hw_state
->dpll
= val
;
9307 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9308 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9310 return val
& DPLL_VCO_ENABLE
;
9313 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9314 struct intel_shared_dpll
*pll
)
9316 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9317 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9320 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9321 struct intel_shared_dpll
*pll
)
9323 /* PCH refclock must be enabled first */
9324 assert_pch_refclk_enabled(dev_priv
);
9326 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9328 /* Wait for the clocks to stabilize. */
9329 POSTING_READ(PCH_DPLL(pll
->id
));
9332 /* The pixel multiplier can only be updated once the
9333 * DPLL is enabled and the clocks are stable.
9335 * So write it again.
9337 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9338 POSTING_READ(PCH_DPLL(pll
->id
));
9342 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9343 struct intel_shared_dpll
*pll
)
9345 struct drm_device
*dev
= dev_priv
->dev
;
9346 struct intel_crtc
*crtc
;
9348 /* Make sure no transcoder isn't still depending on us. */
9349 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9350 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9351 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9354 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9355 POSTING_READ(PCH_DPLL(pll
->id
));
9359 static char *ibx_pch_dpll_names
[] = {
9364 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9369 dev_priv
->num_shared_dpll
= 2;
9371 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9372 dev_priv
->shared_dplls
[i
].id
= i
;
9373 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9374 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9375 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9376 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9377 dev_priv
->shared_dplls
[i
].get_hw_state
=
9378 ibx_pch_dpll_get_hw_state
;
9382 static void intel_shared_dpll_init(struct drm_device
*dev
)
9384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9386 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9387 ibx_pch_dpll_init(dev
);
9389 dev_priv
->num_shared_dpll
= 0;
9391 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9392 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9393 dev_priv
->num_shared_dpll
);
9396 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9398 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9399 struct intel_crtc
*intel_crtc
;
9402 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
9403 if (intel_crtc
== NULL
)
9406 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9408 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9409 for (i
= 0; i
< 256; i
++) {
9410 intel_crtc
->lut_r
[i
] = i
;
9411 intel_crtc
->lut_g
[i
] = i
;
9412 intel_crtc
->lut_b
[i
] = i
;
9415 /* Swap pipes & planes for FBC on pre-965 */
9416 intel_crtc
->pipe
= pipe
;
9417 intel_crtc
->plane
= pipe
;
9418 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9419 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9420 intel_crtc
->plane
= !pipe
;
9423 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9424 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9425 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9426 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9428 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9431 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9432 struct drm_file
*file
)
9434 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9435 struct drm_mode_object
*drmmode_obj
;
9436 struct intel_crtc
*crtc
;
9438 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9441 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9442 DRM_MODE_OBJECT_CRTC
);
9445 DRM_ERROR("no such CRTC id\n");
9449 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9450 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9455 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9457 struct drm_device
*dev
= encoder
->base
.dev
;
9458 struct intel_encoder
*source_encoder
;
9462 list_for_each_entry(source_encoder
,
9463 &dev
->mode_config
.encoder_list
, base
.head
) {
9465 if (encoder
== source_encoder
)
9466 index_mask
|= (1 << entry
);
9468 /* Intel hw has only one MUX where enocoders could be cloned. */
9469 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9470 index_mask
|= (1 << entry
);
9478 static bool has_edp_a(struct drm_device
*dev
)
9480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9482 if (!IS_MOBILE(dev
))
9485 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9489 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9495 static void intel_setup_outputs(struct drm_device
*dev
)
9497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9498 struct intel_encoder
*encoder
;
9499 bool dpd_is_edp
= false;
9501 intel_lvds_init(dev
);
9504 intel_crt_init(dev
);
9509 /* Haswell uses DDI functions to detect digital outputs */
9510 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9511 /* DDI A only supports eDP */
9513 intel_ddi_init(dev
, PORT_A
);
9515 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9517 found
= I915_READ(SFUSE_STRAP
);
9519 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9520 intel_ddi_init(dev
, PORT_B
);
9521 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9522 intel_ddi_init(dev
, PORT_C
);
9523 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9524 intel_ddi_init(dev
, PORT_D
);
9525 } else if (HAS_PCH_SPLIT(dev
)) {
9527 dpd_is_edp
= intel_dpd_is_edp(dev
);
9530 intel_dp_init(dev
, DP_A
, PORT_A
);
9532 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9533 /* PCH SDVOB multiplex with HDMIB */
9534 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9536 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9537 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9538 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9541 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9542 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9544 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9545 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9547 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9548 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9550 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9551 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9552 } else if (IS_VALLEYVIEW(dev
)) {
9553 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9554 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9555 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9557 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9558 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9562 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9563 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9565 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9566 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9569 intel_dsi_init(dev
);
9570 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9573 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9574 DRM_DEBUG_KMS("probing SDVOB\n");
9575 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9576 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9577 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9578 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9581 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9582 intel_dp_init(dev
, DP_B
, PORT_B
);
9585 /* Before G4X SDVOC doesn't have its own detect register */
9587 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9588 DRM_DEBUG_KMS("probing SDVOC\n");
9589 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9592 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9594 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9595 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9596 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9598 if (SUPPORTS_INTEGRATED_DP(dev
))
9599 intel_dp_init(dev
, DP_C
, PORT_C
);
9602 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9603 (I915_READ(DP_D
) & DP_DETECTED
))
9604 intel_dp_init(dev
, DP_D
, PORT_D
);
9605 } else if (IS_GEN2(dev
))
9606 intel_dvo_init(dev
);
9608 if (SUPPORTS_TV(dev
))
9611 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9612 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9613 encoder
->base
.possible_clones
=
9614 intel_encoder_clones(encoder
);
9617 intel_init_pch_refclk(dev
);
9619 drm_helper_move_panel_connectors_to_head(dev
);
9622 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9624 drm_framebuffer_cleanup(&fb
->base
);
9625 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9628 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9630 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9632 intel_framebuffer_fini(intel_fb
);
9636 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9637 struct drm_file
*file
,
9638 unsigned int *handle
)
9640 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9641 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9643 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9646 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9647 .destroy
= intel_user_framebuffer_destroy
,
9648 .create_handle
= intel_user_framebuffer_create_handle
,
9651 int intel_framebuffer_init(struct drm_device
*dev
,
9652 struct intel_framebuffer
*intel_fb
,
9653 struct drm_mode_fb_cmd2
*mode_cmd
,
9654 struct drm_i915_gem_object
*obj
)
9659 if (obj
->tiling_mode
== I915_TILING_Y
) {
9660 DRM_DEBUG("hardware does not support tiling Y\n");
9664 if (mode_cmd
->pitches
[0] & 63) {
9665 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9666 mode_cmd
->pitches
[0]);
9670 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9671 pitch_limit
= 32*1024;
9672 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9673 if (obj
->tiling_mode
)
9674 pitch_limit
= 16*1024;
9676 pitch_limit
= 32*1024;
9677 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9678 if (obj
->tiling_mode
)
9679 pitch_limit
= 8*1024;
9681 pitch_limit
= 16*1024;
9683 /* XXX DSPC is limited to 4k tiled */
9684 pitch_limit
= 8*1024;
9686 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9687 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9688 obj
->tiling_mode
? "tiled" : "linear",
9689 mode_cmd
->pitches
[0], pitch_limit
);
9693 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9694 mode_cmd
->pitches
[0] != obj
->stride
) {
9695 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9696 mode_cmd
->pitches
[0], obj
->stride
);
9700 /* Reject formats not supported by any plane early. */
9701 switch (mode_cmd
->pixel_format
) {
9703 case DRM_FORMAT_RGB565
:
9704 case DRM_FORMAT_XRGB8888
:
9705 case DRM_FORMAT_ARGB8888
:
9707 case DRM_FORMAT_XRGB1555
:
9708 case DRM_FORMAT_ARGB1555
:
9709 if (INTEL_INFO(dev
)->gen
> 3) {
9710 DRM_DEBUG("unsupported pixel format: %s\n",
9711 drm_get_format_name(mode_cmd
->pixel_format
));
9715 case DRM_FORMAT_XBGR8888
:
9716 case DRM_FORMAT_ABGR8888
:
9717 case DRM_FORMAT_XRGB2101010
:
9718 case DRM_FORMAT_ARGB2101010
:
9719 case DRM_FORMAT_XBGR2101010
:
9720 case DRM_FORMAT_ABGR2101010
:
9721 if (INTEL_INFO(dev
)->gen
< 4) {
9722 DRM_DEBUG("unsupported pixel format: %s\n",
9723 drm_get_format_name(mode_cmd
->pixel_format
));
9727 case DRM_FORMAT_YUYV
:
9728 case DRM_FORMAT_UYVY
:
9729 case DRM_FORMAT_YVYU
:
9730 case DRM_FORMAT_VYUY
:
9731 if (INTEL_INFO(dev
)->gen
< 5) {
9732 DRM_DEBUG("unsupported pixel format: %s\n",
9733 drm_get_format_name(mode_cmd
->pixel_format
));
9738 DRM_DEBUG("unsupported pixel format: %s\n",
9739 drm_get_format_name(mode_cmd
->pixel_format
));
9743 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9744 if (mode_cmd
->offsets
[0] != 0)
9747 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9748 intel_fb
->obj
= obj
;
9750 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9752 DRM_ERROR("framebuffer init failed %d\n", ret
);
9759 static struct drm_framebuffer
*
9760 intel_user_framebuffer_create(struct drm_device
*dev
,
9761 struct drm_file
*filp
,
9762 struct drm_mode_fb_cmd2
*mode_cmd
)
9764 struct drm_i915_gem_object
*obj
;
9766 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9767 mode_cmd
->handles
[0]));
9768 if (&obj
->base
== NULL
)
9769 return ERR_PTR(-ENOENT
);
9771 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9774 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9775 .fb_create
= intel_user_framebuffer_create
,
9776 .output_poll_changed
= intel_fb_output_poll_changed
,
9779 /* Set up chip specific display functions */
9780 static void intel_init_display(struct drm_device
*dev
)
9782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9784 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9785 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9786 else if (IS_VALLEYVIEW(dev
))
9787 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9788 else if (IS_PINEVIEW(dev
))
9789 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9791 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9794 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9795 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9796 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9797 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9798 dev_priv
->display
.off
= haswell_crtc_off
;
9799 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9800 } else if (HAS_PCH_SPLIT(dev
)) {
9801 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
9802 dev_priv
->display
.get_clock
= ironlake_crtc_clock_get
;
9803 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9804 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
9805 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
9806 dev_priv
->display
.off
= ironlake_crtc_off
;
9807 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9808 } else if (IS_VALLEYVIEW(dev
)) {
9809 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9810 dev_priv
->display
.get_clock
= i9xx_crtc_clock_get
;
9811 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9812 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
9813 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9814 dev_priv
->display
.off
= i9xx_crtc_off
;
9815 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9817 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9818 dev_priv
->display
.get_clock
= i9xx_crtc_clock_get
;
9819 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9820 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
9821 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9822 dev_priv
->display
.off
= i9xx_crtc_off
;
9823 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9826 /* Returns the core display clock speed */
9827 if (IS_VALLEYVIEW(dev
))
9828 dev_priv
->display
.get_display_clock_speed
=
9829 valleyview_get_display_clock_speed
;
9830 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9831 dev_priv
->display
.get_display_clock_speed
=
9832 i945_get_display_clock_speed
;
9833 else if (IS_I915G(dev
))
9834 dev_priv
->display
.get_display_clock_speed
=
9835 i915_get_display_clock_speed
;
9836 else if (IS_I945GM(dev
) || IS_845G(dev
))
9837 dev_priv
->display
.get_display_clock_speed
=
9838 i9xx_misc_get_display_clock_speed
;
9839 else if (IS_PINEVIEW(dev
))
9840 dev_priv
->display
.get_display_clock_speed
=
9841 pnv_get_display_clock_speed
;
9842 else if (IS_I915GM(dev
))
9843 dev_priv
->display
.get_display_clock_speed
=
9844 i915gm_get_display_clock_speed
;
9845 else if (IS_I865G(dev
))
9846 dev_priv
->display
.get_display_clock_speed
=
9847 i865_get_display_clock_speed
;
9848 else if (IS_I85X(dev
))
9849 dev_priv
->display
.get_display_clock_speed
=
9850 i855_get_display_clock_speed
;
9852 dev_priv
->display
.get_display_clock_speed
=
9853 i830_get_display_clock_speed
;
9855 if (HAS_PCH_SPLIT(dev
)) {
9857 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
9858 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9859 } else if (IS_GEN6(dev
)) {
9860 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
9861 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9862 } else if (IS_IVYBRIDGE(dev
)) {
9863 /* FIXME: detect B0+ stepping and use auto training */
9864 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
9865 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9866 dev_priv
->display
.modeset_global_resources
=
9867 ivb_modeset_global_resources
;
9868 } else if (IS_HASWELL(dev
)) {
9869 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
9870 dev_priv
->display
.write_eld
= haswell_write_eld
;
9871 dev_priv
->display
.modeset_global_resources
=
9872 haswell_modeset_global_resources
;
9874 } else if (IS_G4X(dev
)) {
9875 dev_priv
->display
.write_eld
= g4x_write_eld
;
9878 /* Default just returns -ENODEV to indicate unsupported */
9879 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
9881 switch (INTEL_INFO(dev
)->gen
) {
9883 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
9887 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
9892 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
9896 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
9899 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
9905 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9906 * resume, or other times. This quirk makes sure that's the case for
9909 static void quirk_pipea_force(struct drm_device
*dev
)
9911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9913 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
9914 DRM_INFO("applying pipe a force quirk\n");
9918 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9920 static void quirk_ssc_force_disable(struct drm_device
*dev
)
9922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9923 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9924 DRM_INFO("applying lvds SSC disable quirk\n");
9928 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9931 static void quirk_invert_brightness(struct drm_device
*dev
)
9933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9934 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
9935 DRM_INFO("applying inverted panel brightness quirk\n");
9939 * Some machines (Dell XPS13) suffer broken backlight controls if
9940 * BLM_PCH_PWM_ENABLE is set.
9942 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
9944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9945 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
9946 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9949 struct intel_quirk
{
9951 int subsystem_vendor
;
9952 int subsystem_device
;
9953 void (*hook
)(struct drm_device
*dev
);
9956 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9957 struct intel_dmi_quirk
{
9958 void (*hook
)(struct drm_device
*dev
);
9959 const struct dmi_system_id (*dmi_id_list
)[];
9962 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
9964 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
9968 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
9970 .dmi_id_list
= &(const struct dmi_system_id
[]) {
9972 .callback
= intel_dmi_reverse_brightness
,
9973 .ident
= "NCR Corporation",
9974 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
9975 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
9978 { } /* terminating entry */
9980 .hook
= quirk_invert_brightness
,
9984 static struct intel_quirk intel_quirks
[] = {
9985 /* HP Mini needs pipe A force quirk (LP: #322104) */
9986 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9988 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9989 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9991 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9992 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9994 /* 830/845 need to leave pipe A & dpll A up */
9995 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9996 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9998 /* Lenovo U160 cannot use SSC on LVDS */
9999 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10001 /* Sony Vaio Y cannot use SSC on LVDS */
10002 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10004 /* Acer Aspire 5734Z must invert backlight brightness */
10005 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
10007 /* Acer/eMachines G725 */
10008 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
10010 /* Acer/eMachines e725 */
10011 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
10013 /* Acer/Packard Bell NCL20 */
10014 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
10016 /* Acer Aspire 4736Z */
10017 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
10019 /* Dell XPS13 HD Sandy Bridge */
10020 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10021 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10022 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10025 static void intel_init_quirks(struct drm_device
*dev
)
10027 struct pci_dev
*d
= dev
->pdev
;
10030 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10031 struct intel_quirk
*q
= &intel_quirks
[i
];
10033 if (d
->device
== q
->device
&&
10034 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10035 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10036 (d
->subsystem_device
== q
->subsystem_device
||
10037 q
->subsystem_device
== PCI_ANY_ID
))
10040 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10041 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10042 intel_dmi_quirks
[i
].hook(dev
);
10046 /* Disable the VGA plane that we never use */
10047 static void i915_disable_vga(struct drm_device
*dev
)
10049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10051 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10053 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10054 outb(SR01
, VGA_SR_INDEX
);
10055 sr1
= inb(VGA_SR_DATA
);
10056 outb(sr1
| 1<<5, VGA_SR_DATA
);
10058 /* Disable VGA memory on Intel HD */
10059 if (HAS_PCH_SPLIT(dev
)) {
10060 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10061 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10062 VGA_RSRC_NORMAL_IO
|
10063 VGA_RSRC_NORMAL_MEM
);
10066 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10069 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10070 POSTING_READ(vga_reg
);
10073 static void i915_enable_vga(struct drm_device
*dev
)
10075 /* Enable VGA memory on Intel HD */
10076 if (HAS_PCH_SPLIT(dev
)) {
10077 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10078 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10079 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10080 VGA_RSRC_LEGACY_MEM
|
10081 VGA_RSRC_NORMAL_IO
|
10082 VGA_RSRC_NORMAL_MEM
);
10083 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10087 void intel_modeset_init_hw(struct drm_device
*dev
)
10089 intel_init_power_well(dev
);
10091 intel_prepare_ddi(dev
);
10093 intel_init_clock_gating(dev
);
10095 mutex_lock(&dev
->struct_mutex
);
10096 intel_enable_gt_powersave(dev
);
10097 mutex_unlock(&dev
->struct_mutex
);
10100 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10102 intel_suspend_hw(dev
);
10105 void intel_modeset_init(struct drm_device
*dev
)
10107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10110 drm_mode_config_init(dev
);
10112 dev
->mode_config
.min_width
= 0;
10113 dev
->mode_config
.min_height
= 0;
10115 dev
->mode_config
.preferred_depth
= 24;
10116 dev
->mode_config
.prefer_shadow
= 1;
10118 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10120 intel_init_quirks(dev
);
10122 intel_init_pm(dev
);
10124 if (INTEL_INFO(dev
)->num_pipes
== 0)
10127 intel_init_display(dev
);
10129 if (IS_GEN2(dev
)) {
10130 dev
->mode_config
.max_width
= 2048;
10131 dev
->mode_config
.max_height
= 2048;
10132 } else if (IS_GEN3(dev
)) {
10133 dev
->mode_config
.max_width
= 4096;
10134 dev
->mode_config
.max_height
= 4096;
10136 dev
->mode_config
.max_width
= 8192;
10137 dev
->mode_config
.max_height
= 8192;
10139 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10141 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10142 INTEL_INFO(dev
)->num_pipes
,
10143 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10146 intel_crtc_init(dev
, i
);
10147 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10148 ret
= intel_plane_init(dev
, i
, j
);
10150 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10151 pipe_name(i
), sprite_name(i
, j
), ret
);
10155 intel_cpu_pll_init(dev
);
10156 intel_shared_dpll_init(dev
);
10158 /* Just disable it once at startup */
10159 i915_disable_vga(dev
);
10160 intel_setup_outputs(dev
);
10162 /* Just in case the BIOS is doing something questionable. */
10163 intel_disable_fbc(dev
);
10167 intel_connector_break_all_links(struct intel_connector
*connector
)
10169 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10170 connector
->base
.encoder
= NULL
;
10171 connector
->encoder
->connectors_active
= false;
10172 connector
->encoder
->base
.crtc
= NULL
;
10175 static void intel_enable_pipe_a(struct drm_device
*dev
)
10177 struct intel_connector
*connector
;
10178 struct drm_connector
*crt
= NULL
;
10179 struct intel_load_detect_pipe load_detect_temp
;
10181 /* We can't just switch on the pipe A, we need to set things up with a
10182 * proper mode and output configuration. As a gross hack, enable pipe A
10183 * by enabling the load detect pipe once. */
10184 list_for_each_entry(connector
,
10185 &dev
->mode_config
.connector_list
,
10187 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10188 crt
= &connector
->base
;
10196 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10197 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10203 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10205 struct drm_device
*dev
= crtc
->base
.dev
;
10206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10209 if (INTEL_INFO(dev
)->num_pipes
== 1)
10212 reg
= DSPCNTR(!crtc
->plane
);
10213 val
= I915_READ(reg
);
10215 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10216 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10222 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10224 struct drm_device
*dev
= crtc
->base
.dev
;
10225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10228 /* Clear any frame start delays used for debugging left by the BIOS */
10229 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10230 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10232 /* We need to sanitize the plane -> pipe mapping first because this will
10233 * disable the crtc (and hence change the state) if it is wrong. Note
10234 * that gen4+ has a fixed plane -> pipe mapping. */
10235 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10236 struct intel_connector
*connector
;
10239 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10240 crtc
->base
.base
.id
);
10242 /* Pipe has the wrong plane attached and the plane is active.
10243 * Temporarily change the plane mapping and disable everything
10245 plane
= crtc
->plane
;
10246 crtc
->plane
= !plane
;
10247 dev_priv
->display
.crtc_disable(&crtc
->base
);
10248 crtc
->plane
= plane
;
10250 /* ... and break all links. */
10251 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10253 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10256 intel_connector_break_all_links(connector
);
10259 WARN_ON(crtc
->active
);
10260 crtc
->base
.enabled
= false;
10263 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10264 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10265 /* BIOS forgot to enable pipe A, this mostly happens after
10266 * resume. Force-enable the pipe to fix this, the update_dpms
10267 * call below we restore the pipe to the right state, but leave
10268 * the required bits on. */
10269 intel_enable_pipe_a(dev
);
10272 /* Adjust the state of the output pipe according to whether we
10273 * have active connectors/encoders. */
10274 intel_crtc_update_dpms(&crtc
->base
);
10276 if (crtc
->active
!= crtc
->base
.enabled
) {
10277 struct intel_encoder
*encoder
;
10279 /* This can happen either due to bugs in the get_hw_state
10280 * functions or because the pipe is force-enabled due to the
10282 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10283 crtc
->base
.base
.id
,
10284 crtc
->base
.enabled
? "enabled" : "disabled",
10285 crtc
->active
? "enabled" : "disabled");
10287 crtc
->base
.enabled
= crtc
->active
;
10289 /* Because we only establish the connector -> encoder ->
10290 * crtc links if something is active, this means the
10291 * crtc is now deactivated. Break the links. connector
10292 * -> encoder links are only establish when things are
10293 * actually up, hence no need to break them. */
10294 WARN_ON(crtc
->active
);
10296 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10297 WARN_ON(encoder
->connectors_active
);
10298 encoder
->base
.crtc
= NULL
;
10303 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10305 struct intel_connector
*connector
;
10306 struct drm_device
*dev
= encoder
->base
.dev
;
10308 /* We need to check both for a crtc link (meaning that the
10309 * encoder is active and trying to read from a pipe) and the
10310 * pipe itself being active. */
10311 bool has_active_crtc
= encoder
->base
.crtc
&&
10312 to_intel_crtc(encoder
->base
.crtc
)->active
;
10314 if (encoder
->connectors_active
&& !has_active_crtc
) {
10315 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10316 encoder
->base
.base
.id
,
10317 drm_get_encoder_name(&encoder
->base
));
10319 /* Connector is active, but has no active pipe. This is
10320 * fallout from our resume register restoring. Disable
10321 * the encoder manually again. */
10322 if (encoder
->base
.crtc
) {
10323 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10324 encoder
->base
.base
.id
,
10325 drm_get_encoder_name(&encoder
->base
));
10326 encoder
->disable(encoder
);
10329 /* Inconsistent output/port/pipe state happens presumably due to
10330 * a bug in one of the get_hw_state functions. Or someplace else
10331 * in our code, like the register restore mess on resume. Clamp
10332 * things to off as a safer default. */
10333 list_for_each_entry(connector
,
10334 &dev
->mode_config
.connector_list
,
10336 if (connector
->encoder
!= encoder
)
10339 intel_connector_break_all_links(connector
);
10342 /* Enabled encoders without active connectors will be fixed in
10343 * the crtc fixup. */
10346 void i915_redisable_vga(struct drm_device
*dev
)
10348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10349 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10351 /* This function can be called both from intel_modeset_setup_hw_state or
10352 * at a very early point in our resume sequence, where the power well
10353 * structures are not yet restored. Since this function is at a very
10354 * paranoid "someone might have enabled VGA while we were not looking"
10355 * level, just check if the power well is enabled instead of trying to
10356 * follow the "don't touch the power well if we don't need it" policy
10357 * the rest of the driver uses. */
10358 if (HAS_POWER_WELL(dev
) &&
10359 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10362 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
10363 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10364 i915_disable_vga(dev
);
10368 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10372 struct intel_crtc
*crtc
;
10373 struct intel_encoder
*encoder
;
10374 struct intel_connector
*connector
;
10377 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10379 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10381 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10384 crtc
->base
.enabled
= crtc
->active
;
10386 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10387 crtc
->base
.base
.id
,
10388 crtc
->active
? "enabled" : "disabled");
10391 /* FIXME: Smash this into the new shared dpll infrastructure. */
10393 intel_ddi_setup_hw_pll_state(dev
);
10395 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10396 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10398 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10400 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10402 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10405 pll
->refcount
= pll
->active
;
10407 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10408 pll
->name
, pll
->refcount
, pll
->on
);
10411 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10415 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10416 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10417 encoder
->base
.crtc
= &crtc
->base
;
10418 if (encoder
->get_config
)
10419 encoder
->get_config(encoder
, &crtc
->config
);
10421 encoder
->base
.crtc
= NULL
;
10424 encoder
->connectors_active
= false;
10425 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10426 encoder
->base
.base
.id
,
10427 drm_get_encoder_name(&encoder
->base
),
10428 encoder
->base
.crtc
? "enabled" : "disabled",
10432 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10436 if (dev_priv
->display
.get_clock
)
10437 dev_priv
->display
.get_clock(crtc
,
10441 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10443 if (connector
->get_hw_state(connector
)) {
10444 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10445 connector
->encoder
->connectors_active
= true;
10446 connector
->base
.encoder
= &connector
->encoder
->base
;
10448 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10449 connector
->base
.encoder
= NULL
;
10451 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10452 connector
->base
.base
.id
,
10453 drm_get_connector_name(&connector
->base
),
10454 connector
->base
.encoder
? "enabled" : "disabled");
10458 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10459 * and i915 state tracking structures. */
10460 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10461 bool force_restore
)
10463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10465 struct drm_plane
*plane
;
10466 struct intel_crtc
*crtc
;
10467 struct intel_encoder
*encoder
;
10470 intel_modeset_readout_hw_state(dev
);
10473 * Now that we have the config, copy it to each CRTC struct
10474 * Note that this could go away if we move to using crtc_config
10475 * checking everywhere.
10477 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10479 if (crtc
->active
&& i915_fastboot
) {
10480 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10482 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10483 crtc
->base
.base
.id
);
10484 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10488 /* HW state is read out, now we need to sanitize this mess. */
10489 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10491 intel_sanitize_encoder(encoder
);
10494 for_each_pipe(pipe
) {
10495 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10496 intel_sanitize_crtc(crtc
);
10497 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10500 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10501 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10503 if (!pll
->on
|| pll
->active
)
10506 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10508 pll
->disable(dev_priv
, pll
);
10512 if (force_restore
) {
10514 * We need to use raw interfaces for restoring state to avoid
10515 * checking (bogus) intermediate states.
10517 for_each_pipe(pipe
) {
10518 struct drm_crtc
*crtc
=
10519 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10521 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10524 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
10525 intel_plane_restore(plane
);
10527 i915_redisable_vga(dev
);
10529 intel_modeset_update_staged_output_state(dev
);
10532 intel_modeset_check_state(dev
);
10534 drm_mode_config_reset(dev
);
10537 void intel_modeset_gem_init(struct drm_device
*dev
)
10539 intel_modeset_init_hw(dev
);
10541 intel_setup_overlay(dev
);
10543 intel_modeset_setup_hw_state(dev
, false);
10546 void intel_modeset_cleanup(struct drm_device
*dev
)
10548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10549 struct drm_crtc
*crtc
;
10552 * Interrupts and polling as the first thing to avoid creating havoc.
10553 * Too much stuff here (turning of rps, connectors, ...) would
10554 * experience fancy races otherwise.
10556 drm_irq_uninstall(dev
);
10557 cancel_work_sync(&dev_priv
->hotplug_work
);
10559 * Due to the hpd irq storm handling the hotplug work can re-arm the
10560 * poll handlers. Hence disable polling after hpd handling is shut down.
10562 drm_kms_helper_poll_fini(dev
);
10564 mutex_lock(&dev
->struct_mutex
);
10566 intel_unregister_dsm_handler();
10568 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10569 /* Skip inactive CRTCs */
10573 intel_increase_pllclock(crtc
);
10576 intel_disable_fbc(dev
);
10578 i915_enable_vga(dev
);
10580 intel_disable_gt_powersave(dev
);
10582 ironlake_teardown_rc6(dev
);
10584 mutex_unlock(&dev
->struct_mutex
);
10586 /* flush any delayed tasks or pending work */
10587 flush_scheduled_work();
10589 /* destroy backlight, if any, before the connectors */
10590 intel_panel_destroy_backlight(dev
);
10592 drm_mode_config_cleanup(dev
);
10594 intel_cleanup_overlay(dev
);
10598 * Return which encoder is currently attached for connector.
10600 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10602 return &intel_attached_encoder(connector
)->base
;
10605 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10606 struct intel_encoder
*encoder
)
10608 connector
->encoder
= encoder
;
10609 drm_mode_connector_attach_encoder(&connector
->base
,
10614 * set vga decode state - true == enable VGA decode
10616 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10621 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10623 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10625 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10626 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10630 struct intel_display_error_state
{
10632 u32 power_well_driver
;
10634 int num_transcoders
;
10636 struct intel_cursor_error_state
{
10641 } cursor
[I915_MAX_PIPES
];
10643 struct intel_pipe_error_state
{
10645 } pipe
[I915_MAX_PIPES
];
10647 struct intel_plane_error_state
{
10655 } plane
[I915_MAX_PIPES
];
10657 struct intel_transcoder_error_state
{
10658 enum transcoder cpu_transcoder
;
10671 struct intel_display_error_state
*
10672 intel_display_capture_error_state(struct drm_device
*dev
)
10674 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10675 struct intel_display_error_state
*error
;
10676 int transcoders
[] = {
10684 if (INTEL_INFO(dev
)->num_pipes
== 0)
10687 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10691 if (HAS_POWER_WELL(dev
))
10692 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10695 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10696 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10697 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10698 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10700 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10701 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10702 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10705 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10706 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10707 if (INTEL_INFO(dev
)->gen
<= 3) {
10708 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10709 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10711 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10712 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10713 if (INTEL_INFO(dev
)->gen
>= 4) {
10714 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10715 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10718 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10721 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
10722 if (HAS_DDI(dev_priv
->dev
))
10723 error
->num_transcoders
++; /* Account for eDP. */
10725 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10726 enum transcoder cpu_transcoder
= transcoders
[i
];
10728 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
10730 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10731 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10732 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10733 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10734 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10735 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10736 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10739 /* In the code above we read the registers without checking if the power
10740 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10741 * prevent the next I915_WRITE from detecting it and printing an error
10743 intel_uncore_clear_errors(dev
);
10748 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10751 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10752 struct drm_device
*dev
,
10753 struct intel_display_error_state
*error
)
10760 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10761 if (HAS_POWER_WELL(dev
))
10762 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10763 error
->power_well_driver
);
10765 err_printf(m
, "Pipe [%d]:\n", i
);
10766 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10768 err_printf(m
, "Plane [%d]:\n", i
);
10769 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10770 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10771 if (INTEL_INFO(dev
)->gen
<= 3) {
10772 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10773 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10775 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10776 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10777 if (INTEL_INFO(dev
)->gen
>= 4) {
10778 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10779 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10782 err_printf(m
, "Cursor [%d]:\n", i
);
10783 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10784 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10785 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
10788 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10789 err_printf(m
, " CPU transcoder: %c\n",
10790 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
10791 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
10792 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
10793 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
10794 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
10795 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
10796 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
10797 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);