2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
33 #include "intel_drv.h"
36 #include "drm_dp_helper.h"
38 #include "drm_crtc_helper.h"
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
43 static void intel_update_watermarks(struct drm_device
*dev
);
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
67 #define INTEL_P2_NUM 2
68 typedef struct intel_limit intel_limit_t
;
70 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
73 int, int, intel_clock_t
*);
76 #define I8XX_DOT_MIN 25000
77 #define I8XX_DOT_MAX 350000
78 #define I8XX_VCO_MIN 930000
79 #define I8XX_VCO_MAX 1400000
83 #define I8XX_M_MAX 140
84 #define I8XX_M1_MIN 18
85 #define I8XX_M1_MAX 26
87 #define I8XX_M2_MAX 16
89 #define I8XX_P_MAX 128
91 #define I8XX_P1_MAX 33
92 #define I8XX_P1_LVDS_MIN 1
93 #define I8XX_P1_LVDS_MAX 6
94 #define I8XX_P2_SLOW 4
95 #define I8XX_P2_FAST 2
96 #define I8XX_P2_LVDS_SLOW 14
97 #define I8XX_P2_LVDS_FAST 7
98 #define I8XX_P2_SLOW_LIMIT 165000
100 #define I9XX_DOT_MIN 20000
101 #define I9XX_DOT_MAX 400000
102 #define I9XX_VCO_MIN 1400000
103 #define I9XX_VCO_MAX 2800000
104 #define PINEVIEW_VCO_MIN 1700000
105 #define PINEVIEW_VCO_MAX 3500000
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN 3
110 #define PINEVIEW_N_MAX 6
111 #define I9XX_M_MIN 70
112 #define I9XX_M_MAX 120
113 #define PINEVIEW_M_MIN 2
114 #define PINEVIEW_M_MAX 256
115 #define I9XX_M1_MIN 10
116 #define I9XX_M1_MAX 22
117 #define I9XX_M2_MIN 5
118 #define I9XX_M2_MAX 9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN 0
121 #define PINEVIEW_M1_MAX 0
122 #define PINEVIEW_M2_MIN 0
123 #define PINEVIEW_M2_MAX 254
124 #define I9XX_P_SDVO_DAC_MIN 5
125 #define I9XX_P_SDVO_DAC_MAX 80
126 #define I9XX_P_LVDS_MIN 7
127 #define I9XX_P_LVDS_MAX 98
128 #define PINEVIEW_P_LVDS_MIN 7
129 #define PINEVIEW_P_LVDS_MAX 112
130 #define I9XX_P1_MIN 1
131 #define I9XX_P1_MAX 8
132 #define I9XX_P2_SDVO_DAC_SLOW 10
133 #define I9XX_P2_SDVO_DAC_FAST 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135 #define I9XX_P2_LVDS_SLOW 14
136 #define I9XX_P2_LVDS_FAST 7
137 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN 25000
141 #define G4X_DOT_SDVO_MAX 270000
142 #define G4X_VCO_MIN 1750000
143 #define G4X_VCO_MAX 3500000
144 #define G4X_N_SDVO_MIN 1
145 #define G4X_N_SDVO_MAX 4
146 #define G4X_M_SDVO_MIN 104
147 #define G4X_M_SDVO_MAX 138
148 #define G4X_M1_SDVO_MIN 17
149 #define G4X_M1_SDVO_MAX 23
150 #define G4X_M2_SDVO_MIN 5
151 #define G4X_M2_SDVO_MAX 11
152 #define G4X_P_SDVO_MIN 10
153 #define G4X_P_SDVO_MAX 30
154 #define G4X_P1_SDVO_MIN 1
155 #define G4X_P1_SDVO_MAX 3
156 #define G4X_P2_SDVO_SLOW 10
157 #define G4X_P2_SDVO_FAST 10
158 #define G4X_P2_SDVO_LIMIT 270000
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN 22000
162 #define G4X_DOT_HDMI_DAC_MAX 400000
163 #define G4X_N_HDMI_DAC_MIN 1
164 #define G4X_N_HDMI_DAC_MAX 4
165 #define G4X_M_HDMI_DAC_MIN 104
166 #define G4X_M_HDMI_DAC_MAX 138
167 #define G4X_M1_HDMI_DAC_MIN 16
168 #define G4X_M1_HDMI_DAC_MAX 23
169 #define G4X_M2_HDMI_DAC_MIN 5
170 #define G4X_M2_HDMI_DAC_MAX 11
171 #define G4X_P_HDMI_DAC_MIN 5
172 #define G4X_P_HDMI_DAC_MAX 80
173 #define G4X_P1_HDMI_DAC_MIN 1
174 #define G4X_P1_HDMI_DAC_MAX 8
175 #define G4X_P2_HDMI_DAC_SLOW 10
176 #define G4X_P2_HDMI_DAC_FAST 5
177 #define G4X_P2_HDMI_DAC_LIMIT 165000
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN 161670
219 #define G4X_DOT_DISPLAY_PORT_MAX 227000
220 #define G4X_N_DISPLAY_PORT_MIN 1
221 #define G4X_N_DISPLAY_PORT_MAX 2
222 #define G4X_M_DISPLAY_PORT_MIN 97
223 #define G4X_M_DISPLAY_PORT_MAX 108
224 #define G4X_M1_DISPLAY_PORT_MIN 0x10
225 #define G4X_M1_DISPLAY_PORT_MAX 0x12
226 #define G4X_M2_DISPLAY_PORT_MIN 0x05
227 #define G4X_M2_DISPLAY_PORT_MAX 0x06
228 #define G4X_P_DISPLAY_PORT_MIN 10
229 #define G4X_P_DISPLAY_PORT_MAX 20
230 #define G4X_P1_DISPLAY_PORT_MIN 1
231 #define G4X_P1_DISPLAY_PORT_MAX 2
232 #define G4X_P2_DISPLAY_PORT_SLOW 10
233 #define G4X_P2_DISPLAY_PORT_FAST 10
234 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
240 #define IRONLAKE_DOT_MIN 25000
241 #define IRONLAKE_DOT_MAX 350000
242 #define IRONLAKE_VCO_MIN 1760000
243 #define IRONLAKE_VCO_MAX 3510000
244 #define IRONLAKE_M1_MIN 12
245 #define IRONLAKE_M1_MAX 22
246 #define IRONLAKE_M2_MIN 5
247 #define IRONLAKE_M2_MAX 9
248 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
250 /* We have parameter ranges for different type of outputs. */
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN 1
254 #define IRONLAKE_DAC_N_MAX 5
255 #define IRONLAKE_DAC_M_MIN 79
256 #define IRONLAKE_DAC_M_MAX 127
257 #define IRONLAKE_DAC_P_MIN 5
258 #define IRONLAKE_DAC_P_MAX 80
259 #define IRONLAKE_DAC_P1_MIN 1
260 #define IRONLAKE_DAC_P1_MAX 8
261 #define IRONLAKE_DAC_P2_SLOW 10
262 #define IRONLAKE_DAC_P2_FAST 5
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN 1
266 #define IRONLAKE_LVDS_S_N_MAX 3
267 #define IRONLAKE_LVDS_S_M_MIN 79
268 #define IRONLAKE_LVDS_S_M_MAX 118
269 #define IRONLAKE_LVDS_S_P_MIN 28
270 #define IRONLAKE_LVDS_S_P_MAX 112
271 #define IRONLAKE_LVDS_S_P1_MIN 2
272 #define IRONLAKE_LVDS_S_P1_MAX 8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN 1
278 #define IRONLAKE_LVDS_D_N_MAX 3
279 #define IRONLAKE_LVDS_D_M_MIN 79
280 #define IRONLAKE_LVDS_D_M_MAX 127
281 #define IRONLAKE_LVDS_D_P_MIN 14
282 #define IRONLAKE_LVDS_D_P_MAX 56
283 #define IRONLAKE_LVDS_D_P1_MIN 2
284 #define IRONLAKE_LVDS_D_P1_MAX 8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313 #define IRONLAKE_DP_N_MIN 1
314 #define IRONLAKE_DP_N_MAX 2
315 #define IRONLAKE_DP_M_MIN 81
316 #define IRONLAKE_DP_M_MAX 90
317 #define IRONLAKE_DP_P_MIN 10
318 #define IRONLAKE_DP_P_MAX 20
319 #define IRONLAKE_DP_P2_FAST 10
320 #define IRONLAKE_DP_P2_SLOW 10
321 #define IRONLAKE_DP_P2_LIMIT 0
322 #define IRONLAKE_DP_P1_MIN 1
323 #define IRONLAKE_DP_P1_MAX 2
326 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
327 int target
, int refclk
, intel_clock_t
*best_clock
);
329 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
330 int target
, int refclk
, intel_clock_t
*best_clock
);
333 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
334 int target
, int refclk
, intel_clock_t
*best_clock
);
336 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
337 int target
, int refclk
, intel_clock_t
*best_clock
);
339 static const intel_limit_t intel_limits_i8xx_dvo
= {
340 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
341 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
342 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
343 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
344 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
345 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
346 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
347 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
348 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
349 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
350 .find_pll
= intel_find_best_PLL
,
353 static const intel_limit_t intel_limits_i8xx_lvds
= {
354 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
355 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
356 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
357 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
358 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
359 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
360 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
361 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
362 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
363 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
364 .find_pll
= intel_find_best_PLL
,
367 static const intel_limit_t intel_limits_i9xx_sdvo
= {
368 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
369 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
370 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
371 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
372 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
373 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
374 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
375 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
376 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
377 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
378 .find_pll
= intel_find_best_PLL
,
381 static const intel_limit_t intel_limits_i9xx_lvds
= {
382 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
383 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
384 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
385 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
386 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
387 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
388 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
389 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
393 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
394 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
395 .find_pll
= intel_find_best_PLL
,
398 /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo
= {
400 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
401 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
402 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
403 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
404 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
405 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
406 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
407 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
408 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
409 .p2_slow
= G4X_P2_SDVO_SLOW
,
410 .p2_fast
= G4X_P2_SDVO_FAST
412 .find_pll
= intel_g4x_find_best_PLL
,
415 static const intel_limit_t intel_limits_g4x_hdmi
= {
416 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
417 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
418 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
419 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
420 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
421 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
422 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
423 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
424 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
425 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
426 .p2_fast
= G4X_P2_HDMI_DAC_FAST
428 .find_pll
= intel_g4x_find_best_PLL
,
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
432 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
433 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
434 .vco
= { .min
= G4X_VCO_MIN
,
435 .max
= G4X_VCO_MAX
},
436 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
437 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
438 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
439 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
440 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
441 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
442 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
443 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
444 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
445 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
446 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
447 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
448 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
449 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
450 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
452 .find_pll
= intel_g4x_find_best_PLL
,
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
456 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
457 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
458 .vco
= { .min
= G4X_VCO_MIN
,
459 .max
= G4X_VCO_MAX
},
460 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
461 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
462 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
463 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
464 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
465 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
466 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
467 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
468 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
469 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
470 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
471 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
472 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
473 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
474 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
476 .find_pll
= intel_g4x_find_best_PLL
,
479 static const intel_limit_t intel_limits_g4x_display_port
= {
480 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
481 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
482 .vco
= { .min
= G4X_VCO_MIN
,
484 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
485 .max
= G4X_N_DISPLAY_PORT_MAX
},
486 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
487 .max
= G4X_M_DISPLAY_PORT_MAX
},
488 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
489 .max
= G4X_M1_DISPLAY_PORT_MAX
},
490 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
491 .max
= G4X_M2_DISPLAY_PORT_MAX
},
492 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
493 .max
= G4X_P_DISPLAY_PORT_MAX
},
494 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
495 .max
= G4X_P1_DISPLAY_PORT_MAX
},
496 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
497 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
498 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
499 .find_pll
= intel_find_pll_g4x_dp
,
502 static const intel_limit_t intel_limits_pineview_sdvo
= {
503 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
504 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
505 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
506 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
507 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
508 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
509 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
510 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
511 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
512 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
513 .find_pll
= intel_find_best_PLL
,
516 static const intel_limit_t intel_limits_pineview_lvds
= {
517 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
518 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
519 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
520 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
521 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
522 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
523 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
524 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
525 /* Pineview only supports single-channel mode. */
526 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
527 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
528 .find_pll
= intel_find_best_PLL
,
531 static const intel_limit_t intel_limits_ironlake_dac
= {
532 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
533 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
534 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
535 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
536 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
537 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
538 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
539 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
540 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
541 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
542 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
543 .find_pll
= intel_g4x_find_best_PLL
,
546 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
547 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
548 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
549 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
550 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
551 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
552 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
553 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
554 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
555 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
556 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
557 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
558 .find_pll
= intel_g4x_find_best_PLL
,
561 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
562 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
563 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
564 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
565 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
566 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
567 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
568 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
569 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
570 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
571 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
572 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
573 .find_pll
= intel_g4x_find_best_PLL
,
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
577 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
578 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
579 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
580 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
581 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
582 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
583 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
584 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
585 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
586 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
587 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
588 .find_pll
= intel_g4x_find_best_PLL
,
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
592 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
593 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
594 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
595 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
596 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
597 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
598 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
599 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
600 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
601 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
602 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
603 .find_pll
= intel_g4x_find_best_PLL
,
606 static const intel_limit_t intel_limits_ironlake_display_port
= {
607 .dot
= { .min
= IRONLAKE_DOT_MIN
,
608 .max
= IRONLAKE_DOT_MAX
},
609 .vco
= { .min
= IRONLAKE_VCO_MIN
,
610 .max
= IRONLAKE_VCO_MAX
},
611 .n
= { .min
= IRONLAKE_DP_N_MIN
,
612 .max
= IRONLAKE_DP_N_MAX
},
613 .m
= { .min
= IRONLAKE_DP_M_MIN
,
614 .max
= IRONLAKE_DP_M_MAX
},
615 .m1
= { .min
= IRONLAKE_M1_MIN
,
616 .max
= IRONLAKE_M1_MAX
},
617 .m2
= { .min
= IRONLAKE_M2_MIN
,
618 .max
= IRONLAKE_M2_MAX
},
619 .p
= { .min
= IRONLAKE_DP_P_MIN
,
620 .max
= IRONLAKE_DP_P_MAX
},
621 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
622 .max
= IRONLAKE_DP_P1_MAX
},
623 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
624 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
625 .p2_fast
= IRONLAKE_DP_P2_FAST
},
626 .find_pll
= intel_find_pll_ironlake_dp
,
629 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
631 struct drm_device
*dev
= crtc
->dev
;
632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 const intel_limit_t
*limit
;
636 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
637 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
640 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
641 LVDS_CLKB_POWER_UP
) {
642 /* LVDS dual channel */
644 limit
= &intel_limits_ironlake_dual_lvds_100m
;
646 limit
= &intel_limits_ironlake_dual_lvds
;
649 limit
= &intel_limits_ironlake_single_lvds_100m
;
651 limit
= &intel_limits_ironlake_single_lvds
;
653 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
655 limit
= &intel_limits_ironlake_display_port
;
657 limit
= &intel_limits_ironlake_dac
;
662 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
664 struct drm_device
*dev
= crtc
->dev
;
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 const intel_limit_t
*limit
;
668 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
669 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
671 /* LVDS with dual channel */
672 limit
= &intel_limits_g4x_dual_channel_lvds
;
674 /* LVDS with dual channel */
675 limit
= &intel_limits_g4x_single_channel_lvds
;
676 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
677 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
678 limit
= &intel_limits_g4x_hdmi
;
679 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
680 limit
= &intel_limits_g4x_sdvo
;
681 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
682 limit
= &intel_limits_g4x_display_port
;
683 } else /* The option is for other outputs */
684 limit
= &intel_limits_i9xx_sdvo
;
689 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
691 struct drm_device
*dev
= crtc
->dev
;
692 const intel_limit_t
*limit
;
694 if (HAS_PCH_SPLIT(dev
))
695 limit
= intel_ironlake_limit(crtc
);
696 else if (IS_G4X(dev
)) {
697 limit
= intel_g4x_limit(crtc
);
698 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
699 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
700 limit
= &intel_limits_i9xx_lvds
;
702 limit
= &intel_limits_i9xx_sdvo
;
703 } else if (IS_PINEVIEW(dev
)) {
704 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
705 limit
= &intel_limits_pineview_lvds
;
707 limit
= &intel_limits_pineview_sdvo
;
709 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
710 limit
= &intel_limits_i8xx_lvds
;
712 limit
= &intel_limits_i8xx_dvo
;
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
720 clock
->m
= clock
->m2
+ 2;
721 clock
->p
= clock
->p1
* clock
->p2
;
722 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
723 clock
->dot
= clock
->vco
/ clock
->p
;
726 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
728 if (IS_PINEVIEW(dev
)) {
729 pineview_clock(refclk
, clock
);
732 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
733 clock
->p
= clock
->p1
* clock
->p2
;
734 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
735 clock
->dot
= clock
->vco
/ clock
->p
;
739 * Returns whether any output on the specified pipe is of the specified type
741 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
743 struct drm_device
*dev
= crtc
->dev
;
744 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
745 struct drm_encoder
*l_entry
;
747 list_for_each_entry(l_entry
, &mode_config
->encoder_list
, head
) {
748 if (l_entry
&& l_entry
->crtc
== crtc
) {
749 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(l_entry
);
750 if (intel_encoder
->type
== type
)
757 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
759 * Returns whether the given set of divisors are valid for a given refclk with
760 * the given connectors.
763 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
765 const intel_limit_t
*limit
= intel_limit (crtc
);
766 struct drm_device
*dev
= crtc
->dev
;
768 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
769 INTELPllInvalid ("p1 out of range\n");
770 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
771 INTELPllInvalid ("p out of range\n");
772 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
773 INTELPllInvalid ("m2 out of range\n");
774 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
775 INTELPllInvalid ("m1 out of range\n");
776 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
777 INTELPllInvalid ("m1 <= m2\n");
778 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
779 INTELPllInvalid ("m out of range\n");
780 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
781 INTELPllInvalid ("n out of range\n");
782 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
783 INTELPllInvalid ("vco out of range\n");
784 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785 * connector, etc., rather than just a single range.
787 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
788 INTELPllInvalid ("dot out of range\n");
794 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
795 int target
, int refclk
, intel_clock_t
*best_clock
)
798 struct drm_device
*dev
= crtc
->dev
;
799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
804 (I915_READ(LVDS
)) != 0) {
806 * For LVDS, if the panel is on, just rely on its current
807 * settings for dual-channel. We haven't figured out how to
808 * reliably set up different single/dual channel state, if we
811 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
813 clock
.p2
= limit
->p2
.p2_fast
;
815 clock
.p2
= limit
->p2
.p2_slow
;
817 if (target
< limit
->p2
.dot_limit
)
818 clock
.p2
= limit
->p2
.p2_slow
;
820 clock
.p2
= limit
->p2
.p2_fast
;
823 memset (best_clock
, 0, sizeof (*best_clock
));
825 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
827 for (clock
.m2
= limit
->m2
.min
;
828 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
829 /* m1 is always 0 in Pineview */
830 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
832 for (clock
.n
= limit
->n
.min
;
833 clock
.n
<= limit
->n
.max
; clock
.n
++) {
834 for (clock
.p1
= limit
->p1
.min
;
835 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
838 intel_clock(dev
, refclk
, &clock
);
840 if (!intel_PLL_is_valid(crtc
, &clock
))
843 this_err
= abs(clock
.dot
- target
);
844 if (this_err
< err
) {
853 return (err
!= target
);
857 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
858 int target
, int refclk
, intel_clock_t
*best_clock
)
860 struct drm_device
*dev
= crtc
->dev
;
861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
865 /* approximately equals target * 0.00488 */
866 int err_most
= (target
>> 8) + (target
>> 10);
869 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
872 if (HAS_PCH_SPLIT(dev
))
876 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
878 clock
.p2
= limit
->p2
.p2_fast
;
880 clock
.p2
= limit
->p2
.p2_slow
;
882 if (target
< limit
->p2
.dot_limit
)
883 clock
.p2
= limit
->p2
.p2_slow
;
885 clock
.p2
= limit
->p2
.p2_fast
;
888 memset(best_clock
, 0, sizeof(*best_clock
));
889 max_n
= limit
->n
.max
;
890 /* based on hardware requriment prefer smaller n to precision */
891 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
892 /* based on hardware requirment prefere larger m1,m2 */
893 for (clock
.m1
= limit
->m1
.max
;
894 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
895 for (clock
.m2
= limit
->m2
.max
;
896 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
897 for (clock
.p1
= limit
->p1
.max
;
898 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
901 intel_clock(dev
, refclk
, &clock
);
902 if (!intel_PLL_is_valid(crtc
, &clock
))
904 this_err
= abs(clock
.dot
- target
) ;
905 if (this_err
< err_most
) {
919 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
920 int target
, int refclk
, intel_clock_t
*best_clock
)
922 struct drm_device
*dev
= crtc
->dev
;
925 /* return directly when it is eDP */
929 if (target
< 200000) {
942 intel_clock(dev
, refclk
, &clock
);
943 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
949 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
950 int target
, int refclk
, intel_clock_t
*best_clock
)
953 if (target
< 200000) {
966 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
967 clock
.p
= (clock
.p1
* clock
.p2
);
968 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
970 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
975 intel_wait_for_vblank(struct drm_device
*dev
)
977 /* Wait for 20ms, i.e. one cycle at 50hz. */
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
984 struct drm_device
*dev
= crtc
->dev
;
985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
986 struct drm_framebuffer
*fb
= crtc
->fb
;
987 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
988 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
991 u32 fbc_ctl
, fbc_ctl2
;
993 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
995 if (fb
->pitch
< dev_priv
->cfb_pitch
)
996 dev_priv
->cfb_pitch
= fb
->pitch
;
998 /* FBC_CTL wants 64B units */
999 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1000 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1001 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1002 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1004 /* Clear old tags */
1005 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1006 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1009 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1010 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1011 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1012 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1013 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1016 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1018 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1019 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1020 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1021 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1022 fbc_ctl
|= dev_priv
->cfb_fence
;
1023 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1025 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1029 void i8xx_disable_fbc(struct drm_device
*dev
)
1031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1034 if (!I915_HAS_FBC(dev
))
1037 /* Disable compression */
1038 fbc_ctl
= I915_READ(FBC_CONTROL
);
1039 fbc_ctl
&= ~FBC_CTL_EN
;
1040 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1042 /* Wait for compressing bit to clear */
1043 while (I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
)
1046 intel_wait_for_vblank(dev
);
1048 DRM_DEBUG_KMS("disabled FBC\n");
1051 static bool i8xx_fbc_enabled(struct drm_crtc
*crtc
)
1053 struct drm_device
*dev
= crtc
->dev
;
1054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1056 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1059 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1061 struct drm_device
*dev
= crtc
->dev
;
1062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1063 struct drm_framebuffer
*fb
= crtc
->fb
;
1064 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1065 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1066 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1067 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
1069 unsigned long stall_watermark
= 200;
1072 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1073 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1074 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1076 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1077 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1078 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1079 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1081 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1084 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1085 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1086 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1087 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1088 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1091 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1093 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1096 void g4x_disable_fbc(struct drm_device
*dev
)
1098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1101 /* Disable compression */
1102 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1103 dpfc_ctl
&= ~DPFC_CTL_EN
;
1104 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1105 intel_wait_for_vblank(dev
);
1107 DRM_DEBUG_KMS("disabled FBC\n");
1110 static bool g4x_fbc_enabled(struct drm_crtc
*crtc
)
1112 struct drm_device
*dev
= crtc
->dev
;
1113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1115 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1119 * intel_update_fbc - enable/disable FBC as needed
1120 * @crtc: CRTC to point the compressor at
1121 * @mode: mode in use
1123 * Set up the framebuffer compression hardware at mode set time. We
1124 * enable it if possible:
1125 * - plane A only (on pre-965)
1126 * - no pixel mulitply/line duplication
1127 * - no alpha buffer discard
1129 * - framebuffer <= 2048 in width, 1536 in height
1131 * We can't assume that any compression will take place (worst case),
1132 * so the compressed buffer has to be the same size as the uncompressed
1133 * one. It also must reside (along with the line length buffer) in
1136 * We need to enable/disable FBC on a global basis.
1138 static void intel_update_fbc(struct drm_crtc
*crtc
,
1139 struct drm_display_mode
*mode
)
1141 struct drm_device
*dev
= crtc
->dev
;
1142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1143 struct drm_framebuffer
*fb
= crtc
->fb
;
1144 struct intel_framebuffer
*intel_fb
;
1145 struct drm_i915_gem_object
*obj_priv
;
1146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1147 int plane
= intel_crtc
->plane
;
1149 if (!i915_powersave
)
1152 if (!dev_priv
->display
.fbc_enabled
||
1153 !dev_priv
->display
.enable_fbc
||
1154 !dev_priv
->display
.disable_fbc
)
1160 intel_fb
= to_intel_framebuffer(fb
);
1161 obj_priv
= to_intel_bo(intel_fb
->obj
);
1164 * If FBC is already on, we just have to verify that we can
1165 * keep it that way...
1166 * Need to disable if:
1167 * - changing FBC params (stride, fence, mode)
1168 * - new fb is too large to fit in compressed buffer
1169 * - going to an unsupported config (interlace, pixel multiply, etc.)
1171 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1172 DRM_DEBUG_KMS("framebuffer too large, disabling "
1174 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1177 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1178 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1179 DRM_DEBUG_KMS("mode incompatible with compression, "
1181 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1184 if ((mode
->hdisplay
> 2048) ||
1185 (mode
->vdisplay
> 1536)) {
1186 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1187 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1190 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1191 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1192 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1195 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1196 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1197 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1201 if (dev_priv
->display
.fbc_enabled(crtc
)) {
1202 /* We can re-enable it in this case, but need to update pitch */
1203 if (fb
->pitch
> dev_priv
->cfb_pitch
)
1204 dev_priv
->display
.disable_fbc(dev
);
1205 if (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
)
1206 dev_priv
->display
.disable_fbc(dev
);
1207 if (plane
!= dev_priv
->cfb_plane
)
1208 dev_priv
->display
.disable_fbc(dev
);
1211 if (!dev_priv
->display
.fbc_enabled(crtc
)) {
1212 /* Now try to turn it back on if possible */
1213 dev_priv
->display
.enable_fbc(crtc
, 500);
1219 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1220 /* Multiple disables should be harmless */
1221 if (dev_priv
->display
.fbc_enabled(crtc
))
1222 dev_priv
->display
.disable_fbc(dev
);
1226 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1228 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1232 switch (obj_priv
->tiling_mode
) {
1233 case I915_TILING_NONE
:
1234 alignment
= 64 * 1024;
1237 /* pin() will align the object as required by fence */
1241 /* FIXME: Is this true? */
1242 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1248 ret
= i915_gem_object_pin(obj
, alignment
);
1252 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1253 * fence, whereas 965+ only requires a fence if using
1254 * framebuffer compression. For simplicity, we always install
1255 * a fence as the cost is not that onerous.
1257 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1258 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1259 ret
= i915_gem_object_get_fence_reg(obj
);
1261 i915_gem_object_unpin(obj
);
1270 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1271 struct drm_framebuffer
*old_fb
)
1273 struct drm_device
*dev
= crtc
->dev
;
1274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1275 struct drm_i915_master_private
*master_priv
;
1276 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1277 struct intel_framebuffer
*intel_fb
;
1278 struct drm_i915_gem_object
*obj_priv
;
1279 struct drm_gem_object
*obj
;
1280 int pipe
= intel_crtc
->pipe
;
1281 int plane
= intel_crtc
->plane
;
1282 unsigned long Start
, Offset
;
1283 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1284 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1285 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1286 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1287 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1293 DRM_DEBUG_KMS("No FB bound\n");
1302 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1306 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1307 obj
= intel_fb
->obj
;
1308 obj_priv
= to_intel_bo(obj
);
1310 mutex_lock(&dev
->struct_mutex
);
1311 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1313 mutex_unlock(&dev
->struct_mutex
);
1317 ret
= i915_gem_object_set_to_display_plane(obj
);
1319 i915_gem_object_unpin(obj
);
1320 mutex_unlock(&dev
->struct_mutex
);
1324 dspcntr
= I915_READ(dspcntr_reg
);
1325 /* Mask out pixel format bits in case we change it */
1326 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1327 switch (crtc
->fb
->bits_per_pixel
) {
1329 dspcntr
|= DISPPLANE_8BPP
;
1332 if (crtc
->fb
->depth
== 15)
1333 dspcntr
|= DISPPLANE_15_16BPP
;
1335 dspcntr
|= DISPPLANE_16BPP
;
1339 if (crtc
->fb
->depth
== 30)
1340 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
1342 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1345 DRM_ERROR("Unknown color depth\n");
1346 i915_gem_object_unpin(obj
);
1347 mutex_unlock(&dev
->struct_mutex
);
1350 if (IS_I965G(dev
)) {
1351 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1352 dspcntr
|= DISPPLANE_TILED
;
1354 dspcntr
&= ~DISPPLANE_TILED
;
1357 if (HAS_PCH_SPLIT(dev
))
1359 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1361 I915_WRITE(dspcntr_reg
, dspcntr
);
1363 Start
= obj_priv
->gtt_offset
;
1364 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1366 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
1367 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1368 if (IS_I965G(dev
)) {
1369 I915_WRITE(dspbase
, Offset
);
1371 I915_WRITE(dspsurf
, Start
);
1373 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1375 I915_WRITE(dspbase
, Start
+ Offset
);
1379 if ((IS_I965G(dev
) || plane
== 0))
1380 intel_update_fbc(crtc
, &crtc
->mode
);
1382 intel_wait_for_vblank(dev
);
1385 intel_fb
= to_intel_framebuffer(old_fb
);
1386 obj_priv
= to_intel_bo(intel_fb
->obj
);
1387 i915_gem_object_unpin(intel_fb
->obj
);
1389 intel_increase_pllclock(crtc
, true);
1391 mutex_unlock(&dev
->struct_mutex
);
1393 if (!dev
->primary
->master
)
1396 master_priv
= dev
->primary
->master
->driver_priv
;
1397 if (!master_priv
->sarea_priv
)
1401 master_priv
->sarea_priv
->pipeB_x
= x
;
1402 master_priv
->sarea_priv
->pipeB_y
= y
;
1404 master_priv
->sarea_priv
->pipeA_x
= x
;
1405 master_priv
->sarea_priv
->pipeA_y
= y
;
1411 /* Disable the VGA plane that we never use */
1412 static void i915_disable_vga (struct drm_device
*dev
)
1414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1418 if (HAS_PCH_SPLIT(dev
))
1419 vga_reg
= CPU_VGACNTRL
;
1423 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1426 I915_WRITE8(VGA_SR_INDEX
, 1);
1427 sr1
= I915_READ8(VGA_SR_DATA
);
1428 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1431 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1434 static void ironlake_disable_pll_edp (struct drm_crtc
*crtc
)
1436 struct drm_device
*dev
= crtc
->dev
;
1437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1440 DRM_DEBUG_KMS("\n");
1441 dpa_ctl
= I915_READ(DP_A
);
1442 dpa_ctl
&= ~DP_PLL_ENABLE
;
1443 I915_WRITE(DP_A
, dpa_ctl
);
1446 static void ironlake_enable_pll_edp (struct drm_crtc
*crtc
)
1448 struct drm_device
*dev
= crtc
->dev
;
1449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1452 dpa_ctl
= I915_READ(DP_A
);
1453 dpa_ctl
|= DP_PLL_ENABLE
;
1454 I915_WRITE(DP_A
, dpa_ctl
);
1459 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1461 struct drm_device
*dev
= crtc
->dev
;
1462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1466 dpa_ctl
= I915_READ(DP_A
);
1467 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1469 if (clock
< 200000) {
1471 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1472 /* workaround for 160Mhz:
1473 1) program 0x4600c bits 15:0 = 0x8124
1474 2) program 0x46010 bit 0 = 1
1475 3) program 0x46034 bit 24 = 1
1476 4) program 0x64000 bit 14 = 1
1478 temp
= I915_READ(0x4600c);
1480 I915_WRITE(0x4600c, temp
| 0x8124);
1482 temp
= I915_READ(0x46010);
1483 I915_WRITE(0x46010, temp
| 1);
1485 temp
= I915_READ(0x46034);
1486 I915_WRITE(0x46034, temp
| (1 << 24));
1488 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1490 I915_WRITE(DP_A
, dpa_ctl
);
1495 /* The FDI link training functions for ILK/Ibexpeak. */
1496 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1498 struct drm_device
*dev
= crtc
->dev
;
1499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1500 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1501 int pipe
= intel_crtc
->pipe
;
1502 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1503 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1504 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1505 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1506 u32 temp
, tries
= 0;
1508 /* enable CPU FDI TX and PCH FDI RX */
1509 temp
= I915_READ(fdi_tx_reg
);
1510 temp
|= FDI_TX_ENABLE
;
1512 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1513 temp
&= ~FDI_LINK_TRAIN_NONE
;
1514 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1515 I915_WRITE(fdi_tx_reg
, temp
);
1516 I915_READ(fdi_tx_reg
);
1518 temp
= I915_READ(fdi_rx_reg
);
1519 temp
&= ~FDI_LINK_TRAIN_NONE
;
1520 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1521 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1522 I915_READ(fdi_rx_reg
);
1525 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1527 temp
= I915_READ(fdi_rx_imr_reg
);
1528 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1529 temp
&= ~FDI_RX_BIT_LOCK
;
1530 I915_WRITE(fdi_rx_imr_reg
, temp
);
1531 I915_READ(fdi_rx_imr_reg
);
1535 temp
= I915_READ(fdi_rx_iir_reg
);
1536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1538 if ((temp
& FDI_RX_BIT_LOCK
)) {
1539 DRM_DEBUG_KMS("FDI train 1 done.\n");
1540 I915_WRITE(fdi_rx_iir_reg
,
1541 temp
| FDI_RX_BIT_LOCK
);
1548 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1554 temp
= I915_READ(fdi_tx_reg
);
1555 temp
&= ~FDI_LINK_TRAIN_NONE
;
1556 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1557 I915_WRITE(fdi_tx_reg
, temp
);
1559 temp
= I915_READ(fdi_rx_reg
);
1560 temp
&= ~FDI_LINK_TRAIN_NONE
;
1561 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1562 I915_WRITE(fdi_rx_reg
, temp
);
1568 temp
= I915_READ(fdi_rx_iir_reg
);
1569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1571 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1572 I915_WRITE(fdi_rx_iir_reg
,
1573 temp
| FDI_RX_SYMBOL_LOCK
);
1574 DRM_DEBUG_KMS("FDI train 2 done.\n");
1581 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1586 DRM_DEBUG_KMS("FDI train done\n");
1589 static int snb_b_fdi_train_param
[] = {
1590 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1591 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1592 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1593 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1596 /* The FDI link training functions for SNB/Cougarpoint. */
1597 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1599 struct drm_device
*dev
= crtc
->dev
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1602 int pipe
= intel_crtc
->pipe
;
1603 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1604 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1605 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1606 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1609 /* enable CPU FDI TX and PCH FDI RX */
1610 temp
= I915_READ(fdi_tx_reg
);
1611 temp
|= FDI_TX_ENABLE
;
1613 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1614 temp
&= ~FDI_LINK_TRAIN_NONE
;
1615 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1616 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1618 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1619 I915_WRITE(fdi_tx_reg
, temp
);
1620 I915_READ(fdi_tx_reg
);
1622 temp
= I915_READ(fdi_rx_reg
);
1623 if (HAS_PCH_CPT(dev
)) {
1624 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1625 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1627 temp
&= ~FDI_LINK_TRAIN_NONE
;
1628 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1630 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1631 I915_READ(fdi_rx_reg
);
1634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1636 temp
= I915_READ(fdi_rx_imr_reg
);
1637 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1638 temp
&= ~FDI_RX_BIT_LOCK
;
1639 I915_WRITE(fdi_rx_imr_reg
, temp
);
1640 I915_READ(fdi_rx_imr_reg
);
1643 for (i
= 0; i
< 4; i
++ ) {
1644 temp
= I915_READ(fdi_tx_reg
);
1645 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1646 temp
|= snb_b_fdi_train_param
[i
];
1647 I915_WRITE(fdi_tx_reg
, temp
);
1650 temp
= I915_READ(fdi_rx_iir_reg
);
1651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1653 if (temp
& FDI_RX_BIT_LOCK
) {
1654 I915_WRITE(fdi_rx_iir_reg
,
1655 temp
| FDI_RX_BIT_LOCK
);
1656 DRM_DEBUG_KMS("FDI train 1 done.\n");
1661 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1664 temp
= I915_READ(fdi_tx_reg
);
1665 temp
&= ~FDI_LINK_TRAIN_NONE
;
1666 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1668 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1670 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1672 I915_WRITE(fdi_tx_reg
, temp
);
1674 temp
= I915_READ(fdi_rx_reg
);
1675 if (HAS_PCH_CPT(dev
)) {
1676 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1677 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1679 temp
&= ~FDI_LINK_TRAIN_NONE
;
1680 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1682 I915_WRITE(fdi_rx_reg
, temp
);
1685 for (i
= 0; i
< 4; i
++ ) {
1686 temp
= I915_READ(fdi_tx_reg
);
1687 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1688 temp
|= snb_b_fdi_train_param
[i
];
1689 I915_WRITE(fdi_tx_reg
, temp
);
1692 temp
= I915_READ(fdi_rx_iir_reg
);
1693 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1695 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1696 I915_WRITE(fdi_rx_iir_reg
,
1697 temp
| FDI_RX_SYMBOL_LOCK
);
1698 DRM_DEBUG_KMS("FDI train 2 done.\n");
1703 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1705 DRM_DEBUG_KMS("FDI train done.\n");
1708 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1710 struct drm_device
*dev
= crtc
->dev
;
1711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1712 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1713 int pipe
= intel_crtc
->pipe
;
1714 int plane
= intel_crtc
->plane
;
1715 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1716 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1717 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1718 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1719 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1720 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1721 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1722 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1723 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1724 int pf_win_pos
= (pipe
== 0) ? PFA_WIN_POS
: PFB_WIN_POS
;
1725 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1726 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1727 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1728 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1729 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1730 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1731 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1732 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1733 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1734 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1735 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1736 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1737 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
1742 temp
= I915_READ(pipeconf_reg
);
1743 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1745 /* XXX: When our outputs are all unaware of DPMS modes other than off
1746 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1749 case DRM_MODE_DPMS_ON
:
1750 case DRM_MODE_DPMS_STANDBY
:
1751 case DRM_MODE_DPMS_SUSPEND
:
1752 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe
);
1754 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1755 temp
= I915_READ(PCH_LVDS
);
1756 if ((temp
& LVDS_PORT_EN
) == 0) {
1757 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1758 POSTING_READ(PCH_LVDS
);
1763 /* enable eDP PLL */
1764 ironlake_enable_pll_edp(crtc
);
1767 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1768 temp
= I915_READ(fdi_rx_reg
);
1770 * make the BPC in FDI Rx be consistent with that in
1773 temp
&= ~(0x7 << 16);
1774 temp
|= (pipe_bpc
<< 11);
1776 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1777 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
1778 I915_READ(fdi_rx_reg
);
1781 /* Switch from Rawclk to PCDclk */
1782 temp
= I915_READ(fdi_rx_reg
);
1783 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
1784 I915_READ(fdi_rx_reg
);
1787 /* Enable CPU FDI TX PLL, always on for Ironlake */
1788 temp
= I915_READ(fdi_tx_reg
);
1789 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1790 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1791 I915_READ(fdi_tx_reg
);
1796 /* Enable panel fitting for LVDS */
1797 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1798 temp
= I915_READ(pf_ctl_reg
);
1799 I915_WRITE(pf_ctl_reg
, temp
| PF_ENABLE
| PF_FILTER_MED_3x3
);
1801 /* currently full aspect */
1802 I915_WRITE(pf_win_pos
, 0);
1804 I915_WRITE(pf_win_size
,
1805 (dev_priv
->panel_fixed_mode
->hdisplay
<< 16) |
1806 (dev_priv
->panel_fixed_mode
->vdisplay
));
1809 /* Enable CPU pipe */
1810 temp
= I915_READ(pipeconf_reg
);
1811 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1812 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1813 I915_READ(pipeconf_reg
);
1817 /* configure and enable CPU plane */
1818 temp
= I915_READ(dspcntr_reg
);
1819 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1820 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1821 /* Flush the plane changes */
1822 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1826 /* For PCH output, training FDI link */
1828 gen6_fdi_link_train(crtc
);
1830 ironlake_fdi_link_train(crtc
);
1832 /* enable PCH DPLL */
1833 temp
= I915_READ(pch_dpll_reg
);
1834 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1835 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1836 I915_READ(pch_dpll_reg
);
1840 if (HAS_PCH_CPT(dev
)) {
1841 /* Be sure PCH DPLL SEL is set */
1842 temp
= I915_READ(PCH_DPLL_SEL
);
1843 if (trans_dpll_sel
== 0 &&
1844 (temp
& TRANSA_DPLL_ENABLE
) == 0)
1845 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
1846 else if (trans_dpll_sel
== 1 &&
1847 (temp
& TRANSB_DPLL_ENABLE
) == 0)
1848 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
1849 I915_WRITE(PCH_DPLL_SEL
, temp
);
1850 I915_READ(PCH_DPLL_SEL
);
1853 /* set transcoder timing */
1854 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1855 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1856 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
1858 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
1859 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
1860 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
1862 /* enable normal train */
1863 temp
= I915_READ(fdi_tx_reg
);
1864 temp
&= ~FDI_LINK_TRAIN_NONE
;
1865 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1866 FDI_TX_ENHANCE_FRAME_ENABLE
);
1867 I915_READ(fdi_tx_reg
);
1869 temp
= I915_READ(fdi_rx_reg
);
1870 if (HAS_PCH_CPT(dev
)) {
1871 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1872 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
1874 temp
&= ~FDI_LINK_TRAIN_NONE
;
1875 temp
|= FDI_LINK_TRAIN_NONE
;
1877 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
1878 I915_READ(fdi_rx_reg
);
1880 /* wait one idle pattern time */
1883 /* For PCH DP, enable TRANS_DP_CTL */
1884 if (HAS_PCH_CPT(dev
) &&
1885 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
1886 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
1889 reg
= I915_READ(trans_dp_ctl
);
1890 reg
&= ~TRANS_DP_PORT_SEL_MASK
;
1891 reg
= TRANS_DP_OUTPUT_ENABLE
|
1892 TRANS_DP_ENH_FRAMING
|
1893 TRANS_DP_VSYNC_ACTIVE_HIGH
|
1894 TRANS_DP_HSYNC_ACTIVE_HIGH
;
1896 switch (intel_trans_dp_port_sel(crtc
)) {
1898 reg
|= TRANS_DP_PORT_SEL_B
;
1901 reg
|= TRANS_DP_PORT_SEL_C
;
1904 reg
|= TRANS_DP_PORT_SEL_D
;
1907 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1908 reg
|= TRANS_DP_PORT_SEL_B
;
1912 I915_WRITE(trans_dp_ctl
, reg
);
1913 POSTING_READ(trans_dp_ctl
);
1916 /* enable PCH transcoder */
1917 temp
= I915_READ(transconf_reg
);
1919 * make the BPC in transcoder be consistent with
1920 * that in pipeconf reg.
1922 temp
&= ~PIPE_BPC_MASK
;
1924 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
1925 I915_READ(transconf_reg
);
1927 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
1932 intel_crtc_load_lut(crtc
);
1935 case DRM_MODE_DPMS_OFF
:
1936 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe
);
1938 drm_vblank_off(dev
, pipe
);
1939 /* Disable display plane */
1940 temp
= I915_READ(dspcntr_reg
);
1941 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1942 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1943 /* Flush the plane changes */
1944 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1945 I915_READ(dspbase_reg
);
1948 i915_disable_vga(dev
);
1950 /* disable cpu pipe, disable after all planes disabled */
1951 temp
= I915_READ(pipeconf_reg
);
1952 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1953 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1954 I915_READ(pipeconf_reg
);
1956 /* wait for cpu pipe off, pipe state */
1957 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
1963 DRM_DEBUG_KMS("pipe %d off delay\n",
1969 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
1974 temp
= I915_READ(pf_ctl_reg
);
1975 if ((temp
& PF_ENABLE
) != 0) {
1976 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
1977 I915_READ(pf_ctl_reg
);
1979 I915_WRITE(pf_win_size
, 0);
1980 POSTING_READ(pf_win_size
);
1983 /* disable CPU FDI tx and PCH FDI rx */
1984 temp
= I915_READ(fdi_tx_reg
);
1985 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
1986 I915_READ(fdi_tx_reg
);
1988 temp
= I915_READ(fdi_rx_reg
);
1989 /* BPC in FDI rx is consistent with that in pipeconf */
1990 temp
&= ~(0x07 << 16);
1991 temp
|= (pipe_bpc
<< 11);
1992 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
1993 I915_READ(fdi_rx_reg
);
1997 /* still set train pattern 1 */
1998 temp
= I915_READ(fdi_tx_reg
);
1999 temp
&= ~FDI_LINK_TRAIN_NONE
;
2000 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2001 I915_WRITE(fdi_tx_reg
, temp
);
2002 POSTING_READ(fdi_tx_reg
);
2004 temp
= I915_READ(fdi_rx_reg
);
2005 if (HAS_PCH_CPT(dev
)) {
2006 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2007 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2009 temp
&= ~FDI_LINK_TRAIN_NONE
;
2010 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2012 I915_WRITE(fdi_rx_reg
, temp
);
2013 POSTING_READ(fdi_rx_reg
);
2017 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2018 temp
= I915_READ(PCH_LVDS
);
2019 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2020 I915_READ(PCH_LVDS
);
2024 /* disable PCH transcoder */
2025 temp
= I915_READ(transconf_reg
);
2026 if ((temp
& TRANS_ENABLE
) != 0) {
2027 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
2028 I915_READ(transconf_reg
);
2030 /* wait for PCH transcoder off, transcoder state */
2031 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
2037 DRM_DEBUG_KMS("transcoder %d off "
2044 temp
= I915_READ(transconf_reg
);
2045 /* BPC in transcoder is consistent with that in pipeconf */
2046 temp
&= ~PIPE_BPC_MASK
;
2048 I915_WRITE(transconf_reg
, temp
);
2049 I915_READ(transconf_reg
);
2052 if (HAS_PCH_CPT(dev
)) {
2053 /* disable TRANS_DP_CTL */
2054 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2057 reg
= I915_READ(trans_dp_ctl
);
2058 reg
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2059 I915_WRITE(trans_dp_ctl
, reg
);
2060 POSTING_READ(trans_dp_ctl
);
2062 /* disable DPLL_SEL */
2063 temp
= I915_READ(PCH_DPLL_SEL
);
2064 if (trans_dpll_sel
== 0)
2065 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2067 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2068 I915_WRITE(PCH_DPLL_SEL
, temp
);
2069 I915_READ(PCH_DPLL_SEL
);
2073 /* disable PCH DPLL */
2074 temp
= I915_READ(pch_dpll_reg
);
2075 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2076 I915_READ(pch_dpll_reg
);
2079 ironlake_disable_pll_edp(crtc
);
2082 /* Switch from PCDclk to Rawclk */
2083 temp
= I915_READ(fdi_rx_reg
);
2084 temp
&= ~FDI_SEL_PCDCLK
;
2085 I915_WRITE(fdi_rx_reg
, temp
);
2086 I915_READ(fdi_rx_reg
);
2088 /* Disable CPU FDI TX PLL */
2089 temp
= I915_READ(fdi_tx_reg
);
2090 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2091 I915_READ(fdi_tx_reg
);
2094 temp
= I915_READ(fdi_rx_reg
);
2095 temp
&= ~FDI_RX_PLL_ENABLE
;
2096 I915_WRITE(fdi_rx_reg
, temp
);
2097 I915_READ(fdi_rx_reg
);
2099 /* Wait for the clocks to turn off. */
2105 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2107 struct intel_overlay
*overlay
;
2110 if (!enable
&& intel_crtc
->overlay
) {
2111 overlay
= intel_crtc
->overlay
;
2112 mutex_lock(&overlay
->dev
->struct_mutex
);
2114 ret
= intel_overlay_switch_off(overlay
);
2118 ret
= intel_overlay_recover_from_interrupt(overlay
, 0);
2120 /* overlay doesn't react anymore. Usually
2121 * results in a black screen and an unkillable
2124 overlay
->hw_wedged
= HW_WEDGED
;
2128 mutex_unlock(&overlay
->dev
->struct_mutex
);
2130 /* Let userspace switch the overlay on again. In most cases userspace
2131 * has to recompute where to put it anyway. */
2136 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2138 struct drm_device
*dev
= crtc
->dev
;
2139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2141 int pipe
= intel_crtc
->pipe
;
2142 int plane
= intel_crtc
->plane
;
2143 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2144 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2145 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2146 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2149 /* XXX: When our outputs are all unaware of DPMS modes other than off
2150 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2153 case DRM_MODE_DPMS_ON
:
2154 case DRM_MODE_DPMS_STANDBY
:
2155 case DRM_MODE_DPMS_SUSPEND
:
2156 intel_update_watermarks(dev
);
2158 /* Enable the DPLL */
2159 temp
= I915_READ(dpll_reg
);
2160 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2161 I915_WRITE(dpll_reg
, temp
);
2162 I915_READ(dpll_reg
);
2163 /* Wait for the clocks to stabilize. */
2165 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2166 I915_READ(dpll_reg
);
2167 /* Wait for the clocks to stabilize. */
2169 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2170 I915_READ(dpll_reg
);
2171 /* Wait for the clocks to stabilize. */
2175 /* Enable the pipe */
2176 temp
= I915_READ(pipeconf_reg
);
2177 if ((temp
& PIPEACONF_ENABLE
) == 0)
2178 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
2180 /* Enable the plane */
2181 temp
= I915_READ(dspcntr_reg
);
2182 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2183 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
2184 /* Flush the plane changes */
2185 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2188 intel_crtc_load_lut(crtc
);
2190 if ((IS_I965G(dev
) || plane
== 0))
2191 intel_update_fbc(crtc
, &crtc
->mode
);
2193 /* Give the overlay scaler a chance to enable if it's on this pipe */
2194 intel_crtc_dpms_overlay(intel_crtc
, true);
2196 case DRM_MODE_DPMS_OFF
:
2197 intel_update_watermarks(dev
);
2199 /* Give the overlay scaler a chance to disable if it's on this pipe */
2200 intel_crtc_dpms_overlay(intel_crtc
, false);
2201 drm_vblank_off(dev
, pipe
);
2203 if (dev_priv
->cfb_plane
== plane
&&
2204 dev_priv
->display
.disable_fbc
)
2205 dev_priv
->display
.disable_fbc(dev
);
2207 /* Disable the VGA plane that we never use */
2208 i915_disable_vga(dev
);
2210 /* Disable display plane */
2211 temp
= I915_READ(dspcntr_reg
);
2212 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2213 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2214 /* Flush the plane changes */
2215 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2216 I915_READ(dspbase_reg
);
2219 if (!IS_I9XX(dev
)) {
2220 /* Wait for vblank for the disable to take effect */
2221 intel_wait_for_vblank(dev
);
2224 /* Next, disable display pipes */
2225 temp
= I915_READ(pipeconf_reg
);
2226 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2227 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2228 I915_READ(pipeconf_reg
);
2231 /* Wait for vblank for the disable to take effect. */
2232 intel_wait_for_vblank(dev
);
2234 temp
= I915_READ(dpll_reg
);
2235 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
2236 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2237 I915_READ(dpll_reg
);
2240 /* Wait for the clocks to turn off. */
2247 * Sets the power management mode of the pipe and plane.
2249 * This code should probably grow support for turning the cursor off and back
2250 * on appropriately at the same time as we're turning the pipe off/on.
2252 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2254 struct drm_device
*dev
= crtc
->dev
;
2255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2256 struct drm_i915_master_private
*master_priv
;
2257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2258 int pipe
= intel_crtc
->pipe
;
2261 dev_priv
->display
.dpms(crtc
, mode
);
2263 intel_crtc
->dpms_mode
= mode
;
2265 if (!dev
->primary
->master
)
2268 master_priv
= dev
->primary
->master
->driver_priv
;
2269 if (!master_priv
->sarea_priv
)
2272 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2276 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2277 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2280 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2281 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2284 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2289 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
2291 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2292 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2295 static void intel_crtc_commit (struct drm_crtc
*crtc
)
2297 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2298 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2301 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2303 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2304 /* lvds has its own version of prepare see intel_lvds_prepare */
2305 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2308 void intel_encoder_commit (struct drm_encoder
*encoder
)
2310 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2311 /* lvds has its own version of commit see intel_lvds_commit */
2312 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2315 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2316 struct drm_display_mode
*mode
,
2317 struct drm_display_mode
*adjusted_mode
)
2319 struct drm_device
*dev
= crtc
->dev
;
2320 if (HAS_PCH_SPLIT(dev
)) {
2321 /* FDI link clock is fixed at 2.7G */
2322 if (mode
->clock
* 3 > 27000 * 4)
2323 return MODE_CLOCK_HIGH
;
2328 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2333 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2338 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2343 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2347 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2349 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2352 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2353 case GC_DISPLAY_CLOCK_333_MHZ
:
2356 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2362 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2367 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2370 /* Assume that the hardware is in the high speed state. This
2371 * should be the default.
2373 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2374 case GC_CLOCK_133_200
:
2375 case GC_CLOCK_100_200
:
2377 case GC_CLOCK_166_250
:
2379 case GC_CLOCK_100_133
:
2383 /* Shouldn't happen */
2387 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2393 * Return the pipe currently connected to the panel fitter,
2394 * or -1 if the panel fitter is not present or not in use
2396 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2401 /* i830 doesn't have a panel fitter */
2405 pfit_control
= I915_READ(PFIT_CONTROL
);
2407 /* See if the panel fitter is in use */
2408 if ((pfit_control
& PFIT_ENABLE
) == 0)
2411 /* 965 can place panel fitter on either pipe */
2413 return (pfit_control
>> 29) & 0x3;
2415 /* older chips can only use pipe 1 */
2428 fdi_reduce_ratio(u32
*num
, u32
*den
)
2430 while (*num
> 0xffffff || *den
> 0xffffff) {
2436 #define DATA_N 0x800000
2437 #define LINK_N 0x80000
2440 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2441 int link_clock
, struct fdi_m_n
*m_n
)
2445 m_n
->tu
= 64; /* default size */
2447 temp
= (u64
) DATA_N
* pixel_clock
;
2448 temp
= div_u64(temp
, link_clock
);
2449 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2450 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2451 m_n
->gmch_n
= DATA_N
;
2452 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2454 temp
= (u64
) LINK_N
* pixel_clock
;
2455 m_n
->link_m
= div_u64(temp
, link_clock
);
2456 m_n
->link_n
= LINK_N
;
2457 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2461 struct intel_watermark_params
{
2462 unsigned long fifo_size
;
2463 unsigned long max_wm
;
2464 unsigned long default_wm
;
2465 unsigned long guard_size
;
2466 unsigned long cacheline_size
;
2469 /* Pineview has different values for various configs */
2470 static struct intel_watermark_params pineview_display_wm
= {
2471 PINEVIEW_DISPLAY_FIFO
,
2475 PINEVIEW_FIFO_LINE_SIZE
2477 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2478 PINEVIEW_DISPLAY_FIFO
,
2480 PINEVIEW_DFT_HPLLOFF_WM
,
2482 PINEVIEW_FIFO_LINE_SIZE
2484 static struct intel_watermark_params pineview_cursor_wm
= {
2485 PINEVIEW_CURSOR_FIFO
,
2486 PINEVIEW_CURSOR_MAX_WM
,
2487 PINEVIEW_CURSOR_DFT_WM
,
2488 PINEVIEW_CURSOR_GUARD_WM
,
2489 PINEVIEW_FIFO_LINE_SIZE
,
2491 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2492 PINEVIEW_CURSOR_FIFO
,
2493 PINEVIEW_CURSOR_MAX_WM
,
2494 PINEVIEW_CURSOR_DFT_WM
,
2495 PINEVIEW_CURSOR_GUARD_WM
,
2496 PINEVIEW_FIFO_LINE_SIZE
2498 static struct intel_watermark_params g4x_wm_info
= {
2505 static struct intel_watermark_params i945_wm_info
= {
2512 static struct intel_watermark_params i915_wm_info
= {
2519 static struct intel_watermark_params i855_wm_info
= {
2526 static struct intel_watermark_params i830_wm_info
= {
2534 static struct intel_watermark_params ironlake_display_wm_info
= {
2542 static struct intel_watermark_params ironlake_display_srwm_info
= {
2543 ILK_DISPLAY_SR_FIFO
,
2544 ILK_DISPLAY_MAX_SRWM
,
2545 ILK_DISPLAY_DFT_SRWM
,
2550 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2552 ILK_CURSOR_MAX_SRWM
,
2553 ILK_CURSOR_DFT_SRWM
,
2559 * intel_calculate_wm - calculate watermark level
2560 * @clock_in_khz: pixel clock
2561 * @wm: chip FIFO params
2562 * @pixel_size: display pixel size
2563 * @latency_ns: memory latency for the platform
2565 * Calculate the watermark level (the level at which the display plane will
2566 * start fetching from memory again). Each chip has a different display
2567 * FIFO size and allocation, so the caller needs to figure that out and pass
2568 * in the correct intel_watermark_params structure.
2570 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2571 * on the pixel size. When it reaches the watermark level, it'll start
2572 * fetching FIFO line sized based chunks from memory until the FIFO fills
2573 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2574 * will occur, and a display engine hang could result.
2576 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2577 struct intel_watermark_params
*wm
,
2579 unsigned long latency_ns
)
2581 long entries_required
, wm_size
;
2584 * Note: we need to make sure we don't overflow for various clock &
2586 * clocks go from a few thousand to several hundred thousand.
2587 * latency is usually a few thousand
2589 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2591 entries_required
/= wm
->cacheline_size
;
2593 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2595 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2597 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2599 /* Don't promote wm_size to unsigned... */
2600 if (wm_size
> (long)wm
->max_wm
)
2601 wm_size
= wm
->max_wm
;
2603 wm_size
= wm
->default_wm
;
2607 struct cxsr_latency
{
2609 unsigned long fsb_freq
;
2610 unsigned long mem_freq
;
2611 unsigned long display_sr
;
2612 unsigned long display_hpll_disable
;
2613 unsigned long cursor_sr
;
2614 unsigned long cursor_hpll_disable
;
2617 static struct cxsr_latency cxsr_latency_table
[] = {
2618 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2619 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2620 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2622 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2623 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2624 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2626 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2627 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2628 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2630 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2631 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2632 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2634 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2635 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2636 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2638 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2639 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2640 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2643 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int fsb
,
2647 struct cxsr_latency
*latency
;
2649 if (fsb
== 0 || mem
== 0)
2652 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2653 latency
= &cxsr_latency_table
[i
];
2654 if (is_desktop
== latency
->is_desktop
&&
2655 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2659 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2664 static void pineview_disable_cxsr(struct drm_device
*dev
)
2666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2669 /* deactivate cxsr */
2670 reg
= I915_READ(DSPFW3
);
2671 reg
&= ~(PINEVIEW_SELF_REFRESH_EN
);
2672 I915_WRITE(DSPFW3
, reg
);
2673 DRM_INFO("Big FIFO is disabled\n");
2677 * Latency for FIFO fetches is dependent on several factors:
2678 * - memory configuration (speed, channels)
2680 * - current MCH state
2681 * It can be fairly high in some situations, so here we assume a fairly
2682 * pessimal value. It's a tradeoff between extra memory fetches (if we
2683 * set this value too high, the FIFO will fetch frequently to stay full)
2684 * and power consumption (set it too low to save power and we might see
2685 * FIFO underruns and display "flicker").
2687 * A value of 5us seems to be a good balance; safe for very low end
2688 * platforms but not overly aggressive on lower latency configs.
2690 static const int latency_ns
= 5000;
2692 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2695 uint32_t dsparb
= I915_READ(DSPARB
);
2699 size
= dsparb
& 0x7f;
2701 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) -
2704 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2705 plane
? "B" : "A", size
);
2710 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 uint32_t dsparb
= I915_READ(DSPARB
);
2717 size
= dsparb
& 0x1ff;
2719 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) -
2721 size
>>= 1; /* Convert to cachelines */
2723 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2724 plane
? "B" : "A", size
);
2729 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2732 uint32_t dsparb
= I915_READ(DSPARB
);
2735 size
= dsparb
& 0x7f;
2736 size
>>= 2; /* Convert to cachelines */
2738 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2745 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
2747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2748 uint32_t dsparb
= I915_READ(DSPARB
);
2751 size
= dsparb
& 0x7f;
2752 size
>>= 1; /* Convert to cachelines */
2754 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2755 plane
? "B" : "A", size
);
2760 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
2761 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2766 struct cxsr_latency
*latency
;
2769 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->fsb_freq
,
2770 dev_priv
->mem_freq
);
2772 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2773 pineview_disable_cxsr(dev
);
2777 if (!planea_clock
|| !planeb_clock
) {
2778 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2781 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
2782 pixel_size
, latency
->display_sr
);
2783 reg
= I915_READ(DSPFW1
);
2784 reg
&= ~DSPFW_SR_MASK
;
2785 reg
|= wm
<< DSPFW_SR_SHIFT
;
2786 I915_WRITE(DSPFW1
, reg
);
2787 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
2790 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
2791 pixel_size
, latency
->cursor_sr
);
2792 reg
= I915_READ(DSPFW3
);
2793 reg
&= ~DSPFW_CURSOR_SR_MASK
;
2794 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
2795 I915_WRITE(DSPFW3
, reg
);
2797 /* Display HPLL off SR */
2798 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
2799 pixel_size
, latency
->display_hpll_disable
);
2800 reg
= I915_READ(DSPFW3
);
2801 reg
&= ~DSPFW_HPLL_SR_MASK
;
2802 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
2803 I915_WRITE(DSPFW3
, reg
);
2805 /* cursor HPLL off SR */
2806 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
2807 pixel_size
, latency
->cursor_hpll_disable
);
2808 reg
= I915_READ(DSPFW3
);
2809 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
2810 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
2811 I915_WRITE(DSPFW3
, reg
);
2812 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
2815 reg
= I915_READ(DSPFW3
);
2816 reg
|= PINEVIEW_SELF_REFRESH_EN
;
2817 I915_WRITE(DSPFW3
, reg
);
2818 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2820 pineview_disable_cxsr(dev
);
2821 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2825 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
2826 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2829 int total_size
, cacheline_size
;
2830 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
2831 struct intel_watermark_params planea_params
, planeb_params
;
2832 unsigned long line_time_us
;
2833 int sr_clock
, sr_entries
= 0, entries_required
;
2835 /* Create copies of the base settings for each pipe */
2836 planea_params
= planeb_params
= g4x_wm_info
;
2838 /* Grab a couple of global values before we overwrite them */
2839 total_size
= planea_params
.fifo_size
;
2840 cacheline_size
= planea_params
.cacheline_size
;
2843 * Note: we need to make sure we don't overflow for various clock &
2845 * clocks go from a few thousand to several hundred thousand.
2846 * latency is usually a few thousand
2848 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
2850 entries_required
/= G4X_FIFO_LINE_SIZE
;
2851 planea_wm
= entries_required
+ planea_params
.guard_size
;
2853 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
2855 entries_required
/= G4X_FIFO_LINE_SIZE
;
2856 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
2858 cursora_wm
= cursorb_wm
= 16;
2861 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2863 /* Calc sr entries for one plane configs */
2864 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2865 /* self-refresh has much higher latency */
2866 static const int sr_latency_ns
= 12000;
2868 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2869 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2871 /* Use ns/us then divide to preserve precision */
2872 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2873 pixel_size
* sr_hdisplay
) / 1000;
2874 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2875 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2876 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2878 /* Turn off self refresh if both pipes are enabled */
2879 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2883 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2884 planea_wm
, planeb_wm
, sr_entries
);
2889 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
2890 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
2891 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
2892 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
2893 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
2894 /* HPLL off in SR has some issues on G4x... disable it */
2895 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
2896 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
2899 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
2900 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2903 unsigned long line_time_us
;
2904 int sr_clock
, sr_entries
, srwm
= 1;
2906 /* Calc sr entries for one plane configs */
2907 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2908 /* self-refresh has much higher latency */
2909 static const int sr_latency_ns
= 12000;
2911 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2912 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2914 /* Use ns/us then divide to preserve precision */
2915 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2916 pixel_size
* sr_hdisplay
) / 1000;
2917 sr_entries
= roundup(sr_entries
/ I915_FIFO_LINE_SIZE
, 1);
2918 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2919 srwm
= I945_FIFO_SIZE
- sr_entries
;
2923 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2925 /* Turn off self refresh if both pipes are enabled */
2926 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2930 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2933 /* 965 has limitations... */
2934 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
2936 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
2939 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
2940 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2945 int total_size
, cacheline_size
, cwm
, srwm
= 1;
2946 int planea_wm
, planeb_wm
;
2947 struct intel_watermark_params planea_params
, planeb_params
;
2948 unsigned long line_time_us
;
2949 int sr_clock
, sr_entries
= 0;
2951 /* Create copies of the base settings for each pipe */
2952 if (IS_I965GM(dev
) || IS_I945GM(dev
))
2953 planea_params
= planeb_params
= i945_wm_info
;
2954 else if (IS_I9XX(dev
))
2955 planea_params
= planeb_params
= i915_wm_info
;
2957 planea_params
= planeb_params
= i855_wm_info
;
2959 /* Grab a couple of global values before we overwrite them */
2960 total_size
= planea_params
.fifo_size
;
2961 cacheline_size
= planea_params
.cacheline_size
;
2963 /* Update per-plane FIFO sizes */
2964 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
2965 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
2967 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
2968 pixel_size
, latency_ns
);
2969 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
2970 pixel_size
, latency_ns
);
2971 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2974 * Overlay gets an aggressive default since video jitter is bad.
2978 /* Calc sr entries for one plane configs */
2979 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
2980 (!planea_clock
|| !planeb_clock
)) {
2981 /* self-refresh has much higher latency */
2982 static const int sr_latency_ns
= 6000;
2984 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2985 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2987 /* Use ns/us then divide to preserve precision */
2988 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2989 pixel_size
* sr_hdisplay
) / 1000;
2990 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2991 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
2992 srwm
= total_size
- sr_entries
;
2996 if (IS_I945G(dev
) || IS_I945GM(dev
))
2997 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
2998 else if (IS_I915GM(dev
)) {
2999 /* 915M has a smaller SRWM field */
3000 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3001 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3004 /* Turn off self refresh if both pipes are enabled */
3005 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3006 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3008 } else if (IS_I915GM(dev
)) {
3009 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3013 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3014 planea_wm
, planeb_wm
, cwm
, srwm
);
3016 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3017 fwater_hi
= (cwm
& 0x1f);
3019 /* Set request length to 8 cachelines per fetch */
3020 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3021 fwater_hi
= fwater_hi
| (1 << 8);
3023 I915_WRITE(FW_BLC
, fwater_lo
);
3024 I915_WRITE(FW_BLC2
, fwater_hi
);
3027 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3028 int unused2
, int pixel_size
)
3030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3031 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3034 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3036 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3037 pixel_size
, latency_ns
);
3038 fwater_lo
|= (3<<8) | planea_wm
;
3040 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3042 I915_WRITE(FW_BLC
, fwater_lo
);
3045 #define ILK_LP0_PLANE_LATENCY 700
3047 static void ironlake_update_wm(struct drm_device
*dev
, int planea_clock
,
3048 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
3050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3051 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3052 int sr_wm
, cursor_wm
;
3053 unsigned long line_time_us
;
3054 int sr_clock
, entries_required
;
3057 /* Calculate and update the watermark for plane A */
3059 entries_required
= ((planea_clock
/ 1000) * pixel_size
*
3060 ILK_LP0_PLANE_LATENCY
) / 1000;
3061 entries_required
= DIV_ROUND_UP(entries_required
,
3062 ironlake_display_wm_info
.cacheline_size
);
3063 planea_wm
= entries_required
+
3064 ironlake_display_wm_info
.guard_size
;
3066 if (planea_wm
> (int)ironlake_display_wm_info
.max_wm
)
3067 planea_wm
= ironlake_display_wm_info
.max_wm
;
3070 reg_value
= I915_READ(WM0_PIPEA_ILK
);
3071 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3072 reg_value
|= (planea_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3073 (cursora_wm
& WM0_PIPE_CURSOR_MASK
);
3074 I915_WRITE(WM0_PIPEA_ILK
, reg_value
);
3075 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3076 "cursor: %d\n", planea_wm
, cursora_wm
);
3078 /* Calculate and update the watermark for plane B */
3080 entries_required
= ((planeb_clock
/ 1000) * pixel_size
*
3081 ILK_LP0_PLANE_LATENCY
) / 1000;
3082 entries_required
= DIV_ROUND_UP(entries_required
,
3083 ironlake_display_wm_info
.cacheline_size
);
3084 planeb_wm
= entries_required
+
3085 ironlake_display_wm_info
.guard_size
;
3087 if (planeb_wm
> (int)ironlake_display_wm_info
.max_wm
)
3088 planeb_wm
= ironlake_display_wm_info
.max_wm
;
3091 reg_value
= I915_READ(WM0_PIPEB_ILK
);
3092 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3093 reg_value
|= (planeb_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3094 (cursorb_wm
& WM0_PIPE_CURSOR_MASK
);
3095 I915_WRITE(WM0_PIPEB_ILK
, reg_value
);
3096 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3097 "cursor: %d\n", planeb_wm
, cursorb_wm
);
3101 * Calculate and update the self-refresh watermark only when one
3102 * display plane is used.
3104 if (!planea_clock
|| !planeb_clock
) {
3106 /* Read the self-refresh latency. The unit is 0.5us */
3107 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3109 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3110 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
3112 /* Use ns/us then divide to preserve precision */
3113 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3116 /* calculate the self-refresh watermark for display plane */
3117 entries_required
= line_count
* sr_hdisplay
* pixel_size
;
3118 entries_required
= DIV_ROUND_UP(entries_required
,
3119 ironlake_display_srwm_info
.cacheline_size
);
3120 sr_wm
= entries_required
+
3121 ironlake_display_srwm_info
.guard_size
;
3123 /* calculate the self-refresh watermark for display cursor */
3124 entries_required
= line_count
* pixel_size
* 64;
3125 entries_required
= DIV_ROUND_UP(entries_required
,
3126 ironlake_cursor_srwm_info
.cacheline_size
);
3127 cursor_wm
= entries_required
+
3128 ironlake_cursor_srwm_info
.guard_size
;
3130 /* configure watermark and enable self-refresh */
3131 reg_value
= I915_READ(WM1_LP_ILK
);
3132 reg_value
&= ~(WM1_LP_LATENCY_MASK
| WM1_LP_SR_MASK
|
3133 WM1_LP_CURSOR_MASK
);
3134 reg_value
|= WM1_LP_SR_EN
|
3135 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3136 (sr_wm
<< WM1_LP_SR_SHIFT
) | cursor_wm
;
3138 I915_WRITE(WM1_LP_ILK
, reg_value
);
3139 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3140 "cursor %d\n", sr_wm
, cursor_wm
);
3143 /* Turn off self refresh if both pipes are enabled */
3144 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
3148 * intel_update_watermarks - update FIFO watermark values based on current modes
3150 * Calculate watermark values for the various WM regs based on current mode
3151 * and plane configuration.
3153 * There are several cases to deal with here:
3154 * - normal (i.e. non-self-refresh)
3155 * - self-refresh (SR) mode
3156 * - lines are large relative to FIFO size (buffer can hold up to 2)
3157 * - lines are small relative to FIFO size (buffer can hold more than 2
3158 * lines), so need to account for TLB latency
3160 * The normal calculation is:
3161 * watermark = dotclock * bytes per pixel * latency
3162 * where latency is platform & configuration dependent (we assume pessimal
3165 * The SR calculation is:
3166 * watermark = (trunc(latency/line time)+1) * surface width *
3169 * line time = htotal / dotclock
3170 * and latency is assumed to be high, as above.
3172 * The final value programmed to the register should always be rounded up,
3173 * and include an extra 2 entries to account for clock crossings.
3175 * We don't use the sprite, so we can ignore that. And on Crestline we have
3176 * to set the non-SR watermarks to 8.
3178 static void intel_update_watermarks(struct drm_device
*dev
)
3180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3181 struct drm_crtc
*crtc
;
3182 struct intel_crtc
*intel_crtc
;
3183 int sr_hdisplay
= 0;
3184 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3185 int enabled
= 0, pixel_size
= 0;
3187 if (!dev_priv
->display
.update_wm
)
3190 /* Get the clock config from both planes */
3191 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3192 intel_crtc
= to_intel_crtc(crtc
);
3193 if (crtc
->enabled
) {
3195 if (intel_crtc
->plane
== 0) {
3196 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3197 intel_crtc
->pipe
, crtc
->mode
.clock
);
3198 planea_clock
= crtc
->mode
.clock
;
3200 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3201 intel_crtc
->pipe
, crtc
->mode
.clock
);
3202 planeb_clock
= crtc
->mode
.clock
;
3204 sr_hdisplay
= crtc
->mode
.hdisplay
;
3205 sr_clock
= crtc
->mode
.clock
;
3207 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3209 pixel_size
= 4; /* by default */
3216 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3217 sr_hdisplay
, pixel_size
);
3220 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3221 struct drm_display_mode
*mode
,
3222 struct drm_display_mode
*adjusted_mode
,
3224 struct drm_framebuffer
*old_fb
)
3226 struct drm_device
*dev
= crtc
->dev
;
3227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3229 int pipe
= intel_crtc
->pipe
;
3230 int plane
= intel_crtc
->plane
;
3231 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
3232 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3233 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
3234 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
3235 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
3236 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
3237 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
3238 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
3239 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
3240 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
3241 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
3242 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
3243 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
3244 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
3245 int refclk
, num_connectors
= 0;
3246 intel_clock_t clock
, reduced_clock
;
3247 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3248 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3249 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3250 bool is_edp
= false;
3251 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3252 struct drm_encoder
*encoder
;
3253 struct intel_encoder
*intel_encoder
= NULL
;
3254 const intel_limit_t
*limit
;
3256 struct fdi_m_n m_n
= {0};
3257 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
3258 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
3259 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
3260 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
3261 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
3262 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
3263 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
3264 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
3265 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
3266 int lvds_reg
= LVDS
;
3268 int sdvo_pixel_multiply
;
3271 drm_vblank_pre_modeset(dev
, pipe
);
3273 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
3275 if (!encoder
|| encoder
->crtc
!= crtc
)
3278 intel_encoder
= enc_to_intel_encoder(encoder
);
3280 switch (intel_encoder
->type
) {
3281 case INTEL_OUTPUT_LVDS
:
3284 case INTEL_OUTPUT_SDVO
:
3285 case INTEL_OUTPUT_HDMI
:
3287 if (intel_encoder
->needs_tv_clock
)
3290 case INTEL_OUTPUT_DVO
:
3293 case INTEL_OUTPUT_TVOUT
:
3296 case INTEL_OUTPUT_ANALOG
:
3299 case INTEL_OUTPUT_DISPLAYPORT
:
3302 case INTEL_OUTPUT_EDP
:
3310 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3311 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3312 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3314 } else if (IS_I9XX(dev
)) {
3316 if (HAS_PCH_SPLIT(dev
))
3317 refclk
= 120000; /* 120Mhz refclk */
3324 * Returns a set of divisors for the desired target clock with the given
3325 * refclk, or FALSE. The returned values represent the clock equation:
3326 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3328 limit
= intel_limit(crtc
);
3329 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3331 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3332 drm_vblank_post_modeset(dev
, pipe
);
3336 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3337 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3338 dev_priv
->lvds_downclock
,
3341 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3343 * If the different P is found, it means that we can't
3344 * switch the display clock by using the FP0/FP1.
3345 * In such case we will disable the LVDS downclock
3348 DRM_DEBUG_KMS("Different P is found for "
3349 "LVDS clock/downclock\n");
3350 has_reduced_clock
= 0;
3353 /* SDVO TV has fixed PLL values depend on its clock range,
3354 this mirrors vbios setting. */
3355 if (is_sdvo
&& is_tv
) {
3356 if (adjusted_mode
->clock
>= 100000
3357 && adjusted_mode
->clock
< 140500) {
3363 } else if (adjusted_mode
->clock
>= 140500
3364 && adjusted_mode
->clock
<= 200000) {
3374 if (HAS_PCH_SPLIT(dev
)) {
3375 int lane
= 0, link_bw
, bpp
;
3376 /* eDP doesn't require FDI link, so just set DP M/N
3377 according to current link config */
3379 target_clock
= mode
->clock
;
3380 intel_edp_link_config(intel_encoder
,
3383 /* DP over FDI requires target mode clock
3384 instead of link clock */
3386 target_clock
= mode
->clock
;
3388 target_clock
= adjusted_mode
->clock
;
3392 /* determine panel color depth */
3393 temp
= I915_READ(pipeconf_reg
);
3394 temp
&= ~PIPE_BPC_MASK
;
3396 int lvds_reg
= I915_READ(PCH_LVDS
);
3397 /* the BPC will be 6 if it is 18-bit LVDS panel */
3398 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3402 } else if (is_edp
) {
3403 switch (dev_priv
->edp_bpp
/3) {
3419 I915_WRITE(pipeconf_reg
, temp
);
3420 I915_READ(pipeconf_reg
);
3422 switch (temp
& PIPE_BPC_MASK
) {
3436 DRM_ERROR("unknown pipe bpc value\n");
3442 * Account for spread spectrum to avoid
3443 * oversubscribing the link. Max center spread
3444 * is 2.5%; use 5% for safety's sake.
3446 u32 bps
= target_clock
* bpp
* 21 / 20;
3447 lane
= bps
/ (link_bw
* 8) + 1;
3450 intel_crtc
->fdi_lanes
= lane
;
3452 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3455 /* Ironlake: try to setup display ref clock before DPLL
3456 * enabling. This is only under driver's control after
3457 * PCH B stepping, previous chipset stepping should be
3458 * ignoring this setting.
3460 if (HAS_PCH_SPLIT(dev
)) {
3461 temp
= I915_READ(PCH_DREF_CONTROL
);
3462 /* Always enable nonspread source */
3463 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3464 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3465 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3466 POSTING_READ(PCH_DREF_CONTROL
);
3468 temp
&= ~DREF_SSC_SOURCE_MASK
;
3469 temp
|= DREF_SSC_SOURCE_ENABLE
;
3470 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3471 POSTING_READ(PCH_DREF_CONTROL
);
3476 if (dev_priv
->lvds_use_ssc
) {
3477 temp
|= DREF_SSC1_ENABLE
;
3478 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3479 POSTING_READ(PCH_DREF_CONTROL
);
3483 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3484 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3485 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3486 POSTING_READ(PCH_DREF_CONTROL
);
3488 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3489 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3490 POSTING_READ(PCH_DREF_CONTROL
);
3495 if (IS_PINEVIEW(dev
)) {
3496 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3497 if (has_reduced_clock
)
3498 fp2
= (1 << reduced_clock
.n
) << 16 |
3499 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3501 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3502 if (has_reduced_clock
)
3503 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3507 if (!HAS_PCH_SPLIT(dev
))
3508 dpll
= DPLL_VGA_MODE_DIS
;
3512 dpll
|= DPLLB_MODE_LVDS
;
3514 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3516 dpll
|= DPLL_DVO_HIGH_SPEED
;
3517 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3518 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3519 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3520 else if (HAS_PCH_SPLIT(dev
))
3521 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3524 dpll
|= DPLL_DVO_HIGH_SPEED
;
3526 /* compute bitmask from p1 value */
3527 if (IS_PINEVIEW(dev
))
3528 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3530 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3532 if (HAS_PCH_SPLIT(dev
))
3533 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3534 if (IS_G4X(dev
) && has_reduced_clock
)
3535 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3539 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3542 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3545 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3548 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3551 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
))
3552 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3555 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3558 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3560 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3562 dpll
|= PLL_P2_DIVIDE_BY_4
;
3566 if (is_sdvo
&& is_tv
)
3567 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3569 /* XXX: just matching BIOS for now */
3570 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3572 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3573 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3575 dpll
|= PLL_REF_INPUT_DREFCLK
;
3577 /* setup pipeconf */
3578 pipeconf
= I915_READ(pipeconf_reg
);
3580 /* Set up the display plane register */
3581 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3583 /* Ironlake's plane is forced to pipe, bit 24 is to
3584 enable color space conversion */
3585 if (!HAS_PCH_SPLIT(dev
)) {
3587 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3589 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3592 if (pipe
== 0 && !IS_I965G(dev
)) {
3593 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3596 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3600 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3601 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3603 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3606 /* Disable the panel fitter if it was on our pipe */
3607 if (!HAS_PCH_SPLIT(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3608 I915_WRITE(PFIT_CONTROL
, 0);
3610 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3611 drm_mode_debug_printmodeline(mode
);
3613 /* assign to Ironlake registers */
3614 if (HAS_PCH_SPLIT(dev
)) {
3615 fp_reg
= pch_fp_reg
;
3616 dpll_reg
= pch_dpll_reg
;
3620 ironlake_disable_pll_edp(crtc
);
3621 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
3622 I915_WRITE(fp_reg
, fp
);
3623 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3624 I915_READ(dpll_reg
);
3628 /* enable transcoder DPLL */
3629 if (HAS_PCH_CPT(dev
)) {
3630 temp
= I915_READ(PCH_DPLL_SEL
);
3631 if (trans_dpll_sel
== 0)
3632 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
3634 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3635 I915_WRITE(PCH_DPLL_SEL
, temp
);
3636 I915_READ(PCH_DPLL_SEL
);
3640 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3641 * This is an exception to the general rule that mode_set doesn't turn
3647 if (HAS_PCH_SPLIT(dev
))
3648 lvds_reg
= PCH_LVDS
;
3650 lvds
= I915_READ(lvds_reg
);
3651 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3653 if (HAS_PCH_CPT(dev
))
3654 lvds
|= PORT_TRANS_B_SEL_CPT
;
3656 lvds
|= LVDS_PIPEB_SELECT
;
3658 if (HAS_PCH_CPT(dev
))
3659 lvds
&= ~PORT_TRANS_SEL_MASK
;
3661 lvds
&= ~LVDS_PIPEB_SELECT
;
3663 /* set the corresponsding LVDS_BORDER bit */
3664 lvds
|= dev_priv
->lvds_border_bits
;
3665 /* Set the B0-B3 data pairs corresponding to whether we're going to
3666 * set the DPLLs for dual-channel mode or not.
3669 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3671 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3673 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3674 * appropriately here, but we need to look more thoroughly into how
3675 * panels behave in the two modes.
3677 /* set the dithering flag */
3678 if (IS_I965G(dev
)) {
3679 if (dev_priv
->lvds_dither
) {
3680 if (HAS_PCH_SPLIT(dev
))
3681 pipeconf
|= PIPE_ENABLE_DITHER
;
3683 lvds
|= LVDS_ENABLE_DITHER
;
3685 if (HAS_PCH_SPLIT(dev
))
3686 pipeconf
&= ~PIPE_ENABLE_DITHER
;
3688 lvds
&= ~LVDS_ENABLE_DITHER
;
3691 I915_WRITE(lvds_reg
, lvds
);
3692 I915_READ(lvds_reg
);
3695 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3696 else if (HAS_PCH_SPLIT(dev
)) {
3697 /* For non-DP output, clear any trans DP clock recovery setting.*/
3699 I915_WRITE(TRANSA_DATA_M1
, 0);
3700 I915_WRITE(TRANSA_DATA_N1
, 0);
3701 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
3702 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
3704 I915_WRITE(TRANSB_DATA_M1
, 0);
3705 I915_WRITE(TRANSB_DATA_N1
, 0);
3706 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
3707 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
3712 I915_WRITE(fp_reg
, fp
);
3713 I915_WRITE(dpll_reg
, dpll
);
3714 I915_READ(dpll_reg
);
3715 /* Wait for the clocks to stabilize. */
3718 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
)) {
3720 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3721 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
3722 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
3724 I915_WRITE(dpll_md_reg
, 0);
3726 /* write it again -- the BIOS does, after all */
3727 I915_WRITE(dpll_reg
, dpll
);
3729 I915_READ(dpll_reg
);
3730 /* Wait for the clocks to stabilize. */
3734 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
3735 I915_WRITE(fp_reg
+ 4, fp2
);
3736 intel_crtc
->lowfreq_avail
= true;
3737 if (HAS_PIPE_CXSR(dev
)) {
3738 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3739 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
3742 I915_WRITE(fp_reg
+ 4, fp
);
3743 intel_crtc
->lowfreq_avail
= false;
3744 if (HAS_PIPE_CXSR(dev
)) {
3745 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3746 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
3750 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
3751 ((adjusted_mode
->crtc_htotal
- 1) << 16));
3752 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
3753 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
3754 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
3755 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
3756 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
3757 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
3758 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
3759 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
3760 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
3761 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
3762 /* pipesrc and dspsize control the size that is scaled from, which should
3763 * always be the user's requested size.
3765 if (!HAS_PCH_SPLIT(dev
)) {
3766 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
3767 (mode
->hdisplay
- 1));
3768 I915_WRITE(dsppos_reg
, 0);
3770 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
3772 if (HAS_PCH_SPLIT(dev
)) {
3773 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
3774 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
3775 I915_WRITE(link_m1_reg
, m_n
.link_m
);
3776 I915_WRITE(link_n1_reg
, m_n
.link_n
);
3779 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
3781 /* enable FDI RX PLL too */
3782 temp
= I915_READ(fdi_rx_reg
);
3783 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
3784 I915_READ(fdi_rx_reg
);
3787 /* enable FDI TX PLL too */
3788 temp
= I915_READ(fdi_tx_reg
);
3789 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
3790 I915_READ(fdi_tx_reg
);
3792 /* enable FDI RX PCDCLK */
3793 temp
= I915_READ(fdi_rx_reg
);
3794 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
3795 I915_READ(fdi_rx_reg
);
3800 I915_WRITE(pipeconf_reg
, pipeconf
);
3801 I915_READ(pipeconf_reg
);
3803 intel_wait_for_vblank(dev
);
3805 if (IS_IRONLAKE(dev
)) {
3806 /* enable address swizzle for tiling buffer */
3807 temp
= I915_READ(DISP_ARB_CTL
);
3808 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
3811 I915_WRITE(dspcntr_reg
, dspcntr
);
3813 /* Flush the plane changes */
3814 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
3816 if ((IS_I965G(dev
) || plane
== 0))
3817 intel_update_fbc(crtc
, &crtc
->mode
);
3819 intel_update_watermarks(dev
);
3821 drm_vblank_post_modeset(dev
, pipe
);
3826 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3827 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3829 struct drm_device
*dev
= crtc
->dev
;
3830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3831 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3832 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
3835 /* The clocks have to be on to load the palette. */
3839 /* use legacy palette for Ironlake */
3840 if (HAS_PCH_SPLIT(dev
))
3841 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
3844 for (i
= 0; i
< 256; i
++) {
3845 I915_WRITE(palreg
+ 4 * i
,
3846 (intel_crtc
->lut_r
[i
] << 16) |
3847 (intel_crtc
->lut_g
[i
] << 8) |
3848 intel_crtc
->lut_b
[i
]);
3852 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
3853 struct drm_file
*file_priv
,
3855 uint32_t width
, uint32_t height
)
3857 struct drm_device
*dev
= crtc
->dev
;
3858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3860 struct drm_gem_object
*bo
;
3861 struct drm_i915_gem_object
*obj_priv
;
3862 int pipe
= intel_crtc
->pipe
;
3863 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
3864 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
3865 uint32_t temp
= I915_READ(control
);
3869 DRM_DEBUG_KMS("\n");
3871 /* if we want to turn off the cursor ignore width and height */
3873 DRM_DEBUG_KMS("cursor off\n");
3874 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3875 temp
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
3876 temp
|= CURSOR_MODE_DISABLE
;
3878 temp
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
3882 mutex_lock(&dev
->struct_mutex
);
3886 /* Currently we only support 64x64 cursors */
3887 if (width
!= 64 || height
!= 64) {
3888 DRM_ERROR("we currently only support 64x64 cursors\n");
3892 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
3896 obj_priv
= to_intel_bo(bo
);
3898 if (bo
->size
< width
* height
* 4) {
3899 DRM_ERROR("buffer is to small\n");
3904 /* we only need to pin inside GTT if cursor is non-phy */
3905 mutex_lock(&dev
->struct_mutex
);
3906 if (!dev_priv
->info
->cursor_needs_physical
) {
3907 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
3909 DRM_ERROR("failed to pin cursor bo\n");
3912 addr
= obj_priv
->gtt_offset
;
3914 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
3916 DRM_ERROR("failed to attach phys object\n");
3919 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
3923 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
3925 /* Hooray for CUR*CNTR differences */
3926 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3927 temp
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
3928 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
3929 temp
|= (pipe
<< 28); /* Connect to correct pipe */
3931 temp
&= ~(CURSOR_FORMAT_MASK
);
3932 temp
|= CURSOR_ENABLE
;
3933 temp
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
3937 I915_WRITE(control
, temp
);
3938 I915_WRITE(base
, addr
);
3940 if (intel_crtc
->cursor_bo
) {
3941 if (dev_priv
->info
->cursor_needs_physical
) {
3942 if (intel_crtc
->cursor_bo
!= bo
)
3943 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
3945 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
3946 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
3949 mutex_unlock(&dev
->struct_mutex
);
3951 intel_crtc
->cursor_addr
= addr
;
3952 intel_crtc
->cursor_bo
= bo
;
3956 mutex_unlock(&dev
->struct_mutex
);
3958 drm_gem_object_unreference_unlocked(bo
);
3962 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
3964 struct drm_device
*dev
= crtc
->dev
;
3965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3966 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3967 struct intel_framebuffer
*intel_fb
;
3968 int pipe
= intel_crtc
->pipe
;
3973 intel_fb
= to_intel_framebuffer(crtc
->fb
);
3974 intel_mark_busy(dev
, intel_fb
->obj
);
3978 temp
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
3982 temp
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
3986 temp
|= x
<< CURSOR_X_SHIFT
;
3987 temp
|= y
<< CURSOR_Y_SHIFT
;
3989 adder
= intel_crtc
->cursor_addr
;
3990 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
3991 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
3996 /** Sets the color ramps on behalf of RandR */
3997 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
3998 u16 blue
, int regno
)
4000 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4002 intel_crtc
->lut_r
[regno
] = red
>> 8;
4003 intel_crtc
->lut_g
[regno
] = green
>> 8;
4004 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4007 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4008 u16
*blue
, int regno
)
4010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4012 *red
= intel_crtc
->lut_r
[regno
] << 8;
4013 *green
= intel_crtc
->lut_g
[regno
] << 8;
4014 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4017 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4018 u16
*blue
, uint32_t size
)
4020 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4026 for (i
= 0; i
< 256; i
++) {
4027 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4028 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4029 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4032 intel_crtc_load_lut(crtc
);
4036 * Get a pipe with a simple mode set on it for doing load-based monitor
4039 * It will be up to the load-detect code to adjust the pipe as appropriate for
4040 * its requirements. The pipe will be connected to no other encoders.
4042 * Currently this code will only succeed if there is a pipe with no encoders
4043 * configured for it. In the future, it could choose to temporarily disable
4044 * some outputs to free up a pipe for its use.
4046 * \return crtc, or NULL if no pipes are available.
4049 /* VESA 640x480x72Hz mode to set on the pipe */
4050 static struct drm_display_mode load_detect_mode
= {
4051 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4052 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4055 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4056 struct drm_connector
*connector
,
4057 struct drm_display_mode
*mode
,
4060 struct intel_crtc
*intel_crtc
;
4061 struct drm_crtc
*possible_crtc
;
4062 struct drm_crtc
*supported_crtc
=NULL
;
4063 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4064 struct drm_crtc
*crtc
= NULL
;
4065 struct drm_device
*dev
= encoder
->dev
;
4066 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4067 struct drm_crtc_helper_funcs
*crtc_funcs
;
4071 * Algorithm gets a little messy:
4072 * - if the connector already has an assigned crtc, use it (but make
4073 * sure it's on first)
4074 * - try to find the first unused crtc that can drive this connector,
4075 * and use that if we find one
4076 * - if there are no unused crtcs available, try to use the first
4077 * one we found that supports the connector
4080 /* See if we already have a CRTC for this connector */
4081 if (encoder
->crtc
) {
4082 crtc
= encoder
->crtc
;
4083 /* Make sure the crtc and connector are running */
4084 intel_crtc
= to_intel_crtc(crtc
);
4085 *dpms_mode
= intel_crtc
->dpms_mode
;
4086 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4087 crtc_funcs
= crtc
->helper_private
;
4088 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4089 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4094 /* Find an unused one (if possible) */
4095 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4097 if (!(encoder
->possible_crtcs
& (1 << i
)))
4099 if (!possible_crtc
->enabled
) {
4100 crtc
= possible_crtc
;
4103 if (!supported_crtc
)
4104 supported_crtc
= possible_crtc
;
4108 * If we didn't find an unused CRTC, don't use any.
4114 encoder
->crtc
= crtc
;
4115 connector
->encoder
= encoder
;
4116 intel_encoder
->load_detect_temp
= true;
4118 intel_crtc
= to_intel_crtc(crtc
);
4119 *dpms_mode
= intel_crtc
->dpms_mode
;
4121 if (!crtc
->enabled
) {
4123 mode
= &load_detect_mode
;
4124 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4126 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4127 crtc_funcs
= crtc
->helper_private
;
4128 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4131 /* Add this connector to the crtc */
4132 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4133 encoder_funcs
->commit(encoder
);
4135 /* let the connector get through one full cycle before testing */
4136 intel_wait_for_vblank(dev
);
4141 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4142 struct drm_connector
*connector
, int dpms_mode
)
4144 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4145 struct drm_device
*dev
= encoder
->dev
;
4146 struct drm_crtc
*crtc
= encoder
->crtc
;
4147 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4148 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4150 if (intel_encoder
->load_detect_temp
) {
4151 encoder
->crtc
= NULL
;
4152 connector
->encoder
= NULL
;
4153 intel_encoder
->load_detect_temp
= false;
4154 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4155 drm_helper_disable_unused_functions(dev
);
4158 /* Switch crtc and encoder back off if necessary */
4159 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4160 if (encoder
->crtc
== crtc
)
4161 encoder_funcs
->dpms(encoder
, dpms_mode
);
4162 crtc_funcs
->dpms(crtc
, dpms_mode
);
4166 /* Returns the clock of the currently programmed mode of the given pipe. */
4167 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4171 int pipe
= intel_crtc
->pipe
;
4172 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4174 intel_clock_t clock
;
4176 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4177 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4179 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4181 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4182 if (IS_PINEVIEW(dev
)) {
4183 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4184 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4186 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4187 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4191 if (IS_PINEVIEW(dev
))
4192 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4193 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4195 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4196 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4198 switch (dpll
& DPLL_MODE_MASK
) {
4199 case DPLLB_MODE_DAC_SERIAL
:
4200 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4203 case DPLLB_MODE_LVDS
:
4204 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4208 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4209 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4213 /* XXX: Handle the 100Mhz refclk */
4214 intel_clock(dev
, 96000, &clock
);
4216 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4219 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4220 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4223 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4224 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4225 /* XXX: might not be 66MHz */
4226 intel_clock(dev
, 66000, &clock
);
4228 intel_clock(dev
, 48000, &clock
);
4230 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4233 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4234 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4236 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4241 intel_clock(dev
, 48000, &clock
);
4245 /* XXX: It would be nice to validate the clocks, but we can't reuse
4246 * i830PllIsValid() because it relies on the xf86_config connector
4247 * configuration being accurate, which it isn't necessarily.
4253 /** Returns the currently programmed mode of the given pipe. */
4254 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4255 struct drm_crtc
*crtc
)
4257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4258 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4259 int pipe
= intel_crtc
->pipe
;
4260 struct drm_display_mode
*mode
;
4261 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4262 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4263 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4264 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4266 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4270 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4271 mode
->hdisplay
= (htot
& 0xffff) + 1;
4272 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4273 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4274 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4275 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4276 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4277 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4278 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4280 drm_mode_set_name(mode
);
4281 drm_mode_set_crtcinfo(mode
, 0);
4286 #define GPU_IDLE_TIMEOUT 500 /* ms */
4288 /* When this timer fires, we've been idle for awhile */
4289 static void intel_gpu_idle_timer(unsigned long arg
)
4291 struct drm_device
*dev
= (struct drm_device
*)arg
;
4292 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4294 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4296 dev_priv
->busy
= false;
4298 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4301 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4303 static void intel_crtc_idle_timer(unsigned long arg
)
4305 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4306 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4307 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4309 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4311 intel_crtc
->busy
= false;
4313 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4316 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
4318 struct drm_device
*dev
= crtc
->dev
;
4319 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4320 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4321 int pipe
= intel_crtc
->pipe
;
4322 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4323 int dpll
= I915_READ(dpll_reg
);
4325 if (HAS_PCH_SPLIT(dev
))
4328 if (!dev_priv
->lvds_downclock_avail
)
4331 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4332 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4334 /* Unlock panel regs */
4335 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
4337 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4338 I915_WRITE(dpll_reg
, dpll
);
4339 dpll
= I915_READ(dpll_reg
);
4340 intel_wait_for_vblank(dev
);
4341 dpll
= I915_READ(dpll_reg
);
4342 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4343 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4345 /* ...and lock them again */
4346 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4349 /* Schedule downclock */
4351 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4352 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4355 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4357 struct drm_device
*dev
= crtc
->dev
;
4358 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4359 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4360 int pipe
= intel_crtc
->pipe
;
4361 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4362 int dpll
= I915_READ(dpll_reg
);
4364 if (HAS_PCH_SPLIT(dev
))
4367 if (!dev_priv
->lvds_downclock_avail
)
4371 * Since this is called by a timer, we should never get here in
4374 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4375 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4377 /* Unlock panel regs */
4378 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
4380 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4381 I915_WRITE(dpll_reg
, dpll
);
4382 dpll
= I915_READ(dpll_reg
);
4383 intel_wait_for_vblank(dev
);
4384 dpll
= I915_READ(dpll_reg
);
4385 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4386 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4388 /* ...and lock them again */
4389 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4395 * intel_idle_update - adjust clocks for idleness
4396 * @work: work struct
4398 * Either the GPU or display (or both) went idle. Check the busy status
4399 * here and adjust the CRTC and GPU clocks as necessary.
4401 static void intel_idle_update(struct work_struct
*work
)
4403 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4405 struct drm_device
*dev
= dev_priv
->dev
;
4406 struct drm_crtc
*crtc
;
4407 struct intel_crtc
*intel_crtc
;
4409 if (!i915_powersave
)
4412 mutex_lock(&dev
->struct_mutex
);
4414 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4415 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4416 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4419 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4420 /* Skip inactive CRTCs */
4424 intel_crtc
= to_intel_crtc(crtc
);
4425 if (!intel_crtc
->busy
)
4426 intel_decrease_pllclock(crtc
);
4429 mutex_unlock(&dev
->struct_mutex
);
4433 * intel_mark_busy - mark the GPU and possibly the display busy
4435 * @obj: object we're operating on
4437 * Callers can use this function to indicate that the GPU is busy processing
4438 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4439 * buffer), we'll also mark the display as busy, so we know to increase its
4442 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4444 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4445 struct drm_crtc
*crtc
= NULL
;
4446 struct intel_framebuffer
*intel_fb
;
4447 struct intel_crtc
*intel_crtc
;
4449 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4452 if (!dev_priv
->busy
) {
4453 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4456 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4457 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4458 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4459 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4461 dev_priv
->busy
= true;
4463 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4464 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4466 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4470 intel_crtc
= to_intel_crtc(crtc
);
4471 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4472 if (intel_fb
->obj
== obj
) {
4473 if (!intel_crtc
->busy
) {
4474 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4477 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4478 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4479 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4480 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4482 /* Non-busy -> busy, upclock */
4483 intel_increase_pllclock(crtc
, true);
4484 intel_crtc
->busy
= true;
4486 /* Busy -> busy, put off timer */
4487 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4488 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4494 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4498 drm_crtc_cleanup(crtc
);
4502 struct intel_unpin_work
{
4503 struct work_struct work
;
4504 struct drm_device
*dev
;
4505 struct drm_gem_object
*old_fb_obj
;
4506 struct drm_gem_object
*pending_flip_obj
;
4507 struct drm_pending_vblank_event
*event
;
4511 static void intel_unpin_work_fn(struct work_struct
*__work
)
4513 struct intel_unpin_work
*work
=
4514 container_of(__work
, struct intel_unpin_work
, work
);
4516 mutex_lock(&work
->dev
->struct_mutex
);
4517 i915_gem_object_unpin(work
->old_fb_obj
);
4518 drm_gem_object_unreference(work
->pending_flip_obj
);
4519 drm_gem_object_unreference(work
->old_fb_obj
);
4520 mutex_unlock(&work
->dev
->struct_mutex
);
4524 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
4526 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4527 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
4528 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4529 struct intel_unpin_work
*work
;
4530 struct drm_i915_gem_object
*obj_priv
;
4531 struct drm_pending_vblank_event
*e
;
4533 unsigned long flags
;
4535 /* Ignore early vblank irqs */
4536 if (intel_crtc
== NULL
)
4539 spin_lock_irqsave(&dev
->event_lock
, flags
);
4540 work
= intel_crtc
->unpin_work
;
4541 if (work
== NULL
|| !work
->pending
) {
4542 if (work
&& !work
->pending
) {
4543 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4544 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4546 atomic_read(&obj_priv
->pending_flip
));
4548 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4552 intel_crtc
->unpin_work
= NULL
;
4553 drm_vblank_put(dev
, intel_crtc
->pipe
);
4557 do_gettimeofday(&now
);
4558 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4559 e
->event
.tv_sec
= now
.tv_sec
;
4560 e
->event
.tv_usec
= now
.tv_usec
;
4561 list_add_tail(&e
->base
.link
,
4562 &e
->base
.file_priv
->event_list
);
4563 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4566 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4568 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4570 /* Initial scanout buffer will have a 0 pending flip count */
4571 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4572 atomic_dec_and_test(&obj_priv
->pending_flip
))
4573 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4574 schedule_work(&work
->work
);
4577 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
4579 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4580 struct intel_crtc
*intel_crtc
=
4581 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
4582 unsigned long flags
;
4584 spin_lock_irqsave(&dev
->event_lock
, flags
);
4585 if (intel_crtc
->unpin_work
) {
4586 intel_crtc
->unpin_work
->pending
= 1;
4588 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4590 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4593 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
4594 struct drm_framebuffer
*fb
,
4595 struct drm_pending_vblank_event
*event
)
4597 struct drm_device
*dev
= crtc
->dev
;
4598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4599 struct intel_framebuffer
*intel_fb
;
4600 struct drm_i915_gem_object
*obj_priv
;
4601 struct drm_gem_object
*obj
;
4602 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4603 struct intel_unpin_work
*work
;
4604 unsigned long flags
;
4605 int pipesrc_reg
= (intel_crtc
->pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
4609 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
4613 mutex_lock(&dev
->struct_mutex
);
4615 work
->event
= event
;
4616 work
->dev
= crtc
->dev
;
4617 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4618 work
->old_fb_obj
= intel_fb
->obj
;
4619 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
4621 /* We borrow the event spin lock for protecting unpin_work */
4622 spin_lock_irqsave(&dev
->event_lock
, flags
);
4623 if (intel_crtc
->unpin_work
) {
4624 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4625 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4627 mutex_unlock(&dev
->struct_mutex
);
4630 intel_crtc
->unpin_work
= work
;
4631 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4633 intel_fb
= to_intel_framebuffer(fb
);
4634 obj
= intel_fb
->obj
;
4636 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
4638 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4641 intel_crtc
->unpin_work
= NULL
;
4642 mutex_unlock(&dev
->struct_mutex
);
4646 /* Reference the objects for the scheduled work. */
4647 drm_gem_object_reference(work
->old_fb_obj
);
4648 drm_gem_object_reference(obj
);
4651 i915_gem_object_flush_write_domain(obj
);
4652 drm_vblank_get(dev
, intel_crtc
->pipe
);
4653 obj_priv
= to_intel_bo(obj
);
4654 atomic_inc(&obj_priv
->pending_flip
);
4655 work
->pending_flip_obj
= obj
;
4658 OUT_RING(MI_DISPLAY_FLIP
|
4659 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
4660 OUT_RING(fb
->pitch
);
4661 if (IS_I965G(dev
)) {
4662 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
4663 pipesrc
= I915_READ(pipesrc_reg
);
4664 OUT_RING(pipesrc
& 0x0fff0fff);
4666 OUT_RING(obj_priv
->gtt_offset
);
4671 mutex_unlock(&dev
->struct_mutex
);
4676 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
4677 .dpms
= intel_crtc_dpms
,
4678 .mode_fixup
= intel_crtc_mode_fixup
,
4679 .mode_set
= intel_crtc_mode_set
,
4680 .mode_set_base
= intel_pipe_set_base
,
4681 .prepare
= intel_crtc_prepare
,
4682 .commit
= intel_crtc_commit
,
4683 .load_lut
= intel_crtc_load_lut
,
4686 static const struct drm_crtc_funcs intel_crtc_funcs
= {
4687 .cursor_set
= intel_crtc_cursor_set
,
4688 .cursor_move
= intel_crtc_cursor_move
,
4689 .gamma_set
= intel_crtc_gamma_set
,
4690 .set_config
= drm_crtc_helper_set_config
,
4691 .destroy
= intel_crtc_destroy
,
4692 .page_flip
= intel_crtc_page_flip
,
4696 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
4698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4699 struct intel_crtc
*intel_crtc
;
4702 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
4703 if (intel_crtc
== NULL
)
4706 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
4708 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
4709 intel_crtc
->pipe
= pipe
;
4710 intel_crtc
->plane
= pipe
;
4711 for (i
= 0; i
< 256; i
++) {
4712 intel_crtc
->lut_r
[i
] = i
;
4713 intel_crtc
->lut_g
[i
] = i
;
4714 intel_crtc
->lut_b
[i
] = i
;
4717 /* Swap pipes & planes for FBC on pre-965 */
4718 intel_crtc
->pipe
= pipe
;
4719 intel_crtc
->plane
= pipe
;
4720 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
4721 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4722 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
4725 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
4726 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
4727 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
4728 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
4730 intel_crtc
->cursor_addr
= 0;
4731 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4732 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
4734 intel_crtc
->busy
= false;
4736 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
4737 (unsigned long)intel_crtc
);
4740 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
4741 struct drm_file
*file_priv
)
4743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4744 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
4745 struct drm_mode_object
*drmmode_obj
;
4746 struct intel_crtc
*crtc
;
4749 DRM_ERROR("called with no initialization\n");
4753 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
4754 DRM_MODE_OBJECT_CRTC
);
4757 DRM_ERROR("no such CRTC id\n");
4761 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
4762 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
4767 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
4769 struct drm_crtc
*crtc
= NULL
;
4771 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4772 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4773 if (intel_crtc
->pipe
== pipe
)
4779 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
4782 struct drm_encoder
*encoder
;
4785 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4786 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
4787 if (type_mask
& intel_encoder
->clone_mask
)
4788 index_mask
|= (1 << entry
);
4795 static void intel_setup_outputs(struct drm_device
*dev
)
4797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4798 struct drm_encoder
*encoder
;
4800 intel_crt_init(dev
);
4802 /* Set up integrated LVDS */
4803 if (IS_MOBILE(dev
) && !IS_I830(dev
))
4804 intel_lvds_init(dev
);
4806 if (HAS_PCH_SPLIT(dev
)) {
4809 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
4810 intel_dp_init(dev
, DP_A
);
4812 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
4813 /* PCH SDVOB multiplex with HDMIB */
4814 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
4816 intel_hdmi_init(dev
, HDMIB
);
4817 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
4818 intel_dp_init(dev
, PCH_DP_B
);
4821 if (I915_READ(HDMIC
) & PORT_DETECTED
)
4822 intel_hdmi_init(dev
, HDMIC
);
4824 if (I915_READ(HDMID
) & PORT_DETECTED
)
4825 intel_hdmi_init(dev
, HDMID
);
4827 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
4828 intel_dp_init(dev
, PCH_DP_C
);
4830 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
4831 intel_dp_init(dev
, PCH_DP_D
);
4833 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
4836 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4837 DRM_DEBUG_KMS("probing SDVOB\n");
4838 found
= intel_sdvo_init(dev
, SDVOB
);
4839 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
4840 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4841 intel_hdmi_init(dev
, SDVOB
);
4844 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
4845 DRM_DEBUG_KMS("probing DP_B\n");
4846 intel_dp_init(dev
, DP_B
);
4850 /* Before G4X SDVOC doesn't have its own detect register */
4852 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4853 DRM_DEBUG_KMS("probing SDVOC\n");
4854 found
= intel_sdvo_init(dev
, SDVOC
);
4857 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
4859 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
4860 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4861 intel_hdmi_init(dev
, SDVOC
);
4863 if (SUPPORTS_INTEGRATED_DP(dev
)) {
4864 DRM_DEBUG_KMS("probing DP_C\n");
4865 intel_dp_init(dev
, DP_C
);
4869 if (SUPPORTS_INTEGRATED_DP(dev
) &&
4870 (I915_READ(DP_D
) & DP_DETECTED
)) {
4871 DRM_DEBUG_KMS("probing DP_D\n");
4872 intel_dp_init(dev
, DP_D
);
4874 } else if (IS_GEN2(dev
))
4875 intel_dvo_init(dev
);
4877 if (SUPPORTS_TV(dev
))
4880 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4881 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
4883 encoder
->possible_crtcs
= intel_encoder
->crtc_mask
;
4884 encoder
->possible_clones
= intel_encoder_clones(dev
,
4885 intel_encoder
->clone_mask
);
4889 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
4891 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4893 drm_framebuffer_cleanup(fb
);
4894 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
4899 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
4900 struct drm_file
*file_priv
,
4901 unsigned int *handle
)
4903 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4904 struct drm_gem_object
*object
= intel_fb
->obj
;
4906 return drm_gem_handle_create(file_priv
, object
, handle
);
4909 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
4910 .destroy
= intel_user_framebuffer_destroy
,
4911 .create_handle
= intel_user_framebuffer_create_handle
,
4914 int intel_framebuffer_init(struct drm_device
*dev
,
4915 struct intel_framebuffer
*intel_fb
,
4916 struct drm_mode_fb_cmd
*mode_cmd
,
4917 struct drm_gem_object
*obj
)
4921 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
4923 DRM_ERROR("framebuffer init failed %d\n", ret
);
4927 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
4928 intel_fb
->obj
= obj
;
4932 static struct drm_framebuffer
*
4933 intel_user_framebuffer_create(struct drm_device
*dev
,
4934 struct drm_file
*filp
,
4935 struct drm_mode_fb_cmd
*mode_cmd
)
4937 struct drm_gem_object
*obj
;
4938 struct intel_framebuffer
*intel_fb
;
4941 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
4945 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
4949 ret
= intel_framebuffer_init(dev
, intel_fb
,
4952 drm_gem_object_unreference_unlocked(obj
);
4957 return &intel_fb
->base
;
4960 static const struct drm_mode_config_funcs intel_mode_funcs
= {
4961 .fb_create
= intel_user_framebuffer_create
,
4964 static struct drm_gem_object
*
4965 intel_alloc_power_context(struct drm_device
*dev
)
4967 struct drm_gem_object
*pwrctx
;
4970 pwrctx
= i915_gem_alloc_object(dev
, 4096);
4972 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4976 mutex_lock(&dev
->struct_mutex
);
4977 ret
= i915_gem_object_pin(pwrctx
, 4096);
4979 DRM_ERROR("failed to pin power context: %d\n", ret
);
4983 ret
= i915_gem_object_set_to_gtt_domain(pwrctx
, 1);
4985 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
4988 mutex_unlock(&dev
->struct_mutex
);
4993 i915_gem_object_unpin(pwrctx
);
4995 drm_gem_object_unreference(pwrctx
);
4996 mutex_unlock(&dev
->struct_mutex
);
5000 void ironlake_enable_drps(struct drm_device
*dev
)
5002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5003 u32 rgvmodectl
= I915_READ(MEMMODECTL
), rgvswctl
;
5004 u8 fmax
, fmin
, fstart
, vstart
;
5007 /* 100ms RC evaluation intervals */
5008 I915_WRITE(RCUPEI
, 100000);
5009 I915_WRITE(RCDNEI
, 100000);
5011 /* Set max/min thresholds to 90ms and 80ms respectively */
5012 I915_WRITE(RCBMAXAVG
, 90000);
5013 I915_WRITE(RCBMINAVG
, 80000);
5015 I915_WRITE(MEMIHYST
, 1);
5017 /* Set up min, max, and cur for interrupt handling */
5018 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5019 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5020 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5021 MEMMODE_FSTART_SHIFT
;
5022 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5025 dev_priv
->max_delay
= fstart
; /* can't go to fmax w/o IPS */
5026 dev_priv
->min_delay
= fmin
;
5027 dev_priv
->cur_delay
= fstart
;
5029 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5032 * Interrupts will be enabled in ironlake_irq_postinstall
5035 I915_WRITE(VIDSTART
, vstart
);
5036 POSTING_READ(VIDSTART
);
5038 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5039 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5041 while (I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) {
5043 DRM_ERROR("stuck trying to change perf mode\n");
5050 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5051 (fstart
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5052 I915_WRITE(MEMSWCTL
, rgvswctl
);
5053 POSTING_READ(MEMSWCTL
);
5055 rgvswctl
|= MEMCTL_CMD_STS
;
5056 I915_WRITE(MEMSWCTL
, rgvswctl
);
5059 void ironlake_disable_drps(struct drm_device
*dev
)
5061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5065 /* Ack interrupts, disable EFC interrupt */
5066 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5067 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5068 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5069 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5070 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5072 /* Go back to the starting frequency */
5073 fstart
= (I915_READ(MEMMODECTL
) & MEMMODE_FSTART_MASK
) >>
5074 MEMMODE_FSTART_SHIFT
;
5075 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5076 (fstart
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5077 I915_WRITE(MEMSWCTL
, rgvswctl
);
5079 rgvswctl
|= MEMCTL_CMD_STS
;
5080 I915_WRITE(MEMSWCTL
, rgvswctl
);
5085 void intel_init_clock_gating(struct drm_device
*dev
)
5087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5090 * Disable clock gating reported to work incorrectly according to the
5091 * specs, but enable as much else as we can.
5093 if (HAS_PCH_SPLIT(dev
)) {
5094 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5096 if (IS_IRONLAKE(dev
)) {
5097 /* Required for FBC */
5098 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5099 /* Required for CxSR */
5100 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5102 I915_WRITE(PCH_3DCGDIS0
,
5103 MARIUNIT_CLOCK_GATE_DISABLE
|
5104 SVSMUNIT_CLOCK_GATE_DISABLE
);
5107 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5110 * According to the spec the following bits should be set in
5111 * order to enable memory self-refresh
5112 * The bit 22/21 of 0x42004
5113 * The bit 5 of 0x42020
5114 * The bit 15 of 0x45000
5116 if (IS_IRONLAKE(dev
)) {
5117 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5118 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5119 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5120 I915_WRITE(ILK_DSPCLK_GATE
,
5121 (I915_READ(ILK_DSPCLK_GATE
) |
5122 ILK_DPARB_CLK_GATE
));
5123 I915_WRITE(DISP_ARB_CTL
,
5124 (I915_READ(DISP_ARB_CTL
) |
5128 } else if (IS_G4X(dev
)) {
5129 uint32_t dspclk_gate
;
5130 I915_WRITE(RENCLK_GATE_D1
, 0);
5131 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5132 GS_UNIT_CLOCK_GATE_DISABLE
|
5133 CL_UNIT_CLOCK_GATE_DISABLE
);
5134 I915_WRITE(RAMCLK_GATE_D
, 0);
5135 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5136 OVRUNIT_CLOCK_GATE_DISABLE
|
5137 OVCUNIT_CLOCK_GATE_DISABLE
;
5139 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5140 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5141 } else if (IS_I965GM(dev
)) {
5142 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5143 I915_WRITE(RENCLK_GATE_D2
, 0);
5144 I915_WRITE(DSPCLK_GATE_D
, 0);
5145 I915_WRITE(RAMCLK_GATE_D
, 0);
5146 I915_WRITE16(DEUC
, 0);
5147 } else if (IS_I965G(dev
)) {
5148 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5149 I965_RCC_CLOCK_GATE_DISABLE
|
5150 I965_RCPB_CLOCK_GATE_DISABLE
|
5151 I965_ISC_CLOCK_GATE_DISABLE
|
5152 I965_FBC_CLOCK_GATE_DISABLE
);
5153 I915_WRITE(RENCLK_GATE_D2
, 0);
5154 } else if (IS_I9XX(dev
)) {
5155 u32 dstate
= I915_READ(D_STATE
);
5157 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5158 DSTATE_DOT_CLOCK_GATING
;
5159 I915_WRITE(D_STATE
, dstate
);
5160 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5161 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5162 } else if (IS_I830(dev
)) {
5163 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5167 * GPU can automatically power down the render unit if given a page
5170 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5171 struct drm_i915_gem_object
*obj_priv
= NULL
;
5173 if (dev_priv
->pwrctx
) {
5174 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5176 struct drm_gem_object
*pwrctx
;
5178 pwrctx
= intel_alloc_power_context(dev
);
5180 dev_priv
->pwrctx
= pwrctx
;
5181 obj_priv
= to_intel_bo(pwrctx
);
5186 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5187 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5188 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5193 /* Set up chip specific display functions */
5194 static void intel_init_display(struct drm_device
*dev
)
5196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5198 /* We always want a DPMS function */
5199 if (HAS_PCH_SPLIT(dev
))
5200 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5202 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5204 /* Only mobile has FBC, leave pointers NULL for other chips */
5205 if (IS_MOBILE(dev
)) {
5207 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5208 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5209 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5210 } else if (IS_I965GM(dev
)) {
5211 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5212 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5213 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5215 /* 855GM needs testing */
5218 /* Returns the core display clock speed */
5219 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5220 dev_priv
->display
.get_display_clock_speed
=
5221 i945_get_display_clock_speed
;
5222 else if (IS_I915G(dev
))
5223 dev_priv
->display
.get_display_clock_speed
=
5224 i915_get_display_clock_speed
;
5225 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5226 dev_priv
->display
.get_display_clock_speed
=
5227 i9xx_misc_get_display_clock_speed
;
5228 else if (IS_I915GM(dev
))
5229 dev_priv
->display
.get_display_clock_speed
=
5230 i915gm_get_display_clock_speed
;
5231 else if (IS_I865G(dev
))
5232 dev_priv
->display
.get_display_clock_speed
=
5233 i865_get_display_clock_speed
;
5234 else if (IS_I85X(dev
))
5235 dev_priv
->display
.get_display_clock_speed
=
5236 i855_get_display_clock_speed
;
5238 dev_priv
->display
.get_display_clock_speed
=
5239 i830_get_display_clock_speed
;
5241 /* For FIFO watermark updates */
5242 if (HAS_PCH_SPLIT(dev
)) {
5243 if (IS_IRONLAKE(dev
)) {
5244 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5245 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5247 DRM_DEBUG_KMS("Failed to get proper latency. "
5249 dev_priv
->display
.update_wm
= NULL
;
5252 dev_priv
->display
.update_wm
= NULL
;
5253 } else if (IS_PINEVIEW(dev
)) {
5254 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5256 dev_priv
->mem_freq
)) {
5257 DRM_INFO("failed to find known CxSR latency "
5258 "(found fsb freq %d, mem freq %d), "
5260 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5261 /* Disable CxSR and never update its watermark again */
5262 pineview_disable_cxsr(dev
);
5263 dev_priv
->display
.update_wm
= NULL
;
5265 dev_priv
->display
.update_wm
= pineview_update_wm
;
5266 } else if (IS_G4X(dev
))
5267 dev_priv
->display
.update_wm
= g4x_update_wm
;
5268 else if (IS_I965G(dev
))
5269 dev_priv
->display
.update_wm
= i965_update_wm
;
5270 else if (IS_I9XX(dev
) || IS_MOBILE(dev
)) {
5271 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5272 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5275 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5276 else if (IS_845G(dev
))
5277 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5279 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5280 dev_priv
->display
.update_wm
= i830_update_wm
;
5284 void intel_modeset_init(struct drm_device
*dev
)
5286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5290 drm_mode_config_init(dev
);
5292 dev
->mode_config
.min_width
= 0;
5293 dev
->mode_config
.min_height
= 0;
5295 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
5297 intel_init_display(dev
);
5299 if (IS_I965G(dev
)) {
5300 dev
->mode_config
.max_width
= 8192;
5301 dev
->mode_config
.max_height
= 8192;
5302 } else if (IS_I9XX(dev
)) {
5303 dev
->mode_config
.max_width
= 4096;
5304 dev
->mode_config
.max_height
= 4096;
5306 dev
->mode_config
.max_width
= 2048;
5307 dev
->mode_config
.max_height
= 2048;
5310 /* set memory base */
5312 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
5314 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
5316 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
5320 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5321 num_pipe
, num_pipe
> 1 ? "s" : "");
5323 for (i
= 0; i
< num_pipe
; i
++) {
5324 intel_crtc_init(dev
, i
);
5327 intel_setup_outputs(dev
);
5329 intel_init_clock_gating(dev
);
5331 if (IS_IRONLAKE_M(dev
))
5332 ironlake_enable_drps(dev
);
5334 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
5335 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
5336 (unsigned long)dev
);
5338 intel_setup_overlay(dev
);
5341 void intel_modeset_cleanup(struct drm_device
*dev
)
5343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5344 struct drm_crtc
*crtc
;
5345 struct intel_crtc
*intel_crtc
;
5347 mutex_lock(&dev
->struct_mutex
);
5349 intel_fbdev_fini(dev
);
5351 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5352 /* Skip inactive CRTCs */
5356 intel_crtc
= to_intel_crtc(crtc
);
5357 intel_increase_pllclock(crtc
, false);
5358 del_timer_sync(&intel_crtc
->idle_timer
);
5361 del_timer_sync(&dev_priv
->idle_timer
);
5363 if (dev_priv
->display
.disable_fbc
)
5364 dev_priv
->display
.disable_fbc(dev
);
5366 if (dev_priv
->pwrctx
) {
5367 struct drm_i915_gem_object
*obj_priv
;
5369 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5370 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
5372 i915_gem_object_unpin(dev_priv
->pwrctx
);
5373 drm_gem_object_unreference(dev_priv
->pwrctx
);
5376 if (IS_IRONLAKE_M(dev
))
5377 ironlake_disable_drps(dev
);
5379 mutex_unlock(&dev
->struct_mutex
);
5381 drm_mode_config_cleanup(dev
);
5386 * Return which encoder is currently attached for connector.
5388 struct drm_encoder
*intel_attached_encoder (struct drm_connector
*connector
)
5390 struct drm_mode_object
*obj
;
5391 struct drm_encoder
*encoder
;
5394 for (i
= 0; i
< DRM_CONNECTOR_MAX_ENCODER
; i
++) {
5395 if (connector
->encoder_ids
[i
] == 0)
5398 obj
= drm_mode_object_find(connector
->dev
,
5399 connector
->encoder_ids
[i
],
5400 DRM_MODE_OBJECT_ENCODER
);
5404 encoder
= obj_to_encoder(obj
);
5411 * set vga decode state - true == enable VGA decode
5413 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
5415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5418 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
5420 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
5422 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
5423 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);