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drm/i915: use pipe_config for lvds dithering
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
80 };
81
82 /* FDI */
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
85 int
86 intel_pch_rawclk(struct drm_device *dev)
87 {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93 }
94
95 static bool
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99 static bool
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
103
104 static bool
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
111 {
112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
117 }
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
131 };
132
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
145 };
146
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
159 };
160
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
173 };
174
175
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
188 },
189 .find_pll = intel_g4x_find_best_PLL,
190 };
191
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
204 };
205
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
217 },
218 .find_pll = intel_g4x_find_best_PLL,
219 };
220
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
232 },
233 .find_pll = intel_g4x_find_best_PLL,
234 };
235
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
250 };
251
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
264 };
265
266 /* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
283 };
284
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
311 };
312
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
340 };
341
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354 };
355
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368 };
369
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382 };
383
384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385 {
386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
387
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
390 return 0;
391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
398 return 0;
399 }
400
401 return I915_READ(DPIO_DATA);
402 }
403
404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
405 {
406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
407
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
410 return;
411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
419 }
420
421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
423 {
424 struct drm_device *dev = crtc->dev;
425 const intel_limit_t *limit;
426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
439 } else
440 limit = &intel_limits_ironlake_dac;
441
442 return limit;
443 }
444
445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446 {
447 struct drm_device *dev = crtc->dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
453 else
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
462
463 return limit;
464 }
465
466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
467 {
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
478 else
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
494 limit = &intel_limits_i8xx_lvds;
495 else
496 limit = &intel_limits_i8xx_dvo;
497 }
498 return limit;
499 }
500
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk, intel_clock_t *clock)
503 {
504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508 }
509
510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511 {
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513 }
514
515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516 {
517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
519 return;
520 }
521 clock->m = i9xx_dpll_compute_m(clock);
522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525 }
526
527 /**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
531 {
532 struct drm_device *dev = crtc->dev;
533 struct intel_encoder *encoder;
534
535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
537 return true;
538
539 return false;
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock->p < limit->p.min || limit->p.max < clock->p)
555 INTELPllInvalid("p out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock->m < limit->m.min || limit->m.max < clock->m)
563 INTELPllInvalid("m out of range\n");
564 if (clock->n < limit->n.min || limit->n.max < clock->n)
565 INTELPllInvalid("n out of range\n");
566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
572 INTELPllInvalid("dot out of range\n");
573
574 return true;
575 }
576
577 static bool
578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
581
582 {
583 struct drm_device *dev = crtc->dev;
584 intel_clock_t clock;
585 int err = target;
586
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
588 /*
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
592 */
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
604 memset(best_clock, 0, sizeof(*best_clock));
605
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
617 int this_err;
618
619 intel_clock(dev, refclk, &clock);
620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
622 continue;
623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638 }
639
640 static bool
641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
644 {
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
647 int max_n;
648 bool found;
649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 int lvds_reg;
655
656 if (HAS_PCH_SPLIT(dev))
657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
660 if (intel_is_dual_link_lvds(dev))
661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
673 /* based on hardware requirement, prefer smaller n to precision */
674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
675 /* based on hardware requirement, prefere larger m1,m2 */
676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
684 intel_clock(dev, refclk, &clock);
685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
687 continue;
688 if (match_clock &&
689 clock.p != match_clock->p)
690 continue;
691
692 this_err = abs(clock.dot - target);
693 if (this_err < err_most) {
694 *best_clock = clock;
695 err_most = this_err;
696 max_n = clock.n;
697 found = true;
698 }
699 }
700 }
701 }
702 }
703 return found;
704 }
705
706 static bool
707 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
708 int target, int refclk, intel_clock_t *match_clock,
709 intel_clock_t *best_clock)
710 {
711 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
712 u32 m, n, fastclk;
713 u32 updrate, minupdate, fracbits, p;
714 unsigned long bestppm, ppm, absppm;
715 int dotclk, flag;
716
717 flag = 0;
718 dotclk = target * 1000;
719 bestppm = 1000000;
720 ppm = absppm = 0;
721 fastclk = dotclk / (2*100);
722 updrate = 0;
723 minupdate = 19200;
724 fracbits = 1;
725 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
726 bestm1 = bestm2 = bestp1 = bestp2 = 0;
727
728 /* based on hardware requirement, prefer smaller n to precision */
729 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
730 updrate = refclk / n;
731 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
732 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
733 if (p2 > 10)
734 p2 = p2 - 1;
735 p = p1 * p2;
736 /* based on hardware requirement, prefer bigger m1,m2 values */
737 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
738 m2 = (((2*(fastclk * p * n / m1 )) +
739 refclk) / (2*refclk));
740 m = m1 * m2;
741 vco = updrate * m;
742 if (vco >= limit->vco.min && vco < limit->vco.max) {
743 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
744 absppm = (ppm > 0) ? ppm : (-ppm);
745 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
746 bestppm = 0;
747 flag = 1;
748 }
749 if (absppm < bestppm - 10) {
750 bestppm = absppm;
751 flag = 1;
752 }
753 if (flag) {
754 bestn = n;
755 bestm1 = m1;
756 bestm2 = m2;
757 bestp1 = p1;
758 bestp2 = p2;
759 flag = 0;
760 }
761 }
762 }
763 }
764 }
765 }
766 best_clock->n = bestn;
767 best_clock->m1 = bestm1;
768 best_clock->m2 = bestm2;
769 best_clock->p1 = bestp1;
770 best_clock->p2 = bestp2;
771
772 return true;
773 }
774
775 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
776 enum pipe pipe)
777 {
778 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
780
781 return intel_crtc->config.cpu_transcoder;
782 }
783
784 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
785 {
786 struct drm_i915_private *dev_priv = dev->dev_private;
787 u32 frame, frame_reg = PIPEFRAME(pipe);
788
789 frame = I915_READ(frame_reg);
790
791 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
792 DRM_DEBUG_KMS("vblank wait timed out\n");
793 }
794
795 /**
796 * intel_wait_for_vblank - wait for vblank on a given pipe
797 * @dev: drm device
798 * @pipe: pipe to wait for
799 *
800 * Wait for vblank to occur on a given pipe. Needed for various bits of
801 * mode setting code.
802 */
803 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
804 {
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 int pipestat_reg = PIPESTAT(pipe);
807
808 if (INTEL_INFO(dev)->gen >= 5) {
809 ironlake_wait_for_vblank(dev, pipe);
810 return;
811 }
812
813 /* Clear existing vblank status. Note this will clear any other
814 * sticky status fields as well.
815 *
816 * This races with i915_driver_irq_handler() with the result
817 * that either function could miss a vblank event. Here it is not
818 * fatal, as we will either wait upon the next vblank interrupt or
819 * timeout. Generally speaking intel_wait_for_vblank() is only
820 * called during modeset at which time the GPU should be idle and
821 * should *not* be performing page flips and thus not waiting on
822 * vblanks...
823 * Currently, the result of us stealing a vblank from the irq
824 * handler is that a single frame will be skipped during swapbuffers.
825 */
826 I915_WRITE(pipestat_reg,
827 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
828
829 /* Wait for vblank interrupt bit to set */
830 if (wait_for(I915_READ(pipestat_reg) &
831 PIPE_VBLANK_INTERRUPT_STATUS,
832 50))
833 DRM_DEBUG_KMS("vblank wait timed out\n");
834 }
835
836 /*
837 * intel_wait_for_pipe_off - wait for pipe to turn off
838 * @dev: drm device
839 * @pipe: pipe to wait for
840 *
841 * After disabling a pipe, we can't wait for vblank in the usual way,
842 * spinning on the vblank interrupt status bit, since we won't actually
843 * see an interrupt when the pipe is disabled.
844 *
845 * On Gen4 and above:
846 * wait for the pipe register state bit to turn off
847 *
848 * Otherwise:
849 * wait for the display line value to settle (it usually
850 * ends up stopping at the start of the next frame).
851 *
852 */
853 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
854 {
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
857 pipe);
858
859 if (INTEL_INFO(dev)->gen >= 4) {
860 int reg = PIPECONF(cpu_transcoder);
861
862 /* Wait for the Pipe State to go off */
863 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
864 100))
865 WARN(1, "pipe_off wait timed out\n");
866 } else {
867 u32 last_line, line_mask;
868 int reg = PIPEDSL(pipe);
869 unsigned long timeout = jiffies + msecs_to_jiffies(100);
870
871 if (IS_GEN2(dev))
872 line_mask = DSL_LINEMASK_GEN2;
873 else
874 line_mask = DSL_LINEMASK_GEN3;
875
876 /* Wait for the display line to settle */
877 do {
878 last_line = I915_READ(reg) & line_mask;
879 mdelay(5);
880 } while (((I915_READ(reg) & line_mask) != last_line) &&
881 time_after(timeout, jiffies));
882 if (time_after(jiffies, timeout))
883 WARN(1, "pipe_off wait timed out\n");
884 }
885 }
886
887 /*
888 * ibx_digital_port_connected - is the specified port connected?
889 * @dev_priv: i915 private structure
890 * @port: the port to test
891 *
892 * Returns true if @port is connected, false otherwise.
893 */
894 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
895 struct intel_digital_port *port)
896 {
897 u32 bit;
898
899 if (HAS_PCH_IBX(dev_priv->dev)) {
900 switch(port->port) {
901 case PORT_B:
902 bit = SDE_PORTB_HOTPLUG;
903 break;
904 case PORT_C:
905 bit = SDE_PORTC_HOTPLUG;
906 break;
907 case PORT_D:
908 bit = SDE_PORTD_HOTPLUG;
909 break;
910 default:
911 return true;
912 }
913 } else {
914 switch(port->port) {
915 case PORT_B:
916 bit = SDE_PORTB_HOTPLUG_CPT;
917 break;
918 case PORT_C:
919 bit = SDE_PORTC_HOTPLUG_CPT;
920 break;
921 case PORT_D:
922 bit = SDE_PORTD_HOTPLUG_CPT;
923 break;
924 default:
925 return true;
926 }
927 }
928
929 return I915_READ(SDEISR) & bit;
930 }
931
932 static const char *state_string(bool enabled)
933 {
934 return enabled ? "on" : "off";
935 }
936
937 /* Only for pre-ILK configs */
938 static void assert_pll(struct drm_i915_private *dev_priv,
939 enum pipe pipe, bool state)
940 {
941 int reg;
942 u32 val;
943 bool cur_state;
944
945 reg = DPLL(pipe);
946 val = I915_READ(reg);
947 cur_state = !!(val & DPLL_VCO_ENABLE);
948 WARN(cur_state != state,
949 "PLL state assertion failure (expected %s, current %s)\n",
950 state_string(state), state_string(cur_state));
951 }
952 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
953 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
954
955 /* For ILK+ */
956 static void assert_pch_pll(struct drm_i915_private *dev_priv,
957 struct intel_pch_pll *pll,
958 struct intel_crtc *crtc,
959 bool state)
960 {
961 u32 val;
962 bool cur_state;
963
964 if (HAS_PCH_LPT(dev_priv->dev)) {
965 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
966 return;
967 }
968
969 if (WARN (!pll,
970 "asserting PCH PLL %s with no PLL\n", state_string(state)))
971 return;
972
973 val = I915_READ(pll->pll_reg);
974 cur_state = !!(val & DPLL_VCO_ENABLE);
975 WARN(cur_state != state,
976 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
977 pll->pll_reg, state_string(state), state_string(cur_state), val);
978
979 /* Make sure the selected PLL is correctly attached to the transcoder */
980 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
981 u32 pch_dpll;
982
983 pch_dpll = I915_READ(PCH_DPLL_SEL);
984 cur_state = pll->pll_reg == _PCH_DPLL_B;
985 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
986 "PLL[%d] not attached to this transcoder %c: %08x\n",
987 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
988 cur_state = !!(val >> (4*crtc->pipe + 3));
989 WARN(cur_state != state,
990 "PLL[%d] not %s on this transcoder %c: %08x\n",
991 pll->pll_reg == _PCH_DPLL_B,
992 state_string(state),
993 pipe_name(crtc->pipe),
994 val);
995 }
996 }
997 }
998 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
999 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1000
1001 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, bool state)
1003 {
1004 int reg;
1005 u32 val;
1006 bool cur_state;
1007 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1008 pipe);
1009
1010 if (HAS_DDI(dev_priv->dev)) {
1011 /* DDI does not have a specific FDI_TX register */
1012 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1013 val = I915_READ(reg);
1014 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1015 } else {
1016 reg = FDI_TX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_TX_ENABLE);
1019 }
1020 WARN(cur_state != state,
1021 "FDI TX state assertion failure (expected %s, current %s)\n",
1022 state_string(state), state_string(cur_state));
1023 }
1024 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1025 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1026
1027 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1028 enum pipe pipe, bool state)
1029 {
1030 int reg;
1031 u32 val;
1032 bool cur_state;
1033
1034 reg = FDI_RX_CTL(pipe);
1035 val = I915_READ(reg);
1036 cur_state = !!(val & FDI_RX_ENABLE);
1037 WARN(cur_state != state,
1038 "FDI RX state assertion failure (expected %s, current %s)\n",
1039 state_string(state), state_string(cur_state));
1040 }
1041 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1042 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1043
1044 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1045 enum pipe pipe)
1046 {
1047 int reg;
1048 u32 val;
1049
1050 /* ILK FDI PLL is always enabled */
1051 if (dev_priv->info->gen == 5)
1052 return;
1053
1054 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1055 if (HAS_DDI(dev_priv->dev))
1056 return;
1057
1058 reg = FDI_TX_CTL(pipe);
1059 val = I915_READ(reg);
1060 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1061 }
1062
1063 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1064 enum pipe pipe)
1065 {
1066 int reg;
1067 u32 val;
1068
1069 reg = FDI_RX_CTL(pipe);
1070 val = I915_READ(reg);
1071 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1072 }
1073
1074 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1075 enum pipe pipe)
1076 {
1077 int pp_reg, lvds_reg;
1078 u32 val;
1079 enum pipe panel_pipe = PIPE_A;
1080 bool locked = true;
1081
1082 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1083 pp_reg = PCH_PP_CONTROL;
1084 lvds_reg = PCH_LVDS;
1085 } else {
1086 pp_reg = PP_CONTROL;
1087 lvds_reg = LVDS;
1088 }
1089
1090 val = I915_READ(pp_reg);
1091 if (!(val & PANEL_POWER_ON) ||
1092 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1093 locked = false;
1094
1095 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1096 panel_pipe = PIPE_B;
1097
1098 WARN(panel_pipe == pipe && locked,
1099 "panel assertion failure, pipe %c regs locked\n",
1100 pipe_name(pipe));
1101 }
1102
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
1105 {
1106 int reg;
1107 u32 val;
1108 bool cur_state;
1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
1111
1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114 state = true;
1115
1116 if (!intel_using_power_well(dev_priv->dev) &&
1117 cpu_transcoder != TRANSCODER_EDP) {
1118 cur_state = false;
1119 } else {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1123 }
1124
1125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
1127 pipe_name(pipe), state_string(state), state_string(cur_state));
1128 }
1129
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
1132 {
1133 int reg;
1134 u32 val;
1135 bool cur_state;
1136
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
1139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
1143 }
1144
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150 {
1151 int reg, i;
1152 u32 val;
1153 int cur_pipe;
1154
1155 /* Planes are fixed to pipes on ILK+ */
1156 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1157 reg = DSPCNTR(pipe);
1158 val = I915_READ(reg);
1159 WARN((val & DISPLAY_PLANE_ENABLE),
1160 "plane %c assertion failure, should be disabled but not\n",
1161 plane_name(pipe));
1162 return;
1163 }
1164
1165 /* Need to check both planes against the pipe */
1166 for (i = 0; i < 2; i++) {
1167 reg = DSPCNTR(i);
1168 val = I915_READ(reg);
1169 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1170 DISPPLANE_SEL_PIPE_SHIFT;
1171 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1172 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1173 plane_name(i), pipe_name(pipe));
1174 }
1175 }
1176
1177 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179 {
1180 int reg, i;
1181 u32 val;
1182
1183 if (!IS_VALLEYVIEW(dev_priv->dev))
1184 return;
1185
1186 /* Need to check both planes against the pipe */
1187 for (i = 0; i < dev_priv->num_plane; i++) {
1188 reg = SPCNTR(pipe, i);
1189 val = I915_READ(reg);
1190 WARN((val & SP_ENABLE),
1191 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1192 sprite_name(pipe, i), pipe_name(pipe));
1193 }
1194 }
1195
1196 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1197 {
1198 u32 val;
1199 bool enabled;
1200
1201 if (HAS_PCH_LPT(dev_priv->dev)) {
1202 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1203 return;
1204 }
1205
1206 val = I915_READ(PCH_DREF_CONTROL);
1207 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1208 DREF_SUPERSPREAD_SOURCE_MASK));
1209 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1210 }
1211
1212 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214 {
1215 int reg;
1216 u32 val;
1217 bool enabled;
1218
1219 reg = TRANSCONF(pipe);
1220 val = I915_READ(reg);
1221 enabled = !!(val & TRANS_ENABLE);
1222 WARN(enabled,
1223 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1224 pipe_name(pipe));
1225 }
1226
1227 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe, u32 port_sel, u32 val)
1229 {
1230 if ((val & DP_PORT_EN) == 0)
1231 return false;
1232
1233 if (HAS_PCH_CPT(dev_priv->dev)) {
1234 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1235 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1236 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1237 return false;
1238 } else {
1239 if ((val & DP_PIPE_MASK) != (pipe << 30))
1240 return false;
1241 }
1242 return true;
1243 }
1244
1245 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 val)
1247 {
1248 if ((val & SDVO_ENABLE) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1253 return false;
1254 } else {
1255 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1256 return false;
1257 }
1258 return true;
1259 }
1260
1261 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1262 enum pipe pipe, u32 val)
1263 {
1264 if ((val & LVDS_PORT_EN) == 0)
1265 return false;
1266
1267 if (HAS_PCH_CPT(dev_priv->dev)) {
1268 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1269 return false;
1270 } else {
1271 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1272 return false;
1273 }
1274 return true;
1275 }
1276
1277 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe, u32 val)
1279 {
1280 if ((val & ADPA_DAC_ENABLE) == 0)
1281 return false;
1282 if (HAS_PCH_CPT(dev_priv->dev)) {
1283 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284 return false;
1285 } else {
1286 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1287 return false;
1288 }
1289 return true;
1290 }
1291
1292 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, int reg, u32 port_sel)
1294 {
1295 u32 val = I915_READ(reg);
1296 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1297 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1298 reg, pipe_name(pipe));
1299
1300 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1301 && (val & DP_PIPEB_SELECT),
1302 "IBX PCH dp port still using transcoder B\n");
1303 }
1304
1305 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe, int reg)
1307 {
1308 u32 val = I915_READ(reg);
1309 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1310 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1311 reg, pipe_name(pipe));
1312
1313 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1314 && (val & SDVO_PIPE_B_SELECT),
1315 "IBX PCH hdmi port still using transcoder B\n");
1316 }
1317
1318 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1319 enum pipe pipe)
1320 {
1321 int reg;
1322 u32 val;
1323
1324 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1326 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1327
1328 reg = PCH_ADPA;
1329 val = I915_READ(reg);
1330 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1331 "PCH VGA enabled on transcoder %c, should be disabled\n",
1332 pipe_name(pipe));
1333
1334 reg = PCH_LVDS;
1335 val = I915_READ(reg);
1336 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1337 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1338 pipe_name(pipe));
1339
1340 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1342 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1343 }
1344
1345 /**
1346 * intel_enable_pll - enable a PLL
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe PLL to enable
1349 *
1350 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1351 * make sure the PLL reg is writable first though, since the panel write
1352 * protect mechanism may be enabled.
1353 *
1354 * Note! This is for pre-ILK only.
1355 *
1356 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1357 */
1358 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1359 {
1360 int reg;
1361 u32 val;
1362
1363 assert_pipe_disabled(dev_priv, pipe);
1364
1365 /* No really, not for ILK+ */
1366 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1367
1368 /* PLL is protected by panel, make sure we can write it */
1369 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1370 assert_panel_unlocked(dev_priv, pipe);
1371
1372 reg = DPLL(pipe);
1373 val = I915_READ(reg);
1374 val |= DPLL_VCO_ENABLE;
1375
1376 /* We do this three times for luck */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383 I915_WRITE(reg, val);
1384 POSTING_READ(reg);
1385 udelay(150); /* wait for warmup */
1386 }
1387
1388 /**
1389 * intel_disable_pll - disable a PLL
1390 * @dev_priv: i915 private structure
1391 * @pipe: pipe PLL to disable
1392 *
1393 * Disable the PLL for @pipe, making sure the pipe is off first.
1394 *
1395 * Note! This is for pre-ILK only.
1396 */
1397 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1398 {
1399 int reg;
1400 u32 val;
1401
1402 /* Don't disable pipe A or pipe A PLLs if needed */
1403 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1404 return;
1405
1406 /* Make sure the pipe isn't still relying on us */
1407 assert_pipe_disabled(dev_priv, pipe);
1408
1409 reg = DPLL(pipe);
1410 val = I915_READ(reg);
1411 val &= ~DPLL_VCO_ENABLE;
1412 I915_WRITE(reg, val);
1413 POSTING_READ(reg);
1414 }
1415
1416 /* SBI access */
1417 static void
1418 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1419 enum intel_sbi_destination destination)
1420 {
1421 u32 tmp;
1422
1423 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1424
1425 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1426 100)) {
1427 DRM_ERROR("timeout waiting for SBI to become ready\n");
1428 return;
1429 }
1430
1431 I915_WRITE(SBI_ADDR, (reg << 16));
1432 I915_WRITE(SBI_DATA, value);
1433
1434 if (destination == SBI_ICLK)
1435 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1436 else
1437 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1438 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1439
1440 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1441 100)) {
1442 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1443 return;
1444 }
1445 }
1446
1447 static u32
1448 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1449 enum intel_sbi_destination destination)
1450 {
1451 u32 value = 0;
1452 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1453
1454 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1455 100)) {
1456 DRM_ERROR("timeout waiting for SBI to become ready\n");
1457 return 0;
1458 }
1459
1460 I915_WRITE(SBI_ADDR, (reg << 16));
1461
1462 if (destination == SBI_ICLK)
1463 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1464 else
1465 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1466 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1467
1468 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1469 100)) {
1470 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1471 return 0;
1472 }
1473
1474 return I915_READ(SBI_DATA);
1475 }
1476
1477 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1478 {
1479 u32 port_mask;
1480
1481 if (!port)
1482 port_mask = DPLL_PORTB_READY_MASK;
1483 else
1484 port_mask = DPLL_PORTC_READY_MASK;
1485
1486 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1487 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1488 'B' + port, I915_READ(DPLL(0)));
1489 }
1490
1491 /**
1492 * ironlake_enable_pch_pll - enable PCH PLL
1493 * @dev_priv: i915 private structure
1494 * @pipe: pipe PLL to enable
1495 *
1496 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1497 * drives the transcoder clock.
1498 */
1499 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1500 {
1501 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1502 struct intel_pch_pll *pll;
1503 int reg;
1504 u32 val;
1505
1506 /* PCH PLLs only available on ILK, SNB and IVB */
1507 BUG_ON(dev_priv->info->gen < 5);
1508 pll = intel_crtc->pch_pll;
1509 if (pll == NULL)
1510 return;
1511
1512 if (WARN_ON(pll->refcount == 0))
1513 return;
1514
1515 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1516 pll->pll_reg, pll->active, pll->on,
1517 intel_crtc->base.base.id);
1518
1519 /* PCH refclock must be enabled first */
1520 assert_pch_refclk_enabled(dev_priv);
1521
1522 if (pll->active++ && pll->on) {
1523 assert_pch_pll_enabled(dev_priv, pll, NULL);
1524 return;
1525 }
1526
1527 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1528
1529 reg = pll->pll_reg;
1530 val = I915_READ(reg);
1531 val |= DPLL_VCO_ENABLE;
1532 I915_WRITE(reg, val);
1533 POSTING_READ(reg);
1534 udelay(200);
1535
1536 pll->on = true;
1537 }
1538
1539 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1540 {
1541 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1542 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1543 int reg;
1544 u32 val;
1545
1546 /* PCH only available on ILK+ */
1547 BUG_ON(dev_priv->info->gen < 5);
1548 if (pll == NULL)
1549 return;
1550
1551 if (WARN_ON(pll->refcount == 0))
1552 return;
1553
1554 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1555 pll->pll_reg, pll->active, pll->on,
1556 intel_crtc->base.base.id);
1557
1558 if (WARN_ON(pll->active == 0)) {
1559 assert_pch_pll_disabled(dev_priv, pll, NULL);
1560 return;
1561 }
1562
1563 if (--pll->active) {
1564 assert_pch_pll_enabled(dev_priv, pll, NULL);
1565 return;
1566 }
1567
1568 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1569
1570 /* Make sure transcoder isn't still depending on us */
1571 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1572
1573 reg = pll->pll_reg;
1574 val = I915_READ(reg);
1575 val &= ~DPLL_VCO_ENABLE;
1576 I915_WRITE(reg, val);
1577 POSTING_READ(reg);
1578 udelay(200);
1579
1580 pll->on = false;
1581 }
1582
1583 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
1585 {
1586 struct drm_device *dev = dev_priv->dev;
1587 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1588 uint32_t reg, val, pipeconf_val;
1589
1590 /* PCH only available on ILK+ */
1591 BUG_ON(dev_priv->info->gen < 5);
1592
1593 /* Make sure PCH DPLL is enabled */
1594 assert_pch_pll_enabled(dev_priv,
1595 to_intel_crtc(crtc)->pch_pll,
1596 to_intel_crtc(crtc));
1597
1598 /* FDI must be feeding us bits for PCH ports */
1599 assert_fdi_tx_enabled(dev_priv, pipe);
1600 assert_fdi_rx_enabled(dev_priv, pipe);
1601
1602 if (HAS_PCH_CPT(dev)) {
1603 /* Workaround: Set the timing override bit before enabling the
1604 * pch transcoder. */
1605 reg = TRANS_CHICKEN2(pipe);
1606 val = I915_READ(reg);
1607 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1608 I915_WRITE(reg, val);
1609 }
1610
1611 reg = TRANSCONF(pipe);
1612 val = I915_READ(reg);
1613 pipeconf_val = I915_READ(PIPECONF(pipe));
1614
1615 if (HAS_PCH_IBX(dev_priv->dev)) {
1616 /*
1617 * make the BPC in transcoder be consistent with
1618 * that in pipeconf reg.
1619 */
1620 val &= ~PIPECONF_BPC_MASK;
1621 val |= pipeconf_val & PIPECONF_BPC_MASK;
1622 }
1623
1624 val &= ~TRANS_INTERLACE_MASK;
1625 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1626 if (HAS_PCH_IBX(dev_priv->dev) &&
1627 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1628 val |= TRANS_LEGACY_INTERLACED_ILK;
1629 else
1630 val |= TRANS_INTERLACED;
1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
1634 I915_WRITE(reg, val | TRANS_ENABLE);
1635 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1636 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1637 }
1638
1639 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum transcoder cpu_transcoder)
1641 {
1642 u32 val, pipeconf_val;
1643
1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
1646
1647 /* FDI must be feeding us bits for PCH ports */
1648 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1649 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1650
1651 /* Workaround: set timing override bit. */
1652 val = I915_READ(_TRANSA_CHICKEN2);
1653 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1654 I915_WRITE(_TRANSA_CHICKEN2, val);
1655
1656 val = TRANS_ENABLE;
1657 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1658
1659 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1660 PIPECONF_INTERLACED_ILK)
1661 val |= TRANS_INTERLACED;
1662 else
1663 val |= TRANS_PROGRESSIVE;
1664
1665 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1666 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1667 DRM_ERROR("Failed to enable PCH transcoder\n");
1668 }
1669
1670 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1671 enum pipe pipe)
1672 {
1673 struct drm_device *dev = dev_priv->dev;
1674 uint32_t reg, val;
1675
1676 /* FDI relies on the transcoder */
1677 assert_fdi_tx_disabled(dev_priv, pipe);
1678 assert_fdi_rx_disabled(dev_priv, pipe);
1679
1680 /* Ports must be off as well */
1681 assert_pch_ports_disabled(dev_priv, pipe);
1682
1683 reg = TRANSCONF(pipe);
1684 val = I915_READ(reg);
1685 val &= ~TRANS_ENABLE;
1686 I915_WRITE(reg, val);
1687 /* wait for PCH transcoder off, transcoder state */
1688 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1689 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1690
1691 if (!HAS_PCH_IBX(dev)) {
1692 /* Workaround: Clear the timing override chicken bit again. */
1693 reg = TRANS_CHICKEN2(pipe);
1694 val = I915_READ(reg);
1695 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1696 I915_WRITE(reg, val);
1697 }
1698 }
1699
1700 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1701 {
1702 u32 val;
1703
1704 val = I915_READ(_TRANSACONF);
1705 val &= ~TRANS_ENABLE;
1706 I915_WRITE(_TRANSACONF, val);
1707 /* wait for PCH transcoder off, transcoder state */
1708 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1709 DRM_ERROR("Failed to disable PCH transcoder\n");
1710
1711 /* Workaround: clear timing override bit. */
1712 val = I915_READ(_TRANSA_CHICKEN2);
1713 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1714 I915_WRITE(_TRANSA_CHICKEN2, val);
1715 }
1716
1717 /**
1718 * intel_enable_pipe - enable a pipe, asserting requirements
1719 * @dev_priv: i915 private structure
1720 * @pipe: pipe to enable
1721 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1722 *
1723 * Enable @pipe, making sure that various hardware specific requirements
1724 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1725 *
1726 * @pipe should be %PIPE_A or %PIPE_B.
1727 *
1728 * Will wait until the pipe is actually running (i.e. first vblank) before
1729 * returning.
1730 */
1731 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1732 bool pch_port)
1733 {
1734 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1735 pipe);
1736 enum pipe pch_transcoder;
1737 int reg;
1738 u32 val;
1739
1740 assert_planes_disabled(dev_priv, pipe);
1741 assert_sprites_disabled(dev_priv, pipe);
1742
1743 if (HAS_PCH_LPT(dev_priv->dev))
1744 pch_transcoder = TRANSCODER_A;
1745 else
1746 pch_transcoder = pipe;
1747
1748 /*
1749 * A pipe without a PLL won't actually be able to drive bits from
1750 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1751 * need the check.
1752 */
1753 if (!HAS_PCH_SPLIT(dev_priv->dev))
1754 assert_pll_enabled(dev_priv, pipe);
1755 else {
1756 if (pch_port) {
1757 /* if driving the PCH, we need FDI enabled */
1758 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1759 assert_fdi_tx_pll_enabled(dev_priv,
1760 (enum pipe) cpu_transcoder);
1761 }
1762 /* FIXME: assert CPU port conditions for SNB+ */
1763 }
1764
1765 reg = PIPECONF(cpu_transcoder);
1766 val = I915_READ(reg);
1767 if (val & PIPECONF_ENABLE)
1768 return;
1769
1770 I915_WRITE(reg, val | PIPECONF_ENABLE);
1771 intel_wait_for_vblank(dev_priv->dev, pipe);
1772 }
1773
1774 /**
1775 * intel_disable_pipe - disable a pipe, asserting requirements
1776 * @dev_priv: i915 private structure
1777 * @pipe: pipe to disable
1778 *
1779 * Disable @pipe, making sure that various hardware specific requirements
1780 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1781 *
1782 * @pipe should be %PIPE_A or %PIPE_B.
1783 *
1784 * Will wait until the pipe has shut down before returning.
1785 */
1786 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1787 enum pipe pipe)
1788 {
1789 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1790 pipe);
1791 int reg;
1792 u32 val;
1793
1794 /*
1795 * Make sure planes won't keep trying to pump pixels to us,
1796 * or we might hang the display.
1797 */
1798 assert_planes_disabled(dev_priv, pipe);
1799 assert_sprites_disabled(dev_priv, pipe);
1800
1801 /* Don't disable pipe A or pipe A PLLs if needed */
1802 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1803 return;
1804
1805 reg = PIPECONF(cpu_transcoder);
1806 val = I915_READ(reg);
1807 if ((val & PIPECONF_ENABLE) == 0)
1808 return;
1809
1810 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1811 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1812 }
1813
1814 /*
1815 * Plane regs are double buffered, going from enabled->disabled needs a
1816 * trigger in order to latch. The display address reg provides this.
1817 */
1818 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1819 enum plane plane)
1820 {
1821 if (dev_priv->info->gen >= 4)
1822 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1823 else
1824 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1825 }
1826
1827 /**
1828 * intel_enable_plane - enable a display plane on a given pipe
1829 * @dev_priv: i915 private structure
1830 * @plane: plane to enable
1831 * @pipe: pipe being fed
1832 *
1833 * Enable @plane on @pipe, making sure that @pipe is running first.
1834 */
1835 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1836 enum plane plane, enum pipe pipe)
1837 {
1838 int reg;
1839 u32 val;
1840
1841 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1842 assert_pipe_enabled(dev_priv, pipe);
1843
1844 reg = DSPCNTR(plane);
1845 val = I915_READ(reg);
1846 if (val & DISPLAY_PLANE_ENABLE)
1847 return;
1848
1849 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1850 intel_flush_display_plane(dev_priv, plane);
1851 intel_wait_for_vblank(dev_priv->dev, pipe);
1852 }
1853
1854 /**
1855 * intel_disable_plane - disable a display plane
1856 * @dev_priv: i915 private structure
1857 * @plane: plane to disable
1858 * @pipe: pipe consuming the data
1859 *
1860 * Disable @plane; should be an independent operation.
1861 */
1862 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1863 enum plane plane, enum pipe pipe)
1864 {
1865 int reg;
1866 u32 val;
1867
1868 reg = DSPCNTR(plane);
1869 val = I915_READ(reg);
1870 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1871 return;
1872
1873 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1874 intel_flush_display_plane(dev_priv, plane);
1875 intel_wait_for_vblank(dev_priv->dev, pipe);
1876 }
1877
1878 static bool need_vtd_wa(struct drm_device *dev)
1879 {
1880 #ifdef CONFIG_INTEL_IOMMU
1881 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1882 return true;
1883 #endif
1884 return false;
1885 }
1886
1887 int
1888 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1889 struct drm_i915_gem_object *obj,
1890 struct intel_ring_buffer *pipelined)
1891 {
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1893 u32 alignment;
1894 int ret;
1895
1896 switch (obj->tiling_mode) {
1897 case I915_TILING_NONE:
1898 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1899 alignment = 128 * 1024;
1900 else if (INTEL_INFO(dev)->gen >= 4)
1901 alignment = 4 * 1024;
1902 else
1903 alignment = 64 * 1024;
1904 break;
1905 case I915_TILING_X:
1906 /* pin() will align the object as required by fence */
1907 alignment = 0;
1908 break;
1909 case I915_TILING_Y:
1910 /* Despite that we check this in framebuffer_init userspace can
1911 * screw us over and change the tiling after the fact. Only
1912 * pinned buffers can't change their tiling. */
1913 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1914 return -EINVAL;
1915 default:
1916 BUG();
1917 }
1918
1919 /* Note that the w/a also requires 64 PTE of padding following the
1920 * bo. We currently fill all unused PTE with the shadow page and so
1921 * we should always have valid PTE following the scanout preventing
1922 * the VT-d warning.
1923 */
1924 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1925 alignment = 256 * 1024;
1926
1927 dev_priv->mm.interruptible = false;
1928 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1929 if (ret)
1930 goto err_interruptible;
1931
1932 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1933 * fence, whereas 965+ only requires a fence if using
1934 * framebuffer compression. For simplicity, we always install
1935 * a fence as the cost is not that onerous.
1936 */
1937 ret = i915_gem_object_get_fence(obj);
1938 if (ret)
1939 goto err_unpin;
1940
1941 i915_gem_object_pin_fence(obj);
1942
1943 dev_priv->mm.interruptible = true;
1944 return 0;
1945
1946 err_unpin:
1947 i915_gem_object_unpin(obj);
1948 err_interruptible:
1949 dev_priv->mm.interruptible = true;
1950 return ret;
1951 }
1952
1953 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1954 {
1955 i915_gem_object_unpin_fence(obj);
1956 i915_gem_object_unpin(obj);
1957 }
1958
1959 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1960 * is assumed to be a power-of-two. */
1961 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1962 unsigned int tiling_mode,
1963 unsigned int cpp,
1964 unsigned int pitch)
1965 {
1966 if (tiling_mode != I915_TILING_NONE) {
1967 unsigned int tile_rows, tiles;
1968
1969 tile_rows = *y / 8;
1970 *y %= 8;
1971
1972 tiles = *x / (512/cpp);
1973 *x %= 512/cpp;
1974
1975 return tile_rows * pitch * 8 + tiles * 4096;
1976 } else {
1977 unsigned int offset;
1978
1979 offset = *y * pitch + *x * cpp;
1980 *y = 0;
1981 *x = (offset & 4095) / cpp;
1982 return offset & -4096;
1983 }
1984 }
1985
1986 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1987 int x, int y)
1988 {
1989 struct drm_device *dev = crtc->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1992 struct intel_framebuffer *intel_fb;
1993 struct drm_i915_gem_object *obj;
1994 int plane = intel_crtc->plane;
1995 unsigned long linear_offset;
1996 u32 dspcntr;
1997 u32 reg;
1998
1999 switch (plane) {
2000 case 0:
2001 case 1:
2002 break;
2003 default:
2004 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2005 return -EINVAL;
2006 }
2007
2008 intel_fb = to_intel_framebuffer(fb);
2009 obj = intel_fb->obj;
2010
2011 reg = DSPCNTR(plane);
2012 dspcntr = I915_READ(reg);
2013 /* Mask out pixel format bits in case we change it */
2014 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2015 switch (fb->pixel_format) {
2016 case DRM_FORMAT_C8:
2017 dspcntr |= DISPPLANE_8BPP;
2018 break;
2019 case DRM_FORMAT_XRGB1555:
2020 case DRM_FORMAT_ARGB1555:
2021 dspcntr |= DISPPLANE_BGRX555;
2022 break;
2023 case DRM_FORMAT_RGB565:
2024 dspcntr |= DISPPLANE_BGRX565;
2025 break;
2026 case DRM_FORMAT_XRGB8888:
2027 case DRM_FORMAT_ARGB8888:
2028 dspcntr |= DISPPLANE_BGRX888;
2029 break;
2030 case DRM_FORMAT_XBGR8888:
2031 case DRM_FORMAT_ABGR8888:
2032 dspcntr |= DISPPLANE_RGBX888;
2033 break;
2034 case DRM_FORMAT_XRGB2101010:
2035 case DRM_FORMAT_ARGB2101010:
2036 dspcntr |= DISPPLANE_BGRX101010;
2037 break;
2038 case DRM_FORMAT_XBGR2101010:
2039 case DRM_FORMAT_ABGR2101010:
2040 dspcntr |= DISPPLANE_RGBX101010;
2041 break;
2042 default:
2043 BUG();
2044 }
2045
2046 if (INTEL_INFO(dev)->gen >= 4) {
2047 if (obj->tiling_mode != I915_TILING_NONE)
2048 dspcntr |= DISPPLANE_TILED;
2049 else
2050 dspcntr &= ~DISPPLANE_TILED;
2051 }
2052
2053 I915_WRITE(reg, dspcntr);
2054
2055 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2056
2057 if (INTEL_INFO(dev)->gen >= 4) {
2058 intel_crtc->dspaddr_offset =
2059 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2060 fb->bits_per_pixel / 8,
2061 fb->pitches[0]);
2062 linear_offset -= intel_crtc->dspaddr_offset;
2063 } else {
2064 intel_crtc->dspaddr_offset = linear_offset;
2065 }
2066
2067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2070 if (INTEL_INFO(dev)->gen >= 4) {
2071 I915_MODIFY_DISPBASE(DSPSURF(plane),
2072 obj->gtt_offset + intel_crtc->dspaddr_offset);
2073 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2074 I915_WRITE(DSPLINOFF(plane), linear_offset);
2075 } else
2076 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2077 POSTING_READ(reg);
2078
2079 return 0;
2080 }
2081
2082 static int ironlake_update_plane(struct drm_crtc *crtc,
2083 struct drm_framebuffer *fb, int x, int y)
2084 {
2085 struct drm_device *dev = crtc->dev;
2086 struct drm_i915_private *dev_priv = dev->dev_private;
2087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2088 struct intel_framebuffer *intel_fb;
2089 struct drm_i915_gem_object *obj;
2090 int plane = intel_crtc->plane;
2091 unsigned long linear_offset;
2092 u32 dspcntr;
2093 u32 reg;
2094
2095 switch (plane) {
2096 case 0:
2097 case 1:
2098 case 2:
2099 break;
2100 default:
2101 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2102 return -EINVAL;
2103 }
2104
2105 intel_fb = to_intel_framebuffer(fb);
2106 obj = intel_fb->obj;
2107
2108 reg = DSPCNTR(plane);
2109 dspcntr = I915_READ(reg);
2110 /* Mask out pixel format bits in case we change it */
2111 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2112 switch (fb->pixel_format) {
2113 case DRM_FORMAT_C8:
2114 dspcntr |= DISPPLANE_8BPP;
2115 break;
2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
2118 break;
2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
2134 break;
2135 default:
2136 BUG();
2137 }
2138
2139 if (obj->tiling_mode != I915_TILING_NONE)
2140 dspcntr |= DISPPLANE_TILED;
2141 else
2142 dspcntr &= ~DISPPLANE_TILED;
2143
2144 /* must disable */
2145 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2146
2147 I915_WRITE(reg, dspcntr);
2148
2149 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2150 intel_crtc->dspaddr_offset =
2151 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2152 fb->bits_per_pixel / 8,
2153 fb->pitches[0]);
2154 linear_offset -= intel_crtc->dspaddr_offset;
2155
2156 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2157 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2158 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2159 I915_MODIFY_DISPBASE(DSPSURF(plane),
2160 obj->gtt_offset + intel_crtc->dspaddr_offset);
2161 if (IS_HASWELL(dev)) {
2162 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2163 } else {
2164 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2165 I915_WRITE(DSPLINOFF(plane), linear_offset);
2166 }
2167 POSTING_READ(reg);
2168
2169 return 0;
2170 }
2171
2172 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2173 static int
2174 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2175 int x, int y, enum mode_set_atomic state)
2176 {
2177 struct drm_device *dev = crtc->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179
2180 if (dev_priv->display.disable_fbc)
2181 dev_priv->display.disable_fbc(dev);
2182 intel_increase_pllclock(crtc);
2183
2184 return dev_priv->display.update_plane(crtc, fb, x, y);
2185 }
2186
2187 void intel_display_handle_reset(struct drm_device *dev)
2188 {
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190 struct drm_crtc *crtc;
2191
2192 /*
2193 * Flips in the rings have been nuked by the reset,
2194 * so complete all pending flips so that user space
2195 * will get its events and not get stuck.
2196 *
2197 * Also update the base address of all primary
2198 * planes to the the last fb to make sure we're
2199 * showing the correct fb after a reset.
2200 *
2201 * Need to make two loops over the crtcs so that we
2202 * don't try to grab a crtc mutex before the
2203 * pending_flip_queue really got woken up.
2204 */
2205
2206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2208 enum plane plane = intel_crtc->plane;
2209
2210 intel_prepare_page_flip(dev, plane);
2211 intel_finish_page_flip_plane(dev, plane);
2212 }
2213
2214 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216
2217 mutex_lock(&crtc->mutex);
2218 if (intel_crtc->active)
2219 dev_priv->display.update_plane(crtc, crtc->fb,
2220 crtc->x, crtc->y);
2221 mutex_unlock(&crtc->mutex);
2222 }
2223 }
2224
2225 static int
2226 intel_finish_fb(struct drm_framebuffer *old_fb)
2227 {
2228 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2229 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2230 bool was_interruptible = dev_priv->mm.interruptible;
2231 int ret;
2232
2233 /* Big Hammer, we also need to ensure that any pending
2234 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2235 * current scanout is retired before unpinning the old
2236 * framebuffer.
2237 *
2238 * This should only fail upon a hung GPU, in which case we
2239 * can safely continue.
2240 */
2241 dev_priv->mm.interruptible = false;
2242 ret = i915_gem_object_finish_gpu(obj);
2243 dev_priv->mm.interruptible = was_interruptible;
2244
2245 return ret;
2246 }
2247
2248 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2249 {
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_master_private *master_priv;
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253
2254 if (!dev->primary->master)
2255 return;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return;
2260
2261 switch (intel_crtc->pipe) {
2262 case 0:
2263 master_priv->sarea_priv->pipeA_x = x;
2264 master_priv->sarea_priv->pipeA_y = y;
2265 break;
2266 case 1:
2267 master_priv->sarea_priv->pipeB_x = x;
2268 master_priv->sarea_priv->pipeB_y = y;
2269 break;
2270 default:
2271 break;
2272 }
2273 }
2274
2275 static int
2276 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2277 struct drm_framebuffer *fb)
2278 {
2279 struct drm_device *dev = crtc->dev;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2282 struct drm_framebuffer *old_fb;
2283 int ret;
2284
2285 /* no fb bound */
2286 if (!fb) {
2287 DRM_ERROR("No FB bound\n");
2288 return 0;
2289 }
2290
2291 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2292 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2293 plane_name(intel_crtc->plane),
2294 INTEL_INFO(dev)->num_pipes);
2295 return -EINVAL;
2296 }
2297
2298 mutex_lock(&dev->struct_mutex);
2299 ret = intel_pin_and_fence_fb_obj(dev,
2300 to_intel_framebuffer(fb)->obj,
2301 NULL);
2302 if (ret != 0) {
2303 mutex_unlock(&dev->struct_mutex);
2304 DRM_ERROR("pin & fence failed\n");
2305 return ret;
2306 }
2307
2308 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2309 if (ret) {
2310 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2311 mutex_unlock(&dev->struct_mutex);
2312 DRM_ERROR("failed to update base address\n");
2313 return ret;
2314 }
2315
2316 old_fb = crtc->fb;
2317 crtc->fb = fb;
2318 crtc->x = x;
2319 crtc->y = y;
2320
2321 if (old_fb) {
2322 intel_wait_for_vblank(dev, intel_crtc->pipe);
2323 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2324 }
2325
2326 intel_update_fbc(dev);
2327 mutex_unlock(&dev->struct_mutex);
2328
2329 intel_crtc_update_sarea_pos(crtc, x, y);
2330
2331 return 0;
2332 }
2333
2334 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2335 {
2336 struct drm_device *dev = crtc->dev;
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2339 int pipe = intel_crtc->pipe;
2340 u32 reg, temp;
2341
2342 /* enable normal train */
2343 reg = FDI_TX_CTL(pipe);
2344 temp = I915_READ(reg);
2345 if (IS_IVYBRIDGE(dev)) {
2346 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2347 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2348 } else {
2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2351 }
2352 I915_WRITE(reg, temp);
2353
2354 reg = FDI_RX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 if (HAS_PCH_CPT(dev)) {
2357 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2358 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2359 } else {
2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_NONE;
2362 }
2363 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2364
2365 /* wait one idle pattern time */
2366 POSTING_READ(reg);
2367 udelay(1000);
2368
2369 /* IVB wants error correction enabled */
2370 if (IS_IVYBRIDGE(dev))
2371 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2372 FDI_FE_ERRC_ENABLE);
2373 }
2374
2375 static void ivb_modeset_global_resources(struct drm_device *dev)
2376 {
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_crtc *pipe_B_crtc =
2379 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2380 struct intel_crtc *pipe_C_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2382 uint32_t temp;
2383
2384 /* When everything is off disable fdi C so that we could enable fdi B
2385 * with all lanes. XXX: This misses the case where a pipe is not using
2386 * any pch resources and so doesn't need any fdi lanes. */
2387 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2389 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2390
2391 temp = I915_READ(SOUTH_CHICKEN1);
2392 temp &= ~FDI_BC_BIFURCATION_SELECT;
2393 DRM_DEBUG_KMS("disabling fdi C rx\n");
2394 I915_WRITE(SOUTH_CHICKEN1, temp);
2395 }
2396 }
2397
2398 /* The FDI link training functions for ILK/Ibexpeak. */
2399 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2400 {
2401 struct drm_device *dev = crtc->dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2404 int pipe = intel_crtc->pipe;
2405 int plane = intel_crtc->plane;
2406 u32 reg, temp, tries;
2407
2408 /* FDI needs bits from pipe & plane first */
2409 assert_pipe_enabled(dev_priv, pipe);
2410 assert_plane_enabled(dev_priv, plane);
2411
2412 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2413 for train result */
2414 reg = FDI_RX_IMR(pipe);
2415 temp = I915_READ(reg);
2416 temp &= ~FDI_RX_SYMBOL_LOCK;
2417 temp &= ~FDI_RX_BIT_LOCK;
2418 I915_WRITE(reg, temp);
2419 I915_READ(reg);
2420 udelay(150);
2421
2422 /* enable CPU FDI TX and PCH FDI RX */
2423 reg = FDI_TX_CTL(pipe);
2424 temp = I915_READ(reg);
2425 temp &= ~(7 << 19);
2426 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_1;
2429 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2430
2431 reg = FDI_RX_CTL(pipe);
2432 temp = I915_READ(reg);
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
2435 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437 POSTING_READ(reg);
2438 udelay(150);
2439
2440 /* Ironlake workaround, enable clock pointer after FDI enable*/
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2442 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2443 FDI_RX_PHASE_SYNC_POINTER_EN);
2444
2445 reg = FDI_RX_IIR(pipe);
2446 for (tries = 0; tries < 5; tries++) {
2447 temp = I915_READ(reg);
2448 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449
2450 if ((temp & FDI_RX_BIT_LOCK)) {
2451 DRM_DEBUG_KMS("FDI train 1 done.\n");
2452 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2453 break;
2454 }
2455 }
2456 if (tries == 5)
2457 DRM_ERROR("FDI train 1 fail!\n");
2458
2459 /* Train 2 */
2460 reg = FDI_TX_CTL(pipe);
2461 temp = I915_READ(reg);
2462 temp &= ~FDI_LINK_TRAIN_NONE;
2463 temp |= FDI_LINK_TRAIN_PATTERN_2;
2464 I915_WRITE(reg, temp);
2465
2466 reg = FDI_RX_CTL(pipe);
2467 temp = I915_READ(reg);
2468 temp &= ~FDI_LINK_TRAIN_NONE;
2469 temp |= FDI_LINK_TRAIN_PATTERN_2;
2470 I915_WRITE(reg, temp);
2471
2472 POSTING_READ(reg);
2473 udelay(150);
2474
2475 reg = FDI_RX_IIR(pipe);
2476 for (tries = 0; tries < 5; tries++) {
2477 temp = I915_READ(reg);
2478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2479
2480 if (temp & FDI_RX_SYMBOL_LOCK) {
2481 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2482 DRM_DEBUG_KMS("FDI train 2 done.\n");
2483 break;
2484 }
2485 }
2486 if (tries == 5)
2487 DRM_ERROR("FDI train 2 fail!\n");
2488
2489 DRM_DEBUG_KMS("FDI train done\n");
2490
2491 }
2492
2493 static const int snb_b_fdi_train_param[] = {
2494 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2495 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2496 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2497 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2498 };
2499
2500 /* The FDI link training functions for SNB/Cougarpoint. */
2501 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2502 {
2503 struct drm_device *dev = crtc->dev;
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506 int pipe = intel_crtc->pipe;
2507 u32 reg, temp, i, retry;
2508
2509 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2510 for train result */
2511 reg = FDI_RX_IMR(pipe);
2512 temp = I915_READ(reg);
2513 temp &= ~FDI_RX_SYMBOL_LOCK;
2514 temp &= ~FDI_RX_BIT_LOCK;
2515 I915_WRITE(reg, temp);
2516
2517 POSTING_READ(reg);
2518 udelay(150);
2519
2520 /* enable CPU FDI TX and PCH FDI RX */
2521 reg = FDI_TX_CTL(pipe);
2522 temp = I915_READ(reg);
2523 temp &= ~(7 << 19);
2524 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_1;
2527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 /* SNB-B */
2529 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2530 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2531
2532 I915_WRITE(FDI_RX_MISC(pipe),
2533 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2534
2535 reg = FDI_RX_CTL(pipe);
2536 temp = I915_READ(reg);
2537 if (HAS_PCH_CPT(dev)) {
2538 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2539 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2540 } else {
2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_1;
2543 }
2544 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2545
2546 POSTING_READ(reg);
2547 udelay(150);
2548
2549 for (i = 0; i < 4; i++) {
2550 reg = FDI_TX_CTL(pipe);
2551 temp = I915_READ(reg);
2552 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553 temp |= snb_b_fdi_train_param[i];
2554 I915_WRITE(reg, temp);
2555
2556 POSTING_READ(reg);
2557 udelay(500);
2558
2559 for (retry = 0; retry < 5; retry++) {
2560 reg = FDI_RX_IIR(pipe);
2561 temp = I915_READ(reg);
2562 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2563 if (temp & FDI_RX_BIT_LOCK) {
2564 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2565 DRM_DEBUG_KMS("FDI train 1 done.\n");
2566 break;
2567 }
2568 udelay(50);
2569 }
2570 if (retry < 5)
2571 break;
2572 }
2573 if (i == 4)
2574 DRM_ERROR("FDI train 1 fail!\n");
2575
2576 /* Train 2 */
2577 reg = FDI_TX_CTL(pipe);
2578 temp = I915_READ(reg);
2579 temp &= ~FDI_LINK_TRAIN_NONE;
2580 temp |= FDI_LINK_TRAIN_PATTERN_2;
2581 if (IS_GEN6(dev)) {
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 /* SNB-B */
2584 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585 }
2586 I915_WRITE(reg, temp);
2587
2588 reg = FDI_RX_CTL(pipe);
2589 temp = I915_READ(reg);
2590 if (HAS_PCH_CPT(dev)) {
2591 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2592 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2593 } else {
2594 temp &= ~FDI_LINK_TRAIN_NONE;
2595 temp |= FDI_LINK_TRAIN_PATTERN_2;
2596 }
2597 I915_WRITE(reg, temp);
2598
2599 POSTING_READ(reg);
2600 udelay(150);
2601
2602 for (i = 0; i < 4; i++) {
2603 reg = FDI_TX_CTL(pipe);
2604 temp = I915_READ(reg);
2605 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2606 temp |= snb_b_fdi_train_param[i];
2607 I915_WRITE(reg, temp);
2608
2609 POSTING_READ(reg);
2610 udelay(500);
2611
2612 for (retry = 0; retry < 5; retry++) {
2613 reg = FDI_RX_IIR(pipe);
2614 temp = I915_READ(reg);
2615 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2616 if (temp & FDI_RX_SYMBOL_LOCK) {
2617 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2618 DRM_DEBUG_KMS("FDI train 2 done.\n");
2619 break;
2620 }
2621 udelay(50);
2622 }
2623 if (retry < 5)
2624 break;
2625 }
2626 if (i == 4)
2627 DRM_ERROR("FDI train 2 fail!\n");
2628
2629 DRM_DEBUG_KMS("FDI train done.\n");
2630 }
2631
2632 /* Manual link training for Ivy Bridge A0 parts */
2633 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2634 {
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638 int pipe = intel_crtc->pipe;
2639 u32 reg, temp, i;
2640
2641 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2642 for train result */
2643 reg = FDI_RX_IMR(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_RX_SYMBOL_LOCK;
2646 temp &= ~FDI_RX_BIT_LOCK;
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(150);
2651
2652 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2653 I915_READ(FDI_RX_IIR(pipe)));
2654
2655 /* enable CPU FDI TX and PCH FDI RX */
2656 reg = FDI_TX_CTL(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~(7 << 19);
2659 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2660 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2661 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2664 temp |= FDI_COMPOSITE_SYNC;
2665 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2666
2667 I915_WRITE(FDI_RX_MISC(pipe),
2668 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2669
2670 reg = FDI_RX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_AUTO;
2673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2674 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2675 temp |= FDI_COMPOSITE_SYNC;
2676 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2677
2678 POSTING_READ(reg);
2679 udelay(150);
2680
2681 for (i = 0; i < 4; i++) {
2682 reg = FDI_TX_CTL(pipe);
2683 temp = I915_READ(reg);
2684 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685 temp |= snb_b_fdi_train_param[i];
2686 I915_WRITE(reg, temp);
2687
2688 POSTING_READ(reg);
2689 udelay(500);
2690
2691 reg = FDI_RX_IIR(pipe);
2692 temp = I915_READ(reg);
2693 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694
2695 if (temp & FDI_RX_BIT_LOCK ||
2696 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2697 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2698 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2699 break;
2700 }
2701 }
2702 if (i == 4)
2703 DRM_ERROR("FDI train 1 fail!\n");
2704
2705 /* Train 2 */
2706 reg = FDI_TX_CTL(pipe);
2707 temp = I915_READ(reg);
2708 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2709 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2710 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2711 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2712 I915_WRITE(reg, temp);
2713
2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2717 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2718 I915_WRITE(reg, temp);
2719
2720 POSTING_READ(reg);
2721 udelay(150);
2722
2723 for (i = 0; i < 4; i++) {
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727 temp |= snb_b_fdi_train_param[i];
2728 I915_WRITE(reg, temp);
2729
2730 POSTING_READ(reg);
2731 udelay(500);
2732
2733 reg = FDI_RX_IIR(pipe);
2734 temp = I915_READ(reg);
2735 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2736
2737 if (temp & FDI_RX_SYMBOL_LOCK) {
2738 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2739 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2740 break;
2741 }
2742 }
2743 if (i == 4)
2744 DRM_ERROR("FDI train 2 fail!\n");
2745
2746 DRM_DEBUG_KMS("FDI train done.\n");
2747 }
2748
2749 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2750 {
2751 struct drm_device *dev = intel_crtc->base.dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 int pipe = intel_crtc->pipe;
2754 u32 reg, temp;
2755
2756
2757 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2758 reg = FDI_RX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~((0x7 << 19) | (0x7 << 16));
2761 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2762 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2763 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2764
2765 POSTING_READ(reg);
2766 udelay(200);
2767
2768 /* Switch from Rawclk to PCDclk */
2769 temp = I915_READ(reg);
2770 I915_WRITE(reg, temp | FDI_PCDCLK);
2771
2772 POSTING_READ(reg);
2773 udelay(200);
2774
2775 /* Enable CPU FDI TX PLL, always on for Ironlake */
2776 reg = FDI_TX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2779 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2780
2781 POSTING_READ(reg);
2782 udelay(100);
2783 }
2784 }
2785
2786 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2787 {
2788 struct drm_device *dev = intel_crtc->base.dev;
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 int pipe = intel_crtc->pipe;
2791 u32 reg, temp;
2792
2793 /* Switch from PCDclk to Rawclk */
2794 reg = FDI_RX_CTL(pipe);
2795 temp = I915_READ(reg);
2796 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2797
2798 /* Disable CPU FDI TX PLL */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805
2806 reg = FDI_RX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2809
2810 /* Wait for the clocks to turn off. */
2811 POSTING_READ(reg);
2812 udelay(100);
2813 }
2814
2815 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2816 {
2817 struct drm_device *dev = crtc->dev;
2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2820 int pipe = intel_crtc->pipe;
2821 u32 reg, temp;
2822
2823 /* disable CPU FDI tx and PCH FDI rx */
2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2827 POSTING_READ(reg);
2828
2829 reg = FDI_RX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~(0x7 << 16);
2832 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2833 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2834
2835 POSTING_READ(reg);
2836 udelay(100);
2837
2838 /* Ironlake workaround, disable clock pointer after downing FDI */
2839 if (HAS_PCH_IBX(dev)) {
2840 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2841 }
2842
2843 /* still set train pattern 1 */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 I915_WRITE(reg, temp);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if (HAS_PCH_CPT(dev)) {
2853 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 } else {
2856 temp &= ~FDI_LINK_TRAIN_NONE;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 }
2859 /* BPC in FDI rx is consistent with that in PIPECONF */
2860 temp &= ~(0x07 << 16);
2861 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2862 I915_WRITE(reg, temp);
2863
2864 POSTING_READ(reg);
2865 udelay(100);
2866 }
2867
2868 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2869 {
2870 struct drm_device *dev = crtc->dev;
2871 struct drm_i915_private *dev_priv = dev->dev_private;
2872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2873 unsigned long flags;
2874 bool pending;
2875
2876 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2877 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2878 return false;
2879
2880 spin_lock_irqsave(&dev->event_lock, flags);
2881 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2882 spin_unlock_irqrestore(&dev->event_lock, flags);
2883
2884 return pending;
2885 }
2886
2887 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2888 {
2889 struct drm_device *dev = crtc->dev;
2890 struct drm_i915_private *dev_priv = dev->dev_private;
2891
2892 if (crtc->fb == NULL)
2893 return;
2894
2895 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2896
2897 wait_event(dev_priv->pending_flip_queue,
2898 !intel_crtc_has_pending_flip(crtc));
2899
2900 mutex_lock(&dev->struct_mutex);
2901 intel_finish_fb(crtc->fb);
2902 mutex_unlock(&dev->struct_mutex);
2903 }
2904
2905 /* Program iCLKIP clock to the desired frequency */
2906 static void lpt_program_iclkip(struct drm_crtc *crtc)
2907 {
2908 struct drm_device *dev = crtc->dev;
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2911 u32 temp;
2912
2913 mutex_lock(&dev_priv->dpio_lock);
2914
2915 /* It is necessary to ungate the pixclk gate prior to programming
2916 * the divisors, and gate it back when it is done.
2917 */
2918 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2919
2920 /* Disable SSCCTL */
2921 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2922 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2923 SBI_SSCCTL_DISABLE,
2924 SBI_ICLK);
2925
2926 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2927 if (crtc->mode.clock == 20000) {
2928 auxdiv = 1;
2929 divsel = 0x41;
2930 phaseinc = 0x20;
2931 } else {
2932 /* The iCLK virtual clock root frequency is in MHz,
2933 * but the crtc->mode.clock in in KHz. To get the divisors,
2934 * it is necessary to divide one by another, so we
2935 * convert the virtual clock precision to KHz here for higher
2936 * precision.
2937 */
2938 u32 iclk_virtual_root_freq = 172800 * 1000;
2939 u32 iclk_pi_range = 64;
2940 u32 desired_divisor, msb_divisor_value, pi_value;
2941
2942 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2943 msb_divisor_value = desired_divisor / iclk_pi_range;
2944 pi_value = desired_divisor % iclk_pi_range;
2945
2946 auxdiv = 0;
2947 divsel = msb_divisor_value - 2;
2948 phaseinc = pi_value;
2949 }
2950
2951 /* This should not happen with any sane values */
2952 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2953 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2954 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2955 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2956
2957 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2958 crtc->mode.clock,
2959 auxdiv,
2960 divsel,
2961 phasedir,
2962 phaseinc);
2963
2964 /* Program SSCDIVINTPHASE6 */
2965 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2966 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2967 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2968 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2969 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2970 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2971 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2972 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2973
2974 /* Program SSCAUXDIV */
2975 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2976 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2977 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2978 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2979
2980 /* Enable modulator and associated divider */
2981 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2982 temp &= ~SBI_SSCCTL_DISABLE;
2983 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2984
2985 /* Wait for initialization time */
2986 udelay(24);
2987
2988 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2989
2990 mutex_unlock(&dev_priv->dpio_lock);
2991 }
2992
2993 /*
2994 * Enable PCH resources required for PCH ports:
2995 * - PCH PLLs
2996 * - FDI training & RX/TX
2997 * - update transcoder timings
2998 * - DP transcoding bits
2999 * - transcoder
3000 */
3001 static void ironlake_pch_enable(struct drm_crtc *crtc)
3002 {
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006 int pipe = intel_crtc->pipe;
3007 u32 reg, temp;
3008
3009 assert_transcoder_disabled(dev_priv, pipe);
3010
3011 /* Write the TU size bits before fdi link training, so that error
3012 * detection works. */
3013 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3014 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3015
3016 /* For PCH output, training FDI link */
3017 dev_priv->display.fdi_link_train(crtc);
3018
3019 /* XXX: pch pll's can be enabled any time before we enable the PCH
3020 * transcoder, and we actually should do this to not upset any PCH
3021 * transcoder that already use the clock when we share it.
3022 *
3023 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3024 * unconditionally resets the pll - we need that to have the right LVDS
3025 * enable sequence. */
3026 ironlake_enable_pch_pll(intel_crtc);
3027
3028 if (HAS_PCH_CPT(dev)) {
3029 u32 sel;
3030
3031 temp = I915_READ(PCH_DPLL_SEL);
3032 switch (pipe) {
3033 default:
3034 case 0:
3035 temp |= TRANSA_DPLL_ENABLE;
3036 sel = TRANSA_DPLLB_SEL;
3037 break;
3038 case 1:
3039 temp |= TRANSB_DPLL_ENABLE;
3040 sel = TRANSB_DPLLB_SEL;
3041 break;
3042 case 2:
3043 temp |= TRANSC_DPLL_ENABLE;
3044 sel = TRANSC_DPLLB_SEL;
3045 break;
3046 }
3047 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3048 temp |= sel;
3049 else
3050 temp &= ~sel;
3051 I915_WRITE(PCH_DPLL_SEL, temp);
3052 }
3053
3054 /* set transcoder timing, panel must allow it */
3055 assert_panel_unlocked(dev_priv, pipe);
3056 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3057 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3058 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3059
3060 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3061 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3062 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3063 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3064
3065 intel_fdi_normal_train(crtc);
3066
3067 /* For PCH DP, enable TRANS_DP_CTL */
3068 if (HAS_PCH_CPT(dev) &&
3069 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3070 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3071 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3072 reg = TRANS_DP_CTL(pipe);
3073 temp = I915_READ(reg);
3074 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3075 TRANS_DP_SYNC_MASK |
3076 TRANS_DP_BPC_MASK);
3077 temp |= (TRANS_DP_OUTPUT_ENABLE |
3078 TRANS_DP_ENH_FRAMING);
3079 temp |= bpc << 9; /* same format but at 11:9 */
3080
3081 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3082 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3083 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3084 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3085
3086 switch (intel_trans_dp_port_sel(crtc)) {
3087 case PCH_DP_B:
3088 temp |= TRANS_DP_PORT_SEL_B;
3089 break;
3090 case PCH_DP_C:
3091 temp |= TRANS_DP_PORT_SEL_C;
3092 break;
3093 case PCH_DP_D:
3094 temp |= TRANS_DP_PORT_SEL_D;
3095 break;
3096 default:
3097 BUG();
3098 }
3099
3100 I915_WRITE(reg, temp);
3101 }
3102
3103 ironlake_enable_pch_transcoder(dev_priv, pipe);
3104 }
3105
3106 static void lpt_pch_enable(struct drm_crtc *crtc)
3107 {
3108 struct drm_device *dev = crtc->dev;
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3111 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3112
3113 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3114
3115 lpt_program_iclkip(crtc);
3116
3117 /* Set transcoder timing. */
3118 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3119 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3120 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3121
3122 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3123 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3124 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3125 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3126
3127 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3128 }
3129
3130 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3131 {
3132 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3133
3134 if (pll == NULL)
3135 return;
3136
3137 if (pll->refcount == 0) {
3138 WARN(1, "bad PCH PLL refcount\n");
3139 return;
3140 }
3141
3142 --pll->refcount;
3143 intel_crtc->pch_pll = NULL;
3144 }
3145
3146 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3147 {
3148 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3149 struct intel_pch_pll *pll;
3150 int i;
3151
3152 pll = intel_crtc->pch_pll;
3153 if (pll) {
3154 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3155 intel_crtc->base.base.id, pll->pll_reg);
3156 goto prepare;
3157 }
3158
3159 if (HAS_PCH_IBX(dev_priv->dev)) {
3160 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3161 i = intel_crtc->pipe;
3162 pll = &dev_priv->pch_plls[i];
3163
3164 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3165 intel_crtc->base.base.id, pll->pll_reg);
3166
3167 goto found;
3168 }
3169
3170 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3171 pll = &dev_priv->pch_plls[i];
3172
3173 /* Only want to check enabled timings first */
3174 if (pll->refcount == 0)
3175 continue;
3176
3177 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3178 fp == I915_READ(pll->fp0_reg)) {
3179 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3180 intel_crtc->base.base.id,
3181 pll->pll_reg, pll->refcount, pll->active);
3182
3183 goto found;
3184 }
3185 }
3186
3187 /* Ok no matching timings, maybe there's a free one? */
3188 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3189 pll = &dev_priv->pch_plls[i];
3190 if (pll->refcount == 0) {
3191 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3192 intel_crtc->base.base.id, pll->pll_reg);
3193 goto found;
3194 }
3195 }
3196
3197 return NULL;
3198
3199 found:
3200 intel_crtc->pch_pll = pll;
3201 pll->refcount++;
3202 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3203 prepare: /* separate function? */
3204 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3205
3206 /* Wait for the clocks to stabilize before rewriting the regs */
3207 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3208 POSTING_READ(pll->pll_reg);
3209 udelay(150);
3210
3211 I915_WRITE(pll->fp0_reg, fp);
3212 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3213 pll->on = false;
3214 return pll;
3215 }
3216
3217 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3218 {
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 int dslreg = PIPEDSL(pipe);
3221 u32 temp;
3222
3223 temp = I915_READ(dslreg);
3224 udelay(500);
3225 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3226 if (wait_for(I915_READ(dslreg) != temp, 5))
3227 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3228 }
3229 }
3230
3231 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3232 {
3233 struct drm_device *dev = crtc->dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3236 struct intel_encoder *encoder;
3237 int pipe = intel_crtc->pipe;
3238 int plane = intel_crtc->plane;
3239 u32 temp;
3240
3241 WARN_ON(!crtc->enabled);
3242
3243 if (intel_crtc->active)
3244 return;
3245
3246 intel_crtc->active = true;
3247
3248 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3249 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3250
3251 intel_update_watermarks(dev);
3252
3253 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3254 temp = I915_READ(PCH_LVDS);
3255 if ((temp & LVDS_PORT_EN) == 0)
3256 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3257 }
3258
3259
3260 if (intel_crtc->config.has_pch_encoder) {
3261 /* Note: FDI PLL enabling _must_ be done before we enable the
3262 * cpu pipes, hence this is separate from all the other fdi/pch
3263 * enabling. */
3264 ironlake_fdi_pll_enable(intel_crtc);
3265 } else {
3266 assert_fdi_tx_disabled(dev_priv, pipe);
3267 assert_fdi_rx_disabled(dev_priv, pipe);
3268 }
3269
3270 for_each_encoder_on_crtc(dev, crtc, encoder)
3271 if (encoder->pre_enable)
3272 encoder->pre_enable(encoder);
3273
3274 /* Enable panel fitting for LVDS */
3275 if (dev_priv->pch_pf_size &&
3276 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3277 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3278 /* Force use of hard-coded filter coefficients
3279 * as some pre-programmed values are broken,
3280 * e.g. x201.
3281 */
3282 if (IS_IVYBRIDGE(dev))
3283 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3284 PF_PIPE_SEL_IVB(pipe));
3285 else
3286 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3287 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3288 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3289 }
3290
3291 /*
3292 * On ILK+ LUT must be loaded before the pipe is running but with
3293 * clocks enabled
3294 */
3295 intel_crtc_load_lut(crtc);
3296
3297 intel_enable_pipe(dev_priv, pipe,
3298 intel_crtc->config.has_pch_encoder);
3299 intel_enable_plane(dev_priv, plane, pipe);
3300
3301 if (intel_crtc->config.has_pch_encoder)
3302 ironlake_pch_enable(crtc);
3303
3304 mutex_lock(&dev->struct_mutex);
3305 intel_update_fbc(dev);
3306 mutex_unlock(&dev->struct_mutex);
3307
3308 intel_crtc_update_cursor(crtc, true);
3309
3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 encoder->enable(encoder);
3312
3313 if (HAS_PCH_CPT(dev))
3314 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3315
3316 /*
3317 * There seems to be a race in PCH platform hw (at least on some
3318 * outputs) where an enabled pipe still completes any pageflip right
3319 * away (as if the pipe is off) instead of waiting for vblank. As soon
3320 * as the first vblank happend, everything works as expected. Hence just
3321 * wait for one vblank before returning to avoid strange things
3322 * happening.
3323 */
3324 intel_wait_for_vblank(dev, intel_crtc->pipe);
3325 }
3326
3327 static void haswell_crtc_enable(struct drm_crtc *crtc)
3328 {
3329 struct drm_device *dev = crtc->dev;
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332 struct intel_encoder *encoder;
3333 int pipe = intel_crtc->pipe;
3334 int plane = intel_crtc->plane;
3335
3336 WARN_ON(!crtc->enabled);
3337
3338 if (intel_crtc->active)
3339 return;
3340
3341 intel_crtc->active = true;
3342
3343 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3344 if (intel_crtc->config.has_pch_encoder)
3345 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3346
3347 intel_update_watermarks(dev);
3348
3349 if (intel_crtc->config.has_pch_encoder)
3350 dev_priv->display.fdi_link_train(crtc);
3351
3352 for_each_encoder_on_crtc(dev, crtc, encoder)
3353 if (encoder->pre_enable)
3354 encoder->pre_enable(encoder);
3355
3356 intel_ddi_enable_pipe_clock(intel_crtc);
3357
3358 /* Enable panel fitting for eDP */
3359 if (dev_priv->pch_pf_size &&
3360 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3361 /* Force use of hard-coded filter coefficients
3362 * as some pre-programmed values are broken,
3363 * e.g. x201.
3364 */
3365 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3366 PF_PIPE_SEL_IVB(pipe));
3367 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3368 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3369 }
3370
3371 /*
3372 * On ILK+ LUT must be loaded before the pipe is running but with
3373 * clocks enabled
3374 */
3375 intel_crtc_load_lut(crtc);
3376
3377 intel_ddi_set_pipe_settings(crtc);
3378 intel_ddi_enable_transcoder_func(crtc);
3379
3380 intel_enable_pipe(dev_priv, pipe,
3381 intel_crtc->config.has_pch_encoder);
3382 intel_enable_plane(dev_priv, plane, pipe);
3383
3384 if (intel_crtc->config.has_pch_encoder)
3385 lpt_pch_enable(crtc);
3386
3387 mutex_lock(&dev->struct_mutex);
3388 intel_update_fbc(dev);
3389 mutex_unlock(&dev->struct_mutex);
3390
3391 intel_crtc_update_cursor(crtc, true);
3392
3393 for_each_encoder_on_crtc(dev, crtc, encoder)
3394 encoder->enable(encoder);
3395
3396 /*
3397 * There seems to be a race in PCH platform hw (at least on some
3398 * outputs) where an enabled pipe still completes any pageflip right
3399 * away (as if the pipe is off) instead of waiting for vblank. As soon
3400 * as the first vblank happend, everything works as expected. Hence just
3401 * wait for one vblank before returning to avoid strange things
3402 * happening.
3403 */
3404 intel_wait_for_vblank(dev, intel_crtc->pipe);
3405 }
3406
3407 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3408 {
3409 struct drm_device *dev = crtc->dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3412 struct intel_encoder *encoder;
3413 int pipe = intel_crtc->pipe;
3414 int plane = intel_crtc->plane;
3415 u32 reg, temp;
3416
3417
3418 if (!intel_crtc->active)
3419 return;
3420
3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3422 encoder->disable(encoder);
3423
3424 intel_crtc_wait_for_pending_flips(crtc);
3425 drm_vblank_off(dev, pipe);
3426 intel_crtc_update_cursor(crtc, false);
3427
3428 intel_disable_plane(dev_priv, plane, pipe);
3429
3430 if (dev_priv->cfb_plane == plane)
3431 intel_disable_fbc(dev);
3432
3433 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3434 intel_disable_pipe(dev_priv, pipe);
3435
3436 /* Disable PF */
3437 I915_WRITE(PF_CTL(pipe), 0);
3438 I915_WRITE(PF_WIN_SZ(pipe), 0);
3439
3440 for_each_encoder_on_crtc(dev, crtc, encoder)
3441 if (encoder->post_disable)
3442 encoder->post_disable(encoder);
3443
3444 ironlake_fdi_disable(crtc);
3445
3446 ironlake_disable_pch_transcoder(dev_priv, pipe);
3447 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3448
3449 if (HAS_PCH_CPT(dev)) {
3450 /* disable TRANS_DP_CTL */
3451 reg = TRANS_DP_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3454 temp |= TRANS_DP_PORT_SEL_NONE;
3455 I915_WRITE(reg, temp);
3456
3457 /* disable DPLL_SEL */
3458 temp = I915_READ(PCH_DPLL_SEL);
3459 switch (pipe) {
3460 case 0:
3461 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3462 break;
3463 case 1:
3464 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3465 break;
3466 case 2:
3467 /* C shares PLL A or B */
3468 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3469 break;
3470 default:
3471 BUG(); /* wtf */
3472 }
3473 I915_WRITE(PCH_DPLL_SEL, temp);
3474 }
3475
3476 /* disable PCH DPLL */
3477 intel_disable_pch_pll(intel_crtc);
3478
3479 ironlake_fdi_pll_disable(intel_crtc);
3480
3481 intel_crtc->active = false;
3482 intel_update_watermarks(dev);
3483
3484 mutex_lock(&dev->struct_mutex);
3485 intel_update_fbc(dev);
3486 mutex_unlock(&dev->struct_mutex);
3487 }
3488
3489 static void haswell_crtc_disable(struct drm_crtc *crtc)
3490 {
3491 struct drm_device *dev = crtc->dev;
3492 struct drm_i915_private *dev_priv = dev->dev_private;
3493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3494 struct intel_encoder *encoder;
3495 int pipe = intel_crtc->pipe;
3496 int plane = intel_crtc->plane;
3497 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3498
3499 if (!intel_crtc->active)
3500 return;
3501
3502 for_each_encoder_on_crtc(dev, crtc, encoder)
3503 encoder->disable(encoder);
3504
3505 intel_crtc_wait_for_pending_flips(crtc);
3506 drm_vblank_off(dev, pipe);
3507 intel_crtc_update_cursor(crtc, false);
3508
3509 intel_disable_plane(dev_priv, plane, pipe);
3510
3511 if (dev_priv->cfb_plane == plane)
3512 intel_disable_fbc(dev);
3513
3514 if (intel_crtc->config.has_pch_encoder)
3515 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3516 intel_disable_pipe(dev_priv, pipe);
3517
3518 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3519
3520 /* XXX: Once we have proper panel fitter state tracking implemented with
3521 * hardware state read/check support we should switch to only disable
3522 * the panel fitter when we know it's used. */
3523 if (intel_using_power_well(dev)) {
3524 I915_WRITE(PF_CTL(pipe), 0);
3525 I915_WRITE(PF_WIN_SZ(pipe), 0);
3526 }
3527
3528 intel_ddi_disable_pipe_clock(intel_crtc);
3529
3530 for_each_encoder_on_crtc(dev, crtc, encoder)
3531 if (encoder->post_disable)
3532 encoder->post_disable(encoder);
3533
3534 if (intel_crtc->config.has_pch_encoder) {
3535 lpt_disable_pch_transcoder(dev_priv);
3536 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3537 intel_ddi_fdi_disable(crtc);
3538 }
3539
3540 intel_crtc->active = false;
3541 intel_update_watermarks(dev);
3542
3543 mutex_lock(&dev->struct_mutex);
3544 intel_update_fbc(dev);
3545 mutex_unlock(&dev->struct_mutex);
3546 }
3547
3548 static void ironlake_crtc_off(struct drm_crtc *crtc)
3549 {
3550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3551 intel_put_pch_pll(intel_crtc);
3552 }
3553
3554 static void haswell_crtc_off(struct drm_crtc *crtc)
3555 {
3556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557
3558 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3559 * start using it. */
3560 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3561
3562 intel_ddi_put_crtc_pll(crtc);
3563 }
3564
3565 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3566 {
3567 if (!enable && intel_crtc->overlay) {
3568 struct drm_device *dev = intel_crtc->base.dev;
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570
3571 mutex_lock(&dev->struct_mutex);
3572 dev_priv->mm.interruptible = false;
3573 (void) intel_overlay_switch_off(intel_crtc->overlay);
3574 dev_priv->mm.interruptible = true;
3575 mutex_unlock(&dev->struct_mutex);
3576 }
3577
3578 /* Let userspace switch the overlay on again. In most cases userspace
3579 * has to recompute where to put it anyway.
3580 */
3581 }
3582
3583 /**
3584 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3585 * cursor plane briefly if not already running after enabling the display
3586 * plane.
3587 * This workaround avoids occasional blank screens when self refresh is
3588 * enabled.
3589 */
3590 static void
3591 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3592 {
3593 u32 cntl = I915_READ(CURCNTR(pipe));
3594
3595 if ((cntl & CURSOR_MODE) == 0) {
3596 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3597
3598 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3599 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3600 intel_wait_for_vblank(dev_priv->dev, pipe);
3601 I915_WRITE(CURCNTR(pipe), cntl);
3602 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3603 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3604 }
3605 }
3606
3607 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3608 {
3609 struct drm_device *dev = crtc->dev;
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612 struct intel_encoder *encoder;
3613 int pipe = intel_crtc->pipe;
3614 int plane = intel_crtc->plane;
3615
3616 WARN_ON(!crtc->enabled);
3617
3618 if (intel_crtc->active)
3619 return;
3620
3621 intel_crtc->active = true;
3622 intel_update_watermarks(dev);
3623
3624 mutex_lock(&dev_priv->dpio_lock);
3625
3626 for_each_encoder_on_crtc(dev, crtc, encoder)
3627 if (encoder->pre_pll_enable)
3628 encoder->pre_pll_enable(encoder);
3629
3630 intel_enable_pll(dev_priv, pipe);
3631
3632 for_each_encoder_on_crtc(dev, crtc, encoder)
3633 if (encoder->pre_enable)
3634 encoder->pre_enable(encoder);
3635
3636 /* VLV wants encoder enabling _before_ the pipe is up. */
3637 for_each_encoder_on_crtc(dev, crtc, encoder)
3638 encoder->enable(encoder);
3639
3640 intel_enable_pipe(dev_priv, pipe, false);
3641 intel_enable_plane(dev_priv, plane, pipe);
3642
3643 intel_crtc_load_lut(crtc);
3644 intel_update_fbc(dev);
3645
3646 /* Give the overlay scaler a chance to enable if it's on this pipe */
3647 intel_crtc_dpms_overlay(intel_crtc, true);
3648 intel_crtc_update_cursor(crtc, true);
3649
3650 mutex_unlock(&dev_priv->dpio_lock);
3651 }
3652
3653 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3654 {
3655 struct drm_device *dev = crtc->dev;
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658 struct intel_encoder *encoder;
3659 int pipe = intel_crtc->pipe;
3660 int plane = intel_crtc->plane;
3661
3662 WARN_ON(!crtc->enabled);
3663
3664 if (intel_crtc->active)
3665 return;
3666
3667 intel_crtc->active = true;
3668 intel_update_watermarks(dev);
3669
3670 intel_enable_pll(dev_priv, pipe);
3671
3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 if (encoder->pre_enable)
3674 encoder->pre_enable(encoder);
3675
3676 intel_enable_pipe(dev_priv, pipe, false);
3677 intel_enable_plane(dev_priv, plane, pipe);
3678 if (IS_G4X(dev))
3679 g4x_fixup_plane(dev_priv, pipe);
3680
3681 intel_crtc_load_lut(crtc);
3682 intel_update_fbc(dev);
3683
3684 /* Give the overlay scaler a chance to enable if it's on this pipe */
3685 intel_crtc_dpms_overlay(intel_crtc, true);
3686 intel_crtc_update_cursor(crtc, true);
3687
3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 encoder->enable(encoder);
3690 }
3691
3692 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3693 {
3694 struct drm_device *dev = crtc->base.dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 enum pipe pipe;
3697 uint32_t pctl = I915_READ(PFIT_CONTROL);
3698
3699 assert_pipe_disabled(dev_priv, crtc->pipe);
3700
3701 if (INTEL_INFO(dev)->gen >= 4)
3702 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3703 else
3704 pipe = PIPE_B;
3705
3706 if (pipe == crtc->pipe) {
3707 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3708 I915_WRITE(PFIT_CONTROL, 0);
3709 }
3710 }
3711
3712 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3713 {
3714 struct drm_device *dev = crtc->dev;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717 struct intel_encoder *encoder;
3718 int pipe = intel_crtc->pipe;
3719 int plane = intel_crtc->plane;
3720
3721 if (!intel_crtc->active)
3722 return;
3723
3724 for_each_encoder_on_crtc(dev, crtc, encoder)
3725 encoder->disable(encoder);
3726
3727 /* Give the overlay scaler a chance to disable if it's on this pipe */
3728 intel_crtc_wait_for_pending_flips(crtc);
3729 drm_vblank_off(dev, pipe);
3730 intel_crtc_dpms_overlay(intel_crtc, false);
3731 intel_crtc_update_cursor(crtc, false);
3732
3733 if (dev_priv->cfb_plane == plane)
3734 intel_disable_fbc(dev);
3735
3736 intel_disable_plane(dev_priv, plane, pipe);
3737 intel_disable_pipe(dev_priv, pipe);
3738
3739 i9xx_pfit_disable(intel_crtc);
3740
3741 for_each_encoder_on_crtc(dev, crtc, encoder)
3742 if (encoder->post_disable)
3743 encoder->post_disable(encoder);
3744
3745 intel_disable_pll(dev_priv, pipe);
3746
3747 intel_crtc->active = false;
3748 intel_update_fbc(dev);
3749 intel_update_watermarks(dev);
3750 }
3751
3752 static void i9xx_crtc_off(struct drm_crtc *crtc)
3753 {
3754 }
3755
3756 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3757 bool enabled)
3758 {
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_master_private *master_priv;
3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762 int pipe = intel_crtc->pipe;
3763
3764 if (!dev->primary->master)
3765 return;
3766
3767 master_priv = dev->primary->master->driver_priv;
3768 if (!master_priv->sarea_priv)
3769 return;
3770
3771 switch (pipe) {
3772 case 0:
3773 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3774 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3775 break;
3776 case 1:
3777 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3778 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3779 break;
3780 default:
3781 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3782 break;
3783 }
3784 }
3785
3786 /**
3787 * Sets the power management mode of the pipe and plane.
3788 */
3789 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3790 {
3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 struct intel_encoder *intel_encoder;
3794 bool enable = false;
3795
3796 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3797 enable |= intel_encoder->connectors_active;
3798
3799 if (enable)
3800 dev_priv->display.crtc_enable(crtc);
3801 else
3802 dev_priv->display.crtc_disable(crtc);
3803
3804 intel_crtc_update_sarea(crtc, enable);
3805 }
3806
3807 static void intel_crtc_disable(struct drm_crtc *crtc)
3808 {
3809 struct drm_device *dev = crtc->dev;
3810 struct drm_connector *connector;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813
3814 /* crtc should still be enabled when we disable it. */
3815 WARN_ON(!crtc->enabled);
3816
3817 intel_crtc->eld_vld = false;
3818 dev_priv->display.crtc_disable(crtc);
3819 intel_crtc_update_sarea(crtc, false);
3820 dev_priv->display.off(crtc);
3821
3822 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3823 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3824
3825 if (crtc->fb) {
3826 mutex_lock(&dev->struct_mutex);
3827 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3828 mutex_unlock(&dev->struct_mutex);
3829 crtc->fb = NULL;
3830 }
3831
3832 /* Update computed state. */
3833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3834 if (!connector->encoder || !connector->encoder->crtc)
3835 continue;
3836
3837 if (connector->encoder->crtc != crtc)
3838 continue;
3839
3840 connector->dpms = DRM_MODE_DPMS_OFF;
3841 to_intel_encoder(connector->encoder)->connectors_active = false;
3842 }
3843 }
3844
3845 void intel_modeset_disable(struct drm_device *dev)
3846 {
3847 struct drm_crtc *crtc;
3848
3849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3850 if (crtc->enabled)
3851 intel_crtc_disable(crtc);
3852 }
3853 }
3854
3855 void intel_encoder_destroy(struct drm_encoder *encoder)
3856 {
3857 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3858
3859 drm_encoder_cleanup(encoder);
3860 kfree(intel_encoder);
3861 }
3862
3863 /* Simple dpms helper for encodres with just one connector, no cloning and only
3864 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3865 * state of the entire output pipe. */
3866 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3867 {
3868 if (mode == DRM_MODE_DPMS_ON) {
3869 encoder->connectors_active = true;
3870
3871 intel_crtc_update_dpms(encoder->base.crtc);
3872 } else {
3873 encoder->connectors_active = false;
3874
3875 intel_crtc_update_dpms(encoder->base.crtc);
3876 }
3877 }
3878
3879 /* Cross check the actual hw state with our own modeset state tracking (and it's
3880 * internal consistency). */
3881 static void intel_connector_check_state(struct intel_connector *connector)
3882 {
3883 if (connector->get_hw_state(connector)) {
3884 struct intel_encoder *encoder = connector->encoder;
3885 struct drm_crtc *crtc;
3886 bool encoder_enabled;
3887 enum pipe pipe;
3888
3889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3890 connector->base.base.id,
3891 drm_get_connector_name(&connector->base));
3892
3893 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3894 "wrong connector dpms state\n");
3895 WARN(connector->base.encoder != &encoder->base,
3896 "active connector not linked to encoder\n");
3897 WARN(!encoder->connectors_active,
3898 "encoder->connectors_active not set\n");
3899
3900 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3901 WARN(!encoder_enabled, "encoder not enabled\n");
3902 if (WARN_ON(!encoder->base.crtc))
3903 return;
3904
3905 crtc = encoder->base.crtc;
3906
3907 WARN(!crtc->enabled, "crtc not enabled\n");
3908 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3909 WARN(pipe != to_intel_crtc(crtc)->pipe,
3910 "encoder active on the wrong pipe\n");
3911 }
3912 }
3913
3914 /* Even simpler default implementation, if there's really no special case to
3915 * consider. */
3916 void intel_connector_dpms(struct drm_connector *connector, int mode)
3917 {
3918 struct intel_encoder *encoder = intel_attached_encoder(connector);
3919
3920 /* All the simple cases only support two dpms states. */
3921 if (mode != DRM_MODE_DPMS_ON)
3922 mode = DRM_MODE_DPMS_OFF;
3923
3924 if (mode == connector->dpms)
3925 return;
3926
3927 connector->dpms = mode;
3928
3929 /* Only need to change hw state when actually enabled */
3930 if (encoder->base.crtc)
3931 intel_encoder_dpms(encoder, mode);
3932 else
3933 WARN_ON(encoder->connectors_active != false);
3934
3935 intel_modeset_check_state(connector->dev);
3936 }
3937
3938 /* Simple connector->get_hw_state implementation for encoders that support only
3939 * one connector and no cloning and hence the encoder state determines the state
3940 * of the connector. */
3941 bool intel_connector_get_hw_state(struct intel_connector *connector)
3942 {
3943 enum pipe pipe = 0;
3944 struct intel_encoder *encoder = connector->encoder;
3945
3946 return encoder->get_hw_state(encoder, &pipe);
3947 }
3948
3949 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3950 struct intel_crtc_config *pipe_config)
3951 {
3952 struct drm_device *dev = crtc->dev;
3953 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3954
3955 if (HAS_PCH_SPLIT(dev)) {
3956 /* FDI link clock is fixed at 2.7G */
3957 if (pipe_config->requested_mode.clock * 3
3958 > IRONLAKE_FDI_FREQ * 4)
3959 return false;
3960 }
3961
3962 /* All interlaced capable intel hw wants timings in frames. Note though
3963 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3964 * timings, so we need to be careful not to clobber these.*/
3965 if (!pipe_config->timings_set)
3966 drm_mode_set_crtcinfo(adjusted_mode, 0);
3967
3968 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3969 * with a hsync front porch of 0.
3970 */
3971 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3972 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3973 return false;
3974
3975 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
3976 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3977 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
3978 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3979 * for lvds. */
3980 pipe_config->pipe_bpp = 8*3;
3981 }
3982
3983 return true;
3984 }
3985
3986 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3987 {
3988 return 400000; /* FIXME */
3989 }
3990
3991 static int i945_get_display_clock_speed(struct drm_device *dev)
3992 {
3993 return 400000;
3994 }
3995
3996 static int i915_get_display_clock_speed(struct drm_device *dev)
3997 {
3998 return 333000;
3999 }
4000
4001 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4002 {
4003 return 200000;
4004 }
4005
4006 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4007 {
4008 u16 gcfgc = 0;
4009
4010 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4011
4012 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4013 return 133000;
4014 else {
4015 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4016 case GC_DISPLAY_CLOCK_333_MHZ:
4017 return 333000;
4018 default:
4019 case GC_DISPLAY_CLOCK_190_200_MHZ:
4020 return 190000;
4021 }
4022 }
4023 }
4024
4025 static int i865_get_display_clock_speed(struct drm_device *dev)
4026 {
4027 return 266000;
4028 }
4029
4030 static int i855_get_display_clock_speed(struct drm_device *dev)
4031 {
4032 u16 hpllcc = 0;
4033 /* Assume that the hardware is in the high speed state. This
4034 * should be the default.
4035 */
4036 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4037 case GC_CLOCK_133_200:
4038 case GC_CLOCK_100_200:
4039 return 200000;
4040 case GC_CLOCK_166_250:
4041 return 250000;
4042 case GC_CLOCK_100_133:
4043 return 133000;
4044 }
4045
4046 /* Shouldn't happen */
4047 return 0;
4048 }
4049
4050 static int i830_get_display_clock_speed(struct drm_device *dev)
4051 {
4052 return 133000;
4053 }
4054
4055 static void
4056 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4057 {
4058 while (*num > 0xffffff || *den > 0xffffff) {
4059 *num >>= 1;
4060 *den >>= 1;
4061 }
4062 }
4063
4064 void
4065 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4066 int pixel_clock, int link_clock,
4067 struct intel_link_m_n *m_n)
4068 {
4069 m_n->tu = 64;
4070 m_n->gmch_m = bits_per_pixel * pixel_clock;
4071 m_n->gmch_n = link_clock * nlanes * 8;
4072 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4073 m_n->link_m = pixel_clock;
4074 m_n->link_n = link_clock;
4075 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4076 }
4077
4078 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4079 {
4080 if (i915_panel_use_ssc >= 0)
4081 return i915_panel_use_ssc != 0;
4082 return dev_priv->lvds_use_ssc
4083 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4084 }
4085
4086 static int vlv_get_refclk(struct drm_crtc *crtc)
4087 {
4088 struct drm_device *dev = crtc->dev;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 int refclk = 27000; /* for DP & HDMI */
4091
4092 return 100000; /* only one validated so far */
4093
4094 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4095 refclk = 96000;
4096 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4097 if (intel_panel_use_ssc(dev_priv))
4098 refclk = 100000;
4099 else
4100 refclk = 96000;
4101 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4102 refclk = 100000;
4103 }
4104
4105 return refclk;
4106 }
4107
4108 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4109 {
4110 struct drm_device *dev = crtc->dev;
4111 struct drm_i915_private *dev_priv = dev->dev_private;
4112 int refclk;
4113
4114 if (IS_VALLEYVIEW(dev)) {
4115 refclk = vlv_get_refclk(crtc);
4116 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4117 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4118 refclk = dev_priv->lvds_ssc_freq * 1000;
4119 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4120 refclk / 1000);
4121 } else if (!IS_GEN2(dev)) {
4122 refclk = 96000;
4123 } else {
4124 refclk = 48000;
4125 }
4126
4127 return refclk;
4128 }
4129
4130 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4131 {
4132 unsigned dotclock = crtc->config.adjusted_mode.clock;
4133 struct dpll *clock = &crtc->config.dpll;
4134
4135 /* SDVO TV has fixed PLL values depend on its clock range,
4136 this mirrors vbios setting. */
4137 if (dotclock >= 100000 && dotclock < 140500) {
4138 clock->p1 = 2;
4139 clock->p2 = 10;
4140 clock->n = 3;
4141 clock->m1 = 16;
4142 clock->m2 = 8;
4143 } else if (dotclock >= 140500 && dotclock <= 200000) {
4144 clock->p1 = 1;
4145 clock->p2 = 10;
4146 clock->n = 6;
4147 clock->m1 = 12;
4148 clock->m2 = 8;
4149 }
4150
4151 crtc->config.clock_set = true;
4152 }
4153
4154 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4155 {
4156 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4157 }
4158
4159 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4160 {
4161 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4162 }
4163
4164 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4165 intel_clock_t *reduced_clock)
4166 {
4167 struct drm_device *dev = crtc->base.dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 int pipe = crtc->pipe;
4170 u32 fp, fp2 = 0;
4171
4172 if (IS_PINEVIEW(dev)) {
4173 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4174 if (reduced_clock)
4175 fp2 = pnv_dpll_compute_fp(reduced_clock);
4176 } else {
4177 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4178 if (reduced_clock)
4179 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4180 }
4181
4182 I915_WRITE(FP0(pipe), fp);
4183
4184 crtc->lowfreq_avail = false;
4185 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4186 reduced_clock && i915_powersave) {
4187 I915_WRITE(FP1(pipe), fp2);
4188 crtc->lowfreq_avail = true;
4189 } else {
4190 I915_WRITE(FP1(pipe), fp);
4191 }
4192 }
4193
4194 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4195 {
4196 u32 reg_val;
4197
4198 /*
4199 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4200 * and set it to a reasonable value instead.
4201 */
4202 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4203 reg_val &= 0xffffff00;
4204 reg_val |= 0x00000030;
4205 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4206
4207 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4208 reg_val &= 0x8cffffff;
4209 reg_val = 0x8c000000;
4210 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4211
4212 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4213 reg_val &= 0xffffff00;
4214 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4215
4216 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4217 reg_val &= 0x00ffffff;
4218 reg_val |= 0xb0000000;
4219 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4220 }
4221
4222 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4223 {
4224 if (crtc->config.has_pch_encoder)
4225 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4226 else
4227 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4228 }
4229
4230 static void vlv_update_pll(struct intel_crtc *crtc)
4231 {
4232 struct drm_device *dev = crtc->base.dev;
4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234 struct drm_display_mode *adjusted_mode =
4235 &crtc->config.adjusted_mode;
4236 struct intel_encoder *encoder;
4237 int pipe = crtc->pipe;
4238 u32 dpll, mdiv;
4239 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4240 bool is_hdmi;
4241 u32 coreclk, reg_val, temp;
4242
4243 mutex_lock(&dev_priv->dpio_lock);
4244
4245 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4246
4247 bestn = crtc->config.dpll.n;
4248 bestm1 = crtc->config.dpll.m1;
4249 bestm2 = crtc->config.dpll.m2;
4250 bestp1 = crtc->config.dpll.p1;
4251 bestp2 = crtc->config.dpll.p2;
4252
4253 /* See eDP HDMI DPIO driver vbios notes doc */
4254
4255 /* PLL B needs special handling */
4256 if (pipe)
4257 vlv_pllb_recal_opamp(dev_priv);
4258
4259 /* Set up Tx target for periodic Rcomp update */
4260 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4261
4262 /* Disable target IRef on PLL */
4263 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4264 reg_val &= 0x00ffffff;
4265 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4266
4267 /* Disable fast lock */
4268 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4269
4270 /* Set idtafcrecal before PLL is enabled */
4271 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4272 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4273 mdiv |= ((bestn << DPIO_N_SHIFT));
4274 mdiv |= (1 << DPIO_K_SHIFT);
4275 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4276 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4277 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4278 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4279 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4280
4281 mdiv |= DPIO_ENABLE_CALIBRATION;
4282 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4283
4284 /* Set HBR and RBR LPF coefficients */
4285 if (adjusted_mode->clock == 162000 ||
4286 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4287 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4288 0x005f0021);
4289 else
4290 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4291 0x00d0000f);
4292
4293 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4294 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4295 /* Use SSC source */
4296 if (!pipe)
4297 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4298 0x0df40000);
4299 else
4300 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4301 0x0df70000);
4302 } else { /* HDMI or VGA */
4303 /* Use bend source */
4304 if (!pipe)
4305 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4306 0x0df70000);
4307 else
4308 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4309 0x0df40000);
4310 }
4311
4312 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4313 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4314 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4315 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4316 coreclk |= 0x01000000;
4317 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4318
4319 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4320
4321 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4322 if (encoder->pre_pll_enable)
4323 encoder->pre_pll_enable(encoder);
4324
4325 /* Enable DPIO clock input */
4326 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4327 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4328 if (pipe)
4329 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4330
4331 dpll |= DPLL_VCO_ENABLE;
4332 I915_WRITE(DPLL(pipe), dpll);
4333 POSTING_READ(DPLL(pipe));
4334 udelay(150);
4335
4336 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4337 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4338
4339 if (is_hdmi) {
4340 temp = 0;
4341 if (crtc->config.pixel_multiplier > 1) {
4342 temp = (crtc->config.pixel_multiplier - 1)
4343 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4344 }
4345
4346 I915_WRITE(DPLL_MD(pipe), temp);
4347 POSTING_READ(DPLL_MD(pipe));
4348 }
4349
4350 if (crtc->config.has_dp_encoder)
4351 intel_dp_set_m_n(crtc);
4352
4353 mutex_unlock(&dev_priv->dpio_lock);
4354 }
4355
4356 static void i9xx_update_pll(struct intel_crtc *crtc,
4357 intel_clock_t *reduced_clock,
4358 int num_connectors)
4359 {
4360 struct drm_device *dev = crtc->base.dev;
4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362 struct intel_encoder *encoder;
4363 int pipe = crtc->pipe;
4364 u32 dpll;
4365 bool is_sdvo;
4366 struct dpll *clock = &crtc->config.dpll;
4367
4368 i9xx_update_pll_dividers(crtc, reduced_clock);
4369
4370 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4371 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4372
4373 dpll = DPLL_VGA_MODE_DIS;
4374
4375 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4376 dpll |= DPLLB_MODE_LVDS;
4377 else
4378 dpll |= DPLLB_MODE_DAC_SERIAL;
4379
4380 if (is_sdvo) {
4381 if ((crtc->config.pixel_multiplier > 1) &&
4382 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4383 dpll |= (crtc->config.pixel_multiplier - 1)
4384 << SDVO_MULTIPLIER_SHIFT_HIRES;
4385 }
4386 dpll |= DPLL_DVO_HIGH_SPEED;
4387 }
4388 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4389 dpll |= DPLL_DVO_HIGH_SPEED;
4390
4391 /* compute bitmask from p1 value */
4392 if (IS_PINEVIEW(dev))
4393 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4394 else {
4395 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4396 if (IS_G4X(dev) && reduced_clock)
4397 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4398 }
4399 switch (clock->p2) {
4400 case 5:
4401 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4402 break;
4403 case 7:
4404 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4405 break;
4406 case 10:
4407 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4408 break;
4409 case 14:
4410 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4411 break;
4412 }
4413 if (INTEL_INFO(dev)->gen >= 4)
4414 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4415
4416 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4417 dpll |= PLL_REF_INPUT_TVCLKINBC;
4418 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4419 /* XXX: just matching BIOS for now */
4420 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4421 dpll |= 3;
4422 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4423 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4424 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4425 else
4426 dpll |= PLL_REF_INPUT_DREFCLK;
4427
4428 dpll |= DPLL_VCO_ENABLE;
4429 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4430 POSTING_READ(DPLL(pipe));
4431 udelay(150);
4432
4433 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4434 if (encoder->pre_pll_enable)
4435 encoder->pre_pll_enable(encoder);
4436
4437 if (crtc->config.has_dp_encoder)
4438 intel_dp_set_m_n(crtc);
4439
4440 I915_WRITE(DPLL(pipe), dpll);
4441
4442 /* Wait for the clocks to stabilize. */
4443 POSTING_READ(DPLL(pipe));
4444 udelay(150);
4445
4446 if (INTEL_INFO(dev)->gen >= 4) {
4447 u32 temp = 0;
4448 if (is_sdvo) {
4449 temp = 0;
4450 if (crtc->config.pixel_multiplier > 1) {
4451 temp = (crtc->config.pixel_multiplier - 1)
4452 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4453 }
4454 }
4455 I915_WRITE(DPLL_MD(pipe), temp);
4456 } else {
4457 /* The pixel multiplier can only be updated once the
4458 * DPLL is enabled and the clocks are stable.
4459 *
4460 * So write it again.
4461 */
4462 I915_WRITE(DPLL(pipe), dpll);
4463 }
4464 }
4465
4466 static void i8xx_update_pll(struct intel_crtc *crtc,
4467 struct drm_display_mode *adjusted_mode,
4468 intel_clock_t *reduced_clock,
4469 int num_connectors)
4470 {
4471 struct drm_device *dev = crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 struct intel_encoder *encoder;
4474 int pipe = crtc->pipe;
4475 u32 dpll;
4476 struct dpll *clock = &crtc->config.dpll;
4477
4478 i9xx_update_pll_dividers(crtc, reduced_clock);
4479
4480 dpll = DPLL_VGA_MODE_DIS;
4481
4482 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4483 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4484 } else {
4485 if (clock->p1 == 2)
4486 dpll |= PLL_P1_DIVIDE_BY_TWO;
4487 else
4488 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4489 if (clock->p2 == 4)
4490 dpll |= PLL_P2_DIVIDE_BY_4;
4491 }
4492
4493 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4494 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4495 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4496 else
4497 dpll |= PLL_REF_INPUT_DREFCLK;
4498
4499 dpll |= DPLL_VCO_ENABLE;
4500 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4501 POSTING_READ(DPLL(pipe));
4502 udelay(150);
4503
4504 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4505 if (encoder->pre_pll_enable)
4506 encoder->pre_pll_enable(encoder);
4507
4508 I915_WRITE(DPLL(pipe), dpll);
4509
4510 /* Wait for the clocks to stabilize. */
4511 POSTING_READ(DPLL(pipe));
4512 udelay(150);
4513
4514 /* The pixel multiplier can only be updated once the
4515 * DPLL is enabled and the clocks are stable.
4516 *
4517 * So write it again.
4518 */
4519 I915_WRITE(DPLL(pipe), dpll);
4520 }
4521
4522 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4523 struct drm_display_mode *mode,
4524 struct drm_display_mode *adjusted_mode)
4525 {
4526 struct drm_device *dev = intel_crtc->base.dev;
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528 enum pipe pipe = intel_crtc->pipe;
4529 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4530 uint32_t vsyncshift;
4531
4532 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4533 /* the chip adds 2 halflines automatically */
4534 adjusted_mode->crtc_vtotal -= 1;
4535 adjusted_mode->crtc_vblank_end -= 1;
4536 vsyncshift = adjusted_mode->crtc_hsync_start
4537 - adjusted_mode->crtc_htotal / 2;
4538 } else {
4539 vsyncshift = 0;
4540 }
4541
4542 if (INTEL_INFO(dev)->gen > 3)
4543 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4544
4545 I915_WRITE(HTOTAL(cpu_transcoder),
4546 (adjusted_mode->crtc_hdisplay - 1) |
4547 ((adjusted_mode->crtc_htotal - 1) << 16));
4548 I915_WRITE(HBLANK(cpu_transcoder),
4549 (adjusted_mode->crtc_hblank_start - 1) |
4550 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4551 I915_WRITE(HSYNC(cpu_transcoder),
4552 (adjusted_mode->crtc_hsync_start - 1) |
4553 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4554
4555 I915_WRITE(VTOTAL(cpu_transcoder),
4556 (adjusted_mode->crtc_vdisplay - 1) |
4557 ((adjusted_mode->crtc_vtotal - 1) << 16));
4558 I915_WRITE(VBLANK(cpu_transcoder),
4559 (adjusted_mode->crtc_vblank_start - 1) |
4560 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4561 I915_WRITE(VSYNC(cpu_transcoder),
4562 (adjusted_mode->crtc_vsync_start - 1) |
4563 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4564
4565 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4566 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4567 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4568 * bits. */
4569 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4570 (pipe == PIPE_B || pipe == PIPE_C))
4571 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4572
4573 /* pipesrc controls the size that is scaled from, which should
4574 * always be the user's requested size.
4575 */
4576 I915_WRITE(PIPESRC(pipe),
4577 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4578 }
4579
4580 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4581 {
4582 struct drm_device *dev = intel_crtc->base.dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 uint32_t pipeconf;
4585
4586 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4587
4588 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4589 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4590 * core speed.
4591 *
4592 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4593 * pipe == 0 check?
4594 */
4595 if (intel_crtc->config.requested_mode.clock >
4596 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4597 pipeconf |= PIPECONF_DOUBLE_WIDE;
4598 else
4599 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4600 }
4601
4602 /* default to 8bpc */
4603 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4604 if (intel_crtc->config.has_dp_encoder) {
4605 if (intel_crtc->config.dither) {
4606 pipeconf |= PIPECONF_6BPC |
4607 PIPECONF_DITHER_EN |
4608 PIPECONF_DITHER_TYPE_SP;
4609 }
4610 }
4611
4612 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4613 INTEL_OUTPUT_EDP)) {
4614 if (intel_crtc->config.dither) {
4615 pipeconf |= PIPECONF_6BPC |
4616 PIPECONF_ENABLE |
4617 I965_PIPECONF_ACTIVE;
4618 }
4619 }
4620
4621 if (HAS_PIPE_CXSR(dev)) {
4622 if (intel_crtc->lowfreq_avail) {
4623 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4624 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4625 } else {
4626 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4627 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4628 }
4629 }
4630
4631 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4632 if (!IS_GEN2(dev) &&
4633 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4634 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4635 else
4636 pipeconf |= PIPECONF_PROGRESSIVE;
4637
4638 if (IS_VALLEYVIEW(dev)) {
4639 if (intel_crtc->config.limited_color_range)
4640 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4641 else
4642 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4643 }
4644
4645 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4646 POSTING_READ(PIPECONF(intel_crtc->pipe));
4647 }
4648
4649 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4650 int x, int y,
4651 struct drm_framebuffer *fb)
4652 {
4653 struct drm_device *dev = crtc->dev;
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4656 struct drm_display_mode *adjusted_mode =
4657 &intel_crtc->config.adjusted_mode;
4658 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4659 int pipe = intel_crtc->pipe;
4660 int plane = intel_crtc->plane;
4661 int refclk, num_connectors = 0;
4662 intel_clock_t clock, reduced_clock;
4663 u32 dspcntr;
4664 bool ok, has_reduced_clock = false, is_sdvo = false;
4665 bool is_lvds = false, is_tv = false;
4666 struct intel_encoder *encoder;
4667 const intel_limit_t *limit;
4668 int ret;
4669
4670 for_each_encoder_on_crtc(dev, crtc, encoder) {
4671 switch (encoder->type) {
4672 case INTEL_OUTPUT_LVDS:
4673 is_lvds = true;
4674 break;
4675 case INTEL_OUTPUT_SDVO:
4676 case INTEL_OUTPUT_HDMI:
4677 is_sdvo = true;
4678 if (encoder->needs_tv_clock)
4679 is_tv = true;
4680 break;
4681 case INTEL_OUTPUT_TVOUT:
4682 is_tv = true;
4683 break;
4684 }
4685
4686 num_connectors++;
4687 }
4688
4689 refclk = i9xx_get_refclk(crtc, num_connectors);
4690
4691 /*
4692 * Returns a set of divisors for the desired target clock with the given
4693 * refclk, or FALSE. The returned values represent the clock equation:
4694 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4695 */
4696 limit = intel_limit(crtc, refclk);
4697 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4698 &clock);
4699 if (!ok) {
4700 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4701 return -EINVAL;
4702 }
4703
4704 /* Ensure that the cursor is valid for the new mode before changing... */
4705 intel_crtc_update_cursor(crtc, true);
4706
4707 if (is_lvds && dev_priv->lvds_downclock_avail) {
4708 /*
4709 * Ensure we match the reduced clock's P to the target clock.
4710 * If the clocks don't match, we can't switch the display clock
4711 * by using the FP0/FP1. In such case we will disable the LVDS
4712 * downclock feature.
4713 */
4714 has_reduced_clock = limit->find_pll(limit, crtc,
4715 dev_priv->lvds_downclock,
4716 refclk,
4717 &clock,
4718 &reduced_clock);
4719 }
4720 /* Compat-code for transition, will disappear. */
4721 if (!intel_crtc->config.clock_set) {
4722 intel_crtc->config.dpll.n = clock.n;
4723 intel_crtc->config.dpll.m1 = clock.m1;
4724 intel_crtc->config.dpll.m2 = clock.m2;
4725 intel_crtc->config.dpll.p1 = clock.p1;
4726 intel_crtc->config.dpll.p2 = clock.p2;
4727 }
4728
4729 if (is_sdvo && is_tv)
4730 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4731
4732 if (IS_GEN2(dev))
4733 i8xx_update_pll(intel_crtc, adjusted_mode,
4734 has_reduced_clock ? &reduced_clock : NULL,
4735 num_connectors);
4736 else if (IS_VALLEYVIEW(dev))
4737 vlv_update_pll(intel_crtc);
4738 else
4739 i9xx_update_pll(intel_crtc,
4740 has_reduced_clock ? &reduced_clock : NULL,
4741 num_connectors);
4742
4743 /* Set up the display plane register */
4744 dspcntr = DISPPLANE_GAMMA_ENABLE;
4745
4746 if (!IS_VALLEYVIEW(dev)) {
4747 if (pipe == 0)
4748 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4749 else
4750 dspcntr |= DISPPLANE_SEL_PIPE_B;
4751 }
4752
4753 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4754 drm_mode_debug_printmodeline(mode);
4755
4756 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4757
4758 /* pipesrc and dspsize control the size that is scaled from,
4759 * which should always be the user's requested size.
4760 */
4761 I915_WRITE(DSPSIZE(plane),
4762 ((mode->vdisplay - 1) << 16) |
4763 (mode->hdisplay - 1));
4764 I915_WRITE(DSPPOS(plane), 0);
4765
4766 i9xx_set_pipeconf(intel_crtc);
4767
4768 I915_WRITE(DSPCNTR(plane), dspcntr);
4769 POSTING_READ(DSPCNTR(plane));
4770
4771 ret = intel_pipe_set_base(crtc, x, y, fb);
4772
4773 intel_update_watermarks(dev);
4774
4775 return ret;
4776 }
4777
4778 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4779 struct intel_crtc_config *pipe_config)
4780 {
4781 struct drm_device *dev = crtc->base.dev;
4782 struct drm_i915_private *dev_priv = dev->dev_private;
4783 uint32_t tmp;
4784
4785 tmp = I915_READ(PIPECONF(crtc->pipe));
4786 if (!(tmp & PIPECONF_ENABLE))
4787 return false;
4788
4789 return true;
4790 }
4791
4792 static void ironlake_init_pch_refclk(struct drm_device *dev)
4793 {
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 struct drm_mode_config *mode_config = &dev->mode_config;
4796 struct intel_encoder *encoder;
4797 u32 val, final;
4798 bool has_lvds = false;
4799 bool has_cpu_edp = false;
4800 bool has_pch_edp = false;
4801 bool has_panel = false;
4802 bool has_ck505 = false;
4803 bool can_ssc = false;
4804
4805 /* We need to take the global config into account */
4806 list_for_each_entry(encoder, &mode_config->encoder_list,
4807 base.head) {
4808 switch (encoder->type) {
4809 case INTEL_OUTPUT_LVDS:
4810 has_panel = true;
4811 has_lvds = true;
4812 break;
4813 case INTEL_OUTPUT_EDP:
4814 has_panel = true;
4815 if (intel_encoder_is_pch_edp(&encoder->base))
4816 has_pch_edp = true;
4817 else
4818 has_cpu_edp = true;
4819 break;
4820 }
4821 }
4822
4823 if (HAS_PCH_IBX(dev)) {
4824 has_ck505 = dev_priv->display_clock_mode;
4825 can_ssc = has_ck505;
4826 } else {
4827 has_ck505 = false;
4828 can_ssc = true;
4829 }
4830
4831 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4832 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4833 has_ck505);
4834
4835 /* Ironlake: try to setup display ref clock before DPLL
4836 * enabling. This is only under driver's control after
4837 * PCH B stepping, previous chipset stepping should be
4838 * ignoring this setting.
4839 */
4840 val = I915_READ(PCH_DREF_CONTROL);
4841
4842 /* As we must carefully and slowly disable/enable each source in turn,
4843 * compute the final state we want first and check if we need to
4844 * make any changes at all.
4845 */
4846 final = val;
4847 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4848 if (has_ck505)
4849 final |= DREF_NONSPREAD_CK505_ENABLE;
4850 else
4851 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4852
4853 final &= ~DREF_SSC_SOURCE_MASK;
4854 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4855 final &= ~DREF_SSC1_ENABLE;
4856
4857 if (has_panel) {
4858 final |= DREF_SSC_SOURCE_ENABLE;
4859
4860 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4861 final |= DREF_SSC1_ENABLE;
4862
4863 if (has_cpu_edp) {
4864 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4865 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4866 else
4867 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4868 } else
4869 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4870 } else {
4871 final |= DREF_SSC_SOURCE_DISABLE;
4872 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4873 }
4874
4875 if (final == val)
4876 return;
4877
4878 /* Always enable nonspread source */
4879 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4880
4881 if (has_ck505)
4882 val |= DREF_NONSPREAD_CK505_ENABLE;
4883 else
4884 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4885
4886 if (has_panel) {
4887 val &= ~DREF_SSC_SOURCE_MASK;
4888 val |= DREF_SSC_SOURCE_ENABLE;
4889
4890 /* SSC must be turned on before enabling the CPU output */
4891 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4892 DRM_DEBUG_KMS("Using SSC on panel\n");
4893 val |= DREF_SSC1_ENABLE;
4894 } else
4895 val &= ~DREF_SSC1_ENABLE;
4896
4897 /* Get SSC going before enabling the outputs */
4898 I915_WRITE(PCH_DREF_CONTROL, val);
4899 POSTING_READ(PCH_DREF_CONTROL);
4900 udelay(200);
4901
4902 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4903
4904 /* Enable CPU source on CPU attached eDP */
4905 if (has_cpu_edp) {
4906 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4907 DRM_DEBUG_KMS("Using SSC on eDP\n");
4908 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4909 }
4910 else
4911 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4912 } else
4913 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4914
4915 I915_WRITE(PCH_DREF_CONTROL, val);
4916 POSTING_READ(PCH_DREF_CONTROL);
4917 udelay(200);
4918 } else {
4919 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4920
4921 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4922
4923 /* Turn off CPU output */
4924 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4925
4926 I915_WRITE(PCH_DREF_CONTROL, val);
4927 POSTING_READ(PCH_DREF_CONTROL);
4928 udelay(200);
4929
4930 /* Turn off the SSC source */
4931 val &= ~DREF_SSC_SOURCE_MASK;
4932 val |= DREF_SSC_SOURCE_DISABLE;
4933
4934 /* Turn off SSC1 */
4935 val &= ~DREF_SSC1_ENABLE;
4936
4937 I915_WRITE(PCH_DREF_CONTROL, val);
4938 POSTING_READ(PCH_DREF_CONTROL);
4939 udelay(200);
4940 }
4941
4942 BUG_ON(val != final);
4943 }
4944
4945 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4946 static void lpt_init_pch_refclk(struct drm_device *dev)
4947 {
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_mode_config *mode_config = &dev->mode_config;
4950 struct intel_encoder *encoder;
4951 bool has_vga = false;
4952 bool is_sdv = false;
4953 u32 tmp;
4954
4955 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4956 switch (encoder->type) {
4957 case INTEL_OUTPUT_ANALOG:
4958 has_vga = true;
4959 break;
4960 }
4961 }
4962
4963 if (!has_vga)
4964 return;
4965
4966 mutex_lock(&dev_priv->dpio_lock);
4967
4968 /* XXX: Rip out SDV support once Haswell ships for real. */
4969 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4970 is_sdv = true;
4971
4972 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4973 tmp &= ~SBI_SSCCTL_DISABLE;
4974 tmp |= SBI_SSCCTL_PATHALT;
4975 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4976
4977 udelay(24);
4978
4979 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4980 tmp &= ~SBI_SSCCTL_PATHALT;
4981 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4982
4983 if (!is_sdv) {
4984 tmp = I915_READ(SOUTH_CHICKEN2);
4985 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4986 I915_WRITE(SOUTH_CHICKEN2, tmp);
4987
4988 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4989 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4990 DRM_ERROR("FDI mPHY reset assert timeout\n");
4991
4992 tmp = I915_READ(SOUTH_CHICKEN2);
4993 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4994 I915_WRITE(SOUTH_CHICKEN2, tmp);
4995
4996 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4997 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4998 100))
4999 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5000 }
5001
5002 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5003 tmp &= ~(0xFF << 24);
5004 tmp |= (0x12 << 24);
5005 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5006
5007 if (is_sdv) {
5008 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5009 tmp |= 0x7FFF;
5010 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5011 }
5012
5013 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5014 tmp |= (1 << 11);
5015 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5016
5017 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5018 tmp |= (1 << 11);
5019 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5020
5021 if (is_sdv) {
5022 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5023 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5024 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5025
5026 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5027 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5028 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5029
5030 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5031 tmp |= (0x3F << 8);
5032 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5033
5034 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5035 tmp |= (0x3F << 8);
5036 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5037 }
5038
5039 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5040 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5041 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5042
5043 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5044 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5045 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5046
5047 if (!is_sdv) {
5048 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5049 tmp &= ~(7 << 13);
5050 tmp |= (5 << 13);
5051 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5052
5053 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5054 tmp &= ~(7 << 13);
5055 tmp |= (5 << 13);
5056 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5057 }
5058
5059 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5060 tmp &= ~0xFF;
5061 tmp |= 0x1C;
5062 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5063
5064 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5065 tmp &= ~0xFF;
5066 tmp |= 0x1C;
5067 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5068
5069 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5070 tmp &= ~(0xFF << 16);
5071 tmp |= (0x1C << 16);
5072 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5073
5074 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5075 tmp &= ~(0xFF << 16);
5076 tmp |= (0x1C << 16);
5077 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5078
5079 if (!is_sdv) {
5080 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5081 tmp |= (1 << 27);
5082 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5083
5084 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5085 tmp |= (1 << 27);
5086 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5087
5088 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5089 tmp &= ~(0xF << 28);
5090 tmp |= (4 << 28);
5091 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5092
5093 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5094 tmp &= ~(0xF << 28);
5095 tmp |= (4 << 28);
5096 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5097 }
5098
5099 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5100 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5101 tmp |= SBI_DBUFF0_ENABLE;
5102 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5103
5104 mutex_unlock(&dev_priv->dpio_lock);
5105 }
5106
5107 /*
5108 * Initialize reference clocks when the driver loads
5109 */
5110 void intel_init_pch_refclk(struct drm_device *dev)
5111 {
5112 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5113 ironlake_init_pch_refclk(dev);
5114 else if (HAS_PCH_LPT(dev))
5115 lpt_init_pch_refclk(dev);
5116 }
5117
5118 static int ironlake_get_refclk(struct drm_crtc *crtc)
5119 {
5120 struct drm_device *dev = crtc->dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct intel_encoder *encoder;
5123 struct intel_encoder *edp_encoder = NULL;
5124 int num_connectors = 0;
5125 bool is_lvds = false;
5126
5127 for_each_encoder_on_crtc(dev, crtc, encoder) {
5128 switch (encoder->type) {
5129 case INTEL_OUTPUT_LVDS:
5130 is_lvds = true;
5131 break;
5132 case INTEL_OUTPUT_EDP:
5133 edp_encoder = encoder;
5134 break;
5135 }
5136 num_connectors++;
5137 }
5138
5139 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5140 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5141 dev_priv->lvds_ssc_freq);
5142 return dev_priv->lvds_ssc_freq * 1000;
5143 }
5144
5145 return 120000;
5146 }
5147
5148 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5149 struct drm_display_mode *adjusted_mode)
5150 {
5151 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153 int pipe = intel_crtc->pipe;
5154 uint32_t val;
5155
5156 val = I915_READ(PIPECONF(pipe));
5157
5158 val &= ~PIPECONF_BPC_MASK;
5159 switch (intel_crtc->config.pipe_bpp) {
5160 case 18:
5161 val |= PIPECONF_6BPC;
5162 break;
5163 case 24:
5164 val |= PIPECONF_8BPC;
5165 break;
5166 case 30:
5167 val |= PIPECONF_10BPC;
5168 break;
5169 case 36:
5170 val |= PIPECONF_12BPC;
5171 break;
5172 default:
5173 /* Case prevented by intel_choose_pipe_bpp_dither. */
5174 BUG();
5175 }
5176
5177 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5178 if (intel_crtc->config.dither)
5179 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5180
5181 val &= ~PIPECONF_INTERLACE_MASK;
5182 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5183 val |= PIPECONF_INTERLACED_ILK;
5184 else
5185 val |= PIPECONF_PROGRESSIVE;
5186
5187 if (intel_crtc->config.limited_color_range)
5188 val |= PIPECONF_COLOR_RANGE_SELECT;
5189 else
5190 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5191
5192 I915_WRITE(PIPECONF(pipe), val);
5193 POSTING_READ(PIPECONF(pipe));
5194 }
5195
5196 /*
5197 * Set up the pipe CSC unit.
5198 *
5199 * Currently only full range RGB to limited range RGB conversion
5200 * is supported, but eventually this should handle various
5201 * RGB<->YCbCr scenarios as well.
5202 */
5203 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5204 {
5205 struct drm_device *dev = crtc->dev;
5206 struct drm_i915_private *dev_priv = dev->dev_private;
5207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5208 int pipe = intel_crtc->pipe;
5209 uint16_t coeff = 0x7800; /* 1.0 */
5210
5211 /*
5212 * TODO: Check what kind of values actually come out of the pipe
5213 * with these coeff/postoff values and adjust to get the best
5214 * accuracy. Perhaps we even need to take the bpc value into
5215 * consideration.
5216 */
5217
5218 if (intel_crtc->config.limited_color_range)
5219 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5220
5221 /*
5222 * GY/GU and RY/RU should be the other way around according
5223 * to BSpec, but reality doesn't agree. Just set them up in
5224 * a way that results in the correct picture.
5225 */
5226 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5227 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5228
5229 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5230 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5231
5232 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5233 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5234
5235 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5236 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5237 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5238
5239 if (INTEL_INFO(dev)->gen > 6) {
5240 uint16_t postoff = 0;
5241
5242 if (intel_crtc->config.limited_color_range)
5243 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5244
5245 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5246 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5247 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5248
5249 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5250 } else {
5251 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5252
5253 if (intel_crtc->config.limited_color_range)
5254 mode |= CSC_BLACK_SCREEN_OFFSET;
5255
5256 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5257 }
5258 }
5259
5260 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5261 struct drm_display_mode *adjusted_mode)
5262 {
5263 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5265 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5266 uint32_t val;
5267
5268 val = I915_READ(PIPECONF(cpu_transcoder));
5269
5270 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5271 if (intel_crtc->config.dither)
5272 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5273
5274 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5275 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5276 val |= PIPECONF_INTERLACED_ILK;
5277 else
5278 val |= PIPECONF_PROGRESSIVE;
5279
5280 I915_WRITE(PIPECONF(cpu_transcoder), val);
5281 POSTING_READ(PIPECONF(cpu_transcoder));
5282 }
5283
5284 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5285 struct drm_display_mode *adjusted_mode,
5286 intel_clock_t *clock,
5287 bool *has_reduced_clock,
5288 intel_clock_t *reduced_clock)
5289 {
5290 struct drm_device *dev = crtc->dev;
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292 struct intel_encoder *intel_encoder;
5293 int refclk;
5294 const intel_limit_t *limit;
5295 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5296
5297 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5298 switch (intel_encoder->type) {
5299 case INTEL_OUTPUT_LVDS:
5300 is_lvds = true;
5301 break;
5302 case INTEL_OUTPUT_SDVO:
5303 case INTEL_OUTPUT_HDMI:
5304 is_sdvo = true;
5305 if (intel_encoder->needs_tv_clock)
5306 is_tv = true;
5307 break;
5308 case INTEL_OUTPUT_TVOUT:
5309 is_tv = true;
5310 break;
5311 }
5312 }
5313
5314 refclk = ironlake_get_refclk(crtc);
5315
5316 /*
5317 * Returns a set of divisors for the desired target clock with the given
5318 * refclk, or FALSE. The returned values represent the clock equation:
5319 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5320 */
5321 limit = intel_limit(crtc, refclk);
5322 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5323 clock);
5324 if (!ret)
5325 return false;
5326
5327 if (is_lvds && dev_priv->lvds_downclock_avail) {
5328 /*
5329 * Ensure we match the reduced clock's P to the target clock.
5330 * If the clocks don't match, we can't switch the display clock
5331 * by using the FP0/FP1. In such case we will disable the LVDS
5332 * downclock feature.
5333 */
5334 *has_reduced_clock = limit->find_pll(limit, crtc,
5335 dev_priv->lvds_downclock,
5336 refclk,
5337 clock,
5338 reduced_clock);
5339 }
5340
5341 if (is_sdvo && is_tv)
5342 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5343
5344 return true;
5345 }
5346
5347 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5348 {
5349 struct drm_i915_private *dev_priv = dev->dev_private;
5350 uint32_t temp;
5351
5352 temp = I915_READ(SOUTH_CHICKEN1);
5353 if (temp & FDI_BC_BIFURCATION_SELECT)
5354 return;
5355
5356 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5357 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5358
5359 temp |= FDI_BC_BIFURCATION_SELECT;
5360 DRM_DEBUG_KMS("enabling fdi C rx\n");
5361 I915_WRITE(SOUTH_CHICKEN1, temp);
5362 POSTING_READ(SOUTH_CHICKEN1);
5363 }
5364
5365 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5366 {
5367 struct drm_device *dev = intel_crtc->base.dev;
5368 struct drm_i915_private *dev_priv = dev->dev_private;
5369 struct intel_crtc *pipe_B_crtc =
5370 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5371
5372 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5373 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5374 if (intel_crtc->fdi_lanes > 4) {
5375 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5376 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5377 /* Clamp lanes to avoid programming the hw with bogus values. */
5378 intel_crtc->fdi_lanes = 4;
5379
5380 return false;
5381 }
5382
5383 if (INTEL_INFO(dev)->num_pipes == 2)
5384 return true;
5385
5386 switch (intel_crtc->pipe) {
5387 case PIPE_A:
5388 return true;
5389 case PIPE_B:
5390 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5391 intel_crtc->fdi_lanes > 2) {
5392 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5393 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5394 /* Clamp lanes to avoid programming the hw with bogus values. */
5395 intel_crtc->fdi_lanes = 2;
5396
5397 return false;
5398 }
5399
5400 if (intel_crtc->fdi_lanes > 2)
5401 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5402 else
5403 cpt_enable_fdi_bc_bifurcation(dev);
5404
5405 return true;
5406 case PIPE_C:
5407 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5408 if (intel_crtc->fdi_lanes > 2) {
5409 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5410 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5411 /* Clamp lanes to avoid programming the hw with bogus values. */
5412 intel_crtc->fdi_lanes = 2;
5413
5414 return false;
5415 }
5416 } else {
5417 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5418 return false;
5419 }
5420
5421 cpt_enable_fdi_bc_bifurcation(dev);
5422
5423 return true;
5424 default:
5425 BUG();
5426 }
5427 }
5428
5429 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5430 {
5431 /*
5432 * Account for spread spectrum to avoid
5433 * oversubscribing the link. Max center spread
5434 * is 2.5%; use 5% for safety's sake.
5435 */
5436 u32 bps = target_clock * bpp * 21 / 20;
5437 return bps / (link_bw * 8) + 1;
5438 }
5439
5440 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5441 struct intel_link_m_n *m_n)
5442 {
5443 struct drm_device *dev = crtc->base.dev;
5444 struct drm_i915_private *dev_priv = dev->dev_private;
5445 int pipe = crtc->pipe;
5446
5447 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5448 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5449 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5450 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5451 }
5452
5453 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5454 struct intel_link_m_n *m_n)
5455 {
5456 struct drm_device *dev = crtc->base.dev;
5457 struct drm_i915_private *dev_priv = dev->dev_private;
5458 int pipe = crtc->pipe;
5459 enum transcoder transcoder = crtc->config.cpu_transcoder;
5460
5461 if (INTEL_INFO(dev)->gen >= 5) {
5462 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5463 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5464 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5465 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5466 } else {
5467 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5468 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5469 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5470 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5471 }
5472 }
5473
5474 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5475 {
5476 struct drm_device *dev = crtc->dev;
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5478 struct drm_display_mode *adjusted_mode =
5479 &intel_crtc->config.adjusted_mode;
5480 struct intel_link_m_n m_n = {0};
5481 int target_clock, lane, link_bw;
5482
5483 /* FDI is a binary signal running at ~2.7GHz, encoding
5484 * each output octet as 10 bits. The actual frequency
5485 * is stored as a divider into a 100MHz clock, and the
5486 * mode pixel clock is stored in units of 1KHz.
5487 * Hence the bw of each lane in terms of the mode signal
5488 * is:
5489 */
5490 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5491
5492 if (intel_crtc->config.pixel_target_clock)
5493 target_clock = intel_crtc->config.pixel_target_clock;
5494 else
5495 target_clock = adjusted_mode->clock;
5496
5497 lane = ironlake_get_lanes_required(target_clock, link_bw,
5498 intel_crtc->config.pipe_bpp);
5499
5500 intel_crtc->fdi_lanes = lane;
5501
5502 if (intel_crtc->config.pixel_multiplier > 1)
5503 link_bw *= intel_crtc->config.pixel_multiplier;
5504 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5505 link_bw, &m_n);
5506
5507 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5508 }
5509
5510 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5511 {
5512 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5513 }
5514
5515 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5516 u32 *fp,
5517 intel_clock_t *reduced_clock, u32 *fp2)
5518 {
5519 struct drm_crtc *crtc = &intel_crtc->base;
5520 struct drm_device *dev = crtc->dev;
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522 struct intel_encoder *intel_encoder;
5523 uint32_t dpll;
5524 int factor, num_connectors = 0;
5525 bool is_lvds = false, is_sdvo = false, is_tv = false;
5526
5527 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5528 switch (intel_encoder->type) {
5529 case INTEL_OUTPUT_LVDS:
5530 is_lvds = true;
5531 break;
5532 case INTEL_OUTPUT_SDVO:
5533 case INTEL_OUTPUT_HDMI:
5534 is_sdvo = true;
5535 if (intel_encoder->needs_tv_clock)
5536 is_tv = true;
5537 break;
5538 case INTEL_OUTPUT_TVOUT:
5539 is_tv = true;
5540 break;
5541 }
5542
5543 num_connectors++;
5544 }
5545
5546 /* Enable autotuning of the PLL clock (if permissible) */
5547 factor = 21;
5548 if (is_lvds) {
5549 if ((intel_panel_use_ssc(dev_priv) &&
5550 dev_priv->lvds_ssc_freq == 100) ||
5551 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5552 factor = 25;
5553 } else if (is_sdvo && is_tv)
5554 factor = 20;
5555
5556 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5557 *fp |= FP_CB_TUNE;
5558
5559 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5560 *fp2 |= FP_CB_TUNE;
5561
5562 dpll = 0;
5563
5564 if (is_lvds)
5565 dpll |= DPLLB_MODE_LVDS;
5566 else
5567 dpll |= DPLLB_MODE_DAC_SERIAL;
5568 if (is_sdvo) {
5569 if (intel_crtc->config.pixel_multiplier > 1) {
5570 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5571 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5572 }
5573 dpll |= DPLL_DVO_HIGH_SPEED;
5574 }
5575 if (intel_crtc->config.has_dp_encoder &&
5576 intel_crtc->config.has_pch_encoder)
5577 dpll |= DPLL_DVO_HIGH_SPEED;
5578
5579 /* compute bitmask from p1 value */
5580 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5581 /* also FPA1 */
5582 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5583
5584 switch (intel_crtc->config.dpll.p2) {
5585 case 5:
5586 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5587 break;
5588 case 7:
5589 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5590 break;
5591 case 10:
5592 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5593 break;
5594 case 14:
5595 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5596 break;
5597 }
5598
5599 if (is_sdvo && is_tv)
5600 dpll |= PLL_REF_INPUT_TVCLKINBC;
5601 else if (is_tv)
5602 /* XXX: just matching BIOS for now */
5603 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5604 dpll |= 3;
5605 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5606 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5607 else
5608 dpll |= PLL_REF_INPUT_DREFCLK;
5609
5610 return dpll;
5611 }
5612
5613 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5614 int x, int y,
5615 struct drm_framebuffer *fb)
5616 {
5617 struct drm_device *dev = crtc->dev;
5618 struct drm_i915_private *dev_priv = dev->dev_private;
5619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5620 struct drm_display_mode *adjusted_mode =
5621 &intel_crtc->config.adjusted_mode;
5622 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5623 int pipe = intel_crtc->pipe;
5624 int plane = intel_crtc->plane;
5625 int num_connectors = 0;
5626 intel_clock_t clock, reduced_clock;
5627 u32 dpll = 0, fp = 0, fp2 = 0;
5628 bool ok, has_reduced_clock = false;
5629 bool is_lvds = false;
5630 struct intel_encoder *encoder;
5631 int ret;
5632 bool fdi_config_ok;
5633
5634 for_each_encoder_on_crtc(dev, crtc, encoder) {
5635 switch (encoder->type) {
5636 case INTEL_OUTPUT_LVDS:
5637 is_lvds = true;
5638 break;
5639 }
5640
5641 num_connectors++;
5642 }
5643
5644 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5645 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5646
5647 intel_crtc->config.cpu_transcoder = pipe;
5648
5649 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5650 &has_reduced_clock, &reduced_clock);
5651 if (!ok) {
5652 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5653 return -EINVAL;
5654 }
5655 /* Compat-code for transition, will disappear. */
5656 if (!intel_crtc->config.clock_set) {
5657 intel_crtc->config.dpll.n = clock.n;
5658 intel_crtc->config.dpll.m1 = clock.m1;
5659 intel_crtc->config.dpll.m2 = clock.m2;
5660 intel_crtc->config.dpll.p1 = clock.p1;
5661 intel_crtc->config.dpll.p2 = clock.p2;
5662 }
5663
5664 /* Ensure that the cursor is valid for the new mode before changing... */
5665 intel_crtc_update_cursor(crtc, true);
5666
5667 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5668 drm_mode_debug_printmodeline(mode);
5669
5670 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5671 if (intel_crtc->config.has_pch_encoder) {
5672 struct intel_pch_pll *pll;
5673
5674 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5675 if (has_reduced_clock)
5676 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5677
5678 dpll = ironlake_compute_dpll(intel_crtc,
5679 &fp, &reduced_clock,
5680 has_reduced_clock ? &fp2 : NULL);
5681
5682 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5683 if (pll == NULL) {
5684 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5685 pipe_name(pipe));
5686 return -EINVAL;
5687 }
5688 } else
5689 intel_put_pch_pll(intel_crtc);
5690
5691 if (intel_crtc->config.has_dp_encoder)
5692 intel_dp_set_m_n(intel_crtc);
5693
5694 for_each_encoder_on_crtc(dev, crtc, encoder)
5695 if (encoder->pre_pll_enable)
5696 encoder->pre_pll_enable(encoder);
5697
5698 if (intel_crtc->pch_pll) {
5699 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5700
5701 /* Wait for the clocks to stabilize. */
5702 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5703 udelay(150);
5704
5705 /* The pixel multiplier can only be updated once the
5706 * DPLL is enabled and the clocks are stable.
5707 *
5708 * So write it again.
5709 */
5710 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5711 }
5712
5713 intel_crtc->lowfreq_avail = false;
5714 if (intel_crtc->pch_pll) {
5715 if (is_lvds && has_reduced_clock && i915_powersave) {
5716 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5717 intel_crtc->lowfreq_avail = true;
5718 } else {
5719 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5720 }
5721 }
5722
5723 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5724
5725 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5726 * ironlake_check_fdi_lanes. */
5727 intel_crtc->fdi_lanes = 0;
5728 if (intel_crtc->config.has_pch_encoder)
5729 ironlake_fdi_set_m_n(crtc);
5730
5731 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5732
5733 ironlake_set_pipeconf(crtc, adjusted_mode);
5734
5735 /* Set up the display plane register */
5736 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5737 POSTING_READ(DSPCNTR(plane));
5738
5739 ret = intel_pipe_set_base(crtc, x, y, fb);
5740
5741 intel_update_watermarks(dev);
5742
5743 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5744
5745 return fdi_config_ok ? ret : -EINVAL;
5746 }
5747
5748 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5749 struct intel_crtc_config *pipe_config)
5750 {
5751 struct drm_device *dev = crtc->base.dev;
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753 uint32_t tmp;
5754
5755 tmp = I915_READ(PIPECONF(crtc->pipe));
5756 if (!(tmp & PIPECONF_ENABLE))
5757 return false;
5758
5759 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5760 pipe_config->has_pch_encoder = true;
5761
5762 return true;
5763 }
5764
5765 static void haswell_modeset_global_resources(struct drm_device *dev)
5766 {
5767 struct drm_i915_private *dev_priv = dev->dev_private;
5768 bool enable = false;
5769 struct intel_crtc *crtc;
5770 struct intel_encoder *encoder;
5771
5772 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5773 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5774 enable = true;
5775 /* XXX: Should check for edp transcoder here, but thanks to init
5776 * sequence that's not yet available. Just in case desktop eDP
5777 * on PORT D is possible on haswell, too. */
5778 }
5779
5780 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5781 base.head) {
5782 if (encoder->type != INTEL_OUTPUT_EDP &&
5783 encoder->connectors_active)
5784 enable = true;
5785 }
5786
5787 /* Even the eDP panel fitter is outside the always-on well. */
5788 if (dev_priv->pch_pf_size)
5789 enable = true;
5790
5791 intel_set_power_well(dev, enable);
5792 }
5793
5794 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5795 int x, int y,
5796 struct drm_framebuffer *fb)
5797 {
5798 struct drm_device *dev = crtc->dev;
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5801 struct drm_display_mode *adjusted_mode =
5802 &intel_crtc->config.adjusted_mode;
5803 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5804 int pipe = intel_crtc->pipe;
5805 int plane = intel_crtc->plane;
5806 int num_connectors = 0;
5807 bool is_cpu_edp = false;
5808 struct intel_encoder *encoder;
5809 int ret;
5810
5811 for_each_encoder_on_crtc(dev, crtc, encoder) {
5812 switch (encoder->type) {
5813 case INTEL_OUTPUT_EDP:
5814 if (!intel_encoder_is_pch_edp(&encoder->base))
5815 is_cpu_edp = true;
5816 break;
5817 }
5818
5819 num_connectors++;
5820 }
5821
5822 if (is_cpu_edp)
5823 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5824 else
5825 intel_crtc->config.cpu_transcoder = pipe;
5826
5827 /* We are not sure yet this won't happen. */
5828 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5829 INTEL_PCH_TYPE(dev));
5830
5831 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5832 num_connectors, pipe_name(pipe));
5833
5834 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5835 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5836
5837 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5838
5839 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5840 return -EINVAL;
5841
5842 /* Ensure that the cursor is valid for the new mode before changing... */
5843 intel_crtc_update_cursor(crtc, true);
5844
5845 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5846 drm_mode_debug_printmodeline(mode);
5847
5848 if (intel_crtc->config.has_dp_encoder)
5849 intel_dp_set_m_n(intel_crtc);
5850
5851 intel_crtc->lowfreq_avail = false;
5852
5853 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5854
5855 if (intel_crtc->config.has_pch_encoder)
5856 ironlake_fdi_set_m_n(crtc);
5857
5858 haswell_set_pipeconf(crtc, adjusted_mode);
5859
5860 intel_set_pipe_csc(crtc);
5861
5862 /* Set up the display plane register */
5863 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5864 POSTING_READ(DSPCNTR(plane));
5865
5866 ret = intel_pipe_set_base(crtc, x, y, fb);
5867
5868 intel_update_watermarks(dev);
5869
5870 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5871
5872 return ret;
5873 }
5874
5875 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5876 struct intel_crtc_config *pipe_config)
5877 {
5878 struct drm_device *dev = crtc->base.dev;
5879 struct drm_i915_private *dev_priv = dev->dev_private;
5880 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
5881 uint32_t tmp;
5882
5883 if (!intel_using_power_well(dev_priv->dev) &&
5884 cpu_transcoder != TRANSCODER_EDP)
5885 return false;
5886
5887 tmp = I915_READ(PIPECONF(cpu_transcoder));
5888 if (!(tmp & PIPECONF_ENABLE))
5889 return false;
5890
5891 /*
5892 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5893 * DDI E. So just check whether this pipe is wired to DDI E and whether
5894 * the PCH transcoder is on.
5895 */
5896 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
5897 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5898 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5899 pipe_config->has_pch_encoder = true;
5900
5901 return true;
5902 }
5903
5904 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5905 int x, int y,
5906 struct drm_framebuffer *fb)
5907 {
5908 struct drm_device *dev = crtc->dev;
5909 struct drm_i915_private *dev_priv = dev->dev_private;
5910 struct drm_encoder_helper_funcs *encoder_funcs;
5911 struct intel_encoder *encoder;
5912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5913 struct drm_display_mode *adjusted_mode =
5914 &intel_crtc->config.adjusted_mode;
5915 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5916 int pipe = intel_crtc->pipe;
5917 int ret;
5918
5919 drm_vblank_pre_modeset(dev, pipe);
5920
5921 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5922
5923 drm_vblank_post_modeset(dev, pipe);
5924
5925 if (ret != 0)
5926 return ret;
5927
5928 for_each_encoder_on_crtc(dev, crtc, encoder) {
5929 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5930 encoder->base.base.id,
5931 drm_get_encoder_name(&encoder->base),
5932 mode->base.id, mode->name);
5933 if (encoder->mode_set) {
5934 encoder->mode_set(encoder);
5935 } else {
5936 encoder_funcs = encoder->base.helper_private;
5937 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5938 }
5939 }
5940
5941 return 0;
5942 }
5943
5944 static bool intel_eld_uptodate(struct drm_connector *connector,
5945 int reg_eldv, uint32_t bits_eldv,
5946 int reg_elda, uint32_t bits_elda,
5947 int reg_edid)
5948 {
5949 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5950 uint8_t *eld = connector->eld;
5951 uint32_t i;
5952
5953 i = I915_READ(reg_eldv);
5954 i &= bits_eldv;
5955
5956 if (!eld[0])
5957 return !i;
5958
5959 if (!i)
5960 return false;
5961
5962 i = I915_READ(reg_elda);
5963 i &= ~bits_elda;
5964 I915_WRITE(reg_elda, i);
5965
5966 for (i = 0; i < eld[2]; i++)
5967 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5968 return false;
5969
5970 return true;
5971 }
5972
5973 static void g4x_write_eld(struct drm_connector *connector,
5974 struct drm_crtc *crtc)
5975 {
5976 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5977 uint8_t *eld = connector->eld;
5978 uint32_t eldv;
5979 uint32_t len;
5980 uint32_t i;
5981
5982 i = I915_READ(G4X_AUD_VID_DID);
5983
5984 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5985 eldv = G4X_ELDV_DEVCL_DEVBLC;
5986 else
5987 eldv = G4X_ELDV_DEVCTG;
5988
5989 if (intel_eld_uptodate(connector,
5990 G4X_AUD_CNTL_ST, eldv,
5991 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5992 G4X_HDMIW_HDMIEDID))
5993 return;
5994
5995 i = I915_READ(G4X_AUD_CNTL_ST);
5996 i &= ~(eldv | G4X_ELD_ADDR);
5997 len = (i >> 9) & 0x1f; /* ELD buffer size */
5998 I915_WRITE(G4X_AUD_CNTL_ST, i);
5999
6000 if (!eld[0])
6001 return;
6002
6003 len = min_t(uint8_t, eld[2], len);
6004 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6005 for (i = 0; i < len; i++)
6006 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6007
6008 i = I915_READ(G4X_AUD_CNTL_ST);
6009 i |= eldv;
6010 I915_WRITE(G4X_AUD_CNTL_ST, i);
6011 }
6012
6013 static void haswell_write_eld(struct drm_connector *connector,
6014 struct drm_crtc *crtc)
6015 {
6016 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6017 uint8_t *eld = connector->eld;
6018 struct drm_device *dev = crtc->dev;
6019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6020 uint32_t eldv;
6021 uint32_t i;
6022 int len;
6023 int pipe = to_intel_crtc(crtc)->pipe;
6024 int tmp;
6025
6026 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6027 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6028 int aud_config = HSW_AUD_CFG(pipe);
6029 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6030
6031
6032 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6033
6034 /* Audio output enable */
6035 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6036 tmp = I915_READ(aud_cntrl_st2);
6037 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6038 I915_WRITE(aud_cntrl_st2, tmp);
6039
6040 /* Wait for 1 vertical blank */
6041 intel_wait_for_vblank(dev, pipe);
6042
6043 /* Set ELD valid state */
6044 tmp = I915_READ(aud_cntrl_st2);
6045 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6046 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6047 I915_WRITE(aud_cntrl_st2, tmp);
6048 tmp = I915_READ(aud_cntrl_st2);
6049 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6050
6051 /* Enable HDMI mode */
6052 tmp = I915_READ(aud_config);
6053 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6054 /* clear N_programing_enable and N_value_index */
6055 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6056 I915_WRITE(aud_config, tmp);
6057
6058 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6059
6060 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6061 intel_crtc->eld_vld = true;
6062
6063 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6064 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6065 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6066 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6067 } else
6068 I915_WRITE(aud_config, 0);
6069
6070 if (intel_eld_uptodate(connector,
6071 aud_cntrl_st2, eldv,
6072 aud_cntl_st, IBX_ELD_ADDRESS,
6073 hdmiw_hdmiedid))
6074 return;
6075
6076 i = I915_READ(aud_cntrl_st2);
6077 i &= ~eldv;
6078 I915_WRITE(aud_cntrl_st2, i);
6079
6080 if (!eld[0])
6081 return;
6082
6083 i = I915_READ(aud_cntl_st);
6084 i &= ~IBX_ELD_ADDRESS;
6085 I915_WRITE(aud_cntl_st, i);
6086 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6087 DRM_DEBUG_DRIVER("port num:%d\n", i);
6088
6089 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6090 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6091 for (i = 0; i < len; i++)
6092 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6093
6094 i = I915_READ(aud_cntrl_st2);
6095 i |= eldv;
6096 I915_WRITE(aud_cntrl_st2, i);
6097
6098 }
6099
6100 static void ironlake_write_eld(struct drm_connector *connector,
6101 struct drm_crtc *crtc)
6102 {
6103 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6104 uint8_t *eld = connector->eld;
6105 uint32_t eldv;
6106 uint32_t i;
6107 int len;
6108 int hdmiw_hdmiedid;
6109 int aud_config;
6110 int aud_cntl_st;
6111 int aud_cntrl_st2;
6112 int pipe = to_intel_crtc(crtc)->pipe;
6113
6114 if (HAS_PCH_IBX(connector->dev)) {
6115 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6116 aud_config = IBX_AUD_CFG(pipe);
6117 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6118 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6119 } else {
6120 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6121 aud_config = CPT_AUD_CFG(pipe);
6122 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6123 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6124 }
6125
6126 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6127
6128 i = I915_READ(aud_cntl_st);
6129 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6130 if (!i) {
6131 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6132 /* operate blindly on all ports */
6133 eldv = IBX_ELD_VALIDB;
6134 eldv |= IBX_ELD_VALIDB << 4;
6135 eldv |= IBX_ELD_VALIDB << 8;
6136 } else {
6137 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6138 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6139 }
6140
6141 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6142 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6143 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6144 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6145 } else
6146 I915_WRITE(aud_config, 0);
6147
6148 if (intel_eld_uptodate(connector,
6149 aud_cntrl_st2, eldv,
6150 aud_cntl_st, IBX_ELD_ADDRESS,
6151 hdmiw_hdmiedid))
6152 return;
6153
6154 i = I915_READ(aud_cntrl_st2);
6155 i &= ~eldv;
6156 I915_WRITE(aud_cntrl_st2, i);
6157
6158 if (!eld[0])
6159 return;
6160
6161 i = I915_READ(aud_cntl_st);
6162 i &= ~IBX_ELD_ADDRESS;
6163 I915_WRITE(aud_cntl_st, i);
6164
6165 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6166 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6167 for (i = 0; i < len; i++)
6168 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6169
6170 i = I915_READ(aud_cntrl_st2);
6171 i |= eldv;
6172 I915_WRITE(aud_cntrl_st2, i);
6173 }
6174
6175 void intel_write_eld(struct drm_encoder *encoder,
6176 struct drm_display_mode *mode)
6177 {
6178 struct drm_crtc *crtc = encoder->crtc;
6179 struct drm_connector *connector;
6180 struct drm_device *dev = encoder->dev;
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6182
6183 connector = drm_select_eld(encoder, mode);
6184 if (!connector)
6185 return;
6186
6187 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6188 connector->base.id,
6189 drm_get_connector_name(connector),
6190 connector->encoder->base.id,
6191 drm_get_encoder_name(connector->encoder));
6192
6193 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6194
6195 if (dev_priv->display.write_eld)
6196 dev_priv->display.write_eld(connector, crtc);
6197 }
6198
6199 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6200 void intel_crtc_load_lut(struct drm_crtc *crtc)
6201 {
6202 struct drm_device *dev = crtc->dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6205 int palreg = PALETTE(intel_crtc->pipe);
6206 int i;
6207
6208 /* The clocks have to be on to load the palette. */
6209 if (!crtc->enabled || !intel_crtc->active)
6210 return;
6211
6212 /* use legacy palette for Ironlake */
6213 if (HAS_PCH_SPLIT(dev))
6214 palreg = LGC_PALETTE(intel_crtc->pipe);
6215
6216 for (i = 0; i < 256; i++) {
6217 I915_WRITE(palreg + 4 * i,
6218 (intel_crtc->lut_r[i] << 16) |
6219 (intel_crtc->lut_g[i] << 8) |
6220 intel_crtc->lut_b[i]);
6221 }
6222 }
6223
6224 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6225 {
6226 struct drm_device *dev = crtc->dev;
6227 struct drm_i915_private *dev_priv = dev->dev_private;
6228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6229 bool visible = base != 0;
6230 u32 cntl;
6231
6232 if (intel_crtc->cursor_visible == visible)
6233 return;
6234
6235 cntl = I915_READ(_CURACNTR);
6236 if (visible) {
6237 /* On these chipsets we can only modify the base whilst
6238 * the cursor is disabled.
6239 */
6240 I915_WRITE(_CURABASE, base);
6241
6242 cntl &= ~(CURSOR_FORMAT_MASK);
6243 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6244 cntl |= CURSOR_ENABLE |
6245 CURSOR_GAMMA_ENABLE |
6246 CURSOR_FORMAT_ARGB;
6247 } else
6248 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6249 I915_WRITE(_CURACNTR, cntl);
6250
6251 intel_crtc->cursor_visible = visible;
6252 }
6253
6254 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6255 {
6256 struct drm_device *dev = crtc->dev;
6257 struct drm_i915_private *dev_priv = dev->dev_private;
6258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6259 int pipe = intel_crtc->pipe;
6260 bool visible = base != 0;
6261
6262 if (intel_crtc->cursor_visible != visible) {
6263 uint32_t cntl = I915_READ(CURCNTR(pipe));
6264 if (base) {
6265 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6266 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6267 cntl |= pipe << 28; /* Connect to correct pipe */
6268 } else {
6269 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6270 cntl |= CURSOR_MODE_DISABLE;
6271 }
6272 I915_WRITE(CURCNTR(pipe), cntl);
6273
6274 intel_crtc->cursor_visible = visible;
6275 }
6276 /* and commit changes on next vblank */
6277 I915_WRITE(CURBASE(pipe), base);
6278 }
6279
6280 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6281 {
6282 struct drm_device *dev = crtc->dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6285 int pipe = intel_crtc->pipe;
6286 bool visible = base != 0;
6287
6288 if (intel_crtc->cursor_visible != visible) {
6289 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6290 if (base) {
6291 cntl &= ~CURSOR_MODE;
6292 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6293 } else {
6294 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6295 cntl |= CURSOR_MODE_DISABLE;
6296 }
6297 if (IS_HASWELL(dev))
6298 cntl |= CURSOR_PIPE_CSC_ENABLE;
6299 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6300
6301 intel_crtc->cursor_visible = visible;
6302 }
6303 /* and commit changes on next vblank */
6304 I915_WRITE(CURBASE_IVB(pipe), base);
6305 }
6306
6307 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6308 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6309 bool on)
6310 {
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314 int pipe = intel_crtc->pipe;
6315 int x = intel_crtc->cursor_x;
6316 int y = intel_crtc->cursor_y;
6317 u32 base, pos;
6318 bool visible;
6319
6320 pos = 0;
6321
6322 if (on && crtc->enabled && crtc->fb) {
6323 base = intel_crtc->cursor_addr;
6324 if (x > (int) crtc->fb->width)
6325 base = 0;
6326
6327 if (y > (int) crtc->fb->height)
6328 base = 0;
6329 } else
6330 base = 0;
6331
6332 if (x < 0) {
6333 if (x + intel_crtc->cursor_width < 0)
6334 base = 0;
6335
6336 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6337 x = -x;
6338 }
6339 pos |= x << CURSOR_X_SHIFT;
6340
6341 if (y < 0) {
6342 if (y + intel_crtc->cursor_height < 0)
6343 base = 0;
6344
6345 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6346 y = -y;
6347 }
6348 pos |= y << CURSOR_Y_SHIFT;
6349
6350 visible = base != 0;
6351 if (!visible && !intel_crtc->cursor_visible)
6352 return;
6353
6354 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6355 I915_WRITE(CURPOS_IVB(pipe), pos);
6356 ivb_update_cursor(crtc, base);
6357 } else {
6358 I915_WRITE(CURPOS(pipe), pos);
6359 if (IS_845G(dev) || IS_I865G(dev))
6360 i845_update_cursor(crtc, base);
6361 else
6362 i9xx_update_cursor(crtc, base);
6363 }
6364 }
6365
6366 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6367 struct drm_file *file,
6368 uint32_t handle,
6369 uint32_t width, uint32_t height)
6370 {
6371 struct drm_device *dev = crtc->dev;
6372 struct drm_i915_private *dev_priv = dev->dev_private;
6373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6374 struct drm_i915_gem_object *obj;
6375 uint32_t addr;
6376 int ret;
6377
6378 /* if we want to turn off the cursor ignore width and height */
6379 if (!handle) {
6380 DRM_DEBUG_KMS("cursor off\n");
6381 addr = 0;
6382 obj = NULL;
6383 mutex_lock(&dev->struct_mutex);
6384 goto finish;
6385 }
6386
6387 /* Currently we only support 64x64 cursors */
6388 if (width != 64 || height != 64) {
6389 DRM_ERROR("we currently only support 64x64 cursors\n");
6390 return -EINVAL;
6391 }
6392
6393 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6394 if (&obj->base == NULL)
6395 return -ENOENT;
6396
6397 if (obj->base.size < width * height * 4) {
6398 DRM_ERROR("buffer is to small\n");
6399 ret = -ENOMEM;
6400 goto fail;
6401 }
6402
6403 /* we only need to pin inside GTT if cursor is non-phy */
6404 mutex_lock(&dev->struct_mutex);
6405 if (!dev_priv->info->cursor_needs_physical) {
6406 unsigned alignment;
6407
6408 if (obj->tiling_mode) {
6409 DRM_ERROR("cursor cannot be tiled\n");
6410 ret = -EINVAL;
6411 goto fail_locked;
6412 }
6413
6414 /* Note that the w/a also requires 2 PTE of padding following
6415 * the bo. We currently fill all unused PTE with the shadow
6416 * page and so we should always have valid PTE following the
6417 * cursor preventing the VT-d warning.
6418 */
6419 alignment = 0;
6420 if (need_vtd_wa(dev))
6421 alignment = 64*1024;
6422
6423 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6424 if (ret) {
6425 DRM_ERROR("failed to move cursor bo into the GTT\n");
6426 goto fail_locked;
6427 }
6428
6429 ret = i915_gem_object_put_fence(obj);
6430 if (ret) {
6431 DRM_ERROR("failed to release fence for cursor");
6432 goto fail_unpin;
6433 }
6434
6435 addr = obj->gtt_offset;
6436 } else {
6437 int align = IS_I830(dev) ? 16 * 1024 : 256;
6438 ret = i915_gem_attach_phys_object(dev, obj,
6439 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6440 align);
6441 if (ret) {
6442 DRM_ERROR("failed to attach phys object\n");
6443 goto fail_locked;
6444 }
6445 addr = obj->phys_obj->handle->busaddr;
6446 }
6447
6448 if (IS_GEN2(dev))
6449 I915_WRITE(CURSIZE, (height << 12) | width);
6450
6451 finish:
6452 if (intel_crtc->cursor_bo) {
6453 if (dev_priv->info->cursor_needs_physical) {
6454 if (intel_crtc->cursor_bo != obj)
6455 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6456 } else
6457 i915_gem_object_unpin(intel_crtc->cursor_bo);
6458 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6459 }
6460
6461 mutex_unlock(&dev->struct_mutex);
6462
6463 intel_crtc->cursor_addr = addr;
6464 intel_crtc->cursor_bo = obj;
6465 intel_crtc->cursor_width = width;
6466 intel_crtc->cursor_height = height;
6467
6468 intel_crtc_update_cursor(crtc, true);
6469
6470 return 0;
6471 fail_unpin:
6472 i915_gem_object_unpin(obj);
6473 fail_locked:
6474 mutex_unlock(&dev->struct_mutex);
6475 fail:
6476 drm_gem_object_unreference_unlocked(&obj->base);
6477 return ret;
6478 }
6479
6480 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6481 {
6482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6483
6484 intel_crtc->cursor_x = x;
6485 intel_crtc->cursor_y = y;
6486
6487 intel_crtc_update_cursor(crtc, true);
6488
6489 return 0;
6490 }
6491
6492 /** Sets the color ramps on behalf of RandR */
6493 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6494 u16 blue, int regno)
6495 {
6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497
6498 intel_crtc->lut_r[regno] = red >> 8;
6499 intel_crtc->lut_g[regno] = green >> 8;
6500 intel_crtc->lut_b[regno] = blue >> 8;
6501 }
6502
6503 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6504 u16 *blue, int regno)
6505 {
6506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6507
6508 *red = intel_crtc->lut_r[regno] << 8;
6509 *green = intel_crtc->lut_g[regno] << 8;
6510 *blue = intel_crtc->lut_b[regno] << 8;
6511 }
6512
6513 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6514 u16 *blue, uint32_t start, uint32_t size)
6515 {
6516 int end = (start + size > 256) ? 256 : start + size, i;
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6518
6519 for (i = start; i < end; i++) {
6520 intel_crtc->lut_r[i] = red[i] >> 8;
6521 intel_crtc->lut_g[i] = green[i] >> 8;
6522 intel_crtc->lut_b[i] = blue[i] >> 8;
6523 }
6524
6525 intel_crtc_load_lut(crtc);
6526 }
6527
6528 /* VESA 640x480x72Hz mode to set on the pipe */
6529 static struct drm_display_mode load_detect_mode = {
6530 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6531 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6532 };
6533
6534 static struct drm_framebuffer *
6535 intel_framebuffer_create(struct drm_device *dev,
6536 struct drm_mode_fb_cmd2 *mode_cmd,
6537 struct drm_i915_gem_object *obj)
6538 {
6539 struct intel_framebuffer *intel_fb;
6540 int ret;
6541
6542 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6543 if (!intel_fb) {
6544 drm_gem_object_unreference_unlocked(&obj->base);
6545 return ERR_PTR(-ENOMEM);
6546 }
6547
6548 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6549 if (ret) {
6550 drm_gem_object_unreference_unlocked(&obj->base);
6551 kfree(intel_fb);
6552 return ERR_PTR(ret);
6553 }
6554
6555 return &intel_fb->base;
6556 }
6557
6558 static u32
6559 intel_framebuffer_pitch_for_width(int width, int bpp)
6560 {
6561 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6562 return ALIGN(pitch, 64);
6563 }
6564
6565 static u32
6566 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6567 {
6568 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6569 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6570 }
6571
6572 static struct drm_framebuffer *
6573 intel_framebuffer_create_for_mode(struct drm_device *dev,
6574 struct drm_display_mode *mode,
6575 int depth, int bpp)
6576 {
6577 struct drm_i915_gem_object *obj;
6578 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6579
6580 obj = i915_gem_alloc_object(dev,
6581 intel_framebuffer_size_for_mode(mode, bpp));
6582 if (obj == NULL)
6583 return ERR_PTR(-ENOMEM);
6584
6585 mode_cmd.width = mode->hdisplay;
6586 mode_cmd.height = mode->vdisplay;
6587 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6588 bpp);
6589 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6590
6591 return intel_framebuffer_create(dev, &mode_cmd, obj);
6592 }
6593
6594 static struct drm_framebuffer *
6595 mode_fits_in_fbdev(struct drm_device *dev,
6596 struct drm_display_mode *mode)
6597 {
6598 struct drm_i915_private *dev_priv = dev->dev_private;
6599 struct drm_i915_gem_object *obj;
6600 struct drm_framebuffer *fb;
6601
6602 if (dev_priv->fbdev == NULL)
6603 return NULL;
6604
6605 obj = dev_priv->fbdev->ifb.obj;
6606 if (obj == NULL)
6607 return NULL;
6608
6609 fb = &dev_priv->fbdev->ifb.base;
6610 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6611 fb->bits_per_pixel))
6612 return NULL;
6613
6614 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6615 return NULL;
6616
6617 return fb;
6618 }
6619
6620 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6621 struct drm_display_mode *mode,
6622 struct intel_load_detect_pipe *old)
6623 {
6624 struct intel_crtc *intel_crtc;
6625 struct intel_encoder *intel_encoder =
6626 intel_attached_encoder(connector);
6627 struct drm_crtc *possible_crtc;
6628 struct drm_encoder *encoder = &intel_encoder->base;
6629 struct drm_crtc *crtc = NULL;
6630 struct drm_device *dev = encoder->dev;
6631 struct drm_framebuffer *fb;
6632 int i = -1;
6633
6634 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6635 connector->base.id, drm_get_connector_name(connector),
6636 encoder->base.id, drm_get_encoder_name(encoder));
6637
6638 /*
6639 * Algorithm gets a little messy:
6640 *
6641 * - if the connector already has an assigned crtc, use it (but make
6642 * sure it's on first)
6643 *
6644 * - try to find the first unused crtc that can drive this connector,
6645 * and use that if we find one
6646 */
6647
6648 /* See if we already have a CRTC for this connector */
6649 if (encoder->crtc) {
6650 crtc = encoder->crtc;
6651
6652 mutex_lock(&crtc->mutex);
6653
6654 old->dpms_mode = connector->dpms;
6655 old->load_detect_temp = false;
6656
6657 /* Make sure the crtc and connector are running */
6658 if (connector->dpms != DRM_MODE_DPMS_ON)
6659 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6660
6661 return true;
6662 }
6663
6664 /* Find an unused one (if possible) */
6665 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6666 i++;
6667 if (!(encoder->possible_crtcs & (1 << i)))
6668 continue;
6669 if (!possible_crtc->enabled) {
6670 crtc = possible_crtc;
6671 break;
6672 }
6673 }
6674
6675 /*
6676 * If we didn't find an unused CRTC, don't use any.
6677 */
6678 if (!crtc) {
6679 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6680 return false;
6681 }
6682
6683 mutex_lock(&crtc->mutex);
6684 intel_encoder->new_crtc = to_intel_crtc(crtc);
6685 to_intel_connector(connector)->new_encoder = intel_encoder;
6686
6687 intel_crtc = to_intel_crtc(crtc);
6688 old->dpms_mode = connector->dpms;
6689 old->load_detect_temp = true;
6690 old->release_fb = NULL;
6691
6692 if (!mode)
6693 mode = &load_detect_mode;
6694
6695 /* We need a framebuffer large enough to accommodate all accesses
6696 * that the plane may generate whilst we perform load detection.
6697 * We can not rely on the fbcon either being present (we get called
6698 * during its initialisation to detect all boot displays, or it may
6699 * not even exist) or that it is large enough to satisfy the
6700 * requested mode.
6701 */
6702 fb = mode_fits_in_fbdev(dev, mode);
6703 if (fb == NULL) {
6704 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6705 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6706 old->release_fb = fb;
6707 } else
6708 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6709 if (IS_ERR(fb)) {
6710 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6711 mutex_unlock(&crtc->mutex);
6712 return false;
6713 }
6714
6715 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6716 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6717 if (old->release_fb)
6718 old->release_fb->funcs->destroy(old->release_fb);
6719 mutex_unlock(&crtc->mutex);
6720 return false;
6721 }
6722
6723 /* let the connector get through one full cycle before testing */
6724 intel_wait_for_vblank(dev, intel_crtc->pipe);
6725 return true;
6726 }
6727
6728 void intel_release_load_detect_pipe(struct drm_connector *connector,
6729 struct intel_load_detect_pipe *old)
6730 {
6731 struct intel_encoder *intel_encoder =
6732 intel_attached_encoder(connector);
6733 struct drm_encoder *encoder = &intel_encoder->base;
6734 struct drm_crtc *crtc = encoder->crtc;
6735
6736 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6737 connector->base.id, drm_get_connector_name(connector),
6738 encoder->base.id, drm_get_encoder_name(encoder));
6739
6740 if (old->load_detect_temp) {
6741 to_intel_connector(connector)->new_encoder = NULL;
6742 intel_encoder->new_crtc = NULL;
6743 intel_set_mode(crtc, NULL, 0, 0, NULL);
6744
6745 if (old->release_fb) {
6746 drm_framebuffer_unregister_private(old->release_fb);
6747 drm_framebuffer_unreference(old->release_fb);
6748 }
6749
6750 mutex_unlock(&crtc->mutex);
6751 return;
6752 }
6753
6754 /* Switch crtc and encoder back off if necessary */
6755 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6756 connector->funcs->dpms(connector, old->dpms_mode);
6757
6758 mutex_unlock(&crtc->mutex);
6759 }
6760
6761 /* Returns the clock of the currently programmed mode of the given pipe. */
6762 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6763 {
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6766 int pipe = intel_crtc->pipe;
6767 u32 dpll = I915_READ(DPLL(pipe));
6768 u32 fp;
6769 intel_clock_t clock;
6770
6771 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6772 fp = I915_READ(FP0(pipe));
6773 else
6774 fp = I915_READ(FP1(pipe));
6775
6776 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6777 if (IS_PINEVIEW(dev)) {
6778 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6779 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6780 } else {
6781 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6782 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6783 }
6784
6785 if (!IS_GEN2(dev)) {
6786 if (IS_PINEVIEW(dev))
6787 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6788 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6789 else
6790 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6791 DPLL_FPA01_P1_POST_DIV_SHIFT);
6792
6793 switch (dpll & DPLL_MODE_MASK) {
6794 case DPLLB_MODE_DAC_SERIAL:
6795 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6796 5 : 10;
6797 break;
6798 case DPLLB_MODE_LVDS:
6799 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6800 7 : 14;
6801 break;
6802 default:
6803 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6804 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6805 return 0;
6806 }
6807
6808 /* XXX: Handle the 100Mhz refclk */
6809 intel_clock(dev, 96000, &clock);
6810 } else {
6811 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6812
6813 if (is_lvds) {
6814 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6815 DPLL_FPA01_P1_POST_DIV_SHIFT);
6816 clock.p2 = 14;
6817
6818 if ((dpll & PLL_REF_INPUT_MASK) ==
6819 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6820 /* XXX: might not be 66MHz */
6821 intel_clock(dev, 66000, &clock);
6822 } else
6823 intel_clock(dev, 48000, &clock);
6824 } else {
6825 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6826 clock.p1 = 2;
6827 else {
6828 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6829 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6830 }
6831 if (dpll & PLL_P2_DIVIDE_BY_4)
6832 clock.p2 = 4;
6833 else
6834 clock.p2 = 2;
6835
6836 intel_clock(dev, 48000, &clock);
6837 }
6838 }
6839
6840 /* XXX: It would be nice to validate the clocks, but we can't reuse
6841 * i830PllIsValid() because it relies on the xf86_config connector
6842 * configuration being accurate, which it isn't necessarily.
6843 */
6844
6845 return clock.dot;
6846 }
6847
6848 /** Returns the currently programmed mode of the given pipe. */
6849 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6850 struct drm_crtc *crtc)
6851 {
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6854 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6855 struct drm_display_mode *mode;
6856 int htot = I915_READ(HTOTAL(cpu_transcoder));
6857 int hsync = I915_READ(HSYNC(cpu_transcoder));
6858 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6859 int vsync = I915_READ(VSYNC(cpu_transcoder));
6860
6861 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6862 if (!mode)
6863 return NULL;
6864
6865 mode->clock = intel_crtc_clock_get(dev, crtc);
6866 mode->hdisplay = (htot & 0xffff) + 1;
6867 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6868 mode->hsync_start = (hsync & 0xffff) + 1;
6869 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6870 mode->vdisplay = (vtot & 0xffff) + 1;
6871 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6872 mode->vsync_start = (vsync & 0xffff) + 1;
6873 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6874
6875 drm_mode_set_name(mode);
6876
6877 return mode;
6878 }
6879
6880 static void intel_increase_pllclock(struct drm_crtc *crtc)
6881 {
6882 struct drm_device *dev = crtc->dev;
6883 drm_i915_private_t *dev_priv = dev->dev_private;
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 int pipe = intel_crtc->pipe;
6886 int dpll_reg = DPLL(pipe);
6887 int dpll;
6888
6889 if (HAS_PCH_SPLIT(dev))
6890 return;
6891
6892 if (!dev_priv->lvds_downclock_avail)
6893 return;
6894
6895 dpll = I915_READ(dpll_reg);
6896 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6897 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6898
6899 assert_panel_unlocked(dev_priv, pipe);
6900
6901 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6902 I915_WRITE(dpll_reg, dpll);
6903 intel_wait_for_vblank(dev, pipe);
6904
6905 dpll = I915_READ(dpll_reg);
6906 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6907 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6908 }
6909 }
6910
6911 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6912 {
6913 struct drm_device *dev = crtc->dev;
6914 drm_i915_private_t *dev_priv = dev->dev_private;
6915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916
6917 if (HAS_PCH_SPLIT(dev))
6918 return;
6919
6920 if (!dev_priv->lvds_downclock_avail)
6921 return;
6922
6923 /*
6924 * Since this is called by a timer, we should never get here in
6925 * the manual case.
6926 */
6927 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6928 int pipe = intel_crtc->pipe;
6929 int dpll_reg = DPLL(pipe);
6930 int dpll;
6931
6932 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6933
6934 assert_panel_unlocked(dev_priv, pipe);
6935
6936 dpll = I915_READ(dpll_reg);
6937 dpll |= DISPLAY_RATE_SELECT_FPA1;
6938 I915_WRITE(dpll_reg, dpll);
6939 intel_wait_for_vblank(dev, pipe);
6940 dpll = I915_READ(dpll_reg);
6941 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6942 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6943 }
6944
6945 }
6946
6947 void intel_mark_busy(struct drm_device *dev)
6948 {
6949 i915_update_gfx_val(dev->dev_private);
6950 }
6951
6952 void intel_mark_idle(struct drm_device *dev)
6953 {
6954 struct drm_crtc *crtc;
6955
6956 if (!i915_powersave)
6957 return;
6958
6959 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6960 if (!crtc->fb)
6961 continue;
6962
6963 intel_decrease_pllclock(crtc);
6964 }
6965 }
6966
6967 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6968 {
6969 struct drm_device *dev = obj->base.dev;
6970 struct drm_crtc *crtc;
6971
6972 if (!i915_powersave)
6973 return;
6974
6975 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6976 if (!crtc->fb)
6977 continue;
6978
6979 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6980 intel_increase_pllclock(crtc);
6981 }
6982 }
6983
6984 static void intel_crtc_destroy(struct drm_crtc *crtc)
6985 {
6986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6987 struct drm_device *dev = crtc->dev;
6988 struct intel_unpin_work *work;
6989 unsigned long flags;
6990
6991 spin_lock_irqsave(&dev->event_lock, flags);
6992 work = intel_crtc->unpin_work;
6993 intel_crtc->unpin_work = NULL;
6994 spin_unlock_irqrestore(&dev->event_lock, flags);
6995
6996 if (work) {
6997 cancel_work_sync(&work->work);
6998 kfree(work);
6999 }
7000
7001 drm_crtc_cleanup(crtc);
7002
7003 kfree(intel_crtc);
7004 }
7005
7006 static void intel_unpin_work_fn(struct work_struct *__work)
7007 {
7008 struct intel_unpin_work *work =
7009 container_of(__work, struct intel_unpin_work, work);
7010 struct drm_device *dev = work->crtc->dev;
7011
7012 mutex_lock(&dev->struct_mutex);
7013 intel_unpin_fb_obj(work->old_fb_obj);
7014 drm_gem_object_unreference(&work->pending_flip_obj->base);
7015 drm_gem_object_unreference(&work->old_fb_obj->base);
7016
7017 intel_update_fbc(dev);
7018 mutex_unlock(&dev->struct_mutex);
7019
7020 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7021 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7022
7023 kfree(work);
7024 }
7025
7026 static void do_intel_finish_page_flip(struct drm_device *dev,
7027 struct drm_crtc *crtc)
7028 {
7029 drm_i915_private_t *dev_priv = dev->dev_private;
7030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7031 struct intel_unpin_work *work;
7032 unsigned long flags;
7033
7034 /* Ignore early vblank irqs */
7035 if (intel_crtc == NULL)
7036 return;
7037
7038 spin_lock_irqsave(&dev->event_lock, flags);
7039 work = intel_crtc->unpin_work;
7040
7041 /* Ensure we don't miss a work->pending update ... */
7042 smp_rmb();
7043
7044 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7045 spin_unlock_irqrestore(&dev->event_lock, flags);
7046 return;
7047 }
7048
7049 /* and that the unpin work is consistent wrt ->pending. */
7050 smp_rmb();
7051
7052 intel_crtc->unpin_work = NULL;
7053
7054 if (work->event)
7055 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7056
7057 drm_vblank_put(dev, intel_crtc->pipe);
7058
7059 spin_unlock_irqrestore(&dev->event_lock, flags);
7060
7061 wake_up_all(&dev_priv->pending_flip_queue);
7062
7063 queue_work(dev_priv->wq, &work->work);
7064
7065 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7066 }
7067
7068 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7069 {
7070 drm_i915_private_t *dev_priv = dev->dev_private;
7071 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7072
7073 do_intel_finish_page_flip(dev, crtc);
7074 }
7075
7076 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7077 {
7078 drm_i915_private_t *dev_priv = dev->dev_private;
7079 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7080
7081 do_intel_finish_page_flip(dev, crtc);
7082 }
7083
7084 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7085 {
7086 drm_i915_private_t *dev_priv = dev->dev_private;
7087 struct intel_crtc *intel_crtc =
7088 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7089 unsigned long flags;
7090
7091 /* NB: An MMIO update of the plane base pointer will also
7092 * generate a page-flip completion irq, i.e. every modeset
7093 * is also accompanied by a spurious intel_prepare_page_flip().
7094 */
7095 spin_lock_irqsave(&dev->event_lock, flags);
7096 if (intel_crtc->unpin_work)
7097 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7098 spin_unlock_irqrestore(&dev->event_lock, flags);
7099 }
7100
7101 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7102 {
7103 /* Ensure that the work item is consistent when activating it ... */
7104 smp_wmb();
7105 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7106 /* and that it is marked active as soon as the irq could fire. */
7107 smp_wmb();
7108 }
7109
7110 static int intel_gen2_queue_flip(struct drm_device *dev,
7111 struct drm_crtc *crtc,
7112 struct drm_framebuffer *fb,
7113 struct drm_i915_gem_object *obj)
7114 {
7115 struct drm_i915_private *dev_priv = dev->dev_private;
7116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7117 u32 flip_mask;
7118 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7119 int ret;
7120
7121 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7122 if (ret)
7123 goto err;
7124
7125 ret = intel_ring_begin(ring, 6);
7126 if (ret)
7127 goto err_unpin;
7128
7129 /* Can't queue multiple flips, so wait for the previous
7130 * one to finish before executing the next.
7131 */
7132 if (intel_crtc->plane)
7133 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7134 else
7135 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7136 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7137 intel_ring_emit(ring, MI_NOOP);
7138 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7139 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7140 intel_ring_emit(ring, fb->pitches[0]);
7141 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7142 intel_ring_emit(ring, 0); /* aux display base address, unused */
7143
7144 intel_mark_page_flip_active(intel_crtc);
7145 intel_ring_advance(ring);
7146 return 0;
7147
7148 err_unpin:
7149 intel_unpin_fb_obj(obj);
7150 err:
7151 return ret;
7152 }
7153
7154 static int intel_gen3_queue_flip(struct drm_device *dev,
7155 struct drm_crtc *crtc,
7156 struct drm_framebuffer *fb,
7157 struct drm_i915_gem_object *obj)
7158 {
7159 struct drm_i915_private *dev_priv = dev->dev_private;
7160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7161 u32 flip_mask;
7162 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7163 int ret;
7164
7165 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7166 if (ret)
7167 goto err;
7168
7169 ret = intel_ring_begin(ring, 6);
7170 if (ret)
7171 goto err_unpin;
7172
7173 if (intel_crtc->plane)
7174 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7175 else
7176 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7177 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7178 intel_ring_emit(ring, MI_NOOP);
7179 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7180 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7181 intel_ring_emit(ring, fb->pitches[0]);
7182 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7183 intel_ring_emit(ring, MI_NOOP);
7184
7185 intel_mark_page_flip_active(intel_crtc);
7186 intel_ring_advance(ring);
7187 return 0;
7188
7189 err_unpin:
7190 intel_unpin_fb_obj(obj);
7191 err:
7192 return ret;
7193 }
7194
7195 static int intel_gen4_queue_flip(struct drm_device *dev,
7196 struct drm_crtc *crtc,
7197 struct drm_framebuffer *fb,
7198 struct drm_i915_gem_object *obj)
7199 {
7200 struct drm_i915_private *dev_priv = dev->dev_private;
7201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7202 uint32_t pf, pipesrc;
7203 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7204 int ret;
7205
7206 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7207 if (ret)
7208 goto err;
7209
7210 ret = intel_ring_begin(ring, 4);
7211 if (ret)
7212 goto err_unpin;
7213
7214 /* i965+ uses the linear or tiled offsets from the
7215 * Display Registers (which do not change across a page-flip)
7216 * so we need only reprogram the base address.
7217 */
7218 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7219 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7220 intel_ring_emit(ring, fb->pitches[0]);
7221 intel_ring_emit(ring,
7222 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7223 obj->tiling_mode);
7224
7225 /* XXX Enabling the panel-fitter across page-flip is so far
7226 * untested on non-native modes, so ignore it for now.
7227 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7228 */
7229 pf = 0;
7230 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7231 intel_ring_emit(ring, pf | pipesrc);
7232
7233 intel_mark_page_flip_active(intel_crtc);
7234 intel_ring_advance(ring);
7235 return 0;
7236
7237 err_unpin:
7238 intel_unpin_fb_obj(obj);
7239 err:
7240 return ret;
7241 }
7242
7243 static int intel_gen6_queue_flip(struct drm_device *dev,
7244 struct drm_crtc *crtc,
7245 struct drm_framebuffer *fb,
7246 struct drm_i915_gem_object *obj)
7247 {
7248 struct drm_i915_private *dev_priv = dev->dev_private;
7249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7250 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7251 uint32_t pf, pipesrc;
7252 int ret;
7253
7254 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7255 if (ret)
7256 goto err;
7257
7258 ret = intel_ring_begin(ring, 4);
7259 if (ret)
7260 goto err_unpin;
7261
7262 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7263 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7264 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7265 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7266
7267 /* Contrary to the suggestions in the documentation,
7268 * "Enable Panel Fitter" does not seem to be required when page
7269 * flipping with a non-native mode, and worse causes a normal
7270 * modeset to fail.
7271 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7272 */
7273 pf = 0;
7274 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7275 intel_ring_emit(ring, pf | pipesrc);
7276
7277 intel_mark_page_flip_active(intel_crtc);
7278 intel_ring_advance(ring);
7279 return 0;
7280
7281 err_unpin:
7282 intel_unpin_fb_obj(obj);
7283 err:
7284 return ret;
7285 }
7286
7287 /*
7288 * On gen7 we currently use the blit ring because (in early silicon at least)
7289 * the render ring doesn't give us interrpts for page flip completion, which
7290 * means clients will hang after the first flip is queued. Fortunately the
7291 * blit ring generates interrupts properly, so use it instead.
7292 */
7293 static int intel_gen7_queue_flip(struct drm_device *dev,
7294 struct drm_crtc *crtc,
7295 struct drm_framebuffer *fb,
7296 struct drm_i915_gem_object *obj)
7297 {
7298 struct drm_i915_private *dev_priv = dev->dev_private;
7299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7300 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7301 uint32_t plane_bit = 0;
7302 int ret;
7303
7304 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7305 if (ret)
7306 goto err;
7307
7308 switch(intel_crtc->plane) {
7309 case PLANE_A:
7310 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7311 break;
7312 case PLANE_B:
7313 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7314 break;
7315 case PLANE_C:
7316 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7317 break;
7318 default:
7319 WARN_ONCE(1, "unknown plane in flip command\n");
7320 ret = -ENODEV;
7321 goto err_unpin;
7322 }
7323
7324 ret = intel_ring_begin(ring, 4);
7325 if (ret)
7326 goto err_unpin;
7327
7328 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7329 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7330 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7331 intel_ring_emit(ring, (MI_NOOP));
7332
7333 intel_mark_page_flip_active(intel_crtc);
7334 intel_ring_advance(ring);
7335 return 0;
7336
7337 err_unpin:
7338 intel_unpin_fb_obj(obj);
7339 err:
7340 return ret;
7341 }
7342
7343 static int intel_default_queue_flip(struct drm_device *dev,
7344 struct drm_crtc *crtc,
7345 struct drm_framebuffer *fb,
7346 struct drm_i915_gem_object *obj)
7347 {
7348 return -ENODEV;
7349 }
7350
7351 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7352 struct drm_framebuffer *fb,
7353 struct drm_pending_vblank_event *event)
7354 {
7355 struct drm_device *dev = crtc->dev;
7356 struct drm_i915_private *dev_priv = dev->dev_private;
7357 struct drm_framebuffer *old_fb = crtc->fb;
7358 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7360 struct intel_unpin_work *work;
7361 unsigned long flags;
7362 int ret;
7363
7364 /* Can't change pixel format via MI display flips. */
7365 if (fb->pixel_format != crtc->fb->pixel_format)
7366 return -EINVAL;
7367
7368 /*
7369 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7370 * Note that pitch changes could also affect these register.
7371 */
7372 if (INTEL_INFO(dev)->gen > 3 &&
7373 (fb->offsets[0] != crtc->fb->offsets[0] ||
7374 fb->pitches[0] != crtc->fb->pitches[0]))
7375 return -EINVAL;
7376
7377 work = kzalloc(sizeof *work, GFP_KERNEL);
7378 if (work == NULL)
7379 return -ENOMEM;
7380
7381 work->event = event;
7382 work->crtc = crtc;
7383 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7384 INIT_WORK(&work->work, intel_unpin_work_fn);
7385
7386 ret = drm_vblank_get(dev, intel_crtc->pipe);
7387 if (ret)
7388 goto free_work;
7389
7390 /* We borrow the event spin lock for protecting unpin_work */
7391 spin_lock_irqsave(&dev->event_lock, flags);
7392 if (intel_crtc->unpin_work) {
7393 spin_unlock_irqrestore(&dev->event_lock, flags);
7394 kfree(work);
7395 drm_vblank_put(dev, intel_crtc->pipe);
7396
7397 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7398 return -EBUSY;
7399 }
7400 intel_crtc->unpin_work = work;
7401 spin_unlock_irqrestore(&dev->event_lock, flags);
7402
7403 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7404 flush_workqueue(dev_priv->wq);
7405
7406 ret = i915_mutex_lock_interruptible(dev);
7407 if (ret)
7408 goto cleanup;
7409
7410 /* Reference the objects for the scheduled work. */
7411 drm_gem_object_reference(&work->old_fb_obj->base);
7412 drm_gem_object_reference(&obj->base);
7413
7414 crtc->fb = fb;
7415
7416 work->pending_flip_obj = obj;
7417
7418 work->enable_stall_check = true;
7419
7420 atomic_inc(&intel_crtc->unpin_work_count);
7421 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7422
7423 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7424 if (ret)
7425 goto cleanup_pending;
7426
7427 intel_disable_fbc(dev);
7428 intel_mark_fb_busy(obj);
7429 mutex_unlock(&dev->struct_mutex);
7430
7431 trace_i915_flip_request(intel_crtc->plane, obj);
7432
7433 return 0;
7434
7435 cleanup_pending:
7436 atomic_dec(&intel_crtc->unpin_work_count);
7437 crtc->fb = old_fb;
7438 drm_gem_object_unreference(&work->old_fb_obj->base);
7439 drm_gem_object_unreference(&obj->base);
7440 mutex_unlock(&dev->struct_mutex);
7441
7442 cleanup:
7443 spin_lock_irqsave(&dev->event_lock, flags);
7444 intel_crtc->unpin_work = NULL;
7445 spin_unlock_irqrestore(&dev->event_lock, flags);
7446
7447 drm_vblank_put(dev, intel_crtc->pipe);
7448 free_work:
7449 kfree(work);
7450
7451 return ret;
7452 }
7453
7454 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7455 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7456 .load_lut = intel_crtc_load_lut,
7457 };
7458
7459 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7460 {
7461 struct intel_encoder *other_encoder;
7462 struct drm_crtc *crtc = &encoder->new_crtc->base;
7463
7464 if (WARN_ON(!crtc))
7465 return false;
7466
7467 list_for_each_entry(other_encoder,
7468 &crtc->dev->mode_config.encoder_list,
7469 base.head) {
7470
7471 if (&other_encoder->new_crtc->base != crtc ||
7472 encoder == other_encoder)
7473 continue;
7474 else
7475 return true;
7476 }
7477
7478 return false;
7479 }
7480
7481 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7482 struct drm_crtc *crtc)
7483 {
7484 struct drm_device *dev;
7485 struct drm_crtc *tmp;
7486 int crtc_mask = 1;
7487
7488 WARN(!crtc, "checking null crtc?\n");
7489
7490 dev = crtc->dev;
7491
7492 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7493 if (tmp == crtc)
7494 break;
7495 crtc_mask <<= 1;
7496 }
7497
7498 if (encoder->possible_crtcs & crtc_mask)
7499 return true;
7500 return false;
7501 }
7502
7503 /**
7504 * intel_modeset_update_staged_output_state
7505 *
7506 * Updates the staged output configuration state, e.g. after we've read out the
7507 * current hw state.
7508 */
7509 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7510 {
7511 struct intel_encoder *encoder;
7512 struct intel_connector *connector;
7513
7514 list_for_each_entry(connector, &dev->mode_config.connector_list,
7515 base.head) {
7516 connector->new_encoder =
7517 to_intel_encoder(connector->base.encoder);
7518 }
7519
7520 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7521 base.head) {
7522 encoder->new_crtc =
7523 to_intel_crtc(encoder->base.crtc);
7524 }
7525 }
7526
7527 /**
7528 * intel_modeset_commit_output_state
7529 *
7530 * This function copies the stage display pipe configuration to the real one.
7531 */
7532 static void intel_modeset_commit_output_state(struct drm_device *dev)
7533 {
7534 struct intel_encoder *encoder;
7535 struct intel_connector *connector;
7536
7537 list_for_each_entry(connector, &dev->mode_config.connector_list,
7538 base.head) {
7539 connector->base.encoder = &connector->new_encoder->base;
7540 }
7541
7542 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7543 base.head) {
7544 encoder->base.crtc = &encoder->new_crtc->base;
7545 }
7546 }
7547
7548 static int
7549 pipe_config_set_bpp(struct drm_crtc *crtc,
7550 struct drm_framebuffer *fb,
7551 struct intel_crtc_config *pipe_config)
7552 {
7553 struct drm_device *dev = crtc->dev;
7554 struct drm_connector *connector;
7555 int bpp;
7556
7557 switch (fb->pixel_format) {
7558 case DRM_FORMAT_C8:
7559 bpp = 8*3; /* since we go through a colormap */
7560 break;
7561 case DRM_FORMAT_XRGB1555:
7562 case DRM_FORMAT_ARGB1555:
7563 /* checked in intel_framebuffer_init already */
7564 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7565 return -EINVAL;
7566 case DRM_FORMAT_RGB565:
7567 bpp = 6*3; /* min is 18bpp */
7568 break;
7569 case DRM_FORMAT_XBGR8888:
7570 case DRM_FORMAT_ABGR8888:
7571 /* checked in intel_framebuffer_init already */
7572 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7573 return -EINVAL;
7574 case DRM_FORMAT_XRGB8888:
7575 case DRM_FORMAT_ARGB8888:
7576 bpp = 8*3;
7577 break;
7578 case DRM_FORMAT_XRGB2101010:
7579 case DRM_FORMAT_ARGB2101010:
7580 case DRM_FORMAT_XBGR2101010:
7581 case DRM_FORMAT_ABGR2101010:
7582 /* checked in intel_framebuffer_init already */
7583 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7584 return -EINVAL;
7585 bpp = 10*3;
7586 break;
7587 /* TODO: gen4+ supports 16 bpc floating point, too. */
7588 default:
7589 DRM_DEBUG_KMS("unsupported depth\n");
7590 return -EINVAL;
7591 }
7592
7593 pipe_config->pipe_bpp = bpp;
7594
7595 /* Clamp display bpp to EDID value */
7596 list_for_each_entry(connector, &dev->mode_config.connector_list,
7597 head) {
7598 if (connector->encoder && connector->encoder->crtc != crtc)
7599 continue;
7600
7601 /* Don't use an invalid EDID bpc value */
7602 if (connector->display_info.bpc &&
7603 connector->display_info.bpc * 3 < bpp) {
7604 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7605 bpp, connector->display_info.bpc*3);
7606 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7607 }
7608
7609 /* Clamp bpp to 8 on screens without EDID 1.4 */
7610 if (connector->display_info.bpc == 0 && bpp > 24) {
7611 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7612 bpp);
7613 pipe_config->pipe_bpp = 24;
7614 }
7615 }
7616
7617 return bpp;
7618 }
7619
7620 static struct intel_crtc_config *
7621 intel_modeset_pipe_config(struct drm_crtc *crtc,
7622 struct drm_framebuffer *fb,
7623 struct drm_display_mode *mode)
7624 {
7625 struct drm_device *dev = crtc->dev;
7626 struct drm_encoder_helper_funcs *encoder_funcs;
7627 struct intel_encoder *encoder;
7628 struct intel_crtc_config *pipe_config;
7629 int plane_bpp;
7630
7631 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7632 if (!pipe_config)
7633 return ERR_PTR(-ENOMEM);
7634
7635 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7636 drm_mode_copy(&pipe_config->requested_mode, mode);
7637
7638 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7639 if (plane_bpp < 0)
7640 goto fail;
7641
7642 /* Pass our mode to the connectors and the CRTC to give them a chance to
7643 * adjust it according to limitations or connector properties, and also
7644 * a chance to reject the mode entirely.
7645 */
7646 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7647 base.head) {
7648
7649 if (&encoder->new_crtc->base != crtc)
7650 continue;
7651
7652 if (encoder->compute_config) {
7653 if (!(encoder->compute_config(encoder, pipe_config))) {
7654 DRM_DEBUG_KMS("Encoder config failure\n");
7655 goto fail;
7656 }
7657
7658 continue;
7659 }
7660
7661 encoder_funcs = encoder->base.helper_private;
7662 if (!(encoder_funcs->mode_fixup(&encoder->base,
7663 &pipe_config->requested_mode,
7664 &pipe_config->adjusted_mode))) {
7665 DRM_DEBUG_KMS("Encoder fixup failed\n");
7666 goto fail;
7667 }
7668 }
7669
7670 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7671 DRM_DEBUG_KMS("CRTC fixup failed\n");
7672 goto fail;
7673 }
7674 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7675
7676 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7677 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7678 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7679
7680 return pipe_config;
7681 fail:
7682 kfree(pipe_config);
7683 return ERR_PTR(-EINVAL);
7684 }
7685
7686 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7687 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7688 static void
7689 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7690 unsigned *prepare_pipes, unsigned *disable_pipes)
7691 {
7692 struct intel_crtc *intel_crtc;
7693 struct drm_device *dev = crtc->dev;
7694 struct intel_encoder *encoder;
7695 struct intel_connector *connector;
7696 struct drm_crtc *tmp_crtc;
7697
7698 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7699
7700 /* Check which crtcs have changed outputs connected to them, these need
7701 * to be part of the prepare_pipes mask. We don't (yet) support global
7702 * modeset across multiple crtcs, so modeset_pipes will only have one
7703 * bit set at most. */
7704 list_for_each_entry(connector, &dev->mode_config.connector_list,
7705 base.head) {
7706 if (connector->base.encoder == &connector->new_encoder->base)
7707 continue;
7708
7709 if (connector->base.encoder) {
7710 tmp_crtc = connector->base.encoder->crtc;
7711
7712 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7713 }
7714
7715 if (connector->new_encoder)
7716 *prepare_pipes |=
7717 1 << connector->new_encoder->new_crtc->pipe;
7718 }
7719
7720 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7721 base.head) {
7722 if (encoder->base.crtc == &encoder->new_crtc->base)
7723 continue;
7724
7725 if (encoder->base.crtc) {
7726 tmp_crtc = encoder->base.crtc;
7727
7728 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7729 }
7730
7731 if (encoder->new_crtc)
7732 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7733 }
7734
7735 /* Check for any pipes that will be fully disabled ... */
7736 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7737 base.head) {
7738 bool used = false;
7739
7740 /* Don't try to disable disabled crtcs. */
7741 if (!intel_crtc->base.enabled)
7742 continue;
7743
7744 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7745 base.head) {
7746 if (encoder->new_crtc == intel_crtc)
7747 used = true;
7748 }
7749
7750 if (!used)
7751 *disable_pipes |= 1 << intel_crtc->pipe;
7752 }
7753
7754
7755 /* set_mode is also used to update properties on life display pipes. */
7756 intel_crtc = to_intel_crtc(crtc);
7757 if (crtc->enabled)
7758 *prepare_pipes |= 1 << intel_crtc->pipe;
7759
7760 /*
7761 * For simplicity do a full modeset on any pipe where the output routing
7762 * changed. We could be more clever, but that would require us to be
7763 * more careful with calling the relevant encoder->mode_set functions.
7764 */
7765 if (*prepare_pipes)
7766 *modeset_pipes = *prepare_pipes;
7767
7768 /* ... and mask these out. */
7769 *modeset_pipes &= ~(*disable_pipes);
7770 *prepare_pipes &= ~(*disable_pipes);
7771
7772 /*
7773 * HACK: We don't (yet) fully support global modesets. intel_set_config
7774 * obies this rule, but the modeset restore mode of
7775 * intel_modeset_setup_hw_state does not.
7776 */
7777 *modeset_pipes &= 1 << intel_crtc->pipe;
7778 *prepare_pipes &= 1 << intel_crtc->pipe;
7779
7780 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7781 *modeset_pipes, *prepare_pipes, *disable_pipes);
7782 }
7783
7784 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7785 {
7786 struct drm_encoder *encoder;
7787 struct drm_device *dev = crtc->dev;
7788
7789 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7790 if (encoder->crtc == crtc)
7791 return true;
7792
7793 return false;
7794 }
7795
7796 static void
7797 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7798 {
7799 struct intel_encoder *intel_encoder;
7800 struct intel_crtc *intel_crtc;
7801 struct drm_connector *connector;
7802
7803 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7804 base.head) {
7805 if (!intel_encoder->base.crtc)
7806 continue;
7807
7808 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7809
7810 if (prepare_pipes & (1 << intel_crtc->pipe))
7811 intel_encoder->connectors_active = false;
7812 }
7813
7814 intel_modeset_commit_output_state(dev);
7815
7816 /* Update computed state. */
7817 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7818 base.head) {
7819 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7820 }
7821
7822 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7823 if (!connector->encoder || !connector->encoder->crtc)
7824 continue;
7825
7826 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7827
7828 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7829 struct drm_property *dpms_property =
7830 dev->mode_config.dpms_property;
7831
7832 connector->dpms = DRM_MODE_DPMS_ON;
7833 drm_object_property_set_value(&connector->base,
7834 dpms_property,
7835 DRM_MODE_DPMS_ON);
7836
7837 intel_encoder = to_intel_encoder(connector->encoder);
7838 intel_encoder->connectors_active = true;
7839 }
7840 }
7841
7842 }
7843
7844 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7845 list_for_each_entry((intel_crtc), \
7846 &(dev)->mode_config.crtc_list, \
7847 base.head) \
7848 if (mask & (1 <<(intel_crtc)->pipe)) \
7849
7850 static bool
7851 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7852 struct intel_crtc_config *pipe_config)
7853 {
7854 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7855 DRM_ERROR("mismatch in has_pch_encoder "
7856 "(expected %i, found %i)\n",
7857 current_config->has_pch_encoder,
7858 pipe_config->has_pch_encoder);
7859 return false;
7860 }
7861
7862 return true;
7863 }
7864
7865 void
7866 intel_modeset_check_state(struct drm_device *dev)
7867 {
7868 drm_i915_private_t *dev_priv = dev->dev_private;
7869 struct intel_crtc *crtc;
7870 struct intel_encoder *encoder;
7871 struct intel_connector *connector;
7872 struct intel_crtc_config pipe_config;
7873
7874 list_for_each_entry(connector, &dev->mode_config.connector_list,
7875 base.head) {
7876 /* This also checks the encoder/connector hw state with the
7877 * ->get_hw_state callbacks. */
7878 intel_connector_check_state(connector);
7879
7880 WARN(&connector->new_encoder->base != connector->base.encoder,
7881 "connector's staged encoder doesn't match current encoder\n");
7882 }
7883
7884 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7885 base.head) {
7886 bool enabled = false;
7887 bool active = false;
7888 enum pipe pipe, tracked_pipe;
7889
7890 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7891 encoder->base.base.id,
7892 drm_get_encoder_name(&encoder->base));
7893
7894 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7895 "encoder's stage crtc doesn't match current crtc\n");
7896 WARN(encoder->connectors_active && !encoder->base.crtc,
7897 "encoder's active_connectors set, but no crtc\n");
7898
7899 list_for_each_entry(connector, &dev->mode_config.connector_list,
7900 base.head) {
7901 if (connector->base.encoder != &encoder->base)
7902 continue;
7903 enabled = true;
7904 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7905 active = true;
7906 }
7907 WARN(!!encoder->base.crtc != enabled,
7908 "encoder's enabled state mismatch "
7909 "(expected %i, found %i)\n",
7910 !!encoder->base.crtc, enabled);
7911 WARN(active && !encoder->base.crtc,
7912 "active encoder with no crtc\n");
7913
7914 WARN(encoder->connectors_active != active,
7915 "encoder's computed active state doesn't match tracked active state "
7916 "(expected %i, found %i)\n", active, encoder->connectors_active);
7917
7918 active = encoder->get_hw_state(encoder, &pipe);
7919 WARN(active != encoder->connectors_active,
7920 "encoder's hw state doesn't match sw tracking "
7921 "(expected %i, found %i)\n",
7922 encoder->connectors_active, active);
7923
7924 if (!encoder->base.crtc)
7925 continue;
7926
7927 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7928 WARN(active && pipe != tracked_pipe,
7929 "active encoder's pipe doesn't match"
7930 "(expected %i, found %i)\n",
7931 tracked_pipe, pipe);
7932
7933 }
7934
7935 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7936 base.head) {
7937 bool enabled = false;
7938 bool active = false;
7939
7940 DRM_DEBUG_KMS("[CRTC:%d]\n",
7941 crtc->base.base.id);
7942
7943 WARN(crtc->active && !crtc->base.enabled,
7944 "active crtc, but not enabled in sw tracking\n");
7945
7946 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7947 base.head) {
7948 if (encoder->base.crtc != &crtc->base)
7949 continue;
7950 enabled = true;
7951 if (encoder->connectors_active)
7952 active = true;
7953 }
7954 WARN(active != crtc->active,
7955 "crtc's computed active state doesn't match tracked active state "
7956 "(expected %i, found %i)\n", active, crtc->active);
7957 WARN(enabled != crtc->base.enabled,
7958 "crtc's computed enabled state doesn't match tracked enabled state "
7959 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7960
7961 memset(&pipe_config, 0, sizeof(pipe_config));
7962 active = dev_priv->display.get_pipe_config(crtc,
7963 &pipe_config);
7964 WARN(crtc->active != active,
7965 "crtc active state doesn't match with hw state "
7966 "(expected %i, found %i)\n", crtc->active, active);
7967
7968 WARN(active &&
7969 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7970 "pipe state doesn't match!\n");
7971 }
7972 }
7973
7974 static int __intel_set_mode(struct drm_crtc *crtc,
7975 struct drm_display_mode *mode,
7976 int x, int y, struct drm_framebuffer *fb)
7977 {
7978 struct drm_device *dev = crtc->dev;
7979 drm_i915_private_t *dev_priv = dev->dev_private;
7980 struct drm_display_mode *saved_mode, *saved_hwmode;
7981 struct intel_crtc_config *pipe_config = NULL;
7982 struct intel_crtc *intel_crtc;
7983 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7984 int ret = 0;
7985
7986 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7987 if (!saved_mode)
7988 return -ENOMEM;
7989 saved_hwmode = saved_mode + 1;
7990
7991 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7992 &prepare_pipes, &disable_pipes);
7993
7994 *saved_hwmode = crtc->hwmode;
7995 *saved_mode = crtc->mode;
7996
7997 /* Hack: Because we don't (yet) support global modeset on multiple
7998 * crtcs, we don't keep track of the new mode for more than one crtc.
7999 * Hence simply check whether any bit is set in modeset_pipes in all the
8000 * pieces of code that are not yet converted to deal with mutliple crtcs
8001 * changing their mode at the same time. */
8002 if (modeset_pipes) {
8003 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8004 if (IS_ERR(pipe_config)) {
8005 ret = PTR_ERR(pipe_config);
8006 pipe_config = NULL;
8007
8008 goto out;
8009 }
8010 }
8011
8012 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8013 intel_crtc_disable(&intel_crtc->base);
8014
8015 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8016 if (intel_crtc->base.enabled)
8017 dev_priv->display.crtc_disable(&intel_crtc->base);
8018 }
8019
8020 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8021 * to set it here already despite that we pass it down the callchain.
8022 */
8023 if (modeset_pipes) {
8024 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8025 crtc->mode = *mode;
8026 /* mode_set/enable/disable functions rely on a correct pipe
8027 * config. */
8028 to_intel_crtc(crtc)->config = *pipe_config;
8029 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8030 }
8031
8032 /* Only after disabling all output pipelines that will be changed can we
8033 * update the the output configuration. */
8034 intel_modeset_update_state(dev, prepare_pipes);
8035
8036 if (dev_priv->display.modeset_global_resources)
8037 dev_priv->display.modeset_global_resources(dev);
8038
8039 /* Set up the DPLL and any encoders state that needs to adjust or depend
8040 * on the DPLL.
8041 */
8042 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8043 ret = intel_crtc_mode_set(&intel_crtc->base,
8044 x, y, fb);
8045 if (ret)
8046 goto done;
8047 }
8048
8049 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8050 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8051 dev_priv->display.crtc_enable(&intel_crtc->base);
8052
8053 if (modeset_pipes) {
8054 /* Store real post-adjustment hardware mode. */
8055 crtc->hwmode = pipe_config->adjusted_mode;
8056
8057 /* Calculate and store various constants which
8058 * are later needed by vblank and swap-completion
8059 * timestamping. They are derived from true hwmode.
8060 */
8061 drm_calc_timestamping_constants(crtc);
8062 }
8063
8064 /* FIXME: add subpixel order */
8065 done:
8066 if (ret && crtc->enabled) {
8067 crtc->hwmode = *saved_hwmode;
8068 crtc->mode = *saved_mode;
8069 }
8070
8071 out:
8072 kfree(pipe_config);
8073 kfree(saved_mode);
8074 return ret;
8075 }
8076
8077 int intel_set_mode(struct drm_crtc *crtc,
8078 struct drm_display_mode *mode,
8079 int x, int y, struct drm_framebuffer *fb)
8080 {
8081 int ret;
8082
8083 ret = __intel_set_mode(crtc, mode, x, y, fb);
8084
8085 if (ret == 0)
8086 intel_modeset_check_state(crtc->dev);
8087
8088 return ret;
8089 }
8090
8091 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8092 {
8093 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8094 }
8095
8096 #undef for_each_intel_crtc_masked
8097
8098 static void intel_set_config_free(struct intel_set_config *config)
8099 {
8100 if (!config)
8101 return;
8102
8103 kfree(config->save_connector_encoders);
8104 kfree(config->save_encoder_crtcs);
8105 kfree(config);
8106 }
8107
8108 static int intel_set_config_save_state(struct drm_device *dev,
8109 struct intel_set_config *config)
8110 {
8111 struct drm_encoder *encoder;
8112 struct drm_connector *connector;
8113 int count;
8114
8115 config->save_encoder_crtcs =
8116 kcalloc(dev->mode_config.num_encoder,
8117 sizeof(struct drm_crtc *), GFP_KERNEL);
8118 if (!config->save_encoder_crtcs)
8119 return -ENOMEM;
8120
8121 config->save_connector_encoders =
8122 kcalloc(dev->mode_config.num_connector,
8123 sizeof(struct drm_encoder *), GFP_KERNEL);
8124 if (!config->save_connector_encoders)
8125 return -ENOMEM;
8126
8127 /* Copy data. Note that driver private data is not affected.
8128 * Should anything bad happen only the expected state is
8129 * restored, not the drivers personal bookkeeping.
8130 */
8131 count = 0;
8132 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8133 config->save_encoder_crtcs[count++] = encoder->crtc;
8134 }
8135
8136 count = 0;
8137 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8138 config->save_connector_encoders[count++] = connector->encoder;
8139 }
8140
8141 return 0;
8142 }
8143
8144 static void intel_set_config_restore_state(struct drm_device *dev,
8145 struct intel_set_config *config)
8146 {
8147 struct intel_encoder *encoder;
8148 struct intel_connector *connector;
8149 int count;
8150
8151 count = 0;
8152 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8153 encoder->new_crtc =
8154 to_intel_crtc(config->save_encoder_crtcs[count++]);
8155 }
8156
8157 count = 0;
8158 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8159 connector->new_encoder =
8160 to_intel_encoder(config->save_connector_encoders[count++]);
8161 }
8162 }
8163
8164 static void
8165 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8166 struct intel_set_config *config)
8167 {
8168
8169 /* We should be able to check here if the fb has the same properties
8170 * and then just flip_or_move it */
8171 if (set->crtc->fb != set->fb) {
8172 /* If we have no fb then treat it as a full mode set */
8173 if (set->crtc->fb == NULL) {
8174 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8175 config->mode_changed = true;
8176 } else if (set->fb == NULL) {
8177 config->mode_changed = true;
8178 } else if (set->fb->pixel_format !=
8179 set->crtc->fb->pixel_format) {
8180 config->mode_changed = true;
8181 } else
8182 config->fb_changed = true;
8183 }
8184
8185 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8186 config->fb_changed = true;
8187
8188 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8189 DRM_DEBUG_KMS("modes are different, full mode set\n");
8190 drm_mode_debug_printmodeline(&set->crtc->mode);
8191 drm_mode_debug_printmodeline(set->mode);
8192 config->mode_changed = true;
8193 }
8194 }
8195
8196 static int
8197 intel_modeset_stage_output_state(struct drm_device *dev,
8198 struct drm_mode_set *set,
8199 struct intel_set_config *config)
8200 {
8201 struct drm_crtc *new_crtc;
8202 struct intel_connector *connector;
8203 struct intel_encoder *encoder;
8204 int count, ro;
8205
8206 /* The upper layers ensure that we either disable a crtc or have a list
8207 * of connectors. For paranoia, double-check this. */
8208 WARN_ON(!set->fb && (set->num_connectors != 0));
8209 WARN_ON(set->fb && (set->num_connectors == 0));
8210
8211 count = 0;
8212 list_for_each_entry(connector, &dev->mode_config.connector_list,
8213 base.head) {
8214 /* Otherwise traverse passed in connector list and get encoders
8215 * for them. */
8216 for (ro = 0; ro < set->num_connectors; ro++) {
8217 if (set->connectors[ro] == &connector->base) {
8218 connector->new_encoder = connector->encoder;
8219 break;
8220 }
8221 }
8222
8223 /* If we disable the crtc, disable all its connectors. Also, if
8224 * the connector is on the changing crtc but not on the new
8225 * connector list, disable it. */
8226 if ((!set->fb || ro == set->num_connectors) &&
8227 connector->base.encoder &&
8228 connector->base.encoder->crtc == set->crtc) {
8229 connector->new_encoder = NULL;
8230
8231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8232 connector->base.base.id,
8233 drm_get_connector_name(&connector->base));
8234 }
8235
8236
8237 if (&connector->new_encoder->base != connector->base.encoder) {
8238 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8239 config->mode_changed = true;
8240 }
8241 }
8242 /* connector->new_encoder is now updated for all connectors. */
8243
8244 /* Update crtc of enabled connectors. */
8245 count = 0;
8246 list_for_each_entry(connector, &dev->mode_config.connector_list,
8247 base.head) {
8248 if (!connector->new_encoder)
8249 continue;
8250
8251 new_crtc = connector->new_encoder->base.crtc;
8252
8253 for (ro = 0; ro < set->num_connectors; ro++) {
8254 if (set->connectors[ro] == &connector->base)
8255 new_crtc = set->crtc;
8256 }
8257
8258 /* Make sure the new CRTC will work with the encoder */
8259 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8260 new_crtc)) {
8261 return -EINVAL;
8262 }
8263 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8264
8265 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8266 connector->base.base.id,
8267 drm_get_connector_name(&connector->base),
8268 new_crtc->base.id);
8269 }
8270
8271 /* Check for any encoders that needs to be disabled. */
8272 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8273 base.head) {
8274 list_for_each_entry(connector,
8275 &dev->mode_config.connector_list,
8276 base.head) {
8277 if (connector->new_encoder == encoder) {
8278 WARN_ON(!connector->new_encoder->new_crtc);
8279
8280 goto next_encoder;
8281 }
8282 }
8283 encoder->new_crtc = NULL;
8284 next_encoder:
8285 /* Only now check for crtc changes so we don't miss encoders
8286 * that will be disabled. */
8287 if (&encoder->new_crtc->base != encoder->base.crtc) {
8288 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8289 config->mode_changed = true;
8290 }
8291 }
8292 /* Now we've also updated encoder->new_crtc for all encoders. */
8293
8294 return 0;
8295 }
8296
8297 static int intel_crtc_set_config(struct drm_mode_set *set)
8298 {
8299 struct drm_device *dev;
8300 struct drm_mode_set save_set;
8301 struct intel_set_config *config;
8302 int ret;
8303
8304 BUG_ON(!set);
8305 BUG_ON(!set->crtc);
8306 BUG_ON(!set->crtc->helper_private);
8307
8308 /* Enforce sane interface api - has been abused by the fb helper. */
8309 BUG_ON(!set->mode && set->fb);
8310 BUG_ON(set->fb && set->num_connectors == 0);
8311
8312 if (set->fb) {
8313 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8314 set->crtc->base.id, set->fb->base.id,
8315 (int)set->num_connectors, set->x, set->y);
8316 } else {
8317 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8318 }
8319
8320 dev = set->crtc->dev;
8321
8322 ret = -ENOMEM;
8323 config = kzalloc(sizeof(*config), GFP_KERNEL);
8324 if (!config)
8325 goto out_config;
8326
8327 ret = intel_set_config_save_state(dev, config);
8328 if (ret)
8329 goto out_config;
8330
8331 save_set.crtc = set->crtc;
8332 save_set.mode = &set->crtc->mode;
8333 save_set.x = set->crtc->x;
8334 save_set.y = set->crtc->y;
8335 save_set.fb = set->crtc->fb;
8336
8337 /* Compute whether we need a full modeset, only an fb base update or no
8338 * change at all. In the future we might also check whether only the
8339 * mode changed, e.g. for LVDS where we only change the panel fitter in
8340 * such cases. */
8341 intel_set_config_compute_mode_changes(set, config);
8342
8343 ret = intel_modeset_stage_output_state(dev, set, config);
8344 if (ret)
8345 goto fail;
8346
8347 if (config->mode_changed) {
8348 if (set->mode) {
8349 DRM_DEBUG_KMS("attempting to set mode from"
8350 " userspace\n");
8351 drm_mode_debug_printmodeline(set->mode);
8352 }
8353
8354 ret = intel_set_mode(set->crtc, set->mode,
8355 set->x, set->y, set->fb);
8356 if (ret) {
8357 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8358 set->crtc->base.id, ret);
8359 goto fail;
8360 }
8361 } else if (config->fb_changed) {
8362 intel_crtc_wait_for_pending_flips(set->crtc);
8363
8364 ret = intel_pipe_set_base(set->crtc,
8365 set->x, set->y, set->fb);
8366 }
8367
8368 intel_set_config_free(config);
8369
8370 return 0;
8371
8372 fail:
8373 intel_set_config_restore_state(dev, config);
8374
8375 /* Try to restore the config */
8376 if (config->mode_changed &&
8377 intel_set_mode(save_set.crtc, save_set.mode,
8378 save_set.x, save_set.y, save_set.fb))
8379 DRM_ERROR("failed to restore config after modeset failure\n");
8380
8381 out_config:
8382 intel_set_config_free(config);
8383 return ret;
8384 }
8385
8386 static const struct drm_crtc_funcs intel_crtc_funcs = {
8387 .cursor_set = intel_crtc_cursor_set,
8388 .cursor_move = intel_crtc_cursor_move,
8389 .gamma_set = intel_crtc_gamma_set,
8390 .set_config = intel_crtc_set_config,
8391 .destroy = intel_crtc_destroy,
8392 .page_flip = intel_crtc_page_flip,
8393 };
8394
8395 static void intel_cpu_pll_init(struct drm_device *dev)
8396 {
8397 if (HAS_DDI(dev))
8398 intel_ddi_pll_init(dev);
8399 }
8400
8401 static void intel_pch_pll_init(struct drm_device *dev)
8402 {
8403 drm_i915_private_t *dev_priv = dev->dev_private;
8404 int i;
8405
8406 if (dev_priv->num_pch_pll == 0) {
8407 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8408 return;
8409 }
8410
8411 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8412 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8413 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8414 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8415 }
8416 }
8417
8418 static void intel_crtc_init(struct drm_device *dev, int pipe)
8419 {
8420 drm_i915_private_t *dev_priv = dev->dev_private;
8421 struct intel_crtc *intel_crtc;
8422 int i;
8423
8424 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8425 if (intel_crtc == NULL)
8426 return;
8427
8428 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8429
8430 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8431 for (i = 0; i < 256; i++) {
8432 intel_crtc->lut_r[i] = i;
8433 intel_crtc->lut_g[i] = i;
8434 intel_crtc->lut_b[i] = i;
8435 }
8436
8437 /* Swap pipes & planes for FBC on pre-965 */
8438 intel_crtc->pipe = pipe;
8439 intel_crtc->plane = pipe;
8440 intel_crtc->config.cpu_transcoder = pipe;
8441 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8442 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8443 intel_crtc->plane = !pipe;
8444 }
8445
8446 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8447 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8448 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8449 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8450
8451 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8452 }
8453
8454 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8455 struct drm_file *file)
8456 {
8457 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8458 struct drm_mode_object *drmmode_obj;
8459 struct intel_crtc *crtc;
8460
8461 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8462 return -ENODEV;
8463
8464 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8465 DRM_MODE_OBJECT_CRTC);
8466
8467 if (!drmmode_obj) {
8468 DRM_ERROR("no such CRTC id\n");
8469 return -EINVAL;
8470 }
8471
8472 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8473 pipe_from_crtc_id->pipe = crtc->pipe;
8474
8475 return 0;
8476 }
8477
8478 static int intel_encoder_clones(struct intel_encoder *encoder)
8479 {
8480 struct drm_device *dev = encoder->base.dev;
8481 struct intel_encoder *source_encoder;
8482 int index_mask = 0;
8483 int entry = 0;
8484
8485 list_for_each_entry(source_encoder,
8486 &dev->mode_config.encoder_list, base.head) {
8487
8488 if (encoder == source_encoder)
8489 index_mask |= (1 << entry);
8490
8491 /* Intel hw has only one MUX where enocoders could be cloned. */
8492 if (encoder->cloneable && source_encoder->cloneable)
8493 index_mask |= (1 << entry);
8494
8495 entry++;
8496 }
8497
8498 return index_mask;
8499 }
8500
8501 static bool has_edp_a(struct drm_device *dev)
8502 {
8503 struct drm_i915_private *dev_priv = dev->dev_private;
8504
8505 if (!IS_MOBILE(dev))
8506 return false;
8507
8508 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8509 return false;
8510
8511 if (IS_GEN5(dev) &&
8512 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8513 return false;
8514
8515 return true;
8516 }
8517
8518 static void intel_setup_outputs(struct drm_device *dev)
8519 {
8520 struct drm_i915_private *dev_priv = dev->dev_private;
8521 struct intel_encoder *encoder;
8522 bool dpd_is_edp = false;
8523 bool has_lvds;
8524
8525 has_lvds = intel_lvds_init(dev);
8526 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8527 /* disable the panel fitter on everything but LVDS */
8528 I915_WRITE(PFIT_CONTROL, 0);
8529 }
8530
8531 if (!IS_ULT(dev))
8532 intel_crt_init(dev);
8533
8534 if (HAS_DDI(dev)) {
8535 int found;
8536
8537 /* Haswell uses DDI functions to detect digital outputs */
8538 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8539 /* DDI A only supports eDP */
8540 if (found)
8541 intel_ddi_init(dev, PORT_A);
8542
8543 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8544 * register */
8545 found = I915_READ(SFUSE_STRAP);
8546
8547 if (found & SFUSE_STRAP_DDIB_DETECTED)
8548 intel_ddi_init(dev, PORT_B);
8549 if (found & SFUSE_STRAP_DDIC_DETECTED)
8550 intel_ddi_init(dev, PORT_C);
8551 if (found & SFUSE_STRAP_DDID_DETECTED)
8552 intel_ddi_init(dev, PORT_D);
8553 } else if (HAS_PCH_SPLIT(dev)) {
8554 int found;
8555 dpd_is_edp = intel_dpd_is_edp(dev);
8556
8557 if (has_edp_a(dev))
8558 intel_dp_init(dev, DP_A, PORT_A);
8559
8560 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8561 /* PCH SDVOB multiplex with HDMIB */
8562 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8563 if (!found)
8564 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8565 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8566 intel_dp_init(dev, PCH_DP_B, PORT_B);
8567 }
8568
8569 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8570 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8571
8572 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8573 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8574
8575 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8576 intel_dp_init(dev, PCH_DP_C, PORT_C);
8577
8578 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8579 intel_dp_init(dev, PCH_DP_D, PORT_D);
8580 } else if (IS_VALLEYVIEW(dev)) {
8581 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8582 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8583 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8584
8585 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8586 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8587 PORT_B);
8588 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8589 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8590 }
8591 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8592 bool found = false;
8593
8594 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8595 DRM_DEBUG_KMS("probing SDVOB\n");
8596 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8597 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8598 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8599 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8600 }
8601
8602 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8603 DRM_DEBUG_KMS("probing DP_B\n");
8604 intel_dp_init(dev, DP_B, PORT_B);
8605 }
8606 }
8607
8608 /* Before G4X SDVOC doesn't have its own detect register */
8609
8610 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8611 DRM_DEBUG_KMS("probing SDVOC\n");
8612 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8613 }
8614
8615 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8616
8617 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8618 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8619 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8620 }
8621 if (SUPPORTS_INTEGRATED_DP(dev)) {
8622 DRM_DEBUG_KMS("probing DP_C\n");
8623 intel_dp_init(dev, DP_C, PORT_C);
8624 }
8625 }
8626
8627 if (SUPPORTS_INTEGRATED_DP(dev) &&
8628 (I915_READ(DP_D) & DP_DETECTED)) {
8629 DRM_DEBUG_KMS("probing DP_D\n");
8630 intel_dp_init(dev, DP_D, PORT_D);
8631 }
8632 } else if (IS_GEN2(dev))
8633 intel_dvo_init(dev);
8634
8635 if (SUPPORTS_TV(dev))
8636 intel_tv_init(dev);
8637
8638 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8639 encoder->base.possible_crtcs = encoder->crtc_mask;
8640 encoder->base.possible_clones =
8641 intel_encoder_clones(encoder);
8642 }
8643
8644 intel_init_pch_refclk(dev);
8645
8646 drm_helper_move_panel_connectors_to_head(dev);
8647 }
8648
8649 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8650 {
8651 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8652
8653 drm_framebuffer_cleanup(fb);
8654 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8655
8656 kfree(intel_fb);
8657 }
8658
8659 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8660 struct drm_file *file,
8661 unsigned int *handle)
8662 {
8663 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8664 struct drm_i915_gem_object *obj = intel_fb->obj;
8665
8666 return drm_gem_handle_create(file, &obj->base, handle);
8667 }
8668
8669 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8670 .destroy = intel_user_framebuffer_destroy,
8671 .create_handle = intel_user_framebuffer_create_handle,
8672 };
8673
8674 int intel_framebuffer_init(struct drm_device *dev,
8675 struct intel_framebuffer *intel_fb,
8676 struct drm_mode_fb_cmd2 *mode_cmd,
8677 struct drm_i915_gem_object *obj)
8678 {
8679 int ret;
8680
8681 if (obj->tiling_mode == I915_TILING_Y) {
8682 DRM_DEBUG("hardware does not support tiling Y\n");
8683 return -EINVAL;
8684 }
8685
8686 if (mode_cmd->pitches[0] & 63) {
8687 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8688 mode_cmd->pitches[0]);
8689 return -EINVAL;
8690 }
8691
8692 /* FIXME <= Gen4 stride limits are bit unclear */
8693 if (mode_cmd->pitches[0] > 32768) {
8694 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8695 mode_cmd->pitches[0]);
8696 return -EINVAL;
8697 }
8698
8699 if (obj->tiling_mode != I915_TILING_NONE &&
8700 mode_cmd->pitches[0] != obj->stride) {
8701 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8702 mode_cmd->pitches[0], obj->stride);
8703 return -EINVAL;
8704 }
8705
8706 /* Reject formats not supported by any plane early. */
8707 switch (mode_cmd->pixel_format) {
8708 case DRM_FORMAT_C8:
8709 case DRM_FORMAT_RGB565:
8710 case DRM_FORMAT_XRGB8888:
8711 case DRM_FORMAT_ARGB8888:
8712 break;
8713 case DRM_FORMAT_XRGB1555:
8714 case DRM_FORMAT_ARGB1555:
8715 if (INTEL_INFO(dev)->gen > 3) {
8716 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8717 return -EINVAL;
8718 }
8719 break;
8720 case DRM_FORMAT_XBGR8888:
8721 case DRM_FORMAT_ABGR8888:
8722 case DRM_FORMAT_XRGB2101010:
8723 case DRM_FORMAT_ARGB2101010:
8724 case DRM_FORMAT_XBGR2101010:
8725 case DRM_FORMAT_ABGR2101010:
8726 if (INTEL_INFO(dev)->gen < 4) {
8727 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8728 return -EINVAL;
8729 }
8730 break;
8731 case DRM_FORMAT_YUYV:
8732 case DRM_FORMAT_UYVY:
8733 case DRM_FORMAT_YVYU:
8734 case DRM_FORMAT_VYUY:
8735 if (INTEL_INFO(dev)->gen < 5) {
8736 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8737 return -EINVAL;
8738 }
8739 break;
8740 default:
8741 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8742 return -EINVAL;
8743 }
8744
8745 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8746 if (mode_cmd->offsets[0] != 0)
8747 return -EINVAL;
8748
8749 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8750 intel_fb->obj = obj;
8751
8752 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8753 if (ret) {
8754 DRM_ERROR("framebuffer init failed %d\n", ret);
8755 return ret;
8756 }
8757
8758 return 0;
8759 }
8760
8761 static struct drm_framebuffer *
8762 intel_user_framebuffer_create(struct drm_device *dev,
8763 struct drm_file *filp,
8764 struct drm_mode_fb_cmd2 *mode_cmd)
8765 {
8766 struct drm_i915_gem_object *obj;
8767
8768 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8769 mode_cmd->handles[0]));
8770 if (&obj->base == NULL)
8771 return ERR_PTR(-ENOENT);
8772
8773 return intel_framebuffer_create(dev, mode_cmd, obj);
8774 }
8775
8776 static const struct drm_mode_config_funcs intel_mode_funcs = {
8777 .fb_create = intel_user_framebuffer_create,
8778 .output_poll_changed = intel_fb_output_poll_changed,
8779 };
8780
8781 /* Set up chip specific display functions */
8782 static void intel_init_display(struct drm_device *dev)
8783 {
8784 struct drm_i915_private *dev_priv = dev->dev_private;
8785
8786 if (HAS_DDI(dev)) {
8787 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8788 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8789 dev_priv->display.crtc_enable = haswell_crtc_enable;
8790 dev_priv->display.crtc_disable = haswell_crtc_disable;
8791 dev_priv->display.off = haswell_crtc_off;
8792 dev_priv->display.update_plane = ironlake_update_plane;
8793 } else if (HAS_PCH_SPLIT(dev)) {
8794 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8795 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8796 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8797 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8798 dev_priv->display.off = ironlake_crtc_off;
8799 dev_priv->display.update_plane = ironlake_update_plane;
8800 } else if (IS_VALLEYVIEW(dev)) {
8801 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8802 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8803 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8804 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8805 dev_priv->display.off = i9xx_crtc_off;
8806 dev_priv->display.update_plane = i9xx_update_plane;
8807 } else {
8808 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8809 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8810 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8811 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8812 dev_priv->display.off = i9xx_crtc_off;
8813 dev_priv->display.update_plane = i9xx_update_plane;
8814 }
8815
8816 /* Returns the core display clock speed */
8817 if (IS_VALLEYVIEW(dev))
8818 dev_priv->display.get_display_clock_speed =
8819 valleyview_get_display_clock_speed;
8820 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8821 dev_priv->display.get_display_clock_speed =
8822 i945_get_display_clock_speed;
8823 else if (IS_I915G(dev))
8824 dev_priv->display.get_display_clock_speed =
8825 i915_get_display_clock_speed;
8826 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8827 dev_priv->display.get_display_clock_speed =
8828 i9xx_misc_get_display_clock_speed;
8829 else if (IS_I915GM(dev))
8830 dev_priv->display.get_display_clock_speed =
8831 i915gm_get_display_clock_speed;
8832 else if (IS_I865G(dev))
8833 dev_priv->display.get_display_clock_speed =
8834 i865_get_display_clock_speed;
8835 else if (IS_I85X(dev))
8836 dev_priv->display.get_display_clock_speed =
8837 i855_get_display_clock_speed;
8838 else /* 852, 830 */
8839 dev_priv->display.get_display_clock_speed =
8840 i830_get_display_clock_speed;
8841
8842 if (HAS_PCH_SPLIT(dev)) {
8843 if (IS_GEN5(dev)) {
8844 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8845 dev_priv->display.write_eld = ironlake_write_eld;
8846 } else if (IS_GEN6(dev)) {
8847 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8848 dev_priv->display.write_eld = ironlake_write_eld;
8849 } else if (IS_IVYBRIDGE(dev)) {
8850 /* FIXME: detect B0+ stepping and use auto training */
8851 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8852 dev_priv->display.write_eld = ironlake_write_eld;
8853 dev_priv->display.modeset_global_resources =
8854 ivb_modeset_global_resources;
8855 } else if (IS_HASWELL(dev)) {
8856 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8857 dev_priv->display.write_eld = haswell_write_eld;
8858 dev_priv->display.modeset_global_resources =
8859 haswell_modeset_global_resources;
8860 }
8861 } else if (IS_G4X(dev)) {
8862 dev_priv->display.write_eld = g4x_write_eld;
8863 }
8864
8865 /* Default just returns -ENODEV to indicate unsupported */
8866 dev_priv->display.queue_flip = intel_default_queue_flip;
8867
8868 switch (INTEL_INFO(dev)->gen) {
8869 case 2:
8870 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8871 break;
8872
8873 case 3:
8874 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8875 break;
8876
8877 case 4:
8878 case 5:
8879 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8880 break;
8881
8882 case 6:
8883 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8884 break;
8885 case 7:
8886 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8887 break;
8888 }
8889 }
8890
8891 /*
8892 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8893 * resume, or other times. This quirk makes sure that's the case for
8894 * affected systems.
8895 */
8896 static void quirk_pipea_force(struct drm_device *dev)
8897 {
8898 struct drm_i915_private *dev_priv = dev->dev_private;
8899
8900 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8901 DRM_INFO("applying pipe a force quirk\n");
8902 }
8903
8904 /*
8905 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8906 */
8907 static void quirk_ssc_force_disable(struct drm_device *dev)
8908 {
8909 struct drm_i915_private *dev_priv = dev->dev_private;
8910 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8911 DRM_INFO("applying lvds SSC disable quirk\n");
8912 }
8913
8914 /*
8915 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8916 * brightness value
8917 */
8918 static void quirk_invert_brightness(struct drm_device *dev)
8919 {
8920 struct drm_i915_private *dev_priv = dev->dev_private;
8921 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8922 DRM_INFO("applying inverted panel brightness quirk\n");
8923 }
8924
8925 struct intel_quirk {
8926 int device;
8927 int subsystem_vendor;
8928 int subsystem_device;
8929 void (*hook)(struct drm_device *dev);
8930 };
8931
8932 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8933 struct intel_dmi_quirk {
8934 void (*hook)(struct drm_device *dev);
8935 const struct dmi_system_id (*dmi_id_list)[];
8936 };
8937
8938 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8939 {
8940 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8941 return 1;
8942 }
8943
8944 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8945 {
8946 .dmi_id_list = &(const struct dmi_system_id[]) {
8947 {
8948 .callback = intel_dmi_reverse_brightness,
8949 .ident = "NCR Corporation",
8950 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8951 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8952 },
8953 },
8954 { } /* terminating entry */
8955 },
8956 .hook = quirk_invert_brightness,
8957 },
8958 };
8959
8960 static struct intel_quirk intel_quirks[] = {
8961 /* HP Mini needs pipe A force quirk (LP: #322104) */
8962 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8963
8964 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8965 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8966
8967 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8968 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8969
8970 /* 830/845 need to leave pipe A & dpll A up */
8971 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8972 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8973
8974 /* Lenovo U160 cannot use SSC on LVDS */
8975 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8976
8977 /* Sony Vaio Y cannot use SSC on LVDS */
8978 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8979
8980 /* Acer Aspire 5734Z must invert backlight brightness */
8981 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8982
8983 /* Acer/eMachines G725 */
8984 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8985
8986 /* Acer/eMachines e725 */
8987 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8988
8989 /* Acer/Packard Bell NCL20 */
8990 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8991
8992 /* Acer Aspire 4736Z */
8993 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8994 };
8995
8996 static void intel_init_quirks(struct drm_device *dev)
8997 {
8998 struct pci_dev *d = dev->pdev;
8999 int i;
9000
9001 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9002 struct intel_quirk *q = &intel_quirks[i];
9003
9004 if (d->device == q->device &&
9005 (d->subsystem_vendor == q->subsystem_vendor ||
9006 q->subsystem_vendor == PCI_ANY_ID) &&
9007 (d->subsystem_device == q->subsystem_device ||
9008 q->subsystem_device == PCI_ANY_ID))
9009 q->hook(dev);
9010 }
9011 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9012 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9013 intel_dmi_quirks[i].hook(dev);
9014 }
9015 }
9016
9017 /* Disable the VGA plane that we never use */
9018 static void i915_disable_vga(struct drm_device *dev)
9019 {
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021 u8 sr1;
9022 u32 vga_reg = i915_vgacntrl_reg(dev);
9023
9024 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9025 outb(SR01, VGA_SR_INDEX);
9026 sr1 = inb(VGA_SR_DATA);
9027 outb(sr1 | 1<<5, VGA_SR_DATA);
9028 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9029 udelay(300);
9030
9031 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9032 POSTING_READ(vga_reg);
9033 }
9034
9035 void intel_modeset_init_hw(struct drm_device *dev)
9036 {
9037 intel_init_power_well(dev);
9038
9039 intel_prepare_ddi(dev);
9040
9041 intel_init_clock_gating(dev);
9042
9043 mutex_lock(&dev->struct_mutex);
9044 intel_enable_gt_powersave(dev);
9045 mutex_unlock(&dev->struct_mutex);
9046 }
9047
9048 void intel_modeset_init(struct drm_device *dev)
9049 {
9050 struct drm_i915_private *dev_priv = dev->dev_private;
9051 int i, j, ret;
9052
9053 drm_mode_config_init(dev);
9054
9055 dev->mode_config.min_width = 0;
9056 dev->mode_config.min_height = 0;
9057
9058 dev->mode_config.preferred_depth = 24;
9059 dev->mode_config.prefer_shadow = 1;
9060
9061 dev->mode_config.funcs = &intel_mode_funcs;
9062
9063 intel_init_quirks(dev);
9064
9065 intel_init_pm(dev);
9066
9067 if (INTEL_INFO(dev)->num_pipes == 0)
9068 return;
9069
9070 intel_init_display(dev);
9071
9072 if (IS_GEN2(dev)) {
9073 dev->mode_config.max_width = 2048;
9074 dev->mode_config.max_height = 2048;
9075 } else if (IS_GEN3(dev)) {
9076 dev->mode_config.max_width = 4096;
9077 dev->mode_config.max_height = 4096;
9078 } else {
9079 dev->mode_config.max_width = 8192;
9080 dev->mode_config.max_height = 8192;
9081 }
9082 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9083
9084 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9085 INTEL_INFO(dev)->num_pipes,
9086 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9087
9088 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9089 intel_crtc_init(dev, i);
9090 for (j = 0; j < dev_priv->num_plane; j++) {
9091 ret = intel_plane_init(dev, i, j);
9092 if (ret)
9093 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9094 pipe_name(i), sprite_name(i, j), ret);
9095 }
9096 }
9097
9098 intel_cpu_pll_init(dev);
9099 intel_pch_pll_init(dev);
9100
9101 /* Just disable it once at startup */
9102 i915_disable_vga(dev);
9103 intel_setup_outputs(dev);
9104
9105 /* Just in case the BIOS is doing something questionable. */
9106 intel_disable_fbc(dev);
9107 }
9108
9109 static void
9110 intel_connector_break_all_links(struct intel_connector *connector)
9111 {
9112 connector->base.dpms = DRM_MODE_DPMS_OFF;
9113 connector->base.encoder = NULL;
9114 connector->encoder->connectors_active = false;
9115 connector->encoder->base.crtc = NULL;
9116 }
9117
9118 static void intel_enable_pipe_a(struct drm_device *dev)
9119 {
9120 struct intel_connector *connector;
9121 struct drm_connector *crt = NULL;
9122 struct intel_load_detect_pipe load_detect_temp;
9123
9124 /* We can't just switch on the pipe A, we need to set things up with a
9125 * proper mode and output configuration. As a gross hack, enable pipe A
9126 * by enabling the load detect pipe once. */
9127 list_for_each_entry(connector,
9128 &dev->mode_config.connector_list,
9129 base.head) {
9130 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9131 crt = &connector->base;
9132 break;
9133 }
9134 }
9135
9136 if (!crt)
9137 return;
9138
9139 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9140 intel_release_load_detect_pipe(crt, &load_detect_temp);
9141
9142
9143 }
9144
9145 static bool
9146 intel_check_plane_mapping(struct intel_crtc *crtc)
9147 {
9148 struct drm_device *dev = crtc->base.dev;
9149 struct drm_i915_private *dev_priv = dev->dev_private;
9150 u32 reg, val;
9151
9152 if (INTEL_INFO(dev)->num_pipes == 1)
9153 return true;
9154
9155 reg = DSPCNTR(!crtc->plane);
9156 val = I915_READ(reg);
9157
9158 if ((val & DISPLAY_PLANE_ENABLE) &&
9159 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9160 return false;
9161
9162 return true;
9163 }
9164
9165 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9166 {
9167 struct drm_device *dev = crtc->base.dev;
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169 u32 reg;
9170
9171 /* Clear any frame start delays used for debugging left by the BIOS */
9172 reg = PIPECONF(crtc->config.cpu_transcoder);
9173 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9174
9175 /* We need to sanitize the plane -> pipe mapping first because this will
9176 * disable the crtc (and hence change the state) if it is wrong. Note
9177 * that gen4+ has a fixed plane -> pipe mapping. */
9178 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9179 struct intel_connector *connector;
9180 bool plane;
9181
9182 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9183 crtc->base.base.id);
9184
9185 /* Pipe has the wrong plane attached and the plane is active.
9186 * Temporarily change the plane mapping and disable everything
9187 * ... */
9188 plane = crtc->plane;
9189 crtc->plane = !plane;
9190 dev_priv->display.crtc_disable(&crtc->base);
9191 crtc->plane = plane;
9192
9193 /* ... and break all links. */
9194 list_for_each_entry(connector, &dev->mode_config.connector_list,
9195 base.head) {
9196 if (connector->encoder->base.crtc != &crtc->base)
9197 continue;
9198
9199 intel_connector_break_all_links(connector);
9200 }
9201
9202 WARN_ON(crtc->active);
9203 crtc->base.enabled = false;
9204 }
9205
9206 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9207 crtc->pipe == PIPE_A && !crtc->active) {
9208 /* BIOS forgot to enable pipe A, this mostly happens after
9209 * resume. Force-enable the pipe to fix this, the update_dpms
9210 * call below we restore the pipe to the right state, but leave
9211 * the required bits on. */
9212 intel_enable_pipe_a(dev);
9213 }
9214
9215 /* Adjust the state of the output pipe according to whether we
9216 * have active connectors/encoders. */
9217 intel_crtc_update_dpms(&crtc->base);
9218
9219 if (crtc->active != crtc->base.enabled) {
9220 struct intel_encoder *encoder;
9221
9222 /* This can happen either due to bugs in the get_hw_state
9223 * functions or because the pipe is force-enabled due to the
9224 * pipe A quirk. */
9225 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9226 crtc->base.base.id,
9227 crtc->base.enabled ? "enabled" : "disabled",
9228 crtc->active ? "enabled" : "disabled");
9229
9230 crtc->base.enabled = crtc->active;
9231
9232 /* Because we only establish the connector -> encoder ->
9233 * crtc links if something is active, this means the
9234 * crtc is now deactivated. Break the links. connector
9235 * -> encoder links are only establish when things are
9236 * actually up, hence no need to break them. */
9237 WARN_ON(crtc->active);
9238
9239 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9240 WARN_ON(encoder->connectors_active);
9241 encoder->base.crtc = NULL;
9242 }
9243 }
9244 }
9245
9246 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9247 {
9248 struct intel_connector *connector;
9249 struct drm_device *dev = encoder->base.dev;
9250
9251 /* We need to check both for a crtc link (meaning that the
9252 * encoder is active and trying to read from a pipe) and the
9253 * pipe itself being active. */
9254 bool has_active_crtc = encoder->base.crtc &&
9255 to_intel_crtc(encoder->base.crtc)->active;
9256
9257 if (encoder->connectors_active && !has_active_crtc) {
9258 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9259 encoder->base.base.id,
9260 drm_get_encoder_name(&encoder->base));
9261
9262 /* Connector is active, but has no active pipe. This is
9263 * fallout from our resume register restoring. Disable
9264 * the encoder manually again. */
9265 if (encoder->base.crtc) {
9266 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9267 encoder->base.base.id,
9268 drm_get_encoder_name(&encoder->base));
9269 encoder->disable(encoder);
9270 }
9271
9272 /* Inconsistent output/port/pipe state happens presumably due to
9273 * a bug in one of the get_hw_state functions. Or someplace else
9274 * in our code, like the register restore mess on resume. Clamp
9275 * things to off as a safer default. */
9276 list_for_each_entry(connector,
9277 &dev->mode_config.connector_list,
9278 base.head) {
9279 if (connector->encoder != encoder)
9280 continue;
9281
9282 intel_connector_break_all_links(connector);
9283 }
9284 }
9285 /* Enabled encoders without active connectors will be fixed in
9286 * the crtc fixup. */
9287 }
9288
9289 void i915_redisable_vga(struct drm_device *dev)
9290 {
9291 struct drm_i915_private *dev_priv = dev->dev_private;
9292 u32 vga_reg = i915_vgacntrl_reg(dev);
9293
9294 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9295 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9296 i915_disable_vga(dev);
9297 }
9298 }
9299
9300 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9301 * and i915 state tracking structures. */
9302 void intel_modeset_setup_hw_state(struct drm_device *dev,
9303 bool force_restore)
9304 {
9305 struct drm_i915_private *dev_priv = dev->dev_private;
9306 enum pipe pipe;
9307 u32 tmp;
9308 struct drm_plane *plane;
9309 struct intel_crtc *crtc;
9310 struct intel_encoder *encoder;
9311 struct intel_connector *connector;
9312
9313 if (HAS_DDI(dev)) {
9314 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9315
9316 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9317 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9318 case TRANS_DDI_EDP_INPUT_A_ON:
9319 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9320 pipe = PIPE_A;
9321 break;
9322 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9323 pipe = PIPE_B;
9324 break;
9325 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9326 pipe = PIPE_C;
9327 break;
9328 default:
9329 /* A bogus value has been programmed, disable
9330 * the transcoder */
9331 WARN(1, "Bogus eDP source %08x\n", tmp);
9332 intel_ddi_disable_transcoder_func(dev_priv,
9333 TRANSCODER_EDP);
9334 goto setup_pipes;
9335 }
9336
9337 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9338 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9339
9340 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9341 pipe_name(pipe));
9342 }
9343 }
9344
9345 setup_pipes:
9346 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9347 base.head) {
9348 enum transcoder tmp = crtc->config.cpu_transcoder;
9349 memset(&crtc->config, 0, sizeof(crtc->config));
9350 crtc->config.cpu_transcoder = tmp;
9351
9352 crtc->active = dev_priv->display.get_pipe_config(crtc,
9353 &crtc->config);
9354
9355 crtc->base.enabled = crtc->active;
9356
9357 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9358 crtc->base.base.id,
9359 crtc->active ? "enabled" : "disabled");
9360 }
9361
9362 if (HAS_DDI(dev))
9363 intel_ddi_setup_hw_pll_state(dev);
9364
9365 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9366 base.head) {
9367 pipe = 0;
9368
9369 if (encoder->get_hw_state(encoder, &pipe)) {
9370 encoder->base.crtc =
9371 dev_priv->pipe_to_crtc_mapping[pipe];
9372 } else {
9373 encoder->base.crtc = NULL;
9374 }
9375
9376 encoder->connectors_active = false;
9377 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9378 encoder->base.base.id,
9379 drm_get_encoder_name(&encoder->base),
9380 encoder->base.crtc ? "enabled" : "disabled",
9381 pipe);
9382 }
9383
9384 list_for_each_entry(connector, &dev->mode_config.connector_list,
9385 base.head) {
9386 if (connector->get_hw_state(connector)) {
9387 connector->base.dpms = DRM_MODE_DPMS_ON;
9388 connector->encoder->connectors_active = true;
9389 connector->base.encoder = &connector->encoder->base;
9390 } else {
9391 connector->base.dpms = DRM_MODE_DPMS_OFF;
9392 connector->base.encoder = NULL;
9393 }
9394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9395 connector->base.base.id,
9396 drm_get_connector_name(&connector->base),
9397 connector->base.encoder ? "enabled" : "disabled");
9398 }
9399
9400 /* HW state is read out, now we need to sanitize this mess. */
9401 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9402 base.head) {
9403 intel_sanitize_encoder(encoder);
9404 }
9405
9406 for_each_pipe(pipe) {
9407 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9408 intel_sanitize_crtc(crtc);
9409 }
9410
9411 if (force_restore) {
9412 /*
9413 * We need to use raw interfaces for restoring state to avoid
9414 * checking (bogus) intermediate states.
9415 */
9416 for_each_pipe(pipe) {
9417 struct drm_crtc *crtc =
9418 dev_priv->pipe_to_crtc_mapping[pipe];
9419
9420 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9421 crtc->fb);
9422 }
9423 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9424 intel_plane_restore(plane);
9425
9426 i915_redisable_vga(dev);
9427 } else {
9428 intel_modeset_update_staged_output_state(dev);
9429 }
9430
9431 intel_modeset_check_state(dev);
9432
9433 drm_mode_config_reset(dev);
9434 }
9435
9436 void intel_modeset_gem_init(struct drm_device *dev)
9437 {
9438 intel_modeset_init_hw(dev);
9439
9440 intel_setup_overlay(dev);
9441
9442 intel_modeset_setup_hw_state(dev, false);
9443 }
9444
9445 void intel_modeset_cleanup(struct drm_device *dev)
9446 {
9447 struct drm_i915_private *dev_priv = dev->dev_private;
9448 struct drm_crtc *crtc;
9449 struct intel_crtc *intel_crtc;
9450
9451 /*
9452 * Interrupts and polling as the first thing to avoid creating havoc.
9453 * Too much stuff here (turning of rps, connectors, ...) would
9454 * experience fancy races otherwise.
9455 */
9456 drm_irq_uninstall(dev);
9457 cancel_work_sync(&dev_priv->hotplug_work);
9458 /*
9459 * Due to the hpd irq storm handling the hotplug work can re-arm the
9460 * poll handlers. Hence disable polling after hpd handling is shut down.
9461 */
9462 drm_kms_helper_poll_fini(dev);
9463
9464 mutex_lock(&dev->struct_mutex);
9465
9466 intel_unregister_dsm_handler();
9467
9468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9469 /* Skip inactive CRTCs */
9470 if (!crtc->fb)
9471 continue;
9472
9473 intel_crtc = to_intel_crtc(crtc);
9474 intel_increase_pllclock(crtc);
9475 }
9476
9477 intel_disable_fbc(dev);
9478
9479 intel_disable_gt_powersave(dev);
9480
9481 ironlake_teardown_rc6(dev);
9482
9483 mutex_unlock(&dev->struct_mutex);
9484
9485 /* flush any delayed tasks or pending work */
9486 flush_scheduled_work();
9487
9488 /* destroy backlight, if any, before the connectors */
9489 intel_panel_destroy_backlight(dev);
9490
9491 drm_mode_config_cleanup(dev);
9492
9493 intel_cleanup_overlay(dev);
9494 }
9495
9496 /*
9497 * Return which encoder is currently attached for connector.
9498 */
9499 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9500 {
9501 return &intel_attached_encoder(connector)->base;
9502 }
9503
9504 void intel_connector_attach_encoder(struct intel_connector *connector,
9505 struct intel_encoder *encoder)
9506 {
9507 connector->encoder = encoder;
9508 drm_mode_connector_attach_encoder(&connector->base,
9509 &encoder->base);
9510 }
9511
9512 /*
9513 * set vga decode state - true == enable VGA decode
9514 */
9515 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9516 {
9517 struct drm_i915_private *dev_priv = dev->dev_private;
9518 u16 gmch_ctrl;
9519
9520 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9521 if (state)
9522 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9523 else
9524 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9525 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9526 return 0;
9527 }
9528
9529 #ifdef CONFIG_DEBUG_FS
9530 #include <linux/seq_file.h>
9531
9532 struct intel_display_error_state {
9533 struct intel_cursor_error_state {
9534 u32 control;
9535 u32 position;
9536 u32 base;
9537 u32 size;
9538 } cursor[I915_MAX_PIPES];
9539
9540 struct intel_pipe_error_state {
9541 u32 conf;
9542 u32 source;
9543
9544 u32 htotal;
9545 u32 hblank;
9546 u32 hsync;
9547 u32 vtotal;
9548 u32 vblank;
9549 u32 vsync;
9550 } pipe[I915_MAX_PIPES];
9551
9552 struct intel_plane_error_state {
9553 u32 control;
9554 u32 stride;
9555 u32 size;
9556 u32 pos;
9557 u32 addr;
9558 u32 surface;
9559 u32 tile_offset;
9560 } plane[I915_MAX_PIPES];
9561 };
9562
9563 struct intel_display_error_state *
9564 intel_display_capture_error_state(struct drm_device *dev)
9565 {
9566 drm_i915_private_t *dev_priv = dev->dev_private;
9567 struct intel_display_error_state *error;
9568 enum transcoder cpu_transcoder;
9569 int i;
9570
9571 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9572 if (error == NULL)
9573 return NULL;
9574
9575 for_each_pipe(i) {
9576 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9577
9578 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9579 error->cursor[i].control = I915_READ(CURCNTR(i));
9580 error->cursor[i].position = I915_READ(CURPOS(i));
9581 error->cursor[i].base = I915_READ(CURBASE(i));
9582 } else {
9583 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9584 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9585 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9586 }
9587
9588 error->plane[i].control = I915_READ(DSPCNTR(i));
9589 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9590 if (INTEL_INFO(dev)->gen <= 3) {
9591 error->plane[i].size = I915_READ(DSPSIZE(i));
9592 error->plane[i].pos = I915_READ(DSPPOS(i));
9593 }
9594 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9595 error->plane[i].addr = I915_READ(DSPADDR(i));
9596 if (INTEL_INFO(dev)->gen >= 4) {
9597 error->plane[i].surface = I915_READ(DSPSURF(i));
9598 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9599 }
9600
9601 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9602 error->pipe[i].source = I915_READ(PIPESRC(i));
9603 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9604 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9605 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9606 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9607 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9608 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9609 }
9610
9611 return error;
9612 }
9613
9614 void
9615 intel_display_print_error_state(struct seq_file *m,
9616 struct drm_device *dev,
9617 struct intel_display_error_state *error)
9618 {
9619 int i;
9620
9621 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9622 for_each_pipe(i) {
9623 seq_printf(m, "Pipe [%d]:\n", i);
9624 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9625 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9626 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9627 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9628 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9629 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9630 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9631 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9632
9633 seq_printf(m, "Plane [%d]:\n", i);
9634 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9635 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9636 if (INTEL_INFO(dev)->gen <= 3) {
9637 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9638 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9639 }
9640 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9641 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9642 if (INTEL_INFO(dev)->gen >= 4) {
9643 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9644 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9645 }
9646
9647 seq_printf(m, "Cursor [%d]:\n", i);
9648 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9649 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9650 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9651 }
9652 }
9653 #endif
Linux kernel - Deliverables
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