2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
48 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
49 struct intel_crtc_config
*pipe_config
);
50 static void ironlake_crtc_clock_get(struct intel_crtc
*crtc
,
51 struct intel_crtc_config
*pipe_config
);
62 #define INTEL_P2_NUM 2
63 typedef struct intel_limit intel_limit_t
;
65 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
70 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
73 intel_pch_rawclk(struct drm_device
*dev
)
75 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
77 WARN_ON(!HAS_PCH_SPLIT(dev
));
79 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
82 static inline u32
/* units of 100MHz */
83 intel_fdi_link_freq(struct drm_device
*dev
)
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
87 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
92 static const intel_limit_t intel_limits_i8xx_dac
= {
93 .dot
= { .min
= 25000, .max
= 350000 },
94 .vco
= { .min
= 930000, .max
= 1400000 },
95 .n
= { .min
= 3, .max
= 16 },
96 .m
= { .min
= 96, .max
= 140 },
97 .m1
= { .min
= 18, .max
= 26 },
98 .m2
= { .min
= 6, .max
= 16 },
99 .p
= { .min
= 4, .max
= 128 },
100 .p1
= { .min
= 2, .max
= 33 },
101 .p2
= { .dot_limit
= 165000,
102 .p2_slow
= 4, .p2_fast
= 2 },
105 static const intel_limit_t intel_limits_i8xx_dvo
= {
106 .dot
= { .min
= 25000, .max
= 350000 },
107 .vco
= { .min
= 930000, .max
= 1400000 },
108 .n
= { .min
= 3, .max
= 16 },
109 .m
= { .min
= 96, .max
= 140 },
110 .m1
= { .min
= 18, .max
= 26 },
111 .m2
= { .min
= 6, .max
= 16 },
112 .p
= { .min
= 4, .max
= 128 },
113 .p1
= { .min
= 2, .max
= 33 },
114 .p2
= { .dot_limit
= 165000,
115 .p2_slow
= 4, .p2_fast
= 4 },
118 static const intel_limit_t intel_limits_i8xx_lvds
= {
119 .dot
= { .min
= 25000, .max
= 350000 },
120 .vco
= { .min
= 930000, .max
= 1400000 },
121 .n
= { .min
= 3, .max
= 16 },
122 .m
= { .min
= 96, .max
= 140 },
123 .m1
= { .min
= 18, .max
= 26 },
124 .m2
= { .min
= 6, .max
= 16 },
125 .p
= { .min
= 4, .max
= 128 },
126 .p1
= { .min
= 1, .max
= 6 },
127 .p2
= { .dot_limit
= 165000,
128 .p2_slow
= 14, .p2_fast
= 7 },
131 static const intel_limit_t intel_limits_i9xx_sdvo
= {
132 .dot
= { .min
= 20000, .max
= 400000 },
133 .vco
= { .min
= 1400000, .max
= 2800000 },
134 .n
= { .min
= 1, .max
= 6 },
135 .m
= { .min
= 70, .max
= 120 },
136 .m1
= { .min
= 8, .max
= 18 },
137 .m2
= { .min
= 3, .max
= 7 },
138 .p
= { .min
= 5, .max
= 80 },
139 .p1
= { .min
= 1, .max
= 8 },
140 .p2
= { .dot_limit
= 200000,
141 .p2_slow
= 10, .p2_fast
= 5 },
144 static const intel_limit_t intel_limits_i9xx_lvds
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 8, .max
= 18 },
150 .m2
= { .min
= 3, .max
= 7 },
151 .p
= { .min
= 7, .max
= 98 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 112000,
154 .p2_slow
= 14, .p2_fast
= 7 },
158 static const intel_limit_t intel_limits_g4x_sdvo
= {
159 .dot
= { .min
= 25000, .max
= 270000 },
160 .vco
= { .min
= 1750000, .max
= 3500000},
161 .n
= { .min
= 1, .max
= 4 },
162 .m
= { .min
= 104, .max
= 138 },
163 .m1
= { .min
= 17, .max
= 23 },
164 .m2
= { .min
= 5, .max
= 11 },
165 .p
= { .min
= 10, .max
= 30 },
166 .p1
= { .min
= 1, .max
= 3},
167 .p2
= { .dot_limit
= 270000,
173 static const intel_limit_t intel_limits_g4x_hdmi
= {
174 .dot
= { .min
= 22000, .max
= 400000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 16, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 5, .max
= 80 },
181 .p1
= { .min
= 1, .max
= 8},
182 .p2
= { .dot_limit
= 165000,
183 .p2_slow
= 10, .p2_fast
= 5 },
186 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
187 .dot
= { .min
= 20000, .max
= 115000 },
188 .vco
= { .min
= 1750000, .max
= 3500000 },
189 .n
= { .min
= 1, .max
= 3 },
190 .m
= { .min
= 104, .max
= 138 },
191 .m1
= { .min
= 17, .max
= 23 },
192 .m2
= { .min
= 5, .max
= 11 },
193 .p
= { .min
= 28, .max
= 112 },
194 .p1
= { .min
= 2, .max
= 8 },
195 .p2
= { .dot_limit
= 0,
196 .p2_slow
= 14, .p2_fast
= 14
200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
201 .dot
= { .min
= 80000, .max
= 224000 },
202 .vco
= { .min
= 1750000, .max
= 3500000 },
203 .n
= { .min
= 1, .max
= 3 },
204 .m
= { .min
= 104, .max
= 138 },
205 .m1
= { .min
= 17, .max
= 23 },
206 .m2
= { .min
= 5, .max
= 11 },
207 .p
= { .min
= 14, .max
= 42 },
208 .p1
= { .min
= 2, .max
= 6 },
209 .p2
= { .dot_limit
= 0,
210 .p2_slow
= 7, .p2_fast
= 7
214 static const intel_limit_t intel_limits_pineview_sdvo
= {
215 .dot
= { .min
= 20000, .max
= 400000},
216 .vco
= { .min
= 1700000, .max
= 3500000 },
217 /* Pineview's Ncounter is a ring counter */
218 .n
= { .min
= 3, .max
= 6 },
219 .m
= { .min
= 2, .max
= 256 },
220 /* Pineview only has one combined m divider, which we treat as m2. */
221 .m1
= { .min
= 0, .max
= 0 },
222 .m2
= { .min
= 0, .max
= 254 },
223 .p
= { .min
= 5, .max
= 80 },
224 .p1
= { .min
= 1, .max
= 8 },
225 .p2
= { .dot_limit
= 200000,
226 .p2_slow
= 10, .p2_fast
= 5 },
229 static const intel_limit_t intel_limits_pineview_lvds
= {
230 .dot
= { .min
= 20000, .max
= 400000 },
231 .vco
= { .min
= 1700000, .max
= 3500000 },
232 .n
= { .min
= 3, .max
= 6 },
233 .m
= { .min
= 2, .max
= 256 },
234 .m1
= { .min
= 0, .max
= 0 },
235 .m2
= { .min
= 0, .max
= 254 },
236 .p
= { .min
= 7, .max
= 112 },
237 .p1
= { .min
= 1, .max
= 8 },
238 .p2
= { .dot_limit
= 112000,
239 .p2_slow
= 14, .p2_fast
= 14 },
242 /* Ironlake / Sandybridge
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
247 static const intel_limit_t intel_limits_ironlake_dac
= {
248 .dot
= { .min
= 25000, .max
= 350000 },
249 .vco
= { .min
= 1760000, .max
= 3510000 },
250 .n
= { .min
= 1, .max
= 5 },
251 .m
= { .min
= 79, .max
= 127 },
252 .m1
= { .min
= 12, .max
= 22 },
253 .m2
= { .min
= 5, .max
= 9 },
254 .p
= { .min
= 5, .max
= 80 },
255 .p1
= { .min
= 1, .max
= 8 },
256 .p2
= { .dot_limit
= 225000,
257 .p2_slow
= 10, .p2_fast
= 5 },
260 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
261 .dot
= { .min
= 25000, .max
= 350000 },
262 .vco
= { .min
= 1760000, .max
= 3510000 },
263 .n
= { .min
= 1, .max
= 3 },
264 .m
= { .min
= 79, .max
= 118 },
265 .m1
= { .min
= 12, .max
= 22 },
266 .m2
= { .min
= 5, .max
= 9 },
267 .p
= { .min
= 28, .max
= 112 },
268 .p1
= { .min
= 2, .max
= 8 },
269 .p2
= { .dot_limit
= 225000,
270 .p2_slow
= 14, .p2_fast
= 14 },
273 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
274 .dot
= { .min
= 25000, .max
= 350000 },
275 .vco
= { .min
= 1760000, .max
= 3510000 },
276 .n
= { .min
= 1, .max
= 3 },
277 .m
= { .min
= 79, .max
= 127 },
278 .m1
= { .min
= 12, .max
= 22 },
279 .m2
= { .min
= 5, .max
= 9 },
280 .p
= { .min
= 14, .max
= 56 },
281 .p1
= { .min
= 2, .max
= 8 },
282 .p2
= { .dot_limit
= 225000,
283 .p2_slow
= 7, .p2_fast
= 7 },
286 /* LVDS 100mhz refclk limits. */
287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
288 .dot
= { .min
= 25000, .max
= 350000 },
289 .vco
= { .min
= 1760000, .max
= 3510000 },
290 .n
= { .min
= 1, .max
= 2 },
291 .m
= { .min
= 79, .max
= 126 },
292 .m1
= { .min
= 12, .max
= 22 },
293 .m2
= { .min
= 5, .max
= 9 },
294 .p
= { .min
= 28, .max
= 112 },
295 .p1
= { .min
= 2, .max
= 8 },
296 .p2
= { .dot_limit
= 225000,
297 .p2_slow
= 14, .p2_fast
= 14 },
300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 3 },
304 .m
= { .min
= 79, .max
= 126 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 14, .max
= 42 },
308 .p1
= { .min
= 2, .max
= 6 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 7, .p2_fast
= 7 },
313 static const intel_limit_t intel_limits_vlv_dac
= {
314 .dot
= { .min
= 25000, .max
= 270000 },
315 .vco
= { .min
= 4000000, .max
= 6000000 },
316 .n
= { .min
= 1, .max
= 7 },
317 .m
= { .min
= 22, .max
= 450 }, /* guess */
318 .m1
= { .min
= 2, .max
= 3 },
319 .m2
= { .min
= 11, .max
= 156 },
320 .p
= { .min
= 10, .max
= 30 },
321 .p1
= { .min
= 1, .max
= 3 },
322 .p2
= { .dot_limit
= 270000,
323 .p2_slow
= 2, .p2_fast
= 20 },
326 static const intel_limit_t intel_limits_vlv_hdmi
= {
327 .dot
= { .min
= 25000, .max
= 270000 },
328 .vco
= { .min
= 4000000, .max
= 6000000 },
329 .n
= { .min
= 1, .max
= 7 },
330 .m
= { .min
= 60, .max
= 300 }, /* guess */
331 .m1
= { .min
= 2, .max
= 3 },
332 .m2
= { .min
= 11, .max
= 156 },
333 .p
= { .min
= 10, .max
= 30 },
334 .p1
= { .min
= 2, .max
= 3 },
335 .p2
= { .dot_limit
= 270000,
336 .p2_slow
= 2, .p2_fast
= 20 },
339 static const intel_limit_t intel_limits_vlv_dp
= {
340 .dot
= { .min
= 25000, .max
= 270000 },
341 .vco
= { .min
= 4000000, .max
= 6000000 },
342 .n
= { .min
= 1, .max
= 7 },
343 .m
= { .min
= 22, .max
= 450 },
344 .m1
= { .min
= 2, .max
= 3 },
345 .m2
= { .min
= 11, .max
= 156 },
346 .p
= { .min
= 10, .max
= 30 },
347 .p1
= { .min
= 1, .max
= 3 },
348 .p2
= { .dot_limit
= 270000,
349 .p2_slow
= 2, .p2_fast
= 20 },
352 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
355 struct drm_device
*dev
= crtc
->dev
;
356 const intel_limit_t
*limit
;
358 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
359 if (intel_is_dual_link_lvds(dev
)) {
360 if (refclk
== 100000)
361 limit
= &intel_limits_ironlake_dual_lvds_100m
;
363 limit
= &intel_limits_ironlake_dual_lvds
;
365 if (refclk
== 100000)
366 limit
= &intel_limits_ironlake_single_lvds_100m
;
368 limit
= &intel_limits_ironlake_single_lvds
;
371 limit
= &intel_limits_ironlake_dac
;
376 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
378 struct drm_device
*dev
= crtc
->dev
;
379 const intel_limit_t
*limit
;
381 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
382 if (intel_is_dual_link_lvds(dev
))
383 limit
= &intel_limits_g4x_dual_channel_lvds
;
385 limit
= &intel_limits_g4x_single_channel_lvds
;
386 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
387 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
388 limit
= &intel_limits_g4x_hdmi
;
389 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
390 limit
= &intel_limits_g4x_sdvo
;
391 } else /* The option is for other outputs */
392 limit
= &intel_limits_i9xx_sdvo
;
397 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
399 struct drm_device
*dev
= crtc
->dev
;
400 const intel_limit_t
*limit
;
402 if (HAS_PCH_SPLIT(dev
))
403 limit
= intel_ironlake_limit(crtc
, refclk
);
404 else if (IS_G4X(dev
)) {
405 limit
= intel_g4x_limit(crtc
);
406 } else if (IS_PINEVIEW(dev
)) {
407 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
408 limit
= &intel_limits_pineview_lvds
;
410 limit
= &intel_limits_pineview_sdvo
;
411 } else if (IS_VALLEYVIEW(dev
)) {
412 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
413 limit
= &intel_limits_vlv_dac
;
414 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
415 limit
= &intel_limits_vlv_hdmi
;
417 limit
= &intel_limits_vlv_dp
;
418 } else if (!IS_GEN2(dev
)) {
419 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
420 limit
= &intel_limits_i9xx_lvds
;
422 limit
= &intel_limits_i9xx_sdvo
;
424 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
425 limit
= &intel_limits_i8xx_lvds
;
426 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
427 limit
= &intel_limits_i8xx_dvo
;
429 limit
= &intel_limits_i8xx_dac
;
434 /* m1 is reserved as 0 in Pineview, n is a ring counter */
435 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
437 clock
->m
= clock
->m2
+ 2;
438 clock
->p
= clock
->p1
* clock
->p2
;
439 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
440 clock
->dot
= clock
->vco
/ clock
->p
;
443 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
445 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
448 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
450 clock
->m
= i9xx_dpll_compute_m(clock
);
451 clock
->p
= clock
->p1
* clock
->p2
;
452 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
453 clock
->dot
= clock
->vco
/ clock
->p
;
457 * Returns whether any output on the specified pipe is of the specified type
459 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
461 struct drm_device
*dev
= crtc
->dev
;
462 struct intel_encoder
*encoder
;
464 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
465 if (encoder
->type
== type
)
471 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
473 * Returns whether the given set of divisors are valid for a given refclk with
474 * the given connectors.
477 static bool intel_PLL_is_valid(struct drm_device
*dev
,
478 const intel_limit_t
*limit
,
479 const intel_clock_t
*clock
)
481 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
482 INTELPllInvalid("p1 out of range\n");
483 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
484 INTELPllInvalid("p out of range\n");
485 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
486 INTELPllInvalid("m2 out of range\n");
487 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
488 INTELPllInvalid("m1 out of range\n");
489 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
490 INTELPllInvalid("m1 <= m2\n");
491 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
492 INTELPllInvalid("m out of range\n");
493 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
494 INTELPllInvalid("n out of range\n");
495 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
496 INTELPllInvalid("vco out of range\n");
497 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
498 * connector, etc., rather than just a single range.
500 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
501 INTELPllInvalid("dot out of range\n");
507 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
508 int target
, int refclk
, intel_clock_t
*match_clock
,
509 intel_clock_t
*best_clock
)
511 struct drm_device
*dev
= crtc
->dev
;
515 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
517 * For LVDS just rely on its current settings for dual-channel.
518 * We haven't figured out how to reliably set up different
519 * single/dual channel state, if we even can.
521 if (intel_is_dual_link_lvds(dev
))
522 clock
.p2
= limit
->p2
.p2_fast
;
524 clock
.p2
= limit
->p2
.p2_slow
;
526 if (target
< limit
->p2
.dot_limit
)
527 clock
.p2
= limit
->p2
.p2_slow
;
529 clock
.p2
= limit
->p2
.p2_fast
;
532 memset(best_clock
, 0, sizeof(*best_clock
));
534 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
536 for (clock
.m2
= limit
->m2
.min
;
537 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
538 if (clock
.m2
>= clock
.m1
)
540 for (clock
.n
= limit
->n
.min
;
541 clock
.n
<= limit
->n
.max
; clock
.n
++) {
542 for (clock
.p1
= limit
->p1
.min
;
543 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
546 i9xx_clock(refclk
, &clock
);
547 if (!intel_PLL_is_valid(dev
, limit
,
551 clock
.p
!= match_clock
->p
)
554 this_err
= abs(clock
.dot
- target
);
555 if (this_err
< err
) {
564 return (err
!= target
);
568 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
569 int target
, int refclk
, intel_clock_t
*match_clock
,
570 intel_clock_t
*best_clock
)
572 struct drm_device
*dev
= crtc
->dev
;
576 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
578 * For LVDS just rely on its current settings for dual-channel.
579 * We haven't figured out how to reliably set up different
580 * single/dual channel state, if we even can.
582 if (intel_is_dual_link_lvds(dev
))
583 clock
.p2
= limit
->p2
.p2_fast
;
585 clock
.p2
= limit
->p2
.p2_slow
;
587 if (target
< limit
->p2
.dot_limit
)
588 clock
.p2
= limit
->p2
.p2_slow
;
590 clock
.p2
= limit
->p2
.p2_fast
;
593 memset(best_clock
, 0, sizeof(*best_clock
));
595 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
597 for (clock
.m2
= limit
->m2
.min
;
598 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
599 for (clock
.n
= limit
->n
.min
;
600 clock
.n
<= limit
->n
.max
; clock
.n
++) {
601 for (clock
.p1
= limit
->p1
.min
;
602 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
605 pineview_clock(refclk
, &clock
);
606 if (!intel_PLL_is_valid(dev
, limit
,
610 clock
.p
!= match_clock
->p
)
613 this_err
= abs(clock
.dot
- target
);
614 if (this_err
< err
) {
623 return (err
!= target
);
627 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
628 int target
, int refclk
, intel_clock_t
*match_clock
,
629 intel_clock_t
*best_clock
)
631 struct drm_device
*dev
= crtc
->dev
;
635 /* approximately equals target * 0.00585 */
636 int err_most
= (target
>> 8) + (target
>> 9);
639 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
640 if (intel_is_dual_link_lvds(dev
))
641 clock
.p2
= limit
->p2
.p2_fast
;
643 clock
.p2
= limit
->p2
.p2_slow
;
645 if (target
< limit
->p2
.dot_limit
)
646 clock
.p2
= limit
->p2
.p2_slow
;
648 clock
.p2
= limit
->p2
.p2_fast
;
651 memset(best_clock
, 0, sizeof(*best_clock
));
652 max_n
= limit
->n
.max
;
653 /* based on hardware requirement, prefer smaller n to precision */
654 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
655 /* based on hardware requirement, prefere larger m1,m2 */
656 for (clock
.m1
= limit
->m1
.max
;
657 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
658 for (clock
.m2
= limit
->m2
.max
;
659 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
660 for (clock
.p1
= limit
->p1
.max
;
661 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
664 i9xx_clock(refclk
, &clock
);
665 if (!intel_PLL_is_valid(dev
, limit
,
669 this_err
= abs(clock
.dot
- target
);
670 if (this_err
< err_most
) {
684 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
685 int target
, int refclk
, intel_clock_t
*match_clock
,
686 intel_clock_t
*best_clock
)
688 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
690 u32 updrate
, minupdate
, fracbits
, p
;
691 unsigned long bestppm
, ppm
, absppm
;
695 dotclk
= target
* 1000;
698 fastclk
= dotclk
/ (2*100);
702 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
703 bestm1
= bestm2
= bestp1
= bestp2
= 0;
705 /* based on hardware requirement, prefer smaller n to precision */
706 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
707 updrate
= refclk
/ n
;
708 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
709 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
713 /* based on hardware requirement, prefer bigger m1,m2 values */
714 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
715 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
716 refclk
) / (2*refclk
));
719 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
720 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
721 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
722 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
726 if (absppm
< bestppm
- 10) {
743 best_clock
->n
= bestn
;
744 best_clock
->m1
= bestm1
;
745 best_clock
->m2
= bestm2
;
746 best_clock
->p1
= bestp1
;
747 best_clock
->p2
= bestp2
;
752 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
755 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
756 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
758 return intel_crtc
->config
.cpu_transcoder
;
761 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
764 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
766 frame
= I915_READ(frame_reg
);
768 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
769 DRM_DEBUG_KMS("vblank wait timed out\n");
773 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @pipe: pipe to wait for
777 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
783 int pipestat_reg
= PIPESTAT(pipe
);
785 if (INTEL_INFO(dev
)->gen
>= 5) {
786 ironlake_wait_for_vblank(dev
, pipe
);
790 /* Clear existing vblank status. Note this will clear any other
791 * sticky status fields as well.
793 * This races with i915_driver_irq_handler() with the result
794 * that either function could miss a vblank event. Here it is not
795 * fatal, as we will either wait upon the next vblank interrupt or
796 * timeout. Generally speaking intel_wait_for_vblank() is only
797 * called during modeset at which time the GPU should be idle and
798 * should *not* be performing page flips and thus not waiting on
800 * Currently, the result of us stealing a vblank from the irq
801 * handler is that a single frame will be skipped during swapbuffers.
803 I915_WRITE(pipestat_reg
,
804 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
806 /* Wait for vblank interrupt bit to set */
807 if (wait_for(I915_READ(pipestat_reg
) &
808 PIPE_VBLANK_INTERRUPT_STATUS
,
810 DRM_DEBUG_KMS("vblank wait timed out\n");
814 * intel_wait_for_pipe_off - wait for pipe to turn off
816 * @pipe: pipe to wait for
818 * After disabling a pipe, we can't wait for vblank in the usual way,
819 * spinning on the vblank interrupt status bit, since we won't actually
820 * see an interrupt when the pipe is disabled.
823 * wait for the pipe register state bit to turn off
826 * wait for the display line value to settle (it usually
827 * ends up stopping at the start of the next frame).
830 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
833 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
836 if (INTEL_INFO(dev
)->gen
>= 4) {
837 int reg
= PIPECONF(cpu_transcoder
);
839 /* Wait for the Pipe State to go off */
840 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
842 WARN(1, "pipe_off wait timed out\n");
844 u32 last_line
, line_mask
;
845 int reg
= PIPEDSL(pipe
);
846 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
849 line_mask
= DSL_LINEMASK_GEN2
;
851 line_mask
= DSL_LINEMASK_GEN3
;
853 /* Wait for the display line to settle */
855 last_line
= I915_READ(reg
) & line_mask
;
857 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
858 time_after(timeout
, jiffies
));
859 if (time_after(jiffies
, timeout
))
860 WARN(1, "pipe_off wait timed out\n");
865 * ibx_digital_port_connected - is the specified port connected?
866 * @dev_priv: i915 private structure
867 * @port: the port to test
869 * Returns true if @port is connected, false otherwise.
871 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
872 struct intel_digital_port
*port
)
876 if (HAS_PCH_IBX(dev_priv
->dev
)) {
879 bit
= SDE_PORTB_HOTPLUG
;
882 bit
= SDE_PORTC_HOTPLUG
;
885 bit
= SDE_PORTD_HOTPLUG
;
893 bit
= SDE_PORTB_HOTPLUG_CPT
;
896 bit
= SDE_PORTC_HOTPLUG_CPT
;
899 bit
= SDE_PORTD_HOTPLUG_CPT
;
906 return I915_READ(SDEISR
) & bit
;
909 static const char *state_string(bool enabled
)
911 return enabled
? "on" : "off";
914 /* Only for pre-ILK configs */
915 void assert_pll(struct drm_i915_private
*dev_priv
,
916 enum pipe pipe
, bool state
)
923 val
= I915_READ(reg
);
924 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
925 WARN(cur_state
!= state
,
926 "PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state
), state_string(cur_state
));
930 struct intel_shared_dpll
*
931 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
933 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
935 if (crtc
->config
.shared_dpll
< 0)
938 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
942 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
943 struct intel_shared_dpll
*pll
,
947 struct intel_dpll_hw_state hw_state
;
949 if (HAS_PCH_LPT(dev_priv
->dev
)) {
950 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
955 "asserting DPLL %s with no DPLL\n", state_string(state
)))
958 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
959 WARN(cur_state
!= state
,
960 "%s assertion failure (expected %s, current %s)\n",
961 pll
->name
, state_string(state
), state_string(cur_state
));
964 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
965 enum pipe pipe
, bool state
)
970 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
973 if (HAS_DDI(dev_priv
->dev
)) {
974 /* DDI does not have a specific FDI_TX register */
975 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
976 val
= I915_READ(reg
);
977 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
979 reg
= FDI_TX_CTL(pipe
);
980 val
= I915_READ(reg
);
981 cur_state
= !!(val
& FDI_TX_ENABLE
);
983 WARN(cur_state
!= state
,
984 "FDI TX state assertion failure (expected %s, current %s)\n",
985 state_string(state
), state_string(cur_state
));
987 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
988 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
990 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
991 enum pipe pipe
, bool state
)
997 reg
= FDI_RX_CTL(pipe
);
998 val
= I915_READ(reg
);
999 cur_state
= !!(val
& FDI_RX_ENABLE
);
1000 WARN(cur_state
!= state
,
1001 "FDI RX state assertion failure (expected %s, current %s)\n",
1002 state_string(state
), state_string(cur_state
));
1004 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1007 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1013 /* ILK FDI PLL is always enabled */
1014 if (dev_priv
->info
->gen
== 5)
1017 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1018 if (HAS_DDI(dev_priv
->dev
))
1021 reg
= FDI_TX_CTL(pipe
);
1022 val
= I915_READ(reg
);
1023 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1027 enum pipe pipe
, bool state
)
1033 reg
= FDI_RX_CTL(pipe
);
1034 val
= I915_READ(reg
);
1035 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1036 WARN(cur_state
!= state
,
1037 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038 state_string(state
), state_string(cur_state
));
1041 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1044 int pp_reg
, lvds_reg
;
1046 enum pipe panel_pipe
= PIPE_A
;
1049 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1050 pp_reg
= PCH_PP_CONTROL
;
1051 lvds_reg
= PCH_LVDS
;
1053 pp_reg
= PP_CONTROL
;
1057 val
= I915_READ(pp_reg
);
1058 if (!(val
& PANEL_POWER_ON
) ||
1059 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1062 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1063 panel_pipe
= PIPE_B
;
1065 WARN(panel_pipe
== pipe
&& locked
,
1066 "panel assertion failure, pipe %c regs locked\n",
1070 void assert_pipe(struct drm_i915_private
*dev_priv
,
1071 enum pipe pipe
, bool state
)
1076 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1079 /* if we need the pipe A quirk it must be always on */
1080 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1083 if (!intel_display_power_enabled(dev_priv
->dev
,
1084 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1087 reg
= PIPECONF(cpu_transcoder
);
1088 val
= I915_READ(reg
);
1089 cur_state
= !!(val
& PIPECONF_ENABLE
);
1092 WARN(cur_state
!= state
,
1093 "pipe %c assertion failure (expected %s, current %s)\n",
1094 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1097 static void assert_plane(struct drm_i915_private
*dev_priv
,
1098 enum plane plane
, bool state
)
1104 reg
= DSPCNTR(plane
);
1105 val
= I915_READ(reg
);
1106 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1107 WARN(cur_state
!= state
,
1108 "plane %c assertion failure (expected %s, current %s)\n",
1109 plane_name(plane
), state_string(state
), state_string(cur_state
));
1112 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1115 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1118 struct drm_device
*dev
= dev_priv
->dev
;
1123 /* Primary planes are fixed to pipes on gen4+ */
1124 if (INTEL_INFO(dev
)->gen
>= 4) {
1125 reg
= DSPCNTR(pipe
);
1126 val
= I915_READ(reg
);
1127 WARN((val
& DISPLAY_PLANE_ENABLE
),
1128 "plane %c assertion failure, should be disabled but not\n",
1133 /* Need to check both planes against the pipe */
1136 val
= I915_READ(reg
);
1137 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1138 DISPPLANE_SEL_PIPE_SHIFT
;
1139 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1140 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141 plane_name(i
), pipe_name(pipe
));
1145 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1148 struct drm_device
*dev
= dev_priv
->dev
;
1152 if (IS_VALLEYVIEW(dev
)) {
1153 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1154 reg
= SPCNTR(pipe
, i
);
1155 val
= I915_READ(reg
);
1156 WARN((val
& SP_ENABLE
),
1157 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158 sprite_name(pipe
, i
), pipe_name(pipe
));
1160 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1162 val
= I915_READ(reg
);
1163 WARN((val
& SPRITE_ENABLE
),
1164 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1165 plane_name(pipe
), pipe_name(pipe
));
1166 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1167 reg
= DVSCNTR(pipe
);
1168 val
= I915_READ(reg
);
1169 WARN((val
& DVS_ENABLE
),
1170 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1171 plane_name(pipe
), pipe_name(pipe
));
1175 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1180 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1181 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1185 val
= I915_READ(PCH_DREF_CONTROL
);
1186 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1187 DREF_SUPERSPREAD_SOURCE_MASK
));
1188 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1191 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1198 reg
= PCH_TRANSCONF(pipe
);
1199 val
= I915_READ(reg
);
1200 enabled
= !!(val
& TRANS_ENABLE
);
1202 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1206 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1207 enum pipe pipe
, u32 port_sel
, u32 val
)
1209 if ((val
& DP_PORT_EN
) == 0)
1212 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1213 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1214 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1215 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1218 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1224 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1225 enum pipe pipe
, u32 val
)
1227 if ((val
& SDVO_ENABLE
) == 0)
1230 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1231 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1234 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1240 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1241 enum pipe pipe
, u32 val
)
1243 if ((val
& LVDS_PORT_EN
) == 0)
1246 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1247 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1250 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1256 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1257 enum pipe pipe
, u32 val
)
1259 if ((val
& ADPA_DAC_ENABLE
) == 0)
1261 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1262 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1265 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1271 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1272 enum pipe pipe
, int reg
, u32 port_sel
)
1274 u32 val
= I915_READ(reg
);
1275 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1276 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1277 reg
, pipe_name(pipe
));
1279 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1280 && (val
& DP_PIPEB_SELECT
),
1281 "IBX PCH dp port still using transcoder B\n");
1284 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1285 enum pipe pipe
, int reg
)
1287 u32 val
= I915_READ(reg
);
1288 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1289 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1290 reg
, pipe_name(pipe
));
1292 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1293 && (val
& SDVO_PIPE_B_SELECT
),
1294 "IBX PCH hdmi port still using transcoder B\n");
1297 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1303 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1304 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1305 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1308 val
= I915_READ(reg
);
1309 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1310 "PCH VGA enabled on transcoder %c, should be disabled\n",
1314 val
= I915_READ(reg
);
1315 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1316 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1319 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1320 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1321 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1324 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1326 struct drm_device
*dev
= crtc
->base
.dev
;
1327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1328 int reg
= DPLL(crtc
->pipe
);
1329 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1331 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1333 /* No really, not for ILK+ */
1334 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1336 /* PLL is protected by panel, make sure we can write it */
1337 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1338 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1340 I915_WRITE(reg
, dpll
);
1344 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1345 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1347 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1348 POSTING_READ(DPLL_MD(crtc
->pipe
));
1350 /* We do this three times for luck */
1351 I915_WRITE(reg
, dpll
);
1353 udelay(150); /* wait for warmup */
1354 I915_WRITE(reg
, dpll
);
1356 udelay(150); /* wait for warmup */
1357 I915_WRITE(reg
, dpll
);
1359 udelay(150); /* wait for warmup */
1362 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1364 struct drm_device
*dev
= crtc
->base
.dev
;
1365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1366 int reg
= DPLL(crtc
->pipe
);
1367 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1369 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1371 /* No really, not for ILK+ */
1372 BUG_ON(dev_priv
->info
->gen
>= 5);
1374 /* PLL is protected by panel, make sure we can write it */
1375 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1376 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1378 I915_WRITE(reg
, dpll
);
1380 /* Wait for the clocks to stabilize. */
1384 if (INTEL_INFO(dev
)->gen
>= 4) {
1385 I915_WRITE(DPLL_MD(crtc
->pipe
),
1386 crtc
->config
.dpll_hw_state
.dpll_md
);
1388 /* The pixel multiplier can only be updated once the
1389 * DPLL is enabled and the clocks are stable.
1391 * So write it again.
1393 I915_WRITE(reg
, dpll
);
1396 /* We do this three times for luck */
1397 I915_WRITE(reg
, dpll
);
1399 udelay(150); /* wait for warmup */
1400 I915_WRITE(reg
, dpll
);
1402 udelay(150); /* wait for warmup */
1403 I915_WRITE(reg
, dpll
);
1405 udelay(150); /* wait for warmup */
1409 * i9xx_disable_pll - disable a PLL
1410 * @dev_priv: i915 private structure
1411 * @pipe: pipe PLL to disable
1413 * Disable the PLL for @pipe, making sure the pipe is off first.
1415 * Note! This is for pre-ILK only.
1417 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1419 /* Don't disable pipe A or pipe A PLLs if needed */
1420 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1423 /* Make sure the pipe isn't still relying on us */
1424 assert_pipe_disabled(dev_priv
, pipe
);
1426 I915_WRITE(DPLL(pipe
), 0);
1427 POSTING_READ(DPLL(pipe
));
1430 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1435 port_mask
= DPLL_PORTB_READY_MASK
;
1437 port_mask
= DPLL_PORTC_READY_MASK
;
1439 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1440 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1441 'B' + port
, I915_READ(DPLL(0)));
1445 * ironlake_enable_shared_dpll - enable PCH PLL
1446 * @dev_priv: i915 private structure
1447 * @pipe: pipe PLL to enable
1449 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1450 * drives the transcoder clock.
1452 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1454 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1455 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1457 /* PCH PLLs only available on ILK, SNB and IVB */
1458 BUG_ON(dev_priv
->info
->gen
< 5);
1459 if (WARN_ON(pll
== NULL
))
1462 if (WARN_ON(pll
->refcount
== 0))
1465 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1466 pll
->name
, pll
->active
, pll
->on
,
1467 crtc
->base
.base
.id
);
1469 if (pll
->active
++) {
1471 assert_shared_dpll_enabled(dev_priv
, pll
);
1476 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1477 pll
->enable(dev_priv
, pll
);
1481 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1483 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1484 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv
->info
->gen
< 5);
1488 if (WARN_ON(pll
== NULL
))
1491 if (WARN_ON(pll
->refcount
== 0))
1494 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1495 pll
->name
, pll
->active
, pll
->on
,
1496 crtc
->base
.base
.id
);
1498 if (WARN_ON(pll
->active
== 0)) {
1499 assert_shared_dpll_disabled(dev_priv
, pll
);
1503 assert_shared_dpll_enabled(dev_priv
, pll
);
1508 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1509 pll
->disable(dev_priv
, pll
);
1513 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1516 struct drm_device
*dev
= dev_priv
->dev
;
1517 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1518 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1519 uint32_t reg
, val
, pipeconf_val
;
1521 /* PCH only available on ILK+ */
1522 BUG_ON(dev_priv
->info
->gen
< 5);
1524 /* Make sure PCH DPLL is enabled */
1525 assert_shared_dpll_enabled(dev_priv
,
1526 intel_crtc_to_shared_dpll(intel_crtc
));
1528 /* FDI must be feeding us bits for PCH ports */
1529 assert_fdi_tx_enabled(dev_priv
, pipe
);
1530 assert_fdi_rx_enabled(dev_priv
, pipe
);
1532 if (HAS_PCH_CPT(dev
)) {
1533 /* Workaround: Set the timing override bit before enabling the
1534 * pch transcoder. */
1535 reg
= TRANS_CHICKEN2(pipe
);
1536 val
= I915_READ(reg
);
1537 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1538 I915_WRITE(reg
, val
);
1541 reg
= PCH_TRANSCONF(pipe
);
1542 val
= I915_READ(reg
);
1543 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1545 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1547 * make the BPC in transcoder be consistent with
1548 * that in pipeconf reg.
1550 val
&= ~PIPECONF_BPC_MASK
;
1551 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1554 val
&= ~TRANS_INTERLACE_MASK
;
1555 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1556 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1557 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1558 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1560 val
|= TRANS_INTERLACED
;
1562 val
|= TRANS_PROGRESSIVE
;
1564 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1565 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1566 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1569 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1570 enum transcoder cpu_transcoder
)
1572 u32 val
, pipeconf_val
;
1574 /* PCH only available on ILK+ */
1575 BUG_ON(dev_priv
->info
->gen
< 5);
1577 /* FDI must be feeding us bits for PCH ports */
1578 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1579 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1581 /* Workaround: set timing override bit. */
1582 val
= I915_READ(_TRANSA_CHICKEN2
);
1583 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1584 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1587 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1589 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1590 PIPECONF_INTERLACED_ILK
)
1591 val
|= TRANS_INTERLACED
;
1593 val
|= TRANS_PROGRESSIVE
;
1595 I915_WRITE(LPT_TRANSCONF
, val
);
1596 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1597 DRM_ERROR("Failed to enable PCH transcoder\n");
1600 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1603 struct drm_device
*dev
= dev_priv
->dev
;
1606 /* FDI relies on the transcoder */
1607 assert_fdi_tx_disabled(dev_priv
, pipe
);
1608 assert_fdi_rx_disabled(dev_priv
, pipe
);
1610 /* Ports must be off as well */
1611 assert_pch_ports_disabled(dev_priv
, pipe
);
1613 reg
= PCH_TRANSCONF(pipe
);
1614 val
= I915_READ(reg
);
1615 val
&= ~TRANS_ENABLE
;
1616 I915_WRITE(reg
, val
);
1617 /* wait for PCH transcoder off, transcoder state */
1618 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1619 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1621 if (!HAS_PCH_IBX(dev
)) {
1622 /* Workaround: Clear the timing override chicken bit again. */
1623 reg
= TRANS_CHICKEN2(pipe
);
1624 val
= I915_READ(reg
);
1625 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1626 I915_WRITE(reg
, val
);
1630 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1634 val
= I915_READ(LPT_TRANSCONF
);
1635 val
&= ~TRANS_ENABLE
;
1636 I915_WRITE(LPT_TRANSCONF
, val
);
1637 /* wait for PCH transcoder off, transcoder state */
1638 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1639 DRM_ERROR("Failed to disable PCH transcoder\n");
1641 /* Workaround: clear timing override bit. */
1642 val
= I915_READ(_TRANSA_CHICKEN2
);
1643 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1644 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1648 * intel_enable_pipe - enable a pipe, asserting requirements
1649 * @dev_priv: i915 private structure
1650 * @pipe: pipe to enable
1651 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1653 * Enable @pipe, making sure that various hardware specific requirements
1654 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1656 * @pipe should be %PIPE_A or %PIPE_B.
1658 * Will wait until the pipe is actually running (i.e. first vblank) before
1661 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1664 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1666 enum pipe pch_transcoder
;
1670 assert_planes_disabled(dev_priv
, pipe
);
1671 assert_sprites_disabled(dev_priv
, pipe
);
1673 if (HAS_PCH_LPT(dev_priv
->dev
))
1674 pch_transcoder
= TRANSCODER_A
;
1676 pch_transcoder
= pipe
;
1679 * A pipe without a PLL won't actually be able to drive bits from
1680 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1683 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1684 assert_pll_enabled(dev_priv
, pipe
);
1687 /* if driving the PCH, we need FDI enabled */
1688 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1689 assert_fdi_tx_pll_enabled(dev_priv
,
1690 (enum pipe
) cpu_transcoder
);
1692 /* FIXME: assert CPU port conditions for SNB+ */
1695 reg
= PIPECONF(cpu_transcoder
);
1696 val
= I915_READ(reg
);
1697 if (val
& PIPECONF_ENABLE
)
1700 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1701 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1705 * intel_disable_pipe - disable a pipe, asserting requirements
1706 * @dev_priv: i915 private structure
1707 * @pipe: pipe to disable
1709 * Disable @pipe, making sure that various hardware specific requirements
1710 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1712 * @pipe should be %PIPE_A or %PIPE_B.
1714 * Will wait until the pipe has shut down before returning.
1716 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1719 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1725 * Make sure planes won't keep trying to pump pixels to us,
1726 * or we might hang the display.
1728 assert_planes_disabled(dev_priv
, pipe
);
1729 assert_sprites_disabled(dev_priv
, pipe
);
1731 /* Don't disable pipe A or pipe A PLLs if needed */
1732 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1735 reg
= PIPECONF(cpu_transcoder
);
1736 val
= I915_READ(reg
);
1737 if ((val
& PIPECONF_ENABLE
) == 0)
1740 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1741 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1745 * Plane regs are double buffered, going from enabled->disabled needs a
1746 * trigger in order to latch. The display address reg provides this.
1748 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1751 if (dev_priv
->info
->gen
>= 4)
1752 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1754 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1758 * intel_enable_plane - enable a display plane on a given pipe
1759 * @dev_priv: i915 private structure
1760 * @plane: plane to enable
1761 * @pipe: pipe being fed
1763 * Enable @plane on @pipe, making sure that @pipe is running first.
1765 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1766 enum plane plane
, enum pipe pipe
)
1771 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1772 assert_pipe_enabled(dev_priv
, pipe
);
1774 reg
= DSPCNTR(plane
);
1775 val
= I915_READ(reg
);
1776 if (val
& DISPLAY_PLANE_ENABLE
)
1779 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1780 intel_flush_display_plane(dev_priv
, plane
);
1781 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1785 * intel_disable_plane - disable a display plane
1786 * @dev_priv: i915 private structure
1787 * @plane: plane to disable
1788 * @pipe: pipe consuming the data
1790 * Disable @plane; should be an independent operation.
1792 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1793 enum plane plane
, enum pipe pipe
)
1798 reg
= DSPCNTR(plane
);
1799 val
= I915_READ(reg
);
1800 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1803 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1804 intel_flush_display_plane(dev_priv
, plane
);
1805 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1808 static bool need_vtd_wa(struct drm_device
*dev
)
1810 #ifdef CONFIG_INTEL_IOMMU
1811 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1818 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1819 struct drm_i915_gem_object
*obj
,
1820 struct intel_ring_buffer
*pipelined
)
1822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1826 switch (obj
->tiling_mode
) {
1827 case I915_TILING_NONE
:
1828 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1829 alignment
= 128 * 1024;
1830 else if (INTEL_INFO(dev
)->gen
>= 4)
1831 alignment
= 4 * 1024;
1833 alignment
= 64 * 1024;
1836 /* pin() will align the object as required by fence */
1840 /* Despite that we check this in framebuffer_init userspace can
1841 * screw us over and change the tiling after the fact. Only
1842 * pinned buffers can't change their tiling. */
1843 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1849 /* Note that the w/a also requires 64 PTE of padding following the
1850 * bo. We currently fill all unused PTE with the shadow page and so
1851 * we should always have valid PTE following the scanout preventing
1854 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1855 alignment
= 256 * 1024;
1857 dev_priv
->mm
.interruptible
= false;
1858 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1860 goto err_interruptible
;
1862 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1863 * fence, whereas 965+ only requires a fence if using
1864 * framebuffer compression. For simplicity, we always install
1865 * a fence as the cost is not that onerous.
1867 ret
= i915_gem_object_get_fence(obj
);
1871 i915_gem_object_pin_fence(obj
);
1873 dev_priv
->mm
.interruptible
= true;
1877 i915_gem_object_unpin(obj
);
1879 dev_priv
->mm
.interruptible
= true;
1883 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1885 i915_gem_object_unpin_fence(obj
);
1886 i915_gem_object_unpin(obj
);
1889 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1890 * is assumed to be a power-of-two. */
1891 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1892 unsigned int tiling_mode
,
1896 if (tiling_mode
!= I915_TILING_NONE
) {
1897 unsigned int tile_rows
, tiles
;
1902 tiles
= *x
/ (512/cpp
);
1905 return tile_rows
* pitch
* 8 + tiles
* 4096;
1907 unsigned int offset
;
1909 offset
= *y
* pitch
+ *x
* cpp
;
1911 *x
= (offset
& 4095) / cpp
;
1912 return offset
& -4096;
1916 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1919 struct drm_device
*dev
= crtc
->dev
;
1920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1922 struct intel_framebuffer
*intel_fb
;
1923 struct drm_i915_gem_object
*obj
;
1924 int plane
= intel_crtc
->plane
;
1925 unsigned long linear_offset
;
1934 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1938 intel_fb
= to_intel_framebuffer(fb
);
1939 obj
= intel_fb
->obj
;
1941 reg
= DSPCNTR(plane
);
1942 dspcntr
= I915_READ(reg
);
1943 /* Mask out pixel format bits in case we change it */
1944 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1945 switch (fb
->pixel_format
) {
1947 dspcntr
|= DISPPLANE_8BPP
;
1949 case DRM_FORMAT_XRGB1555
:
1950 case DRM_FORMAT_ARGB1555
:
1951 dspcntr
|= DISPPLANE_BGRX555
;
1953 case DRM_FORMAT_RGB565
:
1954 dspcntr
|= DISPPLANE_BGRX565
;
1956 case DRM_FORMAT_XRGB8888
:
1957 case DRM_FORMAT_ARGB8888
:
1958 dspcntr
|= DISPPLANE_BGRX888
;
1960 case DRM_FORMAT_XBGR8888
:
1961 case DRM_FORMAT_ABGR8888
:
1962 dspcntr
|= DISPPLANE_RGBX888
;
1964 case DRM_FORMAT_XRGB2101010
:
1965 case DRM_FORMAT_ARGB2101010
:
1966 dspcntr
|= DISPPLANE_BGRX101010
;
1968 case DRM_FORMAT_XBGR2101010
:
1969 case DRM_FORMAT_ABGR2101010
:
1970 dspcntr
|= DISPPLANE_RGBX101010
;
1976 if (INTEL_INFO(dev
)->gen
>= 4) {
1977 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1978 dspcntr
|= DISPPLANE_TILED
;
1980 dspcntr
&= ~DISPPLANE_TILED
;
1984 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1986 I915_WRITE(reg
, dspcntr
);
1988 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1990 if (INTEL_INFO(dev
)->gen
>= 4) {
1991 intel_crtc
->dspaddr_offset
=
1992 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
1993 fb
->bits_per_pixel
/ 8,
1995 linear_offset
-= intel_crtc
->dspaddr_offset
;
1997 intel_crtc
->dspaddr_offset
= linear_offset
;
2000 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2001 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2003 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2004 if (INTEL_INFO(dev
)->gen
>= 4) {
2005 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2006 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2007 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2008 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2010 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2016 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2017 struct drm_framebuffer
*fb
, int x
, int y
)
2019 struct drm_device
*dev
= crtc
->dev
;
2020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2021 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2022 struct intel_framebuffer
*intel_fb
;
2023 struct drm_i915_gem_object
*obj
;
2024 int plane
= intel_crtc
->plane
;
2025 unsigned long linear_offset
;
2035 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2039 intel_fb
= to_intel_framebuffer(fb
);
2040 obj
= intel_fb
->obj
;
2042 reg
= DSPCNTR(plane
);
2043 dspcntr
= I915_READ(reg
);
2044 /* Mask out pixel format bits in case we change it */
2045 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2046 switch (fb
->pixel_format
) {
2048 dspcntr
|= DISPPLANE_8BPP
;
2050 case DRM_FORMAT_RGB565
:
2051 dspcntr
|= DISPPLANE_BGRX565
;
2053 case DRM_FORMAT_XRGB8888
:
2054 case DRM_FORMAT_ARGB8888
:
2055 dspcntr
|= DISPPLANE_BGRX888
;
2057 case DRM_FORMAT_XBGR8888
:
2058 case DRM_FORMAT_ABGR8888
:
2059 dspcntr
|= DISPPLANE_RGBX888
;
2061 case DRM_FORMAT_XRGB2101010
:
2062 case DRM_FORMAT_ARGB2101010
:
2063 dspcntr
|= DISPPLANE_BGRX101010
;
2065 case DRM_FORMAT_XBGR2101010
:
2066 case DRM_FORMAT_ABGR2101010
:
2067 dspcntr
|= DISPPLANE_RGBX101010
;
2073 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2074 dspcntr
|= DISPPLANE_TILED
;
2076 dspcntr
&= ~DISPPLANE_TILED
;
2079 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2081 I915_WRITE(reg
, dspcntr
);
2083 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2084 intel_crtc
->dspaddr_offset
=
2085 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2086 fb
->bits_per_pixel
/ 8,
2088 linear_offset
-= intel_crtc
->dspaddr_offset
;
2090 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2091 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2093 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2094 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2095 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2096 if (IS_HASWELL(dev
)) {
2097 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2099 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2100 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2107 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2109 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2110 int x
, int y
, enum mode_set_atomic state
)
2112 struct drm_device
*dev
= crtc
->dev
;
2113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2115 if (dev_priv
->display
.disable_fbc
)
2116 dev_priv
->display
.disable_fbc(dev
);
2117 intel_increase_pllclock(crtc
);
2119 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2122 void intel_display_handle_reset(struct drm_device
*dev
)
2124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2125 struct drm_crtc
*crtc
;
2128 * Flips in the rings have been nuked by the reset,
2129 * so complete all pending flips so that user space
2130 * will get its events and not get stuck.
2132 * Also update the base address of all primary
2133 * planes to the the last fb to make sure we're
2134 * showing the correct fb after a reset.
2136 * Need to make two loops over the crtcs so that we
2137 * don't try to grab a crtc mutex before the
2138 * pending_flip_queue really got woken up.
2141 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2142 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2143 enum plane plane
= intel_crtc
->plane
;
2145 intel_prepare_page_flip(dev
, plane
);
2146 intel_finish_page_flip_plane(dev
, plane
);
2149 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2150 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2152 mutex_lock(&crtc
->mutex
);
2153 if (intel_crtc
->active
)
2154 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2156 mutex_unlock(&crtc
->mutex
);
2161 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2163 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2164 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2165 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2168 /* Big Hammer, we also need to ensure that any pending
2169 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2170 * current scanout is retired before unpinning the old
2173 * This should only fail upon a hung GPU, in which case we
2174 * can safely continue.
2176 dev_priv
->mm
.interruptible
= false;
2177 ret
= i915_gem_object_finish_gpu(obj
);
2178 dev_priv
->mm
.interruptible
= was_interruptible
;
2183 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2185 struct drm_device
*dev
= crtc
->dev
;
2186 struct drm_i915_master_private
*master_priv
;
2187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2189 if (!dev
->primary
->master
)
2192 master_priv
= dev
->primary
->master
->driver_priv
;
2193 if (!master_priv
->sarea_priv
)
2196 switch (intel_crtc
->pipe
) {
2198 master_priv
->sarea_priv
->pipeA_x
= x
;
2199 master_priv
->sarea_priv
->pipeA_y
= y
;
2202 master_priv
->sarea_priv
->pipeB_x
= x
;
2203 master_priv
->sarea_priv
->pipeB_y
= y
;
2211 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2212 struct drm_framebuffer
*fb
)
2214 struct drm_device
*dev
= crtc
->dev
;
2215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2216 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2217 struct drm_framebuffer
*old_fb
;
2222 DRM_ERROR("No FB bound\n");
2226 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2227 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2228 plane_name(intel_crtc
->plane
),
2229 INTEL_INFO(dev
)->num_pipes
);
2233 mutex_lock(&dev
->struct_mutex
);
2234 ret
= intel_pin_and_fence_fb_obj(dev
,
2235 to_intel_framebuffer(fb
)->obj
,
2238 mutex_unlock(&dev
->struct_mutex
);
2239 DRM_ERROR("pin & fence failed\n");
2243 /* Update pipe size and adjust fitter if needed */
2244 if (i915_fastboot
) {
2245 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2246 ((crtc
->mode
.hdisplay
- 1) << 16) |
2247 (crtc
->mode
.vdisplay
- 1));
2248 if (!intel_crtc
->config
.pch_pfit
.size
&&
2249 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2250 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2251 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2252 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2253 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2257 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2259 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2260 mutex_unlock(&dev
->struct_mutex
);
2261 DRM_ERROR("failed to update base address\n");
2271 if (intel_crtc
->active
&& old_fb
!= fb
)
2272 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2273 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2276 intel_update_fbc(dev
);
2277 intel_edp_psr_update(dev
);
2278 mutex_unlock(&dev
->struct_mutex
);
2280 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2285 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2287 struct drm_device
*dev
= crtc
->dev
;
2288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2290 int pipe
= intel_crtc
->pipe
;
2293 /* enable normal train */
2294 reg
= FDI_TX_CTL(pipe
);
2295 temp
= I915_READ(reg
);
2296 if (IS_IVYBRIDGE(dev
)) {
2297 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2298 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2300 temp
&= ~FDI_LINK_TRAIN_NONE
;
2301 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2303 I915_WRITE(reg
, temp
);
2305 reg
= FDI_RX_CTL(pipe
);
2306 temp
= I915_READ(reg
);
2307 if (HAS_PCH_CPT(dev
)) {
2308 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2309 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2311 temp
&= ~FDI_LINK_TRAIN_NONE
;
2312 temp
|= FDI_LINK_TRAIN_NONE
;
2314 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2316 /* wait one idle pattern time */
2320 /* IVB wants error correction enabled */
2321 if (IS_IVYBRIDGE(dev
))
2322 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2323 FDI_FE_ERRC_ENABLE
);
2326 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2328 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2331 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2334 struct intel_crtc
*pipe_B_crtc
=
2335 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2336 struct intel_crtc
*pipe_C_crtc
=
2337 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2341 * When everything is off disable fdi C so that we could enable fdi B
2342 * with all lanes. Note that we don't care about enabled pipes without
2343 * an enabled pch encoder.
2345 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2346 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2347 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2348 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2350 temp
= I915_READ(SOUTH_CHICKEN1
);
2351 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2352 DRM_DEBUG_KMS("disabling fdi C rx\n");
2353 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2357 /* The FDI link training functions for ILK/Ibexpeak. */
2358 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2360 struct drm_device
*dev
= crtc
->dev
;
2361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2362 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2363 int pipe
= intel_crtc
->pipe
;
2364 int plane
= intel_crtc
->plane
;
2365 u32 reg
, temp
, tries
;
2367 /* FDI needs bits from pipe & plane first */
2368 assert_pipe_enabled(dev_priv
, pipe
);
2369 assert_plane_enabled(dev_priv
, plane
);
2371 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2373 reg
= FDI_RX_IMR(pipe
);
2374 temp
= I915_READ(reg
);
2375 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2376 temp
&= ~FDI_RX_BIT_LOCK
;
2377 I915_WRITE(reg
, temp
);
2381 /* enable CPU FDI TX and PCH FDI RX */
2382 reg
= FDI_TX_CTL(pipe
);
2383 temp
= I915_READ(reg
);
2384 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2385 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2386 temp
&= ~FDI_LINK_TRAIN_NONE
;
2387 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2388 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2390 reg
= FDI_RX_CTL(pipe
);
2391 temp
= I915_READ(reg
);
2392 temp
&= ~FDI_LINK_TRAIN_NONE
;
2393 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2394 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2399 /* Ironlake workaround, enable clock pointer after FDI enable*/
2400 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2401 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2402 FDI_RX_PHASE_SYNC_POINTER_EN
);
2404 reg
= FDI_RX_IIR(pipe
);
2405 for (tries
= 0; tries
< 5; tries
++) {
2406 temp
= I915_READ(reg
);
2407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2409 if ((temp
& FDI_RX_BIT_LOCK
)) {
2410 DRM_DEBUG_KMS("FDI train 1 done.\n");
2411 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2416 DRM_ERROR("FDI train 1 fail!\n");
2419 reg
= FDI_TX_CTL(pipe
);
2420 temp
= I915_READ(reg
);
2421 temp
&= ~FDI_LINK_TRAIN_NONE
;
2422 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2423 I915_WRITE(reg
, temp
);
2425 reg
= FDI_RX_CTL(pipe
);
2426 temp
= I915_READ(reg
);
2427 temp
&= ~FDI_LINK_TRAIN_NONE
;
2428 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2429 I915_WRITE(reg
, temp
);
2434 reg
= FDI_RX_IIR(pipe
);
2435 for (tries
= 0; tries
< 5; tries
++) {
2436 temp
= I915_READ(reg
);
2437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2439 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2440 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2441 DRM_DEBUG_KMS("FDI train 2 done.\n");
2446 DRM_ERROR("FDI train 2 fail!\n");
2448 DRM_DEBUG_KMS("FDI train done\n");
2452 static const int snb_b_fdi_train_param
[] = {
2453 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2454 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2455 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2456 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2459 /* The FDI link training functions for SNB/Cougarpoint. */
2460 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2462 struct drm_device
*dev
= crtc
->dev
;
2463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2465 int pipe
= intel_crtc
->pipe
;
2466 u32 reg
, temp
, i
, retry
;
2468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2470 reg
= FDI_RX_IMR(pipe
);
2471 temp
= I915_READ(reg
);
2472 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2473 temp
&= ~FDI_RX_BIT_LOCK
;
2474 I915_WRITE(reg
, temp
);
2479 /* enable CPU FDI TX and PCH FDI RX */
2480 reg
= FDI_TX_CTL(pipe
);
2481 temp
= I915_READ(reg
);
2482 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2483 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2484 temp
&= ~FDI_LINK_TRAIN_NONE
;
2485 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2486 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2488 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2489 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2491 I915_WRITE(FDI_RX_MISC(pipe
),
2492 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2494 reg
= FDI_RX_CTL(pipe
);
2495 temp
= I915_READ(reg
);
2496 if (HAS_PCH_CPT(dev
)) {
2497 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2498 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2500 temp
&= ~FDI_LINK_TRAIN_NONE
;
2501 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2503 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2508 for (i
= 0; i
< 4; i
++) {
2509 reg
= FDI_TX_CTL(pipe
);
2510 temp
= I915_READ(reg
);
2511 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2512 temp
|= snb_b_fdi_train_param
[i
];
2513 I915_WRITE(reg
, temp
);
2518 for (retry
= 0; retry
< 5; retry
++) {
2519 reg
= FDI_RX_IIR(pipe
);
2520 temp
= I915_READ(reg
);
2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2522 if (temp
& FDI_RX_BIT_LOCK
) {
2523 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2524 DRM_DEBUG_KMS("FDI train 1 done.\n");
2533 DRM_ERROR("FDI train 1 fail!\n");
2536 reg
= FDI_TX_CTL(pipe
);
2537 temp
= I915_READ(reg
);
2538 temp
&= ~FDI_LINK_TRAIN_NONE
;
2539 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2541 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2543 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2545 I915_WRITE(reg
, temp
);
2547 reg
= FDI_RX_CTL(pipe
);
2548 temp
= I915_READ(reg
);
2549 if (HAS_PCH_CPT(dev
)) {
2550 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2551 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2553 temp
&= ~FDI_LINK_TRAIN_NONE
;
2554 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2556 I915_WRITE(reg
, temp
);
2561 for (i
= 0; i
< 4; i
++) {
2562 reg
= FDI_TX_CTL(pipe
);
2563 temp
= I915_READ(reg
);
2564 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2565 temp
|= snb_b_fdi_train_param
[i
];
2566 I915_WRITE(reg
, temp
);
2571 for (retry
= 0; retry
< 5; retry
++) {
2572 reg
= FDI_RX_IIR(pipe
);
2573 temp
= I915_READ(reg
);
2574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2575 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2576 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2586 DRM_ERROR("FDI train 2 fail!\n");
2588 DRM_DEBUG_KMS("FDI train done.\n");
2591 /* Manual link training for Ivy Bridge A0 parts */
2592 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2594 struct drm_device
*dev
= crtc
->dev
;
2595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2596 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2597 int pipe
= intel_crtc
->pipe
;
2600 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2602 reg
= FDI_RX_IMR(pipe
);
2603 temp
= I915_READ(reg
);
2604 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2605 temp
&= ~FDI_RX_BIT_LOCK
;
2606 I915_WRITE(reg
, temp
);
2611 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2612 I915_READ(FDI_RX_IIR(pipe
)));
2614 /* enable CPU FDI TX and PCH FDI RX */
2615 reg
= FDI_TX_CTL(pipe
);
2616 temp
= I915_READ(reg
);
2617 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2618 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2619 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2620 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2621 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2622 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2623 temp
|= FDI_COMPOSITE_SYNC
;
2624 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2626 I915_WRITE(FDI_RX_MISC(pipe
),
2627 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2629 reg
= FDI_RX_CTL(pipe
);
2630 temp
= I915_READ(reg
);
2631 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2632 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2633 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2634 temp
|= FDI_COMPOSITE_SYNC
;
2635 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2640 for (i
= 0; i
< 4; i
++) {
2641 reg
= FDI_TX_CTL(pipe
);
2642 temp
= I915_READ(reg
);
2643 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2644 temp
|= snb_b_fdi_train_param
[i
];
2645 I915_WRITE(reg
, temp
);
2650 reg
= FDI_RX_IIR(pipe
);
2651 temp
= I915_READ(reg
);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2654 if (temp
& FDI_RX_BIT_LOCK
||
2655 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2656 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2657 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2662 DRM_ERROR("FDI train 1 fail!\n");
2665 reg
= FDI_TX_CTL(pipe
);
2666 temp
= I915_READ(reg
);
2667 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2668 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2669 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2670 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2671 I915_WRITE(reg
, temp
);
2673 reg
= FDI_RX_CTL(pipe
);
2674 temp
= I915_READ(reg
);
2675 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2676 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2677 I915_WRITE(reg
, temp
);
2682 for (i
= 0; i
< 4; i
++) {
2683 reg
= FDI_TX_CTL(pipe
);
2684 temp
= I915_READ(reg
);
2685 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2686 temp
|= snb_b_fdi_train_param
[i
];
2687 I915_WRITE(reg
, temp
);
2692 reg
= FDI_RX_IIR(pipe
);
2693 temp
= I915_READ(reg
);
2694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2696 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2697 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2698 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2703 DRM_ERROR("FDI train 2 fail!\n");
2705 DRM_DEBUG_KMS("FDI train done.\n");
2708 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2710 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2712 int pipe
= intel_crtc
->pipe
;
2716 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2717 reg
= FDI_RX_CTL(pipe
);
2718 temp
= I915_READ(reg
);
2719 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2720 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2721 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2722 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2727 /* Switch from Rawclk to PCDclk */
2728 temp
= I915_READ(reg
);
2729 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2734 /* Enable CPU FDI TX PLL, always on for Ironlake */
2735 reg
= FDI_TX_CTL(pipe
);
2736 temp
= I915_READ(reg
);
2737 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2738 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2745 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2747 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2749 int pipe
= intel_crtc
->pipe
;
2752 /* Switch from PCDclk to Rawclk */
2753 reg
= FDI_RX_CTL(pipe
);
2754 temp
= I915_READ(reg
);
2755 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2757 /* Disable CPU FDI TX PLL */
2758 reg
= FDI_TX_CTL(pipe
);
2759 temp
= I915_READ(reg
);
2760 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2765 reg
= FDI_RX_CTL(pipe
);
2766 temp
= I915_READ(reg
);
2767 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2769 /* Wait for the clocks to turn off. */
2774 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2776 struct drm_device
*dev
= crtc
->dev
;
2777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2778 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2779 int pipe
= intel_crtc
->pipe
;
2782 /* disable CPU FDI tx and PCH FDI rx */
2783 reg
= FDI_TX_CTL(pipe
);
2784 temp
= I915_READ(reg
);
2785 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2788 reg
= FDI_RX_CTL(pipe
);
2789 temp
= I915_READ(reg
);
2790 temp
&= ~(0x7 << 16);
2791 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2792 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2797 /* Ironlake workaround, disable clock pointer after downing FDI */
2798 if (HAS_PCH_IBX(dev
)) {
2799 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2802 /* still set train pattern 1 */
2803 reg
= FDI_TX_CTL(pipe
);
2804 temp
= I915_READ(reg
);
2805 temp
&= ~FDI_LINK_TRAIN_NONE
;
2806 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2807 I915_WRITE(reg
, temp
);
2809 reg
= FDI_RX_CTL(pipe
);
2810 temp
= I915_READ(reg
);
2811 if (HAS_PCH_CPT(dev
)) {
2812 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2813 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2815 temp
&= ~FDI_LINK_TRAIN_NONE
;
2816 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2818 /* BPC in FDI rx is consistent with that in PIPECONF */
2819 temp
&= ~(0x07 << 16);
2820 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2821 I915_WRITE(reg
, temp
);
2827 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2829 struct drm_device
*dev
= crtc
->dev
;
2830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2831 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2832 unsigned long flags
;
2835 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2836 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2839 spin_lock_irqsave(&dev
->event_lock
, flags
);
2840 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2841 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2846 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2848 struct drm_device
*dev
= crtc
->dev
;
2849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2851 if (crtc
->fb
== NULL
)
2854 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2856 wait_event(dev_priv
->pending_flip_queue
,
2857 !intel_crtc_has_pending_flip(crtc
));
2859 mutex_lock(&dev
->struct_mutex
);
2860 intel_finish_fb(crtc
->fb
);
2861 mutex_unlock(&dev
->struct_mutex
);
2864 /* Program iCLKIP clock to the desired frequency */
2865 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2867 struct drm_device
*dev
= crtc
->dev
;
2868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2869 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2872 mutex_lock(&dev_priv
->dpio_lock
);
2874 /* It is necessary to ungate the pixclk gate prior to programming
2875 * the divisors, and gate it back when it is done.
2877 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2879 /* Disable SSCCTL */
2880 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2881 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2885 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2886 if (crtc
->mode
.clock
== 20000) {
2891 /* The iCLK virtual clock root frequency is in MHz,
2892 * but the crtc->mode.clock in in KHz. To get the divisors,
2893 * it is necessary to divide one by another, so we
2894 * convert the virtual clock precision to KHz here for higher
2897 u32 iclk_virtual_root_freq
= 172800 * 1000;
2898 u32 iclk_pi_range
= 64;
2899 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2901 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2902 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2903 pi_value
= desired_divisor
% iclk_pi_range
;
2906 divsel
= msb_divisor_value
- 2;
2907 phaseinc
= pi_value
;
2910 /* This should not happen with any sane values */
2911 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2912 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2913 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2914 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2916 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2923 /* Program SSCDIVINTPHASE6 */
2924 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2925 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2926 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2927 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2928 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2929 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2930 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2931 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2933 /* Program SSCAUXDIV */
2934 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2935 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2936 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2937 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2939 /* Enable modulator and associated divider */
2940 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2941 temp
&= ~SBI_SSCCTL_DISABLE
;
2942 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2944 /* Wait for initialization time */
2947 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2949 mutex_unlock(&dev_priv
->dpio_lock
);
2952 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
2953 enum pipe pch_transcoder
)
2955 struct drm_device
*dev
= crtc
->base
.dev
;
2956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2957 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2959 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
2960 I915_READ(HTOTAL(cpu_transcoder
)));
2961 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
2962 I915_READ(HBLANK(cpu_transcoder
)));
2963 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
2964 I915_READ(HSYNC(cpu_transcoder
)));
2966 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
2967 I915_READ(VTOTAL(cpu_transcoder
)));
2968 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
2969 I915_READ(VBLANK(cpu_transcoder
)));
2970 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
2971 I915_READ(VSYNC(cpu_transcoder
)));
2972 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
2973 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
2977 * Enable PCH resources required for PCH ports:
2979 * - FDI training & RX/TX
2980 * - update transcoder timings
2981 * - DP transcoding bits
2984 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2986 struct drm_device
*dev
= crtc
->dev
;
2987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2989 int pipe
= intel_crtc
->pipe
;
2992 assert_pch_transcoder_disabled(dev_priv
, pipe
);
2994 /* Write the TU size bits before fdi link training, so that error
2995 * detection works. */
2996 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2997 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2999 /* For PCH output, training FDI link */
3000 dev_priv
->display
.fdi_link_train(crtc
);
3002 /* We need to program the right clock selection before writing the pixel
3003 * mutliplier into the DPLL. */
3004 if (HAS_PCH_CPT(dev
)) {
3007 temp
= I915_READ(PCH_DPLL_SEL
);
3008 temp
|= TRANS_DPLL_ENABLE(pipe
);
3009 sel
= TRANS_DPLLB_SEL(pipe
);
3010 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3014 I915_WRITE(PCH_DPLL_SEL
, temp
);
3017 /* XXX: pch pll's can be enabled any time before we enable the PCH
3018 * transcoder, and we actually should do this to not upset any PCH
3019 * transcoder that already use the clock when we share it.
3021 * Note that enable_shared_dpll tries to do the right thing, but
3022 * get_shared_dpll unconditionally resets the pll - we need that to have
3023 * the right LVDS enable sequence. */
3024 ironlake_enable_shared_dpll(intel_crtc
);
3026 /* set transcoder timing, panel must allow it */
3027 assert_panel_unlocked(dev_priv
, pipe
);
3028 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3030 intel_fdi_normal_train(crtc
);
3032 /* For PCH DP, enable TRANS_DP_CTL */
3033 if (HAS_PCH_CPT(dev
) &&
3034 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3035 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3036 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3037 reg
= TRANS_DP_CTL(pipe
);
3038 temp
= I915_READ(reg
);
3039 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3040 TRANS_DP_SYNC_MASK
|
3042 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3043 TRANS_DP_ENH_FRAMING
);
3044 temp
|= bpc
<< 9; /* same format but at 11:9 */
3046 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3047 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3048 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3049 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3051 switch (intel_trans_dp_port_sel(crtc
)) {
3053 temp
|= TRANS_DP_PORT_SEL_B
;
3056 temp
|= TRANS_DP_PORT_SEL_C
;
3059 temp
|= TRANS_DP_PORT_SEL_D
;
3065 I915_WRITE(reg
, temp
);
3068 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3071 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3073 struct drm_device
*dev
= crtc
->dev
;
3074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3075 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3076 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3078 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3080 lpt_program_iclkip(crtc
);
3082 /* Set transcoder timing. */
3083 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3085 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3088 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3090 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3095 if (pll
->refcount
== 0) {
3096 WARN(1, "bad %s refcount\n", pll
->name
);
3100 if (--pll
->refcount
== 0) {
3102 WARN_ON(pll
->active
);
3105 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3108 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3110 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3111 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3112 enum intel_dpll_id i
;
3115 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3116 crtc
->base
.base
.id
, pll
->name
);
3117 intel_put_shared_dpll(crtc
);
3120 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3121 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3122 i
= (enum intel_dpll_id
) crtc
->pipe
;
3123 pll
= &dev_priv
->shared_dplls
[i
];
3125 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3126 crtc
->base
.base
.id
, pll
->name
);
3131 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3132 pll
= &dev_priv
->shared_dplls
[i
];
3134 /* Only want to check enabled timings first */
3135 if (pll
->refcount
== 0)
3138 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3139 sizeof(pll
->hw_state
)) == 0) {
3140 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3142 pll
->name
, pll
->refcount
, pll
->active
);
3148 /* Ok no matching timings, maybe there's a free one? */
3149 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3150 pll
= &dev_priv
->shared_dplls
[i
];
3151 if (pll
->refcount
== 0) {
3152 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3153 crtc
->base
.base
.id
, pll
->name
);
3161 crtc
->config
.shared_dpll
= i
;
3162 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3163 pipe_name(crtc
->pipe
));
3165 if (pll
->active
== 0) {
3166 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3167 sizeof(pll
->hw_state
));
3169 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3171 assert_shared_dpll_disabled(dev_priv
, pll
);
3173 pll
->mode_set(dev_priv
, pll
);
3180 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3183 int dslreg
= PIPEDSL(pipe
);
3186 temp
= I915_READ(dslreg
);
3188 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3189 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3190 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3194 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3196 struct drm_device
*dev
= crtc
->base
.dev
;
3197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3198 int pipe
= crtc
->pipe
;
3200 if (crtc
->config
.pch_pfit
.size
) {
3201 /* Force use of hard-coded filter coefficients
3202 * as some pre-programmed values are broken,
3205 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3206 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3207 PF_PIPE_SEL_IVB(pipe
));
3209 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3210 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3211 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3215 static void intel_enable_planes(struct drm_crtc
*crtc
)
3217 struct drm_device
*dev
= crtc
->dev
;
3218 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3219 struct intel_plane
*intel_plane
;
3221 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3222 if (intel_plane
->pipe
== pipe
)
3223 intel_plane_restore(&intel_plane
->base
);
3226 static void intel_disable_planes(struct drm_crtc
*crtc
)
3228 struct drm_device
*dev
= crtc
->dev
;
3229 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3230 struct intel_plane
*intel_plane
;
3232 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3233 if (intel_plane
->pipe
== pipe
)
3234 intel_plane_disable(&intel_plane
->base
);
3237 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3239 struct drm_device
*dev
= crtc
->dev
;
3240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3242 struct intel_encoder
*encoder
;
3243 int pipe
= intel_crtc
->pipe
;
3244 int plane
= intel_crtc
->plane
;
3246 WARN_ON(!crtc
->enabled
);
3248 if (intel_crtc
->active
)
3251 intel_crtc
->active
= true;
3253 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3254 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3256 intel_update_watermarks(dev
);
3258 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3259 if (encoder
->pre_enable
)
3260 encoder
->pre_enable(encoder
);
3262 if (intel_crtc
->config
.has_pch_encoder
) {
3263 /* Note: FDI PLL enabling _must_ be done before we enable the
3264 * cpu pipes, hence this is separate from all the other fdi/pch
3266 ironlake_fdi_pll_enable(intel_crtc
);
3268 assert_fdi_tx_disabled(dev_priv
, pipe
);
3269 assert_fdi_rx_disabled(dev_priv
, pipe
);
3272 ironlake_pfit_enable(intel_crtc
);
3275 * On ILK+ LUT must be loaded before the pipe is running but with
3278 intel_crtc_load_lut(crtc
);
3280 intel_enable_pipe(dev_priv
, pipe
,
3281 intel_crtc
->config
.has_pch_encoder
);
3282 intel_enable_plane(dev_priv
, plane
, pipe
);
3283 intel_enable_planes(crtc
);
3284 intel_crtc_update_cursor(crtc
, true);
3286 if (intel_crtc
->config
.has_pch_encoder
)
3287 ironlake_pch_enable(crtc
);
3289 mutex_lock(&dev
->struct_mutex
);
3290 intel_update_fbc(dev
);
3291 mutex_unlock(&dev
->struct_mutex
);
3293 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3294 encoder
->enable(encoder
);
3296 if (HAS_PCH_CPT(dev
))
3297 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3300 * There seems to be a race in PCH platform hw (at least on some
3301 * outputs) where an enabled pipe still completes any pageflip right
3302 * away (as if the pipe is off) instead of waiting for vblank. As soon
3303 * as the first vblank happend, everything works as expected. Hence just
3304 * wait for one vblank before returning to avoid strange things
3307 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3310 /* IPS only exists on ULT machines and is tied to pipe A. */
3311 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3313 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3316 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3318 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3320 if (!crtc
->config
.ips_enabled
)
3323 /* We can only enable IPS after we enable a plane and wait for a vblank.
3324 * We guarantee that the plane is enabled by calling intel_enable_ips
3325 * only after intel_enable_plane. And intel_enable_plane already waits
3326 * for a vblank, so all we need to do here is to enable the IPS bit. */
3327 assert_plane_enabled(dev_priv
, crtc
->plane
);
3328 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3331 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3333 struct drm_device
*dev
= crtc
->base
.dev
;
3334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3336 if (!crtc
->config
.ips_enabled
)
3339 assert_plane_enabled(dev_priv
, crtc
->plane
);
3340 I915_WRITE(IPS_CTL
, 0);
3342 /* We need to wait for a vblank before we can disable the plane. */
3343 intel_wait_for_vblank(dev
, crtc
->pipe
);
3346 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3348 struct drm_device
*dev
= crtc
->dev
;
3349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3350 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3351 struct intel_encoder
*encoder
;
3352 int pipe
= intel_crtc
->pipe
;
3353 int plane
= intel_crtc
->plane
;
3355 WARN_ON(!crtc
->enabled
);
3357 if (intel_crtc
->active
)
3360 intel_crtc
->active
= true;
3362 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3363 if (intel_crtc
->config
.has_pch_encoder
)
3364 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3366 intel_update_watermarks(dev
);
3368 if (intel_crtc
->config
.has_pch_encoder
)
3369 dev_priv
->display
.fdi_link_train(crtc
);
3371 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3372 if (encoder
->pre_enable
)
3373 encoder
->pre_enable(encoder
);
3375 intel_ddi_enable_pipe_clock(intel_crtc
);
3377 ironlake_pfit_enable(intel_crtc
);
3380 * On ILK+ LUT must be loaded before the pipe is running but with
3383 intel_crtc_load_lut(crtc
);
3385 intel_ddi_set_pipe_settings(crtc
);
3386 intel_ddi_enable_transcoder_func(crtc
);
3388 intel_enable_pipe(dev_priv
, pipe
,
3389 intel_crtc
->config
.has_pch_encoder
);
3390 intel_enable_plane(dev_priv
, plane
, pipe
);
3391 intel_enable_planes(crtc
);
3392 intel_crtc_update_cursor(crtc
, true);
3394 hsw_enable_ips(intel_crtc
);
3396 if (intel_crtc
->config
.has_pch_encoder
)
3397 lpt_pch_enable(crtc
);
3399 mutex_lock(&dev
->struct_mutex
);
3400 intel_update_fbc(dev
);
3401 mutex_unlock(&dev
->struct_mutex
);
3403 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3404 encoder
->enable(encoder
);
3407 * There seems to be a race in PCH platform hw (at least on some
3408 * outputs) where an enabled pipe still completes any pageflip right
3409 * away (as if the pipe is off) instead of waiting for vblank. As soon
3410 * as the first vblank happend, everything works as expected. Hence just
3411 * wait for one vblank before returning to avoid strange things
3414 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3417 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3419 struct drm_device
*dev
= crtc
->base
.dev
;
3420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3421 int pipe
= crtc
->pipe
;
3423 /* To avoid upsetting the power well on haswell only disable the pfit if
3424 * it's in use. The hw state code will make sure we get this right. */
3425 if (crtc
->config
.pch_pfit
.size
) {
3426 I915_WRITE(PF_CTL(pipe
), 0);
3427 I915_WRITE(PF_WIN_POS(pipe
), 0);
3428 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3432 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3434 struct drm_device
*dev
= crtc
->dev
;
3435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3436 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3437 struct intel_encoder
*encoder
;
3438 int pipe
= intel_crtc
->pipe
;
3439 int plane
= intel_crtc
->plane
;
3443 if (!intel_crtc
->active
)
3446 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3447 encoder
->disable(encoder
);
3449 intel_crtc_wait_for_pending_flips(crtc
);
3450 drm_vblank_off(dev
, pipe
);
3452 if (dev_priv
->fbc
.plane
== plane
)
3453 intel_disable_fbc(dev
);
3455 intel_crtc_update_cursor(crtc
, false);
3456 intel_disable_planes(crtc
);
3457 intel_disable_plane(dev_priv
, plane
, pipe
);
3459 if (intel_crtc
->config
.has_pch_encoder
)
3460 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3462 intel_disable_pipe(dev_priv
, pipe
);
3464 ironlake_pfit_disable(intel_crtc
);
3466 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3467 if (encoder
->post_disable
)
3468 encoder
->post_disable(encoder
);
3470 if (intel_crtc
->config
.has_pch_encoder
) {
3471 ironlake_fdi_disable(crtc
);
3473 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3474 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3476 if (HAS_PCH_CPT(dev
)) {
3477 /* disable TRANS_DP_CTL */
3478 reg
= TRANS_DP_CTL(pipe
);
3479 temp
= I915_READ(reg
);
3480 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3481 TRANS_DP_PORT_SEL_MASK
);
3482 temp
|= TRANS_DP_PORT_SEL_NONE
;
3483 I915_WRITE(reg
, temp
);
3485 /* disable DPLL_SEL */
3486 temp
= I915_READ(PCH_DPLL_SEL
);
3487 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3488 I915_WRITE(PCH_DPLL_SEL
, temp
);
3491 /* disable PCH DPLL */
3492 intel_disable_shared_dpll(intel_crtc
);
3494 ironlake_fdi_pll_disable(intel_crtc
);
3497 intel_crtc
->active
= false;
3498 intel_update_watermarks(dev
);
3500 mutex_lock(&dev
->struct_mutex
);
3501 intel_update_fbc(dev
);
3502 mutex_unlock(&dev
->struct_mutex
);
3505 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3507 struct drm_device
*dev
= crtc
->dev
;
3508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3509 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3510 struct intel_encoder
*encoder
;
3511 int pipe
= intel_crtc
->pipe
;
3512 int plane
= intel_crtc
->plane
;
3513 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3515 if (!intel_crtc
->active
)
3518 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3519 encoder
->disable(encoder
);
3521 intel_crtc_wait_for_pending_flips(crtc
);
3522 drm_vblank_off(dev
, pipe
);
3524 /* FBC must be disabled before disabling the plane on HSW. */
3525 if (dev_priv
->fbc
.plane
== plane
)
3526 intel_disable_fbc(dev
);
3528 hsw_disable_ips(intel_crtc
);
3530 intel_crtc_update_cursor(crtc
, false);
3531 intel_disable_planes(crtc
);
3532 intel_disable_plane(dev_priv
, plane
, pipe
);
3534 if (intel_crtc
->config
.has_pch_encoder
)
3535 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3536 intel_disable_pipe(dev_priv
, pipe
);
3538 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3540 ironlake_pfit_disable(intel_crtc
);
3542 intel_ddi_disable_pipe_clock(intel_crtc
);
3544 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3545 if (encoder
->post_disable
)
3546 encoder
->post_disable(encoder
);
3548 if (intel_crtc
->config
.has_pch_encoder
) {
3549 lpt_disable_pch_transcoder(dev_priv
);
3550 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3551 intel_ddi_fdi_disable(crtc
);
3554 intel_crtc
->active
= false;
3555 intel_update_watermarks(dev
);
3557 mutex_lock(&dev
->struct_mutex
);
3558 intel_update_fbc(dev
);
3559 mutex_unlock(&dev
->struct_mutex
);
3562 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3565 intel_put_shared_dpll(intel_crtc
);
3568 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3570 intel_ddi_put_crtc_pll(crtc
);
3573 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3575 if (!enable
&& intel_crtc
->overlay
) {
3576 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3579 mutex_lock(&dev
->struct_mutex
);
3580 dev_priv
->mm
.interruptible
= false;
3581 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3582 dev_priv
->mm
.interruptible
= true;
3583 mutex_unlock(&dev
->struct_mutex
);
3586 /* Let userspace switch the overlay on again. In most cases userspace
3587 * has to recompute where to put it anyway.
3592 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3593 * cursor plane briefly if not already running after enabling the display
3595 * This workaround avoids occasional blank screens when self refresh is
3599 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3601 u32 cntl
= I915_READ(CURCNTR(pipe
));
3603 if ((cntl
& CURSOR_MODE
) == 0) {
3604 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3606 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3607 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3608 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3609 I915_WRITE(CURCNTR(pipe
), cntl
);
3610 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3611 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3615 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3617 struct drm_device
*dev
= crtc
->base
.dev
;
3618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3619 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3621 if (!crtc
->config
.gmch_pfit
.control
)
3625 * The panel fitter should only be adjusted whilst the pipe is disabled,
3626 * according to register description and PRM.
3628 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3629 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3631 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3632 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3634 /* Border color in case we don't scale up to the full screen. Black by
3635 * default, change to something else for debugging. */
3636 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3639 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3641 struct drm_device
*dev
= crtc
->dev
;
3642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3643 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3644 struct intel_encoder
*encoder
;
3645 int pipe
= intel_crtc
->pipe
;
3646 int plane
= intel_crtc
->plane
;
3648 WARN_ON(!crtc
->enabled
);
3650 if (intel_crtc
->active
)
3653 intel_crtc
->active
= true;
3654 intel_update_watermarks(dev
);
3656 mutex_lock(&dev_priv
->dpio_lock
);
3658 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3659 if (encoder
->pre_pll_enable
)
3660 encoder
->pre_pll_enable(encoder
);
3662 vlv_enable_pll(intel_crtc
);
3664 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3665 if (encoder
->pre_enable
)
3666 encoder
->pre_enable(encoder
);
3668 /* VLV wants encoder enabling _before_ the pipe is up. */
3669 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3670 encoder
->enable(encoder
);
3672 i9xx_pfit_enable(intel_crtc
);
3674 intel_crtc_load_lut(crtc
);
3676 intel_enable_pipe(dev_priv
, pipe
, false);
3677 intel_enable_plane(dev_priv
, plane
, pipe
);
3678 intel_enable_planes(crtc
);
3679 intel_crtc_update_cursor(crtc
, true);
3681 intel_update_fbc(dev
);
3683 mutex_unlock(&dev_priv
->dpio_lock
);
3686 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3688 struct drm_device
*dev
= crtc
->dev
;
3689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3691 struct intel_encoder
*encoder
;
3692 int pipe
= intel_crtc
->pipe
;
3693 int plane
= intel_crtc
->plane
;
3695 WARN_ON(!crtc
->enabled
);
3697 if (intel_crtc
->active
)
3700 intel_crtc
->active
= true;
3701 intel_update_watermarks(dev
);
3703 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3704 if (encoder
->pre_enable
)
3705 encoder
->pre_enable(encoder
);
3707 i9xx_enable_pll(intel_crtc
);
3709 i9xx_pfit_enable(intel_crtc
);
3711 intel_crtc_load_lut(crtc
);
3713 intel_enable_pipe(dev_priv
, pipe
, false);
3714 intel_enable_plane(dev_priv
, plane
, pipe
);
3715 intel_enable_planes(crtc
);
3716 /* The fixup needs to happen before cursor is enabled */
3718 g4x_fixup_plane(dev_priv
, pipe
);
3719 intel_crtc_update_cursor(crtc
, true);
3721 /* Give the overlay scaler a chance to enable if it's on this pipe */
3722 intel_crtc_dpms_overlay(intel_crtc
, true);
3724 intel_update_fbc(dev
);
3726 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3727 encoder
->enable(encoder
);
3730 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3732 struct drm_device
*dev
= crtc
->base
.dev
;
3733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3735 if (!crtc
->config
.gmch_pfit
.control
)
3738 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3740 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3741 I915_READ(PFIT_CONTROL
));
3742 I915_WRITE(PFIT_CONTROL
, 0);
3745 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3747 struct drm_device
*dev
= crtc
->dev
;
3748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3749 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3750 struct intel_encoder
*encoder
;
3751 int pipe
= intel_crtc
->pipe
;
3752 int plane
= intel_crtc
->plane
;
3754 if (!intel_crtc
->active
)
3757 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3758 encoder
->disable(encoder
);
3760 /* Give the overlay scaler a chance to disable if it's on this pipe */
3761 intel_crtc_wait_for_pending_flips(crtc
);
3762 drm_vblank_off(dev
, pipe
);
3764 if (dev_priv
->fbc
.plane
== plane
)
3765 intel_disable_fbc(dev
);
3767 intel_crtc_dpms_overlay(intel_crtc
, false);
3768 intel_crtc_update_cursor(crtc
, false);
3769 intel_disable_planes(crtc
);
3770 intel_disable_plane(dev_priv
, plane
, pipe
);
3772 intel_disable_pipe(dev_priv
, pipe
);
3774 i9xx_pfit_disable(intel_crtc
);
3776 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3777 if (encoder
->post_disable
)
3778 encoder
->post_disable(encoder
);
3780 i9xx_disable_pll(dev_priv
, pipe
);
3782 intel_crtc
->active
= false;
3783 intel_update_fbc(dev
);
3784 intel_update_watermarks(dev
);
3787 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3791 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3794 struct drm_device
*dev
= crtc
->dev
;
3795 struct drm_i915_master_private
*master_priv
;
3796 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3797 int pipe
= intel_crtc
->pipe
;
3799 if (!dev
->primary
->master
)
3802 master_priv
= dev
->primary
->master
->driver_priv
;
3803 if (!master_priv
->sarea_priv
)
3808 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3809 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3812 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3813 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3816 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3822 * Sets the power management mode of the pipe and plane.
3824 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3826 struct drm_device
*dev
= crtc
->dev
;
3827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3828 struct intel_encoder
*intel_encoder
;
3829 bool enable
= false;
3831 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3832 enable
|= intel_encoder
->connectors_active
;
3835 dev_priv
->display
.crtc_enable(crtc
);
3837 dev_priv
->display
.crtc_disable(crtc
);
3839 intel_crtc_update_sarea(crtc
, enable
);
3842 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3844 struct drm_device
*dev
= crtc
->dev
;
3845 struct drm_connector
*connector
;
3846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3847 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3849 /* crtc should still be enabled when we disable it. */
3850 WARN_ON(!crtc
->enabled
);
3852 dev_priv
->display
.crtc_disable(crtc
);
3853 intel_crtc
->eld_vld
= false;
3854 intel_crtc_update_sarea(crtc
, false);
3855 dev_priv
->display
.off(crtc
);
3857 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3858 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3861 mutex_lock(&dev
->struct_mutex
);
3862 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3863 mutex_unlock(&dev
->struct_mutex
);
3867 /* Update computed state. */
3868 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3869 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3872 if (connector
->encoder
->crtc
!= crtc
)
3875 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3876 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3880 void intel_modeset_disable(struct drm_device
*dev
)
3882 struct drm_crtc
*crtc
;
3884 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3886 intel_crtc_disable(crtc
);
3890 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3892 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3894 drm_encoder_cleanup(encoder
);
3895 kfree(intel_encoder
);
3898 /* Simple dpms helper for encodres with just one connector, no cloning and only
3899 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3900 * state of the entire output pipe. */
3901 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3903 if (mode
== DRM_MODE_DPMS_ON
) {
3904 encoder
->connectors_active
= true;
3906 intel_crtc_update_dpms(encoder
->base
.crtc
);
3908 encoder
->connectors_active
= false;
3910 intel_crtc_update_dpms(encoder
->base
.crtc
);
3914 /* Cross check the actual hw state with our own modeset state tracking (and it's
3915 * internal consistency). */
3916 static void intel_connector_check_state(struct intel_connector
*connector
)
3918 if (connector
->get_hw_state(connector
)) {
3919 struct intel_encoder
*encoder
= connector
->encoder
;
3920 struct drm_crtc
*crtc
;
3921 bool encoder_enabled
;
3924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3925 connector
->base
.base
.id
,
3926 drm_get_connector_name(&connector
->base
));
3928 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3929 "wrong connector dpms state\n");
3930 WARN(connector
->base
.encoder
!= &encoder
->base
,
3931 "active connector not linked to encoder\n");
3932 WARN(!encoder
->connectors_active
,
3933 "encoder->connectors_active not set\n");
3935 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3936 WARN(!encoder_enabled
, "encoder not enabled\n");
3937 if (WARN_ON(!encoder
->base
.crtc
))
3940 crtc
= encoder
->base
.crtc
;
3942 WARN(!crtc
->enabled
, "crtc not enabled\n");
3943 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3944 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3945 "encoder active on the wrong pipe\n");
3949 /* Even simpler default implementation, if there's really no special case to
3951 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3953 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3955 /* All the simple cases only support two dpms states. */
3956 if (mode
!= DRM_MODE_DPMS_ON
)
3957 mode
= DRM_MODE_DPMS_OFF
;
3959 if (mode
== connector
->dpms
)
3962 connector
->dpms
= mode
;
3964 /* Only need to change hw state when actually enabled */
3965 if (encoder
->base
.crtc
)
3966 intel_encoder_dpms(encoder
, mode
);
3968 WARN_ON(encoder
->connectors_active
!= false);
3970 intel_modeset_check_state(connector
->dev
);
3973 /* Simple connector->get_hw_state implementation for encoders that support only
3974 * one connector and no cloning and hence the encoder state determines the state
3975 * of the connector. */
3976 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3979 struct intel_encoder
*encoder
= connector
->encoder
;
3981 return encoder
->get_hw_state(encoder
, &pipe
);
3984 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
3985 struct intel_crtc_config
*pipe_config
)
3987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3988 struct intel_crtc
*pipe_B_crtc
=
3989 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3991 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3992 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3993 if (pipe_config
->fdi_lanes
> 4) {
3994 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3995 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3999 if (IS_HASWELL(dev
)) {
4000 if (pipe_config
->fdi_lanes
> 2) {
4001 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4002 pipe_config
->fdi_lanes
);
4009 if (INTEL_INFO(dev
)->num_pipes
== 2)
4012 /* Ivybridge 3 pipe is really complicated */
4017 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4018 pipe_config
->fdi_lanes
> 2) {
4019 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4020 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4025 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4026 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4027 if (pipe_config
->fdi_lanes
> 2) {
4028 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4029 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4033 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4043 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4044 struct intel_crtc_config
*pipe_config
)
4046 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4047 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4048 int lane
, link_bw
, fdi_dotclock
;
4049 bool setup_ok
, needs_recompute
= false;
4052 /* FDI is a binary signal running at ~2.7GHz, encoding
4053 * each output octet as 10 bits. The actual frequency
4054 * is stored as a divider into a 100MHz clock, and the
4055 * mode pixel clock is stored in units of 1KHz.
4056 * Hence the bw of each lane in terms of the mode signal
4059 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4061 fdi_dotclock
= adjusted_mode
->clock
;
4062 fdi_dotclock
/= pipe_config
->pixel_multiplier
;
4064 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4065 pipe_config
->pipe_bpp
);
4067 pipe_config
->fdi_lanes
= lane
;
4069 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4070 link_bw
, &pipe_config
->fdi_m_n
);
4072 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4073 intel_crtc
->pipe
, pipe_config
);
4074 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4075 pipe_config
->pipe_bpp
-= 2*3;
4076 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4077 pipe_config
->pipe_bpp
);
4078 needs_recompute
= true;
4079 pipe_config
->bw_constrained
= true;
4084 if (needs_recompute
)
4087 return setup_ok
? 0 : -EINVAL
;
4090 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4091 struct intel_crtc_config
*pipe_config
)
4093 pipe_config
->ips_enabled
= i915_enable_ips
&&
4094 hsw_crtc_supports_ips(crtc
) &&
4095 pipe_config
->pipe_bpp
== 24;
4098 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4099 struct intel_crtc_config
*pipe_config
)
4101 struct drm_device
*dev
= crtc
->base
.dev
;
4102 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4104 if (HAS_PCH_SPLIT(dev
)) {
4105 /* FDI link clock is fixed at 2.7G */
4106 if (pipe_config
->requested_mode
.clock
* 3
4107 > IRONLAKE_FDI_FREQ
* 4)
4111 /* All interlaced capable intel hw wants timings in frames. Note though
4112 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4113 * timings, so we need to be careful not to clobber these.*/
4114 if (!pipe_config
->timings_set
)
4115 drm_mode_set_crtcinfo(adjusted_mode
, 0);
4117 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4118 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4120 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4121 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4124 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4125 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4126 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4127 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4129 pipe_config
->pipe_bpp
= 8*3;
4133 hsw_compute_ips_config(crtc
, pipe_config
);
4135 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4136 * clock survives for now. */
4137 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4138 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4140 if (pipe_config
->has_pch_encoder
)
4141 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4146 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4148 return 400000; /* FIXME */
4151 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4156 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4161 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4166 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4170 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4172 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4173 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4175 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4177 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4179 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4182 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4183 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4185 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4190 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4194 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4196 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4199 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4200 case GC_DISPLAY_CLOCK_333_MHZ
:
4203 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4209 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4214 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4217 /* Assume that the hardware is in the high speed state. This
4218 * should be the default.
4220 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4221 case GC_CLOCK_133_200
:
4222 case GC_CLOCK_100_200
:
4224 case GC_CLOCK_166_250
:
4226 case GC_CLOCK_100_133
:
4230 /* Shouldn't happen */
4234 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4240 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4242 while (*num
> DATA_LINK_M_N_MASK
||
4243 *den
> DATA_LINK_M_N_MASK
) {
4249 static void compute_m_n(unsigned int m
, unsigned int n
,
4250 uint32_t *ret_m
, uint32_t *ret_n
)
4252 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4253 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4254 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4258 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4259 int pixel_clock
, int link_clock
,
4260 struct intel_link_m_n
*m_n
)
4264 compute_m_n(bits_per_pixel
* pixel_clock
,
4265 link_clock
* nlanes
* 8,
4266 &m_n
->gmch_m
, &m_n
->gmch_n
);
4268 compute_m_n(pixel_clock
, link_clock
,
4269 &m_n
->link_m
, &m_n
->link_n
);
4272 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4274 if (i915_panel_use_ssc
>= 0)
4275 return i915_panel_use_ssc
!= 0;
4276 return dev_priv
->vbt
.lvds_use_ssc
4277 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4280 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4282 struct drm_device
*dev
= crtc
->dev
;
4283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4284 int refclk
= 27000; /* for DP & HDMI */
4286 return 100000; /* only one validated so far */
4288 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4290 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4291 if (intel_panel_use_ssc(dev_priv
))
4295 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4302 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4304 struct drm_device
*dev
= crtc
->dev
;
4305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4308 if (IS_VALLEYVIEW(dev
)) {
4309 refclk
= vlv_get_refclk(crtc
);
4310 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4311 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4312 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4313 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4315 } else if (!IS_GEN2(dev
)) {
4324 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4326 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4329 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4331 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4334 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4335 intel_clock_t
*reduced_clock
)
4337 struct drm_device
*dev
= crtc
->base
.dev
;
4338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4339 int pipe
= crtc
->pipe
;
4342 if (IS_PINEVIEW(dev
)) {
4343 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4345 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4347 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4349 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4352 I915_WRITE(FP0(pipe
), fp
);
4353 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4355 crtc
->lowfreq_avail
= false;
4356 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4357 reduced_clock
&& i915_powersave
) {
4358 I915_WRITE(FP1(pipe
), fp2
);
4359 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4360 crtc
->lowfreq_avail
= true;
4362 I915_WRITE(FP1(pipe
), fp
);
4363 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4367 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
)
4372 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4373 * and set it to a reasonable value instead.
4375 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4376 reg_val
&= 0xffffff00;
4377 reg_val
|= 0x00000030;
4378 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4380 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4381 reg_val
&= 0x8cffffff;
4382 reg_val
= 0x8c000000;
4383 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4385 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4386 reg_val
&= 0xffffff00;
4387 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4389 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4390 reg_val
&= 0x00ffffff;
4391 reg_val
|= 0xb0000000;
4392 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4395 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4396 struct intel_link_m_n
*m_n
)
4398 struct drm_device
*dev
= crtc
->base
.dev
;
4399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4400 int pipe
= crtc
->pipe
;
4402 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4403 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4404 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4405 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4408 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4409 struct intel_link_m_n
*m_n
)
4411 struct drm_device
*dev
= crtc
->base
.dev
;
4412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4413 int pipe
= crtc
->pipe
;
4414 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4416 if (INTEL_INFO(dev
)->gen
>= 5) {
4417 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4418 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4419 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4420 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4422 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4423 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4424 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4425 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4429 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4431 if (crtc
->config
.has_pch_encoder
)
4432 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4434 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4437 static void vlv_update_pll(struct intel_crtc
*crtc
)
4439 struct drm_device
*dev
= crtc
->base
.dev
;
4440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4441 int pipe
= crtc
->pipe
;
4443 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4445 u32 coreclk
, reg_val
, dpll_md
;
4447 mutex_lock(&dev_priv
->dpio_lock
);
4449 is_hdmi
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4451 bestn
= crtc
->config
.dpll
.n
;
4452 bestm1
= crtc
->config
.dpll
.m1
;
4453 bestm2
= crtc
->config
.dpll
.m2
;
4454 bestp1
= crtc
->config
.dpll
.p1
;
4455 bestp2
= crtc
->config
.dpll
.p2
;
4457 /* See eDP HDMI DPIO driver vbios notes doc */
4459 /* PLL B needs special handling */
4461 vlv_pllb_recal_opamp(dev_priv
);
4463 /* Set up Tx target for periodic Rcomp update */
4464 vlv_dpio_write(dev_priv
, DPIO_IREF_BCAST
, 0x0100000f);
4466 /* Disable target IRef on PLL */
4467 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF_CTL(pipe
));
4468 reg_val
&= 0x00ffffff;
4469 vlv_dpio_write(dev_priv
, DPIO_IREF_CTL(pipe
), reg_val
);
4471 /* Disable fast lock */
4472 vlv_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x610);
4474 /* Set idtafcrecal before PLL is enabled */
4475 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4476 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4477 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4478 mdiv
|= (1 << DPIO_K_SHIFT
);
4481 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4482 * but we don't support that).
4483 * Note: don't use the DAC post divider as it seems unstable.
4485 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4486 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4488 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4489 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4491 /* Set HBR and RBR LPF coefficients */
4492 if (crtc
->config
.port_clock
== 162000 ||
4493 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4494 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4495 vlv_dpio_write(dev_priv
, DPIO_LPF_COEFF(pipe
),
4498 vlv_dpio_write(dev_priv
, DPIO_LPF_COEFF(pipe
),
4501 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4502 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4503 /* Use SSC source */
4505 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4508 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4510 } else { /* HDMI or VGA */
4511 /* Use bend source */
4513 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4516 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4520 coreclk
= vlv_dpio_read(dev_priv
, DPIO_CORE_CLK(pipe
));
4521 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4522 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4523 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4524 coreclk
|= 0x01000000;
4525 vlv_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), coreclk
);
4527 vlv_dpio_write(dev_priv
, DPIO_PLL_CML(pipe
), 0x87871000);
4529 /* Enable DPIO clock input */
4530 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4531 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4533 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4535 dpll
|= DPLL_VCO_ENABLE
;
4536 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4538 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4539 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4540 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4542 if (crtc
->config
.has_dp_encoder
)
4543 intel_dp_set_m_n(crtc
);
4545 mutex_unlock(&dev_priv
->dpio_lock
);
4548 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4549 intel_clock_t
*reduced_clock
,
4552 struct drm_device
*dev
= crtc
->base
.dev
;
4553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4556 struct dpll
*clock
= &crtc
->config
.dpll
;
4558 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4560 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4561 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4563 dpll
= DPLL_VGA_MODE_DIS
;
4565 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4566 dpll
|= DPLLB_MODE_LVDS
;
4568 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4570 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4571 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4572 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4576 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4578 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4579 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4581 /* compute bitmask from p1 value */
4582 if (IS_PINEVIEW(dev
))
4583 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4585 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4586 if (IS_G4X(dev
) && reduced_clock
)
4587 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4589 switch (clock
->p2
) {
4591 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4594 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4597 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4600 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4603 if (INTEL_INFO(dev
)->gen
>= 4)
4604 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4606 if (crtc
->config
.sdvo_tv_clock
)
4607 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4608 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4609 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4610 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4612 dpll
|= PLL_REF_INPUT_DREFCLK
;
4614 dpll
|= DPLL_VCO_ENABLE
;
4615 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4617 if (INTEL_INFO(dev
)->gen
>= 4) {
4618 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4619 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4620 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4623 if (crtc
->config
.has_dp_encoder
)
4624 intel_dp_set_m_n(crtc
);
4627 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4628 intel_clock_t
*reduced_clock
,
4631 struct drm_device
*dev
= crtc
->base
.dev
;
4632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4634 struct dpll
*clock
= &crtc
->config
.dpll
;
4636 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4638 dpll
= DPLL_VGA_MODE_DIS
;
4640 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4641 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4644 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4646 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4648 dpll
|= PLL_P2_DIVIDE_BY_4
;
4651 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4652 dpll
|= DPLL_DVO_2X_MODE
;
4654 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4655 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4656 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4658 dpll
|= PLL_REF_INPUT_DREFCLK
;
4660 dpll
|= DPLL_VCO_ENABLE
;
4661 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4664 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4666 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4668 enum pipe pipe
= intel_crtc
->pipe
;
4669 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4670 struct drm_display_mode
*adjusted_mode
=
4671 &intel_crtc
->config
.adjusted_mode
;
4672 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4673 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4675 /* We need to be careful not to changed the adjusted mode, for otherwise
4676 * the hw state checker will get angry at the mismatch. */
4677 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4678 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4680 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4681 /* the chip adds 2 halflines automatically */
4683 crtc_vblank_end
-= 1;
4684 vsyncshift
= adjusted_mode
->crtc_hsync_start
4685 - adjusted_mode
->crtc_htotal
/ 2;
4690 if (INTEL_INFO(dev
)->gen
> 3)
4691 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4693 I915_WRITE(HTOTAL(cpu_transcoder
),
4694 (adjusted_mode
->crtc_hdisplay
- 1) |
4695 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4696 I915_WRITE(HBLANK(cpu_transcoder
),
4697 (adjusted_mode
->crtc_hblank_start
- 1) |
4698 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4699 I915_WRITE(HSYNC(cpu_transcoder
),
4700 (adjusted_mode
->crtc_hsync_start
- 1) |
4701 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4703 I915_WRITE(VTOTAL(cpu_transcoder
),
4704 (adjusted_mode
->crtc_vdisplay
- 1) |
4705 ((crtc_vtotal
- 1) << 16));
4706 I915_WRITE(VBLANK(cpu_transcoder
),
4707 (adjusted_mode
->crtc_vblank_start
- 1) |
4708 ((crtc_vblank_end
- 1) << 16));
4709 I915_WRITE(VSYNC(cpu_transcoder
),
4710 (adjusted_mode
->crtc_vsync_start
- 1) |
4711 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4713 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4714 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4715 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4717 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4718 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4719 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4721 /* pipesrc controls the size that is scaled from, which should
4722 * always be the user's requested size.
4724 I915_WRITE(PIPESRC(pipe
),
4725 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4728 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4729 struct intel_crtc_config
*pipe_config
)
4731 struct drm_device
*dev
= crtc
->base
.dev
;
4732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4733 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4736 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4737 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4738 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4739 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4740 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4741 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4742 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4743 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4744 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4746 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4747 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4748 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4749 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4750 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4751 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4752 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4753 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4754 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4756 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4757 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4758 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4759 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4762 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4763 pipe_config
->requested_mode
.vdisplay
= (tmp
& 0xffff) + 1;
4764 pipe_config
->requested_mode
.hdisplay
= ((tmp
>> 16) & 0xffff) + 1;
4767 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4768 struct intel_crtc_config
*pipe_config
)
4770 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4772 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4773 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4774 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4775 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4777 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4778 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4779 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4780 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4782 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4784 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.clock
;
4785 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4788 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4790 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4796 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4797 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4800 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4803 if (intel_crtc
->config
.requested_mode
.clock
>
4804 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4805 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4808 /* only g4x and later have fancy bpc/dither controls */
4809 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4810 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4811 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4812 pipeconf
|= PIPECONF_DITHER_EN
|
4813 PIPECONF_DITHER_TYPE_SP
;
4815 switch (intel_crtc
->config
.pipe_bpp
) {
4817 pipeconf
|= PIPECONF_6BPC
;
4820 pipeconf
|= PIPECONF_8BPC
;
4823 pipeconf
|= PIPECONF_10BPC
;
4826 /* Case prevented by intel_choose_pipe_bpp_dither. */
4831 if (HAS_PIPE_CXSR(dev
)) {
4832 if (intel_crtc
->lowfreq_avail
) {
4833 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4834 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4836 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4840 if (!IS_GEN2(dev
) &&
4841 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4842 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4844 pipeconf
|= PIPECONF_PROGRESSIVE
;
4846 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4847 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4849 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4850 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4853 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4855 struct drm_framebuffer
*fb
)
4857 struct drm_device
*dev
= crtc
->dev
;
4858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4860 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4861 int pipe
= intel_crtc
->pipe
;
4862 int plane
= intel_crtc
->plane
;
4863 int refclk
, num_connectors
= 0;
4864 intel_clock_t clock
, reduced_clock
;
4866 bool ok
, has_reduced_clock
= false;
4867 bool is_lvds
= false;
4868 struct intel_encoder
*encoder
;
4869 const intel_limit_t
*limit
;
4872 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4873 switch (encoder
->type
) {
4874 case INTEL_OUTPUT_LVDS
:
4882 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4885 * Returns a set of divisors for the desired target clock with the given
4886 * refclk, or FALSE. The returned values represent the clock equation:
4887 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4889 limit
= intel_limit(crtc
, refclk
);
4890 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4891 intel_crtc
->config
.port_clock
,
4892 refclk
, NULL
, &clock
);
4893 if (!ok
&& !intel_crtc
->config
.clock_set
) {
4894 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4898 /* Ensure that the cursor is valid for the new mode before changing... */
4899 intel_crtc_update_cursor(crtc
, true);
4901 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4903 * Ensure we match the reduced clock's P to the target clock.
4904 * If the clocks don't match, we can't switch the display clock
4905 * by using the FP0/FP1. In such case we will disable the LVDS
4906 * downclock feature.
4909 dev_priv
->display
.find_dpll(limit
, crtc
,
4910 dev_priv
->lvds_downclock
,
4914 /* Compat-code for transition, will disappear. */
4915 if (!intel_crtc
->config
.clock_set
) {
4916 intel_crtc
->config
.dpll
.n
= clock
.n
;
4917 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4918 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4919 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4920 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4924 i8xx_update_pll(intel_crtc
,
4925 has_reduced_clock
? &reduced_clock
: NULL
,
4927 else if (IS_VALLEYVIEW(dev
))
4928 vlv_update_pll(intel_crtc
);
4930 i9xx_update_pll(intel_crtc
,
4931 has_reduced_clock
? &reduced_clock
: NULL
,
4934 /* Set up the display plane register */
4935 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4937 if (!IS_VALLEYVIEW(dev
)) {
4939 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4941 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4944 intel_set_pipe_timings(intel_crtc
);
4946 /* pipesrc and dspsize control the size that is scaled from,
4947 * which should always be the user's requested size.
4949 I915_WRITE(DSPSIZE(plane
),
4950 ((mode
->vdisplay
- 1) << 16) |
4951 (mode
->hdisplay
- 1));
4952 I915_WRITE(DSPPOS(plane
), 0);
4954 i9xx_set_pipeconf(intel_crtc
);
4956 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4957 POSTING_READ(DSPCNTR(plane
));
4959 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4961 intel_update_watermarks(dev
);
4966 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
4967 struct intel_crtc_config
*pipe_config
)
4969 struct drm_device
*dev
= crtc
->base
.dev
;
4970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4973 tmp
= I915_READ(PFIT_CONTROL
);
4974 if (!(tmp
& PFIT_ENABLE
))
4977 /* Check whether the pfit is attached to our pipe. */
4978 if (INTEL_INFO(dev
)->gen
< 4) {
4979 if (crtc
->pipe
!= PIPE_B
)
4982 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
4986 pipe_config
->gmch_pfit
.control
= tmp
;
4987 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
4988 if (INTEL_INFO(dev
)->gen
< 5)
4989 pipe_config
->gmch_pfit
.lvds_border_bits
=
4990 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
4993 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4994 struct intel_crtc_config
*pipe_config
)
4996 struct drm_device
*dev
= crtc
->base
.dev
;
4997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5000 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5001 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5003 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5004 if (!(tmp
& PIPECONF_ENABLE
))
5007 intel_get_pipe_timings(crtc
, pipe_config
);
5009 i9xx_get_pfit_config(crtc
, pipe_config
);
5011 if (INTEL_INFO(dev
)->gen
>= 4) {
5012 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5013 pipe_config
->pixel_multiplier
=
5014 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5015 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5016 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5017 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5018 tmp
= I915_READ(DPLL(crtc
->pipe
));
5019 pipe_config
->pixel_multiplier
=
5020 ((tmp
& SDVO_MULTIPLIER_MASK
)
5021 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5023 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5024 * port and will be fixed up in the encoder->get_config
5026 pipe_config
->pixel_multiplier
= 1;
5028 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5029 if (!IS_VALLEYVIEW(dev
)) {
5030 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5031 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5033 /* Mask out read-only status bits. */
5034 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5035 DPLL_PORTC_READY_MASK
|
5036 DPLL_PORTB_READY_MASK
);
5042 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5045 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5046 struct intel_encoder
*encoder
;
5048 bool has_lvds
= false;
5049 bool has_cpu_edp
= false;
5050 bool has_panel
= false;
5051 bool has_ck505
= false;
5052 bool can_ssc
= false;
5054 /* We need to take the global config into account */
5055 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5057 switch (encoder
->type
) {
5058 case INTEL_OUTPUT_LVDS
:
5062 case INTEL_OUTPUT_EDP
:
5064 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5070 if (HAS_PCH_IBX(dev
)) {
5071 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5072 can_ssc
= has_ck505
;
5078 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5079 has_panel
, has_lvds
, has_ck505
);
5081 /* Ironlake: try to setup display ref clock before DPLL
5082 * enabling. This is only under driver's control after
5083 * PCH B stepping, previous chipset stepping should be
5084 * ignoring this setting.
5086 val
= I915_READ(PCH_DREF_CONTROL
);
5088 /* As we must carefully and slowly disable/enable each source in turn,
5089 * compute the final state we want first and check if we need to
5090 * make any changes at all.
5093 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5095 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5097 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5099 final
&= ~DREF_SSC_SOURCE_MASK
;
5100 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5101 final
&= ~DREF_SSC1_ENABLE
;
5104 final
|= DREF_SSC_SOURCE_ENABLE
;
5106 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5107 final
|= DREF_SSC1_ENABLE
;
5110 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5111 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5113 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5115 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5117 final
|= DREF_SSC_SOURCE_DISABLE
;
5118 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5124 /* Always enable nonspread source */
5125 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5128 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5130 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5133 val
&= ~DREF_SSC_SOURCE_MASK
;
5134 val
|= DREF_SSC_SOURCE_ENABLE
;
5136 /* SSC must be turned on before enabling the CPU output */
5137 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5138 DRM_DEBUG_KMS("Using SSC on panel\n");
5139 val
|= DREF_SSC1_ENABLE
;
5141 val
&= ~DREF_SSC1_ENABLE
;
5143 /* Get SSC going before enabling the outputs */
5144 I915_WRITE(PCH_DREF_CONTROL
, val
);
5145 POSTING_READ(PCH_DREF_CONTROL
);
5148 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5150 /* Enable CPU source on CPU attached eDP */
5152 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5153 DRM_DEBUG_KMS("Using SSC on eDP\n");
5154 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5157 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5159 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5161 I915_WRITE(PCH_DREF_CONTROL
, val
);
5162 POSTING_READ(PCH_DREF_CONTROL
);
5165 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5167 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5169 /* Turn off CPU output */
5170 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5172 I915_WRITE(PCH_DREF_CONTROL
, val
);
5173 POSTING_READ(PCH_DREF_CONTROL
);
5176 /* Turn off the SSC source */
5177 val
&= ~DREF_SSC_SOURCE_MASK
;
5178 val
|= DREF_SSC_SOURCE_DISABLE
;
5181 val
&= ~DREF_SSC1_ENABLE
;
5183 I915_WRITE(PCH_DREF_CONTROL
, val
);
5184 POSTING_READ(PCH_DREF_CONTROL
);
5188 BUG_ON(val
!= final
);
5191 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5195 tmp
= I915_READ(SOUTH_CHICKEN2
);
5196 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5197 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5199 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5200 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5201 DRM_ERROR("FDI mPHY reset assert timeout\n");
5203 tmp
= I915_READ(SOUTH_CHICKEN2
);
5204 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5205 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5207 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5208 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5209 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5212 /* WaMPhyProgramming:hsw */
5213 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5217 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5218 tmp
&= ~(0xFF << 24);
5219 tmp
|= (0x12 << 24);
5220 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5222 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5224 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5226 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5228 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5230 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5231 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5232 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5234 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5235 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5236 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5238 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5241 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5243 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5246 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5248 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5251 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5253 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5256 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5258 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5259 tmp
&= ~(0xFF << 16);
5260 tmp
|= (0x1C << 16);
5261 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5263 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5264 tmp
&= ~(0xFF << 16);
5265 tmp
|= (0x1C << 16);
5266 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5268 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5270 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5272 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5274 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5276 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5277 tmp
&= ~(0xF << 28);
5279 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5281 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5282 tmp
&= ~(0xF << 28);
5284 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5287 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5288 * Programming" based on the parameters passed:
5289 * - Sequence to enable CLKOUT_DP
5290 * - Sequence to enable CLKOUT_DP without spread
5291 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5293 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5299 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5301 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5302 with_fdi
, "LP PCH doesn't have FDI\n"))
5305 mutex_lock(&dev_priv
->dpio_lock
);
5307 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5308 tmp
&= ~SBI_SSCCTL_DISABLE
;
5309 tmp
|= SBI_SSCCTL_PATHALT
;
5310 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5315 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5316 tmp
&= ~SBI_SSCCTL_PATHALT
;
5317 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5320 lpt_reset_fdi_mphy(dev_priv
);
5321 lpt_program_fdi_mphy(dev_priv
);
5325 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5326 SBI_GEN0
: SBI_DBUFF0
;
5327 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5328 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5329 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5331 mutex_unlock(&dev_priv
->dpio_lock
);
5334 /* Sequence to disable CLKOUT_DP */
5335 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5340 mutex_lock(&dev_priv
->dpio_lock
);
5342 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5343 SBI_GEN0
: SBI_DBUFF0
;
5344 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5345 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5346 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5348 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5349 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5350 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5351 tmp
|= SBI_SSCCTL_PATHALT
;
5352 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5355 tmp
|= SBI_SSCCTL_DISABLE
;
5356 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5359 mutex_unlock(&dev_priv
->dpio_lock
);
5362 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5364 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5365 struct intel_encoder
*encoder
;
5366 bool has_vga
= false;
5368 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5369 switch (encoder
->type
) {
5370 case INTEL_OUTPUT_ANALOG
:
5377 lpt_enable_clkout_dp(dev
, true, true);
5379 lpt_disable_clkout_dp(dev
);
5383 * Initialize reference clocks when the driver loads
5385 void intel_init_pch_refclk(struct drm_device
*dev
)
5387 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5388 ironlake_init_pch_refclk(dev
);
5389 else if (HAS_PCH_LPT(dev
))
5390 lpt_init_pch_refclk(dev
);
5393 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5395 struct drm_device
*dev
= crtc
->dev
;
5396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5397 struct intel_encoder
*encoder
;
5398 int num_connectors
= 0;
5399 bool is_lvds
= false;
5401 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5402 switch (encoder
->type
) {
5403 case INTEL_OUTPUT_LVDS
:
5410 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5411 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5412 dev_priv
->vbt
.lvds_ssc_freq
);
5413 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5419 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5421 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5422 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5423 int pipe
= intel_crtc
->pipe
;
5428 switch (intel_crtc
->config
.pipe_bpp
) {
5430 val
|= PIPECONF_6BPC
;
5433 val
|= PIPECONF_8BPC
;
5436 val
|= PIPECONF_10BPC
;
5439 val
|= PIPECONF_12BPC
;
5442 /* Case prevented by intel_choose_pipe_bpp_dither. */
5446 if (intel_crtc
->config
.dither
)
5447 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5449 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5450 val
|= PIPECONF_INTERLACED_ILK
;
5452 val
|= PIPECONF_PROGRESSIVE
;
5454 if (intel_crtc
->config
.limited_color_range
)
5455 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5457 I915_WRITE(PIPECONF(pipe
), val
);
5458 POSTING_READ(PIPECONF(pipe
));
5462 * Set up the pipe CSC unit.
5464 * Currently only full range RGB to limited range RGB conversion
5465 * is supported, but eventually this should handle various
5466 * RGB<->YCbCr scenarios as well.
5468 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5470 struct drm_device
*dev
= crtc
->dev
;
5471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5472 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5473 int pipe
= intel_crtc
->pipe
;
5474 uint16_t coeff
= 0x7800; /* 1.0 */
5477 * TODO: Check what kind of values actually come out of the pipe
5478 * with these coeff/postoff values and adjust to get the best
5479 * accuracy. Perhaps we even need to take the bpc value into
5483 if (intel_crtc
->config
.limited_color_range
)
5484 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5487 * GY/GU and RY/RU should be the other way around according
5488 * to BSpec, but reality doesn't agree. Just set them up in
5489 * a way that results in the correct picture.
5491 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5492 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5494 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5495 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5497 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5498 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5500 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5501 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5502 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5504 if (INTEL_INFO(dev
)->gen
> 6) {
5505 uint16_t postoff
= 0;
5507 if (intel_crtc
->config
.limited_color_range
)
5508 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5510 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5511 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5512 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5514 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5516 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5518 if (intel_crtc
->config
.limited_color_range
)
5519 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5521 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5525 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5527 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5528 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5529 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5534 if (intel_crtc
->config
.dither
)
5535 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5537 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5538 val
|= PIPECONF_INTERLACED_ILK
;
5540 val
|= PIPECONF_PROGRESSIVE
;
5542 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5543 POSTING_READ(PIPECONF(cpu_transcoder
));
5545 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5546 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5549 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5550 intel_clock_t
*clock
,
5551 bool *has_reduced_clock
,
5552 intel_clock_t
*reduced_clock
)
5554 struct drm_device
*dev
= crtc
->dev
;
5555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5556 struct intel_encoder
*intel_encoder
;
5558 const intel_limit_t
*limit
;
5559 bool ret
, is_lvds
= false;
5561 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5562 switch (intel_encoder
->type
) {
5563 case INTEL_OUTPUT_LVDS
:
5569 refclk
= ironlake_get_refclk(crtc
);
5572 * Returns a set of divisors for the desired target clock with the given
5573 * refclk, or FALSE. The returned values represent the clock equation:
5574 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5576 limit
= intel_limit(crtc
, refclk
);
5577 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5578 to_intel_crtc(crtc
)->config
.port_clock
,
5579 refclk
, NULL
, clock
);
5583 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5585 * Ensure we match the reduced clock's P to the target clock.
5586 * If the clocks don't match, we can't switch the display clock
5587 * by using the FP0/FP1. In such case we will disable the LVDS
5588 * downclock feature.
5590 *has_reduced_clock
=
5591 dev_priv
->display
.find_dpll(limit
, crtc
,
5592 dev_priv
->lvds_downclock
,
5600 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5605 temp
= I915_READ(SOUTH_CHICKEN1
);
5606 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5609 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5610 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5612 temp
|= FDI_BC_BIFURCATION_SELECT
;
5613 DRM_DEBUG_KMS("enabling fdi C rx\n");
5614 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5615 POSTING_READ(SOUTH_CHICKEN1
);
5618 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5620 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5623 switch (intel_crtc
->pipe
) {
5627 if (intel_crtc
->config
.fdi_lanes
> 2)
5628 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5630 cpt_enable_fdi_bc_bifurcation(dev
);
5634 cpt_enable_fdi_bc_bifurcation(dev
);
5642 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5645 * Account for spread spectrum to avoid
5646 * oversubscribing the link. Max center spread
5647 * is 2.5%; use 5% for safety's sake.
5649 u32 bps
= target_clock
* bpp
* 21 / 20;
5650 return bps
/ (link_bw
* 8) + 1;
5653 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5655 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5658 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5660 intel_clock_t
*reduced_clock
, u32
*fp2
)
5662 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5663 struct drm_device
*dev
= crtc
->dev
;
5664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5665 struct intel_encoder
*intel_encoder
;
5667 int factor
, num_connectors
= 0;
5668 bool is_lvds
= false, is_sdvo
= false;
5670 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5671 switch (intel_encoder
->type
) {
5672 case INTEL_OUTPUT_LVDS
:
5675 case INTEL_OUTPUT_SDVO
:
5676 case INTEL_OUTPUT_HDMI
:
5684 /* Enable autotuning of the PLL clock (if permissible) */
5687 if ((intel_panel_use_ssc(dev_priv
) &&
5688 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5689 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5691 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5694 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5697 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5703 dpll
|= DPLLB_MODE_LVDS
;
5705 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5707 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5708 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5711 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5712 if (intel_crtc
->config
.has_dp_encoder
)
5713 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5715 /* compute bitmask from p1 value */
5716 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5718 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5720 switch (intel_crtc
->config
.dpll
.p2
) {
5722 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5725 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5728 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5731 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5735 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5736 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5738 dpll
|= PLL_REF_INPUT_DREFCLK
;
5740 return dpll
| DPLL_VCO_ENABLE
;
5743 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5745 struct drm_framebuffer
*fb
)
5747 struct drm_device
*dev
= crtc
->dev
;
5748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5749 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5750 int pipe
= intel_crtc
->pipe
;
5751 int plane
= intel_crtc
->plane
;
5752 int num_connectors
= 0;
5753 intel_clock_t clock
, reduced_clock
;
5754 u32 dpll
= 0, fp
= 0, fp2
= 0;
5755 bool ok
, has_reduced_clock
= false;
5756 bool is_lvds
= false;
5757 struct intel_encoder
*encoder
;
5758 struct intel_shared_dpll
*pll
;
5761 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5762 switch (encoder
->type
) {
5763 case INTEL_OUTPUT_LVDS
:
5771 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5772 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5774 ok
= ironlake_compute_clocks(crtc
, &clock
,
5775 &has_reduced_clock
, &reduced_clock
);
5776 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5777 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5780 /* Compat-code for transition, will disappear. */
5781 if (!intel_crtc
->config
.clock_set
) {
5782 intel_crtc
->config
.dpll
.n
= clock
.n
;
5783 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5784 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5785 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5786 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5789 /* Ensure that the cursor is valid for the new mode before changing... */
5790 intel_crtc_update_cursor(crtc
, true);
5792 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5793 if (intel_crtc
->config
.has_pch_encoder
) {
5794 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5795 if (has_reduced_clock
)
5796 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5798 dpll
= ironlake_compute_dpll(intel_crtc
,
5799 &fp
, &reduced_clock
,
5800 has_reduced_clock
? &fp2
: NULL
);
5802 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5803 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5804 if (has_reduced_clock
)
5805 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5807 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5809 pll
= intel_get_shared_dpll(intel_crtc
);
5811 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5816 intel_put_shared_dpll(intel_crtc
);
5818 if (intel_crtc
->config
.has_dp_encoder
)
5819 intel_dp_set_m_n(intel_crtc
);
5821 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5822 intel_crtc
->lowfreq_avail
= true;
5824 intel_crtc
->lowfreq_avail
= false;
5826 if (intel_crtc
->config
.has_pch_encoder
) {
5827 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5831 intel_set_pipe_timings(intel_crtc
);
5833 if (intel_crtc
->config
.has_pch_encoder
) {
5834 intel_cpu_transcoder_set_m_n(intel_crtc
,
5835 &intel_crtc
->config
.fdi_m_n
);
5838 if (IS_IVYBRIDGE(dev
))
5839 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5841 ironlake_set_pipeconf(crtc
);
5843 /* Set up the display plane register */
5844 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5845 POSTING_READ(DSPCNTR(plane
));
5847 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5849 intel_update_watermarks(dev
);
5854 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
5855 struct intel_crtc_config
*pipe_config
)
5857 struct drm_device
*dev
= crtc
->base
.dev
;
5858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5859 enum transcoder transcoder
= pipe_config
->cpu_transcoder
;
5861 pipe_config
->fdi_m_n
.link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
5862 pipe_config
->fdi_m_n
.link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
5863 pipe_config
->fdi_m_n
.gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
5865 pipe_config
->fdi_m_n
.gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
5866 pipe_config
->fdi_m_n
.tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
5867 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5870 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
5871 struct intel_crtc_config
*pipe_config
)
5873 struct drm_device
*dev
= crtc
->base
.dev
;
5874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5877 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
5879 if (tmp
& PF_ENABLE
) {
5880 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
5881 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
5883 /* We currently do not free assignements of panel fitters on
5884 * ivb/hsw (since we don't use the higher upscaling modes which
5885 * differentiates them) so just WARN about this case for now. */
5887 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
5888 PF_PIPE_SEL_IVB(crtc
->pipe
));
5893 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5894 struct intel_crtc_config
*pipe_config
)
5896 struct drm_device
*dev
= crtc
->base
.dev
;
5897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5900 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5901 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5903 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5904 if (!(tmp
& PIPECONF_ENABLE
))
5907 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
5908 struct intel_shared_dpll
*pll
;
5910 pipe_config
->has_pch_encoder
= true;
5912 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
5913 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
5914 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
5916 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
5918 if (HAS_PCH_IBX(dev_priv
->dev
)) {
5919 pipe_config
->shared_dpll
=
5920 (enum intel_dpll_id
) crtc
->pipe
;
5922 tmp
= I915_READ(PCH_DPLL_SEL
);
5923 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
5924 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
5926 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
5929 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
5931 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
5932 &pipe_config
->dpll_hw_state
));
5934 tmp
= pipe_config
->dpll_hw_state
.dpll
;
5935 pipe_config
->pixel_multiplier
=
5936 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
5937 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
5939 pipe_config
->pixel_multiplier
= 1;
5942 intel_get_pipe_timings(crtc
, pipe_config
);
5944 ironlake_get_pfit_config(crtc
, pipe_config
);
5949 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
5951 struct drm_device
*dev
= dev_priv
->dev
;
5952 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
5953 struct intel_crtc
*crtc
;
5954 unsigned long irqflags
;
5955 uint32_t val
, pch_hpd_mask
;
5957 pch_hpd_mask
= SDE_PORTB_HOTPLUG_CPT
| SDE_PORTC_HOTPLUG_CPT
;
5958 if (!(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
))
5959 pch_hpd_mask
|= SDE_PORTD_HOTPLUG_CPT
| SDE_CRT_HOTPLUG_CPT
;
5961 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
5962 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
5963 pipe_name(crtc
->pipe
));
5965 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
5966 WARN(plls
->spll_refcount
, "SPLL enabled\n");
5967 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
5968 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
5969 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
5970 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
5971 "CPU PWM1 enabled\n");
5972 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
5973 "CPU PWM2 enabled\n");
5974 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
5975 "PCH PWM1 enabled\n");
5976 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
5977 "Utility pin enabled\n");
5978 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
5980 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
5981 val
= I915_READ(DEIMR
);
5982 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
5983 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
5984 val
= I915_READ(SDEIMR
);
5985 WARN((val
& ~pch_hpd_mask
) != val
,
5986 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
5987 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
5991 * This function implements pieces of two sequences from BSpec:
5992 * - Sequence for display software to disable LCPLL
5993 * - Sequence for display software to allow package C8+
5994 * The steps implemented here are just the steps that actually touch the LCPLL
5995 * register. Callers should take care of disabling all the display engine
5996 * functions, doing the mode unset, fixing interrupts, etc.
5998 void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
5999 bool switch_to_fclk
, bool allow_power_down
)
6003 assert_can_disable_lcpll(dev_priv
);
6005 val
= I915_READ(LCPLL_CTL
);
6007 if (switch_to_fclk
) {
6008 val
|= LCPLL_CD_SOURCE_FCLK
;
6009 I915_WRITE(LCPLL_CTL
, val
);
6011 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6012 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6013 DRM_ERROR("Switching to FCLK failed\n");
6015 val
= I915_READ(LCPLL_CTL
);
6018 val
|= LCPLL_PLL_DISABLE
;
6019 I915_WRITE(LCPLL_CTL
, val
);
6020 POSTING_READ(LCPLL_CTL
);
6022 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6023 DRM_ERROR("LCPLL still locked\n");
6025 val
= I915_READ(D_COMP
);
6026 val
|= D_COMP_COMP_DISABLE
;
6027 I915_WRITE(D_COMP
, val
);
6028 POSTING_READ(D_COMP
);
6031 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6032 DRM_ERROR("D_COMP RCOMP still in progress\n");
6034 if (allow_power_down
) {
6035 val
= I915_READ(LCPLL_CTL
);
6036 val
|= LCPLL_POWER_DOWN_ALLOW
;
6037 I915_WRITE(LCPLL_CTL
, val
);
6038 POSTING_READ(LCPLL_CTL
);
6043 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6046 void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6050 val
= I915_READ(LCPLL_CTL
);
6052 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6053 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6056 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6057 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6058 I915_WRITE(LCPLL_CTL
, val
);
6061 val
= I915_READ(D_COMP
);
6062 val
|= D_COMP_COMP_FORCE
;
6063 val
&= ~D_COMP_COMP_DISABLE
;
6064 I915_WRITE(D_COMP
, val
);
6067 val
= I915_READ(LCPLL_CTL
);
6068 val
&= ~LCPLL_PLL_DISABLE
;
6069 I915_WRITE(LCPLL_CTL
, val
);
6071 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6072 DRM_ERROR("LCPLL not locked yet\n");
6074 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6075 val
= I915_READ(LCPLL_CTL
);
6076 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6077 I915_WRITE(LCPLL_CTL
, val
);
6079 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6080 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6081 DRM_ERROR("Switching back to LCPLL failed\n");
6085 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6087 bool enable
= false;
6088 struct intel_crtc
*crtc
;
6090 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6091 if (!crtc
->base
.enabled
)
6094 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.size
||
6095 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6099 intel_set_power_well(dev
, enable
);
6102 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6104 struct drm_framebuffer
*fb
)
6106 struct drm_device
*dev
= crtc
->dev
;
6107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6108 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6109 int plane
= intel_crtc
->plane
;
6112 if (!intel_ddi_pll_mode_set(crtc
))
6115 /* Ensure that the cursor is valid for the new mode before changing... */
6116 intel_crtc_update_cursor(crtc
, true);
6118 if (intel_crtc
->config
.has_dp_encoder
)
6119 intel_dp_set_m_n(intel_crtc
);
6121 intel_crtc
->lowfreq_avail
= false;
6123 intel_set_pipe_timings(intel_crtc
);
6125 if (intel_crtc
->config
.has_pch_encoder
) {
6126 intel_cpu_transcoder_set_m_n(intel_crtc
,
6127 &intel_crtc
->config
.fdi_m_n
);
6130 haswell_set_pipeconf(crtc
);
6132 intel_set_pipe_csc(crtc
);
6134 /* Set up the display plane register */
6135 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6136 POSTING_READ(DSPCNTR(plane
));
6138 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6140 intel_update_watermarks(dev
);
6145 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6146 struct intel_crtc_config
*pipe_config
)
6148 struct drm_device
*dev
= crtc
->base
.dev
;
6149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6150 enum intel_display_power_domain pfit_domain
;
6153 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6154 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6156 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6157 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6158 enum pipe trans_edp_pipe
;
6159 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6161 WARN(1, "unknown pipe linked to edp transcoder\n");
6162 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6163 case TRANS_DDI_EDP_INPUT_A_ON
:
6164 trans_edp_pipe
= PIPE_A
;
6166 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6167 trans_edp_pipe
= PIPE_B
;
6169 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6170 trans_edp_pipe
= PIPE_C
;
6174 if (trans_edp_pipe
== crtc
->pipe
)
6175 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6178 if (!intel_display_power_enabled(dev
,
6179 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6182 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6183 if (!(tmp
& PIPECONF_ENABLE
))
6187 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6188 * DDI E. So just check whether this pipe is wired to DDI E and whether
6189 * the PCH transcoder is on.
6191 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6192 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6193 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6194 pipe_config
->has_pch_encoder
= true;
6196 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6197 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6198 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6200 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6203 intel_get_pipe_timings(crtc
, pipe_config
);
6205 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6206 if (intel_display_power_enabled(dev
, pfit_domain
))
6207 ironlake_get_pfit_config(crtc
, pipe_config
);
6209 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6210 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6212 pipe_config
->pixel_multiplier
= 1;
6217 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6219 struct drm_framebuffer
*fb
)
6221 struct drm_device
*dev
= crtc
->dev
;
6222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6223 struct drm_encoder_helper_funcs
*encoder_funcs
;
6224 struct intel_encoder
*encoder
;
6225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6226 struct drm_display_mode
*adjusted_mode
=
6227 &intel_crtc
->config
.adjusted_mode
;
6228 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6229 int pipe
= intel_crtc
->pipe
;
6232 drm_vblank_pre_modeset(dev
, pipe
);
6234 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6236 drm_vblank_post_modeset(dev
, pipe
);
6241 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6242 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6243 encoder
->base
.base
.id
,
6244 drm_get_encoder_name(&encoder
->base
),
6245 mode
->base
.id
, mode
->name
);
6246 if (encoder
->mode_set
) {
6247 encoder
->mode_set(encoder
);
6249 encoder_funcs
= encoder
->base
.helper_private
;
6250 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
6257 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6258 int reg_eldv
, uint32_t bits_eldv
,
6259 int reg_elda
, uint32_t bits_elda
,
6262 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6263 uint8_t *eld
= connector
->eld
;
6266 i
= I915_READ(reg_eldv
);
6275 i
= I915_READ(reg_elda
);
6277 I915_WRITE(reg_elda
, i
);
6279 for (i
= 0; i
< eld
[2]; i
++)
6280 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6286 static void g4x_write_eld(struct drm_connector
*connector
,
6287 struct drm_crtc
*crtc
)
6289 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6290 uint8_t *eld
= connector
->eld
;
6295 i
= I915_READ(G4X_AUD_VID_DID
);
6297 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6298 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6300 eldv
= G4X_ELDV_DEVCTG
;
6302 if (intel_eld_uptodate(connector
,
6303 G4X_AUD_CNTL_ST
, eldv
,
6304 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6305 G4X_HDMIW_HDMIEDID
))
6308 i
= I915_READ(G4X_AUD_CNTL_ST
);
6309 i
&= ~(eldv
| G4X_ELD_ADDR
);
6310 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6311 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6316 len
= min_t(uint8_t, eld
[2], len
);
6317 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6318 for (i
= 0; i
< len
; i
++)
6319 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6321 i
= I915_READ(G4X_AUD_CNTL_ST
);
6323 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6326 static void haswell_write_eld(struct drm_connector
*connector
,
6327 struct drm_crtc
*crtc
)
6329 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6330 uint8_t *eld
= connector
->eld
;
6331 struct drm_device
*dev
= crtc
->dev
;
6332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6336 int pipe
= to_intel_crtc(crtc
)->pipe
;
6339 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6340 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6341 int aud_config
= HSW_AUD_CFG(pipe
);
6342 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6345 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6347 /* Audio output enable */
6348 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6349 tmp
= I915_READ(aud_cntrl_st2
);
6350 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6351 I915_WRITE(aud_cntrl_st2
, tmp
);
6353 /* Wait for 1 vertical blank */
6354 intel_wait_for_vblank(dev
, pipe
);
6356 /* Set ELD valid state */
6357 tmp
= I915_READ(aud_cntrl_st2
);
6358 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6359 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6360 I915_WRITE(aud_cntrl_st2
, tmp
);
6361 tmp
= I915_READ(aud_cntrl_st2
);
6362 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6364 /* Enable HDMI mode */
6365 tmp
= I915_READ(aud_config
);
6366 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6367 /* clear N_programing_enable and N_value_index */
6368 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6369 I915_WRITE(aud_config
, tmp
);
6371 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6373 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6374 intel_crtc
->eld_vld
= true;
6376 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6377 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6378 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6379 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6381 I915_WRITE(aud_config
, 0);
6383 if (intel_eld_uptodate(connector
,
6384 aud_cntrl_st2
, eldv
,
6385 aud_cntl_st
, IBX_ELD_ADDRESS
,
6389 i
= I915_READ(aud_cntrl_st2
);
6391 I915_WRITE(aud_cntrl_st2
, i
);
6396 i
= I915_READ(aud_cntl_st
);
6397 i
&= ~IBX_ELD_ADDRESS
;
6398 I915_WRITE(aud_cntl_st
, i
);
6399 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6400 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6402 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6403 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6404 for (i
= 0; i
< len
; i
++)
6405 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6407 i
= I915_READ(aud_cntrl_st2
);
6409 I915_WRITE(aud_cntrl_st2
, i
);
6413 static void ironlake_write_eld(struct drm_connector
*connector
,
6414 struct drm_crtc
*crtc
)
6416 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6417 uint8_t *eld
= connector
->eld
;
6425 int pipe
= to_intel_crtc(crtc
)->pipe
;
6427 if (HAS_PCH_IBX(connector
->dev
)) {
6428 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6429 aud_config
= IBX_AUD_CFG(pipe
);
6430 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6431 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6433 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6434 aud_config
= CPT_AUD_CFG(pipe
);
6435 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6436 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6439 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6441 i
= I915_READ(aud_cntl_st
);
6442 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6444 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6445 /* operate blindly on all ports */
6446 eldv
= IBX_ELD_VALIDB
;
6447 eldv
|= IBX_ELD_VALIDB
<< 4;
6448 eldv
|= IBX_ELD_VALIDB
<< 8;
6450 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6451 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6454 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6455 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6456 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6457 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6459 I915_WRITE(aud_config
, 0);
6461 if (intel_eld_uptodate(connector
,
6462 aud_cntrl_st2
, eldv
,
6463 aud_cntl_st
, IBX_ELD_ADDRESS
,
6467 i
= I915_READ(aud_cntrl_st2
);
6469 I915_WRITE(aud_cntrl_st2
, i
);
6474 i
= I915_READ(aud_cntl_st
);
6475 i
&= ~IBX_ELD_ADDRESS
;
6476 I915_WRITE(aud_cntl_st
, i
);
6478 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6479 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6480 for (i
= 0; i
< len
; i
++)
6481 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6483 i
= I915_READ(aud_cntrl_st2
);
6485 I915_WRITE(aud_cntrl_st2
, i
);
6488 void intel_write_eld(struct drm_encoder
*encoder
,
6489 struct drm_display_mode
*mode
)
6491 struct drm_crtc
*crtc
= encoder
->crtc
;
6492 struct drm_connector
*connector
;
6493 struct drm_device
*dev
= encoder
->dev
;
6494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6496 connector
= drm_select_eld(encoder
, mode
);
6500 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6502 drm_get_connector_name(connector
),
6503 connector
->encoder
->base
.id
,
6504 drm_get_encoder_name(connector
->encoder
));
6506 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6508 if (dev_priv
->display
.write_eld
)
6509 dev_priv
->display
.write_eld(connector
, crtc
);
6512 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6513 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6515 struct drm_device
*dev
= crtc
->dev
;
6516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6517 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6518 enum pipe pipe
= intel_crtc
->pipe
;
6519 int palreg
= PALETTE(pipe
);
6521 bool reenable_ips
= false;
6523 /* The clocks have to be on to load the palette. */
6524 if (!crtc
->enabled
|| !intel_crtc
->active
)
6527 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
6528 assert_pll_enabled(dev_priv
, pipe
);
6530 /* use legacy palette for Ironlake */
6531 if (HAS_PCH_SPLIT(dev
))
6532 palreg
= LGC_PALETTE(pipe
);
6534 /* Workaround : Do not read or write the pipe palette/gamma data while
6535 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6537 if (intel_crtc
->config
.ips_enabled
&&
6538 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
6539 GAMMA_MODE_MODE_SPLIT
)) {
6540 hsw_disable_ips(intel_crtc
);
6541 reenable_ips
= true;
6544 for (i
= 0; i
< 256; i
++) {
6545 I915_WRITE(palreg
+ 4 * i
,
6546 (intel_crtc
->lut_r
[i
] << 16) |
6547 (intel_crtc
->lut_g
[i
] << 8) |
6548 intel_crtc
->lut_b
[i
]);
6552 hsw_enable_ips(intel_crtc
);
6555 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6557 struct drm_device
*dev
= crtc
->dev
;
6558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6559 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6560 bool visible
= base
!= 0;
6563 if (intel_crtc
->cursor_visible
== visible
)
6566 cntl
= I915_READ(_CURACNTR
);
6568 /* On these chipsets we can only modify the base whilst
6569 * the cursor is disabled.
6571 I915_WRITE(_CURABASE
, base
);
6573 cntl
&= ~(CURSOR_FORMAT_MASK
);
6574 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6575 cntl
|= CURSOR_ENABLE
|
6576 CURSOR_GAMMA_ENABLE
|
6579 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6580 I915_WRITE(_CURACNTR
, cntl
);
6582 intel_crtc
->cursor_visible
= visible
;
6585 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6587 struct drm_device
*dev
= crtc
->dev
;
6588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6589 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6590 int pipe
= intel_crtc
->pipe
;
6591 bool visible
= base
!= 0;
6593 if (intel_crtc
->cursor_visible
!= visible
) {
6594 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6596 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6597 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6598 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6600 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6601 cntl
|= CURSOR_MODE_DISABLE
;
6603 I915_WRITE(CURCNTR(pipe
), cntl
);
6605 intel_crtc
->cursor_visible
= visible
;
6607 /* and commit changes on next vblank */
6608 I915_WRITE(CURBASE(pipe
), base
);
6611 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6613 struct drm_device
*dev
= crtc
->dev
;
6614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6615 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6616 int pipe
= intel_crtc
->pipe
;
6617 bool visible
= base
!= 0;
6619 if (intel_crtc
->cursor_visible
!= visible
) {
6620 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6622 cntl
&= ~CURSOR_MODE
;
6623 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6625 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6626 cntl
|= CURSOR_MODE_DISABLE
;
6628 if (IS_HASWELL(dev
))
6629 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6630 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6632 intel_crtc
->cursor_visible
= visible
;
6634 /* and commit changes on next vblank */
6635 I915_WRITE(CURBASE_IVB(pipe
), base
);
6638 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6639 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6642 struct drm_device
*dev
= crtc
->dev
;
6643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6644 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6645 int pipe
= intel_crtc
->pipe
;
6646 int x
= intel_crtc
->cursor_x
;
6647 int y
= intel_crtc
->cursor_y
;
6653 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6654 base
= intel_crtc
->cursor_addr
;
6655 if (x
> (int) crtc
->fb
->width
)
6658 if (y
> (int) crtc
->fb
->height
)
6664 if (x
+ intel_crtc
->cursor_width
< 0)
6667 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6670 pos
|= x
<< CURSOR_X_SHIFT
;
6673 if (y
+ intel_crtc
->cursor_height
< 0)
6676 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6679 pos
|= y
<< CURSOR_Y_SHIFT
;
6681 visible
= base
!= 0;
6682 if (!visible
&& !intel_crtc
->cursor_visible
)
6685 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6686 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6687 ivb_update_cursor(crtc
, base
);
6689 I915_WRITE(CURPOS(pipe
), pos
);
6690 if (IS_845G(dev
) || IS_I865G(dev
))
6691 i845_update_cursor(crtc
, base
);
6693 i9xx_update_cursor(crtc
, base
);
6697 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6698 struct drm_file
*file
,
6700 uint32_t width
, uint32_t height
)
6702 struct drm_device
*dev
= crtc
->dev
;
6703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6704 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6705 struct drm_i915_gem_object
*obj
;
6709 /* if we want to turn off the cursor ignore width and height */
6711 DRM_DEBUG_KMS("cursor off\n");
6714 mutex_lock(&dev
->struct_mutex
);
6718 /* Currently we only support 64x64 cursors */
6719 if (width
!= 64 || height
!= 64) {
6720 DRM_ERROR("we currently only support 64x64 cursors\n");
6724 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6725 if (&obj
->base
== NULL
)
6728 if (obj
->base
.size
< width
* height
* 4) {
6729 DRM_ERROR("buffer is to small\n");
6734 /* we only need to pin inside GTT if cursor is non-phy */
6735 mutex_lock(&dev
->struct_mutex
);
6736 if (!dev_priv
->info
->cursor_needs_physical
) {
6739 if (obj
->tiling_mode
) {
6740 DRM_ERROR("cursor cannot be tiled\n");
6745 /* Note that the w/a also requires 2 PTE of padding following
6746 * the bo. We currently fill all unused PTE with the shadow
6747 * page and so we should always have valid PTE following the
6748 * cursor preventing the VT-d warning.
6751 if (need_vtd_wa(dev
))
6752 alignment
= 64*1024;
6754 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6756 DRM_ERROR("failed to move cursor bo into the GTT\n");
6760 ret
= i915_gem_object_put_fence(obj
);
6762 DRM_ERROR("failed to release fence for cursor");
6766 addr
= i915_gem_obj_ggtt_offset(obj
);
6768 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6769 ret
= i915_gem_attach_phys_object(dev
, obj
,
6770 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6773 DRM_ERROR("failed to attach phys object\n");
6776 addr
= obj
->phys_obj
->handle
->busaddr
;
6780 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6783 if (intel_crtc
->cursor_bo
) {
6784 if (dev_priv
->info
->cursor_needs_physical
) {
6785 if (intel_crtc
->cursor_bo
!= obj
)
6786 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6788 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6789 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6792 mutex_unlock(&dev
->struct_mutex
);
6794 intel_crtc
->cursor_addr
= addr
;
6795 intel_crtc
->cursor_bo
= obj
;
6796 intel_crtc
->cursor_width
= width
;
6797 intel_crtc
->cursor_height
= height
;
6799 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6803 i915_gem_object_unpin(obj
);
6805 mutex_unlock(&dev
->struct_mutex
);
6807 drm_gem_object_unreference_unlocked(&obj
->base
);
6811 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6813 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6815 intel_crtc
->cursor_x
= x
;
6816 intel_crtc
->cursor_y
= y
;
6818 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6823 /** Sets the color ramps on behalf of RandR */
6824 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6825 u16 blue
, int regno
)
6827 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6829 intel_crtc
->lut_r
[regno
] = red
>> 8;
6830 intel_crtc
->lut_g
[regno
] = green
>> 8;
6831 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6834 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6835 u16
*blue
, int regno
)
6837 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6839 *red
= intel_crtc
->lut_r
[regno
] << 8;
6840 *green
= intel_crtc
->lut_g
[regno
] << 8;
6841 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6844 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6845 u16
*blue
, uint32_t start
, uint32_t size
)
6847 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6850 for (i
= start
; i
< end
; i
++) {
6851 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6852 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6853 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6856 intel_crtc_load_lut(crtc
);
6859 /* VESA 640x480x72Hz mode to set on the pipe */
6860 static struct drm_display_mode load_detect_mode
= {
6861 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6862 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6865 static struct drm_framebuffer
*
6866 intel_framebuffer_create(struct drm_device
*dev
,
6867 struct drm_mode_fb_cmd2
*mode_cmd
,
6868 struct drm_i915_gem_object
*obj
)
6870 struct intel_framebuffer
*intel_fb
;
6873 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6875 drm_gem_object_unreference_unlocked(&obj
->base
);
6876 return ERR_PTR(-ENOMEM
);
6879 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6881 drm_gem_object_unreference_unlocked(&obj
->base
);
6883 return ERR_PTR(ret
);
6886 return &intel_fb
->base
;
6890 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6892 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6893 return ALIGN(pitch
, 64);
6897 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6899 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6900 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6903 static struct drm_framebuffer
*
6904 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6905 struct drm_display_mode
*mode
,
6908 struct drm_i915_gem_object
*obj
;
6909 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6911 obj
= i915_gem_alloc_object(dev
,
6912 intel_framebuffer_size_for_mode(mode
, bpp
));
6914 return ERR_PTR(-ENOMEM
);
6916 mode_cmd
.width
= mode
->hdisplay
;
6917 mode_cmd
.height
= mode
->vdisplay
;
6918 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6920 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6922 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6925 static struct drm_framebuffer
*
6926 mode_fits_in_fbdev(struct drm_device
*dev
,
6927 struct drm_display_mode
*mode
)
6929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6930 struct drm_i915_gem_object
*obj
;
6931 struct drm_framebuffer
*fb
;
6933 if (dev_priv
->fbdev
== NULL
)
6936 obj
= dev_priv
->fbdev
->ifb
.obj
;
6940 fb
= &dev_priv
->fbdev
->ifb
.base
;
6941 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6942 fb
->bits_per_pixel
))
6945 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6951 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6952 struct drm_display_mode
*mode
,
6953 struct intel_load_detect_pipe
*old
)
6955 struct intel_crtc
*intel_crtc
;
6956 struct intel_encoder
*intel_encoder
=
6957 intel_attached_encoder(connector
);
6958 struct drm_crtc
*possible_crtc
;
6959 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6960 struct drm_crtc
*crtc
= NULL
;
6961 struct drm_device
*dev
= encoder
->dev
;
6962 struct drm_framebuffer
*fb
;
6965 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6966 connector
->base
.id
, drm_get_connector_name(connector
),
6967 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6970 * Algorithm gets a little messy:
6972 * - if the connector already has an assigned crtc, use it (but make
6973 * sure it's on first)
6975 * - try to find the first unused crtc that can drive this connector,
6976 * and use that if we find one
6979 /* See if we already have a CRTC for this connector */
6980 if (encoder
->crtc
) {
6981 crtc
= encoder
->crtc
;
6983 mutex_lock(&crtc
->mutex
);
6985 old
->dpms_mode
= connector
->dpms
;
6986 old
->load_detect_temp
= false;
6988 /* Make sure the crtc and connector are running */
6989 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6990 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6995 /* Find an unused one (if possible) */
6996 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6998 if (!(encoder
->possible_crtcs
& (1 << i
)))
7000 if (!possible_crtc
->enabled
) {
7001 crtc
= possible_crtc
;
7007 * If we didn't find an unused CRTC, don't use any.
7010 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7014 mutex_lock(&crtc
->mutex
);
7015 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7016 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7018 intel_crtc
= to_intel_crtc(crtc
);
7019 old
->dpms_mode
= connector
->dpms
;
7020 old
->load_detect_temp
= true;
7021 old
->release_fb
= NULL
;
7024 mode
= &load_detect_mode
;
7026 /* We need a framebuffer large enough to accommodate all accesses
7027 * that the plane may generate whilst we perform load detection.
7028 * We can not rely on the fbcon either being present (we get called
7029 * during its initialisation to detect all boot displays, or it may
7030 * not even exist) or that it is large enough to satisfy the
7033 fb
= mode_fits_in_fbdev(dev
, mode
);
7035 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7036 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7037 old
->release_fb
= fb
;
7039 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7041 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7042 mutex_unlock(&crtc
->mutex
);
7046 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7047 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7048 if (old
->release_fb
)
7049 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7050 mutex_unlock(&crtc
->mutex
);
7054 /* let the connector get through one full cycle before testing */
7055 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7059 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7060 struct intel_load_detect_pipe
*old
)
7062 struct intel_encoder
*intel_encoder
=
7063 intel_attached_encoder(connector
);
7064 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7065 struct drm_crtc
*crtc
= encoder
->crtc
;
7067 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7068 connector
->base
.id
, drm_get_connector_name(connector
),
7069 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7071 if (old
->load_detect_temp
) {
7072 to_intel_connector(connector
)->new_encoder
= NULL
;
7073 intel_encoder
->new_crtc
= NULL
;
7074 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7076 if (old
->release_fb
) {
7077 drm_framebuffer_unregister_private(old
->release_fb
);
7078 drm_framebuffer_unreference(old
->release_fb
);
7081 mutex_unlock(&crtc
->mutex
);
7085 /* Switch crtc and encoder back off if necessary */
7086 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7087 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7089 mutex_unlock(&crtc
->mutex
);
7092 /* Returns the clock of the currently programmed mode of the given pipe. */
7093 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7094 struct intel_crtc_config
*pipe_config
)
7096 struct drm_device
*dev
= crtc
->base
.dev
;
7097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7098 int pipe
= pipe_config
->cpu_transcoder
;
7099 u32 dpll
= I915_READ(DPLL(pipe
));
7101 intel_clock_t clock
;
7103 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7104 fp
= I915_READ(FP0(pipe
));
7106 fp
= I915_READ(FP1(pipe
));
7108 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7109 if (IS_PINEVIEW(dev
)) {
7110 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7111 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7113 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7114 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7117 if (!IS_GEN2(dev
)) {
7118 if (IS_PINEVIEW(dev
))
7119 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7120 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7122 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7123 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7125 switch (dpll
& DPLL_MODE_MASK
) {
7126 case DPLLB_MODE_DAC_SERIAL
:
7127 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7130 case DPLLB_MODE_LVDS
:
7131 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7135 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7136 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7137 pipe_config
->adjusted_mode
.clock
= 0;
7141 if (IS_PINEVIEW(dev
))
7142 pineview_clock(96000, &clock
);
7144 i9xx_clock(96000, &clock
);
7146 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7149 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7150 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7153 if ((dpll
& PLL_REF_INPUT_MASK
) ==
7154 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
7155 /* XXX: might not be 66MHz */
7156 i9xx_clock(66000, &clock
);
7158 i9xx_clock(48000, &clock
);
7160 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7163 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7164 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7166 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7171 i9xx_clock(48000, &clock
);
7175 pipe_config
->adjusted_mode
.clock
= clock
.dot
*
7176 pipe_config
->pixel_multiplier
;
7179 static void ironlake_crtc_clock_get(struct intel_crtc
*crtc
,
7180 struct intel_crtc_config
*pipe_config
)
7182 struct drm_device
*dev
= crtc
->base
.dev
;
7183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7184 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7185 int link_freq
, repeat
;
7189 repeat
= pipe_config
->pixel_multiplier
;
7192 * The calculation for the data clock is:
7193 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7194 * But we want to avoid losing precison if possible, so:
7195 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7197 * and the link clock is simpler:
7198 * link_clock = (m * link_clock * repeat) / n
7202 * We need to get the FDI or DP link clock here to derive
7205 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7206 * For DP, it's either 1.62GHz or 2.7GHz.
7207 * We do our calculations in 10*MHz since we don't need much precison.
7209 if (pipe_config
->has_pch_encoder
)
7210 link_freq
= intel_fdi_link_freq(dev
) * 10000;
7212 link_freq
= pipe_config
->port_clock
;
7214 link_m
= I915_READ(PIPE_LINK_M1(cpu_transcoder
));
7215 link_n
= I915_READ(PIPE_LINK_N1(cpu_transcoder
));
7217 if (!link_m
|| !link_n
)
7220 clock
= ((u64
)link_m
* (u64
)link_freq
* (u64
)repeat
);
7221 do_div(clock
, link_n
);
7223 pipe_config
->adjusted_mode
.clock
= clock
;
7226 /** Returns the currently programmed mode of the given pipe. */
7227 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7228 struct drm_crtc
*crtc
)
7230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7232 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7233 struct drm_display_mode
*mode
;
7234 struct intel_crtc_config pipe_config
;
7235 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7236 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7237 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7238 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7240 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7245 * Construct a pipe_config sufficient for getting the clock info
7246 * back out of crtc_clock_get.
7248 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7249 * to use a real value here instead.
7251 pipe_config
.cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
7252 pipe_config
.pixel_multiplier
= 1;
7253 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7255 mode
->clock
= pipe_config
.adjusted_mode
.clock
;
7256 mode
->hdisplay
= (htot
& 0xffff) + 1;
7257 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7258 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7259 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7260 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7261 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7262 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7263 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7265 drm_mode_set_name(mode
);
7270 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7272 struct drm_device
*dev
= crtc
->dev
;
7273 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7274 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7275 int pipe
= intel_crtc
->pipe
;
7276 int dpll_reg
= DPLL(pipe
);
7279 if (HAS_PCH_SPLIT(dev
))
7282 if (!dev_priv
->lvds_downclock_avail
)
7285 dpll
= I915_READ(dpll_reg
);
7286 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7287 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7289 assert_panel_unlocked(dev_priv
, pipe
);
7291 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7292 I915_WRITE(dpll_reg
, dpll
);
7293 intel_wait_for_vblank(dev
, pipe
);
7295 dpll
= I915_READ(dpll_reg
);
7296 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7297 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7301 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7303 struct drm_device
*dev
= crtc
->dev
;
7304 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7307 if (HAS_PCH_SPLIT(dev
))
7310 if (!dev_priv
->lvds_downclock_avail
)
7314 * Since this is called by a timer, we should never get here in
7317 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7318 int pipe
= intel_crtc
->pipe
;
7319 int dpll_reg
= DPLL(pipe
);
7322 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7324 assert_panel_unlocked(dev_priv
, pipe
);
7326 dpll
= I915_READ(dpll_reg
);
7327 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7328 I915_WRITE(dpll_reg
, dpll
);
7329 intel_wait_for_vblank(dev
, pipe
);
7330 dpll
= I915_READ(dpll_reg
);
7331 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7332 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7337 void intel_mark_busy(struct drm_device
*dev
)
7339 i915_update_gfx_val(dev
->dev_private
);
7342 void intel_mark_idle(struct drm_device
*dev
)
7344 struct drm_crtc
*crtc
;
7346 if (!i915_powersave
)
7349 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7353 intel_decrease_pllclock(crtc
);
7357 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7358 struct intel_ring_buffer
*ring
)
7360 struct drm_device
*dev
= obj
->base
.dev
;
7361 struct drm_crtc
*crtc
;
7363 if (!i915_powersave
)
7366 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7370 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7373 intel_increase_pllclock(crtc
);
7374 if (ring
&& intel_fbc_enabled(dev
))
7375 ring
->fbc_dirty
= true;
7379 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7382 struct drm_device
*dev
= crtc
->dev
;
7383 struct intel_unpin_work
*work
;
7384 unsigned long flags
;
7386 spin_lock_irqsave(&dev
->event_lock
, flags
);
7387 work
= intel_crtc
->unpin_work
;
7388 intel_crtc
->unpin_work
= NULL
;
7389 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7392 cancel_work_sync(&work
->work
);
7396 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7398 drm_crtc_cleanup(crtc
);
7403 static void intel_unpin_work_fn(struct work_struct
*__work
)
7405 struct intel_unpin_work
*work
=
7406 container_of(__work
, struct intel_unpin_work
, work
);
7407 struct drm_device
*dev
= work
->crtc
->dev
;
7409 mutex_lock(&dev
->struct_mutex
);
7410 intel_unpin_fb_obj(work
->old_fb_obj
);
7411 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7412 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7414 intel_update_fbc(dev
);
7415 mutex_unlock(&dev
->struct_mutex
);
7417 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7418 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7423 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7424 struct drm_crtc
*crtc
)
7426 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7427 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7428 struct intel_unpin_work
*work
;
7429 unsigned long flags
;
7431 /* Ignore early vblank irqs */
7432 if (intel_crtc
== NULL
)
7435 spin_lock_irqsave(&dev
->event_lock
, flags
);
7436 work
= intel_crtc
->unpin_work
;
7438 /* Ensure we don't miss a work->pending update ... */
7441 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7442 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7446 /* and that the unpin work is consistent wrt ->pending. */
7449 intel_crtc
->unpin_work
= NULL
;
7452 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7454 drm_vblank_put(dev
, intel_crtc
->pipe
);
7456 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7458 wake_up_all(&dev_priv
->pending_flip_queue
);
7460 queue_work(dev_priv
->wq
, &work
->work
);
7462 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7465 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7467 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7468 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7470 do_intel_finish_page_flip(dev
, crtc
);
7473 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7475 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7476 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7478 do_intel_finish_page_flip(dev
, crtc
);
7481 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7483 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7484 struct intel_crtc
*intel_crtc
=
7485 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7486 unsigned long flags
;
7488 /* NB: An MMIO update of the plane base pointer will also
7489 * generate a page-flip completion irq, i.e. every modeset
7490 * is also accompanied by a spurious intel_prepare_page_flip().
7492 spin_lock_irqsave(&dev
->event_lock
, flags
);
7493 if (intel_crtc
->unpin_work
)
7494 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7495 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7498 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7500 /* Ensure that the work item is consistent when activating it ... */
7502 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7503 /* and that it is marked active as soon as the irq could fire. */
7507 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7508 struct drm_crtc
*crtc
,
7509 struct drm_framebuffer
*fb
,
7510 struct drm_i915_gem_object
*obj
)
7512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7515 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7518 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7522 ret
= intel_ring_begin(ring
, 6);
7526 /* Can't queue multiple flips, so wait for the previous
7527 * one to finish before executing the next.
7529 if (intel_crtc
->plane
)
7530 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7532 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7533 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7534 intel_ring_emit(ring
, MI_NOOP
);
7535 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7536 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7537 intel_ring_emit(ring
, fb
->pitches
[0]);
7538 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7539 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7541 intel_mark_page_flip_active(intel_crtc
);
7542 intel_ring_advance(ring
);
7546 intel_unpin_fb_obj(obj
);
7551 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7552 struct drm_crtc
*crtc
,
7553 struct drm_framebuffer
*fb
,
7554 struct drm_i915_gem_object
*obj
)
7556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7557 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7559 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7562 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7566 ret
= intel_ring_begin(ring
, 6);
7570 if (intel_crtc
->plane
)
7571 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7573 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7574 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7575 intel_ring_emit(ring
, MI_NOOP
);
7576 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7577 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7578 intel_ring_emit(ring
, fb
->pitches
[0]);
7579 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7580 intel_ring_emit(ring
, MI_NOOP
);
7582 intel_mark_page_flip_active(intel_crtc
);
7583 intel_ring_advance(ring
);
7587 intel_unpin_fb_obj(obj
);
7592 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7593 struct drm_crtc
*crtc
,
7594 struct drm_framebuffer
*fb
,
7595 struct drm_i915_gem_object
*obj
)
7597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7599 uint32_t pf
, pipesrc
;
7600 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7603 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7607 ret
= intel_ring_begin(ring
, 4);
7611 /* i965+ uses the linear or tiled offsets from the
7612 * Display Registers (which do not change across a page-flip)
7613 * so we need only reprogram the base address.
7615 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7616 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7617 intel_ring_emit(ring
, fb
->pitches
[0]);
7618 intel_ring_emit(ring
,
7619 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
7622 /* XXX Enabling the panel-fitter across page-flip is so far
7623 * untested on non-native modes, so ignore it for now.
7624 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7627 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7628 intel_ring_emit(ring
, pf
| pipesrc
);
7630 intel_mark_page_flip_active(intel_crtc
);
7631 intel_ring_advance(ring
);
7635 intel_unpin_fb_obj(obj
);
7640 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7641 struct drm_crtc
*crtc
,
7642 struct drm_framebuffer
*fb
,
7643 struct drm_i915_gem_object
*obj
)
7645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7647 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7648 uint32_t pf
, pipesrc
;
7651 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7655 ret
= intel_ring_begin(ring
, 4);
7659 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7660 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7661 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7662 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7664 /* Contrary to the suggestions in the documentation,
7665 * "Enable Panel Fitter" does not seem to be required when page
7666 * flipping with a non-native mode, and worse causes a normal
7668 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7671 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7672 intel_ring_emit(ring
, pf
| pipesrc
);
7674 intel_mark_page_flip_active(intel_crtc
);
7675 intel_ring_advance(ring
);
7679 intel_unpin_fb_obj(obj
);
7685 * On gen7 we currently use the blit ring because (in early silicon at least)
7686 * the render ring doesn't give us interrpts for page flip completion, which
7687 * means clients will hang after the first flip is queued. Fortunately the
7688 * blit ring generates interrupts properly, so use it instead.
7690 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7691 struct drm_crtc
*crtc
,
7692 struct drm_framebuffer
*fb
,
7693 struct drm_i915_gem_object
*obj
)
7695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7696 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7697 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7698 uint32_t plane_bit
= 0;
7701 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7705 switch(intel_crtc
->plane
) {
7707 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7710 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7713 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7716 WARN_ONCE(1, "unknown plane in flip command\n");
7721 ret
= intel_ring_begin(ring
, 4);
7725 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7726 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7727 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7728 intel_ring_emit(ring
, (MI_NOOP
));
7730 intel_mark_page_flip_active(intel_crtc
);
7731 intel_ring_advance(ring
);
7735 intel_unpin_fb_obj(obj
);
7740 static int intel_default_queue_flip(struct drm_device
*dev
,
7741 struct drm_crtc
*crtc
,
7742 struct drm_framebuffer
*fb
,
7743 struct drm_i915_gem_object
*obj
)
7748 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7749 struct drm_framebuffer
*fb
,
7750 struct drm_pending_vblank_event
*event
)
7752 struct drm_device
*dev
= crtc
->dev
;
7753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7754 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7755 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7756 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7757 struct intel_unpin_work
*work
;
7758 unsigned long flags
;
7761 /* Can't change pixel format via MI display flips. */
7762 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7766 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7767 * Note that pitch changes could also affect these register.
7769 if (INTEL_INFO(dev
)->gen
> 3 &&
7770 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7771 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7774 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7778 work
->event
= event
;
7780 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7781 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7783 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7787 /* We borrow the event spin lock for protecting unpin_work */
7788 spin_lock_irqsave(&dev
->event_lock
, flags
);
7789 if (intel_crtc
->unpin_work
) {
7790 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7792 drm_vblank_put(dev
, intel_crtc
->pipe
);
7794 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7797 intel_crtc
->unpin_work
= work
;
7798 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7800 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7801 flush_workqueue(dev_priv
->wq
);
7803 ret
= i915_mutex_lock_interruptible(dev
);
7807 /* Reference the objects for the scheduled work. */
7808 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7809 drm_gem_object_reference(&obj
->base
);
7813 work
->pending_flip_obj
= obj
;
7815 work
->enable_stall_check
= true;
7817 atomic_inc(&intel_crtc
->unpin_work_count
);
7818 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7820 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7822 goto cleanup_pending
;
7824 intel_disable_fbc(dev
);
7825 intel_mark_fb_busy(obj
, NULL
);
7826 mutex_unlock(&dev
->struct_mutex
);
7828 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7833 atomic_dec(&intel_crtc
->unpin_work_count
);
7835 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7836 drm_gem_object_unreference(&obj
->base
);
7837 mutex_unlock(&dev
->struct_mutex
);
7840 spin_lock_irqsave(&dev
->event_lock
, flags
);
7841 intel_crtc
->unpin_work
= NULL
;
7842 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7844 drm_vblank_put(dev
, intel_crtc
->pipe
);
7851 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7852 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7853 .load_lut
= intel_crtc_load_lut
,
7856 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7857 struct drm_crtc
*crtc
)
7859 struct drm_device
*dev
;
7860 struct drm_crtc
*tmp
;
7863 WARN(!crtc
, "checking null crtc?\n");
7867 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7873 if (encoder
->possible_crtcs
& crtc_mask
)
7879 * intel_modeset_update_staged_output_state
7881 * Updates the staged output configuration state, e.g. after we've read out the
7884 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7886 struct intel_encoder
*encoder
;
7887 struct intel_connector
*connector
;
7889 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7891 connector
->new_encoder
=
7892 to_intel_encoder(connector
->base
.encoder
);
7895 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7898 to_intel_crtc(encoder
->base
.crtc
);
7903 * intel_modeset_commit_output_state
7905 * This function copies the stage display pipe configuration to the real one.
7907 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7909 struct intel_encoder
*encoder
;
7910 struct intel_connector
*connector
;
7912 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7914 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7917 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7919 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7924 connected_sink_compute_bpp(struct intel_connector
* connector
,
7925 struct intel_crtc_config
*pipe_config
)
7927 int bpp
= pipe_config
->pipe_bpp
;
7929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7930 connector
->base
.base
.id
,
7931 drm_get_connector_name(&connector
->base
));
7933 /* Don't use an invalid EDID bpc value */
7934 if (connector
->base
.display_info
.bpc
&&
7935 connector
->base
.display_info
.bpc
* 3 < bpp
) {
7936 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7937 bpp
, connector
->base
.display_info
.bpc
*3);
7938 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
7941 /* Clamp bpp to 8 on screens without EDID 1.4 */
7942 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
7943 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7945 pipe_config
->pipe_bpp
= 24;
7950 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
7951 struct drm_framebuffer
*fb
,
7952 struct intel_crtc_config
*pipe_config
)
7954 struct drm_device
*dev
= crtc
->base
.dev
;
7955 struct intel_connector
*connector
;
7958 switch (fb
->pixel_format
) {
7960 bpp
= 8*3; /* since we go through a colormap */
7962 case DRM_FORMAT_XRGB1555
:
7963 case DRM_FORMAT_ARGB1555
:
7964 /* checked in intel_framebuffer_init already */
7965 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7967 case DRM_FORMAT_RGB565
:
7968 bpp
= 6*3; /* min is 18bpp */
7970 case DRM_FORMAT_XBGR8888
:
7971 case DRM_FORMAT_ABGR8888
:
7972 /* checked in intel_framebuffer_init already */
7973 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7975 case DRM_FORMAT_XRGB8888
:
7976 case DRM_FORMAT_ARGB8888
:
7979 case DRM_FORMAT_XRGB2101010
:
7980 case DRM_FORMAT_ARGB2101010
:
7981 case DRM_FORMAT_XBGR2101010
:
7982 case DRM_FORMAT_ABGR2101010
:
7983 /* checked in intel_framebuffer_init already */
7984 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7988 /* TODO: gen4+ supports 16 bpc floating point, too. */
7990 DRM_DEBUG_KMS("unsupported depth\n");
7994 pipe_config
->pipe_bpp
= bpp
;
7996 /* Clamp display bpp to EDID value */
7997 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7999 if (!connector
->new_encoder
||
8000 connector
->new_encoder
->new_crtc
!= crtc
)
8003 connected_sink_compute_bpp(connector
, pipe_config
);
8009 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8010 struct intel_crtc_config
*pipe_config
,
8011 const char *context
)
8013 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8014 context
, pipe_name(crtc
->pipe
));
8016 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8017 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8018 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8019 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8020 pipe_config
->has_pch_encoder
,
8021 pipe_config
->fdi_lanes
,
8022 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8023 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8024 pipe_config
->fdi_m_n
.tu
);
8025 DRM_DEBUG_KMS("requested mode:\n");
8026 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8027 DRM_DEBUG_KMS("adjusted mode:\n");
8028 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8029 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8030 pipe_config
->gmch_pfit
.control
,
8031 pipe_config
->gmch_pfit
.pgm_ratios
,
8032 pipe_config
->gmch_pfit
.lvds_border_bits
);
8033 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8034 pipe_config
->pch_pfit
.pos
,
8035 pipe_config
->pch_pfit
.size
);
8036 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8039 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8041 int num_encoders
= 0;
8042 bool uncloneable_encoders
= false;
8043 struct intel_encoder
*encoder
;
8045 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8047 if (&encoder
->new_crtc
->base
!= crtc
)
8051 if (!encoder
->cloneable
)
8052 uncloneable_encoders
= true;
8055 return !(num_encoders
> 1 && uncloneable_encoders
);
8058 static struct intel_crtc_config
*
8059 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8060 struct drm_framebuffer
*fb
,
8061 struct drm_display_mode
*mode
)
8063 struct drm_device
*dev
= crtc
->dev
;
8064 struct drm_encoder_helper_funcs
*encoder_funcs
;
8065 struct intel_encoder
*encoder
;
8066 struct intel_crtc_config
*pipe_config
;
8067 int plane_bpp
, ret
= -EINVAL
;
8070 if (!check_encoder_cloning(crtc
)) {
8071 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8072 return ERR_PTR(-EINVAL
);
8075 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8077 return ERR_PTR(-ENOMEM
);
8079 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8080 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8081 pipe_config
->cpu_transcoder
=
8082 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8083 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8085 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8086 * plane pixel format and any sink constraints into account. Returns the
8087 * source plane bpp so that dithering can be selected on mismatches
8088 * after encoders and crtc also have had their say. */
8089 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8095 /* Ensure the port clock defaults are reset when retrying. */
8096 pipe_config
->port_clock
= 0;
8097 pipe_config
->pixel_multiplier
= 1;
8099 /* Pass our mode to the connectors and the CRTC to give them a chance to
8100 * adjust it according to limitations or connector properties, and also
8101 * a chance to reject the mode entirely.
8103 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8106 if (&encoder
->new_crtc
->base
!= crtc
)
8109 if (encoder
->compute_config
) {
8110 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8111 DRM_DEBUG_KMS("Encoder config failure\n");
8118 encoder_funcs
= encoder
->base
.helper_private
;
8119 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
8120 &pipe_config
->requested_mode
,
8121 &pipe_config
->adjusted_mode
))) {
8122 DRM_DEBUG_KMS("Encoder fixup failed\n");
8127 /* Set default port clock if not overwritten by the encoder. Needs to be
8128 * done afterwards in case the encoder adjusts the mode. */
8129 if (!pipe_config
->port_clock
)
8130 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.clock
;
8132 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8134 DRM_DEBUG_KMS("CRTC fixup failed\n");
8139 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8144 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8149 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8150 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8151 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8156 return ERR_PTR(ret
);
8159 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8160 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8162 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8163 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8165 struct intel_crtc
*intel_crtc
;
8166 struct drm_device
*dev
= crtc
->dev
;
8167 struct intel_encoder
*encoder
;
8168 struct intel_connector
*connector
;
8169 struct drm_crtc
*tmp_crtc
;
8171 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8173 /* Check which crtcs have changed outputs connected to them, these need
8174 * to be part of the prepare_pipes mask. We don't (yet) support global
8175 * modeset across multiple crtcs, so modeset_pipes will only have one
8176 * bit set at most. */
8177 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8179 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8182 if (connector
->base
.encoder
) {
8183 tmp_crtc
= connector
->base
.encoder
->crtc
;
8185 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8188 if (connector
->new_encoder
)
8190 1 << connector
->new_encoder
->new_crtc
->pipe
;
8193 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8195 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8198 if (encoder
->base
.crtc
) {
8199 tmp_crtc
= encoder
->base
.crtc
;
8201 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8204 if (encoder
->new_crtc
)
8205 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8208 /* Check for any pipes that will be fully disabled ... */
8209 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8213 /* Don't try to disable disabled crtcs. */
8214 if (!intel_crtc
->base
.enabled
)
8217 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8219 if (encoder
->new_crtc
== intel_crtc
)
8224 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8228 /* set_mode is also used to update properties on life display pipes. */
8229 intel_crtc
= to_intel_crtc(crtc
);
8231 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8234 * For simplicity do a full modeset on any pipe where the output routing
8235 * changed. We could be more clever, but that would require us to be
8236 * more careful with calling the relevant encoder->mode_set functions.
8239 *modeset_pipes
= *prepare_pipes
;
8241 /* ... and mask these out. */
8242 *modeset_pipes
&= ~(*disable_pipes
);
8243 *prepare_pipes
&= ~(*disable_pipes
);
8246 * HACK: We don't (yet) fully support global modesets. intel_set_config
8247 * obies this rule, but the modeset restore mode of
8248 * intel_modeset_setup_hw_state does not.
8250 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8251 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8253 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8254 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8257 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8259 struct drm_encoder
*encoder
;
8260 struct drm_device
*dev
= crtc
->dev
;
8262 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8263 if (encoder
->crtc
== crtc
)
8270 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8272 struct intel_encoder
*intel_encoder
;
8273 struct intel_crtc
*intel_crtc
;
8274 struct drm_connector
*connector
;
8276 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8278 if (!intel_encoder
->base
.crtc
)
8281 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8283 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8284 intel_encoder
->connectors_active
= false;
8287 intel_modeset_commit_output_state(dev
);
8289 /* Update computed state. */
8290 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8292 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8295 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8296 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8299 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8301 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8302 struct drm_property
*dpms_property
=
8303 dev
->mode_config
.dpms_property
;
8305 connector
->dpms
= DRM_MODE_DPMS_ON
;
8306 drm_object_property_set_value(&connector
->base
,
8310 intel_encoder
= to_intel_encoder(connector
->encoder
);
8311 intel_encoder
->connectors_active
= true;
8317 static bool intel_fuzzy_clock_check(struct intel_crtc_config
*cur
,
8318 struct intel_crtc_config
*new)
8320 int clock1
, clock2
, diff
;
8322 clock1
= cur
->adjusted_mode
.clock
;
8323 clock2
= new->adjusted_mode
.clock
;
8325 if (clock1
== clock2
)
8328 if (!clock1
|| !clock2
)
8331 diff
= abs(clock1
- clock2
);
8333 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8339 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8340 list_for_each_entry((intel_crtc), \
8341 &(dev)->mode_config.crtc_list, \
8343 if (mask & (1 <<(intel_crtc)->pipe))
8346 intel_pipe_config_compare(struct drm_device
*dev
,
8347 struct intel_crtc_config
*current_config
,
8348 struct intel_crtc_config
*pipe_config
)
8350 #define PIPE_CONF_CHECK_X(name) \
8351 if (current_config->name != pipe_config->name) { \
8352 DRM_ERROR("mismatch in " #name " " \
8353 "(expected 0x%08x, found 0x%08x)\n", \
8354 current_config->name, \
8355 pipe_config->name); \
8359 #define PIPE_CONF_CHECK_I(name) \
8360 if (current_config->name != pipe_config->name) { \
8361 DRM_ERROR("mismatch in " #name " " \
8362 "(expected %i, found %i)\n", \
8363 current_config->name, \
8364 pipe_config->name); \
8368 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8369 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8370 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8371 "(expected %i, found %i)\n", \
8372 current_config->name & (mask), \
8373 pipe_config->name & (mask)); \
8377 #define PIPE_CONF_QUIRK(quirk) \
8378 ((current_config->quirks | pipe_config->quirks) & (quirk))
8380 PIPE_CONF_CHECK_I(cpu_transcoder
);
8382 PIPE_CONF_CHECK_I(has_pch_encoder
);
8383 PIPE_CONF_CHECK_I(fdi_lanes
);
8384 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8385 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8386 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8387 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8388 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8390 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8391 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8392 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8393 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8394 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8395 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8397 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8398 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8399 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8400 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8401 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8402 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8404 PIPE_CONF_CHECK_I(pixel_multiplier
);
8406 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8407 DRM_MODE_FLAG_INTERLACE
);
8409 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8410 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8411 DRM_MODE_FLAG_PHSYNC
);
8412 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8413 DRM_MODE_FLAG_NHSYNC
);
8414 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8415 DRM_MODE_FLAG_PVSYNC
);
8416 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8417 DRM_MODE_FLAG_NVSYNC
);
8420 PIPE_CONF_CHECK_I(requested_mode
.hdisplay
);
8421 PIPE_CONF_CHECK_I(requested_mode
.vdisplay
);
8423 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8424 /* pfit ratios are autocomputed by the hw on gen4+ */
8425 if (INTEL_INFO(dev
)->gen
< 4)
8426 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8427 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8428 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8429 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8431 PIPE_CONF_CHECK_I(ips_enabled
);
8433 PIPE_CONF_CHECK_I(shared_dpll
);
8434 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8435 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8436 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8437 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8439 #undef PIPE_CONF_CHECK_X
8440 #undef PIPE_CONF_CHECK_I
8441 #undef PIPE_CONF_CHECK_FLAGS
8442 #undef PIPE_CONF_QUIRK
8444 if (!IS_HASWELL(dev
)) {
8445 if (!intel_fuzzy_clock_check(current_config
, pipe_config
)) {
8446 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8447 current_config
->adjusted_mode
.clock
,
8448 pipe_config
->adjusted_mode
.clock
);
8457 check_connector_state(struct drm_device
*dev
)
8459 struct intel_connector
*connector
;
8461 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8463 /* This also checks the encoder/connector hw state with the
8464 * ->get_hw_state callbacks. */
8465 intel_connector_check_state(connector
);
8467 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8468 "connector's staged encoder doesn't match current encoder\n");
8473 check_encoder_state(struct drm_device
*dev
)
8475 struct intel_encoder
*encoder
;
8476 struct intel_connector
*connector
;
8478 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8480 bool enabled
= false;
8481 bool active
= false;
8482 enum pipe pipe
, tracked_pipe
;
8484 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8485 encoder
->base
.base
.id
,
8486 drm_get_encoder_name(&encoder
->base
));
8488 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8489 "encoder's stage crtc doesn't match current crtc\n");
8490 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8491 "encoder's active_connectors set, but no crtc\n");
8493 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8495 if (connector
->base
.encoder
!= &encoder
->base
)
8498 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8501 WARN(!!encoder
->base
.crtc
!= enabled
,
8502 "encoder's enabled state mismatch "
8503 "(expected %i, found %i)\n",
8504 !!encoder
->base
.crtc
, enabled
);
8505 WARN(active
&& !encoder
->base
.crtc
,
8506 "active encoder with no crtc\n");
8508 WARN(encoder
->connectors_active
!= active
,
8509 "encoder's computed active state doesn't match tracked active state "
8510 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8512 active
= encoder
->get_hw_state(encoder
, &pipe
);
8513 WARN(active
!= encoder
->connectors_active
,
8514 "encoder's hw state doesn't match sw tracking "
8515 "(expected %i, found %i)\n",
8516 encoder
->connectors_active
, active
);
8518 if (!encoder
->base
.crtc
)
8521 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8522 WARN(active
&& pipe
!= tracked_pipe
,
8523 "active encoder's pipe doesn't match"
8524 "(expected %i, found %i)\n",
8525 tracked_pipe
, pipe
);
8531 check_crtc_state(struct drm_device
*dev
)
8533 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8534 struct intel_crtc
*crtc
;
8535 struct intel_encoder
*encoder
;
8536 struct intel_crtc_config pipe_config
;
8538 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8540 bool enabled
= false;
8541 bool active
= false;
8543 memset(&pipe_config
, 0, sizeof(pipe_config
));
8545 DRM_DEBUG_KMS("[CRTC:%d]\n",
8546 crtc
->base
.base
.id
);
8548 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8549 "active crtc, but not enabled in sw tracking\n");
8551 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8553 if (encoder
->base
.crtc
!= &crtc
->base
)
8556 if (encoder
->connectors_active
)
8560 WARN(active
!= crtc
->active
,
8561 "crtc's computed active state doesn't match tracked active state "
8562 "(expected %i, found %i)\n", active
, crtc
->active
);
8563 WARN(enabled
!= crtc
->base
.enabled
,
8564 "crtc's computed enabled state doesn't match tracked enabled state "
8565 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8567 active
= dev_priv
->display
.get_pipe_config(crtc
,
8570 /* hw state is inconsistent with the pipe A quirk */
8571 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8572 active
= crtc
->active
;
8574 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8576 if (encoder
->base
.crtc
!= &crtc
->base
)
8578 if (encoder
->get_config
)
8579 encoder
->get_config(encoder
, &pipe_config
);
8582 if (dev_priv
->display
.get_clock
)
8583 dev_priv
->display
.get_clock(crtc
, &pipe_config
);
8585 WARN(crtc
->active
!= active
,
8586 "crtc active state doesn't match with hw state "
8587 "(expected %i, found %i)\n", crtc
->active
, active
);
8590 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8591 WARN(1, "pipe state doesn't match!\n");
8592 intel_dump_pipe_config(crtc
, &pipe_config
,
8594 intel_dump_pipe_config(crtc
, &crtc
->config
,
8601 check_shared_dpll_state(struct drm_device
*dev
)
8603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8604 struct intel_crtc
*crtc
;
8605 struct intel_dpll_hw_state dpll_hw_state
;
8608 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8609 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8610 int enabled_crtcs
= 0, active_crtcs
= 0;
8613 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8615 DRM_DEBUG_KMS("%s\n", pll
->name
);
8617 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
8619 WARN(pll
->active
> pll
->refcount
,
8620 "more active pll users than references: %i vs %i\n",
8621 pll
->active
, pll
->refcount
);
8622 WARN(pll
->active
&& !pll
->on
,
8623 "pll in active use but not on in sw tracking\n");
8624 WARN(pll
->on
&& !pll
->active
,
8625 "pll in on but not on in use in sw tracking\n");
8626 WARN(pll
->on
!= active
,
8627 "pll on state mismatch (expected %i, found %i)\n",
8630 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8632 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8634 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8637 WARN(pll
->active
!= active_crtcs
,
8638 "pll active crtcs mismatch (expected %i, found %i)\n",
8639 pll
->active
, active_crtcs
);
8640 WARN(pll
->refcount
!= enabled_crtcs
,
8641 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8642 pll
->refcount
, enabled_crtcs
);
8644 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
8645 sizeof(dpll_hw_state
)),
8646 "pll hw state mismatch\n");
8651 intel_modeset_check_state(struct drm_device
*dev
)
8653 check_connector_state(dev
);
8654 check_encoder_state(dev
);
8655 check_crtc_state(dev
);
8656 check_shared_dpll_state(dev
);
8659 static int __intel_set_mode(struct drm_crtc
*crtc
,
8660 struct drm_display_mode
*mode
,
8661 int x
, int y
, struct drm_framebuffer
*fb
)
8663 struct drm_device
*dev
= crtc
->dev
;
8664 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8665 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
8666 struct intel_crtc_config
*pipe_config
= NULL
;
8667 struct intel_crtc
*intel_crtc
;
8668 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
8671 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
8674 saved_hwmode
= saved_mode
+ 1;
8676 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
8677 &prepare_pipes
, &disable_pipes
);
8679 *saved_hwmode
= crtc
->hwmode
;
8680 *saved_mode
= crtc
->mode
;
8682 /* Hack: Because we don't (yet) support global modeset on multiple
8683 * crtcs, we don't keep track of the new mode for more than one crtc.
8684 * Hence simply check whether any bit is set in modeset_pipes in all the
8685 * pieces of code that are not yet converted to deal with mutliple crtcs
8686 * changing their mode at the same time. */
8687 if (modeset_pipes
) {
8688 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
8689 if (IS_ERR(pipe_config
)) {
8690 ret
= PTR_ERR(pipe_config
);
8695 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
8699 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
8700 intel_crtc_disable(&intel_crtc
->base
);
8702 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
8703 if (intel_crtc
->base
.enabled
)
8704 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
8707 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8708 * to set it here already despite that we pass it down the callchain.
8710 if (modeset_pipes
) {
8712 /* mode_set/enable/disable functions rely on a correct pipe
8714 to_intel_crtc(crtc
)->config
= *pipe_config
;
8717 /* Only after disabling all output pipelines that will be changed can we
8718 * update the the output configuration. */
8719 intel_modeset_update_state(dev
, prepare_pipes
);
8721 if (dev_priv
->display
.modeset_global_resources
)
8722 dev_priv
->display
.modeset_global_resources(dev
);
8724 /* Set up the DPLL and any encoders state that needs to adjust or depend
8727 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8728 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8734 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8735 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8736 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8738 if (modeset_pipes
) {
8739 /* Store real post-adjustment hardware mode. */
8740 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8742 /* Calculate and store various constants which
8743 * are later needed by vblank and swap-completion
8744 * timestamping. They are derived from true hwmode.
8746 drm_calc_timestamping_constants(crtc
);
8749 /* FIXME: add subpixel order */
8751 if (ret
&& crtc
->enabled
) {
8752 crtc
->hwmode
= *saved_hwmode
;
8753 crtc
->mode
= *saved_mode
;
8762 int intel_set_mode(struct drm_crtc
*crtc
,
8763 struct drm_display_mode
*mode
,
8764 int x
, int y
, struct drm_framebuffer
*fb
)
8768 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8771 intel_modeset_check_state(crtc
->dev
);
8776 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8778 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8781 #undef for_each_intel_crtc_masked
8783 static void intel_set_config_free(struct intel_set_config
*config
)
8788 kfree(config
->save_connector_encoders
);
8789 kfree(config
->save_encoder_crtcs
);
8793 static int intel_set_config_save_state(struct drm_device
*dev
,
8794 struct intel_set_config
*config
)
8796 struct drm_encoder
*encoder
;
8797 struct drm_connector
*connector
;
8800 config
->save_encoder_crtcs
=
8801 kcalloc(dev
->mode_config
.num_encoder
,
8802 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8803 if (!config
->save_encoder_crtcs
)
8806 config
->save_connector_encoders
=
8807 kcalloc(dev
->mode_config
.num_connector
,
8808 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8809 if (!config
->save_connector_encoders
)
8812 /* Copy data. Note that driver private data is not affected.
8813 * Should anything bad happen only the expected state is
8814 * restored, not the drivers personal bookkeeping.
8817 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8818 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8822 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8823 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8829 static void intel_set_config_restore_state(struct drm_device
*dev
,
8830 struct intel_set_config
*config
)
8832 struct intel_encoder
*encoder
;
8833 struct intel_connector
*connector
;
8837 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8839 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8843 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8844 connector
->new_encoder
=
8845 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8850 is_crtc_connector_off(struct drm_mode_set
*set
)
8854 if (set
->num_connectors
== 0)
8857 if (WARN_ON(set
->connectors
== NULL
))
8860 for (i
= 0; i
< set
->num_connectors
; i
++)
8861 if (set
->connectors
[i
]->encoder
&&
8862 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
8863 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
8870 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8871 struct intel_set_config
*config
)
8874 /* We should be able to check here if the fb has the same properties
8875 * and then just flip_or_move it */
8876 if (is_crtc_connector_off(set
)) {
8877 config
->mode_changed
= true;
8878 } else if (set
->crtc
->fb
!= set
->fb
) {
8879 /* If we have no fb then treat it as a full mode set */
8880 if (set
->crtc
->fb
== NULL
) {
8881 struct intel_crtc
*intel_crtc
=
8882 to_intel_crtc(set
->crtc
);
8884 if (intel_crtc
->active
&& i915_fastboot
) {
8885 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8886 config
->fb_changed
= true;
8888 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8889 config
->mode_changed
= true;
8891 } else if (set
->fb
== NULL
) {
8892 config
->mode_changed
= true;
8893 } else if (set
->fb
->pixel_format
!=
8894 set
->crtc
->fb
->pixel_format
) {
8895 config
->mode_changed
= true;
8897 config
->fb_changed
= true;
8901 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8902 config
->fb_changed
= true;
8904 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8905 DRM_DEBUG_KMS("modes are different, full mode set\n");
8906 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8907 drm_mode_debug_printmodeline(set
->mode
);
8908 config
->mode_changed
= true;
8913 intel_modeset_stage_output_state(struct drm_device
*dev
,
8914 struct drm_mode_set
*set
,
8915 struct intel_set_config
*config
)
8917 struct drm_crtc
*new_crtc
;
8918 struct intel_connector
*connector
;
8919 struct intel_encoder
*encoder
;
8922 /* The upper layers ensure that we either disable a crtc or have a list
8923 * of connectors. For paranoia, double-check this. */
8924 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8925 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8928 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8930 /* Otherwise traverse passed in connector list and get encoders
8932 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8933 if (set
->connectors
[ro
] == &connector
->base
) {
8934 connector
->new_encoder
= connector
->encoder
;
8939 /* If we disable the crtc, disable all its connectors. Also, if
8940 * the connector is on the changing crtc but not on the new
8941 * connector list, disable it. */
8942 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8943 connector
->base
.encoder
&&
8944 connector
->base
.encoder
->crtc
== set
->crtc
) {
8945 connector
->new_encoder
= NULL
;
8947 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8948 connector
->base
.base
.id
,
8949 drm_get_connector_name(&connector
->base
));
8953 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8954 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8955 config
->mode_changed
= true;
8958 /* connector->new_encoder is now updated for all connectors. */
8960 /* Update crtc of enabled connectors. */
8962 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8964 if (!connector
->new_encoder
)
8967 new_crtc
= connector
->new_encoder
->base
.crtc
;
8969 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8970 if (set
->connectors
[ro
] == &connector
->base
)
8971 new_crtc
= set
->crtc
;
8974 /* Make sure the new CRTC will work with the encoder */
8975 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8979 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8981 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8982 connector
->base
.base
.id
,
8983 drm_get_connector_name(&connector
->base
),
8987 /* Check for any encoders that needs to be disabled. */
8988 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8990 list_for_each_entry(connector
,
8991 &dev
->mode_config
.connector_list
,
8993 if (connector
->new_encoder
== encoder
) {
8994 WARN_ON(!connector
->new_encoder
->new_crtc
);
8999 encoder
->new_crtc
= NULL
;
9001 /* Only now check for crtc changes so we don't miss encoders
9002 * that will be disabled. */
9003 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9004 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9005 config
->mode_changed
= true;
9008 /* Now we've also updated encoder->new_crtc for all encoders. */
9013 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9015 struct drm_device
*dev
;
9016 struct drm_mode_set save_set
;
9017 struct intel_set_config
*config
;
9022 BUG_ON(!set
->crtc
->helper_private
);
9024 /* Enforce sane interface api - has been abused by the fb helper. */
9025 BUG_ON(!set
->mode
&& set
->fb
);
9026 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9029 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9030 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9031 (int)set
->num_connectors
, set
->x
, set
->y
);
9033 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9036 dev
= set
->crtc
->dev
;
9039 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9043 ret
= intel_set_config_save_state(dev
, config
);
9047 save_set
.crtc
= set
->crtc
;
9048 save_set
.mode
= &set
->crtc
->mode
;
9049 save_set
.x
= set
->crtc
->x
;
9050 save_set
.y
= set
->crtc
->y
;
9051 save_set
.fb
= set
->crtc
->fb
;
9053 /* Compute whether we need a full modeset, only an fb base update or no
9054 * change at all. In the future we might also check whether only the
9055 * mode changed, e.g. for LVDS where we only change the panel fitter in
9057 intel_set_config_compute_mode_changes(set
, config
);
9059 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9063 if (config
->mode_changed
) {
9064 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9065 set
->x
, set
->y
, set
->fb
);
9066 } else if (config
->fb_changed
) {
9067 intel_crtc_wait_for_pending_flips(set
->crtc
);
9069 ret
= intel_pipe_set_base(set
->crtc
,
9070 set
->x
, set
->y
, set
->fb
);
9074 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9075 set
->crtc
->base
.id
, ret
);
9077 intel_set_config_restore_state(dev
, config
);
9079 /* Try to restore the config */
9080 if (config
->mode_changed
&&
9081 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9082 save_set
.x
, save_set
.y
, save_set
.fb
))
9083 DRM_ERROR("failed to restore config after modeset failure\n");
9087 intel_set_config_free(config
);
9091 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9092 .cursor_set
= intel_crtc_cursor_set
,
9093 .cursor_move
= intel_crtc_cursor_move
,
9094 .gamma_set
= intel_crtc_gamma_set
,
9095 .set_config
= intel_crtc_set_config
,
9096 .destroy
= intel_crtc_destroy
,
9097 .page_flip
= intel_crtc_page_flip
,
9100 static void intel_cpu_pll_init(struct drm_device
*dev
)
9103 intel_ddi_pll_init(dev
);
9106 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9107 struct intel_shared_dpll
*pll
,
9108 struct intel_dpll_hw_state
*hw_state
)
9112 val
= I915_READ(PCH_DPLL(pll
->id
));
9113 hw_state
->dpll
= val
;
9114 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9115 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9117 return val
& DPLL_VCO_ENABLE
;
9120 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9121 struct intel_shared_dpll
*pll
)
9123 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9124 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9127 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9128 struct intel_shared_dpll
*pll
)
9130 /* PCH refclock must be enabled first */
9131 assert_pch_refclk_enabled(dev_priv
);
9133 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9135 /* Wait for the clocks to stabilize. */
9136 POSTING_READ(PCH_DPLL(pll
->id
));
9139 /* The pixel multiplier can only be updated once the
9140 * DPLL is enabled and the clocks are stable.
9142 * So write it again.
9144 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9145 POSTING_READ(PCH_DPLL(pll
->id
));
9149 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9150 struct intel_shared_dpll
*pll
)
9152 struct drm_device
*dev
= dev_priv
->dev
;
9153 struct intel_crtc
*crtc
;
9155 /* Make sure no transcoder isn't still depending on us. */
9156 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9157 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9158 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9161 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9162 POSTING_READ(PCH_DPLL(pll
->id
));
9166 static char *ibx_pch_dpll_names
[] = {
9171 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9176 dev_priv
->num_shared_dpll
= 2;
9178 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9179 dev_priv
->shared_dplls
[i
].id
= i
;
9180 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9181 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9182 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9183 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9184 dev_priv
->shared_dplls
[i
].get_hw_state
=
9185 ibx_pch_dpll_get_hw_state
;
9189 static void intel_shared_dpll_init(struct drm_device
*dev
)
9191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9193 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9194 ibx_pch_dpll_init(dev
);
9196 dev_priv
->num_shared_dpll
= 0;
9198 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9199 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9200 dev_priv
->num_shared_dpll
);
9203 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9205 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9206 struct intel_crtc
*intel_crtc
;
9209 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
9210 if (intel_crtc
== NULL
)
9213 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9215 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9216 for (i
= 0; i
< 256; i
++) {
9217 intel_crtc
->lut_r
[i
] = i
;
9218 intel_crtc
->lut_g
[i
] = i
;
9219 intel_crtc
->lut_b
[i
] = i
;
9222 /* Swap pipes & planes for FBC on pre-965 */
9223 intel_crtc
->pipe
= pipe
;
9224 intel_crtc
->plane
= pipe
;
9225 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9226 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9227 intel_crtc
->plane
= !pipe
;
9230 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9231 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9232 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9233 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9235 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9238 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9239 struct drm_file
*file
)
9241 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9242 struct drm_mode_object
*drmmode_obj
;
9243 struct intel_crtc
*crtc
;
9245 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9248 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9249 DRM_MODE_OBJECT_CRTC
);
9252 DRM_ERROR("no such CRTC id\n");
9256 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9257 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9262 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9264 struct drm_device
*dev
= encoder
->base
.dev
;
9265 struct intel_encoder
*source_encoder
;
9269 list_for_each_entry(source_encoder
,
9270 &dev
->mode_config
.encoder_list
, base
.head
) {
9272 if (encoder
== source_encoder
)
9273 index_mask
|= (1 << entry
);
9275 /* Intel hw has only one MUX where enocoders could be cloned. */
9276 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9277 index_mask
|= (1 << entry
);
9285 static bool has_edp_a(struct drm_device
*dev
)
9287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9289 if (!IS_MOBILE(dev
))
9292 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9296 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9302 static void intel_setup_outputs(struct drm_device
*dev
)
9304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9305 struct intel_encoder
*encoder
;
9306 bool dpd_is_edp
= false;
9308 intel_lvds_init(dev
);
9311 intel_crt_init(dev
);
9316 /* Haswell uses DDI functions to detect digital outputs */
9317 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9318 /* DDI A only supports eDP */
9320 intel_ddi_init(dev
, PORT_A
);
9322 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9324 found
= I915_READ(SFUSE_STRAP
);
9326 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9327 intel_ddi_init(dev
, PORT_B
);
9328 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9329 intel_ddi_init(dev
, PORT_C
);
9330 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9331 intel_ddi_init(dev
, PORT_D
);
9332 } else if (HAS_PCH_SPLIT(dev
)) {
9334 dpd_is_edp
= intel_dpd_is_edp(dev
);
9337 intel_dp_init(dev
, DP_A
, PORT_A
);
9339 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9340 /* PCH SDVOB multiplex with HDMIB */
9341 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9343 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9344 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9345 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9348 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9349 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9351 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9352 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9354 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9355 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9357 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9358 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9359 } else if (IS_VALLEYVIEW(dev
)) {
9360 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9361 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9362 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
9364 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9365 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9367 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9368 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9370 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9373 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9374 DRM_DEBUG_KMS("probing SDVOB\n");
9375 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9376 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9377 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9378 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9381 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9382 intel_dp_init(dev
, DP_B
, PORT_B
);
9385 /* Before G4X SDVOC doesn't have its own detect register */
9387 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9388 DRM_DEBUG_KMS("probing SDVOC\n");
9389 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9392 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9394 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9395 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9396 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9398 if (SUPPORTS_INTEGRATED_DP(dev
))
9399 intel_dp_init(dev
, DP_C
, PORT_C
);
9402 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9403 (I915_READ(DP_D
) & DP_DETECTED
))
9404 intel_dp_init(dev
, DP_D
, PORT_D
);
9405 } else if (IS_GEN2(dev
))
9406 intel_dvo_init(dev
);
9408 if (SUPPORTS_TV(dev
))
9411 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9412 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9413 encoder
->base
.possible_clones
=
9414 intel_encoder_clones(encoder
);
9417 intel_init_pch_refclk(dev
);
9419 drm_helper_move_panel_connectors_to_head(dev
);
9422 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9424 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9426 drm_framebuffer_cleanup(fb
);
9427 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
9432 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9433 struct drm_file
*file
,
9434 unsigned int *handle
)
9436 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9437 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9439 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9442 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9443 .destroy
= intel_user_framebuffer_destroy
,
9444 .create_handle
= intel_user_framebuffer_create_handle
,
9447 int intel_framebuffer_init(struct drm_device
*dev
,
9448 struct intel_framebuffer
*intel_fb
,
9449 struct drm_mode_fb_cmd2
*mode_cmd
,
9450 struct drm_i915_gem_object
*obj
)
9455 if (obj
->tiling_mode
== I915_TILING_Y
) {
9456 DRM_DEBUG("hardware does not support tiling Y\n");
9460 if (mode_cmd
->pitches
[0] & 63) {
9461 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9462 mode_cmd
->pitches
[0]);
9466 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9467 pitch_limit
= 32*1024;
9468 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9469 if (obj
->tiling_mode
)
9470 pitch_limit
= 16*1024;
9472 pitch_limit
= 32*1024;
9473 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9474 if (obj
->tiling_mode
)
9475 pitch_limit
= 8*1024;
9477 pitch_limit
= 16*1024;
9479 /* XXX DSPC is limited to 4k tiled */
9480 pitch_limit
= 8*1024;
9482 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9483 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9484 obj
->tiling_mode
? "tiled" : "linear",
9485 mode_cmd
->pitches
[0], pitch_limit
);
9489 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9490 mode_cmd
->pitches
[0] != obj
->stride
) {
9491 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9492 mode_cmd
->pitches
[0], obj
->stride
);
9496 /* Reject formats not supported by any plane early. */
9497 switch (mode_cmd
->pixel_format
) {
9499 case DRM_FORMAT_RGB565
:
9500 case DRM_FORMAT_XRGB8888
:
9501 case DRM_FORMAT_ARGB8888
:
9503 case DRM_FORMAT_XRGB1555
:
9504 case DRM_FORMAT_ARGB1555
:
9505 if (INTEL_INFO(dev
)->gen
> 3) {
9506 DRM_DEBUG("unsupported pixel format: %s\n",
9507 drm_get_format_name(mode_cmd
->pixel_format
));
9511 case DRM_FORMAT_XBGR8888
:
9512 case DRM_FORMAT_ABGR8888
:
9513 case DRM_FORMAT_XRGB2101010
:
9514 case DRM_FORMAT_ARGB2101010
:
9515 case DRM_FORMAT_XBGR2101010
:
9516 case DRM_FORMAT_ABGR2101010
:
9517 if (INTEL_INFO(dev
)->gen
< 4) {
9518 DRM_DEBUG("unsupported pixel format: %s\n",
9519 drm_get_format_name(mode_cmd
->pixel_format
));
9523 case DRM_FORMAT_YUYV
:
9524 case DRM_FORMAT_UYVY
:
9525 case DRM_FORMAT_YVYU
:
9526 case DRM_FORMAT_VYUY
:
9527 if (INTEL_INFO(dev
)->gen
< 5) {
9528 DRM_DEBUG("unsupported pixel format: %s\n",
9529 drm_get_format_name(mode_cmd
->pixel_format
));
9534 DRM_DEBUG("unsupported pixel format: %s\n",
9535 drm_get_format_name(mode_cmd
->pixel_format
));
9539 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9540 if (mode_cmd
->offsets
[0] != 0)
9543 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9544 intel_fb
->obj
= obj
;
9546 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9548 DRM_ERROR("framebuffer init failed %d\n", ret
);
9555 static struct drm_framebuffer
*
9556 intel_user_framebuffer_create(struct drm_device
*dev
,
9557 struct drm_file
*filp
,
9558 struct drm_mode_fb_cmd2
*mode_cmd
)
9560 struct drm_i915_gem_object
*obj
;
9562 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9563 mode_cmd
->handles
[0]));
9564 if (&obj
->base
== NULL
)
9565 return ERR_PTR(-ENOENT
);
9567 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9570 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9571 .fb_create
= intel_user_framebuffer_create
,
9572 .output_poll_changed
= intel_fb_output_poll_changed
,
9575 /* Set up chip specific display functions */
9576 static void intel_init_display(struct drm_device
*dev
)
9578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9580 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9581 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9582 else if (IS_VALLEYVIEW(dev
))
9583 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9584 else if (IS_PINEVIEW(dev
))
9585 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9587 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9590 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9591 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9592 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9593 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9594 dev_priv
->display
.off
= haswell_crtc_off
;
9595 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9596 } else if (HAS_PCH_SPLIT(dev
)) {
9597 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
9598 dev_priv
->display
.get_clock
= ironlake_crtc_clock_get
;
9599 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9600 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
9601 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
9602 dev_priv
->display
.off
= ironlake_crtc_off
;
9603 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9604 } else if (IS_VALLEYVIEW(dev
)) {
9605 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9606 dev_priv
->display
.get_clock
= i9xx_crtc_clock_get
;
9607 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9608 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
9609 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9610 dev_priv
->display
.off
= i9xx_crtc_off
;
9611 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9613 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9614 dev_priv
->display
.get_clock
= i9xx_crtc_clock_get
;
9615 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9616 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
9617 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9618 dev_priv
->display
.off
= i9xx_crtc_off
;
9619 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9622 /* Returns the core display clock speed */
9623 if (IS_VALLEYVIEW(dev
))
9624 dev_priv
->display
.get_display_clock_speed
=
9625 valleyview_get_display_clock_speed
;
9626 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9627 dev_priv
->display
.get_display_clock_speed
=
9628 i945_get_display_clock_speed
;
9629 else if (IS_I915G(dev
))
9630 dev_priv
->display
.get_display_clock_speed
=
9631 i915_get_display_clock_speed
;
9632 else if (IS_I945GM(dev
) || IS_845G(dev
))
9633 dev_priv
->display
.get_display_clock_speed
=
9634 i9xx_misc_get_display_clock_speed
;
9635 else if (IS_PINEVIEW(dev
))
9636 dev_priv
->display
.get_display_clock_speed
=
9637 pnv_get_display_clock_speed
;
9638 else if (IS_I915GM(dev
))
9639 dev_priv
->display
.get_display_clock_speed
=
9640 i915gm_get_display_clock_speed
;
9641 else if (IS_I865G(dev
))
9642 dev_priv
->display
.get_display_clock_speed
=
9643 i865_get_display_clock_speed
;
9644 else if (IS_I85X(dev
))
9645 dev_priv
->display
.get_display_clock_speed
=
9646 i855_get_display_clock_speed
;
9648 dev_priv
->display
.get_display_clock_speed
=
9649 i830_get_display_clock_speed
;
9651 if (HAS_PCH_SPLIT(dev
)) {
9653 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
9654 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9655 } else if (IS_GEN6(dev
)) {
9656 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
9657 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9658 } else if (IS_IVYBRIDGE(dev
)) {
9659 /* FIXME: detect B0+ stepping and use auto training */
9660 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
9661 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9662 dev_priv
->display
.modeset_global_resources
=
9663 ivb_modeset_global_resources
;
9664 } else if (IS_HASWELL(dev
)) {
9665 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
9666 dev_priv
->display
.write_eld
= haswell_write_eld
;
9667 dev_priv
->display
.modeset_global_resources
=
9668 haswell_modeset_global_resources
;
9670 } else if (IS_G4X(dev
)) {
9671 dev_priv
->display
.write_eld
= g4x_write_eld
;
9674 /* Default just returns -ENODEV to indicate unsupported */
9675 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
9677 switch (INTEL_INFO(dev
)->gen
) {
9679 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
9683 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
9688 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
9692 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
9695 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
9701 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9702 * resume, or other times. This quirk makes sure that's the case for
9705 static void quirk_pipea_force(struct drm_device
*dev
)
9707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9709 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
9710 DRM_INFO("applying pipe a force quirk\n");
9714 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9716 static void quirk_ssc_force_disable(struct drm_device
*dev
)
9718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9719 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9720 DRM_INFO("applying lvds SSC disable quirk\n");
9724 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9727 static void quirk_invert_brightness(struct drm_device
*dev
)
9729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9730 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
9731 DRM_INFO("applying inverted panel brightness quirk\n");
9735 * Some machines (Dell XPS13) suffer broken backlight controls if
9736 * BLM_PCH_PWM_ENABLE is set.
9738 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
9740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9741 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
9742 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9745 struct intel_quirk
{
9747 int subsystem_vendor
;
9748 int subsystem_device
;
9749 void (*hook
)(struct drm_device
*dev
);
9752 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9753 struct intel_dmi_quirk
{
9754 void (*hook
)(struct drm_device
*dev
);
9755 const struct dmi_system_id (*dmi_id_list
)[];
9758 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
9760 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
9764 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
9766 .dmi_id_list
= &(const struct dmi_system_id
[]) {
9768 .callback
= intel_dmi_reverse_brightness
,
9769 .ident
= "NCR Corporation",
9770 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
9771 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
9774 { } /* terminating entry */
9776 .hook
= quirk_invert_brightness
,
9780 static struct intel_quirk intel_quirks
[] = {
9781 /* HP Mini needs pipe A force quirk (LP: #322104) */
9782 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9784 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9785 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9787 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9788 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9790 /* 830/845 need to leave pipe A & dpll A up */
9791 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9792 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9794 /* Lenovo U160 cannot use SSC on LVDS */
9795 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
9797 /* Sony Vaio Y cannot use SSC on LVDS */
9798 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
9800 /* Acer Aspire 5734Z must invert backlight brightness */
9801 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
9803 /* Acer/eMachines G725 */
9804 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
9806 /* Acer/eMachines e725 */
9807 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
9809 /* Acer/Packard Bell NCL20 */
9810 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
9812 /* Acer Aspire 4736Z */
9813 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
9815 /* Dell XPS13 HD Sandy Bridge */
9816 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
9817 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9818 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
9821 static void intel_init_quirks(struct drm_device
*dev
)
9823 struct pci_dev
*d
= dev
->pdev
;
9826 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
9827 struct intel_quirk
*q
= &intel_quirks
[i
];
9829 if (d
->device
== q
->device
&&
9830 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9831 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9832 (d
->subsystem_device
== q
->subsystem_device
||
9833 q
->subsystem_device
== PCI_ANY_ID
))
9836 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
9837 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
9838 intel_dmi_quirks
[i
].hook(dev
);
9842 /* Disable the VGA plane that we never use */
9843 static void i915_disable_vga(struct drm_device
*dev
)
9845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9847 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9849 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9850 outb(SR01
, VGA_SR_INDEX
);
9851 sr1
= inb(VGA_SR_DATA
);
9852 outb(sr1
| 1<<5, VGA_SR_DATA
);
9853 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9856 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9857 POSTING_READ(vga_reg
);
9860 void intel_modeset_init_hw(struct drm_device
*dev
)
9862 intel_init_power_well(dev
);
9864 intel_prepare_ddi(dev
);
9866 intel_init_clock_gating(dev
);
9868 mutex_lock(&dev
->struct_mutex
);
9869 intel_enable_gt_powersave(dev
);
9870 mutex_unlock(&dev
->struct_mutex
);
9873 void intel_modeset_suspend_hw(struct drm_device
*dev
)
9875 intel_suspend_hw(dev
);
9878 void intel_modeset_init(struct drm_device
*dev
)
9880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9883 drm_mode_config_init(dev
);
9885 dev
->mode_config
.min_width
= 0;
9886 dev
->mode_config
.min_height
= 0;
9888 dev
->mode_config
.preferred_depth
= 24;
9889 dev
->mode_config
.prefer_shadow
= 1;
9891 dev
->mode_config
.funcs
= &intel_mode_funcs
;
9893 intel_init_quirks(dev
);
9897 if (INTEL_INFO(dev
)->num_pipes
== 0)
9900 intel_init_display(dev
);
9903 dev
->mode_config
.max_width
= 2048;
9904 dev
->mode_config
.max_height
= 2048;
9905 } else if (IS_GEN3(dev
)) {
9906 dev
->mode_config
.max_width
= 4096;
9907 dev
->mode_config
.max_height
= 4096;
9909 dev
->mode_config
.max_width
= 8192;
9910 dev
->mode_config
.max_height
= 8192;
9912 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9914 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9915 INTEL_INFO(dev
)->num_pipes
,
9916 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9919 intel_crtc_init(dev
, i
);
9920 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9921 ret
= intel_plane_init(dev
, i
, j
);
9923 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9924 pipe_name(i
), sprite_name(i
, j
), ret
);
9928 intel_cpu_pll_init(dev
);
9929 intel_shared_dpll_init(dev
);
9931 /* Just disable it once at startup */
9932 i915_disable_vga(dev
);
9933 intel_setup_outputs(dev
);
9935 /* Just in case the BIOS is doing something questionable. */
9936 intel_disable_fbc(dev
);
9940 intel_connector_break_all_links(struct intel_connector
*connector
)
9942 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9943 connector
->base
.encoder
= NULL
;
9944 connector
->encoder
->connectors_active
= false;
9945 connector
->encoder
->base
.crtc
= NULL
;
9948 static void intel_enable_pipe_a(struct drm_device
*dev
)
9950 struct intel_connector
*connector
;
9951 struct drm_connector
*crt
= NULL
;
9952 struct intel_load_detect_pipe load_detect_temp
;
9954 /* We can't just switch on the pipe A, we need to set things up with a
9955 * proper mode and output configuration. As a gross hack, enable pipe A
9956 * by enabling the load detect pipe once. */
9957 list_for_each_entry(connector
,
9958 &dev
->mode_config
.connector_list
,
9960 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9961 crt
= &connector
->base
;
9969 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9970 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9976 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9978 struct drm_device
*dev
= crtc
->base
.dev
;
9979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9982 if (INTEL_INFO(dev
)->num_pipes
== 1)
9985 reg
= DSPCNTR(!crtc
->plane
);
9986 val
= I915_READ(reg
);
9988 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9989 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9995 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9997 struct drm_device
*dev
= crtc
->base
.dev
;
9998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10001 /* Clear any frame start delays used for debugging left by the BIOS */
10002 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10003 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10005 /* We need to sanitize the plane -> pipe mapping first because this will
10006 * disable the crtc (and hence change the state) if it is wrong. Note
10007 * that gen4+ has a fixed plane -> pipe mapping. */
10008 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10009 struct intel_connector
*connector
;
10012 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10013 crtc
->base
.base
.id
);
10015 /* Pipe has the wrong plane attached and the plane is active.
10016 * Temporarily change the plane mapping and disable everything
10018 plane
= crtc
->plane
;
10019 crtc
->plane
= !plane
;
10020 dev_priv
->display
.crtc_disable(&crtc
->base
);
10021 crtc
->plane
= plane
;
10023 /* ... and break all links. */
10024 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10026 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10029 intel_connector_break_all_links(connector
);
10032 WARN_ON(crtc
->active
);
10033 crtc
->base
.enabled
= false;
10036 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10037 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10038 /* BIOS forgot to enable pipe A, this mostly happens after
10039 * resume. Force-enable the pipe to fix this, the update_dpms
10040 * call below we restore the pipe to the right state, but leave
10041 * the required bits on. */
10042 intel_enable_pipe_a(dev
);
10045 /* Adjust the state of the output pipe according to whether we
10046 * have active connectors/encoders. */
10047 intel_crtc_update_dpms(&crtc
->base
);
10049 if (crtc
->active
!= crtc
->base
.enabled
) {
10050 struct intel_encoder
*encoder
;
10052 /* This can happen either due to bugs in the get_hw_state
10053 * functions or because the pipe is force-enabled due to the
10055 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10056 crtc
->base
.base
.id
,
10057 crtc
->base
.enabled
? "enabled" : "disabled",
10058 crtc
->active
? "enabled" : "disabled");
10060 crtc
->base
.enabled
= crtc
->active
;
10062 /* Because we only establish the connector -> encoder ->
10063 * crtc links if something is active, this means the
10064 * crtc is now deactivated. Break the links. connector
10065 * -> encoder links are only establish when things are
10066 * actually up, hence no need to break them. */
10067 WARN_ON(crtc
->active
);
10069 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10070 WARN_ON(encoder
->connectors_active
);
10071 encoder
->base
.crtc
= NULL
;
10076 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10078 struct intel_connector
*connector
;
10079 struct drm_device
*dev
= encoder
->base
.dev
;
10081 /* We need to check both for a crtc link (meaning that the
10082 * encoder is active and trying to read from a pipe) and the
10083 * pipe itself being active. */
10084 bool has_active_crtc
= encoder
->base
.crtc
&&
10085 to_intel_crtc(encoder
->base
.crtc
)->active
;
10087 if (encoder
->connectors_active
&& !has_active_crtc
) {
10088 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10089 encoder
->base
.base
.id
,
10090 drm_get_encoder_name(&encoder
->base
));
10092 /* Connector is active, but has no active pipe. This is
10093 * fallout from our resume register restoring. Disable
10094 * the encoder manually again. */
10095 if (encoder
->base
.crtc
) {
10096 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10097 encoder
->base
.base
.id
,
10098 drm_get_encoder_name(&encoder
->base
));
10099 encoder
->disable(encoder
);
10102 /* Inconsistent output/port/pipe state happens presumably due to
10103 * a bug in one of the get_hw_state functions. Or someplace else
10104 * in our code, like the register restore mess on resume. Clamp
10105 * things to off as a safer default. */
10106 list_for_each_entry(connector
,
10107 &dev
->mode_config
.connector_list
,
10109 if (connector
->encoder
!= encoder
)
10112 intel_connector_break_all_links(connector
);
10115 /* Enabled encoders without active connectors will be fixed in
10116 * the crtc fixup. */
10119 void i915_redisable_vga(struct drm_device
*dev
)
10121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10122 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10124 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
10125 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10126 i915_disable_vga(dev
);
10130 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10134 struct intel_crtc
*crtc
;
10135 struct intel_encoder
*encoder
;
10136 struct intel_connector
*connector
;
10139 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10141 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10143 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10146 crtc
->base
.enabled
= crtc
->active
;
10148 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10149 crtc
->base
.base
.id
,
10150 crtc
->active
? "enabled" : "disabled");
10153 /* FIXME: Smash this into the new shared dpll infrastructure. */
10155 intel_ddi_setup_hw_pll_state(dev
);
10157 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10158 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10160 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10162 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10164 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10167 pll
->refcount
= pll
->active
;
10169 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10170 pll
->name
, pll
->refcount
, pll
->on
);
10173 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10177 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10178 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10179 encoder
->base
.crtc
= &crtc
->base
;
10180 if (encoder
->get_config
)
10181 encoder
->get_config(encoder
, &crtc
->config
);
10183 encoder
->base
.crtc
= NULL
;
10186 encoder
->connectors_active
= false;
10187 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10188 encoder
->base
.base
.id
,
10189 drm_get_encoder_name(&encoder
->base
),
10190 encoder
->base
.crtc
? "enabled" : "disabled",
10194 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10198 if (dev_priv
->display
.get_clock
)
10199 dev_priv
->display
.get_clock(crtc
,
10203 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10205 if (connector
->get_hw_state(connector
)) {
10206 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10207 connector
->encoder
->connectors_active
= true;
10208 connector
->base
.encoder
= &connector
->encoder
->base
;
10210 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10211 connector
->base
.encoder
= NULL
;
10213 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10214 connector
->base
.base
.id
,
10215 drm_get_connector_name(&connector
->base
),
10216 connector
->base
.encoder
? "enabled" : "disabled");
10220 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10221 * and i915 state tracking structures. */
10222 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10223 bool force_restore
)
10225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10227 struct drm_plane
*plane
;
10228 struct intel_crtc
*crtc
;
10229 struct intel_encoder
*encoder
;
10232 intel_modeset_readout_hw_state(dev
);
10235 * Now that we have the config, copy it to each CRTC struct
10236 * Note that this could go away if we move to using crtc_config
10237 * checking everywhere.
10239 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10241 if (crtc
->active
&& i915_fastboot
) {
10242 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10244 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10245 crtc
->base
.base
.id
);
10246 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10250 /* HW state is read out, now we need to sanitize this mess. */
10251 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10253 intel_sanitize_encoder(encoder
);
10256 for_each_pipe(pipe
) {
10257 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10258 intel_sanitize_crtc(crtc
);
10259 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10262 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10263 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10265 if (!pll
->on
|| pll
->active
)
10268 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10270 pll
->disable(dev_priv
, pll
);
10274 if (force_restore
) {
10276 * We need to use raw interfaces for restoring state to avoid
10277 * checking (bogus) intermediate states.
10279 for_each_pipe(pipe
) {
10280 struct drm_crtc
*crtc
=
10281 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10283 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10286 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
10287 intel_plane_restore(plane
);
10289 i915_redisable_vga(dev
);
10291 intel_modeset_update_staged_output_state(dev
);
10294 intel_modeset_check_state(dev
);
10296 drm_mode_config_reset(dev
);
10299 void intel_modeset_gem_init(struct drm_device
*dev
)
10301 intel_modeset_init_hw(dev
);
10303 intel_setup_overlay(dev
);
10305 intel_modeset_setup_hw_state(dev
, false);
10308 void intel_modeset_cleanup(struct drm_device
*dev
)
10310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10311 struct drm_crtc
*crtc
;
10312 struct intel_crtc
*intel_crtc
;
10315 * Interrupts and polling as the first thing to avoid creating havoc.
10316 * Too much stuff here (turning of rps, connectors, ...) would
10317 * experience fancy races otherwise.
10319 drm_irq_uninstall(dev
);
10320 cancel_work_sync(&dev_priv
->hotplug_work
);
10322 * Due to the hpd irq storm handling the hotplug work can re-arm the
10323 * poll handlers. Hence disable polling after hpd handling is shut down.
10325 drm_kms_helper_poll_fini(dev
);
10327 mutex_lock(&dev
->struct_mutex
);
10329 intel_unregister_dsm_handler();
10331 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10332 /* Skip inactive CRTCs */
10336 intel_crtc
= to_intel_crtc(crtc
);
10337 intel_increase_pllclock(crtc
);
10340 intel_disable_fbc(dev
);
10342 intel_disable_gt_powersave(dev
);
10344 ironlake_teardown_rc6(dev
);
10346 mutex_unlock(&dev
->struct_mutex
);
10348 /* flush any delayed tasks or pending work */
10349 flush_scheduled_work();
10351 /* destroy backlight, if any, before the connectors */
10352 intel_panel_destroy_backlight(dev
);
10354 drm_mode_config_cleanup(dev
);
10356 intel_cleanup_overlay(dev
);
10360 * Return which encoder is currently attached for connector.
10362 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10364 return &intel_attached_encoder(connector
)->base
;
10367 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10368 struct intel_encoder
*encoder
)
10370 connector
->encoder
= encoder
;
10371 drm_mode_connector_attach_encoder(&connector
->base
,
10376 * set vga decode state - true == enable VGA decode
10378 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10383 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10385 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10387 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10388 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10392 struct intel_display_error_state
{
10394 u32 power_well_driver
;
10396 struct intel_cursor_error_state
{
10401 } cursor
[I915_MAX_PIPES
];
10403 struct intel_pipe_error_state
{
10404 enum transcoder cpu_transcoder
;
10414 } pipe
[I915_MAX_PIPES
];
10416 struct intel_plane_error_state
{
10424 } plane
[I915_MAX_PIPES
];
10427 struct intel_display_error_state
*
10428 intel_display_capture_error_state(struct drm_device
*dev
)
10430 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10431 struct intel_display_error_state
*error
;
10432 enum transcoder cpu_transcoder
;
10435 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10439 if (HAS_POWER_WELL(dev
))
10440 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10443 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
10444 error
->pipe
[i
].cpu_transcoder
= cpu_transcoder
;
10446 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10447 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10448 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10449 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10451 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10452 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10453 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10456 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10457 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10458 if (INTEL_INFO(dev
)->gen
<= 3) {
10459 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10460 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10462 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10463 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10464 if (INTEL_INFO(dev
)->gen
>= 4) {
10465 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10466 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10469 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10470 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10471 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10472 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10473 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10474 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10475 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10476 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10479 /* In the code above we read the registers without checking if the power
10480 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10481 * prevent the next I915_WRITE from detecting it and printing an error
10483 intel_uncore_clear_errors(dev
);
10488 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10491 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10492 struct drm_device
*dev
,
10493 struct intel_display_error_state
*error
)
10497 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10498 if (HAS_POWER_WELL(dev
))
10499 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10500 error
->power_well_driver
);
10502 err_printf(m
, "Pipe [%d]:\n", i
);
10503 err_printf(m
, " CPU transcoder: %c\n",
10504 transcoder_name(error
->pipe
[i
].cpu_transcoder
));
10505 err_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
10506 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10507 err_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
10508 err_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
10509 err_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
10510 err_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
10511 err_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
10512 err_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
10514 err_printf(m
, "Plane [%d]:\n", i
);
10515 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10516 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10517 if (INTEL_INFO(dev
)->gen
<= 3) {
10518 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10519 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10521 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10522 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10523 if (INTEL_INFO(dev
)->gen
>= 4) {
10524 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10525 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10528 err_printf(m
, "Cursor [%d]:\n", i
);
10529 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10530 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10531 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);