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drm/i915: fixup interlaced vertical timings confusion, part 1
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
61 } intel_clock_t;
62
63 typedef struct {
64 int min, max;
65 } intel_range_t;
66
67 typedef struct {
68 int dot_limit;
69 int p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
88 static bool
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92
93 static bool
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
97 static bool
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
101
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
104 {
105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
110 }
111
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
123 .find_pll = intel_find_best_PLL,
124 };
125
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
137 .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
181 },
182 .find_pll = intel_g4x_find_best_PLL,
183 };
184
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
196 .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
210 },
211 .find_pll = intel_g4x_find_best_PLL,
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
225 },
226 .find_pll = intel_g4x_find_best_PLL,
227 };
228
229 static const intel_limit_t intel_limits_g4x_display_port = {
230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
239 .p2_slow = 10, .p2_fast = 10 },
240 .find_pll = intel_find_pll_g4x_dp,
241 };
242
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
246 /* Pineview's Ncounter is a ring counter */
247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
249 /* Pineview only has one combined m divider, which we treat as m2. */
250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
256 .find_pll = intel_find_best_PLL,
257 };
258
259 static const intel_limit_t intel_limits_pineview_lvds = {
260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
270 .find_pll = intel_find_best_PLL,
271 };
272
273 /* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
278 static const intel_limit_t intel_limits_ironlake_dac = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
289 .find_pll = intel_g4x_find_best_PLL,
290 };
291
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
303 .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
329 .p1 = { .min = 2, .max = 8 },
330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
332 .find_pll = intel_g4x_find_best_PLL,
333 };
334
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
343 .p1 = { .min = 2, .max = 6 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
346 .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
359 .p2_slow = 10, .p2_fast = 10 },
360 .find_pll = intel_find_pll_ironlake_dp,
361 };
362
363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
365 {
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 const intel_limit_t *limit;
369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
379 if (refclk == 100000)
380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
387 else
388 limit = &intel_limits_ironlake_dac;
389
390 return limit;
391 }
392
393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394 {
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_dual_channel_lvds;
404 else
405 /* LVDS with dual channel */
406 limit = &intel_limits_g4x_single_channel_lvds;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
409 limit = &intel_limits_g4x_hdmi;
410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
411 limit = &intel_limits_g4x_sdvo;
412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
413 limit = &intel_limits_g4x_display_port;
414 } else /* The option is for other outputs */
415 limit = &intel_limits_i9xx_sdvo;
416
417 return limit;
418 }
419
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
421 {
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
425 if (HAS_PCH_SPLIT(dev))
426 limit = intel_ironlake_limit(crtc, refclk);
427 else if (IS_G4X(dev)) {
428 limit = intel_g4x_limit(crtc);
429 } else if (IS_PINEVIEW(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_pineview_lvds;
432 else
433 limit = &intel_limits_pineview_sdvo;
434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
441 limit = &intel_limits_i8xx_lvds;
442 else
443 limit = &intel_limits_i8xx_dvo;
444 }
445 return limit;
446 }
447
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk, intel_clock_t *clock)
450 {
451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455 }
456
457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458 {
459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
461 return;
462 }
463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467 }
468
469 /**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
473 {
474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
483 }
484
485 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
486 /**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
491 static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
494 {
495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
496 INTELPllInvalid("p1 out of range\n");
497 if (clock->p < limit->p.min || limit->p.max < clock->p)
498 INTELPllInvalid("p out of range\n");
499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
500 INTELPllInvalid("m2 out of range\n");
501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
502 INTELPllInvalid("m1 out of range\n");
503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504 INTELPllInvalid("m1 <= m2\n");
505 if (clock->m < limit->m.min || limit->m.max < clock->m)
506 INTELPllInvalid("m out of range\n");
507 if (clock->n < limit->n.min || limit->n.max < clock->n)
508 INTELPllInvalid("n out of range\n");
509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
510 INTELPllInvalid("vco out of range\n");
511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515 INTELPllInvalid("dot out of range\n");
516
517 return true;
518 }
519
520 static bool
521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
524
525 {
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
529 int err = target;
530
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532 (I915_READ(LVDS)) != 0) {
533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
551 memset(best_clock, 0, sizeof(*best_clock));
552
553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
564 int this_err;
565
566 intel_clock(dev, refclk, &clock);
567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
569 continue;
570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585 }
586
587 static bool
588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
591 {
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
602 int lvds_reg;
603
604 if (HAS_PCH_SPLIT(dev))
605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
622 /* based on hardware requirement, prefer smaller n to precision */
623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624 /* based on hardware requirement, prefere larger m1,m2 */
625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
633 intel_clock(dev, refclk, &clock);
634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
636 continue;
637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
640
641 this_err = abs(clock.dot - target);
642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
652 return found;
653 }
654
655 static bool
656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
659 {
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
662
663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679 }
680
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
682 static bool
683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
686 {
687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
707 }
708
709 /**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
718 {
719 struct drm_i915_private *dev_priv = dev->dev_private;
720 int pipestat_reg = PIPESTAT(pipe);
721
722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
738 /* Wait for vblank interrupt bit to set */
739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
742 DRM_DEBUG_KMS("vblank wait timed out\n");
743 }
744
745 /*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
760 *
761 */
762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
763 {
764 struct drm_i915_private *dev_priv = dev->dev_private;
765
766 if (INTEL_INFO(dev)->gen >= 4) {
767 int reg = PIPECONF(pipe);
768
769 /* Wait for the Pipe State to go off */
770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
775 int reg = PIPEDSL(pipe);
776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
780 last_line = I915_READ(reg) & DSL_LINEMASK;
781 mdelay(5);
782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
787 }
788
789 static const char *state_string(bool enabled)
790 {
791 return enabled ? "on" : "off";
792 }
793
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797 {
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808 }
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
812 /* For ILK+ */
813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815 {
816 int reg;
817 u32 val;
818 bool cur_state;
819
820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839 }
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845 {
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856 }
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862 {
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873 }
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890 }
891
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894 {
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901 }
902
903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905 {
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
909 bool locked = true;
910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
929 pipe_name(pipe));
930 }
931
932 void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
934 {
935 int reg;
936 u32 val;
937 bool cur_state;
938
939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
948 pipe_name(pipe), state_string(state), state_string(cur_state));
949 }
950
951 static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
953 {
954 int reg;
955 u32 val;
956 bool cur_state;
957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
964 }
965
966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971 {
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
976 /* Planes are fixed to pipes on ILK+ */
977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
983 return;
984 }
985
986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
995 }
996 }
997
998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999 {
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011 {
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044 {
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060 {
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076 {
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, int reg, u32 port_sel)
1091 {
1092 u32 val = I915_READ(reg);
1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095 reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100 {
1101 u32 val = I915_READ(reg);
1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104 reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109 {
1110 int reg;
1111 u32 val;
1112
1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
1121 pipe_name(pipe));
1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127 pipe_name(pipe));
1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199 }
1200
1201 /**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211 {
1212 int reg;
1213 u32 val;
1214
1215 if (pipe > 1)
1216 return;
1217
1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 int reg;
1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239 if (pipe > 1)
1240 return;
1241
1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 int reg;
1269 u32 val;
1270
1271 /* PCH only available on ILK+ */
1272 BUG_ON(dev_priv->info->gen < 5);
1273
1274 /* Make sure PCH DPLL is enabled */
1275 assert_pch_pll_enabled(dev_priv, pipe);
1276
1277 /* FDI must be feeding us bits for PCH ports */
1278 assert_fdi_tx_enabled(dev_priv, pipe);
1279 assert_fdi_rx_enabled(dev_priv, pipe);
1280
1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
1283
1284 if (HAS_PCH_IBX(dev_priv->dev)) {
1285 /*
1286 * make the BPC in transcoder be consistent with
1287 * that in pipeconf reg.
1288 */
1289 val &= ~PIPE_BPC_MASK;
1290 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1291 }
1292 I915_WRITE(reg, val | TRANS_ENABLE);
1293 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1294 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1295 }
1296
1297 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299 {
1300 int reg;
1301 u32 val;
1302
1303 /* FDI relies on the transcoder */
1304 assert_fdi_tx_disabled(dev_priv, pipe);
1305 assert_fdi_rx_disabled(dev_priv, pipe);
1306
1307 /* Ports must be off as well */
1308 assert_pch_ports_disabled(dev_priv, pipe);
1309
1310 reg = TRANSCONF(pipe);
1311 val = I915_READ(reg);
1312 val &= ~TRANS_ENABLE;
1313 I915_WRITE(reg, val);
1314 /* wait for PCH transcoder off, transcoder state */
1315 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1316 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1317 }
1318
1319 /**
1320 * intel_enable_pipe - enable a pipe, asserting requirements
1321 * @dev_priv: i915 private structure
1322 * @pipe: pipe to enable
1323 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1324 *
1325 * Enable @pipe, making sure that various hardware specific requirements
1326 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1327 *
1328 * @pipe should be %PIPE_A or %PIPE_B.
1329 *
1330 * Will wait until the pipe is actually running (i.e. first vblank) before
1331 * returning.
1332 */
1333 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1334 bool pch_port)
1335 {
1336 int reg;
1337 u32 val;
1338
1339 /*
1340 * A pipe without a PLL won't actually be able to drive bits from
1341 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1342 * need the check.
1343 */
1344 if (!HAS_PCH_SPLIT(dev_priv->dev))
1345 assert_pll_enabled(dev_priv, pipe);
1346 else {
1347 if (pch_port) {
1348 /* if driving the PCH, we need FDI enabled */
1349 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1350 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1351 }
1352 /* FIXME: assert CPU port conditions for SNB+ */
1353 }
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
1357 if (val & PIPECONF_ENABLE)
1358 return;
1359
1360 I915_WRITE(reg, val | PIPECONF_ENABLE);
1361 intel_wait_for_vblank(dev_priv->dev, pipe);
1362 }
1363
1364 /**
1365 * intel_disable_pipe - disable a pipe, asserting requirements
1366 * @dev_priv: i915 private structure
1367 * @pipe: pipe to disable
1368 *
1369 * Disable @pipe, making sure that various hardware specific requirements
1370 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1371 *
1372 * @pipe should be %PIPE_A or %PIPE_B.
1373 *
1374 * Will wait until the pipe has shut down before returning.
1375 */
1376 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1377 enum pipe pipe)
1378 {
1379 int reg;
1380 u32 val;
1381
1382 /*
1383 * Make sure planes won't keep trying to pump pixels to us,
1384 * or we might hang the display.
1385 */
1386 assert_planes_disabled(dev_priv, pipe);
1387
1388 /* Don't disable pipe A or pipe A PLLs if needed */
1389 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1390 return;
1391
1392 reg = PIPECONF(pipe);
1393 val = I915_READ(reg);
1394 if ((val & PIPECONF_ENABLE) == 0)
1395 return;
1396
1397 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1398 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1399 }
1400
1401 /*
1402 * Plane regs are double buffered, going from enabled->disabled needs a
1403 * trigger in order to latch. The display address reg provides this.
1404 */
1405 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1406 enum plane plane)
1407 {
1408 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1409 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1410 }
1411
1412 /**
1413 * intel_enable_plane - enable a display plane on a given pipe
1414 * @dev_priv: i915 private structure
1415 * @plane: plane to enable
1416 * @pipe: pipe being fed
1417 *
1418 * Enable @plane on @pipe, making sure that @pipe is running first.
1419 */
1420 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1421 enum plane plane, enum pipe pipe)
1422 {
1423 int reg;
1424 u32 val;
1425
1426 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1427 assert_pipe_enabled(dev_priv, pipe);
1428
1429 reg = DSPCNTR(plane);
1430 val = I915_READ(reg);
1431 if (val & DISPLAY_PLANE_ENABLE)
1432 return;
1433
1434 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1435 intel_flush_display_plane(dev_priv, plane);
1436 intel_wait_for_vblank(dev_priv->dev, pipe);
1437 }
1438
1439 /**
1440 * intel_disable_plane - disable a display plane
1441 * @dev_priv: i915 private structure
1442 * @plane: plane to disable
1443 * @pipe: pipe consuming the data
1444 *
1445 * Disable @plane; should be an independent operation.
1446 */
1447 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1448 enum plane plane, enum pipe pipe)
1449 {
1450 int reg;
1451 u32 val;
1452
1453 reg = DSPCNTR(plane);
1454 val = I915_READ(reg);
1455 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1456 return;
1457
1458 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1459 intel_flush_display_plane(dev_priv, plane);
1460 intel_wait_for_vblank(dev_priv->dev, pipe);
1461 }
1462
1463 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, int reg, u32 port_sel)
1465 {
1466 u32 val = I915_READ(reg);
1467 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1468 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1469 I915_WRITE(reg, val & ~DP_PORT_EN);
1470 }
1471 }
1472
1473 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, int reg)
1475 {
1476 u32 val = I915_READ(reg);
1477 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1478 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1479 reg, pipe);
1480 I915_WRITE(reg, val & ~PORT_ENABLE);
1481 }
1482 }
1483
1484 /* Disable any ports connected to this transcoder */
1485 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487 {
1488 u32 reg, val;
1489
1490 val = I915_READ(PCH_PP_CONTROL);
1491 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1492
1493 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1494 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1495 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1496
1497 reg = PCH_ADPA;
1498 val = I915_READ(reg);
1499 if (adpa_pipe_enabled(dev_priv, val, pipe))
1500 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1501
1502 reg = PCH_LVDS;
1503 val = I915_READ(reg);
1504 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1505 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1506 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1507 POSTING_READ(reg);
1508 udelay(100);
1509 }
1510
1511 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1512 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1513 disable_pch_hdmi(dev_priv, pipe, HDMID);
1514 }
1515
1516 static void i8xx_disable_fbc(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 u32 fbc_ctl;
1520
1521 /* Disable compression */
1522 fbc_ctl = I915_READ(FBC_CONTROL);
1523 if ((fbc_ctl & FBC_CTL_EN) == 0)
1524 return;
1525
1526 fbc_ctl &= ~FBC_CTL_EN;
1527 I915_WRITE(FBC_CONTROL, fbc_ctl);
1528
1529 /* Wait for compressing bit to clear */
1530 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1531 DRM_DEBUG_KMS("FBC idle timed out\n");
1532 return;
1533 }
1534
1535 DRM_DEBUG_KMS("disabled FBC\n");
1536 }
1537
1538 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1539 {
1540 struct drm_device *dev = crtc->dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_framebuffer *fb = crtc->fb;
1543 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1544 struct drm_i915_gem_object *obj = intel_fb->obj;
1545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1546 int cfb_pitch;
1547 int plane, i;
1548 u32 fbc_ctl, fbc_ctl2;
1549
1550 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1551 if (fb->pitches[0] < cfb_pitch)
1552 cfb_pitch = fb->pitches[0];
1553
1554 /* FBC_CTL wants 64B units */
1555 cfb_pitch = (cfb_pitch / 64) - 1;
1556 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1557
1558 /* Clear old tags */
1559 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1560 I915_WRITE(FBC_TAG + (i * 4), 0);
1561
1562 /* Set it up... */
1563 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1564 fbc_ctl2 |= plane;
1565 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1566 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1567
1568 /* enable it... */
1569 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1570 if (IS_I945GM(dev))
1571 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1572 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1573 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1574 fbc_ctl |= obj->fence_reg;
1575 I915_WRITE(FBC_CONTROL, fbc_ctl);
1576
1577 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1578 cfb_pitch, crtc->y, intel_crtc->plane);
1579 }
1580
1581 static bool i8xx_fbc_enabled(struct drm_device *dev)
1582 {
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1586 }
1587
1588 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1589 {
1590 struct drm_device *dev = crtc->dev;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592 struct drm_framebuffer *fb = crtc->fb;
1593 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1594 struct drm_i915_gem_object *obj = intel_fb->obj;
1595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1596 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1597 unsigned long stall_watermark = 200;
1598 u32 dpfc_ctl;
1599
1600 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1601 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1602 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1603
1604 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1605 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1606 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1607 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1608
1609 /* enable it... */
1610 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1611
1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613 }
1614
1615 static void g4x_disable_fbc(struct drm_device *dev)
1616 {
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(DPFC_CONTROL);
1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1625
1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
1628 }
1629
1630 static bool g4x_fbc_enabled(struct drm_device *dev)
1631 {
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1635 }
1636
1637 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1638 {
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640 u32 blt_ecoskpd;
1641
1642 /* Make sure blitter notifies FBC of writes */
1643 gen6_gt_force_wake_get(dev_priv);
1644 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1645 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1646 GEN6_BLITTER_LOCK_SHIFT;
1647 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1648 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1649 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1650 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1651 GEN6_BLITTER_LOCK_SHIFT);
1652 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1653 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1654 gen6_gt_force_wake_put(dev_priv);
1655 }
1656
1657 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1658 {
1659 struct drm_device *dev = crtc->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 struct drm_framebuffer *fb = crtc->fb;
1662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1663 struct drm_i915_gem_object *obj = intel_fb->obj;
1664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1665 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1666 unsigned long stall_watermark = 200;
1667 u32 dpfc_ctl;
1668
1669 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1670 dpfc_ctl &= DPFC_RESERVED;
1671 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1672 /* Set persistent mode for front-buffer rendering, ala X. */
1673 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1674 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1675 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1676
1677 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1678 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1679 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1680 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1681 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1682 /* enable it... */
1683 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1684
1685 if (IS_GEN6(dev)) {
1686 I915_WRITE(SNB_DPFC_CTL_SA,
1687 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1688 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1689 sandybridge_blit_fbc_update(dev);
1690 }
1691
1692 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1693 }
1694
1695 static void ironlake_disable_fbc(struct drm_device *dev)
1696 {
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 u32 dpfc_ctl;
1699
1700 /* Disable compression */
1701 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1702 if (dpfc_ctl & DPFC_CTL_EN) {
1703 dpfc_ctl &= ~DPFC_CTL_EN;
1704 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1705
1706 DRM_DEBUG_KMS("disabled FBC\n");
1707 }
1708 }
1709
1710 static bool ironlake_fbc_enabled(struct drm_device *dev)
1711 {
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713
1714 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1715 }
1716
1717 bool intel_fbc_enabled(struct drm_device *dev)
1718 {
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
1721 if (!dev_priv->display.fbc_enabled)
1722 return false;
1723
1724 return dev_priv->display.fbc_enabled(dev);
1725 }
1726
1727 static void intel_fbc_work_fn(struct work_struct *__work)
1728 {
1729 struct intel_fbc_work *work =
1730 container_of(to_delayed_work(__work),
1731 struct intel_fbc_work, work);
1732 struct drm_device *dev = work->crtc->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734
1735 mutex_lock(&dev->struct_mutex);
1736 if (work == dev_priv->fbc_work) {
1737 /* Double check that we haven't switched fb without cancelling
1738 * the prior work.
1739 */
1740 if (work->crtc->fb == work->fb) {
1741 dev_priv->display.enable_fbc(work->crtc,
1742 work->interval);
1743
1744 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1745 dev_priv->cfb_fb = work->crtc->fb->base.id;
1746 dev_priv->cfb_y = work->crtc->y;
1747 }
1748
1749 dev_priv->fbc_work = NULL;
1750 }
1751 mutex_unlock(&dev->struct_mutex);
1752
1753 kfree(work);
1754 }
1755
1756 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1757 {
1758 if (dev_priv->fbc_work == NULL)
1759 return;
1760
1761 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1762
1763 /* Synchronisation is provided by struct_mutex and checking of
1764 * dev_priv->fbc_work, so we can perform the cancellation
1765 * entirely asynchronously.
1766 */
1767 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1768 /* tasklet was killed before being run, clean up */
1769 kfree(dev_priv->fbc_work);
1770
1771 /* Mark the work as no longer wanted so that if it does
1772 * wake-up (because the work was already running and waiting
1773 * for our mutex), it will discover that is no longer
1774 * necessary to run.
1775 */
1776 dev_priv->fbc_work = NULL;
1777 }
1778
1779 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1780 {
1781 struct intel_fbc_work *work;
1782 struct drm_device *dev = crtc->dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784
1785 if (!dev_priv->display.enable_fbc)
1786 return;
1787
1788 intel_cancel_fbc_work(dev_priv);
1789
1790 work = kzalloc(sizeof *work, GFP_KERNEL);
1791 if (work == NULL) {
1792 dev_priv->display.enable_fbc(crtc, interval);
1793 return;
1794 }
1795
1796 work->crtc = crtc;
1797 work->fb = crtc->fb;
1798 work->interval = interval;
1799 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1800
1801 dev_priv->fbc_work = work;
1802
1803 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1804
1805 /* Delay the actual enabling to let pageflipping cease and the
1806 * display to settle before starting the compression. Note that
1807 * this delay also serves a second purpose: it allows for a
1808 * vblank to pass after disabling the FBC before we attempt
1809 * to modify the control registers.
1810 *
1811 * A more complicated solution would involve tracking vblanks
1812 * following the termination of the page-flipping sequence
1813 * and indeed performing the enable as a co-routine and not
1814 * waiting synchronously upon the vblank.
1815 */
1816 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1817 }
1818
1819 void intel_disable_fbc(struct drm_device *dev)
1820 {
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822
1823 intel_cancel_fbc_work(dev_priv);
1824
1825 if (!dev_priv->display.disable_fbc)
1826 return;
1827
1828 dev_priv->display.disable_fbc(dev);
1829 dev_priv->cfb_plane = -1;
1830 }
1831
1832 /**
1833 * intel_update_fbc - enable/disable FBC as needed
1834 * @dev: the drm_device
1835 *
1836 * Set up the framebuffer compression hardware at mode set time. We
1837 * enable it if possible:
1838 * - plane A only (on pre-965)
1839 * - no pixel mulitply/line duplication
1840 * - no alpha buffer discard
1841 * - no dual wide
1842 * - framebuffer <= 2048 in width, 1536 in height
1843 *
1844 * We can't assume that any compression will take place (worst case),
1845 * so the compressed buffer has to be the same size as the uncompressed
1846 * one. It also must reside (along with the line length buffer) in
1847 * stolen memory.
1848 *
1849 * We need to enable/disable FBC on a global basis.
1850 */
1851 static void intel_update_fbc(struct drm_device *dev)
1852 {
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854 struct drm_crtc *crtc = NULL, *tmp_crtc;
1855 struct intel_crtc *intel_crtc;
1856 struct drm_framebuffer *fb;
1857 struct intel_framebuffer *intel_fb;
1858 struct drm_i915_gem_object *obj;
1859 int enable_fbc;
1860
1861 DRM_DEBUG_KMS("\n");
1862
1863 if (!i915_powersave)
1864 return;
1865
1866 if (!I915_HAS_FBC(dev))
1867 return;
1868
1869 /*
1870 * If FBC is already on, we just have to verify that we can
1871 * keep it that way...
1872 * Need to disable if:
1873 * - more than one pipe is active
1874 * - changing FBC params (stride, fence, mode)
1875 * - new fb is too large to fit in compressed buffer
1876 * - going to an unsupported config (interlace, pixel multiply, etc.)
1877 */
1878 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1879 if (tmp_crtc->enabled && tmp_crtc->fb) {
1880 if (crtc) {
1881 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1882 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1883 goto out_disable;
1884 }
1885 crtc = tmp_crtc;
1886 }
1887 }
1888
1889 if (!crtc || crtc->fb == NULL) {
1890 DRM_DEBUG_KMS("no output, disabling\n");
1891 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1892 goto out_disable;
1893 }
1894
1895 intel_crtc = to_intel_crtc(crtc);
1896 fb = crtc->fb;
1897 intel_fb = to_intel_framebuffer(fb);
1898 obj = intel_fb->obj;
1899
1900 enable_fbc = i915_enable_fbc;
1901 if (enable_fbc < 0) {
1902 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1903 enable_fbc = 1;
1904 if (INTEL_INFO(dev)->gen <= 6)
1905 enable_fbc = 0;
1906 }
1907 if (!enable_fbc) {
1908 DRM_DEBUG_KMS("fbc disabled per module param\n");
1909 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1910 goto out_disable;
1911 }
1912 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1913 DRM_DEBUG_KMS("framebuffer too large, disabling "
1914 "compression\n");
1915 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1916 goto out_disable;
1917 }
1918 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1919 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1920 DRM_DEBUG_KMS("mode incompatible with compression, "
1921 "disabling\n");
1922 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1923 goto out_disable;
1924 }
1925 if ((crtc->mode.hdisplay > 2048) ||
1926 (crtc->mode.vdisplay > 1536)) {
1927 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1928 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1929 goto out_disable;
1930 }
1931 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1932 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1933 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1934 goto out_disable;
1935 }
1936
1937 /* The use of a CPU fence is mandatory in order to detect writes
1938 * by the CPU to the scanout and trigger updates to the FBC.
1939 */
1940 if (obj->tiling_mode != I915_TILING_X ||
1941 obj->fence_reg == I915_FENCE_REG_NONE) {
1942 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1943 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1944 goto out_disable;
1945 }
1946
1947 /* If the kernel debugger is active, always disable compression */
1948 if (in_dbg_master())
1949 goto out_disable;
1950
1951 /* If the scanout has not changed, don't modify the FBC settings.
1952 * Note that we make the fundamental assumption that the fb->obj
1953 * cannot be unpinned (and have its GTT offset and fence revoked)
1954 * without first being decoupled from the scanout and FBC disabled.
1955 */
1956 if (dev_priv->cfb_plane == intel_crtc->plane &&
1957 dev_priv->cfb_fb == fb->base.id &&
1958 dev_priv->cfb_y == crtc->y)
1959 return;
1960
1961 if (intel_fbc_enabled(dev)) {
1962 /* We update FBC along two paths, after changing fb/crtc
1963 * configuration (modeswitching) and after page-flipping
1964 * finishes. For the latter, we know that not only did
1965 * we disable the FBC at the start of the page-flip
1966 * sequence, but also more than one vblank has passed.
1967 *
1968 * For the former case of modeswitching, it is possible
1969 * to switch between two FBC valid configurations
1970 * instantaneously so we do need to disable the FBC
1971 * before we can modify its control registers. We also
1972 * have to wait for the next vblank for that to take
1973 * effect. However, since we delay enabling FBC we can
1974 * assume that a vblank has passed since disabling and
1975 * that we can safely alter the registers in the deferred
1976 * callback.
1977 *
1978 * In the scenario that we go from a valid to invalid
1979 * and then back to valid FBC configuration we have
1980 * no strict enforcement that a vblank occurred since
1981 * disabling the FBC. However, along all current pipe
1982 * disabling paths we do need to wait for a vblank at
1983 * some point. And we wait before enabling FBC anyway.
1984 */
1985 DRM_DEBUG_KMS("disabling active FBC for update\n");
1986 intel_disable_fbc(dev);
1987 }
1988
1989 intel_enable_fbc(crtc, 500);
1990 return;
1991
1992 out_disable:
1993 /* Multiple disables should be harmless */
1994 if (intel_fbc_enabled(dev)) {
1995 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1996 intel_disable_fbc(dev);
1997 }
1998 }
1999
2000 int
2001 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2002 struct drm_i915_gem_object *obj,
2003 struct intel_ring_buffer *pipelined)
2004 {
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 u32 alignment;
2007 int ret;
2008
2009 switch (obj->tiling_mode) {
2010 case I915_TILING_NONE:
2011 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2012 alignment = 128 * 1024;
2013 else if (INTEL_INFO(dev)->gen >= 4)
2014 alignment = 4 * 1024;
2015 else
2016 alignment = 64 * 1024;
2017 break;
2018 case I915_TILING_X:
2019 /* pin() will align the object as required by fence */
2020 alignment = 0;
2021 break;
2022 case I915_TILING_Y:
2023 /* FIXME: Is this true? */
2024 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2025 return -EINVAL;
2026 default:
2027 BUG();
2028 }
2029
2030 dev_priv->mm.interruptible = false;
2031 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2032 if (ret)
2033 goto err_interruptible;
2034
2035 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2036 * fence, whereas 965+ only requires a fence if using
2037 * framebuffer compression. For simplicity, we always install
2038 * a fence as the cost is not that onerous.
2039 */
2040 if (obj->tiling_mode != I915_TILING_NONE) {
2041 ret = i915_gem_object_get_fence(obj, pipelined);
2042 if (ret)
2043 goto err_unpin;
2044
2045 i915_gem_object_pin_fence(obj);
2046 }
2047
2048 dev_priv->mm.interruptible = true;
2049 return 0;
2050
2051 err_unpin:
2052 i915_gem_object_unpin(obj);
2053 err_interruptible:
2054 dev_priv->mm.interruptible = true;
2055 return ret;
2056 }
2057
2058 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2059 {
2060 i915_gem_object_unpin_fence(obj);
2061 i915_gem_object_unpin(obj);
2062 }
2063
2064 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2065 int x, int y)
2066 {
2067 struct drm_device *dev = crtc->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2070 struct intel_framebuffer *intel_fb;
2071 struct drm_i915_gem_object *obj;
2072 int plane = intel_crtc->plane;
2073 unsigned long Start, Offset;
2074 u32 dspcntr;
2075 u32 reg;
2076
2077 switch (plane) {
2078 case 0:
2079 case 1:
2080 break;
2081 default:
2082 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2083 return -EINVAL;
2084 }
2085
2086 intel_fb = to_intel_framebuffer(fb);
2087 obj = intel_fb->obj;
2088
2089 reg = DSPCNTR(plane);
2090 dspcntr = I915_READ(reg);
2091 /* Mask out pixel format bits in case we change it */
2092 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2093 switch (fb->bits_per_pixel) {
2094 case 8:
2095 dspcntr |= DISPPLANE_8BPP;
2096 break;
2097 case 16:
2098 if (fb->depth == 15)
2099 dspcntr |= DISPPLANE_15_16BPP;
2100 else
2101 dspcntr |= DISPPLANE_16BPP;
2102 break;
2103 case 24:
2104 case 32:
2105 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2106 break;
2107 default:
2108 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2109 return -EINVAL;
2110 }
2111 if (INTEL_INFO(dev)->gen >= 4) {
2112 if (obj->tiling_mode != I915_TILING_NONE)
2113 dspcntr |= DISPPLANE_TILED;
2114 else
2115 dspcntr &= ~DISPPLANE_TILED;
2116 }
2117
2118 I915_WRITE(reg, dspcntr);
2119
2120 Start = obj->gtt_offset;
2121 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2122
2123 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2124 Start, Offset, x, y, fb->pitches[0]);
2125 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2126 if (INTEL_INFO(dev)->gen >= 4) {
2127 I915_WRITE(DSPSURF(plane), Start);
2128 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129 I915_WRITE(DSPADDR(plane), Offset);
2130 } else
2131 I915_WRITE(DSPADDR(plane), Start + Offset);
2132 POSTING_READ(reg);
2133
2134 return 0;
2135 }
2136
2137 static int ironlake_update_plane(struct drm_crtc *crtc,
2138 struct drm_framebuffer *fb, int x, int y)
2139 {
2140 struct drm_device *dev = crtc->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143 struct intel_framebuffer *intel_fb;
2144 struct drm_i915_gem_object *obj;
2145 int plane = intel_crtc->plane;
2146 unsigned long Start, Offset;
2147 u32 dspcntr;
2148 u32 reg;
2149
2150 switch (plane) {
2151 case 0:
2152 case 1:
2153 case 2:
2154 break;
2155 default:
2156 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2157 return -EINVAL;
2158 }
2159
2160 intel_fb = to_intel_framebuffer(fb);
2161 obj = intel_fb->obj;
2162
2163 reg = DSPCNTR(plane);
2164 dspcntr = I915_READ(reg);
2165 /* Mask out pixel format bits in case we change it */
2166 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2167 switch (fb->bits_per_pixel) {
2168 case 8:
2169 dspcntr |= DISPPLANE_8BPP;
2170 break;
2171 case 16:
2172 if (fb->depth != 16)
2173 return -EINVAL;
2174
2175 dspcntr |= DISPPLANE_16BPP;
2176 break;
2177 case 24:
2178 case 32:
2179 if (fb->depth == 24)
2180 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2181 else if (fb->depth == 30)
2182 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2183 else
2184 return -EINVAL;
2185 break;
2186 default:
2187 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2188 return -EINVAL;
2189 }
2190
2191 if (obj->tiling_mode != I915_TILING_NONE)
2192 dspcntr |= DISPPLANE_TILED;
2193 else
2194 dspcntr &= ~DISPPLANE_TILED;
2195
2196 /* must disable */
2197 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2198
2199 I915_WRITE(reg, dspcntr);
2200
2201 Start = obj->gtt_offset;
2202 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2203
2204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205 Start, Offset, x, y, fb->pitches[0]);
2206 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2207 I915_WRITE(DSPSURF(plane), Start);
2208 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2209 I915_WRITE(DSPADDR(plane), Offset);
2210 POSTING_READ(reg);
2211
2212 return 0;
2213 }
2214
2215 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2216 static int
2217 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2218 int x, int y, enum mode_set_atomic state)
2219 {
2220 struct drm_device *dev = crtc->dev;
2221 struct drm_i915_private *dev_priv = dev->dev_private;
2222 int ret;
2223
2224 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2225 if (ret)
2226 return ret;
2227
2228 intel_update_fbc(dev);
2229 intel_increase_pllclock(crtc);
2230
2231 return 0;
2232 }
2233
2234 static int
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236 struct drm_framebuffer *old_fb)
2237 {
2238 struct drm_device *dev = crtc->dev;
2239 struct drm_i915_master_private *master_priv;
2240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241 int ret;
2242
2243 /* no fb bound */
2244 if (!crtc->fb) {
2245 DRM_ERROR("No FB bound\n");
2246 return 0;
2247 }
2248
2249 switch (intel_crtc->plane) {
2250 case 0:
2251 case 1:
2252 break;
2253 case 2:
2254 if (IS_IVYBRIDGE(dev))
2255 break;
2256 /* fall through otherwise */
2257 default:
2258 DRM_ERROR("no plane for crtc\n");
2259 return -EINVAL;
2260 }
2261
2262 mutex_lock(&dev->struct_mutex);
2263 ret = intel_pin_and_fence_fb_obj(dev,
2264 to_intel_framebuffer(crtc->fb)->obj,
2265 NULL);
2266 if (ret != 0) {
2267 mutex_unlock(&dev->struct_mutex);
2268 DRM_ERROR("pin & fence failed\n");
2269 return ret;
2270 }
2271
2272 if (old_fb) {
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2275
2276 wait_event(dev_priv->pending_flip_queue,
2277 atomic_read(&dev_priv->mm.wedged) ||
2278 atomic_read(&obj->pending_flip) == 0);
2279
2280 /* Big Hammer, we also need to ensure that any pending
2281 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2282 * current scanout is retired before unpinning the old
2283 * framebuffer.
2284 *
2285 * This should only fail upon a hung GPU, in which case we
2286 * can safely continue.
2287 */
2288 ret = i915_gem_object_finish_gpu(obj);
2289 (void) ret;
2290 }
2291
2292 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2293 LEAVE_ATOMIC_MODE_SET);
2294 if (ret) {
2295 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2296 mutex_unlock(&dev->struct_mutex);
2297 DRM_ERROR("failed to update base address\n");
2298 return ret;
2299 }
2300
2301 if (old_fb) {
2302 intel_wait_for_vblank(dev, intel_crtc->pipe);
2303 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2304 }
2305
2306 mutex_unlock(&dev->struct_mutex);
2307
2308 if (!dev->primary->master)
2309 return 0;
2310
2311 master_priv = dev->primary->master->driver_priv;
2312 if (!master_priv->sarea_priv)
2313 return 0;
2314
2315 if (intel_crtc->pipe) {
2316 master_priv->sarea_priv->pipeB_x = x;
2317 master_priv->sarea_priv->pipeB_y = y;
2318 } else {
2319 master_priv->sarea_priv->pipeA_x = x;
2320 master_priv->sarea_priv->pipeA_y = y;
2321 }
2322
2323 return 0;
2324 }
2325
2326 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2327 {
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 u32 dpa_ctl;
2331
2332 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2333 dpa_ctl = I915_READ(DP_A);
2334 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2335
2336 if (clock < 200000) {
2337 u32 temp;
2338 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2339 /* workaround for 160Mhz:
2340 1) program 0x4600c bits 15:0 = 0x8124
2341 2) program 0x46010 bit 0 = 1
2342 3) program 0x46034 bit 24 = 1
2343 4) program 0x64000 bit 14 = 1
2344 */
2345 temp = I915_READ(0x4600c);
2346 temp &= 0xffff0000;
2347 I915_WRITE(0x4600c, temp | 0x8124);
2348
2349 temp = I915_READ(0x46010);
2350 I915_WRITE(0x46010, temp | 1);
2351
2352 temp = I915_READ(0x46034);
2353 I915_WRITE(0x46034, temp | (1 << 24));
2354 } else {
2355 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2356 }
2357 I915_WRITE(DP_A, dpa_ctl);
2358
2359 POSTING_READ(DP_A);
2360 udelay(500);
2361 }
2362
2363 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2364 {
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 u32 reg, temp;
2370
2371 /* enable normal train */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 if (IS_IVYBRIDGE(dev)) {
2375 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2376 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2377 } else {
2378 temp &= ~FDI_LINK_TRAIN_NONE;
2379 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2380 }
2381 I915_WRITE(reg, temp);
2382
2383 reg = FDI_RX_CTL(pipe);
2384 temp = I915_READ(reg);
2385 if (HAS_PCH_CPT(dev)) {
2386 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2387 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2388 } else {
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_NONE;
2391 }
2392 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2393
2394 /* wait one idle pattern time */
2395 POSTING_READ(reg);
2396 udelay(1000);
2397
2398 /* IVB wants error correction enabled */
2399 if (IS_IVYBRIDGE(dev))
2400 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2401 FDI_FE_ERRC_ENABLE);
2402 }
2403
2404 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2405 {
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 u32 flags = I915_READ(SOUTH_CHICKEN1);
2408
2409 flags |= FDI_PHASE_SYNC_OVR(pipe);
2410 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2411 flags |= FDI_PHASE_SYNC_EN(pipe);
2412 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2413 POSTING_READ(SOUTH_CHICKEN1);
2414 }
2415
2416 /* The FDI link training functions for ILK/Ibexpeak. */
2417 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2418 {
2419 struct drm_device *dev = crtc->dev;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422 int pipe = intel_crtc->pipe;
2423 int plane = intel_crtc->plane;
2424 u32 reg, temp, tries;
2425
2426 /* FDI needs bits from pipe & plane first */
2427 assert_pipe_enabled(dev_priv, pipe);
2428 assert_plane_enabled(dev_priv, plane);
2429
2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
2436 I915_WRITE(reg, temp);
2437 I915_READ(reg);
2438 udelay(150);
2439
2440 /* enable CPU FDI TX and PCH FDI RX */
2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
2443 temp &= ~(7 << 19);
2444 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2448
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_1;
2453 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2454
2455 POSTING_READ(reg);
2456 udelay(150);
2457
2458 /* Ironlake workaround, enable clock pointer after FDI enable*/
2459 if (HAS_PCH_IBX(dev)) {
2460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2462 FDI_RX_PHASE_SYNC_POINTER_EN);
2463 }
2464
2465 reg = FDI_RX_IIR(pipe);
2466 for (tries = 0; tries < 5; tries++) {
2467 temp = I915_READ(reg);
2468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2469
2470 if ((temp & FDI_RX_BIT_LOCK)) {
2471 DRM_DEBUG_KMS("FDI train 1 done.\n");
2472 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2473 break;
2474 }
2475 }
2476 if (tries == 5)
2477 DRM_ERROR("FDI train 1 fail!\n");
2478
2479 /* Train 2 */
2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_2;
2484 I915_WRITE(reg, temp);
2485
2486 reg = FDI_RX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_2;
2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
2493 udelay(150);
2494
2495 reg = FDI_RX_IIR(pipe);
2496 for (tries = 0; tries < 5; tries++) {
2497 temp = I915_READ(reg);
2498 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2499
2500 if (temp & FDI_RX_SYMBOL_LOCK) {
2501 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2502 DRM_DEBUG_KMS("FDI train 2 done.\n");
2503 break;
2504 }
2505 }
2506 if (tries == 5)
2507 DRM_ERROR("FDI train 2 fail!\n");
2508
2509 DRM_DEBUG_KMS("FDI train done\n");
2510
2511 }
2512
2513 static const int snb_b_fdi_train_param[] = {
2514 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2515 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2516 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2517 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2518 };
2519
2520 /* The FDI link training functions for SNB/Cougarpoint. */
2521 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2522 {
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 int pipe = intel_crtc->pipe;
2527 u32 reg, temp, i;
2528
2529 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2530 for train result */
2531 reg = FDI_RX_IMR(pipe);
2532 temp = I915_READ(reg);
2533 temp &= ~FDI_RX_SYMBOL_LOCK;
2534 temp &= ~FDI_RX_BIT_LOCK;
2535 I915_WRITE(reg, temp);
2536
2537 POSTING_READ(reg);
2538 udelay(150);
2539
2540 /* enable CPU FDI TX and PCH FDI RX */
2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~(7 << 19);
2544 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_1;
2547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2548 /* SNB-B */
2549 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2550 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2551
2552 reg = FDI_RX_CTL(pipe);
2553 temp = I915_READ(reg);
2554 if (HAS_PCH_CPT(dev)) {
2555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2557 } else {
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_1;
2560 }
2561 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2562
2563 POSTING_READ(reg);
2564 udelay(150);
2565
2566 if (HAS_PCH_CPT(dev))
2567 cpt_phase_pointer_enable(dev, pipe);
2568
2569 for (i = 0; i < 4; i++) {
2570 reg = FDI_TX_CTL(pipe);
2571 temp = I915_READ(reg);
2572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2573 temp |= snb_b_fdi_train_param[i];
2574 I915_WRITE(reg, temp);
2575
2576 POSTING_READ(reg);
2577 udelay(500);
2578
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582
2583 if (temp & FDI_RX_BIT_LOCK) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585 DRM_DEBUG_KMS("FDI train 1 done.\n");
2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2;
2597 if (IS_GEN6(dev)) {
2598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2599 /* SNB-B */
2600 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2601 }
2602 I915_WRITE(reg, temp);
2603
2604 reg = FDI_RX_CTL(pipe);
2605 temp = I915_READ(reg);
2606 if (HAS_PCH_CPT(dev)) {
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2609 } else {
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2;
2612 }
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 for (i = 0; i < 4; i++) {
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(500);
2627
2628 reg = FDI_RX_IIR(pipe);
2629 temp = I915_READ(reg);
2630 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2631
2632 if (temp & FDI_RX_SYMBOL_LOCK) {
2633 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2634 DRM_DEBUG_KMS("FDI train 2 done.\n");
2635 break;
2636 }
2637 }
2638 if (i == 4)
2639 DRM_ERROR("FDI train 2 fail!\n");
2640
2641 DRM_DEBUG_KMS("FDI train done.\n");
2642 }
2643
2644 /* Manual link training for Ivy Bridge A0 parts */
2645 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2646 {
2647 struct drm_device *dev = crtc->dev;
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650 int pipe = intel_crtc->pipe;
2651 u32 reg, temp, i;
2652
2653 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2654 for train result */
2655 reg = FDI_RX_IMR(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_RX_SYMBOL_LOCK;
2658 temp &= ~FDI_RX_BIT_LOCK;
2659 I915_WRITE(reg, temp);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
2664 /* enable CPU FDI TX and PCH FDI RX */
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~(7 << 19);
2668 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2669 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2670 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2673 temp |= FDI_COMPOSITE_SYNC;
2674 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2675
2676 reg = FDI_RX_CTL(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_LINK_TRAIN_AUTO;
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2681 temp |= FDI_COMPOSITE_SYNC;
2682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
2687 if (HAS_PCH_CPT(dev))
2688 cpt_phase_pointer_enable(dev, pipe);
2689
2690 for (i = 0; i < 4; i++) {
2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= snb_b_fdi_train_param[i];
2695 I915_WRITE(reg, temp);
2696
2697 POSTING_READ(reg);
2698 udelay(500);
2699
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done.\n");
2708 break;
2709 }
2710 }
2711 if (i == 4)
2712 DRM_ERROR("FDI train 1 fail!\n");
2713
2714 /* Train 2 */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2718 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2721 I915_WRITE(reg, temp);
2722
2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(150);
2731
2732 for (i = 0; i < 4; i++) {
2733 reg = FDI_TX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= snb_b_fdi_train_param[i];
2737 I915_WRITE(reg, temp);
2738
2739 POSTING_READ(reg);
2740 udelay(500);
2741
2742 reg = FDI_RX_IIR(pipe);
2743 temp = I915_READ(reg);
2744 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2745
2746 if (temp & FDI_RX_SYMBOL_LOCK) {
2747 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2748 DRM_DEBUG_KMS("FDI train 2 done.\n");
2749 break;
2750 }
2751 }
2752 if (i == 4)
2753 DRM_ERROR("FDI train 2 fail!\n");
2754
2755 DRM_DEBUG_KMS("FDI train done.\n");
2756 }
2757
2758 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2759 {
2760 struct drm_device *dev = crtc->dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763 int pipe = intel_crtc->pipe;
2764 u32 reg, temp;
2765
2766 /* Write the TU size bits so error detection works */
2767 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2768 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2769
2770 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2771 reg = FDI_RX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~((0x7 << 19) | (0x7 << 16));
2774 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2775 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2776 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2777
2778 POSTING_READ(reg);
2779 udelay(200);
2780
2781 /* Switch from Rawclk to PCDclk */
2782 temp = I915_READ(reg);
2783 I915_WRITE(reg, temp | FDI_PCDCLK);
2784
2785 POSTING_READ(reg);
2786 udelay(200);
2787
2788 /* Enable CPU FDI TX PLL, always on for Ironlake */
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2792 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2793
2794 POSTING_READ(reg);
2795 udelay(100);
2796 }
2797 }
2798
2799 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2800 {
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 u32 flags = I915_READ(SOUTH_CHICKEN1);
2803
2804 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2805 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2806 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2807 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2808 POSTING_READ(SOUTH_CHICKEN1);
2809 }
2810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2811 {
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 int pipe = intel_crtc->pipe;
2816 u32 reg, temp;
2817
2818 /* disable CPU FDI tx and PCH FDI rx */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2822 POSTING_READ(reg);
2823
2824 reg = FDI_RX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~(0x7 << 16);
2827 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2829
2830 POSTING_READ(reg);
2831 udelay(100);
2832
2833 /* Ironlake workaround, disable clock pointer after downing FDI */
2834 if (HAS_PCH_IBX(dev)) {
2835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2836 I915_WRITE(FDI_RX_CHICKEN(pipe),
2837 I915_READ(FDI_RX_CHICKEN(pipe) &
2838 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2839 } else if (HAS_PCH_CPT(dev)) {
2840 cpt_phase_pointer_disable(dev, pipe);
2841 }
2842
2843 /* still set train pattern 1 */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 I915_WRITE(reg, temp);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if (HAS_PCH_CPT(dev)) {
2853 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 } else {
2856 temp &= ~FDI_LINK_TRAIN_NONE;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 }
2859 /* BPC in FDI rx is consistent with that in PIPECONF */
2860 temp &= ~(0x07 << 16);
2861 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2862 I915_WRITE(reg, temp);
2863
2864 POSTING_READ(reg);
2865 udelay(100);
2866 }
2867
2868 /*
2869 * When we disable a pipe, we need to clear any pending scanline wait events
2870 * to avoid hanging the ring, which we assume we are waiting on.
2871 */
2872 static void intel_clear_scanline_wait(struct drm_device *dev)
2873 {
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 struct intel_ring_buffer *ring;
2876 u32 tmp;
2877
2878 if (IS_GEN2(dev))
2879 /* Can't break the hang on i8xx */
2880 return;
2881
2882 ring = LP_RING(dev_priv);
2883 tmp = I915_READ_CTL(ring);
2884 if (tmp & RING_WAIT)
2885 I915_WRITE_CTL(ring, tmp);
2886 }
2887
2888 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2889 {
2890 struct drm_i915_gem_object *obj;
2891 struct drm_i915_private *dev_priv;
2892
2893 if (crtc->fb == NULL)
2894 return;
2895
2896 obj = to_intel_framebuffer(crtc->fb)->obj;
2897 dev_priv = crtc->dev->dev_private;
2898 wait_event(dev_priv->pending_flip_queue,
2899 atomic_read(&obj->pending_flip) == 0);
2900 }
2901
2902 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2903 {
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_mode_config *mode_config = &dev->mode_config;
2906 struct intel_encoder *encoder;
2907
2908 /*
2909 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2910 * must be driven by its own crtc; no sharing is possible.
2911 */
2912 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2913 if (encoder->base.crtc != crtc)
2914 continue;
2915
2916 switch (encoder->type) {
2917 case INTEL_OUTPUT_EDP:
2918 if (!intel_encoder_is_pch_edp(&encoder->base))
2919 return false;
2920 continue;
2921 }
2922 }
2923
2924 return true;
2925 }
2926
2927 /*
2928 * Enable PCH resources required for PCH ports:
2929 * - PCH PLLs
2930 * - FDI training & RX/TX
2931 * - update transcoder timings
2932 * - DP transcoding bits
2933 * - transcoder
2934 */
2935 static void ironlake_pch_enable(struct drm_crtc *crtc)
2936 {
2937 struct drm_device *dev = crtc->dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2940 int pipe = intel_crtc->pipe;
2941 u32 reg, temp, transc_sel;
2942
2943 /* For PCH output, training FDI link */
2944 dev_priv->display.fdi_link_train(crtc);
2945
2946 intel_enable_pch_pll(dev_priv, pipe);
2947
2948 if (HAS_PCH_CPT(dev)) {
2949 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2950 TRANSC_DPLLB_SEL;
2951
2952 /* Be sure PCH DPLL SEL is set */
2953 temp = I915_READ(PCH_DPLL_SEL);
2954 if (pipe == 0) {
2955 temp &= ~(TRANSA_DPLLB_SEL);
2956 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2957 } else if (pipe == 1) {
2958 temp &= ~(TRANSB_DPLLB_SEL);
2959 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2960 } else if (pipe == 2) {
2961 temp &= ~(TRANSC_DPLLB_SEL);
2962 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2963 }
2964 I915_WRITE(PCH_DPLL_SEL, temp);
2965 }
2966
2967 /* set transcoder timing, panel must allow it */
2968 assert_panel_unlocked(dev_priv, pipe);
2969 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2970 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2971 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2972
2973 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2974 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2975 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2976
2977 intel_fdi_normal_train(crtc);
2978
2979 /* For PCH DP, enable TRANS_DP_CTL */
2980 if (HAS_PCH_CPT(dev) &&
2981 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2982 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2983 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2984 reg = TRANS_DP_CTL(pipe);
2985 temp = I915_READ(reg);
2986 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2987 TRANS_DP_SYNC_MASK |
2988 TRANS_DP_BPC_MASK);
2989 temp |= (TRANS_DP_OUTPUT_ENABLE |
2990 TRANS_DP_ENH_FRAMING);
2991 temp |= bpc << 9; /* same format but at 11:9 */
2992
2993 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2994 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2995 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2996 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2997
2998 switch (intel_trans_dp_port_sel(crtc)) {
2999 case PCH_DP_B:
3000 temp |= TRANS_DP_PORT_SEL_B;
3001 break;
3002 case PCH_DP_C:
3003 temp |= TRANS_DP_PORT_SEL_C;
3004 break;
3005 case PCH_DP_D:
3006 temp |= TRANS_DP_PORT_SEL_D;
3007 break;
3008 default:
3009 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3010 temp |= TRANS_DP_PORT_SEL_B;
3011 break;
3012 }
3013
3014 I915_WRITE(reg, temp);
3015 }
3016
3017 intel_enable_transcoder(dev_priv, pipe);
3018 }
3019
3020 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3021 {
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3024 u32 temp;
3025
3026 temp = I915_READ(dslreg);
3027 udelay(500);
3028 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3029 /* Without this, mode sets may fail silently on FDI */
3030 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3031 udelay(250);
3032 I915_WRITE(tc2reg, 0);
3033 if (wait_for(I915_READ(dslreg) != temp, 5))
3034 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3035 }
3036 }
3037
3038 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3039 {
3040 struct drm_device *dev = crtc->dev;
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043 int pipe = intel_crtc->pipe;
3044 int plane = intel_crtc->plane;
3045 u32 temp;
3046 bool is_pch_port;
3047
3048 if (intel_crtc->active)
3049 return;
3050
3051 intel_crtc->active = true;
3052 intel_update_watermarks(dev);
3053
3054 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3055 temp = I915_READ(PCH_LVDS);
3056 if ((temp & LVDS_PORT_EN) == 0)
3057 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3058 }
3059
3060 is_pch_port = intel_crtc_driving_pch(crtc);
3061
3062 if (is_pch_port)
3063 ironlake_fdi_pll_enable(crtc);
3064 else
3065 ironlake_fdi_disable(crtc);
3066
3067 /* Enable panel fitting for LVDS */
3068 if (dev_priv->pch_pf_size &&
3069 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3070 /* Force use of hard-coded filter coefficients
3071 * as some pre-programmed values are broken,
3072 * e.g. x201.
3073 */
3074 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3075 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3076 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3077 }
3078
3079 /*
3080 * On ILK+ LUT must be loaded before the pipe is running but with
3081 * clocks enabled
3082 */
3083 intel_crtc_load_lut(crtc);
3084
3085 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3086 intel_enable_plane(dev_priv, plane, pipe);
3087
3088 if (is_pch_port)
3089 ironlake_pch_enable(crtc);
3090
3091 mutex_lock(&dev->struct_mutex);
3092 intel_update_fbc(dev);
3093 mutex_unlock(&dev->struct_mutex);
3094
3095 intel_crtc_update_cursor(crtc, true);
3096 }
3097
3098 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3099 {
3100 struct drm_device *dev = crtc->dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3103 int pipe = intel_crtc->pipe;
3104 int plane = intel_crtc->plane;
3105 u32 reg, temp;
3106
3107 if (!intel_crtc->active)
3108 return;
3109
3110 intel_crtc_wait_for_pending_flips(crtc);
3111 drm_vblank_off(dev, pipe);
3112 intel_crtc_update_cursor(crtc, false);
3113
3114 intel_disable_plane(dev_priv, plane, pipe);
3115
3116 if (dev_priv->cfb_plane == plane)
3117 intel_disable_fbc(dev);
3118
3119 intel_disable_pipe(dev_priv, pipe);
3120
3121 /* Disable PF */
3122 I915_WRITE(PF_CTL(pipe), 0);
3123 I915_WRITE(PF_WIN_SZ(pipe), 0);
3124
3125 ironlake_fdi_disable(crtc);
3126
3127 /* This is a horrible layering violation; we should be doing this in
3128 * the connector/encoder ->prepare instead, but we don't always have
3129 * enough information there about the config to know whether it will
3130 * actually be necessary or just cause undesired flicker.
3131 */
3132 intel_disable_pch_ports(dev_priv, pipe);
3133
3134 intel_disable_transcoder(dev_priv, pipe);
3135
3136 if (HAS_PCH_CPT(dev)) {
3137 /* disable TRANS_DP_CTL */
3138 reg = TRANS_DP_CTL(pipe);
3139 temp = I915_READ(reg);
3140 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3141 temp |= TRANS_DP_PORT_SEL_NONE;
3142 I915_WRITE(reg, temp);
3143
3144 /* disable DPLL_SEL */
3145 temp = I915_READ(PCH_DPLL_SEL);
3146 switch (pipe) {
3147 case 0:
3148 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3149 break;
3150 case 1:
3151 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3152 break;
3153 case 2:
3154 /* C shares PLL A or B */
3155 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3156 break;
3157 default:
3158 BUG(); /* wtf */
3159 }
3160 I915_WRITE(PCH_DPLL_SEL, temp);
3161 }
3162
3163 /* disable PCH DPLL */
3164 if (!intel_crtc->no_pll)
3165 intel_disable_pch_pll(dev_priv, pipe);
3166
3167 /* Switch from PCDclk to Rawclk */
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3171
3172 /* Disable CPU FDI TX PLL */
3173 reg = FDI_TX_CTL(pipe);
3174 temp = I915_READ(reg);
3175 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3176
3177 POSTING_READ(reg);
3178 udelay(100);
3179
3180 reg = FDI_RX_CTL(pipe);
3181 temp = I915_READ(reg);
3182 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3183
3184 /* Wait for the clocks to turn off. */
3185 POSTING_READ(reg);
3186 udelay(100);
3187
3188 intel_crtc->active = false;
3189 intel_update_watermarks(dev);
3190
3191 mutex_lock(&dev->struct_mutex);
3192 intel_update_fbc(dev);
3193 intel_clear_scanline_wait(dev);
3194 mutex_unlock(&dev->struct_mutex);
3195 }
3196
3197 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3198 {
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 int pipe = intel_crtc->pipe;
3201 int plane = intel_crtc->plane;
3202
3203 /* XXX: When our outputs are all unaware of DPMS modes other than off
3204 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3205 */
3206 switch (mode) {
3207 case DRM_MODE_DPMS_ON:
3208 case DRM_MODE_DPMS_STANDBY:
3209 case DRM_MODE_DPMS_SUSPEND:
3210 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3211 ironlake_crtc_enable(crtc);
3212 break;
3213
3214 case DRM_MODE_DPMS_OFF:
3215 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3216 ironlake_crtc_disable(crtc);
3217 break;
3218 }
3219 }
3220
3221 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3222 {
3223 if (!enable && intel_crtc->overlay) {
3224 struct drm_device *dev = intel_crtc->base.dev;
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226
3227 mutex_lock(&dev->struct_mutex);
3228 dev_priv->mm.interruptible = false;
3229 (void) intel_overlay_switch_off(intel_crtc->overlay);
3230 dev_priv->mm.interruptible = true;
3231 mutex_unlock(&dev->struct_mutex);
3232 }
3233
3234 /* Let userspace switch the overlay on again. In most cases userspace
3235 * has to recompute where to put it anyway.
3236 */
3237 }
3238
3239 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3240 {
3241 struct drm_device *dev = crtc->dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244 int pipe = intel_crtc->pipe;
3245 int plane = intel_crtc->plane;
3246
3247 if (intel_crtc->active)
3248 return;
3249
3250 intel_crtc->active = true;
3251 intel_update_watermarks(dev);
3252
3253 intel_enable_pll(dev_priv, pipe);
3254 intel_enable_pipe(dev_priv, pipe, false);
3255 intel_enable_plane(dev_priv, plane, pipe);
3256
3257 intel_crtc_load_lut(crtc);
3258 intel_update_fbc(dev);
3259
3260 /* Give the overlay scaler a chance to enable if it's on this pipe */
3261 intel_crtc_dpms_overlay(intel_crtc, true);
3262 intel_crtc_update_cursor(crtc, true);
3263 }
3264
3265 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3266 {
3267 struct drm_device *dev = crtc->dev;
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270 int pipe = intel_crtc->pipe;
3271 int plane = intel_crtc->plane;
3272
3273 if (!intel_crtc->active)
3274 return;
3275
3276 /* Give the overlay scaler a chance to disable if it's on this pipe */
3277 intel_crtc_wait_for_pending_flips(crtc);
3278 drm_vblank_off(dev, pipe);
3279 intel_crtc_dpms_overlay(intel_crtc, false);
3280 intel_crtc_update_cursor(crtc, false);
3281
3282 if (dev_priv->cfb_plane == plane)
3283 intel_disable_fbc(dev);
3284
3285 intel_disable_plane(dev_priv, plane, pipe);
3286 intel_disable_pipe(dev_priv, pipe);
3287 intel_disable_pll(dev_priv, pipe);
3288
3289 intel_crtc->active = false;
3290 intel_update_fbc(dev);
3291 intel_update_watermarks(dev);
3292 intel_clear_scanline_wait(dev);
3293 }
3294
3295 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3296 {
3297 /* XXX: When our outputs are all unaware of DPMS modes other than off
3298 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3299 */
3300 switch (mode) {
3301 case DRM_MODE_DPMS_ON:
3302 case DRM_MODE_DPMS_STANDBY:
3303 case DRM_MODE_DPMS_SUSPEND:
3304 i9xx_crtc_enable(crtc);
3305 break;
3306 case DRM_MODE_DPMS_OFF:
3307 i9xx_crtc_disable(crtc);
3308 break;
3309 }
3310 }
3311
3312 /**
3313 * Sets the power management mode of the pipe and plane.
3314 */
3315 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct drm_i915_master_private *master_priv;
3320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3321 int pipe = intel_crtc->pipe;
3322 bool enabled;
3323
3324 if (intel_crtc->dpms_mode == mode)
3325 return;
3326
3327 intel_crtc->dpms_mode = mode;
3328
3329 dev_priv->display.dpms(crtc, mode);
3330
3331 if (!dev->primary->master)
3332 return;
3333
3334 master_priv = dev->primary->master->driver_priv;
3335 if (!master_priv->sarea_priv)
3336 return;
3337
3338 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3339
3340 switch (pipe) {
3341 case 0:
3342 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3343 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3344 break;
3345 case 1:
3346 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3347 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3348 break;
3349 default:
3350 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3351 break;
3352 }
3353 }
3354
3355 static void intel_crtc_disable(struct drm_crtc *crtc)
3356 {
3357 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3358 struct drm_device *dev = crtc->dev;
3359
3360 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3361 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3362 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3363
3364 if (crtc->fb) {
3365 mutex_lock(&dev->struct_mutex);
3366 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3367 mutex_unlock(&dev->struct_mutex);
3368 }
3369 }
3370
3371 /* Prepare for a mode set.
3372 *
3373 * Note we could be a lot smarter here. We need to figure out which outputs
3374 * will be enabled, which disabled (in short, how the config will changes)
3375 * and perform the minimum necessary steps to accomplish that, e.g. updating
3376 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3377 * panel fitting is in the proper state, etc.
3378 */
3379 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3380 {
3381 i9xx_crtc_disable(crtc);
3382 }
3383
3384 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3385 {
3386 i9xx_crtc_enable(crtc);
3387 }
3388
3389 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3390 {
3391 ironlake_crtc_disable(crtc);
3392 }
3393
3394 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3395 {
3396 ironlake_crtc_enable(crtc);
3397 }
3398
3399 void intel_encoder_prepare(struct drm_encoder *encoder)
3400 {
3401 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3402 /* lvds has its own version of prepare see intel_lvds_prepare */
3403 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3404 }
3405
3406 void intel_encoder_commit(struct drm_encoder *encoder)
3407 {
3408 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3409 struct drm_device *dev = encoder->dev;
3410 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3411 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3412
3413 /* lvds has its own version of commit see intel_lvds_commit */
3414 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3415
3416 if (HAS_PCH_CPT(dev))
3417 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3418 }
3419
3420 void intel_encoder_destroy(struct drm_encoder *encoder)
3421 {
3422 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3423
3424 drm_encoder_cleanup(encoder);
3425 kfree(intel_encoder);
3426 }
3427
3428 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3429 struct drm_display_mode *mode,
3430 struct drm_display_mode *adjusted_mode)
3431 {
3432 struct drm_device *dev = crtc->dev;
3433
3434 if (HAS_PCH_SPLIT(dev)) {
3435 /* FDI link clock is fixed at 2.7G */
3436 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3437 return false;
3438 }
3439
3440 /* All interlaced capable intel hw wants timings in frames. */
3441 drm_mode_set_crtcinfo(adjusted_mode, 0);
3442
3443 return true;
3444 }
3445
3446 static int i945_get_display_clock_speed(struct drm_device *dev)
3447 {
3448 return 400000;
3449 }
3450
3451 static int i915_get_display_clock_speed(struct drm_device *dev)
3452 {
3453 return 333000;
3454 }
3455
3456 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3457 {
3458 return 200000;
3459 }
3460
3461 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3462 {
3463 u16 gcfgc = 0;
3464
3465 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3466
3467 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3468 return 133000;
3469 else {
3470 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3471 case GC_DISPLAY_CLOCK_333_MHZ:
3472 return 333000;
3473 default:
3474 case GC_DISPLAY_CLOCK_190_200_MHZ:
3475 return 190000;
3476 }
3477 }
3478 }
3479
3480 static int i865_get_display_clock_speed(struct drm_device *dev)
3481 {
3482 return 266000;
3483 }
3484
3485 static int i855_get_display_clock_speed(struct drm_device *dev)
3486 {
3487 u16 hpllcc = 0;
3488 /* Assume that the hardware is in the high speed state. This
3489 * should be the default.
3490 */
3491 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3492 case GC_CLOCK_133_200:
3493 case GC_CLOCK_100_200:
3494 return 200000;
3495 case GC_CLOCK_166_250:
3496 return 250000;
3497 case GC_CLOCK_100_133:
3498 return 133000;
3499 }
3500
3501 /* Shouldn't happen */
3502 return 0;
3503 }
3504
3505 static int i830_get_display_clock_speed(struct drm_device *dev)
3506 {
3507 return 133000;
3508 }
3509
3510 struct fdi_m_n {
3511 u32 tu;
3512 u32 gmch_m;
3513 u32 gmch_n;
3514 u32 link_m;
3515 u32 link_n;
3516 };
3517
3518 static void
3519 fdi_reduce_ratio(u32 *num, u32 *den)
3520 {
3521 while (*num > 0xffffff || *den > 0xffffff) {
3522 *num >>= 1;
3523 *den >>= 1;
3524 }
3525 }
3526
3527 static void
3528 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3529 int link_clock, struct fdi_m_n *m_n)
3530 {
3531 m_n->tu = 64; /* default size */
3532
3533 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3534 m_n->gmch_m = bits_per_pixel * pixel_clock;
3535 m_n->gmch_n = link_clock * nlanes * 8;
3536 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3537
3538 m_n->link_m = pixel_clock;
3539 m_n->link_n = link_clock;
3540 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3541 }
3542
3543
3544 struct intel_watermark_params {
3545 unsigned long fifo_size;
3546 unsigned long max_wm;
3547 unsigned long default_wm;
3548 unsigned long guard_size;
3549 unsigned long cacheline_size;
3550 };
3551
3552 /* Pineview has different values for various configs */
3553 static const struct intel_watermark_params pineview_display_wm = {
3554 PINEVIEW_DISPLAY_FIFO,
3555 PINEVIEW_MAX_WM,
3556 PINEVIEW_DFT_WM,
3557 PINEVIEW_GUARD_WM,
3558 PINEVIEW_FIFO_LINE_SIZE
3559 };
3560 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3561 PINEVIEW_DISPLAY_FIFO,
3562 PINEVIEW_MAX_WM,
3563 PINEVIEW_DFT_HPLLOFF_WM,
3564 PINEVIEW_GUARD_WM,
3565 PINEVIEW_FIFO_LINE_SIZE
3566 };
3567 static const struct intel_watermark_params pineview_cursor_wm = {
3568 PINEVIEW_CURSOR_FIFO,
3569 PINEVIEW_CURSOR_MAX_WM,
3570 PINEVIEW_CURSOR_DFT_WM,
3571 PINEVIEW_CURSOR_GUARD_WM,
3572 PINEVIEW_FIFO_LINE_SIZE,
3573 };
3574 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3575 PINEVIEW_CURSOR_FIFO,
3576 PINEVIEW_CURSOR_MAX_WM,
3577 PINEVIEW_CURSOR_DFT_WM,
3578 PINEVIEW_CURSOR_GUARD_WM,
3579 PINEVIEW_FIFO_LINE_SIZE
3580 };
3581 static const struct intel_watermark_params g4x_wm_info = {
3582 G4X_FIFO_SIZE,
3583 G4X_MAX_WM,
3584 G4X_MAX_WM,
3585 2,
3586 G4X_FIFO_LINE_SIZE,
3587 };
3588 static const struct intel_watermark_params g4x_cursor_wm_info = {
3589 I965_CURSOR_FIFO,
3590 I965_CURSOR_MAX_WM,
3591 I965_CURSOR_DFT_WM,
3592 2,
3593 G4X_FIFO_LINE_SIZE,
3594 };
3595 static const struct intel_watermark_params i965_cursor_wm_info = {
3596 I965_CURSOR_FIFO,
3597 I965_CURSOR_MAX_WM,
3598 I965_CURSOR_DFT_WM,
3599 2,
3600 I915_FIFO_LINE_SIZE,
3601 };
3602 static const struct intel_watermark_params i945_wm_info = {
3603 I945_FIFO_SIZE,
3604 I915_MAX_WM,
3605 1,
3606 2,
3607 I915_FIFO_LINE_SIZE
3608 };
3609 static const struct intel_watermark_params i915_wm_info = {
3610 I915_FIFO_SIZE,
3611 I915_MAX_WM,
3612 1,
3613 2,
3614 I915_FIFO_LINE_SIZE
3615 };
3616 static const struct intel_watermark_params i855_wm_info = {
3617 I855GM_FIFO_SIZE,
3618 I915_MAX_WM,
3619 1,
3620 2,
3621 I830_FIFO_LINE_SIZE
3622 };
3623 static const struct intel_watermark_params i830_wm_info = {
3624 I830_FIFO_SIZE,
3625 I915_MAX_WM,
3626 1,
3627 2,
3628 I830_FIFO_LINE_SIZE
3629 };
3630
3631 static const struct intel_watermark_params ironlake_display_wm_info = {
3632 ILK_DISPLAY_FIFO,
3633 ILK_DISPLAY_MAXWM,
3634 ILK_DISPLAY_DFTWM,
3635 2,
3636 ILK_FIFO_LINE_SIZE
3637 };
3638 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3639 ILK_CURSOR_FIFO,
3640 ILK_CURSOR_MAXWM,
3641 ILK_CURSOR_DFTWM,
3642 2,
3643 ILK_FIFO_LINE_SIZE
3644 };
3645 static const struct intel_watermark_params ironlake_display_srwm_info = {
3646 ILK_DISPLAY_SR_FIFO,
3647 ILK_DISPLAY_MAX_SRWM,
3648 ILK_DISPLAY_DFT_SRWM,
3649 2,
3650 ILK_FIFO_LINE_SIZE
3651 };
3652 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3653 ILK_CURSOR_SR_FIFO,
3654 ILK_CURSOR_MAX_SRWM,
3655 ILK_CURSOR_DFT_SRWM,
3656 2,
3657 ILK_FIFO_LINE_SIZE
3658 };
3659
3660 static const struct intel_watermark_params sandybridge_display_wm_info = {
3661 SNB_DISPLAY_FIFO,
3662 SNB_DISPLAY_MAXWM,
3663 SNB_DISPLAY_DFTWM,
3664 2,
3665 SNB_FIFO_LINE_SIZE
3666 };
3667 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3668 SNB_CURSOR_FIFO,
3669 SNB_CURSOR_MAXWM,
3670 SNB_CURSOR_DFTWM,
3671 2,
3672 SNB_FIFO_LINE_SIZE
3673 };
3674 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3675 SNB_DISPLAY_SR_FIFO,
3676 SNB_DISPLAY_MAX_SRWM,
3677 SNB_DISPLAY_DFT_SRWM,
3678 2,
3679 SNB_FIFO_LINE_SIZE
3680 };
3681 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3682 SNB_CURSOR_SR_FIFO,
3683 SNB_CURSOR_MAX_SRWM,
3684 SNB_CURSOR_DFT_SRWM,
3685 2,
3686 SNB_FIFO_LINE_SIZE
3687 };
3688
3689
3690 /**
3691 * intel_calculate_wm - calculate watermark level
3692 * @clock_in_khz: pixel clock
3693 * @wm: chip FIFO params
3694 * @pixel_size: display pixel size
3695 * @latency_ns: memory latency for the platform
3696 *
3697 * Calculate the watermark level (the level at which the display plane will
3698 * start fetching from memory again). Each chip has a different display
3699 * FIFO size and allocation, so the caller needs to figure that out and pass
3700 * in the correct intel_watermark_params structure.
3701 *
3702 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3703 * on the pixel size. When it reaches the watermark level, it'll start
3704 * fetching FIFO line sized based chunks from memory until the FIFO fills
3705 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3706 * will occur, and a display engine hang could result.
3707 */
3708 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3709 const struct intel_watermark_params *wm,
3710 int fifo_size,
3711 int pixel_size,
3712 unsigned long latency_ns)
3713 {
3714 long entries_required, wm_size;
3715
3716 /*
3717 * Note: we need to make sure we don't overflow for various clock &
3718 * latency values.
3719 * clocks go from a few thousand to several hundred thousand.
3720 * latency is usually a few thousand
3721 */
3722 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3723 1000;
3724 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3725
3726 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3727
3728 wm_size = fifo_size - (entries_required + wm->guard_size);
3729
3730 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3731
3732 /* Don't promote wm_size to unsigned... */
3733 if (wm_size > (long)wm->max_wm)
3734 wm_size = wm->max_wm;
3735 if (wm_size <= 0)
3736 wm_size = wm->default_wm;
3737 return wm_size;
3738 }
3739
3740 struct cxsr_latency {
3741 int is_desktop;
3742 int is_ddr3;
3743 unsigned long fsb_freq;
3744 unsigned long mem_freq;
3745 unsigned long display_sr;
3746 unsigned long display_hpll_disable;
3747 unsigned long cursor_sr;
3748 unsigned long cursor_hpll_disable;
3749 };
3750
3751 static const struct cxsr_latency cxsr_latency_table[] = {
3752 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3753 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3754 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3755 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3756 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3757
3758 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3759 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3760 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3761 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3762 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3763
3764 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3765 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3766 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3767 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3768 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3769
3770 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3771 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3772 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3773 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3774 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3775
3776 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3777 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3778 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3779 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3780 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3781
3782 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3783 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3784 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3785 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3786 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3787 };
3788
3789 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3790 int is_ddr3,
3791 int fsb,
3792 int mem)
3793 {
3794 const struct cxsr_latency *latency;
3795 int i;
3796
3797 if (fsb == 0 || mem == 0)
3798 return NULL;
3799
3800 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3801 latency = &cxsr_latency_table[i];
3802 if (is_desktop == latency->is_desktop &&
3803 is_ddr3 == latency->is_ddr3 &&
3804 fsb == latency->fsb_freq && mem == latency->mem_freq)
3805 return latency;
3806 }
3807
3808 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3809
3810 return NULL;
3811 }
3812
3813 static void pineview_disable_cxsr(struct drm_device *dev)
3814 {
3815 struct drm_i915_private *dev_priv = dev->dev_private;
3816
3817 /* deactivate cxsr */
3818 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3819 }
3820
3821 /*
3822 * Latency for FIFO fetches is dependent on several factors:
3823 * - memory configuration (speed, channels)
3824 * - chipset
3825 * - current MCH state
3826 * It can be fairly high in some situations, so here we assume a fairly
3827 * pessimal value. It's a tradeoff between extra memory fetches (if we
3828 * set this value too high, the FIFO will fetch frequently to stay full)
3829 * and power consumption (set it too low to save power and we might see
3830 * FIFO underruns and display "flicker").
3831 *
3832 * A value of 5us seems to be a good balance; safe for very low end
3833 * platforms but not overly aggressive on lower latency configs.
3834 */
3835 static const int latency_ns = 5000;
3836
3837 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3838 {
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 uint32_t dsparb = I915_READ(DSPARB);
3841 int size;
3842
3843 size = dsparb & 0x7f;
3844 if (plane)
3845 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3846
3847 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3848 plane ? "B" : "A", size);
3849
3850 return size;
3851 }
3852
3853 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3854 {
3855 struct drm_i915_private *dev_priv = dev->dev_private;
3856 uint32_t dsparb = I915_READ(DSPARB);
3857 int size;
3858
3859 size = dsparb & 0x1ff;
3860 if (plane)
3861 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3862 size >>= 1; /* Convert to cachelines */
3863
3864 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3865 plane ? "B" : "A", size);
3866
3867 return size;
3868 }
3869
3870 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3871 {
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873 uint32_t dsparb = I915_READ(DSPARB);
3874 int size;
3875
3876 size = dsparb & 0x7f;
3877 size >>= 2; /* Convert to cachelines */
3878
3879 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3880 plane ? "B" : "A",
3881 size);
3882
3883 return size;
3884 }
3885
3886 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3887 {
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 uint32_t dsparb = I915_READ(DSPARB);
3890 int size;
3891
3892 size = dsparb & 0x7f;
3893 size >>= 1; /* Convert to cachelines */
3894
3895 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3896 plane ? "B" : "A", size);
3897
3898 return size;
3899 }
3900
3901 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3902 {
3903 struct drm_crtc *crtc, *enabled = NULL;
3904
3905 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3906 if (crtc->enabled && crtc->fb) {
3907 if (enabled)
3908 return NULL;
3909 enabled = crtc;
3910 }
3911 }
3912
3913 return enabled;
3914 }
3915
3916 static void pineview_update_wm(struct drm_device *dev)
3917 {
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919 struct drm_crtc *crtc;
3920 const struct cxsr_latency *latency;
3921 u32 reg;
3922 unsigned long wm;
3923
3924 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3925 dev_priv->fsb_freq, dev_priv->mem_freq);
3926 if (!latency) {
3927 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3928 pineview_disable_cxsr(dev);
3929 return;
3930 }
3931
3932 crtc = single_enabled_crtc(dev);
3933 if (crtc) {
3934 int clock = crtc->mode.clock;
3935 int pixel_size = crtc->fb->bits_per_pixel / 8;
3936
3937 /* Display SR */
3938 wm = intel_calculate_wm(clock, &pineview_display_wm,
3939 pineview_display_wm.fifo_size,
3940 pixel_size, latency->display_sr);
3941 reg = I915_READ(DSPFW1);
3942 reg &= ~DSPFW_SR_MASK;
3943 reg |= wm << DSPFW_SR_SHIFT;
3944 I915_WRITE(DSPFW1, reg);
3945 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3946
3947 /* cursor SR */
3948 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3949 pineview_display_wm.fifo_size,
3950 pixel_size, latency->cursor_sr);
3951 reg = I915_READ(DSPFW3);
3952 reg &= ~DSPFW_CURSOR_SR_MASK;
3953 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3954 I915_WRITE(DSPFW3, reg);
3955
3956 /* Display HPLL off SR */
3957 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3958 pineview_display_hplloff_wm.fifo_size,
3959 pixel_size, latency->display_hpll_disable);
3960 reg = I915_READ(DSPFW3);
3961 reg &= ~DSPFW_HPLL_SR_MASK;
3962 reg |= wm & DSPFW_HPLL_SR_MASK;
3963 I915_WRITE(DSPFW3, reg);
3964
3965 /* cursor HPLL off SR */
3966 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3967 pineview_display_hplloff_wm.fifo_size,
3968 pixel_size, latency->cursor_hpll_disable);
3969 reg = I915_READ(DSPFW3);
3970 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3971 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3972 I915_WRITE(DSPFW3, reg);
3973 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3974
3975 /* activate cxsr */
3976 I915_WRITE(DSPFW3,
3977 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3978 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3979 } else {
3980 pineview_disable_cxsr(dev);
3981 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3982 }
3983 }
3984
3985 static bool g4x_compute_wm0(struct drm_device *dev,
3986 int plane,
3987 const struct intel_watermark_params *display,
3988 int display_latency_ns,
3989 const struct intel_watermark_params *cursor,
3990 int cursor_latency_ns,
3991 int *plane_wm,
3992 int *cursor_wm)
3993 {
3994 struct drm_crtc *crtc;
3995 int htotal, hdisplay, clock, pixel_size;
3996 int line_time_us, line_count;
3997 int entries, tlb_miss;
3998
3999 crtc = intel_get_crtc_for_plane(dev, plane);
4000 if (crtc->fb == NULL || !crtc->enabled) {
4001 *cursor_wm = cursor->guard_size;
4002 *plane_wm = display->guard_size;
4003 return false;
4004 }
4005
4006 htotal = crtc->mode.htotal;
4007 hdisplay = crtc->mode.hdisplay;
4008 clock = crtc->mode.clock;
4009 pixel_size = crtc->fb->bits_per_pixel / 8;
4010
4011 /* Use the small buffer method to calculate plane watermark */
4012 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4013 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4014 if (tlb_miss > 0)
4015 entries += tlb_miss;
4016 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4017 *plane_wm = entries + display->guard_size;
4018 if (*plane_wm > (int)display->max_wm)
4019 *plane_wm = display->max_wm;
4020
4021 /* Use the large buffer method to calculate cursor watermark */
4022 line_time_us = ((htotal * 1000) / clock);
4023 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4024 entries = line_count * 64 * pixel_size;
4025 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4026 if (tlb_miss > 0)
4027 entries += tlb_miss;
4028 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4029 *cursor_wm = entries + cursor->guard_size;
4030 if (*cursor_wm > (int)cursor->max_wm)
4031 *cursor_wm = (int)cursor->max_wm;
4032
4033 return true;
4034 }
4035
4036 /*
4037 * Check the wm result.
4038 *
4039 * If any calculated watermark values is larger than the maximum value that
4040 * can be programmed into the associated watermark register, that watermark
4041 * must be disabled.
4042 */
4043 static bool g4x_check_srwm(struct drm_device *dev,
4044 int display_wm, int cursor_wm,
4045 const struct intel_watermark_params *display,
4046 const struct intel_watermark_params *cursor)
4047 {
4048 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4049 display_wm, cursor_wm);
4050
4051 if (display_wm > display->max_wm) {
4052 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4053 display_wm, display->max_wm);
4054 return false;
4055 }
4056
4057 if (cursor_wm > cursor->max_wm) {
4058 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4059 cursor_wm, cursor->max_wm);
4060 return false;
4061 }
4062
4063 if (!(display_wm || cursor_wm)) {
4064 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4065 return false;
4066 }
4067
4068 return true;
4069 }
4070
4071 static bool g4x_compute_srwm(struct drm_device *dev,
4072 int plane,
4073 int latency_ns,
4074 const struct intel_watermark_params *display,
4075 const struct intel_watermark_params *cursor,
4076 int *display_wm, int *cursor_wm)
4077 {
4078 struct drm_crtc *crtc;
4079 int hdisplay, htotal, pixel_size, clock;
4080 unsigned long line_time_us;
4081 int line_count, line_size;
4082 int small, large;
4083 int entries;
4084
4085 if (!latency_ns) {
4086 *display_wm = *cursor_wm = 0;
4087 return false;
4088 }
4089
4090 crtc = intel_get_crtc_for_plane(dev, plane);
4091 hdisplay = crtc->mode.hdisplay;
4092 htotal = crtc->mode.htotal;
4093 clock = crtc->mode.clock;
4094 pixel_size = crtc->fb->bits_per_pixel / 8;
4095
4096 line_time_us = (htotal * 1000) / clock;
4097 line_count = (latency_ns / line_time_us + 1000) / 1000;
4098 line_size = hdisplay * pixel_size;
4099
4100 /* Use the minimum of the small and large buffer method for primary */
4101 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4102 large = line_count * line_size;
4103
4104 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4105 *display_wm = entries + display->guard_size;
4106
4107 /* calculate the self-refresh watermark for display cursor */
4108 entries = line_count * pixel_size * 64;
4109 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4110 *cursor_wm = entries + cursor->guard_size;
4111
4112 return g4x_check_srwm(dev,
4113 *display_wm, *cursor_wm,
4114 display, cursor);
4115 }
4116
4117 #define single_plane_enabled(mask) is_power_of_2(mask)
4118
4119 static void g4x_update_wm(struct drm_device *dev)
4120 {
4121 static const int sr_latency_ns = 12000;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4124 int plane_sr, cursor_sr;
4125 unsigned int enabled = 0;
4126
4127 if (g4x_compute_wm0(dev, 0,
4128 &g4x_wm_info, latency_ns,
4129 &g4x_cursor_wm_info, latency_ns,
4130 &planea_wm, &cursora_wm))
4131 enabled |= 1;
4132
4133 if (g4x_compute_wm0(dev, 1,
4134 &g4x_wm_info, latency_ns,
4135 &g4x_cursor_wm_info, latency_ns,
4136 &planeb_wm, &cursorb_wm))
4137 enabled |= 2;
4138
4139 plane_sr = cursor_sr = 0;
4140 if (single_plane_enabled(enabled) &&
4141 g4x_compute_srwm(dev, ffs(enabled) - 1,
4142 sr_latency_ns,
4143 &g4x_wm_info,
4144 &g4x_cursor_wm_info,
4145 &plane_sr, &cursor_sr))
4146 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4147 else
4148 I915_WRITE(FW_BLC_SELF,
4149 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4150
4151 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4152 planea_wm, cursora_wm,
4153 planeb_wm, cursorb_wm,
4154 plane_sr, cursor_sr);
4155
4156 I915_WRITE(DSPFW1,
4157 (plane_sr << DSPFW_SR_SHIFT) |
4158 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4159 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4160 planea_wm);
4161 I915_WRITE(DSPFW2,
4162 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4163 (cursora_wm << DSPFW_CURSORA_SHIFT));
4164 /* HPLL off in SR has some issues on G4x... disable it */
4165 I915_WRITE(DSPFW3,
4166 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4167 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4168 }
4169
4170 static void i965_update_wm(struct drm_device *dev)
4171 {
4172 struct drm_i915_private *dev_priv = dev->dev_private;
4173 struct drm_crtc *crtc;
4174 int srwm = 1;
4175 int cursor_sr = 16;
4176
4177 /* Calc sr entries for one plane configs */
4178 crtc = single_enabled_crtc(dev);
4179 if (crtc) {
4180 /* self-refresh has much higher latency */
4181 static const int sr_latency_ns = 12000;
4182 int clock = crtc->mode.clock;
4183 int htotal = crtc->mode.htotal;
4184 int hdisplay = crtc->mode.hdisplay;
4185 int pixel_size = crtc->fb->bits_per_pixel / 8;
4186 unsigned long line_time_us;
4187 int entries;
4188
4189 line_time_us = ((htotal * 1000) / clock);
4190
4191 /* Use ns/us then divide to preserve precision */
4192 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4193 pixel_size * hdisplay;
4194 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4195 srwm = I965_FIFO_SIZE - entries;
4196 if (srwm < 0)
4197 srwm = 1;
4198 srwm &= 0x1ff;
4199 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4200 entries, srwm);
4201
4202 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4203 pixel_size * 64;
4204 entries = DIV_ROUND_UP(entries,
4205 i965_cursor_wm_info.cacheline_size);
4206 cursor_sr = i965_cursor_wm_info.fifo_size -
4207 (entries + i965_cursor_wm_info.guard_size);
4208
4209 if (cursor_sr > i965_cursor_wm_info.max_wm)
4210 cursor_sr = i965_cursor_wm_info.max_wm;
4211
4212 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4213 "cursor %d\n", srwm, cursor_sr);
4214
4215 if (IS_CRESTLINE(dev))
4216 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4217 } else {
4218 /* Turn off self refresh if both pipes are enabled */
4219 if (IS_CRESTLINE(dev))
4220 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4221 & ~FW_BLC_SELF_EN);
4222 }
4223
4224 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4225 srwm);
4226
4227 /* 965 has limitations... */
4228 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4229 (8 << 16) | (8 << 8) | (8 << 0));
4230 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4231 /* update cursor SR watermark */
4232 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4233 }
4234
4235 static void i9xx_update_wm(struct drm_device *dev)
4236 {
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 const struct intel_watermark_params *wm_info;
4239 uint32_t fwater_lo;
4240 uint32_t fwater_hi;
4241 int cwm, srwm = 1;
4242 int fifo_size;
4243 int planea_wm, planeb_wm;
4244 struct drm_crtc *crtc, *enabled = NULL;
4245
4246 if (IS_I945GM(dev))
4247 wm_info = &i945_wm_info;
4248 else if (!IS_GEN2(dev))
4249 wm_info = &i915_wm_info;
4250 else
4251 wm_info = &i855_wm_info;
4252
4253 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4254 crtc = intel_get_crtc_for_plane(dev, 0);
4255 if (crtc->enabled && crtc->fb) {
4256 planea_wm = intel_calculate_wm(crtc->mode.clock,
4257 wm_info, fifo_size,
4258 crtc->fb->bits_per_pixel / 8,
4259 latency_ns);
4260 enabled = crtc;
4261 } else
4262 planea_wm = fifo_size - wm_info->guard_size;
4263
4264 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4265 crtc = intel_get_crtc_for_plane(dev, 1);
4266 if (crtc->enabled && crtc->fb) {
4267 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4268 wm_info, fifo_size,
4269 crtc->fb->bits_per_pixel / 8,
4270 latency_ns);
4271 if (enabled == NULL)
4272 enabled = crtc;
4273 else
4274 enabled = NULL;
4275 } else
4276 planeb_wm = fifo_size - wm_info->guard_size;
4277
4278 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4279
4280 /*
4281 * Overlay gets an aggressive default since video jitter is bad.
4282 */
4283 cwm = 2;
4284
4285 /* Play safe and disable self-refresh before adjusting watermarks. */
4286 if (IS_I945G(dev) || IS_I945GM(dev))
4287 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4288 else if (IS_I915GM(dev))
4289 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4290
4291 /* Calc sr entries for one plane configs */
4292 if (HAS_FW_BLC(dev) && enabled) {
4293 /* self-refresh has much higher latency */
4294 static const int sr_latency_ns = 6000;
4295 int clock = enabled->mode.clock;
4296 int htotal = enabled->mode.htotal;
4297 int hdisplay = enabled->mode.hdisplay;
4298 int pixel_size = enabled->fb->bits_per_pixel / 8;
4299 unsigned long line_time_us;
4300 int entries;
4301
4302 line_time_us = (htotal * 1000) / clock;
4303
4304 /* Use ns/us then divide to preserve precision */
4305 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4306 pixel_size * hdisplay;
4307 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4308 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4309 srwm = wm_info->fifo_size - entries;
4310 if (srwm < 0)
4311 srwm = 1;
4312
4313 if (IS_I945G(dev) || IS_I945GM(dev))
4314 I915_WRITE(FW_BLC_SELF,
4315 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4316 else if (IS_I915GM(dev))
4317 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4318 }
4319
4320 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4321 planea_wm, planeb_wm, cwm, srwm);
4322
4323 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4324 fwater_hi = (cwm & 0x1f);
4325
4326 /* Set request length to 8 cachelines per fetch */
4327 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4328 fwater_hi = fwater_hi | (1 << 8);
4329
4330 I915_WRITE(FW_BLC, fwater_lo);
4331 I915_WRITE(FW_BLC2, fwater_hi);
4332
4333 if (HAS_FW_BLC(dev)) {
4334 if (enabled) {
4335 if (IS_I945G(dev) || IS_I945GM(dev))
4336 I915_WRITE(FW_BLC_SELF,
4337 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4338 else if (IS_I915GM(dev))
4339 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4340 DRM_DEBUG_KMS("memory self refresh enabled\n");
4341 } else
4342 DRM_DEBUG_KMS("memory self refresh disabled\n");
4343 }
4344 }
4345
4346 static void i830_update_wm(struct drm_device *dev)
4347 {
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4349 struct drm_crtc *crtc;
4350 uint32_t fwater_lo;
4351 int planea_wm;
4352
4353 crtc = single_enabled_crtc(dev);
4354 if (crtc == NULL)
4355 return;
4356
4357 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4358 dev_priv->display.get_fifo_size(dev, 0),
4359 crtc->fb->bits_per_pixel / 8,
4360 latency_ns);
4361 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4362 fwater_lo |= (3<<8) | planea_wm;
4363
4364 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4365
4366 I915_WRITE(FW_BLC, fwater_lo);
4367 }
4368
4369 #define ILK_LP0_PLANE_LATENCY 700
4370 #define ILK_LP0_CURSOR_LATENCY 1300
4371
4372 /*
4373 * Check the wm result.
4374 *
4375 * If any calculated watermark values is larger than the maximum value that
4376 * can be programmed into the associated watermark register, that watermark
4377 * must be disabled.
4378 */
4379 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4380 int fbc_wm, int display_wm, int cursor_wm,
4381 const struct intel_watermark_params *display,
4382 const struct intel_watermark_params *cursor)
4383 {
4384 struct drm_i915_private *dev_priv = dev->dev_private;
4385
4386 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4387 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4388
4389 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4390 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4391 fbc_wm, SNB_FBC_MAX_SRWM, level);
4392
4393 /* fbc has it's own way to disable FBC WM */
4394 I915_WRITE(DISP_ARB_CTL,
4395 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4396 return false;
4397 }
4398
4399 if (display_wm > display->max_wm) {
4400 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4401 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4402 return false;
4403 }
4404
4405 if (cursor_wm > cursor->max_wm) {
4406 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4407 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4408 return false;
4409 }
4410
4411 if (!(fbc_wm || display_wm || cursor_wm)) {
4412 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4413 return false;
4414 }
4415
4416 return true;
4417 }
4418
4419 /*
4420 * Compute watermark values of WM[1-3],
4421 */
4422 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4423 int latency_ns,
4424 const struct intel_watermark_params *display,
4425 const struct intel_watermark_params *cursor,
4426 int *fbc_wm, int *display_wm, int *cursor_wm)
4427 {
4428 struct drm_crtc *crtc;
4429 unsigned long line_time_us;
4430 int hdisplay, htotal, pixel_size, clock;
4431 int line_count, line_size;
4432 int small, large;
4433 int entries;
4434
4435 if (!latency_ns) {
4436 *fbc_wm = *display_wm = *cursor_wm = 0;
4437 return false;
4438 }
4439
4440 crtc = intel_get_crtc_for_plane(dev, plane);
4441 hdisplay = crtc->mode.hdisplay;
4442 htotal = crtc->mode.htotal;
4443 clock = crtc->mode.clock;
4444 pixel_size = crtc->fb->bits_per_pixel / 8;
4445
4446 line_time_us = (htotal * 1000) / clock;
4447 line_count = (latency_ns / line_time_us + 1000) / 1000;
4448 line_size = hdisplay * pixel_size;
4449
4450 /* Use the minimum of the small and large buffer method for primary */
4451 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4452 large = line_count * line_size;
4453
4454 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4455 *display_wm = entries + display->guard_size;
4456
4457 /*
4458 * Spec says:
4459 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4460 */
4461 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4462
4463 /* calculate the self-refresh watermark for display cursor */
4464 entries = line_count * pixel_size * 64;
4465 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4466 *cursor_wm = entries + cursor->guard_size;
4467
4468 return ironlake_check_srwm(dev, level,
4469 *fbc_wm, *display_wm, *cursor_wm,
4470 display, cursor);
4471 }
4472
4473 static void ironlake_update_wm(struct drm_device *dev)
4474 {
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 int fbc_wm, plane_wm, cursor_wm;
4477 unsigned int enabled;
4478
4479 enabled = 0;
4480 if (g4x_compute_wm0(dev, 0,
4481 &ironlake_display_wm_info,
4482 ILK_LP0_PLANE_LATENCY,
4483 &ironlake_cursor_wm_info,
4484 ILK_LP0_CURSOR_LATENCY,
4485 &plane_wm, &cursor_wm)) {
4486 I915_WRITE(WM0_PIPEA_ILK,
4487 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4488 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4489 " plane %d, " "cursor: %d\n",
4490 plane_wm, cursor_wm);
4491 enabled |= 1;
4492 }
4493
4494 if (g4x_compute_wm0(dev, 1,
4495 &ironlake_display_wm_info,
4496 ILK_LP0_PLANE_LATENCY,
4497 &ironlake_cursor_wm_info,
4498 ILK_LP0_CURSOR_LATENCY,
4499 &plane_wm, &cursor_wm)) {
4500 I915_WRITE(WM0_PIPEB_ILK,
4501 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4502 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4503 " plane %d, cursor: %d\n",
4504 plane_wm, cursor_wm);
4505 enabled |= 2;
4506 }
4507
4508 /*
4509 * Calculate and update the self-refresh watermark only when one
4510 * display plane is used.
4511 */
4512 I915_WRITE(WM3_LP_ILK, 0);
4513 I915_WRITE(WM2_LP_ILK, 0);
4514 I915_WRITE(WM1_LP_ILK, 0);
4515
4516 if (!single_plane_enabled(enabled))
4517 return;
4518 enabled = ffs(enabled) - 1;
4519
4520 /* WM1 */
4521 if (!ironlake_compute_srwm(dev, 1, enabled,
4522 ILK_READ_WM1_LATENCY() * 500,
4523 &ironlake_display_srwm_info,
4524 &ironlake_cursor_srwm_info,
4525 &fbc_wm, &plane_wm, &cursor_wm))
4526 return;
4527
4528 I915_WRITE(WM1_LP_ILK,
4529 WM1_LP_SR_EN |
4530 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4531 (fbc_wm << WM1_LP_FBC_SHIFT) |
4532 (plane_wm << WM1_LP_SR_SHIFT) |
4533 cursor_wm);
4534
4535 /* WM2 */
4536 if (!ironlake_compute_srwm(dev, 2, enabled,
4537 ILK_READ_WM2_LATENCY() * 500,
4538 &ironlake_display_srwm_info,
4539 &ironlake_cursor_srwm_info,
4540 &fbc_wm, &plane_wm, &cursor_wm))
4541 return;
4542
4543 I915_WRITE(WM2_LP_ILK,
4544 WM2_LP_EN |
4545 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4546 (fbc_wm << WM1_LP_FBC_SHIFT) |
4547 (plane_wm << WM1_LP_SR_SHIFT) |
4548 cursor_wm);
4549
4550 /*
4551 * WM3 is unsupported on ILK, probably because we don't have latency
4552 * data for that power state
4553 */
4554 }
4555
4556 void sandybridge_update_wm(struct drm_device *dev)
4557 {
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4560 u32 val;
4561 int fbc_wm, plane_wm, cursor_wm;
4562 unsigned int enabled;
4563
4564 enabled = 0;
4565 if (g4x_compute_wm0(dev, 0,
4566 &sandybridge_display_wm_info, latency,
4567 &sandybridge_cursor_wm_info, latency,
4568 &plane_wm, &cursor_wm)) {
4569 val = I915_READ(WM0_PIPEA_ILK);
4570 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4571 I915_WRITE(WM0_PIPEA_ILK, val |
4572 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4573 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4574 " plane %d, " "cursor: %d\n",
4575 plane_wm, cursor_wm);
4576 enabled |= 1;
4577 }
4578
4579 if (g4x_compute_wm0(dev, 1,
4580 &sandybridge_display_wm_info, latency,
4581 &sandybridge_cursor_wm_info, latency,
4582 &plane_wm, &cursor_wm)) {
4583 val = I915_READ(WM0_PIPEB_ILK);
4584 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4585 I915_WRITE(WM0_PIPEB_ILK, val |
4586 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4587 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4588 " plane %d, cursor: %d\n",
4589 plane_wm, cursor_wm);
4590 enabled |= 2;
4591 }
4592
4593 /* IVB has 3 pipes */
4594 if (IS_IVYBRIDGE(dev) &&
4595 g4x_compute_wm0(dev, 2,
4596 &sandybridge_display_wm_info, latency,
4597 &sandybridge_cursor_wm_info, latency,
4598 &plane_wm, &cursor_wm)) {
4599 val = I915_READ(WM0_PIPEC_IVB);
4600 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4601 I915_WRITE(WM0_PIPEC_IVB, val |
4602 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4603 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4604 " plane %d, cursor: %d\n",
4605 plane_wm, cursor_wm);
4606 enabled |= 3;
4607 }
4608
4609 /*
4610 * Calculate and update the self-refresh watermark only when one
4611 * display plane is used.
4612 *
4613 * SNB support 3 levels of watermark.
4614 *
4615 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4616 * and disabled in the descending order
4617 *
4618 */
4619 I915_WRITE(WM3_LP_ILK, 0);
4620 I915_WRITE(WM2_LP_ILK, 0);
4621 I915_WRITE(WM1_LP_ILK, 0);
4622
4623 if (!single_plane_enabled(enabled) ||
4624 dev_priv->sprite_scaling_enabled)
4625 return;
4626 enabled = ffs(enabled) - 1;
4627
4628 /* WM1 */
4629 if (!ironlake_compute_srwm(dev, 1, enabled,
4630 SNB_READ_WM1_LATENCY() * 500,
4631 &sandybridge_display_srwm_info,
4632 &sandybridge_cursor_srwm_info,
4633 &fbc_wm, &plane_wm, &cursor_wm))
4634 return;
4635
4636 I915_WRITE(WM1_LP_ILK,
4637 WM1_LP_SR_EN |
4638 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4639 (fbc_wm << WM1_LP_FBC_SHIFT) |
4640 (plane_wm << WM1_LP_SR_SHIFT) |
4641 cursor_wm);
4642
4643 /* WM2 */
4644 if (!ironlake_compute_srwm(dev, 2, enabled,
4645 SNB_READ_WM2_LATENCY() * 500,
4646 &sandybridge_display_srwm_info,
4647 &sandybridge_cursor_srwm_info,
4648 &fbc_wm, &plane_wm, &cursor_wm))
4649 return;
4650
4651 I915_WRITE(WM2_LP_ILK,
4652 WM2_LP_EN |
4653 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4654 (fbc_wm << WM1_LP_FBC_SHIFT) |
4655 (plane_wm << WM1_LP_SR_SHIFT) |
4656 cursor_wm);
4657
4658 /* WM3 */
4659 if (!ironlake_compute_srwm(dev, 3, enabled,
4660 SNB_READ_WM3_LATENCY() * 500,
4661 &sandybridge_display_srwm_info,
4662 &sandybridge_cursor_srwm_info,
4663 &fbc_wm, &plane_wm, &cursor_wm))
4664 return;
4665
4666 I915_WRITE(WM3_LP_ILK,
4667 WM3_LP_EN |
4668 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4669 (fbc_wm << WM1_LP_FBC_SHIFT) |
4670 (plane_wm << WM1_LP_SR_SHIFT) |
4671 cursor_wm);
4672 }
4673
4674 static bool
4675 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4676 uint32_t sprite_width, int pixel_size,
4677 const struct intel_watermark_params *display,
4678 int display_latency_ns, int *sprite_wm)
4679 {
4680 struct drm_crtc *crtc;
4681 int clock;
4682 int entries, tlb_miss;
4683
4684 crtc = intel_get_crtc_for_plane(dev, plane);
4685 if (crtc->fb == NULL || !crtc->enabled) {
4686 *sprite_wm = display->guard_size;
4687 return false;
4688 }
4689
4690 clock = crtc->mode.clock;
4691
4692 /* Use the small buffer method to calculate the sprite watermark */
4693 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4694 tlb_miss = display->fifo_size*display->cacheline_size -
4695 sprite_width * 8;
4696 if (tlb_miss > 0)
4697 entries += tlb_miss;
4698 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4699 *sprite_wm = entries + display->guard_size;
4700 if (*sprite_wm > (int)display->max_wm)
4701 *sprite_wm = display->max_wm;
4702
4703 return true;
4704 }
4705
4706 static bool
4707 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4708 uint32_t sprite_width, int pixel_size,
4709 const struct intel_watermark_params *display,
4710 int latency_ns, int *sprite_wm)
4711 {
4712 struct drm_crtc *crtc;
4713 unsigned long line_time_us;
4714 int clock;
4715 int line_count, line_size;
4716 int small, large;
4717 int entries;
4718
4719 if (!latency_ns) {
4720 *sprite_wm = 0;
4721 return false;
4722 }
4723
4724 crtc = intel_get_crtc_for_plane(dev, plane);
4725 clock = crtc->mode.clock;
4726
4727 line_time_us = (sprite_width * 1000) / clock;
4728 line_count = (latency_ns / line_time_us + 1000) / 1000;
4729 line_size = sprite_width * pixel_size;
4730
4731 /* Use the minimum of the small and large buffer method for primary */
4732 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4733 large = line_count * line_size;
4734
4735 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4736 *sprite_wm = entries + display->guard_size;
4737
4738 return *sprite_wm > 0x3ff ? false : true;
4739 }
4740
4741 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4742 uint32_t sprite_width, int pixel_size)
4743 {
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4745 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4746 u32 val;
4747 int sprite_wm, reg;
4748 int ret;
4749
4750 switch (pipe) {
4751 case 0:
4752 reg = WM0_PIPEA_ILK;
4753 break;
4754 case 1:
4755 reg = WM0_PIPEB_ILK;
4756 break;
4757 case 2:
4758 reg = WM0_PIPEC_IVB;
4759 break;
4760 default:
4761 return; /* bad pipe */
4762 }
4763
4764 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4765 &sandybridge_display_wm_info,
4766 latency, &sprite_wm);
4767 if (!ret) {
4768 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4769 pipe);
4770 return;
4771 }
4772
4773 val = I915_READ(reg);
4774 val &= ~WM0_PIPE_SPRITE_MASK;
4775 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4776 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4777
4778
4779 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4780 pixel_size,
4781 &sandybridge_display_srwm_info,
4782 SNB_READ_WM1_LATENCY() * 500,
4783 &sprite_wm);
4784 if (!ret) {
4785 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4786 pipe);
4787 return;
4788 }
4789 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4790
4791 /* Only IVB has two more LP watermarks for sprite */
4792 if (!IS_IVYBRIDGE(dev))
4793 return;
4794
4795 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4796 pixel_size,
4797 &sandybridge_display_srwm_info,
4798 SNB_READ_WM2_LATENCY() * 500,
4799 &sprite_wm);
4800 if (!ret) {
4801 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4802 pipe);
4803 return;
4804 }
4805 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4806
4807 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4808 pixel_size,
4809 &sandybridge_display_srwm_info,
4810 SNB_READ_WM3_LATENCY() * 500,
4811 &sprite_wm);
4812 if (!ret) {
4813 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4814 pipe);
4815 return;
4816 }
4817 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4818 }
4819
4820 /**
4821 * intel_update_watermarks - update FIFO watermark values based on current modes
4822 *
4823 * Calculate watermark values for the various WM regs based on current mode
4824 * and plane configuration.
4825 *
4826 * There are several cases to deal with here:
4827 * - normal (i.e. non-self-refresh)
4828 * - self-refresh (SR) mode
4829 * - lines are large relative to FIFO size (buffer can hold up to 2)
4830 * - lines are small relative to FIFO size (buffer can hold more than 2
4831 * lines), so need to account for TLB latency
4832 *
4833 * The normal calculation is:
4834 * watermark = dotclock * bytes per pixel * latency
4835 * where latency is platform & configuration dependent (we assume pessimal
4836 * values here).
4837 *
4838 * The SR calculation is:
4839 * watermark = (trunc(latency/line time)+1) * surface width *
4840 * bytes per pixel
4841 * where
4842 * line time = htotal / dotclock
4843 * surface width = hdisplay for normal plane and 64 for cursor
4844 * and latency is assumed to be high, as above.
4845 *
4846 * The final value programmed to the register should always be rounded up,
4847 * and include an extra 2 entries to account for clock crossings.
4848 *
4849 * We don't use the sprite, so we can ignore that. And on Crestline we have
4850 * to set the non-SR watermarks to 8.
4851 */
4852 static void intel_update_watermarks(struct drm_device *dev)
4853 {
4854 struct drm_i915_private *dev_priv = dev->dev_private;
4855
4856 if (dev_priv->display.update_wm)
4857 dev_priv->display.update_wm(dev);
4858 }
4859
4860 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4861 uint32_t sprite_width, int pixel_size)
4862 {
4863 struct drm_i915_private *dev_priv = dev->dev_private;
4864
4865 if (dev_priv->display.update_sprite_wm)
4866 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4867 pixel_size);
4868 }
4869
4870 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4871 {
4872 if (i915_panel_use_ssc >= 0)
4873 return i915_panel_use_ssc != 0;
4874 return dev_priv->lvds_use_ssc
4875 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4876 }
4877
4878 /**
4879 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4880 * @crtc: CRTC structure
4881 * @mode: requested mode
4882 *
4883 * A pipe may be connected to one or more outputs. Based on the depth of the
4884 * attached framebuffer, choose a good color depth to use on the pipe.
4885 *
4886 * If possible, match the pipe depth to the fb depth. In some cases, this
4887 * isn't ideal, because the connected output supports a lesser or restricted
4888 * set of depths. Resolve that here:
4889 * LVDS typically supports only 6bpc, so clamp down in that case
4890 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4891 * Displays may support a restricted set as well, check EDID and clamp as
4892 * appropriate.
4893 * DP may want to dither down to 6bpc to fit larger modes
4894 *
4895 * RETURNS:
4896 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4897 * true if they don't match).
4898 */
4899 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4900 unsigned int *pipe_bpp,
4901 struct drm_display_mode *mode)
4902 {
4903 struct drm_device *dev = crtc->dev;
4904 struct drm_i915_private *dev_priv = dev->dev_private;
4905 struct drm_encoder *encoder;
4906 struct drm_connector *connector;
4907 unsigned int display_bpc = UINT_MAX, bpc;
4908
4909 /* Walk the encoders & connectors on this crtc, get min bpc */
4910 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4911 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4912
4913 if (encoder->crtc != crtc)
4914 continue;
4915
4916 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4917 unsigned int lvds_bpc;
4918
4919 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4920 LVDS_A3_POWER_UP)
4921 lvds_bpc = 8;
4922 else
4923 lvds_bpc = 6;
4924
4925 if (lvds_bpc < display_bpc) {
4926 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4927 display_bpc = lvds_bpc;
4928 }
4929 continue;
4930 }
4931
4932 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4933 /* Use VBT settings if we have an eDP panel */
4934 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4935
4936 if (edp_bpc < display_bpc) {
4937 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4938 display_bpc = edp_bpc;
4939 }
4940 continue;
4941 }
4942
4943 /* Not one of the known troublemakers, check the EDID */
4944 list_for_each_entry(connector, &dev->mode_config.connector_list,
4945 head) {
4946 if (connector->encoder != encoder)
4947 continue;
4948
4949 /* Don't use an invalid EDID bpc value */
4950 if (connector->display_info.bpc &&
4951 connector->display_info.bpc < display_bpc) {
4952 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4953 display_bpc = connector->display_info.bpc;
4954 }
4955 }
4956
4957 /*
4958 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4959 * through, clamp it down. (Note: >12bpc will be caught below.)
4960 */
4961 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4962 if (display_bpc > 8 && display_bpc < 12) {
4963 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4964 display_bpc = 12;
4965 } else {
4966 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4967 display_bpc = 8;
4968 }
4969 }
4970 }
4971
4972 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4973 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4974 display_bpc = 6;
4975 }
4976
4977 /*
4978 * We could just drive the pipe at the highest bpc all the time and
4979 * enable dithering as needed, but that costs bandwidth. So choose
4980 * the minimum value that expresses the full color range of the fb but
4981 * also stays within the max display bpc discovered above.
4982 */
4983
4984 switch (crtc->fb->depth) {
4985 case 8:
4986 bpc = 8; /* since we go through a colormap */
4987 break;
4988 case 15:
4989 case 16:
4990 bpc = 6; /* min is 18bpp */
4991 break;
4992 case 24:
4993 bpc = 8;
4994 break;
4995 case 30:
4996 bpc = 10;
4997 break;
4998 case 48:
4999 bpc = 12;
5000 break;
5001 default:
5002 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5003 bpc = min((unsigned int)8, display_bpc);
5004 break;
5005 }
5006
5007 display_bpc = min(display_bpc, bpc);
5008
5009 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5010 bpc, display_bpc);
5011
5012 *pipe_bpp = display_bpc * 3;
5013
5014 return display_bpc != bpc;
5015 }
5016
5017 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5018 {
5019 struct drm_device *dev = crtc->dev;
5020 struct drm_i915_private *dev_priv = dev->dev_private;
5021 int refclk;
5022
5023 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5024 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5025 refclk = dev_priv->lvds_ssc_freq * 1000;
5026 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5027 refclk / 1000);
5028 } else if (!IS_GEN2(dev)) {
5029 refclk = 96000;
5030 } else {
5031 refclk = 48000;
5032 }
5033
5034 return refclk;
5035 }
5036
5037 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5038 intel_clock_t *clock)
5039 {
5040 /* SDVO TV has fixed PLL values depend on its clock range,
5041 this mirrors vbios setting. */
5042 if (adjusted_mode->clock >= 100000
5043 && adjusted_mode->clock < 140500) {
5044 clock->p1 = 2;
5045 clock->p2 = 10;
5046 clock->n = 3;
5047 clock->m1 = 16;
5048 clock->m2 = 8;
5049 } else if (adjusted_mode->clock >= 140500
5050 && adjusted_mode->clock <= 200000) {
5051 clock->p1 = 1;
5052 clock->p2 = 10;
5053 clock->n = 6;
5054 clock->m1 = 12;
5055 clock->m2 = 8;
5056 }
5057 }
5058
5059 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5060 intel_clock_t *clock,
5061 intel_clock_t *reduced_clock)
5062 {
5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066 int pipe = intel_crtc->pipe;
5067 u32 fp, fp2 = 0;
5068
5069 if (IS_PINEVIEW(dev)) {
5070 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5071 if (reduced_clock)
5072 fp2 = (1 << reduced_clock->n) << 16 |
5073 reduced_clock->m1 << 8 | reduced_clock->m2;
5074 } else {
5075 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5076 if (reduced_clock)
5077 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5078 reduced_clock->m2;
5079 }
5080
5081 I915_WRITE(FP0(pipe), fp);
5082
5083 intel_crtc->lowfreq_avail = false;
5084 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5085 reduced_clock && i915_powersave) {
5086 I915_WRITE(FP1(pipe), fp2);
5087 intel_crtc->lowfreq_avail = true;
5088 } else {
5089 I915_WRITE(FP1(pipe), fp);
5090 }
5091 }
5092
5093 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5094 struct drm_display_mode *mode,
5095 struct drm_display_mode *adjusted_mode,
5096 int x, int y,
5097 struct drm_framebuffer *old_fb)
5098 {
5099 struct drm_device *dev = crtc->dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5102 int pipe = intel_crtc->pipe;
5103 int plane = intel_crtc->plane;
5104 int refclk, num_connectors = 0;
5105 intel_clock_t clock, reduced_clock;
5106 u32 dpll, dspcntr, pipeconf;
5107 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5108 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5109 struct drm_mode_config *mode_config = &dev->mode_config;
5110 struct intel_encoder *encoder;
5111 const intel_limit_t *limit;
5112 int ret;
5113 u32 temp;
5114 u32 lvds_sync = 0;
5115
5116 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5117 if (encoder->base.crtc != crtc)
5118 continue;
5119
5120 switch (encoder->type) {
5121 case INTEL_OUTPUT_LVDS:
5122 is_lvds = true;
5123 break;
5124 case INTEL_OUTPUT_SDVO:
5125 case INTEL_OUTPUT_HDMI:
5126 is_sdvo = true;
5127 if (encoder->needs_tv_clock)
5128 is_tv = true;
5129 break;
5130 case INTEL_OUTPUT_DVO:
5131 is_dvo = true;
5132 break;
5133 case INTEL_OUTPUT_TVOUT:
5134 is_tv = true;
5135 break;
5136 case INTEL_OUTPUT_ANALOG:
5137 is_crt = true;
5138 break;
5139 case INTEL_OUTPUT_DISPLAYPORT:
5140 is_dp = true;
5141 break;
5142 }
5143
5144 num_connectors++;
5145 }
5146
5147 refclk = i9xx_get_refclk(crtc, num_connectors);
5148
5149 /*
5150 * Returns a set of divisors for the desired target clock with the given
5151 * refclk, or FALSE. The returned values represent the clock equation:
5152 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5153 */
5154 limit = intel_limit(crtc, refclk);
5155 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5156 &clock);
5157 if (!ok) {
5158 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5159 return -EINVAL;
5160 }
5161
5162 /* Ensure that the cursor is valid for the new mode before changing... */
5163 intel_crtc_update_cursor(crtc, true);
5164
5165 if (is_lvds && dev_priv->lvds_downclock_avail) {
5166 /*
5167 * Ensure we match the reduced clock's P to the target clock.
5168 * If the clocks don't match, we can't switch the display clock
5169 * by using the FP0/FP1. In such case we will disable the LVDS
5170 * downclock feature.
5171 */
5172 has_reduced_clock = limit->find_pll(limit, crtc,
5173 dev_priv->lvds_downclock,
5174 refclk,
5175 &clock,
5176 &reduced_clock);
5177 }
5178
5179 if (is_sdvo && is_tv)
5180 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5181
5182 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5183 &reduced_clock : NULL);
5184
5185 dpll = DPLL_VGA_MODE_DIS;
5186
5187 if (!IS_GEN2(dev)) {
5188 if (is_lvds)
5189 dpll |= DPLLB_MODE_LVDS;
5190 else
5191 dpll |= DPLLB_MODE_DAC_SERIAL;
5192 if (is_sdvo) {
5193 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5194 if (pixel_multiplier > 1) {
5195 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5196 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5197 }
5198 dpll |= DPLL_DVO_HIGH_SPEED;
5199 }
5200 if (is_dp)
5201 dpll |= DPLL_DVO_HIGH_SPEED;
5202
5203 /* compute bitmask from p1 value */
5204 if (IS_PINEVIEW(dev))
5205 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5206 else {
5207 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5208 if (IS_G4X(dev) && has_reduced_clock)
5209 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5210 }
5211 switch (clock.p2) {
5212 case 5:
5213 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5214 break;
5215 case 7:
5216 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5217 break;
5218 case 10:
5219 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5220 break;
5221 case 14:
5222 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5223 break;
5224 }
5225 if (INTEL_INFO(dev)->gen >= 4)
5226 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5227 } else {
5228 if (is_lvds) {
5229 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5230 } else {
5231 if (clock.p1 == 2)
5232 dpll |= PLL_P1_DIVIDE_BY_TWO;
5233 else
5234 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5235 if (clock.p2 == 4)
5236 dpll |= PLL_P2_DIVIDE_BY_4;
5237 }
5238 }
5239
5240 if (is_sdvo && is_tv)
5241 dpll |= PLL_REF_INPUT_TVCLKINBC;
5242 else if (is_tv)
5243 /* XXX: just matching BIOS for now */
5244 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5245 dpll |= 3;
5246 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5247 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5248 else
5249 dpll |= PLL_REF_INPUT_DREFCLK;
5250
5251 /* setup pipeconf */
5252 pipeconf = I915_READ(PIPECONF(pipe));
5253
5254 /* Set up the display plane register */
5255 dspcntr = DISPPLANE_GAMMA_ENABLE;
5256
5257 if (pipe == 0)
5258 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5259 else
5260 dspcntr |= DISPPLANE_SEL_PIPE_B;
5261
5262 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5263 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5264 * core speed.
5265 *
5266 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5267 * pipe == 0 check?
5268 */
5269 if (mode->clock >
5270 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5271 pipeconf |= PIPECONF_DOUBLE_WIDE;
5272 else
5273 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5274 }
5275
5276 /* default to 8bpc */
5277 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5278 if (is_dp) {
5279 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5280 pipeconf |= PIPECONF_BPP_6 |
5281 PIPECONF_DITHER_EN |
5282 PIPECONF_DITHER_TYPE_SP;
5283 }
5284 }
5285
5286 dpll |= DPLL_VCO_ENABLE;
5287
5288 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5289 drm_mode_debug_printmodeline(mode);
5290
5291 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5292
5293 POSTING_READ(DPLL(pipe));
5294 udelay(150);
5295
5296 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5297 * This is an exception to the general rule that mode_set doesn't turn
5298 * things on.
5299 */
5300 if (is_lvds) {
5301 temp = I915_READ(LVDS);
5302 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5303 if (pipe == 1) {
5304 temp |= LVDS_PIPEB_SELECT;
5305 } else {
5306 temp &= ~LVDS_PIPEB_SELECT;
5307 }
5308 /* set the corresponsding LVDS_BORDER bit */
5309 temp |= dev_priv->lvds_border_bits;
5310 /* Set the B0-B3 data pairs corresponding to whether we're going to
5311 * set the DPLLs for dual-channel mode or not.
5312 */
5313 if (clock.p2 == 7)
5314 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5315 else
5316 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5317
5318 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5319 * appropriately here, but we need to look more thoroughly into how
5320 * panels behave in the two modes.
5321 */
5322 /* set the dithering flag on LVDS as needed */
5323 if (INTEL_INFO(dev)->gen >= 4) {
5324 if (dev_priv->lvds_dither)
5325 temp |= LVDS_ENABLE_DITHER;
5326 else
5327 temp &= ~LVDS_ENABLE_DITHER;
5328 }
5329 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5330 lvds_sync |= LVDS_HSYNC_POLARITY;
5331 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5332 lvds_sync |= LVDS_VSYNC_POLARITY;
5333 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5334 != lvds_sync) {
5335 char flags[2] = "-+";
5336 DRM_INFO("Changing LVDS panel from "
5337 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5338 flags[!(temp & LVDS_HSYNC_POLARITY)],
5339 flags[!(temp & LVDS_VSYNC_POLARITY)],
5340 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5341 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5342 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5343 temp |= lvds_sync;
5344 }
5345 I915_WRITE(LVDS, temp);
5346 }
5347
5348 if (is_dp) {
5349 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5350 }
5351
5352 I915_WRITE(DPLL(pipe), dpll);
5353
5354 /* Wait for the clocks to stabilize. */
5355 POSTING_READ(DPLL(pipe));
5356 udelay(150);
5357
5358 if (INTEL_INFO(dev)->gen >= 4) {
5359 temp = 0;
5360 if (is_sdvo) {
5361 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5362 if (temp > 1)
5363 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5364 else
5365 temp = 0;
5366 }
5367 I915_WRITE(DPLL_MD(pipe), temp);
5368 } else {
5369 /* The pixel multiplier can only be updated once the
5370 * DPLL is enabled and the clocks are stable.
5371 *
5372 * So write it again.
5373 */
5374 I915_WRITE(DPLL(pipe), dpll);
5375 }
5376
5377 if (HAS_PIPE_CXSR(dev)) {
5378 if (intel_crtc->lowfreq_avail) {
5379 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5380 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5381 } else {
5382 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5383 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5384 }
5385 }
5386
5387 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5388 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5389 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5390 /* the chip adds 2 halflines automatically */
5391 adjusted_mode->crtc_vdisplay -= 1;
5392 adjusted_mode->crtc_vtotal -= 1;
5393 adjusted_mode->crtc_vblank_start -= 1;
5394 adjusted_mode->crtc_vblank_end -= 1;
5395 adjusted_mode->crtc_vsync_end -= 1;
5396 adjusted_mode->crtc_vsync_start -= 1;
5397 } else
5398 pipeconf |= PIPECONF_PROGRESSIVE;
5399
5400 I915_WRITE(HTOTAL(pipe),
5401 (adjusted_mode->crtc_hdisplay - 1) |
5402 ((adjusted_mode->crtc_htotal - 1) << 16));
5403 I915_WRITE(HBLANK(pipe),
5404 (adjusted_mode->crtc_hblank_start - 1) |
5405 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5406 I915_WRITE(HSYNC(pipe),
5407 (adjusted_mode->crtc_hsync_start - 1) |
5408 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5409
5410 I915_WRITE(VTOTAL(pipe),
5411 (adjusted_mode->crtc_vdisplay - 1) |
5412 ((adjusted_mode->crtc_vtotal - 1) << 16));
5413 I915_WRITE(VBLANK(pipe),
5414 (adjusted_mode->crtc_vblank_start - 1) |
5415 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5416 I915_WRITE(VSYNC(pipe),
5417 (adjusted_mode->crtc_vsync_start - 1) |
5418 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5419
5420 /* pipesrc and dspsize control the size that is scaled from,
5421 * which should always be the user's requested size.
5422 */
5423 I915_WRITE(DSPSIZE(plane),
5424 ((mode->vdisplay - 1) << 16) |
5425 (mode->hdisplay - 1));
5426 I915_WRITE(DSPPOS(plane), 0);
5427 I915_WRITE(PIPESRC(pipe),
5428 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5429
5430 I915_WRITE(PIPECONF(pipe), pipeconf);
5431 POSTING_READ(PIPECONF(pipe));
5432 intel_enable_pipe(dev_priv, pipe, false);
5433
5434 intel_wait_for_vblank(dev, pipe);
5435
5436 I915_WRITE(DSPCNTR(plane), dspcntr);
5437 POSTING_READ(DSPCNTR(plane));
5438 intel_enable_plane(dev_priv, plane, pipe);
5439
5440 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5441
5442 intel_update_watermarks(dev);
5443
5444 return ret;
5445 }
5446
5447 /*
5448 * Initialize reference clocks when the driver loads
5449 */
5450 void ironlake_init_pch_refclk(struct drm_device *dev)
5451 {
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453 struct drm_mode_config *mode_config = &dev->mode_config;
5454 struct intel_encoder *encoder;
5455 u32 temp;
5456 bool has_lvds = false;
5457 bool has_cpu_edp = false;
5458 bool has_pch_edp = false;
5459 bool has_panel = false;
5460 bool has_ck505 = false;
5461 bool can_ssc = false;
5462
5463 /* We need to take the global config into account */
5464 list_for_each_entry(encoder, &mode_config->encoder_list,
5465 base.head) {
5466 switch (encoder->type) {
5467 case INTEL_OUTPUT_LVDS:
5468 has_panel = true;
5469 has_lvds = true;
5470 break;
5471 case INTEL_OUTPUT_EDP:
5472 has_panel = true;
5473 if (intel_encoder_is_pch_edp(&encoder->base))
5474 has_pch_edp = true;
5475 else
5476 has_cpu_edp = true;
5477 break;
5478 }
5479 }
5480
5481 if (HAS_PCH_IBX(dev)) {
5482 has_ck505 = dev_priv->display_clock_mode;
5483 can_ssc = has_ck505;
5484 } else {
5485 has_ck505 = false;
5486 can_ssc = true;
5487 }
5488
5489 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5490 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5491 has_ck505);
5492
5493 /* Ironlake: try to setup display ref clock before DPLL
5494 * enabling. This is only under driver's control after
5495 * PCH B stepping, previous chipset stepping should be
5496 * ignoring this setting.
5497 */
5498 temp = I915_READ(PCH_DREF_CONTROL);
5499 /* Always enable nonspread source */
5500 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5501
5502 if (has_ck505)
5503 temp |= DREF_NONSPREAD_CK505_ENABLE;
5504 else
5505 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5506
5507 if (has_panel) {
5508 temp &= ~DREF_SSC_SOURCE_MASK;
5509 temp |= DREF_SSC_SOURCE_ENABLE;
5510
5511 /* SSC must be turned on before enabling the CPU output */
5512 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5513 DRM_DEBUG_KMS("Using SSC on panel\n");
5514 temp |= DREF_SSC1_ENABLE;
5515 }
5516
5517 /* Get SSC going before enabling the outputs */
5518 I915_WRITE(PCH_DREF_CONTROL, temp);
5519 POSTING_READ(PCH_DREF_CONTROL);
5520 udelay(200);
5521
5522 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5523
5524 /* Enable CPU source on CPU attached eDP */
5525 if (has_cpu_edp) {
5526 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5527 DRM_DEBUG_KMS("Using SSC on eDP\n");
5528 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5529 }
5530 else
5531 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5532 } else
5533 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5534
5535 I915_WRITE(PCH_DREF_CONTROL, temp);
5536 POSTING_READ(PCH_DREF_CONTROL);
5537 udelay(200);
5538 } else {
5539 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5540
5541 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5542
5543 /* Turn off CPU output */
5544 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5545
5546 I915_WRITE(PCH_DREF_CONTROL, temp);
5547 POSTING_READ(PCH_DREF_CONTROL);
5548 udelay(200);
5549
5550 /* Turn off the SSC source */
5551 temp &= ~DREF_SSC_SOURCE_MASK;
5552 temp |= DREF_SSC_SOURCE_DISABLE;
5553
5554 /* Turn off SSC1 */
5555 temp &= ~ DREF_SSC1_ENABLE;
5556
5557 I915_WRITE(PCH_DREF_CONTROL, temp);
5558 POSTING_READ(PCH_DREF_CONTROL);
5559 udelay(200);
5560 }
5561 }
5562
5563 static int ironlake_get_refclk(struct drm_crtc *crtc)
5564 {
5565 struct drm_device *dev = crtc->dev;
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 struct intel_encoder *encoder;
5568 struct drm_mode_config *mode_config = &dev->mode_config;
5569 struct intel_encoder *edp_encoder = NULL;
5570 int num_connectors = 0;
5571 bool is_lvds = false;
5572
5573 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5574 if (encoder->base.crtc != crtc)
5575 continue;
5576
5577 switch (encoder->type) {
5578 case INTEL_OUTPUT_LVDS:
5579 is_lvds = true;
5580 break;
5581 case INTEL_OUTPUT_EDP:
5582 edp_encoder = encoder;
5583 break;
5584 }
5585 num_connectors++;
5586 }
5587
5588 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5589 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5590 dev_priv->lvds_ssc_freq);
5591 return dev_priv->lvds_ssc_freq * 1000;
5592 }
5593
5594 return 120000;
5595 }
5596
5597 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5598 struct drm_display_mode *mode,
5599 struct drm_display_mode *adjusted_mode,
5600 int x, int y,
5601 struct drm_framebuffer *old_fb)
5602 {
5603 struct drm_device *dev = crtc->dev;
5604 struct drm_i915_private *dev_priv = dev->dev_private;
5605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5606 int pipe = intel_crtc->pipe;
5607 int plane = intel_crtc->plane;
5608 int refclk, num_connectors = 0;
5609 intel_clock_t clock, reduced_clock;
5610 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5611 bool ok, has_reduced_clock = false, is_sdvo = false;
5612 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5613 struct intel_encoder *has_edp_encoder = NULL;
5614 struct drm_mode_config *mode_config = &dev->mode_config;
5615 struct intel_encoder *encoder;
5616 const intel_limit_t *limit;
5617 int ret;
5618 struct fdi_m_n m_n = {0};
5619 u32 temp;
5620 u32 lvds_sync = 0;
5621 int target_clock, pixel_multiplier, lane, link_bw, factor;
5622 unsigned int pipe_bpp;
5623 bool dither;
5624
5625 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5626 if (encoder->base.crtc != crtc)
5627 continue;
5628
5629 switch (encoder->type) {
5630 case INTEL_OUTPUT_LVDS:
5631 is_lvds = true;
5632 break;
5633 case INTEL_OUTPUT_SDVO:
5634 case INTEL_OUTPUT_HDMI:
5635 is_sdvo = true;
5636 if (encoder->needs_tv_clock)
5637 is_tv = true;
5638 break;
5639 case INTEL_OUTPUT_TVOUT:
5640 is_tv = true;
5641 break;
5642 case INTEL_OUTPUT_ANALOG:
5643 is_crt = true;
5644 break;
5645 case INTEL_OUTPUT_DISPLAYPORT:
5646 is_dp = true;
5647 break;
5648 case INTEL_OUTPUT_EDP:
5649 has_edp_encoder = encoder;
5650 break;
5651 }
5652
5653 num_connectors++;
5654 }
5655
5656 refclk = ironlake_get_refclk(crtc);
5657
5658 /*
5659 * Returns a set of divisors for the desired target clock with the given
5660 * refclk, or FALSE. The returned values represent the clock equation:
5661 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5662 */
5663 limit = intel_limit(crtc, refclk);
5664 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5665 &clock);
5666 if (!ok) {
5667 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5668 return -EINVAL;
5669 }
5670
5671 /* Ensure that the cursor is valid for the new mode before changing... */
5672 intel_crtc_update_cursor(crtc, true);
5673
5674 if (is_lvds && dev_priv->lvds_downclock_avail) {
5675 /*
5676 * Ensure we match the reduced clock's P to the target clock.
5677 * If the clocks don't match, we can't switch the display clock
5678 * by using the FP0/FP1. In such case we will disable the LVDS
5679 * downclock feature.
5680 */
5681 has_reduced_clock = limit->find_pll(limit, crtc,
5682 dev_priv->lvds_downclock,
5683 refclk,
5684 &clock,
5685 &reduced_clock);
5686 }
5687 /* SDVO TV has fixed PLL values depend on its clock range,
5688 this mirrors vbios setting. */
5689 if (is_sdvo && is_tv) {
5690 if (adjusted_mode->clock >= 100000
5691 && adjusted_mode->clock < 140500) {
5692 clock.p1 = 2;
5693 clock.p2 = 10;
5694 clock.n = 3;
5695 clock.m1 = 16;
5696 clock.m2 = 8;
5697 } else if (adjusted_mode->clock >= 140500
5698 && adjusted_mode->clock <= 200000) {
5699 clock.p1 = 1;
5700 clock.p2 = 10;
5701 clock.n = 6;
5702 clock.m1 = 12;
5703 clock.m2 = 8;
5704 }
5705 }
5706
5707 /* FDI link */
5708 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5709 lane = 0;
5710 /* CPU eDP doesn't require FDI link, so just set DP M/N
5711 according to current link config */
5712 if (has_edp_encoder &&
5713 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5714 target_clock = mode->clock;
5715 intel_edp_link_config(has_edp_encoder,
5716 &lane, &link_bw);
5717 } else {
5718 /* [e]DP over FDI requires target mode clock
5719 instead of link clock */
5720 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5721 target_clock = mode->clock;
5722 else
5723 target_clock = adjusted_mode->clock;
5724
5725 /* FDI is a binary signal running at ~2.7GHz, encoding
5726 * each output octet as 10 bits. The actual frequency
5727 * is stored as a divider into a 100MHz clock, and the
5728 * mode pixel clock is stored in units of 1KHz.
5729 * Hence the bw of each lane in terms of the mode signal
5730 * is:
5731 */
5732 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5733 }
5734
5735 /* determine panel color depth */
5736 temp = I915_READ(PIPECONF(pipe));
5737 temp &= ~PIPE_BPC_MASK;
5738 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5739 switch (pipe_bpp) {
5740 case 18:
5741 temp |= PIPE_6BPC;
5742 break;
5743 case 24:
5744 temp |= PIPE_8BPC;
5745 break;
5746 case 30:
5747 temp |= PIPE_10BPC;
5748 break;
5749 case 36:
5750 temp |= PIPE_12BPC;
5751 break;
5752 default:
5753 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5754 pipe_bpp);
5755 temp |= PIPE_8BPC;
5756 pipe_bpp = 24;
5757 break;
5758 }
5759
5760 intel_crtc->bpp = pipe_bpp;
5761 I915_WRITE(PIPECONF(pipe), temp);
5762
5763 if (!lane) {
5764 /*
5765 * Account for spread spectrum to avoid
5766 * oversubscribing the link. Max center spread
5767 * is 2.5%; use 5% for safety's sake.
5768 */
5769 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5770 lane = bps / (link_bw * 8) + 1;
5771 }
5772
5773 intel_crtc->fdi_lanes = lane;
5774
5775 if (pixel_multiplier > 1)
5776 link_bw *= pixel_multiplier;
5777 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5778 &m_n);
5779
5780 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5781 if (has_reduced_clock)
5782 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5783 reduced_clock.m2;
5784
5785 /* Enable autotuning of the PLL clock (if permissible) */
5786 factor = 21;
5787 if (is_lvds) {
5788 if ((intel_panel_use_ssc(dev_priv) &&
5789 dev_priv->lvds_ssc_freq == 100) ||
5790 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5791 factor = 25;
5792 } else if (is_sdvo && is_tv)
5793 factor = 20;
5794
5795 if (clock.m < factor * clock.n)
5796 fp |= FP_CB_TUNE;
5797
5798 dpll = 0;
5799
5800 if (is_lvds)
5801 dpll |= DPLLB_MODE_LVDS;
5802 else
5803 dpll |= DPLLB_MODE_DAC_SERIAL;
5804 if (is_sdvo) {
5805 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5806 if (pixel_multiplier > 1) {
5807 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5808 }
5809 dpll |= DPLL_DVO_HIGH_SPEED;
5810 }
5811 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5812 dpll |= DPLL_DVO_HIGH_SPEED;
5813
5814 /* compute bitmask from p1 value */
5815 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5816 /* also FPA1 */
5817 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5818
5819 switch (clock.p2) {
5820 case 5:
5821 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5822 break;
5823 case 7:
5824 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5825 break;
5826 case 10:
5827 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5828 break;
5829 case 14:
5830 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5831 break;
5832 }
5833
5834 if (is_sdvo && is_tv)
5835 dpll |= PLL_REF_INPUT_TVCLKINBC;
5836 else if (is_tv)
5837 /* XXX: just matching BIOS for now */
5838 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5839 dpll |= 3;
5840 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5841 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5842 else
5843 dpll |= PLL_REF_INPUT_DREFCLK;
5844
5845 /* setup pipeconf */
5846 pipeconf = I915_READ(PIPECONF(pipe));
5847
5848 /* Set up the display plane register */
5849 dspcntr = DISPPLANE_GAMMA_ENABLE;
5850
5851 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5852 drm_mode_debug_printmodeline(mode);
5853
5854 /* PCH eDP needs FDI, but CPU eDP does not */
5855 if (!intel_crtc->no_pll) {
5856 if (!has_edp_encoder ||
5857 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5858 I915_WRITE(PCH_FP0(pipe), fp);
5859 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5860
5861 POSTING_READ(PCH_DPLL(pipe));
5862 udelay(150);
5863 }
5864 } else {
5865 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5866 fp == I915_READ(PCH_FP0(0))) {
5867 intel_crtc->use_pll_a = true;
5868 DRM_DEBUG_KMS("using pipe a dpll\n");
5869 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5870 fp == I915_READ(PCH_FP0(1))) {
5871 intel_crtc->use_pll_a = false;
5872 DRM_DEBUG_KMS("using pipe b dpll\n");
5873 } else {
5874 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5875 return -EINVAL;
5876 }
5877 }
5878
5879 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5880 * This is an exception to the general rule that mode_set doesn't turn
5881 * things on.
5882 */
5883 if (is_lvds) {
5884 temp = I915_READ(PCH_LVDS);
5885 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5886 if (HAS_PCH_CPT(dev)) {
5887 temp &= ~PORT_TRANS_SEL_MASK;
5888 temp |= PORT_TRANS_SEL_CPT(pipe);
5889 } else {
5890 if (pipe == 1)
5891 temp |= LVDS_PIPEB_SELECT;
5892 else
5893 temp &= ~LVDS_PIPEB_SELECT;
5894 }
5895
5896 /* set the corresponsding LVDS_BORDER bit */
5897 temp |= dev_priv->lvds_border_bits;
5898 /* Set the B0-B3 data pairs corresponding to whether we're going to
5899 * set the DPLLs for dual-channel mode or not.
5900 */
5901 if (clock.p2 == 7)
5902 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5903 else
5904 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5905
5906 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5907 * appropriately here, but we need to look more thoroughly into how
5908 * panels behave in the two modes.
5909 */
5910 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5911 lvds_sync |= LVDS_HSYNC_POLARITY;
5912 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5913 lvds_sync |= LVDS_VSYNC_POLARITY;
5914 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5915 != lvds_sync) {
5916 char flags[2] = "-+";
5917 DRM_INFO("Changing LVDS panel from "
5918 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5919 flags[!(temp & LVDS_HSYNC_POLARITY)],
5920 flags[!(temp & LVDS_VSYNC_POLARITY)],
5921 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5922 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5923 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5924 temp |= lvds_sync;
5925 }
5926 I915_WRITE(PCH_LVDS, temp);
5927 }
5928
5929 pipeconf &= ~PIPECONF_DITHER_EN;
5930 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5931 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5932 pipeconf |= PIPECONF_DITHER_EN;
5933 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5934 }
5935 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5936 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5937 } else {
5938 /* For non-DP output, clear any trans DP clock recovery setting.*/
5939 I915_WRITE(TRANSDATA_M1(pipe), 0);
5940 I915_WRITE(TRANSDATA_N1(pipe), 0);
5941 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5942 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5943 }
5944
5945 if (!intel_crtc->no_pll &&
5946 (!has_edp_encoder ||
5947 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5948 I915_WRITE(PCH_DPLL(pipe), dpll);
5949
5950 /* Wait for the clocks to stabilize. */
5951 POSTING_READ(PCH_DPLL(pipe));
5952 udelay(150);
5953
5954 /* The pixel multiplier can only be updated once the
5955 * DPLL is enabled and the clocks are stable.
5956 *
5957 * So write it again.
5958 */
5959 I915_WRITE(PCH_DPLL(pipe), dpll);
5960 }
5961
5962 intel_crtc->lowfreq_avail = false;
5963 if (!intel_crtc->no_pll) {
5964 if (is_lvds && has_reduced_clock && i915_powersave) {
5965 I915_WRITE(PCH_FP1(pipe), fp2);
5966 intel_crtc->lowfreq_avail = true;
5967 if (HAS_PIPE_CXSR(dev)) {
5968 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5969 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5970 }
5971 } else {
5972 I915_WRITE(PCH_FP1(pipe), fp);
5973 if (HAS_PIPE_CXSR(dev)) {
5974 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5975 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5976 }
5977 }
5978 }
5979
5980 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5981 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5982 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5983 /* the chip adds 2 halflines automatically */
5984 adjusted_mode->crtc_vdisplay -= 1;
5985 adjusted_mode->crtc_vtotal -= 1;
5986 adjusted_mode->crtc_vblank_start -= 1;
5987 adjusted_mode->crtc_vblank_end -= 1;
5988 adjusted_mode->crtc_vsync_end -= 1;
5989 adjusted_mode->crtc_vsync_start -= 1;
5990 } else
5991 pipeconf |= PIPECONF_PROGRESSIVE;
5992
5993 I915_WRITE(HTOTAL(pipe),
5994 (adjusted_mode->crtc_hdisplay - 1) |
5995 ((adjusted_mode->crtc_htotal - 1) << 16));
5996 I915_WRITE(HBLANK(pipe),
5997 (adjusted_mode->crtc_hblank_start - 1) |
5998 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5999 I915_WRITE(HSYNC(pipe),
6000 (adjusted_mode->crtc_hsync_start - 1) |
6001 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6002
6003 I915_WRITE(VTOTAL(pipe),
6004 (adjusted_mode->crtc_vdisplay - 1) |
6005 ((adjusted_mode->crtc_vtotal - 1) << 16));
6006 I915_WRITE(VBLANK(pipe),
6007 (adjusted_mode->crtc_vblank_start - 1) |
6008 ((adjusted_mode->crtc_vblank_end - 1) << 16));
6009 I915_WRITE(VSYNC(pipe),
6010 (adjusted_mode->crtc_vsync_start - 1) |
6011 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6012
6013 /* pipesrc controls the size that is scaled from, which should
6014 * always be the user's requested size.
6015 */
6016 I915_WRITE(PIPESRC(pipe),
6017 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6018
6019 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6020 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6021 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6022 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6023
6024 if (has_edp_encoder &&
6025 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6026 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6027 }
6028
6029 I915_WRITE(PIPECONF(pipe), pipeconf);
6030 POSTING_READ(PIPECONF(pipe));
6031
6032 intel_wait_for_vblank(dev, pipe);
6033
6034 I915_WRITE(DSPCNTR(plane), dspcntr);
6035 POSTING_READ(DSPCNTR(plane));
6036
6037 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6038
6039 intel_update_watermarks(dev);
6040
6041 return ret;
6042 }
6043
6044 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6045 struct drm_display_mode *mode,
6046 struct drm_display_mode *adjusted_mode,
6047 int x, int y,
6048 struct drm_framebuffer *old_fb)
6049 {
6050 struct drm_device *dev = crtc->dev;
6051 struct drm_i915_private *dev_priv = dev->dev_private;
6052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6053 int pipe = intel_crtc->pipe;
6054 int ret;
6055
6056 drm_vblank_pre_modeset(dev, pipe);
6057
6058 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6059 x, y, old_fb);
6060 drm_vblank_post_modeset(dev, pipe);
6061
6062 if (ret)
6063 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6064 else
6065 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6066
6067 return ret;
6068 }
6069
6070 static bool intel_eld_uptodate(struct drm_connector *connector,
6071 int reg_eldv, uint32_t bits_eldv,
6072 int reg_elda, uint32_t bits_elda,
6073 int reg_edid)
6074 {
6075 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6076 uint8_t *eld = connector->eld;
6077 uint32_t i;
6078
6079 i = I915_READ(reg_eldv);
6080 i &= bits_eldv;
6081
6082 if (!eld[0])
6083 return !i;
6084
6085 if (!i)
6086 return false;
6087
6088 i = I915_READ(reg_elda);
6089 i &= ~bits_elda;
6090 I915_WRITE(reg_elda, i);
6091
6092 for (i = 0; i < eld[2]; i++)
6093 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6094 return false;
6095
6096 return true;
6097 }
6098
6099 static void g4x_write_eld(struct drm_connector *connector,
6100 struct drm_crtc *crtc)
6101 {
6102 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6103 uint8_t *eld = connector->eld;
6104 uint32_t eldv;
6105 uint32_t len;
6106 uint32_t i;
6107
6108 i = I915_READ(G4X_AUD_VID_DID);
6109
6110 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6111 eldv = G4X_ELDV_DEVCL_DEVBLC;
6112 else
6113 eldv = G4X_ELDV_DEVCTG;
6114
6115 if (intel_eld_uptodate(connector,
6116 G4X_AUD_CNTL_ST, eldv,
6117 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6118 G4X_HDMIW_HDMIEDID))
6119 return;
6120
6121 i = I915_READ(G4X_AUD_CNTL_ST);
6122 i &= ~(eldv | G4X_ELD_ADDR);
6123 len = (i >> 9) & 0x1f; /* ELD buffer size */
6124 I915_WRITE(G4X_AUD_CNTL_ST, i);
6125
6126 if (!eld[0])
6127 return;
6128
6129 len = min_t(uint8_t, eld[2], len);
6130 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6131 for (i = 0; i < len; i++)
6132 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6133
6134 i = I915_READ(G4X_AUD_CNTL_ST);
6135 i |= eldv;
6136 I915_WRITE(G4X_AUD_CNTL_ST, i);
6137 }
6138
6139 static void ironlake_write_eld(struct drm_connector *connector,
6140 struct drm_crtc *crtc)
6141 {
6142 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6143 uint8_t *eld = connector->eld;
6144 uint32_t eldv;
6145 uint32_t i;
6146 int len;
6147 int hdmiw_hdmiedid;
6148 int aud_config;
6149 int aud_cntl_st;
6150 int aud_cntrl_st2;
6151
6152 if (HAS_PCH_IBX(connector->dev)) {
6153 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6154 aud_config = IBX_AUD_CONFIG_A;
6155 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6156 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6157 } else {
6158 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6159 aud_config = CPT_AUD_CONFIG_A;
6160 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6161 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6162 }
6163
6164 i = to_intel_crtc(crtc)->pipe;
6165 hdmiw_hdmiedid += i * 0x100;
6166 aud_cntl_st += i * 0x100;
6167 aud_config += i * 0x100;
6168
6169 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6170
6171 i = I915_READ(aud_cntl_st);
6172 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6173 if (!i) {
6174 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6175 /* operate blindly on all ports */
6176 eldv = IBX_ELD_VALIDB;
6177 eldv |= IBX_ELD_VALIDB << 4;
6178 eldv |= IBX_ELD_VALIDB << 8;
6179 } else {
6180 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6181 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6182 }
6183
6184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6185 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6186 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6187 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6188 } else
6189 I915_WRITE(aud_config, 0);
6190
6191 if (intel_eld_uptodate(connector,
6192 aud_cntrl_st2, eldv,
6193 aud_cntl_st, IBX_ELD_ADDRESS,
6194 hdmiw_hdmiedid))
6195 return;
6196
6197 i = I915_READ(aud_cntrl_st2);
6198 i &= ~eldv;
6199 I915_WRITE(aud_cntrl_st2, i);
6200
6201 if (!eld[0])
6202 return;
6203
6204 i = I915_READ(aud_cntl_st);
6205 i &= ~IBX_ELD_ADDRESS;
6206 I915_WRITE(aud_cntl_st, i);
6207
6208 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6209 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6210 for (i = 0; i < len; i++)
6211 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6212
6213 i = I915_READ(aud_cntrl_st2);
6214 i |= eldv;
6215 I915_WRITE(aud_cntrl_st2, i);
6216 }
6217
6218 void intel_write_eld(struct drm_encoder *encoder,
6219 struct drm_display_mode *mode)
6220 {
6221 struct drm_crtc *crtc = encoder->crtc;
6222 struct drm_connector *connector;
6223 struct drm_device *dev = encoder->dev;
6224 struct drm_i915_private *dev_priv = dev->dev_private;
6225
6226 connector = drm_select_eld(encoder, mode);
6227 if (!connector)
6228 return;
6229
6230 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6231 connector->base.id,
6232 drm_get_connector_name(connector),
6233 connector->encoder->base.id,
6234 drm_get_encoder_name(connector->encoder));
6235
6236 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6237
6238 if (dev_priv->display.write_eld)
6239 dev_priv->display.write_eld(connector, crtc);
6240 }
6241
6242 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6243 void intel_crtc_load_lut(struct drm_crtc *crtc)
6244 {
6245 struct drm_device *dev = crtc->dev;
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6248 int palreg = PALETTE(intel_crtc->pipe);
6249 int i;
6250
6251 /* The clocks have to be on to load the palette. */
6252 if (!crtc->enabled)
6253 return;
6254
6255 /* use legacy palette for Ironlake */
6256 if (HAS_PCH_SPLIT(dev))
6257 palreg = LGC_PALETTE(intel_crtc->pipe);
6258
6259 for (i = 0; i < 256; i++) {
6260 I915_WRITE(palreg + 4 * i,
6261 (intel_crtc->lut_r[i] << 16) |
6262 (intel_crtc->lut_g[i] << 8) |
6263 intel_crtc->lut_b[i]);
6264 }
6265 }
6266
6267 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6268 {
6269 struct drm_device *dev = crtc->dev;
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272 bool visible = base != 0;
6273 u32 cntl;
6274
6275 if (intel_crtc->cursor_visible == visible)
6276 return;
6277
6278 cntl = I915_READ(_CURACNTR);
6279 if (visible) {
6280 /* On these chipsets we can only modify the base whilst
6281 * the cursor is disabled.
6282 */
6283 I915_WRITE(_CURABASE, base);
6284
6285 cntl &= ~(CURSOR_FORMAT_MASK);
6286 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6287 cntl |= CURSOR_ENABLE |
6288 CURSOR_GAMMA_ENABLE |
6289 CURSOR_FORMAT_ARGB;
6290 } else
6291 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6292 I915_WRITE(_CURACNTR, cntl);
6293
6294 intel_crtc->cursor_visible = visible;
6295 }
6296
6297 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6298 {
6299 struct drm_device *dev = crtc->dev;
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6302 int pipe = intel_crtc->pipe;
6303 bool visible = base != 0;
6304
6305 if (intel_crtc->cursor_visible != visible) {
6306 uint32_t cntl = I915_READ(CURCNTR(pipe));
6307 if (base) {
6308 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6309 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6310 cntl |= pipe << 28; /* Connect to correct pipe */
6311 } else {
6312 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6313 cntl |= CURSOR_MODE_DISABLE;
6314 }
6315 I915_WRITE(CURCNTR(pipe), cntl);
6316
6317 intel_crtc->cursor_visible = visible;
6318 }
6319 /* and commit changes on next vblank */
6320 I915_WRITE(CURBASE(pipe), base);
6321 }
6322
6323 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6324 {
6325 struct drm_device *dev = crtc->dev;
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328 int pipe = intel_crtc->pipe;
6329 bool visible = base != 0;
6330
6331 if (intel_crtc->cursor_visible != visible) {
6332 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6333 if (base) {
6334 cntl &= ~CURSOR_MODE;
6335 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6336 } else {
6337 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6338 cntl |= CURSOR_MODE_DISABLE;
6339 }
6340 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6341
6342 intel_crtc->cursor_visible = visible;
6343 }
6344 /* and commit changes on next vblank */
6345 I915_WRITE(CURBASE_IVB(pipe), base);
6346 }
6347
6348 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6349 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6350 bool on)
6351 {
6352 struct drm_device *dev = crtc->dev;
6353 struct drm_i915_private *dev_priv = dev->dev_private;
6354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355 int pipe = intel_crtc->pipe;
6356 int x = intel_crtc->cursor_x;
6357 int y = intel_crtc->cursor_y;
6358 u32 base, pos;
6359 bool visible;
6360
6361 pos = 0;
6362
6363 if (on && crtc->enabled && crtc->fb) {
6364 base = intel_crtc->cursor_addr;
6365 if (x > (int) crtc->fb->width)
6366 base = 0;
6367
6368 if (y > (int) crtc->fb->height)
6369 base = 0;
6370 } else
6371 base = 0;
6372
6373 if (x < 0) {
6374 if (x + intel_crtc->cursor_width < 0)
6375 base = 0;
6376
6377 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6378 x = -x;
6379 }
6380 pos |= x << CURSOR_X_SHIFT;
6381
6382 if (y < 0) {
6383 if (y + intel_crtc->cursor_height < 0)
6384 base = 0;
6385
6386 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6387 y = -y;
6388 }
6389 pos |= y << CURSOR_Y_SHIFT;
6390
6391 visible = base != 0;
6392 if (!visible && !intel_crtc->cursor_visible)
6393 return;
6394
6395 if (IS_IVYBRIDGE(dev)) {
6396 I915_WRITE(CURPOS_IVB(pipe), pos);
6397 ivb_update_cursor(crtc, base);
6398 } else {
6399 I915_WRITE(CURPOS(pipe), pos);
6400 if (IS_845G(dev) || IS_I865G(dev))
6401 i845_update_cursor(crtc, base);
6402 else
6403 i9xx_update_cursor(crtc, base);
6404 }
6405
6406 if (visible)
6407 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6408 }
6409
6410 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6411 struct drm_file *file,
6412 uint32_t handle,
6413 uint32_t width, uint32_t height)
6414 {
6415 struct drm_device *dev = crtc->dev;
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418 struct drm_i915_gem_object *obj;
6419 uint32_t addr;
6420 int ret;
6421
6422 DRM_DEBUG_KMS("\n");
6423
6424 /* if we want to turn off the cursor ignore width and height */
6425 if (!handle) {
6426 DRM_DEBUG_KMS("cursor off\n");
6427 addr = 0;
6428 obj = NULL;
6429 mutex_lock(&dev->struct_mutex);
6430 goto finish;
6431 }
6432
6433 /* Currently we only support 64x64 cursors */
6434 if (width != 64 || height != 64) {
6435 DRM_ERROR("we currently only support 64x64 cursors\n");
6436 return -EINVAL;
6437 }
6438
6439 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6440 if (&obj->base == NULL)
6441 return -ENOENT;
6442
6443 if (obj->base.size < width * height * 4) {
6444 DRM_ERROR("buffer is to small\n");
6445 ret = -ENOMEM;
6446 goto fail;
6447 }
6448
6449 /* we only need to pin inside GTT if cursor is non-phy */
6450 mutex_lock(&dev->struct_mutex);
6451 if (!dev_priv->info->cursor_needs_physical) {
6452 if (obj->tiling_mode) {
6453 DRM_ERROR("cursor cannot be tiled\n");
6454 ret = -EINVAL;
6455 goto fail_locked;
6456 }
6457
6458 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6459 if (ret) {
6460 DRM_ERROR("failed to move cursor bo into the GTT\n");
6461 goto fail_locked;
6462 }
6463
6464 ret = i915_gem_object_put_fence(obj);
6465 if (ret) {
6466 DRM_ERROR("failed to release fence for cursor");
6467 goto fail_unpin;
6468 }
6469
6470 addr = obj->gtt_offset;
6471 } else {
6472 int align = IS_I830(dev) ? 16 * 1024 : 256;
6473 ret = i915_gem_attach_phys_object(dev, obj,
6474 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6475 align);
6476 if (ret) {
6477 DRM_ERROR("failed to attach phys object\n");
6478 goto fail_locked;
6479 }
6480 addr = obj->phys_obj->handle->busaddr;
6481 }
6482
6483 if (IS_GEN2(dev))
6484 I915_WRITE(CURSIZE, (height << 12) | width);
6485
6486 finish:
6487 if (intel_crtc->cursor_bo) {
6488 if (dev_priv->info->cursor_needs_physical) {
6489 if (intel_crtc->cursor_bo != obj)
6490 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6491 } else
6492 i915_gem_object_unpin(intel_crtc->cursor_bo);
6493 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6494 }
6495
6496 mutex_unlock(&dev->struct_mutex);
6497
6498 intel_crtc->cursor_addr = addr;
6499 intel_crtc->cursor_bo = obj;
6500 intel_crtc->cursor_width = width;
6501 intel_crtc->cursor_height = height;
6502
6503 intel_crtc_update_cursor(crtc, true);
6504
6505 return 0;
6506 fail_unpin:
6507 i915_gem_object_unpin(obj);
6508 fail_locked:
6509 mutex_unlock(&dev->struct_mutex);
6510 fail:
6511 drm_gem_object_unreference_unlocked(&obj->base);
6512 return ret;
6513 }
6514
6515 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6516 {
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6518
6519 intel_crtc->cursor_x = x;
6520 intel_crtc->cursor_y = y;
6521
6522 intel_crtc_update_cursor(crtc, true);
6523
6524 return 0;
6525 }
6526
6527 /** Sets the color ramps on behalf of RandR */
6528 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6529 u16 blue, int regno)
6530 {
6531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6532
6533 intel_crtc->lut_r[regno] = red >> 8;
6534 intel_crtc->lut_g[regno] = green >> 8;
6535 intel_crtc->lut_b[regno] = blue >> 8;
6536 }
6537
6538 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6539 u16 *blue, int regno)
6540 {
6541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6542
6543 *red = intel_crtc->lut_r[regno] << 8;
6544 *green = intel_crtc->lut_g[regno] << 8;
6545 *blue = intel_crtc->lut_b[regno] << 8;
6546 }
6547
6548 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6549 u16 *blue, uint32_t start, uint32_t size)
6550 {
6551 int end = (start + size > 256) ? 256 : start + size, i;
6552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6553
6554 for (i = start; i < end; i++) {
6555 intel_crtc->lut_r[i] = red[i] >> 8;
6556 intel_crtc->lut_g[i] = green[i] >> 8;
6557 intel_crtc->lut_b[i] = blue[i] >> 8;
6558 }
6559
6560 intel_crtc_load_lut(crtc);
6561 }
6562
6563 /**
6564 * Get a pipe with a simple mode set on it for doing load-based monitor
6565 * detection.
6566 *
6567 * It will be up to the load-detect code to adjust the pipe as appropriate for
6568 * its requirements. The pipe will be connected to no other encoders.
6569 *
6570 * Currently this code will only succeed if there is a pipe with no encoders
6571 * configured for it. In the future, it could choose to temporarily disable
6572 * some outputs to free up a pipe for its use.
6573 *
6574 * \return crtc, or NULL if no pipes are available.
6575 */
6576
6577 /* VESA 640x480x72Hz mode to set on the pipe */
6578 static struct drm_display_mode load_detect_mode = {
6579 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6580 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6581 };
6582
6583 static struct drm_framebuffer *
6584 intel_framebuffer_create(struct drm_device *dev,
6585 struct drm_mode_fb_cmd2 *mode_cmd,
6586 struct drm_i915_gem_object *obj)
6587 {
6588 struct intel_framebuffer *intel_fb;
6589 int ret;
6590
6591 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6592 if (!intel_fb) {
6593 drm_gem_object_unreference_unlocked(&obj->base);
6594 return ERR_PTR(-ENOMEM);
6595 }
6596
6597 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6598 if (ret) {
6599 drm_gem_object_unreference_unlocked(&obj->base);
6600 kfree(intel_fb);
6601 return ERR_PTR(ret);
6602 }
6603
6604 return &intel_fb->base;
6605 }
6606
6607 static u32
6608 intel_framebuffer_pitch_for_width(int width, int bpp)
6609 {
6610 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6611 return ALIGN(pitch, 64);
6612 }
6613
6614 static u32
6615 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6616 {
6617 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6618 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6619 }
6620
6621 static struct drm_framebuffer *
6622 intel_framebuffer_create_for_mode(struct drm_device *dev,
6623 struct drm_display_mode *mode,
6624 int depth, int bpp)
6625 {
6626 struct drm_i915_gem_object *obj;
6627 struct drm_mode_fb_cmd2 mode_cmd;
6628
6629 obj = i915_gem_alloc_object(dev,
6630 intel_framebuffer_size_for_mode(mode, bpp));
6631 if (obj == NULL)
6632 return ERR_PTR(-ENOMEM);
6633
6634 mode_cmd.width = mode->hdisplay;
6635 mode_cmd.height = mode->vdisplay;
6636 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6637 bpp);
6638 mode_cmd.pixel_format = 0;
6639
6640 return intel_framebuffer_create(dev, &mode_cmd, obj);
6641 }
6642
6643 static struct drm_framebuffer *
6644 mode_fits_in_fbdev(struct drm_device *dev,
6645 struct drm_display_mode *mode)
6646 {
6647 struct drm_i915_private *dev_priv = dev->dev_private;
6648 struct drm_i915_gem_object *obj;
6649 struct drm_framebuffer *fb;
6650
6651 if (dev_priv->fbdev == NULL)
6652 return NULL;
6653
6654 obj = dev_priv->fbdev->ifb.obj;
6655 if (obj == NULL)
6656 return NULL;
6657
6658 fb = &dev_priv->fbdev->ifb.base;
6659 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6660 fb->bits_per_pixel))
6661 return NULL;
6662
6663 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6664 return NULL;
6665
6666 return fb;
6667 }
6668
6669 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6670 struct drm_connector *connector,
6671 struct drm_display_mode *mode,
6672 struct intel_load_detect_pipe *old)
6673 {
6674 struct intel_crtc *intel_crtc;
6675 struct drm_crtc *possible_crtc;
6676 struct drm_encoder *encoder = &intel_encoder->base;
6677 struct drm_crtc *crtc = NULL;
6678 struct drm_device *dev = encoder->dev;
6679 struct drm_framebuffer *old_fb;
6680 int i = -1;
6681
6682 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6683 connector->base.id, drm_get_connector_name(connector),
6684 encoder->base.id, drm_get_encoder_name(encoder));
6685
6686 /*
6687 * Algorithm gets a little messy:
6688 *
6689 * - if the connector already has an assigned crtc, use it (but make
6690 * sure it's on first)
6691 *
6692 * - try to find the first unused crtc that can drive this connector,
6693 * and use that if we find one
6694 */
6695
6696 /* See if we already have a CRTC for this connector */
6697 if (encoder->crtc) {
6698 crtc = encoder->crtc;
6699
6700 intel_crtc = to_intel_crtc(crtc);
6701 old->dpms_mode = intel_crtc->dpms_mode;
6702 old->load_detect_temp = false;
6703
6704 /* Make sure the crtc and connector are running */
6705 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6706 struct drm_encoder_helper_funcs *encoder_funcs;
6707 struct drm_crtc_helper_funcs *crtc_funcs;
6708
6709 crtc_funcs = crtc->helper_private;
6710 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6711
6712 encoder_funcs = encoder->helper_private;
6713 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6714 }
6715
6716 return true;
6717 }
6718
6719 /* Find an unused one (if possible) */
6720 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6721 i++;
6722 if (!(encoder->possible_crtcs & (1 << i)))
6723 continue;
6724 if (!possible_crtc->enabled) {
6725 crtc = possible_crtc;
6726 break;
6727 }
6728 }
6729
6730 /*
6731 * If we didn't find an unused CRTC, don't use any.
6732 */
6733 if (!crtc) {
6734 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6735 return false;
6736 }
6737
6738 encoder->crtc = crtc;
6739 connector->encoder = encoder;
6740
6741 intel_crtc = to_intel_crtc(crtc);
6742 old->dpms_mode = intel_crtc->dpms_mode;
6743 old->load_detect_temp = true;
6744 old->release_fb = NULL;
6745
6746 if (!mode)
6747 mode = &load_detect_mode;
6748
6749 old_fb = crtc->fb;
6750
6751 /* We need a framebuffer large enough to accommodate all accesses
6752 * that the plane may generate whilst we perform load detection.
6753 * We can not rely on the fbcon either being present (we get called
6754 * during its initialisation to detect all boot displays, or it may
6755 * not even exist) or that it is large enough to satisfy the
6756 * requested mode.
6757 */
6758 crtc->fb = mode_fits_in_fbdev(dev, mode);
6759 if (crtc->fb == NULL) {
6760 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6761 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6762 old->release_fb = crtc->fb;
6763 } else
6764 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6765 if (IS_ERR(crtc->fb)) {
6766 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6767 crtc->fb = old_fb;
6768 return false;
6769 }
6770
6771 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6772 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6773 if (old->release_fb)
6774 old->release_fb->funcs->destroy(old->release_fb);
6775 crtc->fb = old_fb;
6776 return false;
6777 }
6778
6779 /* let the connector get through one full cycle before testing */
6780 intel_wait_for_vblank(dev, intel_crtc->pipe);
6781
6782 return true;
6783 }
6784
6785 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6786 struct drm_connector *connector,
6787 struct intel_load_detect_pipe *old)
6788 {
6789 struct drm_encoder *encoder = &intel_encoder->base;
6790 struct drm_device *dev = encoder->dev;
6791 struct drm_crtc *crtc = encoder->crtc;
6792 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6793 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6794
6795 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6796 connector->base.id, drm_get_connector_name(connector),
6797 encoder->base.id, drm_get_encoder_name(encoder));
6798
6799 if (old->load_detect_temp) {
6800 connector->encoder = NULL;
6801 drm_helper_disable_unused_functions(dev);
6802
6803 if (old->release_fb)
6804 old->release_fb->funcs->destroy(old->release_fb);
6805
6806 return;
6807 }
6808
6809 /* Switch crtc and encoder back off if necessary */
6810 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6811 encoder_funcs->dpms(encoder, old->dpms_mode);
6812 crtc_funcs->dpms(crtc, old->dpms_mode);
6813 }
6814 }
6815
6816 /* Returns the clock of the currently programmed mode of the given pipe. */
6817 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6818 {
6819 struct drm_i915_private *dev_priv = dev->dev_private;
6820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6821 int pipe = intel_crtc->pipe;
6822 u32 dpll = I915_READ(DPLL(pipe));
6823 u32 fp;
6824 intel_clock_t clock;
6825
6826 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6827 fp = I915_READ(FP0(pipe));
6828 else
6829 fp = I915_READ(FP1(pipe));
6830
6831 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6832 if (IS_PINEVIEW(dev)) {
6833 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6834 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6835 } else {
6836 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6837 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6838 }
6839
6840 if (!IS_GEN2(dev)) {
6841 if (IS_PINEVIEW(dev))
6842 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6843 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6844 else
6845 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6846 DPLL_FPA01_P1_POST_DIV_SHIFT);
6847
6848 switch (dpll & DPLL_MODE_MASK) {
6849 case DPLLB_MODE_DAC_SERIAL:
6850 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6851 5 : 10;
6852 break;
6853 case DPLLB_MODE_LVDS:
6854 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6855 7 : 14;
6856 break;
6857 default:
6858 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6859 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6860 return 0;
6861 }
6862
6863 /* XXX: Handle the 100Mhz refclk */
6864 intel_clock(dev, 96000, &clock);
6865 } else {
6866 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6867
6868 if (is_lvds) {
6869 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6870 DPLL_FPA01_P1_POST_DIV_SHIFT);
6871 clock.p2 = 14;
6872
6873 if ((dpll & PLL_REF_INPUT_MASK) ==
6874 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6875 /* XXX: might not be 66MHz */
6876 intel_clock(dev, 66000, &clock);
6877 } else
6878 intel_clock(dev, 48000, &clock);
6879 } else {
6880 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6881 clock.p1 = 2;
6882 else {
6883 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6884 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6885 }
6886 if (dpll & PLL_P2_DIVIDE_BY_4)
6887 clock.p2 = 4;
6888 else
6889 clock.p2 = 2;
6890
6891 intel_clock(dev, 48000, &clock);
6892 }
6893 }
6894
6895 /* XXX: It would be nice to validate the clocks, but we can't reuse
6896 * i830PllIsValid() because it relies on the xf86_config connector
6897 * configuration being accurate, which it isn't necessarily.
6898 */
6899
6900 return clock.dot;
6901 }
6902
6903 /** Returns the currently programmed mode of the given pipe. */
6904 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6905 struct drm_crtc *crtc)
6906 {
6907 struct drm_i915_private *dev_priv = dev->dev_private;
6908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6909 int pipe = intel_crtc->pipe;
6910 struct drm_display_mode *mode;
6911 int htot = I915_READ(HTOTAL(pipe));
6912 int hsync = I915_READ(HSYNC(pipe));
6913 int vtot = I915_READ(VTOTAL(pipe));
6914 int vsync = I915_READ(VSYNC(pipe));
6915
6916 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6917 if (!mode)
6918 return NULL;
6919
6920 mode->clock = intel_crtc_clock_get(dev, crtc);
6921 mode->hdisplay = (htot & 0xffff) + 1;
6922 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6923 mode->hsync_start = (hsync & 0xffff) + 1;
6924 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6925 mode->vdisplay = (vtot & 0xffff) + 1;
6926 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6927 mode->vsync_start = (vsync & 0xffff) + 1;
6928 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6929
6930 drm_mode_set_name(mode);
6931 drm_mode_set_crtcinfo(mode, 0);
6932
6933 return mode;
6934 }
6935
6936 #define GPU_IDLE_TIMEOUT 500 /* ms */
6937
6938 /* When this timer fires, we've been idle for awhile */
6939 static void intel_gpu_idle_timer(unsigned long arg)
6940 {
6941 struct drm_device *dev = (struct drm_device *)arg;
6942 drm_i915_private_t *dev_priv = dev->dev_private;
6943
6944 if (!list_empty(&dev_priv->mm.active_list)) {
6945 /* Still processing requests, so just re-arm the timer. */
6946 mod_timer(&dev_priv->idle_timer, jiffies +
6947 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6948 return;
6949 }
6950
6951 dev_priv->busy = false;
6952 queue_work(dev_priv->wq, &dev_priv->idle_work);
6953 }
6954
6955 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6956
6957 static void intel_crtc_idle_timer(unsigned long arg)
6958 {
6959 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6960 struct drm_crtc *crtc = &intel_crtc->base;
6961 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6962 struct intel_framebuffer *intel_fb;
6963
6964 intel_fb = to_intel_framebuffer(crtc->fb);
6965 if (intel_fb && intel_fb->obj->active) {
6966 /* The framebuffer is still being accessed by the GPU. */
6967 mod_timer(&intel_crtc->idle_timer, jiffies +
6968 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6969 return;
6970 }
6971
6972 intel_crtc->busy = false;
6973 queue_work(dev_priv->wq, &dev_priv->idle_work);
6974 }
6975
6976 static void intel_increase_pllclock(struct drm_crtc *crtc)
6977 {
6978 struct drm_device *dev = crtc->dev;
6979 drm_i915_private_t *dev_priv = dev->dev_private;
6980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6981 int pipe = intel_crtc->pipe;
6982 int dpll_reg = DPLL(pipe);
6983 int dpll;
6984
6985 if (HAS_PCH_SPLIT(dev))
6986 return;
6987
6988 if (!dev_priv->lvds_downclock_avail)
6989 return;
6990
6991 dpll = I915_READ(dpll_reg);
6992 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6993 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6994
6995 /* Unlock panel regs */
6996 I915_WRITE(PP_CONTROL,
6997 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6998
6999 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7000 I915_WRITE(dpll_reg, dpll);
7001 intel_wait_for_vblank(dev, pipe);
7002
7003 dpll = I915_READ(dpll_reg);
7004 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7005 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7006
7007 /* ...and lock them again */
7008 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7009 }
7010
7011 /* Schedule downclock */
7012 mod_timer(&intel_crtc->idle_timer, jiffies +
7013 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7014 }
7015
7016 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7017 {
7018 struct drm_device *dev = crtc->dev;
7019 drm_i915_private_t *dev_priv = dev->dev_private;
7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7021 int pipe = intel_crtc->pipe;
7022 int dpll_reg = DPLL(pipe);
7023 int dpll = I915_READ(dpll_reg);
7024
7025 if (HAS_PCH_SPLIT(dev))
7026 return;
7027
7028 if (!dev_priv->lvds_downclock_avail)
7029 return;
7030
7031 /*
7032 * Since this is called by a timer, we should never get here in
7033 * the manual case.
7034 */
7035 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7036 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7037
7038 /* Unlock panel regs */
7039 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7040 PANEL_UNLOCK_REGS);
7041
7042 dpll |= DISPLAY_RATE_SELECT_FPA1;
7043 I915_WRITE(dpll_reg, dpll);
7044 intel_wait_for_vblank(dev, pipe);
7045 dpll = I915_READ(dpll_reg);
7046 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7047 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7048
7049 /* ...and lock them again */
7050 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7051 }
7052
7053 }
7054
7055 /**
7056 * intel_idle_update - adjust clocks for idleness
7057 * @work: work struct
7058 *
7059 * Either the GPU or display (or both) went idle. Check the busy status
7060 * here and adjust the CRTC and GPU clocks as necessary.
7061 */
7062 static void intel_idle_update(struct work_struct *work)
7063 {
7064 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7065 idle_work);
7066 struct drm_device *dev = dev_priv->dev;
7067 struct drm_crtc *crtc;
7068 struct intel_crtc *intel_crtc;
7069
7070 if (!i915_powersave)
7071 return;
7072
7073 mutex_lock(&dev->struct_mutex);
7074
7075 i915_update_gfx_val(dev_priv);
7076
7077 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7078 /* Skip inactive CRTCs */
7079 if (!crtc->fb)
7080 continue;
7081
7082 intel_crtc = to_intel_crtc(crtc);
7083 if (!intel_crtc->busy)
7084 intel_decrease_pllclock(crtc);
7085 }
7086
7087
7088 mutex_unlock(&dev->struct_mutex);
7089 }
7090
7091 /**
7092 * intel_mark_busy - mark the GPU and possibly the display busy
7093 * @dev: drm device
7094 * @obj: object we're operating on
7095 *
7096 * Callers can use this function to indicate that the GPU is busy processing
7097 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7098 * buffer), we'll also mark the display as busy, so we know to increase its
7099 * clock frequency.
7100 */
7101 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7102 {
7103 drm_i915_private_t *dev_priv = dev->dev_private;
7104 struct drm_crtc *crtc = NULL;
7105 struct intel_framebuffer *intel_fb;
7106 struct intel_crtc *intel_crtc;
7107
7108 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7109 return;
7110
7111 if (!dev_priv->busy)
7112 dev_priv->busy = true;
7113 else
7114 mod_timer(&dev_priv->idle_timer, jiffies +
7115 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7116
7117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7118 if (!crtc->fb)
7119 continue;
7120
7121 intel_crtc = to_intel_crtc(crtc);
7122 intel_fb = to_intel_framebuffer(crtc->fb);
7123 if (intel_fb->obj == obj) {
7124 if (!intel_crtc->busy) {
7125 /* Non-busy -> busy, upclock */
7126 intel_increase_pllclock(crtc);
7127 intel_crtc->busy = true;
7128 } else {
7129 /* Busy -> busy, put off timer */
7130 mod_timer(&intel_crtc->idle_timer, jiffies +
7131 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7132 }
7133 }
7134 }
7135 }
7136
7137 static void intel_crtc_destroy(struct drm_crtc *crtc)
7138 {
7139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140 struct drm_device *dev = crtc->dev;
7141 struct intel_unpin_work *work;
7142 unsigned long flags;
7143
7144 spin_lock_irqsave(&dev->event_lock, flags);
7145 work = intel_crtc->unpin_work;
7146 intel_crtc->unpin_work = NULL;
7147 spin_unlock_irqrestore(&dev->event_lock, flags);
7148
7149 if (work) {
7150 cancel_work_sync(&work->work);
7151 kfree(work);
7152 }
7153
7154 drm_crtc_cleanup(crtc);
7155
7156 kfree(intel_crtc);
7157 }
7158
7159 static void intel_unpin_work_fn(struct work_struct *__work)
7160 {
7161 struct intel_unpin_work *work =
7162 container_of(__work, struct intel_unpin_work, work);
7163
7164 mutex_lock(&work->dev->struct_mutex);
7165 intel_unpin_fb_obj(work->old_fb_obj);
7166 drm_gem_object_unreference(&work->pending_flip_obj->base);
7167 drm_gem_object_unreference(&work->old_fb_obj->base);
7168
7169 intel_update_fbc(work->dev);
7170 mutex_unlock(&work->dev->struct_mutex);
7171 kfree(work);
7172 }
7173
7174 static void do_intel_finish_page_flip(struct drm_device *dev,
7175 struct drm_crtc *crtc)
7176 {
7177 drm_i915_private_t *dev_priv = dev->dev_private;
7178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7179 struct intel_unpin_work *work;
7180 struct drm_i915_gem_object *obj;
7181 struct drm_pending_vblank_event *e;
7182 struct timeval tnow, tvbl;
7183 unsigned long flags;
7184
7185 /* Ignore early vblank irqs */
7186 if (intel_crtc == NULL)
7187 return;
7188
7189 do_gettimeofday(&tnow);
7190
7191 spin_lock_irqsave(&dev->event_lock, flags);
7192 work = intel_crtc->unpin_work;
7193 if (work == NULL || !work->pending) {
7194 spin_unlock_irqrestore(&dev->event_lock, flags);
7195 return;
7196 }
7197
7198 intel_crtc->unpin_work = NULL;
7199
7200 if (work->event) {
7201 e = work->event;
7202 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7203
7204 /* Called before vblank count and timestamps have
7205 * been updated for the vblank interval of flip
7206 * completion? Need to increment vblank count and
7207 * add one videorefresh duration to returned timestamp
7208 * to account for this. We assume this happened if we
7209 * get called over 0.9 frame durations after the last
7210 * timestamped vblank.
7211 *
7212 * This calculation can not be used with vrefresh rates
7213 * below 5Hz (10Hz to be on the safe side) without
7214 * promoting to 64 integers.
7215 */
7216 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7217 9 * crtc->framedur_ns) {
7218 e->event.sequence++;
7219 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7220 crtc->framedur_ns);
7221 }
7222
7223 e->event.tv_sec = tvbl.tv_sec;
7224 e->event.tv_usec = tvbl.tv_usec;
7225
7226 list_add_tail(&e->base.link,
7227 &e->base.file_priv->event_list);
7228 wake_up_interruptible(&e->base.file_priv->event_wait);
7229 }
7230
7231 drm_vblank_put(dev, intel_crtc->pipe);
7232
7233 spin_unlock_irqrestore(&dev->event_lock, flags);
7234
7235 obj = work->old_fb_obj;
7236
7237 atomic_clear_mask(1 << intel_crtc->plane,
7238 &obj->pending_flip.counter);
7239 if (atomic_read(&obj->pending_flip) == 0)
7240 wake_up(&dev_priv->pending_flip_queue);
7241
7242 schedule_work(&work->work);
7243
7244 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7245 }
7246
7247 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7248 {
7249 drm_i915_private_t *dev_priv = dev->dev_private;
7250 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7251
7252 do_intel_finish_page_flip(dev, crtc);
7253 }
7254
7255 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7256 {
7257 drm_i915_private_t *dev_priv = dev->dev_private;
7258 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7259
7260 do_intel_finish_page_flip(dev, crtc);
7261 }
7262
7263 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7264 {
7265 drm_i915_private_t *dev_priv = dev->dev_private;
7266 struct intel_crtc *intel_crtc =
7267 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7268 unsigned long flags;
7269
7270 spin_lock_irqsave(&dev->event_lock, flags);
7271 if (intel_crtc->unpin_work) {
7272 if ((++intel_crtc->unpin_work->pending) > 1)
7273 DRM_ERROR("Prepared flip multiple times\n");
7274 } else {
7275 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7276 }
7277 spin_unlock_irqrestore(&dev->event_lock, flags);
7278 }
7279
7280 static int intel_gen2_queue_flip(struct drm_device *dev,
7281 struct drm_crtc *crtc,
7282 struct drm_framebuffer *fb,
7283 struct drm_i915_gem_object *obj)
7284 {
7285 struct drm_i915_private *dev_priv = dev->dev_private;
7286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7287 unsigned long offset;
7288 u32 flip_mask;
7289 int ret;
7290
7291 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7292 if (ret)
7293 goto out;
7294
7295 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7296 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7297
7298 ret = BEGIN_LP_RING(6);
7299 if (ret)
7300 goto out;
7301
7302 /* Can't queue multiple flips, so wait for the previous
7303 * one to finish before executing the next.
7304 */
7305 if (intel_crtc->plane)
7306 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7307 else
7308 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7309 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7310 OUT_RING(MI_NOOP);
7311 OUT_RING(MI_DISPLAY_FLIP |
7312 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7313 OUT_RING(fb->pitches[0]);
7314 OUT_RING(obj->gtt_offset + offset);
7315 OUT_RING(0); /* aux display base address, unused */
7316 ADVANCE_LP_RING();
7317 out:
7318 return ret;
7319 }
7320
7321 static int intel_gen3_queue_flip(struct drm_device *dev,
7322 struct drm_crtc *crtc,
7323 struct drm_framebuffer *fb,
7324 struct drm_i915_gem_object *obj)
7325 {
7326 struct drm_i915_private *dev_priv = dev->dev_private;
7327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7328 unsigned long offset;
7329 u32 flip_mask;
7330 int ret;
7331
7332 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7333 if (ret)
7334 goto out;
7335
7336 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7337 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7338
7339 ret = BEGIN_LP_RING(6);
7340 if (ret)
7341 goto out;
7342
7343 if (intel_crtc->plane)
7344 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7345 else
7346 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7347 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7348 OUT_RING(MI_NOOP);
7349 OUT_RING(MI_DISPLAY_FLIP_I915 |
7350 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7351 OUT_RING(fb->pitches[0]);
7352 OUT_RING(obj->gtt_offset + offset);
7353 OUT_RING(MI_NOOP);
7354
7355 ADVANCE_LP_RING();
7356 out:
7357 return ret;
7358 }
7359
7360 static int intel_gen4_queue_flip(struct drm_device *dev,
7361 struct drm_crtc *crtc,
7362 struct drm_framebuffer *fb,
7363 struct drm_i915_gem_object *obj)
7364 {
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7367 uint32_t pf, pipesrc;
7368 int ret;
7369
7370 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7371 if (ret)
7372 goto out;
7373
7374 ret = BEGIN_LP_RING(4);
7375 if (ret)
7376 goto out;
7377
7378 /* i965+ uses the linear or tiled offsets from the
7379 * Display Registers (which do not change across a page-flip)
7380 * so we need only reprogram the base address.
7381 */
7382 OUT_RING(MI_DISPLAY_FLIP |
7383 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7384 OUT_RING(fb->pitches[0]);
7385 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7386
7387 /* XXX Enabling the panel-fitter across page-flip is so far
7388 * untested on non-native modes, so ignore it for now.
7389 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7390 */
7391 pf = 0;
7392 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7393 OUT_RING(pf | pipesrc);
7394 ADVANCE_LP_RING();
7395 out:
7396 return ret;
7397 }
7398
7399 static int intel_gen6_queue_flip(struct drm_device *dev,
7400 struct drm_crtc *crtc,
7401 struct drm_framebuffer *fb,
7402 struct drm_i915_gem_object *obj)
7403 {
7404 struct drm_i915_private *dev_priv = dev->dev_private;
7405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7406 uint32_t pf, pipesrc;
7407 int ret;
7408
7409 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7410 if (ret)
7411 goto out;
7412
7413 ret = BEGIN_LP_RING(4);
7414 if (ret)
7415 goto out;
7416
7417 OUT_RING(MI_DISPLAY_FLIP |
7418 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7419 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7420 OUT_RING(obj->gtt_offset);
7421
7422 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7423 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7424 OUT_RING(pf | pipesrc);
7425 ADVANCE_LP_RING();
7426 out:
7427 return ret;
7428 }
7429
7430 /*
7431 * On gen7 we currently use the blit ring because (in early silicon at least)
7432 * the render ring doesn't give us interrpts for page flip completion, which
7433 * means clients will hang after the first flip is queued. Fortunately the
7434 * blit ring generates interrupts properly, so use it instead.
7435 */
7436 static int intel_gen7_queue_flip(struct drm_device *dev,
7437 struct drm_crtc *crtc,
7438 struct drm_framebuffer *fb,
7439 struct drm_i915_gem_object *obj)
7440 {
7441 struct drm_i915_private *dev_priv = dev->dev_private;
7442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7443 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7444 int ret;
7445
7446 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7447 if (ret)
7448 goto out;
7449
7450 ret = intel_ring_begin(ring, 4);
7451 if (ret)
7452 goto out;
7453
7454 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7455 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7456 intel_ring_emit(ring, (obj->gtt_offset));
7457 intel_ring_emit(ring, (MI_NOOP));
7458 intel_ring_advance(ring);
7459 out:
7460 return ret;
7461 }
7462
7463 static int intel_default_queue_flip(struct drm_device *dev,
7464 struct drm_crtc *crtc,
7465 struct drm_framebuffer *fb,
7466 struct drm_i915_gem_object *obj)
7467 {
7468 return -ENODEV;
7469 }
7470
7471 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7472 struct drm_framebuffer *fb,
7473 struct drm_pending_vblank_event *event)
7474 {
7475 struct drm_device *dev = crtc->dev;
7476 struct drm_i915_private *dev_priv = dev->dev_private;
7477 struct intel_framebuffer *intel_fb;
7478 struct drm_i915_gem_object *obj;
7479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7480 struct intel_unpin_work *work;
7481 unsigned long flags;
7482 int ret;
7483
7484 work = kzalloc(sizeof *work, GFP_KERNEL);
7485 if (work == NULL)
7486 return -ENOMEM;
7487
7488 work->event = event;
7489 work->dev = crtc->dev;
7490 intel_fb = to_intel_framebuffer(crtc->fb);
7491 work->old_fb_obj = intel_fb->obj;
7492 INIT_WORK(&work->work, intel_unpin_work_fn);
7493
7494 ret = drm_vblank_get(dev, intel_crtc->pipe);
7495 if (ret)
7496 goto free_work;
7497
7498 /* We borrow the event spin lock for protecting unpin_work */
7499 spin_lock_irqsave(&dev->event_lock, flags);
7500 if (intel_crtc->unpin_work) {
7501 spin_unlock_irqrestore(&dev->event_lock, flags);
7502 kfree(work);
7503 drm_vblank_put(dev, intel_crtc->pipe);
7504
7505 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7506 return -EBUSY;
7507 }
7508 intel_crtc->unpin_work = work;
7509 spin_unlock_irqrestore(&dev->event_lock, flags);
7510
7511 intel_fb = to_intel_framebuffer(fb);
7512 obj = intel_fb->obj;
7513
7514 mutex_lock(&dev->struct_mutex);
7515
7516 /* Reference the objects for the scheduled work. */
7517 drm_gem_object_reference(&work->old_fb_obj->base);
7518 drm_gem_object_reference(&obj->base);
7519
7520 crtc->fb = fb;
7521
7522 work->pending_flip_obj = obj;
7523
7524 work->enable_stall_check = true;
7525
7526 /* Block clients from rendering to the new back buffer until
7527 * the flip occurs and the object is no longer visible.
7528 */
7529 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7530
7531 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7532 if (ret)
7533 goto cleanup_pending;
7534
7535 intel_disable_fbc(dev);
7536 mutex_unlock(&dev->struct_mutex);
7537
7538 trace_i915_flip_request(intel_crtc->plane, obj);
7539
7540 return 0;
7541
7542 cleanup_pending:
7543 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7544 drm_gem_object_unreference(&work->old_fb_obj->base);
7545 drm_gem_object_unreference(&obj->base);
7546 mutex_unlock(&dev->struct_mutex);
7547
7548 spin_lock_irqsave(&dev->event_lock, flags);
7549 intel_crtc->unpin_work = NULL;
7550 spin_unlock_irqrestore(&dev->event_lock, flags);
7551
7552 drm_vblank_put(dev, intel_crtc->pipe);
7553 free_work:
7554 kfree(work);
7555
7556 return ret;
7557 }
7558
7559 static void intel_sanitize_modesetting(struct drm_device *dev,
7560 int pipe, int plane)
7561 {
7562 struct drm_i915_private *dev_priv = dev->dev_private;
7563 u32 reg, val;
7564
7565 if (HAS_PCH_SPLIT(dev))
7566 return;
7567
7568 /* Who knows what state these registers were left in by the BIOS or
7569 * grub?
7570 *
7571 * If we leave the registers in a conflicting state (e.g. with the
7572 * display plane reading from the other pipe than the one we intend
7573 * to use) then when we attempt to teardown the active mode, we will
7574 * not disable the pipes and planes in the correct order -- leaving
7575 * a plane reading from a disabled pipe and possibly leading to
7576 * undefined behaviour.
7577 */
7578
7579 reg = DSPCNTR(plane);
7580 val = I915_READ(reg);
7581
7582 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7583 return;
7584 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7585 return;
7586
7587 /* This display plane is active and attached to the other CPU pipe. */
7588 pipe = !pipe;
7589
7590 /* Disable the plane and wait for it to stop reading from the pipe. */
7591 intel_disable_plane(dev_priv, plane, pipe);
7592 intel_disable_pipe(dev_priv, pipe);
7593 }
7594
7595 static void intel_crtc_reset(struct drm_crtc *crtc)
7596 {
7597 struct drm_device *dev = crtc->dev;
7598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7599
7600 /* Reset flags back to the 'unknown' status so that they
7601 * will be correctly set on the initial modeset.
7602 */
7603 intel_crtc->dpms_mode = -1;
7604
7605 /* We need to fix up any BIOS configuration that conflicts with
7606 * our expectations.
7607 */
7608 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7609 }
7610
7611 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7612 .dpms = intel_crtc_dpms,
7613 .mode_fixup = intel_crtc_mode_fixup,
7614 .mode_set = intel_crtc_mode_set,
7615 .mode_set_base = intel_pipe_set_base,
7616 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7617 .load_lut = intel_crtc_load_lut,
7618 .disable = intel_crtc_disable,
7619 };
7620
7621 static const struct drm_crtc_funcs intel_crtc_funcs = {
7622 .reset = intel_crtc_reset,
7623 .cursor_set = intel_crtc_cursor_set,
7624 .cursor_move = intel_crtc_cursor_move,
7625 .gamma_set = intel_crtc_gamma_set,
7626 .set_config = drm_crtc_helper_set_config,
7627 .destroy = intel_crtc_destroy,
7628 .page_flip = intel_crtc_page_flip,
7629 };
7630
7631 static void intel_crtc_init(struct drm_device *dev, int pipe)
7632 {
7633 drm_i915_private_t *dev_priv = dev->dev_private;
7634 struct intel_crtc *intel_crtc;
7635 int i;
7636
7637 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7638 if (intel_crtc == NULL)
7639 return;
7640
7641 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7642
7643 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7644 for (i = 0; i < 256; i++) {
7645 intel_crtc->lut_r[i] = i;
7646 intel_crtc->lut_g[i] = i;
7647 intel_crtc->lut_b[i] = i;
7648 }
7649
7650 /* Swap pipes & planes for FBC on pre-965 */
7651 intel_crtc->pipe = pipe;
7652 intel_crtc->plane = pipe;
7653 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7654 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7655 intel_crtc->plane = !pipe;
7656 }
7657
7658 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7659 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7660 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7661 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7662
7663 intel_crtc_reset(&intel_crtc->base);
7664 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7665 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7666
7667 if (HAS_PCH_SPLIT(dev)) {
7668 if (pipe == 2 && IS_IVYBRIDGE(dev))
7669 intel_crtc->no_pll = true;
7670 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7671 intel_helper_funcs.commit = ironlake_crtc_commit;
7672 } else {
7673 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7674 intel_helper_funcs.commit = i9xx_crtc_commit;
7675 }
7676
7677 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7678
7679 intel_crtc->busy = false;
7680
7681 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7682 (unsigned long)intel_crtc);
7683 }
7684
7685 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7686 struct drm_file *file)
7687 {
7688 drm_i915_private_t *dev_priv = dev->dev_private;
7689 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7690 struct drm_mode_object *drmmode_obj;
7691 struct intel_crtc *crtc;
7692
7693 if (!dev_priv) {
7694 DRM_ERROR("called with no initialization\n");
7695 return -EINVAL;
7696 }
7697
7698 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7699 DRM_MODE_OBJECT_CRTC);
7700
7701 if (!drmmode_obj) {
7702 DRM_ERROR("no such CRTC id\n");
7703 return -EINVAL;
7704 }
7705
7706 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7707 pipe_from_crtc_id->pipe = crtc->pipe;
7708
7709 return 0;
7710 }
7711
7712 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7713 {
7714 struct intel_encoder *encoder;
7715 int index_mask = 0;
7716 int entry = 0;
7717
7718 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7719 if (type_mask & encoder->clone_mask)
7720 index_mask |= (1 << entry);
7721 entry++;
7722 }
7723
7724 return index_mask;
7725 }
7726
7727 static bool has_edp_a(struct drm_device *dev)
7728 {
7729 struct drm_i915_private *dev_priv = dev->dev_private;
7730
7731 if (!IS_MOBILE(dev))
7732 return false;
7733
7734 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7735 return false;
7736
7737 if (IS_GEN5(dev) &&
7738 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7739 return false;
7740
7741 return true;
7742 }
7743
7744 static void intel_setup_outputs(struct drm_device *dev)
7745 {
7746 struct drm_i915_private *dev_priv = dev->dev_private;
7747 struct intel_encoder *encoder;
7748 bool dpd_is_edp = false;
7749 bool has_lvds = false;
7750
7751 if (IS_MOBILE(dev) && !IS_I830(dev))
7752 has_lvds = intel_lvds_init(dev);
7753 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7754 /* disable the panel fitter on everything but LVDS */
7755 I915_WRITE(PFIT_CONTROL, 0);
7756 }
7757
7758 if (HAS_PCH_SPLIT(dev)) {
7759 dpd_is_edp = intel_dpd_is_edp(dev);
7760
7761 if (has_edp_a(dev))
7762 intel_dp_init(dev, DP_A);
7763
7764 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7765 intel_dp_init(dev, PCH_DP_D);
7766 }
7767
7768 intel_crt_init(dev);
7769
7770 if (HAS_PCH_SPLIT(dev)) {
7771 int found;
7772
7773 if (I915_READ(HDMIB) & PORT_DETECTED) {
7774 /* PCH SDVOB multiplex with HDMIB */
7775 found = intel_sdvo_init(dev, PCH_SDVOB);
7776 if (!found)
7777 intel_hdmi_init(dev, HDMIB);
7778 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7779 intel_dp_init(dev, PCH_DP_B);
7780 }
7781
7782 if (I915_READ(HDMIC) & PORT_DETECTED)
7783 intel_hdmi_init(dev, HDMIC);
7784
7785 if (I915_READ(HDMID) & PORT_DETECTED)
7786 intel_hdmi_init(dev, HDMID);
7787
7788 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7789 intel_dp_init(dev, PCH_DP_C);
7790
7791 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7792 intel_dp_init(dev, PCH_DP_D);
7793
7794 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7795 bool found = false;
7796
7797 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7798 DRM_DEBUG_KMS("probing SDVOB\n");
7799 found = intel_sdvo_init(dev, SDVOB);
7800 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7801 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7802 intel_hdmi_init(dev, SDVOB);
7803 }
7804
7805 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7806 DRM_DEBUG_KMS("probing DP_B\n");
7807 intel_dp_init(dev, DP_B);
7808 }
7809 }
7810
7811 /* Before G4X SDVOC doesn't have its own detect register */
7812
7813 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7814 DRM_DEBUG_KMS("probing SDVOC\n");
7815 found = intel_sdvo_init(dev, SDVOC);
7816 }
7817
7818 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7819
7820 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7821 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7822 intel_hdmi_init(dev, SDVOC);
7823 }
7824 if (SUPPORTS_INTEGRATED_DP(dev)) {
7825 DRM_DEBUG_KMS("probing DP_C\n");
7826 intel_dp_init(dev, DP_C);
7827 }
7828 }
7829
7830 if (SUPPORTS_INTEGRATED_DP(dev) &&
7831 (I915_READ(DP_D) & DP_DETECTED)) {
7832 DRM_DEBUG_KMS("probing DP_D\n");
7833 intel_dp_init(dev, DP_D);
7834 }
7835 } else if (IS_GEN2(dev))
7836 intel_dvo_init(dev);
7837
7838 if (SUPPORTS_TV(dev))
7839 intel_tv_init(dev);
7840
7841 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7842 encoder->base.possible_crtcs = encoder->crtc_mask;
7843 encoder->base.possible_clones =
7844 intel_encoder_clones(dev, encoder->clone_mask);
7845 }
7846
7847 /* disable all the possible outputs/crtcs before entering KMS mode */
7848 drm_helper_disable_unused_functions(dev);
7849
7850 if (HAS_PCH_SPLIT(dev))
7851 ironlake_init_pch_refclk(dev);
7852 }
7853
7854 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7855 {
7856 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7857
7858 drm_framebuffer_cleanup(fb);
7859 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7860
7861 kfree(intel_fb);
7862 }
7863
7864 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7865 struct drm_file *file,
7866 unsigned int *handle)
7867 {
7868 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7869 struct drm_i915_gem_object *obj = intel_fb->obj;
7870
7871 return drm_gem_handle_create(file, &obj->base, handle);
7872 }
7873
7874 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7875 .destroy = intel_user_framebuffer_destroy,
7876 .create_handle = intel_user_framebuffer_create_handle,
7877 };
7878
7879 int intel_framebuffer_init(struct drm_device *dev,
7880 struct intel_framebuffer *intel_fb,
7881 struct drm_mode_fb_cmd2 *mode_cmd,
7882 struct drm_i915_gem_object *obj)
7883 {
7884 int ret;
7885
7886 if (obj->tiling_mode == I915_TILING_Y)
7887 return -EINVAL;
7888
7889 if (mode_cmd->pitches[0] & 63)
7890 return -EINVAL;
7891
7892 switch (mode_cmd->pixel_format) {
7893 case DRM_FORMAT_RGB332:
7894 case DRM_FORMAT_RGB565:
7895 case DRM_FORMAT_XRGB8888:
7896 case DRM_FORMAT_ARGB8888:
7897 case DRM_FORMAT_XRGB2101010:
7898 case DRM_FORMAT_ARGB2101010:
7899 /* RGB formats are common across chipsets */
7900 break;
7901 case DRM_FORMAT_YUYV:
7902 case DRM_FORMAT_UYVY:
7903 case DRM_FORMAT_YVYU:
7904 case DRM_FORMAT_VYUY:
7905 break;
7906 default:
7907 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7908 mode_cmd->pixel_format);
7909 return -EINVAL;
7910 }
7911
7912 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7913 if (ret) {
7914 DRM_ERROR("framebuffer init failed %d\n", ret);
7915 return ret;
7916 }
7917
7918 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7919 intel_fb->obj = obj;
7920 return 0;
7921 }
7922
7923 static struct drm_framebuffer *
7924 intel_user_framebuffer_create(struct drm_device *dev,
7925 struct drm_file *filp,
7926 struct drm_mode_fb_cmd2 *mode_cmd)
7927 {
7928 struct drm_i915_gem_object *obj;
7929
7930 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7931 mode_cmd->handles[0]));
7932 if (&obj->base == NULL)
7933 return ERR_PTR(-ENOENT);
7934
7935 return intel_framebuffer_create(dev, mode_cmd, obj);
7936 }
7937
7938 static const struct drm_mode_config_funcs intel_mode_funcs = {
7939 .fb_create = intel_user_framebuffer_create,
7940 .output_poll_changed = intel_fb_output_poll_changed,
7941 };
7942
7943 static struct drm_i915_gem_object *
7944 intel_alloc_context_page(struct drm_device *dev)
7945 {
7946 struct drm_i915_gem_object *ctx;
7947 int ret;
7948
7949 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7950
7951 ctx = i915_gem_alloc_object(dev, 4096);
7952 if (!ctx) {
7953 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7954 return NULL;
7955 }
7956
7957 ret = i915_gem_object_pin(ctx, 4096, true);
7958 if (ret) {
7959 DRM_ERROR("failed to pin power context: %d\n", ret);
7960 goto err_unref;
7961 }
7962
7963 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7964 if (ret) {
7965 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7966 goto err_unpin;
7967 }
7968
7969 return ctx;
7970
7971 err_unpin:
7972 i915_gem_object_unpin(ctx);
7973 err_unref:
7974 drm_gem_object_unreference(&ctx->base);
7975 mutex_unlock(&dev->struct_mutex);
7976 return NULL;
7977 }
7978
7979 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7980 {
7981 struct drm_i915_private *dev_priv = dev->dev_private;
7982 u16 rgvswctl;
7983
7984 rgvswctl = I915_READ16(MEMSWCTL);
7985 if (rgvswctl & MEMCTL_CMD_STS) {
7986 DRM_DEBUG("gpu busy, RCS change rejected\n");
7987 return false; /* still busy with another command */
7988 }
7989
7990 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7991 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7992 I915_WRITE16(MEMSWCTL, rgvswctl);
7993 POSTING_READ16(MEMSWCTL);
7994
7995 rgvswctl |= MEMCTL_CMD_STS;
7996 I915_WRITE16(MEMSWCTL, rgvswctl);
7997
7998 return true;
7999 }
8000
8001 void ironlake_enable_drps(struct drm_device *dev)
8002 {
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 u32 rgvmodectl = I915_READ(MEMMODECTL);
8005 u8 fmax, fmin, fstart, vstart;
8006
8007 /* Enable temp reporting */
8008 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8009 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8010
8011 /* 100ms RC evaluation intervals */
8012 I915_WRITE(RCUPEI, 100000);
8013 I915_WRITE(RCDNEI, 100000);
8014
8015 /* Set max/min thresholds to 90ms and 80ms respectively */
8016 I915_WRITE(RCBMAXAVG, 90000);
8017 I915_WRITE(RCBMINAVG, 80000);
8018
8019 I915_WRITE(MEMIHYST, 1);
8020
8021 /* Set up min, max, and cur for interrupt handling */
8022 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8023 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8024 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8025 MEMMODE_FSTART_SHIFT;
8026
8027 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8028 PXVFREQ_PX_SHIFT;
8029
8030 dev_priv->fmax = fmax; /* IPS callback will increase this */
8031 dev_priv->fstart = fstart;
8032
8033 dev_priv->max_delay = fstart;
8034 dev_priv->min_delay = fmin;
8035 dev_priv->cur_delay = fstart;
8036
8037 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8038 fmax, fmin, fstart);
8039
8040 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8041
8042 /*
8043 * Interrupts will be enabled in ironlake_irq_postinstall
8044 */
8045
8046 I915_WRITE(VIDSTART, vstart);
8047 POSTING_READ(VIDSTART);
8048
8049 rgvmodectl |= MEMMODE_SWMODE_EN;
8050 I915_WRITE(MEMMODECTL, rgvmodectl);
8051
8052 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8053 DRM_ERROR("stuck trying to change perf mode\n");
8054 msleep(1);
8055
8056 ironlake_set_drps(dev, fstart);
8057
8058 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8059 I915_READ(0x112e0);
8060 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8061 dev_priv->last_count2 = I915_READ(0x112f4);
8062 getrawmonotonic(&dev_priv->last_time2);
8063 }
8064
8065 void ironlake_disable_drps(struct drm_device *dev)
8066 {
8067 struct drm_i915_private *dev_priv = dev->dev_private;
8068 u16 rgvswctl = I915_READ16(MEMSWCTL);
8069
8070 /* Ack interrupts, disable EFC interrupt */
8071 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8072 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8073 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8074 I915_WRITE(DEIIR, DE_PCU_EVENT);
8075 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8076
8077 /* Go back to the starting frequency */
8078 ironlake_set_drps(dev, dev_priv->fstart);
8079 msleep(1);
8080 rgvswctl |= MEMCTL_CMD_STS;
8081 I915_WRITE(MEMSWCTL, rgvswctl);
8082 msleep(1);
8083
8084 }
8085
8086 void gen6_set_rps(struct drm_device *dev, u8 val)
8087 {
8088 struct drm_i915_private *dev_priv = dev->dev_private;
8089 u32 swreq;
8090
8091 swreq = (val & 0x3ff) << 25;
8092 I915_WRITE(GEN6_RPNSWREQ, swreq);
8093 }
8094
8095 void gen6_disable_rps(struct drm_device *dev)
8096 {
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098
8099 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8100 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8101 I915_WRITE(GEN6_PMIER, 0);
8102 /* Complete PM interrupt masking here doesn't race with the rps work
8103 * item again unmasking PM interrupts because that is using a different
8104 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8105 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8106
8107 spin_lock_irq(&dev_priv->rps_lock);
8108 dev_priv->pm_iir = 0;
8109 spin_unlock_irq(&dev_priv->rps_lock);
8110
8111 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8112 }
8113
8114 static unsigned long intel_pxfreq(u32 vidfreq)
8115 {
8116 unsigned long freq;
8117 int div = (vidfreq & 0x3f0000) >> 16;
8118 int post = (vidfreq & 0x3000) >> 12;
8119 int pre = (vidfreq & 0x7);
8120
8121 if (!pre)
8122 return 0;
8123
8124 freq = ((div * 133333) / ((1<<post) * pre));
8125
8126 return freq;
8127 }
8128
8129 void intel_init_emon(struct drm_device *dev)
8130 {
8131 struct drm_i915_private *dev_priv = dev->dev_private;
8132 u32 lcfuse;
8133 u8 pxw[16];
8134 int i;
8135
8136 /* Disable to program */
8137 I915_WRITE(ECR, 0);
8138 POSTING_READ(ECR);
8139
8140 /* Program energy weights for various events */
8141 I915_WRITE(SDEW, 0x15040d00);
8142 I915_WRITE(CSIEW0, 0x007f0000);
8143 I915_WRITE(CSIEW1, 0x1e220004);
8144 I915_WRITE(CSIEW2, 0x04000004);
8145
8146 for (i = 0; i < 5; i++)
8147 I915_WRITE(PEW + (i * 4), 0);
8148 for (i = 0; i < 3; i++)
8149 I915_WRITE(DEW + (i * 4), 0);
8150
8151 /* Program P-state weights to account for frequency power adjustment */
8152 for (i = 0; i < 16; i++) {
8153 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8154 unsigned long freq = intel_pxfreq(pxvidfreq);
8155 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8156 PXVFREQ_PX_SHIFT;
8157 unsigned long val;
8158
8159 val = vid * vid;
8160 val *= (freq / 1000);
8161 val *= 255;
8162 val /= (127*127*900);
8163 if (val > 0xff)
8164 DRM_ERROR("bad pxval: %ld\n", val);
8165 pxw[i] = val;
8166 }
8167 /* Render standby states get 0 weight */
8168 pxw[14] = 0;
8169 pxw[15] = 0;
8170
8171 for (i = 0; i < 4; i++) {
8172 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8173 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8174 I915_WRITE(PXW + (i * 4), val);
8175 }
8176
8177 /* Adjust magic regs to magic values (more experimental results) */
8178 I915_WRITE(OGW0, 0);
8179 I915_WRITE(OGW1, 0);
8180 I915_WRITE(EG0, 0x00007f00);
8181 I915_WRITE(EG1, 0x0000000e);
8182 I915_WRITE(EG2, 0x000e0000);
8183 I915_WRITE(EG3, 0x68000300);
8184 I915_WRITE(EG4, 0x42000000);
8185 I915_WRITE(EG5, 0x00140031);
8186 I915_WRITE(EG6, 0);
8187 I915_WRITE(EG7, 0);
8188
8189 for (i = 0; i < 8; i++)
8190 I915_WRITE(PXWL + (i * 4), 0);
8191
8192 /* Enable PMON + select events */
8193 I915_WRITE(ECR, 0x80000019);
8194
8195 lcfuse = I915_READ(LCFUSE02);
8196
8197 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8198 }
8199
8200 static bool intel_enable_rc6(struct drm_device *dev)
8201 {
8202 /*
8203 * Respect the kernel parameter if it is set
8204 */
8205 if (i915_enable_rc6 >= 0)
8206 return i915_enable_rc6;
8207
8208 /*
8209 * Disable RC6 on Ironlake
8210 */
8211 if (INTEL_INFO(dev)->gen == 5)
8212 return 0;
8213
8214 /*
8215 * Disable rc6 on Sandybridge
8216 */
8217 if (INTEL_INFO(dev)->gen == 6) {
8218 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8219 return 0;
8220 }
8221 DRM_DEBUG_DRIVER("RC6 enabled\n");
8222 return 1;
8223 }
8224
8225 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8226 {
8227 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8228 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8229 u32 pcu_mbox, rc6_mask = 0;
8230 int cur_freq, min_freq, max_freq;
8231 int i;
8232
8233 /* Here begins a magic sequence of register writes to enable
8234 * auto-downclocking.
8235 *
8236 * Perhaps there might be some value in exposing these to
8237 * userspace...
8238 */
8239 I915_WRITE(GEN6_RC_STATE, 0);
8240 mutex_lock(&dev_priv->dev->struct_mutex);
8241 gen6_gt_force_wake_get(dev_priv);
8242
8243 /* disable the counters and set deterministic thresholds */
8244 I915_WRITE(GEN6_RC_CONTROL, 0);
8245
8246 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8247 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8248 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8249 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8250 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8251
8252 for (i = 0; i < I915_NUM_RINGS; i++)
8253 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8254
8255 I915_WRITE(GEN6_RC_SLEEP, 0);
8256 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8257 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8258 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8259 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8260
8261 if (intel_enable_rc6(dev_priv->dev))
8262 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8263 GEN6_RC_CTL_RC6_ENABLE;
8264
8265 I915_WRITE(GEN6_RC_CONTROL,
8266 rc6_mask |
8267 GEN6_RC_CTL_EI_MODE(1) |
8268 GEN6_RC_CTL_HW_ENABLE);
8269
8270 I915_WRITE(GEN6_RPNSWREQ,
8271 GEN6_FREQUENCY(10) |
8272 GEN6_OFFSET(0) |
8273 GEN6_AGGRESSIVE_TURBO);
8274 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8275 GEN6_FREQUENCY(12));
8276
8277 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8278 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8279 18 << 24 |
8280 6 << 16);
8281 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8282 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8283 I915_WRITE(GEN6_RP_UP_EI, 100000);
8284 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8285 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8286 I915_WRITE(GEN6_RP_CONTROL,
8287 GEN6_RP_MEDIA_TURBO |
8288 GEN6_RP_MEDIA_HW_MODE |
8289 GEN6_RP_MEDIA_IS_GFX |
8290 GEN6_RP_ENABLE |
8291 GEN6_RP_UP_BUSY_AVG |
8292 GEN6_RP_DOWN_IDLE_CONT);
8293
8294 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8295 500))
8296 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8297
8298 I915_WRITE(GEN6_PCODE_DATA, 0);
8299 I915_WRITE(GEN6_PCODE_MAILBOX,
8300 GEN6_PCODE_READY |
8301 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8302 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8303 500))
8304 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8305
8306 min_freq = (rp_state_cap & 0xff0000) >> 16;
8307 max_freq = rp_state_cap & 0xff;
8308 cur_freq = (gt_perf_status & 0xff00) >> 8;
8309
8310 /* Check for overclock support */
8311 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8312 500))
8313 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8314 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8315 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8316 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8317 500))
8318 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8319 if (pcu_mbox & (1<<31)) { /* OC supported */
8320 max_freq = pcu_mbox & 0xff;
8321 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8322 }
8323
8324 /* In units of 100MHz */
8325 dev_priv->max_delay = max_freq;
8326 dev_priv->min_delay = min_freq;
8327 dev_priv->cur_delay = cur_freq;
8328
8329 /* requires MSI enabled */
8330 I915_WRITE(GEN6_PMIER,
8331 GEN6_PM_MBOX_EVENT |
8332 GEN6_PM_THERMAL_EVENT |
8333 GEN6_PM_RP_DOWN_TIMEOUT |
8334 GEN6_PM_RP_UP_THRESHOLD |
8335 GEN6_PM_RP_DOWN_THRESHOLD |
8336 GEN6_PM_RP_UP_EI_EXPIRED |
8337 GEN6_PM_RP_DOWN_EI_EXPIRED);
8338 spin_lock_irq(&dev_priv->rps_lock);
8339 WARN_ON(dev_priv->pm_iir != 0);
8340 I915_WRITE(GEN6_PMIMR, 0);
8341 spin_unlock_irq(&dev_priv->rps_lock);
8342 /* enable all PM interrupts */
8343 I915_WRITE(GEN6_PMINTRMSK, 0);
8344
8345 gen6_gt_force_wake_put(dev_priv);
8346 mutex_unlock(&dev_priv->dev->struct_mutex);
8347 }
8348
8349 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8350 {
8351 int min_freq = 15;
8352 int gpu_freq, ia_freq, max_ia_freq;
8353 int scaling_factor = 180;
8354
8355 max_ia_freq = cpufreq_quick_get_max(0);
8356 /*
8357 * Default to measured freq if none found, PCU will ensure we don't go
8358 * over
8359 */
8360 if (!max_ia_freq)
8361 max_ia_freq = tsc_khz;
8362
8363 /* Convert from kHz to MHz */
8364 max_ia_freq /= 1000;
8365
8366 mutex_lock(&dev_priv->dev->struct_mutex);
8367
8368 /*
8369 * For each potential GPU frequency, load a ring frequency we'd like
8370 * to use for memory access. We do this by specifying the IA frequency
8371 * the PCU should use as a reference to determine the ring frequency.
8372 */
8373 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8374 gpu_freq--) {
8375 int diff = dev_priv->max_delay - gpu_freq;
8376
8377 /*
8378 * For GPU frequencies less than 750MHz, just use the lowest
8379 * ring freq.
8380 */
8381 if (gpu_freq < min_freq)
8382 ia_freq = 800;
8383 else
8384 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8385 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8386
8387 I915_WRITE(GEN6_PCODE_DATA,
8388 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8389 gpu_freq);
8390 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8391 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8392 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8393 GEN6_PCODE_READY) == 0, 10)) {
8394 DRM_ERROR("pcode write of freq table timed out\n");
8395 continue;
8396 }
8397 }
8398
8399 mutex_unlock(&dev_priv->dev->struct_mutex);
8400 }
8401
8402 static void ironlake_init_clock_gating(struct drm_device *dev)
8403 {
8404 struct drm_i915_private *dev_priv = dev->dev_private;
8405 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8406
8407 /* Required for FBC */
8408 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8409 DPFCRUNIT_CLOCK_GATE_DISABLE |
8410 DPFDUNIT_CLOCK_GATE_DISABLE;
8411 /* Required for CxSR */
8412 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8413
8414 I915_WRITE(PCH_3DCGDIS0,
8415 MARIUNIT_CLOCK_GATE_DISABLE |
8416 SVSMUNIT_CLOCK_GATE_DISABLE);
8417 I915_WRITE(PCH_3DCGDIS1,
8418 VFMUNIT_CLOCK_GATE_DISABLE);
8419
8420 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8421
8422 /*
8423 * According to the spec the following bits should be set in
8424 * order to enable memory self-refresh
8425 * The bit 22/21 of 0x42004
8426 * The bit 5 of 0x42020
8427 * The bit 15 of 0x45000
8428 */
8429 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8430 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8431 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8432 I915_WRITE(ILK_DSPCLK_GATE,
8433 (I915_READ(ILK_DSPCLK_GATE) |
8434 ILK_DPARB_CLK_GATE));
8435 I915_WRITE(DISP_ARB_CTL,
8436 (I915_READ(DISP_ARB_CTL) |
8437 DISP_FBC_WM_DIS));
8438 I915_WRITE(WM3_LP_ILK, 0);
8439 I915_WRITE(WM2_LP_ILK, 0);
8440 I915_WRITE(WM1_LP_ILK, 0);
8441
8442 /*
8443 * Based on the document from hardware guys the following bits
8444 * should be set unconditionally in order to enable FBC.
8445 * The bit 22 of 0x42000
8446 * The bit 22 of 0x42004
8447 * The bit 7,8,9 of 0x42020.
8448 */
8449 if (IS_IRONLAKE_M(dev)) {
8450 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8451 I915_READ(ILK_DISPLAY_CHICKEN1) |
8452 ILK_FBCQ_DIS);
8453 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8454 I915_READ(ILK_DISPLAY_CHICKEN2) |
8455 ILK_DPARB_GATE);
8456 I915_WRITE(ILK_DSPCLK_GATE,
8457 I915_READ(ILK_DSPCLK_GATE) |
8458 ILK_DPFC_DIS1 |
8459 ILK_DPFC_DIS2 |
8460 ILK_CLK_FBC);
8461 }
8462
8463 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8464 I915_READ(ILK_DISPLAY_CHICKEN2) |
8465 ILK_ELPIN_409_SELECT);
8466 I915_WRITE(_3D_CHICKEN2,
8467 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8468 _3D_CHICKEN2_WM_READ_PIPELINED);
8469 }
8470
8471 static void gen6_init_clock_gating(struct drm_device *dev)
8472 {
8473 struct drm_i915_private *dev_priv = dev->dev_private;
8474 int pipe;
8475 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8476
8477 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8478
8479 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8480 I915_READ(ILK_DISPLAY_CHICKEN2) |
8481 ILK_ELPIN_409_SELECT);
8482
8483 I915_WRITE(WM3_LP_ILK, 0);
8484 I915_WRITE(WM2_LP_ILK, 0);
8485 I915_WRITE(WM1_LP_ILK, 0);
8486
8487 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8488 * gating disable must be set. Failure to set it results in
8489 * flickering pixels due to Z write ordering failures after
8490 * some amount of runtime in the Mesa "fire" demo, and Unigine
8491 * Sanctuary and Tropics, and apparently anything else with
8492 * alpha test or pixel discard.
8493 *
8494 * According to the spec, bit 11 (RCCUNIT) must also be set,
8495 * but we didn't debug actual testcases to find it out.
8496 */
8497 I915_WRITE(GEN6_UCGCTL2,
8498 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8499 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8500
8501 /*
8502 * According to the spec the following bits should be
8503 * set in order to enable memory self-refresh and fbc:
8504 * The bit21 and bit22 of 0x42000
8505 * The bit21 and bit22 of 0x42004
8506 * The bit5 and bit7 of 0x42020
8507 * The bit14 of 0x70180
8508 * The bit14 of 0x71180
8509 */
8510 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8511 I915_READ(ILK_DISPLAY_CHICKEN1) |
8512 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8513 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8514 I915_READ(ILK_DISPLAY_CHICKEN2) |
8515 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8516 I915_WRITE(ILK_DSPCLK_GATE,
8517 I915_READ(ILK_DSPCLK_GATE) |
8518 ILK_DPARB_CLK_GATE |
8519 ILK_DPFD_CLK_GATE);
8520
8521 for_each_pipe(pipe) {
8522 I915_WRITE(DSPCNTR(pipe),
8523 I915_READ(DSPCNTR(pipe)) |
8524 DISPPLANE_TRICKLE_FEED_DISABLE);
8525 intel_flush_display_plane(dev_priv, pipe);
8526 }
8527 }
8528
8529 static void ivybridge_init_clock_gating(struct drm_device *dev)
8530 {
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532 int pipe;
8533 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8534
8535 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8536
8537 I915_WRITE(WM3_LP_ILK, 0);
8538 I915_WRITE(WM2_LP_ILK, 0);
8539 I915_WRITE(WM1_LP_ILK, 0);
8540
8541 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8542
8543 I915_WRITE(IVB_CHICKEN3,
8544 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8545 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8546
8547 for_each_pipe(pipe) {
8548 I915_WRITE(DSPCNTR(pipe),
8549 I915_READ(DSPCNTR(pipe)) |
8550 DISPPLANE_TRICKLE_FEED_DISABLE);
8551 intel_flush_display_plane(dev_priv, pipe);
8552 }
8553 }
8554
8555 static void g4x_init_clock_gating(struct drm_device *dev)
8556 {
8557 struct drm_i915_private *dev_priv = dev->dev_private;
8558 uint32_t dspclk_gate;
8559
8560 I915_WRITE(RENCLK_GATE_D1, 0);
8561 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8562 GS_UNIT_CLOCK_GATE_DISABLE |
8563 CL_UNIT_CLOCK_GATE_DISABLE);
8564 I915_WRITE(RAMCLK_GATE_D, 0);
8565 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8566 OVRUNIT_CLOCK_GATE_DISABLE |
8567 OVCUNIT_CLOCK_GATE_DISABLE;
8568 if (IS_GM45(dev))
8569 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8570 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8571 }
8572
8573 static void crestline_init_clock_gating(struct drm_device *dev)
8574 {
8575 struct drm_i915_private *dev_priv = dev->dev_private;
8576
8577 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8578 I915_WRITE(RENCLK_GATE_D2, 0);
8579 I915_WRITE(DSPCLK_GATE_D, 0);
8580 I915_WRITE(RAMCLK_GATE_D, 0);
8581 I915_WRITE16(DEUC, 0);
8582 }
8583
8584 static void broadwater_init_clock_gating(struct drm_device *dev)
8585 {
8586 struct drm_i915_private *dev_priv = dev->dev_private;
8587
8588 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8589 I965_RCC_CLOCK_GATE_DISABLE |
8590 I965_RCPB_CLOCK_GATE_DISABLE |
8591 I965_ISC_CLOCK_GATE_DISABLE |
8592 I965_FBC_CLOCK_GATE_DISABLE);
8593 I915_WRITE(RENCLK_GATE_D2, 0);
8594 }
8595
8596 static void gen3_init_clock_gating(struct drm_device *dev)
8597 {
8598 struct drm_i915_private *dev_priv = dev->dev_private;
8599 u32 dstate = I915_READ(D_STATE);
8600
8601 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8602 DSTATE_DOT_CLOCK_GATING;
8603 I915_WRITE(D_STATE, dstate);
8604 }
8605
8606 static void i85x_init_clock_gating(struct drm_device *dev)
8607 {
8608 struct drm_i915_private *dev_priv = dev->dev_private;
8609
8610 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8611 }
8612
8613 static void i830_init_clock_gating(struct drm_device *dev)
8614 {
8615 struct drm_i915_private *dev_priv = dev->dev_private;
8616
8617 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8618 }
8619
8620 static void ibx_init_clock_gating(struct drm_device *dev)
8621 {
8622 struct drm_i915_private *dev_priv = dev->dev_private;
8623
8624 /*
8625 * On Ibex Peak and Cougar Point, we need to disable clock
8626 * gating for the panel power sequencer or it will fail to
8627 * start up when no ports are active.
8628 */
8629 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8630 }
8631
8632 static void cpt_init_clock_gating(struct drm_device *dev)
8633 {
8634 struct drm_i915_private *dev_priv = dev->dev_private;
8635 int pipe;
8636
8637 /*
8638 * On Ibex Peak and Cougar Point, we need to disable clock
8639 * gating for the panel power sequencer or it will fail to
8640 * start up when no ports are active.
8641 */
8642 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8643 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8644 DPLS_EDP_PPS_FIX_DIS);
8645 /* Without this, mode sets may fail silently on FDI */
8646 for_each_pipe(pipe)
8647 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8648 }
8649
8650 static void ironlake_teardown_rc6(struct drm_device *dev)
8651 {
8652 struct drm_i915_private *dev_priv = dev->dev_private;
8653
8654 if (dev_priv->renderctx) {
8655 i915_gem_object_unpin(dev_priv->renderctx);
8656 drm_gem_object_unreference(&dev_priv->renderctx->base);
8657 dev_priv->renderctx = NULL;
8658 }
8659
8660 if (dev_priv->pwrctx) {
8661 i915_gem_object_unpin(dev_priv->pwrctx);
8662 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8663 dev_priv->pwrctx = NULL;
8664 }
8665 }
8666
8667 static void ironlake_disable_rc6(struct drm_device *dev)
8668 {
8669 struct drm_i915_private *dev_priv = dev->dev_private;
8670
8671 if (I915_READ(PWRCTXA)) {
8672 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8673 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8674 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8675 50);
8676
8677 I915_WRITE(PWRCTXA, 0);
8678 POSTING_READ(PWRCTXA);
8679
8680 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8681 POSTING_READ(RSTDBYCTL);
8682 }
8683
8684 ironlake_teardown_rc6(dev);
8685 }
8686
8687 static int ironlake_setup_rc6(struct drm_device *dev)
8688 {
8689 struct drm_i915_private *dev_priv = dev->dev_private;
8690
8691 if (dev_priv->renderctx == NULL)
8692 dev_priv->renderctx = intel_alloc_context_page(dev);
8693 if (!dev_priv->renderctx)
8694 return -ENOMEM;
8695
8696 if (dev_priv->pwrctx == NULL)
8697 dev_priv->pwrctx = intel_alloc_context_page(dev);
8698 if (!dev_priv->pwrctx) {
8699 ironlake_teardown_rc6(dev);
8700 return -ENOMEM;
8701 }
8702
8703 return 0;
8704 }
8705
8706 void ironlake_enable_rc6(struct drm_device *dev)
8707 {
8708 struct drm_i915_private *dev_priv = dev->dev_private;
8709 int ret;
8710
8711 /* rc6 disabled by default due to repeated reports of hanging during
8712 * boot and resume.
8713 */
8714 if (!intel_enable_rc6(dev))
8715 return;
8716
8717 mutex_lock(&dev->struct_mutex);
8718 ret = ironlake_setup_rc6(dev);
8719 if (ret) {
8720 mutex_unlock(&dev->struct_mutex);
8721 return;
8722 }
8723
8724 /*
8725 * GPU can automatically power down the render unit if given a page
8726 * to save state.
8727 */
8728 ret = BEGIN_LP_RING(6);
8729 if (ret) {
8730 ironlake_teardown_rc6(dev);
8731 mutex_unlock(&dev->struct_mutex);
8732 return;
8733 }
8734
8735 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8736 OUT_RING(MI_SET_CONTEXT);
8737 OUT_RING(dev_priv->renderctx->gtt_offset |
8738 MI_MM_SPACE_GTT |
8739 MI_SAVE_EXT_STATE_EN |
8740 MI_RESTORE_EXT_STATE_EN |
8741 MI_RESTORE_INHIBIT);
8742 OUT_RING(MI_SUSPEND_FLUSH);
8743 OUT_RING(MI_NOOP);
8744 OUT_RING(MI_FLUSH);
8745 ADVANCE_LP_RING();
8746
8747 /*
8748 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8749 * does an implicit flush, combined with MI_FLUSH above, it should be
8750 * safe to assume that renderctx is valid
8751 */
8752 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8753 if (ret) {
8754 DRM_ERROR("failed to enable ironlake power power savings\n");
8755 ironlake_teardown_rc6(dev);
8756 mutex_unlock(&dev->struct_mutex);
8757 return;
8758 }
8759
8760 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8761 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8762 mutex_unlock(&dev->struct_mutex);
8763 }
8764
8765 void intel_init_clock_gating(struct drm_device *dev)
8766 {
8767 struct drm_i915_private *dev_priv = dev->dev_private;
8768
8769 dev_priv->display.init_clock_gating(dev);
8770
8771 if (dev_priv->display.init_pch_clock_gating)
8772 dev_priv->display.init_pch_clock_gating(dev);
8773 }
8774
8775 /* Set up chip specific display functions */
8776 static void intel_init_display(struct drm_device *dev)
8777 {
8778 struct drm_i915_private *dev_priv = dev->dev_private;
8779
8780 /* We always want a DPMS function */
8781 if (HAS_PCH_SPLIT(dev)) {
8782 dev_priv->display.dpms = ironlake_crtc_dpms;
8783 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8784 dev_priv->display.update_plane = ironlake_update_plane;
8785 } else {
8786 dev_priv->display.dpms = i9xx_crtc_dpms;
8787 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8788 dev_priv->display.update_plane = i9xx_update_plane;
8789 }
8790
8791 if (I915_HAS_FBC(dev)) {
8792 if (HAS_PCH_SPLIT(dev)) {
8793 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8794 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8795 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8796 } else if (IS_GM45(dev)) {
8797 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8798 dev_priv->display.enable_fbc = g4x_enable_fbc;
8799 dev_priv->display.disable_fbc = g4x_disable_fbc;
8800 } else if (IS_CRESTLINE(dev)) {
8801 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8802 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8803 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8804 }
8805 /* 855GM needs testing */
8806 }
8807
8808 /* Returns the core display clock speed */
8809 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8810 dev_priv->display.get_display_clock_speed =
8811 i945_get_display_clock_speed;
8812 else if (IS_I915G(dev))
8813 dev_priv->display.get_display_clock_speed =
8814 i915_get_display_clock_speed;
8815 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8816 dev_priv->display.get_display_clock_speed =
8817 i9xx_misc_get_display_clock_speed;
8818 else if (IS_I915GM(dev))
8819 dev_priv->display.get_display_clock_speed =
8820 i915gm_get_display_clock_speed;
8821 else if (IS_I865G(dev))
8822 dev_priv->display.get_display_clock_speed =
8823 i865_get_display_clock_speed;
8824 else if (IS_I85X(dev))
8825 dev_priv->display.get_display_clock_speed =
8826 i855_get_display_clock_speed;
8827 else /* 852, 830 */
8828 dev_priv->display.get_display_clock_speed =
8829 i830_get_display_clock_speed;
8830
8831 /* For FIFO watermark updates */
8832 if (HAS_PCH_SPLIT(dev)) {
8833 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8834 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8835
8836 /* IVB configs may use multi-threaded forcewake */
8837 if (IS_IVYBRIDGE(dev)) {
8838 u32 ecobus;
8839
8840 /* A small trick here - if the bios hasn't configured MT forcewake,
8841 * and if the device is in RC6, then force_wake_mt_get will not wake
8842 * the device and the ECOBUS read will return zero. Which will be
8843 * (correctly) interpreted by the test below as MT forcewake being
8844 * disabled.
8845 */
8846 mutex_lock(&dev->struct_mutex);
8847 __gen6_gt_force_wake_mt_get(dev_priv);
8848 ecobus = I915_READ_NOTRACE(ECOBUS);
8849 __gen6_gt_force_wake_mt_put(dev_priv);
8850 mutex_unlock(&dev->struct_mutex);
8851
8852 if (ecobus & FORCEWAKE_MT_ENABLE) {
8853 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8854 dev_priv->display.force_wake_get =
8855 __gen6_gt_force_wake_mt_get;
8856 dev_priv->display.force_wake_put =
8857 __gen6_gt_force_wake_mt_put;
8858 }
8859 }
8860
8861 if (HAS_PCH_IBX(dev))
8862 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8863 else if (HAS_PCH_CPT(dev))
8864 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8865
8866 if (IS_GEN5(dev)) {
8867 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8868 dev_priv->display.update_wm = ironlake_update_wm;
8869 else {
8870 DRM_DEBUG_KMS("Failed to get proper latency. "
8871 "Disable CxSR\n");
8872 dev_priv->display.update_wm = NULL;
8873 }
8874 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8875 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8876 dev_priv->display.write_eld = ironlake_write_eld;
8877 } else if (IS_GEN6(dev)) {
8878 if (SNB_READ_WM0_LATENCY()) {
8879 dev_priv->display.update_wm = sandybridge_update_wm;
8880 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8881 } else {
8882 DRM_DEBUG_KMS("Failed to read display plane latency. "
8883 "Disable CxSR\n");
8884 dev_priv->display.update_wm = NULL;
8885 }
8886 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8887 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8888 dev_priv->display.write_eld = ironlake_write_eld;
8889 } else if (IS_IVYBRIDGE(dev)) {
8890 /* FIXME: detect B0+ stepping and use auto training */
8891 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8892 if (SNB_READ_WM0_LATENCY()) {
8893 dev_priv->display.update_wm = sandybridge_update_wm;
8894 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8895 } else {
8896 DRM_DEBUG_KMS("Failed to read display plane latency. "
8897 "Disable CxSR\n");
8898 dev_priv->display.update_wm = NULL;
8899 }
8900 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8901 dev_priv->display.write_eld = ironlake_write_eld;
8902 } else
8903 dev_priv->display.update_wm = NULL;
8904 } else if (IS_PINEVIEW(dev)) {
8905 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8906 dev_priv->is_ddr3,
8907 dev_priv->fsb_freq,
8908 dev_priv->mem_freq)) {
8909 DRM_INFO("failed to find known CxSR latency "
8910 "(found ddr%s fsb freq %d, mem freq %d), "
8911 "disabling CxSR\n",
8912 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8913 dev_priv->fsb_freq, dev_priv->mem_freq);
8914 /* Disable CxSR and never update its watermark again */
8915 pineview_disable_cxsr(dev);
8916 dev_priv->display.update_wm = NULL;
8917 } else
8918 dev_priv->display.update_wm = pineview_update_wm;
8919 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8920 } else if (IS_G4X(dev)) {
8921 dev_priv->display.write_eld = g4x_write_eld;
8922 dev_priv->display.update_wm = g4x_update_wm;
8923 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8924 } else if (IS_GEN4(dev)) {
8925 dev_priv->display.update_wm = i965_update_wm;
8926 if (IS_CRESTLINE(dev))
8927 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8928 else if (IS_BROADWATER(dev))
8929 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8930 } else if (IS_GEN3(dev)) {
8931 dev_priv->display.update_wm = i9xx_update_wm;
8932 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8933 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8934 } else if (IS_I865G(dev)) {
8935 dev_priv->display.update_wm = i830_update_wm;
8936 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8937 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8938 } else if (IS_I85X(dev)) {
8939 dev_priv->display.update_wm = i9xx_update_wm;
8940 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8941 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8942 } else {
8943 dev_priv->display.update_wm = i830_update_wm;
8944 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8945 if (IS_845G(dev))
8946 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8947 else
8948 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8949 }
8950
8951 /* Default just returns -ENODEV to indicate unsupported */
8952 dev_priv->display.queue_flip = intel_default_queue_flip;
8953
8954 switch (INTEL_INFO(dev)->gen) {
8955 case 2:
8956 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8957 break;
8958
8959 case 3:
8960 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8961 break;
8962
8963 case 4:
8964 case 5:
8965 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8966 break;
8967
8968 case 6:
8969 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8970 break;
8971 case 7:
8972 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8973 break;
8974 }
8975 }
8976
8977 /*
8978 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8979 * resume, or other times. This quirk makes sure that's the case for
8980 * affected systems.
8981 */
8982 static void quirk_pipea_force(struct drm_device *dev)
8983 {
8984 struct drm_i915_private *dev_priv = dev->dev_private;
8985
8986 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8987 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8988 }
8989
8990 /*
8991 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8992 */
8993 static void quirk_ssc_force_disable(struct drm_device *dev)
8994 {
8995 struct drm_i915_private *dev_priv = dev->dev_private;
8996 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8997 }
8998
8999 struct intel_quirk {
9000 int device;
9001 int subsystem_vendor;
9002 int subsystem_device;
9003 void (*hook)(struct drm_device *dev);
9004 };
9005
9006 struct intel_quirk intel_quirks[] = {
9007 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
9008 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
9009 /* HP Mini needs pipe A force quirk (LP: #322104) */
9010 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9011
9012 /* Thinkpad R31 needs pipe A force quirk */
9013 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9014 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9015 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9016
9017 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9018 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9019 /* ThinkPad X40 needs pipe A force quirk */
9020
9021 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9022 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9023
9024 /* 855 & before need to leave pipe A & dpll A up */
9025 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9026 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9027
9028 /* Lenovo U160 cannot use SSC on LVDS */
9029 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9030
9031 /* Sony Vaio Y cannot use SSC on LVDS */
9032 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9033 };
9034
9035 static void intel_init_quirks(struct drm_device *dev)
9036 {
9037 struct pci_dev *d = dev->pdev;
9038 int i;
9039
9040 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9041 struct intel_quirk *q = &intel_quirks[i];
9042
9043 if (d->device == q->device &&
9044 (d->subsystem_vendor == q->subsystem_vendor ||
9045 q->subsystem_vendor == PCI_ANY_ID) &&
9046 (d->subsystem_device == q->subsystem_device ||
9047 q->subsystem_device == PCI_ANY_ID))
9048 q->hook(dev);
9049 }
9050 }
9051
9052 /* Disable the VGA plane that we never use */
9053 static void i915_disable_vga(struct drm_device *dev)
9054 {
9055 struct drm_i915_private *dev_priv = dev->dev_private;
9056 u8 sr1;
9057 u32 vga_reg;
9058
9059 if (HAS_PCH_SPLIT(dev))
9060 vga_reg = CPU_VGACNTRL;
9061 else
9062 vga_reg = VGACNTRL;
9063
9064 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9065 outb(1, VGA_SR_INDEX);
9066 sr1 = inb(VGA_SR_DATA);
9067 outb(sr1 | 1<<5, VGA_SR_DATA);
9068 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9069 udelay(300);
9070
9071 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9072 POSTING_READ(vga_reg);
9073 }
9074
9075 void intel_modeset_init(struct drm_device *dev)
9076 {
9077 struct drm_i915_private *dev_priv = dev->dev_private;
9078 int i, ret;
9079
9080 drm_mode_config_init(dev);
9081
9082 dev->mode_config.min_width = 0;
9083 dev->mode_config.min_height = 0;
9084
9085 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9086
9087 intel_init_quirks(dev);
9088
9089 intel_init_display(dev);
9090
9091 if (IS_GEN2(dev)) {
9092 dev->mode_config.max_width = 2048;
9093 dev->mode_config.max_height = 2048;
9094 } else if (IS_GEN3(dev)) {
9095 dev->mode_config.max_width = 4096;
9096 dev->mode_config.max_height = 4096;
9097 } else {
9098 dev->mode_config.max_width = 8192;
9099 dev->mode_config.max_height = 8192;
9100 }
9101 dev->mode_config.fb_base = dev->agp->base;
9102
9103 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9104 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9105
9106 for (i = 0; i < dev_priv->num_pipe; i++) {
9107 intel_crtc_init(dev, i);
9108 ret = intel_plane_init(dev, i);
9109 if (ret)
9110 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9111 }
9112
9113 /* Just disable it once at startup */
9114 i915_disable_vga(dev);
9115 intel_setup_outputs(dev);
9116
9117 intel_init_clock_gating(dev);
9118
9119 if (IS_IRONLAKE_M(dev)) {
9120 ironlake_enable_drps(dev);
9121 intel_init_emon(dev);
9122 }
9123
9124 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9125 gen6_enable_rps(dev_priv);
9126 gen6_update_ring_freq(dev_priv);
9127 }
9128
9129 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9130 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9131 (unsigned long)dev);
9132 }
9133
9134 void intel_modeset_gem_init(struct drm_device *dev)
9135 {
9136 if (IS_IRONLAKE_M(dev))
9137 ironlake_enable_rc6(dev);
9138
9139 intel_setup_overlay(dev);
9140 }
9141
9142 void intel_modeset_cleanup(struct drm_device *dev)
9143 {
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9145 struct drm_crtc *crtc;
9146 struct intel_crtc *intel_crtc;
9147
9148 drm_kms_helper_poll_fini(dev);
9149 mutex_lock(&dev->struct_mutex);
9150
9151 intel_unregister_dsm_handler();
9152
9153
9154 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9155 /* Skip inactive CRTCs */
9156 if (!crtc->fb)
9157 continue;
9158
9159 intel_crtc = to_intel_crtc(crtc);
9160 intel_increase_pllclock(crtc);
9161 }
9162
9163 intel_disable_fbc(dev);
9164
9165 if (IS_IRONLAKE_M(dev))
9166 ironlake_disable_drps(dev);
9167 if (IS_GEN6(dev) || IS_GEN7(dev))
9168 gen6_disable_rps(dev);
9169
9170 if (IS_IRONLAKE_M(dev))
9171 ironlake_disable_rc6(dev);
9172
9173 mutex_unlock(&dev->struct_mutex);
9174
9175 /* Disable the irq before mode object teardown, for the irq might
9176 * enqueue unpin/hotplug work. */
9177 drm_irq_uninstall(dev);
9178 cancel_work_sync(&dev_priv->hotplug_work);
9179 cancel_work_sync(&dev_priv->rps_work);
9180
9181 /* flush any delayed tasks or pending work */
9182 flush_scheduled_work();
9183
9184 /* Shut off idle work before the crtcs get freed. */
9185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9186 intel_crtc = to_intel_crtc(crtc);
9187 del_timer_sync(&intel_crtc->idle_timer);
9188 }
9189 del_timer_sync(&dev_priv->idle_timer);
9190 cancel_work_sync(&dev_priv->idle_work);
9191
9192 drm_mode_config_cleanup(dev);
9193 }
9194
9195 /*
9196 * Return which encoder is currently attached for connector.
9197 */
9198 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9199 {
9200 return &intel_attached_encoder(connector)->base;
9201 }
9202
9203 void intel_connector_attach_encoder(struct intel_connector *connector,
9204 struct intel_encoder *encoder)
9205 {
9206 connector->encoder = encoder;
9207 drm_mode_connector_attach_encoder(&connector->base,
9208 &encoder->base);
9209 }
9210
9211 /*
9212 * set vga decode state - true == enable VGA decode
9213 */
9214 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9215 {
9216 struct drm_i915_private *dev_priv = dev->dev_private;
9217 u16 gmch_ctrl;
9218
9219 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9220 if (state)
9221 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9222 else
9223 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9224 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9225 return 0;
9226 }
9227
9228 #ifdef CONFIG_DEBUG_FS
9229 #include <linux/seq_file.h>
9230
9231 struct intel_display_error_state {
9232 struct intel_cursor_error_state {
9233 u32 control;
9234 u32 position;
9235 u32 base;
9236 u32 size;
9237 } cursor[2];
9238
9239 struct intel_pipe_error_state {
9240 u32 conf;
9241 u32 source;
9242
9243 u32 htotal;
9244 u32 hblank;
9245 u32 hsync;
9246 u32 vtotal;
9247 u32 vblank;
9248 u32 vsync;
9249 } pipe[2];
9250
9251 struct intel_plane_error_state {
9252 u32 control;
9253 u32 stride;
9254 u32 size;
9255 u32 pos;
9256 u32 addr;
9257 u32 surface;
9258 u32 tile_offset;
9259 } plane[2];
9260 };
9261
9262 struct intel_display_error_state *
9263 intel_display_capture_error_state(struct drm_device *dev)
9264 {
9265 drm_i915_private_t *dev_priv = dev->dev_private;
9266 struct intel_display_error_state *error;
9267 int i;
9268
9269 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9270 if (error == NULL)
9271 return NULL;
9272
9273 for (i = 0; i < 2; i++) {
9274 error->cursor[i].control = I915_READ(CURCNTR(i));
9275 error->cursor[i].position = I915_READ(CURPOS(i));
9276 error->cursor[i].base = I915_READ(CURBASE(i));
9277
9278 error->plane[i].control = I915_READ(DSPCNTR(i));
9279 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9280 error->plane[i].size = I915_READ(DSPSIZE(i));
9281 error->plane[i].pos = I915_READ(DSPPOS(i));
9282 error->plane[i].addr = I915_READ(DSPADDR(i));
9283 if (INTEL_INFO(dev)->gen >= 4) {
9284 error->plane[i].surface = I915_READ(DSPSURF(i));
9285 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9286 }
9287
9288 error->pipe[i].conf = I915_READ(PIPECONF(i));
9289 error->pipe[i].source = I915_READ(PIPESRC(i));
9290 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9291 error->pipe[i].hblank = I915_READ(HBLANK(i));
9292 error->pipe[i].hsync = I915_READ(HSYNC(i));
9293 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9294 error->pipe[i].vblank = I915_READ(VBLANK(i));
9295 error->pipe[i].vsync = I915_READ(VSYNC(i));
9296 }
9297
9298 return error;
9299 }
9300
9301 void
9302 intel_display_print_error_state(struct seq_file *m,
9303 struct drm_device *dev,
9304 struct intel_display_error_state *error)
9305 {
9306 int i;
9307
9308 for (i = 0; i < 2; i++) {
9309 seq_printf(m, "Pipe [%d]:\n", i);
9310 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9311 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9312 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9313 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9314 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9315 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9316 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9317 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9318
9319 seq_printf(m, "Plane [%d]:\n", i);
9320 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9321 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9322 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9323 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9324 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9325 if (INTEL_INFO(dev)->gen >= 4) {
9326 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9327 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9328 }
9329
9330 seq_printf(m, "Cursor [%d]:\n", i);
9331 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9332 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9333 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9334 }
9335 }
9336 #endif
Linux kernel - Deliverables
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