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4457fc7a9533a18fa1eb45e195cc7362a2de1289
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static bool
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
108 {
109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
114 }
115
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
128 };
129
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
142 };
143
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
170 };
171
172
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
185 },
186 .find_pll = intel_g4x_find_best_PLL,
187 };
188
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
201 };
202
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
214 },
215 .find_pll = intel_g4x_find_best_PLL,
216 };
217
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
229 },
230 .find_pll = intel_g4x_find_best_PLL,
231 };
232
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
245 };
246
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
261 };
262
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
275 };
276
277 /* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
294 };
295
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
308 };
309
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
322 };
323
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
365 };
366
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379 };
380
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393 };
394
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407 };
408
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410 {
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429 out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432 }
433
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436 {
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452 out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454 }
455
456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465 }
466
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471 }
472
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483 };
484
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487 {
488 unsigned int val;
489
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
515 {
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
536 else
537 limit = &intel_limits_ironlake_dac;
538
539 return limit;
540 }
541
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
552 else
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
564
565 return limit;
566 }
567
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
580 else
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
597 else
598 limit = &intel_limits_i8xx_dvo;
599 }
600 return limit;
601 }
602
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610 }
611
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
616 return;
617 }
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622 }
623
624 /**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
631
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
634 return true;
635
636 return false;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
648 {
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
670
671 return true;
672 }
673
674 static bool
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
683 int err = target;
684
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
704 memset(best_clock, 0, sizeof(*best_clock));
705
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
717 int this_err;
718
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
722 continue;
723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738 }
739
740 static bool
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 int lvds_reg;
756
757 if (HAS_PCH_SPLIT(dev))
758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
789 continue;
790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
793
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
805 return found;
806 }
807
808 static bool
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815
816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832 }
833
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
860 }
861 static bool
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 flag = 0;
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928 }
929
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931 {
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939 }
940
941 /**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
953
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
979 DRM_DEBUG_KMS("vblank wait timed out\n");
980 }
981
982 /*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
997 *
998 */
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1005
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
1009 WARN(1, "pipe_off wait timed out\n");
1010 } else {
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 /* Wait for the display line to settle */
1021 do {
1022 last_line = I915_READ(reg) & line_mask;
1023 mdelay(5);
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 WARN(1, "pipe_off wait timed out\n");
1028 }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033 return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039 {
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
1059 {
1060 u32 val;
1061 bool cur_state;
1062
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070 return;
1071
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
1095 }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102 {
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126 {
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148 {
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167 {
1168 int reg;
1169 u32 val;
1170
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182 {
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
1186 bool locked = true;
1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1206 pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1211 {
1212 int reg;
1213 u32 val;
1214 bool cur_state;
1215
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1230 {
1231 int reg;
1232 u32 val;
1233 bool cur_state;
1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
1260 return;
1261 }
1262
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1272 }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277 u32 val;
1278 bool enabled;
1279
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326 {
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342 {
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358 {
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1373 {
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385 {
1386 u32 val = I915_READ(reg);
1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe));
1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397 {
1398 int reg;
1399 u32 val;
1400
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1409 pipe_name(pipe));
1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415 pipe_name(pipe));
1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434 */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518 out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525 unsigned long flags;
1526 u32 value = 0;
1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552 }
1553
1554 /**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565 struct intel_pch_pll *pll;
1566 int reg;
1567 u32 val;
1568
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv->info->gen < 5);
1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
1585 if (pll->active++ && pll->on) {
1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
1598
1599 pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606 int reg;
1607 u32 val;
1608
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
1611 if (pll == NULL)
1612 return;
1613
1614 if (WARN_ON(pll->refcount == 0))
1615 return;
1616
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1620
1621 if (WARN_ON(pll->active == 0)) {
1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623 return;
1624 }
1625
1626 if (--pll->active) {
1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628 return;
1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636 reg = pll->pll_reg;
1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
1642
1643 pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648 {
1649 int reg;
1650 u32 val, pipeconf_val;
1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
1671 pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
1679 val |= pipeconf_val & PIPE_BPC_MASK;
1680 }
1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699 {
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
1735 {
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778 {
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806 enum plane plane)
1807 {
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822 {
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835 intel_flush_display_plane(dev_priv, plane);
1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849 {
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864 enum pipe pipe, int reg, u32 port_sel)
1865 {
1866 u32 val = I915_READ(reg);
1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869 I915_WRITE(reg, val & ~DP_PORT_EN);
1870 }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875 {
1876 u32 val = I915_READ(reg);
1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
1880 I915_WRITE(reg, val & ~PORT_ENABLE);
1881 }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918 struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *pipelined)
1920 {
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 u32 alignment;
1923 int ret;
1924
1925 switch (obj->tiling_mode) {
1926 case I915_TILING_NONE:
1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
1929 else if (INTEL_INFO(dev)->gen >= 4)
1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
1946 dev_priv->mm.interruptible = false;
1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948 if (ret)
1949 goto err_interruptible;
1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
1956 ret = i915_gem_object_get_fence(obj);
1957 if (ret)
1958 goto err_unpin;
1959
1960 i915_gem_object_pin_fence(obj);
1961
1962 dev_priv->mm.interruptible = true;
1963 return 0;
1964
1965 err_unpin:
1966 i915_gem_object_unpin(obj);
1967 err_interruptible:
1968 dev_priv->mm.interruptible = true;
1969 return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983 {
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
1996 {
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
2001 struct drm_i915_gem_object *obj;
2002 int plane = intel_crtc->plane;
2003 unsigned long linear_offset;
2004 u32 dspcntr;
2005 u32 reg;
2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039 return -EINVAL;
2040 }
2041 if (INTEL_INFO(dev)->gen >= 4) {
2042 if (obj->tiling_mode != I915_TILING_NONE)
2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
2048 I915_WRITE(reg, dspcntr);
2049
2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
2059 intel_crtc->dspaddr_offset = linear_offset;
2060 }
2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070 } else
2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072 POSTING_READ(reg);
2073
2074 return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079 {
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
2086 unsigned long linear_offset;
2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 case 2:
2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
2147
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
2155 POSTING_READ(reg);
2156
2157 return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164 {
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
2170 intel_increase_pllclock(crtc);
2171
2172 return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *fb)
2205 {
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210 struct drm_framebuffer *old_fb;
2211 int ret;
2212
2213 /* no fb bound */
2214 if (!fb) {
2215 DRM_ERROR("No FB bound\n");
2216 return 0;
2217 }
2218
2219 if(intel_crtc->plane > dev_priv->num_pipe) {
2220 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2221 intel_crtc->plane,
2222 dev_priv->num_pipe);
2223 return -EINVAL;
2224 }
2225
2226 mutex_lock(&dev->struct_mutex);
2227 ret = intel_pin_and_fence_fb_obj(dev,
2228 to_intel_framebuffer(fb)->obj,
2229 NULL);
2230 if (ret != 0) {
2231 mutex_unlock(&dev->struct_mutex);
2232 DRM_ERROR("pin & fence failed\n");
2233 return ret;
2234 }
2235
2236 if (crtc->fb)
2237 intel_finish_fb(crtc->fb);
2238
2239 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2240 if (ret) {
2241 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2242 mutex_unlock(&dev->struct_mutex);
2243 DRM_ERROR("failed to update base address\n");
2244 return ret;
2245 }
2246
2247 old_fb = crtc->fb;
2248 crtc->fb = fb;
2249 crtc->x = x;
2250 crtc->y = y;
2251
2252 if (old_fb) {
2253 intel_wait_for_vblank(dev, intel_crtc->pipe);
2254 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2255 }
2256
2257 intel_update_fbc(dev);
2258 mutex_unlock(&dev->struct_mutex);
2259
2260 if (!dev->primary->master)
2261 return 0;
2262
2263 master_priv = dev->primary->master->driver_priv;
2264 if (!master_priv->sarea_priv)
2265 return 0;
2266
2267 if (intel_crtc->pipe) {
2268 master_priv->sarea_priv->pipeB_x = x;
2269 master_priv->sarea_priv->pipeB_y = y;
2270 } else {
2271 master_priv->sarea_priv->pipeA_x = x;
2272 master_priv->sarea_priv->pipeA_y = y;
2273 }
2274
2275 return 0;
2276 }
2277
2278 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2279 {
2280 struct drm_device *dev = crtc->dev;
2281 struct drm_i915_private *dev_priv = dev->dev_private;
2282 u32 dpa_ctl;
2283
2284 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2285 dpa_ctl = I915_READ(DP_A);
2286 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2287
2288 if (clock < 200000) {
2289 u32 temp;
2290 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2291 /* workaround for 160Mhz:
2292 1) program 0x4600c bits 15:0 = 0x8124
2293 2) program 0x46010 bit 0 = 1
2294 3) program 0x46034 bit 24 = 1
2295 4) program 0x64000 bit 14 = 1
2296 */
2297 temp = I915_READ(0x4600c);
2298 temp &= 0xffff0000;
2299 I915_WRITE(0x4600c, temp | 0x8124);
2300
2301 temp = I915_READ(0x46010);
2302 I915_WRITE(0x46010, temp | 1);
2303
2304 temp = I915_READ(0x46034);
2305 I915_WRITE(0x46034, temp | (1 << 24));
2306 } else {
2307 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2308 }
2309 I915_WRITE(DP_A, dpa_ctl);
2310
2311 POSTING_READ(DP_A);
2312 udelay(500);
2313 }
2314
2315 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2316 {
2317 struct drm_device *dev = crtc->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320 int pipe = intel_crtc->pipe;
2321 u32 reg, temp;
2322
2323 /* enable normal train */
2324 reg = FDI_TX_CTL(pipe);
2325 temp = I915_READ(reg);
2326 if (IS_IVYBRIDGE(dev)) {
2327 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2328 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2329 } else {
2330 temp &= ~FDI_LINK_TRAIN_NONE;
2331 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2332 }
2333 I915_WRITE(reg, temp);
2334
2335 reg = FDI_RX_CTL(pipe);
2336 temp = I915_READ(reg);
2337 if (HAS_PCH_CPT(dev)) {
2338 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2339 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2340 } else {
2341 temp &= ~FDI_LINK_TRAIN_NONE;
2342 temp |= FDI_LINK_TRAIN_NONE;
2343 }
2344 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2345
2346 /* wait one idle pattern time */
2347 POSTING_READ(reg);
2348 udelay(1000);
2349
2350 /* IVB wants error correction enabled */
2351 if (IS_IVYBRIDGE(dev))
2352 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2353 FDI_FE_ERRC_ENABLE);
2354 }
2355
2356 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2357 {
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 u32 flags = I915_READ(SOUTH_CHICKEN1);
2360
2361 flags |= FDI_PHASE_SYNC_OVR(pipe);
2362 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2363 flags |= FDI_PHASE_SYNC_EN(pipe);
2364 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2365 POSTING_READ(SOUTH_CHICKEN1);
2366 }
2367
2368 /* The FDI link training functions for ILK/Ibexpeak. */
2369 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2370 {
2371 struct drm_device *dev = crtc->dev;
2372 struct drm_i915_private *dev_priv = dev->dev_private;
2373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2374 int pipe = intel_crtc->pipe;
2375 int plane = intel_crtc->plane;
2376 u32 reg, temp, tries;
2377
2378 /* FDI needs bits from pipe & plane first */
2379 assert_pipe_enabled(dev_priv, pipe);
2380 assert_plane_enabled(dev_priv, plane);
2381
2382 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2383 for train result */
2384 reg = FDI_RX_IMR(pipe);
2385 temp = I915_READ(reg);
2386 temp &= ~FDI_RX_SYMBOL_LOCK;
2387 temp &= ~FDI_RX_BIT_LOCK;
2388 I915_WRITE(reg, temp);
2389 I915_READ(reg);
2390 udelay(150);
2391
2392 /* enable CPU FDI TX and PCH FDI RX */
2393 reg = FDI_TX_CTL(pipe);
2394 temp = I915_READ(reg);
2395 temp &= ~(7 << 19);
2396 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
2399 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2400
2401 reg = FDI_RX_CTL(pipe);
2402 temp = I915_READ(reg);
2403 temp &= ~FDI_LINK_TRAIN_NONE;
2404 temp |= FDI_LINK_TRAIN_PATTERN_1;
2405 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2406
2407 POSTING_READ(reg);
2408 udelay(150);
2409
2410 /* Ironlake workaround, enable clock pointer after FDI enable*/
2411 if (HAS_PCH_IBX(dev)) {
2412 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2413 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2414 FDI_RX_PHASE_SYNC_POINTER_EN);
2415 }
2416
2417 reg = FDI_RX_IIR(pipe);
2418 for (tries = 0; tries < 5; tries++) {
2419 temp = I915_READ(reg);
2420 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2421
2422 if ((temp & FDI_RX_BIT_LOCK)) {
2423 DRM_DEBUG_KMS("FDI train 1 done.\n");
2424 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2425 break;
2426 }
2427 }
2428 if (tries == 5)
2429 DRM_ERROR("FDI train 1 fail!\n");
2430
2431 /* Train 2 */
2432 reg = FDI_TX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
2436 I915_WRITE(reg, temp);
2437
2438 reg = FDI_RX_CTL(pipe);
2439 temp = I915_READ(reg);
2440 temp &= ~FDI_LINK_TRAIN_NONE;
2441 temp |= FDI_LINK_TRAIN_PATTERN_2;
2442 I915_WRITE(reg, temp);
2443
2444 POSTING_READ(reg);
2445 udelay(150);
2446
2447 reg = FDI_RX_IIR(pipe);
2448 for (tries = 0; tries < 5; tries++) {
2449 temp = I915_READ(reg);
2450 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2451
2452 if (temp & FDI_RX_SYMBOL_LOCK) {
2453 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2454 DRM_DEBUG_KMS("FDI train 2 done.\n");
2455 break;
2456 }
2457 }
2458 if (tries == 5)
2459 DRM_ERROR("FDI train 2 fail!\n");
2460
2461 DRM_DEBUG_KMS("FDI train done\n");
2462
2463 }
2464
2465 static const int snb_b_fdi_train_param[] = {
2466 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2467 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2468 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2469 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2470 };
2471
2472 /* The FDI link training functions for SNB/Cougarpoint. */
2473 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2474 {
2475 struct drm_device *dev = crtc->dev;
2476 struct drm_i915_private *dev_priv = dev->dev_private;
2477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2478 int pipe = intel_crtc->pipe;
2479 u32 reg, temp, i, retry;
2480
2481 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2482 for train result */
2483 reg = FDI_RX_IMR(pipe);
2484 temp = I915_READ(reg);
2485 temp &= ~FDI_RX_SYMBOL_LOCK;
2486 temp &= ~FDI_RX_BIT_LOCK;
2487 I915_WRITE(reg, temp);
2488
2489 POSTING_READ(reg);
2490 udelay(150);
2491
2492 /* enable CPU FDI TX and PCH FDI RX */
2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 temp &= ~(7 << 19);
2496 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2500 /* SNB-B */
2501 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2502 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2503
2504 reg = FDI_RX_CTL(pipe);
2505 temp = I915_READ(reg);
2506 if (HAS_PCH_CPT(dev)) {
2507 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2508 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2509 } else {
2510 temp &= ~FDI_LINK_TRAIN_NONE;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1;
2512 }
2513 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2514
2515 POSTING_READ(reg);
2516 udelay(150);
2517
2518 if (HAS_PCH_CPT(dev))
2519 cpt_phase_pointer_enable(dev, pipe);
2520
2521 for (i = 0; i < 4; i++) {
2522 reg = FDI_TX_CTL(pipe);
2523 temp = I915_READ(reg);
2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 temp |= snb_b_fdi_train_param[i];
2526 I915_WRITE(reg, temp);
2527
2528 POSTING_READ(reg);
2529 udelay(500);
2530
2531 for (retry = 0; retry < 5; retry++) {
2532 reg = FDI_RX_IIR(pipe);
2533 temp = I915_READ(reg);
2534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535 if (temp & FDI_RX_BIT_LOCK) {
2536 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2537 DRM_DEBUG_KMS("FDI train 1 done.\n");
2538 break;
2539 }
2540 udelay(50);
2541 }
2542 if (retry < 5)
2543 break;
2544 }
2545 if (i == 4)
2546 DRM_ERROR("FDI train 1 fail!\n");
2547
2548 /* Train 2 */
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_2;
2553 if (IS_GEN6(dev)) {
2554 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2555 /* SNB-B */
2556 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2557 }
2558 I915_WRITE(reg, temp);
2559
2560 reg = FDI_RX_CTL(pipe);
2561 temp = I915_READ(reg);
2562 if (HAS_PCH_CPT(dev)) {
2563 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2565 } else {
2566 temp &= ~FDI_LINK_TRAIN_NONE;
2567 temp |= FDI_LINK_TRAIN_PATTERN_2;
2568 }
2569 I915_WRITE(reg, temp);
2570
2571 POSTING_READ(reg);
2572 udelay(150);
2573
2574 for (i = 0; i < 4; i++) {
2575 reg = FDI_TX_CTL(pipe);
2576 temp = I915_READ(reg);
2577 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2578 temp |= snb_b_fdi_train_param[i];
2579 I915_WRITE(reg, temp);
2580
2581 POSTING_READ(reg);
2582 udelay(500);
2583
2584 for (retry = 0; retry < 5; retry++) {
2585 reg = FDI_RX_IIR(pipe);
2586 temp = I915_READ(reg);
2587 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2588 if (temp & FDI_RX_SYMBOL_LOCK) {
2589 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2590 DRM_DEBUG_KMS("FDI train 2 done.\n");
2591 break;
2592 }
2593 udelay(50);
2594 }
2595 if (retry < 5)
2596 break;
2597 }
2598 if (i == 4)
2599 DRM_ERROR("FDI train 2 fail!\n");
2600
2601 DRM_DEBUG_KMS("FDI train done.\n");
2602 }
2603
2604 /* Manual link training for Ivy Bridge A0 parts */
2605 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2606 {
2607 struct drm_device *dev = crtc->dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2610 int pipe = intel_crtc->pipe;
2611 u32 reg, temp, i;
2612
2613 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2614 for train result */
2615 reg = FDI_RX_IMR(pipe);
2616 temp = I915_READ(reg);
2617 temp &= ~FDI_RX_SYMBOL_LOCK;
2618 temp &= ~FDI_RX_BIT_LOCK;
2619 I915_WRITE(reg, temp);
2620
2621 POSTING_READ(reg);
2622 udelay(150);
2623
2624 /* enable CPU FDI TX and PCH FDI RX */
2625 reg = FDI_TX_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~(7 << 19);
2628 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2629 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2630 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2631 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2633 temp |= FDI_COMPOSITE_SYNC;
2634 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2635
2636 reg = FDI_RX_CTL(pipe);
2637 temp = I915_READ(reg);
2638 temp &= ~FDI_LINK_TRAIN_AUTO;
2639 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2640 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2641 temp |= FDI_COMPOSITE_SYNC;
2642 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2643
2644 POSTING_READ(reg);
2645 udelay(150);
2646
2647 if (HAS_PCH_CPT(dev))
2648 cpt_phase_pointer_enable(dev, pipe);
2649
2650 for (i = 0; i < 4; i++) {
2651 reg = FDI_TX_CTL(pipe);
2652 temp = I915_READ(reg);
2653 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2654 temp |= snb_b_fdi_train_param[i];
2655 I915_WRITE(reg, temp);
2656
2657 POSTING_READ(reg);
2658 udelay(500);
2659
2660 reg = FDI_RX_IIR(pipe);
2661 temp = I915_READ(reg);
2662 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2663
2664 if (temp & FDI_RX_BIT_LOCK ||
2665 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2666 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2667 DRM_DEBUG_KMS("FDI train 1 done.\n");
2668 break;
2669 }
2670 }
2671 if (i == 4)
2672 DRM_ERROR("FDI train 1 fail!\n");
2673
2674 /* Train 2 */
2675 reg = FDI_TX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2678 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2679 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2680 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2681 I915_WRITE(reg, temp);
2682
2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2686 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2687 I915_WRITE(reg, temp);
2688
2689 POSTING_READ(reg);
2690 udelay(150);
2691
2692 for (i = 0; i < 4; i++) {
2693 reg = FDI_TX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2696 temp |= snb_b_fdi_train_param[i];
2697 I915_WRITE(reg, temp);
2698
2699 POSTING_READ(reg);
2700 udelay(500);
2701
2702 reg = FDI_RX_IIR(pipe);
2703 temp = I915_READ(reg);
2704 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2705
2706 if (temp & FDI_RX_SYMBOL_LOCK) {
2707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2708 DRM_DEBUG_KMS("FDI train 2 done.\n");
2709 break;
2710 }
2711 }
2712 if (i == 4)
2713 DRM_ERROR("FDI train 2 fail!\n");
2714
2715 DRM_DEBUG_KMS("FDI train done.\n");
2716 }
2717
2718 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2719 {
2720 struct drm_device *dev = intel_crtc->base.dev;
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 int pipe = intel_crtc->pipe;
2723 u32 reg, temp;
2724
2725 /* Write the TU size bits so error detection works */
2726 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2727 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2728
2729 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~((0x7 << 19) | (0x7 << 16));
2733 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2734 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2735 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2736
2737 POSTING_READ(reg);
2738 udelay(200);
2739
2740 /* Switch from Rawclk to PCDclk */
2741 temp = I915_READ(reg);
2742 I915_WRITE(reg, temp | FDI_PCDCLK);
2743
2744 POSTING_READ(reg);
2745 udelay(200);
2746
2747 /* On Haswell, the PLL configuration for ports and pipes is handled
2748 * separately, as part of DDI setup */
2749 if (!IS_HASWELL(dev)) {
2750 /* Enable CPU FDI TX PLL, always on for Ironlake */
2751 reg = FDI_TX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2754 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2755
2756 POSTING_READ(reg);
2757 udelay(100);
2758 }
2759 }
2760 }
2761
2762 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2763 {
2764 struct drm_device *dev = intel_crtc->base.dev;
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766 int pipe = intel_crtc->pipe;
2767 u32 reg, temp;
2768
2769 /* Switch from PCDclk to Rawclk */
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2773
2774 /* Disable CPU FDI TX PLL */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2778
2779 POSTING_READ(reg);
2780 udelay(100);
2781
2782 reg = FDI_RX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2785
2786 /* Wait for the clocks to turn off. */
2787 POSTING_READ(reg);
2788 udelay(100);
2789 }
2790
2791 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2792 {
2793 struct drm_i915_private *dev_priv = dev->dev_private;
2794 u32 flags = I915_READ(SOUTH_CHICKEN1);
2795
2796 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2797 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2798 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2799 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2800 POSTING_READ(SOUTH_CHICKEN1);
2801 }
2802 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2803 {
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807 int pipe = intel_crtc->pipe;
2808 u32 reg, temp;
2809
2810 /* disable CPU FDI tx and PCH FDI rx */
2811 reg = FDI_TX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2814 POSTING_READ(reg);
2815
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 temp &= ~(0x7 << 16);
2819 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2820 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2821
2822 POSTING_READ(reg);
2823 udelay(100);
2824
2825 /* Ironlake workaround, disable clock pointer after downing FDI */
2826 if (HAS_PCH_IBX(dev)) {
2827 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2828 I915_WRITE(FDI_RX_CHICKEN(pipe),
2829 I915_READ(FDI_RX_CHICKEN(pipe) &
2830 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2831 } else if (HAS_PCH_CPT(dev)) {
2832 cpt_phase_pointer_disable(dev, pipe);
2833 }
2834
2835 /* still set train pattern 1 */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~FDI_LINK_TRAIN_NONE;
2839 temp |= FDI_LINK_TRAIN_PATTERN_1;
2840 I915_WRITE(reg, temp);
2841
2842 reg = FDI_RX_CTL(pipe);
2843 temp = I915_READ(reg);
2844 if (HAS_PCH_CPT(dev)) {
2845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2847 } else {
2848 temp &= ~FDI_LINK_TRAIN_NONE;
2849 temp |= FDI_LINK_TRAIN_PATTERN_1;
2850 }
2851 /* BPC in FDI rx is consistent with that in PIPECONF */
2852 temp &= ~(0x07 << 16);
2853 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2854 I915_WRITE(reg, temp);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858 }
2859
2860 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2861 {
2862 struct drm_device *dev = crtc->dev;
2863
2864 if (crtc->fb == NULL)
2865 return;
2866
2867 mutex_lock(&dev->struct_mutex);
2868 intel_finish_fb(crtc->fb);
2869 mutex_unlock(&dev->struct_mutex);
2870 }
2871
2872 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2873 {
2874 struct drm_device *dev = crtc->dev;
2875 struct intel_encoder *intel_encoder;
2876
2877 /*
2878 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2879 * must be driven by its own crtc; no sharing is possible.
2880 */
2881 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2882
2883 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2884 * CPU handles all others */
2885 if (IS_HASWELL(dev)) {
2886 /* It is still unclear how this will work on PPT, so throw up a warning */
2887 WARN_ON(!HAS_PCH_LPT(dev));
2888
2889 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2890 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2891 return true;
2892 } else {
2893 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2894 intel_encoder->type);
2895 return false;
2896 }
2897 }
2898
2899 switch (intel_encoder->type) {
2900 case INTEL_OUTPUT_EDP:
2901 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2902 return false;
2903 continue;
2904 }
2905 }
2906
2907 return true;
2908 }
2909
2910 /* Program iCLKIP clock to the desired frequency */
2911 static void lpt_program_iclkip(struct drm_crtc *crtc)
2912 {
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916 u32 temp;
2917
2918 /* It is necessary to ungate the pixclk gate prior to programming
2919 * the divisors, and gate it back when it is done.
2920 */
2921 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2922
2923 /* Disable SSCCTL */
2924 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2925 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2926 SBI_SSCCTL_DISABLE);
2927
2928 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2929 if (crtc->mode.clock == 20000) {
2930 auxdiv = 1;
2931 divsel = 0x41;
2932 phaseinc = 0x20;
2933 } else {
2934 /* The iCLK virtual clock root frequency is in MHz,
2935 * but the crtc->mode.clock in in KHz. To get the divisors,
2936 * it is necessary to divide one by another, so we
2937 * convert the virtual clock precision to KHz here for higher
2938 * precision.
2939 */
2940 u32 iclk_virtual_root_freq = 172800 * 1000;
2941 u32 iclk_pi_range = 64;
2942 u32 desired_divisor, msb_divisor_value, pi_value;
2943
2944 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2945 msb_divisor_value = desired_divisor / iclk_pi_range;
2946 pi_value = desired_divisor % iclk_pi_range;
2947
2948 auxdiv = 0;
2949 divsel = msb_divisor_value - 2;
2950 phaseinc = pi_value;
2951 }
2952
2953 /* This should not happen with any sane values */
2954 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2955 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2956 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2957 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2958
2959 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2960 crtc->mode.clock,
2961 auxdiv,
2962 divsel,
2963 phasedir,
2964 phaseinc);
2965
2966 /* Program SSCDIVINTPHASE6 */
2967 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2968 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2969 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2970 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2971 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2972 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2973 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2974
2975 intel_sbi_write(dev_priv,
2976 SBI_SSCDIVINTPHASE6,
2977 temp);
2978
2979 /* Program SSCAUXDIV */
2980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2981 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2983 intel_sbi_write(dev_priv,
2984 SBI_SSCAUXDIV6,
2985 temp);
2986
2987
2988 /* Enable modulator and associated divider */
2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2990 temp &= ~SBI_SSCCTL_DISABLE;
2991 intel_sbi_write(dev_priv,
2992 SBI_SSCCTL6,
2993 temp);
2994
2995 /* Wait for initialization time */
2996 udelay(24);
2997
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2999 }
3000
3001 /*
3002 * Enable PCH resources required for PCH ports:
3003 * - PCH PLLs
3004 * - FDI training & RX/TX
3005 * - update transcoder timings
3006 * - DP transcoding bits
3007 * - transcoder
3008 */
3009 static void ironlake_pch_enable(struct drm_crtc *crtc)
3010 {
3011 struct drm_device *dev = crtc->dev;
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3014 int pipe = intel_crtc->pipe;
3015 u32 reg, temp;
3016
3017 assert_transcoder_disabled(dev_priv, pipe);
3018
3019 /* For PCH output, training FDI link */
3020 dev_priv->display.fdi_link_train(crtc);
3021
3022 intel_enable_pch_pll(intel_crtc);
3023
3024 if (HAS_PCH_LPT(dev)) {
3025 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3026 lpt_program_iclkip(crtc);
3027 } else if (HAS_PCH_CPT(dev)) {
3028 u32 sel;
3029
3030 temp = I915_READ(PCH_DPLL_SEL);
3031 switch (pipe) {
3032 default:
3033 case 0:
3034 temp |= TRANSA_DPLL_ENABLE;
3035 sel = TRANSA_DPLLB_SEL;
3036 break;
3037 case 1:
3038 temp |= TRANSB_DPLL_ENABLE;
3039 sel = TRANSB_DPLLB_SEL;
3040 break;
3041 case 2:
3042 temp |= TRANSC_DPLL_ENABLE;
3043 sel = TRANSC_DPLLB_SEL;
3044 break;
3045 }
3046 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3047 temp |= sel;
3048 else
3049 temp &= ~sel;
3050 I915_WRITE(PCH_DPLL_SEL, temp);
3051 }
3052
3053 /* set transcoder timing, panel must allow it */
3054 assert_panel_unlocked(dev_priv, pipe);
3055 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3056 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3057 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3058
3059 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3060 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3061 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3062 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3063
3064 if (!IS_HASWELL(dev))
3065 intel_fdi_normal_train(crtc);
3066
3067 /* For PCH DP, enable TRANS_DP_CTL */
3068 if (HAS_PCH_CPT(dev) &&
3069 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3070 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3071 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3072 reg = TRANS_DP_CTL(pipe);
3073 temp = I915_READ(reg);
3074 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3075 TRANS_DP_SYNC_MASK |
3076 TRANS_DP_BPC_MASK);
3077 temp |= (TRANS_DP_OUTPUT_ENABLE |
3078 TRANS_DP_ENH_FRAMING);
3079 temp |= bpc << 9; /* same format but at 11:9 */
3080
3081 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3082 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3083 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3084 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3085
3086 switch (intel_trans_dp_port_sel(crtc)) {
3087 case PCH_DP_B:
3088 temp |= TRANS_DP_PORT_SEL_B;
3089 break;
3090 case PCH_DP_C:
3091 temp |= TRANS_DP_PORT_SEL_C;
3092 break;
3093 case PCH_DP_D:
3094 temp |= TRANS_DP_PORT_SEL_D;
3095 break;
3096 default:
3097 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3098 temp |= TRANS_DP_PORT_SEL_B;
3099 break;
3100 }
3101
3102 I915_WRITE(reg, temp);
3103 }
3104
3105 intel_enable_transcoder(dev_priv, pipe);
3106 }
3107
3108 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3109 {
3110 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3111
3112 if (pll == NULL)
3113 return;
3114
3115 if (pll->refcount == 0) {
3116 WARN(1, "bad PCH PLL refcount\n");
3117 return;
3118 }
3119
3120 --pll->refcount;
3121 intel_crtc->pch_pll = NULL;
3122 }
3123
3124 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3125 {
3126 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3127 struct intel_pch_pll *pll;
3128 int i;
3129
3130 pll = intel_crtc->pch_pll;
3131 if (pll) {
3132 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3133 intel_crtc->base.base.id, pll->pll_reg);
3134 goto prepare;
3135 }
3136
3137 if (HAS_PCH_IBX(dev_priv->dev)) {
3138 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3139 i = intel_crtc->pipe;
3140 pll = &dev_priv->pch_plls[i];
3141
3142 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3143 intel_crtc->base.base.id, pll->pll_reg);
3144
3145 goto found;
3146 }
3147
3148 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3149 pll = &dev_priv->pch_plls[i];
3150
3151 /* Only want to check enabled timings first */
3152 if (pll->refcount == 0)
3153 continue;
3154
3155 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3156 fp == I915_READ(pll->fp0_reg)) {
3157 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3158 intel_crtc->base.base.id,
3159 pll->pll_reg, pll->refcount, pll->active);
3160
3161 goto found;
3162 }
3163 }
3164
3165 /* Ok no matching timings, maybe there's a free one? */
3166 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3167 pll = &dev_priv->pch_plls[i];
3168 if (pll->refcount == 0) {
3169 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3170 intel_crtc->base.base.id, pll->pll_reg);
3171 goto found;
3172 }
3173 }
3174
3175 return NULL;
3176
3177 found:
3178 intel_crtc->pch_pll = pll;
3179 pll->refcount++;
3180 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3181 prepare: /* separate function? */
3182 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3183
3184 /* Wait for the clocks to stabilize before rewriting the regs */
3185 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3186 POSTING_READ(pll->pll_reg);
3187 udelay(150);
3188
3189 I915_WRITE(pll->fp0_reg, fp);
3190 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3191 pll->on = false;
3192 return pll;
3193 }
3194
3195 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3196 {
3197 struct drm_i915_private *dev_priv = dev->dev_private;
3198 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3199 u32 temp;
3200
3201 temp = I915_READ(dslreg);
3202 udelay(500);
3203 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3204 /* Without this, mode sets may fail silently on FDI */
3205 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3206 udelay(250);
3207 I915_WRITE(tc2reg, 0);
3208 if (wait_for(I915_READ(dslreg) != temp, 5))
3209 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3210 }
3211 }
3212
3213 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3214 {
3215 struct drm_device *dev = crtc->dev;
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218 struct intel_encoder *encoder;
3219 int pipe = intel_crtc->pipe;
3220 int plane = intel_crtc->plane;
3221 u32 temp;
3222 bool is_pch_port;
3223
3224 WARN_ON(!crtc->enabled);
3225
3226 if (intel_crtc->active)
3227 return;
3228
3229 intel_crtc->active = true;
3230 intel_update_watermarks(dev);
3231
3232 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3233 temp = I915_READ(PCH_LVDS);
3234 if ((temp & LVDS_PORT_EN) == 0)
3235 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3236 }
3237
3238 is_pch_port = intel_crtc_driving_pch(crtc);
3239
3240 if (is_pch_port)
3241 ironlake_fdi_pll_enable(intel_crtc);
3242 else
3243 ironlake_fdi_disable(crtc);
3244
3245 /* Enable panel fitting for LVDS */
3246 if (dev_priv->pch_pf_size &&
3247 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3248 /* Force use of hard-coded filter coefficients
3249 * as some pre-programmed values are broken,
3250 * e.g. x201.
3251 */
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3254 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3255 }
3256
3257 /*
3258 * On ILK+ LUT must be loaded before the pipe is running but with
3259 * clocks enabled
3260 */
3261 intel_crtc_load_lut(crtc);
3262
3263 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3264 intel_enable_plane(dev_priv, plane, pipe);
3265
3266 if (is_pch_port)
3267 ironlake_pch_enable(crtc);
3268
3269 mutex_lock(&dev->struct_mutex);
3270 intel_update_fbc(dev);
3271 mutex_unlock(&dev->struct_mutex);
3272
3273 intel_crtc_update_cursor(crtc, true);
3274
3275 for_each_encoder_on_crtc(dev, crtc, encoder)
3276 encoder->enable(encoder);
3277
3278 if (HAS_PCH_CPT(dev))
3279 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3280 }
3281
3282 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3283 {
3284 struct drm_device *dev = crtc->dev;
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3287 struct intel_encoder *encoder;
3288 int pipe = intel_crtc->pipe;
3289 int plane = intel_crtc->plane;
3290 u32 reg, temp;
3291
3292
3293 if (!intel_crtc->active)
3294 return;
3295
3296 for_each_encoder_on_crtc(dev, crtc, encoder)
3297 encoder->disable(encoder);
3298
3299 intel_crtc_wait_for_pending_flips(crtc);
3300 drm_vblank_off(dev, pipe);
3301 intel_crtc_update_cursor(crtc, false);
3302
3303 intel_disable_plane(dev_priv, plane, pipe);
3304
3305 if (dev_priv->cfb_plane == plane)
3306 intel_disable_fbc(dev);
3307
3308 intel_disable_pipe(dev_priv, pipe);
3309
3310 /* Disable PF */
3311 I915_WRITE(PF_CTL(pipe), 0);
3312 I915_WRITE(PF_WIN_SZ(pipe), 0);
3313
3314 ironlake_fdi_disable(crtc);
3315
3316 /* This is a horrible layering violation; we should be doing this in
3317 * the connector/encoder ->prepare instead, but we don't always have
3318 * enough information there about the config to know whether it will
3319 * actually be necessary or just cause undesired flicker.
3320 */
3321 intel_disable_pch_ports(dev_priv, pipe);
3322
3323 intel_disable_transcoder(dev_priv, pipe);
3324
3325 if (HAS_PCH_CPT(dev)) {
3326 /* disable TRANS_DP_CTL */
3327 reg = TRANS_DP_CTL(pipe);
3328 temp = I915_READ(reg);
3329 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3330 temp |= TRANS_DP_PORT_SEL_NONE;
3331 I915_WRITE(reg, temp);
3332
3333 /* disable DPLL_SEL */
3334 temp = I915_READ(PCH_DPLL_SEL);
3335 switch (pipe) {
3336 case 0:
3337 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3338 break;
3339 case 1:
3340 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3341 break;
3342 case 2:
3343 /* C shares PLL A or B */
3344 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3345 break;
3346 default:
3347 BUG(); /* wtf */
3348 }
3349 I915_WRITE(PCH_DPLL_SEL, temp);
3350 }
3351
3352 /* disable PCH DPLL */
3353 intel_disable_pch_pll(intel_crtc);
3354
3355 ironlake_fdi_pll_disable(intel_crtc);
3356
3357 intel_crtc->active = false;
3358 intel_update_watermarks(dev);
3359
3360 mutex_lock(&dev->struct_mutex);
3361 intel_update_fbc(dev);
3362 mutex_unlock(&dev->struct_mutex);
3363 }
3364
3365 static void ironlake_crtc_off(struct drm_crtc *crtc)
3366 {
3367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3368 intel_put_pch_pll(intel_crtc);
3369 }
3370
3371 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3372 {
3373 if (!enable && intel_crtc->overlay) {
3374 struct drm_device *dev = intel_crtc->base.dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376
3377 mutex_lock(&dev->struct_mutex);
3378 dev_priv->mm.interruptible = false;
3379 (void) intel_overlay_switch_off(intel_crtc->overlay);
3380 dev_priv->mm.interruptible = true;
3381 mutex_unlock(&dev->struct_mutex);
3382 }
3383
3384 /* Let userspace switch the overlay on again. In most cases userspace
3385 * has to recompute where to put it anyway.
3386 */
3387 }
3388
3389 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3390 {
3391 struct drm_device *dev = crtc->dev;
3392 struct drm_i915_private *dev_priv = dev->dev_private;
3393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3394 struct intel_encoder *encoder;
3395 int pipe = intel_crtc->pipe;
3396 int plane = intel_crtc->plane;
3397
3398 WARN_ON(!crtc->enabled);
3399
3400 if (intel_crtc->active)
3401 return;
3402
3403 intel_crtc->active = true;
3404 intel_update_watermarks(dev);
3405
3406 intel_enable_pll(dev_priv, pipe);
3407 intel_enable_pipe(dev_priv, pipe, false);
3408 intel_enable_plane(dev_priv, plane, pipe);
3409
3410 intel_crtc_load_lut(crtc);
3411 intel_update_fbc(dev);
3412
3413 /* Give the overlay scaler a chance to enable if it's on this pipe */
3414 intel_crtc_dpms_overlay(intel_crtc, true);
3415 intel_crtc_update_cursor(crtc, true);
3416
3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 encoder->enable(encoder);
3419 }
3420
3421 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3422 {
3423 struct drm_device *dev = crtc->dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426 struct intel_encoder *encoder;
3427 int pipe = intel_crtc->pipe;
3428 int plane = intel_crtc->plane;
3429
3430
3431 if (!intel_crtc->active)
3432 return;
3433
3434 for_each_encoder_on_crtc(dev, crtc, encoder)
3435 encoder->disable(encoder);
3436
3437 /* Give the overlay scaler a chance to disable if it's on this pipe */
3438 intel_crtc_wait_for_pending_flips(crtc);
3439 drm_vblank_off(dev, pipe);
3440 intel_crtc_dpms_overlay(intel_crtc, false);
3441 intel_crtc_update_cursor(crtc, false);
3442
3443 if (dev_priv->cfb_plane == plane)
3444 intel_disable_fbc(dev);
3445
3446 intel_disable_plane(dev_priv, plane, pipe);
3447 intel_disable_pipe(dev_priv, pipe);
3448 intel_disable_pll(dev_priv, pipe);
3449
3450 intel_crtc->active = false;
3451 intel_update_fbc(dev);
3452 intel_update_watermarks(dev);
3453 }
3454
3455 static void i9xx_crtc_off(struct drm_crtc *crtc)
3456 {
3457 }
3458
3459 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3460 bool enabled)
3461 {
3462 struct drm_device *dev = crtc->dev;
3463 struct drm_i915_master_private *master_priv;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465 int pipe = intel_crtc->pipe;
3466
3467 if (!dev->primary->master)
3468 return;
3469
3470 master_priv = dev->primary->master->driver_priv;
3471 if (!master_priv->sarea_priv)
3472 return;
3473
3474 switch (pipe) {
3475 case 0:
3476 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3477 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3478 break;
3479 case 1:
3480 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3481 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3482 break;
3483 default:
3484 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3485 break;
3486 }
3487 }
3488
3489 /**
3490 * Sets the power management mode of the pipe and plane.
3491 */
3492 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3493 {
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_encoder *intel_encoder;
3497 bool enable = false;
3498
3499 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3500 enable |= intel_encoder->connectors_active;
3501
3502 if (enable)
3503 dev_priv->display.crtc_enable(crtc);
3504 else
3505 dev_priv->display.crtc_disable(crtc);
3506
3507 intel_crtc_update_sarea(crtc, enable);
3508 }
3509
3510 static void intel_crtc_noop(struct drm_crtc *crtc)
3511 {
3512 }
3513
3514 static void intel_crtc_disable(struct drm_crtc *crtc)
3515 {
3516 struct drm_device *dev = crtc->dev;
3517 struct drm_connector *connector;
3518 struct drm_i915_private *dev_priv = dev->dev_private;
3519
3520 /* crtc should still be enabled when we disable it. */
3521 WARN_ON(!crtc->enabled);
3522
3523 dev_priv->display.crtc_disable(crtc);
3524 intel_crtc_update_sarea(crtc, false);
3525 dev_priv->display.off(crtc);
3526
3527 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3528 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3529
3530 if (crtc->fb) {
3531 mutex_lock(&dev->struct_mutex);
3532 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3533 mutex_unlock(&dev->struct_mutex);
3534 crtc->fb = NULL;
3535 }
3536
3537 /* Update computed state. */
3538 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3539 if (!connector->encoder || !connector->encoder->crtc)
3540 continue;
3541
3542 if (connector->encoder->crtc != crtc)
3543 continue;
3544
3545 connector->dpms = DRM_MODE_DPMS_OFF;
3546 to_intel_encoder(connector->encoder)->connectors_active = false;
3547 }
3548 }
3549
3550 void intel_modeset_disable(struct drm_device *dev)
3551 {
3552 struct drm_crtc *crtc;
3553
3554 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3555 if (crtc->enabled)
3556 intel_crtc_disable(crtc);
3557 }
3558 }
3559
3560 void intel_encoder_noop(struct drm_encoder *encoder)
3561 {
3562 }
3563
3564 void intel_encoder_destroy(struct drm_encoder *encoder)
3565 {
3566 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3567
3568 drm_encoder_cleanup(encoder);
3569 kfree(intel_encoder);
3570 }
3571
3572 /* Simple dpms helper for encodres with just one connector, no cloning and only
3573 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3574 * state of the entire output pipe. */
3575 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3576 {
3577 if (mode == DRM_MODE_DPMS_ON) {
3578 encoder->connectors_active = true;
3579
3580 intel_crtc_update_dpms(encoder->base.crtc);
3581 } else {
3582 encoder->connectors_active = false;
3583
3584 intel_crtc_update_dpms(encoder->base.crtc);
3585 }
3586 }
3587
3588 /* Cross check the actual hw state with our own modeset state tracking (and it's
3589 * internal consistency). */
3590 static void intel_connector_check_state(struct intel_connector *connector)
3591 {
3592 if (connector->get_hw_state(connector)) {
3593 struct intel_encoder *encoder = connector->encoder;
3594 struct drm_crtc *crtc;
3595 bool encoder_enabled;
3596 enum pipe pipe;
3597
3598 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3599 connector->base.base.id,
3600 drm_get_connector_name(&connector->base));
3601
3602 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3603 "wrong connector dpms state\n");
3604 WARN(connector->base.encoder != &encoder->base,
3605 "active connector not linked to encoder\n");
3606 WARN(!encoder->connectors_active,
3607 "encoder->connectors_active not set\n");
3608
3609 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3610 WARN(!encoder_enabled, "encoder not enabled\n");
3611 if (WARN_ON(!encoder->base.crtc))
3612 return;
3613
3614 crtc = encoder->base.crtc;
3615
3616 WARN(!crtc->enabled, "crtc not enabled\n");
3617 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3618 WARN(pipe != to_intel_crtc(crtc)->pipe,
3619 "encoder active on the wrong pipe\n");
3620 }
3621 }
3622
3623 /* Even simpler default implementation, if there's really no special case to
3624 * consider. */
3625 void intel_connector_dpms(struct drm_connector *connector, int mode)
3626 {
3627 struct intel_encoder *encoder = intel_attached_encoder(connector);
3628
3629 /* All the simple cases only support two dpms states. */
3630 if (mode != DRM_MODE_DPMS_ON)
3631 mode = DRM_MODE_DPMS_OFF;
3632
3633 if (mode == connector->dpms)
3634 return;
3635
3636 connector->dpms = mode;
3637
3638 /* Only need to change hw state when actually enabled */
3639 if (encoder->base.crtc)
3640 intel_encoder_dpms(encoder, mode);
3641 else
3642 WARN_ON(encoder->connectors_active != false);
3643
3644 intel_modeset_check_state(connector->dev);
3645 }
3646
3647 /* Simple connector->get_hw_state implementation for encoders that support only
3648 * one connector and no cloning and hence the encoder state determines the state
3649 * of the connector. */
3650 bool intel_connector_get_hw_state(struct intel_connector *connector)
3651 {
3652 enum pipe pipe = 0;
3653 struct intel_encoder *encoder = connector->encoder;
3654
3655 return encoder->get_hw_state(encoder, &pipe);
3656 }
3657
3658 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3659 const struct drm_display_mode *mode,
3660 struct drm_display_mode *adjusted_mode)
3661 {
3662 struct drm_device *dev = crtc->dev;
3663
3664 if (HAS_PCH_SPLIT(dev)) {
3665 /* FDI link clock is fixed at 2.7G */
3666 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3667 return false;
3668 }
3669
3670 /* All interlaced capable intel hw wants timings in frames. Note though
3671 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3672 * timings, so we need to be careful not to clobber these.*/
3673 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3674 drm_mode_set_crtcinfo(adjusted_mode, 0);
3675
3676 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3677 * with a hsync front porch of 0.
3678 */
3679 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3680 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3681 return false;
3682
3683 return true;
3684 }
3685
3686 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3687 {
3688 return 400000; /* FIXME */
3689 }
3690
3691 static int i945_get_display_clock_speed(struct drm_device *dev)
3692 {
3693 return 400000;
3694 }
3695
3696 static int i915_get_display_clock_speed(struct drm_device *dev)
3697 {
3698 return 333000;
3699 }
3700
3701 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3702 {
3703 return 200000;
3704 }
3705
3706 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3707 {
3708 u16 gcfgc = 0;
3709
3710 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3711
3712 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3713 return 133000;
3714 else {
3715 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3716 case GC_DISPLAY_CLOCK_333_MHZ:
3717 return 333000;
3718 default:
3719 case GC_DISPLAY_CLOCK_190_200_MHZ:
3720 return 190000;
3721 }
3722 }
3723 }
3724
3725 static int i865_get_display_clock_speed(struct drm_device *dev)
3726 {
3727 return 266000;
3728 }
3729
3730 static int i855_get_display_clock_speed(struct drm_device *dev)
3731 {
3732 u16 hpllcc = 0;
3733 /* Assume that the hardware is in the high speed state. This
3734 * should be the default.
3735 */
3736 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3737 case GC_CLOCK_133_200:
3738 case GC_CLOCK_100_200:
3739 return 200000;
3740 case GC_CLOCK_166_250:
3741 return 250000;
3742 case GC_CLOCK_100_133:
3743 return 133000;
3744 }
3745
3746 /* Shouldn't happen */
3747 return 0;
3748 }
3749
3750 static int i830_get_display_clock_speed(struct drm_device *dev)
3751 {
3752 return 133000;
3753 }
3754
3755 struct fdi_m_n {
3756 u32 tu;
3757 u32 gmch_m;
3758 u32 gmch_n;
3759 u32 link_m;
3760 u32 link_n;
3761 };
3762
3763 static void
3764 fdi_reduce_ratio(u32 *num, u32 *den)
3765 {
3766 while (*num > 0xffffff || *den > 0xffffff) {
3767 *num >>= 1;
3768 *den >>= 1;
3769 }
3770 }
3771
3772 static void
3773 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3774 int link_clock, struct fdi_m_n *m_n)
3775 {
3776 m_n->tu = 64; /* default size */
3777
3778 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3779 m_n->gmch_m = bits_per_pixel * pixel_clock;
3780 m_n->gmch_n = link_clock * nlanes * 8;
3781 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3782
3783 m_n->link_m = pixel_clock;
3784 m_n->link_n = link_clock;
3785 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3786 }
3787
3788 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3789 {
3790 if (i915_panel_use_ssc >= 0)
3791 return i915_panel_use_ssc != 0;
3792 return dev_priv->lvds_use_ssc
3793 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3794 }
3795
3796 /**
3797 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3798 * @crtc: CRTC structure
3799 * @mode: requested mode
3800 *
3801 * A pipe may be connected to one or more outputs. Based on the depth of the
3802 * attached framebuffer, choose a good color depth to use on the pipe.
3803 *
3804 * If possible, match the pipe depth to the fb depth. In some cases, this
3805 * isn't ideal, because the connected output supports a lesser or restricted
3806 * set of depths. Resolve that here:
3807 * LVDS typically supports only 6bpc, so clamp down in that case
3808 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3809 * Displays may support a restricted set as well, check EDID and clamp as
3810 * appropriate.
3811 * DP may want to dither down to 6bpc to fit larger modes
3812 *
3813 * RETURNS:
3814 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3815 * true if they don't match).
3816 */
3817 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3818 struct drm_framebuffer *fb,
3819 unsigned int *pipe_bpp,
3820 struct drm_display_mode *mode)
3821 {
3822 struct drm_device *dev = crtc->dev;
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 struct drm_connector *connector;
3825 struct intel_encoder *intel_encoder;
3826 unsigned int display_bpc = UINT_MAX, bpc;
3827
3828 /* Walk the encoders & connectors on this crtc, get min bpc */
3829 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3830
3831 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3832 unsigned int lvds_bpc;
3833
3834 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3835 LVDS_A3_POWER_UP)
3836 lvds_bpc = 8;
3837 else
3838 lvds_bpc = 6;
3839
3840 if (lvds_bpc < display_bpc) {
3841 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3842 display_bpc = lvds_bpc;
3843 }
3844 continue;
3845 }
3846
3847 /* Not one of the known troublemakers, check the EDID */
3848 list_for_each_entry(connector, &dev->mode_config.connector_list,
3849 head) {
3850 if (connector->encoder != &intel_encoder->base)
3851 continue;
3852
3853 /* Don't use an invalid EDID bpc value */
3854 if (connector->display_info.bpc &&
3855 connector->display_info.bpc < display_bpc) {
3856 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3857 display_bpc = connector->display_info.bpc;
3858 }
3859 }
3860
3861 /*
3862 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3863 * through, clamp it down. (Note: >12bpc will be caught below.)
3864 */
3865 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3866 if (display_bpc > 8 && display_bpc < 12) {
3867 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3868 display_bpc = 12;
3869 } else {
3870 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3871 display_bpc = 8;
3872 }
3873 }
3874 }
3875
3876 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3877 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3878 display_bpc = 6;
3879 }
3880
3881 /*
3882 * We could just drive the pipe at the highest bpc all the time and
3883 * enable dithering as needed, but that costs bandwidth. So choose
3884 * the minimum value that expresses the full color range of the fb but
3885 * also stays within the max display bpc discovered above.
3886 */
3887
3888 switch (fb->depth) {
3889 case 8:
3890 bpc = 8; /* since we go through a colormap */
3891 break;
3892 case 15:
3893 case 16:
3894 bpc = 6; /* min is 18bpp */
3895 break;
3896 case 24:
3897 bpc = 8;
3898 break;
3899 case 30:
3900 bpc = 10;
3901 break;
3902 case 48:
3903 bpc = 12;
3904 break;
3905 default:
3906 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3907 bpc = min((unsigned int)8, display_bpc);
3908 break;
3909 }
3910
3911 display_bpc = min(display_bpc, bpc);
3912
3913 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3914 bpc, display_bpc);
3915
3916 *pipe_bpp = display_bpc * 3;
3917
3918 return display_bpc != bpc;
3919 }
3920
3921 static int vlv_get_refclk(struct drm_crtc *crtc)
3922 {
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 int refclk = 27000; /* for DP & HDMI */
3926
3927 return 100000; /* only one validated so far */
3928
3929 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3930 refclk = 96000;
3931 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3932 if (intel_panel_use_ssc(dev_priv))
3933 refclk = 100000;
3934 else
3935 refclk = 96000;
3936 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3937 refclk = 100000;
3938 }
3939
3940 return refclk;
3941 }
3942
3943 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3944 {
3945 struct drm_device *dev = crtc->dev;
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 int refclk;
3948
3949 if (IS_VALLEYVIEW(dev)) {
3950 refclk = vlv_get_refclk(crtc);
3951 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3952 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3953 refclk = dev_priv->lvds_ssc_freq * 1000;
3954 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3955 refclk / 1000);
3956 } else if (!IS_GEN2(dev)) {
3957 refclk = 96000;
3958 } else {
3959 refclk = 48000;
3960 }
3961
3962 return refclk;
3963 }
3964
3965 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3966 intel_clock_t *clock)
3967 {
3968 /* SDVO TV has fixed PLL values depend on its clock range,
3969 this mirrors vbios setting. */
3970 if (adjusted_mode->clock >= 100000
3971 && adjusted_mode->clock < 140500) {
3972 clock->p1 = 2;
3973 clock->p2 = 10;
3974 clock->n = 3;
3975 clock->m1 = 16;
3976 clock->m2 = 8;
3977 } else if (adjusted_mode->clock >= 140500
3978 && adjusted_mode->clock <= 200000) {
3979 clock->p1 = 1;
3980 clock->p2 = 10;
3981 clock->n = 6;
3982 clock->m1 = 12;
3983 clock->m2 = 8;
3984 }
3985 }
3986
3987 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3988 intel_clock_t *clock,
3989 intel_clock_t *reduced_clock)
3990 {
3991 struct drm_device *dev = crtc->dev;
3992 struct drm_i915_private *dev_priv = dev->dev_private;
3993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3994 int pipe = intel_crtc->pipe;
3995 u32 fp, fp2 = 0;
3996
3997 if (IS_PINEVIEW(dev)) {
3998 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3999 if (reduced_clock)
4000 fp2 = (1 << reduced_clock->n) << 16 |
4001 reduced_clock->m1 << 8 | reduced_clock->m2;
4002 } else {
4003 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4004 if (reduced_clock)
4005 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4006 reduced_clock->m2;
4007 }
4008
4009 I915_WRITE(FP0(pipe), fp);
4010
4011 intel_crtc->lowfreq_avail = false;
4012 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4013 reduced_clock && i915_powersave) {
4014 I915_WRITE(FP1(pipe), fp2);
4015 intel_crtc->lowfreq_avail = true;
4016 } else {
4017 I915_WRITE(FP1(pipe), fp);
4018 }
4019 }
4020
4021 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4022 struct drm_display_mode *adjusted_mode)
4023 {
4024 struct drm_device *dev = crtc->dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4027 int pipe = intel_crtc->pipe;
4028 u32 temp;
4029
4030 temp = I915_READ(LVDS);
4031 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4032 if (pipe == 1) {
4033 temp |= LVDS_PIPEB_SELECT;
4034 } else {
4035 temp &= ~LVDS_PIPEB_SELECT;
4036 }
4037 /* set the corresponsding LVDS_BORDER bit */
4038 temp |= dev_priv->lvds_border_bits;
4039 /* Set the B0-B3 data pairs corresponding to whether we're going to
4040 * set the DPLLs for dual-channel mode or not.
4041 */
4042 if (clock->p2 == 7)
4043 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4044 else
4045 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4046
4047 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4048 * appropriately here, but we need to look more thoroughly into how
4049 * panels behave in the two modes.
4050 */
4051 /* set the dithering flag on LVDS as needed */
4052 if (INTEL_INFO(dev)->gen >= 4) {
4053 if (dev_priv->lvds_dither)
4054 temp |= LVDS_ENABLE_DITHER;
4055 else
4056 temp &= ~LVDS_ENABLE_DITHER;
4057 }
4058 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4059 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4060 temp |= LVDS_HSYNC_POLARITY;
4061 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4062 temp |= LVDS_VSYNC_POLARITY;
4063 I915_WRITE(LVDS, temp);
4064 }
4065
4066 static void vlv_update_pll(struct drm_crtc *crtc,
4067 struct drm_display_mode *mode,
4068 struct drm_display_mode *adjusted_mode,
4069 intel_clock_t *clock, intel_clock_t *reduced_clock,
4070 int refclk, int num_connectors)
4071 {
4072 struct drm_device *dev = crtc->dev;
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4075 int pipe = intel_crtc->pipe;
4076 u32 dpll, mdiv, pdiv;
4077 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4078 bool is_hdmi;
4079
4080 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4081
4082 bestn = clock->n;
4083 bestm1 = clock->m1;
4084 bestm2 = clock->m2;
4085 bestp1 = clock->p1;
4086 bestp2 = clock->p2;
4087
4088 /* Enable DPIO clock input */
4089 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4090 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4091 I915_WRITE(DPLL(pipe), dpll);
4092 POSTING_READ(DPLL(pipe));
4093
4094 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4095 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4096 mdiv |= ((bestn << DPIO_N_SHIFT));
4097 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4098 mdiv |= (1 << DPIO_K_SHIFT);
4099 mdiv |= DPIO_ENABLE_CALIBRATION;
4100 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4101
4102 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4103
4104 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4105 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4106 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4107 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4108
4109 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4110
4111 dpll |= DPLL_VCO_ENABLE;
4112 I915_WRITE(DPLL(pipe), dpll);
4113 POSTING_READ(DPLL(pipe));
4114 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4115 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4116
4117 if (is_hdmi) {
4118 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4119
4120 if (temp > 1)
4121 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4122 else
4123 temp = 0;
4124
4125 I915_WRITE(DPLL_MD(pipe), temp);
4126 POSTING_READ(DPLL_MD(pipe));
4127 }
4128
4129 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4130 }
4131
4132 static void i9xx_update_pll(struct drm_crtc *crtc,
4133 struct drm_display_mode *mode,
4134 struct drm_display_mode *adjusted_mode,
4135 intel_clock_t *clock, intel_clock_t *reduced_clock,
4136 int num_connectors)
4137 {
4138 struct drm_device *dev = crtc->dev;
4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4141 int pipe = intel_crtc->pipe;
4142 u32 dpll;
4143 bool is_sdvo;
4144
4145 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4146 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4147
4148 dpll = DPLL_VGA_MODE_DIS;
4149
4150 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4151 dpll |= DPLLB_MODE_LVDS;
4152 else
4153 dpll |= DPLLB_MODE_DAC_SERIAL;
4154 if (is_sdvo) {
4155 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4156 if (pixel_multiplier > 1) {
4157 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4158 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4159 }
4160 dpll |= DPLL_DVO_HIGH_SPEED;
4161 }
4162 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4163 dpll |= DPLL_DVO_HIGH_SPEED;
4164
4165 /* compute bitmask from p1 value */
4166 if (IS_PINEVIEW(dev))
4167 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4168 else {
4169 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4170 if (IS_G4X(dev) && reduced_clock)
4171 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4172 }
4173 switch (clock->p2) {
4174 case 5:
4175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4176 break;
4177 case 7:
4178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4179 break;
4180 case 10:
4181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4182 break;
4183 case 14:
4184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4185 break;
4186 }
4187 if (INTEL_INFO(dev)->gen >= 4)
4188 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4189
4190 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4191 dpll |= PLL_REF_INPUT_TVCLKINBC;
4192 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4193 /* XXX: just matching BIOS for now */
4194 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4195 dpll |= 3;
4196 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4198 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4199 else
4200 dpll |= PLL_REF_INPUT_DREFCLK;
4201
4202 dpll |= DPLL_VCO_ENABLE;
4203 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4204 POSTING_READ(DPLL(pipe));
4205 udelay(150);
4206
4207 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4208 * This is an exception to the general rule that mode_set doesn't turn
4209 * things on.
4210 */
4211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4212 intel_update_lvds(crtc, clock, adjusted_mode);
4213
4214 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4215 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4216
4217 I915_WRITE(DPLL(pipe), dpll);
4218
4219 /* Wait for the clocks to stabilize. */
4220 POSTING_READ(DPLL(pipe));
4221 udelay(150);
4222
4223 if (INTEL_INFO(dev)->gen >= 4) {
4224 u32 temp = 0;
4225 if (is_sdvo) {
4226 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4227 if (temp > 1)
4228 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4229 else
4230 temp = 0;
4231 }
4232 I915_WRITE(DPLL_MD(pipe), temp);
4233 } else {
4234 /* The pixel multiplier can only be updated once the
4235 * DPLL is enabled and the clocks are stable.
4236 *
4237 * So write it again.
4238 */
4239 I915_WRITE(DPLL(pipe), dpll);
4240 }
4241 }
4242
4243 static void i8xx_update_pll(struct drm_crtc *crtc,
4244 struct drm_display_mode *adjusted_mode,
4245 intel_clock_t *clock,
4246 int num_connectors)
4247 {
4248 struct drm_device *dev = crtc->dev;
4249 struct drm_i915_private *dev_priv = dev->dev_private;
4250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251 int pipe = intel_crtc->pipe;
4252 u32 dpll;
4253
4254 dpll = DPLL_VGA_MODE_DIS;
4255
4256 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4257 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4258 } else {
4259 if (clock->p1 == 2)
4260 dpll |= PLL_P1_DIVIDE_BY_TWO;
4261 else
4262 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4263 if (clock->p2 == 4)
4264 dpll |= PLL_P2_DIVIDE_BY_4;
4265 }
4266
4267 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4268 /* XXX: just matching BIOS for now */
4269 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4270 dpll |= 3;
4271 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4272 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4273 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4274 else
4275 dpll |= PLL_REF_INPUT_DREFCLK;
4276
4277 dpll |= DPLL_VCO_ENABLE;
4278 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4279 POSTING_READ(DPLL(pipe));
4280 udelay(150);
4281
4282 I915_WRITE(DPLL(pipe), dpll);
4283
4284 /* Wait for the clocks to stabilize. */
4285 POSTING_READ(DPLL(pipe));
4286 udelay(150);
4287
4288 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4289 * This is an exception to the general rule that mode_set doesn't turn
4290 * things on.
4291 */
4292 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4293 intel_update_lvds(crtc, clock, adjusted_mode);
4294
4295 /* The pixel multiplier can only be updated once the
4296 * DPLL is enabled and the clocks are stable.
4297 *
4298 * So write it again.
4299 */
4300 I915_WRITE(DPLL(pipe), dpll);
4301 }
4302
4303 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4304 struct drm_display_mode *mode,
4305 struct drm_display_mode *adjusted_mode,
4306 int x, int y,
4307 struct drm_framebuffer *fb)
4308 {
4309 struct drm_device *dev = crtc->dev;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4312 int pipe = intel_crtc->pipe;
4313 int plane = intel_crtc->plane;
4314 int refclk, num_connectors = 0;
4315 intel_clock_t clock, reduced_clock;
4316 u32 dspcntr, pipeconf, vsyncshift;
4317 bool ok, has_reduced_clock = false, is_sdvo = false;
4318 bool is_lvds = false, is_tv = false, is_dp = false;
4319 struct intel_encoder *encoder;
4320 const intel_limit_t *limit;
4321 int ret;
4322
4323 for_each_encoder_on_crtc(dev, crtc, encoder) {
4324 switch (encoder->type) {
4325 case INTEL_OUTPUT_LVDS:
4326 is_lvds = true;
4327 break;
4328 case INTEL_OUTPUT_SDVO:
4329 case INTEL_OUTPUT_HDMI:
4330 is_sdvo = true;
4331 if (encoder->needs_tv_clock)
4332 is_tv = true;
4333 break;
4334 case INTEL_OUTPUT_TVOUT:
4335 is_tv = true;
4336 break;
4337 case INTEL_OUTPUT_DISPLAYPORT:
4338 is_dp = true;
4339 break;
4340 }
4341
4342 num_connectors++;
4343 }
4344
4345 refclk = i9xx_get_refclk(crtc, num_connectors);
4346
4347 /*
4348 * Returns a set of divisors for the desired target clock with the given
4349 * refclk, or FALSE. The returned values represent the clock equation:
4350 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4351 */
4352 limit = intel_limit(crtc, refclk);
4353 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4354 &clock);
4355 if (!ok) {
4356 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4357 return -EINVAL;
4358 }
4359
4360 /* Ensure that the cursor is valid for the new mode before changing... */
4361 intel_crtc_update_cursor(crtc, true);
4362
4363 if (is_lvds && dev_priv->lvds_downclock_avail) {
4364 /*
4365 * Ensure we match the reduced clock's P to the target clock.
4366 * If the clocks don't match, we can't switch the display clock
4367 * by using the FP0/FP1. In such case we will disable the LVDS
4368 * downclock feature.
4369 */
4370 has_reduced_clock = limit->find_pll(limit, crtc,
4371 dev_priv->lvds_downclock,
4372 refclk,
4373 &clock,
4374 &reduced_clock);
4375 }
4376
4377 if (is_sdvo && is_tv)
4378 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4379
4380 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4381 &reduced_clock : NULL);
4382
4383 if (IS_GEN2(dev))
4384 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4385 else if (IS_VALLEYVIEW(dev))
4386 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4387 refclk, num_connectors);
4388 else
4389 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4390 has_reduced_clock ? &reduced_clock : NULL,
4391 num_connectors);
4392
4393 /* setup pipeconf */
4394 pipeconf = I915_READ(PIPECONF(pipe));
4395
4396 /* Set up the display plane register */
4397 dspcntr = DISPPLANE_GAMMA_ENABLE;
4398
4399 if (pipe == 0)
4400 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4401 else
4402 dspcntr |= DISPPLANE_SEL_PIPE_B;
4403
4404 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4405 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4406 * core speed.
4407 *
4408 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4409 * pipe == 0 check?
4410 */
4411 if (mode->clock >
4412 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4413 pipeconf |= PIPECONF_DOUBLE_WIDE;
4414 else
4415 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4416 }
4417
4418 /* default to 8bpc */
4419 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4420 if (is_dp) {
4421 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4422 pipeconf |= PIPECONF_BPP_6 |
4423 PIPECONF_DITHER_EN |
4424 PIPECONF_DITHER_TYPE_SP;
4425 }
4426 }
4427
4428 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4429 drm_mode_debug_printmodeline(mode);
4430
4431 if (HAS_PIPE_CXSR(dev)) {
4432 if (intel_crtc->lowfreq_avail) {
4433 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4434 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4435 } else {
4436 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4437 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4438 }
4439 }
4440
4441 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4442 if (!IS_GEN2(dev) &&
4443 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4444 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4445 /* the chip adds 2 halflines automatically */
4446 adjusted_mode->crtc_vtotal -= 1;
4447 adjusted_mode->crtc_vblank_end -= 1;
4448 vsyncshift = adjusted_mode->crtc_hsync_start
4449 - adjusted_mode->crtc_htotal/2;
4450 } else {
4451 pipeconf |= PIPECONF_PROGRESSIVE;
4452 vsyncshift = 0;
4453 }
4454
4455 if (!IS_GEN3(dev))
4456 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4457
4458 I915_WRITE(HTOTAL(pipe),
4459 (adjusted_mode->crtc_hdisplay - 1) |
4460 ((adjusted_mode->crtc_htotal - 1) << 16));
4461 I915_WRITE(HBLANK(pipe),
4462 (adjusted_mode->crtc_hblank_start - 1) |
4463 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4464 I915_WRITE(HSYNC(pipe),
4465 (adjusted_mode->crtc_hsync_start - 1) |
4466 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4467
4468 I915_WRITE(VTOTAL(pipe),
4469 (adjusted_mode->crtc_vdisplay - 1) |
4470 ((adjusted_mode->crtc_vtotal - 1) << 16));
4471 I915_WRITE(VBLANK(pipe),
4472 (adjusted_mode->crtc_vblank_start - 1) |
4473 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4474 I915_WRITE(VSYNC(pipe),
4475 (adjusted_mode->crtc_vsync_start - 1) |
4476 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4477
4478 /* pipesrc and dspsize control the size that is scaled from,
4479 * which should always be the user's requested size.
4480 */
4481 I915_WRITE(DSPSIZE(plane),
4482 ((mode->vdisplay - 1) << 16) |
4483 (mode->hdisplay - 1));
4484 I915_WRITE(DSPPOS(plane), 0);
4485 I915_WRITE(PIPESRC(pipe),
4486 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4487
4488 I915_WRITE(PIPECONF(pipe), pipeconf);
4489 POSTING_READ(PIPECONF(pipe));
4490 intel_enable_pipe(dev_priv, pipe, false);
4491
4492 intel_wait_for_vblank(dev, pipe);
4493
4494 I915_WRITE(DSPCNTR(plane), dspcntr);
4495 POSTING_READ(DSPCNTR(plane));
4496
4497 ret = intel_pipe_set_base(crtc, x, y, fb);
4498
4499 intel_update_watermarks(dev);
4500
4501 return ret;
4502 }
4503
4504 /*
4505 * Initialize reference clocks when the driver loads
4506 */
4507 void ironlake_init_pch_refclk(struct drm_device *dev)
4508 {
4509 struct drm_i915_private *dev_priv = dev->dev_private;
4510 struct drm_mode_config *mode_config = &dev->mode_config;
4511 struct intel_encoder *encoder;
4512 u32 temp;
4513 bool has_lvds = false;
4514 bool has_cpu_edp = false;
4515 bool has_pch_edp = false;
4516 bool has_panel = false;
4517 bool has_ck505 = false;
4518 bool can_ssc = false;
4519
4520 /* We need to take the global config into account */
4521 list_for_each_entry(encoder, &mode_config->encoder_list,
4522 base.head) {
4523 switch (encoder->type) {
4524 case INTEL_OUTPUT_LVDS:
4525 has_panel = true;
4526 has_lvds = true;
4527 break;
4528 case INTEL_OUTPUT_EDP:
4529 has_panel = true;
4530 if (intel_encoder_is_pch_edp(&encoder->base))
4531 has_pch_edp = true;
4532 else
4533 has_cpu_edp = true;
4534 break;
4535 }
4536 }
4537
4538 if (HAS_PCH_IBX(dev)) {
4539 has_ck505 = dev_priv->display_clock_mode;
4540 can_ssc = has_ck505;
4541 } else {
4542 has_ck505 = false;
4543 can_ssc = true;
4544 }
4545
4546 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4547 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4548 has_ck505);
4549
4550 /* Ironlake: try to setup display ref clock before DPLL
4551 * enabling. This is only under driver's control after
4552 * PCH B stepping, previous chipset stepping should be
4553 * ignoring this setting.
4554 */
4555 temp = I915_READ(PCH_DREF_CONTROL);
4556 /* Always enable nonspread source */
4557 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4558
4559 if (has_ck505)
4560 temp |= DREF_NONSPREAD_CK505_ENABLE;
4561 else
4562 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4563
4564 if (has_panel) {
4565 temp &= ~DREF_SSC_SOURCE_MASK;
4566 temp |= DREF_SSC_SOURCE_ENABLE;
4567
4568 /* SSC must be turned on before enabling the CPU output */
4569 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4570 DRM_DEBUG_KMS("Using SSC on panel\n");
4571 temp |= DREF_SSC1_ENABLE;
4572 } else
4573 temp &= ~DREF_SSC1_ENABLE;
4574
4575 /* Get SSC going before enabling the outputs */
4576 I915_WRITE(PCH_DREF_CONTROL, temp);
4577 POSTING_READ(PCH_DREF_CONTROL);
4578 udelay(200);
4579
4580 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4581
4582 /* Enable CPU source on CPU attached eDP */
4583 if (has_cpu_edp) {
4584 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4585 DRM_DEBUG_KMS("Using SSC on eDP\n");
4586 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4587 }
4588 else
4589 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4590 } else
4591 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4592
4593 I915_WRITE(PCH_DREF_CONTROL, temp);
4594 POSTING_READ(PCH_DREF_CONTROL);
4595 udelay(200);
4596 } else {
4597 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4598
4599 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4600
4601 /* Turn off CPU output */
4602 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4603
4604 I915_WRITE(PCH_DREF_CONTROL, temp);
4605 POSTING_READ(PCH_DREF_CONTROL);
4606 udelay(200);
4607
4608 /* Turn off the SSC source */
4609 temp &= ~DREF_SSC_SOURCE_MASK;
4610 temp |= DREF_SSC_SOURCE_DISABLE;
4611
4612 /* Turn off SSC1 */
4613 temp &= ~ DREF_SSC1_ENABLE;
4614
4615 I915_WRITE(PCH_DREF_CONTROL, temp);
4616 POSTING_READ(PCH_DREF_CONTROL);
4617 udelay(200);
4618 }
4619 }
4620
4621 static int ironlake_get_refclk(struct drm_crtc *crtc)
4622 {
4623 struct drm_device *dev = crtc->dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625 struct intel_encoder *encoder;
4626 struct intel_encoder *edp_encoder = NULL;
4627 int num_connectors = 0;
4628 bool is_lvds = false;
4629
4630 for_each_encoder_on_crtc(dev, crtc, encoder) {
4631 switch (encoder->type) {
4632 case INTEL_OUTPUT_LVDS:
4633 is_lvds = true;
4634 break;
4635 case INTEL_OUTPUT_EDP:
4636 edp_encoder = encoder;
4637 break;
4638 }
4639 num_connectors++;
4640 }
4641
4642 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4643 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4644 dev_priv->lvds_ssc_freq);
4645 return dev_priv->lvds_ssc_freq * 1000;
4646 }
4647
4648 return 120000;
4649 }
4650
4651 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4652 struct drm_display_mode *adjusted_mode,
4653 bool dither)
4654 {
4655 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4657 int pipe = intel_crtc->pipe;
4658 uint32_t val;
4659
4660 val = I915_READ(PIPECONF(pipe));
4661
4662 val &= ~PIPE_BPC_MASK;
4663 switch (intel_crtc->bpp) {
4664 case 18:
4665 val |= PIPE_6BPC;
4666 break;
4667 case 24:
4668 val |= PIPE_8BPC;
4669 break;
4670 case 30:
4671 val |= PIPE_10BPC;
4672 break;
4673 case 36:
4674 val |= PIPE_12BPC;
4675 break;
4676 default:
4677 val |= PIPE_8BPC;
4678 break;
4679 }
4680
4681 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4682 if (dither)
4683 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4684
4685 val &= ~PIPECONF_INTERLACE_MASK;
4686 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4687 val |= PIPECONF_INTERLACED_ILK;
4688 else
4689 val |= PIPECONF_PROGRESSIVE;
4690
4691 I915_WRITE(PIPECONF(pipe), val);
4692 POSTING_READ(PIPECONF(pipe));
4693 }
4694
4695 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4696 struct drm_display_mode *mode,
4697 struct drm_display_mode *adjusted_mode,
4698 int x, int y,
4699 struct drm_framebuffer *fb)
4700 {
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 int pipe = intel_crtc->pipe;
4705 int plane = intel_crtc->plane;
4706 int refclk, num_connectors = 0;
4707 intel_clock_t clock, reduced_clock;
4708 u32 dpll, fp = 0, fp2 = 0;
4709 bool ok, has_reduced_clock = false, is_sdvo = false;
4710 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4711 struct intel_encoder *encoder, *edp_encoder = NULL;
4712 const intel_limit_t *limit;
4713 int ret;
4714 struct fdi_m_n m_n = {0};
4715 u32 temp;
4716 int target_clock, pixel_multiplier, lane, link_bw, factor;
4717 unsigned int pipe_bpp;
4718 bool dither;
4719 bool is_cpu_edp = false, is_pch_edp = false;
4720
4721 for_each_encoder_on_crtc(dev, crtc, encoder) {
4722 switch (encoder->type) {
4723 case INTEL_OUTPUT_LVDS:
4724 is_lvds = true;
4725 break;
4726 case INTEL_OUTPUT_SDVO:
4727 case INTEL_OUTPUT_HDMI:
4728 is_sdvo = true;
4729 if (encoder->needs_tv_clock)
4730 is_tv = true;
4731 break;
4732 case INTEL_OUTPUT_TVOUT:
4733 is_tv = true;
4734 break;
4735 case INTEL_OUTPUT_ANALOG:
4736 is_crt = true;
4737 break;
4738 case INTEL_OUTPUT_DISPLAYPORT:
4739 is_dp = true;
4740 break;
4741 case INTEL_OUTPUT_EDP:
4742 is_dp = true;
4743 if (intel_encoder_is_pch_edp(&encoder->base))
4744 is_pch_edp = true;
4745 else
4746 is_cpu_edp = true;
4747 edp_encoder = encoder;
4748 break;
4749 }
4750
4751 num_connectors++;
4752 }
4753
4754 refclk = ironlake_get_refclk(crtc);
4755
4756 /*
4757 * Returns a set of divisors for the desired target clock with the given
4758 * refclk, or FALSE. The returned values represent the clock equation:
4759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4760 */
4761 limit = intel_limit(crtc, refclk);
4762 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4763 &clock);
4764 if (!ok) {
4765 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4766 return -EINVAL;
4767 }
4768
4769 /* Ensure that the cursor is valid for the new mode before changing... */
4770 intel_crtc_update_cursor(crtc, true);
4771
4772 if (is_lvds && dev_priv->lvds_downclock_avail) {
4773 /*
4774 * Ensure we match the reduced clock's P to the target clock.
4775 * If the clocks don't match, we can't switch the display clock
4776 * by using the FP0/FP1. In such case we will disable the LVDS
4777 * downclock feature.
4778 */
4779 has_reduced_clock = limit->find_pll(limit, crtc,
4780 dev_priv->lvds_downclock,
4781 refclk,
4782 &clock,
4783 &reduced_clock);
4784 }
4785
4786 if (is_sdvo && is_tv)
4787 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4788
4789
4790 /* FDI link */
4791 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4792 lane = 0;
4793 /* CPU eDP doesn't require FDI link, so just set DP M/N
4794 according to current link config */
4795 if (is_cpu_edp) {
4796 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4797 } else {
4798 /* FDI is a binary signal running at ~2.7GHz, encoding
4799 * each output octet as 10 bits. The actual frequency
4800 * is stored as a divider into a 100MHz clock, and the
4801 * mode pixel clock is stored in units of 1KHz.
4802 * Hence the bw of each lane in terms of the mode signal
4803 * is:
4804 */
4805 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4806 }
4807
4808 /* [e]DP over FDI requires target mode clock instead of link clock. */
4809 if (edp_encoder)
4810 target_clock = intel_edp_target_clock(edp_encoder, mode);
4811 else if (is_dp)
4812 target_clock = mode->clock;
4813 else
4814 target_clock = adjusted_mode->clock;
4815
4816 /* determine panel color depth */
4817 dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
4818 if (is_lvds && dev_priv->lvds_dither)
4819 dither = true;
4820
4821 if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
4822 pipe_bpp != 36) {
4823 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4824 pipe_bpp);
4825 pipe_bpp = 24;
4826 }
4827 intel_crtc->bpp = pipe_bpp;
4828
4829 if (!lane) {
4830 /*
4831 * Account for spread spectrum to avoid
4832 * oversubscribing the link. Max center spread
4833 * is 2.5%; use 5% for safety's sake.
4834 */
4835 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4836 lane = bps / (link_bw * 8) + 1;
4837 }
4838
4839 intel_crtc->fdi_lanes = lane;
4840
4841 if (pixel_multiplier > 1)
4842 link_bw *= pixel_multiplier;
4843 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4844 &m_n);
4845
4846 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4847 if (has_reduced_clock)
4848 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4849 reduced_clock.m2;
4850
4851 /* Enable autotuning of the PLL clock (if permissible) */
4852 factor = 21;
4853 if (is_lvds) {
4854 if ((intel_panel_use_ssc(dev_priv) &&
4855 dev_priv->lvds_ssc_freq == 100) ||
4856 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4857 factor = 25;
4858 } else if (is_sdvo && is_tv)
4859 factor = 20;
4860
4861 if (clock.m < factor * clock.n)
4862 fp |= FP_CB_TUNE;
4863
4864 dpll = 0;
4865
4866 if (is_lvds)
4867 dpll |= DPLLB_MODE_LVDS;
4868 else
4869 dpll |= DPLLB_MODE_DAC_SERIAL;
4870 if (is_sdvo) {
4871 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4872 if (pixel_multiplier > 1) {
4873 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4874 }
4875 dpll |= DPLL_DVO_HIGH_SPEED;
4876 }
4877 if (is_dp && !is_cpu_edp)
4878 dpll |= DPLL_DVO_HIGH_SPEED;
4879
4880 /* compute bitmask from p1 value */
4881 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4882 /* also FPA1 */
4883 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4884
4885 switch (clock.p2) {
4886 case 5:
4887 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4888 break;
4889 case 7:
4890 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4891 break;
4892 case 10:
4893 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4894 break;
4895 case 14:
4896 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4897 break;
4898 }
4899
4900 if (is_sdvo && is_tv)
4901 dpll |= PLL_REF_INPUT_TVCLKINBC;
4902 else if (is_tv)
4903 /* XXX: just matching BIOS for now */
4904 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4905 dpll |= 3;
4906 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4907 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4908 else
4909 dpll |= PLL_REF_INPUT_DREFCLK;
4910
4911 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4912 drm_mode_debug_printmodeline(mode);
4913
4914 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4915 * pre-Haswell/LPT generation */
4916 if (HAS_PCH_LPT(dev)) {
4917 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4918 pipe);
4919 } else if (!is_cpu_edp) {
4920 struct intel_pch_pll *pll;
4921
4922 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4923 if (pll == NULL) {
4924 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4925 pipe);
4926 return -EINVAL;
4927 }
4928 } else
4929 intel_put_pch_pll(intel_crtc);
4930
4931 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4932 * This is an exception to the general rule that mode_set doesn't turn
4933 * things on.
4934 */
4935 if (is_lvds) {
4936 temp = I915_READ(PCH_LVDS);
4937 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4938 if (HAS_PCH_CPT(dev)) {
4939 temp &= ~PORT_TRANS_SEL_MASK;
4940 temp |= PORT_TRANS_SEL_CPT(pipe);
4941 } else {
4942 if (pipe == 1)
4943 temp |= LVDS_PIPEB_SELECT;
4944 else
4945 temp &= ~LVDS_PIPEB_SELECT;
4946 }
4947
4948 /* set the corresponsding LVDS_BORDER bit */
4949 temp |= dev_priv->lvds_border_bits;
4950 /* Set the B0-B3 data pairs corresponding to whether we're going to
4951 * set the DPLLs for dual-channel mode or not.
4952 */
4953 if (clock.p2 == 7)
4954 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4955 else
4956 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4957
4958 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4959 * appropriately here, but we need to look more thoroughly into how
4960 * panels behave in the two modes.
4961 */
4962 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4963 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4964 temp |= LVDS_HSYNC_POLARITY;
4965 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4966 temp |= LVDS_VSYNC_POLARITY;
4967 I915_WRITE(PCH_LVDS, temp);
4968 }
4969
4970 if (is_dp && !is_cpu_edp) {
4971 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4972 } else {
4973 /* For non-DP output, clear any trans DP clock recovery setting.*/
4974 I915_WRITE(TRANSDATA_M1(pipe), 0);
4975 I915_WRITE(TRANSDATA_N1(pipe), 0);
4976 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4977 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4978 }
4979
4980 if (intel_crtc->pch_pll) {
4981 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4982
4983 /* Wait for the clocks to stabilize. */
4984 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4985 udelay(150);
4986
4987 /* The pixel multiplier can only be updated once the
4988 * DPLL is enabled and the clocks are stable.
4989 *
4990 * So write it again.
4991 */
4992 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4993 }
4994
4995 intel_crtc->lowfreq_avail = false;
4996 if (intel_crtc->pch_pll) {
4997 if (is_lvds && has_reduced_clock && i915_powersave) {
4998 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4999 intel_crtc->lowfreq_avail = true;
5000 } else {
5001 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5002 }
5003 }
5004
5005 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5006 /* the chip adds 2 halflines automatically */
5007 adjusted_mode->crtc_vtotal -= 1;
5008 adjusted_mode->crtc_vblank_end -= 1;
5009 I915_WRITE(VSYNCSHIFT(pipe),
5010 adjusted_mode->crtc_hsync_start
5011 - adjusted_mode->crtc_htotal/2);
5012 } else {
5013 I915_WRITE(VSYNCSHIFT(pipe), 0);
5014 }
5015
5016 I915_WRITE(HTOTAL(pipe),
5017 (adjusted_mode->crtc_hdisplay - 1) |
5018 ((adjusted_mode->crtc_htotal - 1) << 16));
5019 I915_WRITE(HBLANK(pipe),
5020 (adjusted_mode->crtc_hblank_start - 1) |
5021 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5022 I915_WRITE(HSYNC(pipe),
5023 (adjusted_mode->crtc_hsync_start - 1) |
5024 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5025
5026 I915_WRITE(VTOTAL(pipe),
5027 (adjusted_mode->crtc_vdisplay - 1) |
5028 ((adjusted_mode->crtc_vtotal - 1) << 16));
5029 I915_WRITE(VBLANK(pipe),
5030 (adjusted_mode->crtc_vblank_start - 1) |
5031 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5032 I915_WRITE(VSYNC(pipe),
5033 (adjusted_mode->crtc_vsync_start - 1) |
5034 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5035
5036 /* pipesrc controls the size that is scaled from, which should
5037 * always be the user's requested size.
5038 */
5039 I915_WRITE(PIPESRC(pipe),
5040 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5041
5042 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5043 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5044 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5045 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5046
5047 if (is_cpu_edp)
5048 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5049
5050 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5051
5052 intel_wait_for_vblank(dev, pipe);
5053
5054 /* Set up the display plane register */
5055 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5056 POSTING_READ(DSPCNTR(plane));
5057
5058 ret = intel_pipe_set_base(crtc, x, y, fb);
5059
5060 intel_update_watermarks(dev);
5061
5062 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5063
5064 return ret;
5065 }
5066
5067 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5068 struct drm_display_mode *mode,
5069 struct drm_display_mode *adjusted_mode,
5070 int x, int y,
5071 struct drm_framebuffer *fb)
5072 {
5073 struct drm_device *dev = crtc->dev;
5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5076 int pipe = intel_crtc->pipe;
5077 int ret;
5078
5079 drm_vblank_pre_modeset(dev, pipe);
5080
5081 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5082 x, y, fb);
5083 drm_vblank_post_modeset(dev, pipe);
5084
5085 return ret;
5086 }
5087
5088 static bool intel_eld_uptodate(struct drm_connector *connector,
5089 int reg_eldv, uint32_t bits_eldv,
5090 int reg_elda, uint32_t bits_elda,
5091 int reg_edid)
5092 {
5093 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5094 uint8_t *eld = connector->eld;
5095 uint32_t i;
5096
5097 i = I915_READ(reg_eldv);
5098 i &= bits_eldv;
5099
5100 if (!eld[0])
5101 return !i;
5102
5103 if (!i)
5104 return false;
5105
5106 i = I915_READ(reg_elda);
5107 i &= ~bits_elda;
5108 I915_WRITE(reg_elda, i);
5109
5110 for (i = 0; i < eld[2]; i++)
5111 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5112 return false;
5113
5114 return true;
5115 }
5116
5117 static void g4x_write_eld(struct drm_connector *connector,
5118 struct drm_crtc *crtc)
5119 {
5120 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5121 uint8_t *eld = connector->eld;
5122 uint32_t eldv;
5123 uint32_t len;
5124 uint32_t i;
5125
5126 i = I915_READ(G4X_AUD_VID_DID);
5127
5128 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5129 eldv = G4X_ELDV_DEVCL_DEVBLC;
5130 else
5131 eldv = G4X_ELDV_DEVCTG;
5132
5133 if (intel_eld_uptodate(connector,
5134 G4X_AUD_CNTL_ST, eldv,
5135 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5136 G4X_HDMIW_HDMIEDID))
5137 return;
5138
5139 i = I915_READ(G4X_AUD_CNTL_ST);
5140 i &= ~(eldv | G4X_ELD_ADDR);
5141 len = (i >> 9) & 0x1f; /* ELD buffer size */
5142 I915_WRITE(G4X_AUD_CNTL_ST, i);
5143
5144 if (!eld[0])
5145 return;
5146
5147 len = min_t(uint8_t, eld[2], len);
5148 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5149 for (i = 0; i < len; i++)
5150 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5151
5152 i = I915_READ(G4X_AUD_CNTL_ST);
5153 i |= eldv;
5154 I915_WRITE(G4X_AUD_CNTL_ST, i);
5155 }
5156
5157 static void haswell_write_eld(struct drm_connector *connector,
5158 struct drm_crtc *crtc)
5159 {
5160 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5161 uint8_t *eld = connector->eld;
5162 struct drm_device *dev = crtc->dev;
5163 uint32_t eldv;
5164 uint32_t i;
5165 int len;
5166 int pipe = to_intel_crtc(crtc)->pipe;
5167 int tmp;
5168
5169 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5170 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5171 int aud_config = HSW_AUD_CFG(pipe);
5172 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5173
5174
5175 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5176
5177 /* Audio output enable */
5178 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5179 tmp = I915_READ(aud_cntrl_st2);
5180 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5181 I915_WRITE(aud_cntrl_st2, tmp);
5182
5183 /* Wait for 1 vertical blank */
5184 intel_wait_for_vblank(dev, pipe);
5185
5186 /* Set ELD valid state */
5187 tmp = I915_READ(aud_cntrl_st2);
5188 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5189 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5190 I915_WRITE(aud_cntrl_st2, tmp);
5191 tmp = I915_READ(aud_cntrl_st2);
5192 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5193
5194 /* Enable HDMI mode */
5195 tmp = I915_READ(aud_config);
5196 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5197 /* clear N_programing_enable and N_value_index */
5198 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5199 I915_WRITE(aud_config, tmp);
5200
5201 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5202
5203 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5204
5205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5206 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5207 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5208 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5209 } else
5210 I915_WRITE(aud_config, 0);
5211
5212 if (intel_eld_uptodate(connector,
5213 aud_cntrl_st2, eldv,
5214 aud_cntl_st, IBX_ELD_ADDRESS,
5215 hdmiw_hdmiedid))
5216 return;
5217
5218 i = I915_READ(aud_cntrl_st2);
5219 i &= ~eldv;
5220 I915_WRITE(aud_cntrl_st2, i);
5221
5222 if (!eld[0])
5223 return;
5224
5225 i = I915_READ(aud_cntl_st);
5226 i &= ~IBX_ELD_ADDRESS;
5227 I915_WRITE(aud_cntl_st, i);
5228 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5229 DRM_DEBUG_DRIVER("port num:%d\n", i);
5230
5231 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5232 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5233 for (i = 0; i < len; i++)
5234 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5235
5236 i = I915_READ(aud_cntrl_st2);
5237 i |= eldv;
5238 I915_WRITE(aud_cntrl_st2, i);
5239
5240 }
5241
5242 static void ironlake_write_eld(struct drm_connector *connector,
5243 struct drm_crtc *crtc)
5244 {
5245 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5246 uint8_t *eld = connector->eld;
5247 uint32_t eldv;
5248 uint32_t i;
5249 int len;
5250 int hdmiw_hdmiedid;
5251 int aud_config;
5252 int aud_cntl_st;
5253 int aud_cntrl_st2;
5254 int pipe = to_intel_crtc(crtc)->pipe;
5255
5256 if (HAS_PCH_IBX(connector->dev)) {
5257 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5258 aud_config = IBX_AUD_CFG(pipe);
5259 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5260 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5261 } else {
5262 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5263 aud_config = CPT_AUD_CFG(pipe);
5264 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5265 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5266 }
5267
5268 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5269
5270 i = I915_READ(aud_cntl_st);
5271 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5272 if (!i) {
5273 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5274 /* operate blindly on all ports */
5275 eldv = IBX_ELD_VALIDB;
5276 eldv |= IBX_ELD_VALIDB << 4;
5277 eldv |= IBX_ELD_VALIDB << 8;
5278 } else {
5279 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5280 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5281 }
5282
5283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5284 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5285 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5286 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5287 } else
5288 I915_WRITE(aud_config, 0);
5289
5290 if (intel_eld_uptodate(connector,
5291 aud_cntrl_st2, eldv,
5292 aud_cntl_st, IBX_ELD_ADDRESS,
5293 hdmiw_hdmiedid))
5294 return;
5295
5296 i = I915_READ(aud_cntrl_st2);
5297 i &= ~eldv;
5298 I915_WRITE(aud_cntrl_st2, i);
5299
5300 if (!eld[0])
5301 return;
5302
5303 i = I915_READ(aud_cntl_st);
5304 i &= ~IBX_ELD_ADDRESS;
5305 I915_WRITE(aud_cntl_st, i);
5306
5307 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5308 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5309 for (i = 0; i < len; i++)
5310 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5311
5312 i = I915_READ(aud_cntrl_st2);
5313 i |= eldv;
5314 I915_WRITE(aud_cntrl_st2, i);
5315 }
5316
5317 void intel_write_eld(struct drm_encoder *encoder,
5318 struct drm_display_mode *mode)
5319 {
5320 struct drm_crtc *crtc = encoder->crtc;
5321 struct drm_connector *connector;
5322 struct drm_device *dev = encoder->dev;
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324
5325 connector = drm_select_eld(encoder, mode);
5326 if (!connector)
5327 return;
5328
5329 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5330 connector->base.id,
5331 drm_get_connector_name(connector),
5332 connector->encoder->base.id,
5333 drm_get_encoder_name(connector->encoder));
5334
5335 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5336
5337 if (dev_priv->display.write_eld)
5338 dev_priv->display.write_eld(connector, crtc);
5339 }
5340
5341 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5342 void intel_crtc_load_lut(struct drm_crtc *crtc)
5343 {
5344 struct drm_device *dev = crtc->dev;
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5347 int palreg = PALETTE(intel_crtc->pipe);
5348 int i;
5349
5350 /* The clocks have to be on to load the palette. */
5351 if (!crtc->enabled || !intel_crtc->active)
5352 return;
5353
5354 /* use legacy palette for Ironlake */
5355 if (HAS_PCH_SPLIT(dev))
5356 palreg = LGC_PALETTE(intel_crtc->pipe);
5357
5358 for (i = 0; i < 256; i++) {
5359 I915_WRITE(palreg + 4 * i,
5360 (intel_crtc->lut_r[i] << 16) |
5361 (intel_crtc->lut_g[i] << 8) |
5362 intel_crtc->lut_b[i]);
5363 }
5364 }
5365
5366 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5367 {
5368 struct drm_device *dev = crtc->dev;
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5371 bool visible = base != 0;
5372 u32 cntl;
5373
5374 if (intel_crtc->cursor_visible == visible)
5375 return;
5376
5377 cntl = I915_READ(_CURACNTR);
5378 if (visible) {
5379 /* On these chipsets we can only modify the base whilst
5380 * the cursor is disabled.
5381 */
5382 I915_WRITE(_CURABASE, base);
5383
5384 cntl &= ~(CURSOR_FORMAT_MASK);
5385 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5386 cntl |= CURSOR_ENABLE |
5387 CURSOR_GAMMA_ENABLE |
5388 CURSOR_FORMAT_ARGB;
5389 } else
5390 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5391 I915_WRITE(_CURACNTR, cntl);
5392
5393 intel_crtc->cursor_visible = visible;
5394 }
5395
5396 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5397 {
5398 struct drm_device *dev = crtc->dev;
5399 struct drm_i915_private *dev_priv = dev->dev_private;
5400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401 int pipe = intel_crtc->pipe;
5402 bool visible = base != 0;
5403
5404 if (intel_crtc->cursor_visible != visible) {
5405 uint32_t cntl = I915_READ(CURCNTR(pipe));
5406 if (base) {
5407 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5408 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5409 cntl |= pipe << 28; /* Connect to correct pipe */
5410 } else {
5411 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5412 cntl |= CURSOR_MODE_DISABLE;
5413 }
5414 I915_WRITE(CURCNTR(pipe), cntl);
5415
5416 intel_crtc->cursor_visible = visible;
5417 }
5418 /* and commit changes on next vblank */
5419 I915_WRITE(CURBASE(pipe), base);
5420 }
5421
5422 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5423 {
5424 struct drm_device *dev = crtc->dev;
5425 struct drm_i915_private *dev_priv = dev->dev_private;
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427 int pipe = intel_crtc->pipe;
5428 bool visible = base != 0;
5429
5430 if (intel_crtc->cursor_visible != visible) {
5431 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5432 if (base) {
5433 cntl &= ~CURSOR_MODE;
5434 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5435 } else {
5436 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5437 cntl |= CURSOR_MODE_DISABLE;
5438 }
5439 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5440
5441 intel_crtc->cursor_visible = visible;
5442 }
5443 /* and commit changes on next vblank */
5444 I915_WRITE(CURBASE_IVB(pipe), base);
5445 }
5446
5447 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5448 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5449 bool on)
5450 {
5451 struct drm_device *dev = crtc->dev;
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5454 int pipe = intel_crtc->pipe;
5455 int x = intel_crtc->cursor_x;
5456 int y = intel_crtc->cursor_y;
5457 u32 base, pos;
5458 bool visible;
5459
5460 pos = 0;
5461
5462 if (on && crtc->enabled && crtc->fb) {
5463 base = intel_crtc->cursor_addr;
5464 if (x > (int) crtc->fb->width)
5465 base = 0;
5466
5467 if (y > (int) crtc->fb->height)
5468 base = 0;
5469 } else
5470 base = 0;
5471
5472 if (x < 0) {
5473 if (x + intel_crtc->cursor_width < 0)
5474 base = 0;
5475
5476 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5477 x = -x;
5478 }
5479 pos |= x << CURSOR_X_SHIFT;
5480
5481 if (y < 0) {
5482 if (y + intel_crtc->cursor_height < 0)
5483 base = 0;
5484
5485 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5486 y = -y;
5487 }
5488 pos |= y << CURSOR_Y_SHIFT;
5489
5490 visible = base != 0;
5491 if (!visible && !intel_crtc->cursor_visible)
5492 return;
5493
5494 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5495 I915_WRITE(CURPOS_IVB(pipe), pos);
5496 ivb_update_cursor(crtc, base);
5497 } else {
5498 I915_WRITE(CURPOS(pipe), pos);
5499 if (IS_845G(dev) || IS_I865G(dev))
5500 i845_update_cursor(crtc, base);
5501 else
5502 i9xx_update_cursor(crtc, base);
5503 }
5504 }
5505
5506 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5507 struct drm_file *file,
5508 uint32_t handle,
5509 uint32_t width, uint32_t height)
5510 {
5511 struct drm_device *dev = crtc->dev;
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5514 struct drm_i915_gem_object *obj;
5515 uint32_t addr;
5516 int ret;
5517
5518 /* if we want to turn off the cursor ignore width and height */
5519 if (!handle) {
5520 DRM_DEBUG_KMS("cursor off\n");
5521 addr = 0;
5522 obj = NULL;
5523 mutex_lock(&dev->struct_mutex);
5524 goto finish;
5525 }
5526
5527 /* Currently we only support 64x64 cursors */
5528 if (width != 64 || height != 64) {
5529 DRM_ERROR("we currently only support 64x64 cursors\n");
5530 return -EINVAL;
5531 }
5532
5533 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5534 if (&obj->base == NULL)
5535 return -ENOENT;
5536
5537 if (obj->base.size < width * height * 4) {
5538 DRM_ERROR("buffer is to small\n");
5539 ret = -ENOMEM;
5540 goto fail;
5541 }
5542
5543 /* we only need to pin inside GTT if cursor is non-phy */
5544 mutex_lock(&dev->struct_mutex);
5545 if (!dev_priv->info->cursor_needs_physical) {
5546 if (obj->tiling_mode) {
5547 DRM_ERROR("cursor cannot be tiled\n");
5548 ret = -EINVAL;
5549 goto fail_locked;
5550 }
5551
5552 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5553 if (ret) {
5554 DRM_ERROR("failed to move cursor bo into the GTT\n");
5555 goto fail_locked;
5556 }
5557
5558 ret = i915_gem_object_put_fence(obj);
5559 if (ret) {
5560 DRM_ERROR("failed to release fence for cursor");
5561 goto fail_unpin;
5562 }
5563
5564 addr = obj->gtt_offset;
5565 } else {
5566 int align = IS_I830(dev) ? 16 * 1024 : 256;
5567 ret = i915_gem_attach_phys_object(dev, obj,
5568 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5569 align);
5570 if (ret) {
5571 DRM_ERROR("failed to attach phys object\n");
5572 goto fail_locked;
5573 }
5574 addr = obj->phys_obj->handle->busaddr;
5575 }
5576
5577 if (IS_GEN2(dev))
5578 I915_WRITE(CURSIZE, (height << 12) | width);
5579
5580 finish:
5581 if (intel_crtc->cursor_bo) {
5582 if (dev_priv->info->cursor_needs_physical) {
5583 if (intel_crtc->cursor_bo != obj)
5584 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5585 } else
5586 i915_gem_object_unpin(intel_crtc->cursor_bo);
5587 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5588 }
5589
5590 mutex_unlock(&dev->struct_mutex);
5591
5592 intel_crtc->cursor_addr = addr;
5593 intel_crtc->cursor_bo = obj;
5594 intel_crtc->cursor_width = width;
5595 intel_crtc->cursor_height = height;
5596
5597 intel_crtc_update_cursor(crtc, true);
5598
5599 return 0;
5600 fail_unpin:
5601 i915_gem_object_unpin(obj);
5602 fail_locked:
5603 mutex_unlock(&dev->struct_mutex);
5604 fail:
5605 drm_gem_object_unreference_unlocked(&obj->base);
5606 return ret;
5607 }
5608
5609 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5610 {
5611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5612
5613 intel_crtc->cursor_x = x;
5614 intel_crtc->cursor_y = y;
5615
5616 intel_crtc_update_cursor(crtc, true);
5617
5618 return 0;
5619 }
5620
5621 /** Sets the color ramps on behalf of RandR */
5622 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5623 u16 blue, int regno)
5624 {
5625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5626
5627 intel_crtc->lut_r[regno] = red >> 8;
5628 intel_crtc->lut_g[regno] = green >> 8;
5629 intel_crtc->lut_b[regno] = blue >> 8;
5630 }
5631
5632 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5633 u16 *blue, int regno)
5634 {
5635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5636
5637 *red = intel_crtc->lut_r[regno] << 8;
5638 *green = intel_crtc->lut_g[regno] << 8;
5639 *blue = intel_crtc->lut_b[regno] << 8;
5640 }
5641
5642 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5643 u16 *blue, uint32_t start, uint32_t size)
5644 {
5645 int end = (start + size > 256) ? 256 : start + size, i;
5646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5647
5648 for (i = start; i < end; i++) {
5649 intel_crtc->lut_r[i] = red[i] >> 8;
5650 intel_crtc->lut_g[i] = green[i] >> 8;
5651 intel_crtc->lut_b[i] = blue[i] >> 8;
5652 }
5653
5654 intel_crtc_load_lut(crtc);
5655 }
5656
5657 /**
5658 * Get a pipe with a simple mode set on it for doing load-based monitor
5659 * detection.
5660 *
5661 * It will be up to the load-detect code to adjust the pipe as appropriate for
5662 * its requirements. The pipe will be connected to no other encoders.
5663 *
5664 * Currently this code will only succeed if there is a pipe with no encoders
5665 * configured for it. In the future, it could choose to temporarily disable
5666 * some outputs to free up a pipe for its use.
5667 *
5668 * \return crtc, or NULL if no pipes are available.
5669 */
5670
5671 /* VESA 640x480x72Hz mode to set on the pipe */
5672 static struct drm_display_mode load_detect_mode = {
5673 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5674 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5675 };
5676
5677 static struct drm_framebuffer *
5678 intel_framebuffer_create(struct drm_device *dev,
5679 struct drm_mode_fb_cmd2 *mode_cmd,
5680 struct drm_i915_gem_object *obj)
5681 {
5682 struct intel_framebuffer *intel_fb;
5683 int ret;
5684
5685 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5686 if (!intel_fb) {
5687 drm_gem_object_unreference_unlocked(&obj->base);
5688 return ERR_PTR(-ENOMEM);
5689 }
5690
5691 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5692 if (ret) {
5693 drm_gem_object_unreference_unlocked(&obj->base);
5694 kfree(intel_fb);
5695 return ERR_PTR(ret);
5696 }
5697
5698 return &intel_fb->base;
5699 }
5700
5701 static u32
5702 intel_framebuffer_pitch_for_width(int width, int bpp)
5703 {
5704 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5705 return ALIGN(pitch, 64);
5706 }
5707
5708 static u32
5709 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5710 {
5711 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5712 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5713 }
5714
5715 static struct drm_framebuffer *
5716 intel_framebuffer_create_for_mode(struct drm_device *dev,
5717 struct drm_display_mode *mode,
5718 int depth, int bpp)
5719 {
5720 struct drm_i915_gem_object *obj;
5721 struct drm_mode_fb_cmd2 mode_cmd;
5722
5723 obj = i915_gem_alloc_object(dev,
5724 intel_framebuffer_size_for_mode(mode, bpp));
5725 if (obj == NULL)
5726 return ERR_PTR(-ENOMEM);
5727
5728 mode_cmd.width = mode->hdisplay;
5729 mode_cmd.height = mode->vdisplay;
5730 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5731 bpp);
5732 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5733
5734 return intel_framebuffer_create(dev, &mode_cmd, obj);
5735 }
5736
5737 static struct drm_framebuffer *
5738 mode_fits_in_fbdev(struct drm_device *dev,
5739 struct drm_display_mode *mode)
5740 {
5741 struct drm_i915_private *dev_priv = dev->dev_private;
5742 struct drm_i915_gem_object *obj;
5743 struct drm_framebuffer *fb;
5744
5745 if (dev_priv->fbdev == NULL)
5746 return NULL;
5747
5748 obj = dev_priv->fbdev->ifb.obj;
5749 if (obj == NULL)
5750 return NULL;
5751
5752 fb = &dev_priv->fbdev->ifb.base;
5753 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5754 fb->bits_per_pixel))
5755 return NULL;
5756
5757 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5758 return NULL;
5759
5760 return fb;
5761 }
5762
5763 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5764 struct drm_display_mode *mode,
5765 struct intel_load_detect_pipe *old)
5766 {
5767 struct intel_crtc *intel_crtc;
5768 struct intel_encoder *intel_encoder =
5769 intel_attached_encoder(connector);
5770 struct drm_crtc *possible_crtc;
5771 struct drm_encoder *encoder = &intel_encoder->base;
5772 struct drm_crtc *crtc = NULL;
5773 struct drm_device *dev = encoder->dev;
5774 struct drm_framebuffer *fb;
5775 int i = -1;
5776
5777 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5778 connector->base.id, drm_get_connector_name(connector),
5779 encoder->base.id, drm_get_encoder_name(encoder));
5780
5781 /*
5782 * Algorithm gets a little messy:
5783 *
5784 * - if the connector already has an assigned crtc, use it (but make
5785 * sure it's on first)
5786 *
5787 * - try to find the first unused crtc that can drive this connector,
5788 * and use that if we find one
5789 */
5790
5791 /* See if we already have a CRTC for this connector */
5792 if (encoder->crtc) {
5793 crtc = encoder->crtc;
5794
5795 old->dpms_mode = connector->dpms;
5796 old->load_detect_temp = false;
5797
5798 /* Make sure the crtc and connector are running */
5799 if (connector->dpms != DRM_MODE_DPMS_ON)
5800 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5801
5802 return true;
5803 }
5804
5805 /* Find an unused one (if possible) */
5806 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5807 i++;
5808 if (!(encoder->possible_crtcs & (1 << i)))
5809 continue;
5810 if (!possible_crtc->enabled) {
5811 crtc = possible_crtc;
5812 break;
5813 }
5814 }
5815
5816 /*
5817 * If we didn't find an unused CRTC, don't use any.
5818 */
5819 if (!crtc) {
5820 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5821 return false;
5822 }
5823
5824 intel_encoder->new_crtc = to_intel_crtc(crtc);
5825 to_intel_connector(connector)->new_encoder = intel_encoder;
5826
5827 intel_crtc = to_intel_crtc(crtc);
5828 old->dpms_mode = connector->dpms;
5829 old->load_detect_temp = true;
5830 old->release_fb = NULL;
5831
5832 if (!mode)
5833 mode = &load_detect_mode;
5834
5835 /* We need a framebuffer large enough to accommodate all accesses
5836 * that the plane may generate whilst we perform load detection.
5837 * We can not rely on the fbcon either being present (we get called
5838 * during its initialisation to detect all boot displays, or it may
5839 * not even exist) or that it is large enough to satisfy the
5840 * requested mode.
5841 */
5842 fb = mode_fits_in_fbdev(dev, mode);
5843 if (fb == NULL) {
5844 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5845 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5846 old->release_fb = fb;
5847 } else
5848 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5849 if (IS_ERR(fb)) {
5850 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5851 goto fail;
5852 }
5853
5854 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5855 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5856 if (old->release_fb)
5857 old->release_fb->funcs->destroy(old->release_fb);
5858 goto fail;
5859 }
5860
5861 /* let the connector get through one full cycle before testing */
5862 intel_wait_for_vblank(dev, intel_crtc->pipe);
5863
5864 return true;
5865 fail:
5866 connector->encoder = NULL;
5867 encoder->crtc = NULL;
5868 return false;
5869 }
5870
5871 void intel_release_load_detect_pipe(struct drm_connector *connector,
5872 struct intel_load_detect_pipe *old)
5873 {
5874 struct intel_encoder *intel_encoder =
5875 intel_attached_encoder(connector);
5876 struct drm_encoder *encoder = &intel_encoder->base;
5877
5878 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5879 connector->base.id, drm_get_connector_name(connector),
5880 encoder->base.id, drm_get_encoder_name(encoder));
5881
5882 if (old->load_detect_temp) {
5883 struct drm_crtc *crtc = encoder->crtc;
5884
5885 to_intel_connector(connector)->new_encoder = NULL;
5886 intel_encoder->new_crtc = NULL;
5887 intel_set_mode(crtc, NULL, 0, 0, NULL);
5888
5889 if (old->release_fb)
5890 old->release_fb->funcs->destroy(old->release_fb);
5891
5892 return;
5893 }
5894
5895 /* Switch crtc and encoder back off if necessary */
5896 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5897 connector->funcs->dpms(connector, old->dpms_mode);
5898 }
5899
5900 /* Returns the clock of the currently programmed mode of the given pipe. */
5901 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5902 {
5903 struct drm_i915_private *dev_priv = dev->dev_private;
5904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5905 int pipe = intel_crtc->pipe;
5906 u32 dpll = I915_READ(DPLL(pipe));
5907 u32 fp;
5908 intel_clock_t clock;
5909
5910 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5911 fp = I915_READ(FP0(pipe));
5912 else
5913 fp = I915_READ(FP1(pipe));
5914
5915 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5916 if (IS_PINEVIEW(dev)) {
5917 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5918 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5919 } else {
5920 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5921 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5922 }
5923
5924 if (!IS_GEN2(dev)) {
5925 if (IS_PINEVIEW(dev))
5926 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5927 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5928 else
5929 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5930 DPLL_FPA01_P1_POST_DIV_SHIFT);
5931
5932 switch (dpll & DPLL_MODE_MASK) {
5933 case DPLLB_MODE_DAC_SERIAL:
5934 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5935 5 : 10;
5936 break;
5937 case DPLLB_MODE_LVDS:
5938 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5939 7 : 14;
5940 break;
5941 default:
5942 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5943 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5944 return 0;
5945 }
5946
5947 /* XXX: Handle the 100Mhz refclk */
5948 intel_clock(dev, 96000, &clock);
5949 } else {
5950 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5951
5952 if (is_lvds) {
5953 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5954 DPLL_FPA01_P1_POST_DIV_SHIFT);
5955 clock.p2 = 14;
5956
5957 if ((dpll & PLL_REF_INPUT_MASK) ==
5958 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5959 /* XXX: might not be 66MHz */
5960 intel_clock(dev, 66000, &clock);
5961 } else
5962 intel_clock(dev, 48000, &clock);
5963 } else {
5964 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5965 clock.p1 = 2;
5966 else {
5967 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5968 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5969 }
5970 if (dpll & PLL_P2_DIVIDE_BY_4)
5971 clock.p2 = 4;
5972 else
5973 clock.p2 = 2;
5974
5975 intel_clock(dev, 48000, &clock);
5976 }
5977 }
5978
5979 /* XXX: It would be nice to validate the clocks, but we can't reuse
5980 * i830PllIsValid() because it relies on the xf86_config connector
5981 * configuration being accurate, which it isn't necessarily.
5982 */
5983
5984 return clock.dot;
5985 }
5986
5987 /** Returns the currently programmed mode of the given pipe. */
5988 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5989 struct drm_crtc *crtc)
5990 {
5991 struct drm_i915_private *dev_priv = dev->dev_private;
5992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5993 int pipe = intel_crtc->pipe;
5994 struct drm_display_mode *mode;
5995 int htot = I915_READ(HTOTAL(pipe));
5996 int hsync = I915_READ(HSYNC(pipe));
5997 int vtot = I915_READ(VTOTAL(pipe));
5998 int vsync = I915_READ(VSYNC(pipe));
5999
6000 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6001 if (!mode)
6002 return NULL;
6003
6004 mode->clock = intel_crtc_clock_get(dev, crtc);
6005 mode->hdisplay = (htot & 0xffff) + 1;
6006 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6007 mode->hsync_start = (hsync & 0xffff) + 1;
6008 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6009 mode->vdisplay = (vtot & 0xffff) + 1;
6010 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6011 mode->vsync_start = (vsync & 0xffff) + 1;
6012 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6013
6014 drm_mode_set_name(mode);
6015
6016 return mode;
6017 }
6018
6019 static void intel_increase_pllclock(struct drm_crtc *crtc)
6020 {
6021 struct drm_device *dev = crtc->dev;
6022 drm_i915_private_t *dev_priv = dev->dev_private;
6023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6024 int pipe = intel_crtc->pipe;
6025 int dpll_reg = DPLL(pipe);
6026 int dpll;
6027
6028 if (HAS_PCH_SPLIT(dev))
6029 return;
6030
6031 if (!dev_priv->lvds_downclock_avail)
6032 return;
6033
6034 dpll = I915_READ(dpll_reg);
6035 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6036 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6037
6038 assert_panel_unlocked(dev_priv, pipe);
6039
6040 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6041 I915_WRITE(dpll_reg, dpll);
6042 intel_wait_for_vblank(dev, pipe);
6043
6044 dpll = I915_READ(dpll_reg);
6045 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6046 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6047 }
6048 }
6049
6050 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6051 {
6052 struct drm_device *dev = crtc->dev;
6053 drm_i915_private_t *dev_priv = dev->dev_private;
6054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055
6056 if (HAS_PCH_SPLIT(dev))
6057 return;
6058
6059 if (!dev_priv->lvds_downclock_avail)
6060 return;
6061
6062 /*
6063 * Since this is called by a timer, we should never get here in
6064 * the manual case.
6065 */
6066 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6067 int pipe = intel_crtc->pipe;
6068 int dpll_reg = DPLL(pipe);
6069 int dpll;
6070
6071 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6072
6073 assert_panel_unlocked(dev_priv, pipe);
6074
6075 dpll = I915_READ(dpll_reg);
6076 dpll |= DISPLAY_RATE_SELECT_FPA1;
6077 I915_WRITE(dpll_reg, dpll);
6078 intel_wait_for_vblank(dev, pipe);
6079 dpll = I915_READ(dpll_reg);
6080 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6081 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6082 }
6083
6084 }
6085
6086 void intel_mark_busy(struct drm_device *dev)
6087 {
6088 i915_update_gfx_val(dev->dev_private);
6089 }
6090
6091 void intel_mark_idle(struct drm_device *dev)
6092 {
6093 }
6094
6095 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6096 {
6097 struct drm_device *dev = obj->base.dev;
6098 struct drm_crtc *crtc;
6099
6100 if (!i915_powersave)
6101 return;
6102
6103 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6104 if (!crtc->fb)
6105 continue;
6106
6107 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6108 intel_increase_pllclock(crtc);
6109 }
6110 }
6111
6112 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6113 {
6114 struct drm_device *dev = obj->base.dev;
6115 struct drm_crtc *crtc;
6116
6117 if (!i915_powersave)
6118 return;
6119
6120 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6121 if (!crtc->fb)
6122 continue;
6123
6124 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6125 intel_decrease_pllclock(crtc);
6126 }
6127 }
6128
6129 static void intel_crtc_destroy(struct drm_crtc *crtc)
6130 {
6131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6132 struct drm_device *dev = crtc->dev;
6133 struct intel_unpin_work *work;
6134 unsigned long flags;
6135
6136 spin_lock_irqsave(&dev->event_lock, flags);
6137 work = intel_crtc->unpin_work;
6138 intel_crtc->unpin_work = NULL;
6139 spin_unlock_irqrestore(&dev->event_lock, flags);
6140
6141 if (work) {
6142 cancel_work_sync(&work->work);
6143 kfree(work);
6144 }
6145
6146 drm_crtc_cleanup(crtc);
6147
6148 kfree(intel_crtc);
6149 }
6150
6151 static void intel_unpin_work_fn(struct work_struct *__work)
6152 {
6153 struct intel_unpin_work *work =
6154 container_of(__work, struct intel_unpin_work, work);
6155
6156 mutex_lock(&work->dev->struct_mutex);
6157 intel_unpin_fb_obj(work->old_fb_obj);
6158 drm_gem_object_unreference(&work->pending_flip_obj->base);
6159 drm_gem_object_unreference(&work->old_fb_obj->base);
6160
6161 intel_update_fbc(work->dev);
6162 mutex_unlock(&work->dev->struct_mutex);
6163 kfree(work);
6164 }
6165
6166 static void do_intel_finish_page_flip(struct drm_device *dev,
6167 struct drm_crtc *crtc)
6168 {
6169 drm_i915_private_t *dev_priv = dev->dev_private;
6170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6171 struct intel_unpin_work *work;
6172 struct drm_i915_gem_object *obj;
6173 struct drm_pending_vblank_event *e;
6174 struct timeval tnow, tvbl;
6175 unsigned long flags;
6176
6177 /* Ignore early vblank irqs */
6178 if (intel_crtc == NULL)
6179 return;
6180
6181 do_gettimeofday(&tnow);
6182
6183 spin_lock_irqsave(&dev->event_lock, flags);
6184 work = intel_crtc->unpin_work;
6185 if (work == NULL || !work->pending) {
6186 spin_unlock_irqrestore(&dev->event_lock, flags);
6187 return;
6188 }
6189
6190 intel_crtc->unpin_work = NULL;
6191
6192 if (work->event) {
6193 e = work->event;
6194 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6195
6196 /* Called before vblank count and timestamps have
6197 * been updated for the vblank interval of flip
6198 * completion? Need to increment vblank count and
6199 * add one videorefresh duration to returned timestamp
6200 * to account for this. We assume this happened if we
6201 * get called over 0.9 frame durations after the last
6202 * timestamped vblank.
6203 *
6204 * This calculation can not be used with vrefresh rates
6205 * below 5Hz (10Hz to be on the safe side) without
6206 * promoting to 64 integers.
6207 */
6208 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6209 9 * crtc->framedur_ns) {
6210 e->event.sequence++;
6211 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6212 crtc->framedur_ns);
6213 }
6214
6215 e->event.tv_sec = tvbl.tv_sec;
6216 e->event.tv_usec = tvbl.tv_usec;
6217
6218 list_add_tail(&e->base.link,
6219 &e->base.file_priv->event_list);
6220 wake_up_interruptible(&e->base.file_priv->event_wait);
6221 }
6222
6223 drm_vblank_put(dev, intel_crtc->pipe);
6224
6225 spin_unlock_irqrestore(&dev->event_lock, flags);
6226
6227 obj = work->old_fb_obj;
6228
6229 atomic_clear_mask(1 << intel_crtc->plane,
6230 &obj->pending_flip.counter);
6231 if (atomic_read(&obj->pending_flip) == 0)
6232 wake_up(&dev_priv->pending_flip_queue);
6233
6234 schedule_work(&work->work);
6235
6236 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6237 }
6238
6239 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6240 {
6241 drm_i915_private_t *dev_priv = dev->dev_private;
6242 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6243
6244 do_intel_finish_page_flip(dev, crtc);
6245 }
6246
6247 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6248 {
6249 drm_i915_private_t *dev_priv = dev->dev_private;
6250 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6251
6252 do_intel_finish_page_flip(dev, crtc);
6253 }
6254
6255 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6256 {
6257 drm_i915_private_t *dev_priv = dev->dev_private;
6258 struct intel_crtc *intel_crtc =
6259 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6260 unsigned long flags;
6261
6262 spin_lock_irqsave(&dev->event_lock, flags);
6263 if (intel_crtc->unpin_work) {
6264 if ((++intel_crtc->unpin_work->pending) > 1)
6265 DRM_ERROR("Prepared flip multiple times\n");
6266 } else {
6267 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6268 }
6269 spin_unlock_irqrestore(&dev->event_lock, flags);
6270 }
6271
6272 static int intel_gen2_queue_flip(struct drm_device *dev,
6273 struct drm_crtc *crtc,
6274 struct drm_framebuffer *fb,
6275 struct drm_i915_gem_object *obj)
6276 {
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279 u32 flip_mask;
6280 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6281 int ret;
6282
6283 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6284 if (ret)
6285 goto err;
6286
6287 ret = intel_ring_begin(ring, 6);
6288 if (ret)
6289 goto err_unpin;
6290
6291 /* Can't queue multiple flips, so wait for the previous
6292 * one to finish before executing the next.
6293 */
6294 if (intel_crtc->plane)
6295 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6296 else
6297 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6298 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6299 intel_ring_emit(ring, MI_NOOP);
6300 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6301 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6302 intel_ring_emit(ring, fb->pitches[0]);
6303 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6304 intel_ring_emit(ring, 0); /* aux display base address, unused */
6305 intel_ring_advance(ring);
6306 return 0;
6307
6308 err_unpin:
6309 intel_unpin_fb_obj(obj);
6310 err:
6311 return ret;
6312 }
6313
6314 static int intel_gen3_queue_flip(struct drm_device *dev,
6315 struct drm_crtc *crtc,
6316 struct drm_framebuffer *fb,
6317 struct drm_i915_gem_object *obj)
6318 {
6319 struct drm_i915_private *dev_priv = dev->dev_private;
6320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6321 u32 flip_mask;
6322 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6323 int ret;
6324
6325 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6326 if (ret)
6327 goto err;
6328
6329 ret = intel_ring_begin(ring, 6);
6330 if (ret)
6331 goto err_unpin;
6332
6333 if (intel_crtc->plane)
6334 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6335 else
6336 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6337 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6338 intel_ring_emit(ring, MI_NOOP);
6339 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6340 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6341 intel_ring_emit(ring, fb->pitches[0]);
6342 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6343 intel_ring_emit(ring, MI_NOOP);
6344
6345 intel_ring_advance(ring);
6346 return 0;
6347
6348 err_unpin:
6349 intel_unpin_fb_obj(obj);
6350 err:
6351 return ret;
6352 }
6353
6354 static int intel_gen4_queue_flip(struct drm_device *dev,
6355 struct drm_crtc *crtc,
6356 struct drm_framebuffer *fb,
6357 struct drm_i915_gem_object *obj)
6358 {
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 uint32_t pf, pipesrc;
6362 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6363 int ret;
6364
6365 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6366 if (ret)
6367 goto err;
6368
6369 ret = intel_ring_begin(ring, 4);
6370 if (ret)
6371 goto err_unpin;
6372
6373 /* i965+ uses the linear or tiled offsets from the
6374 * Display Registers (which do not change across a page-flip)
6375 * so we need only reprogram the base address.
6376 */
6377 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6378 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6379 intel_ring_emit(ring, fb->pitches[0]);
6380 intel_ring_emit(ring,
6381 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6382 obj->tiling_mode);
6383
6384 /* XXX Enabling the panel-fitter across page-flip is so far
6385 * untested on non-native modes, so ignore it for now.
6386 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6387 */
6388 pf = 0;
6389 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6390 intel_ring_emit(ring, pf | pipesrc);
6391 intel_ring_advance(ring);
6392 return 0;
6393
6394 err_unpin:
6395 intel_unpin_fb_obj(obj);
6396 err:
6397 return ret;
6398 }
6399
6400 static int intel_gen6_queue_flip(struct drm_device *dev,
6401 struct drm_crtc *crtc,
6402 struct drm_framebuffer *fb,
6403 struct drm_i915_gem_object *obj)
6404 {
6405 struct drm_i915_private *dev_priv = dev->dev_private;
6406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6407 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6408 uint32_t pf, pipesrc;
6409 int ret;
6410
6411 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6412 if (ret)
6413 goto err;
6414
6415 ret = intel_ring_begin(ring, 4);
6416 if (ret)
6417 goto err_unpin;
6418
6419 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6421 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6422 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6423
6424 /* Contrary to the suggestions in the documentation,
6425 * "Enable Panel Fitter" does not seem to be required when page
6426 * flipping with a non-native mode, and worse causes a normal
6427 * modeset to fail.
6428 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6429 */
6430 pf = 0;
6431 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6432 intel_ring_emit(ring, pf | pipesrc);
6433 intel_ring_advance(ring);
6434 return 0;
6435
6436 err_unpin:
6437 intel_unpin_fb_obj(obj);
6438 err:
6439 return ret;
6440 }
6441
6442 /*
6443 * On gen7 we currently use the blit ring because (in early silicon at least)
6444 * the render ring doesn't give us interrpts for page flip completion, which
6445 * means clients will hang after the first flip is queued. Fortunately the
6446 * blit ring generates interrupts properly, so use it instead.
6447 */
6448 static int intel_gen7_queue_flip(struct drm_device *dev,
6449 struct drm_crtc *crtc,
6450 struct drm_framebuffer *fb,
6451 struct drm_i915_gem_object *obj)
6452 {
6453 struct drm_i915_private *dev_priv = dev->dev_private;
6454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6455 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6456 uint32_t plane_bit = 0;
6457 int ret;
6458
6459 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6460 if (ret)
6461 goto err;
6462
6463 switch(intel_crtc->plane) {
6464 case PLANE_A:
6465 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6466 break;
6467 case PLANE_B:
6468 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6469 break;
6470 case PLANE_C:
6471 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6472 break;
6473 default:
6474 WARN_ONCE(1, "unknown plane in flip command\n");
6475 ret = -ENODEV;
6476 goto err_unpin;
6477 }
6478
6479 ret = intel_ring_begin(ring, 4);
6480 if (ret)
6481 goto err_unpin;
6482
6483 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6484 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6485 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6486 intel_ring_emit(ring, (MI_NOOP));
6487 intel_ring_advance(ring);
6488 return 0;
6489
6490 err_unpin:
6491 intel_unpin_fb_obj(obj);
6492 err:
6493 return ret;
6494 }
6495
6496 static int intel_default_queue_flip(struct drm_device *dev,
6497 struct drm_crtc *crtc,
6498 struct drm_framebuffer *fb,
6499 struct drm_i915_gem_object *obj)
6500 {
6501 return -ENODEV;
6502 }
6503
6504 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6505 struct drm_framebuffer *fb,
6506 struct drm_pending_vblank_event *event)
6507 {
6508 struct drm_device *dev = crtc->dev;
6509 struct drm_i915_private *dev_priv = dev->dev_private;
6510 struct intel_framebuffer *intel_fb;
6511 struct drm_i915_gem_object *obj;
6512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6513 struct intel_unpin_work *work;
6514 unsigned long flags;
6515 int ret;
6516
6517 /* Can't change pixel format via MI display flips. */
6518 if (fb->pixel_format != crtc->fb->pixel_format)
6519 return -EINVAL;
6520
6521 /*
6522 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6523 * Note that pitch changes could also affect these register.
6524 */
6525 if (INTEL_INFO(dev)->gen > 3 &&
6526 (fb->offsets[0] != crtc->fb->offsets[0] ||
6527 fb->pitches[0] != crtc->fb->pitches[0]))
6528 return -EINVAL;
6529
6530 work = kzalloc(sizeof *work, GFP_KERNEL);
6531 if (work == NULL)
6532 return -ENOMEM;
6533
6534 work->event = event;
6535 work->dev = crtc->dev;
6536 intel_fb = to_intel_framebuffer(crtc->fb);
6537 work->old_fb_obj = intel_fb->obj;
6538 INIT_WORK(&work->work, intel_unpin_work_fn);
6539
6540 ret = drm_vblank_get(dev, intel_crtc->pipe);
6541 if (ret)
6542 goto free_work;
6543
6544 /* We borrow the event spin lock for protecting unpin_work */
6545 spin_lock_irqsave(&dev->event_lock, flags);
6546 if (intel_crtc->unpin_work) {
6547 spin_unlock_irqrestore(&dev->event_lock, flags);
6548 kfree(work);
6549 drm_vblank_put(dev, intel_crtc->pipe);
6550
6551 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6552 return -EBUSY;
6553 }
6554 intel_crtc->unpin_work = work;
6555 spin_unlock_irqrestore(&dev->event_lock, flags);
6556
6557 intel_fb = to_intel_framebuffer(fb);
6558 obj = intel_fb->obj;
6559
6560 ret = i915_mutex_lock_interruptible(dev);
6561 if (ret)
6562 goto cleanup;
6563
6564 /* Reference the objects for the scheduled work. */
6565 drm_gem_object_reference(&work->old_fb_obj->base);
6566 drm_gem_object_reference(&obj->base);
6567
6568 crtc->fb = fb;
6569
6570 work->pending_flip_obj = obj;
6571
6572 work->enable_stall_check = true;
6573
6574 /* Block clients from rendering to the new back buffer until
6575 * the flip occurs and the object is no longer visible.
6576 */
6577 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6578
6579 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6580 if (ret)
6581 goto cleanup_pending;
6582
6583 intel_disable_fbc(dev);
6584 intel_mark_fb_busy(obj);
6585 mutex_unlock(&dev->struct_mutex);
6586
6587 trace_i915_flip_request(intel_crtc->plane, obj);
6588
6589 return 0;
6590
6591 cleanup_pending:
6592 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6593 drm_gem_object_unreference(&work->old_fb_obj->base);
6594 drm_gem_object_unreference(&obj->base);
6595 mutex_unlock(&dev->struct_mutex);
6596
6597 cleanup:
6598 spin_lock_irqsave(&dev->event_lock, flags);
6599 intel_crtc->unpin_work = NULL;
6600 spin_unlock_irqrestore(&dev->event_lock, flags);
6601
6602 drm_vblank_put(dev, intel_crtc->pipe);
6603 free_work:
6604 kfree(work);
6605
6606 return ret;
6607 }
6608
6609 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6610 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6611 .load_lut = intel_crtc_load_lut,
6612 .disable = intel_crtc_noop,
6613 };
6614
6615 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6616 {
6617 struct intel_encoder *other_encoder;
6618 struct drm_crtc *crtc = &encoder->new_crtc->base;
6619
6620 if (WARN_ON(!crtc))
6621 return false;
6622
6623 list_for_each_entry(other_encoder,
6624 &crtc->dev->mode_config.encoder_list,
6625 base.head) {
6626
6627 if (&other_encoder->new_crtc->base != crtc ||
6628 encoder == other_encoder)
6629 continue;
6630 else
6631 return true;
6632 }
6633
6634 return false;
6635 }
6636
6637 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6638 struct drm_crtc *crtc)
6639 {
6640 struct drm_device *dev;
6641 struct drm_crtc *tmp;
6642 int crtc_mask = 1;
6643
6644 WARN(!crtc, "checking null crtc?\n");
6645
6646 dev = crtc->dev;
6647
6648 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6649 if (tmp == crtc)
6650 break;
6651 crtc_mask <<= 1;
6652 }
6653
6654 if (encoder->possible_crtcs & crtc_mask)
6655 return true;
6656 return false;
6657 }
6658
6659 /**
6660 * intel_modeset_update_staged_output_state
6661 *
6662 * Updates the staged output configuration state, e.g. after we've read out the
6663 * current hw state.
6664 */
6665 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6666 {
6667 struct intel_encoder *encoder;
6668 struct intel_connector *connector;
6669
6670 list_for_each_entry(connector, &dev->mode_config.connector_list,
6671 base.head) {
6672 connector->new_encoder =
6673 to_intel_encoder(connector->base.encoder);
6674 }
6675
6676 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6677 base.head) {
6678 encoder->new_crtc =
6679 to_intel_crtc(encoder->base.crtc);
6680 }
6681 }
6682
6683 /**
6684 * intel_modeset_commit_output_state
6685 *
6686 * This function copies the stage display pipe configuration to the real one.
6687 */
6688 static void intel_modeset_commit_output_state(struct drm_device *dev)
6689 {
6690 struct intel_encoder *encoder;
6691 struct intel_connector *connector;
6692
6693 list_for_each_entry(connector, &dev->mode_config.connector_list,
6694 base.head) {
6695 connector->base.encoder = &connector->new_encoder->base;
6696 }
6697
6698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6699 base.head) {
6700 encoder->base.crtc = &encoder->new_crtc->base;
6701 }
6702 }
6703
6704 static struct drm_display_mode *
6705 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6706 struct drm_display_mode *mode)
6707 {
6708 struct drm_device *dev = crtc->dev;
6709 struct drm_display_mode *adjusted_mode;
6710 struct drm_encoder_helper_funcs *encoder_funcs;
6711 struct intel_encoder *encoder;
6712
6713 adjusted_mode = drm_mode_duplicate(dev, mode);
6714 if (!adjusted_mode)
6715 return ERR_PTR(-ENOMEM);
6716
6717 /* Pass our mode to the connectors and the CRTC to give them a chance to
6718 * adjust it according to limitations or connector properties, and also
6719 * a chance to reject the mode entirely.
6720 */
6721 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6722 base.head) {
6723
6724 if (&encoder->new_crtc->base != crtc)
6725 continue;
6726 encoder_funcs = encoder->base.helper_private;
6727 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6728 adjusted_mode))) {
6729 DRM_DEBUG_KMS("Encoder fixup failed\n");
6730 goto fail;
6731 }
6732 }
6733
6734 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6735 DRM_DEBUG_KMS("CRTC fixup failed\n");
6736 goto fail;
6737 }
6738 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6739
6740 return adjusted_mode;
6741 fail:
6742 drm_mode_destroy(dev, adjusted_mode);
6743 return ERR_PTR(-EINVAL);
6744 }
6745
6746 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6747 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6748 static void
6749 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6750 unsigned *prepare_pipes, unsigned *disable_pipes)
6751 {
6752 struct intel_crtc *intel_crtc;
6753 struct drm_device *dev = crtc->dev;
6754 struct intel_encoder *encoder;
6755 struct intel_connector *connector;
6756 struct drm_crtc *tmp_crtc;
6757
6758 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6759
6760 /* Check which crtcs have changed outputs connected to them, these need
6761 * to be part of the prepare_pipes mask. We don't (yet) support global
6762 * modeset across multiple crtcs, so modeset_pipes will only have one
6763 * bit set at most. */
6764 list_for_each_entry(connector, &dev->mode_config.connector_list,
6765 base.head) {
6766 if (connector->base.encoder == &connector->new_encoder->base)
6767 continue;
6768
6769 if (connector->base.encoder) {
6770 tmp_crtc = connector->base.encoder->crtc;
6771
6772 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6773 }
6774
6775 if (connector->new_encoder)
6776 *prepare_pipes |=
6777 1 << connector->new_encoder->new_crtc->pipe;
6778 }
6779
6780 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6781 base.head) {
6782 if (encoder->base.crtc == &encoder->new_crtc->base)
6783 continue;
6784
6785 if (encoder->base.crtc) {
6786 tmp_crtc = encoder->base.crtc;
6787
6788 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6789 }
6790
6791 if (encoder->new_crtc)
6792 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6793 }
6794
6795 /* Check for any pipes that will be fully disabled ... */
6796 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6797 base.head) {
6798 bool used = false;
6799
6800 /* Don't try to disable disabled crtcs. */
6801 if (!intel_crtc->base.enabled)
6802 continue;
6803
6804 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6805 base.head) {
6806 if (encoder->new_crtc == intel_crtc)
6807 used = true;
6808 }
6809
6810 if (!used)
6811 *disable_pipes |= 1 << intel_crtc->pipe;
6812 }
6813
6814
6815 /* set_mode is also used to update properties on life display pipes. */
6816 intel_crtc = to_intel_crtc(crtc);
6817 if (crtc->enabled)
6818 *prepare_pipes |= 1 << intel_crtc->pipe;
6819
6820 /* We only support modeset on one single crtc, hence we need to do that
6821 * only for the passed in crtc iff we change anything else than just
6822 * disable crtcs.
6823 *
6824 * This is actually not true, to be fully compatible with the old crtc
6825 * helper we automatically disable _any_ output (i.e. doesn't need to be
6826 * connected to the crtc we're modesetting on) if it's disconnected.
6827 * Which is a rather nutty api (since changed the output configuration
6828 * without userspace's explicit request can lead to confusion), but
6829 * alas. Hence we currently need to modeset on all pipes we prepare. */
6830 if (*prepare_pipes)
6831 *modeset_pipes = *prepare_pipes;
6832
6833 /* ... and mask these out. */
6834 *modeset_pipes &= ~(*disable_pipes);
6835 *prepare_pipes &= ~(*disable_pipes);
6836 }
6837
6838 static bool intel_crtc_in_use(struct drm_crtc *crtc)
6839 {
6840 struct drm_encoder *encoder;
6841 struct drm_device *dev = crtc->dev;
6842
6843 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6844 if (encoder->crtc == crtc)
6845 return true;
6846
6847 return false;
6848 }
6849
6850 static void
6851 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6852 {
6853 struct intel_encoder *intel_encoder;
6854 struct intel_crtc *intel_crtc;
6855 struct drm_connector *connector;
6856
6857 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6858 base.head) {
6859 if (!intel_encoder->base.crtc)
6860 continue;
6861
6862 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6863
6864 if (prepare_pipes & (1 << intel_crtc->pipe))
6865 intel_encoder->connectors_active = false;
6866 }
6867
6868 intel_modeset_commit_output_state(dev);
6869
6870 /* Update computed state. */
6871 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6872 base.head) {
6873 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6874 }
6875
6876 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6877 if (!connector->encoder || !connector->encoder->crtc)
6878 continue;
6879
6880 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6881
6882 if (prepare_pipes & (1 << intel_crtc->pipe)) {
6883 connector->dpms = DRM_MODE_DPMS_ON;
6884
6885 intel_encoder = to_intel_encoder(connector->encoder);
6886 intel_encoder->connectors_active = true;
6887 }
6888 }
6889
6890 }
6891
6892 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6893 list_for_each_entry((intel_crtc), \
6894 &(dev)->mode_config.crtc_list, \
6895 base.head) \
6896 if (mask & (1 <<(intel_crtc)->pipe)) \
6897
6898 void
6899 intel_modeset_check_state(struct drm_device *dev)
6900 {
6901 struct intel_crtc *crtc;
6902 struct intel_encoder *encoder;
6903 struct intel_connector *connector;
6904
6905 list_for_each_entry(connector, &dev->mode_config.connector_list,
6906 base.head) {
6907 /* This also checks the encoder/connector hw state with the
6908 * ->get_hw_state callbacks. */
6909 intel_connector_check_state(connector);
6910
6911 WARN(&connector->new_encoder->base != connector->base.encoder,
6912 "connector's staged encoder doesn't match current encoder\n");
6913 }
6914
6915 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6916 base.head) {
6917 bool enabled = false;
6918 bool active = false;
6919 enum pipe pipe, tracked_pipe;
6920
6921 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6922 encoder->base.base.id,
6923 drm_get_encoder_name(&encoder->base));
6924
6925 WARN(&encoder->new_crtc->base != encoder->base.crtc,
6926 "encoder's stage crtc doesn't match current crtc\n");
6927 WARN(encoder->connectors_active && !encoder->base.crtc,
6928 "encoder's active_connectors set, but no crtc\n");
6929
6930 list_for_each_entry(connector, &dev->mode_config.connector_list,
6931 base.head) {
6932 if (connector->base.encoder != &encoder->base)
6933 continue;
6934 enabled = true;
6935 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
6936 active = true;
6937 }
6938 WARN(!!encoder->base.crtc != enabled,
6939 "encoder's enabled state mismatch "
6940 "(expected %i, found %i)\n",
6941 !!encoder->base.crtc, enabled);
6942 WARN(active && !encoder->base.crtc,
6943 "active encoder with no crtc\n");
6944
6945 WARN(encoder->connectors_active != active,
6946 "encoder's computed active state doesn't match tracked active state "
6947 "(expected %i, found %i)\n", active, encoder->connectors_active);
6948
6949 active = encoder->get_hw_state(encoder, &pipe);
6950 WARN(active != encoder->connectors_active,
6951 "encoder's hw state doesn't match sw tracking "
6952 "(expected %i, found %i)\n",
6953 encoder->connectors_active, active);
6954
6955 if (!encoder->base.crtc)
6956 continue;
6957
6958 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
6959 WARN(active && pipe != tracked_pipe,
6960 "active encoder's pipe doesn't match"
6961 "(expected %i, found %i)\n",
6962 tracked_pipe, pipe);
6963
6964 }
6965
6966 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
6967 base.head) {
6968 bool enabled = false;
6969 bool active = false;
6970
6971 DRM_DEBUG_KMS("[CRTC:%d]\n",
6972 crtc->base.base.id);
6973
6974 WARN(crtc->active && !crtc->base.enabled,
6975 "active crtc, but not enabled in sw tracking\n");
6976
6977 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6978 base.head) {
6979 if (encoder->base.crtc != &crtc->base)
6980 continue;
6981 enabled = true;
6982 if (encoder->connectors_active)
6983 active = true;
6984 }
6985 WARN(active != crtc->active,
6986 "crtc's computed active state doesn't match tracked active state "
6987 "(expected %i, found %i)\n", active, crtc->active);
6988 WARN(enabled != crtc->base.enabled,
6989 "crtc's computed enabled state doesn't match tracked enabled state "
6990 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
6991
6992 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
6993 }
6994 }
6995
6996 bool intel_set_mode(struct drm_crtc *crtc,
6997 struct drm_display_mode *mode,
6998 int x, int y, struct drm_framebuffer *fb)
6999 {
7000 struct drm_device *dev = crtc->dev;
7001 drm_i915_private_t *dev_priv = dev->dev_private;
7002 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7003 struct drm_encoder_helper_funcs *encoder_funcs;
7004 struct drm_encoder *encoder;
7005 struct intel_crtc *intel_crtc;
7006 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7007 bool ret = true;
7008
7009 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7010 &prepare_pipes, &disable_pipes);
7011
7012 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7013 modeset_pipes, prepare_pipes, disable_pipes);
7014
7015 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7016 intel_crtc_disable(&intel_crtc->base);
7017
7018 saved_hwmode = crtc->hwmode;
7019 saved_mode = crtc->mode;
7020
7021 /* Hack: Because we don't (yet) support global modeset on multiple
7022 * crtcs, we don't keep track of the new mode for more than one crtc.
7023 * Hence simply check whether any bit is set in modeset_pipes in all the
7024 * pieces of code that are not yet converted to deal with mutliple crtcs
7025 * changing their mode at the same time. */
7026 adjusted_mode = NULL;
7027 if (modeset_pipes) {
7028 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7029 if (IS_ERR(adjusted_mode)) {
7030 return false;
7031 }
7032 }
7033
7034 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7035 if (intel_crtc->base.enabled)
7036 dev_priv->display.crtc_disable(&intel_crtc->base);
7037 }
7038
7039 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7040 * to set it here already despite that we pass it down the callchain.
7041 */
7042 if (modeset_pipes)
7043 crtc->mode = *mode;
7044
7045 /* Only after disabling all output pipelines that will be changed can we
7046 * update the the output configuration. */
7047 intel_modeset_update_state(dev, prepare_pipes);
7048
7049 /* Set up the DPLL and any encoders state that needs to adjust or depend
7050 * on the DPLL.
7051 */
7052 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7053 ret = !intel_crtc_mode_set(&intel_crtc->base,
7054 mode, adjusted_mode,
7055 x, y, fb);
7056 if (!ret)
7057 goto done;
7058
7059 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7060
7061 if (encoder->crtc != &intel_crtc->base)
7062 continue;
7063
7064 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7065 encoder->base.id, drm_get_encoder_name(encoder),
7066 mode->base.id, mode->name);
7067 encoder_funcs = encoder->helper_private;
7068 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7069 }
7070 }
7071
7072 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7073 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7074 dev_priv->display.crtc_enable(&intel_crtc->base);
7075
7076 if (modeset_pipes) {
7077 /* Store real post-adjustment hardware mode. */
7078 crtc->hwmode = *adjusted_mode;
7079
7080 /* Calculate and store various constants which
7081 * are later needed by vblank and swap-completion
7082 * timestamping. They are derived from true hwmode.
7083 */
7084 drm_calc_timestamping_constants(crtc);
7085 }
7086
7087 /* FIXME: add subpixel order */
7088 done:
7089 drm_mode_destroy(dev, adjusted_mode);
7090 if (!ret && crtc->enabled) {
7091 crtc->hwmode = saved_hwmode;
7092 crtc->mode = saved_mode;
7093 } else {
7094 intel_modeset_check_state(dev);
7095 }
7096
7097 return ret;
7098 }
7099
7100 #undef for_each_intel_crtc_masked
7101
7102 static void intel_set_config_free(struct intel_set_config *config)
7103 {
7104 if (!config)
7105 return;
7106
7107 kfree(config->save_connector_encoders);
7108 kfree(config->save_encoder_crtcs);
7109 kfree(config);
7110 }
7111
7112 static int intel_set_config_save_state(struct drm_device *dev,
7113 struct intel_set_config *config)
7114 {
7115 struct drm_encoder *encoder;
7116 struct drm_connector *connector;
7117 int count;
7118
7119 config->save_encoder_crtcs =
7120 kcalloc(dev->mode_config.num_encoder,
7121 sizeof(struct drm_crtc *), GFP_KERNEL);
7122 if (!config->save_encoder_crtcs)
7123 return -ENOMEM;
7124
7125 config->save_connector_encoders =
7126 kcalloc(dev->mode_config.num_connector,
7127 sizeof(struct drm_encoder *), GFP_KERNEL);
7128 if (!config->save_connector_encoders)
7129 return -ENOMEM;
7130
7131 /* Copy data. Note that driver private data is not affected.
7132 * Should anything bad happen only the expected state is
7133 * restored, not the drivers personal bookkeeping.
7134 */
7135 count = 0;
7136 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7137 config->save_encoder_crtcs[count++] = encoder->crtc;
7138 }
7139
7140 count = 0;
7141 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7142 config->save_connector_encoders[count++] = connector->encoder;
7143 }
7144
7145 return 0;
7146 }
7147
7148 static void intel_set_config_restore_state(struct drm_device *dev,
7149 struct intel_set_config *config)
7150 {
7151 struct intel_encoder *encoder;
7152 struct intel_connector *connector;
7153 int count;
7154
7155 count = 0;
7156 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7157 encoder->new_crtc =
7158 to_intel_crtc(config->save_encoder_crtcs[count++]);
7159 }
7160
7161 count = 0;
7162 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7163 connector->new_encoder =
7164 to_intel_encoder(config->save_connector_encoders[count++]);
7165 }
7166 }
7167
7168 static void
7169 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7170 struct intel_set_config *config)
7171 {
7172
7173 /* We should be able to check here if the fb has the same properties
7174 * and then just flip_or_move it */
7175 if (set->crtc->fb != set->fb) {
7176 /* If we have no fb then treat it as a full mode set */
7177 if (set->crtc->fb == NULL) {
7178 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7179 config->mode_changed = true;
7180 } else if (set->fb == NULL) {
7181 config->mode_changed = true;
7182 } else if (set->fb->depth != set->crtc->fb->depth) {
7183 config->mode_changed = true;
7184 } else if (set->fb->bits_per_pixel !=
7185 set->crtc->fb->bits_per_pixel) {
7186 config->mode_changed = true;
7187 } else
7188 config->fb_changed = true;
7189 }
7190
7191 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7192 config->fb_changed = true;
7193
7194 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7195 DRM_DEBUG_KMS("modes are different, full mode set\n");
7196 drm_mode_debug_printmodeline(&set->crtc->mode);
7197 drm_mode_debug_printmodeline(set->mode);
7198 config->mode_changed = true;
7199 }
7200 }
7201
7202 static int
7203 intel_modeset_stage_output_state(struct drm_device *dev,
7204 struct drm_mode_set *set,
7205 struct intel_set_config *config)
7206 {
7207 struct drm_crtc *new_crtc;
7208 struct intel_connector *connector;
7209 struct intel_encoder *encoder;
7210 int count, ro;
7211
7212 /* The upper layers ensure that we either disabl a crtc or have a list
7213 * of connectors. For paranoia, double-check this. */
7214 WARN_ON(!set->fb && (set->num_connectors != 0));
7215 WARN_ON(set->fb && (set->num_connectors == 0));
7216
7217 count = 0;
7218 list_for_each_entry(connector, &dev->mode_config.connector_list,
7219 base.head) {
7220 /* Otherwise traverse passed in connector list and get encoders
7221 * for them. */
7222 for (ro = 0; ro < set->num_connectors; ro++) {
7223 if (set->connectors[ro] == &connector->base) {
7224 connector->new_encoder = connector->encoder;
7225 break;
7226 }
7227 }
7228
7229 /* If we disable the crtc, disable all its connectors. Also, if
7230 * the connector is on the changing crtc but not on the new
7231 * connector list, disable it. */
7232 if ((!set->fb || ro == set->num_connectors) &&
7233 connector->base.encoder &&
7234 connector->base.encoder->crtc == set->crtc) {
7235 connector->new_encoder = NULL;
7236
7237 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7238 connector->base.base.id,
7239 drm_get_connector_name(&connector->base));
7240 }
7241
7242
7243 if (&connector->new_encoder->base != connector->base.encoder) {
7244 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7245 config->mode_changed = true;
7246 }
7247
7248 /* Disable all disconnected encoders. */
7249 if (connector->base.status == connector_status_disconnected)
7250 connector->new_encoder = NULL;
7251 }
7252 /* connector->new_encoder is now updated for all connectors. */
7253
7254 /* Update crtc of enabled connectors. */
7255 count = 0;
7256 list_for_each_entry(connector, &dev->mode_config.connector_list,
7257 base.head) {
7258 if (!connector->new_encoder)
7259 continue;
7260
7261 new_crtc = connector->new_encoder->base.crtc;
7262
7263 for (ro = 0; ro < set->num_connectors; ro++) {
7264 if (set->connectors[ro] == &connector->base)
7265 new_crtc = set->crtc;
7266 }
7267
7268 /* Make sure the new CRTC will work with the encoder */
7269 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7270 new_crtc)) {
7271 return -EINVAL;
7272 }
7273 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7274
7275 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7276 connector->base.base.id,
7277 drm_get_connector_name(&connector->base),
7278 new_crtc->base.id);
7279 }
7280
7281 /* Check for any encoders that needs to be disabled. */
7282 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7283 base.head) {
7284 list_for_each_entry(connector,
7285 &dev->mode_config.connector_list,
7286 base.head) {
7287 if (connector->new_encoder == encoder) {
7288 WARN_ON(!connector->new_encoder->new_crtc);
7289
7290 goto next_encoder;
7291 }
7292 }
7293 encoder->new_crtc = NULL;
7294 next_encoder:
7295 /* Only now check for crtc changes so we don't miss encoders
7296 * that will be disabled. */
7297 if (&encoder->new_crtc->base != encoder->base.crtc) {
7298 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7299 config->mode_changed = true;
7300 }
7301 }
7302 /* Now we've also updated encoder->new_crtc for all encoders. */
7303
7304 return 0;
7305 }
7306
7307 static int intel_crtc_set_config(struct drm_mode_set *set)
7308 {
7309 struct drm_device *dev;
7310 struct drm_mode_set save_set;
7311 struct intel_set_config *config;
7312 int ret;
7313 int i;
7314
7315 BUG_ON(!set);
7316 BUG_ON(!set->crtc);
7317 BUG_ON(!set->crtc->helper_private);
7318
7319 if (!set->mode)
7320 set->fb = NULL;
7321
7322 /* The fb helper likes to play gross jokes with ->mode_set_config.
7323 * Unfortunately the crtc helper doesn't do much at all for this case,
7324 * so we have to cope with this madness until the fb helper is fixed up. */
7325 if (set->fb && set->num_connectors == 0)
7326 return 0;
7327
7328 if (set->fb) {
7329 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7330 set->crtc->base.id, set->fb->base.id,
7331 (int)set->num_connectors, set->x, set->y);
7332 } else {
7333 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7334 }
7335
7336 dev = set->crtc->dev;
7337
7338 ret = -ENOMEM;
7339 config = kzalloc(sizeof(*config), GFP_KERNEL);
7340 if (!config)
7341 goto out_config;
7342
7343 ret = intel_set_config_save_state(dev, config);
7344 if (ret)
7345 goto out_config;
7346
7347 save_set.crtc = set->crtc;
7348 save_set.mode = &set->crtc->mode;
7349 save_set.x = set->crtc->x;
7350 save_set.y = set->crtc->y;
7351 save_set.fb = set->crtc->fb;
7352
7353 /* Compute whether we need a full modeset, only an fb base update or no
7354 * change at all. In the future we might also check whether only the
7355 * mode changed, e.g. for LVDS where we only change the panel fitter in
7356 * such cases. */
7357 intel_set_config_compute_mode_changes(set, config);
7358
7359 ret = intel_modeset_stage_output_state(dev, set, config);
7360 if (ret)
7361 goto fail;
7362
7363 if (config->mode_changed) {
7364 if (set->mode) {
7365 DRM_DEBUG_KMS("attempting to set mode from"
7366 " userspace\n");
7367 drm_mode_debug_printmodeline(set->mode);
7368 }
7369
7370 if (!intel_set_mode(set->crtc, set->mode,
7371 set->x, set->y, set->fb)) {
7372 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7373 set->crtc->base.id);
7374 ret = -EINVAL;
7375 goto fail;
7376 }
7377
7378 if (set->crtc->enabled) {
7379 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7380 for (i = 0; i < set->num_connectors; i++) {
7381 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
7382 drm_get_connector_name(set->connectors[i]));
7383 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
7384 }
7385 }
7386 } else if (config->fb_changed) {
7387 ret = intel_pipe_set_base(set->crtc,
7388 set->x, set->y, set->fb);
7389 }
7390
7391 intel_set_config_free(config);
7392
7393 return 0;
7394
7395 fail:
7396 intel_set_config_restore_state(dev, config);
7397
7398 /* Try to restore the config */
7399 if (config->mode_changed &&
7400 !intel_set_mode(save_set.crtc, save_set.mode,
7401 save_set.x, save_set.y, save_set.fb))
7402 DRM_ERROR("failed to restore config after modeset failure\n");
7403
7404 out_config:
7405 intel_set_config_free(config);
7406 return ret;
7407 }
7408
7409 static const struct drm_crtc_funcs intel_crtc_funcs = {
7410 .cursor_set = intel_crtc_cursor_set,
7411 .cursor_move = intel_crtc_cursor_move,
7412 .gamma_set = intel_crtc_gamma_set,
7413 .set_config = intel_crtc_set_config,
7414 .destroy = intel_crtc_destroy,
7415 .page_flip = intel_crtc_page_flip,
7416 };
7417
7418 static void intel_pch_pll_init(struct drm_device *dev)
7419 {
7420 drm_i915_private_t *dev_priv = dev->dev_private;
7421 int i;
7422
7423 if (dev_priv->num_pch_pll == 0) {
7424 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7425 return;
7426 }
7427
7428 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7429 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7430 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7431 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7432 }
7433 }
7434
7435 static void intel_crtc_init(struct drm_device *dev, int pipe)
7436 {
7437 drm_i915_private_t *dev_priv = dev->dev_private;
7438 struct intel_crtc *intel_crtc;
7439 int i;
7440
7441 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7442 if (intel_crtc == NULL)
7443 return;
7444
7445 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7446
7447 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7448 for (i = 0; i < 256; i++) {
7449 intel_crtc->lut_r[i] = i;
7450 intel_crtc->lut_g[i] = i;
7451 intel_crtc->lut_b[i] = i;
7452 }
7453
7454 /* Swap pipes & planes for FBC on pre-965 */
7455 intel_crtc->pipe = pipe;
7456 intel_crtc->plane = pipe;
7457 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7458 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7459 intel_crtc->plane = !pipe;
7460 }
7461
7462 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7463 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7464 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7465 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7466
7467 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7468
7469 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7470 }
7471
7472 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7473 struct drm_file *file)
7474 {
7475 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7476 struct drm_mode_object *drmmode_obj;
7477 struct intel_crtc *crtc;
7478
7479 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7480 return -ENODEV;
7481
7482 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7483 DRM_MODE_OBJECT_CRTC);
7484
7485 if (!drmmode_obj) {
7486 DRM_ERROR("no such CRTC id\n");
7487 return -EINVAL;
7488 }
7489
7490 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7491 pipe_from_crtc_id->pipe = crtc->pipe;
7492
7493 return 0;
7494 }
7495
7496 static int intel_encoder_clones(struct intel_encoder *encoder)
7497 {
7498 struct drm_device *dev = encoder->base.dev;
7499 struct intel_encoder *source_encoder;
7500 int index_mask = 0;
7501 int entry = 0;
7502
7503 list_for_each_entry(source_encoder,
7504 &dev->mode_config.encoder_list, base.head) {
7505
7506 if (encoder == source_encoder)
7507 index_mask |= (1 << entry);
7508
7509 /* Intel hw has only one MUX where enocoders could be cloned. */
7510 if (encoder->cloneable && source_encoder->cloneable)
7511 index_mask |= (1 << entry);
7512
7513 entry++;
7514 }
7515
7516 return index_mask;
7517 }
7518
7519 static bool has_edp_a(struct drm_device *dev)
7520 {
7521 struct drm_i915_private *dev_priv = dev->dev_private;
7522
7523 if (!IS_MOBILE(dev))
7524 return false;
7525
7526 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7527 return false;
7528
7529 if (IS_GEN5(dev) &&
7530 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7531 return false;
7532
7533 return true;
7534 }
7535
7536 static void intel_setup_outputs(struct drm_device *dev)
7537 {
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539 struct intel_encoder *encoder;
7540 bool dpd_is_edp = false;
7541 bool has_lvds;
7542
7543 has_lvds = intel_lvds_init(dev);
7544 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7545 /* disable the panel fitter on everything but LVDS */
7546 I915_WRITE(PFIT_CONTROL, 0);
7547 }
7548
7549 if (HAS_PCH_SPLIT(dev)) {
7550 dpd_is_edp = intel_dpd_is_edp(dev);
7551
7552 if (has_edp_a(dev))
7553 intel_dp_init(dev, DP_A, PORT_A);
7554
7555 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7556 intel_dp_init(dev, PCH_DP_D, PORT_D);
7557 }
7558
7559 intel_crt_init(dev);
7560
7561 if (IS_HASWELL(dev)) {
7562 int found;
7563
7564 /* Haswell uses DDI functions to detect digital outputs */
7565 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7566 /* DDI A only supports eDP */
7567 if (found)
7568 intel_ddi_init(dev, PORT_A);
7569
7570 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7571 * register */
7572 found = I915_READ(SFUSE_STRAP);
7573
7574 if (found & SFUSE_STRAP_DDIB_DETECTED)
7575 intel_ddi_init(dev, PORT_B);
7576 if (found & SFUSE_STRAP_DDIC_DETECTED)
7577 intel_ddi_init(dev, PORT_C);
7578 if (found & SFUSE_STRAP_DDID_DETECTED)
7579 intel_ddi_init(dev, PORT_D);
7580 } else if (HAS_PCH_SPLIT(dev)) {
7581 int found;
7582
7583 if (I915_READ(HDMIB) & PORT_DETECTED) {
7584 /* PCH SDVOB multiplex with HDMIB */
7585 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7586 if (!found)
7587 intel_hdmi_init(dev, HDMIB, PORT_B);
7588 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7589 intel_dp_init(dev, PCH_DP_B, PORT_B);
7590 }
7591
7592 if (I915_READ(HDMIC) & PORT_DETECTED)
7593 intel_hdmi_init(dev, HDMIC, PORT_C);
7594
7595 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7596 intel_hdmi_init(dev, HDMID, PORT_D);
7597
7598 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7599 intel_dp_init(dev, PCH_DP_C, PORT_C);
7600
7601 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7602 intel_dp_init(dev, PCH_DP_D, PORT_D);
7603 } else if (IS_VALLEYVIEW(dev)) {
7604 int found;
7605
7606 if (I915_READ(SDVOB) & PORT_DETECTED) {
7607 /* SDVOB multiplex with HDMIB */
7608 found = intel_sdvo_init(dev, SDVOB, true);
7609 if (!found)
7610 intel_hdmi_init(dev, SDVOB, PORT_B);
7611 if (!found && (I915_READ(DP_B) & DP_DETECTED))
7612 intel_dp_init(dev, DP_B, PORT_B);
7613 }
7614
7615 if (I915_READ(SDVOC) & PORT_DETECTED)
7616 intel_hdmi_init(dev, SDVOC, PORT_C);
7617
7618 /* Shares lanes with HDMI on SDVOC */
7619 if (I915_READ(DP_C) & DP_DETECTED)
7620 intel_dp_init(dev, DP_C, PORT_C);
7621 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7622 bool found = false;
7623
7624 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7625 DRM_DEBUG_KMS("probing SDVOB\n");
7626 found = intel_sdvo_init(dev, SDVOB, true);
7627 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7628 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7629 intel_hdmi_init(dev, SDVOB, PORT_B);
7630 }
7631
7632 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7633 DRM_DEBUG_KMS("probing DP_B\n");
7634 intel_dp_init(dev, DP_B, PORT_B);
7635 }
7636 }
7637
7638 /* Before G4X SDVOC doesn't have its own detect register */
7639
7640 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7641 DRM_DEBUG_KMS("probing SDVOC\n");
7642 found = intel_sdvo_init(dev, SDVOC, false);
7643 }
7644
7645 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7646
7647 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7648 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7649 intel_hdmi_init(dev, SDVOC, PORT_C);
7650 }
7651 if (SUPPORTS_INTEGRATED_DP(dev)) {
7652 DRM_DEBUG_KMS("probing DP_C\n");
7653 intel_dp_init(dev, DP_C, PORT_C);
7654 }
7655 }
7656
7657 if (SUPPORTS_INTEGRATED_DP(dev) &&
7658 (I915_READ(DP_D) & DP_DETECTED)) {
7659 DRM_DEBUG_KMS("probing DP_D\n");
7660 intel_dp_init(dev, DP_D, PORT_D);
7661 }
7662 } else if (IS_GEN2(dev))
7663 intel_dvo_init(dev);
7664
7665 if (SUPPORTS_TV(dev))
7666 intel_tv_init(dev);
7667
7668 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7669 encoder->base.possible_crtcs = encoder->crtc_mask;
7670 encoder->base.possible_clones =
7671 intel_encoder_clones(encoder);
7672 }
7673
7674 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7675 ironlake_init_pch_refclk(dev);
7676 }
7677
7678 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7679 {
7680 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7681
7682 drm_framebuffer_cleanup(fb);
7683 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7684
7685 kfree(intel_fb);
7686 }
7687
7688 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7689 struct drm_file *file,
7690 unsigned int *handle)
7691 {
7692 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7693 struct drm_i915_gem_object *obj = intel_fb->obj;
7694
7695 return drm_gem_handle_create(file, &obj->base, handle);
7696 }
7697
7698 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7699 .destroy = intel_user_framebuffer_destroy,
7700 .create_handle = intel_user_framebuffer_create_handle,
7701 };
7702
7703 int intel_framebuffer_init(struct drm_device *dev,
7704 struct intel_framebuffer *intel_fb,
7705 struct drm_mode_fb_cmd2 *mode_cmd,
7706 struct drm_i915_gem_object *obj)
7707 {
7708 int ret;
7709
7710 if (obj->tiling_mode == I915_TILING_Y)
7711 return -EINVAL;
7712
7713 if (mode_cmd->pitches[0] & 63)
7714 return -EINVAL;
7715
7716 switch (mode_cmd->pixel_format) {
7717 case DRM_FORMAT_RGB332:
7718 case DRM_FORMAT_RGB565:
7719 case DRM_FORMAT_XRGB8888:
7720 case DRM_FORMAT_XBGR8888:
7721 case DRM_FORMAT_ARGB8888:
7722 case DRM_FORMAT_XRGB2101010:
7723 case DRM_FORMAT_ARGB2101010:
7724 /* RGB formats are common across chipsets */
7725 break;
7726 case DRM_FORMAT_YUYV:
7727 case DRM_FORMAT_UYVY:
7728 case DRM_FORMAT_YVYU:
7729 case DRM_FORMAT_VYUY:
7730 break;
7731 default:
7732 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7733 mode_cmd->pixel_format);
7734 return -EINVAL;
7735 }
7736
7737 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7738 if (ret) {
7739 DRM_ERROR("framebuffer init failed %d\n", ret);
7740 return ret;
7741 }
7742
7743 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7744 intel_fb->obj = obj;
7745 return 0;
7746 }
7747
7748 static struct drm_framebuffer *
7749 intel_user_framebuffer_create(struct drm_device *dev,
7750 struct drm_file *filp,
7751 struct drm_mode_fb_cmd2 *mode_cmd)
7752 {
7753 struct drm_i915_gem_object *obj;
7754
7755 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7756 mode_cmd->handles[0]));
7757 if (&obj->base == NULL)
7758 return ERR_PTR(-ENOENT);
7759
7760 return intel_framebuffer_create(dev, mode_cmd, obj);
7761 }
7762
7763 static const struct drm_mode_config_funcs intel_mode_funcs = {
7764 .fb_create = intel_user_framebuffer_create,
7765 .output_poll_changed = intel_fb_output_poll_changed,
7766 };
7767
7768 /* Set up chip specific display functions */
7769 static void intel_init_display(struct drm_device *dev)
7770 {
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772
7773 /* We always want a DPMS function */
7774 if (HAS_PCH_SPLIT(dev)) {
7775 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7776 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7777 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7778 dev_priv->display.off = ironlake_crtc_off;
7779 dev_priv->display.update_plane = ironlake_update_plane;
7780 } else {
7781 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7782 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7783 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7784 dev_priv->display.off = i9xx_crtc_off;
7785 dev_priv->display.update_plane = i9xx_update_plane;
7786 }
7787
7788 /* Returns the core display clock speed */
7789 if (IS_VALLEYVIEW(dev))
7790 dev_priv->display.get_display_clock_speed =
7791 valleyview_get_display_clock_speed;
7792 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7793 dev_priv->display.get_display_clock_speed =
7794 i945_get_display_clock_speed;
7795 else if (IS_I915G(dev))
7796 dev_priv->display.get_display_clock_speed =
7797 i915_get_display_clock_speed;
7798 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7799 dev_priv->display.get_display_clock_speed =
7800 i9xx_misc_get_display_clock_speed;
7801 else if (IS_I915GM(dev))
7802 dev_priv->display.get_display_clock_speed =
7803 i915gm_get_display_clock_speed;
7804 else if (IS_I865G(dev))
7805 dev_priv->display.get_display_clock_speed =
7806 i865_get_display_clock_speed;
7807 else if (IS_I85X(dev))
7808 dev_priv->display.get_display_clock_speed =
7809 i855_get_display_clock_speed;
7810 else /* 852, 830 */
7811 dev_priv->display.get_display_clock_speed =
7812 i830_get_display_clock_speed;
7813
7814 if (HAS_PCH_SPLIT(dev)) {
7815 if (IS_GEN5(dev)) {
7816 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7817 dev_priv->display.write_eld = ironlake_write_eld;
7818 } else if (IS_GEN6(dev)) {
7819 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7820 dev_priv->display.write_eld = ironlake_write_eld;
7821 } else if (IS_IVYBRIDGE(dev)) {
7822 /* FIXME: detect B0+ stepping and use auto training */
7823 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7824 dev_priv->display.write_eld = ironlake_write_eld;
7825 } else if (IS_HASWELL(dev)) {
7826 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7827 dev_priv->display.write_eld = haswell_write_eld;
7828 } else
7829 dev_priv->display.update_wm = NULL;
7830 } else if (IS_G4X(dev)) {
7831 dev_priv->display.write_eld = g4x_write_eld;
7832 }
7833
7834 /* Default just returns -ENODEV to indicate unsupported */
7835 dev_priv->display.queue_flip = intel_default_queue_flip;
7836
7837 switch (INTEL_INFO(dev)->gen) {
7838 case 2:
7839 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7840 break;
7841
7842 case 3:
7843 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7844 break;
7845
7846 case 4:
7847 case 5:
7848 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7849 break;
7850
7851 case 6:
7852 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7853 break;
7854 case 7:
7855 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7856 break;
7857 }
7858 }
7859
7860 /*
7861 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7862 * resume, or other times. This quirk makes sure that's the case for
7863 * affected systems.
7864 */
7865 static void quirk_pipea_force(struct drm_device *dev)
7866 {
7867 struct drm_i915_private *dev_priv = dev->dev_private;
7868
7869 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7870 DRM_INFO("applying pipe a force quirk\n");
7871 }
7872
7873 /*
7874 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7875 */
7876 static void quirk_ssc_force_disable(struct drm_device *dev)
7877 {
7878 struct drm_i915_private *dev_priv = dev->dev_private;
7879 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7880 DRM_INFO("applying lvds SSC disable quirk\n");
7881 }
7882
7883 /*
7884 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7885 * brightness value
7886 */
7887 static void quirk_invert_brightness(struct drm_device *dev)
7888 {
7889 struct drm_i915_private *dev_priv = dev->dev_private;
7890 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7891 DRM_INFO("applying inverted panel brightness quirk\n");
7892 }
7893
7894 struct intel_quirk {
7895 int device;
7896 int subsystem_vendor;
7897 int subsystem_device;
7898 void (*hook)(struct drm_device *dev);
7899 };
7900
7901 static struct intel_quirk intel_quirks[] = {
7902 /* HP Mini needs pipe A force quirk (LP: #322104) */
7903 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7904
7905 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7906 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7907
7908 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7909 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7910
7911 /* 855 & before need to leave pipe A & dpll A up */
7912 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7913 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7914 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7915
7916 /* Lenovo U160 cannot use SSC on LVDS */
7917 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7918
7919 /* Sony Vaio Y cannot use SSC on LVDS */
7920 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7921
7922 /* Acer Aspire 5734Z must invert backlight brightness */
7923 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7924 };
7925
7926 static void intel_init_quirks(struct drm_device *dev)
7927 {
7928 struct pci_dev *d = dev->pdev;
7929 int i;
7930
7931 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7932 struct intel_quirk *q = &intel_quirks[i];
7933
7934 if (d->device == q->device &&
7935 (d->subsystem_vendor == q->subsystem_vendor ||
7936 q->subsystem_vendor == PCI_ANY_ID) &&
7937 (d->subsystem_device == q->subsystem_device ||
7938 q->subsystem_device == PCI_ANY_ID))
7939 q->hook(dev);
7940 }
7941 }
7942
7943 /* Disable the VGA plane that we never use */
7944 static void i915_disable_vga(struct drm_device *dev)
7945 {
7946 struct drm_i915_private *dev_priv = dev->dev_private;
7947 u8 sr1;
7948 u32 vga_reg;
7949
7950 if (HAS_PCH_SPLIT(dev))
7951 vga_reg = CPU_VGACNTRL;
7952 else
7953 vga_reg = VGACNTRL;
7954
7955 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7956 outb(SR01, VGA_SR_INDEX);
7957 sr1 = inb(VGA_SR_DATA);
7958 outb(sr1 | 1<<5, VGA_SR_DATA);
7959 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7960 udelay(300);
7961
7962 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7963 POSTING_READ(vga_reg);
7964 }
7965
7966 void intel_modeset_init_hw(struct drm_device *dev)
7967 {
7968 /* We attempt to init the necessary power wells early in the initialization
7969 * time, so the subsystems that expect power to be enabled can work.
7970 */
7971 intel_init_power_wells(dev);
7972
7973 intel_prepare_ddi(dev);
7974
7975 intel_init_clock_gating(dev);
7976
7977 mutex_lock(&dev->struct_mutex);
7978 intel_enable_gt_powersave(dev);
7979 mutex_unlock(&dev->struct_mutex);
7980 }
7981
7982 void intel_modeset_init(struct drm_device *dev)
7983 {
7984 struct drm_i915_private *dev_priv = dev->dev_private;
7985 int i, ret;
7986
7987 drm_mode_config_init(dev);
7988
7989 dev->mode_config.min_width = 0;
7990 dev->mode_config.min_height = 0;
7991
7992 dev->mode_config.preferred_depth = 24;
7993 dev->mode_config.prefer_shadow = 1;
7994
7995 dev->mode_config.funcs = &intel_mode_funcs;
7996
7997 intel_init_quirks(dev);
7998
7999 intel_init_pm(dev);
8000
8001 intel_init_display(dev);
8002
8003 if (IS_GEN2(dev)) {
8004 dev->mode_config.max_width = 2048;
8005 dev->mode_config.max_height = 2048;
8006 } else if (IS_GEN3(dev)) {
8007 dev->mode_config.max_width = 4096;
8008 dev->mode_config.max_height = 4096;
8009 } else {
8010 dev->mode_config.max_width = 8192;
8011 dev->mode_config.max_height = 8192;
8012 }
8013 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8014
8015 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8016 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8017
8018 for (i = 0; i < dev_priv->num_pipe; i++) {
8019 intel_crtc_init(dev, i);
8020 ret = intel_plane_init(dev, i);
8021 if (ret)
8022 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8023 }
8024
8025 intel_pch_pll_init(dev);
8026
8027 /* Just disable it once at startup */
8028 i915_disable_vga(dev);
8029 intel_setup_outputs(dev);
8030 }
8031
8032 static void
8033 intel_connector_break_all_links(struct intel_connector *connector)
8034 {
8035 connector->base.dpms = DRM_MODE_DPMS_OFF;
8036 connector->base.encoder = NULL;
8037 connector->encoder->connectors_active = false;
8038 connector->encoder->base.crtc = NULL;
8039 }
8040
8041 static void intel_enable_pipe_a(struct drm_device *dev)
8042 {
8043 struct intel_connector *connector;
8044 struct drm_connector *crt = NULL;
8045 struct intel_load_detect_pipe load_detect_temp;
8046
8047 /* We can't just switch on the pipe A, we need to set things up with a
8048 * proper mode and output configuration. As a gross hack, enable pipe A
8049 * by enabling the load detect pipe once. */
8050 list_for_each_entry(connector,
8051 &dev->mode_config.connector_list,
8052 base.head) {
8053 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8054 crt = &connector->base;
8055 break;
8056 }
8057 }
8058
8059 if (!crt)
8060 return;
8061
8062 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8063 intel_release_load_detect_pipe(crt, &load_detect_temp);
8064
8065
8066 }
8067
8068 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8069 {
8070 struct drm_device *dev = crtc->base.dev;
8071 struct drm_i915_private *dev_priv = dev->dev_private;
8072 u32 reg, val;
8073
8074 /* Clear any frame start delays used for debugging left by the BIOS */
8075 reg = PIPECONF(crtc->pipe);
8076 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8077
8078 /* We need to sanitize the plane -> pipe mapping first because this will
8079 * disable the crtc (and hence change the state) if it is wrong. */
8080 if (!HAS_PCH_SPLIT(dev)) {
8081 struct intel_connector *connector;
8082 bool plane;
8083
8084 reg = DSPCNTR(crtc->plane);
8085 val = I915_READ(reg);
8086
8087 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8088 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8089 goto ok;
8090
8091 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8092 crtc->base.base.id);
8093
8094 /* Pipe has the wrong plane attached and the plane is active.
8095 * Temporarily change the plane mapping and disable everything
8096 * ... */
8097 plane = crtc->plane;
8098 crtc->plane = !plane;
8099 dev_priv->display.crtc_disable(&crtc->base);
8100 crtc->plane = plane;
8101
8102 /* ... and break all links. */
8103 list_for_each_entry(connector, &dev->mode_config.connector_list,
8104 base.head) {
8105 if (connector->encoder->base.crtc != &crtc->base)
8106 continue;
8107
8108 intel_connector_break_all_links(connector);
8109 }
8110
8111 WARN_ON(crtc->active);
8112 crtc->base.enabled = false;
8113 }
8114 ok:
8115
8116 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8117 crtc->pipe == PIPE_A && !crtc->active) {
8118 /* BIOS forgot to enable pipe A, this mostly happens after
8119 * resume. Force-enable the pipe to fix this, the update_dpms
8120 * call below we restore the pipe to the right state, but leave
8121 * the required bits on. */
8122 intel_enable_pipe_a(dev);
8123 }
8124
8125 /* Adjust the state of the output pipe according to whether we
8126 * have active connectors/encoders. */
8127 intel_crtc_update_dpms(&crtc->base);
8128
8129 if (crtc->active != crtc->base.enabled) {
8130 struct intel_encoder *encoder;
8131
8132 /* This can happen either due to bugs in the get_hw_state
8133 * functions or because the pipe is force-enabled due to the
8134 * pipe A quirk. */
8135 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8136 crtc->base.base.id,
8137 crtc->base.enabled ? "enabled" : "disabled",
8138 crtc->active ? "enabled" : "disabled");
8139
8140 crtc->base.enabled = crtc->active;
8141
8142 /* Because we only establish the connector -> encoder ->
8143 * crtc links if something is active, this means the
8144 * crtc is now deactivated. Break the links. connector
8145 * -> encoder links are only establish when things are
8146 * actually up, hence no need to break them. */
8147 WARN_ON(crtc->active);
8148
8149 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8150 WARN_ON(encoder->connectors_active);
8151 encoder->base.crtc = NULL;
8152 }
8153 }
8154 }
8155
8156 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8157 {
8158 struct intel_connector *connector;
8159 struct drm_device *dev = encoder->base.dev;
8160
8161 /* We need to check both for a crtc link (meaning that the
8162 * encoder is active and trying to read from a pipe) and the
8163 * pipe itself being active. */
8164 bool has_active_crtc = encoder->base.crtc &&
8165 to_intel_crtc(encoder->base.crtc)->active;
8166
8167 if (encoder->connectors_active && !has_active_crtc) {
8168 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8169 encoder->base.base.id,
8170 drm_get_encoder_name(&encoder->base));
8171
8172 /* Connector is active, but has no active pipe. This is
8173 * fallout from our resume register restoring. Disable
8174 * the encoder manually again. */
8175 if (encoder->base.crtc) {
8176 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8177 encoder->base.base.id,
8178 drm_get_encoder_name(&encoder->base));
8179 encoder->disable(encoder);
8180 }
8181
8182 /* Inconsistent output/port/pipe state happens presumably due to
8183 * a bug in one of the get_hw_state functions. Or someplace else
8184 * in our code, like the register restore mess on resume. Clamp
8185 * things to off as a safer default. */
8186 list_for_each_entry(connector,
8187 &dev->mode_config.connector_list,
8188 base.head) {
8189 if (connector->encoder != encoder)
8190 continue;
8191
8192 intel_connector_break_all_links(connector);
8193 }
8194 }
8195 /* Enabled encoders without active connectors will be fixed in
8196 * the crtc fixup. */
8197 }
8198
8199 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8200 * and i915 state tracking structures. */
8201 void intel_modeset_setup_hw_state(struct drm_device *dev)
8202 {
8203 struct drm_i915_private *dev_priv = dev->dev_private;
8204 enum pipe pipe;
8205 u32 tmp;
8206 struct intel_crtc *crtc;
8207 struct intel_encoder *encoder;
8208 struct intel_connector *connector;
8209
8210 for_each_pipe(pipe) {
8211 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8212
8213 tmp = I915_READ(PIPECONF(pipe));
8214 if (tmp & PIPECONF_ENABLE)
8215 crtc->active = true;
8216 else
8217 crtc->active = false;
8218
8219 crtc->base.enabled = crtc->active;
8220
8221 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8222 crtc->base.base.id,
8223 crtc->active ? "enabled" : "disabled");
8224 }
8225
8226 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8227 base.head) {
8228 pipe = 0;
8229
8230 if (encoder->get_hw_state(encoder, &pipe)) {
8231 encoder->base.crtc =
8232 dev_priv->pipe_to_crtc_mapping[pipe];
8233 } else {
8234 encoder->base.crtc = NULL;
8235 }
8236
8237 encoder->connectors_active = false;
8238 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8239 encoder->base.base.id,
8240 drm_get_encoder_name(&encoder->base),
8241 encoder->base.crtc ? "enabled" : "disabled",
8242 pipe);
8243 }
8244
8245 list_for_each_entry(connector, &dev->mode_config.connector_list,
8246 base.head) {
8247 if (connector->get_hw_state(connector)) {
8248 connector->base.dpms = DRM_MODE_DPMS_ON;
8249 connector->encoder->connectors_active = true;
8250 connector->base.encoder = &connector->encoder->base;
8251 } else {
8252 connector->base.dpms = DRM_MODE_DPMS_OFF;
8253 connector->base.encoder = NULL;
8254 }
8255 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8256 connector->base.base.id,
8257 drm_get_connector_name(&connector->base),
8258 connector->base.encoder ? "enabled" : "disabled");
8259 }
8260
8261 /* HW state is read out, now we need to sanitize this mess. */
8262 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8263 base.head) {
8264 intel_sanitize_encoder(encoder);
8265 }
8266
8267 for_each_pipe(pipe) {
8268 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8269 intel_sanitize_crtc(crtc);
8270 }
8271
8272 intel_modeset_update_staged_output_state(dev);
8273
8274 intel_modeset_check_state(dev);
8275 }
8276
8277 void intel_modeset_gem_init(struct drm_device *dev)
8278 {
8279 intel_modeset_init_hw(dev);
8280
8281 intel_setup_overlay(dev);
8282
8283 intel_modeset_setup_hw_state(dev);
8284 }
8285
8286 void intel_modeset_cleanup(struct drm_device *dev)
8287 {
8288 struct drm_i915_private *dev_priv = dev->dev_private;
8289 struct drm_crtc *crtc;
8290 struct intel_crtc *intel_crtc;
8291
8292 drm_kms_helper_poll_fini(dev);
8293 mutex_lock(&dev->struct_mutex);
8294
8295 intel_unregister_dsm_handler();
8296
8297
8298 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8299 /* Skip inactive CRTCs */
8300 if (!crtc->fb)
8301 continue;
8302
8303 intel_crtc = to_intel_crtc(crtc);
8304 intel_increase_pllclock(crtc);
8305 }
8306
8307 intel_disable_fbc(dev);
8308
8309 intel_disable_gt_powersave(dev);
8310
8311 ironlake_teardown_rc6(dev);
8312
8313 if (IS_VALLEYVIEW(dev))
8314 vlv_init_dpio(dev);
8315
8316 mutex_unlock(&dev->struct_mutex);
8317
8318 /* Disable the irq before mode object teardown, for the irq might
8319 * enqueue unpin/hotplug work. */
8320 drm_irq_uninstall(dev);
8321 cancel_work_sync(&dev_priv->hotplug_work);
8322 cancel_work_sync(&dev_priv->rps.work);
8323
8324 /* flush any delayed tasks or pending work */
8325 flush_scheduled_work();
8326
8327 drm_mode_config_cleanup(dev);
8328 }
8329
8330 /*
8331 * Return which encoder is currently attached for connector.
8332 */
8333 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8334 {
8335 return &intel_attached_encoder(connector)->base;
8336 }
8337
8338 void intel_connector_attach_encoder(struct intel_connector *connector,
8339 struct intel_encoder *encoder)
8340 {
8341 connector->encoder = encoder;
8342 drm_mode_connector_attach_encoder(&connector->base,
8343 &encoder->base);
8344 }
8345
8346 /*
8347 * set vga decode state - true == enable VGA decode
8348 */
8349 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8350 {
8351 struct drm_i915_private *dev_priv = dev->dev_private;
8352 u16 gmch_ctrl;
8353
8354 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8355 if (state)
8356 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8357 else
8358 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8359 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8360 return 0;
8361 }
8362
8363 #ifdef CONFIG_DEBUG_FS
8364 #include <linux/seq_file.h>
8365
8366 struct intel_display_error_state {
8367 struct intel_cursor_error_state {
8368 u32 control;
8369 u32 position;
8370 u32 base;
8371 u32 size;
8372 } cursor[I915_MAX_PIPES];
8373
8374 struct intel_pipe_error_state {
8375 u32 conf;
8376 u32 source;
8377
8378 u32 htotal;
8379 u32 hblank;
8380 u32 hsync;
8381 u32 vtotal;
8382 u32 vblank;
8383 u32 vsync;
8384 } pipe[I915_MAX_PIPES];
8385
8386 struct intel_plane_error_state {
8387 u32 control;
8388 u32 stride;
8389 u32 size;
8390 u32 pos;
8391 u32 addr;
8392 u32 surface;
8393 u32 tile_offset;
8394 } plane[I915_MAX_PIPES];
8395 };
8396
8397 struct intel_display_error_state *
8398 intel_display_capture_error_state(struct drm_device *dev)
8399 {
8400 drm_i915_private_t *dev_priv = dev->dev_private;
8401 struct intel_display_error_state *error;
8402 int i;
8403
8404 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8405 if (error == NULL)
8406 return NULL;
8407
8408 for_each_pipe(i) {
8409 error->cursor[i].control = I915_READ(CURCNTR(i));
8410 error->cursor[i].position = I915_READ(CURPOS(i));
8411 error->cursor[i].base = I915_READ(CURBASE(i));
8412
8413 error->plane[i].control = I915_READ(DSPCNTR(i));
8414 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8415 error->plane[i].size = I915_READ(DSPSIZE(i));
8416 error->plane[i].pos = I915_READ(DSPPOS(i));
8417 error->plane[i].addr = I915_READ(DSPADDR(i));
8418 if (INTEL_INFO(dev)->gen >= 4) {
8419 error->plane[i].surface = I915_READ(DSPSURF(i));
8420 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8421 }
8422
8423 error->pipe[i].conf = I915_READ(PIPECONF(i));
8424 error->pipe[i].source = I915_READ(PIPESRC(i));
8425 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8426 error->pipe[i].hblank = I915_READ(HBLANK(i));
8427 error->pipe[i].hsync = I915_READ(HSYNC(i));
8428 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8429 error->pipe[i].vblank = I915_READ(VBLANK(i));
8430 error->pipe[i].vsync = I915_READ(VSYNC(i));
8431 }
8432
8433 return error;
8434 }
8435
8436 void
8437 intel_display_print_error_state(struct seq_file *m,
8438 struct drm_device *dev,
8439 struct intel_display_error_state *error)
8440 {
8441 drm_i915_private_t *dev_priv = dev->dev_private;
8442 int i;
8443
8444 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8445 for_each_pipe(i) {
8446 seq_printf(m, "Pipe [%d]:\n", i);
8447 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8448 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8449 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8450 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8451 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8452 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8453 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8454 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8455
8456 seq_printf(m, "Plane [%d]:\n", i);
8457 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8458 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8459 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8460 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8461 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8462 if (INTEL_INFO(dev)->gen >= 4) {
8463 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8464 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8465 }
8466
8467 seq_printf(m, "Cursor [%d]:\n", i);
8468 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8469 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8470 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8471 }
8472 }
8473 #endif
Linux kernel - Deliverables
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