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drm/i915: Pass in plane state when (un)pinning frame buffers
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 {
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112 }
113
114 typedef struct {
115 int min, max;
116 } intel_range_t;
117
118 typedef struct {
119 int dot_limit;
120 int p2_slow, p2_fast;
121 } intel_p2_t;
122
123 typedef struct intel_limit intel_limit_t;
124 struct intel_limit {
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
127 };
128
129 int
130 intel_pch_rawclk(struct drm_device *dev)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 }
138
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
141 {
142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
147 }
148
149 static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
160 };
161
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173 };
174
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
186 };
187
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
199 };
200
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
212 };
213
214
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
227 },
228 };
229
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
254 },
255 };
256
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
268 },
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 };
285
286 static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 /* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
304 static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
315 };
316
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 };
342
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
355 };
356
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
368 };
369
370 static const intel_limit_t intel_limits_vlv = {
371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 };
385
386 static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4800000, .max = 6480000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 };
401
402 static void vlv_clock(int refclk, intel_clock_t *clock)
403 {
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410 }
411
412 /**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 {
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
419
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
422 return true;
423
424 return false;
425 }
426
427 /**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446 int refclk)
447 {
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
463 } else
464 limit = &intel_limits_ironlake_dac;
465
466 return limit;
467 }
468
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 {
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
473
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
477 else
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
486
487 return limit;
488 }
489
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 {
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
494
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
502 else
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
513 } else {
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
518 else
519 limit = &intel_limits_i8xx_dac;
520 }
521 return limit;
522 }
523
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
526 {
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533 }
534
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 {
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538 }
539
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 {
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548 }
549
550 static void chv_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559 }
560
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 /**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
570 {
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
598
599 return true;
600 }
601
602 static bool
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->base.dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 static bool
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 struct drm_device *dev = crtc->base.dev;
669 intel_clock_t clock;
670 int err = target;
671
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 /*
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
677 */
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
689 memset(best_clock, 0, sizeof(*best_clock));
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
704 continue;
705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720 }
721
722 static bool
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
726 {
727 struct drm_device *dev = crtc->base.dev;
728 intel_clock_t clock;
729 int max_n;
730 bool found;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
733 found = false;
734
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(dev)) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817 }
818
819 static bool
820 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
821 int target, int refclk, intel_clock_t *match_clock,
822 intel_clock_t *best_clock)
823 {
824 struct drm_device *dev = crtc->base.dev;
825 intel_clock_t clock;
826 unsigned int bestppm = 1000000;
827 /* min update 19.2 MHz */
828 int max_n = min(limit->n.max, refclk / 19200);
829 bool found = false;
830
831 target *= 5; /* fast clock */
832
833 memset(best_clock, 0, sizeof(*best_clock));
834
835 /* based on hardware requirement, prefer smaller n to precision */
836 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
840 clock.p = clock.p1 * clock.p2;
841 /* based on hardware requirement, prefer bigger m1,m2 values */
842 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
843 unsigned int ppm;
844
845 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
846 refclk * clock.m1);
847
848 vlv_clock(refclk, &clock);
849
850 if (!intel_PLL_is_valid(dev, limit,
851 &clock))
852 continue;
853
854 if (!vlv_PLL_is_optimal(dev, target,
855 &clock,
856 best_clock,
857 bestppm, &ppm))
858 continue;
859
860 *best_clock = clock;
861 bestppm = ppm;
862 found = true;
863 }
864 }
865 }
866 }
867
868 return found;
869 }
870
871 static bool
872 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875 {
876 struct drm_device *dev = crtc->base.dev;
877 unsigned int best_error_ppm;
878 intel_clock_t clock;
879 uint64_t m2;
880 int found = false;
881
882 memset(best_clock, 0, sizeof(*best_clock));
883 best_error_ppm = 1000000;
884
885 /*
886 * Based on hardware doc, the n always set to 1, and m1 always
887 * set to 2. If requires to support 200Mhz refclk, we need to
888 * revisit this because n may not 1 anymore.
889 */
890 clock.n = 1, clock.m1 = 2;
891 target *= 5; /* fast clock */
892
893 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
894 for (clock.p2 = limit->p2.p2_fast;
895 clock.p2 >= limit->p2.p2_slow;
896 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
897 unsigned int error_ppm;
898
899 clock.p = clock.p1 * clock.p2;
900
901 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
902 clock.n) << 22, refclk * clock.m1);
903
904 if (m2 > INT_MAX/clock.m1)
905 continue;
906
907 clock.m2 = m2;
908
909 chv_clock(refclk, &clock);
910
911 if (!intel_PLL_is_valid(dev, limit, &clock))
912 continue;
913
914 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
915 best_error_ppm, &error_ppm))
916 continue;
917
918 *best_clock = clock;
919 best_error_ppm = error_ppm;
920 found = true;
921 }
922 }
923
924 return found;
925 }
926
927 bool intel_crtc_active(struct drm_crtc *crtc)
928 {
929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
930
931 /* Be paranoid as we can arrive here with only partial
932 * state retrieved from the hardware during setup.
933 *
934 * We can ditch the adjusted_mode.crtc_clock check as soon
935 * as Haswell has gained clock readout/fastboot support.
936 *
937 * We can ditch the crtc->primary->fb check as soon as we can
938 * properly reconstruct framebuffers.
939 *
940 * FIXME: The intel_crtc->active here should be switched to
941 * crtc->state->active once we have proper CRTC states wired up
942 * for atomic.
943 */
944 return intel_crtc->active && crtc->primary->state->fb &&
945 intel_crtc->config->base.adjusted_mode.crtc_clock;
946 }
947
948 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950 {
951 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
953
954 return intel_crtc->config->cpu_transcoder;
955 }
956
957 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
958 {
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 u32 reg = PIPEDSL(pipe);
961 u32 line1, line2;
962 u32 line_mask;
963
964 if (IS_GEN2(dev))
965 line_mask = DSL_LINEMASK_GEN2;
966 else
967 line_mask = DSL_LINEMASK_GEN3;
968
969 line1 = I915_READ(reg) & line_mask;
970 mdelay(5);
971 line2 = I915_READ(reg) & line_mask;
972
973 return line1 == line2;
974 }
975
976 /*
977 * intel_wait_for_pipe_off - wait for pipe to turn off
978 * @crtc: crtc whose pipe to wait for
979 *
980 * After disabling a pipe, we can't wait for vblank in the usual way,
981 * spinning on the vblank interrupt status bit, since we won't actually
982 * see an interrupt when the pipe is disabled.
983 *
984 * On Gen4 and above:
985 * wait for the pipe register state bit to turn off
986 *
987 * Otherwise:
988 * wait for the display line value to settle (it usually
989 * ends up stopping at the start of the next frame).
990 *
991 */
992 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
993 {
994 struct drm_device *dev = crtc->base.dev;
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
997 enum pipe pipe = crtc->pipe;
998
999 if (INTEL_INFO(dev)->gen >= 4) {
1000 int reg = PIPECONF(cpu_transcoder);
1001
1002 /* Wait for the Pipe State to go off */
1003 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1004 100))
1005 WARN(1, "pipe_off wait timed out\n");
1006 } else {
1007 /* Wait for the display line to settle */
1008 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1009 WARN(1, "pipe_off wait timed out\n");
1010 }
1011 }
1012
1013 /*
1014 * ibx_digital_port_connected - is the specified port connected?
1015 * @dev_priv: i915 private structure
1016 * @port: the port to test
1017 *
1018 * Returns true if @port is connected, false otherwise.
1019 */
1020 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021 struct intel_digital_port *port)
1022 {
1023 u32 bit;
1024
1025 if (HAS_PCH_IBX(dev_priv->dev)) {
1026 switch (port->port) {
1027 case PORT_B:
1028 bit = SDE_PORTB_HOTPLUG;
1029 break;
1030 case PORT_C:
1031 bit = SDE_PORTC_HOTPLUG;
1032 break;
1033 case PORT_D:
1034 bit = SDE_PORTD_HOTPLUG;
1035 break;
1036 default:
1037 return true;
1038 }
1039 } else {
1040 switch (port->port) {
1041 case PORT_B:
1042 bit = SDE_PORTB_HOTPLUG_CPT;
1043 break;
1044 case PORT_C:
1045 bit = SDE_PORTC_HOTPLUG_CPT;
1046 break;
1047 case PORT_D:
1048 bit = SDE_PORTD_HOTPLUG_CPT;
1049 break;
1050 default:
1051 return true;
1052 }
1053 }
1054
1055 return I915_READ(SDEISR) & bit;
1056 }
1057
1058 static const char *state_string(bool enabled)
1059 {
1060 return enabled ? "on" : "off";
1061 }
1062
1063 /* Only for pre-ILK configs */
1064 void assert_pll(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 int reg;
1068 u32 val;
1069 bool cur_state;
1070
1071 reg = DPLL(pipe);
1072 val = I915_READ(reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 I915_STATE_WARN(cur_state != state,
1075 "PLL state assertion failure (expected %s, current %s)\n",
1076 state_string(state), state_string(cur_state));
1077 }
1078
1079 /* XXX: the dsi pll is shared between MIPI DSI ports */
1080 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081 {
1082 u32 val;
1083 bool cur_state;
1084
1085 mutex_lock(&dev_priv->dpio_lock);
1086 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087 mutex_unlock(&dev_priv->dpio_lock);
1088
1089 cur_state = val & DSI_PLL_VCO_EN;
1090 I915_STATE_WARN(cur_state != state,
1091 "DSI PLL state assertion failure (expected %s, current %s)\n",
1092 state_string(state), state_string(cur_state));
1093 }
1094 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1096
1097 struct intel_shared_dpll *
1098 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1099 {
1100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1101
1102 if (crtc->config->shared_dpll < 0)
1103 return NULL;
1104
1105 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1106 }
1107
1108 /* For ILK+ */
1109 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110 struct intel_shared_dpll *pll,
1111 bool state)
1112 {
1113 bool cur_state;
1114 struct intel_dpll_hw_state hw_state;
1115
1116 if (WARN (!pll,
1117 "asserting DPLL %s with no DPLL\n", state_string(state)))
1118 return;
1119
1120 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1121 I915_STATE_WARN(cur_state != state,
1122 "%s assertion failure (expected %s, current %s)\n",
1123 pll->name, state_string(state), state_string(cur_state));
1124 }
1125
1126 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1128 {
1129 int reg;
1130 u32 val;
1131 bool cur_state;
1132 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133 pipe);
1134
1135 if (HAS_DDI(dev_priv->dev)) {
1136 /* DDI does not have a specific FDI_TX register */
1137 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1138 val = I915_READ(reg);
1139 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1140 } else {
1141 reg = FDI_TX_CTL(pipe);
1142 val = I915_READ(reg);
1143 cur_state = !!(val & FDI_TX_ENABLE);
1144 }
1145 I915_STATE_WARN(cur_state != state,
1146 "FDI TX state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148 }
1149 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1151
1152 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153 enum pipe pipe, bool state)
1154 {
1155 int reg;
1156 u32 val;
1157 bool cur_state;
1158
1159 reg = FDI_RX_CTL(pipe);
1160 val = I915_READ(reg);
1161 cur_state = !!(val & FDI_RX_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171 {
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1177 return;
1178
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (HAS_DDI(dev_priv->dev))
1181 return;
1182
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 int reg;
1192 u32 val;
1193 bool cur_state;
1194
1195 reg = FDI_RX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1198 I915_STATE_WARN(cur_state != state,
1199 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200 state_string(state), state_string(cur_state));
1201 }
1202
1203 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205 {
1206 struct drm_device *dev = dev_priv->dev;
1207 int pp_reg;
1208 u32 val;
1209 enum pipe panel_pipe = PIPE_A;
1210 bool locked = true;
1211
1212 if (WARN_ON(HAS_DDI(dev)))
1213 return;
1214
1215 if (HAS_PCH_SPLIT(dev)) {
1216 u32 port_sel;
1217
1218 pp_reg = PCH_PP_CONTROL;
1219 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1220
1221 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224 /* XXX: else fix for eDP */
1225 } else if (IS_VALLEYVIEW(dev)) {
1226 /* presumably write lock depends on pipe, not port select */
1227 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1228 panel_pipe = pipe;
1229 } else {
1230 pp_reg = PP_CONTROL;
1231 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232 panel_pipe = PIPE_B;
1233 }
1234
1235 val = I915_READ(pp_reg);
1236 if (!(val & PANEL_POWER_ON) ||
1237 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1238 locked = false;
1239
1240 I915_STATE_WARN(panel_pipe == pipe && locked,
1241 "panel assertion failure, pipe %c regs locked\n",
1242 pipe_name(pipe));
1243 }
1244
1245 static void assert_cursor(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247 {
1248 struct drm_device *dev = dev_priv->dev;
1249 bool cur_state;
1250
1251 if (IS_845G(dev) || IS_I865G(dev))
1252 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1253 else
1254 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1255
1256 I915_STATE_WARN(cur_state != state,
1257 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258 pipe_name(pipe), state_string(state), state_string(cur_state));
1259 }
1260 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1262
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, bool state)
1265 {
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1270 pipe);
1271
1272 /* if we need the pipe quirk it must be always on */
1273 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1275 state = true;
1276
1277 if (!intel_display_power_is_enabled(dev_priv,
1278 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1279 cur_state = false;
1280 } else {
1281 reg = PIPECONF(cpu_transcoder);
1282 val = I915_READ(reg);
1283 cur_state = !!(val & PIPECONF_ENABLE);
1284 }
1285
1286 I915_STATE_WARN(cur_state != state,
1287 "pipe %c assertion failure (expected %s, current %s)\n",
1288 pipe_name(pipe), state_string(state), state_string(cur_state));
1289 }
1290
1291 static void assert_plane(struct drm_i915_private *dev_priv,
1292 enum plane plane, bool state)
1293 {
1294 int reg;
1295 u32 val;
1296 bool cur_state;
1297
1298 reg = DSPCNTR(plane);
1299 val = I915_READ(reg);
1300 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1301 I915_STATE_WARN(cur_state != state,
1302 "plane %c assertion failure (expected %s, current %s)\n",
1303 plane_name(plane), state_string(state), state_string(cur_state));
1304 }
1305
1306 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1308
1309 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311 {
1312 struct drm_device *dev = dev_priv->dev;
1313 int reg, i;
1314 u32 val;
1315 int cur_pipe;
1316
1317 /* Primary planes are fixed to pipes on gen4+ */
1318 if (INTEL_INFO(dev)->gen >= 4) {
1319 reg = DSPCNTR(pipe);
1320 val = I915_READ(reg);
1321 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1322 "plane %c assertion failure, should be disabled but not\n",
1323 plane_name(pipe));
1324 return;
1325 }
1326
1327 /* Need to check both planes against the pipe */
1328 for_each_pipe(dev_priv, i) {
1329 reg = DSPCNTR(i);
1330 val = I915_READ(reg);
1331 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332 DISPPLANE_SEL_PIPE_SHIFT;
1333 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1334 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(i), pipe_name(pipe));
1336 }
1337 }
1338
1339 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341 {
1342 struct drm_device *dev = dev_priv->dev;
1343 int reg, sprite;
1344 u32 val;
1345
1346 if (INTEL_INFO(dev)->gen >= 9) {
1347 for_each_sprite(dev_priv, pipe, sprite) {
1348 val = I915_READ(PLANE_CTL(pipe, sprite));
1349 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1350 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351 sprite, pipe_name(pipe));
1352 }
1353 } else if (IS_VALLEYVIEW(dev)) {
1354 for_each_sprite(dev_priv, pipe, sprite) {
1355 reg = SPCNTR(pipe, sprite);
1356 val = I915_READ(reg);
1357 I915_STATE_WARN(val & SP_ENABLE,
1358 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1359 sprite_name(pipe, sprite), pipe_name(pipe));
1360 }
1361 } else if (INTEL_INFO(dev)->gen >= 7) {
1362 reg = SPRCTL(pipe);
1363 val = I915_READ(reg);
1364 I915_STATE_WARN(val & SPRITE_ENABLE,
1365 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1366 plane_name(pipe), pipe_name(pipe));
1367 } else if (INTEL_INFO(dev)->gen >= 5) {
1368 reg = DVSCNTR(pipe);
1369 val = I915_READ(reg);
1370 I915_STATE_WARN(val & DVS_ENABLE,
1371 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1372 plane_name(pipe), pipe_name(pipe));
1373 }
1374 }
1375
1376 static void assert_vblank_disabled(struct drm_crtc *crtc)
1377 {
1378 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1379 drm_crtc_vblank_put(crtc);
1380 }
1381
1382 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1383 {
1384 u32 val;
1385 bool enabled;
1386
1387 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1388
1389 val = I915_READ(PCH_DREF_CONTROL);
1390 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391 DREF_SUPERSPREAD_SOURCE_MASK));
1392 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1393 }
1394
1395 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397 {
1398 int reg;
1399 u32 val;
1400 bool enabled;
1401
1402 reg = PCH_TRANSCONF(pipe);
1403 val = I915_READ(reg);
1404 enabled = !!(val & TRANS_ENABLE);
1405 I915_STATE_WARN(enabled,
1406 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407 pipe_name(pipe));
1408 }
1409
1410 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 port_sel, u32 val)
1412 {
1413 if ((val & DP_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420 return false;
1421 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423 return false;
1424 } else {
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426 return false;
1427 }
1428 return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433 {
1434 if ((val & SDVO_ENABLE) == 0)
1435 return false;
1436
1437 if (HAS_PCH_CPT(dev_priv->dev)) {
1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439 return false;
1440 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442 return false;
1443 } else {
1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445 return false;
1446 }
1447 return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1452 {
1453 if ((val & LVDS_PORT_EN) == 0)
1454 return false;
1455
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461 return false;
1462 }
1463 return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1468 {
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1470 return false;
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473 return false;
1474 } else {
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476 return false;
1477 }
1478 return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, int reg, u32 port_sel)
1483 {
1484 u32 val = I915_READ(reg);
1485 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487 reg, pipe_name(pipe));
1488
1489 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1490 && (val & DP_PIPEB_SELECT),
1491 "IBX PCH dp port still using transcoder B\n");
1492 }
1493
1494 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, int reg)
1496 {
1497 u32 val = I915_READ(reg);
1498 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500 reg, pipe_name(pipe));
1501
1502 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1503 && (val & SDVO_PIPE_B_SELECT),
1504 "IBX PCH hdmi port still using transcoder B\n");
1505 }
1506
1507 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508 enum pipe pipe)
1509 {
1510 int reg;
1511 u32 val;
1512
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517 reg = PCH_ADPA;
1518 val = I915_READ(reg);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1521 pipe_name(pipe));
1522
1523 reg = PCH_LVDS;
1524 val = I915_READ(reg);
1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1527 pipe_name(pipe));
1528
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1532 }
1533
1534 static void intel_init_dpio(struct drm_device *dev)
1535 {
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 if (!IS_VALLEYVIEW(dev))
1539 return;
1540
1541 /*
1542 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543 * CHV x1 PHY (DP/HDMI D)
1544 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1545 */
1546 if (IS_CHERRYVIEW(dev)) {
1547 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1549 } else {
1550 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1551 }
1552 }
1553
1554 static void vlv_enable_pll(struct intel_crtc *crtc,
1555 const struct intel_crtc_state *pipe_config)
1556 {
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int reg = DPLL(crtc->pipe);
1560 u32 dpll = pipe_config->dpll_hw_state.dpll;
1561
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564 /* No really, not for ILK+ */
1565 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1566
1567 /* PLL is protected by panel, make sure we can write it */
1568 if (IS_MOBILE(dev_priv->dev))
1569 assert_panel_unlocked(dev_priv, crtc->pipe);
1570
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150);
1574
1575 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1577
1578 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1579 POSTING_READ(DPLL_MD(crtc->pipe));
1580
1581 /* We do this three times for luck */
1582 I915_WRITE(reg, dpll);
1583 POSTING_READ(reg);
1584 udelay(150); /* wait for warmup */
1585 I915_WRITE(reg, dpll);
1586 POSTING_READ(reg);
1587 udelay(150); /* wait for warmup */
1588 I915_WRITE(reg, dpll);
1589 POSTING_READ(reg);
1590 udelay(150); /* wait for warmup */
1591 }
1592
1593 static void chv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1595 {
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 int pipe = crtc->pipe;
1599 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1600 u32 tmp;
1601
1602 assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1605
1606 mutex_lock(&dev_priv->dpio_lock);
1607
1608 /* Enable back the 10bit clock to display controller */
1609 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 tmp |= DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1612
1613 /*
1614 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1615 */
1616 udelay(1);
1617
1618 /* Enable PLL */
1619 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1620
1621 /* Check PLL is locked */
1622 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1623 DRM_ERROR("PLL %d failed to lock\n", pipe);
1624
1625 /* not sure when this should be written */
1626 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627 POSTING_READ(DPLL_MD(pipe));
1628
1629 mutex_unlock(&dev_priv->dpio_lock);
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634 struct intel_crtc *crtc;
1635 int count = 0;
1636
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->active &&
1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641 return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 int reg = DPLL(crtc->pipe);
1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651 assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653 /* No really, not for ILK+ */
1654 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1655
1656 /* PLL is protected by panel, make sure we can write it */
1657 if (IS_MOBILE(dev) && !IS_I830(dev))
1658 assert_panel_unlocked(dev_priv, crtc->pipe);
1659
1660 /* Enable DVO 2x clock on both PLLs if necessary */
1661 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662 /*
1663 * It appears to be important that we don't enable this
1664 * for the current pipe before otherwise configuring the
1665 * PLL. No idea how this should be handled if multiple
1666 * DVO outputs are enabled simultaneosly.
1667 */
1668 dpll |= DPLL_DVO_2X_MODE;
1669 I915_WRITE(DPLL(!crtc->pipe),
1670 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1671 }
1672
1673 /* Wait for the clocks to stabilize. */
1674 POSTING_READ(reg);
1675 udelay(150);
1676
1677 if (INTEL_INFO(dev)->gen >= 4) {
1678 I915_WRITE(DPLL_MD(crtc->pipe),
1679 crtc->config->dpll_hw_state.dpll_md);
1680 } else {
1681 /* The pixel multiplier can only be updated once the
1682 * DPLL is enabled and the clocks are stable.
1683 *
1684 * So write it again.
1685 */
1686 I915_WRITE(reg, dpll);
1687 }
1688
1689 /* We do this three times for luck */
1690 I915_WRITE(reg, dpll);
1691 POSTING_READ(reg);
1692 udelay(150); /* wait for warmup */
1693 I915_WRITE(reg, dpll);
1694 POSTING_READ(reg);
1695 udelay(150); /* wait for warmup */
1696 I915_WRITE(reg, dpll);
1697 POSTING_READ(reg);
1698 udelay(150); /* wait for warmup */
1699 }
1700
1701 /**
1702 * i9xx_disable_pll - disable a PLL
1703 * @dev_priv: i915 private structure
1704 * @pipe: pipe PLL to disable
1705 *
1706 * Disable the PLL for @pipe, making sure the pipe is off first.
1707 *
1708 * Note! This is for pre-ILK only.
1709 */
1710 static void i9xx_disable_pll(struct intel_crtc *crtc)
1711 {
1712 struct drm_device *dev = crtc->base.dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 enum pipe pipe = crtc->pipe;
1715
1716 /* Disable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) &&
1718 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1719 intel_num_dvo_pipes(dev) == 1) {
1720 I915_WRITE(DPLL(PIPE_B),
1721 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722 I915_WRITE(DPLL(PIPE_A),
1723 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1724 }
1725
1726 /* Don't disable pipe or pipe PLLs if needed */
1727 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1729 return;
1730
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1733
1734 I915_WRITE(DPLL(pipe), 0);
1735 POSTING_READ(DPLL(pipe));
1736 }
1737
1738 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1739 {
1740 u32 val = 0;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
1745 /*
1746 * Leave integrated clock source and reference clock enabled for pipe B.
1747 * The latter is needed for VGA hotplug / manual detection.
1748 */
1749 if (pipe == PIPE_B)
1750 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
1753
1754 }
1755
1756 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757 {
1758 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1759 u32 val;
1760
1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
1763
1764 /* Set PLL en = 0 */
1765 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1766 if (pipe != PIPE_A)
1767 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
1770
1771 mutex_lock(&dev_priv->dpio_lock);
1772
1773 /* Disable 10bit clock to display controller */
1774 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775 val &= ~DPIO_DCLKP_EN;
1776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1777
1778 /* disable left/right clock distribution */
1779 if (pipe != PIPE_B) {
1780 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1783 } else {
1784 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1787 }
1788
1789 mutex_unlock(&dev_priv->dpio_lock);
1790 }
1791
1792 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793 struct intel_digital_port *dport)
1794 {
1795 u32 port_mask;
1796 int dpll_reg;
1797
1798 switch (dport->port) {
1799 case PORT_B:
1800 port_mask = DPLL_PORTB_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 break;
1803 case PORT_C:
1804 port_mask = DPLL_PORTC_READY_MASK;
1805 dpll_reg = DPLL(0);
1806 break;
1807 case PORT_D:
1808 port_mask = DPLL_PORTD_READY_MASK;
1809 dpll_reg = DPIO_PHY_STATUS;
1810 break;
1811 default:
1812 BUG();
1813 }
1814
1815 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1816 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1817 port_name(dport->port), I915_READ(dpll_reg));
1818 }
1819
1820 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1821 {
1822 struct drm_device *dev = crtc->base.dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1825
1826 if (WARN_ON(pll == NULL))
1827 return;
1828
1829 WARN_ON(!pll->config.crtc_mask);
1830 if (pll->active == 0) {
1831 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1832 WARN_ON(pll->on);
1833 assert_shared_dpll_disabled(dev_priv, pll);
1834
1835 pll->mode_set(dev_priv, pll);
1836 }
1837 }
1838
1839 /**
1840 * intel_enable_shared_dpll - enable PCH PLL
1841 * @dev_priv: i915 private structure
1842 * @pipe: pipe PLL to enable
1843 *
1844 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845 * drives the transcoder clock.
1846 */
1847 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1848 {
1849 struct drm_device *dev = crtc->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1852
1853 if (WARN_ON(pll == NULL))
1854 return;
1855
1856 if (WARN_ON(pll->config.crtc_mask == 0))
1857 return;
1858
1859 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1860 pll->name, pll->active, pll->on,
1861 crtc->base.base.id);
1862
1863 if (pll->active++) {
1864 WARN_ON(!pll->on);
1865 assert_shared_dpll_enabled(dev_priv, pll);
1866 return;
1867 }
1868 WARN_ON(pll->on);
1869
1870 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1871
1872 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1873 pll->enable(dev_priv, pll);
1874 pll->on = true;
1875 }
1876
1877 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1878 {
1879 struct drm_device *dev = crtc->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1882
1883 /* PCH only available on ILK+ */
1884 BUG_ON(INTEL_INFO(dev)->gen < 5);
1885 if (WARN_ON(pll == NULL))
1886 return;
1887
1888 if (WARN_ON(pll->config.crtc_mask == 0))
1889 return;
1890
1891 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892 pll->name, pll->active, pll->on,
1893 crtc->base.base.id);
1894
1895 if (WARN_ON(pll->active == 0)) {
1896 assert_shared_dpll_disabled(dev_priv, pll);
1897 return;
1898 }
1899
1900 assert_shared_dpll_enabled(dev_priv, pll);
1901 WARN_ON(!pll->on);
1902 if (--pll->active)
1903 return;
1904
1905 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1906 pll->disable(dev_priv, pll);
1907 pll->on = false;
1908
1909 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1910 }
1911
1912 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1913 enum pipe pipe)
1914 {
1915 struct drm_device *dev = dev_priv->dev;
1916 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1918 uint32_t reg, val, pipeconf_val;
1919
1920 /* PCH only available on ILK+ */
1921 BUG_ON(!HAS_PCH_SPLIT(dev));
1922
1923 /* Make sure PCH DPLL is enabled */
1924 assert_shared_dpll_enabled(dev_priv,
1925 intel_crtc_to_shared_dpll(intel_crtc));
1926
1927 /* FDI must be feeding us bits for PCH ports */
1928 assert_fdi_tx_enabled(dev_priv, pipe);
1929 assert_fdi_rx_enabled(dev_priv, pipe);
1930
1931 if (HAS_PCH_CPT(dev)) {
1932 /* Workaround: Set the timing override bit before enabling the
1933 * pch transcoder. */
1934 reg = TRANS_CHICKEN2(pipe);
1935 val = I915_READ(reg);
1936 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937 I915_WRITE(reg, val);
1938 }
1939
1940 reg = PCH_TRANSCONF(pipe);
1941 val = I915_READ(reg);
1942 pipeconf_val = I915_READ(PIPECONF(pipe));
1943
1944 if (HAS_PCH_IBX(dev_priv->dev)) {
1945 /*
1946 * make the BPC in transcoder be consistent with
1947 * that in pipeconf reg.
1948 */
1949 val &= ~PIPECONF_BPC_MASK;
1950 val |= pipeconf_val & PIPECONF_BPC_MASK;
1951 }
1952
1953 val &= ~TRANS_INTERLACE_MASK;
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1955 if (HAS_PCH_IBX(dev_priv->dev) &&
1956 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1957 val |= TRANS_LEGACY_INTERLACED_ILK;
1958 else
1959 val |= TRANS_INTERLACED;
1960 else
1961 val |= TRANS_PROGRESSIVE;
1962
1963 I915_WRITE(reg, val | TRANS_ENABLE);
1964 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1965 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1966 }
1967
1968 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum transcoder cpu_transcoder)
1970 {
1971 u32 val, pipeconf_val;
1972
1973 /* PCH only available on ILK+ */
1974 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1975
1976 /* FDI must be feeding us bits for PCH ports */
1977 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1978 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1979
1980 /* Workaround: set timing override bit. */
1981 val = I915_READ(_TRANSA_CHICKEN2);
1982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1983 I915_WRITE(_TRANSA_CHICKEN2, val);
1984
1985 val = TRANS_ENABLE;
1986 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1987
1988 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989 PIPECONF_INTERLACED_ILK)
1990 val |= TRANS_INTERLACED;
1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
1994 I915_WRITE(LPT_TRANSCONF, val);
1995 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1996 DRM_ERROR("Failed to enable PCH transcoder\n");
1997 }
1998
1999 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2000 enum pipe pipe)
2001 {
2002 struct drm_device *dev = dev_priv->dev;
2003 uint32_t reg, val;
2004
2005 /* FDI relies on the transcoder */
2006 assert_fdi_tx_disabled(dev_priv, pipe);
2007 assert_fdi_rx_disabled(dev_priv, pipe);
2008
2009 /* Ports must be off as well */
2010 assert_pch_ports_disabled(dev_priv, pipe);
2011
2012 reg = PCH_TRANSCONF(pipe);
2013 val = I915_READ(reg);
2014 val &= ~TRANS_ENABLE;
2015 I915_WRITE(reg, val);
2016 /* wait for PCH transcoder off, transcoder state */
2017 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2018 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2019
2020 if (!HAS_PCH_IBX(dev)) {
2021 /* Workaround: Clear the timing override chicken bit again. */
2022 reg = TRANS_CHICKEN2(pipe);
2023 val = I915_READ(reg);
2024 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(reg, val);
2026 }
2027 }
2028
2029 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2030 {
2031 u32 val;
2032
2033 val = I915_READ(LPT_TRANSCONF);
2034 val &= ~TRANS_ENABLE;
2035 I915_WRITE(LPT_TRANSCONF, val);
2036 /* wait for PCH transcoder off, transcoder state */
2037 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2038 DRM_ERROR("Failed to disable PCH transcoder\n");
2039
2040 /* Workaround: clear timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044 }
2045
2046 /**
2047 * intel_enable_pipe - enable a pipe, asserting requirements
2048 * @crtc: crtc responsible for the pipe
2049 *
2050 * Enable @crtc's pipe, making sure that various hardware specific requirements
2051 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2052 */
2053 static void intel_enable_pipe(struct intel_crtc *crtc)
2054 {
2055 struct drm_device *dev = crtc->base.dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 enum pipe pipe = crtc->pipe;
2058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059 pipe);
2060 enum pipe pch_transcoder;
2061 int reg;
2062 u32 val;
2063
2064 assert_planes_disabled(dev_priv, pipe);
2065 assert_cursor_disabled(dev_priv, pipe);
2066 assert_sprites_disabled(dev_priv, pipe);
2067
2068 if (HAS_PCH_LPT(dev_priv->dev))
2069 pch_transcoder = TRANSCODER_A;
2070 else
2071 pch_transcoder = pipe;
2072
2073 /*
2074 * A pipe without a PLL won't actually be able to drive bits from
2075 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2076 * need the check.
2077 */
2078 if (!HAS_PCH_SPLIT(dev_priv->dev))
2079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2080 assert_dsi_pll_enabled(dev_priv);
2081 else
2082 assert_pll_enabled(dev_priv, pipe);
2083 else {
2084 if (crtc->config->has_pch_encoder) {
2085 /* if driving the PCH, we need FDI enabled */
2086 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2087 assert_fdi_tx_pll_enabled(dev_priv,
2088 (enum pipe) cpu_transcoder);
2089 }
2090 /* FIXME: assert CPU port conditions for SNB+ */
2091 }
2092
2093 reg = PIPECONF(cpu_transcoder);
2094 val = I915_READ(reg);
2095 if (val & PIPECONF_ENABLE) {
2096 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2098 return;
2099 }
2100
2101 I915_WRITE(reg, val | PIPECONF_ENABLE);
2102 POSTING_READ(reg);
2103 }
2104
2105 /**
2106 * intel_disable_pipe - disable a pipe, asserting requirements
2107 * @crtc: crtc whose pipes is to be disabled
2108 *
2109 * Disable the pipe of @crtc, making sure that various hardware
2110 * specific requirements are met, if applicable, e.g. plane
2111 * disabled, panel fitter off, etc.
2112 *
2113 * Will wait until the pipe has shut down before returning.
2114 */
2115 static void intel_disable_pipe(struct intel_crtc *crtc)
2116 {
2117 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2118 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2119 enum pipe pipe = crtc->pipe;
2120 int reg;
2121 u32 val;
2122
2123 /*
2124 * Make sure planes won't keep trying to pump pixels to us,
2125 * or we might hang the display.
2126 */
2127 assert_planes_disabled(dev_priv, pipe);
2128 assert_cursor_disabled(dev_priv, pipe);
2129 assert_sprites_disabled(dev_priv, pipe);
2130
2131 reg = PIPECONF(cpu_transcoder);
2132 val = I915_READ(reg);
2133 if ((val & PIPECONF_ENABLE) == 0)
2134 return;
2135
2136 /*
2137 * Double wide has implications for planes
2138 * so best keep it disabled when not needed.
2139 */
2140 if (crtc->config->double_wide)
2141 val &= ~PIPECONF_DOUBLE_WIDE;
2142
2143 /* Don't disable pipe or pipe PLLs if needed */
2144 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2146 val &= ~PIPECONF_ENABLE;
2147
2148 I915_WRITE(reg, val);
2149 if ((val & PIPECONF_ENABLE) == 0)
2150 intel_wait_for_pipe_off(crtc);
2151 }
2152
2153 /*
2154 * Plane regs are double buffered, going from enabled->disabled needs a
2155 * trigger in order to latch. The display address reg provides this.
2156 */
2157 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2158 enum plane plane)
2159 {
2160 struct drm_device *dev = dev_priv->dev;
2161 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2162
2163 I915_WRITE(reg, I915_READ(reg));
2164 POSTING_READ(reg);
2165 }
2166
2167 /**
2168 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2169 * @plane: plane to be enabled
2170 * @crtc: crtc for the plane
2171 *
2172 * Enable @plane on @crtc, making sure that the pipe is running first.
2173 */
2174 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175 struct drm_crtc *crtc)
2176 {
2177 struct drm_device *dev = plane->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2182 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2183
2184 if (intel_crtc->primary_enabled)
2185 return;
2186
2187 intel_crtc->primary_enabled = true;
2188
2189 dev_priv->display.update_primary_plane(crtc, plane->fb,
2190 crtc->x, crtc->y);
2191
2192 /*
2193 * BDW signals flip done immediately if the plane
2194 * is disabled, even if the plane enable is already
2195 * armed to occur at the next vblank :(
2196 */
2197 if (IS_BROADWELL(dev))
2198 intel_wait_for_vblank(dev, intel_crtc->pipe);
2199 }
2200
2201 /**
2202 * intel_disable_primary_hw_plane - disable the primary hardware plane
2203 * @plane: plane to be disabled
2204 * @crtc: crtc for the plane
2205 *
2206 * Disable @plane on @crtc, making sure that the pipe is running first.
2207 */
2208 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209 struct drm_crtc *crtc)
2210 {
2211 struct drm_device *dev = plane->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214
2215 if (WARN_ON(!intel_crtc->active))
2216 return;
2217
2218 if (!intel_crtc->primary_enabled)
2219 return;
2220
2221 intel_crtc->primary_enabled = false;
2222
2223 dev_priv->display.update_primary_plane(crtc, plane->fb,
2224 crtc->x, crtc->y);
2225 }
2226
2227 static bool need_vtd_wa(struct drm_device *dev)
2228 {
2229 #ifdef CONFIG_INTEL_IOMMU
2230 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231 return true;
2232 #endif
2233 return false;
2234 }
2235
2236 static unsigned int
2237 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238 uint64_t fb_format_modifier)
2239 {
2240 unsigned int tile_height;
2241 uint32_t pixel_bytes;
2242
2243 switch (fb_format_modifier) {
2244 case DRM_FORMAT_MOD_NONE:
2245 tile_height = 1;
2246 break;
2247 case I915_FORMAT_MOD_X_TILED:
2248 tile_height = IS_GEN2(dev) ? 16 : 8;
2249 break;
2250 case I915_FORMAT_MOD_Y_TILED:
2251 tile_height = 32;
2252 break;
2253 case I915_FORMAT_MOD_Yf_TILED:
2254 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255 switch (pixel_bytes) {
2256 default:
2257 case 1:
2258 tile_height = 64;
2259 break;
2260 case 2:
2261 case 4:
2262 tile_height = 32;
2263 break;
2264 case 8:
2265 tile_height = 16;
2266 break;
2267 case 16:
2268 WARN_ONCE(1,
2269 "128-bit pixels are not supported for display!");
2270 tile_height = 16;
2271 break;
2272 }
2273 break;
2274 default:
2275 MISSING_CASE(fb_format_modifier);
2276 tile_height = 1;
2277 break;
2278 }
2279
2280 return tile_height;
2281 }
2282
2283 unsigned int
2284 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285 uint32_t pixel_format, uint64_t fb_format_modifier)
2286 {
2287 return ALIGN(height, intel_tile_height(dev, pixel_format,
2288 fb_format_modifier));
2289 }
2290
2291 int
2292 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2293 struct drm_framebuffer *fb,
2294 const struct drm_plane_state *plane_state,
2295 struct intel_engine_cs *pipelined)
2296 {
2297 struct drm_device *dev = fb->dev;
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2300 u32 alignment;
2301 int ret;
2302
2303 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2304
2305 switch (fb->modifier[0]) {
2306 case DRM_FORMAT_MOD_NONE:
2307 if (INTEL_INFO(dev)->gen >= 9)
2308 alignment = 256 * 1024;
2309 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2310 alignment = 128 * 1024;
2311 else if (INTEL_INFO(dev)->gen >= 4)
2312 alignment = 4 * 1024;
2313 else
2314 alignment = 64 * 1024;
2315 break;
2316 case I915_FORMAT_MOD_X_TILED:
2317 if (INTEL_INFO(dev)->gen >= 9)
2318 alignment = 256 * 1024;
2319 else {
2320 /* pin() will align the object as required by fence */
2321 alignment = 0;
2322 }
2323 break;
2324 case I915_FORMAT_MOD_Y_TILED:
2325 case I915_FORMAT_MOD_Yf_TILED:
2326 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2327 "Y tiling bo slipped through, driver bug!\n"))
2328 return -EINVAL;
2329 alignment = 1 * 1024 * 1024;
2330 break;
2331 default:
2332 MISSING_CASE(fb->modifier[0]);
2333 return -EINVAL;
2334 }
2335
2336 /* Note that the w/a also requires 64 PTE of padding following the
2337 * bo. We currently fill all unused PTE with the shadow page and so
2338 * we should always have valid PTE following the scanout preventing
2339 * the VT-d warning.
2340 */
2341 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2342 alignment = 256 * 1024;
2343
2344 /*
2345 * Global gtt pte registers are special registers which actually forward
2346 * writes to a chunk of system memory. Which means that there is no risk
2347 * that the register values disappear as soon as we call
2348 * intel_runtime_pm_put(), so it is correct to wrap only the
2349 * pin/unpin/fence and not more.
2350 */
2351 intel_runtime_pm_get(dev_priv);
2352
2353 dev_priv->mm.interruptible = false;
2354 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2355 &i915_ggtt_view_normal);
2356 if (ret)
2357 goto err_interruptible;
2358
2359 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2360 * fence, whereas 965+ only requires a fence if using
2361 * framebuffer compression. For simplicity, we always install
2362 * a fence as the cost is not that onerous.
2363 */
2364 ret = i915_gem_object_get_fence(obj);
2365 if (ret)
2366 goto err_unpin;
2367
2368 i915_gem_object_pin_fence(obj);
2369
2370 dev_priv->mm.interruptible = true;
2371 intel_runtime_pm_put(dev_priv);
2372 return 0;
2373
2374 err_unpin:
2375 i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal);
2376 err_interruptible:
2377 dev_priv->mm.interruptible = true;
2378 intel_runtime_pm_put(dev_priv);
2379 return ret;
2380 }
2381
2382 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2383 const struct drm_plane_state *plane_state)
2384 {
2385 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2386
2387 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2388
2389 i915_gem_object_unpin_fence(obj);
2390 i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal);
2391 }
2392
2393 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2394 * is assumed to be a power-of-two. */
2395 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2396 unsigned int tiling_mode,
2397 unsigned int cpp,
2398 unsigned int pitch)
2399 {
2400 if (tiling_mode != I915_TILING_NONE) {
2401 unsigned int tile_rows, tiles;
2402
2403 tile_rows = *y / 8;
2404 *y %= 8;
2405
2406 tiles = *x / (512/cpp);
2407 *x %= 512/cpp;
2408
2409 return tile_rows * pitch * 8 + tiles * 4096;
2410 } else {
2411 unsigned int offset;
2412
2413 offset = *y * pitch + *x * cpp;
2414 *y = 0;
2415 *x = (offset & 4095) / cpp;
2416 return offset & -4096;
2417 }
2418 }
2419
2420 static int i9xx_format_to_fourcc(int format)
2421 {
2422 switch (format) {
2423 case DISPPLANE_8BPP:
2424 return DRM_FORMAT_C8;
2425 case DISPPLANE_BGRX555:
2426 return DRM_FORMAT_XRGB1555;
2427 case DISPPLANE_BGRX565:
2428 return DRM_FORMAT_RGB565;
2429 default:
2430 case DISPPLANE_BGRX888:
2431 return DRM_FORMAT_XRGB8888;
2432 case DISPPLANE_RGBX888:
2433 return DRM_FORMAT_XBGR8888;
2434 case DISPPLANE_BGRX101010:
2435 return DRM_FORMAT_XRGB2101010;
2436 case DISPPLANE_RGBX101010:
2437 return DRM_FORMAT_XBGR2101010;
2438 }
2439 }
2440
2441 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2442 {
2443 switch (format) {
2444 case PLANE_CTL_FORMAT_RGB_565:
2445 return DRM_FORMAT_RGB565;
2446 default:
2447 case PLANE_CTL_FORMAT_XRGB_8888:
2448 if (rgb_order) {
2449 if (alpha)
2450 return DRM_FORMAT_ABGR8888;
2451 else
2452 return DRM_FORMAT_XBGR8888;
2453 } else {
2454 if (alpha)
2455 return DRM_FORMAT_ARGB8888;
2456 else
2457 return DRM_FORMAT_XRGB8888;
2458 }
2459 case PLANE_CTL_FORMAT_XRGB_2101010:
2460 if (rgb_order)
2461 return DRM_FORMAT_XBGR2101010;
2462 else
2463 return DRM_FORMAT_XRGB2101010;
2464 }
2465 }
2466
2467 static bool
2468 intel_alloc_plane_obj(struct intel_crtc *crtc,
2469 struct intel_initial_plane_config *plane_config)
2470 {
2471 struct drm_device *dev = crtc->base.dev;
2472 struct drm_i915_gem_object *obj = NULL;
2473 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2474 struct drm_framebuffer *fb = &plane_config->fb->base;
2475 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2476 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2477 PAGE_SIZE);
2478
2479 size_aligned -= base_aligned;
2480
2481 if (plane_config->size == 0)
2482 return false;
2483
2484 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2485 base_aligned,
2486 base_aligned,
2487 size_aligned);
2488 if (!obj)
2489 return false;
2490
2491 obj->tiling_mode = plane_config->tiling;
2492 if (obj->tiling_mode == I915_TILING_X)
2493 obj->stride = fb->pitches[0];
2494
2495 mode_cmd.pixel_format = fb->pixel_format;
2496 mode_cmd.width = fb->width;
2497 mode_cmd.height = fb->height;
2498 mode_cmd.pitches[0] = fb->pitches[0];
2499 mode_cmd.modifier[0] = fb->modifier[0];
2500 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2501
2502 mutex_lock(&dev->struct_mutex);
2503
2504 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2505 &mode_cmd, obj)) {
2506 DRM_DEBUG_KMS("intel fb init failed\n");
2507 goto out_unref_obj;
2508 }
2509
2510 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2511 mutex_unlock(&dev->struct_mutex);
2512
2513 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2514 return true;
2515
2516 out_unref_obj:
2517 drm_gem_object_unreference(&obj->base);
2518 mutex_unlock(&dev->struct_mutex);
2519 return false;
2520 }
2521
2522 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2523 static void
2524 update_state_fb(struct drm_plane *plane)
2525 {
2526 if (plane->fb == plane->state->fb)
2527 return;
2528
2529 if (plane->state->fb)
2530 drm_framebuffer_unreference(plane->state->fb);
2531 plane->state->fb = plane->fb;
2532 if (plane->state->fb)
2533 drm_framebuffer_reference(plane->state->fb);
2534 }
2535
2536 static void
2537 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2538 struct intel_initial_plane_config *plane_config)
2539 {
2540 struct drm_device *dev = intel_crtc->base.dev;
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 struct drm_crtc *c;
2543 struct intel_crtc *i;
2544 struct drm_i915_gem_object *obj;
2545
2546 if (!plane_config->fb)
2547 return;
2548
2549 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2550 struct drm_plane *primary = intel_crtc->base.primary;
2551
2552 primary->fb = &plane_config->fb->base;
2553 primary->state->crtc = &intel_crtc->base;
2554 update_state_fb(primary);
2555
2556 return;
2557 }
2558
2559 kfree(plane_config->fb);
2560
2561 /*
2562 * Failed to alloc the obj, check to see if we should share
2563 * an fb with another CRTC instead
2564 */
2565 for_each_crtc(dev, c) {
2566 i = to_intel_crtc(c);
2567
2568 if (c == &intel_crtc->base)
2569 continue;
2570
2571 if (!i->active)
2572 continue;
2573
2574 obj = intel_fb_obj(c->primary->fb);
2575 if (obj == NULL)
2576 continue;
2577
2578 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2579 struct drm_plane *primary = intel_crtc->base.primary;
2580
2581 if (obj->tiling_mode != I915_TILING_NONE)
2582 dev_priv->preserve_bios_swizzle = true;
2583
2584 drm_framebuffer_reference(c->primary->fb);
2585 primary->fb = c->primary->fb;
2586 primary->state->crtc = &intel_crtc->base;
2587 update_state_fb(intel_crtc->base.primary);
2588 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2589 break;
2590 }
2591 }
2592 }
2593
2594 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2595 struct drm_framebuffer *fb,
2596 int x, int y)
2597 {
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 struct drm_i915_gem_object *obj;
2602 int plane = intel_crtc->plane;
2603 unsigned long linear_offset;
2604 u32 dspcntr;
2605 u32 reg = DSPCNTR(plane);
2606 int pixel_size;
2607
2608 if (!intel_crtc->primary_enabled) {
2609 I915_WRITE(reg, 0);
2610 if (INTEL_INFO(dev)->gen >= 4)
2611 I915_WRITE(DSPSURF(plane), 0);
2612 else
2613 I915_WRITE(DSPADDR(plane), 0);
2614 POSTING_READ(reg);
2615 return;
2616 }
2617
2618 obj = intel_fb_obj(fb);
2619 if (WARN_ON(obj == NULL))
2620 return;
2621
2622 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2623
2624 dspcntr = DISPPLANE_GAMMA_ENABLE;
2625
2626 dspcntr |= DISPLAY_PLANE_ENABLE;
2627
2628 if (INTEL_INFO(dev)->gen < 4) {
2629 if (intel_crtc->pipe == PIPE_B)
2630 dspcntr |= DISPPLANE_SEL_PIPE_B;
2631
2632 /* pipesrc and dspsize control the size that is scaled from,
2633 * which should always be the user's requested size.
2634 */
2635 I915_WRITE(DSPSIZE(plane),
2636 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2637 (intel_crtc->config->pipe_src_w - 1));
2638 I915_WRITE(DSPPOS(plane), 0);
2639 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2640 I915_WRITE(PRIMSIZE(plane),
2641 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2642 (intel_crtc->config->pipe_src_w - 1));
2643 I915_WRITE(PRIMPOS(plane), 0);
2644 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2645 }
2646
2647 switch (fb->pixel_format) {
2648 case DRM_FORMAT_C8:
2649 dspcntr |= DISPPLANE_8BPP;
2650 break;
2651 case DRM_FORMAT_XRGB1555:
2652 case DRM_FORMAT_ARGB1555:
2653 dspcntr |= DISPPLANE_BGRX555;
2654 break;
2655 case DRM_FORMAT_RGB565:
2656 dspcntr |= DISPPLANE_BGRX565;
2657 break;
2658 case DRM_FORMAT_XRGB8888:
2659 case DRM_FORMAT_ARGB8888:
2660 dspcntr |= DISPPLANE_BGRX888;
2661 break;
2662 case DRM_FORMAT_XBGR8888:
2663 case DRM_FORMAT_ABGR8888:
2664 dspcntr |= DISPPLANE_RGBX888;
2665 break;
2666 case DRM_FORMAT_XRGB2101010:
2667 case DRM_FORMAT_ARGB2101010:
2668 dspcntr |= DISPPLANE_BGRX101010;
2669 break;
2670 case DRM_FORMAT_XBGR2101010:
2671 case DRM_FORMAT_ABGR2101010:
2672 dspcntr |= DISPPLANE_RGBX101010;
2673 break;
2674 default:
2675 BUG();
2676 }
2677
2678 if (INTEL_INFO(dev)->gen >= 4 &&
2679 obj->tiling_mode != I915_TILING_NONE)
2680 dspcntr |= DISPPLANE_TILED;
2681
2682 if (IS_G4X(dev))
2683 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2684
2685 linear_offset = y * fb->pitches[0] + x * pixel_size;
2686
2687 if (INTEL_INFO(dev)->gen >= 4) {
2688 intel_crtc->dspaddr_offset =
2689 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2690 pixel_size,
2691 fb->pitches[0]);
2692 linear_offset -= intel_crtc->dspaddr_offset;
2693 } else {
2694 intel_crtc->dspaddr_offset = linear_offset;
2695 }
2696
2697 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2698 dspcntr |= DISPPLANE_ROTATE_180;
2699
2700 x += (intel_crtc->config->pipe_src_w - 1);
2701 y += (intel_crtc->config->pipe_src_h - 1);
2702
2703 /* Finding the last pixel of the last line of the display
2704 data and adding to linear_offset*/
2705 linear_offset +=
2706 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2707 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2708 }
2709
2710 I915_WRITE(reg, dspcntr);
2711
2712 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2713 if (INTEL_INFO(dev)->gen >= 4) {
2714 I915_WRITE(DSPSURF(plane),
2715 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2716 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2717 I915_WRITE(DSPLINOFF(plane), linear_offset);
2718 } else
2719 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2720 POSTING_READ(reg);
2721 }
2722
2723 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2724 struct drm_framebuffer *fb,
2725 int x, int y)
2726 {
2727 struct drm_device *dev = crtc->dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2730 struct drm_i915_gem_object *obj;
2731 int plane = intel_crtc->plane;
2732 unsigned long linear_offset;
2733 u32 dspcntr;
2734 u32 reg = DSPCNTR(plane);
2735 int pixel_size;
2736
2737 if (!intel_crtc->primary_enabled) {
2738 I915_WRITE(reg, 0);
2739 I915_WRITE(DSPSURF(plane), 0);
2740 POSTING_READ(reg);
2741 return;
2742 }
2743
2744 obj = intel_fb_obj(fb);
2745 if (WARN_ON(obj == NULL))
2746 return;
2747
2748 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2749
2750 dspcntr = DISPPLANE_GAMMA_ENABLE;
2751
2752 dspcntr |= DISPLAY_PLANE_ENABLE;
2753
2754 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2755 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2756
2757 switch (fb->pixel_format) {
2758 case DRM_FORMAT_C8:
2759 dspcntr |= DISPPLANE_8BPP;
2760 break;
2761 case DRM_FORMAT_RGB565:
2762 dspcntr |= DISPPLANE_BGRX565;
2763 break;
2764 case DRM_FORMAT_XRGB8888:
2765 case DRM_FORMAT_ARGB8888:
2766 dspcntr |= DISPPLANE_BGRX888;
2767 break;
2768 case DRM_FORMAT_XBGR8888:
2769 case DRM_FORMAT_ABGR8888:
2770 dspcntr |= DISPPLANE_RGBX888;
2771 break;
2772 case DRM_FORMAT_XRGB2101010:
2773 case DRM_FORMAT_ARGB2101010:
2774 dspcntr |= DISPPLANE_BGRX101010;
2775 break;
2776 case DRM_FORMAT_XBGR2101010:
2777 case DRM_FORMAT_ABGR2101010:
2778 dspcntr |= DISPPLANE_RGBX101010;
2779 break;
2780 default:
2781 BUG();
2782 }
2783
2784 if (obj->tiling_mode != I915_TILING_NONE)
2785 dspcntr |= DISPPLANE_TILED;
2786
2787 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2788 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2789
2790 linear_offset = y * fb->pitches[0] + x * pixel_size;
2791 intel_crtc->dspaddr_offset =
2792 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2793 pixel_size,
2794 fb->pitches[0]);
2795 linear_offset -= intel_crtc->dspaddr_offset;
2796 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2797 dspcntr |= DISPPLANE_ROTATE_180;
2798
2799 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2800 x += (intel_crtc->config->pipe_src_w - 1);
2801 y += (intel_crtc->config->pipe_src_h - 1);
2802
2803 /* Finding the last pixel of the last line of the display
2804 data and adding to linear_offset*/
2805 linear_offset +=
2806 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2807 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2808 }
2809 }
2810
2811 I915_WRITE(reg, dspcntr);
2812
2813 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2814 I915_WRITE(DSPSURF(plane),
2815 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2816 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2817 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2818 } else {
2819 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2820 I915_WRITE(DSPLINOFF(plane), linear_offset);
2821 }
2822 POSTING_READ(reg);
2823 }
2824
2825 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2826 uint32_t pixel_format)
2827 {
2828 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2829
2830 /*
2831 * The stride is either expressed as a multiple of 64 bytes
2832 * chunks for linear buffers or in number of tiles for tiled
2833 * buffers.
2834 */
2835 switch (fb_modifier) {
2836 case DRM_FORMAT_MOD_NONE:
2837 return 64;
2838 case I915_FORMAT_MOD_X_TILED:
2839 if (INTEL_INFO(dev)->gen == 2)
2840 return 128;
2841 return 512;
2842 case I915_FORMAT_MOD_Y_TILED:
2843 /* No need to check for old gens and Y tiling since this is
2844 * about the display engine and those will be blocked before
2845 * we get here.
2846 */
2847 return 128;
2848 case I915_FORMAT_MOD_Yf_TILED:
2849 if (bits_per_pixel == 8)
2850 return 64;
2851 else
2852 return 128;
2853 default:
2854 MISSING_CASE(fb_modifier);
2855 return 64;
2856 }
2857 }
2858
2859 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2860 struct drm_framebuffer *fb,
2861 int x, int y)
2862 {
2863 struct drm_device *dev = crtc->dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2866 struct drm_i915_gem_object *obj;
2867 int pipe = intel_crtc->pipe;
2868 u32 plane_ctl, stride_div;
2869
2870 if (!intel_crtc->primary_enabled) {
2871 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2872 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2873 POSTING_READ(PLANE_CTL(pipe, 0));
2874 return;
2875 }
2876
2877 plane_ctl = PLANE_CTL_ENABLE |
2878 PLANE_CTL_PIPE_GAMMA_ENABLE |
2879 PLANE_CTL_PIPE_CSC_ENABLE;
2880
2881 switch (fb->pixel_format) {
2882 case DRM_FORMAT_RGB565:
2883 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2884 break;
2885 case DRM_FORMAT_XRGB8888:
2886 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2887 break;
2888 case DRM_FORMAT_ARGB8888:
2889 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2890 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2891 break;
2892 case DRM_FORMAT_XBGR8888:
2893 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2894 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2895 break;
2896 case DRM_FORMAT_ABGR8888:
2897 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2898 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2899 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2900 break;
2901 case DRM_FORMAT_XRGB2101010:
2902 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2903 break;
2904 case DRM_FORMAT_XBGR2101010:
2905 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2906 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2907 break;
2908 default:
2909 BUG();
2910 }
2911
2912 switch (fb->modifier[0]) {
2913 case DRM_FORMAT_MOD_NONE:
2914 break;
2915 case I915_FORMAT_MOD_X_TILED:
2916 plane_ctl |= PLANE_CTL_TILED_X;
2917 break;
2918 case I915_FORMAT_MOD_Y_TILED:
2919 plane_ctl |= PLANE_CTL_TILED_Y;
2920 break;
2921 case I915_FORMAT_MOD_Yf_TILED:
2922 plane_ctl |= PLANE_CTL_TILED_YF;
2923 break;
2924 default:
2925 MISSING_CASE(fb->modifier[0]);
2926 }
2927
2928 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2929 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2930 plane_ctl |= PLANE_CTL_ROTATE_180;
2931
2932 obj = intel_fb_obj(fb);
2933 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2934 fb->pixel_format);
2935
2936 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2937
2938 I915_WRITE(PLANE_POS(pipe, 0), 0);
2939 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2940 I915_WRITE(PLANE_SIZE(pipe, 0),
2941 (intel_crtc->config->pipe_src_h - 1) << 16 |
2942 (intel_crtc->config->pipe_src_w - 1));
2943 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2944 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2945
2946 POSTING_READ(PLANE_SURF(pipe, 0));
2947 }
2948
2949 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2950 static int
2951 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2952 int x, int y, enum mode_set_atomic state)
2953 {
2954 struct drm_device *dev = crtc->dev;
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956
2957 if (dev_priv->display.disable_fbc)
2958 dev_priv->display.disable_fbc(dev);
2959
2960 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2961
2962 return 0;
2963 }
2964
2965 static void intel_complete_page_flips(struct drm_device *dev)
2966 {
2967 struct drm_crtc *crtc;
2968
2969 for_each_crtc(dev, crtc) {
2970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971 enum plane plane = intel_crtc->plane;
2972
2973 intel_prepare_page_flip(dev, plane);
2974 intel_finish_page_flip_plane(dev, plane);
2975 }
2976 }
2977
2978 static void intel_update_primary_planes(struct drm_device *dev)
2979 {
2980 struct drm_i915_private *dev_priv = dev->dev_private;
2981 struct drm_crtc *crtc;
2982
2983 for_each_crtc(dev, crtc) {
2984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2985
2986 drm_modeset_lock(&crtc->mutex, NULL);
2987 /*
2988 * FIXME: Once we have proper support for primary planes (and
2989 * disabling them without disabling the entire crtc) allow again
2990 * a NULL crtc->primary->fb.
2991 */
2992 if (intel_crtc->active && crtc->primary->fb)
2993 dev_priv->display.update_primary_plane(crtc,
2994 crtc->primary->fb,
2995 crtc->x,
2996 crtc->y);
2997 drm_modeset_unlock(&crtc->mutex);
2998 }
2999 }
3000
3001 void intel_prepare_reset(struct drm_device *dev)
3002 {
3003 struct drm_i915_private *dev_priv = to_i915(dev);
3004 struct intel_crtc *crtc;
3005
3006 /* no reset support for gen2 */
3007 if (IS_GEN2(dev))
3008 return;
3009
3010 /* reset doesn't touch the display */
3011 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3012 return;
3013
3014 drm_modeset_lock_all(dev);
3015
3016 /*
3017 * Disabling the crtcs gracefully seems nicer. Also the
3018 * g33 docs say we should at least disable all the planes.
3019 */
3020 for_each_intel_crtc(dev, crtc) {
3021 if (crtc->active)
3022 dev_priv->display.crtc_disable(&crtc->base);
3023 }
3024 }
3025
3026 void intel_finish_reset(struct drm_device *dev)
3027 {
3028 struct drm_i915_private *dev_priv = to_i915(dev);
3029
3030 /*
3031 * Flips in the rings will be nuked by the reset,
3032 * so complete all pending flips so that user space
3033 * will get its events and not get stuck.
3034 */
3035 intel_complete_page_flips(dev);
3036
3037 /* no reset support for gen2 */
3038 if (IS_GEN2(dev))
3039 return;
3040
3041 /* reset doesn't touch the display */
3042 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3043 /*
3044 * Flips in the rings have been nuked by the reset,
3045 * so update the base address of all primary
3046 * planes to the the last fb to make sure we're
3047 * showing the correct fb after a reset.
3048 */
3049 intel_update_primary_planes(dev);
3050 return;
3051 }
3052
3053 /*
3054 * The display has been reset as well,
3055 * so need a full re-initialization.
3056 */
3057 intel_runtime_pm_disable_interrupts(dev_priv);
3058 intel_runtime_pm_enable_interrupts(dev_priv);
3059
3060 intel_modeset_init_hw(dev);
3061
3062 spin_lock_irq(&dev_priv->irq_lock);
3063 if (dev_priv->display.hpd_irq_setup)
3064 dev_priv->display.hpd_irq_setup(dev);
3065 spin_unlock_irq(&dev_priv->irq_lock);
3066
3067 intel_modeset_setup_hw_state(dev, true);
3068
3069 intel_hpd_init(dev_priv);
3070
3071 drm_modeset_unlock_all(dev);
3072 }
3073
3074 static int
3075 intel_finish_fb(struct drm_framebuffer *old_fb)
3076 {
3077 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3078 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3079 bool was_interruptible = dev_priv->mm.interruptible;
3080 int ret;
3081
3082 /* Big Hammer, we also need to ensure that any pending
3083 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3084 * current scanout is retired before unpinning the old
3085 * framebuffer.
3086 *
3087 * This should only fail upon a hung GPU, in which case we
3088 * can safely continue.
3089 */
3090 dev_priv->mm.interruptible = false;
3091 ret = i915_gem_object_finish_gpu(obj);
3092 dev_priv->mm.interruptible = was_interruptible;
3093
3094 return ret;
3095 }
3096
3097 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3098 {
3099 struct drm_device *dev = crtc->dev;
3100 struct drm_i915_private *dev_priv = dev->dev_private;
3101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102 bool pending;
3103
3104 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3105 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3106 return false;
3107
3108 spin_lock_irq(&dev->event_lock);
3109 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3110 spin_unlock_irq(&dev->event_lock);
3111
3112 return pending;
3113 }
3114
3115 static void intel_update_pipe_size(struct intel_crtc *crtc)
3116 {
3117 struct drm_device *dev = crtc->base.dev;
3118 struct drm_i915_private *dev_priv = dev->dev_private;
3119 const struct drm_display_mode *adjusted_mode;
3120
3121 if (!i915.fastboot)
3122 return;
3123
3124 /*
3125 * Update pipe size and adjust fitter if needed: the reason for this is
3126 * that in compute_mode_changes we check the native mode (not the pfit
3127 * mode) to see if we can flip rather than do a full mode set. In the
3128 * fastboot case, we'll flip, but if we don't update the pipesrc and
3129 * pfit state, we'll end up with a big fb scanned out into the wrong
3130 * sized surface.
3131 *
3132 * To fix this properly, we need to hoist the checks up into
3133 * compute_mode_changes (or above), check the actual pfit state and
3134 * whether the platform allows pfit disable with pipe active, and only
3135 * then update the pipesrc and pfit state, even on the flip path.
3136 */
3137
3138 adjusted_mode = &crtc->config->base.adjusted_mode;
3139
3140 I915_WRITE(PIPESRC(crtc->pipe),
3141 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3142 (adjusted_mode->crtc_vdisplay - 1));
3143 if (!crtc->config->pch_pfit.enabled &&
3144 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3145 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3146 I915_WRITE(PF_CTL(crtc->pipe), 0);
3147 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3148 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3149 }
3150 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3151 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3152 }
3153
3154 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3155 {
3156 struct drm_device *dev = crtc->dev;
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159 int pipe = intel_crtc->pipe;
3160 u32 reg, temp;
3161
3162 /* enable normal train */
3163 reg = FDI_TX_CTL(pipe);
3164 temp = I915_READ(reg);
3165 if (IS_IVYBRIDGE(dev)) {
3166 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3167 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3168 } else {
3169 temp &= ~FDI_LINK_TRAIN_NONE;
3170 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3171 }
3172 I915_WRITE(reg, temp);
3173
3174 reg = FDI_RX_CTL(pipe);
3175 temp = I915_READ(reg);
3176 if (HAS_PCH_CPT(dev)) {
3177 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3178 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3179 } else {
3180 temp &= ~FDI_LINK_TRAIN_NONE;
3181 temp |= FDI_LINK_TRAIN_NONE;
3182 }
3183 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3184
3185 /* wait one idle pattern time */
3186 POSTING_READ(reg);
3187 udelay(1000);
3188
3189 /* IVB wants error correction enabled */
3190 if (IS_IVYBRIDGE(dev))
3191 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3192 FDI_FE_ERRC_ENABLE);
3193 }
3194
3195 /* The FDI link training functions for ILK/Ibexpeak. */
3196 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3197 {
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201 int pipe = intel_crtc->pipe;
3202 u32 reg, temp, tries;
3203
3204 /* FDI needs bits from pipe first */
3205 assert_pipe_enabled(dev_priv, pipe);
3206
3207 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3208 for train result */
3209 reg = FDI_RX_IMR(pipe);
3210 temp = I915_READ(reg);
3211 temp &= ~FDI_RX_SYMBOL_LOCK;
3212 temp &= ~FDI_RX_BIT_LOCK;
3213 I915_WRITE(reg, temp);
3214 I915_READ(reg);
3215 udelay(150);
3216
3217 /* enable CPU FDI TX and PCH FDI RX */
3218 reg = FDI_TX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3221 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3222 temp &= ~FDI_LINK_TRAIN_NONE;
3223 temp |= FDI_LINK_TRAIN_PATTERN_1;
3224 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3225
3226 reg = FDI_RX_CTL(pipe);
3227 temp = I915_READ(reg);
3228 temp &= ~FDI_LINK_TRAIN_NONE;
3229 temp |= FDI_LINK_TRAIN_PATTERN_1;
3230 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3231
3232 POSTING_READ(reg);
3233 udelay(150);
3234
3235 /* Ironlake workaround, enable clock pointer after FDI enable*/
3236 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3237 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3238 FDI_RX_PHASE_SYNC_POINTER_EN);
3239
3240 reg = FDI_RX_IIR(pipe);
3241 for (tries = 0; tries < 5; tries++) {
3242 temp = I915_READ(reg);
3243 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3244
3245 if ((temp & FDI_RX_BIT_LOCK)) {
3246 DRM_DEBUG_KMS("FDI train 1 done.\n");
3247 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3248 break;
3249 }
3250 }
3251 if (tries == 5)
3252 DRM_ERROR("FDI train 1 fail!\n");
3253
3254 /* Train 2 */
3255 reg = FDI_TX_CTL(pipe);
3256 temp = I915_READ(reg);
3257 temp &= ~FDI_LINK_TRAIN_NONE;
3258 temp |= FDI_LINK_TRAIN_PATTERN_2;
3259 I915_WRITE(reg, temp);
3260
3261 reg = FDI_RX_CTL(pipe);
3262 temp = I915_READ(reg);
3263 temp &= ~FDI_LINK_TRAIN_NONE;
3264 temp |= FDI_LINK_TRAIN_PATTERN_2;
3265 I915_WRITE(reg, temp);
3266
3267 POSTING_READ(reg);
3268 udelay(150);
3269
3270 reg = FDI_RX_IIR(pipe);
3271 for (tries = 0; tries < 5; tries++) {
3272 temp = I915_READ(reg);
3273 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3274
3275 if (temp & FDI_RX_SYMBOL_LOCK) {
3276 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3277 DRM_DEBUG_KMS("FDI train 2 done.\n");
3278 break;
3279 }
3280 }
3281 if (tries == 5)
3282 DRM_ERROR("FDI train 2 fail!\n");
3283
3284 DRM_DEBUG_KMS("FDI train done\n");
3285
3286 }
3287
3288 static const int snb_b_fdi_train_param[] = {
3289 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3290 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3291 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3292 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3293 };
3294
3295 /* The FDI link training functions for SNB/Cougarpoint. */
3296 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3297 {
3298 struct drm_device *dev = crtc->dev;
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3301 int pipe = intel_crtc->pipe;
3302 u32 reg, temp, i, retry;
3303
3304 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3305 for train result */
3306 reg = FDI_RX_IMR(pipe);
3307 temp = I915_READ(reg);
3308 temp &= ~FDI_RX_SYMBOL_LOCK;
3309 temp &= ~FDI_RX_BIT_LOCK;
3310 I915_WRITE(reg, temp);
3311
3312 POSTING_READ(reg);
3313 udelay(150);
3314
3315 /* enable CPU FDI TX and PCH FDI RX */
3316 reg = FDI_TX_CTL(pipe);
3317 temp = I915_READ(reg);
3318 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3319 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3320 temp &= ~FDI_LINK_TRAIN_NONE;
3321 temp |= FDI_LINK_TRAIN_PATTERN_1;
3322 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3323 /* SNB-B */
3324 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3325 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3326
3327 I915_WRITE(FDI_RX_MISC(pipe),
3328 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3329
3330 reg = FDI_RX_CTL(pipe);
3331 temp = I915_READ(reg);
3332 if (HAS_PCH_CPT(dev)) {
3333 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3334 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3335 } else {
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_PATTERN_1;
3338 }
3339 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3340
3341 POSTING_READ(reg);
3342 udelay(150);
3343
3344 for (i = 0; i < 4; i++) {
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3348 temp |= snb_b_fdi_train_param[i];
3349 I915_WRITE(reg, temp);
3350
3351 POSTING_READ(reg);
3352 udelay(500);
3353
3354 for (retry = 0; retry < 5; retry++) {
3355 reg = FDI_RX_IIR(pipe);
3356 temp = I915_READ(reg);
3357 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3358 if (temp & FDI_RX_BIT_LOCK) {
3359 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3360 DRM_DEBUG_KMS("FDI train 1 done.\n");
3361 break;
3362 }
3363 udelay(50);
3364 }
3365 if (retry < 5)
3366 break;
3367 }
3368 if (i == 4)
3369 DRM_ERROR("FDI train 1 fail!\n");
3370
3371 /* Train 2 */
3372 reg = FDI_TX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 temp &= ~FDI_LINK_TRAIN_NONE;
3375 temp |= FDI_LINK_TRAIN_PATTERN_2;
3376 if (IS_GEN6(dev)) {
3377 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3378 /* SNB-B */
3379 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3380 }
3381 I915_WRITE(reg, temp);
3382
3383 reg = FDI_RX_CTL(pipe);
3384 temp = I915_READ(reg);
3385 if (HAS_PCH_CPT(dev)) {
3386 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3387 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3388 } else {
3389 temp &= ~FDI_LINK_TRAIN_NONE;
3390 temp |= FDI_LINK_TRAIN_PATTERN_2;
3391 }
3392 I915_WRITE(reg, temp);
3393
3394 POSTING_READ(reg);
3395 udelay(150);
3396
3397 for (i = 0; i < 4; i++) {
3398 reg = FDI_TX_CTL(pipe);
3399 temp = I915_READ(reg);
3400 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3401 temp |= snb_b_fdi_train_param[i];
3402 I915_WRITE(reg, temp);
3403
3404 POSTING_READ(reg);
3405 udelay(500);
3406
3407 for (retry = 0; retry < 5; retry++) {
3408 reg = FDI_RX_IIR(pipe);
3409 temp = I915_READ(reg);
3410 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3411 if (temp & FDI_RX_SYMBOL_LOCK) {
3412 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3413 DRM_DEBUG_KMS("FDI train 2 done.\n");
3414 break;
3415 }
3416 udelay(50);
3417 }
3418 if (retry < 5)
3419 break;
3420 }
3421 if (i == 4)
3422 DRM_ERROR("FDI train 2 fail!\n");
3423
3424 DRM_DEBUG_KMS("FDI train done.\n");
3425 }
3426
3427 /* Manual link training for Ivy Bridge A0 parts */
3428 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3429 {
3430 struct drm_device *dev = crtc->dev;
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433 int pipe = intel_crtc->pipe;
3434 u32 reg, temp, i, j;
3435
3436 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3437 for train result */
3438 reg = FDI_RX_IMR(pipe);
3439 temp = I915_READ(reg);
3440 temp &= ~FDI_RX_SYMBOL_LOCK;
3441 temp &= ~FDI_RX_BIT_LOCK;
3442 I915_WRITE(reg, temp);
3443
3444 POSTING_READ(reg);
3445 udelay(150);
3446
3447 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3448 I915_READ(FDI_RX_IIR(pipe)));
3449
3450 /* Try each vswing and preemphasis setting twice before moving on */
3451 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3452 /* disable first in case we need to retry */
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3456 temp &= ~FDI_TX_ENABLE;
3457 I915_WRITE(reg, temp);
3458
3459 reg = FDI_RX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 temp &= ~FDI_LINK_TRAIN_AUTO;
3462 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3463 temp &= ~FDI_RX_ENABLE;
3464 I915_WRITE(reg, temp);
3465
3466 /* enable CPU FDI TX and PCH FDI RX */
3467 reg = FDI_TX_CTL(pipe);
3468 temp = I915_READ(reg);
3469 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3470 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3471 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3473 temp |= snb_b_fdi_train_param[j/2];
3474 temp |= FDI_COMPOSITE_SYNC;
3475 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3476
3477 I915_WRITE(FDI_RX_MISC(pipe),
3478 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3479
3480 reg = FDI_RX_CTL(pipe);
3481 temp = I915_READ(reg);
3482 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3483 temp |= FDI_COMPOSITE_SYNC;
3484 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3485
3486 POSTING_READ(reg);
3487 udelay(1); /* should be 0.5us */
3488
3489 for (i = 0; i < 4; i++) {
3490 reg = FDI_RX_IIR(pipe);
3491 temp = I915_READ(reg);
3492 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3493
3494 if (temp & FDI_RX_BIT_LOCK ||
3495 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3496 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3497 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3498 i);
3499 break;
3500 }
3501 udelay(1); /* should be 0.5us */
3502 }
3503 if (i == 4) {
3504 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3505 continue;
3506 }
3507
3508 /* Train 2 */
3509 reg = FDI_TX_CTL(pipe);
3510 temp = I915_READ(reg);
3511 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3512 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3513 I915_WRITE(reg, temp);
3514
3515 reg = FDI_RX_CTL(pipe);
3516 temp = I915_READ(reg);
3517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3519 I915_WRITE(reg, temp);
3520
3521 POSTING_READ(reg);
3522 udelay(2); /* should be 1.5us */
3523
3524 for (i = 0; i < 4; i++) {
3525 reg = FDI_RX_IIR(pipe);
3526 temp = I915_READ(reg);
3527 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3528
3529 if (temp & FDI_RX_SYMBOL_LOCK ||
3530 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3531 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3532 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3533 i);
3534 goto train_done;
3535 }
3536 udelay(2); /* should be 1.5us */
3537 }
3538 if (i == 4)
3539 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3540 }
3541
3542 train_done:
3543 DRM_DEBUG_KMS("FDI train done.\n");
3544 }
3545
3546 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3547 {
3548 struct drm_device *dev = intel_crtc->base.dev;
3549 struct drm_i915_private *dev_priv = dev->dev_private;
3550 int pipe = intel_crtc->pipe;
3551 u32 reg, temp;
3552
3553
3554 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3555 reg = FDI_RX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3558 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3559 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3560 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3561
3562 POSTING_READ(reg);
3563 udelay(200);
3564
3565 /* Switch from Rawclk to PCDclk */
3566 temp = I915_READ(reg);
3567 I915_WRITE(reg, temp | FDI_PCDCLK);
3568
3569 POSTING_READ(reg);
3570 udelay(200);
3571
3572 /* Enable CPU FDI TX PLL, always on for Ironlake */
3573 reg = FDI_TX_CTL(pipe);
3574 temp = I915_READ(reg);
3575 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3576 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3577
3578 POSTING_READ(reg);
3579 udelay(100);
3580 }
3581 }
3582
3583 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3584 {
3585 struct drm_device *dev = intel_crtc->base.dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 int pipe = intel_crtc->pipe;
3588 u32 reg, temp;
3589
3590 /* Switch from PCDclk to Rawclk */
3591 reg = FDI_RX_CTL(pipe);
3592 temp = I915_READ(reg);
3593 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3594
3595 /* Disable CPU FDI TX PLL */
3596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3599
3600 POSTING_READ(reg);
3601 udelay(100);
3602
3603 reg = FDI_RX_CTL(pipe);
3604 temp = I915_READ(reg);
3605 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3606
3607 /* Wait for the clocks to turn off. */
3608 POSTING_READ(reg);
3609 udelay(100);
3610 }
3611
3612 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3613 {
3614 struct drm_device *dev = crtc->dev;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 int pipe = intel_crtc->pipe;
3618 u32 reg, temp;
3619
3620 /* disable CPU FDI tx and PCH FDI rx */
3621 reg = FDI_TX_CTL(pipe);
3622 temp = I915_READ(reg);
3623 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3624 POSTING_READ(reg);
3625
3626 reg = FDI_RX_CTL(pipe);
3627 temp = I915_READ(reg);
3628 temp &= ~(0x7 << 16);
3629 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3630 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3631
3632 POSTING_READ(reg);
3633 udelay(100);
3634
3635 /* Ironlake workaround, disable clock pointer after downing FDI */
3636 if (HAS_PCH_IBX(dev))
3637 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3638
3639 /* still set train pattern 1 */
3640 reg = FDI_TX_CTL(pipe);
3641 temp = I915_READ(reg);
3642 temp &= ~FDI_LINK_TRAIN_NONE;
3643 temp |= FDI_LINK_TRAIN_PATTERN_1;
3644 I915_WRITE(reg, temp);
3645
3646 reg = FDI_RX_CTL(pipe);
3647 temp = I915_READ(reg);
3648 if (HAS_PCH_CPT(dev)) {
3649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3650 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3651 } else {
3652 temp &= ~FDI_LINK_TRAIN_NONE;
3653 temp |= FDI_LINK_TRAIN_PATTERN_1;
3654 }
3655 /* BPC in FDI rx is consistent with that in PIPECONF */
3656 temp &= ~(0x07 << 16);
3657 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3658 I915_WRITE(reg, temp);
3659
3660 POSTING_READ(reg);
3661 udelay(100);
3662 }
3663
3664 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3665 {
3666 struct intel_crtc *crtc;
3667
3668 /* Note that we don't need to be called with mode_config.lock here
3669 * as our list of CRTC objects is static for the lifetime of the
3670 * device and so cannot disappear as we iterate. Similarly, we can
3671 * happily treat the predicates as racy, atomic checks as userspace
3672 * cannot claim and pin a new fb without at least acquring the
3673 * struct_mutex and so serialising with us.
3674 */
3675 for_each_intel_crtc(dev, crtc) {
3676 if (atomic_read(&crtc->unpin_work_count) == 0)
3677 continue;
3678
3679 if (crtc->unpin_work)
3680 intel_wait_for_vblank(dev, crtc->pipe);
3681
3682 return true;
3683 }
3684
3685 return false;
3686 }
3687
3688 static void page_flip_completed(struct intel_crtc *intel_crtc)
3689 {
3690 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3691 struct intel_unpin_work *work = intel_crtc->unpin_work;
3692
3693 /* ensure that the unpin work is consistent wrt ->pending. */
3694 smp_rmb();
3695 intel_crtc->unpin_work = NULL;
3696
3697 if (work->event)
3698 drm_send_vblank_event(intel_crtc->base.dev,
3699 intel_crtc->pipe,
3700 work->event);
3701
3702 drm_crtc_vblank_put(&intel_crtc->base);
3703
3704 wake_up_all(&dev_priv->pending_flip_queue);
3705 queue_work(dev_priv->wq, &work->work);
3706
3707 trace_i915_flip_complete(intel_crtc->plane,
3708 work->pending_flip_obj);
3709 }
3710
3711 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3712 {
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715
3716 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3717 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3718 !intel_crtc_has_pending_flip(crtc),
3719 60*HZ) == 0)) {
3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721
3722 spin_lock_irq(&dev->event_lock);
3723 if (intel_crtc->unpin_work) {
3724 WARN_ONCE(1, "Removing stuck page flip\n");
3725 page_flip_completed(intel_crtc);
3726 }
3727 spin_unlock_irq(&dev->event_lock);
3728 }
3729
3730 if (crtc->primary->fb) {
3731 mutex_lock(&dev->struct_mutex);
3732 intel_finish_fb(crtc->primary->fb);
3733 mutex_unlock(&dev->struct_mutex);
3734 }
3735 }
3736
3737 /* Program iCLKIP clock to the desired frequency */
3738 static void lpt_program_iclkip(struct drm_crtc *crtc)
3739 {
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3743 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3744 u32 temp;
3745
3746 mutex_lock(&dev_priv->dpio_lock);
3747
3748 /* It is necessary to ungate the pixclk gate prior to programming
3749 * the divisors, and gate it back when it is done.
3750 */
3751 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3752
3753 /* Disable SSCCTL */
3754 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3755 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3756 SBI_SSCCTL_DISABLE,
3757 SBI_ICLK);
3758
3759 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3760 if (clock == 20000) {
3761 auxdiv = 1;
3762 divsel = 0x41;
3763 phaseinc = 0x20;
3764 } else {
3765 /* The iCLK virtual clock root frequency is in MHz,
3766 * but the adjusted_mode->crtc_clock in in KHz. To get the
3767 * divisors, it is necessary to divide one by another, so we
3768 * convert the virtual clock precision to KHz here for higher
3769 * precision.
3770 */
3771 u32 iclk_virtual_root_freq = 172800 * 1000;
3772 u32 iclk_pi_range = 64;
3773 u32 desired_divisor, msb_divisor_value, pi_value;
3774
3775 desired_divisor = (iclk_virtual_root_freq / clock);
3776 msb_divisor_value = desired_divisor / iclk_pi_range;
3777 pi_value = desired_divisor % iclk_pi_range;
3778
3779 auxdiv = 0;
3780 divsel = msb_divisor_value - 2;
3781 phaseinc = pi_value;
3782 }
3783
3784 /* This should not happen with any sane values */
3785 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3786 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3787 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3788 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3789
3790 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3791 clock,
3792 auxdiv,
3793 divsel,
3794 phasedir,
3795 phaseinc);
3796
3797 /* Program SSCDIVINTPHASE6 */
3798 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3799 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3800 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3801 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3802 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3803 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3804 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3805 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3806
3807 /* Program SSCAUXDIV */
3808 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3809 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3810 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3811 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3812
3813 /* Enable modulator and associated divider */
3814 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3815 temp &= ~SBI_SSCCTL_DISABLE;
3816 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3817
3818 /* Wait for initialization time */
3819 udelay(24);
3820
3821 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3822
3823 mutex_unlock(&dev_priv->dpio_lock);
3824 }
3825
3826 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3827 enum pipe pch_transcoder)
3828 {
3829 struct drm_device *dev = crtc->base.dev;
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3832
3833 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3834 I915_READ(HTOTAL(cpu_transcoder)));
3835 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3836 I915_READ(HBLANK(cpu_transcoder)));
3837 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3838 I915_READ(HSYNC(cpu_transcoder)));
3839
3840 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3841 I915_READ(VTOTAL(cpu_transcoder)));
3842 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3843 I915_READ(VBLANK(cpu_transcoder)));
3844 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3845 I915_READ(VSYNC(cpu_transcoder)));
3846 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3847 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3848 }
3849
3850 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3851 {
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 uint32_t temp;
3854
3855 temp = I915_READ(SOUTH_CHICKEN1);
3856 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3857 return;
3858
3859 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3860 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3861
3862 temp &= ~FDI_BC_BIFURCATION_SELECT;
3863 if (enable)
3864 temp |= FDI_BC_BIFURCATION_SELECT;
3865
3866 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3867 I915_WRITE(SOUTH_CHICKEN1, temp);
3868 POSTING_READ(SOUTH_CHICKEN1);
3869 }
3870
3871 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3872 {
3873 struct drm_device *dev = intel_crtc->base.dev;
3874
3875 switch (intel_crtc->pipe) {
3876 case PIPE_A:
3877 break;
3878 case PIPE_B:
3879 if (intel_crtc->config->fdi_lanes > 2)
3880 cpt_set_fdi_bc_bifurcation(dev, false);
3881 else
3882 cpt_set_fdi_bc_bifurcation(dev, true);
3883
3884 break;
3885 case PIPE_C:
3886 cpt_set_fdi_bc_bifurcation(dev, true);
3887
3888 break;
3889 default:
3890 BUG();
3891 }
3892 }
3893
3894 /*
3895 * Enable PCH resources required for PCH ports:
3896 * - PCH PLLs
3897 * - FDI training & RX/TX
3898 * - update transcoder timings
3899 * - DP transcoding bits
3900 * - transcoder
3901 */
3902 static void ironlake_pch_enable(struct drm_crtc *crtc)
3903 {
3904 struct drm_device *dev = crtc->dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3907 int pipe = intel_crtc->pipe;
3908 u32 reg, temp;
3909
3910 assert_pch_transcoder_disabled(dev_priv, pipe);
3911
3912 if (IS_IVYBRIDGE(dev))
3913 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3914
3915 /* Write the TU size bits before fdi link training, so that error
3916 * detection works. */
3917 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3918 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3919
3920 /* For PCH output, training FDI link */
3921 dev_priv->display.fdi_link_train(crtc);
3922
3923 /* We need to program the right clock selection before writing the pixel
3924 * mutliplier into the DPLL. */
3925 if (HAS_PCH_CPT(dev)) {
3926 u32 sel;
3927
3928 temp = I915_READ(PCH_DPLL_SEL);
3929 temp |= TRANS_DPLL_ENABLE(pipe);
3930 sel = TRANS_DPLLB_SEL(pipe);
3931 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3932 temp |= sel;
3933 else
3934 temp &= ~sel;
3935 I915_WRITE(PCH_DPLL_SEL, temp);
3936 }
3937
3938 /* XXX: pch pll's can be enabled any time before we enable the PCH
3939 * transcoder, and we actually should do this to not upset any PCH
3940 * transcoder that already use the clock when we share it.
3941 *
3942 * Note that enable_shared_dpll tries to do the right thing, but
3943 * get_shared_dpll unconditionally resets the pll - we need that to have
3944 * the right LVDS enable sequence. */
3945 intel_enable_shared_dpll(intel_crtc);
3946
3947 /* set transcoder timing, panel must allow it */
3948 assert_panel_unlocked(dev_priv, pipe);
3949 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3950
3951 intel_fdi_normal_train(crtc);
3952
3953 /* For PCH DP, enable TRANS_DP_CTL */
3954 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3955 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3956 reg = TRANS_DP_CTL(pipe);
3957 temp = I915_READ(reg);
3958 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3959 TRANS_DP_SYNC_MASK |
3960 TRANS_DP_BPC_MASK);
3961 temp |= (TRANS_DP_OUTPUT_ENABLE |
3962 TRANS_DP_ENH_FRAMING);
3963 temp |= bpc << 9; /* same format but at 11:9 */
3964
3965 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3966 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3967 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3968 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3969
3970 switch (intel_trans_dp_port_sel(crtc)) {
3971 case PCH_DP_B:
3972 temp |= TRANS_DP_PORT_SEL_B;
3973 break;
3974 case PCH_DP_C:
3975 temp |= TRANS_DP_PORT_SEL_C;
3976 break;
3977 case PCH_DP_D:
3978 temp |= TRANS_DP_PORT_SEL_D;
3979 break;
3980 default:
3981 BUG();
3982 }
3983
3984 I915_WRITE(reg, temp);
3985 }
3986
3987 ironlake_enable_pch_transcoder(dev_priv, pipe);
3988 }
3989
3990 static void lpt_pch_enable(struct drm_crtc *crtc)
3991 {
3992 struct drm_device *dev = crtc->dev;
3993 struct drm_i915_private *dev_priv = dev->dev_private;
3994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3995 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3996
3997 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3998
3999 lpt_program_iclkip(crtc);
4000
4001 /* Set transcoder timing. */
4002 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4003
4004 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4005 }
4006
4007 void intel_put_shared_dpll(struct intel_crtc *crtc)
4008 {
4009 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4010
4011 if (pll == NULL)
4012 return;
4013
4014 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4015 WARN(1, "bad %s crtc mask\n", pll->name);
4016 return;
4017 }
4018
4019 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4020 if (pll->config.crtc_mask == 0) {
4021 WARN_ON(pll->on);
4022 WARN_ON(pll->active);
4023 }
4024
4025 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4026 }
4027
4028 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4029 struct intel_crtc_state *crtc_state)
4030 {
4031 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4032 struct intel_shared_dpll *pll;
4033 enum intel_dpll_id i;
4034
4035 if (HAS_PCH_IBX(dev_priv->dev)) {
4036 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4037 i = (enum intel_dpll_id) crtc->pipe;
4038 pll = &dev_priv->shared_dplls[i];
4039
4040 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4041 crtc->base.base.id, pll->name);
4042
4043 WARN_ON(pll->new_config->crtc_mask);
4044
4045 goto found;
4046 }
4047
4048 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4049 pll = &dev_priv->shared_dplls[i];
4050
4051 /* Only want to check enabled timings first */
4052 if (pll->new_config->crtc_mask == 0)
4053 continue;
4054
4055 if (memcmp(&crtc_state->dpll_hw_state,
4056 &pll->new_config->hw_state,
4057 sizeof(pll->new_config->hw_state)) == 0) {
4058 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4059 crtc->base.base.id, pll->name,
4060 pll->new_config->crtc_mask,
4061 pll->active);
4062 goto found;
4063 }
4064 }
4065
4066 /* Ok no matching timings, maybe there's a free one? */
4067 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4068 pll = &dev_priv->shared_dplls[i];
4069 if (pll->new_config->crtc_mask == 0) {
4070 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4071 crtc->base.base.id, pll->name);
4072 goto found;
4073 }
4074 }
4075
4076 return NULL;
4077
4078 found:
4079 if (pll->new_config->crtc_mask == 0)
4080 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4081
4082 crtc_state->shared_dpll = i;
4083 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4084 pipe_name(crtc->pipe));
4085
4086 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4087
4088 return pll;
4089 }
4090
4091 /**
4092 * intel_shared_dpll_start_config - start a new PLL staged config
4093 * @dev_priv: DRM device
4094 * @clear_pipes: mask of pipes that will have their PLLs freed
4095 *
4096 * Starts a new PLL staged config, copying the current config but
4097 * releasing the references of pipes specified in clear_pipes.
4098 */
4099 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4100 unsigned clear_pipes)
4101 {
4102 struct intel_shared_dpll *pll;
4103 enum intel_dpll_id i;
4104
4105 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4106 pll = &dev_priv->shared_dplls[i];
4107
4108 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4109 GFP_KERNEL);
4110 if (!pll->new_config)
4111 goto cleanup;
4112
4113 pll->new_config->crtc_mask &= ~clear_pipes;
4114 }
4115
4116 return 0;
4117
4118 cleanup:
4119 while (--i >= 0) {
4120 pll = &dev_priv->shared_dplls[i];
4121 kfree(pll->new_config);
4122 pll->new_config = NULL;
4123 }
4124
4125 return -ENOMEM;
4126 }
4127
4128 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4129 {
4130 struct intel_shared_dpll *pll;
4131 enum intel_dpll_id i;
4132
4133 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4134 pll = &dev_priv->shared_dplls[i];
4135
4136 WARN_ON(pll->new_config == &pll->config);
4137
4138 pll->config = *pll->new_config;
4139 kfree(pll->new_config);
4140 pll->new_config = NULL;
4141 }
4142 }
4143
4144 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4145 {
4146 struct intel_shared_dpll *pll;
4147 enum intel_dpll_id i;
4148
4149 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4150 pll = &dev_priv->shared_dplls[i];
4151
4152 WARN_ON(pll->new_config == &pll->config);
4153
4154 kfree(pll->new_config);
4155 pll->new_config = NULL;
4156 }
4157 }
4158
4159 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4160 {
4161 struct drm_i915_private *dev_priv = dev->dev_private;
4162 int dslreg = PIPEDSL(pipe);
4163 u32 temp;
4164
4165 temp = I915_READ(dslreg);
4166 udelay(500);
4167 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4168 if (wait_for(I915_READ(dslreg) != temp, 5))
4169 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4170 }
4171 }
4172
4173 static void skylake_pfit_enable(struct intel_crtc *crtc)
4174 {
4175 struct drm_device *dev = crtc->base.dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 int pipe = crtc->pipe;
4178
4179 if (crtc->config->pch_pfit.enabled) {
4180 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4181 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4182 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4183 }
4184 }
4185
4186 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4187 {
4188 struct drm_device *dev = crtc->base.dev;
4189 struct drm_i915_private *dev_priv = dev->dev_private;
4190 int pipe = crtc->pipe;
4191
4192 if (crtc->config->pch_pfit.enabled) {
4193 /* Force use of hard-coded filter coefficients
4194 * as some pre-programmed values are broken,
4195 * e.g. x201.
4196 */
4197 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4198 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4199 PF_PIPE_SEL_IVB(pipe));
4200 else
4201 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4202 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4203 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4204 }
4205 }
4206
4207 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4208 {
4209 struct drm_device *dev = crtc->dev;
4210 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4211 struct drm_plane *plane;
4212 struct intel_plane *intel_plane;
4213
4214 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4215 intel_plane = to_intel_plane(plane);
4216 if (intel_plane->pipe == pipe)
4217 intel_plane_restore(&intel_plane->base);
4218 }
4219 }
4220
4221 /*
4222 * Disable a plane internally without actually modifying the plane's state.
4223 * This will allow us to easily restore the plane later by just reprogramming
4224 * its state.
4225 */
4226 static void disable_plane_internal(struct drm_plane *plane)
4227 {
4228 struct intel_plane *intel_plane = to_intel_plane(plane);
4229 struct drm_plane_state *state =
4230 plane->funcs->atomic_duplicate_state(plane);
4231 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4232
4233 intel_state->visible = false;
4234 intel_plane->commit_plane(plane, intel_state);
4235
4236 intel_plane_destroy_state(plane, state);
4237 }
4238
4239 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4240 {
4241 struct drm_device *dev = crtc->dev;
4242 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4243 struct drm_plane *plane;
4244 struct intel_plane *intel_plane;
4245
4246 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4247 intel_plane = to_intel_plane(plane);
4248 if (plane->fb && intel_plane->pipe == pipe)
4249 disable_plane_internal(plane);
4250 }
4251 }
4252
4253 void hsw_enable_ips(struct intel_crtc *crtc)
4254 {
4255 struct drm_device *dev = crtc->base.dev;
4256 struct drm_i915_private *dev_priv = dev->dev_private;
4257
4258 if (!crtc->config->ips_enabled)
4259 return;
4260
4261 /* We can only enable IPS after we enable a plane and wait for a vblank */
4262 intel_wait_for_vblank(dev, crtc->pipe);
4263
4264 assert_plane_enabled(dev_priv, crtc->plane);
4265 if (IS_BROADWELL(dev)) {
4266 mutex_lock(&dev_priv->rps.hw_lock);
4267 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4268 mutex_unlock(&dev_priv->rps.hw_lock);
4269 /* Quoting Art Runyan: "its not safe to expect any particular
4270 * value in IPS_CTL bit 31 after enabling IPS through the
4271 * mailbox." Moreover, the mailbox may return a bogus state,
4272 * so we need to just enable it and continue on.
4273 */
4274 } else {
4275 I915_WRITE(IPS_CTL, IPS_ENABLE);
4276 /* The bit only becomes 1 in the next vblank, so this wait here
4277 * is essentially intel_wait_for_vblank. If we don't have this
4278 * and don't wait for vblanks until the end of crtc_enable, then
4279 * the HW state readout code will complain that the expected
4280 * IPS_CTL value is not the one we read. */
4281 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4282 DRM_ERROR("Timed out waiting for IPS enable\n");
4283 }
4284 }
4285
4286 void hsw_disable_ips(struct intel_crtc *crtc)
4287 {
4288 struct drm_device *dev = crtc->base.dev;
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290
4291 if (!crtc->config->ips_enabled)
4292 return;
4293
4294 assert_plane_enabled(dev_priv, crtc->plane);
4295 if (IS_BROADWELL(dev)) {
4296 mutex_lock(&dev_priv->rps.hw_lock);
4297 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4298 mutex_unlock(&dev_priv->rps.hw_lock);
4299 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4300 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4301 DRM_ERROR("Timed out waiting for IPS disable\n");
4302 } else {
4303 I915_WRITE(IPS_CTL, 0);
4304 POSTING_READ(IPS_CTL);
4305 }
4306
4307 /* We need to wait for a vblank before we can disable the plane. */
4308 intel_wait_for_vblank(dev, crtc->pipe);
4309 }
4310
4311 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4312 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4313 {
4314 struct drm_device *dev = crtc->dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 enum pipe pipe = intel_crtc->pipe;
4318 int palreg = PALETTE(pipe);
4319 int i;
4320 bool reenable_ips = false;
4321
4322 /* The clocks have to be on to load the palette. */
4323 if (!crtc->state->enable || !intel_crtc->active)
4324 return;
4325
4326 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4327 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4328 assert_dsi_pll_enabled(dev_priv);
4329 else
4330 assert_pll_enabled(dev_priv, pipe);
4331 }
4332
4333 /* use legacy palette for Ironlake */
4334 if (!HAS_GMCH_DISPLAY(dev))
4335 palreg = LGC_PALETTE(pipe);
4336
4337 /* Workaround : Do not read or write the pipe palette/gamma data while
4338 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4339 */
4340 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4341 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4342 GAMMA_MODE_MODE_SPLIT)) {
4343 hsw_disable_ips(intel_crtc);
4344 reenable_ips = true;
4345 }
4346
4347 for (i = 0; i < 256; i++) {
4348 I915_WRITE(palreg + 4 * i,
4349 (intel_crtc->lut_r[i] << 16) |
4350 (intel_crtc->lut_g[i] << 8) |
4351 intel_crtc->lut_b[i]);
4352 }
4353
4354 if (reenable_ips)
4355 hsw_enable_ips(intel_crtc);
4356 }
4357
4358 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4359 {
4360 if (!enable && intel_crtc->overlay) {
4361 struct drm_device *dev = intel_crtc->base.dev;
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363
4364 mutex_lock(&dev->struct_mutex);
4365 dev_priv->mm.interruptible = false;
4366 (void) intel_overlay_switch_off(intel_crtc->overlay);
4367 dev_priv->mm.interruptible = true;
4368 mutex_unlock(&dev->struct_mutex);
4369 }
4370
4371 /* Let userspace switch the overlay on again. In most cases userspace
4372 * has to recompute where to put it anyway.
4373 */
4374 }
4375
4376 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4377 {
4378 struct drm_device *dev = crtc->dev;
4379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4380 int pipe = intel_crtc->pipe;
4381
4382 intel_enable_primary_hw_plane(crtc->primary, crtc);
4383 intel_enable_sprite_planes(crtc);
4384 intel_crtc_update_cursor(crtc, true);
4385 intel_crtc_dpms_overlay(intel_crtc, true);
4386
4387 hsw_enable_ips(intel_crtc);
4388
4389 mutex_lock(&dev->struct_mutex);
4390 intel_fbc_update(dev);
4391 mutex_unlock(&dev->struct_mutex);
4392
4393 /*
4394 * FIXME: Once we grow proper nuclear flip support out of this we need
4395 * to compute the mask of flip planes precisely. For the time being
4396 * consider this a flip from a NULL plane.
4397 */
4398 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4399 }
4400
4401 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4402 {
4403 struct drm_device *dev = crtc->dev;
4404 struct drm_i915_private *dev_priv = dev->dev_private;
4405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4406 int pipe = intel_crtc->pipe;
4407
4408 intel_crtc_wait_for_pending_flips(crtc);
4409
4410 if (dev_priv->fbc.crtc == intel_crtc)
4411 intel_fbc_disable(dev);
4412
4413 hsw_disable_ips(intel_crtc);
4414
4415 intel_crtc_dpms_overlay(intel_crtc, false);
4416 intel_crtc_update_cursor(crtc, false);
4417 intel_disable_sprite_planes(crtc);
4418 intel_disable_primary_hw_plane(crtc->primary, crtc);
4419
4420 /*
4421 * FIXME: Once we grow proper nuclear flip support out of this we need
4422 * to compute the mask of flip planes precisely. For the time being
4423 * consider this a flip to a NULL plane.
4424 */
4425 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4426 }
4427
4428 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4429 {
4430 struct drm_device *dev = crtc->dev;
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4433 struct intel_encoder *encoder;
4434 int pipe = intel_crtc->pipe;
4435
4436 WARN_ON(!crtc->state->enable);
4437
4438 if (intel_crtc->active)
4439 return;
4440
4441 if (intel_crtc->config->has_pch_encoder)
4442 intel_prepare_shared_dpll(intel_crtc);
4443
4444 if (intel_crtc->config->has_dp_encoder)
4445 intel_dp_set_m_n(intel_crtc, M1_N1);
4446
4447 intel_set_pipe_timings(intel_crtc);
4448
4449 if (intel_crtc->config->has_pch_encoder) {
4450 intel_cpu_transcoder_set_m_n(intel_crtc,
4451 &intel_crtc->config->fdi_m_n, NULL);
4452 }
4453
4454 ironlake_set_pipeconf(crtc);
4455
4456 intel_crtc->active = true;
4457
4458 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4459 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4460
4461 for_each_encoder_on_crtc(dev, crtc, encoder)
4462 if (encoder->pre_enable)
4463 encoder->pre_enable(encoder);
4464
4465 if (intel_crtc->config->has_pch_encoder) {
4466 /* Note: FDI PLL enabling _must_ be done before we enable the
4467 * cpu pipes, hence this is separate from all the other fdi/pch
4468 * enabling. */
4469 ironlake_fdi_pll_enable(intel_crtc);
4470 } else {
4471 assert_fdi_tx_disabled(dev_priv, pipe);
4472 assert_fdi_rx_disabled(dev_priv, pipe);
4473 }
4474
4475 ironlake_pfit_enable(intel_crtc);
4476
4477 /*
4478 * On ILK+ LUT must be loaded before the pipe is running but with
4479 * clocks enabled
4480 */
4481 intel_crtc_load_lut(crtc);
4482
4483 intel_update_watermarks(crtc);
4484 intel_enable_pipe(intel_crtc);
4485
4486 if (intel_crtc->config->has_pch_encoder)
4487 ironlake_pch_enable(crtc);
4488
4489 assert_vblank_disabled(crtc);
4490 drm_crtc_vblank_on(crtc);
4491
4492 for_each_encoder_on_crtc(dev, crtc, encoder)
4493 encoder->enable(encoder);
4494
4495 if (HAS_PCH_CPT(dev))
4496 cpt_verify_modeset(dev, intel_crtc->pipe);
4497
4498 intel_crtc_enable_planes(crtc);
4499 }
4500
4501 /* IPS only exists on ULT machines and is tied to pipe A. */
4502 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4503 {
4504 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4505 }
4506
4507 /*
4508 * This implements the workaround described in the "notes" section of the mode
4509 * set sequence documentation. When going from no pipes or single pipe to
4510 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4511 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4512 */
4513 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4514 {
4515 struct drm_device *dev = crtc->base.dev;
4516 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4517
4518 /* We want to get the other_active_crtc only if there's only 1 other
4519 * active crtc. */
4520 for_each_intel_crtc(dev, crtc_it) {
4521 if (!crtc_it->active || crtc_it == crtc)
4522 continue;
4523
4524 if (other_active_crtc)
4525 return;
4526
4527 other_active_crtc = crtc_it;
4528 }
4529 if (!other_active_crtc)
4530 return;
4531
4532 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4533 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4534 }
4535
4536 static void haswell_crtc_enable(struct drm_crtc *crtc)
4537 {
4538 struct drm_device *dev = crtc->dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 struct intel_encoder *encoder;
4542 int pipe = intel_crtc->pipe;
4543
4544 WARN_ON(!crtc->state->enable);
4545
4546 if (intel_crtc->active)
4547 return;
4548
4549 if (intel_crtc_to_shared_dpll(intel_crtc))
4550 intel_enable_shared_dpll(intel_crtc);
4551
4552 if (intel_crtc->config->has_dp_encoder)
4553 intel_dp_set_m_n(intel_crtc, M1_N1);
4554
4555 intel_set_pipe_timings(intel_crtc);
4556
4557 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4558 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4559 intel_crtc->config->pixel_multiplier - 1);
4560 }
4561
4562 if (intel_crtc->config->has_pch_encoder) {
4563 intel_cpu_transcoder_set_m_n(intel_crtc,
4564 &intel_crtc->config->fdi_m_n, NULL);
4565 }
4566
4567 haswell_set_pipeconf(crtc);
4568
4569 intel_set_pipe_csc(crtc);
4570
4571 intel_crtc->active = true;
4572
4573 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4574 for_each_encoder_on_crtc(dev, crtc, encoder)
4575 if (encoder->pre_enable)
4576 encoder->pre_enable(encoder);
4577
4578 if (intel_crtc->config->has_pch_encoder) {
4579 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4580 true);
4581 dev_priv->display.fdi_link_train(crtc);
4582 }
4583
4584 intel_ddi_enable_pipe_clock(intel_crtc);
4585
4586 if (IS_SKYLAKE(dev))
4587 skylake_pfit_enable(intel_crtc);
4588 else
4589 ironlake_pfit_enable(intel_crtc);
4590
4591 /*
4592 * On ILK+ LUT must be loaded before the pipe is running but with
4593 * clocks enabled
4594 */
4595 intel_crtc_load_lut(crtc);
4596
4597 intel_ddi_set_pipe_settings(crtc);
4598 intel_ddi_enable_transcoder_func(crtc);
4599
4600 intel_update_watermarks(crtc);
4601 intel_enable_pipe(intel_crtc);
4602
4603 if (intel_crtc->config->has_pch_encoder)
4604 lpt_pch_enable(crtc);
4605
4606 if (intel_crtc->config->dp_encoder_is_mst)
4607 intel_ddi_set_vc_payload_alloc(crtc, true);
4608
4609 assert_vblank_disabled(crtc);
4610 drm_crtc_vblank_on(crtc);
4611
4612 for_each_encoder_on_crtc(dev, crtc, encoder) {
4613 encoder->enable(encoder);
4614 intel_opregion_notify_encoder(encoder, true);
4615 }
4616
4617 /* If we change the relative order between pipe/planes enabling, we need
4618 * to change the workaround. */
4619 haswell_mode_set_planes_workaround(intel_crtc);
4620 intel_crtc_enable_planes(crtc);
4621 }
4622
4623 static void skylake_pfit_disable(struct intel_crtc *crtc)
4624 {
4625 struct drm_device *dev = crtc->base.dev;
4626 struct drm_i915_private *dev_priv = dev->dev_private;
4627 int pipe = crtc->pipe;
4628
4629 /* To avoid upsetting the power well on haswell only disable the pfit if
4630 * it's in use. The hw state code will make sure we get this right. */
4631 if (crtc->config->pch_pfit.enabled) {
4632 I915_WRITE(PS_CTL(pipe), 0);
4633 I915_WRITE(PS_WIN_POS(pipe), 0);
4634 I915_WRITE(PS_WIN_SZ(pipe), 0);
4635 }
4636 }
4637
4638 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4639 {
4640 struct drm_device *dev = crtc->base.dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642 int pipe = crtc->pipe;
4643
4644 /* To avoid upsetting the power well on haswell only disable the pfit if
4645 * it's in use. The hw state code will make sure we get this right. */
4646 if (crtc->config->pch_pfit.enabled) {
4647 I915_WRITE(PF_CTL(pipe), 0);
4648 I915_WRITE(PF_WIN_POS(pipe), 0);
4649 I915_WRITE(PF_WIN_SZ(pipe), 0);
4650 }
4651 }
4652
4653 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4654 {
4655 struct drm_device *dev = crtc->dev;
4656 struct drm_i915_private *dev_priv = dev->dev_private;
4657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4658 struct intel_encoder *encoder;
4659 int pipe = intel_crtc->pipe;
4660 u32 reg, temp;
4661
4662 if (!intel_crtc->active)
4663 return;
4664
4665 intel_crtc_disable_planes(crtc);
4666
4667 for_each_encoder_on_crtc(dev, crtc, encoder)
4668 encoder->disable(encoder);
4669
4670 drm_crtc_vblank_off(crtc);
4671 assert_vblank_disabled(crtc);
4672
4673 if (intel_crtc->config->has_pch_encoder)
4674 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4675
4676 intel_disable_pipe(intel_crtc);
4677
4678 ironlake_pfit_disable(intel_crtc);
4679
4680 for_each_encoder_on_crtc(dev, crtc, encoder)
4681 if (encoder->post_disable)
4682 encoder->post_disable(encoder);
4683
4684 if (intel_crtc->config->has_pch_encoder) {
4685 ironlake_fdi_disable(crtc);
4686
4687 ironlake_disable_pch_transcoder(dev_priv, pipe);
4688
4689 if (HAS_PCH_CPT(dev)) {
4690 /* disable TRANS_DP_CTL */
4691 reg = TRANS_DP_CTL(pipe);
4692 temp = I915_READ(reg);
4693 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4694 TRANS_DP_PORT_SEL_MASK);
4695 temp |= TRANS_DP_PORT_SEL_NONE;
4696 I915_WRITE(reg, temp);
4697
4698 /* disable DPLL_SEL */
4699 temp = I915_READ(PCH_DPLL_SEL);
4700 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4701 I915_WRITE(PCH_DPLL_SEL, temp);
4702 }
4703
4704 /* disable PCH DPLL */
4705 intel_disable_shared_dpll(intel_crtc);
4706
4707 ironlake_fdi_pll_disable(intel_crtc);
4708 }
4709
4710 intel_crtc->active = false;
4711 intel_update_watermarks(crtc);
4712
4713 mutex_lock(&dev->struct_mutex);
4714 intel_fbc_update(dev);
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 static void haswell_crtc_disable(struct drm_crtc *crtc)
4719 {
4720 struct drm_device *dev = crtc->dev;
4721 struct drm_i915_private *dev_priv = dev->dev_private;
4722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4723 struct intel_encoder *encoder;
4724 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4725
4726 if (!intel_crtc->active)
4727 return;
4728
4729 intel_crtc_disable_planes(crtc);
4730
4731 for_each_encoder_on_crtc(dev, crtc, encoder) {
4732 intel_opregion_notify_encoder(encoder, false);
4733 encoder->disable(encoder);
4734 }
4735
4736 drm_crtc_vblank_off(crtc);
4737 assert_vblank_disabled(crtc);
4738
4739 if (intel_crtc->config->has_pch_encoder)
4740 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4741 false);
4742 intel_disable_pipe(intel_crtc);
4743
4744 if (intel_crtc->config->dp_encoder_is_mst)
4745 intel_ddi_set_vc_payload_alloc(crtc, false);
4746
4747 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4748
4749 if (IS_SKYLAKE(dev))
4750 skylake_pfit_disable(intel_crtc);
4751 else
4752 ironlake_pfit_disable(intel_crtc);
4753
4754 intel_ddi_disable_pipe_clock(intel_crtc);
4755
4756 if (intel_crtc->config->has_pch_encoder) {
4757 lpt_disable_pch_transcoder(dev_priv);
4758 intel_ddi_fdi_disable(crtc);
4759 }
4760
4761 for_each_encoder_on_crtc(dev, crtc, encoder)
4762 if (encoder->post_disable)
4763 encoder->post_disable(encoder);
4764
4765 intel_crtc->active = false;
4766 intel_update_watermarks(crtc);
4767
4768 mutex_lock(&dev->struct_mutex);
4769 intel_fbc_update(dev);
4770 mutex_unlock(&dev->struct_mutex);
4771
4772 if (intel_crtc_to_shared_dpll(intel_crtc))
4773 intel_disable_shared_dpll(intel_crtc);
4774 }
4775
4776 static void ironlake_crtc_off(struct drm_crtc *crtc)
4777 {
4778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4779 intel_put_shared_dpll(intel_crtc);
4780 }
4781
4782
4783 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4784 {
4785 struct drm_device *dev = crtc->base.dev;
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787 struct intel_crtc_state *pipe_config = crtc->config;
4788
4789 if (!pipe_config->gmch_pfit.control)
4790 return;
4791
4792 /*
4793 * The panel fitter should only be adjusted whilst the pipe is disabled,
4794 * according to register description and PRM.
4795 */
4796 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4797 assert_pipe_disabled(dev_priv, crtc->pipe);
4798
4799 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4800 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4801
4802 /* Border color in case we don't scale up to the full screen. Black by
4803 * default, change to something else for debugging. */
4804 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4805 }
4806
4807 static enum intel_display_power_domain port_to_power_domain(enum port port)
4808 {
4809 switch (port) {
4810 case PORT_A:
4811 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4812 case PORT_B:
4813 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4814 case PORT_C:
4815 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4816 case PORT_D:
4817 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4818 default:
4819 WARN_ON_ONCE(1);
4820 return POWER_DOMAIN_PORT_OTHER;
4821 }
4822 }
4823
4824 #define for_each_power_domain(domain, mask) \
4825 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4826 if ((1 << (domain)) & (mask))
4827
4828 enum intel_display_power_domain
4829 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4830 {
4831 struct drm_device *dev = intel_encoder->base.dev;
4832 struct intel_digital_port *intel_dig_port;
4833
4834 switch (intel_encoder->type) {
4835 case INTEL_OUTPUT_UNKNOWN:
4836 /* Only DDI platforms should ever use this output type */
4837 WARN_ON_ONCE(!HAS_DDI(dev));
4838 case INTEL_OUTPUT_DISPLAYPORT:
4839 case INTEL_OUTPUT_HDMI:
4840 case INTEL_OUTPUT_EDP:
4841 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4842 return port_to_power_domain(intel_dig_port->port);
4843 case INTEL_OUTPUT_DP_MST:
4844 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4845 return port_to_power_domain(intel_dig_port->port);
4846 case INTEL_OUTPUT_ANALOG:
4847 return POWER_DOMAIN_PORT_CRT;
4848 case INTEL_OUTPUT_DSI:
4849 return POWER_DOMAIN_PORT_DSI;
4850 default:
4851 return POWER_DOMAIN_PORT_OTHER;
4852 }
4853 }
4854
4855 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4856 {
4857 struct drm_device *dev = crtc->dev;
4858 struct intel_encoder *intel_encoder;
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860 enum pipe pipe = intel_crtc->pipe;
4861 unsigned long mask;
4862 enum transcoder transcoder;
4863
4864 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4865
4866 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4867 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4868 if (intel_crtc->config->pch_pfit.enabled ||
4869 intel_crtc->config->pch_pfit.force_thru)
4870 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4871
4872 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4873 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4874
4875 return mask;
4876 }
4877
4878 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4879 {
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4882 struct intel_crtc *crtc;
4883
4884 /*
4885 * First get all needed power domains, then put all unneeded, to avoid
4886 * any unnecessary toggling of the power wells.
4887 */
4888 for_each_intel_crtc(dev, crtc) {
4889 enum intel_display_power_domain domain;
4890
4891 if (!crtc->base.state->enable)
4892 continue;
4893
4894 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4895
4896 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4897 intel_display_power_get(dev_priv, domain);
4898 }
4899
4900 if (dev_priv->display.modeset_global_resources)
4901 dev_priv->display.modeset_global_resources(dev);
4902
4903 for_each_intel_crtc(dev, crtc) {
4904 enum intel_display_power_domain domain;
4905
4906 for_each_power_domain(domain, crtc->enabled_power_domains)
4907 intel_display_power_put(dev_priv, domain);
4908
4909 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4910 }
4911
4912 intel_display_set_init_power(dev_priv, false);
4913 }
4914
4915 /* returns HPLL frequency in kHz */
4916 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4917 {
4918 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4919
4920 /* Obtain SKU information */
4921 mutex_lock(&dev_priv->dpio_lock);
4922 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4923 CCK_FUSE_HPLL_FREQ_MASK;
4924 mutex_unlock(&dev_priv->dpio_lock);
4925
4926 return vco_freq[hpll_freq] * 1000;
4927 }
4928
4929 static void vlv_update_cdclk(struct drm_device *dev)
4930 {
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4932
4933 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4934 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4935 dev_priv->vlv_cdclk_freq);
4936
4937 /*
4938 * Program the gmbus_freq based on the cdclk frequency.
4939 * BSpec erroneously claims we should aim for 4MHz, but
4940 * in fact 1MHz is the correct frequency.
4941 */
4942 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4943 }
4944
4945 /* Adjust CDclk dividers to allow high res or save power if possible */
4946 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4947 {
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 u32 val, cmd;
4950
4951 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4952
4953 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4954 cmd = 2;
4955 else if (cdclk == 266667)
4956 cmd = 1;
4957 else
4958 cmd = 0;
4959
4960 mutex_lock(&dev_priv->rps.hw_lock);
4961 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4962 val &= ~DSPFREQGUAR_MASK;
4963 val |= (cmd << DSPFREQGUAR_SHIFT);
4964 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4965 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4966 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4967 50)) {
4968 DRM_ERROR("timed out waiting for CDclk change\n");
4969 }
4970 mutex_unlock(&dev_priv->rps.hw_lock);
4971
4972 if (cdclk == 400000) {
4973 u32 divider;
4974
4975 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4976
4977 mutex_lock(&dev_priv->dpio_lock);
4978 /* adjust cdclk divider */
4979 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4980 val &= ~DISPLAY_FREQUENCY_VALUES;
4981 val |= divider;
4982 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4983
4984 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4985 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4986 50))
4987 DRM_ERROR("timed out waiting for CDclk change\n");
4988 mutex_unlock(&dev_priv->dpio_lock);
4989 }
4990
4991 mutex_lock(&dev_priv->dpio_lock);
4992 /* adjust self-refresh exit latency value */
4993 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4994 val &= ~0x7f;
4995
4996 /*
4997 * For high bandwidth configs, we set a higher latency in the bunit
4998 * so that the core display fetch happens in time to avoid underruns.
4999 */
5000 if (cdclk == 400000)
5001 val |= 4500 / 250; /* 4.5 usec */
5002 else
5003 val |= 3000 / 250; /* 3.0 usec */
5004 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5005 mutex_unlock(&dev_priv->dpio_lock);
5006
5007 vlv_update_cdclk(dev);
5008 }
5009
5010 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5011 {
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 u32 val, cmd;
5014
5015 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5016
5017 switch (cdclk) {
5018 case 333333:
5019 case 320000:
5020 case 266667:
5021 case 200000:
5022 break;
5023 default:
5024 MISSING_CASE(cdclk);
5025 return;
5026 }
5027
5028 /*
5029 * Specs are full of misinformation, but testing on actual
5030 * hardware has shown that we just need to write the desired
5031 * CCK divider into the Punit register.
5032 */
5033 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5034
5035 mutex_lock(&dev_priv->rps.hw_lock);
5036 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5037 val &= ~DSPFREQGUAR_MASK_CHV;
5038 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5039 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5040 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5041 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5042 50)) {
5043 DRM_ERROR("timed out waiting for CDclk change\n");
5044 }
5045 mutex_unlock(&dev_priv->rps.hw_lock);
5046
5047 vlv_update_cdclk(dev);
5048 }
5049
5050 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5051 int max_pixclk)
5052 {
5053 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5054 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5055
5056 /*
5057 * Really only a few cases to deal with, as only 4 CDclks are supported:
5058 * 200MHz
5059 * 267MHz
5060 * 320/333MHz (depends on HPLL freq)
5061 * 400MHz (VLV only)
5062 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5063 * of the lower bin and adjust if needed.
5064 *
5065 * We seem to get an unstable or solid color picture at 200MHz.
5066 * Not sure what's wrong. For now use 200MHz only when all pipes
5067 * are off.
5068 */
5069 if (!IS_CHERRYVIEW(dev_priv) &&
5070 max_pixclk > freq_320*limit/100)
5071 return 400000;
5072 else if (max_pixclk > 266667*limit/100)
5073 return freq_320;
5074 else if (max_pixclk > 0)
5075 return 266667;
5076 else
5077 return 200000;
5078 }
5079
5080 /* compute the max pixel clock for new configuration */
5081 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5082 {
5083 struct drm_device *dev = dev_priv->dev;
5084 struct intel_crtc *intel_crtc;
5085 int max_pixclk = 0;
5086
5087 for_each_intel_crtc(dev, intel_crtc) {
5088 if (intel_crtc->new_enabled)
5089 max_pixclk = max(max_pixclk,
5090 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5091 }
5092
5093 return max_pixclk;
5094 }
5095
5096 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5097 unsigned *prepare_pipes)
5098 {
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 struct intel_crtc *intel_crtc;
5101 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5102
5103 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5104 dev_priv->vlv_cdclk_freq)
5105 return;
5106
5107 /* disable/enable all currently active pipes while we change cdclk */
5108 for_each_intel_crtc(dev, intel_crtc)
5109 if (intel_crtc->base.state->enable)
5110 *prepare_pipes |= (1 << intel_crtc->pipe);
5111 }
5112
5113 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5114 {
5115 unsigned int credits, default_credits;
5116
5117 if (IS_CHERRYVIEW(dev_priv))
5118 default_credits = PFI_CREDIT(12);
5119 else
5120 default_credits = PFI_CREDIT(8);
5121
5122 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5123 /* CHV suggested value is 31 or 63 */
5124 if (IS_CHERRYVIEW(dev_priv))
5125 credits = PFI_CREDIT_31;
5126 else
5127 credits = PFI_CREDIT(15);
5128 } else {
5129 credits = default_credits;
5130 }
5131
5132 /*
5133 * WA - write default credits before re-programming
5134 * FIXME: should we also set the resend bit here?
5135 */
5136 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5137 default_credits);
5138
5139 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5140 credits | PFI_CREDIT_RESEND);
5141
5142 /*
5143 * FIXME is this guaranteed to clear
5144 * immediately or should we poll for it?
5145 */
5146 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5147 }
5148
5149 static void valleyview_modeset_global_resources(struct drm_device *dev)
5150 {
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5153 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5154
5155 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5156 /*
5157 * FIXME: We can end up here with all power domains off, yet
5158 * with a CDCLK frequency other than the minimum. To account
5159 * for this take the PIPE-A power domain, which covers the HW
5160 * blocks needed for the following programming. This can be
5161 * removed once it's guaranteed that we get here either with
5162 * the minimum CDCLK set, or the required power domains
5163 * enabled.
5164 */
5165 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5166
5167 if (IS_CHERRYVIEW(dev))
5168 cherryview_set_cdclk(dev, req_cdclk);
5169 else
5170 valleyview_set_cdclk(dev, req_cdclk);
5171
5172 vlv_program_pfi_credits(dev_priv);
5173
5174 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5175 }
5176 }
5177
5178 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5179 {
5180 struct drm_device *dev = crtc->dev;
5181 struct drm_i915_private *dev_priv = to_i915(dev);
5182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5183 struct intel_encoder *encoder;
5184 int pipe = intel_crtc->pipe;
5185 bool is_dsi;
5186
5187 WARN_ON(!crtc->state->enable);
5188
5189 if (intel_crtc->active)
5190 return;
5191
5192 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5193
5194 if (!is_dsi) {
5195 if (IS_CHERRYVIEW(dev))
5196 chv_prepare_pll(intel_crtc, intel_crtc->config);
5197 else
5198 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5199 }
5200
5201 if (intel_crtc->config->has_dp_encoder)
5202 intel_dp_set_m_n(intel_crtc, M1_N1);
5203
5204 intel_set_pipe_timings(intel_crtc);
5205
5206 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208
5209 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5210 I915_WRITE(CHV_CANVAS(pipe), 0);
5211 }
5212
5213 i9xx_set_pipeconf(intel_crtc);
5214
5215 intel_crtc->active = true;
5216
5217 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5218
5219 for_each_encoder_on_crtc(dev, crtc, encoder)
5220 if (encoder->pre_pll_enable)
5221 encoder->pre_pll_enable(encoder);
5222
5223 if (!is_dsi) {
5224 if (IS_CHERRYVIEW(dev))
5225 chv_enable_pll(intel_crtc, intel_crtc->config);
5226 else
5227 vlv_enable_pll(intel_crtc, intel_crtc->config);
5228 }
5229
5230 for_each_encoder_on_crtc(dev, crtc, encoder)
5231 if (encoder->pre_enable)
5232 encoder->pre_enable(encoder);
5233
5234 i9xx_pfit_enable(intel_crtc);
5235
5236 intel_crtc_load_lut(crtc);
5237
5238 intel_update_watermarks(crtc);
5239 intel_enable_pipe(intel_crtc);
5240
5241 assert_vblank_disabled(crtc);
5242 drm_crtc_vblank_on(crtc);
5243
5244 for_each_encoder_on_crtc(dev, crtc, encoder)
5245 encoder->enable(encoder);
5246
5247 intel_crtc_enable_planes(crtc);
5248
5249 /* Underruns don't raise interrupts, so check manually. */
5250 i9xx_check_fifo_underruns(dev_priv);
5251 }
5252
5253 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5254 {
5255 struct drm_device *dev = crtc->base.dev;
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257
5258 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5259 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5260 }
5261
5262 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5263 {
5264 struct drm_device *dev = crtc->dev;
5265 struct drm_i915_private *dev_priv = to_i915(dev);
5266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5267 struct intel_encoder *encoder;
5268 int pipe = intel_crtc->pipe;
5269
5270 WARN_ON(!crtc->state->enable);
5271
5272 if (intel_crtc->active)
5273 return;
5274
5275 i9xx_set_pll_dividers(intel_crtc);
5276
5277 if (intel_crtc->config->has_dp_encoder)
5278 intel_dp_set_m_n(intel_crtc, M1_N1);
5279
5280 intel_set_pipe_timings(intel_crtc);
5281
5282 i9xx_set_pipeconf(intel_crtc);
5283
5284 intel_crtc->active = true;
5285
5286 if (!IS_GEN2(dev))
5287 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5288
5289 for_each_encoder_on_crtc(dev, crtc, encoder)
5290 if (encoder->pre_enable)
5291 encoder->pre_enable(encoder);
5292
5293 i9xx_enable_pll(intel_crtc);
5294
5295 i9xx_pfit_enable(intel_crtc);
5296
5297 intel_crtc_load_lut(crtc);
5298
5299 intel_update_watermarks(crtc);
5300 intel_enable_pipe(intel_crtc);
5301
5302 assert_vblank_disabled(crtc);
5303 drm_crtc_vblank_on(crtc);
5304
5305 for_each_encoder_on_crtc(dev, crtc, encoder)
5306 encoder->enable(encoder);
5307
5308 intel_crtc_enable_planes(crtc);
5309
5310 /*
5311 * Gen2 reports pipe underruns whenever all planes are disabled.
5312 * So don't enable underrun reporting before at least some planes
5313 * are enabled.
5314 * FIXME: Need to fix the logic to work when we turn off all planes
5315 * but leave the pipe running.
5316 */
5317 if (IS_GEN2(dev))
5318 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5319
5320 /* Underruns don't raise interrupts, so check manually. */
5321 i9xx_check_fifo_underruns(dev_priv);
5322 }
5323
5324 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5325 {
5326 struct drm_device *dev = crtc->base.dev;
5327 struct drm_i915_private *dev_priv = dev->dev_private;
5328
5329 if (!crtc->config->gmch_pfit.control)
5330 return;
5331
5332 assert_pipe_disabled(dev_priv, crtc->pipe);
5333
5334 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5335 I915_READ(PFIT_CONTROL));
5336 I915_WRITE(PFIT_CONTROL, 0);
5337 }
5338
5339 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5340 {
5341 struct drm_device *dev = crtc->dev;
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5344 struct intel_encoder *encoder;
5345 int pipe = intel_crtc->pipe;
5346
5347 if (!intel_crtc->active)
5348 return;
5349
5350 /*
5351 * Gen2 reports pipe underruns whenever all planes are disabled.
5352 * So diasble underrun reporting before all the planes get disabled.
5353 * FIXME: Need to fix the logic to work when we turn off all planes
5354 * but leave the pipe running.
5355 */
5356 if (IS_GEN2(dev))
5357 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5358
5359 /*
5360 * Vblank time updates from the shadow to live plane control register
5361 * are blocked if the memory self-refresh mode is active at that
5362 * moment. So to make sure the plane gets truly disabled, disable
5363 * first the self-refresh mode. The self-refresh enable bit in turn
5364 * will be checked/applied by the HW only at the next frame start
5365 * event which is after the vblank start event, so we need to have a
5366 * wait-for-vblank between disabling the plane and the pipe.
5367 */
5368 intel_set_memory_cxsr(dev_priv, false);
5369 intel_crtc_disable_planes(crtc);
5370
5371 /*
5372 * On gen2 planes are double buffered but the pipe isn't, so we must
5373 * wait for planes to fully turn off before disabling the pipe.
5374 * We also need to wait on all gmch platforms because of the
5375 * self-refresh mode constraint explained above.
5376 */
5377 intel_wait_for_vblank(dev, pipe);
5378
5379 for_each_encoder_on_crtc(dev, crtc, encoder)
5380 encoder->disable(encoder);
5381
5382 drm_crtc_vblank_off(crtc);
5383 assert_vblank_disabled(crtc);
5384
5385 intel_disable_pipe(intel_crtc);
5386
5387 i9xx_pfit_disable(intel_crtc);
5388
5389 for_each_encoder_on_crtc(dev, crtc, encoder)
5390 if (encoder->post_disable)
5391 encoder->post_disable(encoder);
5392
5393 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5394 if (IS_CHERRYVIEW(dev))
5395 chv_disable_pll(dev_priv, pipe);
5396 else if (IS_VALLEYVIEW(dev))
5397 vlv_disable_pll(dev_priv, pipe);
5398 else
5399 i9xx_disable_pll(intel_crtc);
5400 }
5401
5402 if (!IS_GEN2(dev))
5403 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5404
5405 intel_crtc->active = false;
5406 intel_update_watermarks(crtc);
5407
5408 mutex_lock(&dev->struct_mutex);
5409 intel_fbc_update(dev);
5410 mutex_unlock(&dev->struct_mutex);
5411 }
5412
5413 static void i9xx_crtc_off(struct drm_crtc *crtc)
5414 {
5415 }
5416
5417 /* Master function to enable/disable CRTC and corresponding power wells */
5418 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5419 {
5420 struct drm_device *dev = crtc->dev;
5421 struct drm_i915_private *dev_priv = dev->dev_private;
5422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5423 enum intel_display_power_domain domain;
5424 unsigned long domains;
5425
5426 if (enable) {
5427 if (!intel_crtc->active) {
5428 domains = get_crtc_power_domains(crtc);
5429 for_each_power_domain(domain, domains)
5430 intel_display_power_get(dev_priv, domain);
5431 intel_crtc->enabled_power_domains = domains;
5432
5433 dev_priv->display.crtc_enable(crtc);
5434 }
5435 } else {
5436 if (intel_crtc->active) {
5437 dev_priv->display.crtc_disable(crtc);
5438
5439 domains = intel_crtc->enabled_power_domains;
5440 for_each_power_domain(domain, domains)
5441 intel_display_power_put(dev_priv, domain);
5442 intel_crtc->enabled_power_domains = 0;
5443 }
5444 }
5445 }
5446
5447 /**
5448 * Sets the power management mode of the pipe and plane.
5449 */
5450 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5451 {
5452 struct drm_device *dev = crtc->dev;
5453 struct intel_encoder *intel_encoder;
5454 bool enable = false;
5455
5456 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5457 enable |= intel_encoder->connectors_active;
5458
5459 intel_crtc_control(crtc, enable);
5460 }
5461
5462 static void intel_crtc_disable(struct drm_crtc *crtc)
5463 {
5464 struct drm_device *dev = crtc->dev;
5465 struct drm_connector *connector;
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467
5468 /* crtc should still be enabled when we disable it. */
5469 WARN_ON(!crtc->state->enable);
5470
5471 dev_priv->display.crtc_disable(crtc);
5472 dev_priv->display.off(crtc);
5473
5474 crtc->primary->funcs->disable_plane(crtc->primary);
5475
5476 /* Update computed state. */
5477 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5478 if (!connector->encoder || !connector->encoder->crtc)
5479 continue;
5480
5481 if (connector->encoder->crtc != crtc)
5482 continue;
5483
5484 connector->dpms = DRM_MODE_DPMS_OFF;
5485 to_intel_encoder(connector->encoder)->connectors_active = false;
5486 }
5487 }
5488
5489 void intel_encoder_destroy(struct drm_encoder *encoder)
5490 {
5491 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5492
5493 drm_encoder_cleanup(encoder);
5494 kfree(intel_encoder);
5495 }
5496
5497 /* Simple dpms helper for encoders with just one connector, no cloning and only
5498 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5499 * state of the entire output pipe. */
5500 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5501 {
5502 if (mode == DRM_MODE_DPMS_ON) {
5503 encoder->connectors_active = true;
5504
5505 intel_crtc_update_dpms(encoder->base.crtc);
5506 } else {
5507 encoder->connectors_active = false;
5508
5509 intel_crtc_update_dpms(encoder->base.crtc);
5510 }
5511 }
5512
5513 /* Cross check the actual hw state with our own modeset state tracking (and it's
5514 * internal consistency). */
5515 static void intel_connector_check_state(struct intel_connector *connector)
5516 {
5517 if (connector->get_hw_state(connector)) {
5518 struct intel_encoder *encoder = connector->encoder;
5519 struct drm_crtc *crtc;
5520 bool encoder_enabled;
5521 enum pipe pipe;
5522
5523 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5524 connector->base.base.id,
5525 connector->base.name);
5526
5527 /* there is no real hw state for MST connectors */
5528 if (connector->mst_port)
5529 return;
5530
5531 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5532 "wrong connector dpms state\n");
5533 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5534 "active connector not linked to encoder\n");
5535
5536 if (encoder) {
5537 I915_STATE_WARN(!encoder->connectors_active,
5538 "encoder->connectors_active not set\n");
5539
5540 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5541 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5542 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5543 return;
5544
5545 crtc = encoder->base.crtc;
5546
5547 I915_STATE_WARN(!crtc->state->enable,
5548 "crtc not enabled\n");
5549 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5550 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5551 "encoder active on the wrong pipe\n");
5552 }
5553 }
5554 }
5555
5556 /* Even simpler default implementation, if there's really no special case to
5557 * consider. */
5558 void intel_connector_dpms(struct drm_connector *connector, int mode)
5559 {
5560 /* All the simple cases only support two dpms states. */
5561 if (mode != DRM_MODE_DPMS_ON)
5562 mode = DRM_MODE_DPMS_OFF;
5563
5564 if (mode == connector->dpms)
5565 return;
5566
5567 connector->dpms = mode;
5568
5569 /* Only need to change hw state when actually enabled */
5570 if (connector->encoder)
5571 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5572
5573 intel_modeset_check_state(connector->dev);
5574 }
5575
5576 /* Simple connector->get_hw_state implementation for encoders that support only
5577 * one connector and no cloning and hence the encoder state determines the state
5578 * of the connector. */
5579 bool intel_connector_get_hw_state(struct intel_connector *connector)
5580 {
5581 enum pipe pipe = 0;
5582 struct intel_encoder *encoder = connector->encoder;
5583
5584 return encoder->get_hw_state(encoder, &pipe);
5585 }
5586
5587 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5588 {
5589 struct intel_crtc *crtc =
5590 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5591
5592 if (crtc->base.state->enable &&
5593 crtc->config->has_pch_encoder)
5594 return crtc->config->fdi_lanes;
5595
5596 return 0;
5597 }
5598
5599 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5600 struct intel_crtc_state *pipe_config)
5601 {
5602 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5603 pipe_name(pipe), pipe_config->fdi_lanes);
5604 if (pipe_config->fdi_lanes > 4) {
5605 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5606 pipe_name(pipe), pipe_config->fdi_lanes);
5607 return false;
5608 }
5609
5610 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5611 if (pipe_config->fdi_lanes > 2) {
5612 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5613 pipe_config->fdi_lanes);
5614 return false;
5615 } else {
5616 return true;
5617 }
5618 }
5619
5620 if (INTEL_INFO(dev)->num_pipes == 2)
5621 return true;
5622
5623 /* Ivybridge 3 pipe is really complicated */
5624 switch (pipe) {
5625 case PIPE_A:
5626 return true;
5627 case PIPE_B:
5628 if (pipe_config->fdi_lanes > 2 &&
5629 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5630 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5631 pipe_name(pipe), pipe_config->fdi_lanes);
5632 return false;
5633 }
5634 return true;
5635 case PIPE_C:
5636 if (pipe_config->fdi_lanes > 2) {
5637 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5638 pipe_name(pipe), pipe_config->fdi_lanes);
5639 return false;
5640 }
5641 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5642 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5643 return false;
5644 }
5645 return true;
5646 default:
5647 BUG();
5648 }
5649 }
5650
5651 #define RETRY 1
5652 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5653 struct intel_crtc_state *pipe_config)
5654 {
5655 struct drm_device *dev = intel_crtc->base.dev;
5656 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5657 int lane, link_bw, fdi_dotclock;
5658 bool setup_ok, needs_recompute = false;
5659
5660 retry:
5661 /* FDI is a binary signal running at ~2.7GHz, encoding
5662 * each output octet as 10 bits. The actual frequency
5663 * is stored as a divider into a 100MHz clock, and the
5664 * mode pixel clock is stored in units of 1KHz.
5665 * Hence the bw of each lane in terms of the mode signal
5666 * is:
5667 */
5668 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5669
5670 fdi_dotclock = adjusted_mode->crtc_clock;
5671
5672 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5673 pipe_config->pipe_bpp);
5674
5675 pipe_config->fdi_lanes = lane;
5676
5677 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5678 link_bw, &pipe_config->fdi_m_n);
5679
5680 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5681 intel_crtc->pipe, pipe_config);
5682 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5683 pipe_config->pipe_bpp -= 2*3;
5684 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5685 pipe_config->pipe_bpp);
5686 needs_recompute = true;
5687 pipe_config->bw_constrained = true;
5688
5689 goto retry;
5690 }
5691
5692 if (needs_recompute)
5693 return RETRY;
5694
5695 return setup_ok ? 0 : -EINVAL;
5696 }
5697
5698 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5699 struct intel_crtc_state *pipe_config)
5700 {
5701 pipe_config->ips_enabled = i915.enable_ips &&
5702 hsw_crtc_supports_ips(crtc) &&
5703 pipe_config->pipe_bpp <= 24;
5704 }
5705
5706 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5707 struct intel_crtc_state *pipe_config)
5708 {
5709 struct drm_device *dev = crtc->base.dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5712
5713 /* FIXME should check pixel clock limits on all platforms */
5714 if (INTEL_INFO(dev)->gen < 4) {
5715 int clock_limit =
5716 dev_priv->display.get_display_clock_speed(dev);
5717
5718 /*
5719 * Enable pixel doubling when the dot clock
5720 * is > 90% of the (display) core speed.
5721 *
5722 * GDG double wide on either pipe,
5723 * otherwise pipe A only.
5724 */
5725 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5726 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5727 clock_limit *= 2;
5728 pipe_config->double_wide = true;
5729 }
5730
5731 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5732 return -EINVAL;
5733 }
5734
5735 /*
5736 * Pipe horizontal size must be even in:
5737 * - DVO ganged mode
5738 * - LVDS dual channel mode
5739 * - Double wide pipe
5740 */
5741 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5742 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5743 pipe_config->pipe_src_w &= ~1;
5744
5745 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5746 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5747 */
5748 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5749 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5750 return -EINVAL;
5751
5752 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5753 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5754 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5755 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5756 * for lvds. */
5757 pipe_config->pipe_bpp = 8*3;
5758 }
5759
5760 if (HAS_IPS(dev))
5761 hsw_compute_ips_config(crtc, pipe_config);
5762
5763 if (pipe_config->has_pch_encoder)
5764 return ironlake_fdi_compute_config(crtc, pipe_config);
5765
5766 return 0;
5767 }
5768
5769 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5770 {
5771 struct drm_i915_private *dev_priv = dev->dev_private;
5772 u32 val;
5773 int divider;
5774
5775 if (dev_priv->hpll_freq == 0)
5776 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5777
5778 mutex_lock(&dev_priv->dpio_lock);
5779 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5780 mutex_unlock(&dev_priv->dpio_lock);
5781
5782 divider = val & DISPLAY_FREQUENCY_VALUES;
5783
5784 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5785 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5786 "cdclk change in progress\n");
5787
5788 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5789 }
5790
5791 static int i945_get_display_clock_speed(struct drm_device *dev)
5792 {
5793 return 400000;
5794 }
5795
5796 static int i915_get_display_clock_speed(struct drm_device *dev)
5797 {
5798 return 333000;
5799 }
5800
5801 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5802 {
5803 return 200000;
5804 }
5805
5806 static int pnv_get_display_clock_speed(struct drm_device *dev)
5807 {
5808 u16 gcfgc = 0;
5809
5810 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5811
5812 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5813 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5814 return 267000;
5815 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5816 return 333000;
5817 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5818 return 444000;
5819 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5820 return 200000;
5821 default:
5822 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5823 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5824 return 133000;
5825 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5826 return 167000;
5827 }
5828 }
5829
5830 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5831 {
5832 u16 gcfgc = 0;
5833
5834 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5835
5836 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5837 return 133000;
5838 else {
5839 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5840 case GC_DISPLAY_CLOCK_333_MHZ:
5841 return 333000;
5842 default:
5843 case GC_DISPLAY_CLOCK_190_200_MHZ:
5844 return 190000;
5845 }
5846 }
5847 }
5848
5849 static int i865_get_display_clock_speed(struct drm_device *dev)
5850 {
5851 return 266000;
5852 }
5853
5854 static int i855_get_display_clock_speed(struct drm_device *dev)
5855 {
5856 u16 hpllcc = 0;
5857 /* Assume that the hardware is in the high speed state. This
5858 * should be the default.
5859 */
5860 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5861 case GC_CLOCK_133_200:
5862 case GC_CLOCK_100_200:
5863 return 200000;
5864 case GC_CLOCK_166_250:
5865 return 250000;
5866 case GC_CLOCK_100_133:
5867 return 133000;
5868 }
5869
5870 /* Shouldn't happen */
5871 return 0;
5872 }
5873
5874 static int i830_get_display_clock_speed(struct drm_device *dev)
5875 {
5876 return 133000;
5877 }
5878
5879 static void
5880 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5881 {
5882 while (*num > DATA_LINK_M_N_MASK ||
5883 *den > DATA_LINK_M_N_MASK) {
5884 *num >>= 1;
5885 *den >>= 1;
5886 }
5887 }
5888
5889 static void compute_m_n(unsigned int m, unsigned int n,
5890 uint32_t *ret_m, uint32_t *ret_n)
5891 {
5892 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5893 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5894 intel_reduce_m_n_ratio(ret_m, ret_n);
5895 }
5896
5897 void
5898 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5899 int pixel_clock, int link_clock,
5900 struct intel_link_m_n *m_n)
5901 {
5902 m_n->tu = 64;
5903
5904 compute_m_n(bits_per_pixel * pixel_clock,
5905 link_clock * nlanes * 8,
5906 &m_n->gmch_m, &m_n->gmch_n);
5907
5908 compute_m_n(pixel_clock, link_clock,
5909 &m_n->link_m, &m_n->link_n);
5910 }
5911
5912 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5913 {
5914 if (i915.panel_use_ssc >= 0)
5915 return i915.panel_use_ssc != 0;
5916 return dev_priv->vbt.lvds_use_ssc
5917 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5918 }
5919
5920 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5921 {
5922 struct drm_device *dev = crtc->base.dev;
5923 struct drm_i915_private *dev_priv = dev->dev_private;
5924 int refclk;
5925
5926 if (IS_VALLEYVIEW(dev)) {
5927 refclk = 100000;
5928 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5929 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5930 refclk = dev_priv->vbt.lvds_ssc_freq;
5931 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5932 } else if (!IS_GEN2(dev)) {
5933 refclk = 96000;
5934 } else {
5935 refclk = 48000;
5936 }
5937
5938 return refclk;
5939 }
5940
5941 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5942 {
5943 return (1 << dpll->n) << 16 | dpll->m2;
5944 }
5945
5946 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5947 {
5948 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5949 }
5950
5951 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5952 struct intel_crtc_state *crtc_state,
5953 intel_clock_t *reduced_clock)
5954 {
5955 struct drm_device *dev = crtc->base.dev;
5956 u32 fp, fp2 = 0;
5957
5958 if (IS_PINEVIEW(dev)) {
5959 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5960 if (reduced_clock)
5961 fp2 = pnv_dpll_compute_fp(reduced_clock);
5962 } else {
5963 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5964 if (reduced_clock)
5965 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5966 }
5967
5968 crtc_state->dpll_hw_state.fp0 = fp;
5969
5970 crtc->lowfreq_avail = false;
5971 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5972 reduced_clock && i915.powersave) {
5973 crtc_state->dpll_hw_state.fp1 = fp2;
5974 crtc->lowfreq_avail = true;
5975 } else {
5976 crtc_state->dpll_hw_state.fp1 = fp;
5977 }
5978 }
5979
5980 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5981 pipe)
5982 {
5983 u32 reg_val;
5984
5985 /*
5986 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5987 * and set it to a reasonable value instead.
5988 */
5989 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5990 reg_val &= 0xffffff00;
5991 reg_val |= 0x00000030;
5992 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5993
5994 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5995 reg_val &= 0x8cffffff;
5996 reg_val = 0x8c000000;
5997 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5998
5999 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6000 reg_val &= 0xffffff00;
6001 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6002
6003 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6004 reg_val &= 0x00ffffff;
6005 reg_val |= 0xb0000000;
6006 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6007 }
6008
6009 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6010 struct intel_link_m_n *m_n)
6011 {
6012 struct drm_device *dev = crtc->base.dev;
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014 int pipe = crtc->pipe;
6015
6016 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6017 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6018 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6019 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6020 }
6021
6022 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6023 struct intel_link_m_n *m_n,
6024 struct intel_link_m_n *m2_n2)
6025 {
6026 struct drm_device *dev = crtc->base.dev;
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028 int pipe = crtc->pipe;
6029 enum transcoder transcoder = crtc->config->cpu_transcoder;
6030
6031 if (INTEL_INFO(dev)->gen >= 5) {
6032 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6033 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6034 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6035 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6036 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6037 * for gen < 8) and if DRRS is supported (to make sure the
6038 * registers are not unnecessarily accessed).
6039 */
6040 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6041 crtc->config->has_drrs) {
6042 I915_WRITE(PIPE_DATA_M2(transcoder),
6043 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6044 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6045 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6046 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6047 }
6048 } else {
6049 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6050 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6051 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6052 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6053 }
6054 }
6055
6056 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6057 {
6058 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6059
6060 if (m_n == M1_N1) {
6061 dp_m_n = &crtc->config->dp_m_n;
6062 dp_m2_n2 = &crtc->config->dp_m2_n2;
6063 } else if (m_n == M2_N2) {
6064
6065 /*
6066 * M2_N2 registers are not supported. Hence m2_n2 divider value
6067 * needs to be programmed into M1_N1.
6068 */
6069 dp_m_n = &crtc->config->dp_m2_n2;
6070 } else {
6071 DRM_ERROR("Unsupported divider value\n");
6072 return;
6073 }
6074
6075 if (crtc->config->has_pch_encoder)
6076 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6077 else
6078 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6079 }
6080
6081 static void vlv_update_pll(struct intel_crtc *crtc,
6082 struct intel_crtc_state *pipe_config)
6083 {
6084 u32 dpll, dpll_md;
6085
6086 /*
6087 * Enable DPIO clock input. We should never disable the reference
6088 * clock for pipe B, since VGA hotplug / manual detection depends
6089 * on it.
6090 */
6091 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6092 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6093 /* We should never disable this, set it here for state tracking */
6094 if (crtc->pipe == PIPE_B)
6095 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6096 dpll |= DPLL_VCO_ENABLE;
6097 pipe_config->dpll_hw_state.dpll = dpll;
6098
6099 dpll_md = (pipe_config->pixel_multiplier - 1)
6100 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6101 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6102 }
6103
6104 static void vlv_prepare_pll(struct intel_crtc *crtc,
6105 const struct intel_crtc_state *pipe_config)
6106 {
6107 struct drm_device *dev = crtc->base.dev;
6108 struct drm_i915_private *dev_priv = dev->dev_private;
6109 int pipe = crtc->pipe;
6110 u32 mdiv;
6111 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6112 u32 coreclk, reg_val;
6113
6114 mutex_lock(&dev_priv->dpio_lock);
6115
6116 bestn = pipe_config->dpll.n;
6117 bestm1 = pipe_config->dpll.m1;
6118 bestm2 = pipe_config->dpll.m2;
6119 bestp1 = pipe_config->dpll.p1;
6120 bestp2 = pipe_config->dpll.p2;
6121
6122 /* See eDP HDMI DPIO driver vbios notes doc */
6123
6124 /* PLL B needs special handling */
6125 if (pipe == PIPE_B)
6126 vlv_pllb_recal_opamp(dev_priv, pipe);
6127
6128 /* Set up Tx target for periodic Rcomp update */
6129 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6130
6131 /* Disable target IRef on PLL */
6132 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6133 reg_val &= 0x00ffffff;
6134 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6135
6136 /* Disable fast lock */
6137 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6138
6139 /* Set idtafcrecal before PLL is enabled */
6140 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6141 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6142 mdiv |= ((bestn << DPIO_N_SHIFT));
6143 mdiv |= (1 << DPIO_K_SHIFT);
6144
6145 /*
6146 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6147 * but we don't support that).
6148 * Note: don't use the DAC post divider as it seems unstable.
6149 */
6150 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6151 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6152
6153 mdiv |= DPIO_ENABLE_CALIBRATION;
6154 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6155
6156 /* Set HBR and RBR LPF coefficients */
6157 if (pipe_config->port_clock == 162000 ||
6158 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6159 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6160 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6161 0x009f0003);
6162 else
6163 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6164 0x00d0000f);
6165
6166 if (pipe_config->has_dp_encoder) {
6167 /* Use SSC source */
6168 if (pipe == PIPE_A)
6169 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6170 0x0df40000);
6171 else
6172 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6173 0x0df70000);
6174 } else { /* HDMI or VGA */
6175 /* Use bend source */
6176 if (pipe == PIPE_A)
6177 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6178 0x0df70000);
6179 else
6180 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6181 0x0df40000);
6182 }
6183
6184 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6185 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6186 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6187 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6188 coreclk |= 0x01000000;
6189 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6190
6191 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6192 mutex_unlock(&dev_priv->dpio_lock);
6193 }
6194
6195 static void chv_update_pll(struct intel_crtc *crtc,
6196 struct intel_crtc_state *pipe_config)
6197 {
6198 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6199 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6200 DPLL_VCO_ENABLE;
6201 if (crtc->pipe != PIPE_A)
6202 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6203
6204 pipe_config->dpll_hw_state.dpll_md =
6205 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6206 }
6207
6208 static void chv_prepare_pll(struct intel_crtc *crtc,
6209 const struct intel_crtc_state *pipe_config)
6210 {
6211 struct drm_device *dev = crtc->base.dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 int pipe = crtc->pipe;
6214 int dpll_reg = DPLL(crtc->pipe);
6215 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6216 u32 loopfilter, tribuf_calcntr;
6217 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6218 u32 dpio_val;
6219 int vco;
6220
6221 bestn = pipe_config->dpll.n;
6222 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6223 bestm1 = pipe_config->dpll.m1;
6224 bestm2 = pipe_config->dpll.m2 >> 22;
6225 bestp1 = pipe_config->dpll.p1;
6226 bestp2 = pipe_config->dpll.p2;
6227 vco = pipe_config->dpll.vco;
6228 dpio_val = 0;
6229 loopfilter = 0;
6230
6231 /*
6232 * Enable Refclk and SSC
6233 */
6234 I915_WRITE(dpll_reg,
6235 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6236
6237 mutex_lock(&dev_priv->dpio_lock);
6238
6239 /* p1 and p2 divider */
6240 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6241 5 << DPIO_CHV_S1_DIV_SHIFT |
6242 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6243 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6244 1 << DPIO_CHV_K_DIV_SHIFT);
6245
6246 /* Feedback post-divider - m2 */
6247 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6248
6249 /* Feedback refclk divider - n and m1 */
6250 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6251 DPIO_CHV_M1_DIV_BY_2 |
6252 1 << DPIO_CHV_N_DIV_SHIFT);
6253
6254 /* M2 fraction division */
6255 if (bestm2_frac)
6256 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6257
6258 /* M2 fraction division enable */
6259 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6260 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6261 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6262 if (bestm2_frac)
6263 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6264 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6265
6266 /* Program digital lock detect threshold */
6267 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6268 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6269 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6270 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6271 if (!bestm2_frac)
6272 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6273 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6274
6275 /* Loop filter */
6276 if (vco == 5400000) {
6277 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6278 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6279 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6280 tribuf_calcntr = 0x9;
6281 } else if (vco <= 6200000) {
6282 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6283 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6284 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6285 tribuf_calcntr = 0x9;
6286 } else if (vco <= 6480000) {
6287 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6288 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6289 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6290 tribuf_calcntr = 0x8;
6291 } else {
6292 /* Not supported. Apply the same limits as in the max case */
6293 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6294 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6295 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6296 tribuf_calcntr = 0;
6297 }
6298 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6299
6300 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6301 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6302 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6303 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6304
6305 /* AFC Recal */
6306 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6307 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6308 DPIO_AFC_RECAL);
6309
6310 mutex_unlock(&dev_priv->dpio_lock);
6311 }
6312
6313 /**
6314 * vlv_force_pll_on - forcibly enable just the PLL
6315 * @dev_priv: i915 private structure
6316 * @pipe: pipe PLL to enable
6317 * @dpll: PLL configuration
6318 *
6319 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6320 * in cases where we need the PLL enabled even when @pipe is not going to
6321 * be enabled.
6322 */
6323 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6324 const struct dpll *dpll)
6325 {
6326 struct intel_crtc *crtc =
6327 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6328 struct intel_crtc_state pipe_config = {
6329 .pixel_multiplier = 1,
6330 .dpll = *dpll,
6331 };
6332
6333 if (IS_CHERRYVIEW(dev)) {
6334 chv_update_pll(crtc, &pipe_config);
6335 chv_prepare_pll(crtc, &pipe_config);
6336 chv_enable_pll(crtc, &pipe_config);
6337 } else {
6338 vlv_update_pll(crtc, &pipe_config);
6339 vlv_prepare_pll(crtc, &pipe_config);
6340 vlv_enable_pll(crtc, &pipe_config);
6341 }
6342 }
6343
6344 /**
6345 * vlv_force_pll_off - forcibly disable just the PLL
6346 * @dev_priv: i915 private structure
6347 * @pipe: pipe PLL to disable
6348 *
6349 * Disable the PLL for @pipe. To be used in cases where we need
6350 * the PLL enabled even when @pipe is not going to be enabled.
6351 */
6352 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6353 {
6354 if (IS_CHERRYVIEW(dev))
6355 chv_disable_pll(to_i915(dev), pipe);
6356 else
6357 vlv_disable_pll(to_i915(dev), pipe);
6358 }
6359
6360 static void i9xx_update_pll(struct intel_crtc *crtc,
6361 struct intel_crtc_state *crtc_state,
6362 intel_clock_t *reduced_clock,
6363 int num_connectors)
6364 {
6365 struct drm_device *dev = crtc->base.dev;
6366 struct drm_i915_private *dev_priv = dev->dev_private;
6367 u32 dpll;
6368 bool is_sdvo;
6369 struct dpll *clock = &crtc_state->dpll;
6370
6371 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6372
6373 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6374 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6375
6376 dpll = DPLL_VGA_MODE_DIS;
6377
6378 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6379 dpll |= DPLLB_MODE_LVDS;
6380 else
6381 dpll |= DPLLB_MODE_DAC_SERIAL;
6382
6383 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6384 dpll |= (crtc_state->pixel_multiplier - 1)
6385 << SDVO_MULTIPLIER_SHIFT_HIRES;
6386 }
6387
6388 if (is_sdvo)
6389 dpll |= DPLL_SDVO_HIGH_SPEED;
6390
6391 if (crtc_state->has_dp_encoder)
6392 dpll |= DPLL_SDVO_HIGH_SPEED;
6393
6394 /* compute bitmask from p1 value */
6395 if (IS_PINEVIEW(dev))
6396 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6397 else {
6398 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6399 if (IS_G4X(dev) && reduced_clock)
6400 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6401 }
6402 switch (clock->p2) {
6403 case 5:
6404 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6405 break;
6406 case 7:
6407 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6408 break;
6409 case 10:
6410 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6411 break;
6412 case 14:
6413 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6414 break;
6415 }
6416 if (INTEL_INFO(dev)->gen >= 4)
6417 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6418
6419 if (crtc_state->sdvo_tv_clock)
6420 dpll |= PLL_REF_INPUT_TVCLKINBC;
6421 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6422 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6423 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6424 else
6425 dpll |= PLL_REF_INPUT_DREFCLK;
6426
6427 dpll |= DPLL_VCO_ENABLE;
6428 crtc_state->dpll_hw_state.dpll = dpll;
6429
6430 if (INTEL_INFO(dev)->gen >= 4) {
6431 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6432 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6433 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6434 }
6435 }
6436
6437 static void i8xx_update_pll(struct intel_crtc *crtc,
6438 struct intel_crtc_state *crtc_state,
6439 intel_clock_t *reduced_clock,
6440 int num_connectors)
6441 {
6442 struct drm_device *dev = crtc->base.dev;
6443 struct drm_i915_private *dev_priv = dev->dev_private;
6444 u32 dpll;
6445 struct dpll *clock = &crtc_state->dpll;
6446
6447 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6448
6449 dpll = DPLL_VGA_MODE_DIS;
6450
6451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6452 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6453 } else {
6454 if (clock->p1 == 2)
6455 dpll |= PLL_P1_DIVIDE_BY_TWO;
6456 else
6457 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6458 if (clock->p2 == 4)
6459 dpll |= PLL_P2_DIVIDE_BY_4;
6460 }
6461
6462 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6463 dpll |= DPLL_DVO_2X_MODE;
6464
6465 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6466 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6467 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6468 else
6469 dpll |= PLL_REF_INPUT_DREFCLK;
6470
6471 dpll |= DPLL_VCO_ENABLE;
6472 crtc_state->dpll_hw_state.dpll = dpll;
6473 }
6474
6475 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6476 {
6477 struct drm_device *dev = intel_crtc->base.dev;
6478 struct drm_i915_private *dev_priv = dev->dev_private;
6479 enum pipe pipe = intel_crtc->pipe;
6480 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6481 struct drm_display_mode *adjusted_mode =
6482 &intel_crtc->config->base.adjusted_mode;
6483 uint32_t crtc_vtotal, crtc_vblank_end;
6484 int vsyncshift = 0;
6485
6486 /* We need to be careful not to changed the adjusted mode, for otherwise
6487 * the hw state checker will get angry at the mismatch. */
6488 crtc_vtotal = adjusted_mode->crtc_vtotal;
6489 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6490
6491 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6492 /* the chip adds 2 halflines automatically */
6493 crtc_vtotal -= 1;
6494 crtc_vblank_end -= 1;
6495
6496 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6497 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6498 else
6499 vsyncshift = adjusted_mode->crtc_hsync_start -
6500 adjusted_mode->crtc_htotal / 2;
6501 if (vsyncshift < 0)
6502 vsyncshift += adjusted_mode->crtc_htotal;
6503 }
6504
6505 if (INTEL_INFO(dev)->gen > 3)
6506 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6507
6508 I915_WRITE(HTOTAL(cpu_transcoder),
6509 (adjusted_mode->crtc_hdisplay - 1) |
6510 ((adjusted_mode->crtc_htotal - 1) << 16));
6511 I915_WRITE(HBLANK(cpu_transcoder),
6512 (adjusted_mode->crtc_hblank_start - 1) |
6513 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6514 I915_WRITE(HSYNC(cpu_transcoder),
6515 (adjusted_mode->crtc_hsync_start - 1) |
6516 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6517
6518 I915_WRITE(VTOTAL(cpu_transcoder),
6519 (adjusted_mode->crtc_vdisplay - 1) |
6520 ((crtc_vtotal - 1) << 16));
6521 I915_WRITE(VBLANK(cpu_transcoder),
6522 (adjusted_mode->crtc_vblank_start - 1) |
6523 ((crtc_vblank_end - 1) << 16));
6524 I915_WRITE(VSYNC(cpu_transcoder),
6525 (adjusted_mode->crtc_vsync_start - 1) |
6526 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6527
6528 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6529 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6530 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6531 * bits. */
6532 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6533 (pipe == PIPE_B || pipe == PIPE_C))
6534 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6535
6536 /* pipesrc controls the size that is scaled from, which should
6537 * always be the user's requested size.
6538 */
6539 I915_WRITE(PIPESRC(pipe),
6540 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6541 (intel_crtc->config->pipe_src_h - 1));
6542 }
6543
6544 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6545 struct intel_crtc_state *pipe_config)
6546 {
6547 struct drm_device *dev = crtc->base.dev;
6548 struct drm_i915_private *dev_priv = dev->dev_private;
6549 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6550 uint32_t tmp;
6551
6552 tmp = I915_READ(HTOTAL(cpu_transcoder));
6553 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6554 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6555 tmp = I915_READ(HBLANK(cpu_transcoder));
6556 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6557 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6558 tmp = I915_READ(HSYNC(cpu_transcoder));
6559 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6560 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6561
6562 tmp = I915_READ(VTOTAL(cpu_transcoder));
6563 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6564 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6565 tmp = I915_READ(VBLANK(cpu_transcoder));
6566 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6567 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6568 tmp = I915_READ(VSYNC(cpu_transcoder));
6569 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6570 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6571
6572 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6573 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6574 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6575 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6576 }
6577
6578 tmp = I915_READ(PIPESRC(crtc->pipe));
6579 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6580 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6581
6582 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6583 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6584 }
6585
6586 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6587 struct intel_crtc_state *pipe_config)
6588 {
6589 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6590 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6591 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6592 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6593
6594 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6595 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6596 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6597 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6598
6599 mode->flags = pipe_config->base.adjusted_mode.flags;
6600
6601 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6602 mode->flags |= pipe_config->base.adjusted_mode.flags;
6603 }
6604
6605 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6606 {
6607 struct drm_device *dev = intel_crtc->base.dev;
6608 struct drm_i915_private *dev_priv = dev->dev_private;
6609 uint32_t pipeconf;
6610
6611 pipeconf = 0;
6612
6613 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6614 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6615 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6616
6617 if (intel_crtc->config->double_wide)
6618 pipeconf |= PIPECONF_DOUBLE_WIDE;
6619
6620 /* only g4x and later have fancy bpc/dither controls */
6621 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6622 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6623 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6624 pipeconf |= PIPECONF_DITHER_EN |
6625 PIPECONF_DITHER_TYPE_SP;
6626
6627 switch (intel_crtc->config->pipe_bpp) {
6628 case 18:
6629 pipeconf |= PIPECONF_6BPC;
6630 break;
6631 case 24:
6632 pipeconf |= PIPECONF_8BPC;
6633 break;
6634 case 30:
6635 pipeconf |= PIPECONF_10BPC;
6636 break;
6637 default:
6638 /* Case prevented by intel_choose_pipe_bpp_dither. */
6639 BUG();
6640 }
6641 }
6642
6643 if (HAS_PIPE_CXSR(dev)) {
6644 if (intel_crtc->lowfreq_avail) {
6645 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6646 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6647 } else {
6648 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6649 }
6650 }
6651
6652 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6653 if (INTEL_INFO(dev)->gen < 4 ||
6654 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6655 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6656 else
6657 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6658 } else
6659 pipeconf |= PIPECONF_PROGRESSIVE;
6660
6661 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6662 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6663
6664 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6665 POSTING_READ(PIPECONF(intel_crtc->pipe));
6666 }
6667
6668 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6669 struct intel_crtc_state *crtc_state)
6670 {
6671 struct drm_device *dev = crtc->base.dev;
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673 int refclk, num_connectors = 0;
6674 intel_clock_t clock, reduced_clock;
6675 bool ok, has_reduced_clock = false;
6676 bool is_lvds = false, is_dsi = false;
6677 struct intel_encoder *encoder;
6678 const intel_limit_t *limit;
6679
6680 for_each_intel_encoder(dev, encoder) {
6681 if (encoder->new_crtc != crtc)
6682 continue;
6683
6684 switch (encoder->type) {
6685 case INTEL_OUTPUT_LVDS:
6686 is_lvds = true;
6687 break;
6688 case INTEL_OUTPUT_DSI:
6689 is_dsi = true;
6690 break;
6691 default:
6692 break;
6693 }
6694
6695 num_connectors++;
6696 }
6697
6698 if (is_dsi)
6699 return 0;
6700
6701 if (!crtc_state->clock_set) {
6702 refclk = i9xx_get_refclk(crtc, num_connectors);
6703
6704 /*
6705 * Returns a set of divisors for the desired target clock with
6706 * the given refclk, or FALSE. The returned values represent
6707 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6708 * 2) / p1 / p2.
6709 */
6710 limit = intel_limit(crtc, refclk);
6711 ok = dev_priv->display.find_dpll(limit, crtc,
6712 crtc_state->port_clock,
6713 refclk, NULL, &clock);
6714 if (!ok) {
6715 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6716 return -EINVAL;
6717 }
6718
6719 if (is_lvds && dev_priv->lvds_downclock_avail) {
6720 /*
6721 * Ensure we match the reduced clock's P to the target
6722 * clock. If the clocks don't match, we can't switch
6723 * the display clock by using the FP0/FP1. In such case
6724 * we will disable the LVDS downclock feature.
6725 */
6726 has_reduced_clock =
6727 dev_priv->display.find_dpll(limit, crtc,
6728 dev_priv->lvds_downclock,
6729 refclk, &clock,
6730 &reduced_clock);
6731 }
6732 /* Compat-code for transition, will disappear. */
6733 crtc_state->dpll.n = clock.n;
6734 crtc_state->dpll.m1 = clock.m1;
6735 crtc_state->dpll.m2 = clock.m2;
6736 crtc_state->dpll.p1 = clock.p1;
6737 crtc_state->dpll.p2 = clock.p2;
6738 }
6739
6740 if (IS_GEN2(dev)) {
6741 i8xx_update_pll(crtc, crtc_state,
6742 has_reduced_clock ? &reduced_clock : NULL,
6743 num_connectors);
6744 } else if (IS_CHERRYVIEW(dev)) {
6745 chv_update_pll(crtc, crtc_state);
6746 } else if (IS_VALLEYVIEW(dev)) {
6747 vlv_update_pll(crtc, crtc_state);
6748 } else {
6749 i9xx_update_pll(crtc, crtc_state,
6750 has_reduced_clock ? &reduced_clock : NULL,
6751 num_connectors);
6752 }
6753
6754 return 0;
6755 }
6756
6757 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6758 struct intel_crtc_state *pipe_config)
6759 {
6760 struct drm_device *dev = crtc->base.dev;
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 uint32_t tmp;
6763
6764 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6765 return;
6766
6767 tmp = I915_READ(PFIT_CONTROL);
6768 if (!(tmp & PFIT_ENABLE))
6769 return;
6770
6771 /* Check whether the pfit is attached to our pipe. */
6772 if (INTEL_INFO(dev)->gen < 4) {
6773 if (crtc->pipe != PIPE_B)
6774 return;
6775 } else {
6776 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6777 return;
6778 }
6779
6780 pipe_config->gmch_pfit.control = tmp;
6781 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6782 if (INTEL_INFO(dev)->gen < 5)
6783 pipe_config->gmch_pfit.lvds_border_bits =
6784 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6785 }
6786
6787 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6788 struct intel_crtc_state *pipe_config)
6789 {
6790 struct drm_device *dev = crtc->base.dev;
6791 struct drm_i915_private *dev_priv = dev->dev_private;
6792 int pipe = pipe_config->cpu_transcoder;
6793 intel_clock_t clock;
6794 u32 mdiv;
6795 int refclk = 100000;
6796
6797 /* In case of MIPI DPLL will not even be used */
6798 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6799 return;
6800
6801 mutex_lock(&dev_priv->dpio_lock);
6802 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6803 mutex_unlock(&dev_priv->dpio_lock);
6804
6805 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6806 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6807 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6808 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6809 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6810
6811 vlv_clock(refclk, &clock);
6812
6813 /* clock.dot is the fast clock */
6814 pipe_config->port_clock = clock.dot / 5;
6815 }
6816
6817 static void
6818 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6819 struct intel_initial_plane_config *plane_config)
6820 {
6821 struct drm_device *dev = crtc->base.dev;
6822 struct drm_i915_private *dev_priv = dev->dev_private;
6823 u32 val, base, offset;
6824 int pipe = crtc->pipe, plane = crtc->plane;
6825 int fourcc, pixel_format;
6826 unsigned int aligned_height;
6827 struct drm_framebuffer *fb;
6828 struct intel_framebuffer *intel_fb;
6829
6830 val = I915_READ(DSPCNTR(plane));
6831 if (!(val & DISPLAY_PLANE_ENABLE))
6832 return;
6833
6834 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6835 if (!intel_fb) {
6836 DRM_DEBUG_KMS("failed to alloc fb\n");
6837 return;
6838 }
6839
6840 fb = &intel_fb->base;
6841
6842 if (INTEL_INFO(dev)->gen >= 4) {
6843 if (val & DISPPLANE_TILED) {
6844 plane_config->tiling = I915_TILING_X;
6845 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6846 }
6847 }
6848
6849 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6850 fourcc = i9xx_format_to_fourcc(pixel_format);
6851 fb->pixel_format = fourcc;
6852 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6853
6854 if (INTEL_INFO(dev)->gen >= 4) {
6855 if (plane_config->tiling)
6856 offset = I915_READ(DSPTILEOFF(plane));
6857 else
6858 offset = I915_READ(DSPLINOFF(plane));
6859 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6860 } else {
6861 base = I915_READ(DSPADDR(plane));
6862 }
6863 plane_config->base = base;
6864
6865 val = I915_READ(PIPESRC(pipe));
6866 fb->width = ((val >> 16) & 0xfff) + 1;
6867 fb->height = ((val >> 0) & 0xfff) + 1;
6868
6869 val = I915_READ(DSPSTRIDE(pipe));
6870 fb->pitches[0] = val & 0xffffffc0;
6871
6872 aligned_height = intel_fb_align_height(dev, fb->height,
6873 fb->pixel_format,
6874 fb->modifier[0]);
6875
6876 plane_config->size = fb->pitches[0] * aligned_height;
6877
6878 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6879 pipe_name(pipe), plane, fb->width, fb->height,
6880 fb->bits_per_pixel, base, fb->pitches[0],
6881 plane_config->size);
6882
6883 plane_config->fb = intel_fb;
6884 }
6885
6886 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6887 struct intel_crtc_state *pipe_config)
6888 {
6889 struct drm_device *dev = crtc->base.dev;
6890 struct drm_i915_private *dev_priv = dev->dev_private;
6891 int pipe = pipe_config->cpu_transcoder;
6892 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6893 intel_clock_t clock;
6894 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6895 int refclk = 100000;
6896
6897 mutex_lock(&dev_priv->dpio_lock);
6898 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6899 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6900 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6901 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6902 mutex_unlock(&dev_priv->dpio_lock);
6903
6904 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6905 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6906 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6907 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6908 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6909
6910 chv_clock(refclk, &clock);
6911
6912 /* clock.dot is the fast clock */
6913 pipe_config->port_clock = clock.dot / 5;
6914 }
6915
6916 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6917 struct intel_crtc_state *pipe_config)
6918 {
6919 struct drm_device *dev = crtc->base.dev;
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 uint32_t tmp;
6922
6923 if (!intel_display_power_is_enabled(dev_priv,
6924 POWER_DOMAIN_PIPE(crtc->pipe)))
6925 return false;
6926
6927 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6928 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6929
6930 tmp = I915_READ(PIPECONF(crtc->pipe));
6931 if (!(tmp & PIPECONF_ENABLE))
6932 return false;
6933
6934 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6935 switch (tmp & PIPECONF_BPC_MASK) {
6936 case PIPECONF_6BPC:
6937 pipe_config->pipe_bpp = 18;
6938 break;
6939 case PIPECONF_8BPC:
6940 pipe_config->pipe_bpp = 24;
6941 break;
6942 case PIPECONF_10BPC:
6943 pipe_config->pipe_bpp = 30;
6944 break;
6945 default:
6946 break;
6947 }
6948 }
6949
6950 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6951 pipe_config->limited_color_range = true;
6952
6953 if (INTEL_INFO(dev)->gen < 4)
6954 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6955
6956 intel_get_pipe_timings(crtc, pipe_config);
6957
6958 i9xx_get_pfit_config(crtc, pipe_config);
6959
6960 if (INTEL_INFO(dev)->gen >= 4) {
6961 tmp = I915_READ(DPLL_MD(crtc->pipe));
6962 pipe_config->pixel_multiplier =
6963 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6964 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6965 pipe_config->dpll_hw_state.dpll_md = tmp;
6966 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6967 tmp = I915_READ(DPLL(crtc->pipe));
6968 pipe_config->pixel_multiplier =
6969 ((tmp & SDVO_MULTIPLIER_MASK)
6970 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6971 } else {
6972 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6973 * port and will be fixed up in the encoder->get_config
6974 * function. */
6975 pipe_config->pixel_multiplier = 1;
6976 }
6977 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6978 if (!IS_VALLEYVIEW(dev)) {
6979 /*
6980 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6981 * on 830. Filter it out here so that we don't
6982 * report errors due to that.
6983 */
6984 if (IS_I830(dev))
6985 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6986
6987 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6988 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6989 } else {
6990 /* Mask out read-only status bits. */
6991 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6992 DPLL_PORTC_READY_MASK |
6993 DPLL_PORTB_READY_MASK);
6994 }
6995
6996 if (IS_CHERRYVIEW(dev))
6997 chv_crtc_clock_get(crtc, pipe_config);
6998 else if (IS_VALLEYVIEW(dev))
6999 vlv_crtc_clock_get(crtc, pipe_config);
7000 else
7001 i9xx_crtc_clock_get(crtc, pipe_config);
7002
7003 return true;
7004 }
7005
7006 static void ironlake_init_pch_refclk(struct drm_device *dev)
7007 {
7008 struct drm_i915_private *dev_priv = dev->dev_private;
7009 struct intel_encoder *encoder;
7010 u32 val, final;
7011 bool has_lvds = false;
7012 bool has_cpu_edp = false;
7013 bool has_panel = false;
7014 bool has_ck505 = false;
7015 bool can_ssc = false;
7016
7017 /* We need to take the global config into account */
7018 for_each_intel_encoder(dev, encoder) {
7019 switch (encoder->type) {
7020 case INTEL_OUTPUT_LVDS:
7021 has_panel = true;
7022 has_lvds = true;
7023 break;
7024 case INTEL_OUTPUT_EDP:
7025 has_panel = true;
7026 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7027 has_cpu_edp = true;
7028 break;
7029 default:
7030 break;
7031 }
7032 }
7033
7034 if (HAS_PCH_IBX(dev)) {
7035 has_ck505 = dev_priv->vbt.display_clock_mode;
7036 can_ssc = has_ck505;
7037 } else {
7038 has_ck505 = false;
7039 can_ssc = true;
7040 }
7041
7042 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7043 has_panel, has_lvds, has_ck505);
7044
7045 /* Ironlake: try to setup display ref clock before DPLL
7046 * enabling. This is only under driver's control after
7047 * PCH B stepping, previous chipset stepping should be
7048 * ignoring this setting.
7049 */
7050 val = I915_READ(PCH_DREF_CONTROL);
7051
7052 /* As we must carefully and slowly disable/enable each source in turn,
7053 * compute the final state we want first and check if we need to
7054 * make any changes at all.
7055 */
7056 final = val;
7057 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7058 if (has_ck505)
7059 final |= DREF_NONSPREAD_CK505_ENABLE;
7060 else
7061 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7062
7063 final &= ~DREF_SSC_SOURCE_MASK;
7064 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7065 final &= ~DREF_SSC1_ENABLE;
7066
7067 if (has_panel) {
7068 final |= DREF_SSC_SOURCE_ENABLE;
7069
7070 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7071 final |= DREF_SSC1_ENABLE;
7072
7073 if (has_cpu_edp) {
7074 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7075 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7076 else
7077 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7078 } else
7079 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7080 } else {
7081 final |= DREF_SSC_SOURCE_DISABLE;
7082 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7083 }
7084
7085 if (final == val)
7086 return;
7087
7088 /* Always enable nonspread source */
7089 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7090
7091 if (has_ck505)
7092 val |= DREF_NONSPREAD_CK505_ENABLE;
7093 else
7094 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7095
7096 if (has_panel) {
7097 val &= ~DREF_SSC_SOURCE_MASK;
7098 val |= DREF_SSC_SOURCE_ENABLE;
7099
7100 /* SSC must be turned on before enabling the CPU output */
7101 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7102 DRM_DEBUG_KMS("Using SSC on panel\n");
7103 val |= DREF_SSC1_ENABLE;
7104 } else
7105 val &= ~DREF_SSC1_ENABLE;
7106
7107 /* Get SSC going before enabling the outputs */
7108 I915_WRITE(PCH_DREF_CONTROL, val);
7109 POSTING_READ(PCH_DREF_CONTROL);
7110 udelay(200);
7111
7112 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7113
7114 /* Enable CPU source on CPU attached eDP */
7115 if (has_cpu_edp) {
7116 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7117 DRM_DEBUG_KMS("Using SSC on eDP\n");
7118 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7119 } else
7120 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7121 } else
7122 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7123
7124 I915_WRITE(PCH_DREF_CONTROL, val);
7125 POSTING_READ(PCH_DREF_CONTROL);
7126 udelay(200);
7127 } else {
7128 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7129
7130 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7131
7132 /* Turn off CPU output */
7133 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7134
7135 I915_WRITE(PCH_DREF_CONTROL, val);
7136 POSTING_READ(PCH_DREF_CONTROL);
7137 udelay(200);
7138
7139 /* Turn off the SSC source */
7140 val &= ~DREF_SSC_SOURCE_MASK;
7141 val |= DREF_SSC_SOURCE_DISABLE;
7142
7143 /* Turn off SSC1 */
7144 val &= ~DREF_SSC1_ENABLE;
7145
7146 I915_WRITE(PCH_DREF_CONTROL, val);
7147 POSTING_READ(PCH_DREF_CONTROL);
7148 udelay(200);
7149 }
7150
7151 BUG_ON(val != final);
7152 }
7153
7154 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7155 {
7156 uint32_t tmp;
7157
7158 tmp = I915_READ(SOUTH_CHICKEN2);
7159 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7160 I915_WRITE(SOUTH_CHICKEN2, tmp);
7161
7162 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7163 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7164 DRM_ERROR("FDI mPHY reset assert timeout\n");
7165
7166 tmp = I915_READ(SOUTH_CHICKEN2);
7167 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7168 I915_WRITE(SOUTH_CHICKEN2, tmp);
7169
7170 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7171 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7172 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7173 }
7174
7175 /* WaMPhyProgramming:hsw */
7176 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7177 {
7178 uint32_t tmp;
7179
7180 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7181 tmp &= ~(0xFF << 24);
7182 tmp |= (0x12 << 24);
7183 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7184
7185 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7186 tmp |= (1 << 11);
7187 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7188
7189 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7190 tmp |= (1 << 11);
7191 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7192
7193 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7194 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7195 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7196
7197 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7198 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7199 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7200
7201 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7202 tmp &= ~(7 << 13);
7203 tmp |= (5 << 13);
7204 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7205
7206 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7207 tmp &= ~(7 << 13);
7208 tmp |= (5 << 13);
7209 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7210
7211 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7212 tmp &= ~0xFF;
7213 tmp |= 0x1C;
7214 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7215
7216 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7217 tmp &= ~0xFF;
7218 tmp |= 0x1C;
7219 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7220
7221 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7222 tmp &= ~(0xFF << 16);
7223 tmp |= (0x1C << 16);
7224 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7225
7226 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7227 tmp &= ~(0xFF << 16);
7228 tmp |= (0x1C << 16);
7229 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7230
7231 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7232 tmp |= (1 << 27);
7233 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7234
7235 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7236 tmp |= (1 << 27);
7237 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7238
7239 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7240 tmp &= ~(0xF << 28);
7241 tmp |= (4 << 28);
7242 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7243
7244 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7245 tmp &= ~(0xF << 28);
7246 tmp |= (4 << 28);
7247 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7248 }
7249
7250 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7251 * Programming" based on the parameters passed:
7252 * - Sequence to enable CLKOUT_DP
7253 * - Sequence to enable CLKOUT_DP without spread
7254 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7255 */
7256 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7257 bool with_fdi)
7258 {
7259 struct drm_i915_private *dev_priv = dev->dev_private;
7260 uint32_t reg, tmp;
7261
7262 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7263 with_spread = true;
7264 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7265 with_fdi, "LP PCH doesn't have FDI\n"))
7266 with_fdi = false;
7267
7268 mutex_lock(&dev_priv->dpio_lock);
7269
7270 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7271 tmp &= ~SBI_SSCCTL_DISABLE;
7272 tmp |= SBI_SSCCTL_PATHALT;
7273 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7274
7275 udelay(24);
7276
7277 if (with_spread) {
7278 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7279 tmp &= ~SBI_SSCCTL_PATHALT;
7280 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7281
7282 if (with_fdi) {
7283 lpt_reset_fdi_mphy(dev_priv);
7284 lpt_program_fdi_mphy(dev_priv);
7285 }
7286 }
7287
7288 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7289 SBI_GEN0 : SBI_DBUFF0;
7290 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7291 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7292 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7293
7294 mutex_unlock(&dev_priv->dpio_lock);
7295 }
7296
7297 /* Sequence to disable CLKOUT_DP */
7298 static void lpt_disable_clkout_dp(struct drm_device *dev)
7299 {
7300 struct drm_i915_private *dev_priv = dev->dev_private;
7301 uint32_t reg, tmp;
7302
7303 mutex_lock(&dev_priv->dpio_lock);
7304
7305 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7306 SBI_GEN0 : SBI_DBUFF0;
7307 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7308 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7309 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7310
7311 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7312 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7313 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7314 tmp |= SBI_SSCCTL_PATHALT;
7315 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7316 udelay(32);
7317 }
7318 tmp |= SBI_SSCCTL_DISABLE;
7319 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7320 }
7321
7322 mutex_unlock(&dev_priv->dpio_lock);
7323 }
7324
7325 static void lpt_init_pch_refclk(struct drm_device *dev)
7326 {
7327 struct intel_encoder *encoder;
7328 bool has_vga = false;
7329
7330 for_each_intel_encoder(dev, encoder) {
7331 switch (encoder->type) {
7332 case INTEL_OUTPUT_ANALOG:
7333 has_vga = true;
7334 break;
7335 default:
7336 break;
7337 }
7338 }
7339
7340 if (has_vga)
7341 lpt_enable_clkout_dp(dev, true, true);
7342 else
7343 lpt_disable_clkout_dp(dev);
7344 }
7345
7346 /*
7347 * Initialize reference clocks when the driver loads
7348 */
7349 void intel_init_pch_refclk(struct drm_device *dev)
7350 {
7351 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7352 ironlake_init_pch_refclk(dev);
7353 else if (HAS_PCH_LPT(dev))
7354 lpt_init_pch_refclk(dev);
7355 }
7356
7357 static int ironlake_get_refclk(struct drm_crtc *crtc)
7358 {
7359 struct drm_device *dev = crtc->dev;
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361 struct intel_encoder *encoder;
7362 int num_connectors = 0;
7363 bool is_lvds = false;
7364
7365 for_each_intel_encoder(dev, encoder) {
7366 if (encoder->new_crtc != to_intel_crtc(crtc))
7367 continue;
7368
7369 switch (encoder->type) {
7370 case INTEL_OUTPUT_LVDS:
7371 is_lvds = true;
7372 break;
7373 default:
7374 break;
7375 }
7376 num_connectors++;
7377 }
7378
7379 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7380 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7381 dev_priv->vbt.lvds_ssc_freq);
7382 return dev_priv->vbt.lvds_ssc_freq;
7383 }
7384
7385 return 120000;
7386 }
7387
7388 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7389 {
7390 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7392 int pipe = intel_crtc->pipe;
7393 uint32_t val;
7394
7395 val = 0;
7396
7397 switch (intel_crtc->config->pipe_bpp) {
7398 case 18:
7399 val |= PIPECONF_6BPC;
7400 break;
7401 case 24:
7402 val |= PIPECONF_8BPC;
7403 break;
7404 case 30:
7405 val |= PIPECONF_10BPC;
7406 break;
7407 case 36:
7408 val |= PIPECONF_12BPC;
7409 break;
7410 default:
7411 /* Case prevented by intel_choose_pipe_bpp_dither. */
7412 BUG();
7413 }
7414
7415 if (intel_crtc->config->dither)
7416 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7417
7418 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7419 val |= PIPECONF_INTERLACED_ILK;
7420 else
7421 val |= PIPECONF_PROGRESSIVE;
7422
7423 if (intel_crtc->config->limited_color_range)
7424 val |= PIPECONF_COLOR_RANGE_SELECT;
7425
7426 I915_WRITE(PIPECONF(pipe), val);
7427 POSTING_READ(PIPECONF(pipe));
7428 }
7429
7430 /*
7431 * Set up the pipe CSC unit.
7432 *
7433 * Currently only full range RGB to limited range RGB conversion
7434 * is supported, but eventually this should handle various
7435 * RGB<->YCbCr scenarios as well.
7436 */
7437 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7438 {
7439 struct drm_device *dev = crtc->dev;
7440 struct drm_i915_private *dev_priv = dev->dev_private;
7441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7442 int pipe = intel_crtc->pipe;
7443 uint16_t coeff = 0x7800; /* 1.0 */
7444
7445 /*
7446 * TODO: Check what kind of values actually come out of the pipe
7447 * with these coeff/postoff values and adjust to get the best
7448 * accuracy. Perhaps we even need to take the bpc value into
7449 * consideration.
7450 */
7451
7452 if (intel_crtc->config->limited_color_range)
7453 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7454
7455 /*
7456 * GY/GU and RY/RU should be the other way around according
7457 * to BSpec, but reality doesn't agree. Just set them up in
7458 * a way that results in the correct picture.
7459 */
7460 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7461 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7462
7463 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7464 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7465
7466 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7467 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7468
7469 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7470 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7471 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7472
7473 if (INTEL_INFO(dev)->gen > 6) {
7474 uint16_t postoff = 0;
7475
7476 if (intel_crtc->config->limited_color_range)
7477 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7478
7479 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7480 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7481 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7482
7483 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7484 } else {
7485 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7486
7487 if (intel_crtc->config->limited_color_range)
7488 mode |= CSC_BLACK_SCREEN_OFFSET;
7489
7490 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7491 }
7492 }
7493
7494 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7495 {
7496 struct drm_device *dev = crtc->dev;
7497 struct drm_i915_private *dev_priv = dev->dev_private;
7498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7499 enum pipe pipe = intel_crtc->pipe;
7500 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7501 uint32_t val;
7502
7503 val = 0;
7504
7505 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7506 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7507
7508 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7509 val |= PIPECONF_INTERLACED_ILK;
7510 else
7511 val |= PIPECONF_PROGRESSIVE;
7512
7513 I915_WRITE(PIPECONF(cpu_transcoder), val);
7514 POSTING_READ(PIPECONF(cpu_transcoder));
7515
7516 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7517 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7518
7519 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7520 val = 0;
7521
7522 switch (intel_crtc->config->pipe_bpp) {
7523 case 18:
7524 val |= PIPEMISC_DITHER_6_BPC;
7525 break;
7526 case 24:
7527 val |= PIPEMISC_DITHER_8_BPC;
7528 break;
7529 case 30:
7530 val |= PIPEMISC_DITHER_10_BPC;
7531 break;
7532 case 36:
7533 val |= PIPEMISC_DITHER_12_BPC;
7534 break;
7535 default:
7536 /* Case prevented by pipe_config_set_bpp. */
7537 BUG();
7538 }
7539
7540 if (intel_crtc->config->dither)
7541 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7542
7543 I915_WRITE(PIPEMISC(pipe), val);
7544 }
7545 }
7546
7547 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7548 struct intel_crtc_state *crtc_state,
7549 intel_clock_t *clock,
7550 bool *has_reduced_clock,
7551 intel_clock_t *reduced_clock)
7552 {
7553 struct drm_device *dev = crtc->dev;
7554 struct drm_i915_private *dev_priv = dev->dev_private;
7555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7556 int refclk;
7557 const intel_limit_t *limit;
7558 bool ret, is_lvds = false;
7559
7560 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7561
7562 refclk = ironlake_get_refclk(crtc);
7563
7564 /*
7565 * Returns a set of divisors for the desired target clock with the given
7566 * refclk, or FALSE. The returned values represent the clock equation:
7567 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7568 */
7569 limit = intel_limit(intel_crtc, refclk);
7570 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7571 crtc_state->port_clock,
7572 refclk, NULL, clock);
7573 if (!ret)
7574 return false;
7575
7576 if (is_lvds && dev_priv->lvds_downclock_avail) {
7577 /*
7578 * Ensure we match the reduced clock's P to the target clock.
7579 * If the clocks don't match, we can't switch the display clock
7580 * by using the FP0/FP1. In such case we will disable the LVDS
7581 * downclock feature.
7582 */
7583 *has_reduced_clock =
7584 dev_priv->display.find_dpll(limit, intel_crtc,
7585 dev_priv->lvds_downclock,
7586 refclk, clock,
7587 reduced_clock);
7588 }
7589
7590 return true;
7591 }
7592
7593 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7594 {
7595 /*
7596 * Account for spread spectrum to avoid
7597 * oversubscribing the link. Max center spread
7598 * is 2.5%; use 5% for safety's sake.
7599 */
7600 u32 bps = target_clock * bpp * 21 / 20;
7601 return DIV_ROUND_UP(bps, link_bw * 8);
7602 }
7603
7604 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7605 {
7606 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7607 }
7608
7609 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7610 struct intel_crtc_state *crtc_state,
7611 u32 *fp,
7612 intel_clock_t *reduced_clock, u32 *fp2)
7613 {
7614 struct drm_crtc *crtc = &intel_crtc->base;
7615 struct drm_device *dev = crtc->dev;
7616 struct drm_i915_private *dev_priv = dev->dev_private;
7617 struct intel_encoder *intel_encoder;
7618 uint32_t dpll;
7619 int factor, num_connectors = 0;
7620 bool is_lvds = false, is_sdvo = false;
7621
7622 for_each_intel_encoder(dev, intel_encoder) {
7623 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7624 continue;
7625
7626 switch (intel_encoder->type) {
7627 case INTEL_OUTPUT_LVDS:
7628 is_lvds = true;
7629 break;
7630 case INTEL_OUTPUT_SDVO:
7631 case INTEL_OUTPUT_HDMI:
7632 is_sdvo = true;
7633 break;
7634 default:
7635 break;
7636 }
7637
7638 num_connectors++;
7639 }
7640
7641 /* Enable autotuning of the PLL clock (if permissible) */
7642 factor = 21;
7643 if (is_lvds) {
7644 if ((intel_panel_use_ssc(dev_priv) &&
7645 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7646 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7647 factor = 25;
7648 } else if (crtc_state->sdvo_tv_clock)
7649 factor = 20;
7650
7651 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7652 *fp |= FP_CB_TUNE;
7653
7654 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7655 *fp2 |= FP_CB_TUNE;
7656
7657 dpll = 0;
7658
7659 if (is_lvds)
7660 dpll |= DPLLB_MODE_LVDS;
7661 else
7662 dpll |= DPLLB_MODE_DAC_SERIAL;
7663
7664 dpll |= (crtc_state->pixel_multiplier - 1)
7665 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7666
7667 if (is_sdvo)
7668 dpll |= DPLL_SDVO_HIGH_SPEED;
7669 if (crtc_state->has_dp_encoder)
7670 dpll |= DPLL_SDVO_HIGH_SPEED;
7671
7672 /* compute bitmask from p1 value */
7673 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7674 /* also FPA1 */
7675 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7676
7677 switch (crtc_state->dpll.p2) {
7678 case 5:
7679 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7680 break;
7681 case 7:
7682 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7683 break;
7684 case 10:
7685 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7686 break;
7687 case 14:
7688 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7689 break;
7690 }
7691
7692 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7693 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7694 else
7695 dpll |= PLL_REF_INPUT_DREFCLK;
7696
7697 return dpll | DPLL_VCO_ENABLE;
7698 }
7699
7700 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7701 struct intel_crtc_state *crtc_state)
7702 {
7703 struct drm_device *dev = crtc->base.dev;
7704 intel_clock_t clock, reduced_clock;
7705 u32 dpll = 0, fp = 0, fp2 = 0;
7706 bool ok, has_reduced_clock = false;
7707 bool is_lvds = false;
7708 struct intel_shared_dpll *pll;
7709
7710 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7711
7712 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7713 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7714
7715 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7716 &has_reduced_clock, &reduced_clock);
7717 if (!ok && !crtc_state->clock_set) {
7718 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7719 return -EINVAL;
7720 }
7721 /* Compat-code for transition, will disappear. */
7722 if (!crtc_state->clock_set) {
7723 crtc_state->dpll.n = clock.n;
7724 crtc_state->dpll.m1 = clock.m1;
7725 crtc_state->dpll.m2 = clock.m2;
7726 crtc_state->dpll.p1 = clock.p1;
7727 crtc_state->dpll.p2 = clock.p2;
7728 }
7729
7730 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7731 if (crtc_state->has_pch_encoder) {
7732 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7733 if (has_reduced_clock)
7734 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7735
7736 dpll = ironlake_compute_dpll(crtc, crtc_state,
7737 &fp, &reduced_clock,
7738 has_reduced_clock ? &fp2 : NULL);
7739
7740 crtc_state->dpll_hw_state.dpll = dpll;
7741 crtc_state->dpll_hw_state.fp0 = fp;
7742 if (has_reduced_clock)
7743 crtc_state->dpll_hw_state.fp1 = fp2;
7744 else
7745 crtc_state->dpll_hw_state.fp1 = fp;
7746
7747 pll = intel_get_shared_dpll(crtc, crtc_state);
7748 if (pll == NULL) {
7749 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7750 pipe_name(crtc->pipe));
7751 return -EINVAL;
7752 }
7753 }
7754
7755 if (is_lvds && has_reduced_clock && i915.powersave)
7756 crtc->lowfreq_avail = true;
7757 else
7758 crtc->lowfreq_avail = false;
7759
7760 return 0;
7761 }
7762
7763 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7764 struct intel_link_m_n *m_n)
7765 {
7766 struct drm_device *dev = crtc->base.dev;
7767 struct drm_i915_private *dev_priv = dev->dev_private;
7768 enum pipe pipe = crtc->pipe;
7769
7770 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7771 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7772 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7773 & ~TU_SIZE_MASK;
7774 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7775 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7776 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7777 }
7778
7779 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7780 enum transcoder transcoder,
7781 struct intel_link_m_n *m_n,
7782 struct intel_link_m_n *m2_n2)
7783 {
7784 struct drm_device *dev = crtc->base.dev;
7785 struct drm_i915_private *dev_priv = dev->dev_private;
7786 enum pipe pipe = crtc->pipe;
7787
7788 if (INTEL_INFO(dev)->gen >= 5) {
7789 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7790 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7791 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7792 & ~TU_SIZE_MASK;
7793 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7794 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7795 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7796 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7797 * gen < 8) and if DRRS is supported (to make sure the
7798 * registers are not unnecessarily read).
7799 */
7800 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7801 crtc->config->has_drrs) {
7802 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7803 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7804 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7805 & ~TU_SIZE_MASK;
7806 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7807 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7808 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7809 }
7810 } else {
7811 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7812 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7813 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7814 & ~TU_SIZE_MASK;
7815 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7816 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7817 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7818 }
7819 }
7820
7821 void intel_dp_get_m_n(struct intel_crtc *crtc,
7822 struct intel_crtc_state *pipe_config)
7823 {
7824 if (pipe_config->has_pch_encoder)
7825 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7826 else
7827 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7828 &pipe_config->dp_m_n,
7829 &pipe_config->dp_m2_n2);
7830 }
7831
7832 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7833 struct intel_crtc_state *pipe_config)
7834 {
7835 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7836 &pipe_config->fdi_m_n, NULL);
7837 }
7838
7839 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7840 struct intel_crtc_state *pipe_config)
7841 {
7842 struct drm_device *dev = crtc->base.dev;
7843 struct drm_i915_private *dev_priv = dev->dev_private;
7844 uint32_t tmp;
7845
7846 tmp = I915_READ(PS_CTL(crtc->pipe));
7847
7848 if (tmp & PS_ENABLE) {
7849 pipe_config->pch_pfit.enabled = true;
7850 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7851 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7852 }
7853 }
7854
7855 static void
7856 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7857 struct intel_initial_plane_config *plane_config)
7858 {
7859 struct drm_device *dev = crtc->base.dev;
7860 struct drm_i915_private *dev_priv = dev->dev_private;
7861 u32 val, base, offset, stride_mult, tiling;
7862 int pipe = crtc->pipe;
7863 int fourcc, pixel_format;
7864 unsigned int aligned_height;
7865 struct drm_framebuffer *fb;
7866 struct intel_framebuffer *intel_fb;
7867
7868 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7869 if (!intel_fb) {
7870 DRM_DEBUG_KMS("failed to alloc fb\n");
7871 return;
7872 }
7873
7874 fb = &intel_fb->base;
7875
7876 val = I915_READ(PLANE_CTL(pipe, 0));
7877 if (!(val & PLANE_CTL_ENABLE))
7878 goto error;
7879
7880 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7881 fourcc = skl_format_to_fourcc(pixel_format,
7882 val & PLANE_CTL_ORDER_RGBX,
7883 val & PLANE_CTL_ALPHA_MASK);
7884 fb->pixel_format = fourcc;
7885 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7886
7887 tiling = val & PLANE_CTL_TILED_MASK;
7888 switch (tiling) {
7889 case PLANE_CTL_TILED_LINEAR:
7890 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7891 break;
7892 case PLANE_CTL_TILED_X:
7893 plane_config->tiling = I915_TILING_X;
7894 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7895 break;
7896 case PLANE_CTL_TILED_Y:
7897 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7898 break;
7899 case PLANE_CTL_TILED_YF:
7900 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7901 break;
7902 default:
7903 MISSING_CASE(tiling);
7904 goto error;
7905 }
7906
7907 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7908 plane_config->base = base;
7909
7910 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7911
7912 val = I915_READ(PLANE_SIZE(pipe, 0));
7913 fb->height = ((val >> 16) & 0xfff) + 1;
7914 fb->width = ((val >> 0) & 0x1fff) + 1;
7915
7916 val = I915_READ(PLANE_STRIDE(pipe, 0));
7917 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7918 fb->pixel_format);
7919 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7920
7921 aligned_height = intel_fb_align_height(dev, fb->height,
7922 fb->pixel_format,
7923 fb->modifier[0]);
7924
7925 plane_config->size = fb->pitches[0] * aligned_height;
7926
7927 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7928 pipe_name(pipe), fb->width, fb->height,
7929 fb->bits_per_pixel, base, fb->pitches[0],
7930 plane_config->size);
7931
7932 plane_config->fb = intel_fb;
7933 return;
7934
7935 error:
7936 kfree(fb);
7937 }
7938
7939 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7940 struct intel_crtc_state *pipe_config)
7941 {
7942 struct drm_device *dev = crtc->base.dev;
7943 struct drm_i915_private *dev_priv = dev->dev_private;
7944 uint32_t tmp;
7945
7946 tmp = I915_READ(PF_CTL(crtc->pipe));
7947
7948 if (tmp & PF_ENABLE) {
7949 pipe_config->pch_pfit.enabled = true;
7950 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7951 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7952
7953 /* We currently do not free assignements of panel fitters on
7954 * ivb/hsw (since we don't use the higher upscaling modes which
7955 * differentiates them) so just WARN about this case for now. */
7956 if (IS_GEN7(dev)) {
7957 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7958 PF_PIPE_SEL_IVB(crtc->pipe));
7959 }
7960 }
7961 }
7962
7963 static void
7964 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7965 struct intel_initial_plane_config *plane_config)
7966 {
7967 struct drm_device *dev = crtc->base.dev;
7968 struct drm_i915_private *dev_priv = dev->dev_private;
7969 u32 val, base, offset;
7970 int pipe = crtc->pipe;
7971 int fourcc, pixel_format;
7972 unsigned int aligned_height;
7973 struct drm_framebuffer *fb;
7974 struct intel_framebuffer *intel_fb;
7975
7976 val = I915_READ(DSPCNTR(pipe));
7977 if (!(val & DISPLAY_PLANE_ENABLE))
7978 return;
7979
7980 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7981 if (!intel_fb) {
7982 DRM_DEBUG_KMS("failed to alloc fb\n");
7983 return;
7984 }
7985
7986 fb = &intel_fb->base;
7987
7988 if (INTEL_INFO(dev)->gen >= 4) {
7989 if (val & DISPPLANE_TILED) {
7990 plane_config->tiling = I915_TILING_X;
7991 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7992 }
7993 }
7994
7995 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7996 fourcc = i9xx_format_to_fourcc(pixel_format);
7997 fb->pixel_format = fourcc;
7998 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7999
8000 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8001 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8002 offset = I915_READ(DSPOFFSET(pipe));
8003 } else {
8004 if (plane_config->tiling)
8005 offset = I915_READ(DSPTILEOFF(pipe));
8006 else
8007 offset = I915_READ(DSPLINOFF(pipe));
8008 }
8009 plane_config->base = base;
8010
8011 val = I915_READ(PIPESRC(pipe));
8012 fb->width = ((val >> 16) & 0xfff) + 1;
8013 fb->height = ((val >> 0) & 0xfff) + 1;
8014
8015 val = I915_READ(DSPSTRIDE(pipe));
8016 fb->pitches[0] = val & 0xffffffc0;
8017
8018 aligned_height = intel_fb_align_height(dev, fb->height,
8019 fb->pixel_format,
8020 fb->modifier[0]);
8021
8022 plane_config->size = fb->pitches[0] * aligned_height;
8023
8024 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8025 pipe_name(pipe), fb->width, fb->height,
8026 fb->bits_per_pixel, base, fb->pitches[0],
8027 plane_config->size);
8028
8029 plane_config->fb = intel_fb;
8030 }
8031
8032 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8033 struct intel_crtc_state *pipe_config)
8034 {
8035 struct drm_device *dev = crtc->base.dev;
8036 struct drm_i915_private *dev_priv = dev->dev_private;
8037 uint32_t tmp;
8038
8039 if (!intel_display_power_is_enabled(dev_priv,
8040 POWER_DOMAIN_PIPE(crtc->pipe)))
8041 return false;
8042
8043 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8044 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8045
8046 tmp = I915_READ(PIPECONF(crtc->pipe));
8047 if (!(tmp & PIPECONF_ENABLE))
8048 return false;
8049
8050 switch (tmp & PIPECONF_BPC_MASK) {
8051 case PIPECONF_6BPC:
8052 pipe_config->pipe_bpp = 18;
8053 break;
8054 case PIPECONF_8BPC:
8055 pipe_config->pipe_bpp = 24;
8056 break;
8057 case PIPECONF_10BPC:
8058 pipe_config->pipe_bpp = 30;
8059 break;
8060 case PIPECONF_12BPC:
8061 pipe_config->pipe_bpp = 36;
8062 break;
8063 default:
8064 break;
8065 }
8066
8067 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8068 pipe_config->limited_color_range = true;
8069
8070 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8071 struct intel_shared_dpll *pll;
8072
8073 pipe_config->has_pch_encoder = true;
8074
8075 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8076 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8077 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8078
8079 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8080
8081 if (HAS_PCH_IBX(dev_priv->dev)) {
8082 pipe_config->shared_dpll =
8083 (enum intel_dpll_id) crtc->pipe;
8084 } else {
8085 tmp = I915_READ(PCH_DPLL_SEL);
8086 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8087 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8088 else
8089 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8090 }
8091
8092 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8093
8094 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8095 &pipe_config->dpll_hw_state));
8096
8097 tmp = pipe_config->dpll_hw_state.dpll;
8098 pipe_config->pixel_multiplier =
8099 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8100 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8101
8102 ironlake_pch_clock_get(crtc, pipe_config);
8103 } else {
8104 pipe_config->pixel_multiplier = 1;
8105 }
8106
8107 intel_get_pipe_timings(crtc, pipe_config);
8108
8109 ironlake_get_pfit_config(crtc, pipe_config);
8110
8111 return true;
8112 }
8113
8114 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8115 {
8116 struct drm_device *dev = dev_priv->dev;
8117 struct intel_crtc *crtc;
8118
8119 for_each_intel_crtc(dev, crtc)
8120 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8121 pipe_name(crtc->pipe));
8122
8123 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8124 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8125 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8126 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8127 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8128 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8129 "CPU PWM1 enabled\n");
8130 if (IS_HASWELL(dev))
8131 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8132 "CPU PWM2 enabled\n");
8133 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8134 "PCH PWM1 enabled\n");
8135 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8136 "Utility pin enabled\n");
8137 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8138
8139 /*
8140 * In theory we can still leave IRQs enabled, as long as only the HPD
8141 * interrupts remain enabled. We used to check for that, but since it's
8142 * gen-specific and since we only disable LCPLL after we fully disable
8143 * the interrupts, the check below should be enough.
8144 */
8145 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8146 }
8147
8148 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8149 {
8150 struct drm_device *dev = dev_priv->dev;
8151
8152 if (IS_HASWELL(dev))
8153 return I915_READ(D_COMP_HSW);
8154 else
8155 return I915_READ(D_COMP_BDW);
8156 }
8157
8158 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8159 {
8160 struct drm_device *dev = dev_priv->dev;
8161
8162 if (IS_HASWELL(dev)) {
8163 mutex_lock(&dev_priv->rps.hw_lock);
8164 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8165 val))
8166 DRM_ERROR("Failed to write to D_COMP\n");
8167 mutex_unlock(&dev_priv->rps.hw_lock);
8168 } else {
8169 I915_WRITE(D_COMP_BDW, val);
8170 POSTING_READ(D_COMP_BDW);
8171 }
8172 }
8173
8174 /*
8175 * This function implements pieces of two sequences from BSpec:
8176 * - Sequence for display software to disable LCPLL
8177 * - Sequence for display software to allow package C8+
8178 * The steps implemented here are just the steps that actually touch the LCPLL
8179 * register. Callers should take care of disabling all the display engine
8180 * functions, doing the mode unset, fixing interrupts, etc.
8181 */
8182 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8183 bool switch_to_fclk, bool allow_power_down)
8184 {
8185 uint32_t val;
8186
8187 assert_can_disable_lcpll(dev_priv);
8188
8189 val = I915_READ(LCPLL_CTL);
8190
8191 if (switch_to_fclk) {
8192 val |= LCPLL_CD_SOURCE_FCLK;
8193 I915_WRITE(LCPLL_CTL, val);
8194
8195 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8196 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8197 DRM_ERROR("Switching to FCLK failed\n");
8198
8199 val = I915_READ(LCPLL_CTL);
8200 }
8201
8202 val |= LCPLL_PLL_DISABLE;
8203 I915_WRITE(LCPLL_CTL, val);
8204 POSTING_READ(LCPLL_CTL);
8205
8206 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8207 DRM_ERROR("LCPLL still locked\n");
8208
8209 val = hsw_read_dcomp(dev_priv);
8210 val |= D_COMP_COMP_DISABLE;
8211 hsw_write_dcomp(dev_priv, val);
8212 ndelay(100);
8213
8214 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8215 1))
8216 DRM_ERROR("D_COMP RCOMP still in progress\n");
8217
8218 if (allow_power_down) {
8219 val = I915_READ(LCPLL_CTL);
8220 val |= LCPLL_POWER_DOWN_ALLOW;
8221 I915_WRITE(LCPLL_CTL, val);
8222 POSTING_READ(LCPLL_CTL);
8223 }
8224 }
8225
8226 /*
8227 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8228 * source.
8229 */
8230 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8231 {
8232 uint32_t val;
8233
8234 val = I915_READ(LCPLL_CTL);
8235
8236 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8237 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8238 return;
8239
8240 /*
8241 * Make sure we're not on PC8 state before disabling PC8, otherwise
8242 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8243 */
8244 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8245
8246 if (val & LCPLL_POWER_DOWN_ALLOW) {
8247 val &= ~LCPLL_POWER_DOWN_ALLOW;
8248 I915_WRITE(LCPLL_CTL, val);
8249 POSTING_READ(LCPLL_CTL);
8250 }
8251
8252 val = hsw_read_dcomp(dev_priv);
8253 val |= D_COMP_COMP_FORCE;
8254 val &= ~D_COMP_COMP_DISABLE;
8255 hsw_write_dcomp(dev_priv, val);
8256
8257 val = I915_READ(LCPLL_CTL);
8258 val &= ~LCPLL_PLL_DISABLE;
8259 I915_WRITE(LCPLL_CTL, val);
8260
8261 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8262 DRM_ERROR("LCPLL not locked yet\n");
8263
8264 if (val & LCPLL_CD_SOURCE_FCLK) {
8265 val = I915_READ(LCPLL_CTL);
8266 val &= ~LCPLL_CD_SOURCE_FCLK;
8267 I915_WRITE(LCPLL_CTL, val);
8268
8269 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8270 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8271 DRM_ERROR("Switching back to LCPLL failed\n");
8272 }
8273
8274 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8275 }
8276
8277 /*
8278 * Package states C8 and deeper are really deep PC states that can only be
8279 * reached when all the devices on the system allow it, so even if the graphics
8280 * device allows PC8+, it doesn't mean the system will actually get to these
8281 * states. Our driver only allows PC8+ when going into runtime PM.
8282 *
8283 * The requirements for PC8+ are that all the outputs are disabled, the power
8284 * well is disabled and most interrupts are disabled, and these are also
8285 * requirements for runtime PM. When these conditions are met, we manually do
8286 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8287 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8288 * hang the machine.
8289 *
8290 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8291 * the state of some registers, so when we come back from PC8+ we need to
8292 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8293 * need to take care of the registers kept by RC6. Notice that this happens even
8294 * if we don't put the device in PCI D3 state (which is what currently happens
8295 * because of the runtime PM support).
8296 *
8297 * For more, read "Display Sequences for Package C8" on the hardware
8298 * documentation.
8299 */
8300 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8301 {
8302 struct drm_device *dev = dev_priv->dev;
8303 uint32_t val;
8304
8305 DRM_DEBUG_KMS("Enabling package C8+\n");
8306
8307 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8308 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8309 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8310 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8311 }
8312
8313 lpt_disable_clkout_dp(dev);
8314 hsw_disable_lcpll(dev_priv, true, true);
8315 }
8316
8317 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8318 {
8319 struct drm_device *dev = dev_priv->dev;
8320 uint32_t val;
8321
8322 DRM_DEBUG_KMS("Disabling package C8+\n");
8323
8324 hsw_restore_lcpll(dev_priv);
8325 lpt_init_pch_refclk(dev);
8326
8327 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8328 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8329 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8330 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8331 }
8332
8333 intel_prepare_ddi(dev);
8334 }
8335
8336 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8337 struct intel_crtc_state *crtc_state)
8338 {
8339 if (!intel_ddi_pll_select(crtc, crtc_state))
8340 return -EINVAL;
8341
8342 crtc->lowfreq_avail = false;
8343
8344 return 0;
8345 }
8346
8347 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8348 enum port port,
8349 struct intel_crtc_state *pipe_config)
8350 {
8351 u32 temp, dpll_ctl1;
8352
8353 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8354 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8355
8356 switch (pipe_config->ddi_pll_sel) {
8357 case SKL_DPLL0:
8358 /*
8359 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8360 * of the shared DPLL framework and thus needs to be read out
8361 * separately
8362 */
8363 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8364 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8365 break;
8366 case SKL_DPLL1:
8367 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8368 break;
8369 case SKL_DPLL2:
8370 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8371 break;
8372 case SKL_DPLL3:
8373 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8374 break;
8375 }
8376 }
8377
8378 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8379 enum port port,
8380 struct intel_crtc_state *pipe_config)
8381 {
8382 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8383
8384 switch (pipe_config->ddi_pll_sel) {
8385 case PORT_CLK_SEL_WRPLL1:
8386 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8387 break;
8388 case PORT_CLK_SEL_WRPLL2:
8389 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8390 break;
8391 }
8392 }
8393
8394 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8395 struct intel_crtc_state *pipe_config)
8396 {
8397 struct drm_device *dev = crtc->base.dev;
8398 struct drm_i915_private *dev_priv = dev->dev_private;
8399 struct intel_shared_dpll *pll;
8400 enum port port;
8401 uint32_t tmp;
8402
8403 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8404
8405 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8406
8407 if (IS_SKYLAKE(dev))
8408 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8409 else
8410 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8411
8412 if (pipe_config->shared_dpll >= 0) {
8413 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8414
8415 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8416 &pipe_config->dpll_hw_state));
8417 }
8418
8419 /*
8420 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8421 * DDI E. So just check whether this pipe is wired to DDI E and whether
8422 * the PCH transcoder is on.
8423 */
8424 if (INTEL_INFO(dev)->gen < 9 &&
8425 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8426 pipe_config->has_pch_encoder = true;
8427
8428 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8429 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8430 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8431
8432 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8433 }
8434 }
8435
8436 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8437 struct intel_crtc_state *pipe_config)
8438 {
8439 struct drm_device *dev = crtc->base.dev;
8440 struct drm_i915_private *dev_priv = dev->dev_private;
8441 enum intel_display_power_domain pfit_domain;
8442 uint32_t tmp;
8443
8444 if (!intel_display_power_is_enabled(dev_priv,
8445 POWER_DOMAIN_PIPE(crtc->pipe)))
8446 return false;
8447
8448 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8449 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8450
8451 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8452 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8453 enum pipe trans_edp_pipe;
8454 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8455 default:
8456 WARN(1, "unknown pipe linked to edp transcoder\n");
8457 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8458 case TRANS_DDI_EDP_INPUT_A_ON:
8459 trans_edp_pipe = PIPE_A;
8460 break;
8461 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8462 trans_edp_pipe = PIPE_B;
8463 break;
8464 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8465 trans_edp_pipe = PIPE_C;
8466 break;
8467 }
8468
8469 if (trans_edp_pipe == crtc->pipe)
8470 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8471 }
8472
8473 if (!intel_display_power_is_enabled(dev_priv,
8474 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8475 return false;
8476
8477 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8478 if (!(tmp & PIPECONF_ENABLE))
8479 return false;
8480
8481 haswell_get_ddi_port_state(crtc, pipe_config);
8482
8483 intel_get_pipe_timings(crtc, pipe_config);
8484
8485 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8486 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8487 if (IS_SKYLAKE(dev))
8488 skylake_get_pfit_config(crtc, pipe_config);
8489 else
8490 ironlake_get_pfit_config(crtc, pipe_config);
8491 }
8492
8493 if (IS_HASWELL(dev))
8494 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8495 (I915_READ(IPS_CTL) & IPS_ENABLE);
8496
8497 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8498 pipe_config->pixel_multiplier =
8499 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8500 } else {
8501 pipe_config->pixel_multiplier = 1;
8502 }
8503
8504 return true;
8505 }
8506
8507 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8508 {
8509 struct drm_device *dev = crtc->dev;
8510 struct drm_i915_private *dev_priv = dev->dev_private;
8511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8512 uint32_t cntl = 0, size = 0;
8513
8514 if (base) {
8515 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8516 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8517 unsigned int stride = roundup_pow_of_two(width) * 4;
8518
8519 switch (stride) {
8520 default:
8521 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8522 width, stride);
8523 stride = 256;
8524 /* fallthrough */
8525 case 256:
8526 case 512:
8527 case 1024:
8528 case 2048:
8529 break;
8530 }
8531
8532 cntl |= CURSOR_ENABLE |
8533 CURSOR_GAMMA_ENABLE |
8534 CURSOR_FORMAT_ARGB |
8535 CURSOR_STRIDE(stride);
8536
8537 size = (height << 12) | width;
8538 }
8539
8540 if (intel_crtc->cursor_cntl != 0 &&
8541 (intel_crtc->cursor_base != base ||
8542 intel_crtc->cursor_size != size ||
8543 intel_crtc->cursor_cntl != cntl)) {
8544 /* On these chipsets we can only modify the base/size/stride
8545 * whilst the cursor is disabled.
8546 */
8547 I915_WRITE(_CURACNTR, 0);
8548 POSTING_READ(_CURACNTR);
8549 intel_crtc->cursor_cntl = 0;
8550 }
8551
8552 if (intel_crtc->cursor_base != base) {
8553 I915_WRITE(_CURABASE, base);
8554 intel_crtc->cursor_base = base;
8555 }
8556
8557 if (intel_crtc->cursor_size != size) {
8558 I915_WRITE(CURSIZE, size);
8559 intel_crtc->cursor_size = size;
8560 }
8561
8562 if (intel_crtc->cursor_cntl != cntl) {
8563 I915_WRITE(_CURACNTR, cntl);
8564 POSTING_READ(_CURACNTR);
8565 intel_crtc->cursor_cntl = cntl;
8566 }
8567 }
8568
8569 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8570 {
8571 struct drm_device *dev = crtc->dev;
8572 struct drm_i915_private *dev_priv = dev->dev_private;
8573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8574 int pipe = intel_crtc->pipe;
8575 uint32_t cntl;
8576
8577 cntl = 0;
8578 if (base) {
8579 cntl = MCURSOR_GAMMA_ENABLE;
8580 switch (intel_crtc->base.cursor->state->crtc_w) {
8581 case 64:
8582 cntl |= CURSOR_MODE_64_ARGB_AX;
8583 break;
8584 case 128:
8585 cntl |= CURSOR_MODE_128_ARGB_AX;
8586 break;
8587 case 256:
8588 cntl |= CURSOR_MODE_256_ARGB_AX;
8589 break;
8590 default:
8591 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8592 return;
8593 }
8594 cntl |= pipe << 28; /* Connect to correct pipe */
8595
8596 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8597 cntl |= CURSOR_PIPE_CSC_ENABLE;
8598 }
8599
8600 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8601 cntl |= CURSOR_ROTATE_180;
8602
8603 if (intel_crtc->cursor_cntl != cntl) {
8604 I915_WRITE(CURCNTR(pipe), cntl);
8605 POSTING_READ(CURCNTR(pipe));
8606 intel_crtc->cursor_cntl = cntl;
8607 }
8608
8609 /* and commit changes on next vblank */
8610 I915_WRITE(CURBASE(pipe), base);
8611 POSTING_READ(CURBASE(pipe));
8612
8613 intel_crtc->cursor_base = base;
8614 }
8615
8616 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8617 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8618 bool on)
8619 {
8620 struct drm_device *dev = crtc->dev;
8621 struct drm_i915_private *dev_priv = dev->dev_private;
8622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623 int pipe = intel_crtc->pipe;
8624 int x = crtc->cursor_x;
8625 int y = crtc->cursor_y;
8626 u32 base = 0, pos = 0;
8627
8628 if (on)
8629 base = intel_crtc->cursor_addr;
8630
8631 if (x >= intel_crtc->config->pipe_src_w)
8632 base = 0;
8633
8634 if (y >= intel_crtc->config->pipe_src_h)
8635 base = 0;
8636
8637 if (x < 0) {
8638 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8639 base = 0;
8640
8641 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8642 x = -x;
8643 }
8644 pos |= x << CURSOR_X_SHIFT;
8645
8646 if (y < 0) {
8647 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8648 base = 0;
8649
8650 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8651 y = -y;
8652 }
8653 pos |= y << CURSOR_Y_SHIFT;
8654
8655 if (base == 0 && intel_crtc->cursor_base == 0)
8656 return;
8657
8658 I915_WRITE(CURPOS(pipe), pos);
8659
8660 /* ILK+ do this automagically */
8661 if (HAS_GMCH_DISPLAY(dev) &&
8662 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8663 base += (intel_crtc->base.cursor->state->crtc_h *
8664 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8665 }
8666
8667 if (IS_845G(dev) || IS_I865G(dev))
8668 i845_update_cursor(crtc, base);
8669 else
8670 i9xx_update_cursor(crtc, base);
8671 }
8672
8673 static bool cursor_size_ok(struct drm_device *dev,
8674 uint32_t width, uint32_t height)
8675 {
8676 if (width == 0 || height == 0)
8677 return false;
8678
8679 /*
8680 * 845g/865g are special in that they are only limited by
8681 * the width of their cursors, the height is arbitrary up to
8682 * the precision of the register. Everything else requires
8683 * square cursors, limited to a few power-of-two sizes.
8684 */
8685 if (IS_845G(dev) || IS_I865G(dev)) {
8686 if ((width & 63) != 0)
8687 return false;
8688
8689 if (width > (IS_845G(dev) ? 64 : 512))
8690 return false;
8691
8692 if (height > 1023)
8693 return false;
8694 } else {
8695 switch (width | height) {
8696 case 256:
8697 case 128:
8698 if (IS_GEN2(dev))
8699 return false;
8700 case 64:
8701 break;
8702 default:
8703 return false;
8704 }
8705 }
8706
8707 return true;
8708 }
8709
8710 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8711 u16 *blue, uint32_t start, uint32_t size)
8712 {
8713 int end = (start + size > 256) ? 256 : start + size, i;
8714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8715
8716 for (i = start; i < end; i++) {
8717 intel_crtc->lut_r[i] = red[i] >> 8;
8718 intel_crtc->lut_g[i] = green[i] >> 8;
8719 intel_crtc->lut_b[i] = blue[i] >> 8;
8720 }
8721
8722 intel_crtc_load_lut(crtc);
8723 }
8724
8725 /* VESA 640x480x72Hz mode to set on the pipe */
8726 static struct drm_display_mode load_detect_mode = {
8727 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8728 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8729 };
8730
8731 struct drm_framebuffer *
8732 __intel_framebuffer_create(struct drm_device *dev,
8733 struct drm_mode_fb_cmd2 *mode_cmd,
8734 struct drm_i915_gem_object *obj)
8735 {
8736 struct intel_framebuffer *intel_fb;
8737 int ret;
8738
8739 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8740 if (!intel_fb) {
8741 drm_gem_object_unreference(&obj->base);
8742 return ERR_PTR(-ENOMEM);
8743 }
8744
8745 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8746 if (ret)
8747 goto err;
8748
8749 return &intel_fb->base;
8750 err:
8751 drm_gem_object_unreference(&obj->base);
8752 kfree(intel_fb);
8753
8754 return ERR_PTR(ret);
8755 }
8756
8757 static struct drm_framebuffer *
8758 intel_framebuffer_create(struct drm_device *dev,
8759 struct drm_mode_fb_cmd2 *mode_cmd,
8760 struct drm_i915_gem_object *obj)
8761 {
8762 struct drm_framebuffer *fb;
8763 int ret;
8764
8765 ret = i915_mutex_lock_interruptible(dev);
8766 if (ret)
8767 return ERR_PTR(ret);
8768 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8769 mutex_unlock(&dev->struct_mutex);
8770
8771 return fb;
8772 }
8773
8774 static u32
8775 intel_framebuffer_pitch_for_width(int width, int bpp)
8776 {
8777 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8778 return ALIGN(pitch, 64);
8779 }
8780
8781 static u32
8782 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8783 {
8784 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8785 return PAGE_ALIGN(pitch * mode->vdisplay);
8786 }
8787
8788 static struct drm_framebuffer *
8789 intel_framebuffer_create_for_mode(struct drm_device *dev,
8790 struct drm_display_mode *mode,
8791 int depth, int bpp)
8792 {
8793 struct drm_i915_gem_object *obj;
8794 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8795
8796 obj = i915_gem_alloc_object(dev,
8797 intel_framebuffer_size_for_mode(mode, bpp));
8798 if (obj == NULL)
8799 return ERR_PTR(-ENOMEM);
8800
8801 mode_cmd.width = mode->hdisplay;
8802 mode_cmd.height = mode->vdisplay;
8803 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8804 bpp);
8805 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8806
8807 return intel_framebuffer_create(dev, &mode_cmd, obj);
8808 }
8809
8810 static struct drm_framebuffer *
8811 mode_fits_in_fbdev(struct drm_device *dev,
8812 struct drm_display_mode *mode)
8813 {
8814 #ifdef CONFIG_DRM_I915_FBDEV
8815 struct drm_i915_private *dev_priv = dev->dev_private;
8816 struct drm_i915_gem_object *obj;
8817 struct drm_framebuffer *fb;
8818
8819 if (!dev_priv->fbdev)
8820 return NULL;
8821
8822 if (!dev_priv->fbdev->fb)
8823 return NULL;
8824
8825 obj = dev_priv->fbdev->fb->obj;
8826 BUG_ON(!obj);
8827
8828 fb = &dev_priv->fbdev->fb->base;
8829 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8830 fb->bits_per_pixel))
8831 return NULL;
8832
8833 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8834 return NULL;
8835
8836 return fb;
8837 #else
8838 return NULL;
8839 #endif
8840 }
8841
8842 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8843 struct drm_display_mode *mode,
8844 struct intel_load_detect_pipe *old,
8845 struct drm_modeset_acquire_ctx *ctx)
8846 {
8847 struct intel_crtc *intel_crtc;
8848 struct intel_encoder *intel_encoder =
8849 intel_attached_encoder(connector);
8850 struct drm_crtc *possible_crtc;
8851 struct drm_encoder *encoder = &intel_encoder->base;
8852 struct drm_crtc *crtc = NULL;
8853 struct drm_device *dev = encoder->dev;
8854 struct drm_framebuffer *fb;
8855 struct drm_mode_config *config = &dev->mode_config;
8856 int ret, i = -1;
8857
8858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8859 connector->base.id, connector->name,
8860 encoder->base.id, encoder->name);
8861
8862 retry:
8863 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8864 if (ret)
8865 goto fail_unlock;
8866
8867 /*
8868 * Algorithm gets a little messy:
8869 *
8870 * - if the connector already has an assigned crtc, use it (but make
8871 * sure it's on first)
8872 *
8873 * - try to find the first unused crtc that can drive this connector,
8874 * and use that if we find one
8875 */
8876
8877 /* See if we already have a CRTC for this connector */
8878 if (encoder->crtc) {
8879 crtc = encoder->crtc;
8880
8881 ret = drm_modeset_lock(&crtc->mutex, ctx);
8882 if (ret)
8883 goto fail_unlock;
8884 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8885 if (ret)
8886 goto fail_unlock;
8887
8888 old->dpms_mode = connector->dpms;
8889 old->load_detect_temp = false;
8890
8891 /* Make sure the crtc and connector are running */
8892 if (connector->dpms != DRM_MODE_DPMS_ON)
8893 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8894
8895 return true;
8896 }
8897
8898 /* Find an unused one (if possible) */
8899 for_each_crtc(dev, possible_crtc) {
8900 i++;
8901 if (!(encoder->possible_crtcs & (1 << i)))
8902 continue;
8903 if (possible_crtc->state->enable)
8904 continue;
8905 /* This can occur when applying the pipe A quirk on resume. */
8906 if (to_intel_crtc(possible_crtc)->new_enabled)
8907 continue;
8908
8909 crtc = possible_crtc;
8910 break;
8911 }
8912
8913 /*
8914 * If we didn't find an unused CRTC, don't use any.
8915 */
8916 if (!crtc) {
8917 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8918 goto fail_unlock;
8919 }
8920
8921 ret = drm_modeset_lock(&crtc->mutex, ctx);
8922 if (ret)
8923 goto fail_unlock;
8924 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8925 if (ret)
8926 goto fail_unlock;
8927 intel_encoder->new_crtc = to_intel_crtc(crtc);
8928 to_intel_connector(connector)->new_encoder = intel_encoder;
8929
8930 intel_crtc = to_intel_crtc(crtc);
8931 intel_crtc->new_enabled = true;
8932 intel_crtc->new_config = intel_crtc->config;
8933 old->dpms_mode = connector->dpms;
8934 old->load_detect_temp = true;
8935 old->release_fb = NULL;
8936
8937 if (!mode)
8938 mode = &load_detect_mode;
8939
8940 /* We need a framebuffer large enough to accommodate all accesses
8941 * that the plane may generate whilst we perform load detection.
8942 * We can not rely on the fbcon either being present (we get called
8943 * during its initialisation to detect all boot displays, or it may
8944 * not even exist) or that it is large enough to satisfy the
8945 * requested mode.
8946 */
8947 fb = mode_fits_in_fbdev(dev, mode);
8948 if (fb == NULL) {
8949 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8950 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8951 old->release_fb = fb;
8952 } else
8953 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8954 if (IS_ERR(fb)) {
8955 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8956 goto fail;
8957 }
8958
8959 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8960 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8961 if (old->release_fb)
8962 old->release_fb->funcs->destroy(old->release_fb);
8963 goto fail;
8964 }
8965 crtc->primary->crtc = crtc;
8966
8967 /* let the connector get through one full cycle before testing */
8968 intel_wait_for_vblank(dev, intel_crtc->pipe);
8969 return true;
8970
8971 fail:
8972 intel_crtc->new_enabled = crtc->state->enable;
8973 if (intel_crtc->new_enabled)
8974 intel_crtc->new_config = intel_crtc->config;
8975 else
8976 intel_crtc->new_config = NULL;
8977 fail_unlock:
8978 if (ret == -EDEADLK) {
8979 drm_modeset_backoff(ctx);
8980 goto retry;
8981 }
8982
8983 return false;
8984 }
8985
8986 void intel_release_load_detect_pipe(struct drm_connector *connector,
8987 struct intel_load_detect_pipe *old)
8988 {
8989 struct intel_encoder *intel_encoder =
8990 intel_attached_encoder(connector);
8991 struct drm_encoder *encoder = &intel_encoder->base;
8992 struct drm_crtc *crtc = encoder->crtc;
8993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8994
8995 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8996 connector->base.id, connector->name,
8997 encoder->base.id, encoder->name);
8998
8999 if (old->load_detect_temp) {
9000 to_intel_connector(connector)->new_encoder = NULL;
9001 intel_encoder->new_crtc = NULL;
9002 intel_crtc->new_enabled = false;
9003 intel_crtc->new_config = NULL;
9004 intel_set_mode(crtc, NULL, 0, 0, NULL);
9005
9006 if (old->release_fb) {
9007 drm_framebuffer_unregister_private(old->release_fb);
9008 drm_framebuffer_unreference(old->release_fb);
9009 }
9010
9011 return;
9012 }
9013
9014 /* Switch crtc and encoder back off if necessary */
9015 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9016 connector->funcs->dpms(connector, old->dpms_mode);
9017 }
9018
9019 static int i9xx_pll_refclk(struct drm_device *dev,
9020 const struct intel_crtc_state *pipe_config)
9021 {
9022 struct drm_i915_private *dev_priv = dev->dev_private;
9023 u32 dpll = pipe_config->dpll_hw_state.dpll;
9024
9025 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9026 return dev_priv->vbt.lvds_ssc_freq;
9027 else if (HAS_PCH_SPLIT(dev))
9028 return 120000;
9029 else if (!IS_GEN2(dev))
9030 return 96000;
9031 else
9032 return 48000;
9033 }
9034
9035 /* Returns the clock of the currently programmed mode of the given pipe. */
9036 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9037 struct intel_crtc_state *pipe_config)
9038 {
9039 struct drm_device *dev = crtc->base.dev;
9040 struct drm_i915_private *dev_priv = dev->dev_private;
9041 int pipe = pipe_config->cpu_transcoder;
9042 u32 dpll = pipe_config->dpll_hw_state.dpll;
9043 u32 fp;
9044 intel_clock_t clock;
9045 int refclk = i9xx_pll_refclk(dev, pipe_config);
9046
9047 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9048 fp = pipe_config->dpll_hw_state.fp0;
9049 else
9050 fp = pipe_config->dpll_hw_state.fp1;
9051
9052 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9053 if (IS_PINEVIEW(dev)) {
9054 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9055 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9056 } else {
9057 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9058 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9059 }
9060
9061 if (!IS_GEN2(dev)) {
9062 if (IS_PINEVIEW(dev))
9063 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9064 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9065 else
9066 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9067 DPLL_FPA01_P1_POST_DIV_SHIFT);
9068
9069 switch (dpll & DPLL_MODE_MASK) {
9070 case DPLLB_MODE_DAC_SERIAL:
9071 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9072 5 : 10;
9073 break;
9074 case DPLLB_MODE_LVDS:
9075 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9076 7 : 14;
9077 break;
9078 default:
9079 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9080 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9081 return;
9082 }
9083
9084 if (IS_PINEVIEW(dev))
9085 pineview_clock(refclk, &clock);
9086 else
9087 i9xx_clock(refclk, &clock);
9088 } else {
9089 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9090 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9091
9092 if (is_lvds) {
9093 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9094 DPLL_FPA01_P1_POST_DIV_SHIFT);
9095
9096 if (lvds & LVDS_CLKB_POWER_UP)
9097 clock.p2 = 7;
9098 else
9099 clock.p2 = 14;
9100 } else {
9101 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9102 clock.p1 = 2;
9103 else {
9104 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9105 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9106 }
9107 if (dpll & PLL_P2_DIVIDE_BY_4)
9108 clock.p2 = 4;
9109 else
9110 clock.p2 = 2;
9111 }
9112
9113 i9xx_clock(refclk, &clock);
9114 }
9115
9116 /*
9117 * This value includes pixel_multiplier. We will use
9118 * port_clock to compute adjusted_mode.crtc_clock in the
9119 * encoder's get_config() function.
9120 */
9121 pipe_config->port_clock = clock.dot;
9122 }
9123
9124 int intel_dotclock_calculate(int link_freq,
9125 const struct intel_link_m_n *m_n)
9126 {
9127 /*
9128 * The calculation for the data clock is:
9129 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9130 * But we want to avoid losing precison if possible, so:
9131 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9132 *
9133 * and the link clock is simpler:
9134 * link_clock = (m * link_clock) / n
9135 */
9136
9137 if (!m_n->link_n)
9138 return 0;
9139
9140 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9141 }
9142
9143 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9144 struct intel_crtc_state *pipe_config)
9145 {
9146 struct drm_device *dev = crtc->base.dev;
9147
9148 /* read out port_clock from the DPLL */
9149 i9xx_crtc_clock_get(crtc, pipe_config);
9150
9151 /*
9152 * This value does not include pixel_multiplier.
9153 * We will check that port_clock and adjusted_mode.crtc_clock
9154 * agree once we know their relationship in the encoder's
9155 * get_config() function.
9156 */
9157 pipe_config->base.adjusted_mode.crtc_clock =
9158 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9159 &pipe_config->fdi_m_n);
9160 }
9161
9162 /** Returns the currently programmed mode of the given pipe. */
9163 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9164 struct drm_crtc *crtc)
9165 {
9166 struct drm_i915_private *dev_priv = dev->dev_private;
9167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9168 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9169 struct drm_display_mode *mode;
9170 struct intel_crtc_state pipe_config;
9171 int htot = I915_READ(HTOTAL(cpu_transcoder));
9172 int hsync = I915_READ(HSYNC(cpu_transcoder));
9173 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9174 int vsync = I915_READ(VSYNC(cpu_transcoder));
9175 enum pipe pipe = intel_crtc->pipe;
9176
9177 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9178 if (!mode)
9179 return NULL;
9180
9181 /*
9182 * Construct a pipe_config sufficient for getting the clock info
9183 * back out of crtc_clock_get.
9184 *
9185 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9186 * to use a real value here instead.
9187 */
9188 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9189 pipe_config.pixel_multiplier = 1;
9190 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9191 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9192 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9193 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9194
9195 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9196 mode->hdisplay = (htot & 0xffff) + 1;
9197 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9198 mode->hsync_start = (hsync & 0xffff) + 1;
9199 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9200 mode->vdisplay = (vtot & 0xffff) + 1;
9201 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9202 mode->vsync_start = (vsync & 0xffff) + 1;
9203 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9204
9205 drm_mode_set_name(mode);
9206
9207 return mode;
9208 }
9209
9210 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9211 {
9212 struct drm_device *dev = crtc->dev;
9213 struct drm_i915_private *dev_priv = dev->dev_private;
9214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9215
9216 if (!HAS_GMCH_DISPLAY(dev))
9217 return;
9218
9219 if (!dev_priv->lvds_downclock_avail)
9220 return;
9221
9222 /*
9223 * Since this is called by a timer, we should never get here in
9224 * the manual case.
9225 */
9226 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9227 int pipe = intel_crtc->pipe;
9228 int dpll_reg = DPLL(pipe);
9229 int dpll;
9230
9231 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9232
9233 assert_panel_unlocked(dev_priv, pipe);
9234
9235 dpll = I915_READ(dpll_reg);
9236 dpll |= DISPLAY_RATE_SELECT_FPA1;
9237 I915_WRITE(dpll_reg, dpll);
9238 intel_wait_for_vblank(dev, pipe);
9239 dpll = I915_READ(dpll_reg);
9240 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9241 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9242 }
9243
9244 }
9245
9246 void intel_mark_busy(struct drm_device *dev)
9247 {
9248 struct drm_i915_private *dev_priv = dev->dev_private;
9249
9250 if (dev_priv->mm.busy)
9251 return;
9252
9253 intel_runtime_pm_get(dev_priv);
9254 i915_update_gfx_val(dev_priv);
9255 if (INTEL_INFO(dev)->gen >= 6)
9256 gen6_rps_busy(dev_priv);
9257 dev_priv->mm.busy = true;
9258 }
9259
9260 void intel_mark_idle(struct drm_device *dev)
9261 {
9262 struct drm_i915_private *dev_priv = dev->dev_private;
9263 struct drm_crtc *crtc;
9264
9265 if (!dev_priv->mm.busy)
9266 return;
9267
9268 dev_priv->mm.busy = false;
9269
9270 if (!i915.powersave)
9271 goto out;
9272
9273 for_each_crtc(dev, crtc) {
9274 if (!crtc->primary->fb)
9275 continue;
9276
9277 intel_decrease_pllclock(crtc);
9278 }
9279
9280 if (INTEL_INFO(dev)->gen >= 6)
9281 gen6_rps_idle(dev->dev_private);
9282
9283 out:
9284 intel_runtime_pm_put(dev_priv);
9285 }
9286
9287 static void intel_crtc_set_state(struct intel_crtc *crtc,
9288 struct intel_crtc_state *crtc_state)
9289 {
9290 kfree(crtc->config);
9291 crtc->config = crtc_state;
9292 crtc->base.state = &crtc_state->base;
9293 }
9294
9295 static void intel_crtc_destroy(struct drm_crtc *crtc)
9296 {
9297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9298 struct drm_device *dev = crtc->dev;
9299 struct intel_unpin_work *work;
9300
9301 spin_lock_irq(&dev->event_lock);
9302 work = intel_crtc->unpin_work;
9303 intel_crtc->unpin_work = NULL;
9304 spin_unlock_irq(&dev->event_lock);
9305
9306 if (work) {
9307 cancel_work_sync(&work->work);
9308 kfree(work);
9309 }
9310
9311 intel_crtc_set_state(intel_crtc, NULL);
9312 drm_crtc_cleanup(crtc);
9313
9314 kfree(intel_crtc);
9315 }
9316
9317 static void intel_unpin_work_fn(struct work_struct *__work)
9318 {
9319 struct intel_unpin_work *work =
9320 container_of(__work, struct intel_unpin_work, work);
9321 struct drm_device *dev = work->crtc->dev;
9322 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9323
9324 mutex_lock(&dev->struct_mutex);
9325 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9326 drm_gem_object_unreference(&work->pending_flip_obj->base);
9327
9328 intel_fbc_update(dev);
9329
9330 if (work->flip_queued_req)
9331 i915_gem_request_assign(&work->flip_queued_req, NULL);
9332 mutex_unlock(&dev->struct_mutex);
9333
9334 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9335 drm_framebuffer_unreference(work->old_fb);
9336
9337 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9338 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9339
9340 kfree(work);
9341 }
9342
9343 static void do_intel_finish_page_flip(struct drm_device *dev,
9344 struct drm_crtc *crtc)
9345 {
9346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9347 struct intel_unpin_work *work;
9348 unsigned long flags;
9349
9350 /* Ignore early vblank irqs */
9351 if (intel_crtc == NULL)
9352 return;
9353
9354 /*
9355 * This is called both by irq handlers and the reset code (to complete
9356 * lost pageflips) so needs the full irqsave spinlocks.
9357 */
9358 spin_lock_irqsave(&dev->event_lock, flags);
9359 work = intel_crtc->unpin_work;
9360
9361 /* Ensure we don't miss a work->pending update ... */
9362 smp_rmb();
9363
9364 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9365 spin_unlock_irqrestore(&dev->event_lock, flags);
9366 return;
9367 }
9368
9369 page_flip_completed(intel_crtc);
9370
9371 spin_unlock_irqrestore(&dev->event_lock, flags);
9372 }
9373
9374 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9375 {
9376 struct drm_i915_private *dev_priv = dev->dev_private;
9377 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9378
9379 do_intel_finish_page_flip(dev, crtc);
9380 }
9381
9382 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9383 {
9384 struct drm_i915_private *dev_priv = dev->dev_private;
9385 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9386
9387 do_intel_finish_page_flip(dev, crtc);
9388 }
9389
9390 /* Is 'a' after or equal to 'b'? */
9391 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9392 {
9393 return !((a - b) & 0x80000000);
9394 }
9395
9396 static bool page_flip_finished(struct intel_crtc *crtc)
9397 {
9398 struct drm_device *dev = crtc->base.dev;
9399 struct drm_i915_private *dev_priv = dev->dev_private;
9400
9401 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9402 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9403 return true;
9404
9405 /*
9406 * The relevant registers doen't exist on pre-ctg.
9407 * As the flip done interrupt doesn't trigger for mmio
9408 * flips on gmch platforms, a flip count check isn't
9409 * really needed there. But since ctg has the registers,
9410 * include it in the check anyway.
9411 */
9412 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9413 return true;
9414
9415 /*
9416 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9417 * used the same base address. In that case the mmio flip might
9418 * have completed, but the CS hasn't even executed the flip yet.
9419 *
9420 * A flip count check isn't enough as the CS might have updated
9421 * the base address just after start of vblank, but before we
9422 * managed to process the interrupt. This means we'd complete the
9423 * CS flip too soon.
9424 *
9425 * Combining both checks should get us a good enough result. It may
9426 * still happen that the CS flip has been executed, but has not
9427 * yet actually completed. But in case the base address is the same
9428 * anyway, we don't really care.
9429 */
9430 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9431 crtc->unpin_work->gtt_offset &&
9432 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9433 crtc->unpin_work->flip_count);
9434 }
9435
9436 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9437 {
9438 struct drm_i915_private *dev_priv = dev->dev_private;
9439 struct intel_crtc *intel_crtc =
9440 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9441 unsigned long flags;
9442
9443
9444 /*
9445 * This is called both by irq handlers and the reset code (to complete
9446 * lost pageflips) so needs the full irqsave spinlocks.
9447 *
9448 * NB: An MMIO update of the plane base pointer will also
9449 * generate a page-flip completion irq, i.e. every modeset
9450 * is also accompanied by a spurious intel_prepare_page_flip().
9451 */
9452 spin_lock_irqsave(&dev->event_lock, flags);
9453 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9454 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9455 spin_unlock_irqrestore(&dev->event_lock, flags);
9456 }
9457
9458 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9459 {
9460 /* Ensure that the work item is consistent when activating it ... */
9461 smp_wmb();
9462 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9463 /* and that it is marked active as soon as the irq could fire. */
9464 smp_wmb();
9465 }
9466
9467 static int intel_gen2_queue_flip(struct drm_device *dev,
9468 struct drm_crtc *crtc,
9469 struct drm_framebuffer *fb,
9470 struct drm_i915_gem_object *obj,
9471 struct intel_engine_cs *ring,
9472 uint32_t flags)
9473 {
9474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9475 u32 flip_mask;
9476 int ret;
9477
9478 ret = intel_ring_begin(ring, 6);
9479 if (ret)
9480 return ret;
9481
9482 /* Can't queue multiple flips, so wait for the previous
9483 * one to finish before executing the next.
9484 */
9485 if (intel_crtc->plane)
9486 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9487 else
9488 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9489 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9490 intel_ring_emit(ring, MI_NOOP);
9491 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9492 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9493 intel_ring_emit(ring, fb->pitches[0]);
9494 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9495 intel_ring_emit(ring, 0); /* aux display base address, unused */
9496
9497 intel_mark_page_flip_active(intel_crtc);
9498 __intel_ring_advance(ring);
9499 return 0;
9500 }
9501
9502 static int intel_gen3_queue_flip(struct drm_device *dev,
9503 struct drm_crtc *crtc,
9504 struct drm_framebuffer *fb,
9505 struct drm_i915_gem_object *obj,
9506 struct intel_engine_cs *ring,
9507 uint32_t flags)
9508 {
9509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9510 u32 flip_mask;
9511 int ret;
9512
9513 ret = intel_ring_begin(ring, 6);
9514 if (ret)
9515 return ret;
9516
9517 if (intel_crtc->plane)
9518 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9519 else
9520 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9521 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9522 intel_ring_emit(ring, MI_NOOP);
9523 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9524 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9525 intel_ring_emit(ring, fb->pitches[0]);
9526 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9527 intel_ring_emit(ring, MI_NOOP);
9528
9529 intel_mark_page_flip_active(intel_crtc);
9530 __intel_ring_advance(ring);
9531 return 0;
9532 }
9533
9534 static int intel_gen4_queue_flip(struct drm_device *dev,
9535 struct drm_crtc *crtc,
9536 struct drm_framebuffer *fb,
9537 struct drm_i915_gem_object *obj,
9538 struct intel_engine_cs *ring,
9539 uint32_t flags)
9540 {
9541 struct drm_i915_private *dev_priv = dev->dev_private;
9542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9543 uint32_t pf, pipesrc;
9544 int ret;
9545
9546 ret = intel_ring_begin(ring, 4);
9547 if (ret)
9548 return ret;
9549
9550 /* i965+ uses the linear or tiled offsets from the
9551 * Display Registers (which do not change across a page-flip)
9552 * so we need only reprogram the base address.
9553 */
9554 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9555 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9556 intel_ring_emit(ring, fb->pitches[0]);
9557 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9558 obj->tiling_mode);
9559
9560 /* XXX Enabling the panel-fitter across page-flip is so far
9561 * untested on non-native modes, so ignore it for now.
9562 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9563 */
9564 pf = 0;
9565 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9566 intel_ring_emit(ring, pf | pipesrc);
9567
9568 intel_mark_page_flip_active(intel_crtc);
9569 __intel_ring_advance(ring);
9570 return 0;
9571 }
9572
9573 static int intel_gen6_queue_flip(struct drm_device *dev,
9574 struct drm_crtc *crtc,
9575 struct drm_framebuffer *fb,
9576 struct drm_i915_gem_object *obj,
9577 struct intel_engine_cs *ring,
9578 uint32_t flags)
9579 {
9580 struct drm_i915_private *dev_priv = dev->dev_private;
9581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9582 uint32_t pf, pipesrc;
9583 int ret;
9584
9585 ret = intel_ring_begin(ring, 4);
9586 if (ret)
9587 return ret;
9588
9589 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9590 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9591 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9592 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9593
9594 /* Contrary to the suggestions in the documentation,
9595 * "Enable Panel Fitter" does not seem to be required when page
9596 * flipping with a non-native mode, and worse causes a normal
9597 * modeset to fail.
9598 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9599 */
9600 pf = 0;
9601 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9602 intel_ring_emit(ring, pf | pipesrc);
9603
9604 intel_mark_page_flip_active(intel_crtc);
9605 __intel_ring_advance(ring);
9606 return 0;
9607 }
9608
9609 static int intel_gen7_queue_flip(struct drm_device *dev,
9610 struct drm_crtc *crtc,
9611 struct drm_framebuffer *fb,
9612 struct drm_i915_gem_object *obj,
9613 struct intel_engine_cs *ring,
9614 uint32_t flags)
9615 {
9616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9617 uint32_t plane_bit = 0;
9618 int len, ret;
9619
9620 switch (intel_crtc->plane) {
9621 case PLANE_A:
9622 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9623 break;
9624 case PLANE_B:
9625 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9626 break;
9627 case PLANE_C:
9628 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9629 break;
9630 default:
9631 WARN_ONCE(1, "unknown plane in flip command\n");
9632 return -ENODEV;
9633 }
9634
9635 len = 4;
9636 if (ring->id == RCS) {
9637 len += 6;
9638 /*
9639 * On Gen 8, SRM is now taking an extra dword to accommodate
9640 * 48bits addresses, and we need a NOOP for the batch size to
9641 * stay even.
9642 */
9643 if (IS_GEN8(dev))
9644 len += 2;
9645 }
9646
9647 /*
9648 * BSpec MI_DISPLAY_FLIP for IVB:
9649 * "The full packet must be contained within the same cache line."
9650 *
9651 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9652 * cacheline, if we ever start emitting more commands before
9653 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9654 * then do the cacheline alignment, and finally emit the
9655 * MI_DISPLAY_FLIP.
9656 */
9657 ret = intel_ring_cacheline_align(ring);
9658 if (ret)
9659 return ret;
9660
9661 ret = intel_ring_begin(ring, len);
9662 if (ret)
9663 return ret;
9664
9665 /* Unmask the flip-done completion message. Note that the bspec says that
9666 * we should do this for both the BCS and RCS, and that we must not unmask
9667 * more than one flip event at any time (or ensure that one flip message
9668 * can be sent by waiting for flip-done prior to queueing new flips).
9669 * Experimentation says that BCS works despite DERRMR masking all
9670 * flip-done completion events and that unmasking all planes at once
9671 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9672 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9673 */
9674 if (ring->id == RCS) {
9675 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9676 intel_ring_emit(ring, DERRMR);
9677 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9678 DERRMR_PIPEB_PRI_FLIP_DONE |
9679 DERRMR_PIPEC_PRI_FLIP_DONE));
9680 if (IS_GEN8(dev))
9681 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9682 MI_SRM_LRM_GLOBAL_GTT);
9683 else
9684 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9685 MI_SRM_LRM_GLOBAL_GTT);
9686 intel_ring_emit(ring, DERRMR);
9687 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9688 if (IS_GEN8(dev)) {
9689 intel_ring_emit(ring, 0);
9690 intel_ring_emit(ring, MI_NOOP);
9691 }
9692 }
9693
9694 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9695 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9696 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9697 intel_ring_emit(ring, (MI_NOOP));
9698
9699 intel_mark_page_flip_active(intel_crtc);
9700 __intel_ring_advance(ring);
9701 return 0;
9702 }
9703
9704 static bool use_mmio_flip(struct intel_engine_cs *ring,
9705 struct drm_i915_gem_object *obj)
9706 {
9707 /*
9708 * This is not being used for older platforms, because
9709 * non-availability of flip done interrupt forces us to use
9710 * CS flips. Older platforms derive flip done using some clever
9711 * tricks involving the flip_pending status bits and vblank irqs.
9712 * So using MMIO flips there would disrupt this mechanism.
9713 */
9714
9715 if (ring == NULL)
9716 return true;
9717
9718 if (INTEL_INFO(ring->dev)->gen < 5)
9719 return false;
9720
9721 if (i915.use_mmio_flip < 0)
9722 return false;
9723 else if (i915.use_mmio_flip > 0)
9724 return true;
9725 else if (i915.enable_execlists)
9726 return true;
9727 else
9728 return ring != i915_gem_request_get_ring(obj->last_read_req);
9729 }
9730
9731 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9732 {
9733 struct drm_device *dev = intel_crtc->base.dev;
9734 struct drm_i915_private *dev_priv = dev->dev_private;
9735 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9736 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9737 struct drm_i915_gem_object *obj = intel_fb->obj;
9738 const enum pipe pipe = intel_crtc->pipe;
9739 u32 ctl, stride;
9740
9741 ctl = I915_READ(PLANE_CTL(pipe, 0));
9742 ctl &= ~PLANE_CTL_TILED_MASK;
9743 if (obj->tiling_mode == I915_TILING_X)
9744 ctl |= PLANE_CTL_TILED_X;
9745
9746 /*
9747 * The stride is either expressed as a multiple of 64 bytes chunks for
9748 * linear buffers or in number of tiles for tiled buffers.
9749 */
9750 stride = fb->pitches[0] >> 6;
9751 if (obj->tiling_mode == I915_TILING_X)
9752 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9753
9754 /*
9755 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9756 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9757 */
9758 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9759 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9760
9761 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9762 POSTING_READ(PLANE_SURF(pipe, 0));
9763 }
9764
9765 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9766 {
9767 struct drm_device *dev = intel_crtc->base.dev;
9768 struct drm_i915_private *dev_priv = dev->dev_private;
9769 struct intel_framebuffer *intel_fb =
9770 to_intel_framebuffer(intel_crtc->base.primary->fb);
9771 struct drm_i915_gem_object *obj = intel_fb->obj;
9772 u32 dspcntr;
9773 u32 reg;
9774
9775 reg = DSPCNTR(intel_crtc->plane);
9776 dspcntr = I915_READ(reg);
9777
9778 if (obj->tiling_mode != I915_TILING_NONE)
9779 dspcntr |= DISPPLANE_TILED;
9780 else
9781 dspcntr &= ~DISPPLANE_TILED;
9782
9783 I915_WRITE(reg, dspcntr);
9784
9785 I915_WRITE(DSPSURF(intel_crtc->plane),
9786 intel_crtc->unpin_work->gtt_offset);
9787 POSTING_READ(DSPSURF(intel_crtc->plane));
9788
9789 }
9790
9791 /*
9792 * XXX: This is the temporary way to update the plane registers until we get
9793 * around to using the usual plane update functions for MMIO flips
9794 */
9795 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9796 {
9797 struct drm_device *dev = intel_crtc->base.dev;
9798 bool atomic_update;
9799 u32 start_vbl_count;
9800
9801 intel_mark_page_flip_active(intel_crtc);
9802
9803 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9804
9805 if (INTEL_INFO(dev)->gen >= 9)
9806 skl_do_mmio_flip(intel_crtc);
9807 else
9808 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9809 ilk_do_mmio_flip(intel_crtc);
9810
9811 if (atomic_update)
9812 intel_pipe_update_end(intel_crtc, start_vbl_count);
9813 }
9814
9815 static void intel_mmio_flip_work_func(struct work_struct *work)
9816 {
9817 struct intel_crtc *crtc =
9818 container_of(work, struct intel_crtc, mmio_flip.work);
9819 struct intel_mmio_flip *mmio_flip;
9820
9821 mmio_flip = &crtc->mmio_flip;
9822 if (mmio_flip->req)
9823 WARN_ON(__i915_wait_request(mmio_flip->req,
9824 crtc->reset_counter,
9825 false, NULL, NULL) != 0);
9826
9827 intel_do_mmio_flip(crtc);
9828 if (mmio_flip->req) {
9829 mutex_lock(&crtc->base.dev->struct_mutex);
9830 i915_gem_request_assign(&mmio_flip->req, NULL);
9831 mutex_unlock(&crtc->base.dev->struct_mutex);
9832 }
9833 }
9834
9835 static int intel_queue_mmio_flip(struct drm_device *dev,
9836 struct drm_crtc *crtc,
9837 struct drm_framebuffer *fb,
9838 struct drm_i915_gem_object *obj,
9839 struct intel_engine_cs *ring,
9840 uint32_t flags)
9841 {
9842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9843
9844 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9845 obj->last_write_req);
9846
9847 schedule_work(&intel_crtc->mmio_flip.work);
9848
9849 return 0;
9850 }
9851
9852 static int intel_default_queue_flip(struct drm_device *dev,
9853 struct drm_crtc *crtc,
9854 struct drm_framebuffer *fb,
9855 struct drm_i915_gem_object *obj,
9856 struct intel_engine_cs *ring,
9857 uint32_t flags)
9858 {
9859 return -ENODEV;
9860 }
9861
9862 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9863 struct drm_crtc *crtc)
9864 {
9865 struct drm_i915_private *dev_priv = dev->dev_private;
9866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9867 struct intel_unpin_work *work = intel_crtc->unpin_work;
9868 u32 addr;
9869
9870 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9871 return true;
9872
9873 if (!work->enable_stall_check)
9874 return false;
9875
9876 if (work->flip_ready_vblank == 0) {
9877 if (work->flip_queued_req &&
9878 !i915_gem_request_completed(work->flip_queued_req, true))
9879 return false;
9880
9881 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9882 }
9883
9884 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9885 return false;
9886
9887 /* Potential stall - if we see that the flip has happened,
9888 * assume a missed interrupt. */
9889 if (INTEL_INFO(dev)->gen >= 4)
9890 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9891 else
9892 addr = I915_READ(DSPADDR(intel_crtc->plane));
9893
9894 /* There is a potential issue here with a false positive after a flip
9895 * to the same address. We could address this by checking for a
9896 * non-incrementing frame counter.
9897 */
9898 return addr == work->gtt_offset;
9899 }
9900
9901 void intel_check_page_flip(struct drm_device *dev, int pipe)
9902 {
9903 struct drm_i915_private *dev_priv = dev->dev_private;
9904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9906
9907 WARN_ON(!in_interrupt());
9908
9909 if (crtc == NULL)
9910 return;
9911
9912 spin_lock(&dev->event_lock);
9913 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9914 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9915 intel_crtc->unpin_work->flip_queued_vblank,
9916 drm_vblank_count(dev, pipe));
9917 page_flip_completed(intel_crtc);
9918 }
9919 spin_unlock(&dev->event_lock);
9920 }
9921
9922 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9923 struct drm_framebuffer *fb,
9924 struct drm_pending_vblank_event *event,
9925 uint32_t page_flip_flags)
9926 {
9927 struct drm_device *dev = crtc->dev;
9928 struct drm_i915_private *dev_priv = dev->dev_private;
9929 struct drm_framebuffer *old_fb = crtc->primary->fb;
9930 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9932 struct drm_plane *primary = crtc->primary;
9933 enum pipe pipe = intel_crtc->pipe;
9934 struct intel_unpin_work *work;
9935 struct intel_engine_cs *ring;
9936 int ret;
9937
9938 /*
9939 * drm_mode_page_flip_ioctl() should already catch this, but double
9940 * check to be safe. In the future we may enable pageflipping from
9941 * a disabled primary plane.
9942 */
9943 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9944 return -EBUSY;
9945
9946 /* Can't change pixel format via MI display flips. */
9947 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9948 return -EINVAL;
9949
9950 /*
9951 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9952 * Note that pitch changes could also affect these register.
9953 */
9954 if (INTEL_INFO(dev)->gen > 3 &&
9955 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9956 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9957 return -EINVAL;
9958
9959 if (i915_terminally_wedged(&dev_priv->gpu_error))
9960 goto out_hang;
9961
9962 work = kzalloc(sizeof(*work), GFP_KERNEL);
9963 if (work == NULL)
9964 return -ENOMEM;
9965
9966 work->event = event;
9967 work->crtc = crtc;
9968 work->old_fb = old_fb;
9969 INIT_WORK(&work->work, intel_unpin_work_fn);
9970
9971 ret = drm_crtc_vblank_get(crtc);
9972 if (ret)
9973 goto free_work;
9974
9975 /* We borrow the event spin lock for protecting unpin_work */
9976 spin_lock_irq(&dev->event_lock);
9977 if (intel_crtc->unpin_work) {
9978 /* Before declaring the flip queue wedged, check if
9979 * the hardware completed the operation behind our backs.
9980 */
9981 if (__intel_pageflip_stall_check(dev, crtc)) {
9982 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9983 page_flip_completed(intel_crtc);
9984 } else {
9985 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9986 spin_unlock_irq(&dev->event_lock);
9987
9988 drm_crtc_vblank_put(crtc);
9989 kfree(work);
9990 return -EBUSY;
9991 }
9992 }
9993 intel_crtc->unpin_work = work;
9994 spin_unlock_irq(&dev->event_lock);
9995
9996 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9997 flush_workqueue(dev_priv->wq);
9998
9999 /* Reference the objects for the scheduled work. */
10000 drm_framebuffer_reference(work->old_fb);
10001 drm_gem_object_reference(&obj->base);
10002
10003 crtc->primary->fb = fb;
10004 update_state_fb(crtc->primary);
10005
10006 work->pending_flip_obj = obj;
10007
10008 ret = i915_mutex_lock_interruptible(dev);
10009 if (ret)
10010 goto cleanup;
10011
10012 atomic_inc(&intel_crtc->unpin_work_count);
10013 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10014
10015 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10016 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10017
10018 if (IS_VALLEYVIEW(dev)) {
10019 ring = &dev_priv->ring[BCS];
10020 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10021 /* vlv: DISPLAY_FLIP fails to change tiling */
10022 ring = NULL;
10023 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10024 ring = &dev_priv->ring[BCS];
10025 } else if (INTEL_INFO(dev)->gen >= 7) {
10026 ring = i915_gem_request_get_ring(obj->last_read_req);
10027 if (ring == NULL || ring->id != RCS)
10028 ring = &dev_priv->ring[BCS];
10029 } else {
10030 ring = &dev_priv->ring[RCS];
10031 }
10032
10033 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10034 crtc->primary->state, ring);
10035 if (ret)
10036 goto cleanup_pending;
10037
10038 work->gtt_offset =
10039 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10040
10041 if (use_mmio_flip(ring, obj)) {
10042 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10043 page_flip_flags);
10044 if (ret)
10045 goto cleanup_unpin;
10046
10047 i915_gem_request_assign(&work->flip_queued_req,
10048 obj->last_write_req);
10049 } else {
10050 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10051 page_flip_flags);
10052 if (ret)
10053 goto cleanup_unpin;
10054
10055 i915_gem_request_assign(&work->flip_queued_req,
10056 intel_ring_get_request(ring));
10057 }
10058
10059 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10060 work->enable_stall_check = true;
10061
10062 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10063 INTEL_FRONTBUFFER_PRIMARY(pipe));
10064
10065 intel_fbc_disable(dev);
10066 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10067 mutex_unlock(&dev->struct_mutex);
10068
10069 trace_i915_flip_request(intel_crtc->plane, obj);
10070
10071 return 0;
10072
10073 cleanup_unpin:
10074 intel_unpin_fb_obj(fb, crtc->primary->state);
10075 cleanup_pending:
10076 atomic_dec(&intel_crtc->unpin_work_count);
10077 mutex_unlock(&dev->struct_mutex);
10078 cleanup:
10079 crtc->primary->fb = old_fb;
10080 update_state_fb(crtc->primary);
10081
10082 drm_gem_object_unreference_unlocked(&obj->base);
10083 drm_framebuffer_unreference(work->old_fb);
10084
10085 spin_lock_irq(&dev->event_lock);
10086 intel_crtc->unpin_work = NULL;
10087 spin_unlock_irq(&dev->event_lock);
10088
10089 drm_crtc_vblank_put(crtc);
10090 free_work:
10091 kfree(work);
10092
10093 if (ret == -EIO) {
10094 out_hang:
10095 ret = intel_plane_restore(primary);
10096 if (ret == 0 && event) {
10097 spin_lock_irq(&dev->event_lock);
10098 drm_send_vblank_event(dev, pipe, event);
10099 spin_unlock_irq(&dev->event_lock);
10100 }
10101 }
10102 return ret;
10103 }
10104
10105 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10106 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10107 .load_lut = intel_crtc_load_lut,
10108 .atomic_begin = intel_begin_crtc_commit,
10109 .atomic_flush = intel_finish_crtc_commit,
10110 };
10111
10112 /**
10113 * intel_modeset_update_staged_output_state
10114 *
10115 * Updates the staged output configuration state, e.g. after we've read out the
10116 * current hw state.
10117 */
10118 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10119 {
10120 struct intel_crtc *crtc;
10121 struct intel_encoder *encoder;
10122 struct intel_connector *connector;
10123
10124 for_each_intel_connector(dev, connector) {
10125 connector->new_encoder =
10126 to_intel_encoder(connector->base.encoder);
10127 }
10128
10129 for_each_intel_encoder(dev, encoder) {
10130 encoder->new_crtc =
10131 to_intel_crtc(encoder->base.crtc);
10132 }
10133
10134 for_each_intel_crtc(dev, crtc) {
10135 crtc->new_enabled = crtc->base.state->enable;
10136
10137 if (crtc->new_enabled)
10138 crtc->new_config = crtc->config;
10139 else
10140 crtc->new_config = NULL;
10141 }
10142 }
10143
10144 /**
10145 * intel_modeset_commit_output_state
10146 *
10147 * This function copies the stage display pipe configuration to the real one.
10148 */
10149 static void intel_modeset_commit_output_state(struct drm_device *dev)
10150 {
10151 struct intel_crtc *crtc;
10152 struct intel_encoder *encoder;
10153 struct intel_connector *connector;
10154
10155 for_each_intel_connector(dev, connector) {
10156 connector->base.encoder = &connector->new_encoder->base;
10157 }
10158
10159 for_each_intel_encoder(dev, encoder) {
10160 encoder->base.crtc = &encoder->new_crtc->base;
10161 }
10162
10163 for_each_intel_crtc(dev, crtc) {
10164 crtc->base.state->enable = crtc->new_enabled;
10165 crtc->base.enabled = crtc->new_enabled;
10166 }
10167 }
10168
10169 static void
10170 connected_sink_compute_bpp(struct intel_connector *connector,
10171 struct intel_crtc_state *pipe_config)
10172 {
10173 int bpp = pipe_config->pipe_bpp;
10174
10175 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10176 connector->base.base.id,
10177 connector->base.name);
10178
10179 /* Don't use an invalid EDID bpc value */
10180 if (connector->base.display_info.bpc &&
10181 connector->base.display_info.bpc * 3 < bpp) {
10182 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10183 bpp, connector->base.display_info.bpc*3);
10184 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10185 }
10186
10187 /* Clamp bpp to 8 on screens without EDID 1.4 */
10188 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10189 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10190 bpp);
10191 pipe_config->pipe_bpp = 24;
10192 }
10193 }
10194
10195 static int
10196 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10197 struct drm_framebuffer *fb,
10198 struct intel_crtc_state *pipe_config)
10199 {
10200 struct drm_device *dev = crtc->base.dev;
10201 struct intel_connector *connector;
10202 int bpp;
10203
10204 switch (fb->pixel_format) {
10205 case DRM_FORMAT_C8:
10206 bpp = 8*3; /* since we go through a colormap */
10207 break;
10208 case DRM_FORMAT_XRGB1555:
10209 case DRM_FORMAT_ARGB1555:
10210 /* checked in intel_framebuffer_init already */
10211 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10212 return -EINVAL;
10213 case DRM_FORMAT_RGB565:
10214 bpp = 6*3; /* min is 18bpp */
10215 break;
10216 case DRM_FORMAT_XBGR8888:
10217 case DRM_FORMAT_ABGR8888:
10218 /* checked in intel_framebuffer_init already */
10219 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10220 return -EINVAL;
10221 case DRM_FORMAT_XRGB8888:
10222 case DRM_FORMAT_ARGB8888:
10223 bpp = 8*3;
10224 break;
10225 case DRM_FORMAT_XRGB2101010:
10226 case DRM_FORMAT_ARGB2101010:
10227 case DRM_FORMAT_XBGR2101010:
10228 case DRM_FORMAT_ABGR2101010:
10229 /* checked in intel_framebuffer_init already */
10230 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10231 return -EINVAL;
10232 bpp = 10*3;
10233 break;
10234 /* TODO: gen4+ supports 16 bpc floating point, too. */
10235 default:
10236 DRM_DEBUG_KMS("unsupported depth\n");
10237 return -EINVAL;
10238 }
10239
10240 pipe_config->pipe_bpp = bpp;
10241
10242 /* Clamp display bpp to EDID value */
10243 for_each_intel_connector(dev, connector) {
10244 if (!connector->new_encoder ||
10245 connector->new_encoder->new_crtc != crtc)
10246 continue;
10247
10248 connected_sink_compute_bpp(connector, pipe_config);
10249 }
10250
10251 return bpp;
10252 }
10253
10254 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10255 {
10256 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10257 "type: 0x%x flags: 0x%x\n",
10258 mode->crtc_clock,
10259 mode->crtc_hdisplay, mode->crtc_hsync_start,
10260 mode->crtc_hsync_end, mode->crtc_htotal,
10261 mode->crtc_vdisplay, mode->crtc_vsync_start,
10262 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10263 }
10264
10265 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10266 struct intel_crtc_state *pipe_config,
10267 const char *context)
10268 {
10269 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10270 context, pipe_name(crtc->pipe));
10271
10272 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10273 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10274 pipe_config->pipe_bpp, pipe_config->dither);
10275 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10276 pipe_config->has_pch_encoder,
10277 pipe_config->fdi_lanes,
10278 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10279 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10280 pipe_config->fdi_m_n.tu);
10281 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10282 pipe_config->has_dp_encoder,
10283 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10284 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10285 pipe_config->dp_m_n.tu);
10286
10287 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10288 pipe_config->has_dp_encoder,
10289 pipe_config->dp_m2_n2.gmch_m,
10290 pipe_config->dp_m2_n2.gmch_n,
10291 pipe_config->dp_m2_n2.link_m,
10292 pipe_config->dp_m2_n2.link_n,
10293 pipe_config->dp_m2_n2.tu);
10294
10295 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10296 pipe_config->has_audio,
10297 pipe_config->has_infoframe);
10298
10299 DRM_DEBUG_KMS("requested mode:\n");
10300 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10301 DRM_DEBUG_KMS("adjusted mode:\n");
10302 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10303 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10304 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10305 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10306 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10307 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10308 pipe_config->gmch_pfit.control,
10309 pipe_config->gmch_pfit.pgm_ratios,
10310 pipe_config->gmch_pfit.lvds_border_bits);
10311 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10312 pipe_config->pch_pfit.pos,
10313 pipe_config->pch_pfit.size,
10314 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10315 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10316 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10317 }
10318
10319 static bool encoders_cloneable(const struct intel_encoder *a,
10320 const struct intel_encoder *b)
10321 {
10322 /* masks could be asymmetric, so check both ways */
10323 return a == b || (a->cloneable & (1 << b->type) &&
10324 b->cloneable & (1 << a->type));
10325 }
10326
10327 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10328 struct intel_encoder *encoder)
10329 {
10330 struct drm_device *dev = crtc->base.dev;
10331 struct intel_encoder *source_encoder;
10332
10333 for_each_intel_encoder(dev, source_encoder) {
10334 if (source_encoder->new_crtc != crtc)
10335 continue;
10336
10337 if (!encoders_cloneable(encoder, source_encoder))
10338 return false;
10339 }
10340
10341 return true;
10342 }
10343
10344 static bool check_encoder_cloning(struct intel_crtc *crtc)
10345 {
10346 struct drm_device *dev = crtc->base.dev;
10347 struct intel_encoder *encoder;
10348
10349 for_each_intel_encoder(dev, encoder) {
10350 if (encoder->new_crtc != crtc)
10351 continue;
10352
10353 if (!check_single_encoder_cloning(crtc, encoder))
10354 return false;
10355 }
10356
10357 return true;
10358 }
10359
10360 static bool check_digital_port_conflicts(struct drm_device *dev)
10361 {
10362 struct intel_connector *connector;
10363 unsigned int used_ports = 0;
10364
10365 /*
10366 * Walk the connector list instead of the encoder
10367 * list to detect the problem on ddi platforms
10368 * where there's just one encoder per digital port.
10369 */
10370 for_each_intel_connector(dev, connector) {
10371 struct intel_encoder *encoder = connector->new_encoder;
10372
10373 if (!encoder)
10374 continue;
10375
10376 WARN_ON(!encoder->new_crtc);
10377
10378 switch (encoder->type) {
10379 unsigned int port_mask;
10380 case INTEL_OUTPUT_UNKNOWN:
10381 if (WARN_ON(!HAS_DDI(dev)))
10382 break;
10383 case INTEL_OUTPUT_DISPLAYPORT:
10384 case INTEL_OUTPUT_HDMI:
10385 case INTEL_OUTPUT_EDP:
10386 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10387
10388 /* the same port mustn't appear more than once */
10389 if (used_ports & port_mask)
10390 return false;
10391
10392 used_ports |= port_mask;
10393 default:
10394 break;
10395 }
10396 }
10397
10398 return true;
10399 }
10400
10401 static struct intel_crtc_state *
10402 intel_modeset_pipe_config(struct drm_crtc *crtc,
10403 struct drm_framebuffer *fb,
10404 struct drm_display_mode *mode)
10405 {
10406 struct drm_device *dev = crtc->dev;
10407 struct intel_encoder *encoder;
10408 struct intel_crtc_state *pipe_config;
10409 int plane_bpp, ret = -EINVAL;
10410 bool retry = true;
10411
10412 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10413 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10414 return ERR_PTR(-EINVAL);
10415 }
10416
10417 if (!check_digital_port_conflicts(dev)) {
10418 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10419 return ERR_PTR(-EINVAL);
10420 }
10421
10422 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10423 if (!pipe_config)
10424 return ERR_PTR(-ENOMEM);
10425
10426 pipe_config->base.crtc = crtc;
10427 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10428 drm_mode_copy(&pipe_config->base.mode, mode);
10429
10430 pipe_config->cpu_transcoder =
10431 (enum transcoder) to_intel_crtc(crtc)->pipe;
10432 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10433
10434 /*
10435 * Sanitize sync polarity flags based on requested ones. If neither
10436 * positive or negative polarity is requested, treat this as meaning
10437 * negative polarity.
10438 */
10439 if (!(pipe_config->base.adjusted_mode.flags &
10440 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10441 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10442
10443 if (!(pipe_config->base.adjusted_mode.flags &
10444 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10445 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10446
10447 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10448 * plane pixel format and any sink constraints into account. Returns the
10449 * source plane bpp so that dithering can be selected on mismatches
10450 * after encoders and crtc also have had their say. */
10451 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10452 fb, pipe_config);
10453 if (plane_bpp < 0)
10454 goto fail;
10455
10456 /*
10457 * Determine the real pipe dimensions. Note that stereo modes can
10458 * increase the actual pipe size due to the frame doubling and
10459 * insertion of additional space for blanks between the frame. This
10460 * is stored in the crtc timings. We use the requested mode to do this
10461 * computation to clearly distinguish it from the adjusted mode, which
10462 * can be changed by the connectors in the below retry loop.
10463 */
10464 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10465 &pipe_config->pipe_src_w,
10466 &pipe_config->pipe_src_h);
10467
10468 encoder_retry:
10469 /* Ensure the port clock defaults are reset when retrying. */
10470 pipe_config->port_clock = 0;
10471 pipe_config->pixel_multiplier = 1;
10472
10473 /* Fill in default crtc timings, allow encoders to overwrite them. */
10474 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10475 CRTC_STEREO_DOUBLE);
10476
10477 /* Pass our mode to the connectors and the CRTC to give them a chance to
10478 * adjust it according to limitations or connector properties, and also
10479 * a chance to reject the mode entirely.
10480 */
10481 for_each_intel_encoder(dev, encoder) {
10482
10483 if (&encoder->new_crtc->base != crtc)
10484 continue;
10485
10486 if (!(encoder->compute_config(encoder, pipe_config))) {
10487 DRM_DEBUG_KMS("Encoder config failure\n");
10488 goto fail;
10489 }
10490 }
10491
10492 /* Set default port clock if not overwritten by the encoder. Needs to be
10493 * done afterwards in case the encoder adjusts the mode. */
10494 if (!pipe_config->port_clock)
10495 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10496 * pipe_config->pixel_multiplier;
10497
10498 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10499 if (ret < 0) {
10500 DRM_DEBUG_KMS("CRTC fixup failed\n");
10501 goto fail;
10502 }
10503
10504 if (ret == RETRY) {
10505 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10506 ret = -EINVAL;
10507 goto fail;
10508 }
10509
10510 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10511 retry = false;
10512 goto encoder_retry;
10513 }
10514
10515 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10516 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10517 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10518
10519 return pipe_config;
10520 fail:
10521 kfree(pipe_config);
10522 return ERR_PTR(ret);
10523 }
10524
10525 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10526 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10527 static void
10528 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10529 unsigned *prepare_pipes, unsigned *disable_pipes)
10530 {
10531 struct intel_crtc *intel_crtc;
10532 struct drm_device *dev = crtc->dev;
10533 struct intel_encoder *encoder;
10534 struct intel_connector *connector;
10535 struct drm_crtc *tmp_crtc;
10536
10537 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10538
10539 /* Check which crtcs have changed outputs connected to them, these need
10540 * to be part of the prepare_pipes mask. We don't (yet) support global
10541 * modeset across multiple crtcs, so modeset_pipes will only have one
10542 * bit set at most. */
10543 for_each_intel_connector(dev, connector) {
10544 if (connector->base.encoder == &connector->new_encoder->base)
10545 continue;
10546
10547 if (connector->base.encoder) {
10548 tmp_crtc = connector->base.encoder->crtc;
10549
10550 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10551 }
10552
10553 if (connector->new_encoder)
10554 *prepare_pipes |=
10555 1 << connector->new_encoder->new_crtc->pipe;
10556 }
10557
10558 for_each_intel_encoder(dev, encoder) {
10559 if (encoder->base.crtc == &encoder->new_crtc->base)
10560 continue;
10561
10562 if (encoder->base.crtc) {
10563 tmp_crtc = encoder->base.crtc;
10564
10565 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10566 }
10567
10568 if (encoder->new_crtc)
10569 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10570 }
10571
10572 /* Check for pipes that will be enabled/disabled ... */
10573 for_each_intel_crtc(dev, intel_crtc) {
10574 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10575 continue;
10576
10577 if (!intel_crtc->new_enabled)
10578 *disable_pipes |= 1 << intel_crtc->pipe;
10579 else
10580 *prepare_pipes |= 1 << intel_crtc->pipe;
10581 }
10582
10583
10584 /* set_mode is also used to update properties on life display pipes. */
10585 intel_crtc = to_intel_crtc(crtc);
10586 if (intel_crtc->new_enabled)
10587 *prepare_pipes |= 1 << intel_crtc->pipe;
10588
10589 /*
10590 * For simplicity do a full modeset on any pipe where the output routing
10591 * changed. We could be more clever, but that would require us to be
10592 * more careful with calling the relevant encoder->mode_set functions.
10593 */
10594 if (*prepare_pipes)
10595 *modeset_pipes = *prepare_pipes;
10596
10597 /* ... and mask these out. */
10598 *modeset_pipes &= ~(*disable_pipes);
10599 *prepare_pipes &= ~(*disable_pipes);
10600
10601 /*
10602 * HACK: We don't (yet) fully support global modesets. intel_set_config
10603 * obies this rule, but the modeset restore mode of
10604 * intel_modeset_setup_hw_state does not.
10605 */
10606 *modeset_pipes &= 1 << intel_crtc->pipe;
10607 *prepare_pipes &= 1 << intel_crtc->pipe;
10608
10609 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10610 *modeset_pipes, *prepare_pipes, *disable_pipes);
10611 }
10612
10613 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10614 {
10615 struct drm_encoder *encoder;
10616 struct drm_device *dev = crtc->dev;
10617
10618 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10619 if (encoder->crtc == crtc)
10620 return true;
10621
10622 return false;
10623 }
10624
10625 static void
10626 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10627 {
10628 struct drm_i915_private *dev_priv = dev->dev_private;
10629 struct intel_encoder *intel_encoder;
10630 struct intel_crtc *intel_crtc;
10631 struct drm_connector *connector;
10632
10633 intel_shared_dpll_commit(dev_priv);
10634
10635 for_each_intel_encoder(dev, intel_encoder) {
10636 if (!intel_encoder->base.crtc)
10637 continue;
10638
10639 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10640
10641 if (prepare_pipes & (1 << intel_crtc->pipe))
10642 intel_encoder->connectors_active = false;
10643 }
10644
10645 intel_modeset_commit_output_state(dev);
10646
10647 /* Double check state. */
10648 for_each_intel_crtc(dev, intel_crtc) {
10649 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10650 WARN_ON(intel_crtc->new_config &&
10651 intel_crtc->new_config != intel_crtc->config);
10652 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10653 }
10654
10655 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10656 if (!connector->encoder || !connector->encoder->crtc)
10657 continue;
10658
10659 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10660
10661 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10662 struct drm_property *dpms_property =
10663 dev->mode_config.dpms_property;
10664
10665 connector->dpms = DRM_MODE_DPMS_ON;
10666 drm_object_property_set_value(&connector->base,
10667 dpms_property,
10668 DRM_MODE_DPMS_ON);
10669
10670 intel_encoder = to_intel_encoder(connector->encoder);
10671 intel_encoder->connectors_active = true;
10672 }
10673 }
10674
10675 }
10676
10677 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10678 {
10679 int diff;
10680
10681 if (clock1 == clock2)
10682 return true;
10683
10684 if (!clock1 || !clock2)
10685 return false;
10686
10687 diff = abs(clock1 - clock2);
10688
10689 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10690 return true;
10691
10692 return false;
10693 }
10694
10695 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10696 list_for_each_entry((intel_crtc), \
10697 &(dev)->mode_config.crtc_list, \
10698 base.head) \
10699 if (mask & (1 <<(intel_crtc)->pipe))
10700
10701 static bool
10702 intel_pipe_config_compare(struct drm_device *dev,
10703 struct intel_crtc_state *current_config,
10704 struct intel_crtc_state *pipe_config)
10705 {
10706 #define PIPE_CONF_CHECK_X(name) \
10707 if (current_config->name != pipe_config->name) { \
10708 DRM_ERROR("mismatch in " #name " " \
10709 "(expected 0x%08x, found 0x%08x)\n", \
10710 current_config->name, \
10711 pipe_config->name); \
10712 return false; \
10713 }
10714
10715 #define PIPE_CONF_CHECK_I(name) \
10716 if (current_config->name != pipe_config->name) { \
10717 DRM_ERROR("mismatch in " #name " " \
10718 "(expected %i, found %i)\n", \
10719 current_config->name, \
10720 pipe_config->name); \
10721 return false; \
10722 }
10723
10724 /* This is required for BDW+ where there is only one set of registers for
10725 * switching between high and low RR.
10726 * This macro can be used whenever a comparison has to be made between one
10727 * hw state and multiple sw state variables.
10728 */
10729 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10730 if ((current_config->name != pipe_config->name) && \
10731 (current_config->alt_name != pipe_config->name)) { \
10732 DRM_ERROR("mismatch in " #name " " \
10733 "(expected %i or %i, found %i)\n", \
10734 current_config->name, \
10735 current_config->alt_name, \
10736 pipe_config->name); \
10737 return false; \
10738 }
10739
10740 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10741 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10742 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10743 "(expected %i, found %i)\n", \
10744 current_config->name & (mask), \
10745 pipe_config->name & (mask)); \
10746 return false; \
10747 }
10748
10749 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10750 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10751 DRM_ERROR("mismatch in " #name " " \
10752 "(expected %i, found %i)\n", \
10753 current_config->name, \
10754 pipe_config->name); \
10755 return false; \
10756 }
10757
10758 #define PIPE_CONF_QUIRK(quirk) \
10759 ((current_config->quirks | pipe_config->quirks) & (quirk))
10760
10761 PIPE_CONF_CHECK_I(cpu_transcoder);
10762
10763 PIPE_CONF_CHECK_I(has_pch_encoder);
10764 PIPE_CONF_CHECK_I(fdi_lanes);
10765 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10766 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10767 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10768 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10769 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10770
10771 PIPE_CONF_CHECK_I(has_dp_encoder);
10772
10773 if (INTEL_INFO(dev)->gen < 8) {
10774 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10775 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10776 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10777 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10778 PIPE_CONF_CHECK_I(dp_m_n.tu);
10779
10780 if (current_config->has_drrs) {
10781 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10782 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10783 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10784 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10785 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10786 }
10787 } else {
10788 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10789 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10790 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10791 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10792 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10793 }
10794
10795 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10796 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10797 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10798 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10799 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10800 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10801
10802 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10803 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10804 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10805 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10806 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10807 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10808
10809 PIPE_CONF_CHECK_I(pixel_multiplier);
10810 PIPE_CONF_CHECK_I(has_hdmi_sink);
10811 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10812 IS_VALLEYVIEW(dev))
10813 PIPE_CONF_CHECK_I(limited_color_range);
10814 PIPE_CONF_CHECK_I(has_infoframe);
10815
10816 PIPE_CONF_CHECK_I(has_audio);
10817
10818 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10819 DRM_MODE_FLAG_INTERLACE);
10820
10821 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10822 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10823 DRM_MODE_FLAG_PHSYNC);
10824 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10825 DRM_MODE_FLAG_NHSYNC);
10826 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10827 DRM_MODE_FLAG_PVSYNC);
10828 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10829 DRM_MODE_FLAG_NVSYNC);
10830 }
10831
10832 PIPE_CONF_CHECK_I(pipe_src_w);
10833 PIPE_CONF_CHECK_I(pipe_src_h);
10834
10835 /*
10836 * FIXME: BIOS likes to set up a cloned config with lvds+external
10837 * screen. Since we don't yet re-compute the pipe config when moving
10838 * just the lvds port away to another pipe the sw tracking won't match.
10839 *
10840 * Proper atomic modesets with recomputed global state will fix this.
10841 * Until then just don't check gmch state for inherited modes.
10842 */
10843 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10844 PIPE_CONF_CHECK_I(gmch_pfit.control);
10845 /* pfit ratios are autocomputed by the hw on gen4+ */
10846 if (INTEL_INFO(dev)->gen < 4)
10847 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10848 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10849 }
10850
10851 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10852 if (current_config->pch_pfit.enabled) {
10853 PIPE_CONF_CHECK_I(pch_pfit.pos);
10854 PIPE_CONF_CHECK_I(pch_pfit.size);
10855 }
10856
10857 /* BDW+ don't expose a synchronous way to read the state */
10858 if (IS_HASWELL(dev))
10859 PIPE_CONF_CHECK_I(ips_enabled);
10860
10861 PIPE_CONF_CHECK_I(double_wide);
10862
10863 PIPE_CONF_CHECK_X(ddi_pll_sel);
10864
10865 PIPE_CONF_CHECK_I(shared_dpll);
10866 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10867 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10868 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10869 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10870 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10871 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10872 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10873 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10874
10875 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10876 PIPE_CONF_CHECK_I(pipe_bpp);
10877
10878 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10879 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10880
10881 #undef PIPE_CONF_CHECK_X
10882 #undef PIPE_CONF_CHECK_I
10883 #undef PIPE_CONF_CHECK_I_ALT
10884 #undef PIPE_CONF_CHECK_FLAGS
10885 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10886 #undef PIPE_CONF_QUIRK
10887
10888 return true;
10889 }
10890
10891 static void check_wm_state(struct drm_device *dev)
10892 {
10893 struct drm_i915_private *dev_priv = dev->dev_private;
10894 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10895 struct intel_crtc *intel_crtc;
10896 int plane;
10897
10898 if (INTEL_INFO(dev)->gen < 9)
10899 return;
10900
10901 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10902 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10903
10904 for_each_intel_crtc(dev, intel_crtc) {
10905 struct skl_ddb_entry *hw_entry, *sw_entry;
10906 const enum pipe pipe = intel_crtc->pipe;
10907
10908 if (!intel_crtc->active)
10909 continue;
10910
10911 /* planes */
10912 for_each_plane(dev_priv, pipe, plane) {
10913 hw_entry = &hw_ddb.plane[pipe][plane];
10914 sw_entry = &sw_ddb->plane[pipe][plane];
10915
10916 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10917 continue;
10918
10919 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10920 "(expected (%u,%u), found (%u,%u))\n",
10921 pipe_name(pipe), plane + 1,
10922 sw_entry->start, sw_entry->end,
10923 hw_entry->start, hw_entry->end);
10924 }
10925
10926 /* cursor */
10927 hw_entry = &hw_ddb.cursor[pipe];
10928 sw_entry = &sw_ddb->cursor[pipe];
10929
10930 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10931 continue;
10932
10933 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10934 "(expected (%u,%u), found (%u,%u))\n",
10935 pipe_name(pipe),
10936 sw_entry->start, sw_entry->end,
10937 hw_entry->start, hw_entry->end);
10938 }
10939 }
10940
10941 static void
10942 check_connector_state(struct drm_device *dev)
10943 {
10944 struct intel_connector *connector;
10945
10946 for_each_intel_connector(dev, connector) {
10947 /* This also checks the encoder/connector hw state with the
10948 * ->get_hw_state callbacks. */
10949 intel_connector_check_state(connector);
10950
10951 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10952 "connector's staged encoder doesn't match current encoder\n");
10953 }
10954 }
10955
10956 static void
10957 check_encoder_state(struct drm_device *dev)
10958 {
10959 struct intel_encoder *encoder;
10960 struct intel_connector *connector;
10961
10962 for_each_intel_encoder(dev, encoder) {
10963 bool enabled = false;
10964 bool active = false;
10965 enum pipe pipe, tracked_pipe;
10966
10967 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10968 encoder->base.base.id,
10969 encoder->base.name);
10970
10971 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10972 "encoder's stage crtc doesn't match current crtc\n");
10973 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10974 "encoder's active_connectors set, but no crtc\n");
10975
10976 for_each_intel_connector(dev, connector) {
10977 if (connector->base.encoder != &encoder->base)
10978 continue;
10979 enabled = true;
10980 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10981 active = true;
10982 }
10983 /*
10984 * for MST connectors if we unplug the connector is gone
10985 * away but the encoder is still connected to a crtc
10986 * until a modeset happens in response to the hotplug.
10987 */
10988 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10989 continue;
10990
10991 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10992 "encoder's enabled state mismatch "
10993 "(expected %i, found %i)\n",
10994 !!encoder->base.crtc, enabled);
10995 I915_STATE_WARN(active && !encoder->base.crtc,
10996 "active encoder with no crtc\n");
10997
10998 I915_STATE_WARN(encoder->connectors_active != active,
10999 "encoder's computed active state doesn't match tracked active state "
11000 "(expected %i, found %i)\n", active, encoder->connectors_active);
11001
11002 active = encoder->get_hw_state(encoder, &pipe);
11003 I915_STATE_WARN(active != encoder->connectors_active,
11004 "encoder's hw state doesn't match sw tracking "
11005 "(expected %i, found %i)\n",
11006 encoder->connectors_active, active);
11007
11008 if (!encoder->base.crtc)
11009 continue;
11010
11011 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11012 I915_STATE_WARN(active && pipe != tracked_pipe,
11013 "active encoder's pipe doesn't match"
11014 "(expected %i, found %i)\n",
11015 tracked_pipe, pipe);
11016
11017 }
11018 }
11019
11020 static void
11021 check_crtc_state(struct drm_device *dev)
11022 {
11023 struct drm_i915_private *dev_priv = dev->dev_private;
11024 struct intel_crtc *crtc;
11025 struct intel_encoder *encoder;
11026 struct intel_crtc_state pipe_config;
11027
11028 for_each_intel_crtc(dev, crtc) {
11029 bool enabled = false;
11030 bool active = false;
11031
11032 memset(&pipe_config, 0, sizeof(pipe_config));
11033
11034 DRM_DEBUG_KMS("[CRTC:%d]\n",
11035 crtc->base.base.id);
11036
11037 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11038 "active crtc, but not enabled in sw tracking\n");
11039
11040 for_each_intel_encoder(dev, encoder) {
11041 if (encoder->base.crtc != &crtc->base)
11042 continue;
11043 enabled = true;
11044 if (encoder->connectors_active)
11045 active = true;
11046 }
11047
11048 I915_STATE_WARN(active != crtc->active,
11049 "crtc's computed active state doesn't match tracked active state "
11050 "(expected %i, found %i)\n", active, crtc->active);
11051 I915_STATE_WARN(enabled != crtc->base.state->enable,
11052 "crtc's computed enabled state doesn't match tracked enabled state "
11053 "(expected %i, found %i)\n", enabled,
11054 crtc->base.state->enable);
11055
11056 active = dev_priv->display.get_pipe_config(crtc,
11057 &pipe_config);
11058
11059 /* hw state is inconsistent with the pipe quirk */
11060 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11061 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11062 active = crtc->active;
11063
11064 for_each_intel_encoder(dev, encoder) {
11065 enum pipe pipe;
11066 if (encoder->base.crtc != &crtc->base)
11067 continue;
11068 if (encoder->get_hw_state(encoder, &pipe))
11069 encoder->get_config(encoder, &pipe_config);
11070 }
11071
11072 I915_STATE_WARN(crtc->active != active,
11073 "crtc active state doesn't match with hw state "
11074 "(expected %i, found %i)\n", crtc->active, active);
11075
11076 if (active &&
11077 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11078 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11079 intel_dump_pipe_config(crtc, &pipe_config,
11080 "[hw state]");
11081 intel_dump_pipe_config(crtc, crtc->config,
11082 "[sw state]");
11083 }
11084 }
11085 }
11086
11087 static void
11088 check_shared_dpll_state(struct drm_device *dev)
11089 {
11090 struct drm_i915_private *dev_priv = dev->dev_private;
11091 struct intel_crtc *crtc;
11092 struct intel_dpll_hw_state dpll_hw_state;
11093 int i;
11094
11095 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11096 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11097 int enabled_crtcs = 0, active_crtcs = 0;
11098 bool active;
11099
11100 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11101
11102 DRM_DEBUG_KMS("%s\n", pll->name);
11103
11104 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11105
11106 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11107 "more active pll users than references: %i vs %i\n",
11108 pll->active, hweight32(pll->config.crtc_mask));
11109 I915_STATE_WARN(pll->active && !pll->on,
11110 "pll in active use but not on in sw tracking\n");
11111 I915_STATE_WARN(pll->on && !pll->active,
11112 "pll in on but not on in use in sw tracking\n");
11113 I915_STATE_WARN(pll->on != active,
11114 "pll on state mismatch (expected %i, found %i)\n",
11115 pll->on, active);
11116
11117 for_each_intel_crtc(dev, crtc) {
11118 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11119 enabled_crtcs++;
11120 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11121 active_crtcs++;
11122 }
11123 I915_STATE_WARN(pll->active != active_crtcs,
11124 "pll active crtcs mismatch (expected %i, found %i)\n",
11125 pll->active, active_crtcs);
11126 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11127 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11128 hweight32(pll->config.crtc_mask), enabled_crtcs);
11129
11130 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11131 sizeof(dpll_hw_state)),
11132 "pll hw state mismatch\n");
11133 }
11134 }
11135
11136 void
11137 intel_modeset_check_state(struct drm_device *dev)
11138 {
11139 check_wm_state(dev);
11140 check_connector_state(dev);
11141 check_encoder_state(dev);
11142 check_crtc_state(dev);
11143 check_shared_dpll_state(dev);
11144 }
11145
11146 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11147 int dotclock)
11148 {
11149 /*
11150 * FDI already provided one idea for the dotclock.
11151 * Yell if the encoder disagrees.
11152 */
11153 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11154 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11155 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11156 }
11157
11158 static void update_scanline_offset(struct intel_crtc *crtc)
11159 {
11160 struct drm_device *dev = crtc->base.dev;
11161
11162 /*
11163 * The scanline counter increments at the leading edge of hsync.
11164 *
11165 * On most platforms it starts counting from vtotal-1 on the
11166 * first active line. That means the scanline counter value is
11167 * always one less than what we would expect. Ie. just after
11168 * start of vblank, which also occurs at start of hsync (on the
11169 * last active line), the scanline counter will read vblank_start-1.
11170 *
11171 * On gen2 the scanline counter starts counting from 1 instead
11172 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11173 * to keep the value positive), instead of adding one.
11174 *
11175 * On HSW+ the behaviour of the scanline counter depends on the output
11176 * type. For DP ports it behaves like most other platforms, but on HDMI
11177 * there's an extra 1 line difference. So we need to add two instead of
11178 * one to the value.
11179 */
11180 if (IS_GEN2(dev)) {
11181 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11182 int vtotal;
11183
11184 vtotal = mode->crtc_vtotal;
11185 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11186 vtotal /= 2;
11187
11188 crtc->scanline_offset = vtotal - 1;
11189 } else if (HAS_DDI(dev) &&
11190 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11191 crtc->scanline_offset = 2;
11192 } else
11193 crtc->scanline_offset = 1;
11194 }
11195
11196 static struct intel_crtc_state *
11197 intel_modeset_compute_config(struct drm_crtc *crtc,
11198 struct drm_display_mode *mode,
11199 struct drm_framebuffer *fb,
11200 unsigned *modeset_pipes,
11201 unsigned *prepare_pipes,
11202 unsigned *disable_pipes)
11203 {
11204 struct intel_crtc_state *pipe_config = NULL;
11205
11206 intel_modeset_affected_pipes(crtc, modeset_pipes,
11207 prepare_pipes, disable_pipes);
11208
11209 if ((*modeset_pipes) == 0)
11210 goto out;
11211
11212 /*
11213 * Note this needs changes when we start tracking multiple modes
11214 * and crtcs. At that point we'll need to compute the whole config
11215 * (i.e. one pipe_config for each crtc) rather than just the one
11216 * for this crtc.
11217 */
11218 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11219 if (IS_ERR(pipe_config)) {
11220 goto out;
11221 }
11222 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11223 "[modeset]");
11224
11225 out:
11226 return pipe_config;
11227 }
11228
11229 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11230 unsigned modeset_pipes,
11231 unsigned disable_pipes)
11232 {
11233 struct drm_i915_private *dev_priv = to_i915(dev);
11234 unsigned clear_pipes = modeset_pipes | disable_pipes;
11235 struct intel_crtc *intel_crtc;
11236 int ret = 0;
11237
11238 if (!dev_priv->display.crtc_compute_clock)
11239 return 0;
11240
11241 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11242 if (ret)
11243 goto done;
11244
11245 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11246 struct intel_crtc_state *state = intel_crtc->new_config;
11247 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11248 state);
11249 if (ret) {
11250 intel_shared_dpll_abort_config(dev_priv);
11251 goto done;
11252 }
11253 }
11254
11255 done:
11256 return ret;
11257 }
11258
11259 static int __intel_set_mode(struct drm_crtc *crtc,
11260 struct drm_display_mode *mode,
11261 int x, int y, struct drm_framebuffer *fb,
11262 struct intel_crtc_state *pipe_config,
11263 unsigned modeset_pipes,
11264 unsigned prepare_pipes,
11265 unsigned disable_pipes)
11266 {
11267 struct drm_device *dev = crtc->dev;
11268 struct drm_i915_private *dev_priv = dev->dev_private;
11269 struct drm_display_mode *saved_mode;
11270 struct intel_crtc *intel_crtc;
11271 int ret = 0;
11272
11273 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11274 if (!saved_mode)
11275 return -ENOMEM;
11276
11277 *saved_mode = crtc->mode;
11278
11279 if (modeset_pipes)
11280 to_intel_crtc(crtc)->new_config = pipe_config;
11281
11282 /*
11283 * See if the config requires any additional preparation, e.g.
11284 * to adjust global state with pipes off. We need to do this
11285 * here so we can get the modeset_pipe updated config for the new
11286 * mode set on this crtc. For other crtcs we need to use the
11287 * adjusted_mode bits in the crtc directly.
11288 */
11289 if (IS_VALLEYVIEW(dev)) {
11290 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11291
11292 /* may have added more to prepare_pipes than we should */
11293 prepare_pipes &= ~disable_pipes;
11294 }
11295
11296 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11297 if (ret)
11298 goto done;
11299
11300 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11301 intel_crtc_disable(&intel_crtc->base);
11302
11303 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11304 if (intel_crtc->base.state->enable)
11305 dev_priv->display.crtc_disable(&intel_crtc->base);
11306 }
11307
11308 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11309 * to set it here already despite that we pass it down the callchain.
11310 *
11311 * Note we'll need to fix this up when we start tracking multiple
11312 * pipes; here we assume a single modeset_pipe and only track the
11313 * single crtc and mode.
11314 */
11315 if (modeset_pipes) {
11316 crtc->mode = *mode;
11317 /* mode_set/enable/disable functions rely on a correct pipe
11318 * config. */
11319 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11320
11321 /*
11322 * Calculate and store various constants which
11323 * are later needed by vblank and swap-completion
11324 * timestamping. They are derived from true hwmode.
11325 */
11326 drm_calc_timestamping_constants(crtc,
11327 &pipe_config->base.adjusted_mode);
11328 }
11329
11330 /* Only after disabling all output pipelines that will be changed can we
11331 * update the the output configuration. */
11332 intel_modeset_update_state(dev, prepare_pipes);
11333
11334 modeset_update_crtc_power_domains(dev);
11335
11336 /* Set up the DPLL and any encoders state that needs to adjust or depend
11337 * on the DPLL.
11338 */
11339 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11340 struct drm_plane *primary = intel_crtc->base.primary;
11341 int vdisplay, hdisplay;
11342
11343 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11344 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11345 fb, 0, 0,
11346 hdisplay, vdisplay,
11347 x << 16, y << 16,
11348 hdisplay << 16, vdisplay << 16);
11349 }
11350
11351 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11352 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11353 update_scanline_offset(intel_crtc);
11354
11355 dev_priv->display.crtc_enable(&intel_crtc->base);
11356 }
11357
11358 /* FIXME: add subpixel order */
11359 done:
11360 if (ret && crtc->state->enable)
11361 crtc->mode = *saved_mode;
11362
11363 kfree(saved_mode);
11364 return ret;
11365 }
11366
11367 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11368 struct drm_display_mode *mode,
11369 int x, int y, struct drm_framebuffer *fb,
11370 struct intel_crtc_state *pipe_config,
11371 unsigned modeset_pipes,
11372 unsigned prepare_pipes,
11373 unsigned disable_pipes)
11374 {
11375 int ret;
11376
11377 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11378 prepare_pipes, disable_pipes);
11379
11380 if (ret == 0)
11381 intel_modeset_check_state(crtc->dev);
11382
11383 return ret;
11384 }
11385
11386 static int intel_set_mode(struct drm_crtc *crtc,
11387 struct drm_display_mode *mode,
11388 int x, int y, struct drm_framebuffer *fb)
11389 {
11390 struct intel_crtc_state *pipe_config;
11391 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11392
11393 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11394 &modeset_pipes,
11395 &prepare_pipes,
11396 &disable_pipes);
11397
11398 if (IS_ERR(pipe_config))
11399 return PTR_ERR(pipe_config);
11400
11401 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11402 modeset_pipes, prepare_pipes,
11403 disable_pipes);
11404 }
11405
11406 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11407 {
11408 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11409 }
11410
11411 #undef for_each_intel_crtc_masked
11412
11413 static void intel_set_config_free(struct intel_set_config *config)
11414 {
11415 if (!config)
11416 return;
11417
11418 kfree(config->save_connector_encoders);
11419 kfree(config->save_encoder_crtcs);
11420 kfree(config->save_crtc_enabled);
11421 kfree(config);
11422 }
11423
11424 static int intel_set_config_save_state(struct drm_device *dev,
11425 struct intel_set_config *config)
11426 {
11427 struct drm_crtc *crtc;
11428 struct drm_encoder *encoder;
11429 struct drm_connector *connector;
11430 int count;
11431
11432 config->save_crtc_enabled =
11433 kcalloc(dev->mode_config.num_crtc,
11434 sizeof(bool), GFP_KERNEL);
11435 if (!config->save_crtc_enabled)
11436 return -ENOMEM;
11437
11438 config->save_encoder_crtcs =
11439 kcalloc(dev->mode_config.num_encoder,
11440 sizeof(struct drm_crtc *), GFP_KERNEL);
11441 if (!config->save_encoder_crtcs)
11442 return -ENOMEM;
11443
11444 config->save_connector_encoders =
11445 kcalloc(dev->mode_config.num_connector,
11446 sizeof(struct drm_encoder *), GFP_KERNEL);
11447 if (!config->save_connector_encoders)
11448 return -ENOMEM;
11449
11450 /* Copy data. Note that driver private data is not affected.
11451 * Should anything bad happen only the expected state is
11452 * restored, not the drivers personal bookkeeping.
11453 */
11454 count = 0;
11455 for_each_crtc(dev, crtc) {
11456 config->save_crtc_enabled[count++] = crtc->state->enable;
11457 }
11458
11459 count = 0;
11460 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11461 config->save_encoder_crtcs[count++] = encoder->crtc;
11462 }
11463
11464 count = 0;
11465 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11466 config->save_connector_encoders[count++] = connector->encoder;
11467 }
11468
11469 return 0;
11470 }
11471
11472 static void intel_set_config_restore_state(struct drm_device *dev,
11473 struct intel_set_config *config)
11474 {
11475 struct intel_crtc *crtc;
11476 struct intel_encoder *encoder;
11477 struct intel_connector *connector;
11478 int count;
11479
11480 count = 0;
11481 for_each_intel_crtc(dev, crtc) {
11482 crtc->new_enabled = config->save_crtc_enabled[count++];
11483
11484 if (crtc->new_enabled)
11485 crtc->new_config = crtc->config;
11486 else
11487 crtc->new_config = NULL;
11488 }
11489
11490 count = 0;
11491 for_each_intel_encoder(dev, encoder) {
11492 encoder->new_crtc =
11493 to_intel_crtc(config->save_encoder_crtcs[count++]);
11494 }
11495
11496 count = 0;
11497 for_each_intel_connector(dev, connector) {
11498 connector->new_encoder =
11499 to_intel_encoder(config->save_connector_encoders[count++]);
11500 }
11501 }
11502
11503 static bool
11504 is_crtc_connector_off(struct drm_mode_set *set)
11505 {
11506 int i;
11507
11508 if (set->num_connectors == 0)
11509 return false;
11510
11511 if (WARN_ON(set->connectors == NULL))
11512 return false;
11513
11514 for (i = 0; i < set->num_connectors; i++)
11515 if (set->connectors[i]->encoder &&
11516 set->connectors[i]->encoder->crtc == set->crtc &&
11517 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11518 return true;
11519
11520 return false;
11521 }
11522
11523 static void
11524 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11525 struct intel_set_config *config)
11526 {
11527
11528 /* We should be able to check here if the fb has the same properties
11529 * and then just flip_or_move it */
11530 if (is_crtc_connector_off(set)) {
11531 config->mode_changed = true;
11532 } else if (set->crtc->primary->fb != set->fb) {
11533 /*
11534 * If we have no fb, we can only flip as long as the crtc is
11535 * active, otherwise we need a full mode set. The crtc may
11536 * be active if we've only disabled the primary plane, or
11537 * in fastboot situations.
11538 */
11539 if (set->crtc->primary->fb == NULL) {
11540 struct intel_crtc *intel_crtc =
11541 to_intel_crtc(set->crtc);
11542
11543 if (intel_crtc->active) {
11544 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11545 config->fb_changed = true;
11546 } else {
11547 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11548 config->mode_changed = true;
11549 }
11550 } else if (set->fb == NULL) {
11551 config->mode_changed = true;
11552 } else if (set->fb->pixel_format !=
11553 set->crtc->primary->fb->pixel_format) {
11554 config->mode_changed = true;
11555 } else {
11556 config->fb_changed = true;
11557 }
11558 }
11559
11560 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11561 config->fb_changed = true;
11562
11563 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11564 DRM_DEBUG_KMS("modes are different, full mode set\n");
11565 drm_mode_debug_printmodeline(&set->crtc->mode);
11566 drm_mode_debug_printmodeline(set->mode);
11567 config->mode_changed = true;
11568 }
11569
11570 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11571 set->crtc->base.id, config->mode_changed, config->fb_changed);
11572 }
11573
11574 static int
11575 intel_modeset_stage_output_state(struct drm_device *dev,
11576 struct drm_mode_set *set,
11577 struct intel_set_config *config)
11578 {
11579 struct intel_connector *connector;
11580 struct intel_encoder *encoder;
11581 struct intel_crtc *crtc;
11582 int ro;
11583
11584 /* The upper layers ensure that we either disable a crtc or have a list
11585 * of connectors. For paranoia, double-check this. */
11586 WARN_ON(!set->fb && (set->num_connectors != 0));
11587 WARN_ON(set->fb && (set->num_connectors == 0));
11588
11589 for_each_intel_connector(dev, connector) {
11590 /* Otherwise traverse passed in connector list and get encoders
11591 * for them. */
11592 for (ro = 0; ro < set->num_connectors; ro++) {
11593 if (set->connectors[ro] == &connector->base) {
11594 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11595 break;
11596 }
11597 }
11598
11599 /* If we disable the crtc, disable all its connectors. Also, if
11600 * the connector is on the changing crtc but not on the new
11601 * connector list, disable it. */
11602 if ((!set->fb || ro == set->num_connectors) &&
11603 connector->base.encoder &&
11604 connector->base.encoder->crtc == set->crtc) {
11605 connector->new_encoder = NULL;
11606
11607 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11608 connector->base.base.id,
11609 connector->base.name);
11610 }
11611
11612
11613 if (&connector->new_encoder->base != connector->base.encoder) {
11614 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11615 connector->base.base.id,
11616 connector->base.name);
11617 config->mode_changed = true;
11618 }
11619 }
11620 /* connector->new_encoder is now updated for all connectors. */
11621
11622 /* Update crtc of enabled connectors. */
11623 for_each_intel_connector(dev, connector) {
11624 struct drm_crtc *new_crtc;
11625
11626 if (!connector->new_encoder)
11627 continue;
11628
11629 new_crtc = connector->new_encoder->base.crtc;
11630
11631 for (ro = 0; ro < set->num_connectors; ro++) {
11632 if (set->connectors[ro] == &connector->base)
11633 new_crtc = set->crtc;
11634 }
11635
11636 /* Make sure the new CRTC will work with the encoder */
11637 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11638 new_crtc)) {
11639 return -EINVAL;
11640 }
11641 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11642
11643 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11644 connector->base.base.id,
11645 connector->base.name,
11646 new_crtc->base.id);
11647 }
11648
11649 /* Check for any encoders that needs to be disabled. */
11650 for_each_intel_encoder(dev, encoder) {
11651 int num_connectors = 0;
11652 for_each_intel_connector(dev, connector) {
11653 if (connector->new_encoder == encoder) {
11654 WARN_ON(!connector->new_encoder->new_crtc);
11655 num_connectors++;
11656 }
11657 }
11658
11659 if (num_connectors == 0)
11660 encoder->new_crtc = NULL;
11661 else if (num_connectors > 1)
11662 return -EINVAL;
11663
11664 /* Only now check for crtc changes so we don't miss encoders
11665 * that will be disabled. */
11666 if (&encoder->new_crtc->base != encoder->base.crtc) {
11667 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11668 encoder->base.base.id,
11669 encoder->base.name);
11670 config->mode_changed = true;
11671 }
11672 }
11673 /* Now we've also updated encoder->new_crtc for all encoders. */
11674 for_each_intel_connector(dev, connector) {
11675 if (connector->new_encoder)
11676 if (connector->new_encoder != connector->encoder)
11677 connector->encoder = connector->new_encoder;
11678 }
11679 for_each_intel_crtc(dev, crtc) {
11680 crtc->new_enabled = false;
11681
11682 for_each_intel_encoder(dev, encoder) {
11683 if (encoder->new_crtc == crtc) {
11684 crtc->new_enabled = true;
11685 break;
11686 }
11687 }
11688
11689 if (crtc->new_enabled != crtc->base.state->enable) {
11690 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11691 crtc->base.base.id,
11692 crtc->new_enabled ? "en" : "dis");
11693 config->mode_changed = true;
11694 }
11695
11696 if (crtc->new_enabled)
11697 crtc->new_config = crtc->config;
11698 else
11699 crtc->new_config = NULL;
11700 }
11701
11702 return 0;
11703 }
11704
11705 static void disable_crtc_nofb(struct intel_crtc *crtc)
11706 {
11707 struct drm_device *dev = crtc->base.dev;
11708 struct intel_encoder *encoder;
11709 struct intel_connector *connector;
11710
11711 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11712 pipe_name(crtc->pipe));
11713
11714 for_each_intel_connector(dev, connector) {
11715 if (connector->new_encoder &&
11716 connector->new_encoder->new_crtc == crtc)
11717 connector->new_encoder = NULL;
11718 }
11719
11720 for_each_intel_encoder(dev, encoder) {
11721 if (encoder->new_crtc == crtc)
11722 encoder->new_crtc = NULL;
11723 }
11724
11725 crtc->new_enabled = false;
11726 crtc->new_config = NULL;
11727 }
11728
11729 static int intel_crtc_set_config(struct drm_mode_set *set)
11730 {
11731 struct drm_device *dev;
11732 struct drm_mode_set save_set;
11733 struct intel_set_config *config;
11734 struct intel_crtc_state *pipe_config;
11735 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11736 int ret;
11737
11738 BUG_ON(!set);
11739 BUG_ON(!set->crtc);
11740 BUG_ON(!set->crtc->helper_private);
11741
11742 /* Enforce sane interface api - has been abused by the fb helper. */
11743 BUG_ON(!set->mode && set->fb);
11744 BUG_ON(set->fb && set->num_connectors == 0);
11745
11746 if (set->fb) {
11747 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11748 set->crtc->base.id, set->fb->base.id,
11749 (int)set->num_connectors, set->x, set->y);
11750 } else {
11751 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11752 }
11753
11754 dev = set->crtc->dev;
11755
11756 ret = -ENOMEM;
11757 config = kzalloc(sizeof(*config), GFP_KERNEL);
11758 if (!config)
11759 goto out_config;
11760
11761 ret = intel_set_config_save_state(dev, config);
11762 if (ret)
11763 goto out_config;
11764
11765 save_set.crtc = set->crtc;
11766 save_set.mode = &set->crtc->mode;
11767 save_set.x = set->crtc->x;
11768 save_set.y = set->crtc->y;
11769 save_set.fb = set->crtc->primary->fb;
11770
11771 /* Compute whether we need a full modeset, only an fb base update or no
11772 * change at all. In the future we might also check whether only the
11773 * mode changed, e.g. for LVDS where we only change the panel fitter in
11774 * such cases. */
11775 intel_set_config_compute_mode_changes(set, config);
11776
11777 ret = intel_modeset_stage_output_state(dev, set, config);
11778 if (ret)
11779 goto fail;
11780
11781 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11782 set->fb,
11783 &modeset_pipes,
11784 &prepare_pipes,
11785 &disable_pipes);
11786 if (IS_ERR(pipe_config)) {
11787 ret = PTR_ERR(pipe_config);
11788 goto fail;
11789 } else if (pipe_config) {
11790 if (pipe_config->has_audio !=
11791 to_intel_crtc(set->crtc)->config->has_audio)
11792 config->mode_changed = true;
11793
11794 /*
11795 * Note we have an issue here with infoframes: current code
11796 * only updates them on the full mode set path per hw
11797 * requirements. So here we should be checking for any
11798 * required changes and forcing a mode set.
11799 */
11800 }
11801
11802 /* set_mode will free it in the mode_changed case */
11803 if (!config->mode_changed)
11804 kfree(pipe_config);
11805
11806 intel_update_pipe_size(to_intel_crtc(set->crtc));
11807
11808 if (config->mode_changed) {
11809 ret = intel_set_mode_pipes(set->crtc, set->mode,
11810 set->x, set->y, set->fb, pipe_config,
11811 modeset_pipes, prepare_pipes,
11812 disable_pipes);
11813 } else if (config->fb_changed) {
11814 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11815 struct drm_plane *primary = set->crtc->primary;
11816 int vdisplay, hdisplay;
11817
11818 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11819 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11820 0, 0, hdisplay, vdisplay,
11821 set->x << 16, set->y << 16,
11822 hdisplay << 16, vdisplay << 16);
11823
11824 /*
11825 * We need to make sure the primary plane is re-enabled if it
11826 * has previously been turned off.
11827 */
11828 if (!intel_crtc->primary_enabled && ret == 0) {
11829 WARN_ON(!intel_crtc->active);
11830 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11831 }
11832
11833 /*
11834 * In the fastboot case this may be our only check of the
11835 * state after boot. It would be better to only do it on
11836 * the first update, but we don't have a nice way of doing that
11837 * (and really, set_config isn't used much for high freq page
11838 * flipping, so increasing its cost here shouldn't be a big
11839 * deal).
11840 */
11841 if (i915.fastboot && ret == 0)
11842 intel_modeset_check_state(set->crtc->dev);
11843 }
11844
11845 if (ret) {
11846 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11847 set->crtc->base.id, ret);
11848 fail:
11849 intel_set_config_restore_state(dev, config);
11850
11851 /*
11852 * HACK: if the pipe was on, but we didn't have a framebuffer,
11853 * force the pipe off to avoid oopsing in the modeset code
11854 * due to fb==NULL. This should only happen during boot since
11855 * we don't yet reconstruct the FB from the hardware state.
11856 */
11857 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11858 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11859
11860 /* Try to restore the config */
11861 if (config->mode_changed &&
11862 intel_set_mode(save_set.crtc, save_set.mode,
11863 save_set.x, save_set.y, save_set.fb))
11864 DRM_ERROR("failed to restore config after modeset failure\n");
11865 }
11866
11867 out_config:
11868 intel_set_config_free(config);
11869 return ret;
11870 }
11871
11872 static const struct drm_crtc_funcs intel_crtc_funcs = {
11873 .gamma_set = intel_crtc_gamma_set,
11874 .set_config = intel_crtc_set_config,
11875 .destroy = intel_crtc_destroy,
11876 .page_flip = intel_crtc_page_flip,
11877 .atomic_duplicate_state = intel_crtc_duplicate_state,
11878 .atomic_destroy_state = intel_crtc_destroy_state,
11879 };
11880
11881 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11882 struct intel_shared_dpll *pll,
11883 struct intel_dpll_hw_state *hw_state)
11884 {
11885 uint32_t val;
11886
11887 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11888 return false;
11889
11890 val = I915_READ(PCH_DPLL(pll->id));
11891 hw_state->dpll = val;
11892 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11893 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11894
11895 return val & DPLL_VCO_ENABLE;
11896 }
11897
11898 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11899 struct intel_shared_dpll *pll)
11900 {
11901 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11902 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11903 }
11904
11905 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11906 struct intel_shared_dpll *pll)
11907 {
11908 /* PCH refclock must be enabled first */
11909 ibx_assert_pch_refclk_enabled(dev_priv);
11910
11911 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11912
11913 /* Wait for the clocks to stabilize. */
11914 POSTING_READ(PCH_DPLL(pll->id));
11915 udelay(150);
11916
11917 /* The pixel multiplier can only be updated once the
11918 * DPLL is enabled and the clocks are stable.
11919 *
11920 * So write it again.
11921 */
11922 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11923 POSTING_READ(PCH_DPLL(pll->id));
11924 udelay(200);
11925 }
11926
11927 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11928 struct intel_shared_dpll *pll)
11929 {
11930 struct drm_device *dev = dev_priv->dev;
11931 struct intel_crtc *crtc;
11932
11933 /* Make sure no transcoder isn't still depending on us. */
11934 for_each_intel_crtc(dev, crtc) {
11935 if (intel_crtc_to_shared_dpll(crtc) == pll)
11936 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11937 }
11938
11939 I915_WRITE(PCH_DPLL(pll->id), 0);
11940 POSTING_READ(PCH_DPLL(pll->id));
11941 udelay(200);
11942 }
11943
11944 static char *ibx_pch_dpll_names[] = {
11945 "PCH DPLL A",
11946 "PCH DPLL B",
11947 };
11948
11949 static void ibx_pch_dpll_init(struct drm_device *dev)
11950 {
11951 struct drm_i915_private *dev_priv = dev->dev_private;
11952 int i;
11953
11954 dev_priv->num_shared_dpll = 2;
11955
11956 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11957 dev_priv->shared_dplls[i].id = i;
11958 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11959 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11960 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11961 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11962 dev_priv->shared_dplls[i].get_hw_state =
11963 ibx_pch_dpll_get_hw_state;
11964 }
11965 }
11966
11967 static void intel_shared_dpll_init(struct drm_device *dev)
11968 {
11969 struct drm_i915_private *dev_priv = dev->dev_private;
11970
11971 if (HAS_DDI(dev))
11972 intel_ddi_pll_init(dev);
11973 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11974 ibx_pch_dpll_init(dev);
11975 else
11976 dev_priv->num_shared_dpll = 0;
11977
11978 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11979 }
11980
11981 /**
11982 * intel_prepare_plane_fb - Prepare fb for usage on plane
11983 * @plane: drm plane to prepare for
11984 * @fb: framebuffer to prepare for presentation
11985 *
11986 * Prepares a framebuffer for usage on a display plane. Generally this
11987 * involves pinning the underlying object and updating the frontbuffer tracking
11988 * bits. Some older platforms need special physical address handling for
11989 * cursor planes.
11990 *
11991 * Returns 0 on success, negative error code on failure.
11992 */
11993 int
11994 intel_prepare_plane_fb(struct drm_plane *plane,
11995 struct drm_framebuffer *fb,
11996 const struct drm_plane_state *new_state)
11997 {
11998 struct drm_device *dev = plane->dev;
11999 struct intel_plane *intel_plane = to_intel_plane(plane);
12000 enum pipe pipe = intel_plane->pipe;
12001 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12002 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12003 unsigned frontbuffer_bits = 0;
12004 int ret = 0;
12005
12006 if (!obj)
12007 return 0;
12008
12009 switch (plane->type) {
12010 case DRM_PLANE_TYPE_PRIMARY:
12011 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12012 break;
12013 case DRM_PLANE_TYPE_CURSOR:
12014 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12015 break;
12016 case DRM_PLANE_TYPE_OVERLAY:
12017 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12018 break;
12019 }
12020
12021 mutex_lock(&dev->struct_mutex);
12022
12023 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12024 INTEL_INFO(dev)->cursor_needs_physical) {
12025 int align = IS_I830(dev) ? 16 * 1024 : 256;
12026 ret = i915_gem_object_attach_phys(obj, align);
12027 if (ret)
12028 DRM_DEBUG_KMS("failed to attach phys object\n");
12029 } else {
12030 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12031 }
12032
12033 if (ret == 0)
12034 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12035
12036 mutex_unlock(&dev->struct_mutex);
12037
12038 return ret;
12039 }
12040
12041 /**
12042 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12043 * @plane: drm plane to clean up for
12044 * @fb: old framebuffer that was on plane
12045 *
12046 * Cleans up a framebuffer that has just been removed from a plane.
12047 */
12048 void
12049 intel_cleanup_plane_fb(struct drm_plane *plane,
12050 struct drm_framebuffer *fb,
12051 const struct drm_plane_state *old_state)
12052 {
12053 struct drm_device *dev = plane->dev;
12054 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12055
12056 if (WARN_ON(!obj))
12057 return;
12058
12059 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12060 !INTEL_INFO(dev)->cursor_needs_physical) {
12061 mutex_lock(&dev->struct_mutex);
12062 intel_unpin_fb_obj(fb, old_state);
12063 mutex_unlock(&dev->struct_mutex);
12064 }
12065 }
12066
12067 static int
12068 intel_check_primary_plane(struct drm_plane *plane,
12069 struct intel_plane_state *state)
12070 {
12071 struct drm_device *dev = plane->dev;
12072 struct drm_i915_private *dev_priv = dev->dev_private;
12073 struct drm_crtc *crtc = state->base.crtc;
12074 struct intel_crtc *intel_crtc;
12075 struct drm_framebuffer *fb = state->base.fb;
12076 struct drm_rect *dest = &state->dst;
12077 struct drm_rect *src = &state->src;
12078 const struct drm_rect *clip = &state->clip;
12079 int ret;
12080
12081 crtc = crtc ? crtc : plane->crtc;
12082 intel_crtc = to_intel_crtc(crtc);
12083
12084 ret = drm_plane_helper_check_update(plane, crtc, fb,
12085 src, dest, clip,
12086 DRM_PLANE_HELPER_NO_SCALING,
12087 DRM_PLANE_HELPER_NO_SCALING,
12088 false, true, &state->visible);
12089 if (ret)
12090 return ret;
12091
12092 if (intel_crtc->active) {
12093 intel_crtc->atomic.wait_for_flips = true;
12094
12095 /*
12096 * FBC does not work on some platforms for rotated
12097 * planes, so disable it when rotation is not 0 and
12098 * update it when rotation is set back to 0.
12099 *
12100 * FIXME: This is redundant with the fbc update done in
12101 * the primary plane enable function except that that
12102 * one is done too late. We eventually need to unify
12103 * this.
12104 */
12105 if (intel_crtc->primary_enabled &&
12106 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12107 dev_priv->fbc.crtc == intel_crtc &&
12108 state->base.rotation != BIT(DRM_ROTATE_0)) {
12109 intel_crtc->atomic.disable_fbc = true;
12110 }
12111
12112 if (state->visible) {
12113 /*
12114 * BDW signals flip done immediately if the plane
12115 * is disabled, even if the plane enable is already
12116 * armed to occur at the next vblank :(
12117 */
12118 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12119 intel_crtc->atomic.wait_vblank = true;
12120 }
12121
12122 intel_crtc->atomic.fb_bits |=
12123 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12124
12125 intel_crtc->atomic.update_fbc = true;
12126
12127 /* Update watermarks on tiling changes. */
12128 if (!plane->state->fb || !state->base.fb ||
12129 plane->state->fb->modifier[0] !=
12130 state->base.fb->modifier[0])
12131 intel_crtc->atomic.update_wm = true;
12132 }
12133
12134 return 0;
12135 }
12136
12137 static void
12138 intel_commit_primary_plane(struct drm_plane *plane,
12139 struct intel_plane_state *state)
12140 {
12141 struct drm_crtc *crtc = state->base.crtc;
12142 struct drm_framebuffer *fb = state->base.fb;
12143 struct drm_device *dev = plane->dev;
12144 struct drm_i915_private *dev_priv = dev->dev_private;
12145 struct intel_crtc *intel_crtc;
12146 struct drm_rect *src = &state->src;
12147
12148 crtc = crtc ? crtc : plane->crtc;
12149 intel_crtc = to_intel_crtc(crtc);
12150
12151 plane->fb = fb;
12152 crtc->x = src->x1 >> 16;
12153 crtc->y = src->y1 >> 16;
12154
12155 if (intel_crtc->active) {
12156 if (state->visible) {
12157 /* FIXME: kill this fastboot hack */
12158 intel_update_pipe_size(intel_crtc);
12159
12160 intel_crtc->primary_enabled = true;
12161
12162 dev_priv->display.update_primary_plane(crtc, plane->fb,
12163 crtc->x, crtc->y);
12164 } else {
12165 /*
12166 * If clipping results in a non-visible primary plane,
12167 * we'll disable the primary plane. Note that this is
12168 * a bit different than what happens if userspace
12169 * explicitly disables the plane by passing fb=0
12170 * because plane->fb still gets set and pinned.
12171 */
12172 intel_disable_primary_hw_plane(plane, crtc);
12173 }
12174 }
12175 }
12176
12177 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12178 {
12179 struct drm_device *dev = crtc->dev;
12180 struct drm_i915_private *dev_priv = dev->dev_private;
12181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12182 struct intel_plane *intel_plane;
12183 struct drm_plane *p;
12184 unsigned fb_bits = 0;
12185
12186 /* Track fb's for any planes being disabled */
12187 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12188 intel_plane = to_intel_plane(p);
12189
12190 if (intel_crtc->atomic.disabled_planes &
12191 (1 << drm_plane_index(p))) {
12192 switch (p->type) {
12193 case DRM_PLANE_TYPE_PRIMARY:
12194 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12195 break;
12196 case DRM_PLANE_TYPE_CURSOR:
12197 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12198 break;
12199 case DRM_PLANE_TYPE_OVERLAY:
12200 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12201 break;
12202 }
12203
12204 mutex_lock(&dev->struct_mutex);
12205 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12206 mutex_unlock(&dev->struct_mutex);
12207 }
12208 }
12209
12210 if (intel_crtc->atomic.wait_for_flips)
12211 intel_crtc_wait_for_pending_flips(crtc);
12212
12213 if (intel_crtc->atomic.disable_fbc)
12214 intel_fbc_disable(dev);
12215
12216 if (intel_crtc->atomic.pre_disable_primary)
12217 intel_pre_disable_primary(crtc);
12218
12219 if (intel_crtc->atomic.update_wm)
12220 intel_update_watermarks(crtc);
12221
12222 intel_runtime_pm_get(dev_priv);
12223
12224 /* Perform vblank evasion around commit operation */
12225 if (intel_crtc->active)
12226 intel_crtc->atomic.evade =
12227 intel_pipe_update_start(intel_crtc,
12228 &intel_crtc->atomic.start_vbl_count);
12229 }
12230
12231 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12232 {
12233 struct drm_device *dev = crtc->dev;
12234 struct drm_i915_private *dev_priv = dev->dev_private;
12235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12236 struct drm_plane *p;
12237
12238 if (intel_crtc->atomic.evade)
12239 intel_pipe_update_end(intel_crtc,
12240 intel_crtc->atomic.start_vbl_count);
12241
12242 intel_runtime_pm_put(dev_priv);
12243
12244 if (intel_crtc->atomic.wait_vblank)
12245 intel_wait_for_vblank(dev, intel_crtc->pipe);
12246
12247 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12248
12249 if (intel_crtc->atomic.update_fbc) {
12250 mutex_lock(&dev->struct_mutex);
12251 intel_fbc_update(dev);
12252 mutex_unlock(&dev->struct_mutex);
12253 }
12254
12255 if (intel_crtc->atomic.post_enable_primary)
12256 intel_post_enable_primary(crtc);
12257
12258 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12259 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12260 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12261 false, false);
12262
12263 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12264 }
12265
12266 /**
12267 * intel_plane_destroy - destroy a plane
12268 * @plane: plane to destroy
12269 *
12270 * Common destruction function for all types of planes (primary, cursor,
12271 * sprite).
12272 */
12273 void intel_plane_destroy(struct drm_plane *plane)
12274 {
12275 struct intel_plane *intel_plane = to_intel_plane(plane);
12276 drm_plane_cleanup(plane);
12277 kfree(intel_plane);
12278 }
12279
12280 const struct drm_plane_funcs intel_plane_funcs = {
12281 .update_plane = drm_plane_helper_update,
12282 .disable_plane = drm_plane_helper_disable,
12283 .destroy = intel_plane_destroy,
12284 .set_property = drm_atomic_helper_plane_set_property,
12285 .atomic_get_property = intel_plane_atomic_get_property,
12286 .atomic_set_property = intel_plane_atomic_set_property,
12287 .atomic_duplicate_state = intel_plane_duplicate_state,
12288 .atomic_destroy_state = intel_plane_destroy_state,
12289
12290 };
12291
12292 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12293 int pipe)
12294 {
12295 struct intel_plane *primary;
12296 struct intel_plane_state *state;
12297 const uint32_t *intel_primary_formats;
12298 int num_formats;
12299
12300 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12301 if (primary == NULL)
12302 return NULL;
12303
12304 state = intel_create_plane_state(&primary->base);
12305 if (!state) {
12306 kfree(primary);
12307 return NULL;
12308 }
12309 primary->base.state = &state->base;
12310
12311 primary->can_scale = false;
12312 primary->max_downscale = 1;
12313 primary->pipe = pipe;
12314 primary->plane = pipe;
12315 primary->check_plane = intel_check_primary_plane;
12316 primary->commit_plane = intel_commit_primary_plane;
12317 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12318 primary->plane = !pipe;
12319
12320 if (INTEL_INFO(dev)->gen <= 3) {
12321 intel_primary_formats = intel_primary_formats_gen2;
12322 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12323 } else {
12324 intel_primary_formats = intel_primary_formats_gen4;
12325 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12326 }
12327
12328 drm_universal_plane_init(dev, &primary->base, 0,
12329 &intel_plane_funcs,
12330 intel_primary_formats, num_formats,
12331 DRM_PLANE_TYPE_PRIMARY);
12332
12333 if (INTEL_INFO(dev)->gen >= 4) {
12334 if (!dev->mode_config.rotation_property)
12335 dev->mode_config.rotation_property =
12336 drm_mode_create_rotation_property(dev,
12337 BIT(DRM_ROTATE_0) |
12338 BIT(DRM_ROTATE_180));
12339 if (dev->mode_config.rotation_property)
12340 drm_object_attach_property(&primary->base.base,
12341 dev->mode_config.rotation_property,
12342 state->base.rotation);
12343 }
12344
12345 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12346
12347 return &primary->base;
12348 }
12349
12350 static int
12351 intel_check_cursor_plane(struct drm_plane *plane,
12352 struct intel_plane_state *state)
12353 {
12354 struct drm_crtc *crtc = state->base.crtc;
12355 struct drm_device *dev = plane->dev;
12356 struct drm_framebuffer *fb = state->base.fb;
12357 struct drm_rect *dest = &state->dst;
12358 struct drm_rect *src = &state->src;
12359 const struct drm_rect *clip = &state->clip;
12360 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12361 struct intel_crtc *intel_crtc;
12362 unsigned stride;
12363 int ret;
12364
12365 crtc = crtc ? crtc : plane->crtc;
12366 intel_crtc = to_intel_crtc(crtc);
12367
12368 ret = drm_plane_helper_check_update(plane, crtc, fb,
12369 src, dest, clip,
12370 DRM_PLANE_HELPER_NO_SCALING,
12371 DRM_PLANE_HELPER_NO_SCALING,
12372 true, true, &state->visible);
12373 if (ret)
12374 return ret;
12375
12376
12377 /* if we want to turn off the cursor ignore width and height */
12378 if (!obj)
12379 goto finish;
12380
12381 /* Check for which cursor types we support */
12382 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12383 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12384 state->base.crtc_w, state->base.crtc_h);
12385 return -EINVAL;
12386 }
12387
12388 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12389 if (obj->base.size < stride * state->base.crtc_h) {
12390 DRM_DEBUG_KMS("buffer is too small\n");
12391 return -ENOMEM;
12392 }
12393
12394 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12395 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12396 ret = -EINVAL;
12397 }
12398
12399 finish:
12400 if (intel_crtc->active) {
12401 if (plane->state->crtc_w != state->base.crtc_w)
12402 intel_crtc->atomic.update_wm = true;
12403
12404 intel_crtc->atomic.fb_bits |=
12405 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12406 }
12407
12408 return ret;
12409 }
12410
12411 static void
12412 intel_commit_cursor_plane(struct drm_plane *plane,
12413 struct intel_plane_state *state)
12414 {
12415 struct drm_crtc *crtc = state->base.crtc;
12416 struct drm_device *dev = plane->dev;
12417 struct intel_crtc *intel_crtc;
12418 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12419 uint32_t addr;
12420
12421 crtc = crtc ? crtc : plane->crtc;
12422 intel_crtc = to_intel_crtc(crtc);
12423
12424 plane->fb = state->base.fb;
12425 crtc->cursor_x = state->base.crtc_x;
12426 crtc->cursor_y = state->base.crtc_y;
12427
12428 if (intel_crtc->cursor_bo == obj)
12429 goto update;
12430
12431 if (!obj)
12432 addr = 0;
12433 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12434 addr = i915_gem_obj_ggtt_offset(obj);
12435 else
12436 addr = obj->phys_handle->busaddr;
12437
12438 intel_crtc->cursor_addr = addr;
12439 intel_crtc->cursor_bo = obj;
12440 update:
12441
12442 if (intel_crtc->active)
12443 intel_crtc_update_cursor(crtc, state->visible);
12444 }
12445
12446 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12447 int pipe)
12448 {
12449 struct intel_plane *cursor;
12450 struct intel_plane_state *state;
12451
12452 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12453 if (cursor == NULL)
12454 return NULL;
12455
12456 state = intel_create_plane_state(&cursor->base);
12457 if (!state) {
12458 kfree(cursor);
12459 return NULL;
12460 }
12461 cursor->base.state = &state->base;
12462
12463 cursor->can_scale = false;
12464 cursor->max_downscale = 1;
12465 cursor->pipe = pipe;
12466 cursor->plane = pipe;
12467 cursor->check_plane = intel_check_cursor_plane;
12468 cursor->commit_plane = intel_commit_cursor_plane;
12469
12470 drm_universal_plane_init(dev, &cursor->base, 0,
12471 &intel_plane_funcs,
12472 intel_cursor_formats,
12473 ARRAY_SIZE(intel_cursor_formats),
12474 DRM_PLANE_TYPE_CURSOR);
12475
12476 if (INTEL_INFO(dev)->gen >= 4) {
12477 if (!dev->mode_config.rotation_property)
12478 dev->mode_config.rotation_property =
12479 drm_mode_create_rotation_property(dev,
12480 BIT(DRM_ROTATE_0) |
12481 BIT(DRM_ROTATE_180));
12482 if (dev->mode_config.rotation_property)
12483 drm_object_attach_property(&cursor->base.base,
12484 dev->mode_config.rotation_property,
12485 state->base.rotation);
12486 }
12487
12488 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12489
12490 return &cursor->base;
12491 }
12492
12493 static void intel_crtc_init(struct drm_device *dev, int pipe)
12494 {
12495 struct drm_i915_private *dev_priv = dev->dev_private;
12496 struct intel_crtc *intel_crtc;
12497 struct intel_crtc_state *crtc_state = NULL;
12498 struct drm_plane *primary = NULL;
12499 struct drm_plane *cursor = NULL;
12500 int i, ret;
12501
12502 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12503 if (intel_crtc == NULL)
12504 return;
12505
12506 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12507 if (!crtc_state)
12508 goto fail;
12509 intel_crtc_set_state(intel_crtc, crtc_state);
12510 crtc_state->base.crtc = &intel_crtc->base;
12511
12512 primary = intel_primary_plane_create(dev, pipe);
12513 if (!primary)
12514 goto fail;
12515
12516 cursor = intel_cursor_plane_create(dev, pipe);
12517 if (!cursor)
12518 goto fail;
12519
12520 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12521 cursor, &intel_crtc_funcs);
12522 if (ret)
12523 goto fail;
12524
12525 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12526 for (i = 0; i < 256; i++) {
12527 intel_crtc->lut_r[i] = i;
12528 intel_crtc->lut_g[i] = i;
12529 intel_crtc->lut_b[i] = i;
12530 }
12531
12532 /*
12533 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12534 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12535 */
12536 intel_crtc->pipe = pipe;
12537 intel_crtc->plane = pipe;
12538 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12539 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12540 intel_crtc->plane = !pipe;
12541 }
12542
12543 intel_crtc->cursor_base = ~0;
12544 intel_crtc->cursor_cntl = ~0;
12545 intel_crtc->cursor_size = ~0;
12546
12547 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12548 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12549 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12550 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12551
12552 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12553
12554 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12555
12556 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12557 return;
12558
12559 fail:
12560 if (primary)
12561 drm_plane_cleanup(primary);
12562 if (cursor)
12563 drm_plane_cleanup(cursor);
12564 kfree(crtc_state);
12565 kfree(intel_crtc);
12566 }
12567
12568 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12569 {
12570 struct drm_encoder *encoder = connector->base.encoder;
12571 struct drm_device *dev = connector->base.dev;
12572
12573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12574
12575 if (!encoder || WARN_ON(!encoder->crtc))
12576 return INVALID_PIPE;
12577
12578 return to_intel_crtc(encoder->crtc)->pipe;
12579 }
12580
12581 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12582 struct drm_file *file)
12583 {
12584 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12585 struct drm_crtc *drmmode_crtc;
12586 struct intel_crtc *crtc;
12587
12588 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12589
12590 if (!drmmode_crtc) {
12591 DRM_ERROR("no such CRTC id\n");
12592 return -ENOENT;
12593 }
12594
12595 crtc = to_intel_crtc(drmmode_crtc);
12596 pipe_from_crtc_id->pipe = crtc->pipe;
12597
12598 return 0;
12599 }
12600
12601 static int intel_encoder_clones(struct intel_encoder *encoder)
12602 {
12603 struct drm_device *dev = encoder->base.dev;
12604 struct intel_encoder *source_encoder;
12605 int index_mask = 0;
12606 int entry = 0;
12607
12608 for_each_intel_encoder(dev, source_encoder) {
12609 if (encoders_cloneable(encoder, source_encoder))
12610 index_mask |= (1 << entry);
12611
12612 entry++;
12613 }
12614
12615 return index_mask;
12616 }
12617
12618 static bool has_edp_a(struct drm_device *dev)
12619 {
12620 struct drm_i915_private *dev_priv = dev->dev_private;
12621
12622 if (!IS_MOBILE(dev))
12623 return false;
12624
12625 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12626 return false;
12627
12628 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12629 return false;
12630
12631 return true;
12632 }
12633
12634 static bool intel_crt_present(struct drm_device *dev)
12635 {
12636 struct drm_i915_private *dev_priv = dev->dev_private;
12637
12638 if (INTEL_INFO(dev)->gen >= 9)
12639 return false;
12640
12641 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12642 return false;
12643
12644 if (IS_CHERRYVIEW(dev))
12645 return false;
12646
12647 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12648 return false;
12649
12650 return true;
12651 }
12652
12653 static void intel_setup_outputs(struct drm_device *dev)
12654 {
12655 struct drm_i915_private *dev_priv = dev->dev_private;
12656 struct intel_encoder *encoder;
12657 struct drm_connector *connector;
12658 bool dpd_is_edp = false;
12659
12660 intel_lvds_init(dev);
12661
12662 if (intel_crt_present(dev))
12663 intel_crt_init(dev);
12664
12665 if (HAS_DDI(dev)) {
12666 int found;
12667
12668 /*
12669 * Haswell uses DDI functions to detect digital outputs.
12670 * On SKL pre-D0 the strap isn't connected, so we assume
12671 * it's there.
12672 */
12673 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12674 /* WaIgnoreDDIAStrap: skl */
12675 if (found ||
12676 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12677 intel_ddi_init(dev, PORT_A);
12678
12679 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12680 * register */
12681 found = I915_READ(SFUSE_STRAP);
12682
12683 if (found & SFUSE_STRAP_DDIB_DETECTED)
12684 intel_ddi_init(dev, PORT_B);
12685 if (found & SFUSE_STRAP_DDIC_DETECTED)
12686 intel_ddi_init(dev, PORT_C);
12687 if (found & SFUSE_STRAP_DDID_DETECTED)
12688 intel_ddi_init(dev, PORT_D);
12689 } else if (HAS_PCH_SPLIT(dev)) {
12690 int found;
12691 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12692
12693 if (has_edp_a(dev))
12694 intel_dp_init(dev, DP_A, PORT_A);
12695
12696 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12697 /* PCH SDVOB multiplex with HDMIB */
12698 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12699 if (!found)
12700 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12701 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12702 intel_dp_init(dev, PCH_DP_B, PORT_B);
12703 }
12704
12705 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12706 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12707
12708 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12709 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12710
12711 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12712 intel_dp_init(dev, PCH_DP_C, PORT_C);
12713
12714 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12715 intel_dp_init(dev, PCH_DP_D, PORT_D);
12716 } else if (IS_VALLEYVIEW(dev)) {
12717 /*
12718 * The DP_DETECTED bit is the latched state of the DDC
12719 * SDA pin at boot. However since eDP doesn't require DDC
12720 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12721 * eDP ports may have been muxed to an alternate function.
12722 * Thus we can't rely on the DP_DETECTED bit alone to detect
12723 * eDP ports. Consult the VBT as well as DP_DETECTED to
12724 * detect eDP ports.
12725 */
12726 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12727 !intel_dp_is_edp(dev, PORT_B))
12728 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12729 PORT_B);
12730 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12731 intel_dp_is_edp(dev, PORT_B))
12732 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12733
12734 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12735 !intel_dp_is_edp(dev, PORT_C))
12736 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12737 PORT_C);
12738 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12739 intel_dp_is_edp(dev, PORT_C))
12740 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12741
12742 if (IS_CHERRYVIEW(dev)) {
12743 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12744 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12745 PORT_D);
12746 /* eDP not supported on port D, so don't check VBT */
12747 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12748 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12749 }
12750
12751 intel_dsi_init(dev);
12752 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12753 bool found = false;
12754
12755 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12756 DRM_DEBUG_KMS("probing SDVOB\n");
12757 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12758 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12759 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12760 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12761 }
12762
12763 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12764 intel_dp_init(dev, DP_B, PORT_B);
12765 }
12766
12767 /* Before G4X SDVOC doesn't have its own detect register */
12768
12769 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12770 DRM_DEBUG_KMS("probing SDVOC\n");
12771 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12772 }
12773
12774 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12775
12776 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12777 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12778 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12779 }
12780 if (SUPPORTS_INTEGRATED_DP(dev))
12781 intel_dp_init(dev, DP_C, PORT_C);
12782 }
12783
12784 if (SUPPORTS_INTEGRATED_DP(dev) &&
12785 (I915_READ(DP_D) & DP_DETECTED))
12786 intel_dp_init(dev, DP_D, PORT_D);
12787 } else if (IS_GEN2(dev))
12788 intel_dvo_init(dev);
12789
12790 if (SUPPORTS_TV(dev))
12791 intel_tv_init(dev);
12792
12793 /*
12794 * FIXME: We don't have full atomic support yet, but we want to be
12795 * able to enable/test plane updates via the atomic interface in the
12796 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12797 * will take some atomic codepaths to lookup properties during
12798 * drmModeGetConnector() that unconditionally dereference
12799 * connector->state.
12800 *
12801 * We create a dummy connector state here for each connector to ensure
12802 * the DRM core doesn't try to dereference a NULL connector->state.
12803 * The actual connector properties will never be updated or contain
12804 * useful information, but since we're doing this specifically for
12805 * testing/debug of the plane operations (and only when a specific
12806 * kernel module option is given), that shouldn't really matter.
12807 *
12808 * Once atomic support for crtc's + connectors lands, this loop should
12809 * be removed since we'll be setting up real connector state, which
12810 * will contain Intel-specific properties.
12811 */
12812 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12813 list_for_each_entry(connector,
12814 &dev->mode_config.connector_list,
12815 head) {
12816 if (!WARN_ON(connector->state)) {
12817 connector->state =
12818 kzalloc(sizeof(*connector->state),
12819 GFP_KERNEL);
12820 }
12821 }
12822 }
12823
12824 intel_psr_init(dev);
12825
12826 for_each_intel_encoder(dev, encoder) {
12827 encoder->base.possible_crtcs = encoder->crtc_mask;
12828 encoder->base.possible_clones =
12829 intel_encoder_clones(encoder);
12830 }
12831
12832 intel_init_pch_refclk(dev);
12833
12834 drm_helper_move_panel_connectors_to_head(dev);
12835 }
12836
12837 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12838 {
12839 struct drm_device *dev = fb->dev;
12840 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12841
12842 drm_framebuffer_cleanup(fb);
12843 mutex_lock(&dev->struct_mutex);
12844 WARN_ON(!intel_fb->obj->framebuffer_references--);
12845 drm_gem_object_unreference(&intel_fb->obj->base);
12846 mutex_unlock(&dev->struct_mutex);
12847 kfree(intel_fb);
12848 }
12849
12850 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12851 struct drm_file *file,
12852 unsigned int *handle)
12853 {
12854 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12855 struct drm_i915_gem_object *obj = intel_fb->obj;
12856
12857 return drm_gem_handle_create(file, &obj->base, handle);
12858 }
12859
12860 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12861 .destroy = intel_user_framebuffer_destroy,
12862 .create_handle = intel_user_framebuffer_create_handle,
12863 };
12864
12865 static
12866 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12867 uint32_t pixel_format)
12868 {
12869 u32 gen = INTEL_INFO(dev)->gen;
12870
12871 if (gen >= 9) {
12872 /* "The stride in bytes must not exceed the of the size of 8K
12873 * pixels and 32K bytes."
12874 */
12875 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12876 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12877 return 32*1024;
12878 } else if (gen >= 4) {
12879 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12880 return 16*1024;
12881 else
12882 return 32*1024;
12883 } else if (gen >= 3) {
12884 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12885 return 8*1024;
12886 else
12887 return 16*1024;
12888 } else {
12889 /* XXX DSPC is limited to 4k tiled */
12890 return 8*1024;
12891 }
12892 }
12893
12894 static int intel_framebuffer_init(struct drm_device *dev,
12895 struct intel_framebuffer *intel_fb,
12896 struct drm_mode_fb_cmd2 *mode_cmd,
12897 struct drm_i915_gem_object *obj)
12898 {
12899 unsigned int aligned_height;
12900 int ret;
12901 u32 pitch_limit, stride_alignment;
12902
12903 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12904
12905 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12906 /* Enforce that fb modifier and tiling mode match, but only for
12907 * X-tiled. This is needed for FBC. */
12908 if (!!(obj->tiling_mode == I915_TILING_X) !=
12909 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12910 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12911 return -EINVAL;
12912 }
12913 } else {
12914 if (obj->tiling_mode == I915_TILING_X)
12915 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12916 else if (obj->tiling_mode == I915_TILING_Y) {
12917 DRM_DEBUG("No Y tiling for legacy addfb\n");
12918 return -EINVAL;
12919 }
12920 }
12921
12922 /* Passed in modifier sanity checking. */
12923 switch (mode_cmd->modifier[0]) {
12924 case I915_FORMAT_MOD_Y_TILED:
12925 case I915_FORMAT_MOD_Yf_TILED:
12926 if (INTEL_INFO(dev)->gen < 9) {
12927 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12928 mode_cmd->modifier[0]);
12929 return -EINVAL;
12930 }
12931 case DRM_FORMAT_MOD_NONE:
12932 case I915_FORMAT_MOD_X_TILED:
12933 break;
12934 default:
12935 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12936 mode_cmd->modifier[0]);
12937 return -EINVAL;
12938 }
12939
12940 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12941 mode_cmd->pixel_format);
12942 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12943 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12944 mode_cmd->pitches[0], stride_alignment);
12945 return -EINVAL;
12946 }
12947
12948 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12949 mode_cmd->pixel_format);
12950 if (mode_cmd->pitches[0] > pitch_limit) {
12951 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12952 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12953 "tiled" : "linear",
12954 mode_cmd->pitches[0], pitch_limit);
12955 return -EINVAL;
12956 }
12957
12958 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12959 mode_cmd->pitches[0] != obj->stride) {
12960 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12961 mode_cmd->pitches[0], obj->stride);
12962 return -EINVAL;
12963 }
12964
12965 /* Reject formats not supported by any plane early. */
12966 switch (mode_cmd->pixel_format) {
12967 case DRM_FORMAT_C8:
12968 case DRM_FORMAT_RGB565:
12969 case DRM_FORMAT_XRGB8888:
12970 case DRM_FORMAT_ARGB8888:
12971 break;
12972 case DRM_FORMAT_XRGB1555:
12973 case DRM_FORMAT_ARGB1555:
12974 if (INTEL_INFO(dev)->gen > 3) {
12975 DRM_DEBUG("unsupported pixel format: %s\n",
12976 drm_get_format_name(mode_cmd->pixel_format));
12977 return -EINVAL;
12978 }
12979 break;
12980 case DRM_FORMAT_XBGR8888:
12981 case DRM_FORMAT_ABGR8888:
12982 case DRM_FORMAT_XRGB2101010:
12983 case DRM_FORMAT_ARGB2101010:
12984 case DRM_FORMAT_XBGR2101010:
12985 case DRM_FORMAT_ABGR2101010:
12986 if (INTEL_INFO(dev)->gen < 4) {
12987 DRM_DEBUG("unsupported pixel format: %s\n",
12988 drm_get_format_name(mode_cmd->pixel_format));
12989 return -EINVAL;
12990 }
12991 break;
12992 case DRM_FORMAT_YUYV:
12993 case DRM_FORMAT_UYVY:
12994 case DRM_FORMAT_YVYU:
12995 case DRM_FORMAT_VYUY:
12996 if (INTEL_INFO(dev)->gen < 5) {
12997 DRM_DEBUG("unsupported pixel format: %s\n",
12998 drm_get_format_name(mode_cmd->pixel_format));
12999 return -EINVAL;
13000 }
13001 break;
13002 default:
13003 DRM_DEBUG("unsupported pixel format: %s\n",
13004 drm_get_format_name(mode_cmd->pixel_format));
13005 return -EINVAL;
13006 }
13007
13008 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13009 if (mode_cmd->offsets[0] != 0)
13010 return -EINVAL;
13011
13012 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13013 mode_cmd->pixel_format,
13014 mode_cmd->modifier[0]);
13015 /* FIXME drm helper for size checks (especially planar formats)? */
13016 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13017 return -EINVAL;
13018
13019 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13020 intel_fb->obj = obj;
13021 intel_fb->obj->framebuffer_references++;
13022
13023 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13024 if (ret) {
13025 DRM_ERROR("framebuffer init failed %d\n", ret);
13026 return ret;
13027 }
13028
13029 return 0;
13030 }
13031
13032 static struct drm_framebuffer *
13033 intel_user_framebuffer_create(struct drm_device *dev,
13034 struct drm_file *filp,
13035 struct drm_mode_fb_cmd2 *mode_cmd)
13036 {
13037 struct drm_i915_gem_object *obj;
13038
13039 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13040 mode_cmd->handles[0]));
13041 if (&obj->base == NULL)
13042 return ERR_PTR(-ENOENT);
13043
13044 return intel_framebuffer_create(dev, mode_cmd, obj);
13045 }
13046
13047 #ifndef CONFIG_DRM_I915_FBDEV
13048 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13049 {
13050 }
13051 #endif
13052
13053 static const struct drm_mode_config_funcs intel_mode_funcs = {
13054 .fb_create = intel_user_framebuffer_create,
13055 .output_poll_changed = intel_fbdev_output_poll_changed,
13056 .atomic_check = intel_atomic_check,
13057 .atomic_commit = intel_atomic_commit,
13058 };
13059
13060 /* Set up chip specific display functions */
13061 static void intel_init_display(struct drm_device *dev)
13062 {
13063 struct drm_i915_private *dev_priv = dev->dev_private;
13064
13065 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13066 dev_priv->display.find_dpll = g4x_find_best_dpll;
13067 else if (IS_CHERRYVIEW(dev))
13068 dev_priv->display.find_dpll = chv_find_best_dpll;
13069 else if (IS_VALLEYVIEW(dev))
13070 dev_priv->display.find_dpll = vlv_find_best_dpll;
13071 else if (IS_PINEVIEW(dev))
13072 dev_priv->display.find_dpll = pnv_find_best_dpll;
13073 else
13074 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13075
13076 if (INTEL_INFO(dev)->gen >= 9) {
13077 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13078 dev_priv->display.get_initial_plane_config =
13079 skylake_get_initial_plane_config;
13080 dev_priv->display.crtc_compute_clock =
13081 haswell_crtc_compute_clock;
13082 dev_priv->display.crtc_enable = haswell_crtc_enable;
13083 dev_priv->display.crtc_disable = haswell_crtc_disable;
13084 dev_priv->display.off = ironlake_crtc_off;
13085 dev_priv->display.update_primary_plane =
13086 skylake_update_primary_plane;
13087 } else if (HAS_DDI(dev)) {
13088 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13089 dev_priv->display.get_initial_plane_config =
13090 ironlake_get_initial_plane_config;
13091 dev_priv->display.crtc_compute_clock =
13092 haswell_crtc_compute_clock;
13093 dev_priv->display.crtc_enable = haswell_crtc_enable;
13094 dev_priv->display.crtc_disable = haswell_crtc_disable;
13095 dev_priv->display.off = ironlake_crtc_off;
13096 dev_priv->display.update_primary_plane =
13097 ironlake_update_primary_plane;
13098 } else if (HAS_PCH_SPLIT(dev)) {
13099 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13100 dev_priv->display.get_initial_plane_config =
13101 ironlake_get_initial_plane_config;
13102 dev_priv->display.crtc_compute_clock =
13103 ironlake_crtc_compute_clock;
13104 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13105 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13106 dev_priv->display.off = ironlake_crtc_off;
13107 dev_priv->display.update_primary_plane =
13108 ironlake_update_primary_plane;
13109 } else if (IS_VALLEYVIEW(dev)) {
13110 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13111 dev_priv->display.get_initial_plane_config =
13112 i9xx_get_initial_plane_config;
13113 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13114 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13115 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13116 dev_priv->display.off = i9xx_crtc_off;
13117 dev_priv->display.update_primary_plane =
13118 i9xx_update_primary_plane;
13119 } else {
13120 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13121 dev_priv->display.get_initial_plane_config =
13122 i9xx_get_initial_plane_config;
13123 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13124 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13125 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13126 dev_priv->display.off = i9xx_crtc_off;
13127 dev_priv->display.update_primary_plane =
13128 i9xx_update_primary_plane;
13129 }
13130
13131 /* Returns the core display clock speed */
13132 if (IS_VALLEYVIEW(dev))
13133 dev_priv->display.get_display_clock_speed =
13134 valleyview_get_display_clock_speed;
13135 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13136 dev_priv->display.get_display_clock_speed =
13137 i945_get_display_clock_speed;
13138 else if (IS_I915G(dev))
13139 dev_priv->display.get_display_clock_speed =
13140 i915_get_display_clock_speed;
13141 else if (IS_I945GM(dev) || IS_845G(dev))
13142 dev_priv->display.get_display_clock_speed =
13143 i9xx_misc_get_display_clock_speed;
13144 else if (IS_PINEVIEW(dev))
13145 dev_priv->display.get_display_clock_speed =
13146 pnv_get_display_clock_speed;
13147 else if (IS_I915GM(dev))
13148 dev_priv->display.get_display_clock_speed =
13149 i915gm_get_display_clock_speed;
13150 else if (IS_I865G(dev))
13151 dev_priv->display.get_display_clock_speed =
13152 i865_get_display_clock_speed;
13153 else if (IS_I85X(dev))
13154 dev_priv->display.get_display_clock_speed =
13155 i855_get_display_clock_speed;
13156 else /* 852, 830 */
13157 dev_priv->display.get_display_clock_speed =
13158 i830_get_display_clock_speed;
13159
13160 if (IS_GEN5(dev)) {
13161 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13162 } else if (IS_GEN6(dev)) {
13163 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13164 } else if (IS_IVYBRIDGE(dev)) {
13165 /* FIXME: detect B0+ stepping and use auto training */
13166 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13167 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13168 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13169 } else if (IS_VALLEYVIEW(dev)) {
13170 dev_priv->display.modeset_global_resources =
13171 valleyview_modeset_global_resources;
13172 }
13173
13174 switch (INTEL_INFO(dev)->gen) {
13175 case 2:
13176 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13177 break;
13178
13179 case 3:
13180 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13181 break;
13182
13183 case 4:
13184 case 5:
13185 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13186 break;
13187
13188 case 6:
13189 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13190 break;
13191 case 7:
13192 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13193 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13194 break;
13195 case 9:
13196 /* Drop through - unsupported since execlist only. */
13197 default:
13198 /* Default just returns -ENODEV to indicate unsupported */
13199 dev_priv->display.queue_flip = intel_default_queue_flip;
13200 }
13201
13202 intel_panel_init_backlight_funcs(dev);
13203
13204 mutex_init(&dev_priv->pps_mutex);
13205 }
13206
13207 /*
13208 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13209 * resume, or other times. This quirk makes sure that's the case for
13210 * affected systems.
13211 */
13212 static void quirk_pipea_force(struct drm_device *dev)
13213 {
13214 struct drm_i915_private *dev_priv = dev->dev_private;
13215
13216 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13217 DRM_INFO("applying pipe a force quirk\n");
13218 }
13219
13220 static void quirk_pipeb_force(struct drm_device *dev)
13221 {
13222 struct drm_i915_private *dev_priv = dev->dev_private;
13223
13224 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13225 DRM_INFO("applying pipe b force quirk\n");
13226 }
13227
13228 /*
13229 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13230 */
13231 static void quirk_ssc_force_disable(struct drm_device *dev)
13232 {
13233 struct drm_i915_private *dev_priv = dev->dev_private;
13234 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13235 DRM_INFO("applying lvds SSC disable quirk\n");
13236 }
13237
13238 /*
13239 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13240 * brightness value
13241 */
13242 static void quirk_invert_brightness(struct drm_device *dev)
13243 {
13244 struct drm_i915_private *dev_priv = dev->dev_private;
13245 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13246 DRM_INFO("applying inverted panel brightness quirk\n");
13247 }
13248
13249 /* Some VBT's incorrectly indicate no backlight is present */
13250 static void quirk_backlight_present(struct drm_device *dev)
13251 {
13252 struct drm_i915_private *dev_priv = dev->dev_private;
13253 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13254 DRM_INFO("applying backlight present quirk\n");
13255 }
13256
13257 struct intel_quirk {
13258 int device;
13259 int subsystem_vendor;
13260 int subsystem_device;
13261 void (*hook)(struct drm_device *dev);
13262 };
13263
13264 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13265 struct intel_dmi_quirk {
13266 void (*hook)(struct drm_device *dev);
13267 const struct dmi_system_id (*dmi_id_list)[];
13268 };
13269
13270 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13271 {
13272 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13273 return 1;
13274 }
13275
13276 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13277 {
13278 .dmi_id_list = &(const struct dmi_system_id[]) {
13279 {
13280 .callback = intel_dmi_reverse_brightness,
13281 .ident = "NCR Corporation",
13282 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13283 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13284 },
13285 },
13286 { } /* terminating entry */
13287 },
13288 .hook = quirk_invert_brightness,
13289 },
13290 };
13291
13292 static struct intel_quirk intel_quirks[] = {
13293 /* HP Mini needs pipe A force quirk (LP: #322104) */
13294 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13295
13296 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13297 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13298
13299 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13300 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13301
13302 /* 830 needs to leave pipe A & dpll A up */
13303 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13304
13305 /* 830 needs to leave pipe B & dpll B up */
13306 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13307
13308 /* Lenovo U160 cannot use SSC on LVDS */
13309 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13310
13311 /* Sony Vaio Y cannot use SSC on LVDS */
13312 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13313
13314 /* Acer Aspire 5734Z must invert backlight brightness */
13315 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13316
13317 /* Acer/eMachines G725 */
13318 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13319
13320 /* Acer/eMachines e725 */
13321 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13322
13323 /* Acer/Packard Bell NCL20 */
13324 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13325
13326 /* Acer Aspire 4736Z */
13327 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13328
13329 /* Acer Aspire 5336 */
13330 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13331
13332 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13333 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13334
13335 /* Acer C720 Chromebook (Core i3 4005U) */
13336 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13337
13338 /* Apple Macbook 2,1 (Core 2 T7400) */
13339 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13340
13341 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13342 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13343
13344 /* HP Chromebook 14 (Celeron 2955U) */
13345 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13346
13347 /* Dell Chromebook 11 */
13348 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13349 };
13350
13351 static void intel_init_quirks(struct drm_device *dev)
13352 {
13353 struct pci_dev *d = dev->pdev;
13354 int i;
13355
13356 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13357 struct intel_quirk *q = &intel_quirks[i];
13358
13359 if (d->device == q->device &&
13360 (d->subsystem_vendor == q->subsystem_vendor ||
13361 q->subsystem_vendor == PCI_ANY_ID) &&
13362 (d->subsystem_device == q->subsystem_device ||
13363 q->subsystem_device == PCI_ANY_ID))
13364 q->hook(dev);
13365 }
13366 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13367 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13368 intel_dmi_quirks[i].hook(dev);
13369 }
13370 }
13371
13372 /* Disable the VGA plane that we never use */
13373 static void i915_disable_vga(struct drm_device *dev)
13374 {
13375 struct drm_i915_private *dev_priv = dev->dev_private;
13376 u8 sr1;
13377 u32 vga_reg = i915_vgacntrl_reg(dev);
13378
13379 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13380 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13381 outb(SR01, VGA_SR_INDEX);
13382 sr1 = inb(VGA_SR_DATA);
13383 outb(sr1 | 1<<5, VGA_SR_DATA);
13384 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13385 udelay(300);
13386
13387 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13388 POSTING_READ(vga_reg);
13389 }
13390
13391 void intel_modeset_init_hw(struct drm_device *dev)
13392 {
13393 intel_prepare_ddi(dev);
13394
13395 if (IS_VALLEYVIEW(dev))
13396 vlv_update_cdclk(dev);
13397
13398 intel_init_clock_gating(dev);
13399
13400 intel_enable_gt_powersave(dev);
13401 }
13402
13403 void intel_modeset_init(struct drm_device *dev)
13404 {
13405 struct drm_i915_private *dev_priv = dev->dev_private;
13406 int sprite, ret;
13407 enum pipe pipe;
13408 struct intel_crtc *crtc;
13409
13410 drm_mode_config_init(dev);
13411
13412 dev->mode_config.min_width = 0;
13413 dev->mode_config.min_height = 0;
13414
13415 dev->mode_config.preferred_depth = 24;
13416 dev->mode_config.prefer_shadow = 1;
13417
13418 dev->mode_config.allow_fb_modifiers = true;
13419
13420 dev->mode_config.funcs = &intel_mode_funcs;
13421
13422 intel_init_quirks(dev);
13423
13424 intel_init_pm(dev);
13425
13426 if (INTEL_INFO(dev)->num_pipes == 0)
13427 return;
13428
13429 intel_init_display(dev);
13430 intel_init_audio(dev);
13431
13432 if (IS_GEN2(dev)) {
13433 dev->mode_config.max_width = 2048;
13434 dev->mode_config.max_height = 2048;
13435 } else if (IS_GEN3(dev)) {
13436 dev->mode_config.max_width = 4096;
13437 dev->mode_config.max_height = 4096;
13438 } else {
13439 dev->mode_config.max_width = 8192;
13440 dev->mode_config.max_height = 8192;
13441 }
13442
13443 if (IS_845G(dev) || IS_I865G(dev)) {
13444 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13445 dev->mode_config.cursor_height = 1023;
13446 } else if (IS_GEN2(dev)) {
13447 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13448 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13449 } else {
13450 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13451 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13452 }
13453
13454 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13455
13456 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13457 INTEL_INFO(dev)->num_pipes,
13458 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13459
13460 for_each_pipe(dev_priv, pipe) {
13461 intel_crtc_init(dev, pipe);
13462 for_each_sprite(dev_priv, pipe, sprite) {
13463 ret = intel_plane_init(dev, pipe, sprite);
13464 if (ret)
13465 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13466 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13467 }
13468 }
13469
13470 intel_init_dpio(dev);
13471
13472 intel_shared_dpll_init(dev);
13473
13474 /* Just disable it once at startup */
13475 i915_disable_vga(dev);
13476 intel_setup_outputs(dev);
13477
13478 /* Just in case the BIOS is doing something questionable. */
13479 intel_fbc_disable(dev);
13480
13481 drm_modeset_lock_all(dev);
13482 intel_modeset_setup_hw_state(dev, false);
13483 drm_modeset_unlock_all(dev);
13484
13485 for_each_intel_crtc(dev, crtc) {
13486 if (!crtc->active)
13487 continue;
13488
13489 /*
13490 * Note that reserving the BIOS fb up front prevents us
13491 * from stuffing other stolen allocations like the ring
13492 * on top. This prevents some ugliness at boot time, and
13493 * can even allow for smooth boot transitions if the BIOS
13494 * fb is large enough for the active pipe configuration.
13495 */
13496 if (dev_priv->display.get_initial_plane_config) {
13497 dev_priv->display.get_initial_plane_config(crtc,
13498 &crtc->plane_config);
13499 /*
13500 * If the fb is shared between multiple heads, we'll
13501 * just get the first one.
13502 */
13503 intel_find_plane_obj(crtc, &crtc->plane_config);
13504 }
13505 }
13506 }
13507
13508 static void intel_enable_pipe_a(struct drm_device *dev)
13509 {
13510 struct intel_connector *connector;
13511 struct drm_connector *crt = NULL;
13512 struct intel_load_detect_pipe load_detect_temp;
13513 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13514
13515 /* We can't just switch on the pipe A, we need to set things up with a
13516 * proper mode and output configuration. As a gross hack, enable pipe A
13517 * by enabling the load detect pipe once. */
13518 for_each_intel_connector(dev, connector) {
13519 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13520 crt = &connector->base;
13521 break;
13522 }
13523 }
13524
13525 if (!crt)
13526 return;
13527
13528 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13529 intel_release_load_detect_pipe(crt, &load_detect_temp);
13530 }
13531
13532 static bool
13533 intel_check_plane_mapping(struct intel_crtc *crtc)
13534 {
13535 struct drm_device *dev = crtc->base.dev;
13536 struct drm_i915_private *dev_priv = dev->dev_private;
13537 u32 reg, val;
13538
13539 if (INTEL_INFO(dev)->num_pipes == 1)
13540 return true;
13541
13542 reg = DSPCNTR(!crtc->plane);
13543 val = I915_READ(reg);
13544
13545 if ((val & DISPLAY_PLANE_ENABLE) &&
13546 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13547 return false;
13548
13549 return true;
13550 }
13551
13552 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13553 {
13554 struct drm_device *dev = crtc->base.dev;
13555 struct drm_i915_private *dev_priv = dev->dev_private;
13556 u32 reg;
13557
13558 /* Clear any frame start delays used for debugging left by the BIOS */
13559 reg = PIPECONF(crtc->config->cpu_transcoder);
13560 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13561
13562 /* restore vblank interrupts to correct state */
13563 drm_crtc_vblank_reset(&crtc->base);
13564 if (crtc->active) {
13565 update_scanline_offset(crtc);
13566 drm_crtc_vblank_on(&crtc->base);
13567 }
13568
13569 /* We need to sanitize the plane -> pipe mapping first because this will
13570 * disable the crtc (and hence change the state) if it is wrong. Note
13571 * that gen4+ has a fixed plane -> pipe mapping. */
13572 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13573 struct intel_connector *connector;
13574 bool plane;
13575
13576 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13577 crtc->base.base.id);
13578
13579 /* Pipe has the wrong plane attached and the plane is active.
13580 * Temporarily change the plane mapping and disable everything
13581 * ... */
13582 plane = crtc->plane;
13583 crtc->plane = !plane;
13584 crtc->primary_enabled = true;
13585 dev_priv->display.crtc_disable(&crtc->base);
13586 crtc->plane = plane;
13587
13588 /* ... and break all links. */
13589 for_each_intel_connector(dev, connector) {
13590 if (connector->encoder->base.crtc != &crtc->base)
13591 continue;
13592
13593 connector->base.dpms = DRM_MODE_DPMS_OFF;
13594 connector->base.encoder = NULL;
13595 }
13596 /* multiple connectors may have the same encoder:
13597 * handle them and break crtc link separately */
13598 for_each_intel_connector(dev, connector)
13599 if (connector->encoder->base.crtc == &crtc->base) {
13600 connector->encoder->base.crtc = NULL;
13601 connector->encoder->connectors_active = false;
13602 }
13603
13604 WARN_ON(crtc->active);
13605 crtc->base.state->enable = false;
13606 crtc->base.enabled = false;
13607 }
13608
13609 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13610 crtc->pipe == PIPE_A && !crtc->active) {
13611 /* BIOS forgot to enable pipe A, this mostly happens after
13612 * resume. Force-enable the pipe to fix this, the update_dpms
13613 * call below we restore the pipe to the right state, but leave
13614 * the required bits on. */
13615 intel_enable_pipe_a(dev);
13616 }
13617
13618 /* Adjust the state of the output pipe according to whether we
13619 * have active connectors/encoders. */
13620 intel_crtc_update_dpms(&crtc->base);
13621
13622 if (crtc->active != crtc->base.state->enable) {
13623 struct intel_encoder *encoder;
13624
13625 /* This can happen either due to bugs in the get_hw_state
13626 * functions or because the pipe is force-enabled due to the
13627 * pipe A quirk. */
13628 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13629 crtc->base.base.id,
13630 crtc->base.state->enable ? "enabled" : "disabled",
13631 crtc->active ? "enabled" : "disabled");
13632
13633 crtc->base.state->enable = crtc->active;
13634 crtc->base.enabled = crtc->active;
13635
13636 /* Because we only establish the connector -> encoder ->
13637 * crtc links if something is active, this means the
13638 * crtc is now deactivated. Break the links. connector
13639 * -> encoder links are only establish when things are
13640 * actually up, hence no need to break them. */
13641 WARN_ON(crtc->active);
13642
13643 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13644 WARN_ON(encoder->connectors_active);
13645 encoder->base.crtc = NULL;
13646 }
13647 }
13648
13649 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13650 /*
13651 * We start out with underrun reporting disabled to avoid races.
13652 * For correct bookkeeping mark this on active crtcs.
13653 *
13654 * Also on gmch platforms we dont have any hardware bits to
13655 * disable the underrun reporting. Which means we need to start
13656 * out with underrun reporting disabled also on inactive pipes,
13657 * since otherwise we'll complain about the garbage we read when
13658 * e.g. coming up after runtime pm.
13659 *
13660 * No protection against concurrent access is required - at
13661 * worst a fifo underrun happens which also sets this to false.
13662 */
13663 crtc->cpu_fifo_underrun_disabled = true;
13664 crtc->pch_fifo_underrun_disabled = true;
13665 }
13666 }
13667
13668 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13669 {
13670 struct intel_connector *connector;
13671 struct drm_device *dev = encoder->base.dev;
13672
13673 /* We need to check both for a crtc link (meaning that the
13674 * encoder is active and trying to read from a pipe) and the
13675 * pipe itself being active. */
13676 bool has_active_crtc = encoder->base.crtc &&
13677 to_intel_crtc(encoder->base.crtc)->active;
13678
13679 if (encoder->connectors_active && !has_active_crtc) {
13680 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13681 encoder->base.base.id,
13682 encoder->base.name);
13683
13684 /* Connector is active, but has no active pipe. This is
13685 * fallout from our resume register restoring. Disable
13686 * the encoder manually again. */
13687 if (encoder->base.crtc) {
13688 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13689 encoder->base.base.id,
13690 encoder->base.name);
13691 encoder->disable(encoder);
13692 if (encoder->post_disable)
13693 encoder->post_disable(encoder);
13694 }
13695 encoder->base.crtc = NULL;
13696 encoder->connectors_active = false;
13697
13698 /* Inconsistent output/port/pipe state happens presumably due to
13699 * a bug in one of the get_hw_state functions. Or someplace else
13700 * in our code, like the register restore mess on resume. Clamp
13701 * things to off as a safer default. */
13702 for_each_intel_connector(dev, connector) {
13703 if (connector->encoder != encoder)
13704 continue;
13705 connector->base.dpms = DRM_MODE_DPMS_OFF;
13706 connector->base.encoder = NULL;
13707 }
13708 }
13709 /* Enabled encoders without active connectors will be fixed in
13710 * the crtc fixup. */
13711 }
13712
13713 void i915_redisable_vga_power_on(struct drm_device *dev)
13714 {
13715 struct drm_i915_private *dev_priv = dev->dev_private;
13716 u32 vga_reg = i915_vgacntrl_reg(dev);
13717
13718 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13719 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13720 i915_disable_vga(dev);
13721 }
13722 }
13723
13724 void i915_redisable_vga(struct drm_device *dev)
13725 {
13726 struct drm_i915_private *dev_priv = dev->dev_private;
13727
13728 /* This function can be called both from intel_modeset_setup_hw_state or
13729 * at a very early point in our resume sequence, where the power well
13730 * structures are not yet restored. Since this function is at a very
13731 * paranoid "someone might have enabled VGA while we were not looking"
13732 * level, just check if the power well is enabled instead of trying to
13733 * follow the "don't touch the power well if we don't need it" policy
13734 * the rest of the driver uses. */
13735 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13736 return;
13737
13738 i915_redisable_vga_power_on(dev);
13739 }
13740
13741 static bool primary_get_hw_state(struct intel_crtc *crtc)
13742 {
13743 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13744
13745 if (!crtc->active)
13746 return false;
13747
13748 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13749 }
13750
13751 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13752 {
13753 struct drm_i915_private *dev_priv = dev->dev_private;
13754 enum pipe pipe;
13755 struct intel_crtc *crtc;
13756 struct intel_encoder *encoder;
13757 struct intel_connector *connector;
13758 int i;
13759
13760 for_each_intel_crtc(dev, crtc) {
13761 memset(crtc->config, 0, sizeof(*crtc->config));
13762
13763 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13764
13765 crtc->active = dev_priv->display.get_pipe_config(crtc,
13766 crtc->config);
13767
13768 crtc->base.state->enable = crtc->active;
13769 crtc->base.enabled = crtc->active;
13770 crtc->primary_enabled = primary_get_hw_state(crtc);
13771
13772 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13773 crtc->base.base.id,
13774 crtc->active ? "enabled" : "disabled");
13775 }
13776
13777 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13778 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13779
13780 pll->on = pll->get_hw_state(dev_priv, pll,
13781 &pll->config.hw_state);
13782 pll->active = 0;
13783 pll->config.crtc_mask = 0;
13784 for_each_intel_crtc(dev, crtc) {
13785 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13786 pll->active++;
13787 pll->config.crtc_mask |= 1 << crtc->pipe;
13788 }
13789 }
13790
13791 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13792 pll->name, pll->config.crtc_mask, pll->on);
13793
13794 if (pll->config.crtc_mask)
13795 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13796 }
13797
13798 for_each_intel_encoder(dev, encoder) {
13799 pipe = 0;
13800
13801 if (encoder->get_hw_state(encoder, &pipe)) {
13802 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13803 encoder->base.crtc = &crtc->base;
13804 encoder->get_config(encoder, crtc->config);
13805 } else {
13806 encoder->base.crtc = NULL;
13807 }
13808
13809 encoder->connectors_active = false;
13810 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13811 encoder->base.base.id,
13812 encoder->base.name,
13813 encoder->base.crtc ? "enabled" : "disabled",
13814 pipe_name(pipe));
13815 }
13816
13817 for_each_intel_connector(dev, connector) {
13818 if (connector->get_hw_state(connector)) {
13819 connector->base.dpms = DRM_MODE_DPMS_ON;
13820 connector->encoder->connectors_active = true;
13821 connector->base.encoder = &connector->encoder->base;
13822 } else {
13823 connector->base.dpms = DRM_MODE_DPMS_OFF;
13824 connector->base.encoder = NULL;
13825 }
13826 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13827 connector->base.base.id,
13828 connector->base.name,
13829 connector->base.encoder ? "enabled" : "disabled");
13830 }
13831 }
13832
13833 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13834 * and i915 state tracking structures. */
13835 void intel_modeset_setup_hw_state(struct drm_device *dev,
13836 bool force_restore)
13837 {
13838 struct drm_i915_private *dev_priv = dev->dev_private;
13839 enum pipe pipe;
13840 struct intel_crtc *crtc;
13841 struct intel_encoder *encoder;
13842 int i;
13843
13844 intel_modeset_readout_hw_state(dev);
13845
13846 /*
13847 * Now that we have the config, copy it to each CRTC struct
13848 * Note that this could go away if we move to using crtc_config
13849 * checking everywhere.
13850 */
13851 for_each_intel_crtc(dev, crtc) {
13852 if (crtc->active && i915.fastboot) {
13853 intel_mode_from_pipe_config(&crtc->base.mode,
13854 crtc->config);
13855 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13856 crtc->base.base.id);
13857 drm_mode_debug_printmodeline(&crtc->base.mode);
13858 }
13859 }
13860
13861 /* HW state is read out, now we need to sanitize this mess. */
13862 for_each_intel_encoder(dev, encoder) {
13863 intel_sanitize_encoder(encoder);
13864 }
13865
13866 for_each_pipe(dev_priv, pipe) {
13867 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13868 intel_sanitize_crtc(crtc);
13869 intel_dump_pipe_config(crtc, crtc->config,
13870 "[setup_hw_state]");
13871 }
13872
13873 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13874 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13875
13876 if (!pll->on || pll->active)
13877 continue;
13878
13879 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13880
13881 pll->disable(dev_priv, pll);
13882 pll->on = false;
13883 }
13884
13885 if (IS_GEN9(dev))
13886 skl_wm_get_hw_state(dev);
13887 else if (HAS_PCH_SPLIT(dev))
13888 ilk_wm_get_hw_state(dev);
13889
13890 if (force_restore) {
13891 i915_redisable_vga(dev);
13892
13893 /*
13894 * We need to use raw interfaces for restoring state to avoid
13895 * checking (bogus) intermediate states.
13896 */
13897 for_each_pipe(dev_priv, pipe) {
13898 struct drm_crtc *crtc =
13899 dev_priv->pipe_to_crtc_mapping[pipe];
13900
13901 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13902 crtc->primary->fb);
13903 }
13904 } else {
13905 intel_modeset_update_staged_output_state(dev);
13906 }
13907
13908 intel_modeset_check_state(dev);
13909 }
13910
13911 void intel_modeset_gem_init(struct drm_device *dev)
13912 {
13913 struct drm_i915_private *dev_priv = dev->dev_private;
13914 struct drm_crtc *c;
13915 struct drm_i915_gem_object *obj;
13916
13917 mutex_lock(&dev->struct_mutex);
13918 intel_init_gt_powersave(dev);
13919 mutex_unlock(&dev->struct_mutex);
13920
13921 /*
13922 * There may be no VBT; and if the BIOS enabled SSC we can
13923 * just keep using it to avoid unnecessary flicker. Whereas if the
13924 * BIOS isn't using it, don't assume it will work even if the VBT
13925 * indicates as much.
13926 */
13927 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13928 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13929 DREF_SSC1_ENABLE);
13930
13931 intel_modeset_init_hw(dev);
13932
13933 intel_setup_overlay(dev);
13934
13935 /*
13936 * Make sure any fbs we allocated at startup are properly
13937 * pinned & fenced. When we do the allocation it's too early
13938 * for this.
13939 */
13940 mutex_lock(&dev->struct_mutex);
13941 for_each_crtc(dev, c) {
13942 obj = intel_fb_obj(c->primary->fb);
13943 if (obj == NULL)
13944 continue;
13945
13946 if (intel_pin_and_fence_fb_obj(c->primary,
13947 c->primary->fb,
13948 c->primary->state,
13949 NULL)) {
13950 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13951 to_intel_crtc(c)->pipe);
13952 drm_framebuffer_unreference(c->primary->fb);
13953 c->primary->fb = NULL;
13954 update_state_fb(c->primary);
13955 }
13956 }
13957 mutex_unlock(&dev->struct_mutex);
13958
13959 intel_backlight_register(dev);
13960 }
13961
13962 void intel_connector_unregister(struct intel_connector *intel_connector)
13963 {
13964 struct drm_connector *connector = &intel_connector->base;
13965
13966 intel_panel_destroy_backlight(connector);
13967 drm_connector_unregister(connector);
13968 }
13969
13970 void intel_modeset_cleanup(struct drm_device *dev)
13971 {
13972 struct drm_i915_private *dev_priv = dev->dev_private;
13973 struct drm_connector *connector;
13974
13975 intel_disable_gt_powersave(dev);
13976
13977 intel_backlight_unregister(dev);
13978
13979 /*
13980 * Interrupts and polling as the first thing to avoid creating havoc.
13981 * Too much stuff here (turning of connectors, ...) would
13982 * experience fancy races otherwise.
13983 */
13984 intel_irq_uninstall(dev_priv);
13985
13986 /*
13987 * Due to the hpd irq storm handling the hotplug work can re-arm the
13988 * poll handlers. Hence disable polling after hpd handling is shut down.
13989 */
13990 drm_kms_helper_poll_fini(dev);
13991
13992 mutex_lock(&dev->struct_mutex);
13993
13994 intel_unregister_dsm_handler();
13995
13996 intel_fbc_disable(dev);
13997
13998 mutex_unlock(&dev->struct_mutex);
13999
14000 /* flush any delayed tasks or pending work */
14001 flush_scheduled_work();
14002
14003 /* destroy the backlight and sysfs files before encoders/connectors */
14004 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14005 struct intel_connector *intel_connector;
14006
14007 intel_connector = to_intel_connector(connector);
14008 intel_connector->unregister(intel_connector);
14009 }
14010
14011 drm_mode_config_cleanup(dev);
14012
14013 intel_cleanup_overlay(dev);
14014
14015 mutex_lock(&dev->struct_mutex);
14016 intel_cleanup_gt_powersave(dev);
14017 mutex_unlock(&dev->struct_mutex);
14018 }
14019
14020 /*
14021 * Return which encoder is currently attached for connector.
14022 */
14023 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14024 {
14025 return &intel_attached_encoder(connector)->base;
14026 }
14027
14028 void intel_connector_attach_encoder(struct intel_connector *connector,
14029 struct intel_encoder *encoder)
14030 {
14031 connector->encoder = encoder;
14032 drm_mode_connector_attach_encoder(&connector->base,
14033 &encoder->base);
14034 }
14035
14036 /*
14037 * set vga decode state - true == enable VGA decode
14038 */
14039 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14040 {
14041 struct drm_i915_private *dev_priv = dev->dev_private;
14042 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14043 u16 gmch_ctrl;
14044
14045 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14046 DRM_ERROR("failed to read control word\n");
14047 return -EIO;
14048 }
14049
14050 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14051 return 0;
14052
14053 if (state)
14054 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14055 else
14056 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14057
14058 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14059 DRM_ERROR("failed to write control word\n");
14060 return -EIO;
14061 }
14062
14063 return 0;
14064 }
14065
14066 struct intel_display_error_state {
14067
14068 u32 power_well_driver;
14069
14070 int num_transcoders;
14071
14072 struct intel_cursor_error_state {
14073 u32 control;
14074 u32 position;
14075 u32 base;
14076 u32 size;
14077 } cursor[I915_MAX_PIPES];
14078
14079 struct intel_pipe_error_state {
14080 bool power_domain_on;
14081 u32 source;
14082 u32 stat;
14083 } pipe[I915_MAX_PIPES];
14084
14085 struct intel_plane_error_state {
14086 u32 control;
14087 u32 stride;
14088 u32 size;
14089 u32 pos;
14090 u32 addr;
14091 u32 surface;
14092 u32 tile_offset;
14093 } plane[I915_MAX_PIPES];
14094
14095 struct intel_transcoder_error_state {
14096 bool power_domain_on;
14097 enum transcoder cpu_transcoder;
14098
14099 u32 conf;
14100
14101 u32 htotal;
14102 u32 hblank;
14103 u32 hsync;
14104 u32 vtotal;
14105 u32 vblank;
14106 u32 vsync;
14107 } transcoder[4];
14108 };
14109
14110 struct intel_display_error_state *
14111 intel_display_capture_error_state(struct drm_device *dev)
14112 {
14113 struct drm_i915_private *dev_priv = dev->dev_private;
14114 struct intel_display_error_state *error;
14115 int transcoders[] = {
14116 TRANSCODER_A,
14117 TRANSCODER_B,
14118 TRANSCODER_C,
14119 TRANSCODER_EDP,
14120 };
14121 int i;
14122
14123 if (INTEL_INFO(dev)->num_pipes == 0)
14124 return NULL;
14125
14126 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14127 if (error == NULL)
14128 return NULL;
14129
14130 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14131 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14132
14133 for_each_pipe(dev_priv, i) {
14134 error->pipe[i].power_domain_on =
14135 __intel_display_power_is_enabled(dev_priv,
14136 POWER_DOMAIN_PIPE(i));
14137 if (!error->pipe[i].power_domain_on)
14138 continue;
14139
14140 error->cursor[i].control = I915_READ(CURCNTR(i));
14141 error->cursor[i].position = I915_READ(CURPOS(i));
14142 error->cursor[i].base = I915_READ(CURBASE(i));
14143
14144 error->plane[i].control = I915_READ(DSPCNTR(i));
14145 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14146 if (INTEL_INFO(dev)->gen <= 3) {
14147 error->plane[i].size = I915_READ(DSPSIZE(i));
14148 error->plane[i].pos = I915_READ(DSPPOS(i));
14149 }
14150 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14151 error->plane[i].addr = I915_READ(DSPADDR(i));
14152 if (INTEL_INFO(dev)->gen >= 4) {
14153 error->plane[i].surface = I915_READ(DSPSURF(i));
14154 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14155 }
14156
14157 error->pipe[i].source = I915_READ(PIPESRC(i));
14158
14159 if (HAS_GMCH_DISPLAY(dev))
14160 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14161 }
14162
14163 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14164 if (HAS_DDI(dev_priv->dev))
14165 error->num_transcoders++; /* Account for eDP. */
14166
14167 for (i = 0; i < error->num_transcoders; i++) {
14168 enum transcoder cpu_transcoder = transcoders[i];
14169
14170 error->transcoder[i].power_domain_on =
14171 __intel_display_power_is_enabled(dev_priv,
14172 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14173 if (!error->transcoder[i].power_domain_on)
14174 continue;
14175
14176 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14177
14178 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14179 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14180 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14181 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14182 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14183 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14184 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14185 }
14186
14187 return error;
14188 }
14189
14190 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14191
14192 void
14193 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14194 struct drm_device *dev,
14195 struct intel_display_error_state *error)
14196 {
14197 struct drm_i915_private *dev_priv = dev->dev_private;
14198 int i;
14199
14200 if (!error)
14201 return;
14202
14203 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14204 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14205 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14206 error->power_well_driver);
14207 for_each_pipe(dev_priv, i) {
14208 err_printf(m, "Pipe [%d]:\n", i);
14209 err_printf(m, " Power: %s\n",
14210 error->pipe[i].power_domain_on ? "on" : "off");
14211 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14212 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14213
14214 err_printf(m, "Plane [%d]:\n", i);
14215 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14216 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14217 if (INTEL_INFO(dev)->gen <= 3) {
14218 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14219 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14220 }
14221 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14222 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14223 if (INTEL_INFO(dev)->gen >= 4) {
14224 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14225 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14226 }
14227
14228 err_printf(m, "Cursor [%d]:\n", i);
14229 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14230 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14231 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14232 }
14233
14234 for (i = 0; i < error->num_transcoders; i++) {
14235 err_printf(m, "CPU transcoder: %c\n",
14236 transcoder_name(error->transcoder[i].cpu_transcoder));
14237 err_printf(m, " Power: %s\n",
14238 error->transcoder[i].power_domain_on ? "on" : "off");
14239 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14240 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14241 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14242 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14243 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14244 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14245 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14246 }
14247 }
14248
14249 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14250 {
14251 struct intel_crtc *crtc;
14252
14253 for_each_intel_crtc(dev, crtc) {
14254 struct intel_unpin_work *work;
14255
14256 spin_lock_irq(&dev->event_lock);
14257
14258 work = crtc->unpin_work;
14259
14260 if (work && work->event &&
14261 work->event->base.file_priv == file) {
14262 kfree(work->event);
14263 work->event = NULL;
14264 }
14265
14266 spin_unlock_irq(&dev->event_lock);
14267 }
14268 }
Linux kernel - Deliverables
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