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drm/i915: Do not run most checks when there's no modeset.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
114
115 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
116 {
117 if (!connector->mst_port)
118 return connector->encoder;
119 else
120 return &connector->mst_port->mst_encoders[pipe]->base;
121 }
122
123 typedef struct {
124 int min, max;
125 } intel_range_t;
126
127 typedef struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } intel_p2_t;
131
132 typedef struct intel_limit intel_limit_t;
133 struct intel_limit {
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
136 };
137
138 int
139 intel_pch_rawclk(struct drm_device *dev)
140 {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142
143 WARN_ON(!HAS_PCH_SPLIT(dev));
144
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146 }
147
148 static inline u32 /* units of 100MHz */
149 intel_fdi_link_freq(struct drm_device *dev)
150 {
151 if (IS_GEN5(dev)) {
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
154 } else
155 return 27;
156 }
157
158 static const intel_limit_t intel_limits_i8xx_dac = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
182 };
183
184 static const intel_limit_t intel_limits_i8xx_lvds = {
185 .dot = { .min = 25000, .max = 350000 },
186 .vco = { .min = 908000, .max = 1512000 },
187 .n = { .min = 2, .max = 16 },
188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_sdvo = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
208 };
209
210 static const intel_limit_t intel_limits_i9xx_lvds = {
211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
221 };
222
223
224 static const intel_limit_t intel_limits_g4x_sdvo = {
225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
234 .p2_slow = 10,
235 .p2_fast = 10
236 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_hdmi = {
240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
250 };
251
252 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
263 },
264 };
265
266 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
277 },
278 };
279
280 static const intel_limit_t intel_limits_pineview_sdvo = {
281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
283 /* Pineview's Ncounter is a ring counter */
284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
286 /* Pineview only has one combined m divider, which we treat as m2. */
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
293 };
294
295 static const intel_limit_t intel_limits_pineview_lvds = {
296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
306 };
307
308 /* Ironlake / Sandybridge
309 *
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
312 */
313 static const intel_limit_t intel_limits_ironlake_dac = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_single_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 };
351
352 /* LVDS 100mhz refclk limits. */
353 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
364 };
365
366 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
377 };
378
379 static const intel_limit_t intel_limits_vlv = {
380 /*
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
385 */
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
387 .vco = { .min = 4000000, .max = 6000000 },
388 .n = { .min = 1, .max = 7 },
389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
391 .p1 = { .min = 2, .max = 3 },
392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
393 };
394
395 static const intel_limit_t intel_limits_chv = {
396 /*
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
401 */
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
403 .vco = { .min = 4800000, .max = 6480000 },
404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409 };
410
411 static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
421 };
422
423 static void vlv_clock(int refclk, intel_clock_t *clock)
424 {
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
427 if (WARN_ON(clock->n == 0 || clock->p == 0))
428 return;
429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
431 }
432
433 static bool
434 needs_modeset(struct drm_crtc_state *state)
435 {
436 return state->mode_changed || state->active_changed;
437 }
438
439 /**
440 * Returns whether any output on the specified pipe is of the specified type
441 */
442 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 struct intel_encoder *encoder;
446
447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
448 if (encoder->type == type)
449 return true;
450
451 return false;
452 }
453
454 /**
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
458 * encoder->crtc.
459 */
460 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
461 int type)
462 {
463 struct drm_atomic_state *state = crtc_state->base.state;
464 struct drm_connector *connector;
465 struct drm_connector_state *connector_state;
466 struct intel_encoder *encoder;
467 int i, num_connectors = 0;
468
469 for_each_connector_in_state(state, connector, connector_state, i) {
470 if (connector_state->crtc != crtc_state->base.crtc)
471 continue;
472
473 num_connectors++;
474
475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
477 return true;
478 }
479
480 WARN_ON(num_connectors == 0);
481
482 return false;
483 }
484
485 static const intel_limit_t *
486 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
487 {
488 struct drm_device *dev = crtc_state->base.crtc->dev;
489 const intel_limit_t *limit;
490
491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
492 if (intel_is_dual_link_lvds(dev)) {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_dual_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_dual_lvds;
497 } else {
498 if (refclk == 100000)
499 limit = &intel_limits_ironlake_single_lvds_100m;
500 else
501 limit = &intel_limits_ironlake_single_lvds;
502 }
503 } else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *
510 intel_g4x_limit(struct intel_crtc_state *crtc_state)
511 {
512 struct drm_device *dev = crtc_state->base.crtc->dev;
513 const intel_limit_t *limit;
514
515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
516 if (intel_is_dual_link_lvds(dev))
517 limit = &intel_limits_g4x_dual_channel_lvds;
518 else
519 limit = &intel_limits_g4x_single_channel_lvds;
520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
522 limit = &intel_limits_g4x_hdmi;
523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
524 limit = &intel_limits_g4x_sdvo;
525 } else /* The option is for other outputs */
526 limit = &intel_limits_i9xx_sdvo;
527
528 return limit;
529 }
530
531 static const intel_limit_t *
532 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
533 {
534 struct drm_device *dev = crtc_state->base.crtc->dev;
535 const intel_limit_t *limit;
536
537 if (IS_BROXTON(dev))
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
540 limit = intel_ironlake_limit(crtc_state, refclk);
541 else if (IS_G4X(dev)) {
542 limit = intel_g4x_limit(crtc_state);
543 } else if (IS_PINEVIEW(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_pineview_lvds;
546 else
547 limit = &intel_limits_pineview_sdvo;
548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
550 } else if (IS_VALLEYVIEW(dev)) {
551 limit = &intel_limits_vlv;
552 } else if (!IS_GEN2(dev)) {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i9xx_lvds;
555 else
556 limit = &intel_limits_i9xx_sdvo;
557 } else {
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
559 limit = &intel_limits_i8xx_lvds;
560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
561 limit = &intel_limits_i8xx_dvo;
562 else
563 limit = &intel_limits_i8xx_dac;
564 }
565 return limit;
566 }
567
568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
569 static void pineview_clock(int refclk, intel_clock_t *clock)
570 {
571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
577 }
578
579 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
580 {
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582 }
583
584 static void i9xx_clock(int refclk, intel_clock_t *clock)
585 {
586 clock->m = i9xx_dpll_compute_m(clock);
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
589 return;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592 }
593
594 static void chv_clock(int refclk, intel_clock_t *clock)
595 {
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return;
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
601 clock->n << 22);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603 }
604
605 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
606 /**
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
609 */
610
611 static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
614 {
615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
618 INTELPllInvalid("p1 out of range\n");
619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
620 INTELPllInvalid("m2 out of range\n");
621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
622 INTELPllInvalid("m1 out of range\n");
623
624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
627
628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
642
643 return true;
644 }
645
646 static bool
647 i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
651 {
652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
653 struct drm_device *dev = crtc->base.dev;
654 intel_clock_t clock;
655 int err = target;
656
657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
658 /*
659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
662 */
663 if (intel_is_dual_link_lvds(dev))
664 clock.p2 = limit->p2.p2_fast;
665 else
666 clock.p2 = limit->p2.p2_slow;
667 } else {
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
670 else
671 clock.p2 = limit->p2.p2_fast;
672 }
673
674 memset(best_clock, 0, sizeof(*best_clock));
675
676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
677 clock.m1++) {
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
680 if (clock.m2 >= clock.m1)
681 break;
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
686 int this_err;
687
688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
690 &clock))
691 continue;
692 if (match_clock &&
693 clock.p != match_clock->p)
694 continue;
695
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
698 *best_clock = clock;
699 err = this_err;
700 }
701 }
702 }
703 }
704 }
705
706 return (err != target);
707 }
708
709 static bool
710 pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
714 {
715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
716 struct drm_device *dev = crtc->base.dev;
717 intel_clock_t clock;
718 int err = target;
719
720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
721 /*
722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
725 */
726 if (intel_is_dual_link_lvds(dev))
727 clock.p2 = limit->p2.p2_fast;
728 else
729 clock.p2 = limit->p2.p2_slow;
730 } else {
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
733 else
734 clock.p2 = limit->p2.p2_fast;
735 }
736
737 memset(best_clock, 0, sizeof(*best_clock));
738
739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 clock.m1++) {
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
747 int this_err;
748
749 pineview_clock(refclk, &clock);
750 if (!intel_PLL_is_valid(dev, limit,
751 &clock))
752 continue;
753 if (match_clock &&
754 clock.p != match_clock->p)
755 continue;
756
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
759 *best_clock = clock;
760 err = this_err;
761 }
762 }
763 }
764 }
765 }
766
767 return (err != target);
768 }
769
770 static bool
771 g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
775 {
776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
777 struct drm_device *dev = crtc->base.dev;
778 intel_clock_t clock;
779 int max_n;
780 bool found;
781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
783 found = false;
784
785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
786 if (intel_is_dual_link_lvds(dev))
787 clock.p2 = limit->p2.p2_fast;
788 else
789 clock.p2 = limit->p2.p2_slow;
790 } else {
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
793 else
794 clock.p2 = limit->p2.p2_fast;
795 }
796
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
799 /* based on hardware requirement, prefer smaller n to precision */
800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
801 /* based on hardware requirement, prefere larger m1,m2 */
802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
808 int this_err;
809
810 i9xx_clock(refclk, &clock);
811 if (!intel_PLL_is_valid(dev, limit,
812 &clock))
813 continue;
814
815 this_err = abs(clock.dot - target);
816 if (this_err < err_most) {
817 *best_clock = clock;
818 err_most = this_err;
819 max_n = clock.n;
820 found = true;
821 }
822 }
823 }
824 }
825 }
826 return found;
827 }
828
829 /*
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
832 */
833 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
838 {
839 /*
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
842 */
843 if (IS_CHERRYVIEW(dev)) {
844 *error_ppm = 0;
845
846 return calculated_clock->p > best_clock->p;
847 }
848
849 if (WARN_ON_ONCE(!target_freq))
850 return false;
851
852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
854 target_freq);
855 /*
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
859 */
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
861 *error_ppm = 0;
862
863 return true;
864 }
865
866 return *error_ppm + 10 < best_error_ppm;
867 }
868
869 static bool
870 vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
874 {
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
876 struct drm_device *dev = crtc->base.dev;
877 intel_clock_t clock;
878 unsigned int bestppm = 1000000;
879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
881 bool found = false;
882
883 target *= 5; /* fast clock */
884
885 memset(best_clock, 0, sizeof(*best_clock));
886
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
892 clock.p = clock.p1 * clock.p2;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
895 unsigned int ppm;
896
897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
898 refclk * clock.m1);
899
900 vlv_clock(refclk, &clock);
901
902 if (!intel_PLL_is_valid(dev, limit,
903 &clock))
904 continue;
905
906 if (!vlv_PLL_is_optimal(dev, target,
907 &clock,
908 best_clock,
909 bestppm, &ppm))
910 continue;
911
912 *best_clock = clock;
913 bestppm = ppm;
914 found = true;
915 }
916 }
917 }
918 }
919
920 return found;
921 }
922
923 static bool
924 chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
928 {
929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
930 struct drm_device *dev = crtc->base.dev;
931 unsigned int best_error_ppm;
932 intel_clock_t clock;
933 uint64_t m2;
934 int found = false;
935
936 memset(best_clock, 0, sizeof(*best_clock));
937 best_error_ppm = 1000000;
938
939 /*
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
943 */
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
946
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
951 unsigned int error_ppm;
952
953 clock.p = clock.p1 * clock.p2;
954
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
957
958 if (m2 > INT_MAX/clock.m1)
959 continue;
960
961 clock.m2 = m2;
962
963 chv_clock(refclk, &clock);
964
965 if (!intel_PLL_is_valid(dev, limit, &clock))
966 continue;
967
968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
970 continue;
971
972 *best_clock = clock;
973 best_error_ppm = error_ppm;
974 found = true;
975 }
976 }
977
978 return found;
979 }
980
981 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
983 {
984 int refclk = i9xx_get_refclk(crtc_state, 0);
985
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
988 }
989
990 bool intel_crtc_active(struct drm_crtc *crtc)
991 {
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
996 *
997 * We can ditch the adjusted_mode.crtc_clock check as soon
998 * as Haswell has gained clock readout/fastboot support.
999 *
1000 * We can ditch the crtc->primary->fb check as soon as we can
1001 * properly reconstruct framebuffers.
1002 *
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1005 * for atomic.
1006 */
1007 return intel_crtc->active && crtc->primary->state->fb &&
1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
1009 }
1010
1011 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013 {
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
1017 return intel_crtc->config->cpu_transcoder;
1018 }
1019
1020 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021 {
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1024 u32 line1, line2;
1025 u32 line_mask;
1026
1027 if (IS_GEN2(dev))
1028 line_mask = DSL_LINEMASK_GEN2;
1029 else
1030 line_mask = DSL_LINEMASK_GEN3;
1031
1032 line1 = I915_READ(reg) & line_mask;
1033 mdelay(5);
1034 line2 = I915_READ(reg) & line_mask;
1035
1036 return line1 == line2;
1037 }
1038
1039 /*
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
1041 * @crtc: crtc whose pipe to wait for
1042 *
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1046 *
1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1049 *
1050 * Otherwise:
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
1053 *
1054 */
1055 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1056 {
1057 struct drm_device *dev = crtc->base.dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1060 enum pipe pipe = crtc->pipe;
1061
1062 if (INTEL_INFO(dev)->gen >= 4) {
1063 int reg = PIPECONF(cpu_transcoder);
1064
1065 /* Wait for the Pipe State to go off */
1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067 100))
1068 WARN(1, "pipe_off wait timed out\n");
1069 } else {
1070 /* Wait for the display line to settle */
1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1072 WARN(1, "pipe_off wait timed out\n");
1073 }
1074 }
1075
1076 /*
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1080 *
1081 * Returns true if @port is connected, false otherwise.
1082 */
1083 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1085 {
1086 u32 bit;
1087
1088 if (HAS_PCH_IBX(dev_priv->dev)) {
1089 switch (port->port) {
1090 case PORT_B:
1091 bit = SDE_PORTB_HOTPLUG;
1092 break;
1093 case PORT_C:
1094 bit = SDE_PORTC_HOTPLUG;
1095 break;
1096 case PORT_D:
1097 bit = SDE_PORTD_HOTPLUG;
1098 break;
1099 default:
1100 return true;
1101 }
1102 } else {
1103 switch (port->port) {
1104 case PORT_B:
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1106 break;
1107 case PORT_C:
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1109 break;
1110 case PORT_D:
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1112 break;
1113 default:
1114 return true;
1115 }
1116 }
1117
1118 return I915_READ(SDEISR) & bit;
1119 }
1120
1121 static const char *state_string(bool enabled)
1122 {
1123 return enabled ? "on" : "off";
1124 }
1125
1126 /* Only for pre-ILK configs */
1127 void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
1129 {
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DPLL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
1137 I915_STATE_WARN(cur_state != state,
1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141
1142 /* XXX: the dsi pll is shared between MIPI DSI ports */
1143 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 mutex_lock(&dev_priv->sb_lock);
1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1150 mutex_unlock(&dev_priv->sb_lock);
1151
1152 cur_state = val & DSI_PLL_VCO_EN;
1153 I915_STATE_WARN(cur_state != state,
1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156 }
1157 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
1160 struct intel_shared_dpll *
1161 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162 {
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
1165 if (crtc->config->shared_dpll < 0)
1166 return NULL;
1167
1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1169 }
1170
1171 /* For ILK+ */
1172 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1174 bool state)
1175 {
1176 bool cur_state;
1177 struct intel_dpll_hw_state hw_state;
1178
1179 if (WARN (!pll,
1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
1181 return;
1182
1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1184 I915_STATE_WARN(cur_state != state,
1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 int reg;
1193 u32 val;
1194 bool cur_state;
1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196 pipe);
1197
1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1203 } else {
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1207 }
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217 {
1218 int reg;
1219 u32 val;
1220 bool cur_state;
1221
1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1228 }
1229 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 int reg;
1236 u32 val;
1237
1238 /* ILK FDI PLL is always enabled */
1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1240 return;
1241
1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243 if (HAS_DDI(dev_priv->dev))
1244 return;
1245
1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1249 }
1250
1251 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
1264 }
1265
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268 {
1269 struct drm_device *dev = dev_priv->dev;
1270 int pp_reg;
1271 u32 val;
1272 enum pipe panel_pipe = PIPE_A;
1273 bool locked = true;
1274
1275 if (WARN_ON(HAS_DDI(dev)))
1276 return;
1277
1278 if (HAS_PCH_SPLIT(dev)) {
1279 u32 port_sel;
1280
1281 pp_reg = PCH_PP_CONTROL;
1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291 panel_pipe = pipe;
1292 } else {
1293 pp_reg = PP_CONTROL;
1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
1296 }
1297
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1301 locked = false;
1302
1303 I915_STATE_WARN(panel_pipe == pipe && locked,
1304 "panel assertion failure, pipe %c regs locked\n",
1305 pipe_name(pipe));
1306 }
1307
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1310 {
1311 struct drm_device *dev = dev_priv->dev;
1312 bool cur_state;
1313
1314 if (IS_845G(dev) || IS_I865G(dev))
1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1316 else
1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1318
1319 I915_STATE_WARN(cur_state != state,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1322 }
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 int reg;
1330 u32 val;
1331 bool cur_state;
1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333 pipe);
1334
1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338 state = true;
1339
1340 if (!intel_display_power_is_enabled(dev_priv,
1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1342 cur_state = false;
1343 } else {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1347 }
1348
1349 I915_STATE_WARN(cur_state != state,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
1356 {
1357 int reg;
1358 u32 val;
1359 bool cur_state;
1360
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1364 I915_STATE_WARN(cur_state != state,
1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
1367 }
1368
1369 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
1372 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374 {
1375 struct drm_device *dev = dev_priv->dev;
1376 int reg, i;
1377 u32 val;
1378 int cur_pipe;
1379
1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1385 "plane %c assertion failure, should be disabled but not\n",
1386 plane_name(pipe));
1387 return;
1388 }
1389
1390 /* Need to check both planes against the pipe */
1391 for_each_pipe(dev_priv, i) {
1392 reg = DSPCNTR(i);
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
1399 }
1400 }
1401
1402 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404 {
1405 struct drm_device *dev = dev_priv->dev;
1406 int reg, sprite;
1407 u32 val;
1408
1409 if (INTEL_INFO(dev)->gen >= 9) {
1410 for_each_sprite(dev_priv, pipe, sprite) {
1411 val = I915_READ(PLANE_CTL(pipe, sprite));
1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1415 }
1416 } else if (IS_VALLEYVIEW(dev)) {
1417 for_each_sprite(dev_priv, pipe, sprite) {
1418 reg = SPCNTR(pipe, sprite);
1419 val = I915_READ(reg);
1420 I915_STATE_WARN(val & SP_ENABLE,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 sprite_name(pipe, sprite), pipe_name(pipe));
1423 }
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1425 reg = SPRCTL(pipe);
1426 val = I915_READ(reg);
1427 I915_STATE_WARN(val & SPRITE_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
1432 val = I915_READ(reg);
1433 I915_STATE_WARN(val & DVS_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 }
1437 }
1438
1439 static void assert_vblank_disabled(struct drm_crtc *crtc)
1440 {
1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1442 drm_crtc_vblank_put(crtc);
1443 }
1444
1445 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446 {
1447 u32 val;
1448 bool enabled;
1449
1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1451
1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1456 }
1457
1458 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
1460 {
1461 int reg;
1462 u32 val;
1463 bool enabled;
1464
1465 reg = PCH_TRANSCONF(pipe);
1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
1468 I915_STATE_WARN(enabled,
1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470 pipe_name(pipe));
1471 }
1472
1473 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
1475 {
1476 if ((val & DP_PORT_EN) == 0)
1477 return false;
1478
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483 return false;
1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486 return false;
1487 } else {
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489 return false;
1490 }
1491 return true;
1492 }
1493
1494 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1496 {
1497 if ((val & SDVO_ENABLE) == 0)
1498 return false;
1499
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1502 return false;
1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505 return false;
1506 } else {
1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1508 return false;
1509 }
1510 return true;
1511 }
1512
1513 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1515 {
1516 if ((val & LVDS_PORT_EN) == 0)
1517 return false;
1518
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 return false;
1522 } else {
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524 return false;
1525 }
1526 return true;
1527 }
1528
1529 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1531 {
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1533 return false;
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536 return false;
1537 } else {
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539 return false;
1540 }
1541 return true;
1542 }
1543
1544 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, int reg, u32 port_sel)
1546 {
1547 u32 val = I915_READ(reg);
1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg, pipe_name(pipe));
1551
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1553 && (val & DP_PIPEB_SELECT),
1554 "IBX PCH dp port still using transcoder B\n");
1555 }
1556
1557 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1559 {
1560 u32 val = I915_READ(reg);
1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563 reg, pipe_name(pipe));
1564
1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1566 && (val & SDVO_PIPE_B_SELECT),
1567 "IBX PCH hdmi port still using transcoder B\n");
1568 }
1569
1570 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571 enum pipe pipe)
1572 {
1573 int reg;
1574 u32 val;
1575
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1579
1580 reg = PCH_ADPA;
1581 val = I915_READ(reg);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1584 pipe_name(pipe));
1585
1586 reg = PCH_LVDS;
1587 val = I915_READ(reg);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void intel_init_dpio(struct drm_device *dev)
1598 {
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 if (!IS_VALLEYVIEW(dev))
1602 return;
1603
1604 /*
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608 */
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612 } else {
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614 }
1615 }
1616
1617 static void vlv_enable_pll(struct intel_crtc *crtc,
1618 const struct intel_crtc_state *pipe_config)
1619 {
1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
1624
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630 /* PLL is protected by panel, make sure we can write it */
1631 if (IS_MOBILE(dev_priv->dev))
1632 assert_panel_unlocked(dev_priv, crtc->pipe);
1633
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1642 POSTING_READ(DPLL_MD(crtc->pipe));
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 }
1655
1656 static void chv_enable_pll(struct intel_crtc *crtc,
1657 const struct intel_crtc_state *pipe_config)
1658 {
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1663 u32 tmp;
1664
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
1669 mutex_lock(&dev_priv->sb_lock);
1670
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
1676 mutex_unlock(&dev_priv->sb_lock);
1677
1678 /*
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 */
1681 udelay(1);
1682
1683 /* Enable PLL */
1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1685
1686 /* Check PLL is locked */
1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
1690 /* not sure when this should be written */
1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1692 POSTING_READ(DPLL_MD(pipe));
1693 }
1694
1695 static int intel_num_dvo_pipes(struct drm_device *dev)
1696 {
1697 struct intel_crtc *crtc;
1698 int count = 0;
1699
1700 for_each_intel_crtc(dev, crtc)
1701 count += crtc->base.state->active &&
1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703
1704 return count;
1705 }
1706
1707 static void i9xx_enable_pll(struct intel_crtc *crtc)
1708 {
1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
1713
1714 assert_pipe_disabled(dev_priv, crtc->pipe);
1715
1716 /* No really, not for ILK+ */
1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1718
1719 /* PLL is protected by panel, make sure we can write it */
1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
1722
1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725 /*
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1730 */
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734 }
1735
1736 /* Wait for the clocks to stabilize. */
1737 POSTING_READ(reg);
1738 udelay(150);
1739
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
1742 crtc->config->dpll_hw_state.dpll_md);
1743 } else {
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1746 *
1747 * So write it again.
1748 */
1749 I915_WRITE(reg, dpll);
1750 }
1751
1752 /* We do this three times for luck */
1753 I915_WRITE(reg, dpll);
1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
1756 I915_WRITE(reg, dpll);
1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
1759 I915_WRITE(reg, dpll);
1760 POSTING_READ(reg);
1761 udelay(150); /* wait for warmup */
1762 }
1763
1764 /**
1765 * i9xx_disable_pll - disable a PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1768 *
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1770 *
1771 * Note! This is for pre-ILK only.
1772 */
1773 static void i9xx_disable_pll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1778
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1780 if (IS_I830(dev) &&
1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782 !intel_num_dvo_pipes(dev)) {
1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787 }
1788
1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1792 return;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
1799 }
1800
1801 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802 {
1803 u32 val = 0;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /*
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1811 */
1812 if (pipe == PIPE_B)
1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
1816
1817 }
1818
1819 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820 {
1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1822 u32 val;
1823
1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
1826
1827 /* Set PLL en = 0 */
1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1829 if (pipe != PIPE_A)
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
1833
1834 mutex_lock(&dev_priv->sb_lock);
1835
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846 } else {
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850 }
1851
1852 mutex_unlock(&dev_priv->sb_lock);
1853 }
1854
1855 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
1858 {
1859 u32 port_mask;
1860 int dpll_reg;
1861
1862 switch (dport->port) {
1863 case PORT_B:
1864 port_mask = DPLL_PORTB_READY_MASK;
1865 dpll_reg = DPLL(0);
1866 break;
1867 case PORT_C:
1868 port_mask = DPLL_PORTC_READY_MASK;
1869 dpll_reg = DPLL(0);
1870 expected_mask <<= 4;
1871 break;
1872 case PORT_D:
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
1875 break;
1876 default:
1877 BUG();
1878 }
1879
1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1883 }
1884
1885 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886 {
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
1891 if (WARN_ON(pll == NULL))
1892 return;
1893
1894 WARN_ON(!pll->config.crtc_mask);
1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897 WARN_ON(pll->on);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900 pll->mode_set(dev_priv, pll);
1901 }
1902 }
1903
1904 /**
1905 * intel_enable_shared_dpll - enable PCH PLL
1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1908 *
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1911 */
1912 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1913 {
1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1917
1918 if (WARN_ON(pll == NULL))
1919 return;
1920
1921 if (WARN_ON(pll->config.crtc_mask == 0))
1922 return;
1923
1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925 pll->name, pll->active, pll->on,
1926 crtc->base.base.id);
1927
1928 if (pll->active++) {
1929 WARN_ON(!pll->on);
1930 assert_shared_dpll_enabled(dev_priv, pll);
1931 return;
1932 }
1933 WARN_ON(pll->on);
1934
1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1938 pll->enable(dev_priv, pll);
1939 pll->on = true;
1940 }
1941
1942 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1943 {
1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1947
1948 /* PCH only available on ILK+ */
1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
1950 if (WARN_ON(pll == NULL))
1951 return;
1952
1953 if (WARN_ON(pll->config.crtc_mask == 0))
1954 return;
1955
1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
1958 crtc->base.base.id);
1959
1960 if (WARN_ON(pll->active == 0)) {
1961 assert_shared_dpll_disabled(dev_priv, pll);
1962 return;
1963 }
1964
1965 assert_shared_dpll_enabled(dev_priv, pll);
1966 WARN_ON(!pll->on);
1967 if (--pll->active)
1968 return;
1969
1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1971 pll->disable(dev_priv, pll);
1972 pll->on = false;
1973
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1975 }
1976
1977 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978 enum pipe pipe)
1979 {
1980 struct drm_device *dev = dev_priv->dev;
1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 uint32_t reg, val, pipeconf_val;
1984
1985 /* PCH only available on ILK+ */
1986 BUG_ON(!HAS_PCH_SPLIT(dev));
1987
1988 /* Make sure PCH DPLL is enabled */
1989 assert_shared_dpll_enabled(dev_priv,
1990 intel_crtc_to_shared_dpll(intel_crtc));
1991
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1995
1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
2003 }
2004
2005 reg = PCH_TRANSCONF(pipe);
2006 val = I915_READ(reg);
2007 pipeconf_val = I915_READ(PIPECONF(pipe));
2008
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2010 /*
2011 * Make the BPC in transcoder be consistent with
2012 * that in pipeconf reg. For HDMI we must use 8bpc
2013 * here for both 8bpc and 12bpc.
2014 */
2015 val &= ~PIPECONF_BPC_MASK;
2016 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2017 val |= PIPECONF_8BPC;
2018 else
2019 val |= pipeconf_val & PIPECONF_BPC_MASK;
2020 }
2021
2022 val &= ~TRANS_INTERLACE_MASK;
2023 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2024 if (HAS_PCH_IBX(dev_priv->dev) &&
2025 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2026 val |= TRANS_LEGACY_INTERLACED_ILK;
2027 else
2028 val |= TRANS_INTERLACED;
2029 else
2030 val |= TRANS_PROGRESSIVE;
2031
2032 I915_WRITE(reg, val | TRANS_ENABLE);
2033 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2034 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2035 }
2036
2037 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2038 enum transcoder cpu_transcoder)
2039 {
2040 u32 val, pipeconf_val;
2041
2042 /* PCH only available on ILK+ */
2043 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2044
2045 /* FDI must be feeding us bits for PCH ports */
2046 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2047 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2048
2049 /* Workaround: set timing override bit. */
2050 val = I915_READ(_TRANSA_CHICKEN2);
2051 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2052 I915_WRITE(_TRANSA_CHICKEN2, val);
2053
2054 val = TRANS_ENABLE;
2055 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2056
2057 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2058 PIPECONF_INTERLACED_ILK)
2059 val |= TRANS_INTERLACED;
2060 else
2061 val |= TRANS_PROGRESSIVE;
2062
2063 I915_WRITE(LPT_TRANSCONF, val);
2064 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2065 DRM_ERROR("Failed to enable PCH transcoder\n");
2066 }
2067
2068 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2069 enum pipe pipe)
2070 {
2071 struct drm_device *dev = dev_priv->dev;
2072 uint32_t reg, val;
2073
2074 /* FDI relies on the transcoder */
2075 assert_fdi_tx_disabled(dev_priv, pipe);
2076 assert_fdi_rx_disabled(dev_priv, pipe);
2077
2078 /* Ports must be off as well */
2079 assert_pch_ports_disabled(dev_priv, pipe);
2080
2081 reg = PCH_TRANSCONF(pipe);
2082 val = I915_READ(reg);
2083 val &= ~TRANS_ENABLE;
2084 I915_WRITE(reg, val);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2087 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2088
2089 if (!HAS_PCH_IBX(dev)) {
2090 /* Workaround: Clear the timing override chicken bit again. */
2091 reg = TRANS_CHICKEN2(pipe);
2092 val = I915_READ(reg);
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(reg, val);
2095 }
2096 }
2097
2098 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2099 {
2100 u32 val;
2101
2102 val = I915_READ(LPT_TRANSCONF);
2103 val &= ~TRANS_ENABLE;
2104 I915_WRITE(LPT_TRANSCONF, val);
2105 /* wait for PCH transcoder off, transcoder state */
2106 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2107 DRM_ERROR("Failed to disable PCH transcoder\n");
2108
2109 /* Workaround: clear timing override bit. */
2110 val = I915_READ(_TRANSA_CHICKEN2);
2111 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2112 I915_WRITE(_TRANSA_CHICKEN2, val);
2113 }
2114
2115 /**
2116 * intel_enable_pipe - enable a pipe, asserting requirements
2117 * @crtc: crtc responsible for the pipe
2118 *
2119 * Enable @crtc's pipe, making sure that various hardware specific requirements
2120 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2121 */
2122 static void intel_enable_pipe(struct intel_crtc *crtc)
2123 {
2124 struct drm_device *dev = crtc->base.dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 enum pipe pipe = crtc->pipe;
2127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2128 pipe);
2129 enum pipe pch_transcoder;
2130 int reg;
2131 u32 val;
2132
2133 assert_planes_disabled(dev_priv, pipe);
2134 assert_cursor_disabled(dev_priv, pipe);
2135 assert_sprites_disabled(dev_priv, pipe);
2136
2137 if (HAS_PCH_LPT(dev_priv->dev))
2138 pch_transcoder = TRANSCODER_A;
2139 else
2140 pch_transcoder = pipe;
2141
2142 /*
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 * need the check.
2146 */
2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2149 assert_dsi_pll_enabled(dev_priv);
2150 else
2151 assert_pll_enabled(dev_priv, pipe);
2152 else {
2153 if (crtc->config->has_pch_encoder) {
2154 /* if driving the PCH, we need FDI enabled */
2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
2158 }
2159 /* FIXME: assert CPU port conditions for SNB+ */
2160 }
2161
2162 reg = PIPECONF(cpu_transcoder);
2163 val = I915_READ(reg);
2164 if (val & PIPECONF_ENABLE) {
2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2167 return;
2168 }
2169
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
2171 POSTING_READ(reg);
2172 }
2173
2174 /**
2175 * intel_disable_pipe - disable a pipe, asserting requirements
2176 * @crtc: crtc whose pipes is to be disabled
2177 *
2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
2181 *
2182 * Will wait until the pipe has shut down before returning.
2183 */
2184 static void intel_disable_pipe(struct intel_crtc *crtc)
2185 {
2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2188 enum pipe pipe = crtc->pipe;
2189 int reg;
2190 u32 val;
2191
2192 /*
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2195 */
2196 assert_planes_disabled(dev_priv, pipe);
2197 assert_cursor_disabled(dev_priv, pipe);
2198 assert_sprites_disabled(dev_priv, pipe);
2199
2200 reg = PIPECONF(cpu_transcoder);
2201 val = I915_READ(reg);
2202 if ((val & PIPECONF_ENABLE) == 0)
2203 return;
2204
2205 /*
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2208 */
2209 if (crtc->config->double_wide)
2210 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212 /* Don't disable pipe or pipe PLLs if needed */
2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2215 val &= ~PIPECONF_ENABLE;
2216
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
2220 }
2221
2222 /**
2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
2226 *
2227 * Enable @plane on @crtc, making sure that the pipe is running first.
2228 */
2229 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
2231 {
2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2238 to_intel_plane_state(plane->state)->visible = true;
2239
2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2241 crtc->x, crtc->y);
2242 }
2243
2244 static bool need_vtd_wa(struct drm_device *dev)
2245 {
2246 #ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248 return true;
2249 #endif
2250 return false;
2251 }
2252
2253 unsigned int
2254 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
2256 {
2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
2259
2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2262 tile_height = 1;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2266 break;
2267 case I915_FORMAT_MOD_Y_TILED:
2268 tile_height = 32;
2269 break;
2270 case I915_FORMAT_MOD_Yf_TILED:
2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
2273 default:
2274 case 1:
2275 tile_height = 64;
2276 break;
2277 case 2:
2278 case 4:
2279 tile_height = 32;
2280 break;
2281 case 8:
2282 tile_height = 16;
2283 break;
2284 case 16:
2285 WARN_ONCE(1,
2286 "128-bit pixels are not supported for display!");
2287 tile_height = 16;
2288 break;
2289 }
2290 break;
2291 default:
2292 MISSING_CASE(fb_format_modifier);
2293 tile_height = 1;
2294 break;
2295 }
2296
2297 return tile_height;
2298 }
2299
2300 unsigned int
2301 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2303 {
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
2306 }
2307
2308 static int
2309 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2311 {
2312 struct intel_rotation_info *info = &view->rotation_info;
2313
2314 *view = i915_ggtt_view_normal;
2315
2316 if (!plane_state)
2317 return 0;
2318
2319 if (!intel_rotation_90_or_270(plane_state->rotation))
2320 return 0;
2321
2322 *view = i915_ggtt_view_rotated;
2323
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2328
2329 return 0;
2330 }
2331
2332 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2333 {
2334 if (INTEL_INFO(dev_priv)->gen >= 9)
2335 return 256 * 1024;
2336 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2337 IS_VALLEYVIEW(dev_priv))
2338 return 128 * 1024;
2339 else if (INTEL_INFO(dev_priv)->gen >= 4)
2340 return 4 * 1024;
2341 else
2342 return 0;
2343 }
2344
2345 int
2346 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2347 struct drm_framebuffer *fb,
2348 const struct drm_plane_state *plane_state,
2349 struct intel_engine_cs *pipelined)
2350 {
2351 struct drm_device *dev = fb->dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2354 struct i915_ggtt_view view;
2355 u32 alignment;
2356 int ret;
2357
2358 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2359
2360 switch (fb->modifier[0]) {
2361 case DRM_FORMAT_MOD_NONE:
2362 alignment = intel_linear_alignment(dev_priv);
2363 break;
2364 case I915_FORMAT_MOD_X_TILED:
2365 if (INTEL_INFO(dev)->gen >= 9)
2366 alignment = 256 * 1024;
2367 else {
2368 /* pin() will align the object as required by fence */
2369 alignment = 0;
2370 }
2371 break;
2372 case I915_FORMAT_MOD_Y_TILED:
2373 case I915_FORMAT_MOD_Yf_TILED:
2374 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2375 "Y tiling bo slipped through, driver bug!\n"))
2376 return -EINVAL;
2377 alignment = 1 * 1024 * 1024;
2378 break;
2379 default:
2380 MISSING_CASE(fb->modifier[0]);
2381 return -EINVAL;
2382 }
2383
2384 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2385 if (ret)
2386 return ret;
2387
2388 /* Note that the w/a also requires 64 PTE of padding following the
2389 * bo. We currently fill all unused PTE with the shadow page and so
2390 * we should always have valid PTE following the scanout preventing
2391 * the VT-d warning.
2392 */
2393 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2394 alignment = 256 * 1024;
2395
2396 /*
2397 * Global gtt pte registers are special registers which actually forward
2398 * writes to a chunk of system memory. Which means that there is no risk
2399 * that the register values disappear as soon as we call
2400 * intel_runtime_pm_put(), so it is correct to wrap only the
2401 * pin/unpin/fence and not more.
2402 */
2403 intel_runtime_pm_get(dev_priv);
2404
2405 dev_priv->mm.interruptible = false;
2406 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2407 &view);
2408 if (ret)
2409 goto err_interruptible;
2410
2411 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2412 * fence, whereas 965+ only requires a fence if using
2413 * framebuffer compression. For simplicity, we always install
2414 * a fence as the cost is not that onerous.
2415 */
2416 ret = i915_gem_object_get_fence(obj);
2417 if (ret)
2418 goto err_unpin;
2419
2420 i915_gem_object_pin_fence(obj);
2421
2422 dev_priv->mm.interruptible = true;
2423 intel_runtime_pm_put(dev_priv);
2424 return 0;
2425
2426 err_unpin:
2427 i915_gem_object_unpin_from_display_plane(obj, &view);
2428 err_interruptible:
2429 dev_priv->mm.interruptible = true;
2430 intel_runtime_pm_put(dev_priv);
2431 return ret;
2432 }
2433
2434 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2435 const struct drm_plane_state *plane_state)
2436 {
2437 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2438 struct i915_ggtt_view view;
2439 int ret;
2440
2441 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2442
2443 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2444 WARN_ONCE(ret, "Couldn't get view from plane state!");
2445
2446 i915_gem_object_unpin_fence(obj);
2447 i915_gem_object_unpin_from_display_plane(obj, &view);
2448 }
2449
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453 int *x, int *y,
2454 unsigned int tiling_mode,
2455 unsigned int cpp,
2456 unsigned int pitch)
2457 {
2458 if (tiling_mode != I915_TILING_NONE) {
2459 unsigned int tile_rows, tiles;
2460
2461 tile_rows = *y / 8;
2462 *y %= 8;
2463
2464 tiles = *x / (512/cpp);
2465 *x %= 512/cpp;
2466
2467 return tile_rows * pitch * 8 + tiles * 4096;
2468 } else {
2469 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470 unsigned int offset;
2471
2472 offset = *y * pitch + *x * cpp;
2473 *y = (offset & alignment) / pitch;
2474 *x = ((offset & alignment) - *y * pitch) / cpp;
2475 return offset & ~alignment;
2476 }
2477 }
2478
2479 static int i9xx_format_to_fourcc(int format)
2480 {
2481 switch (format) {
2482 case DISPPLANE_8BPP:
2483 return DRM_FORMAT_C8;
2484 case DISPPLANE_BGRX555:
2485 return DRM_FORMAT_XRGB1555;
2486 case DISPPLANE_BGRX565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case DISPPLANE_BGRX888:
2490 return DRM_FORMAT_XRGB8888;
2491 case DISPPLANE_RGBX888:
2492 return DRM_FORMAT_XBGR8888;
2493 case DISPPLANE_BGRX101010:
2494 return DRM_FORMAT_XRGB2101010;
2495 case DISPPLANE_RGBX101010:
2496 return DRM_FORMAT_XBGR2101010;
2497 }
2498 }
2499
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501 {
2502 switch (format) {
2503 case PLANE_CTL_FORMAT_RGB_565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case PLANE_CTL_FORMAT_XRGB_8888:
2507 if (rgb_order) {
2508 if (alpha)
2509 return DRM_FORMAT_ABGR8888;
2510 else
2511 return DRM_FORMAT_XBGR8888;
2512 } else {
2513 if (alpha)
2514 return DRM_FORMAT_ARGB8888;
2515 else
2516 return DRM_FORMAT_XRGB8888;
2517 }
2518 case PLANE_CTL_FORMAT_XRGB_2101010:
2519 if (rgb_order)
2520 return DRM_FORMAT_XBGR2101010;
2521 else
2522 return DRM_FORMAT_XRGB2101010;
2523 }
2524 }
2525
2526 static bool
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528 struct intel_initial_plane_config *plane_config)
2529 {
2530 struct drm_device *dev = crtc->base.dev;
2531 struct drm_i915_gem_object *obj = NULL;
2532 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2533 struct drm_framebuffer *fb = &plane_config->fb->base;
2534 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2535 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2536 PAGE_SIZE);
2537
2538 size_aligned -= base_aligned;
2539
2540 if (plane_config->size == 0)
2541 return false;
2542
2543 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2544 base_aligned,
2545 base_aligned,
2546 size_aligned);
2547 if (!obj)
2548 return false;
2549
2550 obj->tiling_mode = plane_config->tiling;
2551 if (obj->tiling_mode == I915_TILING_X)
2552 obj->stride = fb->pitches[0];
2553
2554 mode_cmd.pixel_format = fb->pixel_format;
2555 mode_cmd.width = fb->width;
2556 mode_cmd.height = fb->height;
2557 mode_cmd.pitches[0] = fb->pitches[0];
2558 mode_cmd.modifier[0] = fb->modifier[0];
2559 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2560
2561 mutex_lock(&dev->struct_mutex);
2562 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2563 &mode_cmd, obj)) {
2564 DRM_DEBUG_KMS("intel fb init failed\n");
2565 goto out_unref_obj;
2566 }
2567 mutex_unlock(&dev->struct_mutex);
2568
2569 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2570 return true;
2571
2572 out_unref_obj:
2573 drm_gem_object_unreference(&obj->base);
2574 mutex_unlock(&dev->struct_mutex);
2575 return false;
2576 }
2577
2578 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2579 static void
2580 update_state_fb(struct drm_plane *plane)
2581 {
2582 if (plane->fb == plane->state->fb)
2583 return;
2584
2585 if (plane->state->fb)
2586 drm_framebuffer_unreference(plane->state->fb);
2587 plane->state->fb = plane->fb;
2588 if (plane->state->fb)
2589 drm_framebuffer_reference(plane->state->fb);
2590 }
2591
2592 static void
2593 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2594 struct intel_initial_plane_config *plane_config)
2595 {
2596 struct drm_device *dev = intel_crtc->base.dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct drm_crtc *c;
2599 struct intel_crtc *i;
2600 struct drm_i915_gem_object *obj;
2601 struct drm_plane *primary = intel_crtc->base.primary;
2602 struct drm_framebuffer *fb;
2603
2604 if (!plane_config->fb)
2605 return;
2606
2607 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608 fb = &plane_config->fb->base;
2609 goto valid_fb;
2610 }
2611
2612 kfree(plane_config->fb);
2613
2614 /*
2615 * Failed to alloc the obj, check to see if we should share
2616 * an fb with another CRTC instead
2617 */
2618 for_each_crtc(dev, c) {
2619 i = to_intel_crtc(c);
2620
2621 if (c == &intel_crtc->base)
2622 continue;
2623
2624 if (!i->active)
2625 continue;
2626
2627 fb = c->primary->fb;
2628 if (!fb)
2629 continue;
2630
2631 obj = intel_fb_obj(fb);
2632 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633 drm_framebuffer_reference(fb);
2634 goto valid_fb;
2635 }
2636 }
2637
2638 return;
2639
2640 valid_fb:
2641 obj = intel_fb_obj(fb);
2642 if (obj->tiling_mode != I915_TILING_NONE)
2643 dev_priv->preserve_bios_swizzle = true;
2644
2645 primary->fb = fb;
2646 primary->crtc = primary->state->crtc = &intel_crtc->base;
2647 update_state_fb(primary);
2648 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2649 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2650 }
2651
2652 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653 struct drm_framebuffer *fb,
2654 int x, int y)
2655 {
2656 struct drm_device *dev = crtc->dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2659 struct drm_plane *primary = crtc->primary;
2660 bool visible = to_intel_plane_state(primary->state)->visible;
2661 struct drm_i915_gem_object *obj;
2662 int plane = intel_crtc->plane;
2663 unsigned long linear_offset;
2664 u32 dspcntr;
2665 u32 reg = DSPCNTR(plane);
2666 int pixel_size;
2667
2668 if (!visible || !fb) {
2669 I915_WRITE(reg, 0);
2670 if (INTEL_INFO(dev)->gen >= 4)
2671 I915_WRITE(DSPSURF(plane), 0);
2672 else
2673 I915_WRITE(DSPADDR(plane), 0);
2674 POSTING_READ(reg);
2675 return;
2676 }
2677
2678 obj = intel_fb_obj(fb);
2679 if (WARN_ON(obj == NULL))
2680 return;
2681
2682 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
2684 dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
2686 dspcntr |= DISPLAY_PLANE_ENABLE;
2687
2688 if (INTEL_INFO(dev)->gen < 4) {
2689 if (intel_crtc->pipe == PIPE_B)
2690 dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2694 */
2695 I915_WRITE(DSPSIZE(plane),
2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
2698 I915_WRITE(DSPPOS(plane), 0);
2699 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700 I915_WRITE(PRIMSIZE(plane),
2701 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702 (intel_crtc->config->pipe_src_w - 1));
2703 I915_WRITE(PRIMPOS(plane), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2705 }
2706
2707 switch (fb->pixel_format) {
2708 case DRM_FORMAT_C8:
2709 dspcntr |= DISPPLANE_8BPP;
2710 break;
2711 case DRM_FORMAT_XRGB1555:
2712 dspcntr |= DISPPLANE_BGRX555;
2713 break;
2714 case DRM_FORMAT_RGB565:
2715 dspcntr |= DISPPLANE_BGRX565;
2716 break;
2717 case DRM_FORMAT_XRGB8888:
2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
2721 dspcntr |= DISPPLANE_RGBX888;
2722 break;
2723 case DRM_FORMAT_XRGB2101010:
2724 dspcntr |= DISPPLANE_BGRX101010;
2725 break;
2726 case DRM_FORMAT_XBGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
2736
2737 if (IS_G4X(dev))
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
2741
2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
2744 intel_gen4_compute_page_offset(dev_priv,
2745 &x, &y, obj->tiling_mode,
2746 pixel_size,
2747 fb->pitches[0]);
2748 linear_offset -= intel_crtc->dspaddr_offset;
2749 } else {
2750 intel_crtc->dspaddr_offset = linear_offset;
2751 }
2752
2753 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2754 dspcntr |= DISPPLANE_ROTATE_180;
2755
2756 x += (intel_crtc->config->pipe_src_w - 1);
2757 y += (intel_crtc->config->pipe_src_h - 1);
2758
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2761 linear_offset +=
2762 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2764 }
2765
2766 I915_WRITE(reg, dspcntr);
2767
2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769 if (INTEL_INFO(dev)->gen >= 4) {
2770 I915_WRITE(DSPSURF(plane),
2771 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2772 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2773 I915_WRITE(DSPLINOFF(plane), linear_offset);
2774 } else
2775 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2776 POSTING_READ(reg);
2777 }
2778
2779 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2781 int x, int y)
2782 {
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786 struct drm_plane *primary = crtc->primary;
2787 bool visible = to_intel_plane_state(primary->state)->visible;
2788 struct drm_i915_gem_object *obj;
2789 int plane = intel_crtc->plane;
2790 unsigned long linear_offset;
2791 u32 dspcntr;
2792 u32 reg = DSPCNTR(plane);
2793 int pixel_size;
2794
2795 if (!visible || !fb) {
2796 I915_WRITE(reg, 0);
2797 I915_WRITE(DSPSURF(plane), 0);
2798 POSTING_READ(reg);
2799 return;
2800 }
2801
2802 obj = intel_fb_obj(fb);
2803 if (WARN_ON(obj == NULL))
2804 return;
2805
2806 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2807
2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2809
2810 dspcntr |= DISPLAY_PLANE_ENABLE;
2811
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2814
2815 switch (fb->pixel_format) {
2816 case DRM_FORMAT_C8:
2817 dspcntr |= DISPPLANE_8BPP;
2818 break;
2819 case DRM_FORMAT_RGB565:
2820 dspcntr |= DISPPLANE_BGRX565;
2821 break;
2822 case DRM_FORMAT_XRGB8888:
2823 dspcntr |= DISPPLANE_BGRX888;
2824 break;
2825 case DRM_FORMAT_XBGR8888:
2826 dspcntr |= DISPPLANE_RGBX888;
2827 break;
2828 case DRM_FORMAT_XRGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 dspcntr |= DISPPLANE_RGBX101010;
2833 break;
2834 default:
2835 BUG();
2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
2840
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2843
2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
2845 intel_crtc->dspaddr_offset =
2846 intel_gen4_compute_page_offset(dev_priv,
2847 &x, &y, obj->tiling_mode,
2848 pixel_size,
2849 fb->pitches[0]);
2850 linear_offset -= intel_crtc->dspaddr_offset;
2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
2867
2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
2877 POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882 {
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912 }
2913
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916 {
2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920 view = &i915_ggtt_view_rotated;
2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923 }
2924
2925 /*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929 {
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 dev = intel_crtc->base.dev;
2936 dev_priv = dev->dev_private;
2937 scaler_state = &intel_crtc->config->scaler_state;
2938
2939 /* loop through and disable scalers that aren't in use */
2940 for (i = 0; i < intel_crtc->num_scalers; i++) {
2941 if (!scaler_state->scalers[i].in_use) {
2942 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2943 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2944 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2945 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2946 intel_crtc->base.base.id, intel_crtc->pipe, i);
2947 }
2948 }
2949 }
2950
2951 u32 skl_plane_ctl_format(uint32_t pixel_format)
2952 {
2953 switch (pixel_format) {
2954 case DRM_FORMAT_C8:
2955 return PLANE_CTL_FORMAT_INDEXED;
2956 case DRM_FORMAT_RGB565:
2957 return PLANE_CTL_FORMAT_RGB_565;
2958 case DRM_FORMAT_XBGR8888:
2959 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2960 case DRM_FORMAT_XRGB8888:
2961 return PLANE_CTL_FORMAT_XRGB_8888;
2962 /*
2963 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2964 * to be already pre-multiplied. We need to add a knob (or a different
2965 * DRM_FORMAT) for user-space to configure that.
2966 */
2967 case DRM_FORMAT_ABGR8888:
2968 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2969 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2970 case DRM_FORMAT_ARGB8888:
2971 return PLANE_CTL_FORMAT_XRGB_8888 |
2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2973 case DRM_FORMAT_XRGB2101010:
2974 return PLANE_CTL_FORMAT_XRGB_2101010;
2975 case DRM_FORMAT_XBGR2101010:
2976 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2977 case DRM_FORMAT_YUYV:
2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2979 case DRM_FORMAT_YVYU:
2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2981 case DRM_FORMAT_UYVY:
2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2983 case DRM_FORMAT_VYUY:
2984 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2985 default:
2986 MISSING_CASE(pixel_format);
2987 }
2988
2989 return 0;
2990 }
2991
2992 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2993 {
2994 switch (fb_modifier) {
2995 case DRM_FORMAT_MOD_NONE:
2996 break;
2997 case I915_FORMAT_MOD_X_TILED:
2998 return PLANE_CTL_TILED_X;
2999 case I915_FORMAT_MOD_Y_TILED:
3000 return PLANE_CTL_TILED_Y;
3001 case I915_FORMAT_MOD_Yf_TILED:
3002 return PLANE_CTL_TILED_YF;
3003 default:
3004 MISSING_CASE(fb_modifier);
3005 }
3006
3007 return 0;
3008 }
3009
3010 u32 skl_plane_ctl_rotation(unsigned int rotation)
3011 {
3012 switch (rotation) {
3013 case BIT(DRM_ROTATE_0):
3014 break;
3015 /*
3016 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3017 * while i915 HW rotation is clockwise, thats why this swapping.
3018 */
3019 case BIT(DRM_ROTATE_90):
3020 return PLANE_CTL_ROTATE_270;
3021 case BIT(DRM_ROTATE_180):
3022 return PLANE_CTL_ROTATE_180;
3023 case BIT(DRM_ROTATE_270):
3024 return PLANE_CTL_ROTATE_90;
3025 default:
3026 MISSING_CASE(rotation);
3027 }
3028
3029 return 0;
3030 }
3031
3032 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3033 struct drm_framebuffer *fb,
3034 int x, int y)
3035 {
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 struct drm_plane *plane = crtc->primary;
3040 bool visible = to_intel_plane_state(plane->state)->visible;
3041 struct drm_i915_gem_object *obj;
3042 int pipe = intel_crtc->pipe;
3043 u32 plane_ctl, stride_div, stride;
3044 u32 tile_height, plane_offset, plane_size;
3045 unsigned int rotation;
3046 int x_offset, y_offset;
3047 unsigned long surf_addr;
3048 struct intel_crtc_state *crtc_state = intel_crtc->config;
3049 struct intel_plane_state *plane_state;
3050 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3051 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3052 int scaler_id = -1;
3053
3054 plane_state = to_intel_plane_state(plane->state);
3055
3056 if (!visible || !fb) {
3057 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3058 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3059 POSTING_READ(PLANE_CTL(pipe, 0));
3060 return;
3061 }
3062
3063 plane_ctl = PLANE_CTL_ENABLE |
3064 PLANE_CTL_PIPE_GAMMA_ENABLE |
3065 PLANE_CTL_PIPE_CSC_ENABLE;
3066
3067 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3068 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3069 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3070
3071 rotation = plane->state->rotation;
3072 plane_ctl |= skl_plane_ctl_rotation(rotation);
3073
3074 obj = intel_fb_obj(fb);
3075 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3076 fb->pixel_format);
3077 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3078
3079 /*
3080 * FIXME: intel_plane_state->src, dst aren't set when transitional
3081 * update_plane helpers are called from legacy paths.
3082 * Once full atomic crtc is available, below check can be avoided.
3083 */
3084 if (drm_rect_width(&plane_state->src)) {
3085 scaler_id = plane_state->scaler_id;
3086 src_x = plane_state->src.x1 >> 16;
3087 src_y = plane_state->src.y1 >> 16;
3088 src_w = drm_rect_width(&plane_state->src) >> 16;
3089 src_h = drm_rect_height(&plane_state->src) >> 16;
3090 dst_x = plane_state->dst.x1;
3091 dst_y = plane_state->dst.y1;
3092 dst_w = drm_rect_width(&plane_state->dst);
3093 dst_h = drm_rect_height(&plane_state->dst);
3094
3095 WARN_ON(x != src_x || y != src_y);
3096 } else {
3097 src_w = intel_crtc->config->pipe_src_w;
3098 src_h = intel_crtc->config->pipe_src_h;
3099 }
3100
3101 if (intel_rotation_90_or_270(rotation)) {
3102 /* stride = Surface height in tiles */
3103 tile_height = intel_tile_height(dev, fb->pixel_format,
3104 fb->modifier[0]);
3105 stride = DIV_ROUND_UP(fb->height, tile_height);
3106 x_offset = stride * tile_height - y - src_h;
3107 y_offset = x;
3108 plane_size = (src_w - 1) << 16 | (src_h - 1);
3109 } else {
3110 stride = fb->pitches[0] / stride_div;
3111 x_offset = x;
3112 y_offset = y;
3113 plane_size = (src_h - 1) << 16 | (src_w - 1);
3114 }
3115 plane_offset = y_offset << 16 | x_offset;
3116
3117 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3118 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3119 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3120 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3121
3122 if (scaler_id >= 0) {
3123 uint32_t ps_ctrl = 0;
3124
3125 WARN_ON(!dst_w || !dst_h);
3126 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3127 crtc_state->scaler_state.scalers[scaler_id].mode;
3128 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3129 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3130 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3131 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3132 I915_WRITE(PLANE_POS(pipe, 0), 0);
3133 } else {
3134 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3135 }
3136
3137 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3138
3139 POSTING_READ(PLANE_SURF(pipe, 0));
3140 }
3141
3142 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3143 static int
3144 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3145 int x, int y, enum mode_set_atomic state)
3146 {
3147 struct drm_device *dev = crtc->dev;
3148 struct drm_i915_private *dev_priv = dev->dev_private;
3149
3150 if (dev_priv->display.disable_fbc)
3151 dev_priv->display.disable_fbc(dev);
3152
3153 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3154
3155 return 0;
3156 }
3157
3158 static void intel_complete_page_flips(struct drm_device *dev)
3159 {
3160 struct drm_crtc *crtc;
3161
3162 for_each_crtc(dev, crtc) {
3163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3164 enum plane plane = intel_crtc->plane;
3165
3166 intel_prepare_page_flip(dev, plane);
3167 intel_finish_page_flip_plane(dev, plane);
3168 }
3169 }
3170
3171 static void intel_update_primary_planes(struct drm_device *dev)
3172 {
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 struct drm_crtc *crtc;
3175
3176 for_each_crtc(dev, crtc) {
3177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3178
3179 drm_modeset_lock(&crtc->mutex, NULL);
3180 /*
3181 * FIXME: Once we have proper support for primary planes (and
3182 * disabling them without disabling the entire crtc) allow again
3183 * a NULL crtc->primary->fb.
3184 */
3185 if (intel_crtc->active && crtc->primary->fb)
3186 dev_priv->display.update_primary_plane(crtc,
3187 crtc->primary->fb,
3188 crtc->x,
3189 crtc->y);
3190 drm_modeset_unlock(&crtc->mutex);
3191 }
3192 }
3193
3194 void intel_prepare_reset(struct drm_device *dev)
3195 {
3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
3205 /*
3206 * Disabling the crtcs gracefully seems nicer. Also the
3207 * g33 docs say we should at least disable all the planes.
3208 */
3209 intel_display_suspend(dev);
3210 }
3211
3212 void intel_finish_reset(struct drm_device *dev)
3213 {
3214 struct drm_i915_private *dev_priv = to_i915(dev);
3215
3216 /*
3217 * Flips in the rings will be nuked by the reset,
3218 * so complete all pending flips so that user space
3219 * will get its events and not get stuck.
3220 */
3221 intel_complete_page_flips(dev);
3222
3223 /* no reset support for gen2 */
3224 if (IS_GEN2(dev))
3225 return;
3226
3227 /* reset doesn't touch the display */
3228 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3229 /*
3230 * Flips in the rings have been nuked by the reset,
3231 * so update the base address of all primary
3232 * planes to the the last fb to make sure we're
3233 * showing the correct fb after a reset.
3234 */
3235 intel_update_primary_planes(dev);
3236 return;
3237 }
3238
3239 /*
3240 * The display has been reset as well,
3241 * so need a full re-initialization.
3242 */
3243 intel_runtime_pm_disable_interrupts(dev_priv);
3244 intel_runtime_pm_enable_interrupts(dev_priv);
3245
3246 intel_modeset_init_hw(dev);
3247
3248 spin_lock_irq(&dev_priv->irq_lock);
3249 if (dev_priv->display.hpd_irq_setup)
3250 dev_priv->display.hpd_irq_setup(dev);
3251 spin_unlock_irq(&dev_priv->irq_lock);
3252
3253 intel_modeset_setup_hw_state(dev, true);
3254
3255 intel_hpd_init(dev_priv);
3256
3257 drm_modeset_unlock_all(dev);
3258 }
3259
3260 static void
3261 intel_finish_fb(struct drm_framebuffer *old_fb)
3262 {
3263 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3264 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3265 bool was_interruptible = dev_priv->mm.interruptible;
3266 int ret;
3267
3268 /* Big Hammer, we also need to ensure that any pending
3269 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3270 * current scanout is retired before unpinning the old
3271 * framebuffer. Note that we rely on userspace rendering
3272 * into the buffer attached to the pipe they are waiting
3273 * on. If not, userspace generates a GPU hang with IPEHR
3274 * point to the MI_WAIT_FOR_EVENT.
3275 *
3276 * This should only fail upon a hung GPU, in which case we
3277 * can safely continue.
3278 */
3279 dev_priv->mm.interruptible = false;
3280 ret = i915_gem_object_wait_rendering(obj, true);
3281 dev_priv->mm.interruptible = was_interruptible;
3282
3283 WARN_ON(ret);
3284 }
3285
3286 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3287 {
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291 bool pending;
3292
3293 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3294 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3295 return false;
3296
3297 spin_lock_irq(&dev->event_lock);
3298 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3299 spin_unlock_irq(&dev->event_lock);
3300
3301 return pending;
3302 }
3303
3304 static void intel_update_pipe_size(struct intel_crtc *crtc)
3305 {
3306 struct drm_device *dev = crtc->base.dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 const struct drm_display_mode *adjusted_mode;
3309
3310 if (!i915.fastboot)
3311 return;
3312
3313 /*
3314 * Update pipe size and adjust fitter if needed: the reason for this is
3315 * that in compute_mode_changes we check the native mode (not the pfit
3316 * mode) to see if we can flip rather than do a full mode set. In the
3317 * fastboot case, we'll flip, but if we don't update the pipesrc and
3318 * pfit state, we'll end up with a big fb scanned out into the wrong
3319 * sized surface.
3320 *
3321 * To fix this properly, we need to hoist the checks up into
3322 * compute_mode_changes (or above), check the actual pfit state and
3323 * whether the platform allows pfit disable with pipe active, and only
3324 * then update the pipesrc and pfit state, even on the flip path.
3325 */
3326
3327 adjusted_mode = &crtc->config->base.adjusted_mode;
3328
3329 I915_WRITE(PIPESRC(crtc->pipe),
3330 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3331 (adjusted_mode->crtc_vdisplay - 1));
3332 if (!crtc->config->pch_pfit.enabled &&
3333 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3334 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3335 I915_WRITE(PF_CTL(crtc->pipe), 0);
3336 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3337 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3338 }
3339 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3340 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3341 }
3342
3343 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3344 {
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 int pipe = intel_crtc->pipe;
3349 u32 reg, temp;
3350
3351 /* enable normal train */
3352 reg = FDI_TX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 if (IS_IVYBRIDGE(dev)) {
3355 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3356 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3357 } else {
3358 temp &= ~FDI_LINK_TRAIN_NONE;
3359 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3360 }
3361 I915_WRITE(reg, temp);
3362
3363 reg = FDI_RX_CTL(pipe);
3364 temp = I915_READ(reg);
3365 if (HAS_PCH_CPT(dev)) {
3366 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3367 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3368 } else {
3369 temp &= ~FDI_LINK_TRAIN_NONE;
3370 temp |= FDI_LINK_TRAIN_NONE;
3371 }
3372 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3373
3374 /* wait one idle pattern time */
3375 POSTING_READ(reg);
3376 udelay(1000);
3377
3378 /* IVB wants error correction enabled */
3379 if (IS_IVYBRIDGE(dev))
3380 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3381 FDI_FE_ERRC_ENABLE);
3382 }
3383
3384 /* The FDI link training functions for ILK/Ibexpeak. */
3385 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3386 {
3387 struct drm_device *dev = crtc->dev;
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3390 int pipe = intel_crtc->pipe;
3391 u32 reg, temp, tries;
3392
3393 /* FDI needs bits from pipe first */
3394 assert_pipe_enabled(dev_priv, pipe);
3395
3396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3397 for train result */
3398 reg = FDI_RX_IMR(pipe);
3399 temp = I915_READ(reg);
3400 temp &= ~FDI_RX_SYMBOL_LOCK;
3401 temp &= ~FDI_RX_BIT_LOCK;
3402 I915_WRITE(reg, temp);
3403 I915_READ(reg);
3404 udelay(150);
3405
3406 /* enable CPU FDI TX and PCH FDI RX */
3407 reg = FDI_TX_CTL(pipe);
3408 temp = I915_READ(reg);
3409 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3410 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3411 temp &= ~FDI_LINK_TRAIN_NONE;
3412 temp |= FDI_LINK_TRAIN_PATTERN_1;
3413 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3414
3415 reg = FDI_RX_CTL(pipe);
3416 temp = I915_READ(reg);
3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3420
3421 POSTING_READ(reg);
3422 udelay(150);
3423
3424 /* Ironlake workaround, enable clock pointer after FDI enable*/
3425 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3426 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3427 FDI_RX_PHASE_SYNC_POINTER_EN);
3428
3429 reg = FDI_RX_IIR(pipe);
3430 for (tries = 0; tries < 5; tries++) {
3431 temp = I915_READ(reg);
3432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3433
3434 if ((temp & FDI_RX_BIT_LOCK)) {
3435 DRM_DEBUG_KMS("FDI train 1 done.\n");
3436 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3437 break;
3438 }
3439 }
3440 if (tries == 5)
3441 DRM_ERROR("FDI train 1 fail!\n");
3442
3443 /* Train 2 */
3444 reg = FDI_TX_CTL(pipe);
3445 temp = I915_READ(reg);
3446 temp &= ~FDI_LINK_TRAIN_NONE;
3447 temp |= FDI_LINK_TRAIN_PATTERN_2;
3448 I915_WRITE(reg, temp);
3449
3450 reg = FDI_RX_CTL(pipe);
3451 temp = I915_READ(reg);
3452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_2;
3454 I915_WRITE(reg, temp);
3455
3456 POSTING_READ(reg);
3457 udelay(150);
3458
3459 reg = FDI_RX_IIR(pipe);
3460 for (tries = 0; tries < 5; tries++) {
3461 temp = I915_READ(reg);
3462 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3463
3464 if (temp & FDI_RX_SYMBOL_LOCK) {
3465 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3466 DRM_DEBUG_KMS("FDI train 2 done.\n");
3467 break;
3468 }
3469 }
3470 if (tries == 5)
3471 DRM_ERROR("FDI train 2 fail!\n");
3472
3473 DRM_DEBUG_KMS("FDI train done\n");
3474
3475 }
3476
3477 static const int snb_b_fdi_train_param[] = {
3478 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3479 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3480 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3481 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3482 };
3483
3484 /* The FDI link training functions for SNB/Cougarpoint. */
3485 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3486 {
3487 struct drm_device *dev = crtc->dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490 int pipe = intel_crtc->pipe;
3491 u32 reg, temp, i, retry;
3492
3493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3494 for train result */
3495 reg = FDI_RX_IMR(pipe);
3496 temp = I915_READ(reg);
3497 temp &= ~FDI_RX_SYMBOL_LOCK;
3498 temp &= ~FDI_RX_BIT_LOCK;
3499 I915_WRITE(reg, temp);
3500
3501 POSTING_READ(reg);
3502 udelay(150);
3503
3504 /* enable CPU FDI TX and PCH FDI RX */
3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3508 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3509 temp &= ~FDI_LINK_TRAIN_NONE;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1;
3511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3512 /* SNB-B */
3513 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3514 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3515
3516 I915_WRITE(FDI_RX_MISC(pipe),
3517 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3518
3519 reg = FDI_RX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 if (HAS_PCH_CPT(dev)) {
3522 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3523 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3524 } else {
3525 temp &= ~FDI_LINK_TRAIN_NONE;
3526 temp |= FDI_LINK_TRAIN_PATTERN_1;
3527 }
3528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3529
3530 POSTING_READ(reg);
3531 udelay(150);
3532
3533 for (i = 0; i < 4; i++) {
3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3537 temp |= snb_b_fdi_train_param[i];
3538 I915_WRITE(reg, temp);
3539
3540 POSTING_READ(reg);
3541 udelay(500);
3542
3543 for (retry = 0; retry < 5; retry++) {
3544 reg = FDI_RX_IIR(pipe);
3545 temp = I915_READ(reg);
3546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3547 if (temp & FDI_RX_BIT_LOCK) {
3548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3549 DRM_DEBUG_KMS("FDI train 1 done.\n");
3550 break;
3551 }
3552 udelay(50);
3553 }
3554 if (retry < 5)
3555 break;
3556 }
3557 if (i == 4)
3558 DRM_ERROR("FDI train 1 fail!\n");
3559
3560 /* Train 2 */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp &= ~FDI_LINK_TRAIN_NONE;
3564 temp |= FDI_LINK_TRAIN_PATTERN_2;
3565 if (IS_GEN6(dev)) {
3566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3567 /* SNB-B */
3568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3569 }
3570 I915_WRITE(reg, temp);
3571
3572 reg = FDI_RX_CTL(pipe);
3573 temp = I915_READ(reg);
3574 if (HAS_PCH_CPT(dev)) {
3575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3576 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3577 } else {
3578 temp &= ~FDI_LINK_TRAIN_NONE;
3579 temp |= FDI_LINK_TRAIN_PATTERN_2;
3580 }
3581 I915_WRITE(reg, temp);
3582
3583 POSTING_READ(reg);
3584 udelay(150);
3585
3586 for (i = 0; i < 4; i++) {
3587 reg = FDI_TX_CTL(pipe);
3588 temp = I915_READ(reg);
3589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3590 temp |= snb_b_fdi_train_param[i];
3591 I915_WRITE(reg, temp);
3592
3593 POSTING_READ(reg);
3594 udelay(500);
3595
3596 for (retry = 0; retry < 5; retry++) {
3597 reg = FDI_RX_IIR(pipe);
3598 temp = I915_READ(reg);
3599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3600 if (temp & FDI_RX_SYMBOL_LOCK) {
3601 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3602 DRM_DEBUG_KMS("FDI train 2 done.\n");
3603 break;
3604 }
3605 udelay(50);
3606 }
3607 if (retry < 5)
3608 break;
3609 }
3610 if (i == 4)
3611 DRM_ERROR("FDI train 2 fail!\n");
3612
3613 DRM_DEBUG_KMS("FDI train done.\n");
3614 }
3615
3616 /* Manual link training for Ivy Bridge A0 parts */
3617 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3618 {
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 int pipe = intel_crtc->pipe;
3623 u32 reg, temp, i, j;
3624
3625 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3626 for train result */
3627 reg = FDI_RX_IMR(pipe);
3628 temp = I915_READ(reg);
3629 temp &= ~FDI_RX_SYMBOL_LOCK;
3630 temp &= ~FDI_RX_BIT_LOCK;
3631 I915_WRITE(reg, temp);
3632
3633 POSTING_READ(reg);
3634 udelay(150);
3635
3636 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3637 I915_READ(FDI_RX_IIR(pipe)));
3638
3639 /* Try each vswing and preemphasis setting twice before moving on */
3640 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3641 /* disable first in case we need to retry */
3642 reg = FDI_TX_CTL(pipe);
3643 temp = I915_READ(reg);
3644 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3645 temp &= ~FDI_TX_ENABLE;
3646 I915_WRITE(reg, temp);
3647
3648 reg = FDI_RX_CTL(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_LINK_TRAIN_AUTO;
3651 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3652 temp &= ~FDI_RX_ENABLE;
3653 I915_WRITE(reg, temp);
3654
3655 /* enable CPU FDI TX and PCH FDI RX */
3656 reg = FDI_TX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3659 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3662 temp |= snb_b_fdi_train_param[j/2];
3663 temp |= FDI_COMPOSITE_SYNC;
3664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3665
3666 I915_WRITE(FDI_RX_MISC(pipe),
3667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3668
3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3674
3675 POSTING_READ(reg);
3676 udelay(1); /* should be 0.5us */
3677
3678 for (i = 0; i < 4; i++) {
3679 reg = FDI_RX_IIR(pipe);
3680 temp = I915_READ(reg);
3681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3682
3683 if (temp & FDI_RX_BIT_LOCK ||
3684 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3685 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3686 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3687 i);
3688 break;
3689 }
3690 udelay(1); /* should be 0.5us */
3691 }
3692 if (i == 4) {
3693 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3694 continue;
3695 }
3696
3697 /* Train 2 */
3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3701 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3702 I915_WRITE(reg, temp);
3703
3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3707 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3708 I915_WRITE(reg, temp);
3709
3710 POSTING_READ(reg);
3711 udelay(2); /* should be 1.5us */
3712
3713 for (i = 0; i < 4; i++) {
3714 reg = FDI_RX_IIR(pipe);
3715 temp = I915_READ(reg);
3716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3717
3718 if (temp & FDI_RX_SYMBOL_LOCK ||
3719 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3720 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3721 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3722 i);
3723 goto train_done;
3724 }
3725 udelay(2); /* should be 1.5us */
3726 }
3727 if (i == 4)
3728 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3729 }
3730
3731 train_done:
3732 DRM_DEBUG_KMS("FDI train done.\n");
3733 }
3734
3735 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3736 {
3737 struct drm_device *dev = intel_crtc->base.dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 int pipe = intel_crtc->pipe;
3740 u32 reg, temp;
3741
3742
3743 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3744 reg = FDI_RX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3747 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3749 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3750
3751 POSTING_READ(reg);
3752 udelay(200);
3753
3754 /* Switch from Rawclk to PCDclk */
3755 temp = I915_READ(reg);
3756 I915_WRITE(reg, temp | FDI_PCDCLK);
3757
3758 POSTING_READ(reg);
3759 udelay(200);
3760
3761 /* Enable CPU FDI TX PLL, always on for Ironlake */
3762 reg = FDI_TX_CTL(pipe);
3763 temp = I915_READ(reg);
3764 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3765 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3766
3767 POSTING_READ(reg);
3768 udelay(100);
3769 }
3770 }
3771
3772 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3773 {
3774 struct drm_device *dev = intel_crtc->base.dev;
3775 struct drm_i915_private *dev_priv = dev->dev_private;
3776 int pipe = intel_crtc->pipe;
3777 u32 reg, temp;
3778
3779 /* Switch from PCDclk to Rawclk */
3780 reg = FDI_RX_CTL(pipe);
3781 temp = I915_READ(reg);
3782 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3783
3784 /* Disable CPU FDI TX PLL */
3785 reg = FDI_TX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3788
3789 POSTING_READ(reg);
3790 udelay(100);
3791
3792 reg = FDI_RX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3795
3796 /* Wait for the clocks to turn off. */
3797 POSTING_READ(reg);
3798 udelay(100);
3799 }
3800
3801 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3802 {
3803 struct drm_device *dev = crtc->dev;
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3806 int pipe = intel_crtc->pipe;
3807 u32 reg, temp;
3808
3809 /* disable CPU FDI tx and PCH FDI rx */
3810 reg = FDI_TX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3813 POSTING_READ(reg);
3814
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 temp &= ~(0x7 << 16);
3818 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3819 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3820
3821 POSTING_READ(reg);
3822 udelay(100);
3823
3824 /* Ironlake workaround, disable clock pointer after downing FDI */
3825 if (HAS_PCH_IBX(dev))
3826 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3827
3828 /* still set train pattern 1 */
3829 reg = FDI_TX_CTL(pipe);
3830 temp = I915_READ(reg);
3831 temp &= ~FDI_LINK_TRAIN_NONE;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1;
3833 I915_WRITE(reg, temp);
3834
3835 reg = FDI_RX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 if (HAS_PCH_CPT(dev)) {
3838 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3840 } else {
3841 temp &= ~FDI_LINK_TRAIN_NONE;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1;
3843 }
3844 /* BPC in FDI rx is consistent with that in PIPECONF */
3845 temp &= ~(0x07 << 16);
3846 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3847 I915_WRITE(reg, temp);
3848
3849 POSTING_READ(reg);
3850 udelay(100);
3851 }
3852
3853 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3854 {
3855 struct intel_crtc *crtc;
3856
3857 /* Note that we don't need to be called with mode_config.lock here
3858 * as our list of CRTC objects is static for the lifetime of the
3859 * device and so cannot disappear as we iterate. Similarly, we can
3860 * happily treat the predicates as racy, atomic checks as userspace
3861 * cannot claim and pin a new fb without at least acquring the
3862 * struct_mutex and so serialising with us.
3863 */
3864 for_each_intel_crtc(dev, crtc) {
3865 if (atomic_read(&crtc->unpin_work_count) == 0)
3866 continue;
3867
3868 if (crtc->unpin_work)
3869 intel_wait_for_vblank(dev, crtc->pipe);
3870
3871 return true;
3872 }
3873
3874 return false;
3875 }
3876
3877 static void page_flip_completed(struct intel_crtc *intel_crtc)
3878 {
3879 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3880 struct intel_unpin_work *work = intel_crtc->unpin_work;
3881
3882 /* ensure that the unpin work is consistent wrt ->pending. */
3883 smp_rmb();
3884 intel_crtc->unpin_work = NULL;
3885
3886 if (work->event)
3887 drm_send_vblank_event(intel_crtc->base.dev,
3888 intel_crtc->pipe,
3889 work->event);
3890
3891 drm_crtc_vblank_put(&intel_crtc->base);
3892
3893 wake_up_all(&dev_priv->pending_flip_queue);
3894 queue_work(dev_priv->wq, &work->work);
3895
3896 trace_i915_flip_complete(intel_crtc->plane,
3897 work->pending_flip_obj);
3898 }
3899
3900 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3901 {
3902 struct drm_device *dev = crtc->dev;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904
3905 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3906 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3907 !intel_crtc_has_pending_flip(crtc),
3908 60*HZ) == 0)) {
3909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3910
3911 spin_lock_irq(&dev->event_lock);
3912 if (intel_crtc->unpin_work) {
3913 WARN_ONCE(1, "Removing stuck page flip\n");
3914 page_flip_completed(intel_crtc);
3915 }
3916 spin_unlock_irq(&dev->event_lock);
3917 }
3918
3919 if (crtc->primary->fb) {
3920 mutex_lock(&dev->struct_mutex);
3921 intel_finish_fb(crtc->primary->fb);
3922 mutex_unlock(&dev->struct_mutex);
3923 }
3924 }
3925
3926 /* Program iCLKIP clock to the desired frequency */
3927 static void lpt_program_iclkip(struct drm_crtc *crtc)
3928 {
3929 struct drm_device *dev = crtc->dev;
3930 struct drm_i915_private *dev_priv = dev->dev_private;
3931 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3932 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3933 u32 temp;
3934
3935 mutex_lock(&dev_priv->sb_lock);
3936
3937 /* It is necessary to ungate the pixclk gate prior to programming
3938 * the divisors, and gate it back when it is done.
3939 */
3940 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3941
3942 /* Disable SSCCTL */
3943 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3944 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3945 SBI_SSCCTL_DISABLE,
3946 SBI_ICLK);
3947
3948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3949 if (clock == 20000) {
3950 auxdiv = 1;
3951 divsel = 0x41;
3952 phaseinc = 0x20;
3953 } else {
3954 /* The iCLK virtual clock root frequency is in MHz,
3955 * but the adjusted_mode->crtc_clock in in KHz. To get the
3956 * divisors, it is necessary to divide one by another, so we
3957 * convert the virtual clock precision to KHz here for higher
3958 * precision.
3959 */
3960 u32 iclk_virtual_root_freq = 172800 * 1000;
3961 u32 iclk_pi_range = 64;
3962 u32 desired_divisor, msb_divisor_value, pi_value;
3963
3964 desired_divisor = (iclk_virtual_root_freq / clock);
3965 msb_divisor_value = desired_divisor / iclk_pi_range;
3966 pi_value = desired_divisor % iclk_pi_range;
3967
3968 auxdiv = 0;
3969 divsel = msb_divisor_value - 2;
3970 phaseinc = pi_value;
3971 }
3972
3973 /* This should not happen with any sane values */
3974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3978
3979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3980 clock,
3981 auxdiv,
3982 divsel,
3983 phasedir,
3984 phaseinc);
3985
3986 /* Program SSCDIVINTPHASE6 */
3987 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3988 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3989 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3990 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3991 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3992 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3993 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3994 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3995
3996 /* Program SSCAUXDIV */
3997 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3998 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3999 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4000 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4001
4002 /* Enable modulator and associated divider */
4003 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4004 temp &= ~SBI_SSCCTL_DISABLE;
4005 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4006
4007 /* Wait for initialization time */
4008 udelay(24);
4009
4010 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4011
4012 mutex_unlock(&dev_priv->sb_lock);
4013 }
4014
4015 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4016 enum pipe pch_transcoder)
4017 {
4018 struct drm_device *dev = crtc->base.dev;
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4021
4022 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4023 I915_READ(HTOTAL(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4025 I915_READ(HBLANK(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4027 I915_READ(HSYNC(cpu_transcoder)));
4028
4029 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4030 I915_READ(VTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4032 I915_READ(VBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4034 I915_READ(VSYNC(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4036 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4037 }
4038
4039 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4040 {
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042 uint32_t temp;
4043
4044 temp = I915_READ(SOUTH_CHICKEN1);
4045 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4046 return;
4047
4048 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4049 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4050
4051 temp &= ~FDI_BC_BIFURCATION_SELECT;
4052 if (enable)
4053 temp |= FDI_BC_BIFURCATION_SELECT;
4054
4055 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4056 I915_WRITE(SOUTH_CHICKEN1, temp);
4057 POSTING_READ(SOUTH_CHICKEN1);
4058 }
4059
4060 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4061 {
4062 struct drm_device *dev = intel_crtc->base.dev;
4063
4064 switch (intel_crtc->pipe) {
4065 case PIPE_A:
4066 break;
4067 case PIPE_B:
4068 if (intel_crtc->config->fdi_lanes > 2)
4069 cpt_set_fdi_bc_bifurcation(dev, false);
4070 else
4071 cpt_set_fdi_bc_bifurcation(dev, true);
4072
4073 break;
4074 case PIPE_C:
4075 cpt_set_fdi_bc_bifurcation(dev, true);
4076
4077 break;
4078 default:
4079 BUG();
4080 }
4081 }
4082
4083 /*
4084 * Enable PCH resources required for PCH ports:
4085 * - PCH PLLs
4086 * - FDI training & RX/TX
4087 * - update transcoder timings
4088 * - DP transcoding bits
4089 * - transcoder
4090 */
4091 static void ironlake_pch_enable(struct drm_crtc *crtc)
4092 {
4093 struct drm_device *dev = crtc->dev;
4094 struct drm_i915_private *dev_priv = dev->dev_private;
4095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4096 int pipe = intel_crtc->pipe;
4097 u32 reg, temp;
4098
4099 assert_pch_transcoder_disabled(dev_priv, pipe);
4100
4101 if (IS_IVYBRIDGE(dev))
4102 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4103
4104 /* Write the TU size bits before fdi link training, so that error
4105 * detection works. */
4106 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4107 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4108
4109 /* For PCH output, training FDI link */
4110 dev_priv->display.fdi_link_train(crtc);
4111
4112 /* We need to program the right clock selection before writing the pixel
4113 * mutliplier into the DPLL. */
4114 if (HAS_PCH_CPT(dev)) {
4115 u32 sel;
4116
4117 temp = I915_READ(PCH_DPLL_SEL);
4118 temp |= TRANS_DPLL_ENABLE(pipe);
4119 sel = TRANS_DPLLB_SEL(pipe);
4120 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4121 temp |= sel;
4122 else
4123 temp &= ~sel;
4124 I915_WRITE(PCH_DPLL_SEL, temp);
4125 }
4126
4127 /* XXX: pch pll's can be enabled any time before we enable the PCH
4128 * transcoder, and we actually should do this to not upset any PCH
4129 * transcoder that already use the clock when we share it.
4130 *
4131 * Note that enable_shared_dpll tries to do the right thing, but
4132 * get_shared_dpll unconditionally resets the pll - we need that to have
4133 * the right LVDS enable sequence. */
4134 intel_enable_shared_dpll(intel_crtc);
4135
4136 /* set transcoder timing, panel must allow it */
4137 assert_panel_unlocked(dev_priv, pipe);
4138 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4139
4140 intel_fdi_normal_train(crtc);
4141
4142 /* For PCH DP, enable TRANS_DP_CTL */
4143 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4144 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4145 reg = TRANS_DP_CTL(pipe);
4146 temp = I915_READ(reg);
4147 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4148 TRANS_DP_SYNC_MASK |
4149 TRANS_DP_BPC_MASK);
4150 temp |= TRANS_DP_OUTPUT_ENABLE;
4151 temp |= bpc << 9; /* same format but at 11:9 */
4152
4153 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4154 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4155 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4156 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4157
4158 switch (intel_trans_dp_port_sel(crtc)) {
4159 case PCH_DP_B:
4160 temp |= TRANS_DP_PORT_SEL_B;
4161 break;
4162 case PCH_DP_C:
4163 temp |= TRANS_DP_PORT_SEL_C;
4164 break;
4165 case PCH_DP_D:
4166 temp |= TRANS_DP_PORT_SEL_D;
4167 break;
4168 default:
4169 BUG();
4170 }
4171
4172 I915_WRITE(reg, temp);
4173 }
4174
4175 ironlake_enable_pch_transcoder(dev_priv, pipe);
4176 }
4177
4178 static void lpt_pch_enable(struct drm_crtc *crtc)
4179 {
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4184
4185 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4186
4187 lpt_program_iclkip(crtc);
4188
4189 /* Set transcoder timing. */
4190 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4191
4192 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4193 }
4194
4195 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4196 struct intel_crtc_state *crtc_state)
4197 {
4198 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4199 struct intel_shared_dpll *pll;
4200 struct intel_shared_dpll_config *shared_dpll;
4201 enum intel_dpll_id i;
4202
4203 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4204
4205 if (HAS_PCH_IBX(dev_priv->dev)) {
4206 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4207 i = (enum intel_dpll_id) crtc->pipe;
4208 pll = &dev_priv->shared_dplls[i];
4209
4210 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4211 crtc->base.base.id, pll->name);
4212
4213 WARN_ON(shared_dpll[i].crtc_mask);
4214
4215 goto found;
4216 }
4217
4218 if (IS_BROXTON(dev_priv->dev)) {
4219 /* PLL is attached to port in bxt */
4220 struct intel_encoder *encoder;
4221 struct intel_digital_port *intel_dig_port;
4222
4223 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4224 if (WARN_ON(!encoder))
4225 return NULL;
4226
4227 intel_dig_port = enc_to_dig_port(&encoder->base);
4228 /* 1:1 mapping between ports and PLLs */
4229 i = (enum intel_dpll_id)intel_dig_port->port;
4230 pll = &dev_priv->shared_dplls[i];
4231 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4232 crtc->base.base.id, pll->name);
4233 WARN_ON(shared_dpll[i].crtc_mask);
4234
4235 goto found;
4236 }
4237
4238 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4239 pll = &dev_priv->shared_dplls[i];
4240
4241 /* Only want to check enabled timings first */
4242 if (shared_dpll[i].crtc_mask == 0)
4243 continue;
4244
4245 if (memcmp(&crtc_state->dpll_hw_state,
4246 &shared_dpll[i].hw_state,
4247 sizeof(crtc_state->dpll_hw_state)) == 0) {
4248 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4249 crtc->base.base.id, pll->name,
4250 shared_dpll[i].crtc_mask,
4251 pll->active);
4252 goto found;
4253 }
4254 }
4255
4256 /* Ok no matching timings, maybe there's a free one? */
4257 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4258 pll = &dev_priv->shared_dplls[i];
4259 if (shared_dpll[i].crtc_mask == 0) {
4260 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4261 crtc->base.base.id, pll->name);
4262 goto found;
4263 }
4264 }
4265
4266 return NULL;
4267
4268 found:
4269 if (shared_dpll[i].crtc_mask == 0)
4270 shared_dpll[i].hw_state =
4271 crtc_state->dpll_hw_state;
4272
4273 crtc_state->shared_dpll = i;
4274 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4275 pipe_name(crtc->pipe));
4276
4277 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4278
4279 return pll;
4280 }
4281
4282 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4283 {
4284 struct drm_i915_private *dev_priv = to_i915(state->dev);
4285 struct intel_shared_dpll_config *shared_dpll;
4286 struct intel_shared_dpll *pll;
4287 enum intel_dpll_id i;
4288
4289 if (!to_intel_atomic_state(state)->dpll_set)
4290 return;
4291
4292 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4293 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4294 pll = &dev_priv->shared_dplls[i];
4295 pll->config = shared_dpll[i];
4296 }
4297 }
4298
4299 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4300 {
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 int dslreg = PIPEDSL(pipe);
4303 u32 temp;
4304
4305 temp = I915_READ(dslreg);
4306 udelay(500);
4307 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4308 if (wait_for(I915_READ(dslreg) != temp, 5))
4309 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4310 }
4311 }
4312
4313 static int
4314 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4315 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4316 int src_w, int src_h, int dst_w, int dst_h)
4317 {
4318 struct intel_crtc_scaler_state *scaler_state =
4319 &crtc_state->scaler_state;
4320 struct intel_crtc *intel_crtc =
4321 to_intel_crtc(crtc_state->base.crtc);
4322 int need_scaling;
4323
4324 need_scaling = intel_rotation_90_or_270(rotation) ?
4325 (src_h != dst_w || src_w != dst_h):
4326 (src_w != dst_w || src_h != dst_h);
4327
4328 /*
4329 * if plane is being disabled or scaler is no more required or force detach
4330 * - free scaler binded to this plane/crtc
4331 * - in order to do this, update crtc->scaler_usage
4332 *
4333 * Here scaler state in crtc_state is set free so that
4334 * scaler can be assigned to other user. Actual register
4335 * update to free the scaler is done in plane/panel-fit programming.
4336 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4337 */
4338 if (force_detach || !need_scaling) {
4339 if (*scaler_id >= 0) {
4340 scaler_state->scaler_users &= ~(1 << scaler_user);
4341 scaler_state->scalers[*scaler_id].in_use = 0;
4342
4343 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4344 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4345 intel_crtc->pipe, scaler_user, *scaler_id,
4346 scaler_state->scaler_users);
4347 *scaler_id = -1;
4348 }
4349 return 0;
4350 }
4351
4352 /* range checks */
4353 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4354 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4355
4356 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4357 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4358 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4359 "size is out of scaler range\n",
4360 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4361 return -EINVAL;
4362 }
4363
4364 /* mark this plane as a scaler user in crtc_state */
4365 scaler_state->scaler_users |= (1 << scaler_user);
4366 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4367 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4368 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4369 scaler_state->scaler_users);
4370
4371 return 0;
4372 }
4373
4374 /**
4375 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4376 *
4377 * @state: crtc's scaler state
4378 * @force_detach: whether to forcibly disable scaler
4379 *
4380 * Return
4381 * 0 - scaler_usage updated successfully
4382 * error - requested scaling cannot be supported or other error condition
4383 */
4384 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4385 {
4386 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4387 struct drm_display_mode *adjusted_mode =
4388 &state->base.adjusted_mode;
4389
4390 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4391 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4392
4393 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4394 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4395 state->pipe_src_w, state->pipe_src_h,
4396 adjusted_mode->hdisplay, adjusted_mode->hdisplay);
4397 }
4398
4399 /**
4400 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4401 *
4402 * @state: crtc's scaler state
4403 * @plane_state: atomic plane state to update
4404 *
4405 * Return
4406 * 0 - scaler_usage updated successfully
4407 * error - requested scaling cannot be supported or other error condition
4408 */
4409 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4410 struct intel_plane_state *plane_state)
4411 {
4412
4413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4414 struct intel_plane *intel_plane =
4415 to_intel_plane(plane_state->base.plane);
4416 struct drm_framebuffer *fb = plane_state->base.fb;
4417 int ret;
4418
4419 bool force_detach = !fb || !plane_state->visible;
4420
4421 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4422 intel_plane->base.base.id, intel_crtc->pipe,
4423 drm_plane_index(&intel_plane->base));
4424
4425 ret = skl_update_scaler(crtc_state, force_detach,
4426 drm_plane_index(&intel_plane->base),
4427 &plane_state->scaler_id,
4428 plane_state->base.rotation,
4429 drm_rect_width(&plane_state->src) >> 16,
4430 drm_rect_height(&plane_state->src) >> 16,
4431 drm_rect_width(&plane_state->dst),
4432 drm_rect_height(&plane_state->dst));
4433
4434 if (ret || plane_state->scaler_id < 0)
4435 return ret;
4436
4437 /* check colorkey */
4438 if (WARN_ON(intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4439 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4440 intel_plane->base.base.id);
4441 return -EINVAL;
4442 }
4443
4444 /* Check src format */
4445 switch (fb->pixel_format) {
4446 case DRM_FORMAT_RGB565:
4447 case DRM_FORMAT_XBGR8888:
4448 case DRM_FORMAT_XRGB8888:
4449 case DRM_FORMAT_ABGR8888:
4450 case DRM_FORMAT_ARGB8888:
4451 case DRM_FORMAT_XRGB2101010:
4452 case DRM_FORMAT_XBGR2101010:
4453 case DRM_FORMAT_YUYV:
4454 case DRM_FORMAT_YVYU:
4455 case DRM_FORMAT_UYVY:
4456 case DRM_FORMAT_VYUY:
4457 break;
4458 default:
4459 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4460 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4461 return -EINVAL;
4462 }
4463
4464 return 0;
4465 }
4466
4467 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4468 {
4469 struct drm_device *dev = crtc->base.dev;
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 int pipe = crtc->pipe;
4472 struct intel_crtc_scaler_state *scaler_state =
4473 &crtc->config->scaler_state;
4474
4475 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4476
4477 /* To update pfit, first update scaler state */
4478 skl_update_scaler_crtc(crtc->config, !enable);
4479 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4480 skl_detach_scalers(crtc);
4481 if (!enable)
4482 return;
4483
4484 if (crtc->config->pch_pfit.enabled) {
4485 int id;
4486
4487 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4488 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4489 return;
4490 }
4491
4492 id = scaler_state->scaler_id;
4493 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4494 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4495 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4496 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4497
4498 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4499 }
4500 }
4501
4502 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4503 {
4504 struct drm_device *dev = crtc->base.dev;
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506 int pipe = crtc->pipe;
4507
4508 if (crtc->config->pch_pfit.enabled) {
4509 /* Force use of hard-coded filter coefficients
4510 * as some pre-programmed values are broken,
4511 * e.g. x201.
4512 */
4513 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4514 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4515 PF_PIPE_SEL_IVB(pipe));
4516 else
4517 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4518 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4519 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4520 }
4521 }
4522
4523 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4524 {
4525 struct drm_device *dev = crtc->dev;
4526 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4527 struct drm_plane *plane;
4528 struct intel_plane *intel_plane;
4529
4530 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4531 intel_plane = to_intel_plane(plane);
4532 if (intel_plane->pipe == pipe)
4533 intel_plane_restore(&intel_plane->base);
4534 }
4535 }
4536
4537 void hsw_enable_ips(struct intel_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->base.dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541
4542 if (!crtc->config->ips_enabled)
4543 return;
4544
4545 /* We can only enable IPS after we enable a plane and wait for a vblank */
4546 intel_wait_for_vblank(dev, crtc->pipe);
4547
4548 assert_plane_enabled(dev_priv, crtc->plane);
4549 if (IS_BROADWELL(dev)) {
4550 mutex_lock(&dev_priv->rps.hw_lock);
4551 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4552 mutex_unlock(&dev_priv->rps.hw_lock);
4553 /* Quoting Art Runyan: "its not safe to expect any particular
4554 * value in IPS_CTL bit 31 after enabling IPS through the
4555 * mailbox." Moreover, the mailbox may return a bogus state,
4556 * so we need to just enable it and continue on.
4557 */
4558 } else {
4559 I915_WRITE(IPS_CTL, IPS_ENABLE);
4560 /* The bit only becomes 1 in the next vblank, so this wait here
4561 * is essentially intel_wait_for_vblank. If we don't have this
4562 * and don't wait for vblanks until the end of crtc_enable, then
4563 * the HW state readout code will complain that the expected
4564 * IPS_CTL value is not the one we read. */
4565 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4566 DRM_ERROR("Timed out waiting for IPS enable\n");
4567 }
4568 }
4569
4570 void hsw_disable_ips(struct intel_crtc *crtc)
4571 {
4572 struct drm_device *dev = crtc->base.dev;
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574
4575 if (!crtc->config->ips_enabled)
4576 return;
4577
4578 assert_plane_enabled(dev_priv, crtc->plane);
4579 if (IS_BROADWELL(dev)) {
4580 mutex_lock(&dev_priv->rps.hw_lock);
4581 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4582 mutex_unlock(&dev_priv->rps.hw_lock);
4583 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4584 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4585 DRM_ERROR("Timed out waiting for IPS disable\n");
4586 } else {
4587 I915_WRITE(IPS_CTL, 0);
4588 POSTING_READ(IPS_CTL);
4589 }
4590
4591 /* We need to wait for a vblank before we can disable the plane. */
4592 intel_wait_for_vblank(dev, crtc->pipe);
4593 }
4594
4595 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4596 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4597 {
4598 struct drm_device *dev = crtc->dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4601 enum pipe pipe = intel_crtc->pipe;
4602 int palreg = PALETTE(pipe);
4603 int i;
4604 bool reenable_ips = false;
4605
4606 /* The clocks have to be on to load the palette. */
4607 if (!crtc->state->active)
4608 return;
4609
4610 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4611 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4612 assert_dsi_pll_enabled(dev_priv);
4613 else
4614 assert_pll_enabled(dev_priv, pipe);
4615 }
4616
4617 /* use legacy palette for Ironlake */
4618 if (!HAS_GMCH_DISPLAY(dev))
4619 palreg = LGC_PALETTE(pipe);
4620
4621 /* Workaround : Do not read or write the pipe palette/gamma data while
4622 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4623 */
4624 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4625 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4626 GAMMA_MODE_MODE_SPLIT)) {
4627 hsw_disable_ips(intel_crtc);
4628 reenable_ips = true;
4629 }
4630
4631 for (i = 0; i < 256; i++) {
4632 I915_WRITE(palreg + 4 * i,
4633 (intel_crtc->lut_r[i] << 16) |
4634 (intel_crtc->lut_g[i] << 8) |
4635 intel_crtc->lut_b[i]);
4636 }
4637
4638 if (reenable_ips)
4639 hsw_enable_ips(intel_crtc);
4640 }
4641
4642 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4643 {
4644 if (intel_crtc->overlay) {
4645 struct drm_device *dev = intel_crtc->base.dev;
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647
4648 mutex_lock(&dev->struct_mutex);
4649 dev_priv->mm.interruptible = false;
4650 (void) intel_overlay_switch_off(intel_crtc->overlay);
4651 dev_priv->mm.interruptible = true;
4652 mutex_unlock(&dev->struct_mutex);
4653 }
4654
4655 /* Let userspace switch the overlay on again. In most cases userspace
4656 * has to recompute where to put it anyway.
4657 */
4658 }
4659
4660 /**
4661 * intel_post_enable_primary - Perform operations after enabling primary plane
4662 * @crtc: the CRTC whose primary plane was just enabled
4663 *
4664 * Performs potentially sleeping operations that must be done after the primary
4665 * plane is enabled, such as updating FBC and IPS. Note that this may be
4666 * called due to an explicit primary plane update, or due to an implicit
4667 * re-enable that is caused when a sprite plane is updated to no longer
4668 * completely hide the primary plane.
4669 */
4670 static void
4671 intel_post_enable_primary(struct drm_crtc *crtc)
4672 {
4673 struct drm_device *dev = crtc->dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4676 int pipe = intel_crtc->pipe;
4677
4678 /*
4679 * BDW signals flip done immediately if the plane
4680 * is disabled, even if the plane enable is already
4681 * armed to occur at the next vblank :(
4682 */
4683 if (IS_BROADWELL(dev))
4684 intel_wait_for_vblank(dev, pipe);
4685
4686 /*
4687 * FIXME IPS should be fine as long as one plane is
4688 * enabled, but in practice it seems to have problems
4689 * when going from primary only to sprite only and vice
4690 * versa.
4691 */
4692 hsw_enable_ips(intel_crtc);
4693
4694 mutex_lock(&dev->struct_mutex);
4695 intel_fbc_update(dev);
4696 mutex_unlock(&dev->struct_mutex);
4697
4698 /*
4699 * Gen2 reports pipe underruns whenever all planes are disabled.
4700 * So don't enable underrun reporting before at least some planes
4701 * are enabled.
4702 * FIXME: Need to fix the logic to work when we turn off all planes
4703 * but leave the pipe running.
4704 */
4705 if (IS_GEN2(dev))
4706 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4707
4708 /* Underruns don't raise interrupts, so check manually. */
4709 if (HAS_GMCH_DISPLAY(dev))
4710 i9xx_check_fifo_underruns(dev_priv);
4711 }
4712
4713 /**
4714 * intel_pre_disable_primary - Perform operations before disabling primary plane
4715 * @crtc: the CRTC whose primary plane is to be disabled
4716 *
4717 * Performs potentially sleeping operations that must be done before the
4718 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4719 * be called due to an explicit primary plane update, or due to an implicit
4720 * disable that is caused when a sprite plane completely hides the primary
4721 * plane.
4722 */
4723 static void
4724 intel_pre_disable_primary(struct drm_crtc *crtc)
4725 {
4726 struct drm_device *dev = crtc->dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729 int pipe = intel_crtc->pipe;
4730
4731 /*
4732 * Gen2 reports pipe underruns whenever all planes are disabled.
4733 * So diasble underrun reporting before all the planes get disabled.
4734 * FIXME: Need to fix the logic to work when we turn off all planes
4735 * but leave the pipe running.
4736 */
4737 if (IS_GEN2(dev))
4738 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4739
4740 /*
4741 * Vblank time updates from the shadow to live plane control register
4742 * are blocked if the memory self-refresh mode is active at that
4743 * moment. So to make sure the plane gets truly disabled, disable
4744 * first the self-refresh mode. The self-refresh enable bit in turn
4745 * will be checked/applied by the HW only at the next frame start
4746 * event which is after the vblank start event, so we need to have a
4747 * wait-for-vblank between disabling the plane and the pipe.
4748 */
4749 if (HAS_GMCH_DISPLAY(dev))
4750 intel_set_memory_cxsr(dev_priv, false);
4751
4752 mutex_lock(&dev->struct_mutex);
4753 if (dev_priv->fbc.crtc == intel_crtc)
4754 intel_fbc_disable(dev);
4755 mutex_unlock(&dev->struct_mutex);
4756
4757 /*
4758 * FIXME IPS should be fine as long as one plane is
4759 * enabled, but in practice it seems to have problems
4760 * when going from primary only to sprite only and vice
4761 * versa.
4762 */
4763 hsw_disable_ips(intel_crtc);
4764 }
4765
4766 static void intel_post_plane_update(struct intel_crtc *crtc)
4767 {
4768 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4769 struct drm_device *dev = crtc->base.dev;
4770 struct drm_plane *plane;
4771
4772 if (atomic->wait_vblank)
4773 intel_wait_for_vblank(dev, crtc->pipe);
4774
4775 intel_frontbuffer_flip(dev, atomic->fb_bits);
4776
4777 if (atomic->update_fbc) {
4778 mutex_lock(&dev->struct_mutex);
4779 intel_fbc_update(dev);
4780 mutex_unlock(&dev->struct_mutex);
4781 }
4782
4783 if (atomic->post_enable_primary)
4784 intel_post_enable_primary(&crtc->base);
4785
4786 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4787 intel_update_sprite_watermarks(plane, &crtc->base,
4788 0, 0, 0, false, false);
4789
4790 memset(atomic, 0, sizeof(*atomic));
4791 }
4792
4793 static void intel_pre_plane_update(struct intel_crtc *crtc)
4794 {
4795 struct drm_device *dev = crtc->base.dev;
4796 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4797 struct drm_plane *p;
4798
4799 /* Track fb's for any planes being disabled */
4800
4801 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4802 struct intel_plane *plane = to_intel_plane(p);
4803 unsigned fb_bits = 0;
4804
4805 switch (p->type) {
4806 case DRM_PLANE_TYPE_PRIMARY:
4807 fb_bits = INTEL_FRONTBUFFER_PRIMARY(plane->pipe);
4808 break;
4809 case DRM_PLANE_TYPE_CURSOR:
4810 fb_bits = INTEL_FRONTBUFFER_CURSOR(plane->pipe);
4811 break;
4812 case DRM_PLANE_TYPE_OVERLAY:
4813 fb_bits = INTEL_FRONTBUFFER_SPRITE(plane->pipe);
4814 break;
4815 }
4816
4817 mutex_lock(&dev->struct_mutex);
4818 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, fb_bits);
4819 mutex_unlock(&dev->struct_mutex);
4820 }
4821
4822 if (atomic->wait_for_flips)
4823 intel_crtc_wait_for_pending_flips(&crtc->base);
4824
4825 if (atomic->disable_fbc)
4826 intel_fbc_disable(dev);
4827
4828 if (atomic->pre_disable_primary)
4829 intel_pre_disable_primary(&crtc->base);
4830 }
4831
4832 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4833 {
4834 struct drm_device *dev = crtc->dev;
4835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4836 int pipe = intel_crtc->pipe;
4837
4838 intel_enable_primary_hw_plane(crtc->primary, crtc);
4839 intel_enable_sprite_planes(crtc);
4840 if (to_intel_plane_state(crtc->cursor->state)->visible)
4841 intel_crtc_update_cursor(crtc, true);
4842
4843 intel_post_enable_primary(crtc);
4844
4845 /*
4846 * FIXME: Once we grow proper nuclear flip support out of this we need
4847 * to compute the mask of flip planes precisely. For the time being
4848 * consider this a flip to a NULL plane.
4849 */
4850 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4851 }
4852
4853 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4854 {
4855 struct drm_device *dev = crtc->dev;
4856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857 struct intel_plane *intel_plane;
4858 int pipe = intel_crtc->pipe;
4859
4860 intel_crtc_wait_for_pending_flips(crtc);
4861
4862 intel_pre_disable_primary(crtc);
4863
4864 intel_crtc_dpms_overlay_disable(intel_crtc);
4865 for_each_intel_plane(dev, intel_plane) {
4866 if (intel_plane->pipe == pipe) {
4867 struct drm_crtc *from = intel_plane->base.crtc;
4868
4869 intel_plane->disable_plane(&intel_plane->base,
4870 from ?: crtc);
4871 }
4872 }
4873
4874 /*
4875 * FIXME: Once we grow proper nuclear flip support out of this we need
4876 * to compute the mask of flip planes precisely. For the time being
4877 * consider this a flip to a NULL plane.
4878 */
4879 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4880 }
4881
4882 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4883 {
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 struct intel_encoder *encoder;
4888 int pipe = intel_crtc->pipe;
4889
4890 if (WARN_ON(intel_crtc->active))
4891 return;
4892
4893 if (intel_crtc->config->has_pch_encoder)
4894 intel_prepare_shared_dpll(intel_crtc);
4895
4896 if (intel_crtc->config->has_dp_encoder)
4897 intel_dp_set_m_n(intel_crtc, M1_N1);
4898
4899 intel_set_pipe_timings(intel_crtc);
4900
4901 if (intel_crtc->config->has_pch_encoder) {
4902 intel_cpu_transcoder_set_m_n(intel_crtc,
4903 &intel_crtc->config->fdi_m_n, NULL);
4904 }
4905
4906 ironlake_set_pipeconf(crtc);
4907
4908 intel_crtc->active = true;
4909
4910 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4911 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4912
4913 for_each_encoder_on_crtc(dev, crtc, encoder)
4914 if (encoder->pre_enable)
4915 encoder->pre_enable(encoder);
4916
4917 if (intel_crtc->config->has_pch_encoder) {
4918 /* Note: FDI PLL enabling _must_ be done before we enable the
4919 * cpu pipes, hence this is separate from all the other fdi/pch
4920 * enabling. */
4921 ironlake_fdi_pll_enable(intel_crtc);
4922 } else {
4923 assert_fdi_tx_disabled(dev_priv, pipe);
4924 assert_fdi_rx_disabled(dev_priv, pipe);
4925 }
4926
4927 ironlake_pfit_enable(intel_crtc);
4928
4929 /*
4930 * On ILK+ LUT must be loaded before the pipe is running but with
4931 * clocks enabled
4932 */
4933 intel_crtc_load_lut(crtc);
4934
4935 intel_update_watermarks(crtc);
4936 intel_enable_pipe(intel_crtc);
4937
4938 if (intel_crtc->config->has_pch_encoder)
4939 ironlake_pch_enable(crtc);
4940
4941 assert_vblank_disabled(crtc);
4942 drm_crtc_vblank_on(crtc);
4943
4944 for_each_encoder_on_crtc(dev, crtc, encoder)
4945 encoder->enable(encoder);
4946
4947 if (HAS_PCH_CPT(dev))
4948 cpt_verify_modeset(dev, intel_crtc->pipe);
4949 }
4950
4951 /* IPS only exists on ULT machines and is tied to pipe A. */
4952 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4953 {
4954 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4955 }
4956
4957 static void haswell_crtc_enable(struct drm_crtc *crtc)
4958 {
4959 struct drm_device *dev = crtc->dev;
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962 struct intel_encoder *encoder;
4963 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4964 struct intel_crtc_state *pipe_config =
4965 to_intel_crtc_state(crtc->state);
4966
4967 if (WARN_ON(intel_crtc->active))
4968 return;
4969
4970 if (intel_crtc_to_shared_dpll(intel_crtc))
4971 intel_enable_shared_dpll(intel_crtc);
4972
4973 if (intel_crtc->config->has_dp_encoder)
4974 intel_dp_set_m_n(intel_crtc, M1_N1);
4975
4976 intel_set_pipe_timings(intel_crtc);
4977
4978 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4979 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4980 intel_crtc->config->pixel_multiplier - 1);
4981 }
4982
4983 if (intel_crtc->config->has_pch_encoder) {
4984 intel_cpu_transcoder_set_m_n(intel_crtc,
4985 &intel_crtc->config->fdi_m_n, NULL);
4986 }
4987
4988 haswell_set_pipeconf(crtc);
4989
4990 intel_set_pipe_csc(crtc);
4991
4992 intel_crtc->active = true;
4993
4994 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4995 for_each_encoder_on_crtc(dev, crtc, encoder)
4996 if (encoder->pre_enable)
4997 encoder->pre_enable(encoder);
4998
4999 if (intel_crtc->config->has_pch_encoder) {
5000 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5001 true);
5002 dev_priv->display.fdi_link_train(crtc);
5003 }
5004
5005 intel_ddi_enable_pipe_clock(intel_crtc);
5006
5007 if (INTEL_INFO(dev)->gen == 9)
5008 skylake_pfit_update(intel_crtc, 1);
5009 else if (INTEL_INFO(dev)->gen < 9)
5010 ironlake_pfit_enable(intel_crtc);
5011 else
5012 MISSING_CASE(INTEL_INFO(dev)->gen);
5013
5014 /*
5015 * On ILK+ LUT must be loaded before the pipe is running but with
5016 * clocks enabled
5017 */
5018 intel_crtc_load_lut(crtc);
5019
5020 intel_ddi_set_pipe_settings(crtc);
5021 intel_ddi_enable_transcoder_func(crtc);
5022
5023 intel_update_watermarks(crtc);
5024 intel_enable_pipe(intel_crtc);
5025
5026 if (intel_crtc->config->has_pch_encoder)
5027 lpt_pch_enable(crtc);
5028
5029 if (intel_crtc->config->dp_encoder_is_mst)
5030 intel_ddi_set_vc_payload_alloc(crtc, true);
5031
5032 assert_vblank_disabled(crtc);
5033 drm_crtc_vblank_on(crtc);
5034
5035 for_each_encoder_on_crtc(dev, crtc, encoder) {
5036 encoder->enable(encoder);
5037 intel_opregion_notify_encoder(encoder, true);
5038 }
5039
5040 /* If we change the relative order between pipe/planes enabling, we need
5041 * to change the workaround. */
5042 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5043 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5044 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5045 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5046 }
5047 }
5048
5049 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5050 {
5051 struct drm_device *dev = crtc->base.dev;
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 int pipe = crtc->pipe;
5054
5055 /* To avoid upsetting the power well on haswell only disable the pfit if
5056 * it's in use. The hw state code will make sure we get this right. */
5057 if (crtc->config->pch_pfit.enabled) {
5058 I915_WRITE(PF_CTL(pipe), 0);
5059 I915_WRITE(PF_WIN_POS(pipe), 0);
5060 I915_WRITE(PF_WIN_SZ(pipe), 0);
5061 }
5062 }
5063
5064 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5065 {
5066 struct drm_device *dev = crtc->dev;
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5069 struct intel_encoder *encoder;
5070 int pipe = intel_crtc->pipe;
5071 u32 reg, temp;
5072
5073 if (WARN_ON(!intel_crtc->active))
5074 return;
5075
5076 for_each_encoder_on_crtc(dev, crtc, encoder)
5077 encoder->disable(encoder);
5078
5079 drm_crtc_vblank_off(crtc);
5080 assert_vblank_disabled(crtc);
5081
5082 if (intel_crtc->config->has_pch_encoder)
5083 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5084
5085 intel_disable_pipe(intel_crtc);
5086
5087 ironlake_pfit_disable(intel_crtc);
5088
5089 if (intel_crtc->config->has_pch_encoder)
5090 ironlake_fdi_disable(crtc);
5091
5092 for_each_encoder_on_crtc(dev, crtc, encoder)
5093 if (encoder->post_disable)
5094 encoder->post_disable(encoder);
5095
5096 if (intel_crtc->config->has_pch_encoder) {
5097 ironlake_disable_pch_transcoder(dev_priv, pipe);
5098
5099 if (HAS_PCH_CPT(dev)) {
5100 /* disable TRANS_DP_CTL */
5101 reg = TRANS_DP_CTL(pipe);
5102 temp = I915_READ(reg);
5103 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5104 TRANS_DP_PORT_SEL_MASK);
5105 temp |= TRANS_DP_PORT_SEL_NONE;
5106 I915_WRITE(reg, temp);
5107
5108 /* disable DPLL_SEL */
5109 temp = I915_READ(PCH_DPLL_SEL);
5110 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5111 I915_WRITE(PCH_DPLL_SEL, temp);
5112 }
5113
5114 /* disable PCH DPLL */
5115 intel_disable_shared_dpll(intel_crtc);
5116
5117 ironlake_fdi_pll_disable(intel_crtc);
5118 }
5119
5120 intel_crtc->active = false;
5121 intel_update_watermarks(crtc);
5122
5123 mutex_lock(&dev->struct_mutex);
5124 intel_fbc_update(dev);
5125 mutex_unlock(&dev->struct_mutex);
5126 }
5127
5128 static void haswell_crtc_disable(struct drm_crtc *crtc)
5129 {
5130 struct drm_device *dev = crtc->dev;
5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133 struct intel_encoder *encoder;
5134 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5135
5136 if (WARN_ON(!intel_crtc->active))
5137 return;
5138
5139 for_each_encoder_on_crtc(dev, crtc, encoder) {
5140 intel_opregion_notify_encoder(encoder, false);
5141 encoder->disable(encoder);
5142 }
5143
5144 drm_crtc_vblank_off(crtc);
5145 assert_vblank_disabled(crtc);
5146
5147 if (intel_crtc->config->has_pch_encoder)
5148 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5149 false);
5150 intel_disable_pipe(intel_crtc);
5151
5152 if (intel_crtc->config->dp_encoder_is_mst)
5153 intel_ddi_set_vc_payload_alloc(crtc, false);
5154
5155 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5156
5157 if (INTEL_INFO(dev)->gen == 9)
5158 skylake_pfit_update(intel_crtc, 0);
5159 else if (INTEL_INFO(dev)->gen < 9)
5160 ironlake_pfit_disable(intel_crtc);
5161 else
5162 MISSING_CASE(INTEL_INFO(dev)->gen);
5163
5164 intel_ddi_disable_pipe_clock(intel_crtc);
5165
5166 if (intel_crtc->config->has_pch_encoder) {
5167 lpt_disable_pch_transcoder(dev_priv);
5168 intel_ddi_fdi_disable(crtc);
5169 }
5170
5171 for_each_encoder_on_crtc(dev, crtc, encoder)
5172 if (encoder->post_disable)
5173 encoder->post_disable(encoder);
5174
5175 intel_crtc->active = false;
5176 intel_update_watermarks(crtc);
5177
5178 mutex_lock(&dev->struct_mutex);
5179 intel_fbc_update(dev);
5180 mutex_unlock(&dev->struct_mutex);
5181
5182 if (intel_crtc_to_shared_dpll(intel_crtc))
5183 intel_disable_shared_dpll(intel_crtc);
5184 }
5185
5186 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5187 {
5188 struct drm_device *dev = crtc->base.dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc_state *pipe_config = crtc->config;
5191
5192 if (!pipe_config->gmch_pfit.control)
5193 return;
5194
5195 /*
5196 * The panel fitter should only be adjusted whilst the pipe is disabled,
5197 * according to register description and PRM.
5198 */
5199 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5200 assert_pipe_disabled(dev_priv, crtc->pipe);
5201
5202 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5203 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5204
5205 /* Border color in case we don't scale up to the full screen. Black by
5206 * default, change to something else for debugging. */
5207 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5208 }
5209
5210 static enum intel_display_power_domain port_to_power_domain(enum port port)
5211 {
5212 switch (port) {
5213 case PORT_A:
5214 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5215 case PORT_B:
5216 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5217 case PORT_C:
5218 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5219 case PORT_D:
5220 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5221 default:
5222 WARN_ON_ONCE(1);
5223 return POWER_DOMAIN_PORT_OTHER;
5224 }
5225 }
5226
5227 #define for_each_power_domain(domain, mask) \
5228 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5229 if ((1 << (domain)) & (mask))
5230
5231 enum intel_display_power_domain
5232 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5233 {
5234 struct drm_device *dev = intel_encoder->base.dev;
5235 struct intel_digital_port *intel_dig_port;
5236
5237 switch (intel_encoder->type) {
5238 case INTEL_OUTPUT_UNKNOWN:
5239 /* Only DDI platforms should ever use this output type */
5240 WARN_ON_ONCE(!HAS_DDI(dev));
5241 case INTEL_OUTPUT_DISPLAYPORT:
5242 case INTEL_OUTPUT_HDMI:
5243 case INTEL_OUTPUT_EDP:
5244 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5245 return port_to_power_domain(intel_dig_port->port);
5246 case INTEL_OUTPUT_DP_MST:
5247 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5248 return port_to_power_domain(intel_dig_port->port);
5249 case INTEL_OUTPUT_ANALOG:
5250 return POWER_DOMAIN_PORT_CRT;
5251 case INTEL_OUTPUT_DSI:
5252 return POWER_DOMAIN_PORT_DSI;
5253 default:
5254 return POWER_DOMAIN_PORT_OTHER;
5255 }
5256 }
5257
5258 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5259 {
5260 struct drm_device *dev = crtc->dev;
5261 struct intel_encoder *intel_encoder;
5262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5263 enum pipe pipe = intel_crtc->pipe;
5264 unsigned long mask;
5265 enum transcoder transcoder;
5266
5267 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5268
5269 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5270 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5271 if (intel_crtc->config->pch_pfit.enabled ||
5272 intel_crtc->config->pch_pfit.force_thru)
5273 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5274
5275 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5276 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5277
5278 return mask;
5279 }
5280
5281 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5282 {
5283 struct drm_device *dev = state->dev;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5286 struct intel_crtc *crtc;
5287
5288 /*
5289 * First get all needed power domains, then put all unneeded, to avoid
5290 * any unnecessary toggling of the power wells.
5291 */
5292 for_each_intel_crtc(dev, crtc) {
5293 enum intel_display_power_domain domain;
5294
5295 if (!crtc->base.state->enable)
5296 continue;
5297
5298 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5299
5300 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5301 intel_display_power_get(dev_priv, domain);
5302 }
5303
5304 if (dev_priv->display.modeset_global_resources)
5305 dev_priv->display.modeset_global_resources(state);
5306
5307 for_each_intel_crtc(dev, crtc) {
5308 enum intel_display_power_domain domain;
5309
5310 for_each_power_domain(domain, crtc->enabled_power_domains)
5311 intel_display_power_put(dev_priv, domain);
5312
5313 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5314 }
5315
5316 intel_display_set_init_power(dev_priv, false);
5317 }
5318
5319 static void intel_update_max_cdclk(struct drm_device *dev)
5320 {
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322
5323 if (IS_SKYLAKE(dev)) {
5324 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5325
5326 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5327 dev_priv->max_cdclk_freq = 675000;
5328 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5329 dev_priv->max_cdclk_freq = 540000;
5330 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5331 dev_priv->max_cdclk_freq = 450000;
5332 else
5333 dev_priv->max_cdclk_freq = 337500;
5334 } else if (IS_BROADWELL(dev)) {
5335 /*
5336 * FIXME with extra cooling we can allow
5337 * 540 MHz for ULX and 675 Mhz for ULT.
5338 * How can we know if extra cooling is
5339 * available? PCI ID, VTB, something else?
5340 */
5341 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5342 dev_priv->max_cdclk_freq = 450000;
5343 else if (IS_BDW_ULX(dev))
5344 dev_priv->max_cdclk_freq = 450000;
5345 else if (IS_BDW_ULT(dev))
5346 dev_priv->max_cdclk_freq = 540000;
5347 else
5348 dev_priv->max_cdclk_freq = 675000;
5349 } else if (IS_CHERRYVIEW(dev)) {
5350 dev_priv->max_cdclk_freq = 320000;
5351 } else if (IS_VALLEYVIEW(dev)) {
5352 dev_priv->max_cdclk_freq = 400000;
5353 } else {
5354 /* otherwise assume cdclk is fixed */
5355 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5356 }
5357
5358 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5359 dev_priv->max_cdclk_freq);
5360 }
5361
5362 static void intel_update_cdclk(struct drm_device *dev)
5363 {
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365
5366 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5367 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5368 dev_priv->cdclk_freq);
5369
5370 /*
5371 * Program the gmbus_freq based on the cdclk frequency.
5372 * BSpec erroneously claims we should aim for 4MHz, but
5373 * in fact 1MHz is the correct frequency.
5374 */
5375 if (IS_VALLEYVIEW(dev)) {
5376 /*
5377 * Program the gmbus_freq based on the cdclk frequency.
5378 * BSpec erroneously claims we should aim for 4MHz, but
5379 * in fact 1MHz is the correct frequency.
5380 */
5381 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5382 }
5383
5384 if (dev_priv->max_cdclk_freq == 0)
5385 intel_update_max_cdclk(dev);
5386 }
5387
5388 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5389 {
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391 uint32_t divider;
5392 uint32_t ratio;
5393 uint32_t current_freq;
5394 int ret;
5395
5396 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5397 switch (frequency) {
5398 case 144000:
5399 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5400 ratio = BXT_DE_PLL_RATIO(60);
5401 break;
5402 case 288000:
5403 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5404 ratio = BXT_DE_PLL_RATIO(60);
5405 break;
5406 case 384000:
5407 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5408 ratio = BXT_DE_PLL_RATIO(60);
5409 break;
5410 case 576000:
5411 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5412 ratio = BXT_DE_PLL_RATIO(60);
5413 break;
5414 case 624000:
5415 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5416 ratio = BXT_DE_PLL_RATIO(65);
5417 break;
5418 case 19200:
5419 /*
5420 * Bypass frequency with DE PLL disabled. Init ratio, divider
5421 * to suppress GCC warning.
5422 */
5423 ratio = 0;
5424 divider = 0;
5425 break;
5426 default:
5427 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5428
5429 return;
5430 }
5431
5432 mutex_lock(&dev_priv->rps.hw_lock);
5433 /* Inform power controller of upcoming frequency change */
5434 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5435 0x80000000);
5436 mutex_unlock(&dev_priv->rps.hw_lock);
5437
5438 if (ret) {
5439 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5440 ret, frequency);
5441 return;
5442 }
5443
5444 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5445 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5446 current_freq = current_freq * 500 + 1000;
5447
5448 /*
5449 * DE PLL has to be disabled when
5450 * - setting to 19.2MHz (bypass, PLL isn't used)
5451 * - before setting to 624MHz (PLL needs toggling)
5452 * - before setting to any frequency from 624MHz (PLL needs toggling)
5453 */
5454 if (frequency == 19200 || frequency == 624000 ||
5455 current_freq == 624000) {
5456 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5457 /* Timeout 200us */
5458 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5459 1))
5460 DRM_ERROR("timout waiting for DE PLL unlock\n");
5461 }
5462
5463 if (frequency != 19200) {
5464 uint32_t val;
5465
5466 val = I915_READ(BXT_DE_PLL_CTL);
5467 val &= ~BXT_DE_PLL_RATIO_MASK;
5468 val |= ratio;
5469 I915_WRITE(BXT_DE_PLL_CTL, val);
5470
5471 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5472 /* Timeout 200us */
5473 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5474 DRM_ERROR("timeout waiting for DE PLL lock\n");
5475
5476 val = I915_READ(CDCLK_CTL);
5477 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5478 val |= divider;
5479 /*
5480 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5481 * enable otherwise.
5482 */
5483 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5484 if (frequency >= 500000)
5485 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5486
5487 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5488 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5489 val |= (frequency - 1000) / 500;
5490 I915_WRITE(CDCLK_CTL, val);
5491 }
5492
5493 mutex_lock(&dev_priv->rps.hw_lock);
5494 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5495 DIV_ROUND_UP(frequency, 25000));
5496 mutex_unlock(&dev_priv->rps.hw_lock);
5497
5498 if (ret) {
5499 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5500 ret, frequency);
5501 return;
5502 }
5503
5504 intel_update_cdclk(dev);
5505 }
5506
5507 void broxton_init_cdclk(struct drm_device *dev)
5508 {
5509 struct drm_i915_private *dev_priv = dev->dev_private;
5510 uint32_t val;
5511
5512 /*
5513 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5514 * or else the reset will hang because there is no PCH to respond.
5515 * Move the handshake programming to initialization sequence.
5516 * Previously was left up to BIOS.
5517 */
5518 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5519 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5520 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5521
5522 /* Enable PG1 for cdclk */
5523 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5524
5525 /* check if cd clock is enabled */
5526 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5527 DRM_DEBUG_KMS("Display already initialized\n");
5528 return;
5529 }
5530
5531 /*
5532 * FIXME:
5533 * - The initial CDCLK needs to be read from VBT.
5534 * Need to make this change after VBT has changes for BXT.
5535 * - check if setting the max (or any) cdclk freq is really necessary
5536 * here, it belongs to modeset time
5537 */
5538 broxton_set_cdclk(dev, 624000);
5539
5540 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5541 POSTING_READ(DBUF_CTL);
5542
5543 udelay(10);
5544
5545 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5546 DRM_ERROR("DBuf power enable timeout!\n");
5547 }
5548
5549 void broxton_uninit_cdclk(struct drm_device *dev)
5550 {
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552
5553 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5554 POSTING_READ(DBUF_CTL);
5555
5556 udelay(10);
5557
5558 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5559 DRM_ERROR("DBuf power disable timeout!\n");
5560
5561 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5562 broxton_set_cdclk(dev, 19200);
5563
5564 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5565 }
5566
5567 static const struct skl_cdclk_entry {
5568 unsigned int freq;
5569 unsigned int vco;
5570 } skl_cdclk_frequencies[] = {
5571 { .freq = 308570, .vco = 8640 },
5572 { .freq = 337500, .vco = 8100 },
5573 { .freq = 432000, .vco = 8640 },
5574 { .freq = 450000, .vco = 8100 },
5575 { .freq = 540000, .vco = 8100 },
5576 { .freq = 617140, .vco = 8640 },
5577 { .freq = 675000, .vco = 8100 },
5578 };
5579
5580 static unsigned int skl_cdclk_decimal(unsigned int freq)
5581 {
5582 return (freq - 1000) / 500;
5583 }
5584
5585 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5586 {
5587 unsigned int i;
5588
5589 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5590 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5591
5592 if (e->freq == freq)
5593 return e->vco;
5594 }
5595
5596 return 8100;
5597 }
5598
5599 static void
5600 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5601 {
5602 unsigned int min_freq;
5603 u32 val;
5604
5605 /* select the minimum CDCLK before enabling DPLL 0 */
5606 val = I915_READ(CDCLK_CTL);
5607 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5608 val |= CDCLK_FREQ_337_308;
5609
5610 if (required_vco == 8640)
5611 min_freq = 308570;
5612 else
5613 min_freq = 337500;
5614
5615 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5616
5617 I915_WRITE(CDCLK_CTL, val);
5618 POSTING_READ(CDCLK_CTL);
5619
5620 /*
5621 * We always enable DPLL0 with the lowest link rate possible, but still
5622 * taking into account the VCO required to operate the eDP panel at the
5623 * desired frequency. The usual DP link rates operate with a VCO of
5624 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5625 * The modeset code is responsible for the selection of the exact link
5626 * rate later on, with the constraint of choosing a frequency that
5627 * works with required_vco.
5628 */
5629 val = I915_READ(DPLL_CTRL1);
5630
5631 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5632 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5633 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5634 if (required_vco == 8640)
5635 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5636 SKL_DPLL0);
5637 else
5638 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5639 SKL_DPLL0);
5640
5641 I915_WRITE(DPLL_CTRL1, val);
5642 POSTING_READ(DPLL_CTRL1);
5643
5644 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5645
5646 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5647 DRM_ERROR("DPLL0 not locked\n");
5648 }
5649
5650 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5651 {
5652 int ret;
5653 u32 val;
5654
5655 /* inform PCU we want to change CDCLK */
5656 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5657 mutex_lock(&dev_priv->rps.hw_lock);
5658 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5659 mutex_unlock(&dev_priv->rps.hw_lock);
5660
5661 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5662 }
5663
5664 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5665 {
5666 unsigned int i;
5667
5668 for (i = 0; i < 15; i++) {
5669 if (skl_cdclk_pcu_ready(dev_priv))
5670 return true;
5671 udelay(10);
5672 }
5673
5674 return false;
5675 }
5676
5677 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5678 {
5679 struct drm_device *dev = dev_priv->dev;
5680 u32 freq_select, pcu_ack;
5681
5682 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5683
5684 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5685 DRM_ERROR("failed to inform PCU about cdclk change\n");
5686 return;
5687 }
5688
5689 /* set CDCLK_CTL */
5690 switch(freq) {
5691 case 450000:
5692 case 432000:
5693 freq_select = CDCLK_FREQ_450_432;
5694 pcu_ack = 1;
5695 break;
5696 case 540000:
5697 freq_select = CDCLK_FREQ_540;
5698 pcu_ack = 2;
5699 break;
5700 case 308570:
5701 case 337500:
5702 default:
5703 freq_select = CDCLK_FREQ_337_308;
5704 pcu_ack = 0;
5705 break;
5706 case 617140:
5707 case 675000:
5708 freq_select = CDCLK_FREQ_675_617;
5709 pcu_ack = 3;
5710 break;
5711 }
5712
5713 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5714 POSTING_READ(CDCLK_CTL);
5715
5716 /* inform PCU of the change */
5717 mutex_lock(&dev_priv->rps.hw_lock);
5718 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5719 mutex_unlock(&dev_priv->rps.hw_lock);
5720
5721 intel_update_cdclk(dev);
5722 }
5723
5724 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5725 {
5726 /* disable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5733 DRM_ERROR("DBuf power disable timeout\n");
5734
5735 /* disable DPLL0 */
5736 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5737 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5738 DRM_ERROR("Couldn't disable DPLL0\n");
5739
5740 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5741 }
5742
5743 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5744 {
5745 u32 val;
5746 unsigned int required_vco;
5747
5748 /* enable PCH reset handshake */
5749 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5750 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5751
5752 /* enable PG1 and Misc I/O */
5753 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5754
5755 /* DPLL0 already enabed !? */
5756 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5757 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5758 return;
5759 }
5760
5761 /* enable DPLL0 */
5762 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5763 skl_dpll0_enable(dev_priv, required_vco);
5764
5765 /* set CDCLK to the frequency the BIOS chose */
5766 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5767
5768 /* enable DBUF power */
5769 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5770 POSTING_READ(DBUF_CTL);
5771
5772 udelay(10);
5773
5774 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5775 DRM_ERROR("DBuf power enable timeout\n");
5776 }
5777
5778 /* returns HPLL frequency in kHz */
5779 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5780 {
5781 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5782
5783 /* Obtain SKU information */
5784 mutex_lock(&dev_priv->sb_lock);
5785 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5786 CCK_FUSE_HPLL_FREQ_MASK;
5787 mutex_unlock(&dev_priv->sb_lock);
5788
5789 return vco_freq[hpll_freq] * 1000;
5790 }
5791
5792 /* Adjust CDclk dividers to allow high res or save power if possible */
5793 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5794 {
5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796 u32 val, cmd;
5797
5798 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5799 != dev_priv->cdclk_freq);
5800
5801 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5802 cmd = 2;
5803 else if (cdclk == 266667)
5804 cmd = 1;
5805 else
5806 cmd = 0;
5807
5808 mutex_lock(&dev_priv->rps.hw_lock);
5809 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5810 val &= ~DSPFREQGUAR_MASK;
5811 val |= (cmd << DSPFREQGUAR_SHIFT);
5812 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5813 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5814 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5815 50)) {
5816 DRM_ERROR("timed out waiting for CDclk change\n");
5817 }
5818 mutex_unlock(&dev_priv->rps.hw_lock);
5819
5820 mutex_lock(&dev_priv->sb_lock);
5821
5822 if (cdclk == 400000) {
5823 u32 divider;
5824
5825 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5826
5827 /* adjust cdclk divider */
5828 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5829 val &= ~DISPLAY_FREQUENCY_VALUES;
5830 val |= divider;
5831 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5832
5833 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5834 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5835 50))
5836 DRM_ERROR("timed out waiting for CDclk change\n");
5837 }
5838
5839 /* adjust self-refresh exit latency value */
5840 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5841 val &= ~0x7f;
5842
5843 /*
5844 * For high bandwidth configs, we set a higher latency in the bunit
5845 * so that the core display fetch happens in time to avoid underruns.
5846 */
5847 if (cdclk == 400000)
5848 val |= 4500 / 250; /* 4.5 usec */
5849 else
5850 val |= 3000 / 250; /* 3.0 usec */
5851 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5852
5853 mutex_unlock(&dev_priv->sb_lock);
5854
5855 intel_update_cdclk(dev);
5856 }
5857
5858 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5859 {
5860 struct drm_i915_private *dev_priv = dev->dev_private;
5861 u32 val, cmd;
5862
5863 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5864 != dev_priv->cdclk_freq);
5865
5866 switch (cdclk) {
5867 case 333333:
5868 case 320000:
5869 case 266667:
5870 case 200000:
5871 break;
5872 default:
5873 MISSING_CASE(cdclk);
5874 return;
5875 }
5876
5877 /*
5878 * Specs are full of misinformation, but testing on actual
5879 * hardware has shown that we just need to write the desired
5880 * CCK divider into the Punit register.
5881 */
5882 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5883
5884 mutex_lock(&dev_priv->rps.hw_lock);
5885 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5886 val &= ~DSPFREQGUAR_MASK_CHV;
5887 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5888 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5889 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5890 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5891 50)) {
5892 DRM_ERROR("timed out waiting for CDclk change\n");
5893 }
5894 mutex_unlock(&dev_priv->rps.hw_lock);
5895
5896 intel_update_cdclk(dev);
5897 }
5898
5899 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5900 int max_pixclk)
5901 {
5902 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5903 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5904
5905 /*
5906 * Really only a few cases to deal with, as only 4 CDclks are supported:
5907 * 200MHz
5908 * 267MHz
5909 * 320/333MHz (depends on HPLL freq)
5910 * 400MHz (VLV only)
5911 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5912 * of the lower bin and adjust if needed.
5913 *
5914 * We seem to get an unstable or solid color picture at 200MHz.
5915 * Not sure what's wrong. For now use 200MHz only when all pipes
5916 * are off.
5917 */
5918 if (!IS_CHERRYVIEW(dev_priv) &&
5919 max_pixclk > freq_320*limit/100)
5920 return 400000;
5921 else if (max_pixclk > 266667*limit/100)
5922 return freq_320;
5923 else if (max_pixclk > 0)
5924 return 266667;
5925 else
5926 return 200000;
5927 }
5928
5929 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5930 int max_pixclk)
5931 {
5932 /*
5933 * FIXME:
5934 * - remove the guardband, it's not needed on BXT
5935 * - set 19.2MHz bypass frequency if there are no active pipes
5936 */
5937 if (max_pixclk > 576000*9/10)
5938 return 624000;
5939 else if (max_pixclk > 384000*9/10)
5940 return 576000;
5941 else if (max_pixclk > 288000*9/10)
5942 return 384000;
5943 else if (max_pixclk > 144000*9/10)
5944 return 288000;
5945 else
5946 return 144000;
5947 }
5948
5949 /* Compute the max pixel clock for new configuration. Uses atomic state if
5950 * that's non-NULL, look at current state otherwise. */
5951 static int intel_mode_max_pixclk(struct drm_device *dev,
5952 struct drm_atomic_state *state)
5953 {
5954 struct intel_crtc *intel_crtc;
5955 struct intel_crtc_state *crtc_state;
5956 int max_pixclk = 0;
5957
5958 for_each_intel_crtc(dev, intel_crtc) {
5959 if (state)
5960 crtc_state =
5961 intel_atomic_get_crtc_state(state, intel_crtc);
5962 else
5963 crtc_state = intel_crtc->config;
5964 if (IS_ERR(crtc_state))
5965 return PTR_ERR(crtc_state);
5966
5967 if (!crtc_state->base.enable)
5968 continue;
5969
5970 max_pixclk = max(max_pixclk,
5971 crtc_state->base.adjusted_mode.crtc_clock);
5972 }
5973
5974 return max_pixclk;
5975 }
5976
5977 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5978 {
5979 struct drm_i915_private *dev_priv = to_i915(state->dev);
5980 struct drm_crtc *crtc;
5981 struct drm_crtc_state *crtc_state;
5982 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5983 int cdclk, ret = 0;
5984
5985 if (max_pixclk < 0)
5986 return max_pixclk;
5987
5988 if (IS_VALLEYVIEW(dev_priv))
5989 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5990 else
5991 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5992
5993 if (cdclk == dev_priv->cdclk_freq)
5994 return 0;
5995
5996 /* add all active pipes to the state */
5997 for_each_crtc(state->dev, crtc) {
5998 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5999 if (IS_ERR(crtc_state))
6000 return PTR_ERR(crtc_state);
6001
6002 if (!crtc_state->active || needs_modeset(crtc_state))
6003 continue;
6004
6005 crtc_state->mode_changed = true;
6006
6007 ret = drm_atomic_add_affected_connectors(state, crtc);
6008 if (ret)
6009 break;
6010
6011 ret = drm_atomic_add_affected_planes(state, crtc);
6012 if (ret)
6013 break;
6014 }
6015
6016 return ret;
6017 }
6018
6019 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6020 {
6021 unsigned int credits, default_credits;
6022
6023 if (IS_CHERRYVIEW(dev_priv))
6024 default_credits = PFI_CREDIT(12);
6025 else
6026 default_credits = PFI_CREDIT(8);
6027
6028 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
6029 /* CHV suggested value is 31 or 63 */
6030 if (IS_CHERRYVIEW(dev_priv))
6031 credits = PFI_CREDIT_63;
6032 else
6033 credits = PFI_CREDIT(15);
6034 } else {
6035 credits = default_credits;
6036 }
6037
6038 /*
6039 * WA - write default credits before re-programming
6040 * FIXME: should we also set the resend bit here?
6041 */
6042 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6043 default_credits);
6044
6045 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6046 credits | PFI_CREDIT_RESEND);
6047
6048 /*
6049 * FIXME is this guaranteed to clear
6050 * immediately or should we poll for it?
6051 */
6052 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6053 }
6054
6055 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6056 {
6057 struct drm_device *dev = old_state->dev;
6058 struct drm_i915_private *dev_priv = dev->dev_private;
6059 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6060 int req_cdclk;
6061
6062 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6063 * never fail. */
6064 if (WARN_ON(max_pixclk < 0))
6065 return;
6066
6067 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6068
6069 if (req_cdclk != dev_priv->cdclk_freq) {
6070 /*
6071 * FIXME: We can end up here with all power domains off, yet
6072 * with a CDCLK frequency other than the minimum. To account
6073 * for this take the PIPE-A power domain, which covers the HW
6074 * blocks needed for the following programming. This can be
6075 * removed once it's guaranteed that we get here either with
6076 * the minimum CDCLK set, or the required power domains
6077 * enabled.
6078 */
6079 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6080
6081 if (IS_CHERRYVIEW(dev))
6082 cherryview_set_cdclk(dev, req_cdclk);
6083 else
6084 valleyview_set_cdclk(dev, req_cdclk);
6085
6086 vlv_program_pfi_credits(dev_priv);
6087
6088 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6089 }
6090 }
6091
6092 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6093 {
6094 struct drm_device *dev = crtc->dev;
6095 struct drm_i915_private *dev_priv = to_i915(dev);
6096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6097 struct intel_encoder *encoder;
6098 int pipe = intel_crtc->pipe;
6099 bool is_dsi;
6100
6101 if (WARN_ON(intel_crtc->active))
6102 return;
6103
6104 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6105
6106 if (!is_dsi) {
6107 if (IS_CHERRYVIEW(dev))
6108 chv_prepare_pll(intel_crtc, intel_crtc->config);
6109 else
6110 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6111 }
6112
6113 if (intel_crtc->config->has_dp_encoder)
6114 intel_dp_set_m_n(intel_crtc, M1_N1);
6115
6116 intel_set_pipe_timings(intel_crtc);
6117
6118 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6119 struct drm_i915_private *dev_priv = dev->dev_private;
6120
6121 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6122 I915_WRITE(CHV_CANVAS(pipe), 0);
6123 }
6124
6125 i9xx_set_pipeconf(intel_crtc);
6126
6127 intel_crtc->active = true;
6128
6129 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6130
6131 for_each_encoder_on_crtc(dev, crtc, encoder)
6132 if (encoder->pre_pll_enable)
6133 encoder->pre_pll_enable(encoder);
6134
6135 if (!is_dsi) {
6136 if (IS_CHERRYVIEW(dev))
6137 chv_enable_pll(intel_crtc, intel_crtc->config);
6138 else
6139 vlv_enable_pll(intel_crtc, intel_crtc->config);
6140 }
6141
6142 for_each_encoder_on_crtc(dev, crtc, encoder)
6143 if (encoder->pre_enable)
6144 encoder->pre_enable(encoder);
6145
6146 i9xx_pfit_enable(intel_crtc);
6147
6148 intel_crtc_load_lut(crtc);
6149
6150 intel_update_watermarks(crtc);
6151 intel_enable_pipe(intel_crtc);
6152
6153 assert_vblank_disabled(crtc);
6154 drm_crtc_vblank_on(crtc);
6155
6156 for_each_encoder_on_crtc(dev, crtc, encoder)
6157 encoder->enable(encoder);
6158 }
6159
6160 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6161 {
6162 struct drm_device *dev = crtc->base.dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164
6165 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6166 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6167 }
6168
6169 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6170 {
6171 struct drm_device *dev = crtc->dev;
6172 struct drm_i915_private *dev_priv = to_i915(dev);
6173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6174 struct intel_encoder *encoder;
6175 int pipe = intel_crtc->pipe;
6176
6177 if (WARN_ON(intel_crtc->active))
6178 return;
6179
6180 i9xx_set_pll_dividers(intel_crtc);
6181
6182 if (intel_crtc->config->has_dp_encoder)
6183 intel_dp_set_m_n(intel_crtc, M1_N1);
6184
6185 intel_set_pipe_timings(intel_crtc);
6186
6187 i9xx_set_pipeconf(intel_crtc);
6188
6189 intel_crtc->active = true;
6190
6191 if (!IS_GEN2(dev))
6192 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6193
6194 for_each_encoder_on_crtc(dev, crtc, encoder)
6195 if (encoder->pre_enable)
6196 encoder->pre_enable(encoder);
6197
6198 i9xx_enable_pll(intel_crtc);
6199
6200 i9xx_pfit_enable(intel_crtc);
6201
6202 intel_crtc_load_lut(crtc);
6203
6204 intel_update_watermarks(crtc);
6205 intel_enable_pipe(intel_crtc);
6206
6207 assert_vblank_disabled(crtc);
6208 drm_crtc_vblank_on(crtc);
6209
6210 for_each_encoder_on_crtc(dev, crtc, encoder)
6211 encoder->enable(encoder);
6212 }
6213
6214 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6215 {
6216 struct drm_device *dev = crtc->base.dev;
6217 struct drm_i915_private *dev_priv = dev->dev_private;
6218
6219 if (!crtc->config->gmch_pfit.control)
6220 return;
6221
6222 assert_pipe_disabled(dev_priv, crtc->pipe);
6223
6224 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6225 I915_READ(PFIT_CONTROL));
6226 I915_WRITE(PFIT_CONTROL, 0);
6227 }
6228
6229 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6230 {
6231 struct drm_device *dev = crtc->dev;
6232 struct drm_i915_private *dev_priv = dev->dev_private;
6233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6234 struct intel_encoder *encoder;
6235 int pipe = intel_crtc->pipe;
6236
6237 if (WARN_ON(!intel_crtc->active))
6238 return;
6239
6240 /*
6241 * On gen2 planes are double buffered but the pipe isn't, so we must
6242 * wait for planes to fully turn off before disabling the pipe.
6243 * We also need to wait on all gmch platforms because of the
6244 * self-refresh mode constraint explained above.
6245 */
6246 intel_wait_for_vblank(dev, pipe);
6247
6248 for_each_encoder_on_crtc(dev, crtc, encoder)
6249 encoder->disable(encoder);
6250
6251 drm_crtc_vblank_off(crtc);
6252 assert_vblank_disabled(crtc);
6253
6254 intel_disable_pipe(intel_crtc);
6255
6256 i9xx_pfit_disable(intel_crtc);
6257
6258 for_each_encoder_on_crtc(dev, crtc, encoder)
6259 if (encoder->post_disable)
6260 encoder->post_disable(encoder);
6261
6262 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6263 if (IS_CHERRYVIEW(dev))
6264 chv_disable_pll(dev_priv, pipe);
6265 else if (IS_VALLEYVIEW(dev))
6266 vlv_disable_pll(dev_priv, pipe);
6267 else
6268 i9xx_disable_pll(intel_crtc);
6269 }
6270
6271 if (!IS_GEN2(dev))
6272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6273
6274 intel_crtc->active = false;
6275 intel_update_watermarks(crtc);
6276
6277 mutex_lock(&dev->struct_mutex);
6278 intel_fbc_update(dev);
6279 mutex_unlock(&dev->struct_mutex);
6280 }
6281
6282 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6283 {
6284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6285 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6286 enum intel_display_power_domain domain;
6287 unsigned long domains;
6288
6289 if (!intel_crtc->active)
6290 return;
6291
6292 intel_crtc_disable_planes(crtc);
6293 dev_priv->display.crtc_disable(crtc);
6294
6295 domains = intel_crtc->enabled_power_domains;
6296 for_each_power_domain(domain, domains)
6297 intel_display_power_put(dev_priv, domain);
6298 intel_crtc->enabled_power_domains = 0;
6299 }
6300
6301 /*
6302 * turn all crtc's off, but do not adjust state
6303 * This has to be paired with a call to intel_modeset_setup_hw_state.
6304 */
6305 void intel_display_suspend(struct drm_device *dev)
6306 {
6307 struct drm_crtc *crtc;
6308
6309 for_each_crtc(dev, crtc)
6310 intel_crtc_disable_noatomic(crtc);
6311 }
6312
6313 /* Master function to enable/disable CRTC and corresponding power wells */
6314 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6315 {
6316 struct drm_device *dev = crtc->dev;
6317 struct drm_mode_config *config = &dev->mode_config;
6318 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6320 struct intel_crtc_state *pipe_config;
6321 struct drm_atomic_state *state;
6322 int ret;
6323
6324 if (enable == intel_crtc->active)
6325 return 0;
6326
6327 if (enable && !crtc->state->enable)
6328 return 0;
6329
6330 /* this function should be called with drm_modeset_lock_all for now */
6331 if (WARN_ON(!ctx))
6332 return -EIO;
6333 lockdep_assert_held(&ctx->ww_ctx);
6334
6335 state = drm_atomic_state_alloc(dev);
6336 if (WARN_ON(!state))
6337 return -ENOMEM;
6338
6339 state->acquire_ctx = ctx;
6340 state->allow_modeset = true;
6341
6342 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6343 if (IS_ERR(pipe_config)) {
6344 ret = PTR_ERR(pipe_config);
6345 goto err;
6346 }
6347 pipe_config->base.active = enable;
6348
6349 ret = intel_set_mode(state);
6350 if (!ret)
6351 return ret;
6352
6353 err:
6354 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6355 drm_atomic_state_free(state);
6356 return ret;
6357 }
6358
6359 /**
6360 * Sets the power management mode of the pipe and plane.
6361 */
6362 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6363 {
6364 struct drm_device *dev = crtc->dev;
6365 struct intel_encoder *intel_encoder;
6366 bool enable = false;
6367
6368 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6369 enable |= intel_encoder->connectors_active;
6370
6371 intel_crtc_control(crtc, enable);
6372 }
6373
6374 void intel_encoder_destroy(struct drm_encoder *encoder)
6375 {
6376 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6377
6378 drm_encoder_cleanup(encoder);
6379 kfree(intel_encoder);
6380 }
6381
6382 /* Simple dpms helper for encoders with just one connector, no cloning and only
6383 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6384 * state of the entire output pipe. */
6385 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6386 {
6387 if (mode == DRM_MODE_DPMS_ON) {
6388 encoder->connectors_active = true;
6389
6390 intel_crtc_update_dpms(encoder->base.crtc);
6391 } else {
6392 encoder->connectors_active = false;
6393
6394 intel_crtc_update_dpms(encoder->base.crtc);
6395 }
6396 }
6397
6398 /* Cross check the actual hw state with our own modeset state tracking (and it's
6399 * internal consistency). */
6400 static void intel_connector_check_state(struct intel_connector *connector)
6401 {
6402 if (connector->get_hw_state(connector)) {
6403 struct intel_encoder *encoder = connector->encoder;
6404 struct drm_crtc *crtc;
6405 bool encoder_enabled;
6406 enum pipe pipe;
6407
6408 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6409 connector->base.base.id,
6410 connector->base.name);
6411
6412 /* there is no real hw state for MST connectors */
6413 if (connector->mst_port)
6414 return;
6415
6416 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6417 "wrong connector dpms state\n");
6418 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6419 "active connector not linked to encoder\n");
6420
6421 if (encoder) {
6422 I915_STATE_WARN(!encoder->connectors_active,
6423 "encoder->connectors_active not set\n");
6424
6425 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6426 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6427 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6428 return;
6429
6430 crtc = encoder->base.crtc;
6431
6432 I915_STATE_WARN(!crtc->state->enable,
6433 "crtc not enabled\n");
6434 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6435 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6436 "encoder active on the wrong pipe\n");
6437 }
6438 }
6439 }
6440
6441 int intel_connector_init(struct intel_connector *connector)
6442 {
6443 struct drm_connector_state *connector_state;
6444
6445 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6446 if (!connector_state)
6447 return -ENOMEM;
6448
6449 connector->base.state = connector_state;
6450 return 0;
6451 }
6452
6453 struct intel_connector *intel_connector_alloc(void)
6454 {
6455 struct intel_connector *connector;
6456
6457 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6458 if (!connector)
6459 return NULL;
6460
6461 if (intel_connector_init(connector) < 0) {
6462 kfree(connector);
6463 return NULL;
6464 }
6465
6466 return connector;
6467 }
6468
6469 /* Even simpler default implementation, if there's really no special case to
6470 * consider. */
6471 void intel_connector_dpms(struct drm_connector *connector, int mode)
6472 {
6473 /* All the simple cases only support two dpms states. */
6474 if (mode != DRM_MODE_DPMS_ON)
6475 mode = DRM_MODE_DPMS_OFF;
6476
6477 if (mode == connector->dpms)
6478 return;
6479
6480 connector->dpms = mode;
6481
6482 /* Only need to change hw state when actually enabled */
6483 if (connector->encoder)
6484 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6485
6486 intel_modeset_check_state(connector->dev);
6487 }
6488
6489 /* Simple connector->get_hw_state implementation for encoders that support only
6490 * one connector and no cloning and hence the encoder state determines the state
6491 * of the connector. */
6492 bool intel_connector_get_hw_state(struct intel_connector *connector)
6493 {
6494 enum pipe pipe = 0;
6495 struct intel_encoder *encoder = connector->encoder;
6496
6497 return encoder->get_hw_state(encoder, &pipe);
6498 }
6499
6500 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6501 {
6502 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6503 return crtc_state->fdi_lanes;
6504
6505 return 0;
6506 }
6507
6508 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6509 struct intel_crtc_state *pipe_config)
6510 {
6511 struct drm_atomic_state *state = pipe_config->base.state;
6512 struct intel_crtc *other_crtc;
6513 struct intel_crtc_state *other_crtc_state;
6514
6515 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6516 pipe_name(pipe), pipe_config->fdi_lanes);
6517 if (pipe_config->fdi_lanes > 4) {
6518 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6519 pipe_name(pipe), pipe_config->fdi_lanes);
6520 return -EINVAL;
6521 }
6522
6523 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6524 if (pipe_config->fdi_lanes > 2) {
6525 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6526 pipe_config->fdi_lanes);
6527 return -EINVAL;
6528 } else {
6529 return 0;
6530 }
6531 }
6532
6533 if (INTEL_INFO(dev)->num_pipes == 2)
6534 return 0;
6535
6536 /* Ivybridge 3 pipe is really complicated */
6537 switch (pipe) {
6538 case PIPE_A:
6539 return 0;
6540 case PIPE_B:
6541 if (pipe_config->fdi_lanes <= 2)
6542 return 0;
6543
6544 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6545 other_crtc_state =
6546 intel_atomic_get_crtc_state(state, other_crtc);
6547 if (IS_ERR(other_crtc_state))
6548 return PTR_ERR(other_crtc_state);
6549
6550 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6551 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6552 pipe_name(pipe), pipe_config->fdi_lanes);
6553 return -EINVAL;
6554 }
6555 return 0;
6556 case PIPE_C:
6557 if (pipe_config->fdi_lanes > 2) {
6558 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6559 pipe_name(pipe), pipe_config->fdi_lanes);
6560 return -EINVAL;
6561 }
6562
6563 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6564 other_crtc_state =
6565 intel_atomic_get_crtc_state(state, other_crtc);
6566 if (IS_ERR(other_crtc_state))
6567 return PTR_ERR(other_crtc_state);
6568
6569 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6570 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6571 return -EINVAL;
6572 }
6573 return 0;
6574 default:
6575 BUG();
6576 }
6577 }
6578
6579 #define RETRY 1
6580 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6581 struct intel_crtc_state *pipe_config)
6582 {
6583 struct drm_device *dev = intel_crtc->base.dev;
6584 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6585 int lane, link_bw, fdi_dotclock, ret;
6586 bool needs_recompute = false;
6587
6588 retry:
6589 /* FDI is a binary signal running at ~2.7GHz, encoding
6590 * each output octet as 10 bits. The actual frequency
6591 * is stored as a divider into a 100MHz clock, and the
6592 * mode pixel clock is stored in units of 1KHz.
6593 * Hence the bw of each lane in terms of the mode signal
6594 * is:
6595 */
6596 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6597
6598 fdi_dotclock = adjusted_mode->crtc_clock;
6599
6600 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6601 pipe_config->pipe_bpp);
6602
6603 pipe_config->fdi_lanes = lane;
6604
6605 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6606 link_bw, &pipe_config->fdi_m_n);
6607
6608 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6609 intel_crtc->pipe, pipe_config);
6610 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6611 pipe_config->pipe_bpp -= 2*3;
6612 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6613 pipe_config->pipe_bpp);
6614 needs_recompute = true;
6615 pipe_config->bw_constrained = true;
6616
6617 goto retry;
6618 }
6619
6620 if (needs_recompute)
6621 return RETRY;
6622
6623 return ret;
6624 }
6625
6626 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6627 struct intel_crtc_state *pipe_config)
6628 {
6629 if (pipe_config->pipe_bpp > 24)
6630 return false;
6631
6632 /* HSW can handle pixel rate up to cdclk? */
6633 if (IS_HASWELL(dev_priv->dev))
6634 return true;
6635
6636 /*
6637 * We compare against max which means we must take
6638 * the increased cdclk requirement into account when
6639 * calculating the new cdclk.
6640 *
6641 * Should measure whether using a lower cdclk w/o IPS
6642 */
6643 return ilk_pipe_pixel_rate(pipe_config) <=
6644 dev_priv->max_cdclk_freq * 95 / 100;
6645 }
6646
6647 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6648 struct intel_crtc_state *pipe_config)
6649 {
6650 struct drm_device *dev = crtc->base.dev;
6651 struct drm_i915_private *dev_priv = dev->dev_private;
6652
6653 pipe_config->ips_enabled = i915.enable_ips &&
6654 hsw_crtc_supports_ips(crtc) &&
6655 pipe_config_supports_ips(dev_priv, pipe_config);
6656 }
6657
6658 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6659 struct intel_crtc_state *pipe_config)
6660 {
6661 struct drm_device *dev = crtc->base.dev;
6662 struct drm_i915_private *dev_priv = dev->dev_private;
6663 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6664
6665 /* FIXME should check pixel clock limits on all platforms */
6666 if (INTEL_INFO(dev)->gen < 4) {
6667 int clock_limit = dev_priv->max_cdclk_freq;
6668
6669 /*
6670 * Enable pixel doubling when the dot clock
6671 * is > 90% of the (display) core speed.
6672 *
6673 * GDG double wide on either pipe,
6674 * otherwise pipe A only.
6675 */
6676 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6677 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6678 clock_limit *= 2;
6679 pipe_config->double_wide = true;
6680 }
6681
6682 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6683 return -EINVAL;
6684 }
6685
6686 /*
6687 * Pipe horizontal size must be even in:
6688 * - DVO ganged mode
6689 * - LVDS dual channel mode
6690 * - Double wide pipe
6691 */
6692 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6693 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6694 pipe_config->pipe_src_w &= ~1;
6695
6696 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6697 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6698 */
6699 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6700 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6701 return -EINVAL;
6702
6703 if (HAS_IPS(dev))
6704 hsw_compute_ips_config(crtc, pipe_config);
6705
6706 if (pipe_config->has_pch_encoder)
6707 return ironlake_fdi_compute_config(crtc, pipe_config);
6708
6709 return 0;
6710 }
6711
6712 static int skylake_get_display_clock_speed(struct drm_device *dev)
6713 {
6714 struct drm_i915_private *dev_priv = to_i915(dev);
6715 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6716 uint32_t cdctl = I915_READ(CDCLK_CTL);
6717 uint32_t linkrate;
6718
6719 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6720 return 24000; /* 24MHz is the cd freq with NSSC ref */
6721
6722 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6723 return 540000;
6724
6725 linkrate = (I915_READ(DPLL_CTRL1) &
6726 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6727
6728 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6729 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6730 /* vco 8640 */
6731 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6732 case CDCLK_FREQ_450_432:
6733 return 432000;
6734 case CDCLK_FREQ_337_308:
6735 return 308570;
6736 case CDCLK_FREQ_675_617:
6737 return 617140;
6738 default:
6739 WARN(1, "Unknown cd freq selection\n");
6740 }
6741 } else {
6742 /* vco 8100 */
6743 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6744 case CDCLK_FREQ_450_432:
6745 return 450000;
6746 case CDCLK_FREQ_337_308:
6747 return 337500;
6748 case CDCLK_FREQ_675_617:
6749 return 675000;
6750 default:
6751 WARN(1, "Unknown cd freq selection\n");
6752 }
6753 }
6754
6755 /* error case, do as if DPLL0 isn't enabled */
6756 return 24000;
6757 }
6758
6759 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6760 {
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 uint32_t lcpll = I915_READ(LCPLL_CTL);
6763 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6764
6765 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6766 return 800000;
6767 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6768 return 450000;
6769 else if (freq == LCPLL_CLK_FREQ_450)
6770 return 450000;
6771 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6772 return 540000;
6773 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6774 return 337500;
6775 else
6776 return 675000;
6777 }
6778
6779 static int haswell_get_display_clock_speed(struct drm_device *dev)
6780 {
6781 struct drm_i915_private *dev_priv = dev->dev_private;
6782 uint32_t lcpll = I915_READ(LCPLL_CTL);
6783 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6784
6785 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6786 return 800000;
6787 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6788 return 450000;
6789 else if (freq == LCPLL_CLK_FREQ_450)
6790 return 450000;
6791 else if (IS_HSW_ULT(dev))
6792 return 337500;
6793 else
6794 return 540000;
6795 }
6796
6797 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6798 {
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6800 u32 val;
6801 int divider;
6802
6803 if (dev_priv->hpll_freq == 0)
6804 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6805
6806 mutex_lock(&dev_priv->sb_lock);
6807 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6808 mutex_unlock(&dev_priv->sb_lock);
6809
6810 divider = val & DISPLAY_FREQUENCY_VALUES;
6811
6812 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6813 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6814 "cdclk change in progress\n");
6815
6816 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6817 }
6818
6819 static int ilk_get_display_clock_speed(struct drm_device *dev)
6820 {
6821 return 450000;
6822 }
6823
6824 static int i945_get_display_clock_speed(struct drm_device *dev)
6825 {
6826 return 400000;
6827 }
6828
6829 static int i915_get_display_clock_speed(struct drm_device *dev)
6830 {
6831 return 333333;
6832 }
6833
6834 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6835 {
6836 return 200000;
6837 }
6838
6839 static int pnv_get_display_clock_speed(struct drm_device *dev)
6840 {
6841 u16 gcfgc = 0;
6842
6843 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6844
6845 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6846 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6847 return 266667;
6848 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6849 return 333333;
6850 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6851 return 444444;
6852 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6853 return 200000;
6854 default:
6855 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6856 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6857 return 133333;
6858 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6859 return 166667;
6860 }
6861 }
6862
6863 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6864 {
6865 u16 gcfgc = 0;
6866
6867 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6868
6869 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6870 return 133333;
6871 else {
6872 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6873 case GC_DISPLAY_CLOCK_333_MHZ:
6874 return 333333;
6875 default:
6876 case GC_DISPLAY_CLOCK_190_200_MHZ:
6877 return 190000;
6878 }
6879 }
6880 }
6881
6882 static int i865_get_display_clock_speed(struct drm_device *dev)
6883 {
6884 return 266667;
6885 }
6886
6887 static int i85x_get_display_clock_speed(struct drm_device *dev)
6888 {
6889 u16 hpllcc = 0;
6890
6891 /*
6892 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6893 * encoding is different :(
6894 * FIXME is this the right way to detect 852GM/852GMV?
6895 */
6896 if (dev->pdev->revision == 0x1)
6897 return 133333;
6898
6899 pci_bus_read_config_word(dev->pdev->bus,
6900 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6901
6902 /* Assume that the hardware is in the high speed state. This
6903 * should be the default.
6904 */
6905 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6906 case GC_CLOCK_133_200:
6907 case GC_CLOCK_133_200_2:
6908 case GC_CLOCK_100_200:
6909 return 200000;
6910 case GC_CLOCK_166_250:
6911 return 250000;
6912 case GC_CLOCK_100_133:
6913 return 133333;
6914 case GC_CLOCK_133_266:
6915 case GC_CLOCK_133_266_2:
6916 case GC_CLOCK_166_266:
6917 return 266667;
6918 }
6919
6920 /* Shouldn't happen */
6921 return 0;
6922 }
6923
6924 static int i830_get_display_clock_speed(struct drm_device *dev)
6925 {
6926 return 133333;
6927 }
6928
6929 static unsigned int intel_hpll_vco(struct drm_device *dev)
6930 {
6931 struct drm_i915_private *dev_priv = dev->dev_private;
6932 static const unsigned int blb_vco[8] = {
6933 [0] = 3200000,
6934 [1] = 4000000,
6935 [2] = 5333333,
6936 [3] = 4800000,
6937 [4] = 6400000,
6938 };
6939 static const unsigned int pnv_vco[8] = {
6940 [0] = 3200000,
6941 [1] = 4000000,
6942 [2] = 5333333,
6943 [3] = 4800000,
6944 [4] = 2666667,
6945 };
6946 static const unsigned int cl_vco[8] = {
6947 [0] = 3200000,
6948 [1] = 4000000,
6949 [2] = 5333333,
6950 [3] = 6400000,
6951 [4] = 3333333,
6952 [5] = 3566667,
6953 [6] = 4266667,
6954 };
6955 static const unsigned int elk_vco[8] = {
6956 [0] = 3200000,
6957 [1] = 4000000,
6958 [2] = 5333333,
6959 [3] = 4800000,
6960 };
6961 static const unsigned int ctg_vco[8] = {
6962 [0] = 3200000,
6963 [1] = 4000000,
6964 [2] = 5333333,
6965 [3] = 6400000,
6966 [4] = 2666667,
6967 [5] = 4266667,
6968 };
6969 const unsigned int *vco_table;
6970 unsigned int vco;
6971 uint8_t tmp = 0;
6972
6973 /* FIXME other chipsets? */
6974 if (IS_GM45(dev))
6975 vco_table = ctg_vco;
6976 else if (IS_G4X(dev))
6977 vco_table = elk_vco;
6978 else if (IS_CRESTLINE(dev))
6979 vco_table = cl_vco;
6980 else if (IS_PINEVIEW(dev))
6981 vco_table = pnv_vco;
6982 else if (IS_G33(dev))
6983 vco_table = blb_vco;
6984 else
6985 return 0;
6986
6987 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6988
6989 vco = vco_table[tmp & 0x7];
6990 if (vco == 0)
6991 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6992 else
6993 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6994
6995 return vco;
6996 }
6997
6998 static int gm45_get_display_clock_speed(struct drm_device *dev)
6999 {
7000 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7001 uint16_t tmp = 0;
7002
7003 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7004
7005 cdclk_sel = (tmp >> 12) & 0x1;
7006
7007 switch (vco) {
7008 case 2666667:
7009 case 4000000:
7010 case 5333333:
7011 return cdclk_sel ? 333333 : 222222;
7012 case 3200000:
7013 return cdclk_sel ? 320000 : 228571;
7014 default:
7015 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7016 return 222222;
7017 }
7018 }
7019
7020 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7021 {
7022 static const uint8_t div_3200[] = { 16, 10, 8 };
7023 static const uint8_t div_4000[] = { 20, 12, 10 };
7024 static const uint8_t div_5333[] = { 24, 16, 14 };
7025 const uint8_t *div_table;
7026 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7027 uint16_t tmp = 0;
7028
7029 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7030
7031 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7032
7033 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7034 goto fail;
7035
7036 switch (vco) {
7037 case 3200000:
7038 div_table = div_3200;
7039 break;
7040 case 4000000:
7041 div_table = div_4000;
7042 break;
7043 case 5333333:
7044 div_table = div_5333;
7045 break;
7046 default:
7047 goto fail;
7048 }
7049
7050 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7051
7052 fail:
7053 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7054 return 200000;
7055 }
7056
7057 static int g33_get_display_clock_speed(struct drm_device *dev)
7058 {
7059 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7060 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7061 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7062 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7063 const uint8_t *div_table;
7064 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7065 uint16_t tmp = 0;
7066
7067 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7068
7069 cdclk_sel = (tmp >> 4) & 0x7;
7070
7071 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7072 goto fail;
7073
7074 switch (vco) {
7075 case 3200000:
7076 div_table = div_3200;
7077 break;
7078 case 4000000:
7079 div_table = div_4000;
7080 break;
7081 case 4800000:
7082 div_table = div_4800;
7083 break;
7084 case 5333333:
7085 div_table = div_5333;
7086 break;
7087 default:
7088 goto fail;
7089 }
7090
7091 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7092
7093 fail:
7094 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7095 return 190476;
7096 }
7097
7098 static void
7099 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7100 {
7101 while (*num > DATA_LINK_M_N_MASK ||
7102 *den > DATA_LINK_M_N_MASK) {
7103 *num >>= 1;
7104 *den >>= 1;
7105 }
7106 }
7107
7108 static void compute_m_n(unsigned int m, unsigned int n,
7109 uint32_t *ret_m, uint32_t *ret_n)
7110 {
7111 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7112 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7113 intel_reduce_m_n_ratio(ret_m, ret_n);
7114 }
7115
7116 void
7117 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7118 int pixel_clock, int link_clock,
7119 struct intel_link_m_n *m_n)
7120 {
7121 m_n->tu = 64;
7122
7123 compute_m_n(bits_per_pixel * pixel_clock,
7124 link_clock * nlanes * 8,
7125 &m_n->gmch_m, &m_n->gmch_n);
7126
7127 compute_m_n(pixel_clock, link_clock,
7128 &m_n->link_m, &m_n->link_n);
7129 }
7130
7131 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7132 {
7133 if (i915.panel_use_ssc >= 0)
7134 return i915.panel_use_ssc != 0;
7135 return dev_priv->vbt.lvds_use_ssc
7136 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7137 }
7138
7139 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7140 int num_connectors)
7141 {
7142 struct drm_device *dev = crtc_state->base.crtc->dev;
7143 struct drm_i915_private *dev_priv = dev->dev_private;
7144 int refclk;
7145
7146 WARN_ON(!crtc_state->base.state);
7147
7148 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7149 refclk = 100000;
7150 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7151 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7152 refclk = dev_priv->vbt.lvds_ssc_freq;
7153 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7154 } else if (!IS_GEN2(dev)) {
7155 refclk = 96000;
7156 } else {
7157 refclk = 48000;
7158 }
7159
7160 return refclk;
7161 }
7162
7163 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7164 {
7165 return (1 << dpll->n) << 16 | dpll->m2;
7166 }
7167
7168 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7169 {
7170 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7171 }
7172
7173 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7174 struct intel_crtc_state *crtc_state,
7175 intel_clock_t *reduced_clock)
7176 {
7177 struct drm_device *dev = crtc->base.dev;
7178 u32 fp, fp2 = 0;
7179
7180 if (IS_PINEVIEW(dev)) {
7181 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7182 if (reduced_clock)
7183 fp2 = pnv_dpll_compute_fp(reduced_clock);
7184 } else {
7185 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7186 if (reduced_clock)
7187 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7188 }
7189
7190 crtc_state->dpll_hw_state.fp0 = fp;
7191
7192 crtc->lowfreq_avail = false;
7193 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7194 reduced_clock) {
7195 crtc_state->dpll_hw_state.fp1 = fp2;
7196 crtc->lowfreq_avail = true;
7197 } else {
7198 crtc_state->dpll_hw_state.fp1 = fp;
7199 }
7200 }
7201
7202 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7203 pipe)
7204 {
7205 u32 reg_val;
7206
7207 /*
7208 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7209 * and set it to a reasonable value instead.
7210 */
7211 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7212 reg_val &= 0xffffff00;
7213 reg_val |= 0x00000030;
7214 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7215
7216 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7217 reg_val &= 0x8cffffff;
7218 reg_val = 0x8c000000;
7219 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7220
7221 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7222 reg_val &= 0xffffff00;
7223 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7224
7225 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7226 reg_val &= 0x00ffffff;
7227 reg_val |= 0xb0000000;
7228 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7229 }
7230
7231 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7232 struct intel_link_m_n *m_n)
7233 {
7234 struct drm_device *dev = crtc->base.dev;
7235 struct drm_i915_private *dev_priv = dev->dev_private;
7236 int pipe = crtc->pipe;
7237
7238 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7239 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7240 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7241 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7242 }
7243
7244 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7245 struct intel_link_m_n *m_n,
7246 struct intel_link_m_n *m2_n2)
7247 {
7248 struct drm_device *dev = crtc->base.dev;
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 int pipe = crtc->pipe;
7251 enum transcoder transcoder = crtc->config->cpu_transcoder;
7252
7253 if (INTEL_INFO(dev)->gen >= 5) {
7254 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7255 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7256 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7257 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7258 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7259 * for gen < 8) and if DRRS is supported (to make sure the
7260 * registers are not unnecessarily accessed).
7261 */
7262 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7263 crtc->config->has_drrs) {
7264 I915_WRITE(PIPE_DATA_M2(transcoder),
7265 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7266 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7267 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7268 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7269 }
7270 } else {
7271 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7272 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7273 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7274 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7275 }
7276 }
7277
7278 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7279 {
7280 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7281
7282 if (m_n == M1_N1) {
7283 dp_m_n = &crtc->config->dp_m_n;
7284 dp_m2_n2 = &crtc->config->dp_m2_n2;
7285 } else if (m_n == M2_N2) {
7286
7287 /*
7288 * M2_N2 registers are not supported. Hence m2_n2 divider value
7289 * needs to be programmed into M1_N1.
7290 */
7291 dp_m_n = &crtc->config->dp_m2_n2;
7292 } else {
7293 DRM_ERROR("Unsupported divider value\n");
7294 return;
7295 }
7296
7297 if (crtc->config->has_pch_encoder)
7298 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7299 else
7300 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7301 }
7302
7303 static void vlv_update_pll(struct intel_crtc *crtc,
7304 struct intel_crtc_state *pipe_config)
7305 {
7306 u32 dpll, dpll_md;
7307
7308 /*
7309 * Enable DPIO clock input. We should never disable the reference
7310 * clock for pipe B, since VGA hotplug / manual detection depends
7311 * on it.
7312 */
7313 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7314 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7315 /* We should never disable this, set it here for state tracking */
7316 if (crtc->pipe == PIPE_B)
7317 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7318 dpll |= DPLL_VCO_ENABLE;
7319 pipe_config->dpll_hw_state.dpll = dpll;
7320
7321 dpll_md = (pipe_config->pixel_multiplier - 1)
7322 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7323 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7324 }
7325
7326 static void vlv_prepare_pll(struct intel_crtc *crtc,
7327 const struct intel_crtc_state *pipe_config)
7328 {
7329 struct drm_device *dev = crtc->base.dev;
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 int pipe = crtc->pipe;
7332 u32 mdiv;
7333 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7334 u32 coreclk, reg_val;
7335
7336 mutex_lock(&dev_priv->sb_lock);
7337
7338 bestn = pipe_config->dpll.n;
7339 bestm1 = pipe_config->dpll.m1;
7340 bestm2 = pipe_config->dpll.m2;
7341 bestp1 = pipe_config->dpll.p1;
7342 bestp2 = pipe_config->dpll.p2;
7343
7344 /* See eDP HDMI DPIO driver vbios notes doc */
7345
7346 /* PLL B needs special handling */
7347 if (pipe == PIPE_B)
7348 vlv_pllb_recal_opamp(dev_priv, pipe);
7349
7350 /* Set up Tx target for periodic Rcomp update */
7351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7352
7353 /* Disable target IRef on PLL */
7354 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7355 reg_val &= 0x00ffffff;
7356 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7357
7358 /* Disable fast lock */
7359 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7360
7361 /* Set idtafcrecal before PLL is enabled */
7362 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7363 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7364 mdiv |= ((bestn << DPIO_N_SHIFT));
7365 mdiv |= (1 << DPIO_K_SHIFT);
7366
7367 /*
7368 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7369 * but we don't support that).
7370 * Note: don't use the DAC post divider as it seems unstable.
7371 */
7372 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7373 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7374
7375 mdiv |= DPIO_ENABLE_CALIBRATION;
7376 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7377
7378 /* Set HBR and RBR LPF coefficients */
7379 if (pipe_config->port_clock == 162000 ||
7380 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7381 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7383 0x009f0003);
7384 else
7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7386 0x00d0000f);
7387
7388 if (pipe_config->has_dp_encoder) {
7389 /* Use SSC source */
7390 if (pipe == PIPE_A)
7391 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7392 0x0df40000);
7393 else
7394 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7395 0x0df70000);
7396 } else { /* HDMI or VGA */
7397 /* Use bend source */
7398 if (pipe == PIPE_A)
7399 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7400 0x0df70000);
7401 else
7402 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7403 0x0df40000);
7404 }
7405
7406 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7407 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7409 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7410 coreclk |= 0x01000000;
7411 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7412
7413 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7414 mutex_unlock(&dev_priv->sb_lock);
7415 }
7416
7417 static void chv_update_pll(struct intel_crtc *crtc,
7418 struct intel_crtc_state *pipe_config)
7419 {
7420 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7421 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7422 DPLL_VCO_ENABLE;
7423 if (crtc->pipe != PIPE_A)
7424 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7425
7426 pipe_config->dpll_hw_state.dpll_md =
7427 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7428 }
7429
7430 static void chv_prepare_pll(struct intel_crtc *crtc,
7431 const struct intel_crtc_state *pipe_config)
7432 {
7433 struct drm_device *dev = crtc->base.dev;
7434 struct drm_i915_private *dev_priv = dev->dev_private;
7435 int pipe = crtc->pipe;
7436 int dpll_reg = DPLL(crtc->pipe);
7437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7438 u32 loopfilter, tribuf_calcntr;
7439 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7440 u32 dpio_val;
7441 int vco;
7442
7443 bestn = pipe_config->dpll.n;
7444 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7445 bestm1 = pipe_config->dpll.m1;
7446 bestm2 = pipe_config->dpll.m2 >> 22;
7447 bestp1 = pipe_config->dpll.p1;
7448 bestp2 = pipe_config->dpll.p2;
7449 vco = pipe_config->dpll.vco;
7450 dpio_val = 0;
7451 loopfilter = 0;
7452
7453 /*
7454 * Enable Refclk and SSC
7455 */
7456 I915_WRITE(dpll_reg,
7457 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7458
7459 mutex_lock(&dev_priv->sb_lock);
7460
7461 /* p1 and p2 divider */
7462 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7463 5 << DPIO_CHV_S1_DIV_SHIFT |
7464 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7465 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7466 1 << DPIO_CHV_K_DIV_SHIFT);
7467
7468 /* Feedback post-divider - m2 */
7469 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7470
7471 /* Feedback refclk divider - n and m1 */
7472 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7473 DPIO_CHV_M1_DIV_BY_2 |
7474 1 << DPIO_CHV_N_DIV_SHIFT);
7475
7476 /* M2 fraction division */
7477 if (bestm2_frac)
7478 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7479
7480 /* M2 fraction division enable */
7481 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7482 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7483 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7484 if (bestm2_frac)
7485 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7486 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7487
7488 /* Program digital lock detect threshold */
7489 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7490 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7491 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7492 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7493 if (!bestm2_frac)
7494 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7495 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7496
7497 /* Loop filter */
7498 if (vco == 5400000) {
7499 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7500 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7501 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7502 tribuf_calcntr = 0x9;
7503 } else if (vco <= 6200000) {
7504 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7505 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7506 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7507 tribuf_calcntr = 0x9;
7508 } else if (vco <= 6480000) {
7509 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7510 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7511 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7512 tribuf_calcntr = 0x8;
7513 } else {
7514 /* Not supported. Apply the same limits as in the max case */
7515 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7516 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7517 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7518 tribuf_calcntr = 0;
7519 }
7520 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7521
7522 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7523 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7524 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7525 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7526
7527 /* AFC Recal */
7528 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7529 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7530 DPIO_AFC_RECAL);
7531
7532 mutex_unlock(&dev_priv->sb_lock);
7533 }
7534
7535 /**
7536 * vlv_force_pll_on - forcibly enable just the PLL
7537 * @dev_priv: i915 private structure
7538 * @pipe: pipe PLL to enable
7539 * @dpll: PLL configuration
7540 *
7541 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7542 * in cases where we need the PLL enabled even when @pipe is not going to
7543 * be enabled.
7544 */
7545 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7546 const struct dpll *dpll)
7547 {
7548 struct intel_crtc *crtc =
7549 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7550 struct intel_crtc_state pipe_config = {
7551 .base.crtc = &crtc->base,
7552 .pixel_multiplier = 1,
7553 .dpll = *dpll,
7554 };
7555
7556 if (IS_CHERRYVIEW(dev)) {
7557 chv_update_pll(crtc, &pipe_config);
7558 chv_prepare_pll(crtc, &pipe_config);
7559 chv_enable_pll(crtc, &pipe_config);
7560 } else {
7561 vlv_update_pll(crtc, &pipe_config);
7562 vlv_prepare_pll(crtc, &pipe_config);
7563 vlv_enable_pll(crtc, &pipe_config);
7564 }
7565 }
7566
7567 /**
7568 * vlv_force_pll_off - forcibly disable just the PLL
7569 * @dev_priv: i915 private structure
7570 * @pipe: pipe PLL to disable
7571 *
7572 * Disable the PLL for @pipe. To be used in cases where we need
7573 * the PLL enabled even when @pipe is not going to be enabled.
7574 */
7575 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7576 {
7577 if (IS_CHERRYVIEW(dev))
7578 chv_disable_pll(to_i915(dev), pipe);
7579 else
7580 vlv_disable_pll(to_i915(dev), pipe);
7581 }
7582
7583 static void i9xx_update_pll(struct intel_crtc *crtc,
7584 struct intel_crtc_state *crtc_state,
7585 intel_clock_t *reduced_clock,
7586 int num_connectors)
7587 {
7588 struct drm_device *dev = crtc->base.dev;
7589 struct drm_i915_private *dev_priv = dev->dev_private;
7590 u32 dpll;
7591 bool is_sdvo;
7592 struct dpll *clock = &crtc_state->dpll;
7593
7594 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7595
7596 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7597 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7598
7599 dpll = DPLL_VGA_MODE_DIS;
7600
7601 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7602 dpll |= DPLLB_MODE_LVDS;
7603 else
7604 dpll |= DPLLB_MODE_DAC_SERIAL;
7605
7606 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7607 dpll |= (crtc_state->pixel_multiplier - 1)
7608 << SDVO_MULTIPLIER_SHIFT_HIRES;
7609 }
7610
7611 if (is_sdvo)
7612 dpll |= DPLL_SDVO_HIGH_SPEED;
7613
7614 if (crtc_state->has_dp_encoder)
7615 dpll |= DPLL_SDVO_HIGH_SPEED;
7616
7617 /* compute bitmask from p1 value */
7618 if (IS_PINEVIEW(dev))
7619 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7620 else {
7621 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7622 if (IS_G4X(dev) && reduced_clock)
7623 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7624 }
7625 switch (clock->p2) {
7626 case 5:
7627 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7628 break;
7629 case 7:
7630 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7631 break;
7632 case 10:
7633 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7634 break;
7635 case 14:
7636 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7637 break;
7638 }
7639 if (INTEL_INFO(dev)->gen >= 4)
7640 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7641
7642 if (crtc_state->sdvo_tv_clock)
7643 dpll |= PLL_REF_INPUT_TVCLKINBC;
7644 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7645 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7646 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7647 else
7648 dpll |= PLL_REF_INPUT_DREFCLK;
7649
7650 dpll |= DPLL_VCO_ENABLE;
7651 crtc_state->dpll_hw_state.dpll = dpll;
7652
7653 if (INTEL_INFO(dev)->gen >= 4) {
7654 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7655 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7656 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7657 }
7658 }
7659
7660 static void i8xx_update_pll(struct intel_crtc *crtc,
7661 struct intel_crtc_state *crtc_state,
7662 intel_clock_t *reduced_clock,
7663 int num_connectors)
7664 {
7665 struct drm_device *dev = crtc->base.dev;
7666 struct drm_i915_private *dev_priv = dev->dev_private;
7667 u32 dpll;
7668 struct dpll *clock = &crtc_state->dpll;
7669
7670 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7671
7672 dpll = DPLL_VGA_MODE_DIS;
7673
7674 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7675 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7676 } else {
7677 if (clock->p1 == 2)
7678 dpll |= PLL_P1_DIVIDE_BY_TWO;
7679 else
7680 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7681 if (clock->p2 == 4)
7682 dpll |= PLL_P2_DIVIDE_BY_4;
7683 }
7684
7685 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7686 dpll |= DPLL_DVO_2X_MODE;
7687
7688 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7689 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7690 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7691 else
7692 dpll |= PLL_REF_INPUT_DREFCLK;
7693
7694 dpll |= DPLL_VCO_ENABLE;
7695 crtc_state->dpll_hw_state.dpll = dpll;
7696 }
7697
7698 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7699 {
7700 struct drm_device *dev = intel_crtc->base.dev;
7701 struct drm_i915_private *dev_priv = dev->dev_private;
7702 enum pipe pipe = intel_crtc->pipe;
7703 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7704 struct drm_display_mode *adjusted_mode =
7705 &intel_crtc->config->base.adjusted_mode;
7706 uint32_t crtc_vtotal, crtc_vblank_end;
7707 int vsyncshift = 0;
7708
7709 /* We need to be careful not to changed the adjusted mode, for otherwise
7710 * the hw state checker will get angry at the mismatch. */
7711 crtc_vtotal = adjusted_mode->crtc_vtotal;
7712 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7713
7714 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7715 /* the chip adds 2 halflines automatically */
7716 crtc_vtotal -= 1;
7717 crtc_vblank_end -= 1;
7718
7719 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7720 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7721 else
7722 vsyncshift = adjusted_mode->crtc_hsync_start -
7723 adjusted_mode->crtc_htotal / 2;
7724 if (vsyncshift < 0)
7725 vsyncshift += adjusted_mode->crtc_htotal;
7726 }
7727
7728 if (INTEL_INFO(dev)->gen > 3)
7729 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7730
7731 I915_WRITE(HTOTAL(cpu_transcoder),
7732 (adjusted_mode->crtc_hdisplay - 1) |
7733 ((adjusted_mode->crtc_htotal - 1) << 16));
7734 I915_WRITE(HBLANK(cpu_transcoder),
7735 (adjusted_mode->crtc_hblank_start - 1) |
7736 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7737 I915_WRITE(HSYNC(cpu_transcoder),
7738 (adjusted_mode->crtc_hsync_start - 1) |
7739 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7740
7741 I915_WRITE(VTOTAL(cpu_transcoder),
7742 (adjusted_mode->crtc_vdisplay - 1) |
7743 ((crtc_vtotal - 1) << 16));
7744 I915_WRITE(VBLANK(cpu_transcoder),
7745 (adjusted_mode->crtc_vblank_start - 1) |
7746 ((crtc_vblank_end - 1) << 16));
7747 I915_WRITE(VSYNC(cpu_transcoder),
7748 (adjusted_mode->crtc_vsync_start - 1) |
7749 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7750
7751 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7752 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7753 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7754 * bits. */
7755 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7756 (pipe == PIPE_B || pipe == PIPE_C))
7757 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7758
7759 /* pipesrc controls the size that is scaled from, which should
7760 * always be the user's requested size.
7761 */
7762 I915_WRITE(PIPESRC(pipe),
7763 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7764 (intel_crtc->config->pipe_src_h - 1));
7765 }
7766
7767 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7768 struct intel_crtc_state *pipe_config)
7769 {
7770 struct drm_device *dev = crtc->base.dev;
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7773 uint32_t tmp;
7774
7775 tmp = I915_READ(HTOTAL(cpu_transcoder));
7776 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7777 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7778 tmp = I915_READ(HBLANK(cpu_transcoder));
7779 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7780 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7781 tmp = I915_READ(HSYNC(cpu_transcoder));
7782 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7783 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7784
7785 tmp = I915_READ(VTOTAL(cpu_transcoder));
7786 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7787 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7788 tmp = I915_READ(VBLANK(cpu_transcoder));
7789 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7790 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7791 tmp = I915_READ(VSYNC(cpu_transcoder));
7792 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7793 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7794
7795 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7796 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7797 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7798 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7799 }
7800
7801 tmp = I915_READ(PIPESRC(crtc->pipe));
7802 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7803 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7804
7805 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7806 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7807 }
7808
7809 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7810 struct intel_crtc_state *pipe_config)
7811 {
7812 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7813 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7814 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7815 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7816
7817 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7818 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7819 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7820 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7821
7822 mode->flags = pipe_config->base.adjusted_mode.flags;
7823
7824 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7825 mode->flags |= pipe_config->base.adjusted_mode.flags;
7826 }
7827
7828 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7829 {
7830 struct drm_device *dev = intel_crtc->base.dev;
7831 struct drm_i915_private *dev_priv = dev->dev_private;
7832 uint32_t pipeconf;
7833
7834 pipeconf = 0;
7835
7836 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7837 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7838 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7839
7840 if (intel_crtc->config->double_wide)
7841 pipeconf |= PIPECONF_DOUBLE_WIDE;
7842
7843 /* only g4x and later have fancy bpc/dither controls */
7844 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7845 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7846 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7847 pipeconf |= PIPECONF_DITHER_EN |
7848 PIPECONF_DITHER_TYPE_SP;
7849
7850 switch (intel_crtc->config->pipe_bpp) {
7851 case 18:
7852 pipeconf |= PIPECONF_6BPC;
7853 break;
7854 case 24:
7855 pipeconf |= PIPECONF_8BPC;
7856 break;
7857 case 30:
7858 pipeconf |= PIPECONF_10BPC;
7859 break;
7860 default:
7861 /* Case prevented by intel_choose_pipe_bpp_dither. */
7862 BUG();
7863 }
7864 }
7865
7866 if (HAS_PIPE_CXSR(dev)) {
7867 if (intel_crtc->lowfreq_avail) {
7868 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7869 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7870 } else {
7871 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7872 }
7873 }
7874
7875 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7876 if (INTEL_INFO(dev)->gen < 4 ||
7877 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7878 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7879 else
7880 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7881 } else
7882 pipeconf |= PIPECONF_PROGRESSIVE;
7883
7884 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7885 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7886
7887 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7888 POSTING_READ(PIPECONF(intel_crtc->pipe));
7889 }
7890
7891 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7892 struct intel_crtc_state *crtc_state)
7893 {
7894 struct drm_device *dev = crtc->base.dev;
7895 struct drm_i915_private *dev_priv = dev->dev_private;
7896 int refclk, num_connectors = 0;
7897 intel_clock_t clock, reduced_clock;
7898 bool ok, has_reduced_clock = false;
7899 bool is_lvds = false, is_dsi = false;
7900 struct intel_encoder *encoder;
7901 const intel_limit_t *limit;
7902 struct drm_atomic_state *state = crtc_state->base.state;
7903 struct drm_connector *connector;
7904 struct drm_connector_state *connector_state;
7905 int i;
7906
7907 memset(&crtc_state->dpll_hw_state, 0,
7908 sizeof(crtc_state->dpll_hw_state));
7909
7910 for_each_connector_in_state(state, connector, connector_state, i) {
7911 if (connector_state->crtc != &crtc->base)
7912 continue;
7913
7914 encoder = to_intel_encoder(connector_state->best_encoder);
7915
7916 switch (encoder->type) {
7917 case INTEL_OUTPUT_LVDS:
7918 is_lvds = true;
7919 break;
7920 case INTEL_OUTPUT_DSI:
7921 is_dsi = true;
7922 break;
7923 default:
7924 break;
7925 }
7926
7927 num_connectors++;
7928 }
7929
7930 if (is_dsi)
7931 return 0;
7932
7933 if (!crtc_state->clock_set) {
7934 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7935
7936 /*
7937 * Returns a set of divisors for the desired target clock with
7938 * the given refclk, or FALSE. The returned values represent
7939 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7940 * 2) / p1 / p2.
7941 */
7942 limit = intel_limit(crtc_state, refclk);
7943 ok = dev_priv->display.find_dpll(limit, crtc_state,
7944 crtc_state->port_clock,
7945 refclk, NULL, &clock);
7946 if (!ok) {
7947 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7948 return -EINVAL;
7949 }
7950
7951 if (is_lvds && dev_priv->lvds_downclock_avail) {
7952 /*
7953 * Ensure we match the reduced clock's P to the target
7954 * clock. If the clocks don't match, we can't switch
7955 * the display clock by using the FP0/FP1. In such case
7956 * we will disable the LVDS downclock feature.
7957 */
7958 has_reduced_clock =
7959 dev_priv->display.find_dpll(limit, crtc_state,
7960 dev_priv->lvds_downclock,
7961 refclk, &clock,
7962 &reduced_clock);
7963 }
7964 /* Compat-code for transition, will disappear. */
7965 crtc_state->dpll.n = clock.n;
7966 crtc_state->dpll.m1 = clock.m1;
7967 crtc_state->dpll.m2 = clock.m2;
7968 crtc_state->dpll.p1 = clock.p1;
7969 crtc_state->dpll.p2 = clock.p2;
7970 }
7971
7972 if (IS_GEN2(dev)) {
7973 i8xx_update_pll(crtc, crtc_state,
7974 has_reduced_clock ? &reduced_clock : NULL,
7975 num_connectors);
7976 } else if (IS_CHERRYVIEW(dev)) {
7977 chv_update_pll(crtc, crtc_state);
7978 } else if (IS_VALLEYVIEW(dev)) {
7979 vlv_update_pll(crtc, crtc_state);
7980 } else {
7981 i9xx_update_pll(crtc, crtc_state,
7982 has_reduced_clock ? &reduced_clock : NULL,
7983 num_connectors);
7984 }
7985
7986 return 0;
7987 }
7988
7989 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7990 struct intel_crtc_state *pipe_config)
7991 {
7992 struct drm_device *dev = crtc->base.dev;
7993 struct drm_i915_private *dev_priv = dev->dev_private;
7994 uint32_t tmp;
7995
7996 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7997 return;
7998
7999 tmp = I915_READ(PFIT_CONTROL);
8000 if (!(tmp & PFIT_ENABLE))
8001 return;
8002
8003 /* Check whether the pfit is attached to our pipe. */
8004 if (INTEL_INFO(dev)->gen < 4) {
8005 if (crtc->pipe != PIPE_B)
8006 return;
8007 } else {
8008 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8009 return;
8010 }
8011
8012 pipe_config->gmch_pfit.control = tmp;
8013 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8014 if (INTEL_INFO(dev)->gen < 5)
8015 pipe_config->gmch_pfit.lvds_border_bits =
8016 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8017 }
8018
8019 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8020 struct intel_crtc_state *pipe_config)
8021 {
8022 struct drm_device *dev = crtc->base.dev;
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 int pipe = pipe_config->cpu_transcoder;
8025 intel_clock_t clock;
8026 u32 mdiv;
8027 int refclk = 100000;
8028
8029 /* In case of MIPI DPLL will not even be used */
8030 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8031 return;
8032
8033 mutex_lock(&dev_priv->sb_lock);
8034 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8035 mutex_unlock(&dev_priv->sb_lock);
8036
8037 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8038 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8039 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8040 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8041 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8042
8043 vlv_clock(refclk, &clock);
8044
8045 /* clock.dot is the fast clock */
8046 pipe_config->port_clock = clock.dot / 5;
8047 }
8048
8049 static void
8050 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8051 struct intel_initial_plane_config *plane_config)
8052 {
8053 struct drm_device *dev = crtc->base.dev;
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8055 u32 val, base, offset;
8056 int pipe = crtc->pipe, plane = crtc->plane;
8057 int fourcc, pixel_format;
8058 unsigned int aligned_height;
8059 struct drm_framebuffer *fb;
8060 struct intel_framebuffer *intel_fb;
8061
8062 val = I915_READ(DSPCNTR(plane));
8063 if (!(val & DISPLAY_PLANE_ENABLE))
8064 return;
8065
8066 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8067 if (!intel_fb) {
8068 DRM_DEBUG_KMS("failed to alloc fb\n");
8069 return;
8070 }
8071
8072 fb = &intel_fb->base;
8073
8074 if (INTEL_INFO(dev)->gen >= 4) {
8075 if (val & DISPPLANE_TILED) {
8076 plane_config->tiling = I915_TILING_X;
8077 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8078 }
8079 }
8080
8081 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8082 fourcc = i9xx_format_to_fourcc(pixel_format);
8083 fb->pixel_format = fourcc;
8084 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8085
8086 if (INTEL_INFO(dev)->gen >= 4) {
8087 if (plane_config->tiling)
8088 offset = I915_READ(DSPTILEOFF(plane));
8089 else
8090 offset = I915_READ(DSPLINOFF(plane));
8091 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8092 } else {
8093 base = I915_READ(DSPADDR(plane));
8094 }
8095 plane_config->base = base;
8096
8097 val = I915_READ(PIPESRC(pipe));
8098 fb->width = ((val >> 16) & 0xfff) + 1;
8099 fb->height = ((val >> 0) & 0xfff) + 1;
8100
8101 val = I915_READ(DSPSTRIDE(pipe));
8102 fb->pitches[0] = val & 0xffffffc0;
8103
8104 aligned_height = intel_fb_align_height(dev, fb->height,
8105 fb->pixel_format,
8106 fb->modifier[0]);
8107
8108 plane_config->size = fb->pitches[0] * aligned_height;
8109
8110 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8111 pipe_name(pipe), plane, fb->width, fb->height,
8112 fb->bits_per_pixel, base, fb->pitches[0],
8113 plane_config->size);
8114
8115 plane_config->fb = intel_fb;
8116 }
8117
8118 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8119 struct intel_crtc_state *pipe_config)
8120 {
8121 struct drm_device *dev = crtc->base.dev;
8122 struct drm_i915_private *dev_priv = dev->dev_private;
8123 int pipe = pipe_config->cpu_transcoder;
8124 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8125 intel_clock_t clock;
8126 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8127 int refclk = 100000;
8128
8129 mutex_lock(&dev_priv->sb_lock);
8130 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8131 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8132 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8133 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8134 mutex_unlock(&dev_priv->sb_lock);
8135
8136 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8137 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8138 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8139 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8140 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8141
8142 chv_clock(refclk, &clock);
8143
8144 /* clock.dot is the fast clock */
8145 pipe_config->port_clock = clock.dot / 5;
8146 }
8147
8148 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8149 struct intel_crtc_state *pipe_config)
8150 {
8151 struct drm_device *dev = crtc->base.dev;
8152 struct drm_i915_private *dev_priv = dev->dev_private;
8153 uint32_t tmp;
8154
8155 if (!intel_display_power_is_enabled(dev_priv,
8156 POWER_DOMAIN_PIPE(crtc->pipe)))
8157 return false;
8158
8159 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8160 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8161
8162 tmp = I915_READ(PIPECONF(crtc->pipe));
8163 if (!(tmp & PIPECONF_ENABLE))
8164 return false;
8165
8166 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8167 switch (tmp & PIPECONF_BPC_MASK) {
8168 case PIPECONF_6BPC:
8169 pipe_config->pipe_bpp = 18;
8170 break;
8171 case PIPECONF_8BPC:
8172 pipe_config->pipe_bpp = 24;
8173 break;
8174 case PIPECONF_10BPC:
8175 pipe_config->pipe_bpp = 30;
8176 break;
8177 default:
8178 break;
8179 }
8180 }
8181
8182 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8183 pipe_config->limited_color_range = true;
8184
8185 if (INTEL_INFO(dev)->gen < 4)
8186 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8187
8188 intel_get_pipe_timings(crtc, pipe_config);
8189
8190 i9xx_get_pfit_config(crtc, pipe_config);
8191
8192 if (INTEL_INFO(dev)->gen >= 4) {
8193 tmp = I915_READ(DPLL_MD(crtc->pipe));
8194 pipe_config->pixel_multiplier =
8195 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8196 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8197 pipe_config->dpll_hw_state.dpll_md = tmp;
8198 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8199 tmp = I915_READ(DPLL(crtc->pipe));
8200 pipe_config->pixel_multiplier =
8201 ((tmp & SDVO_MULTIPLIER_MASK)
8202 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8203 } else {
8204 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8205 * port and will be fixed up in the encoder->get_config
8206 * function. */
8207 pipe_config->pixel_multiplier = 1;
8208 }
8209 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8210 if (!IS_VALLEYVIEW(dev)) {
8211 /*
8212 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8213 * on 830. Filter it out here so that we don't
8214 * report errors due to that.
8215 */
8216 if (IS_I830(dev))
8217 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8218
8219 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8220 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8221 } else {
8222 /* Mask out read-only status bits. */
8223 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8224 DPLL_PORTC_READY_MASK |
8225 DPLL_PORTB_READY_MASK);
8226 }
8227
8228 if (IS_CHERRYVIEW(dev))
8229 chv_crtc_clock_get(crtc, pipe_config);
8230 else if (IS_VALLEYVIEW(dev))
8231 vlv_crtc_clock_get(crtc, pipe_config);
8232 else
8233 i9xx_crtc_clock_get(crtc, pipe_config);
8234
8235 return true;
8236 }
8237
8238 static void ironlake_init_pch_refclk(struct drm_device *dev)
8239 {
8240 struct drm_i915_private *dev_priv = dev->dev_private;
8241 struct intel_encoder *encoder;
8242 u32 val, final;
8243 bool has_lvds = false;
8244 bool has_cpu_edp = false;
8245 bool has_panel = false;
8246 bool has_ck505 = false;
8247 bool can_ssc = false;
8248
8249 /* We need to take the global config into account */
8250 for_each_intel_encoder(dev, encoder) {
8251 switch (encoder->type) {
8252 case INTEL_OUTPUT_LVDS:
8253 has_panel = true;
8254 has_lvds = true;
8255 break;
8256 case INTEL_OUTPUT_EDP:
8257 has_panel = true;
8258 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8259 has_cpu_edp = true;
8260 break;
8261 default:
8262 break;
8263 }
8264 }
8265
8266 if (HAS_PCH_IBX(dev)) {
8267 has_ck505 = dev_priv->vbt.display_clock_mode;
8268 can_ssc = has_ck505;
8269 } else {
8270 has_ck505 = false;
8271 can_ssc = true;
8272 }
8273
8274 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8275 has_panel, has_lvds, has_ck505);
8276
8277 /* Ironlake: try to setup display ref clock before DPLL
8278 * enabling. This is only under driver's control after
8279 * PCH B stepping, previous chipset stepping should be
8280 * ignoring this setting.
8281 */
8282 val = I915_READ(PCH_DREF_CONTROL);
8283
8284 /* As we must carefully and slowly disable/enable each source in turn,
8285 * compute the final state we want first and check if we need to
8286 * make any changes at all.
8287 */
8288 final = val;
8289 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8290 if (has_ck505)
8291 final |= DREF_NONSPREAD_CK505_ENABLE;
8292 else
8293 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8294
8295 final &= ~DREF_SSC_SOURCE_MASK;
8296 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8297 final &= ~DREF_SSC1_ENABLE;
8298
8299 if (has_panel) {
8300 final |= DREF_SSC_SOURCE_ENABLE;
8301
8302 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8303 final |= DREF_SSC1_ENABLE;
8304
8305 if (has_cpu_edp) {
8306 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8307 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8308 else
8309 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8310 } else
8311 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8312 } else {
8313 final |= DREF_SSC_SOURCE_DISABLE;
8314 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8315 }
8316
8317 if (final == val)
8318 return;
8319
8320 /* Always enable nonspread source */
8321 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8322
8323 if (has_ck505)
8324 val |= DREF_NONSPREAD_CK505_ENABLE;
8325 else
8326 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8327
8328 if (has_panel) {
8329 val &= ~DREF_SSC_SOURCE_MASK;
8330 val |= DREF_SSC_SOURCE_ENABLE;
8331
8332 /* SSC must be turned on before enabling the CPU output */
8333 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8334 DRM_DEBUG_KMS("Using SSC on panel\n");
8335 val |= DREF_SSC1_ENABLE;
8336 } else
8337 val &= ~DREF_SSC1_ENABLE;
8338
8339 /* Get SSC going before enabling the outputs */
8340 I915_WRITE(PCH_DREF_CONTROL, val);
8341 POSTING_READ(PCH_DREF_CONTROL);
8342 udelay(200);
8343
8344 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8345
8346 /* Enable CPU source on CPU attached eDP */
8347 if (has_cpu_edp) {
8348 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8349 DRM_DEBUG_KMS("Using SSC on eDP\n");
8350 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8351 } else
8352 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8353 } else
8354 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8355
8356 I915_WRITE(PCH_DREF_CONTROL, val);
8357 POSTING_READ(PCH_DREF_CONTROL);
8358 udelay(200);
8359 } else {
8360 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8361
8362 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8363
8364 /* Turn off CPU output */
8365 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8366
8367 I915_WRITE(PCH_DREF_CONTROL, val);
8368 POSTING_READ(PCH_DREF_CONTROL);
8369 udelay(200);
8370
8371 /* Turn off the SSC source */
8372 val &= ~DREF_SSC_SOURCE_MASK;
8373 val |= DREF_SSC_SOURCE_DISABLE;
8374
8375 /* Turn off SSC1 */
8376 val &= ~DREF_SSC1_ENABLE;
8377
8378 I915_WRITE(PCH_DREF_CONTROL, val);
8379 POSTING_READ(PCH_DREF_CONTROL);
8380 udelay(200);
8381 }
8382
8383 BUG_ON(val != final);
8384 }
8385
8386 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8387 {
8388 uint32_t tmp;
8389
8390 tmp = I915_READ(SOUTH_CHICKEN2);
8391 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8392 I915_WRITE(SOUTH_CHICKEN2, tmp);
8393
8394 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8395 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8396 DRM_ERROR("FDI mPHY reset assert timeout\n");
8397
8398 tmp = I915_READ(SOUTH_CHICKEN2);
8399 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8400 I915_WRITE(SOUTH_CHICKEN2, tmp);
8401
8402 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8403 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8404 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8405 }
8406
8407 /* WaMPhyProgramming:hsw */
8408 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8409 {
8410 uint32_t tmp;
8411
8412 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8413 tmp &= ~(0xFF << 24);
8414 tmp |= (0x12 << 24);
8415 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8416
8417 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8418 tmp |= (1 << 11);
8419 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8420
8421 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8422 tmp |= (1 << 11);
8423 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8424
8425 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8426 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8427 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8428
8429 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8430 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8431 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8432
8433 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8434 tmp &= ~(7 << 13);
8435 tmp |= (5 << 13);
8436 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8437
8438 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8439 tmp &= ~(7 << 13);
8440 tmp |= (5 << 13);
8441 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8442
8443 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8444 tmp &= ~0xFF;
8445 tmp |= 0x1C;
8446 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8447
8448 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8449 tmp &= ~0xFF;
8450 tmp |= 0x1C;
8451 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8452
8453 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8454 tmp &= ~(0xFF << 16);
8455 tmp |= (0x1C << 16);
8456 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8457
8458 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8459 tmp &= ~(0xFF << 16);
8460 tmp |= (0x1C << 16);
8461 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8462
8463 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8464 tmp |= (1 << 27);
8465 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8466
8467 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8468 tmp |= (1 << 27);
8469 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8470
8471 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8472 tmp &= ~(0xF << 28);
8473 tmp |= (4 << 28);
8474 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8475
8476 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8477 tmp &= ~(0xF << 28);
8478 tmp |= (4 << 28);
8479 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8480 }
8481
8482 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8483 * Programming" based on the parameters passed:
8484 * - Sequence to enable CLKOUT_DP
8485 * - Sequence to enable CLKOUT_DP without spread
8486 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8487 */
8488 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8489 bool with_fdi)
8490 {
8491 struct drm_i915_private *dev_priv = dev->dev_private;
8492 uint32_t reg, tmp;
8493
8494 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8495 with_spread = true;
8496 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8497 with_fdi, "LP PCH doesn't have FDI\n"))
8498 with_fdi = false;
8499
8500 mutex_lock(&dev_priv->sb_lock);
8501
8502 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8503 tmp &= ~SBI_SSCCTL_DISABLE;
8504 tmp |= SBI_SSCCTL_PATHALT;
8505 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8506
8507 udelay(24);
8508
8509 if (with_spread) {
8510 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8511 tmp &= ~SBI_SSCCTL_PATHALT;
8512 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8513
8514 if (with_fdi) {
8515 lpt_reset_fdi_mphy(dev_priv);
8516 lpt_program_fdi_mphy(dev_priv);
8517 }
8518 }
8519
8520 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8521 SBI_GEN0 : SBI_DBUFF0;
8522 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8523 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8524 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8525
8526 mutex_unlock(&dev_priv->sb_lock);
8527 }
8528
8529 /* Sequence to disable CLKOUT_DP */
8530 static void lpt_disable_clkout_dp(struct drm_device *dev)
8531 {
8532 struct drm_i915_private *dev_priv = dev->dev_private;
8533 uint32_t reg, tmp;
8534
8535 mutex_lock(&dev_priv->sb_lock);
8536
8537 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8538 SBI_GEN0 : SBI_DBUFF0;
8539 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8540 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8541 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8542
8543 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8544 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8545 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8546 tmp |= SBI_SSCCTL_PATHALT;
8547 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8548 udelay(32);
8549 }
8550 tmp |= SBI_SSCCTL_DISABLE;
8551 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8552 }
8553
8554 mutex_unlock(&dev_priv->sb_lock);
8555 }
8556
8557 static void lpt_init_pch_refclk(struct drm_device *dev)
8558 {
8559 struct intel_encoder *encoder;
8560 bool has_vga = false;
8561
8562 for_each_intel_encoder(dev, encoder) {
8563 switch (encoder->type) {
8564 case INTEL_OUTPUT_ANALOG:
8565 has_vga = true;
8566 break;
8567 default:
8568 break;
8569 }
8570 }
8571
8572 if (has_vga)
8573 lpt_enable_clkout_dp(dev, true, true);
8574 else
8575 lpt_disable_clkout_dp(dev);
8576 }
8577
8578 /*
8579 * Initialize reference clocks when the driver loads
8580 */
8581 void intel_init_pch_refclk(struct drm_device *dev)
8582 {
8583 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8584 ironlake_init_pch_refclk(dev);
8585 else if (HAS_PCH_LPT(dev))
8586 lpt_init_pch_refclk(dev);
8587 }
8588
8589 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8590 {
8591 struct drm_device *dev = crtc_state->base.crtc->dev;
8592 struct drm_i915_private *dev_priv = dev->dev_private;
8593 struct drm_atomic_state *state = crtc_state->base.state;
8594 struct drm_connector *connector;
8595 struct drm_connector_state *connector_state;
8596 struct intel_encoder *encoder;
8597 int num_connectors = 0, i;
8598 bool is_lvds = false;
8599
8600 for_each_connector_in_state(state, connector, connector_state, i) {
8601 if (connector_state->crtc != crtc_state->base.crtc)
8602 continue;
8603
8604 encoder = to_intel_encoder(connector_state->best_encoder);
8605
8606 switch (encoder->type) {
8607 case INTEL_OUTPUT_LVDS:
8608 is_lvds = true;
8609 break;
8610 default:
8611 break;
8612 }
8613 num_connectors++;
8614 }
8615
8616 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8617 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8618 dev_priv->vbt.lvds_ssc_freq);
8619 return dev_priv->vbt.lvds_ssc_freq;
8620 }
8621
8622 return 120000;
8623 }
8624
8625 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8626 {
8627 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629 int pipe = intel_crtc->pipe;
8630 uint32_t val;
8631
8632 val = 0;
8633
8634 switch (intel_crtc->config->pipe_bpp) {
8635 case 18:
8636 val |= PIPECONF_6BPC;
8637 break;
8638 case 24:
8639 val |= PIPECONF_8BPC;
8640 break;
8641 case 30:
8642 val |= PIPECONF_10BPC;
8643 break;
8644 case 36:
8645 val |= PIPECONF_12BPC;
8646 break;
8647 default:
8648 /* Case prevented by intel_choose_pipe_bpp_dither. */
8649 BUG();
8650 }
8651
8652 if (intel_crtc->config->dither)
8653 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8654
8655 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8656 val |= PIPECONF_INTERLACED_ILK;
8657 else
8658 val |= PIPECONF_PROGRESSIVE;
8659
8660 if (intel_crtc->config->limited_color_range)
8661 val |= PIPECONF_COLOR_RANGE_SELECT;
8662
8663 I915_WRITE(PIPECONF(pipe), val);
8664 POSTING_READ(PIPECONF(pipe));
8665 }
8666
8667 /*
8668 * Set up the pipe CSC unit.
8669 *
8670 * Currently only full range RGB to limited range RGB conversion
8671 * is supported, but eventually this should handle various
8672 * RGB<->YCbCr scenarios as well.
8673 */
8674 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8675 {
8676 struct drm_device *dev = crtc->dev;
8677 struct drm_i915_private *dev_priv = dev->dev_private;
8678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8679 int pipe = intel_crtc->pipe;
8680 uint16_t coeff = 0x7800; /* 1.0 */
8681
8682 /*
8683 * TODO: Check what kind of values actually come out of the pipe
8684 * with these coeff/postoff values and adjust to get the best
8685 * accuracy. Perhaps we even need to take the bpc value into
8686 * consideration.
8687 */
8688
8689 if (intel_crtc->config->limited_color_range)
8690 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8691
8692 /*
8693 * GY/GU and RY/RU should be the other way around according
8694 * to BSpec, but reality doesn't agree. Just set them up in
8695 * a way that results in the correct picture.
8696 */
8697 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8698 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8699
8700 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8701 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8702
8703 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8704 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8705
8706 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8707 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8708 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8709
8710 if (INTEL_INFO(dev)->gen > 6) {
8711 uint16_t postoff = 0;
8712
8713 if (intel_crtc->config->limited_color_range)
8714 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8715
8716 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8717 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8718 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8719
8720 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8721 } else {
8722 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8723
8724 if (intel_crtc->config->limited_color_range)
8725 mode |= CSC_BLACK_SCREEN_OFFSET;
8726
8727 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8728 }
8729 }
8730
8731 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8732 {
8733 struct drm_device *dev = crtc->dev;
8734 struct drm_i915_private *dev_priv = dev->dev_private;
8735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8736 enum pipe pipe = intel_crtc->pipe;
8737 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8738 uint32_t val;
8739
8740 val = 0;
8741
8742 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8743 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8744
8745 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8746 val |= PIPECONF_INTERLACED_ILK;
8747 else
8748 val |= PIPECONF_PROGRESSIVE;
8749
8750 I915_WRITE(PIPECONF(cpu_transcoder), val);
8751 POSTING_READ(PIPECONF(cpu_transcoder));
8752
8753 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8754 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8755
8756 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8757 val = 0;
8758
8759 switch (intel_crtc->config->pipe_bpp) {
8760 case 18:
8761 val |= PIPEMISC_DITHER_6_BPC;
8762 break;
8763 case 24:
8764 val |= PIPEMISC_DITHER_8_BPC;
8765 break;
8766 case 30:
8767 val |= PIPEMISC_DITHER_10_BPC;
8768 break;
8769 case 36:
8770 val |= PIPEMISC_DITHER_12_BPC;
8771 break;
8772 default:
8773 /* Case prevented by pipe_config_set_bpp. */
8774 BUG();
8775 }
8776
8777 if (intel_crtc->config->dither)
8778 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8779
8780 I915_WRITE(PIPEMISC(pipe), val);
8781 }
8782 }
8783
8784 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8785 struct intel_crtc_state *crtc_state,
8786 intel_clock_t *clock,
8787 bool *has_reduced_clock,
8788 intel_clock_t *reduced_clock)
8789 {
8790 struct drm_device *dev = crtc->dev;
8791 struct drm_i915_private *dev_priv = dev->dev_private;
8792 int refclk;
8793 const intel_limit_t *limit;
8794 bool ret, is_lvds = false;
8795
8796 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8797
8798 refclk = ironlake_get_refclk(crtc_state);
8799
8800 /*
8801 * Returns a set of divisors for the desired target clock with the given
8802 * refclk, or FALSE. The returned values represent the clock equation:
8803 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8804 */
8805 limit = intel_limit(crtc_state, refclk);
8806 ret = dev_priv->display.find_dpll(limit, crtc_state,
8807 crtc_state->port_clock,
8808 refclk, NULL, clock);
8809 if (!ret)
8810 return false;
8811
8812 if (is_lvds && dev_priv->lvds_downclock_avail) {
8813 /*
8814 * Ensure we match the reduced clock's P to the target clock.
8815 * If the clocks don't match, we can't switch the display clock
8816 * by using the FP0/FP1. In such case we will disable the LVDS
8817 * downclock feature.
8818 */
8819 *has_reduced_clock =
8820 dev_priv->display.find_dpll(limit, crtc_state,
8821 dev_priv->lvds_downclock,
8822 refclk, clock,
8823 reduced_clock);
8824 }
8825
8826 return true;
8827 }
8828
8829 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8830 {
8831 /*
8832 * Account for spread spectrum to avoid
8833 * oversubscribing the link. Max center spread
8834 * is 2.5%; use 5% for safety's sake.
8835 */
8836 u32 bps = target_clock * bpp * 21 / 20;
8837 return DIV_ROUND_UP(bps, link_bw * 8);
8838 }
8839
8840 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8841 {
8842 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8843 }
8844
8845 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8846 struct intel_crtc_state *crtc_state,
8847 u32 *fp,
8848 intel_clock_t *reduced_clock, u32 *fp2)
8849 {
8850 struct drm_crtc *crtc = &intel_crtc->base;
8851 struct drm_device *dev = crtc->dev;
8852 struct drm_i915_private *dev_priv = dev->dev_private;
8853 struct drm_atomic_state *state = crtc_state->base.state;
8854 struct drm_connector *connector;
8855 struct drm_connector_state *connector_state;
8856 struct intel_encoder *encoder;
8857 uint32_t dpll;
8858 int factor, num_connectors = 0, i;
8859 bool is_lvds = false, is_sdvo = false;
8860
8861 for_each_connector_in_state(state, connector, connector_state, i) {
8862 if (connector_state->crtc != crtc_state->base.crtc)
8863 continue;
8864
8865 encoder = to_intel_encoder(connector_state->best_encoder);
8866
8867 switch (encoder->type) {
8868 case INTEL_OUTPUT_LVDS:
8869 is_lvds = true;
8870 break;
8871 case INTEL_OUTPUT_SDVO:
8872 case INTEL_OUTPUT_HDMI:
8873 is_sdvo = true;
8874 break;
8875 default:
8876 break;
8877 }
8878
8879 num_connectors++;
8880 }
8881
8882 /* Enable autotuning of the PLL clock (if permissible) */
8883 factor = 21;
8884 if (is_lvds) {
8885 if ((intel_panel_use_ssc(dev_priv) &&
8886 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8887 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8888 factor = 25;
8889 } else if (crtc_state->sdvo_tv_clock)
8890 factor = 20;
8891
8892 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8893 *fp |= FP_CB_TUNE;
8894
8895 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8896 *fp2 |= FP_CB_TUNE;
8897
8898 dpll = 0;
8899
8900 if (is_lvds)
8901 dpll |= DPLLB_MODE_LVDS;
8902 else
8903 dpll |= DPLLB_MODE_DAC_SERIAL;
8904
8905 dpll |= (crtc_state->pixel_multiplier - 1)
8906 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8907
8908 if (is_sdvo)
8909 dpll |= DPLL_SDVO_HIGH_SPEED;
8910 if (crtc_state->has_dp_encoder)
8911 dpll |= DPLL_SDVO_HIGH_SPEED;
8912
8913 /* compute bitmask from p1 value */
8914 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8915 /* also FPA1 */
8916 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8917
8918 switch (crtc_state->dpll.p2) {
8919 case 5:
8920 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8921 break;
8922 case 7:
8923 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8924 break;
8925 case 10:
8926 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8927 break;
8928 case 14:
8929 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8930 break;
8931 }
8932
8933 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8934 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8935 else
8936 dpll |= PLL_REF_INPUT_DREFCLK;
8937
8938 return dpll | DPLL_VCO_ENABLE;
8939 }
8940
8941 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8942 struct intel_crtc_state *crtc_state)
8943 {
8944 struct drm_device *dev = crtc->base.dev;
8945 intel_clock_t clock, reduced_clock;
8946 u32 dpll = 0, fp = 0, fp2 = 0;
8947 bool ok, has_reduced_clock = false;
8948 bool is_lvds = false;
8949 struct intel_shared_dpll *pll;
8950
8951 memset(&crtc_state->dpll_hw_state, 0,
8952 sizeof(crtc_state->dpll_hw_state));
8953
8954 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8955
8956 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8957 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8958
8959 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8960 &has_reduced_clock, &reduced_clock);
8961 if (!ok && !crtc_state->clock_set) {
8962 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8963 return -EINVAL;
8964 }
8965 /* Compat-code for transition, will disappear. */
8966 if (!crtc_state->clock_set) {
8967 crtc_state->dpll.n = clock.n;
8968 crtc_state->dpll.m1 = clock.m1;
8969 crtc_state->dpll.m2 = clock.m2;
8970 crtc_state->dpll.p1 = clock.p1;
8971 crtc_state->dpll.p2 = clock.p2;
8972 }
8973
8974 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8975 if (crtc_state->has_pch_encoder) {
8976 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8977 if (has_reduced_clock)
8978 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8979
8980 dpll = ironlake_compute_dpll(crtc, crtc_state,
8981 &fp, &reduced_clock,
8982 has_reduced_clock ? &fp2 : NULL);
8983
8984 crtc_state->dpll_hw_state.dpll = dpll;
8985 crtc_state->dpll_hw_state.fp0 = fp;
8986 if (has_reduced_clock)
8987 crtc_state->dpll_hw_state.fp1 = fp2;
8988 else
8989 crtc_state->dpll_hw_state.fp1 = fp;
8990
8991 pll = intel_get_shared_dpll(crtc, crtc_state);
8992 if (pll == NULL) {
8993 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8994 pipe_name(crtc->pipe));
8995 return -EINVAL;
8996 }
8997 }
8998
8999 if (is_lvds && has_reduced_clock)
9000 crtc->lowfreq_avail = true;
9001 else
9002 crtc->lowfreq_avail = false;
9003
9004 return 0;
9005 }
9006
9007 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9008 struct intel_link_m_n *m_n)
9009 {
9010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 enum pipe pipe = crtc->pipe;
9013
9014 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9015 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9016 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9017 & ~TU_SIZE_MASK;
9018 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9019 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9020 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9021 }
9022
9023 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9024 enum transcoder transcoder,
9025 struct intel_link_m_n *m_n,
9026 struct intel_link_m_n *m2_n2)
9027 {
9028 struct drm_device *dev = crtc->base.dev;
9029 struct drm_i915_private *dev_priv = dev->dev_private;
9030 enum pipe pipe = crtc->pipe;
9031
9032 if (INTEL_INFO(dev)->gen >= 5) {
9033 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9034 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9035 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9036 & ~TU_SIZE_MASK;
9037 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9038 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9039 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9040 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9041 * gen < 8) and if DRRS is supported (to make sure the
9042 * registers are not unnecessarily read).
9043 */
9044 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9045 crtc->config->has_drrs) {
9046 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9047 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9048 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9049 & ~TU_SIZE_MASK;
9050 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9051 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9052 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9053 }
9054 } else {
9055 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9056 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9057 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9058 & ~TU_SIZE_MASK;
9059 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9060 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9061 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9062 }
9063 }
9064
9065 void intel_dp_get_m_n(struct intel_crtc *crtc,
9066 struct intel_crtc_state *pipe_config)
9067 {
9068 if (pipe_config->has_pch_encoder)
9069 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9070 else
9071 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9072 &pipe_config->dp_m_n,
9073 &pipe_config->dp_m2_n2);
9074 }
9075
9076 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9077 struct intel_crtc_state *pipe_config)
9078 {
9079 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9080 &pipe_config->fdi_m_n, NULL);
9081 }
9082
9083 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9084 struct intel_crtc_state *pipe_config)
9085 {
9086 struct drm_device *dev = crtc->base.dev;
9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9089 uint32_t ps_ctrl = 0;
9090 int id = -1;
9091 int i;
9092
9093 /* find scaler attached to this pipe */
9094 for (i = 0; i < crtc->num_scalers; i++) {
9095 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9096 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9097 id = i;
9098 pipe_config->pch_pfit.enabled = true;
9099 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9100 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9101 break;
9102 }
9103 }
9104
9105 scaler_state->scaler_id = id;
9106 if (id >= 0) {
9107 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9108 } else {
9109 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9110 }
9111 }
9112
9113 static void
9114 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9115 struct intel_initial_plane_config *plane_config)
9116 {
9117 struct drm_device *dev = crtc->base.dev;
9118 struct drm_i915_private *dev_priv = dev->dev_private;
9119 u32 val, base, offset, stride_mult, tiling;
9120 int pipe = crtc->pipe;
9121 int fourcc, pixel_format;
9122 unsigned int aligned_height;
9123 struct drm_framebuffer *fb;
9124 struct intel_framebuffer *intel_fb;
9125
9126 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9127 if (!intel_fb) {
9128 DRM_DEBUG_KMS("failed to alloc fb\n");
9129 return;
9130 }
9131
9132 fb = &intel_fb->base;
9133
9134 val = I915_READ(PLANE_CTL(pipe, 0));
9135 if (!(val & PLANE_CTL_ENABLE))
9136 goto error;
9137
9138 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9139 fourcc = skl_format_to_fourcc(pixel_format,
9140 val & PLANE_CTL_ORDER_RGBX,
9141 val & PLANE_CTL_ALPHA_MASK);
9142 fb->pixel_format = fourcc;
9143 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9144
9145 tiling = val & PLANE_CTL_TILED_MASK;
9146 switch (tiling) {
9147 case PLANE_CTL_TILED_LINEAR:
9148 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9149 break;
9150 case PLANE_CTL_TILED_X:
9151 plane_config->tiling = I915_TILING_X;
9152 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9153 break;
9154 case PLANE_CTL_TILED_Y:
9155 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9156 break;
9157 case PLANE_CTL_TILED_YF:
9158 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9159 break;
9160 default:
9161 MISSING_CASE(tiling);
9162 goto error;
9163 }
9164
9165 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9166 plane_config->base = base;
9167
9168 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9169
9170 val = I915_READ(PLANE_SIZE(pipe, 0));
9171 fb->height = ((val >> 16) & 0xfff) + 1;
9172 fb->width = ((val >> 0) & 0x1fff) + 1;
9173
9174 val = I915_READ(PLANE_STRIDE(pipe, 0));
9175 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9176 fb->pixel_format);
9177 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9178
9179 aligned_height = intel_fb_align_height(dev, fb->height,
9180 fb->pixel_format,
9181 fb->modifier[0]);
9182
9183 plane_config->size = fb->pitches[0] * aligned_height;
9184
9185 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9186 pipe_name(pipe), fb->width, fb->height,
9187 fb->bits_per_pixel, base, fb->pitches[0],
9188 plane_config->size);
9189
9190 plane_config->fb = intel_fb;
9191 return;
9192
9193 error:
9194 kfree(fb);
9195 }
9196
9197 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9198 struct intel_crtc_state *pipe_config)
9199 {
9200 struct drm_device *dev = crtc->base.dev;
9201 struct drm_i915_private *dev_priv = dev->dev_private;
9202 uint32_t tmp;
9203
9204 tmp = I915_READ(PF_CTL(crtc->pipe));
9205
9206 if (tmp & PF_ENABLE) {
9207 pipe_config->pch_pfit.enabled = true;
9208 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9209 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9210
9211 /* We currently do not free assignements of panel fitters on
9212 * ivb/hsw (since we don't use the higher upscaling modes which
9213 * differentiates them) so just WARN about this case for now. */
9214 if (IS_GEN7(dev)) {
9215 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9216 PF_PIPE_SEL_IVB(crtc->pipe));
9217 }
9218 }
9219 }
9220
9221 static void
9222 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9223 struct intel_initial_plane_config *plane_config)
9224 {
9225 struct drm_device *dev = crtc->base.dev;
9226 struct drm_i915_private *dev_priv = dev->dev_private;
9227 u32 val, base, offset;
9228 int pipe = crtc->pipe;
9229 int fourcc, pixel_format;
9230 unsigned int aligned_height;
9231 struct drm_framebuffer *fb;
9232 struct intel_framebuffer *intel_fb;
9233
9234 val = I915_READ(DSPCNTR(pipe));
9235 if (!(val & DISPLAY_PLANE_ENABLE))
9236 return;
9237
9238 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9239 if (!intel_fb) {
9240 DRM_DEBUG_KMS("failed to alloc fb\n");
9241 return;
9242 }
9243
9244 fb = &intel_fb->base;
9245
9246 if (INTEL_INFO(dev)->gen >= 4) {
9247 if (val & DISPPLANE_TILED) {
9248 plane_config->tiling = I915_TILING_X;
9249 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9250 }
9251 }
9252
9253 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9254 fourcc = i9xx_format_to_fourcc(pixel_format);
9255 fb->pixel_format = fourcc;
9256 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9257
9258 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9259 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9260 offset = I915_READ(DSPOFFSET(pipe));
9261 } else {
9262 if (plane_config->tiling)
9263 offset = I915_READ(DSPTILEOFF(pipe));
9264 else
9265 offset = I915_READ(DSPLINOFF(pipe));
9266 }
9267 plane_config->base = base;
9268
9269 val = I915_READ(PIPESRC(pipe));
9270 fb->width = ((val >> 16) & 0xfff) + 1;
9271 fb->height = ((val >> 0) & 0xfff) + 1;
9272
9273 val = I915_READ(DSPSTRIDE(pipe));
9274 fb->pitches[0] = val & 0xffffffc0;
9275
9276 aligned_height = intel_fb_align_height(dev, fb->height,
9277 fb->pixel_format,
9278 fb->modifier[0]);
9279
9280 plane_config->size = fb->pitches[0] * aligned_height;
9281
9282 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9283 pipe_name(pipe), fb->width, fb->height,
9284 fb->bits_per_pixel, base, fb->pitches[0],
9285 plane_config->size);
9286
9287 plane_config->fb = intel_fb;
9288 }
9289
9290 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9291 struct intel_crtc_state *pipe_config)
9292 {
9293 struct drm_device *dev = crtc->base.dev;
9294 struct drm_i915_private *dev_priv = dev->dev_private;
9295 uint32_t tmp;
9296
9297 if (!intel_display_power_is_enabled(dev_priv,
9298 POWER_DOMAIN_PIPE(crtc->pipe)))
9299 return false;
9300
9301 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9302 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9303
9304 tmp = I915_READ(PIPECONF(crtc->pipe));
9305 if (!(tmp & PIPECONF_ENABLE))
9306 return false;
9307
9308 switch (tmp & PIPECONF_BPC_MASK) {
9309 case PIPECONF_6BPC:
9310 pipe_config->pipe_bpp = 18;
9311 break;
9312 case PIPECONF_8BPC:
9313 pipe_config->pipe_bpp = 24;
9314 break;
9315 case PIPECONF_10BPC:
9316 pipe_config->pipe_bpp = 30;
9317 break;
9318 case PIPECONF_12BPC:
9319 pipe_config->pipe_bpp = 36;
9320 break;
9321 default:
9322 break;
9323 }
9324
9325 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9326 pipe_config->limited_color_range = true;
9327
9328 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9329 struct intel_shared_dpll *pll;
9330
9331 pipe_config->has_pch_encoder = true;
9332
9333 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9334 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9335 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9336
9337 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9338
9339 if (HAS_PCH_IBX(dev_priv->dev)) {
9340 pipe_config->shared_dpll =
9341 (enum intel_dpll_id) crtc->pipe;
9342 } else {
9343 tmp = I915_READ(PCH_DPLL_SEL);
9344 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9345 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9346 else
9347 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9348 }
9349
9350 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9351
9352 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9353 &pipe_config->dpll_hw_state));
9354
9355 tmp = pipe_config->dpll_hw_state.dpll;
9356 pipe_config->pixel_multiplier =
9357 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9358 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9359
9360 ironlake_pch_clock_get(crtc, pipe_config);
9361 } else {
9362 pipe_config->pixel_multiplier = 1;
9363 }
9364
9365 intel_get_pipe_timings(crtc, pipe_config);
9366
9367 ironlake_get_pfit_config(crtc, pipe_config);
9368
9369 return true;
9370 }
9371
9372 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9373 {
9374 struct drm_device *dev = dev_priv->dev;
9375 struct intel_crtc *crtc;
9376
9377 for_each_intel_crtc(dev, crtc)
9378 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9379 pipe_name(crtc->pipe));
9380
9381 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9382 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9383 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9384 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9385 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9386 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9387 "CPU PWM1 enabled\n");
9388 if (IS_HASWELL(dev))
9389 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9390 "CPU PWM2 enabled\n");
9391 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9392 "PCH PWM1 enabled\n");
9393 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9394 "Utility pin enabled\n");
9395 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9396
9397 /*
9398 * In theory we can still leave IRQs enabled, as long as only the HPD
9399 * interrupts remain enabled. We used to check for that, but since it's
9400 * gen-specific and since we only disable LCPLL after we fully disable
9401 * the interrupts, the check below should be enough.
9402 */
9403 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9404 }
9405
9406 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9407 {
9408 struct drm_device *dev = dev_priv->dev;
9409
9410 if (IS_HASWELL(dev))
9411 return I915_READ(D_COMP_HSW);
9412 else
9413 return I915_READ(D_COMP_BDW);
9414 }
9415
9416 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9417 {
9418 struct drm_device *dev = dev_priv->dev;
9419
9420 if (IS_HASWELL(dev)) {
9421 mutex_lock(&dev_priv->rps.hw_lock);
9422 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9423 val))
9424 DRM_ERROR("Failed to write to D_COMP\n");
9425 mutex_unlock(&dev_priv->rps.hw_lock);
9426 } else {
9427 I915_WRITE(D_COMP_BDW, val);
9428 POSTING_READ(D_COMP_BDW);
9429 }
9430 }
9431
9432 /*
9433 * This function implements pieces of two sequences from BSpec:
9434 * - Sequence for display software to disable LCPLL
9435 * - Sequence for display software to allow package C8+
9436 * The steps implemented here are just the steps that actually touch the LCPLL
9437 * register. Callers should take care of disabling all the display engine
9438 * functions, doing the mode unset, fixing interrupts, etc.
9439 */
9440 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9441 bool switch_to_fclk, bool allow_power_down)
9442 {
9443 uint32_t val;
9444
9445 assert_can_disable_lcpll(dev_priv);
9446
9447 val = I915_READ(LCPLL_CTL);
9448
9449 if (switch_to_fclk) {
9450 val |= LCPLL_CD_SOURCE_FCLK;
9451 I915_WRITE(LCPLL_CTL, val);
9452
9453 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9454 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9455 DRM_ERROR("Switching to FCLK failed\n");
9456
9457 val = I915_READ(LCPLL_CTL);
9458 }
9459
9460 val |= LCPLL_PLL_DISABLE;
9461 I915_WRITE(LCPLL_CTL, val);
9462 POSTING_READ(LCPLL_CTL);
9463
9464 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9465 DRM_ERROR("LCPLL still locked\n");
9466
9467 val = hsw_read_dcomp(dev_priv);
9468 val |= D_COMP_COMP_DISABLE;
9469 hsw_write_dcomp(dev_priv, val);
9470 ndelay(100);
9471
9472 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9473 1))
9474 DRM_ERROR("D_COMP RCOMP still in progress\n");
9475
9476 if (allow_power_down) {
9477 val = I915_READ(LCPLL_CTL);
9478 val |= LCPLL_POWER_DOWN_ALLOW;
9479 I915_WRITE(LCPLL_CTL, val);
9480 POSTING_READ(LCPLL_CTL);
9481 }
9482 }
9483
9484 /*
9485 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9486 * source.
9487 */
9488 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9489 {
9490 uint32_t val;
9491
9492 val = I915_READ(LCPLL_CTL);
9493
9494 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9495 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9496 return;
9497
9498 /*
9499 * Make sure we're not on PC8 state before disabling PC8, otherwise
9500 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9501 */
9502 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9503
9504 if (val & LCPLL_POWER_DOWN_ALLOW) {
9505 val &= ~LCPLL_POWER_DOWN_ALLOW;
9506 I915_WRITE(LCPLL_CTL, val);
9507 POSTING_READ(LCPLL_CTL);
9508 }
9509
9510 val = hsw_read_dcomp(dev_priv);
9511 val |= D_COMP_COMP_FORCE;
9512 val &= ~D_COMP_COMP_DISABLE;
9513 hsw_write_dcomp(dev_priv, val);
9514
9515 val = I915_READ(LCPLL_CTL);
9516 val &= ~LCPLL_PLL_DISABLE;
9517 I915_WRITE(LCPLL_CTL, val);
9518
9519 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9520 DRM_ERROR("LCPLL not locked yet\n");
9521
9522 if (val & LCPLL_CD_SOURCE_FCLK) {
9523 val = I915_READ(LCPLL_CTL);
9524 val &= ~LCPLL_CD_SOURCE_FCLK;
9525 I915_WRITE(LCPLL_CTL, val);
9526
9527 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9528 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9529 DRM_ERROR("Switching back to LCPLL failed\n");
9530 }
9531
9532 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9533 intel_update_cdclk(dev_priv->dev);
9534 }
9535
9536 /*
9537 * Package states C8 and deeper are really deep PC states that can only be
9538 * reached when all the devices on the system allow it, so even if the graphics
9539 * device allows PC8+, it doesn't mean the system will actually get to these
9540 * states. Our driver only allows PC8+ when going into runtime PM.
9541 *
9542 * The requirements for PC8+ are that all the outputs are disabled, the power
9543 * well is disabled and most interrupts are disabled, and these are also
9544 * requirements for runtime PM. When these conditions are met, we manually do
9545 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9546 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9547 * hang the machine.
9548 *
9549 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9550 * the state of some registers, so when we come back from PC8+ we need to
9551 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9552 * need to take care of the registers kept by RC6. Notice that this happens even
9553 * if we don't put the device in PCI D3 state (which is what currently happens
9554 * because of the runtime PM support).
9555 *
9556 * For more, read "Display Sequences for Package C8" on the hardware
9557 * documentation.
9558 */
9559 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9560 {
9561 struct drm_device *dev = dev_priv->dev;
9562 uint32_t val;
9563
9564 DRM_DEBUG_KMS("Enabling package C8+\n");
9565
9566 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9567 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9568 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9569 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9570 }
9571
9572 lpt_disable_clkout_dp(dev);
9573 hsw_disable_lcpll(dev_priv, true, true);
9574 }
9575
9576 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9577 {
9578 struct drm_device *dev = dev_priv->dev;
9579 uint32_t val;
9580
9581 DRM_DEBUG_KMS("Disabling package C8+\n");
9582
9583 hsw_restore_lcpll(dev_priv);
9584 lpt_init_pch_refclk(dev);
9585
9586 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9587 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9588 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9589 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9590 }
9591
9592 intel_prepare_ddi(dev);
9593 }
9594
9595 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9596 {
9597 struct drm_device *dev = old_state->dev;
9598 struct drm_i915_private *dev_priv = dev->dev_private;
9599 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9600 int req_cdclk;
9601
9602 /* see the comment in valleyview_modeset_global_resources */
9603 if (WARN_ON(max_pixclk < 0))
9604 return;
9605
9606 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9607
9608 if (req_cdclk != dev_priv->cdclk_freq)
9609 broxton_set_cdclk(dev, req_cdclk);
9610 }
9611
9612 /* compute the max rate for new configuration */
9613 static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9614 {
9615 struct drm_device *dev = dev_priv->dev;
9616 struct intel_crtc *intel_crtc;
9617 struct drm_crtc *crtc;
9618 int max_pixel_rate = 0;
9619 int pixel_rate;
9620
9621 for_each_crtc(dev, crtc) {
9622 if (!crtc->state->enable)
9623 continue;
9624
9625 intel_crtc = to_intel_crtc(crtc);
9626 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9627
9628 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9629 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9630 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9631
9632 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9633 }
9634
9635 return max_pixel_rate;
9636 }
9637
9638 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9639 {
9640 struct drm_i915_private *dev_priv = dev->dev_private;
9641 uint32_t val, data;
9642 int ret;
9643
9644 if (WARN((I915_READ(LCPLL_CTL) &
9645 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9646 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9647 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9648 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9649 "trying to change cdclk frequency with cdclk not enabled\n"))
9650 return;
9651
9652 mutex_lock(&dev_priv->rps.hw_lock);
9653 ret = sandybridge_pcode_write(dev_priv,
9654 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9655 mutex_unlock(&dev_priv->rps.hw_lock);
9656 if (ret) {
9657 DRM_ERROR("failed to inform pcode about cdclk change\n");
9658 return;
9659 }
9660
9661 val = I915_READ(LCPLL_CTL);
9662 val |= LCPLL_CD_SOURCE_FCLK;
9663 I915_WRITE(LCPLL_CTL, val);
9664
9665 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9666 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9667 DRM_ERROR("Switching to FCLK failed\n");
9668
9669 val = I915_READ(LCPLL_CTL);
9670 val &= ~LCPLL_CLK_FREQ_MASK;
9671
9672 switch (cdclk) {
9673 case 450000:
9674 val |= LCPLL_CLK_FREQ_450;
9675 data = 0;
9676 break;
9677 case 540000:
9678 val |= LCPLL_CLK_FREQ_54O_BDW;
9679 data = 1;
9680 break;
9681 case 337500:
9682 val |= LCPLL_CLK_FREQ_337_5_BDW;
9683 data = 2;
9684 break;
9685 case 675000:
9686 val |= LCPLL_CLK_FREQ_675_BDW;
9687 data = 3;
9688 break;
9689 default:
9690 WARN(1, "invalid cdclk frequency\n");
9691 return;
9692 }
9693
9694 I915_WRITE(LCPLL_CTL, val);
9695
9696 val = I915_READ(LCPLL_CTL);
9697 val &= ~LCPLL_CD_SOURCE_FCLK;
9698 I915_WRITE(LCPLL_CTL, val);
9699
9700 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9701 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9702 DRM_ERROR("Switching back to LCPLL failed\n");
9703
9704 mutex_lock(&dev_priv->rps.hw_lock);
9705 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9706 mutex_unlock(&dev_priv->rps.hw_lock);
9707
9708 intel_update_cdclk(dev);
9709
9710 WARN(cdclk != dev_priv->cdclk_freq,
9711 "cdclk requested %d kHz but got %d kHz\n",
9712 cdclk, dev_priv->cdclk_freq);
9713 }
9714
9715 static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9716 int max_pixel_rate)
9717 {
9718 int cdclk;
9719
9720 /*
9721 * FIXME should also account for plane ratio
9722 * once 64bpp pixel formats are supported.
9723 */
9724 if (max_pixel_rate > 540000)
9725 cdclk = 675000;
9726 else if (max_pixel_rate > 450000)
9727 cdclk = 540000;
9728 else if (max_pixel_rate > 337500)
9729 cdclk = 450000;
9730 else
9731 cdclk = 337500;
9732
9733 /*
9734 * FIXME move the cdclk caclulation to
9735 * compute_config() so we can fail gracegully.
9736 */
9737 if (cdclk > dev_priv->max_cdclk_freq) {
9738 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9739 cdclk, dev_priv->max_cdclk_freq);
9740 cdclk = dev_priv->max_cdclk_freq;
9741 }
9742
9743 return cdclk;
9744 }
9745
9746 static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9747 {
9748 struct drm_i915_private *dev_priv = to_i915(state->dev);
9749 struct drm_crtc *crtc;
9750 struct drm_crtc_state *crtc_state;
9751 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9752 int cdclk, i;
9753
9754 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9755
9756 if (cdclk == dev_priv->cdclk_freq)
9757 return 0;
9758
9759 /* add all active pipes to the state */
9760 for_each_crtc(state->dev, crtc) {
9761 if (!crtc->state->enable)
9762 continue;
9763
9764 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9765 if (IS_ERR(crtc_state))
9766 return PTR_ERR(crtc_state);
9767 }
9768
9769 /* disable/enable all currently active pipes while we change cdclk */
9770 for_each_crtc_in_state(state, crtc, crtc_state, i)
9771 if (crtc_state->enable)
9772 crtc_state->mode_changed = true;
9773
9774 return 0;
9775 }
9776
9777 static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9778 {
9779 struct drm_device *dev = state->dev;
9780 struct drm_i915_private *dev_priv = dev->dev_private;
9781 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9782 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9783
9784 if (req_cdclk != dev_priv->cdclk_freq)
9785 broadwell_set_cdclk(dev, req_cdclk);
9786 }
9787
9788 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9789 struct intel_crtc_state *crtc_state)
9790 {
9791 if (!intel_ddi_pll_select(crtc, crtc_state))
9792 return -EINVAL;
9793
9794 crtc->lowfreq_avail = false;
9795
9796 return 0;
9797 }
9798
9799 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9800 enum port port,
9801 struct intel_crtc_state *pipe_config)
9802 {
9803 switch (port) {
9804 case PORT_A:
9805 pipe_config->ddi_pll_sel = SKL_DPLL0;
9806 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9807 break;
9808 case PORT_B:
9809 pipe_config->ddi_pll_sel = SKL_DPLL1;
9810 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9811 break;
9812 case PORT_C:
9813 pipe_config->ddi_pll_sel = SKL_DPLL2;
9814 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9815 break;
9816 default:
9817 DRM_ERROR("Incorrect port type\n");
9818 }
9819 }
9820
9821 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9822 enum port port,
9823 struct intel_crtc_state *pipe_config)
9824 {
9825 u32 temp, dpll_ctl1;
9826
9827 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9828 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9829
9830 switch (pipe_config->ddi_pll_sel) {
9831 case SKL_DPLL0:
9832 /*
9833 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9834 * of the shared DPLL framework and thus needs to be read out
9835 * separately
9836 */
9837 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9838 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9839 break;
9840 case SKL_DPLL1:
9841 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9842 break;
9843 case SKL_DPLL2:
9844 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9845 break;
9846 case SKL_DPLL3:
9847 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9848 break;
9849 }
9850 }
9851
9852 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9853 enum port port,
9854 struct intel_crtc_state *pipe_config)
9855 {
9856 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9857
9858 switch (pipe_config->ddi_pll_sel) {
9859 case PORT_CLK_SEL_WRPLL1:
9860 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9861 break;
9862 case PORT_CLK_SEL_WRPLL2:
9863 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9864 break;
9865 }
9866 }
9867
9868 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9869 struct intel_crtc_state *pipe_config)
9870 {
9871 struct drm_device *dev = crtc->base.dev;
9872 struct drm_i915_private *dev_priv = dev->dev_private;
9873 struct intel_shared_dpll *pll;
9874 enum port port;
9875 uint32_t tmp;
9876
9877 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9878
9879 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9880
9881 if (IS_SKYLAKE(dev))
9882 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9883 else if (IS_BROXTON(dev))
9884 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9885 else
9886 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9887
9888 if (pipe_config->shared_dpll >= 0) {
9889 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9890
9891 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9892 &pipe_config->dpll_hw_state));
9893 }
9894
9895 /*
9896 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9897 * DDI E. So just check whether this pipe is wired to DDI E and whether
9898 * the PCH transcoder is on.
9899 */
9900 if (INTEL_INFO(dev)->gen < 9 &&
9901 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9902 pipe_config->has_pch_encoder = true;
9903
9904 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9905 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9906 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9907
9908 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9909 }
9910 }
9911
9912 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9913 struct intel_crtc_state *pipe_config)
9914 {
9915 struct drm_device *dev = crtc->base.dev;
9916 struct drm_i915_private *dev_priv = dev->dev_private;
9917 enum intel_display_power_domain pfit_domain;
9918 uint32_t tmp;
9919
9920 if (!intel_display_power_is_enabled(dev_priv,
9921 POWER_DOMAIN_PIPE(crtc->pipe)))
9922 return false;
9923
9924 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9925 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9926
9927 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9928 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9929 enum pipe trans_edp_pipe;
9930 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9931 default:
9932 WARN(1, "unknown pipe linked to edp transcoder\n");
9933 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9934 case TRANS_DDI_EDP_INPUT_A_ON:
9935 trans_edp_pipe = PIPE_A;
9936 break;
9937 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9938 trans_edp_pipe = PIPE_B;
9939 break;
9940 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9941 trans_edp_pipe = PIPE_C;
9942 break;
9943 }
9944
9945 if (trans_edp_pipe == crtc->pipe)
9946 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9947 }
9948
9949 if (!intel_display_power_is_enabled(dev_priv,
9950 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9951 return false;
9952
9953 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9954 if (!(tmp & PIPECONF_ENABLE))
9955 return false;
9956
9957 haswell_get_ddi_port_state(crtc, pipe_config);
9958
9959 intel_get_pipe_timings(crtc, pipe_config);
9960
9961 if (INTEL_INFO(dev)->gen >= 9) {
9962 skl_init_scalers(dev, crtc, pipe_config);
9963 }
9964
9965 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9966
9967 if (INTEL_INFO(dev)->gen >= 9) {
9968 pipe_config->scaler_state.scaler_id = -1;
9969 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9970 }
9971
9972 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9973 if (INTEL_INFO(dev)->gen == 9)
9974 skylake_get_pfit_config(crtc, pipe_config);
9975 else if (INTEL_INFO(dev)->gen < 9)
9976 ironlake_get_pfit_config(crtc, pipe_config);
9977 else
9978 MISSING_CASE(INTEL_INFO(dev)->gen);
9979 }
9980
9981 if (IS_HASWELL(dev))
9982 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9983 (I915_READ(IPS_CTL) & IPS_ENABLE);
9984
9985 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9986 pipe_config->pixel_multiplier =
9987 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9988 } else {
9989 pipe_config->pixel_multiplier = 1;
9990 }
9991
9992 return true;
9993 }
9994
9995 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9996 {
9997 struct drm_device *dev = crtc->dev;
9998 struct drm_i915_private *dev_priv = dev->dev_private;
9999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10000 uint32_t cntl = 0, size = 0;
10001
10002 if (base) {
10003 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10004 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
10005 unsigned int stride = roundup_pow_of_two(width) * 4;
10006
10007 switch (stride) {
10008 default:
10009 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10010 width, stride);
10011 stride = 256;
10012 /* fallthrough */
10013 case 256:
10014 case 512:
10015 case 1024:
10016 case 2048:
10017 break;
10018 }
10019
10020 cntl |= CURSOR_ENABLE |
10021 CURSOR_GAMMA_ENABLE |
10022 CURSOR_FORMAT_ARGB |
10023 CURSOR_STRIDE(stride);
10024
10025 size = (height << 12) | width;
10026 }
10027
10028 if (intel_crtc->cursor_cntl != 0 &&
10029 (intel_crtc->cursor_base != base ||
10030 intel_crtc->cursor_size != size ||
10031 intel_crtc->cursor_cntl != cntl)) {
10032 /* On these chipsets we can only modify the base/size/stride
10033 * whilst the cursor is disabled.
10034 */
10035 I915_WRITE(_CURACNTR, 0);
10036 POSTING_READ(_CURACNTR);
10037 intel_crtc->cursor_cntl = 0;
10038 }
10039
10040 if (intel_crtc->cursor_base != base) {
10041 I915_WRITE(_CURABASE, base);
10042 intel_crtc->cursor_base = base;
10043 }
10044
10045 if (intel_crtc->cursor_size != size) {
10046 I915_WRITE(CURSIZE, size);
10047 intel_crtc->cursor_size = size;
10048 }
10049
10050 if (intel_crtc->cursor_cntl != cntl) {
10051 I915_WRITE(_CURACNTR, cntl);
10052 POSTING_READ(_CURACNTR);
10053 intel_crtc->cursor_cntl = cntl;
10054 }
10055 }
10056
10057 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10058 {
10059 struct drm_device *dev = crtc->dev;
10060 struct drm_i915_private *dev_priv = dev->dev_private;
10061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10062 int pipe = intel_crtc->pipe;
10063 uint32_t cntl;
10064
10065 cntl = 0;
10066 if (base) {
10067 cntl = MCURSOR_GAMMA_ENABLE;
10068 switch (intel_crtc->base.cursor->state->crtc_w) {
10069 case 64:
10070 cntl |= CURSOR_MODE_64_ARGB_AX;
10071 break;
10072 case 128:
10073 cntl |= CURSOR_MODE_128_ARGB_AX;
10074 break;
10075 case 256:
10076 cntl |= CURSOR_MODE_256_ARGB_AX;
10077 break;
10078 default:
10079 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10080 return;
10081 }
10082 cntl |= pipe << 28; /* Connect to correct pipe */
10083
10084 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10085 cntl |= CURSOR_PIPE_CSC_ENABLE;
10086 }
10087
10088 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10089 cntl |= CURSOR_ROTATE_180;
10090
10091 if (intel_crtc->cursor_cntl != cntl) {
10092 I915_WRITE(CURCNTR(pipe), cntl);
10093 POSTING_READ(CURCNTR(pipe));
10094 intel_crtc->cursor_cntl = cntl;
10095 }
10096
10097 /* and commit changes on next vblank */
10098 I915_WRITE(CURBASE(pipe), base);
10099 POSTING_READ(CURBASE(pipe));
10100
10101 intel_crtc->cursor_base = base;
10102 }
10103
10104 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10105 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10106 bool on)
10107 {
10108 struct drm_device *dev = crtc->dev;
10109 struct drm_i915_private *dev_priv = dev->dev_private;
10110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10111 int pipe = intel_crtc->pipe;
10112 int x = crtc->cursor_x;
10113 int y = crtc->cursor_y;
10114 u32 base = 0, pos = 0;
10115
10116 if (on)
10117 base = intel_crtc->cursor_addr;
10118
10119 if (x >= intel_crtc->config->pipe_src_w)
10120 base = 0;
10121
10122 if (y >= intel_crtc->config->pipe_src_h)
10123 base = 0;
10124
10125 if (x < 0) {
10126 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10127 base = 0;
10128
10129 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10130 x = -x;
10131 }
10132 pos |= x << CURSOR_X_SHIFT;
10133
10134 if (y < 0) {
10135 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10136 base = 0;
10137
10138 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10139 y = -y;
10140 }
10141 pos |= y << CURSOR_Y_SHIFT;
10142
10143 if (base == 0 && intel_crtc->cursor_base == 0)
10144 return;
10145
10146 I915_WRITE(CURPOS(pipe), pos);
10147
10148 /* ILK+ do this automagically */
10149 if (HAS_GMCH_DISPLAY(dev) &&
10150 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10151 base += (intel_crtc->base.cursor->state->crtc_h *
10152 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10153 }
10154
10155 if (IS_845G(dev) || IS_I865G(dev))
10156 i845_update_cursor(crtc, base);
10157 else
10158 i9xx_update_cursor(crtc, base);
10159 }
10160
10161 static bool cursor_size_ok(struct drm_device *dev,
10162 uint32_t width, uint32_t height)
10163 {
10164 if (width == 0 || height == 0)
10165 return false;
10166
10167 /*
10168 * 845g/865g are special in that they are only limited by
10169 * the width of their cursors, the height is arbitrary up to
10170 * the precision of the register. Everything else requires
10171 * square cursors, limited to a few power-of-two sizes.
10172 */
10173 if (IS_845G(dev) || IS_I865G(dev)) {
10174 if ((width & 63) != 0)
10175 return false;
10176
10177 if (width > (IS_845G(dev) ? 64 : 512))
10178 return false;
10179
10180 if (height > 1023)
10181 return false;
10182 } else {
10183 switch (width | height) {
10184 case 256:
10185 case 128:
10186 if (IS_GEN2(dev))
10187 return false;
10188 case 64:
10189 break;
10190 default:
10191 return false;
10192 }
10193 }
10194
10195 return true;
10196 }
10197
10198 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10199 u16 *blue, uint32_t start, uint32_t size)
10200 {
10201 int end = (start + size > 256) ? 256 : start + size, i;
10202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10203
10204 for (i = start; i < end; i++) {
10205 intel_crtc->lut_r[i] = red[i] >> 8;
10206 intel_crtc->lut_g[i] = green[i] >> 8;
10207 intel_crtc->lut_b[i] = blue[i] >> 8;
10208 }
10209
10210 intel_crtc_load_lut(crtc);
10211 }
10212
10213 /* VESA 640x480x72Hz mode to set on the pipe */
10214 static struct drm_display_mode load_detect_mode = {
10215 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10216 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10217 };
10218
10219 struct drm_framebuffer *
10220 __intel_framebuffer_create(struct drm_device *dev,
10221 struct drm_mode_fb_cmd2 *mode_cmd,
10222 struct drm_i915_gem_object *obj)
10223 {
10224 struct intel_framebuffer *intel_fb;
10225 int ret;
10226
10227 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10228 if (!intel_fb) {
10229 drm_gem_object_unreference(&obj->base);
10230 return ERR_PTR(-ENOMEM);
10231 }
10232
10233 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10234 if (ret)
10235 goto err;
10236
10237 return &intel_fb->base;
10238 err:
10239 drm_gem_object_unreference(&obj->base);
10240 kfree(intel_fb);
10241
10242 return ERR_PTR(ret);
10243 }
10244
10245 static struct drm_framebuffer *
10246 intel_framebuffer_create(struct drm_device *dev,
10247 struct drm_mode_fb_cmd2 *mode_cmd,
10248 struct drm_i915_gem_object *obj)
10249 {
10250 struct drm_framebuffer *fb;
10251 int ret;
10252
10253 ret = i915_mutex_lock_interruptible(dev);
10254 if (ret)
10255 return ERR_PTR(ret);
10256 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10257 mutex_unlock(&dev->struct_mutex);
10258
10259 return fb;
10260 }
10261
10262 static u32
10263 intel_framebuffer_pitch_for_width(int width, int bpp)
10264 {
10265 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10266 return ALIGN(pitch, 64);
10267 }
10268
10269 static u32
10270 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10271 {
10272 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10273 return PAGE_ALIGN(pitch * mode->vdisplay);
10274 }
10275
10276 static struct drm_framebuffer *
10277 intel_framebuffer_create_for_mode(struct drm_device *dev,
10278 struct drm_display_mode *mode,
10279 int depth, int bpp)
10280 {
10281 struct drm_i915_gem_object *obj;
10282 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10283
10284 obj = i915_gem_alloc_object(dev,
10285 intel_framebuffer_size_for_mode(mode, bpp));
10286 if (obj == NULL)
10287 return ERR_PTR(-ENOMEM);
10288
10289 mode_cmd.width = mode->hdisplay;
10290 mode_cmd.height = mode->vdisplay;
10291 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10292 bpp);
10293 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10294
10295 return intel_framebuffer_create(dev, &mode_cmd, obj);
10296 }
10297
10298 static struct drm_framebuffer *
10299 mode_fits_in_fbdev(struct drm_device *dev,
10300 struct drm_display_mode *mode)
10301 {
10302 #ifdef CONFIG_DRM_I915_FBDEV
10303 struct drm_i915_private *dev_priv = dev->dev_private;
10304 struct drm_i915_gem_object *obj;
10305 struct drm_framebuffer *fb;
10306
10307 if (!dev_priv->fbdev)
10308 return NULL;
10309
10310 if (!dev_priv->fbdev->fb)
10311 return NULL;
10312
10313 obj = dev_priv->fbdev->fb->obj;
10314 BUG_ON(!obj);
10315
10316 fb = &dev_priv->fbdev->fb->base;
10317 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10318 fb->bits_per_pixel))
10319 return NULL;
10320
10321 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10322 return NULL;
10323
10324 return fb;
10325 #else
10326 return NULL;
10327 #endif
10328 }
10329
10330 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10331 struct drm_crtc *crtc,
10332 struct drm_display_mode *mode,
10333 struct drm_framebuffer *fb,
10334 int x, int y)
10335 {
10336 struct drm_plane_state *plane_state;
10337 int hdisplay, vdisplay;
10338 int ret;
10339
10340 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10341 if (IS_ERR(plane_state))
10342 return PTR_ERR(plane_state);
10343
10344 if (mode)
10345 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10346 else
10347 hdisplay = vdisplay = 0;
10348
10349 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10350 if (ret)
10351 return ret;
10352 drm_atomic_set_fb_for_plane(plane_state, fb);
10353 plane_state->crtc_x = 0;
10354 plane_state->crtc_y = 0;
10355 plane_state->crtc_w = hdisplay;
10356 plane_state->crtc_h = vdisplay;
10357 plane_state->src_x = x << 16;
10358 plane_state->src_y = y << 16;
10359 plane_state->src_w = hdisplay << 16;
10360 plane_state->src_h = vdisplay << 16;
10361
10362 return 0;
10363 }
10364
10365 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10366 struct drm_display_mode *mode,
10367 struct intel_load_detect_pipe *old,
10368 struct drm_modeset_acquire_ctx *ctx)
10369 {
10370 struct intel_crtc *intel_crtc;
10371 struct intel_encoder *intel_encoder =
10372 intel_attached_encoder(connector);
10373 struct drm_crtc *possible_crtc;
10374 struct drm_encoder *encoder = &intel_encoder->base;
10375 struct drm_crtc *crtc = NULL;
10376 struct drm_device *dev = encoder->dev;
10377 struct drm_framebuffer *fb;
10378 struct drm_mode_config *config = &dev->mode_config;
10379 struct drm_atomic_state *state = NULL;
10380 struct drm_connector_state *connector_state;
10381 struct intel_crtc_state *crtc_state;
10382 int ret, i = -1;
10383
10384 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10385 connector->base.id, connector->name,
10386 encoder->base.id, encoder->name);
10387
10388 retry:
10389 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10390 if (ret)
10391 goto fail_unlock;
10392
10393 /*
10394 * Algorithm gets a little messy:
10395 *
10396 * - if the connector already has an assigned crtc, use it (but make
10397 * sure it's on first)
10398 *
10399 * - try to find the first unused crtc that can drive this connector,
10400 * and use that if we find one
10401 */
10402
10403 /* See if we already have a CRTC for this connector */
10404 if (encoder->crtc) {
10405 crtc = encoder->crtc;
10406
10407 ret = drm_modeset_lock(&crtc->mutex, ctx);
10408 if (ret)
10409 goto fail_unlock;
10410 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10411 if (ret)
10412 goto fail_unlock;
10413
10414 old->dpms_mode = connector->dpms;
10415 old->load_detect_temp = false;
10416
10417 /* Make sure the crtc and connector are running */
10418 if (connector->dpms != DRM_MODE_DPMS_ON)
10419 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10420
10421 return true;
10422 }
10423
10424 /* Find an unused one (if possible) */
10425 for_each_crtc(dev, possible_crtc) {
10426 i++;
10427 if (!(encoder->possible_crtcs & (1 << i)))
10428 continue;
10429 if (possible_crtc->state->enable)
10430 continue;
10431 /* This can occur when applying the pipe A quirk on resume. */
10432 if (to_intel_crtc(possible_crtc)->new_enabled)
10433 continue;
10434
10435 crtc = possible_crtc;
10436 break;
10437 }
10438
10439 /*
10440 * If we didn't find an unused CRTC, don't use any.
10441 */
10442 if (!crtc) {
10443 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10444 goto fail_unlock;
10445 }
10446
10447 ret = drm_modeset_lock(&crtc->mutex, ctx);
10448 if (ret)
10449 goto fail_unlock;
10450 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10451 if (ret)
10452 goto fail_unlock;
10453 intel_encoder->new_crtc = to_intel_crtc(crtc);
10454 to_intel_connector(connector)->new_encoder = intel_encoder;
10455
10456 intel_crtc = to_intel_crtc(crtc);
10457 intel_crtc->new_enabled = true;
10458 old->dpms_mode = connector->dpms;
10459 old->load_detect_temp = true;
10460 old->release_fb = NULL;
10461
10462 state = drm_atomic_state_alloc(dev);
10463 if (!state)
10464 return false;
10465
10466 state->acquire_ctx = ctx;
10467
10468 connector_state = drm_atomic_get_connector_state(state, connector);
10469 if (IS_ERR(connector_state)) {
10470 ret = PTR_ERR(connector_state);
10471 goto fail;
10472 }
10473
10474 connector_state->crtc = crtc;
10475 connector_state->best_encoder = &intel_encoder->base;
10476
10477 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10478 if (IS_ERR(crtc_state)) {
10479 ret = PTR_ERR(crtc_state);
10480 goto fail;
10481 }
10482
10483 crtc_state->base.active = crtc_state->base.enable = true;
10484
10485 if (!mode)
10486 mode = &load_detect_mode;
10487
10488 /* We need a framebuffer large enough to accommodate all accesses
10489 * that the plane may generate whilst we perform load detection.
10490 * We can not rely on the fbcon either being present (we get called
10491 * during its initialisation to detect all boot displays, or it may
10492 * not even exist) or that it is large enough to satisfy the
10493 * requested mode.
10494 */
10495 fb = mode_fits_in_fbdev(dev, mode);
10496 if (fb == NULL) {
10497 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10498 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10499 old->release_fb = fb;
10500 } else
10501 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10502 if (IS_ERR(fb)) {
10503 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10504 goto fail;
10505 }
10506
10507 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10508 if (ret)
10509 goto fail;
10510
10511 drm_mode_copy(&crtc_state->base.mode, mode);
10512
10513 if (intel_set_mode(state)) {
10514 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10515 if (old->release_fb)
10516 old->release_fb->funcs->destroy(old->release_fb);
10517 goto fail;
10518 }
10519 crtc->primary->crtc = crtc;
10520
10521 /* let the connector get through one full cycle before testing */
10522 intel_wait_for_vblank(dev, intel_crtc->pipe);
10523 return true;
10524
10525 fail:
10526 intel_crtc->new_enabled = crtc->state->enable;
10527 fail_unlock:
10528 drm_atomic_state_free(state);
10529 state = NULL;
10530
10531 if (ret == -EDEADLK) {
10532 drm_modeset_backoff(ctx);
10533 goto retry;
10534 }
10535
10536 return false;
10537 }
10538
10539 void intel_release_load_detect_pipe(struct drm_connector *connector,
10540 struct intel_load_detect_pipe *old,
10541 struct drm_modeset_acquire_ctx *ctx)
10542 {
10543 struct drm_device *dev = connector->dev;
10544 struct intel_encoder *intel_encoder =
10545 intel_attached_encoder(connector);
10546 struct drm_encoder *encoder = &intel_encoder->base;
10547 struct drm_crtc *crtc = encoder->crtc;
10548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10549 struct drm_atomic_state *state;
10550 struct drm_connector_state *connector_state;
10551 struct intel_crtc_state *crtc_state;
10552 int ret;
10553
10554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10555 connector->base.id, connector->name,
10556 encoder->base.id, encoder->name);
10557
10558 if (old->load_detect_temp) {
10559 state = drm_atomic_state_alloc(dev);
10560 if (!state)
10561 goto fail;
10562
10563 state->acquire_ctx = ctx;
10564
10565 connector_state = drm_atomic_get_connector_state(state, connector);
10566 if (IS_ERR(connector_state))
10567 goto fail;
10568
10569 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10570 if (IS_ERR(crtc_state))
10571 goto fail;
10572
10573 to_intel_connector(connector)->new_encoder = NULL;
10574 intel_encoder->new_crtc = NULL;
10575 intel_crtc->new_enabled = false;
10576
10577 connector_state->best_encoder = NULL;
10578 connector_state->crtc = NULL;
10579
10580 crtc_state->base.enable = crtc_state->base.active = false;
10581
10582 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10583 0, 0);
10584 if (ret)
10585 goto fail;
10586
10587 ret = intel_set_mode(state);
10588 if (ret)
10589 goto fail;
10590
10591 if (old->release_fb) {
10592 drm_framebuffer_unregister_private(old->release_fb);
10593 drm_framebuffer_unreference(old->release_fb);
10594 }
10595
10596 return;
10597 }
10598
10599 /* Switch crtc and encoder back off if necessary */
10600 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10601 connector->funcs->dpms(connector, old->dpms_mode);
10602
10603 return;
10604 fail:
10605 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10606 drm_atomic_state_free(state);
10607 }
10608
10609 static int i9xx_pll_refclk(struct drm_device *dev,
10610 const struct intel_crtc_state *pipe_config)
10611 {
10612 struct drm_i915_private *dev_priv = dev->dev_private;
10613 u32 dpll = pipe_config->dpll_hw_state.dpll;
10614
10615 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10616 return dev_priv->vbt.lvds_ssc_freq;
10617 else if (HAS_PCH_SPLIT(dev))
10618 return 120000;
10619 else if (!IS_GEN2(dev))
10620 return 96000;
10621 else
10622 return 48000;
10623 }
10624
10625 /* Returns the clock of the currently programmed mode of the given pipe. */
10626 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10627 struct intel_crtc_state *pipe_config)
10628 {
10629 struct drm_device *dev = crtc->base.dev;
10630 struct drm_i915_private *dev_priv = dev->dev_private;
10631 int pipe = pipe_config->cpu_transcoder;
10632 u32 dpll = pipe_config->dpll_hw_state.dpll;
10633 u32 fp;
10634 intel_clock_t clock;
10635 int refclk = i9xx_pll_refclk(dev, pipe_config);
10636
10637 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10638 fp = pipe_config->dpll_hw_state.fp0;
10639 else
10640 fp = pipe_config->dpll_hw_state.fp1;
10641
10642 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10643 if (IS_PINEVIEW(dev)) {
10644 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10645 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10646 } else {
10647 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10648 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10649 }
10650
10651 if (!IS_GEN2(dev)) {
10652 if (IS_PINEVIEW(dev))
10653 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10654 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10655 else
10656 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10657 DPLL_FPA01_P1_POST_DIV_SHIFT);
10658
10659 switch (dpll & DPLL_MODE_MASK) {
10660 case DPLLB_MODE_DAC_SERIAL:
10661 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10662 5 : 10;
10663 break;
10664 case DPLLB_MODE_LVDS:
10665 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10666 7 : 14;
10667 break;
10668 default:
10669 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10670 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10671 return;
10672 }
10673
10674 if (IS_PINEVIEW(dev))
10675 pineview_clock(refclk, &clock);
10676 else
10677 i9xx_clock(refclk, &clock);
10678 } else {
10679 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10680 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10681
10682 if (is_lvds) {
10683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10684 DPLL_FPA01_P1_POST_DIV_SHIFT);
10685
10686 if (lvds & LVDS_CLKB_POWER_UP)
10687 clock.p2 = 7;
10688 else
10689 clock.p2 = 14;
10690 } else {
10691 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10692 clock.p1 = 2;
10693 else {
10694 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10695 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10696 }
10697 if (dpll & PLL_P2_DIVIDE_BY_4)
10698 clock.p2 = 4;
10699 else
10700 clock.p2 = 2;
10701 }
10702
10703 i9xx_clock(refclk, &clock);
10704 }
10705
10706 /*
10707 * This value includes pixel_multiplier. We will use
10708 * port_clock to compute adjusted_mode.crtc_clock in the
10709 * encoder's get_config() function.
10710 */
10711 pipe_config->port_clock = clock.dot;
10712 }
10713
10714 int intel_dotclock_calculate(int link_freq,
10715 const struct intel_link_m_n *m_n)
10716 {
10717 /*
10718 * The calculation for the data clock is:
10719 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10720 * But we want to avoid losing precison if possible, so:
10721 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10722 *
10723 * and the link clock is simpler:
10724 * link_clock = (m * link_clock) / n
10725 */
10726
10727 if (!m_n->link_n)
10728 return 0;
10729
10730 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10731 }
10732
10733 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10734 struct intel_crtc_state *pipe_config)
10735 {
10736 struct drm_device *dev = crtc->base.dev;
10737
10738 /* read out port_clock from the DPLL */
10739 i9xx_crtc_clock_get(crtc, pipe_config);
10740
10741 /*
10742 * This value does not include pixel_multiplier.
10743 * We will check that port_clock and adjusted_mode.crtc_clock
10744 * agree once we know their relationship in the encoder's
10745 * get_config() function.
10746 */
10747 pipe_config->base.adjusted_mode.crtc_clock =
10748 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10749 &pipe_config->fdi_m_n);
10750 }
10751
10752 /** Returns the currently programmed mode of the given pipe. */
10753 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10754 struct drm_crtc *crtc)
10755 {
10756 struct drm_i915_private *dev_priv = dev->dev_private;
10757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10758 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10759 struct drm_display_mode *mode;
10760 struct intel_crtc_state pipe_config;
10761 int htot = I915_READ(HTOTAL(cpu_transcoder));
10762 int hsync = I915_READ(HSYNC(cpu_transcoder));
10763 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10764 int vsync = I915_READ(VSYNC(cpu_transcoder));
10765 enum pipe pipe = intel_crtc->pipe;
10766
10767 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10768 if (!mode)
10769 return NULL;
10770
10771 /*
10772 * Construct a pipe_config sufficient for getting the clock info
10773 * back out of crtc_clock_get.
10774 *
10775 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10776 * to use a real value here instead.
10777 */
10778 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10779 pipe_config.pixel_multiplier = 1;
10780 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10781 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10782 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10783 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10784
10785 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10786 mode->hdisplay = (htot & 0xffff) + 1;
10787 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10788 mode->hsync_start = (hsync & 0xffff) + 1;
10789 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10790 mode->vdisplay = (vtot & 0xffff) + 1;
10791 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10792 mode->vsync_start = (vsync & 0xffff) + 1;
10793 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10794
10795 drm_mode_set_name(mode);
10796
10797 return mode;
10798 }
10799
10800 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10801 {
10802 struct drm_device *dev = crtc->dev;
10803 struct drm_i915_private *dev_priv = dev->dev_private;
10804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10805
10806 if (!HAS_GMCH_DISPLAY(dev))
10807 return;
10808
10809 if (!dev_priv->lvds_downclock_avail)
10810 return;
10811
10812 /*
10813 * Since this is called by a timer, we should never get here in
10814 * the manual case.
10815 */
10816 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10817 int pipe = intel_crtc->pipe;
10818 int dpll_reg = DPLL(pipe);
10819 int dpll;
10820
10821 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10822
10823 assert_panel_unlocked(dev_priv, pipe);
10824
10825 dpll = I915_READ(dpll_reg);
10826 dpll |= DISPLAY_RATE_SELECT_FPA1;
10827 I915_WRITE(dpll_reg, dpll);
10828 intel_wait_for_vblank(dev, pipe);
10829 dpll = I915_READ(dpll_reg);
10830 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10831 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10832 }
10833
10834 }
10835
10836 void intel_mark_busy(struct drm_device *dev)
10837 {
10838 struct drm_i915_private *dev_priv = dev->dev_private;
10839
10840 if (dev_priv->mm.busy)
10841 return;
10842
10843 intel_runtime_pm_get(dev_priv);
10844 i915_update_gfx_val(dev_priv);
10845 if (INTEL_INFO(dev)->gen >= 6)
10846 gen6_rps_busy(dev_priv);
10847 dev_priv->mm.busy = true;
10848 }
10849
10850 void intel_mark_idle(struct drm_device *dev)
10851 {
10852 struct drm_i915_private *dev_priv = dev->dev_private;
10853 struct drm_crtc *crtc;
10854
10855 if (!dev_priv->mm.busy)
10856 return;
10857
10858 dev_priv->mm.busy = false;
10859
10860 for_each_crtc(dev, crtc) {
10861 if (!crtc->primary->fb)
10862 continue;
10863
10864 intel_decrease_pllclock(crtc);
10865 }
10866
10867 if (INTEL_INFO(dev)->gen >= 6)
10868 gen6_rps_idle(dev->dev_private);
10869
10870 intel_runtime_pm_put(dev_priv);
10871 }
10872
10873 static void intel_crtc_destroy(struct drm_crtc *crtc)
10874 {
10875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10876 struct drm_device *dev = crtc->dev;
10877 struct intel_unpin_work *work;
10878
10879 spin_lock_irq(&dev->event_lock);
10880 work = intel_crtc->unpin_work;
10881 intel_crtc->unpin_work = NULL;
10882 spin_unlock_irq(&dev->event_lock);
10883
10884 if (work) {
10885 cancel_work_sync(&work->work);
10886 kfree(work);
10887 }
10888
10889 drm_crtc_cleanup(crtc);
10890
10891 kfree(intel_crtc);
10892 }
10893
10894 static void intel_unpin_work_fn(struct work_struct *__work)
10895 {
10896 struct intel_unpin_work *work =
10897 container_of(__work, struct intel_unpin_work, work);
10898 struct drm_device *dev = work->crtc->dev;
10899 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10900
10901 mutex_lock(&dev->struct_mutex);
10902 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10903 drm_gem_object_unreference(&work->pending_flip_obj->base);
10904
10905 intel_fbc_update(dev);
10906
10907 if (work->flip_queued_req)
10908 i915_gem_request_assign(&work->flip_queued_req, NULL);
10909 mutex_unlock(&dev->struct_mutex);
10910
10911 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10912 drm_framebuffer_unreference(work->old_fb);
10913
10914 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10915 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10916
10917 kfree(work);
10918 }
10919
10920 static void do_intel_finish_page_flip(struct drm_device *dev,
10921 struct drm_crtc *crtc)
10922 {
10923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10924 struct intel_unpin_work *work;
10925 unsigned long flags;
10926
10927 /* Ignore early vblank irqs */
10928 if (intel_crtc == NULL)
10929 return;
10930
10931 /*
10932 * This is called both by irq handlers and the reset code (to complete
10933 * lost pageflips) so needs the full irqsave spinlocks.
10934 */
10935 spin_lock_irqsave(&dev->event_lock, flags);
10936 work = intel_crtc->unpin_work;
10937
10938 /* Ensure we don't miss a work->pending update ... */
10939 smp_rmb();
10940
10941 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10942 spin_unlock_irqrestore(&dev->event_lock, flags);
10943 return;
10944 }
10945
10946 page_flip_completed(intel_crtc);
10947
10948 spin_unlock_irqrestore(&dev->event_lock, flags);
10949 }
10950
10951 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10952 {
10953 struct drm_i915_private *dev_priv = dev->dev_private;
10954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10955
10956 do_intel_finish_page_flip(dev, crtc);
10957 }
10958
10959 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10960 {
10961 struct drm_i915_private *dev_priv = dev->dev_private;
10962 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10963
10964 do_intel_finish_page_flip(dev, crtc);
10965 }
10966
10967 /* Is 'a' after or equal to 'b'? */
10968 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10969 {
10970 return !((a - b) & 0x80000000);
10971 }
10972
10973 static bool page_flip_finished(struct intel_crtc *crtc)
10974 {
10975 struct drm_device *dev = crtc->base.dev;
10976 struct drm_i915_private *dev_priv = dev->dev_private;
10977
10978 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10979 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10980 return true;
10981
10982 /*
10983 * The relevant registers doen't exist on pre-ctg.
10984 * As the flip done interrupt doesn't trigger for mmio
10985 * flips on gmch platforms, a flip count check isn't
10986 * really needed there. But since ctg has the registers,
10987 * include it in the check anyway.
10988 */
10989 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10990 return true;
10991
10992 /*
10993 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10994 * used the same base address. In that case the mmio flip might
10995 * have completed, but the CS hasn't even executed the flip yet.
10996 *
10997 * A flip count check isn't enough as the CS might have updated
10998 * the base address just after start of vblank, but before we
10999 * managed to process the interrupt. This means we'd complete the
11000 * CS flip too soon.
11001 *
11002 * Combining both checks should get us a good enough result. It may
11003 * still happen that the CS flip has been executed, but has not
11004 * yet actually completed. But in case the base address is the same
11005 * anyway, we don't really care.
11006 */
11007 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11008 crtc->unpin_work->gtt_offset &&
11009 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
11010 crtc->unpin_work->flip_count);
11011 }
11012
11013 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11014 {
11015 struct drm_i915_private *dev_priv = dev->dev_private;
11016 struct intel_crtc *intel_crtc =
11017 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11018 unsigned long flags;
11019
11020
11021 /*
11022 * This is called both by irq handlers and the reset code (to complete
11023 * lost pageflips) so needs the full irqsave spinlocks.
11024 *
11025 * NB: An MMIO update of the plane base pointer will also
11026 * generate a page-flip completion irq, i.e. every modeset
11027 * is also accompanied by a spurious intel_prepare_page_flip().
11028 */
11029 spin_lock_irqsave(&dev->event_lock, flags);
11030 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11031 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11032 spin_unlock_irqrestore(&dev->event_lock, flags);
11033 }
11034
11035 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
11036 {
11037 /* Ensure that the work item is consistent when activating it ... */
11038 smp_wmb();
11039 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11040 /* and that it is marked active as soon as the irq could fire. */
11041 smp_wmb();
11042 }
11043
11044 static int intel_gen2_queue_flip(struct drm_device *dev,
11045 struct drm_crtc *crtc,
11046 struct drm_framebuffer *fb,
11047 struct drm_i915_gem_object *obj,
11048 struct intel_engine_cs *ring,
11049 uint32_t flags)
11050 {
11051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11052 u32 flip_mask;
11053 int ret;
11054
11055 ret = intel_ring_begin(ring, 6);
11056 if (ret)
11057 return ret;
11058
11059 /* Can't queue multiple flips, so wait for the previous
11060 * one to finish before executing the next.
11061 */
11062 if (intel_crtc->plane)
11063 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11064 else
11065 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11066 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11067 intel_ring_emit(ring, MI_NOOP);
11068 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11069 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11070 intel_ring_emit(ring, fb->pitches[0]);
11071 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11072 intel_ring_emit(ring, 0); /* aux display base address, unused */
11073
11074 intel_mark_page_flip_active(intel_crtc);
11075 __intel_ring_advance(ring);
11076 return 0;
11077 }
11078
11079 static int intel_gen3_queue_flip(struct drm_device *dev,
11080 struct drm_crtc *crtc,
11081 struct drm_framebuffer *fb,
11082 struct drm_i915_gem_object *obj,
11083 struct intel_engine_cs *ring,
11084 uint32_t flags)
11085 {
11086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11087 u32 flip_mask;
11088 int ret;
11089
11090 ret = intel_ring_begin(ring, 6);
11091 if (ret)
11092 return ret;
11093
11094 if (intel_crtc->plane)
11095 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11096 else
11097 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11098 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11099 intel_ring_emit(ring, MI_NOOP);
11100 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11101 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11102 intel_ring_emit(ring, fb->pitches[0]);
11103 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11104 intel_ring_emit(ring, MI_NOOP);
11105
11106 intel_mark_page_flip_active(intel_crtc);
11107 __intel_ring_advance(ring);
11108 return 0;
11109 }
11110
11111 static int intel_gen4_queue_flip(struct drm_device *dev,
11112 struct drm_crtc *crtc,
11113 struct drm_framebuffer *fb,
11114 struct drm_i915_gem_object *obj,
11115 struct intel_engine_cs *ring,
11116 uint32_t flags)
11117 {
11118 struct drm_i915_private *dev_priv = dev->dev_private;
11119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11120 uint32_t pf, pipesrc;
11121 int ret;
11122
11123 ret = intel_ring_begin(ring, 4);
11124 if (ret)
11125 return ret;
11126
11127 /* i965+ uses the linear or tiled offsets from the
11128 * Display Registers (which do not change across a page-flip)
11129 * so we need only reprogram the base address.
11130 */
11131 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11132 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11133 intel_ring_emit(ring, fb->pitches[0]);
11134 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11135 obj->tiling_mode);
11136
11137 /* XXX Enabling the panel-fitter across page-flip is so far
11138 * untested on non-native modes, so ignore it for now.
11139 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11140 */
11141 pf = 0;
11142 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11143 intel_ring_emit(ring, pf | pipesrc);
11144
11145 intel_mark_page_flip_active(intel_crtc);
11146 __intel_ring_advance(ring);
11147 return 0;
11148 }
11149
11150 static int intel_gen6_queue_flip(struct drm_device *dev,
11151 struct drm_crtc *crtc,
11152 struct drm_framebuffer *fb,
11153 struct drm_i915_gem_object *obj,
11154 struct intel_engine_cs *ring,
11155 uint32_t flags)
11156 {
11157 struct drm_i915_private *dev_priv = dev->dev_private;
11158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11159 uint32_t pf, pipesrc;
11160 int ret;
11161
11162 ret = intel_ring_begin(ring, 4);
11163 if (ret)
11164 return ret;
11165
11166 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11167 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11168 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11169 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11170
11171 /* Contrary to the suggestions in the documentation,
11172 * "Enable Panel Fitter" does not seem to be required when page
11173 * flipping with a non-native mode, and worse causes a normal
11174 * modeset to fail.
11175 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11176 */
11177 pf = 0;
11178 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11179 intel_ring_emit(ring, pf | pipesrc);
11180
11181 intel_mark_page_flip_active(intel_crtc);
11182 __intel_ring_advance(ring);
11183 return 0;
11184 }
11185
11186 static int intel_gen7_queue_flip(struct drm_device *dev,
11187 struct drm_crtc *crtc,
11188 struct drm_framebuffer *fb,
11189 struct drm_i915_gem_object *obj,
11190 struct intel_engine_cs *ring,
11191 uint32_t flags)
11192 {
11193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11194 uint32_t plane_bit = 0;
11195 int len, ret;
11196
11197 switch (intel_crtc->plane) {
11198 case PLANE_A:
11199 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11200 break;
11201 case PLANE_B:
11202 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11203 break;
11204 case PLANE_C:
11205 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11206 break;
11207 default:
11208 WARN_ONCE(1, "unknown plane in flip command\n");
11209 return -ENODEV;
11210 }
11211
11212 len = 4;
11213 if (ring->id == RCS) {
11214 len += 6;
11215 /*
11216 * On Gen 8, SRM is now taking an extra dword to accommodate
11217 * 48bits addresses, and we need a NOOP for the batch size to
11218 * stay even.
11219 */
11220 if (IS_GEN8(dev))
11221 len += 2;
11222 }
11223
11224 /*
11225 * BSpec MI_DISPLAY_FLIP for IVB:
11226 * "The full packet must be contained within the same cache line."
11227 *
11228 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11229 * cacheline, if we ever start emitting more commands before
11230 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11231 * then do the cacheline alignment, and finally emit the
11232 * MI_DISPLAY_FLIP.
11233 */
11234 ret = intel_ring_cacheline_align(ring);
11235 if (ret)
11236 return ret;
11237
11238 ret = intel_ring_begin(ring, len);
11239 if (ret)
11240 return ret;
11241
11242 /* Unmask the flip-done completion message. Note that the bspec says that
11243 * we should do this for both the BCS and RCS, and that we must not unmask
11244 * more than one flip event at any time (or ensure that one flip message
11245 * can be sent by waiting for flip-done prior to queueing new flips).
11246 * Experimentation says that BCS works despite DERRMR masking all
11247 * flip-done completion events and that unmasking all planes at once
11248 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11249 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11250 */
11251 if (ring->id == RCS) {
11252 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11253 intel_ring_emit(ring, DERRMR);
11254 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11255 DERRMR_PIPEB_PRI_FLIP_DONE |
11256 DERRMR_PIPEC_PRI_FLIP_DONE));
11257 if (IS_GEN8(dev))
11258 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11259 MI_SRM_LRM_GLOBAL_GTT);
11260 else
11261 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11262 MI_SRM_LRM_GLOBAL_GTT);
11263 intel_ring_emit(ring, DERRMR);
11264 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11265 if (IS_GEN8(dev)) {
11266 intel_ring_emit(ring, 0);
11267 intel_ring_emit(ring, MI_NOOP);
11268 }
11269 }
11270
11271 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11272 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11273 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11274 intel_ring_emit(ring, (MI_NOOP));
11275
11276 intel_mark_page_flip_active(intel_crtc);
11277 __intel_ring_advance(ring);
11278 return 0;
11279 }
11280
11281 static bool use_mmio_flip(struct intel_engine_cs *ring,
11282 struct drm_i915_gem_object *obj)
11283 {
11284 /*
11285 * This is not being used for older platforms, because
11286 * non-availability of flip done interrupt forces us to use
11287 * CS flips. Older platforms derive flip done using some clever
11288 * tricks involving the flip_pending status bits and vblank irqs.
11289 * So using MMIO flips there would disrupt this mechanism.
11290 */
11291
11292 if (ring == NULL)
11293 return true;
11294
11295 if (INTEL_INFO(ring->dev)->gen < 5)
11296 return false;
11297
11298 if (i915.use_mmio_flip < 0)
11299 return false;
11300 else if (i915.use_mmio_flip > 0)
11301 return true;
11302 else if (i915.enable_execlists)
11303 return true;
11304 else
11305 return ring != i915_gem_request_get_ring(obj->last_write_req);
11306 }
11307
11308 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11309 {
11310 struct drm_device *dev = intel_crtc->base.dev;
11311 struct drm_i915_private *dev_priv = dev->dev_private;
11312 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11313 const enum pipe pipe = intel_crtc->pipe;
11314 u32 ctl, stride;
11315
11316 ctl = I915_READ(PLANE_CTL(pipe, 0));
11317 ctl &= ~PLANE_CTL_TILED_MASK;
11318 switch (fb->modifier[0]) {
11319 case DRM_FORMAT_MOD_NONE:
11320 break;
11321 case I915_FORMAT_MOD_X_TILED:
11322 ctl |= PLANE_CTL_TILED_X;
11323 break;
11324 case I915_FORMAT_MOD_Y_TILED:
11325 ctl |= PLANE_CTL_TILED_Y;
11326 break;
11327 case I915_FORMAT_MOD_Yf_TILED:
11328 ctl |= PLANE_CTL_TILED_YF;
11329 break;
11330 default:
11331 MISSING_CASE(fb->modifier[0]);
11332 }
11333
11334 /*
11335 * The stride is either expressed as a multiple of 64 bytes chunks for
11336 * linear buffers or in number of tiles for tiled buffers.
11337 */
11338 stride = fb->pitches[0] /
11339 intel_fb_stride_alignment(dev, fb->modifier[0],
11340 fb->pixel_format);
11341
11342 /*
11343 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11344 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11345 */
11346 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11347 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11348
11349 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11350 POSTING_READ(PLANE_SURF(pipe, 0));
11351 }
11352
11353 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11354 {
11355 struct drm_device *dev = intel_crtc->base.dev;
11356 struct drm_i915_private *dev_priv = dev->dev_private;
11357 struct intel_framebuffer *intel_fb =
11358 to_intel_framebuffer(intel_crtc->base.primary->fb);
11359 struct drm_i915_gem_object *obj = intel_fb->obj;
11360 u32 dspcntr;
11361 u32 reg;
11362
11363 reg = DSPCNTR(intel_crtc->plane);
11364 dspcntr = I915_READ(reg);
11365
11366 if (obj->tiling_mode != I915_TILING_NONE)
11367 dspcntr |= DISPPLANE_TILED;
11368 else
11369 dspcntr &= ~DISPPLANE_TILED;
11370
11371 I915_WRITE(reg, dspcntr);
11372
11373 I915_WRITE(DSPSURF(intel_crtc->plane),
11374 intel_crtc->unpin_work->gtt_offset);
11375 POSTING_READ(DSPSURF(intel_crtc->plane));
11376
11377 }
11378
11379 /*
11380 * XXX: This is the temporary way to update the plane registers until we get
11381 * around to using the usual plane update functions for MMIO flips
11382 */
11383 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11384 {
11385 struct drm_device *dev = intel_crtc->base.dev;
11386 bool atomic_update;
11387 u32 start_vbl_count;
11388
11389 intel_mark_page_flip_active(intel_crtc);
11390
11391 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11392
11393 if (INTEL_INFO(dev)->gen >= 9)
11394 skl_do_mmio_flip(intel_crtc);
11395 else
11396 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11397 ilk_do_mmio_flip(intel_crtc);
11398
11399 if (atomic_update)
11400 intel_pipe_update_end(intel_crtc, start_vbl_count);
11401 }
11402
11403 static void intel_mmio_flip_work_func(struct work_struct *work)
11404 {
11405 struct intel_mmio_flip *mmio_flip =
11406 container_of(work, struct intel_mmio_flip, work);
11407
11408 if (mmio_flip->req)
11409 WARN_ON(__i915_wait_request(mmio_flip->req,
11410 mmio_flip->crtc->reset_counter,
11411 false, NULL,
11412 &mmio_flip->i915->rps.mmioflips));
11413
11414 intel_do_mmio_flip(mmio_flip->crtc);
11415
11416 i915_gem_request_unreference__unlocked(mmio_flip->req);
11417 kfree(mmio_flip);
11418 }
11419
11420 static int intel_queue_mmio_flip(struct drm_device *dev,
11421 struct drm_crtc *crtc,
11422 struct drm_framebuffer *fb,
11423 struct drm_i915_gem_object *obj,
11424 struct intel_engine_cs *ring,
11425 uint32_t flags)
11426 {
11427 struct intel_mmio_flip *mmio_flip;
11428
11429 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11430 if (mmio_flip == NULL)
11431 return -ENOMEM;
11432
11433 mmio_flip->i915 = to_i915(dev);
11434 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11435 mmio_flip->crtc = to_intel_crtc(crtc);
11436
11437 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11438 schedule_work(&mmio_flip->work);
11439
11440 return 0;
11441 }
11442
11443 static int intel_default_queue_flip(struct drm_device *dev,
11444 struct drm_crtc *crtc,
11445 struct drm_framebuffer *fb,
11446 struct drm_i915_gem_object *obj,
11447 struct intel_engine_cs *ring,
11448 uint32_t flags)
11449 {
11450 return -ENODEV;
11451 }
11452
11453 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11454 struct drm_crtc *crtc)
11455 {
11456 struct drm_i915_private *dev_priv = dev->dev_private;
11457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11458 struct intel_unpin_work *work = intel_crtc->unpin_work;
11459 u32 addr;
11460
11461 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11462 return true;
11463
11464 if (!work->enable_stall_check)
11465 return false;
11466
11467 if (work->flip_ready_vblank == 0) {
11468 if (work->flip_queued_req &&
11469 !i915_gem_request_completed(work->flip_queued_req, true))
11470 return false;
11471
11472 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11473 }
11474
11475 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11476 return false;
11477
11478 /* Potential stall - if we see that the flip has happened,
11479 * assume a missed interrupt. */
11480 if (INTEL_INFO(dev)->gen >= 4)
11481 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11482 else
11483 addr = I915_READ(DSPADDR(intel_crtc->plane));
11484
11485 /* There is a potential issue here with a false positive after a flip
11486 * to the same address. We could address this by checking for a
11487 * non-incrementing frame counter.
11488 */
11489 return addr == work->gtt_offset;
11490 }
11491
11492 void intel_check_page_flip(struct drm_device *dev, int pipe)
11493 {
11494 struct drm_i915_private *dev_priv = dev->dev_private;
11495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11497 struct intel_unpin_work *work;
11498
11499 WARN_ON(!in_interrupt());
11500
11501 if (crtc == NULL)
11502 return;
11503
11504 spin_lock(&dev->event_lock);
11505 work = intel_crtc->unpin_work;
11506 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11507 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11508 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11509 page_flip_completed(intel_crtc);
11510 work = NULL;
11511 }
11512 if (work != NULL &&
11513 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11514 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11515 spin_unlock(&dev->event_lock);
11516 }
11517
11518 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11519 struct drm_framebuffer *fb,
11520 struct drm_pending_vblank_event *event,
11521 uint32_t page_flip_flags)
11522 {
11523 struct drm_device *dev = crtc->dev;
11524 struct drm_i915_private *dev_priv = dev->dev_private;
11525 struct drm_framebuffer *old_fb = crtc->primary->fb;
11526 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11528 struct drm_plane *primary = crtc->primary;
11529 enum pipe pipe = intel_crtc->pipe;
11530 struct intel_unpin_work *work;
11531 struct intel_engine_cs *ring;
11532 bool mmio_flip;
11533 int ret;
11534
11535 /*
11536 * drm_mode_page_flip_ioctl() should already catch this, but double
11537 * check to be safe. In the future we may enable pageflipping from
11538 * a disabled primary plane.
11539 */
11540 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11541 return -EBUSY;
11542
11543 /* Can't change pixel format via MI display flips. */
11544 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11545 return -EINVAL;
11546
11547 /*
11548 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11549 * Note that pitch changes could also affect these register.
11550 */
11551 if (INTEL_INFO(dev)->gen > 3 &&
11552 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11553 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11554 return -EINVAL;
11555
11556 if (i915_terminally_wedged(&dev_priv->gpu_error))
11557 goto out_hang;
11558
11559 work = kzalloc(sizeof(*work), GFP_KERNEL);
11560 if (work == NULL)
11561 return -ENOMEM;
11562
11563 work->event = event;
11564 work->crtc = crtc;
11565 work->old_fb = old_fb;
11566 INIT_WORK(&work->work, intel_unpin_work_fn);
11567
11568 ret = drm_crtc_vblank_get(crtc);
11569 if (ret)
11570 goto free_work;
11571
11572 /* We borrow the event spin lock for protecting unpin_work */
11573 spin_lock_irq(&dev->event_lock);
11574 if (intel_crtc->unpin_work) {
11575 /* Before declaring the flip queue wedged, check if
11576 * the hardware completed the operation behind our backs.
11577 */
11578 if (__intel_pageflip_stall_check(dev, crtc)) {
11579 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11580 page_flip_completed(intel_crtc);
11581 } else {
11582 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11583 spin_unlock_irq(&dev->event_lock);
11584
11585 drm_crtc_vblank_put(crtc);
11586 kfree(work);
11587 return -EBUSY;
11588 }
11589 }
11590 intel_crtc->unpin_work = work;
11591 spin_unlock_irq(&dev->event_lock);
11592
11593 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11594 flush_workqueue(dev_priv->wq);
11595
11596 /* Reference the objects for the scheduled work. */
11597 drm_framebuffer_reference(work->old_fb);
11598 drm_gem_object_reference(&obj->base);
11599
11600 crtc->primary->fb = fb;
11601 update_state_fb(crtc->primary);
11602
11603 work->pending_flip_obj = obj;
11604
11605 ret = i915_mutex_lock_interruptible(dev);
11606 if (ret)
11607 goto cleanup;
11608
11609 atomic_inc(&intel_crtc->unpin_work_count);
11610 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11611
11612 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11613 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11614
11615 if (IS_VALLEYVIEW(dev)) {
11616 ring = &dev_priv->ring[BCS];
11617 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11618 /* vlv: DISPLAY_FLIP fails to change tiling */
11619 ring = NULL;
11620 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11621 ring = &dev_priv->ring[BCS];
11622 } else if (INTEL_INFO(dev)->gen >= 7) {
11623 ring = i915_gem_request_get_ring(obj->last_write_req);
11624 if (ring == NULL || ring->id != RCS)
11625 ring = &dev_priv->ring[BCS];
11626 } else {
11627 ring = &dev_priv->ring[RCS];
11628 }
11629
11630 mmio_flip = use_mmio_flip(ring, obj);
11631
11632 /* When using CS flips, we want to emit semaphores between rings.
11633 * However, when using mmio flips we will create a task to do the
11634 * synchronisation, so all we want here is to pin the framebuffer
11635 * into the display plane and skip any waits.
11636 */
11637 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11638 crtc->primary->state,
11639 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11640 if (ret)
11641 goto cleanup_pending;
11642
11643 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11644 + intel_crtc->dspaddr_offset;
11645
11646 if (mmio_flip) {
11647 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11648 page_flip_flags);
11649 if (ret)
11650 goto cleanup_unpin;
11651
11652 i915_gem_request_assign(&work->flip_queued_req,
11653 obj->last_write_req);
11654 } else {
11655 if (obj->last_write_req) {
11656 ret = i915_gem_check_olr(obj->last_write_req);
11657 if (ret)
11658 goto cleanup_unpin;
11659 }
11660
11661 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11662 page_flip_flags);
11663 if (ret)
11664 goto cleanup_unpin;
11665
11666 i915_gem_request_assign(&work->flip_queued_req,
11667 intel_ring_get_request(ring));
11668 }
11669
11670 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11671 work->enable_stall_check = true;
11672
11673 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11674 INTEL_FRONTBUFFER_PRIMARY(pipe));
11675
11676 intel_fbc_disable(dev);
11677 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11678 mutex_unlock(&dev->struct_mutex);
11679
11680 trace_i915_flip_request(intel_crtc->plane, obj);
11681
11682 return 0;
11683
11684 cleanup_unpin:
11685 intel_unpin_fb_obj(fb, crtc->primary->state);
11686 cleanup_pending:
11687 atomic_dec(&intel_crtc->unpin_work_count);
11688 mutex_unlock(&dev->struct_mutex);
11689 cleanup:
11690 crtc->primary->fb = old_fb;
11691 update_state_fb(crtc->primary);
11692
11693 drm_gem_object_unreference_unlocked(&obj->base);
11694 drm_framebuffer_unreference(work->old_fb);
11695
11696 spin_lock_irq(&dev->event_lock);
11697 intel_crtc->unpin_work = NULL;
11698 spin_unlock_irq(&dev->event_lock);
11699
11700 drm_crtc_vblank_put(crtc);
11701 free_work:
11702 kfree(work);
11703
11704 if (ret == -EIO) {
11705 struct drm_atomic_state *state;
11706 struct drm_plane_state *plane_state;
11707
11708 out_hang:
11709 state = drm_atomic_state_alloc(dev);
11710 if (!state)
11711 return -ENOMEM;
11712 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11713
11714 retry:
11715 plane_state = drm_atomic_get_plane_state(state, primary);
11716 ret = PTR_ERR_OR_ZERO(plane_state);
11717 if (!ret) {
11718 drm_atomic_set_fb_for_plane(plane_state, fb);
11719
11720 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11721 if (!ret)
11722 ret = drm_atomic_commit(state);
11723 }
11724
11725 if (ret == -EDEADLK) {
11726 drm_modeset_backoff(state->acquire_ctx);
11727 drm_atomic_state_clear(state);
11728 goto retry;
11729 }
11730
11731 if (ret)
11732 drm_atomic_state_free(state);
11733
11734 if (ret == 0 && event) {
11735 spin_lock_irq(&dev->event_lock);
11736 drm_send_vblank_event(dev, pipe, event);
11737 spin_unlock_irq(&dev->event_lock);
11738 }
11739 }
11740 return ret;
11741 }
11742
11743
11744 /**
11745 * intel_wm_need_update - Check whether watermarks need updating
11746 * @plane: drm plane
11747 * @state: new plane state
11748 *
11749 * Check current plane state versus the new one to determine whether
11750 * watermarks need to be recalculated.
11751 *
11752 * Returns true or false.
11753 */
11754 static bool intel_wm_need_update(struct drm_plane *plane,
11755 struct drm_plane_state *state)
11756 {
11757 /* Update watermarks on tiling changes. */
11758 if (!plane->state->fb || !state->fb ||
11759 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11760 plane->state->rotation != state->rotation)
11761 return true;
11762
11763 if (plane->state->crtc_w != state->crtc_w)
11764 return true;
11765
11766 return false;
11767 }
11768
11769 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11770 struct drm_plane_state *plane_state)
11771 {
11772 struct drm_crtc *crtc = crtc_state->crtc;
11773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11774 struct drm_plane *plane = plane_state->plane;
11775 struct drm_device *dev = crtc->dev;
11776 struct drm_i915_private *dev_priv = dev->dev_private;
11777 struct intel_plane_state *old_plane_state =
11778 to_intel_plane_state(plane->state);
11779 int idx = intel_crtc->base.base.id, ret;
11780 int i = drm_plane_index(plane);
11781 bool mode_changed = needs_modeset(crtc_state);
11782 bool was_crtc_enabled = crtc->state->active;
11783 bool is_crtc_enabled = crtc_state->active;
11784
11785 bool turn_off, turn_on, visible, was_visible;
11786 struct drm_framebuffer *fb = plane_state->fb;
11787
11788 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11789 plane->type != DRM_PLANE_TYPE_CURSOR) {
11790 ret = skl_update_scaler_plane(
11791 to_intel_crtc_state(crtc_state),
11792 to_intel_plane_state(plane_state));
11793 if (ret)
11794 return ret;
11795 }
11796
11797 /*
11798 * Disabling a plane is always okay; we just need to update
11799 * fb tracking in a special way since cleanup_fb() won't
11800 * get called by the plane helpers.
11801 */
11802 if (old_plane_state->base.fb && !fb)
11803 intel_crtc->atomic.disabled_planes |= 1 << i;
11804
11805 /* don't run rest during modeset yet */
11806 if (!intel_crtc->active || mode_changed)
11807 return 0;
11808
11809 was_visible = old_plane_state->visible;
11810 visible = to_intel_plane_state(plane_state)->visible;
11811
11812 if (!was_crtc_enabled && WARN_ON(was_visible))
11813 was_visible = false;
11814
11815 if (!is_crtc_enabled && WARN_ON(visible))
11816 visible = false;
11817
11818 if (!was_visible && !visible)
11819 return 0;
11820
11821 turn_off = was_visible && (!visible || mode_changed);
11822 turn_on = visible && (!was_visible || mode_changed);
11823
11824 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11825 plane->base.id, fb ? fb->base.id : -1);
11826
11827 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11828 plane->base.id, was_visible, visible,
11829 turn_off, turn_on, mode_changed);
11830
11831 if (intel_wm_need_update(plane, plane_state))
11832 intel_crtc->atomic.update_wm = true;
11833
11834 switch (plane->type) {
11835 case DRM_PLANE_TYPE_PRIMARY:
11836 if (visible)
11837 intel_crtc->atomic.fb_bits |=
11838 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11839
11840 intel_crtc->atomic.wait_for_flips = true;
11841 intel_crtc->atomic.pre_disable_primary = turn_off;
11842 intel_crtc->atomic.post_enable_primary = turn_on;
11843
11844 if (turn_off)
11845 intel_crtc->atomic.disable_fbc = true;
11846
11847 /*
11848 * FBC does not work on some platforms for rotated
11849 * planes, so disable it when rotation is not 0 and
11850 * update it when rotation is set back to 0.
11851 *
11852 * FIXME: This is redundant with the fbc update done in
11853 * the primary plane enable function except that that
11854 * one is done too late. We eventually need to unify
11855 * this.
11856 */
11857
11858 if (visible &&
11859 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11860 dev_priv->fbc.crtc == intel_crtc &&
11861 plane_state->rotation != BIT(DRM_ROTATE_0))
11862 intel_crtc->atomic.disable_fbc = true;
11863
11864 /*
11865 * BDW signals flip done immediately if the plane
11866 * is disabled, even if the plane enable is already
11867 * armed to occur at the next vblank :(
11868 */
11869 if (turn_on && IS_BROADWELL(dev))
11870 intel_crtc->atomic.wait_vblank = true;
11871
11872 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11873 break;
11874 case DRM_PLANE_TYPE_CURSOR:
11875 if (visible)
11876 intel_crtc->atomic.fb_bits |=
11877 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
11878 break;
11879 case DRM_PLANE_TYPE_OVERLAY:
11880 /*
11881 * 'prepare' is never called when plane is being disabled, so
11882 * we need to handle frontbuffer tracking as a special case
11883 */
11884 if (visible)
11885 intel_crtc->atomic.fb_bits |=
11886 INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
11887
11888 if (turn_off && is_crtc_enabled) {
11889 intel_crtc->atomic.wait_vblank = true;
11890 intel_crtc->atomic.update_sprite_watermarks |=
11891 1 << i;
11892 }
11893 break;
11894 }
11895 return 0;
11896 }
11897
11898 static bool encoders_cloneable(const struct intel_encoder *a,
11899 const struct intel_encoder *b)
11900 {
11901 /* masks could be asymmetric, so check both ways */
11902 return a == b || (a->cloneable & (1 << b->type) &&
11903 b->cloneable & (1 << a->type));
11904 }
11905
11906 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11907 struct intel_crtc *crtc,
11908 struct intel_encoder *encoder)
11909 {
11910 struct intel_encoder *source_encoder;
11911 struct drm_connector *connector;
11912 struct drm_connector_state *connector_state;
11913 int i;
11914
11915 for_each_connector_in_state(state, connector, connector_state, i) {
11916 if (connector_state->crtc != &crtc->base)
11917 continue;
11918
11919 source_encoder =
11920 to_intel_encoder(connector_state->best_encoder);
11921 if (!encoders_cloneable(encoder, source_encoder))
11922 return false;
11923 }
11924
11925 return true;
11926 }
11927
11928 static bool check_encoder_cloning(struct drm_atomic_state *state,
11929 struct intel_crtc *crtc)
11930 {
11931 struct intel_encoder *encoder;
11932 struct drm_connector *connector;
11933 struct drm_connector_state *connector_state;
11934 int i;
11935
11936 for_each_connector_in_state(state, connector, connector_state, i) {
11937 if (connector_state->crtc != &crtc->base)
11938 continue;
11939
11940 encoder = to_intel_encoder(connector_state->best_encoder);
11941 if (!check_single_encoder_cloning(state, crtc, encoder))
11942 return false;
11943 }
11944
11945 return true;
11946 }
11947
11948 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11949 struct drm_crtc_state *crtc_state)
11950 {
11951 struct drm_device *dev = crtc->dev;
11952 struct drm_i915_private *dev_priv = dev->dev_private;
11953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11954 struct intel_crtc_state *pipe_config =
11955 to_intel_crtc_state(crtc_state);
11956 struct drm_atomic_state *state = crtc_state->state;
11957 int ret, idx = crtc->base.id;
11958 bool mode_changed = needs_modeset(crtc_state);
11959
11960 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11961 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11962 return -EINVAL;
11963 }
11964
11965 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11966 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11967 idx, crtc->state->active, intel_crtc->active);
11968
11969 if (mode_changed && crtc_state->enable &&
11970 dev_priv->display.crtc_compute_clock &&
11971 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11972 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11973 pipe_config);
11974 if (ret)
11975 return ret;
11976 }
11977
11978 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11979 }
11980
11981 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11982 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11983 .load_lut = intel_crtc_load_lut,
11984 .atomic_begin = intel_begin_crtc_commit,
11985 .atomic_flush = intel_finish_crtc_commit,
11986 .atomic_check = intel_crtc_atomic_check,
11987 };
11988
11989 /**
11990 * intel_modeset_update_staged_output_state
11991 *
11992 * Updates the staged output configuration state, e.g. after we've read out the
11993 * current hw state.
11994 */
11995 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11996 {
11997 struct intel_crtc *crtc;
11998 struct intel_encoder *encoder;
11999 struct intel_connector *connector;
12000
12001 for_each_intel_connector(dev, connector) {
12002 connector->new_encoder =
12003 to_intel_encoder(connector->base.encoder);
12004 }
12005
12006 for_each_intel_encoder(dev, encoder) {
12007 encoder->new_crtc =
12008 to_intel_crtc(encoder->base.crtc);
12009 }
12010
12011 for_each_intel_crtc(dev, crtc) {
12012 crtc->new_enabled = crtc->base.state->enable;
12013 }
12014 }
12015
12016 /* Transitional helper to copy current connector/encoder state to
12017 * connector->state. This is needed so that code that is partially
12018 * converted to atomic does the right thing.
12019 */
12020 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12021 {
12022 struct intel_connector *connector;
12023
12024 for_each_intel_connector(dev, connector) {
12025 if (connector->base.encoder) {
12026 connector->base.state->best_encoder =
12027 connector->base.encoder;
12028 connector->base.state->crtc =
12029 connector->base.encoder->crtc;
12030 } else {
12031 connector->base.state->best_encoder = NULL;
12032 connector->base.state->crtc = NULL;
12033 }
12034 }
12035 }
12036
12037 static void
12038 connected_sink_compute_bpp(struct intel_connector *connector,
12039 struct intel_crtc_state *pipe_config)
12040 {
12041 int bpp = pipe_config->pipe_bpp;
12042
12043 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12044 connector->base.base.id,
12045 connector->base.name);
12046
12047 /* Don't use an invalid EDID bpc value */
12048 if (connector->base.display_info.bpc &&
12049 connector->base.display_info.bpc * 3 < bpp) {
12050 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12051 bpp, connector->base.display_info.bpc*3);
12052 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12053 }
12054
12055 /* Clamp bpp to 8 on screens without EDID 1.4 */
12056 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12057 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12058 bpp);
12059 pipe_config->pipe_bpp = 24;
12060 }
12061 }
12062
12063 static int
12064 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12065 struct intel_crtc_state *pipe_config)
12066 {
12067 struct drm_device *dev = crtc->base.dev;
12068 struct drm_atomic_state *state;
12069 struct drm_connector *connector;
12070 struct drm_connector_state *connector_state;
12071 int bpp, i;
12072
12073 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12074 bpp = 10*3;
12075 else if (INTEL_INFO(dev)->gen >= 5)
12076 bpp = 12*3;
12077 else
12078 bpp = 8*3;
12079
12080
12081 pipe_config->pipe_bpp = bpp;
12082
12083 state = pipe_config->base.state;
12084
12085 /* Clamp display bpp to EDID value */
12086 for_each_connector_in_state(state, connector, connector_state, i) {
12087 if (connector_state->crtc != &crtc->base)
12088 continue;
12089
12090 connected_sink_compute_bpp(to_intel_connector(connector),
12091 pipe_config);
12092 }
12093
12094 return bpp;
12095 }
12096
12097 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12098 {
12099 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12100 "type: 0x%x flags: 0x%x\n",
12101 mode->crtc_clock,
12102 mode->crtc_hdisplay, mode->crtc_hsync_start,
12103 mode->crtc_hsync_end, mode->crtc_htotal,
12104 mode->crtc_vdisplay, mode->crtc_vsync_start,
12105 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12106 }
12107
12108 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12109 struct intel_crtc_state *pipe_config,
12110 const char *context)
12111 {
12112 struct drm_device *dev = crtc->base.dev;
12113 struct drm_plane *plane;
12114 struct intel_plane *intel_plane;
12115 struct intel_plane_state *state;
12116 struct drm_framebuffer *fb;
12117
12118 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12119 context, pipe_config, pipe_name(crtc->pipe));
12120
12121 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12122 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12123 pipe_config->pipe_bpp, pipe_config->dither);
12124 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12125 pipe_config->has_pch_encoder,
12126 pipe_config->fdi_lanes,
12127 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12128 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12129 pipe_config->fdi_m_n.tu);
12130 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12131 pipe_config->has_dp_encoder,
12132 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12133 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12134 pipe_config->dp_m_n.tu);
12135
12136 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12137 pipe_config->has_dp_encoder,
12138 pipe_config->dp_m2_n2.gmch_m,
12139 pipe_config->dp_m2_n2.gmch_n,
12140 pipe_config->dp_m2_n2.link_m,
12141 pipe_config->dp_m2_n2.link_n,
12142 pipe_config->dp_m2_n2.tu);
12143
12144 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12145 pipe_config->has_audio,
12146 pipe_config->has_infoframe);
12147
12148 DRM_DEBUG_KMS("requested mode:\n");
12149 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12150 DRM_DEBUG_KMS("adjusted mode:\n");
12151 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12152 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12153 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12154 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12155 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12156 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12157 crtc->num_scalers,
12158 pipe_config->scaler_state.scaler_users,
12159 pipe_config->scaler_state.scaler_id);
12160 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12161 pipe_config->gmch_pfit.control,
12162 pipe_config->gmch_pfit.pgm_ratios,
12163 pipe_config->gmch_pfit.lvds_border_bits);
12164 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12165 pipe_config->pch_pfit.pos,
12166 pipe_config->pch_pfit.size,
12167 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12168 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12169 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12170
12171 if (IS_BROXTON(dev)) {
12172 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
12173 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12174 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
12175 pipe_config->ddi_pll_sel,
12176 pipe_config->dpll_hw_state.ebb0,
12177 pipe_config->dpll_hw_state.pll0,
12178 pipe_config->dpll_hw_state.pll1,
12179 pipe_config->dpll_hw_state.pll2,
12180 pipe_config->dpll_hw_state.pll3,
12181 pipe_config->dpll_hw_state.pll6,
12182 pipe_config->dpll_hw_state.pll8,
12183 pipe_config->dpll_hw_state.pcsdw12);
12184 } else if (IS_SKYLAKE(dev)) {
12185 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12186 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12187 pipe_config->ddi_pll_sel,
12188 pipe_config->dpll_hw_state.ctrl1,
12189 pipe_config->dpll_hw_state.cfgcr1,
12190 pipe_config->dpll_hw_state.cfgcr2);
12191 } else if (HAS_DDI(dev)) {
12192 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12193 pipe_config->ddi_pll_sel,
12194 pipe_config->dpll_hw_state.wrpll);
12195 } else {
12196 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12197 "fp0: 0x%x, fp1: 0x%x\n",
12198 pipe_config->dpll_hw_state.dpll,
12199 pipe_config->dpll_hw_state.dpll_md,
12200 pipe_config->dpll_hw_state.fp0,
12201 pipe_config->dpll_hw_state.fp1);
12202 }
12203
12204 DRM_DEBUG_KMS("planes on this crtc\n");
12205 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12206 intel_plane = to_intel_plane(plane);
12207 if (intel_plane->pipe != crtc->pipe)
12208 continue;
12209
12210 state = to_intel_plane_state(plane->state);
12211 fb = state->base.fb;
12212 if (!fb) {
12213 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12214 "disabled, scaler_id = %d\n",
12215 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12216 plane->base.id, intel_plane->pipe,
12217 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12218 drm_plane_index(plane), state->scaler_id);
12219 continue;
12220 }
12221
12222 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12223 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12224 plane->base.id, intel_plane->pipe,
12225 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12226 drm_plane_index(plane));
12227 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12228 fb->base.id, fb->width, fb->height, fb->pixel_format);
12229 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12230 state->scaler_id,
12231 state->src.x1 >> 16, state->src.y1 >> 16,
12232 drm_rect_width(&state->src) >> 16,
12233 drm_rect_height(&state->src) >> 16,
12234 state->dst.x1, state->dst.y1,
12235 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12236 }
12237 }
12238
12239 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12240 {
12241 struct drm_device *dev = state->dev;
12242 struct intel_encoder *encoder;
12243 struct drm_connector *connector;
12244 struct drm_connector_state *connector_state;
12245 unsigned int used_ports = 0;
12246 int i;
12247
12248 /*
12249 * Walk the connector list instead of the encoder
12250 * list to detect the problem on ddi platforms
12251 * where there's just one encoder per digital port.
12252 */
12253 for_each_connector_in_state(state, connector, connector_state, i) {
12254 if (!connector_state->best_encoder)
12255 continue;
12256
12257 encoder = to_intel_encoder(connector_state->best_encoder);
12258
12259 WARN_ON(!connector_state->crtc);
12260
12261 switch (encoder->type) {
12262 unsigned int port_mask;
12263 case INTEL_OUTPUT_UNKNOWN:
12264 if (WARN_ON(!HAS_DDI(dev)))
12265 break;
12266 case INTEL_OUTPUT_DISPLAYPORT:
12267 case INTEL_OUTPUT_HDMI:
12268 case INTEL_OUTPUT_EDP:
12269 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12270
12271 /* the same port mustn't appear more than once */
12272 if (used_ports & port_mask)
12273 return false;
12274
12275 used_ports |= port_mask;
12276 default:
12277 break;
12278 }
12279 }
12280
12281 return true;
12282 }
12283
12284 static void
12285 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12286 {
12287 struct drm_crtc_state tmp_state;
12288 struct intel_crtc_scaler_state scaler_state;
12289 struct intel_dpll_hw_state dpll_hw_state;
12290 enum intel_dpll_id shared_dpll;
12291 uint32_t ddi_pll_sel;
12292
12293 /* FIXME: before the switch to atomic started, a new pipe_config was
12294 * kzalloc'd. Code that depends on any field being zero should be
12295 * fixed, so that the crtc_state can be safely duplicated. For now,
12296 * only fields that are know to not cause problems are preserved. */
12297
12298 tmp_state = crtc_state->base;
12299 scaler_state = crtc_state->scaler_state;
12300 shared_dpll = crtc_state->shared_dpll;
12301 dpll_hw_state = crtc_state->dpll_hw_state;
12302 ddi_pll_sel = crtc_state->ddi_pll_sel;
12303
12304 memset(crtc_state, 0, sizeof *crtc_state);
12305
12306 crtc_state->base = tmp_state;
12307 crtc_state->scaler_state = scaler_state;
12308 crtc_state->shared_dpll = shared_dpll;
12309 crtc_state->dpll_hw_state = dpll_hw_state;
12310 crtc_state->ddi_pll_sel = ddi_pll_sel;
12311 }
12312
12313 static int
12314 intel_modeset_pipe_config(struct drm_crtc *crtc,
12315 struct intel_crtc_state *pipe_config)
12316 {
12317 struct drm_atomic_state *state = pipe_config->base.state;
12318 struct intel_encoder *encoder;
12319 struct drm_connector *connector;
12320 struct drm_connector_state *connector_state;
12321 int base_bpp, ret = -EINVAL;
12322 int i;
12323 bool retry = true;
12324
12325 clear_intel_crtc_state(pipe_config);
12326
12327 pipe_config->cpu_transcoder =
12328 (enum transcoder) to_intel_crtc(crtc)->pipe;
12329
12330 /*
12331 * Sanitize sync polarity flags based on requested ones. If neither
12332 * positive or negative polarity is requested, treat this as meaning
12333 * negative polarity.
12334 */
12335 if (!(pipe_config->base.adjusted_mode.flags &
12336 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12337 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12338
12339 if (!(pipe_config->base.adjusted_mode.flags &
12340 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12341 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12342
12343 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12344 * plane pixel format and any sink constraints into account. Returns the
12345 * source plane bpp so that dithering can be selected on mismatches
12346 * after encoders and crtc also have had their say. */
12347 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12348 pipe_config);
12349 if (base_bpp < 0)
12350 goto fail;
12351
12352 /*
12353 * Determine the real pipe dimensions. Note that stereo modes can
12354 * increase the actual pipe size due to the frame doubling and
12355 * insertion of additional space for blanks between the frame. This
12356 * is stored in the crtc timings. We use the requested mode to do this
12357 * computation to clearly distinguish it from the adjusted mode, which
12358 * can be changed by the connectors in the below retry loop.
12359 */
12360 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12361 &pipe_config->pipe_src_w,
12362 &pipe_config->pipe_src_h);
12363
12364 encoder_retry:
12365 /* Ensure the port clock defaults are reset when retrying. */
12366 pipe_config->port_clock = 0;
12367 pipe_config->pixel_multiplier = 1;
12368
12369 /* Fill in default crtc timings, allow encoders to overwrite them. */
12370 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12371 CRTC_STEREO_DOUBLE);
12372
12373 /* Pass our mode to the connectors and the CRTC to give them a chance to
12374 * adjust it according to limitations or connector properties, and also
12375 * a chance to reject the mode entirely.
12376 */
12377 for_each_connector_in_state(state, connector, connector_state, i) {
12378 if (connector_state->crtc != crtc)
12379 continue;
12380
12381 encoder = to_intel_encoder(connector_state->best_encoder);
12382
12383 if (!(encoder->compute_config(encoder, pipe_config))) {
12384 DRM_DEBUG_KMS("Encoder config failure\n");
12385 goto fail;
12386 }
12387 }
12388
12389 /* Set default port clock if not overwritten by the encoder. Needs to be
12390 * done afterwards in case the encoder adjusts the mode. */
12391 if (!pipe_config->port_clock)
12392 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12393 * pipe_config->pixel_multiplier;
12394
12395 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12396 if (ret < 0) {
12397 DRM_DEBUG_KMS("CRTC fixup failed\n");
12398 goto fail;
12399 }
12400
12401 if (ret == RETRY) {
12402 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12403 ret = -EINVAL;
12404 goto fail;
12405 }
12406
12407 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12408 retry = false;
12409 goto encoder_retry;
12410 }
12411
12412 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12413 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12414 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12415
12416 /* Check if we need to force a modeset */
12417 if (pipe_config->has_audio !=
12418 to_intel_crtc_state(crtc->state)->has_audio) {
12419 pipe_config->base.mode_changed = true;
12420 ret = drm_atomic_add_affected_planes(state, crtc);
12421 }
12422
12423 /*
12424 * Note we have an issue here with infoframes: current code
12425 * only updates them on the full mode set path per hw
12426 * requirements. So here we should be checking for any
12427 * required changes and forcing a mode set.
12428 */
12429 fail:
12430 return ret;
12431 }
12432
12433 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12434 {
12435 struct drm_encoder *encoder;
12436 struct drm_device *dev = crtc->dev;
12437
12438 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12439 if (encoder->crtc == crtc)
12440 return true;
12441
12442 return false;
12443 }
12444
12445 static void
12446 intel_modeset_update_state(struct drm_atomic_state *state)
12447 {
12448 struct drm_device *dev = state->dev;
12449 struct intel_encoder *intel_encoder;
12450 struct drm_crtc *crtc;
12451 struct drm_crtc_state *crtc_state;
12452 struct drm_connector *connector;
12453
12454 intel_shared_dpll_commit(state);
12455
12456 for_each_intel_encoder(dev, intel_encoder) {
12457 if (!intel_encoder->base.crtc)
12458 continue;
12459
12460 crtc = intel_encoder->base.crtc;
12461 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12462 if (!crtc_state || !needs_modeset(crtc->state))
12463 continue;
12464
12465 intel_encoder->connectors_active = false;
12466 }
12467
12468 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12469 intel_modeset_update_staged_output_state(state->dev);
12470
12471 /* Double check state. */
12472 for_each_crtc(dev, crtc) {
12473 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12474
12475 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12476
12477 /* Update hwmode for vblank functions */
12478 if (crtc->state->active)
12479 crtc->hwmode = crtc->state->adjusted_mode;
12480 else
12481 crtc->hwmode.crtc_clock = 0;
12482 }
12483
12484 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12485 if (!connector->encoder || !connector->encoder->crtc)
12486 continue;
12487
12488 crtc = connector->encoder->crtc;
12489 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12490 if (!crtc_state || !needs_modeset(crtc->state))
12491 continue;
12492
12493 if (crtc->state->active) {
12494 struct drm_property *dpms_property =
12495 dev->mode_config.dpms_property;
12496
12497 connector->dpms = DRM_MODE_DPMS_ON;
12498 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12499
12500 intel_encoder = to_intel_encoder(connector->encoder);
12501 intel_encoder->connectors_active = true;
12502 } else
12503 connector->dpms = DRM_MODE_DPMS_OFF;
12504 }
12505 }
12506
12507 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12508 {
12509 int diff;
12510
12511 if (clock1 == clock2)
12512 return true;
12513
12514 if (!clock1 || !clock2)
12515 return false;
12516
12517 diff = abs(clock1 - clock2);
12518
12519 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12520 return true;
12521
12522 return false;
12523 }
12524
12525 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12526 list_for_each_entry((intel_crtc), \
12527 &(dev)->mode_config.crtc_list, \
12528 base.head) \
12529 if (mask & (1 <<(intel_crtc)->pipe))
12530
12531 static bool
12532 intel_pipe_config_compare(struct drm_device *dev,
12533 struct intel_crtc_state *current_config,
12534 struct intel_crtc_state *pipe_config)
12535 {
12536 #define PIPE_CONF_CHECK_X(name) \
12537 if (current_config->name != pipe_config->name) { \
12538 DRM_ERROR("mismatch in " #name " " \
12539 "(expected 0x%08x, found 0x%08x)\n", \
12540 current_config->name, \
12541 pipe_config->name); \
12542 return false; \
12543 }
12544
12545 #define PIPE_CONF_CHECK_I(name) \
12546 if (current_config->name != pipe_config->name) { \
12547 DRM_ERROR("mismatch in " #name " " \
12548 "(expected %i, found %i)\n", \
12549 current_config->name, \
12550 pipe_config->name); \
12551 return false; \
12552 }
12553
12554 /* This is required for BDW+ where there is only one set of registers for
12555 * switching between high and low RR.
12556 * This macro can be used whenever a comparison has to be made between one
12557 * hw state and multiple sw state variables.
12558 */
12559 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12560 if ((current_config->name != pipe_config->name) && \
12561 (current_config->alt_name != pipe_config->name)) { \
12562 DRM_ERROR("mismatch in " #name " " \
12563 "(expected %i or %i, found %i)\n", \
12564 current_config->name, \
12565 current_config->alt_name, \
12566 pipe_config->name); \
12567 return false; \
12568 }
12569
12570 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12571 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12572 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12573 "(expected %i, found %i)\n", \
12574 current_config->name & (mask), \
12575 pipe_config->name & (mask)); \
12576 return false; \
12577 }
12578
12579 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12580 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12581 DRM_ERROR("mismatch in " #name " " \
12582 "(expected %i, found %i)\n", \
12583 current_config->name, \
12584 pipe_config->name); \
12585 return false; \
12586 }
12587
12588 #define PIPE_CONF_QUIRK(quirk) \
12589 ((current_config->quirks | pipe_config->quirks) & (quirk))
12590
12591 PIPE_CONF_CHECK_I(cpu_transcoder);
12592
12593 PIPE_CONF_CHECK_I(has_pch_encoder);
12594 PIPE_CONF_CHECK_I(fdi_lanes);
12595 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12596 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12597 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12598 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12599 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12600
12601 PIPE_CONF_CHECK_I(has_dp_encoder);
12602
12603 if (INTEL_INFO(dev)->gen < 8) {
12604 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12605 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12606 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12607 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12608 PIPE_CONF_CHECK_I(dp_m_n.tu);
12609
12610 if (current_config->has_drrs) {
12611 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12612 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12613 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12614 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12615 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12616 }
12617 } else {
12618 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12619 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12620 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12621 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12622 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12623 }
12624
12625 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12626 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12627 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12628 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12629 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12630 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12631
12632 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12633 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12634 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12635 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12636 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12637 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12638
12639 PIPE_CONF_CHECK_I(pixel_multiplier);
12640 PIPE_CONF_CHECK_I(has_hdmi_sink);
12641 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12642 IS_VALLEYVIEW(dev))
12643 PIPE_CONF_CHECK_I(limited_color_range);
12644 PIPE_CONF_CHECK_I(has_infoframe);
12645
12646 PIPE_CONF_CHECK_I(has_audio);
12647
12648 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12649 DRM_MODE_FLAG_INTERLACE);
12650
12651 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12652 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12653 DRM_MODE_FLAG_PHSYNC);
12654 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12655 DRM_MODE_FLAG_NHSYNC);
12656 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12657 DRM_MODE_FLAG_PVSYNC);
12658 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12659 DRM_MODE_FLAG_NVSYNC);
12660 }
12661
12662 PIPE_CONF_CHECK_I(pipe_src_w);
12663 PIPE_CONF_CHECK_I(pipe_src_h);
12664
12665 /*
12666 * FIXME: BIOS likes to set up a cloned config with lvds+external
12667 * screen. Since we don't yet re-compute the pipe config when moving
12668 * just the lvds port away to another pipe the sw tracking won't match.
12669 *
12670 * Proper atomic modesets with recomputed global state will fix this.
12671 * Until then just don't check gmch state for inherited modes.
12672 */
12673 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12674 PIPE_CONF_CHECK_I(gmch_pfit.control);
12675 /* pfit ratios are autocomputed by the hw on gen4+ */
12676 if (INTEL_INFO(dev)->gen < 4)
12677 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12678 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12679 }
12680
12681 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12682 if (current_config->pch_pfit.enabled) {
12683 PIPE_CONF_CHECK_I(pch_pfit.pos);
12684 PIPE_CONF_CHECK_I(pch_pfit.size);
12685 }
12686
12687 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12688
12689 /* BDW+ don't expose a synchronous way to read the state */
12690 if (IS_HASWELL(dev))
12691 PIPE_CONF_CHECK_I(ips_enabled);
12692
12693 PIPE_CONF_CHECK_I(double_wide);
12694
12695 PIPE_CONF_CHECK_X(ddi_pll_sel);
12696
12697 PIPE_CONF_CHECK_I(shared_dpll);
12698 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12699 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12700 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12701 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12702 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12703 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12704 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12705 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12706
12707 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12708 PIPE_CONF_CHECK_I(pipe_bpp);
12709
12710 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12711 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12712
12713 #undef PIPE_CONF_CHECK_X
12714 #undef PIPE_CONF_CHECK_I
12715 #undef PIPE_CONF_CHECK_I_ALT
12716 #undef PIPE_CONF_CHECK_FLAGS
12717 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12718 #undef PIPE_CONF_QUIRK
12719
12720 return true;
12721 }
12722
12723 static void check_wm_state(struct drm_device *dev)
12724 {
12725 struct drm_i915_private *dev_priv = dev->dev_private;
12726 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12727 struct intel_crtc *intel_crtc;
12728 int plane;
12729
12730 if (INTEL_INFO(dev)->gen < 9)
12731 return;
12732
12733 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12734 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12735
12736 for_each_intel_crtc(dev, intel_crtc) {
12737 struct skl_ddb_entry *hw_entry, *sw_entry;
12738 const enum pipe pipe = intel_crtc->pipe;
12739
12740 if (!intel_crtc->active)
12741 continue;
12742
12743 /* planes */
12744 for_each_plane(dev_priv, pipe, plane) {
12745 hw_entry = &hw_ddb.plane[pipe][plane];
12746 sw_entry = &sw_ddb->plane[pipe][plane];
12747
12748 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12749 continue;
12750
12751 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12752 "(expected (%u,%u), found (%u,%u))\n",
12753 pipe_name(pipe), plane + 1,
12754 sw_entry->start, sw_entry->end,
12755 hw_entry->start, hw_entry->end);
12756 }
12757
12758 /* cursor */
12759 hw_entry = &hw_ddb.cursor[pipe];
12760 sw_entry = &sw_ddb->cursor[pipe];
12761
12762 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12763 continue;
12764
12765 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12766 "(expected (%u,%u), found (%u,%u))\n",
12767 pipe_name(pipe),
12768 sw_entry->start, sw_entry->end,
12769 hw_entry->start, hw_entry->end);
12770 }
12771 }
12772
12773 static void
12774 check_connector_state(struct drm_device *dev)
12775 {
12776 struct intel_connector *connector;
12777
12778 for_each_intel_connector(dev, connector) {
12779 /* This also checks the encoder/connector hw state with the
12780 * ->get_hw_state callbacks. */
12781 intel_connector_check_state(connector);
12782
12783 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12784 "connector's staged encoder doesn't match current encoder\n");
12785 }
12786 }
12787
12788 static void
12789 check_encoder_state(struct drm_device *dev)
12790 {
12791 struct intel_encoder *encoder;
12792 struct intel_connector *connector;
12793
12794 for_each_intel_encoder(dev, encoder) {
12795 bool enabled = false;
12796 bool active = false;
12797 enum pipe pipe, tracked_pipe;
12798
12799 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12800 encoder->base.base.id,
12801 encoder->base.name);
12802
12803 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12804 "encoder's stage crtc doesn't match current crtc\n");
12805 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12806 "encoder's active_connectors set, but no crtc\n");
12807
12808 for_each_intel_connector(dev, connector) {
12809 if (connector->base.encoder != &encoder->base)
12810 continue;
12811 enabled = true;
12812 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12813 active = true;
12814 }
12815 /*
12816 * for MST connectors if we unplug the connector is gone
12817 * away but the encoder is still connected to a crtc
12818 * until a modeset happens in response to the hotplug.
12819 */
12820 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12821 continue;
12822
12823 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12824 "encoder's enabled state mismatch "
12825 "(expected %i, found %i)\n",
12826 !!encoder->base.crtc, enabled);
12827 I915_STATE_WARN(active && !encoder->base.crtc,
12828 "active encoder with no crtc\n");
12829
12830 I915_STATE_WARN(encoder->connectors_active != active,
12831 "encoder's computed active state doesn't match tracked active state "
12832 "(expected %i, found %i)\n", active, encoder->connectors_active);
12833
12834 active = encoder->get_hw_state(encoder, &pipe);
12835 I915_STATE_WARN(active != encoder->connectors_active,
12836 "encoder's hw state doesn't match sw tracking "
12837 "(expected %i, found %i)\n",
12838 encoder->connectors_active, active);
12839
12840 if (!encoder->base.crtc)
12841 continue;
12842
12843 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12844 I915_STATE_WARN(active && pipe != tracked_pipe,
12845 "active encoder's pipe doesn't match"
12846 "(expected %i, found %i)\n",
12847 tracked_pipe, pipe);
12848
12849 }
12850 }
12851
12852 static void
12853 check_crtc_state(struct drm_device *dev)
12854 {
12855 struct drm_i915_private *dev_priv = dev->dev_private;
12856 struct intel_crtc *crtc;
12857 struct intel_encoder *encoder;
12858 struct intel_crtc_state pipe_config;
12859
12860 for_each_intel_crtc(dev, crtc) {
12861 bool enabled = false;
12862 bool active = false;
12863
12864 memset(&pipe_config, 0, sizeof(pipe_config));
12865
12866 DRM_DEBUG_KMS("[CRTC:%d]\n",
12867 crtc->base.base.id);
12868
12869 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12870 "active crtc, but not enabled in sw tracking\n");
12871
12872 for_each_intel_encoder(dev, encoder) {
12873 if (encoder->base.crtc != &crtc->base)
12874 continue;
12875 enabled = true;
12876 if (encoder->connectors_active)
12877 active = true;
12878 }
12879
12880 I915_STATE_WARN(active != crtc->active,
12881 "crtc's computed active state doesn't match tracked active state "
12882 "(expected %i, found %i)\n", active, crtc->active);
12883 I915_STATE_WARN(enabled != crtc->base.state->enable,
12884 "crtc's computed enabled state doesn't match tracked enabled state "
12885 "(expected %i, found %i)\n", enabled,
12886 crtc->base.state->enable);
12887
12888 active = dev_priv->display.get_pipe_config(crtc,
12889 &pipe_config);
12890
12891 /* hw state is inconsistent with the pipe quirk */
12892 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12893 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12894 active = crtc->active;
12895
12896 for_each_intel_encoder(dev, encoder) {
12897 enum pipe pipe;
12898 if (encoder->base.crtc != &crtc->base)
12899 continue;
12900 if (encoder->get_hw_state(encoder, &pipe))
12901 encoder->get_config(encoder, &pipe_config);
12902 }
12903
12904 I915_STATE_WARN(crtc->active != active,
12905 "crtc active state doesn't match with hw state "
12906 "(expected %i, found %i)\n", crtc->active, active);
12907
12908 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12909 "transitional active state does not match atomic hw state "
12910 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12911
12912 if (active &&
12913 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12914 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12915 intel_dump_pipe_config(crtc, &pipe_config,
12916 "[hw state]");
12917 intel_dump_pipe_config(crtc, crtc->config,
12918 "[sw state]");
12919 }
12920 }
12921 }
12922
12923 static void
12924 check_shared_dpll_state(struct drm_device *dev)
12925 {
12926 struct drm_i915_private *dev_priv = dev->dev_private;
12927 struct intel_crtc *crtc;
12928 struct intel_dpll_hw_state dpll_hw_state;
12929 int i;
12930
12931 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12932 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12933 int enabled_crtcs = 0, active_crtcs = 0;
12934 bool active;
12935
12936 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12937
12938 DRM_DEBUG_KMS("%s\n", pll->name);
12939
12940 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12941
12942 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12943 "more active pll users than references: %i vs %i\n",
12944 pll->active, hweight32(pll->config.crtc_mask));
12945 I915_STATE_WARN(pll->active && !pll->on,
12946 "pll in active use but not on in sw tracking\n");
12947 I915_STATE_WARN(pll->on && !pll->active,
12948 "pll in on but not on in use in sw tracking\n");
12949 I915_STATE_WARN(pll->on != active,
12950 "pll on state mismatch (expected %i, found %i)\n",
12951 pll->on, active);
12952
12953 for_each_intel_crtc(dev, crtc) {
12954 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12955 enabled_crtcs++;
12956 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12957 active_crtcs++;
12958 }
12959 I915_STATE_WARN(pll->active != active_crtcs,
12960 "pll active crtcs mismatch (expected %i, found %i)\n",
12961 pll->active, active_crtcs);
12962 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12963 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12964 hweight32(pll->config.crtc_mask), enabled_crtcs);
12965
12966 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12967 sizeof(dpll_hw_state)),
12968 "pll hw state mismatch\n");
12969 }
12970 }
12971
12972 void
12973 intel_modeset_check_state(struct drm_device *dev)
12974 {
12975 check_wm_state(dev);
12976 check_connector_state(dev);
12977 check_encoder_state(dev);
12978 check_crtc_state(dev);
12979 check_shared_dpll_state(dev);
12980 }
12981
12982 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12983 int dotclock)
12984 {
12985 /*
12986 * FDI already provided one idea for the dotclock.
12987 * Yell if the encoder disagrees.
12988 */
12989 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12990 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12991 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12992 }
12993
12994 static void update_scanline_offset(struct intel_crtc *crtc)
12995 {
12996 struct drm_device *dev = crtc->base.dev;
12997
12998 /*
12999 * The scanline counter increments at the leading edge of hsync.
13000 *
13001 * On most platforms it starts counting from vtotal-1 on the
13002 * first active line. That means the scanline counter value is
13003 * always one less than what we would expect. Ie. just after
13004 * start of vblank, which also occurs at start of hsync (on the
13005 * last active line), the scanline counter will read vblank_start-1.
13006 *
13007 * On gen2 the scanline counter starts counting from 1 instead
13008 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13009 * to keep the value positive), instead of adding one.
13010 *
13011 * On HSW+ the behaviour of the scanline counter depends on the output
13012 * type. For DP ports it behaves like most other platforms, but on HDMI
13013 * there's an extra 1 line difference. So we need to add two instead of
13014 * one to the value.
13015 */
13016 if (IS_GEN2(dev)) {
13017 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
13018 int vtotal;
13019
13020 vtotal = mode->crtc_vtotal;
13021 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
13022 vtotal /= 2;
13023
13024 crtc->scanline_offset = vtotal - 1;
13025 } else if (HAS_DDI(dev) &&
13026 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13027 crtc->scanline_offset = 2;
13028 } else
13029 crtc->scanline_offset = 1;
13030 }
13031
13032 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13033 {
13034 struct drm_device *dev = state->dev;
13035 struct drm_i915_private *dev_priv = to_i915(dev);
13036 struct intel_shared_dpll_config *shared_dpll = NULL;
13037 struct intel_crtc *intel_crtc;
13038 struct intel_crtc_state *intel_crtc_state;
13039 struct drm_crtc *crtc;
13040 struct drm_crtc_state *crtc_state;
13041 int i;
13042
13043 if (!dev_priv->display.crtc_compute_clock)
13044 return;
13045
13046 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13047 int dpll;
13048
13049 intel_crtc = to_intel_crtc(crtc);
13050 intel_crtc_state = to_intel_crtc_state(crtc_state);
13051 dpll = intel_crtc_state->shared_dpll;
13052
13053 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13054 continue;
13055
13056 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13057
13058 if (!shared_dpll)
13059 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13060
13061 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13062 }
13063 }
13064
13065 /*
13066 * This implements the workaround described in the "notes" section of the mode
13067 * set sequence documentation. When going from no pipes or single pipe to
13068 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13069 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13070 */
13071 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13072 {
13073 struct drm_crtc_state *crtc_state;
13074 struct intel_crtc *intel_crtc;
13075 struct drm_crtc *crtc;
13076 struct intel_crtc_state *first_crtc_state = NULL;
13077 struct intel_crtc_state *other_crtc_state = NULL;
13078 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13079 int i;
13080
13081 /* look at all crtc's that are going to be enabled in during modeset */
13082 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13083 intel_crtc = to_intel_crtc(crtc);
13084
13085 if (!crtc_state->active || !needs_modeset(crtc_state))
13086 continue;
13087
13088 if (first_crtc_state) {
13089 other_crtc_state = to_intel_crtc_state(crtc_state);
13090 break;
13091 } else {
13092 first_crtc_state = to_intel_crtc_state(crtc_state);
13093 first_pipe = intel_crtc->pipe;
13094 }
13095 }
13096
13097 /* No workaround needed? */
13098 if (!first_crtc_state)
13099 return 0;
13100
13101 /* w/a possibly needed, check how many crtc's are already enabled. */
13102 for_each_intel_crtc(state->dev, intel_crtc) {
13103 struct intel_crtc_state *pipe_config;
13104
13105 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13106 if (IS_ERR(pipe_config))
13107 return PTR_ERR(pipe_config);
13108
13109 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13110
13111 if (!pipe_config->base.active ||
13112 needs_modeset(&pipe_config->base))
13113 continue;
13114
13115 /* 2 or more enabled crtcs means no need for w/a */
13116 if (enabled_pipe != INVALID_PIPE)
13117 return 0;
13118
13119 enabled_pipe = intel_crtc->pipe;
13120 }
13121
13122 if (enabled_pipe != INVALID_PIPE)
13123 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13124 else if (other_crtc_state)
13125 other_crtc_state->hsw_workaround_pipe = first_pipe;
13126
13127 return 0;
13128 }
13129
13130 /* Code that should eventually be part of atomic_check() */
13131 static int intel_modeset_checks(struct drm_atomic_state *state)
13132 {
13133 struct drm_device *dev = state->dev;
13134 int ret;
13135
13136 if (!check_digital_port_conflicts(state)) {
13137 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13138 return -EINVAL;
13139 }
13140
13141 /*
13142 * See if the config requires any additional preparation, e.g.
13143 * to adjust global state with pipes off. We need to do this
13144 * here so we can get the modeset_pipe updated config for the new
13145 * mode set on this crtc. For other crtcs we need to use the
13146 * adjusted_mode bits in the crtc directly.
13147 */
13148 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
13149 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
13150 ret = valleyview_modeset_global_pipes(state);
13151 else
13152 ret = broadwell_modeset_global_pipes(state);
13153
13154 if (ret)
13155 return ret;
13156 }
13157
13158 intel_modeset_clear_plls(state);
13159
13160 if (IS_HASWELL(dev))
13161 return haswell_mode_set_planes_workaround(state);
13162
13163 return 0;
13164 }
13165
13166 static int
13167 intel_modeset_compute_config(struct drm_atomic_state *state)
13168 {
13169 struct drm_crtc *crtc;
13170 struct drm_crtc_state *crtc_state;
13171 int ret, i;
13172 bool any_ms = false;
13173
13174 ret = drm_atomic_helper_check_modeset(state->dev, state);
13175 if (ret)
13176 return ret;
13177
13178 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13179 if (!crtc_state->enable) {
13180 if (needs_modeset(crtc_state))
13181 any_ms = true;
13182 continue;
13183 }
13184
13185 if (!needs_modeset(crtc_state)) {
13186 ret = drm_atomic_add_affected_connectors(state, crtc);
13187 if (ret)
13188 return ret;
13189 }
13190
13191 ret = intel_modeset_pipe_config(crtc,
13192 to_intel_crtc_state(crtc_state));
13193 if (ret)
13194 return ret;
13195
13196 if (needs_modeset(crtc_state))
13197 any_ms = true;
13198
13199 intel_dump_pipe_config(to_intel_crtc(crtc),
13200 to_intel_crtc_state(crtc_state),
13201 "[modeset]");
13202 }
13203
13204 if (any_ms) {
13205 ret = intel_modeset_checks(state);
13206
13207 if (ret)
13208 return ret;
13209 }
13210
13211 return drm_atomic_helper_check_planes(state->dev, state);
13212 }
13213
13214 static int __intel_set_mode(struct drm_atomic_state *state)
13215 {
13216 struct drm_device *dev = state->dev;
13217 struct drm_i915_private *dev_priv = dev->dev_private;
13218 struct drm_crtc *crtc;
13219 struct drm_crtc_state *crtc_state;
13220 int ret = 0;
13221 int i;
13222 bool any_ms = false;
13223
13224 ret = drm_atomic_helper_prepare_planes(dev, state);
13225 if (ret)
13226 return ret;
13227
13228 drm_atomic_helper_swap_state(dev, state);
13229
13230 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13231 if (!needs_modeset(crtc->state))
13232 continue;
13233
13234 any_ms = true;
13235 if (!crtc_state->active)
13236 continue;
13237
13238 intel_crtc_disable_planes(crtc);
13239 dev_priv->display.crtc_disable(crtc);
13240 }
13241
13242 /* Only after disabling all output pipelines that will be changed can we
13243 * update the the output configuration. */
13244 intel_modeset_update_state(state);
13245
13246 /* The state has been swaped above, so state actually contains the
13247 * old state now. */
13248 if (any_ms)
13249 modeset_update_crtc_power_domains(state);
13250
13251 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13252 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13253 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13254
13255 if (!needs_modeset(crtc->state) || !crtc->state->active)
13256 continue;
13257
13258 update_scanline_offset(to_intel_crtc(crtc));
13259
13260 dev_priv->display.crtc_enable(crtc);
13261 intel_crtc_enable_planes(crtc);
13262 }
13263
13264 /* FIXME: add subpixel order */
13265
13266 drm_atomic_helper_cleanup_planes(dev, state);
13267
13268 drm_atomic_state_free(state);
13269
13270 return 0;
13271 }
13272
13273 static int intel_set_mode_checked(struct drm_atomic_state *state)
13274 {
13275 struct drm_device *dev = state->dev;
13276 int ret;
13277
13278 ret = __intel_set_mode(state);
13279 if (ret == 0)
13280 intel_modeset_check_state(dev);
13281
13282 return ret;
13283 }
13284
13285 static int intel_set_mode(struct drm_atomic_state *state)
13286 {
13287 int ret;
13288
13289 ret = intel_modeset_compute_config(state);
13290 if (ret)
13291 return ret;
13292
13293 return intel_set_mode_checked(state);
13294 }
13295
13296 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13297 {
13298 struct drm_device *dev = crtc->dev;
13299 struct drm_atomic_state *state;
13300 struct intel_crtc *intel_crtc;
13301 struct intel_encoder *encoder;
13302 struct intel_connector *connector;
13303 struct drm_connector_state *connector_state;
13304 struct intel_crtc_state *crtc_state;
13305 int ret;
13306
13307 state = drm_atomic_state_alloc(dev);
13308 if (!state) {
13309 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13310 crtc->base.id);
13311 return;
13312 }
13313
13314 state->acquire_ctx = dev->mode_config.acquire_ctx;
13315
13316 /* The force restore path in the HW readout code relies on the staged
13317 * config still keeping the user requested config while the actual
13318 * state has been overwritten by the configuration read from HW. We
13319 * need to copy the staged config to the atomic state, otherwise the
13320 * mode set will just reapply the state the HW is already in. */
13321 for_each_intel_encoder(dev, encoder) {
13322 if (&encoder->new_crtc->base != crtc)
13323 continue;
13324
13325 for_each_intel_connector(dev, connector) {
13326 if (connector->new_encoder != encoder)
13327 continue;
13328
13329 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13330 if (IS_ERR(connector_state)) {
13331 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13332 connector->base.base.id,
13333 connector->base.name,
13334 PTR_ERR(connector_state));
13335 continue;
13336 }
13337
13338 connector_state->crtc = crtc;
13339 connector_state->best_encoder = &encoder->base;
13340 }
13341 }
13342
13343 for_each_intel_crtc(dev, intel_crtc) {
13344 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13345 continue;
13346
13347 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13348 if (IS_ERR(crtc_state)) {
13349 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13350 intel_crtc->base.base.id,
13351 PTR_ERR(crtc_state));
13352 continue;
13353 }
13354
13355 crtc_state->base.active = crtc_state->base.enable =
13356 intel_crtc->new_enabled;
13357
13358 if (&intel_crtc->base == crtc)
13359 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13360 }
13361
13362 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13363 crtc->primary->fb, crtc->x, crtc->y);
13364
13365 ret = intel_set_mode(state);
13366 if (ret)
13367 drm_atomic_state_free(state);
13368 }
13369
13370 #undef for_each_intel_crtc_masked
13371
13372 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13373 struct drm_mode_set *set)
13374 {
13375 int ro;
13376
13377 for (ro = 0; ro < set->num_connectors; ro++)
13378 if (set->connectors[ro] == &connector->base)
13379 return true;
13380
13381 return false;
13382 }
13383
13384 static int
13385 intel_modeset_stage_output_state(struct drm_device *dev,
13386 struct drm_mode_set *set,
13387 struct drm_atomic_state *state)
13388 {
13389 struct intel_connector *connector;
13390 struct drm_connector *drm_connector;
13391 struct drm_connector_state *connector_state;
13392 struct drm_crtc *crtc;
13393 struct drm_crtc_state *crtc_state;
13394 int i, ret;
13395
13396 /* The upper layers ensure that we either disable a crtc or have a list
13397 * of connectors. For paranoia, double-check this. */
13398 WARN_ON(!set->fb && (set->num_connectors != 0));
13399 WARN_ON(set->fb && (set->num_connectors == 0));
13400
13401 for_each_intel_connector(dev, connector) {
13402 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13403
13404 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13405 continue;
13406
13407 connector_state =
13408 drm_atomic_get_connector_state(state, &connector->base);
13409 if (IS_ERR(connector_state))
13410 return PTR_ERR(connector_state);
13411
13412 if (in_mode_set) {
13413 int pipe = to_intel_crtc(set->crtc)->pipe;
13414 connector_state->best_encoder =
13415 &intel_find_encoder(connector, pipe)->base;
13416 }
13417
13418 if (connector->base.state->crtc != set->crtc)
13419 continue;
13420
13421 /* If we disable the crtc, disable all its connectors. Also, if
13422 * the connector is on the changing crtc but not on the new
13423 * connector list, disable it. */
13424 if (!set->fb || !in_mode_set) {
13425 connector_state->best_encoder = NULL;
13426
13427 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13428 connector->base.base.id,
13429 connector->base.name);
13430 }
13431 }
13432 /* connector->new_encoder is now updated for all connectors. */
13433
13434 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13435 connector = to_intel_connector(drm_connector);
13436
13437 if (!connector_state->best_encoder) {
13438 ret = drm_atomic_set_crtc_for_connector(connector_state,
13439 NULL);
13440 if (ret)
13441 return ret;
13442
13443 continue;
13444 }
13445
13446 if (intel_connector_in_mode_set(connector, set)) {
13447 struct drm_crtc *crtc = connector->base.state->crtc;
13448
13449 /* If this connector was in a previous crtc, add it
13450 * to the state. We might need to disable it. */
13451 if (crtc) {
13452 crtc_state =
13453 drm_atomic_get_crtc_state(state, crtc);
13454 if (IS_ERR(crtc_state))
13455 return PTR_ERR(crtc_state);
13456 }
13457
13458 ret = drm_atomic_set_crtc_for_connector(connector_state,
13459 set->crtc);
13460 if (ret)
13461 return ret;
13462 }
13463
13464 /* Make sure the new CRTC will work with the encoder */
13465 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13466 connector_state->crtc)) {
13467 return -EINVAL;
13468 }
13469
13470 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13471 connector->base.base.id,
13472 connector->base.name,
13473 connector_state->crtc->base.id);
13474
13475 if (connector_state->best_encoder != &connector->encoder->base)
13476 connector->encoder =
13477 to_intel_encoder(connector_state->best_encoder);
13478 }
13479
13480 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13481 bool has_connectors;
13482
13483 ret = drm_atomic_add_affected_connectors(state, crtc);
13484 if (ret)
13485 return ret;
13486
13487 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13488 if (has_connectors != crtc_state->enable)
13489 crtc_state->enable =
13490 crtc_state->active = has_connectors;
13491 }
13492
13493 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13494 set->fb, set->x, set->y);
13495 if (ret)
13496 return ret;
13497
13498 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13499 if (IS_ERR(crtc_state))
13500 return PTR_ERR(crtc_state);
13501
13502 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13503 if (ret)
13504 return ret;
13505
13506 if (set->num_connectors)
13507 crtc_state->active = true;
13508
13509 return 0;
13510 }
13511
13512 static int intel_crtc_set_config(struct drm_mode_set *set)
13513 {
13514 struct drm_device *dev;
13515 struct drm_atomic_state *state = NULL;
13516 int ret;
13517
13518 BUG_ON(!set);
13519 BUG_ON(!set->crtc);
13520 BUG_ON(!set->crtc->helper_private);
13521
13522 /* Enforce sane interface api - has been abused by the fb helper. */
13523 BUG_ON(!set->mode && set->fb);
13524 BUG_ON(set->fb && set->num_connectors == 0);
13525
13526 if (set->fb) {
13527 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13528 set->crtc->base.id, set->fb->base.id,
13529 (int)set->num_connectors, set->x, set->y);
13530 } else {
13531 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13532 }
13533
13534 dev = set->crtc->dev;
13535
13536 state = drm_atomic_state_alloc(dev);
13537 if (!state)
13538 return -ENOMEM;
13539
13540 state->acquire_ctx = dev->mode_config.acquire_ctx;
13541
13542 ret = intel_modeset_stage_output_state(dev, set, state);
13543 if (ret)
13544 goto out;
13545
13546 ret = intel_modeset_compute_config(state);
13547 if (ret)
13548 goto out;
13549
13550 intel_update_pipe_size(to_intel_crtc(set->crtc));
13551
13552 ret = intel_set_mode_checked(state);
13553 if (ret) {
13554 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13555 set->crtc->base.id, ret);
13556 }
13557
13558 out:
13559 if (ret)
13560 drm_atomic_state_free(state);
13561 return ret;
13562 }
13563
13564 static const struct drm_crtc_funcs intel_crtc_funcs = {
13565 .gamma_set = intel_crtc_gamma_set,
13566 .set_config = intel_crtc_set_config,
13567 .destroy = intel_crtc_destroy,
13568 .page_flip = intel_crtc_page_flip,
13569 .atomic_duplicate_state = intel_crtc_duplicate_state,
13570 .atomic_destroy_state = intel_crtc_destroy_state,
13571 };
13572
13573 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13574 struct intel_shared_dpll *pll,
13575 struct intel_dpll_hw_state *hw_state)
13576 {
13577 uint32_t val;
13578
13579 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13580 return false;
13581
13582 val = I915_READ(PCH_DPLL(pll->id));
13583 hw_state->dpll = val;
13584 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13585 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13586
13587 return val & DPLL_VCO_ENABLE;
13588 }
13589
13590 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13591 struct intel_shared_dpll *pll)
13592 {
13593 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13594 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13595 }
13596
13597 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13598 struct intel_shared_dpll *pll)
13599 {
13600 /* PCH refclock must be enabled first */
13601 ibx_assert_pch_refclk_enabled(dev_priv);
13602
13603 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13604
13605 /* Wait for the clocks to stabilize. */
13606 POSTING_READ(PCH_DPLL(pll->id));
13607 udelay(150);
13608
13609 /* The pixel multiplier can only be updated once the
13610 * DPLL is enabled and the clocks are stable.
13611 *
13612 * So write it again.
13613 */
13614 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13615 POSTING_READ(PCH_DPLL(pll->id));
13616 udelay(200);
13617 }
13618
13619 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13620 struct intel_shared_dpll *pll)
13621 {
13622 struct drm_device *dev = dev_priv->dev;
13623 struct intel_crtc *crtc;
13624
13625 /* Make sure no transcoder isn't still depending on us. */
13626 for_each_intel_crtc(dev, crtc) {
13627 if (intel_crtc_to_shared_dpll(crtc) == pll)
13628 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13629 }
13630
13631 I915_WRITE(PCH_DPLL(pll->id), 0);
13632 POSTING_READ(PCH_DPLL(pll->id));
13633 udelay(200);
13634 }
13635
13636 static char *ibx_pch_dpll_names[] = {
13637 "PCH DPLL A",
13638 "PCH DPLL B",
13639 };
13640
13641 static void ibx_pch_dpll_init(struct drm_device *dev)
13642 {
13643 struct drm_i915_private *dev_priv = dev->dev_private;
13644 int i;
13645
13646 dev_priv->num_shared_dpll = 2;
13647
13648 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13649 dev_priv->shared_dplls[i].id = i;
13650 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13651 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13652 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13653 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13654 dev_priv->shared_dplls[i].get_hw_state =
13655 ibx_pch_dpll_get_hw_state;
13656 }
13657 }
13658
13659 static void intel_shared_dpll_init(struct drm_device *dev)
13660 {
13661 struct drm_i915_private *dev_priv = dev->dev_private;
13662
13663 intel_update_cdclk(dev);
13664
13665 if (HAS_DDI(dev))
13666 intel_ddi_pll_init(dev);
13667 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13668 ibx_pch_dpll_init(dev);
13669 else
13670 dev_priv->num_shared_dpll = 0;
13671
13672 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13673 }
13674
13675 /**
13676 * intel_prepare_plane_fb - Prepare fb for usage on plane
13677 * @plane: drm plane to prepare for
13678 * @fb: framebuffer to prepare for presentation
13679 *
13680 * Prepares a framebuffer for usage on a display plane. Generally this
13681 * involves pinning the underlying object and updating the frontbuffer tracking
13682 * bits. Some older platforms need special physical address handling for
13683 * cursor planes.
13684 *
13685 * Returns 0 on success, negative error code on failure.
13686 */
13687 int
13688 intel_prepare_plane_fb(struct drm_plane *plane,
13689 struct drm_framebuffer *fb,
13690 const struct drm_plane_state *new_state)
13691 {
13692 struct drm_device *dev = plane->dev;
13693 struct intel_plane *intel_plane = to_intel_plane(plane);
13694 enum pipe pipe = intel_plane->pipe;
13695 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13696 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13697 unsigned frontbuffer_bits = 0;
13698 int ret = 0;
13699
13700 if (!obj)
13701 return 0;
13702
13703 switch (plane->type) {
13704 case DRM_PLANE_TYPE_PRIMARY:
13705 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13706 break;
13707 case DRM_PLANE_TYPE_CURSOR:
13708 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13709 break;
13710 case DRM_PLANE_TYPE_OVERLAY:
13711 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13712 break;
13713 }
13714
13715 mutex_lock(&dev->struct_mutex);
13716
13717 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13718 INTEL_INFO(dev)->cursor_needs_physical) {
13719 int align = IS_I830(dev) ? 16 * 1024 : 256;
13720 ret = i915_gem_object_attach_phys(obj, align);
13721 if (ret)
13722 DRM_DEBUG_KMS("failed to attach phys object\n");
13723 } else {
13724 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13725 }
13726
13727 if (ret == 0)
13728 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13729
13730 mutex_unlock(&dev->struct_mutex);
13731
13732 return ret;
13733 }
13734
13735 /**
13736 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13737 * @plane: drm plane to clean up for
13738 * @fb: old framebuffer that was on plane
13739 *
13740 * Cleans up a framebuffer that has just been removed from a plane.
13741 */
13742 void
13743 intel_cleanup_plane_fb(struct drm_plane *plane,
13744 struct drm_framebuffer *fb,
13745 const struct drm_plane_state *old_state)
13746 {
13747 struct drm_device *dev = plane->dev;
13748 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13749
13750 if (WARN_ON(!obj))
13751 return;
13752
13753 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13754 !INTEL_INFO(dev)->cursor_needs_physical) {
13755 mutex_lock(&dev->struct_mutex);
13756 intel_unpin_fb_obj(fb, old_state);
13757 mutex_unlock(&dev->struct_mutex);
13758 }
13759 }
13760
13761 int
13762 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13763 {
13764 int max_scale;
13765 struct drm_device *dev;
13766 struct drm_i915_private *dev_priv;
13767 int crtc_clock, cdclk;
13768
13769 if (!intel_crtc || !crtc_state)
13770 return DRM_PLANE_HELPER_NO_SCALING;
13771
13772 dev = intel_crtc->base.dev;
13773 dev_priv = dev->dev_private;
13774 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13775 cdclk = dev_priv->display.get_display_clock_speed(dev);
13776
13777 if (!crtc_clock || !cdclk)
13778 return DRM_PLANE_HELPER_NO_SCALING;
13779
13780 /*
13781 * skl max scale is lower of:
13782 * close to 3 but not 3, -1 is for that purpose
13783 * or
13784 * cdclk/crtc_clock
13785 */
13786 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13787
13788 return max_scale;
13789 }
13790
13791 static int
13792 intel_check_primary_plane(struct drm_plane *plane,
13793 struct intel_crtc_state *crtc_state,
13794 struct intel_plane_state *state)
13795 {
13796 struct drm_crtc *crtc = state->base.crtc;
13797 struct drm_framebuffer *fb = state->base.fb;
13798 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13799 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13800 bool can_position = false;
13801
13802 /* use scaler when colorkey is not required */
13803 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13804 to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13805 min_scale = 1;
13806 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13807 can_position = true;
13808 }
13809
13810 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13811 &state->dst, &state->clip,
13812 min_scale, max_scale,
13813 can_position, true,
13814 &state->visible);
13815 }
13816
13817 static void
13818 intel_commit_primary_plane(struct drm_plane *plane,
13819 struct intel_plane_state *state)
13820 {
13821 struct drm_crtc *crtc = state->base.crtc;
13822 struct drm_framebuffer *fb = state->base.fb;
13823 struct drm_device *dev = plane->dev;
13824 struct drm_i915_private *dev_priv = dev->dev_private;
13825 struct intel_crtc *intel_crtc;
13826 struct drm_rect *src = &state->src;
13827
13828 crtc = crtc ? crtc : plane->crtc;
13829 intel_crtc = to_intel_crtc(crtc);
13830
13831 plane->fb = fb;
13832 crtc->x = src->x1 >> 16;
13833 crtc->y = src->y1 >> 16;
13834
13835 if (!intel_crtc->active)
13836 return;
13837
13838 if (state->visible)
13839 /* FIXME: kill this fastboot hack */
13840 intel_update_pipe_size(intel_crtc);
13841
13842 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13843 }
13844
13845 static void
13846 intel_disable_primary_plane(struct drm_plane *plane,
13847 struct drm_crtc *crtc)
13848 {
13849 struct drm_device *dev = plane->dev;
13850 struct drm_i915_private *dev_priv = dev->dev_private;
13851
13852 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13853 }
13854
13855 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13856 {
13857 struct drm_device *dev = crtc->dev;
13858 struct drm_i915_private *dev_priv = dev->dev_private;
13859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13860
13861 intel_pre_plane_update(intel_crtc);
13862
13863 if (intel_crtc->atomic.update_wm)
13864 intel_update_watermarks(crtc);
13865
13866 intel_runtime_pm_get(dev_priv);
13867
13868 /* Perform vblank evasion around commit operation */
13869 if (crtc->state->active && !needs_modeset(crtc->state))
13870 intel_crtc->atomic.evade =
13871 intel_pipe_update_start(intel_crtc,
13872 &intel_crtc->atomic.start_vbl_count);
13873
13874 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13875 skl_detach_scalers(intel_crtc);
13876 }
13877
13878 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13879 {
13880 struct drm_device *dev = crtc->dev;
13881 struct drm_i915_private *dev_priv = dev->dev_private;
13882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13883
13884 if (intel_crtc->atomic.evade)
13885 intel_pipe_update_end(intel_crtc,
13886 intel_crtc->atomic.start_vbl_count);
13887
13888 intel_runtime_pm_put(dev_priv);
13889
13890 intel_post_plane_update(intel_crtc);
13891 }
13892
13893 /**
13894 * intel_plane_destroy - destroy a plane
13895 * @plane: plane to destroy
13896 *
13897 * Common destruction function for all types of planes (primary, cursor,
13898 * sprite).
13899 */
13900 void intel_plane_destroy(struct drm_plane *plane)
13901 {
13902 struct intel_plane *intel_plane = to_intel_plane(plane);
13903 drm_plane_cleanup(plane);
13904 kfree(intel_plane);
13905 }
13906
13907 const struct drm_plane_funcs intel_plane_funcs = {
13908 .update_plane = drm_atomic_helper_update_plane,
13909 .disable_plane = drm_atomic_helper_disable_plane,
13910 .destroy = intel_plane_destroy,
13911 .set_property = drm_atomic_helper_plane_set_property,
13912 .atomic_get_property = intel_plane_atomic_get_property,
13913 .atomic_set_property = intel_plane_atomic_set_property,
13914 .atomic_duplicate_state = intel_plane_duplicate_state,
13915 .atomic_destroy_state = intel_plane_destroy_state,
13916
13917 };
13918
13919 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13920 int pipe)
13921 {
13922 struct intel_plane *primary;
13923 struct intel_plane_state *state;
13924 const uint32_t *intel_primary_formats;
13925 int num_formats;
13926
13927 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13928 if (primary == NULL)
13929 return NULL;
13930
13931 state = intel_create_plane_state(&primary->base);
13932 if (!state) {
13933 kfree(primary);
13934 return NULL;
13935 }
13936 primary->base.state = &state->base;
13937
13938 primary->can_scale = false;
13939 primary->max_downscale = 1;
13940 if (INTEL_INFO(dev)->gen >= 9) {
13941 primary->can_scale = true;
13942 state->scaler_id = -1;
13943 }
13944 primary->pipe = pipe;
13945 primary->plane = pipe;
13946 primary->check_plane = intel_check_primary_plane;
13947 primary->commit_plane = intel_commit_primary_plane;
13948 primary->disable_plane = intel_disable_primary_plane;
13949 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13950 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13951 primary->plane = !pipe;
13952
13953 if (INTEL_INFO(dev)->gen >= 9) {
13954 intel_primary_formats = skl_primary_formats;
13955 num_formats = ARRAY_SIZE(skl_primary_formats);
13956 } else if (INTEL_INFO(dev)->gen >= 4) {
13957 intel_primary_formats = i965_primary_formats;
13958 num_formats = ARRAY_SIZE(i965_primary_formats);
13959 } else {
13960 intel_primary_formats = i8xx_primary_formats;
13961 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13962 }
13963
13964 drm_universal_plane_init(dev, &primary->base, 0,
13965 &intel_plane_funcs,
13966 intel_primary_formats, num_formats,
13967 DRM_PLANE_TYPE_PRIMARY);
13968
13969 if (INTEL_INFO(dev)->gen >= 4)
13970 intel_create_rotation_property(dev, primary);
13971
13972 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13973
13974 return &primary->base;
13975 }
13976
13977 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13978 {
13979 if (!dev->mode_config.rotation_property) {
13980 unsigned long flags = BIT(DRM_ROTATE_0) |
13981 BIT(DRM_ROTATE_180);
13982
13983 if (INTEL_INFO(dev)->gen >= 9)
13984 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13985
13986 dev->mode_config.rotation_property =
13987 drm_mode_create_rotation_property(dev, flags);
13988 }
13989 if (dev->mode_config.rotation_property)
13990 drm_object_attach_property(&plane->base.base,
13991 dev->mode_config.rotation_property,
13992 plane->base.state->rotation);
13993 }
13994
13995 static int
13996 intel_check_cursor_plane(struct drm_plane *plane,
13997 struct intel_crtc_state *crtc_state,
13998 struct intel_plane_state *state)
13999 {
14000 struct drm_crtc *crtc = crtc_state->base.crtc;
14001 struct drm_framebuffer *fb = state->base.fb;
14002 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14003 unsigned stride;
14004 int ret;
14005
14006 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14007 &state->dst, &state->clip,
14008 DRM_PLANE_HELPER_NO_SCALING,
14009 DRM_PLANE_HELPER_NO_SCALING,
14010 true, true, &state->visible);
14011 if (ret)
14012 return ret;
14013
14014 /* if we want to turn off the cursor ignore width and height */
14015 if (!obj)
14016 return 0;
14017
14018 /* Check for which cursor types we support */
14019 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14020 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14021 state->base.crtc_w, state->base.crtc_h);
14022 return -EINVAL;
14023 }
14024
14025 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14026 if (obj->base.size < stride * state->base.crtc_h) {
14027 DRM_DEBUG_KMS("buffer is too small\n");
14028 return -ENOMEM;
14029 }
14030
14031 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14032 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14033 return -EINVAL;
14034 }
14035
14036 return 0;
14037 }
14038
14039 static void
14040 intel_disable_cursor_plane(struct drm_plane *plane,
14041 struct drm_crtc *crtc)
14042 {
14043 intel_crtc_update_cursor(crtc, false);
14044 }
14045
14046 static void
14047 intel_commit_cursor_plane(struct drm_plane *plane,
14048 struct intel_plane_state *state)
14049 {
14050 struct drm_crtc *crtc = state->base.crtc;
14051 struct drm_device *dev = plane->dev;
14052 struct intel_crtc *intel_crtc;
14053 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14054 uint32_t addr;
14055
14056 crtc = crtc ? crtc : plane->crtc;
14057 intel_crtc = to_intel_crtc(crtc);
14058
14059 plane->fb = state->base.fb;
14060 crtc->cursor_x = state->base.crtc_x;
14061 crtc->cursor_y = state->base.crtc_y;
14062
14063 if (intel_crtc->cursor_bo == obj)
14064 goto update;
14065
14066 if (!obj)
14067 addr = 0;
14068 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14069 addr = i915_gem_obj_ggtt_offset(obj);
14070 else
14071 addr = obj->phys_handle->busaddr;
14072
14073 intel_crtc->cursor_addr = addr;
14074 intel_crtc->cursor_bo = obj;
14075
14076 update:
14077 if (intel_crtc->active)
14078 intel_crtc_update_cursor(crtc, state->visible);
14079 }
14080
14081 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14082 int pipe)
14083 {
14084 struct intel_plane *cursor;
14085 struct intel_plane_state *state;
14086
14087 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14088 if (cursor == NULL)
14089 return NULL;
14090
14091 state = intel_create_plane_state(&cursor->base);
14092 if (!state) {
14093 kfree(cursor);
14094 return NULL;
14095 }
14096 cursor->base.state = &state->base;
14097
14098 cursor->can_scale = false;
14099 cursor->max_downscale = 1;
14100 cursor->pipe = pipe;
14101 cursor->plane = pipe;
14102 cursor->check_plane = intel_check_cursor_plane;
14103 cursor->commit_plane = intel_commit_cursor_plane;
14104 cursor->disable_plane = intel_disable_cursor_plane;
14105
14106 drm_universal_plane_init(dev, &cursor->base, 0,
14107 &intel_plane_funcs,
14108 intel_cursor_formats,
14109 ARRAY_SIZE(intel_cursor_formats),
14110 DRM_PLANE_TYPE_CURSOR);
14111
14112 if (INTEL_INFO(dev)->gen >= 4) {
14113 if (!dev->mode_config.rotation_property)
14114 dev->mode_config.rotation_property =
14115 drm_mode_create_rotation_property(dev,
14116 BIT(DRM_ROTATE_0) |
14117 BIT(DRM_ROTATE_180));
14118 if (dev->mode_config.rotation_property)
14119 drm_object_attach_property(&cursor->base.base,
14120 dev->mode_config.rotation_property,
14121 state->base.rotation);
14122 }
14123
14124 if (INTEL_INFO(dev)->gen >=9)
14125 state->scaler_id = -1;
14126
14127 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14128
14129 return &cursor->base;
14130 }
14131
14132 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14133 struct intel_crtc_state *crtc_state)
14134 {
14135 int i;
14136 struct intel_scaler *intel_scaler;
14137 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14138
14139 for (i = 0; i < intel_crtc->num_scalers; i++) {
14140 intel_scaler = &scaler_state->scalers[i];
14141 intel_scaler->in_use = 0;
14142 intel_scaler->mode = PS_SCALER_MODE_DYN;
14143 }
14144
14145 scaler_state->scaler_id = -1;
14146 }
14147
14148 static void intel_crtc_init(struct drm_device *dev, int pipe)
14149 {
14150 struct drm_i915_private *dev_priv = dev->dev_private;
14151 struct intel_crtc *intel_crtc;
14152 struct intel_crtc_state *crtc_state = NULL;
14153 struct drm_plane *primary = NULL;
14154 struct drm_plane *cursor = NULL;
14155 int i, ret;
14156
14157 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14158 if (intel_crtc == NULL)
14159 return;
14160
14161 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14162 if (!crtc_state)
14163 goto fail;
14164 intel_crtc->config = crtc_state;
14165 intel_crtc->base.state = &crtc_state->base;
14166 crtc_state->base.crtc = &intel_crtc->base;
14167
14168 /* initialize shared scalers */
14169 if (INTEL_INFO(dev)->gen >= 9) {
14170 if (pipe == PIPE_C)
14171 intel_crtc->num_scalers = 1;
14172 else
14173 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14174
14175 skl_init_scalers(dev, intel_crtc, crtc_state);
14176 }
14177
14178 primary = intel_primary_plane_create(dev, pipe);
14179 if (!primary)
14180 goto fail;
14181
14182 cursor = intel_cursor_plane_create(dev, pipe);
14183 if (!cursor)
14184 goto fail;
14185
14186 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14187 cursor, &intel_crtc_funcs);
14188 if (ret)
14189 goto fail;
14190
14191 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14192 for (i = 0; i < 256; i++) {
14193 intel_crtc->lut_r[i] = i;
14194 intel_crtc->lut_g[i] = i;
14195 intel_crtc->lut_b[i] = i;
14196 }
14197
14198 /*
14199 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14200 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14201 */
14202 intel_crtc->pipe = pipe;
14203 intel_crtc->plane = pipe;
14204 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14205 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14206 intel_crtc->plane = !pipe;
14207 }
14208
14209 intel_crtc->cursor_base = ~0;
14210 intel_crtc->cursor_cntl = ~0;
14211 intel_crtc->cursor_size = ~0;
14212
14213 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14214 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14215 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14216 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14217
14218 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14219
14220 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14221 return;
14222
14223 fail:
14224 if (primary)
14225 drm_plane_cleanup(primary);
14226 if (cursor)
14227 drm_plane_cleanup(cursor);
14228 kfree(crtc_state);
14229 kfree(intel_crtc);
14230 }
14231
14232 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14233 {
14234 struct drm_encoder *encoder = connector->base.encoder;
14235 struct drm_device *dev = connector->base.dev;
14236
14237 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14238
14239 if (!encoder || WARN_ON(!encoder->crtc))
14240 return INVALID_PIPE;
14241
14242 return to_intel_crtc(encoder->crtc)->pipe;
14243 }
14244
14245 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14246 struct drm_file *file)
14247 {
14248 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14249 struct drm_crtc *drmmode_crtc;
14250 struct intel_crtc *crtc;
14251
14252 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14253
14254 if (!drmmode_crtc) {
14255 DRM_ERROR("no such CRTC id\n");
14256 return -ENOENT;
14257 }
14258
14259 crtc = to_intel_crtc(drmmode_crtc);
14260 pipe_from_crtc_id->pipe = crtc->pipe;
14261
14262 return 0;
14263 }
14264
14265 static int intel_encoder_clones(struct intel_encoder *encoder)
14266 {
14267 struct drm_device *dev = encoder->base.dev;
14268 struct intel_encoder *source_encoder;
14269 int index_mask = 0;
14270 int entry = 0;
14271
14272 for_each_intel_encoder(dev, source_encoder) {
14273 if (encoders_cloneable(encoder, source_encoder))
14274 index_mask |= (1 << entry);
14275
14276 entry++;
14277 }
14278
14279 return index_mask;
14280 }
14281
14282 static bool has_edp_a(struct drm_device *dev)
14283 {
14284 struct drm_i915_private *dev_priv = dev->dev_private;
14285
14286 if (!IS_MOBILE(dev))
14287 return false;
14288
14289 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14290 return false;
14291
14292 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14293 return false;
14294
14295 return true;
14296 }
14297
14298 static bool intel_crt_present(struct drm_device *dev)
14299 {
14300 struct drm_i915_private *dev_priv = dev->dev_private;
14301
14302 if (INTEL_INFO(dev)->gen >= 9)
14303 return false;
14304
14305 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14306 return false;
14307
14308 if (IS_CHERRYVIEW(dev))
14309 return false;
14310
14311 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14312 return false;
14313
14314 return true;
14315 }
14316
14317 static void intel_setup_outputs(struct drm_device *dev)
14318 {
14319 struct drm_i915_private *dev_priv = dev->dev_private;
14320 struct intel_encoder *encoder;
14321 bool dpd_is_edp = false;
14322
14323 intel_lvds_init(dev);
14324
14325 if (intel_crt_present(dev))
14326 intel_crt_init(dev);
14327
14328 if (IS_BROXTON(dev)) {
14329 /*
14330 * FIXME: Broxton doesn't support port detection via the
14331 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14332 * detect the ports.
14333 */
14334 intel_ddi_init(dev, PORT_A);
14335 intel_ddi_init(dev, PORT_B);
14336 intel_ddi_init(dev, PORT_C);
14337 } else if (HAS_DDI(dev)) {
14338 int found;
14339
14340 /*
14341 * Haswell uses DDI functions to detect digital outputs.
14342 * On SKL pre-D0 the strap isn't connected, so we assume
14343 * it's there.
14344 */
14345 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14346 /* WaIgnoreDDIAStrap: skl */
14347 if (found ||
14348 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14349 intel_ddi_init(dev, PORT_A);
14350
14351 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14352 * register */
14353 found = I915_READ(SFUSE_STRAP);
14354
14355 if (found & SFUSE_STRAP_DDIB_DETECTED)
14356 intel_ddi_init(dev, PORT_B);
14357 if (found & SFUSE_STRAP_DDIC_DETECTED)
14358 intel_ddi_init(dev, PORT_C);
14359 if (found & SFUSE_STRAP_DDID_DETECTED)
14360 intel_ddi_init(dev, PORT_D);
14361 } else if (HAS_PCH_SPLIT(dev)) {
14362 int found;
14363 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14364
14365 if (has_edp_a(dev))
14366 intel_dp_init(dev, DP_A, PORT_A);
14367
14368 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14369 /* PCH SDVOB multiplex with HDMIB */
14370 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14371 if (!found)
14372 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14373 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14374 intel_dp_init(dev, PCH_DP_B, PORT_B);
14375 }
14376
14377 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14378 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14379
14380 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14381 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14382
14383 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14384 intel_dp_init(dev, PCH_DP_C, PORT_C);
14385
14386 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14387 intel_dp_init(dev, PCH_DP_D, PORT_D);
14388 } else if (IS_VALLEYVIEW(dev)) {
14389 /*
14390 * The DP_DETECTED bit is the latched state of the DDC
14391 * SDA pin at boot. However since eDP doesn't require DDC
14392 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14393 * eDP ports may have been muxed to an alternate function.
14394 * Thus we can't rely on the DP_DETECTED bit alone to detect
14395 * eDP ports. Consult the VBT as well as DP_DETECTED to
14396 * detect eDP ports.
14397 */
14398 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14399 !intel_dp_is_edp(dev, PORT_B))
14400 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14401 PORT_B);
14402 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14403 intel_dp_is_edp(dev, PORT_B))
14404 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14405
14406 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14407 !intel_dp_is_edp(dev, PORT_C))
14408 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14409 PORT_C);
14410 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14411 intel_dp_is_edp(dev, PORT_C))
14412 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14413
14414 if (IS_CHERRYVIEW(dev)) {
14415 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14416 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14417 PORT_D);
14418 /* eDP not supported on port D, so don't check VBT */
14419 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14420 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14421 }
14422
14423 intel_dsi_init(dev);
14424 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14425 bool found = false;
14426
14427 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14428 DRM_DEBUG_KMS("probing SDVOB\n");
14429 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14430 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14431 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14432 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14433 }
14434
14435 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14436 intel_dp_init(dev, DP_B, PORT_B);
14437 }
14438
14439 /* Before G4X SDVOC doesn't have its own detect register */
14440
14441 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14442 DRM_DEBUG_KMS("probing SDVOC\n");
14443 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14444 }
14445
14446 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14447
14448 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14449 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14450 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14451 }
14452 if (SUPPORTS_INTEGRATED_DP(dev))
14453 intel_dp_init(dev, DP_C, PORT_C);
14454 }
14455
14456 if (SUPPORTS_INTEGRATED_DP(dev) &&
14457 (I915_READ(DP_D) & DP_DETECTED))
14458 intel_dp_init(dev, DP_D, PORT_D);
14459 } else if (IS_GEN2(dev))
14460 intel_dvo_init(dev);
14461
14462 if (SUPPORTS_TV(dev))
14463 intel_tv_init(dev);
14464
14465 intel_psr_init(dev);
14466
14467 for_each_intel_encoder(dev, encoder) {
14468 encoder->base.possible_crtcs = encoder->crtc_mask;
14469 encoder->base.possible_clones =
14470 intel_encoder_clones(encoder);
14471 }
14472
14473 intel_init_pch_refclk(dev);
14474
14475 drm_helper_move_panel_connectors_to_head(dev);
14476 }
14477
14478 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14479 {
14480 struct drm_device *dev = fb->dev;
14481 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14482
14483 drm_framebuffer_cleanup(fb);
14484 mutex_lock(&dev->struct_mutex);
14485 WARN_ON(!intel_fb->obj->framebuffer_references--);
14486 drm_gem_object_unreference(&intel_fb->obj->base);
14487 mutex_unlock(&dev->struct_mutex);
14488 kfree(intel_fb);
14489 }
14490
14491 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14492 struct drm_file *file,
14493 unsigned int *handle)
14494 {
14495 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14496 struct drm_i915_gem_object *obj = intel_fb->obj;
14497
14498 return drm_gem_handle_create(file, &obj->base, handle);
14499 }
14500
14501 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14502 .destroy = intel_user_framebuffer_destroy,
14503 .create_handle = intel_user_framebuffer_create_handle,
14504 };
14505
14506 static
14507 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14508 uint32_t pixel_format)
14509 {
14510 u32 gen = INTEL_INFO(dev)->gen;
14511
14512 if (gen >= 9) {
14513 /* "The stride in bytes must not exceed the of the size of 8K
14514 * pixels and 32K bytes."
14515 */
14516 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14517 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14518 return 32*1024;
14519 } else if (gen >= 4) {
14520 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14521 return 16*1024;
14522 else
14523 return 32*1024;
14524 } else if (gen >= 3) {
14525 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14526 return 8*1024;
14527 else
14528 return 16*1024;
14529 } else {
14530 /* XXX DSPC is limited to 4k tiled */
14531 return 8*1024;
14532 }
14533 }
14534
14535 static int intel_framebuffer_init(struct drm_device *dev,
14536 struct intel_framebuffer *intel_fb,
14537 struct drm_mode_fb_cmd2 *mode_cmd,
14538 struct drm_i915_gem_object *obj)
14539 {
14540 unsigned int aligned_height;
14541 int ret;
14542 u32 pitch_limit, stride_alignment;
14543
14544 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14545
14546 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14547 /* Enforce that fb modifier and tiling mode match, but only for
14548 * X-tiled. This is needed for FBC. */
14549 if (!!(obj->tiling_mode == I915_TILING_X) !=
14550 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14551 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14552 return -EINVAL;
14553 }
14554 } else {
14555 if (obj->tiling_mode == I915_TILING_X)
14556 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14557 else if (obj->tiling_mode == I915_TILING_Y) {
14558 DRM_DEBUG("No Y tiling for legacy addfb\n");
14559 return -EINVAL;
14560 }
14561 }
14562
14563 /* Passed in modifier sanity checking. */
14564 switch (mode_cmd->modifier[0]) {
14565 case I915_FORMAT_MOD_Y_TILED:
14566 case I915_FORMAT_MOD_Yf_TILED:
14567 if (INTEL_INFO(dev)->gen < 9) {
14568 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14569 mode_cmd->modifier[0]);
14570 return -EINVAL;
14571 }
14572 case DRM_FORMAT_MOD_NONE:
14573 case I915_FORMAT_MOD_X_TILED:
14574 break;
14575 default:
14576 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14577 mode_cmd->modifier[0]);
14578 return -EINVAL;
14579 }
14580
14581 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14582 mode_cmd->pixel_format);
14583 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14584 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14585 mode_cmd->pitches[0], stride_alignment);
14586 return -EINVAL;
14587 }
14588
14589 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14590 mode_cmd->pixel_format);
14591 if (mode_cmd->pitches[0] > pitch_limit) {
14592 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14593 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14594 "tiled" : "linear",
14595 mode_cmd->pitches[0], pitch_limit);
14596 return -EINVAL;
14597 }
14598
14599 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14600 mode_cmd->pitches[0] != obj->stride) {
14601 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14602 mode_cmd->pitches[0], obj->stride);
14603 return -EINVAL;
14604 }
14605
14606 /* Reject formats not supported by any plane early. */
14607 switch (mode_cmd->pixel_format) {
14608 case DRM_FORMAT_C8:
14609 case DRM_FORMAT_RGB565:
14610 case DRM_FORMAT_XRGB8888:
14611 case DRM_FORMAT_ARGB8888:
14612 break;
14613 case DRM_FORMAT_XRGB1555:
14614 if (INTEL_INFO(dev)->gen > 3) {
14615 DRM_DEBUG("unsupported pixel format: %s\n",
14616 drm_get_format_name(mode_cmd->pixel_format));
14617 return -EINVAL;
14618 }
14619 break;
14620 case DRM_FORMAT_ABGR8888:
14621 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14622 DRM_DEBUG("unsupported pixel format: %s\n",
14623 drm_get_format_name(mode_cmd->pixel_format));
14624 return -EINVAL;
14625 }
14626 break;
14627 case DRM_FORMAT_XBGR8888:
14628 case DRM_FORMAT_XRGB2101010:
14629 case DRM_FORMAT_XBGR2101010:
14630 if (INTEL_INFO(dev)->gen < 4) {
14631 DRM_DEBUG("unsupported pixel format: %s\n",
14632 drm_get_format_name(mode_cmd->pixel_format));
14633 return -EINVAL;
14634 }
14635 break;
14636 case DRM_FORMAT_ABGR2101010:
14637 if (!IS_VALLEYVIEW(dev)) {
14638 DRM_DEBUG("unsupported pixel format: %s\n",
14639 drm_get_format_name(mode_cmd->pixel_format));
14640 return -EINVAL;
14641 }
14642 break;
14643 case DRM_FORMAT_YUYV:
14644 case DRM_FORMAT_UYVY:
14645 case DRM_FORMAT_YVYU:
14646 case DRM_FORMAT_VYUY:
14647 if (INTEL_INFO(dev)->gen < 5) {
14648 DRM_DEBUG("unsupported pixel format: %s\n",
14649 drm_get_format_name(mode_cmd->pixel_format));
14650 return -EINVAL;
14651 }
14652 break;
14653 default:
14654 DRM_DEBUG("unsupported pixel format: %s\n",
14655 drm_get_format_name(mode_cmd->pixel_format));
14656 return -EINVAL;
14657 }
14658
14659 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14660 if (mode_cmd->offsets[0] != 0)
14661 return -EINVAL;
14662
14663 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14664 mode_cmd->pixel_format,
14665 mode_cmd->modifier[0]);
14666 /* FIXME drm helper for size checks (especially planar formats)? */
14667 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14668 return -EINVAL;
14669
14670 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14671 intel_fb->obj = obj;
14672 intel_fb->obj->framebuffer_references++;
14673
14674 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14675 if (ret) {
14676 DRM_ERROR("framebuffer init failed %d\n", ret);
14677 return ret;
14678 }
14679
14680 return 0;
14681 }
14682
14683 static struct drm_framebuffer *
14684 intel_user_framebuffer_create(struct drm_device *dev,
14685 struct drm_file *filp,
14686 struct drm_mode_fb_cmd2 *mode_cmd)
14687 {
14688 struct drm_i915_gem_object *obj;
14689
14690 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14691 mode_cmd->handles[0]));
14692 if (&obj->base == NULL)
14693 return ERR_PTR(-ENOENT);
14694
14695 return intel_framebuffer_create(dev, mode_cmd, obj);
14696 }
14697
14698 #ifndef CONFIG_DRM_I915_FBDEV
14699 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14700 {
14701 }
14702 #endif
14703
14704 static const struct drm_mode_config_funcs intel_mode_funcs = {
14705 .fb_create = intel_user_framebuffer_create,
14706 .output_poll_changed = intel_fbdev_output_poll_changed,
14707 .atomic_check = intel_atomic_check,
14708 .atomic_commit = intel_atomic_commit,
14709 .atomic_state_alloc = intel_atomic_state_alloc,
14710 .atomic_state_clear = intel_atomic_state_clear,
14711 };
14712
14713 /* Set up chip specific display functions */
14714 static void intel_init_display(struct drm_device *dev)
14715 {
14716 struct drm_i915_private *dev_priv = dev->dev_private;
14717
14718 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14719 dev_priv->display.find_dpll = g4x_find_best_dpll;
14720 else if (IS_CHERRYVIEW(dev))
14721 dev_priv->display.find_dpll = chv_find_best_dpll;
14722 else if (IS_VALLEYVIEW(dev))
14723 dev_priv->display.find_dpll = vlv_find_best_dpll;
14724 else if (IS_PINEVIEW(dev))
14725 dev_priv->display.find_dpll = pnv_find_best_dpll;
14726 else
14727 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14728
14729 if (INTEL_INFO(dev)->gen >= 9) {
14730 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14731 dev_priv->display.get_initial_plane_config =
14732 skylake_get_initial_plane_config;
14733 dev_priv->display.crtc_compute_clock =
14734 haswell_crtc_compute_clock;
14735 dev_priv->display.crtc_enable = haswell_crtc_enable;
14736 dev_priv->display.crtc_disable = haswell_crtc_disable;
14737 dev_priv->display.update_primary_plane =
14738 skylake_update_primary_plane;
14739 } else if (HAS_DDI(dev)) {
14740 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14741 dev_priv->display.get_initial_plane_config =
14742 ironlake_get_initial_plane_config;
14743 dev_priv->display.crtc_compute_clock =
14744 haswell_crtc_compute_clock;
14745 dev_priv->display.crtc_enable = haswell_crtc_enable;
14746 dev_priv->display.crtc_disable = haswell_crtc_disable;
14747 dev_priv->display.update_primary_plane =
14748 ironlake_update_primary_plane;
14749 } else if (HAS_PCH_SPLIT(dev)) {
14750 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14751 dev_priv->display.get_initial_plane_config =
14752 ironlake_get_initial_plane_config;
14753 dev_priv->display.crtc_compute_clock =
14754 ironlake_crtc_compute_clock;
14755 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14756 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14757 dev_priv->display.update_primary_plane =
14758 ironlake_update_primary_plane;
14759 } else if (IS_VALLEYVIEW(dev)) {
14760 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14761 dev_priv->display.get_initial_plane_config =
14762 i9xx_get_initial_plane_config;
14763 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14764 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14765 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14766 dev_priv->display.update_primary_plane =
14767 i9xx_update_primary_plane;
14768 } else {
14769 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14770 dev_priv->display.get_initial_plane_config =
14771 i9xx_get_initial_plane_config;
14772 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14773 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14774 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14775 dev_priv->display.update_primary_plane =
14776 i9xx_update_primary_plane;
14777 }
14778
14779 /* Returns the core display clock speed */
14780 if (IS_SKYLAKE(dev))
14781 dev_priv->display.get_display_clock_speed =
14782 skylake_get_display_clock_speed;
14783 else if (IS_BROADWELL(dev))
14784 dev_priv->display.get_display_clock_speed =
14785 broadwell_get_display_clock_speed;
14786 else if (IS_HASWELL(dev))
14787 dev_priv->display.get_display_clock_speed =
14788 haswell_get_display_clock_speed;
14789 else if (IS_VALLEYVIEW(dev))
14790 dev_priv->display.get_display_clock_speed =
14791 valleyview_get_display_clock_speed;
14792 else if (IS_GEN5(dev))
14793 dev_priv->display.get_display_clock_speed =
14794 ilk_get_display_clock_speed;
14795 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14796 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14797 dev_priv->display.get_display_clock_speed =
14798 i945_get_display_clock_speed;
14799 else if (IS_GM45(dev))
14800 dev_priv->display.get_display_clock_speed =
14801 gm45_get_display_clock_speed;
14802 else if (IS_CRESTLINE(dev))
14803 dev_priv->display.get_display_clock_speed =
14804 i965gm_get_display_clock_speed;
14805 else if (IS_PINEVIEW(dev))
14806 dev_priv->display.get_display_clock_speed =
14807 pnv_get_display_clock_speed;
14808 else if (IS_G33(dev) || IS_G4X(dev))
14809 dev_priv->display.get_display_clock_speed =
14810 g33_get_display_clock_speed;
14811 else if (IS_I915G(dev))
14812 dev_priv->display.get_display_clock_speed =
14813 i915_get_display_clock_speed;
14814 else if (IS_I945GM(dev) || IS_845G(dev))
14815 dev_priv->display.get_display_clock_speed =
14816 i9xx_misc_get_display_clock_speed;
14817 else if (IS_PINEVIEW(dev))
14818 dev_priv->display.get_display_clock_speed =
14819 pnv_get_display_clock_speed;
14820 else if (IS_I915GM(dev))
14821 dev_priv->display.get_display_clock_speed =
14822 i915gm_get_display_clock_speed;
14823 else if (IS_I865G(dev))
14824 dev_priv->display.get_display_clock_speed =
14825 i865_get_display_clock_speed;
14826 else if (IS_I85X(dev))
14827 dev_priv->display.get_display_clock_speed =
14828 i85x_get_display_clock_speed;
14829 else { /* 830 */
14830 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14831 dev_priv->display.get_display_clock_speed =
14832 i830_get_display_clock_speed;
14833 }
14834
14835 if (IS_GEN5(dev)) {
14836 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14837 } else if (IS_GEN6(dev)) {
14838 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14839 } else if (IS_IVYBRIDGE(dev)) {
14840 /* FIXME: detect B0+ stepping and use auto training */
14841 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14842 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14843 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14844 if (IS_BROADWELL(dev))
14845 dev_priv->display.modeset_global_resources =
14846 broadwell_modeset_global_resources;
14847 } else if (IS_VALLEYVIEW(dev)) {
14848 dev_priv->display.modeset_global_resources =
14849 valleyview_modeset_global_resources;
14850 } else if (IS_BROXTON(dev)) {
14851 dev_priv->display.modeset_global_resources =
14852 broxton_modeset_global_resources;
14853 }
14854
14855 switch (INTEL_INFO(dev)->gen) {
14856 case 2:
14857 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14858 break;
14859
14860 case 3:
14861 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14862 break;
14863
14864 case 4:
14865 case 5:
14866 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14867 break;
14868
14869 case 6:
14870 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14871 break;
14872 case 7:
14873 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14874 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14875 break;
14876 case 9:
14877 /* Drop through - unsupported since execlist only. */
14878 default:
14879 /* Default just returns -ENODEV to indicate unsupported */
14880 dev_priv->display.queue_flip = intel_default_queue_flip;
14881 }
14882
14883 intel_panel_init_backlight_funcs(dev);
14884
14885 mutex_init(&dev_priv->pps_mutex);
14886 }
14887
14888 /*
14889 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14890 * resume, or other times. This quirk makes sure that's the case for
14891 * affected systems.
14892 */
14893 static void quirk_pipea_force(struct drm_device *dev)
14894 {
14895 struct drm_i915_private *dev_priv = dev->dev_private;
14896
14897 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14898 DRM_INFO("applying pipe a force quirk\n");
14899 }
14900
14901 static void quirk_pipeb_force(struct drm_device *dev)
14902 {
14903 struct drm_i915_private *dev_priv = dev->dev_private;
14904
14905 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14906 DRM_INFO("applying pipe b force quirk\n");
14907 }
14908
14909 /*
14910 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14911 */
14912 static void quirk_ssc_force_disable(struct drm_device *dev)
14913 {
14914 struct drm_i915_private *dev_priv = dev->dev_private;
14915 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14916 DRM_INFO("applying lvds SSC disable quirk\n");
14917 }
14918
14919 /*
14920 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14921 * brightness value
14922 */
14923 static void quirk_invert_brightness(struct drm_device *dev)
14924 {
14925 struct drm_i915_private *dev_priv = dev->dev_private;
14926 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14927 DRM_INFO("applying inverted panel brightness quirk\n");
14928 }
14929
14930 /* Some VBT's incorrectly indicate no backlight is present */
14931 static void quirk_backlight_present(struct drm_device *dev)
14932 {
14933 struct drm_i915_private *dev_priv = dev->dev_private;
14934 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14935 DRM_INFO("applying backlight present quirk\n");
14936 }
14937
14938 struct intel_quirk {
14939 int device;
14940 int subsystem_vendor;
14941 int subsystem_device;
14942 void (*hook)(struct drm_device *dev);
14943 };
14944
14945 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14946 struct intel_dmi_quirk {
14947 void (*hook)(struct drm_device *dev);
14948 const struct dmi_system_id (*dmi_id_list)[];
14949 };
14950
14951 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14952 {
14953 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14954 return 1;
14955 }
14956
14957 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14958 {
14959 .dmi_id_list = &(const struct dmi_system_id[]) {
14960 {
14961 .callback = intel_dmi_reverse_brightness,
14962 .ident = "NCR Corporation",
14963 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14964 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14965 },
14966 },
14967 { } /* terminating entry */
14968 },
14969 .hook = quirk_invert_brightness,
14970 },
14971 };
14972
14973 static struct intel_quirk intel_quirks[] = {
14974 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14975 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14976
14977 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14978 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14979
14980 /* 830 needs to leave pipe A & dpll A up */
14981 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14982
14983 /* 830 needs to leave pipe B & dpll B up */
14984 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14985
14986 /* Lenovo U160 cannot use SSC on LVDS */
14987 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14988
14989 /* Sony Vaio Y cannot use SSC on LVDS */
14990 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14991
14992 /* Acer Aspire 5734Z must invert backlight brightness */
14993 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14994
14995 /* Acer/eMachines G725 */
14996 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14997
14998 /* Acer/eMachines e725 */
14999 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15000
15001 /* Acer/Packard Bell NCL20 */
15002 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15003
15004 /* Acer Aspire 4736Z */
15005 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15006
15007 /* Acer Aspire 5336 */
15008 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15009
15010 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15011 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15012
15013 /* Acer C720 Chromebook (Core i3 4005U) */
15014 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15015
15016 /* Apple Macbook 2,1 (Core 2 T7400) */
15017 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15018
15019 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15020 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15021
15022 /* HP Chromebook 14 (Celeron 2955U) */
15023 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15024
15025 /* Dell Chromebook 11 */
15026 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15027 };
15028
15029 static void intel_init_quirks(struct drm_device *dev)
15030 {
15031 struct pci_dev *d = dev->pdev;
15032 int i;
15033
15034 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15035 struct intel_quirk *q = &intel_quirks[i];
15036
15037 if (d->device == q->device &&
15038 (d->subsystem_vendor == q->subsystem_vendor ||
15039 q->subsystem_vendor == PCI_ANY_ID) &&
15040 (d->subsystem_device == q->subsystem_device ||
15041 q->subsystem_device == PCI_ANY_ID))
15042 q->hook(dev);
15043 }
15044 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15045 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15046 intel_dmi_quirks[i].hook(dev);
15047 }
15048 }
15049
15050 /* Disable the VGA plane that we never use */
15051 static void i915_disable_vga(struct drm_device *dev)
15052 {
15053 struct drm_i915_private *dev_priv = dev->dev_private;
15054 u8 sr1;
15055 u32 vga_reg = i915_vgacntrl_reg(dev);
15056
15057 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15058 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15059 outb(SR01, VGA_SR_INDEX);
15060 sr1 = inb(VGA_SR_DATA);
15061 outb(sr1 | 1<<5, VGA_SR_DATA);
15062 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15063 udelay(300);
15064
15065 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15066 POSTING_READ(vga_reg);
15067 }
15068
15069 void intel_modeset_init_hw(struct drm_device *dev)
15070 {
15071 intel_update_cdclk(dev);
15072 intel_prepare_ddi(dev);
15073 intel_init_clock_gating(dev);
15074 intel_enable_gt_powersave(dev);
15075 }
15076
15077 void intel_modeset_init(struct drm_device *dev)
15078 {
15079 struct drm_i915_private *dev_priv = dev->dev_private;
15080 int sprite, ret;
15081 enum pipe pipe;
15082 struct intel_crtc *crtc;
15083
15084 drm_mode_config_init(dev);
15085
15086 dev->mode_config.min_width = 0;
15087 dev->mode_config.min_height = 0;
15088
15089 dev->mode_config.preferred_depth = 24;
15090 dev->mode_config.prefer_shadow = 1;
15091
15092 dev->mode_config.allow_fb_modifiers = true;
15093
15094 dev->mode_config.funcs = &intel_mode_funcs;
15095
15096 intel_init_quirks(dev);
15097
15098 intel_init_pm(dev);
15099
15100 if (INTEL_INFO(dev)->num_pipes == 0)
15101 return;
15102
15103 intel_init_display(dev);
15104 intel_init_audio(dev);
15105
15106 if (IS_GEN2(dev)) {
15107 dev->mode_config.max_width = 2048;
15108 dev->mode_config.max_height = 2048;
15109 } else if (IS_GEN3(dev)) {
15110 dev->mode_config.max_width = 4096;
15111 dev->mode_config.max_height = 4096;
15112 } else {
15113 dev->mode_config.max_width = 8192;
15114 dev->mode_config.max_height = 8192;
15115 }
15116
15117 if (IS_845G(dev) || IS_I865G(dev)) {
15118 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15119 dev->mode_config.cursor_height = 1023;
15120 } else if (IS_GEN2(dev)) {
15121 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15122 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15123 } else {
15124 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15125 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15126 }
15127
15128 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15129
15130 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15131 INTEL_INFO(dev)->num_pipes,
15132 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15133
15134 for_each_pipe(dev_priv, pipe) {
15135 intel_crtc_init(dev, pipe);
15136 for_each_sprite(dev_priv, pipe, sprite) {
15137 ret = intel_plane_init(dev, pipe, sprite);
15138 if (ret)
15139 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15140 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15141 }
15142 }
15143
15144 intel_init_dpio(dev);
15145
15146 intel_shared_dpll_init(dev);
15147
15148 /* Just disable it once at startup */
15149 i915_disable_vga(dev);
15150 intel_setup_outputs(dev);
15151
15152 /* Just in case the BIOS is doing something questionable. */
15153 intel_fbc_disable(dev);
15154
15155 drm_modeset_lock_all(dev);
15156 intel_modeset_setup_hw_state(dev, false);
15157 drm_modeset_unlock_all(dev);
15158
15159 for_each_intel_crtc(dev, crtc) {
15160 if (!crtc->active)
15161 continue;
15162
15163 /*
15164 * Note that reserving the BIOS fb up front prevents us
15165 * from stuffing other stolen allocations like the ring
15166 * on top. This prevents some ugliness at boot time, and
15167 * can even allow for smooth boot transitions if the BIOS
15168 * fb is large enough for the active pipe configuration.
15169 */
15170 if (dev_priv->display.get_initial_plane_config) {
15171 dev_priv->display.get_initial_plane_config(crtc,
15172 &crtc->plane_config);
15173 /*
15174 * If the fb is shared between multiple heads, we'll
15175 * just get the first one.
15176 */
15177 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15178 }
15179 }
15180 }
15181
15182 static void intel_enable_pipe_a(struct drm_device *dev)
15183 {
15184 struct intel_connector *connector;
15185 struct drm_connector *crt = NULL;
15186 struct intel_load_detect_pipe load_detect_temp;
15187 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15188
15189 /* We can't just switch on the pipe A, we need to set things up with a
15190 * proper mode and output configuration. As a gross hack, enable pipe A
15191 * by enabling the load detect pipe once. */
15192 for_each_intel_connector(dev, connector) {
15193 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15194 crt = &connector->base;
15195 break;
15196 }
15197 }
15198
15199 if (!crt)
15200 return;
15201
15202 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15203 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15204 }
15205
15206 static bool
15207 intel_check_plane_mapping(struct intel_crtc *crtc)
15208 {
15209 struct drm_device *dev = crtc->base.dev;
15210 struct drm_i915_private *dev_priv = dev->dev_private;
15211 u32 reg, val;
15212
15213 if (INTEL_INFO(dev)->num_pipes == 1)
15214 return true;
15215
15216 reg = DSPCNTR(!crtc->plane);
15217 val = I915_READ(reg);
15218
15219 if ((val & DISPLAY_PLANE_ENABLE) &&
15220 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15221 return false;
15222
15223 return true;
15224 }
15225
15226 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15227 {
15228 struct drm_device *dev = crtc->base.dev;
15229 struct drm_i915_private *dev_priv = dev->dev_private;
15230 struct intel_encoder *encoder;
15231 u32 reg;
15232 bool enable;
15233
15234 /* Clear any frame start delays used for debugging left by the BIOS */
15235 reg = PIPECONF(crtc->config->cpu_transcoder);
15236 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15237
15238 /* restore vblank interrupts to correct state */
15239 drm_crtc_vblank_reset(&crtc->base);
15240 if (crtc->active) {
15241 update_scanline_offset(crtc);
15242 drm_crtc_vblank_on(&crtc->base);
15243 }
15244
15245 /* We need to sanitize the plane -> pipe mapping first because this will
15246 * disable the crtc (and hence change the state) if it is wrong. Note
15247 * that gen4+ has a fixed plane -> pipe mapping. */
15248 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15249 bool plane;
15250
15251 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15252 crtc->base.base.id);
15253
15254 /* Pipe has the wrong plane attached and the plane is active.
15255 * Temporarily change the plane mapping and disable everything
15256 * ... */
15257 plane = crtc->plane;
15258 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15259 crtc->plane = !plane;
15260 intel_crtc_disable_noatomic(&crtc->base);
15261 crtc->plane = plane;
15262 }
15263
15264 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15265 crtc->pipe == PIPE_A && !crtc->active) {
15266 /* BIOS forgot to enable pipe A, this mostly happens after
15267 * resume. Force-enable the pipe to fix this, the update_dpms
15268 * call below we restore the pipe to the right state, but leave
15269 * the required bits on. */
15270 intel_enable_pipe_a(dev);
15271 }
15272
15273 /* Adjust the state of the output pipe according to whether we
15274 * have active connectors/encoders. */
15275 enable = false;
15276 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15277 enable |= encoder->connectors_active;
15278
15279 if (!enable)
15280 intel_crtc_disable_noatomic(&crtc->base);
15281
15282 if (crtc->active != crtc->base.state->active) {
15283
15284 /* This can happen either due to bugs in the get_hw_state
15285 * functions or because of calls to intel_crtc_disable_noatomic,
15286 * or because the pipe is force-enabled due to the
15287 * pipe A quirk. */
15288 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15289 crtc->base.base.id,
15290 crtc->base.state->enable ? "enabled" : "disabled",
15291 crtc->active ? "enabled" : "disabled");
15292
15293 crtc->base.state->enable = crtc->active;
15294 crtc->base.state->active = crtc->active;
15295 crtc->base.enabled = crtc->active;
15296
15297 /* Because we only establish the connector -> encoder ->
15298 * crtc links if something is active, this means the
15299 * crtc is now deactivated. Break the links. connector
15300 * -> encoder links are only establish when things are
15301 * actually up, hence no need to break them. */
15302 WARN_ON(crtc->active);
15303
15304 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15305 WARN_ON(encoder->connectors_active);
15306 encoder->base.crtc = NULL;
15307 }
15308 }
15309
15310 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15311 /*
15312 * We start out with underrun reporting disabled to avoid races.
15313 * For correct bookkeeping mark this on active crtcs.
15314 *
15315 * Also on gmch platforms we dont have any hardware bits to
15316 * disable the underrun reporting. Which means we need to start
15317 * out with underrun reporting disabled also on inactive pipes,
15318 * since otherwise we'll complain about the garbage we read when
15319 * e.g. coming up after runtime pm.
15320 *
15321 * No protection against concurrent access is required - at
15322 * worst a fifo underrun happens which also sets this to false.
15323 */
15324 crtc->cpu_fifo_underrun_disabled = true;
15325 crtc->pch_fifo_underrun_disabled = true;
15326 }
15327 }
15328
15329 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15330 {
15331 struct intel_connector *connector;
15332 struct drm_device *dev = encoder->base.dev;
15333
15334 /* We need to check both for a crtc link (meaning that the
15335 * encoder is active and trying to read from a pipe) and the
15336 * pipe itself being active. */
15337 bool has_active_crtc = encoder->base.crtc &&
15338 to_intel_crtc(encoder->base.crtc)->active;
15339
15340 if (encoder->connectors_active && !has_active_crtc) {
15341 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15342 encoder->base.base.id,
15343 encoder->base.name);
15344
15345 /* Connector is active, but has no active pipe. This is
15346 * fallout from our resume register restoring. Disable
15347 * the encoder manually again. */
15348 if (encoder->base.crtc) {
15349 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15350 encoder->base.base.id,
15351 encoder->base.name);
15352 encoder->disable(encoder);
15353 if (encoder->post_disable)
15354 encoder->post_disable(encoder);
15355 }
15356 encoder->base.crtc = NULL;
15357 encoder->connectors_active = false;
15358
15359 /* Inconsistent output/port/pipe state happens presumably due to
15360 * a bug in one of the get_hw_state functions. Or someplace else
15361 * in our code, like the register restore mess on resume. Clamp
15362 * things to off as a safer default. */
15363 for_each_intel_connector(dev, connector) {
15364 if (connector->encoder != encoder)
15365 continue;
15366 connector->base.dpms = DRM_MODE_DPMS_OFF;
15367 connector->base.encoder = NULL;
15368 }
15369 }
15370 /* Enabled encoders without active connectors will be fixed in
15371 * the crtc fixup. */
15372 }
15373
15374 void i915_redisable_vga_power_on(struct drm_device *dev)
15375 {
15376 struct drm_i915_private *dev_priv = dev->dev_private;
15377 u32 vga_reg = i915_vgacntrl_reg(dev);
15378
15379 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15380 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15381 i915_disable_vga(dev);
15382 }
15383 }
15384
15385 void i915_redisable_vga(struct drm_device *dev)
15386 {
15387 struct drm_i915_private *dev_priv = dev->dev_private;
15388
15389 /* This function can be called both from intel_modeset_setup_hw_state or
15390 * at a very early point in our resume sequence, where the power well
15391 * structures are not yet restored. Since this function is at a very
15392 * paranoid "someone might have enabled VGA while we were not looking"
15393 * level, just check if the power well is enabled instead of trying to
15394 * follow the "don't touch the power well if we don't need it" policy
15395 * the rest of the driver uses. */
15396 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15397 return;
15398
15399 i915_redisable_vga_power_on(dev);
15400 }
15401
15402 static bool primary_get_hw_state(struct intel_crtc *crtc)
15403 {
15404 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15405
15406 if (!crtc->active)
15407 return false;
15408
15409 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15410 }
15411
15412 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15413 {
15414 struct drm_i915_private *dev_priv = dev->dev_private;
15415 enum pipe pipe;
15416 struct intel_crtc *crtc;
15417 struct intel_encoder *encoder;
15418 struct intel_connector *connector;
15419 int i;
15420
15421 for_each_intel_crtc(dev, crtc) {
15422 struct drm_plane *primary = crtc->base.primary;
15423 struct intel_plane_state *plane_state;
15424
15425 memset(crtc->config, 0, sizeof(*crtc->config));
15426 crtc->config->base.crtc = &crtc->base;
15427
15428 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15429
15430 crtc->active = dev_priv->display.get_pipe_config(crtc,
15431 crtc->config);
15432
15433 crtc->base.state->enable = crtc->active;
15434 crtc->base.state->active = crtc->active;
15435 crtc->base.enabled = crtc->active;
15436 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15437
15438 plane_state = to_intel_plane_state(primary->state);
15439 plane_state->visible = primary_get_hw_state(crtc);
15440
15441 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15442 crtc->base.base.id,
15443 crtc->active ? "enabled" : "disabled");
15444 }
15445
15446 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15447 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15448
15449 pll->on = pll->get_hw_state(dev_priv, pll,
15450 &pll->config.hw_state);
15451 pll->active = 0;
15452 pll->config.crtc_mask = 0;
15453 for_each_intel_crtc(dev, crtc) {
15454 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15455 pll->active++;
15456 pll->config.crtc_mask |= 1 << crtc->pipe;
15457 }
15458 }
15459
15460 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15461 pll->name, pll->config.crtc_mask, pll->on);
15462
15463 if (pll->config.crtc_mask)
15464 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15465 }
15466
15467 for_each_intel_encoder(dev, encoder) {
15468 pipe = 0;
15469
15470 if (encoder->get_hw_state(encoder, &pipe)) {
15471 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15472 encoder->base.crtc = &crtc->base;
15473 encoder->get_config(encoder, crtc->config);
15474 } else {
15475 encoder->base.crtc = NULL;
15476 }
15477
15478 encoder->connectors_active = false;
15479 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15480 encoder->base.base.id,
15481 encoder->base.name,
15482 encoder->base.crtc ? "enabled" : "disabled",
15483 pipe_name(pipe));
15484 }
15485
15486 for_each_intel_connector(dev, connector) {
15487 if (connector->get_hw_state(connector)) {
15488 connector->base.dpms = DRM_MODE_DPMS_ON;
15489 connector->encoder->connectors_active = true;
15490 connector->base.encoder = &connector->encoder->base;
15491 } else {
15492 connector->base.dpms = DRM_MODE_DPMS_OFF;
15493 connector->base.encoder = NULL;
15494 }
15495 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15496 connector->base.base.id,
15497 connector->base.name,
15498 connector->base.encoder ? "enabled" : "disabled");
15499 }
15500 }
15501
15502 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15503 * and i915 state tracking structures. */
15504 void intel_modeset_setup_hw_state(struct drm_device *dev,
15505 bool force_restore)
15506 {
15507 struct drm_i915_private *dev_priv = dev->dev_private;
15508 enum pipe pipe;
15509 struct intel_crtc *crtc;
15510 struct intel_encoder *encoder;
15511 int i;
15512
15513 intel_modeset_readout_hw_state(dev);
15514
15515 /*
15516 * Now that we have the config, copy it to each CRTC struct
15517 * Note that this could go away if we move to using crtc_config
15518 * checking everywhere.
15519 */
15520 for_each_intel_crtc(dev, crtc) {
15521 if (crtc->active && i915.fastboot) {
15522 intel_mode_from_pipe_config(&crtc->base.mode,
15523 crtc->config);
15524 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15525 crtc->base.base.id);
15526 drm_mode_debug_printmodeline(&crtc->base.mode);
15527 }
15528 }
15529
15530 /* HW state is read out, now we need to sanitize this mess. */
15531 for_each_intel_encoder(dev, encoder) {
15532 intel_sanitize_encoder(encoder);
15533 }
15534
15535 for_each_pipe(dev_priv, pipe) {
15536 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15537 intel_sanitize_crtc(crtc);
15538 intel_dump_pipe_config(crtc, crtc->config,
15539 "[setup_hw_state]");
15540 }
15541
15542 intel_modeset_update_connector_atomic_state(dev);
15543
15544 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15545 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15546
15547 if (!pll->on || pll->active)
15548 continue;
15549
15550 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15551
15552 pll->disable(dev_priv, pll);
15553 pll->on = false;
15554 }
15555
15556 if (IS_GEN9(dev))
15557 skl_wm_get_hw_state(dev);
15558 else if (HAS_PCH_SPLIT(dev))
15559 ilk_wm_get_hw_state(dev);
15560
15561 if (force_restore) {
15562 i915_redisable_vga(dev);
15563
15564 /*
15565 * We need to use raw interfaces for restoring state to avoid
15566 * checking (bogus) intermediate states.
15567 */
15568 for_each_pipe(dev_priv, pipe) {
15569 struct drm_crtc *crtc =
15570 dev_priv->pipe_to_crtc_mapping[pipe];
15571
15572 intel_crtc_restore_mode(crtc);
15573 }
15574 } else {
15575 intel_modeset_update_staged_output_state(dev);
15576 }
15577
15578 intel_modeset_check_state(dev);
15579 }
15580
15581 void intel_modeset_gem_init(struct drm_device *dev)
15582 {
15583 struct drm_i915_private *dev_priv = dev->dev_private;
15584 struct drm_crtc *c;
15585 struct drm_i915_gem_object *obj;
15586 int ret;
15587
15588 mutex_lock(&dev->struct_mutex);
15589 intel_init_gt_powersave(dev);
15590 mutex_unlock(&dev->struct_mutex);
15591
15592 /*
15593 * There may be no VBT; and if the BIOS enabled SSC we can
15594 * just keep using it to avoid unnecessary flicker. Whereas if the
15595 * BIOS isn't using it, don't assume it will work even if the VBT
15596 * indicates as much.
15597 */
15598 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15599 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15600 DREF_SSC1_ENABLE);
15601
15602 intel_modeset_init_hw(dev);
15603
15604 intel_setup_overlay(dev);
15605
15606 /*
15607 * Make sure any fbs we allocated at startup are properly
15608 * pinned & fenced. When we do the allocation it's too early
15609 * for this.
15610 */
15611 for_each_crtc(dev, c) {
15612 obj = intel_fb_obj(c->primary->fb);
15613 if (obj == NULL)
15614 continue;
15615
15616 mutex_lock(&dev->struct_mutex);
15617 ret = intel_pin_and_fence_fb_obj(c->primary,
15618 c->primary->fb,
15619 c->primary->state,
15620 NULL);
15621 mutex_unlock(&dev->struct_mutex);
15622 if (ret) {
15623 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15624 to_intel_crtc(c)->pipe);
15625 drm_framebuffer_unreference(c->primary->fb);
15626 c->primary->fb = NULL;
15627 c->primary->crtc = c->primary->state->crtc = NULL;
15628 update_state_fb(c->primary);
15629 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15630 }
15631 }
15632
15633 intel_backlight_register(dev);
15634 }
15635
15636 void intel_connector_unregister(struct intel_connector *intel_connector)
15637 {
15638 struct drm_connector *connector = &intel_connector->base;
15639
15640 intel_panel_destroy_backlight(connector);
15641 drm_connector_unregister(connector);
15642 }
15643
15644 void intel_modeset_cleanup(struct drm_device *dev)
15645 {
15646 struct drm_i915_private *dev_priv = dev->dev_private;
15647 struct drm_connector *connector;
15648
15649 intel_disable_gt_powersave(dev);
15650
15651 intel_backlight_unregister(dev);
15652
15653 /*
15654 * Interrupts and polling as the first thing to avoid creating havoc.
15655 * Too much stuff here (turning of connectors, ...) would
15656 * experience fancy races otherwise.
15657 */
15658 intel_irq_uninstall(dev_priv);
15659
15660 /*
15661 * Due to the hpd irq storm handling the hotplug work can re-arm the
15662 * poll handlers. Hence disable polling after hpd handling is shut down.
15663 */
15664 drm_kms_helper_poll_fini(dev);
15665
15666 mutex_lock(&dev->struct_mutex);
15667
15668 intel_unregister_dsm_handler();
15669
15670 intel_fbc_disable(dev);
15671
15672 mutex_unlock(&dev->struct_mutex);
15673
15674 /* flush any delayed tasks or pending work */
15675 flush_scheduled_work();
15676
15677 /* destroy the backlight and sysfs files before encoders/connectors */
15678 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15679 struct intel_connector *intel_connector;
15680
15681 intel_connector = to_intel_connector(connector);
15682 intel_connector->unregister(intel_connector);
15683 }
15684
15685 drm_mode_config_cleanup(dev);
15686
15687 intel_cleanup_overlay(dev);
15688
15689 mutex_lock(&dev->struct_mutex);
15690 intel_cleanup_gt_powersave(dev);
15691 mutex_unlock(&dev->struct_mutex);
15692 }
15693
15694 /*
15695 * Return which encoder is currently attached for connector.
15696 */
15697 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15698 {
15699 return &intel_attached_encoder(connector)->base;
15700 }
15701
15702 void intel_connector_attach_encoder(struct intel_connector *connector,
15703 struct intel_encoder *encoder)
15704 {
15705 connector->encoder = encoder;
15706 drm_mode_connector_attach_encoder(&connector->base,
15707 &encoder->base);
15708 }
15709
15710 /*
15711 * set vga decode state - true == enable VGA decode
15712 */
15713 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15714 {
15715 struct drm_i915_private *dev_priv = dev->dev_private;
15716 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15717 u16 gmch_ctrl;
15718
15719 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15720 DRM_ERROR("failed to read control word\n");
15721 return -EIO;
15722 }
15723
15724 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15725 return 0;
15726
15727 if (state)
15728 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15729 else
15730 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15731
15732 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15733 DRM_ERROR("failed to write control word\n");
15734 return -EIO;
15735 }
15736
15737 return 0;
15738 }
15739
15740 struct intel_display_error_state {
15741
15742 u32 power_well_driver;
15743
15744 int num_transcoders;
15745
15746 struct intel_cursor_error_state {
15747 u32 control;
15748 u32 position;
15749 u32 base;
15750 u32 size;
15751 } cursor[I915_MAX_PIPES];
15752
15753 struct intel_pipe_error_state {
15754 bool power_domain_on;
15755 u32 source;
15756 u32 stat;
15757 } pipe[I915_MAX_PIPES];
15758
15759 struct intel_plane_error_state {
15760 u32 control;
15761 u32 stride;
15762 u32 size;
15763 u32 pos;
15764 u32 addr;
15765 u32 surface;
15766 u32 tile_offset;
15767 } plane[I915_MAX_PIPES];
15768
15769 struct intel_transcoder_error_state {
15770 bool power_domain_on;
15771 enum transcoder cpu_transcoder;
15772
15773 u32 conf;
15774
15775 u32 htotal;
15776 u32 hblank;
15777 u32 hsync;
15778 u32 vtotal;
15779 u32 vblank;
15780 u32 vsync;
15781 } transcoder[4];
15782 };
15783
15784 struct intel_display_error_state *
15785 intel_display_capture_error_state(struct drm_device *dev)
15786 {
15787 struct drm_i915_private *dev_priv = dev->dev_private;
15788 struct intel_display_error_state *error;
15789 int transcoders[] = {
15790 TRANSCODER_A,
15791 TRANSCODER_B,
15792 TRANSCODER_C,
15793 TRANSCODER_EDP,
15794 };
15795 int i;
15796
15797 if (INTEL_INFO(dev)->num_pipes == 0)
15798 return NULL;
15799
15800 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15801 if (error == NULL)
15802 return NULL;
15803
15804 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15805 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15806
15807 for_each_pipe(dev_priv, i) {
15808 error->pipe[i].power_domain_on =
15809 __intel_display_power_is_enabled(dev_priv,
15810 POWER_DOMAIN_PIPE(i));
15811 if (!error->pipe[i].power_domain_on)
15812 continue;
15813
15814 error->cursor[i].control = I915_READ(CURCNTR(i));
15815 error->cursor[i].position = I915_READ(CURPOS(i));
15816 error->cursor[i].base = I915_READ(CURBASE(i));
15817
15818 error->plane[i].control = I915_READ(DSPCNTR(i));
15819 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15820 if (INTEL_INFO(dev)->gen <= 3) {
15821 error->plane[i].size = I915_READ(DSPSIZE(i));
15822 error->plane[i].pos = I915_READ(DSPPOS(i));
15823 }
15824 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15825 error->plane[i].addr = I915_READ(DSPADDR(i));
15826 if (INTEL_INFO(dev)->gen >= 4) {
15827 error->plane[i].surface = I915_READ(DSPSURF(i));
15828 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15829 }
15830
15831 error->pipe[i].source = I915_READ(PIPESRC(i));
15832
15833 if (HAS_GMCH_DISPLAY(dev))
15834 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15835 }
15836
15837 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15838 if (HAS_DDI(dev_priv->dev))
15839 error->num_transcoders++; /* Account for eDP. */
15840
15841 for (i = 0; i < error->num_transcoders; i++) {
15842 enum transcoder cpu_transcoder = transcoders[i];
15843
15844 error->transcoder[i].power_domain_on =
15845 __intel_display_power_is_enabled(dev_priv,
15846 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15847 if (!error->transcoder[i].power_domain_on)
15848 continue;
15849
15850 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15851
15852 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15853 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15854 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15855 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15856 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15857 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15858 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15859 }
15860
15861 return error;
15862 }
15863
15864 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15865
15866 void
15867 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15868 struct drm_device *dev,
15869 struct intel_display_error_state *error)
15870 {
15871 struct drm_i915_private *dev_priv = dev->dev_private;
15872 int i;
15873
15874 if (!error)
15875 return;
15876
15877 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15878 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15879 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15880 error->power_well_driver);
15881 for_each_pipe(dev_priv, i) {
15882 err_printf(m, "Pipe [%d]:\n", i);
15883 err_printf(m, " Power: %s\n",
15884 error->pipe[i].power_domain_on ? "on" : "off");
15885 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15886 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15887
15888 err_printf(m, "Plane [%d]:\n", i);
15889 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15890 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15891 if (INTEL_INFO(dev)->gen <= 3) {
15892 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15893 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15894 }
15895 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15896 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15897 if (INTEL_INFO(dev)->gen >= 4) {
15898 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15899 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15900 }
15901
15902 err_printf(m, "Cursor [%d]:\n", i);
15903 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15904 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15905 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15906 }
15907
15908 for (i = 0; i < error->num_transcoders; i++) {
15909 err_printf(m, "CPU transcoder: %c\n",
15910 transcoder_name(error->transcoder[i].cpu_transcoder));
15911 err_printf(m, " Power: %s\n",
15912 error->transcoder[i].power_domain_on ? "on" : "off");
15913 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15914 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15915 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15916 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15917 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15918 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15919 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15920 }
15921 }
15922
15923 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15924 {
15925 struct intel_crtc *crtc;
15926
15927 for_each_intel_crtc(dev, crtc) {
15928 struct intel_unpin_work *work;
15929
15930 spin_lock_irq(&dev->event_lock);
15931
15932 work = crtc->unpin_work;
15933
15934 if (work && work->event &&
15935 work->event->base.file_priv == file) {
15936 kfree(work->event);
15937 work->event = NULL;
15938 }
15939
15940 spin_unlock_irq(&dev->event_lock);
15941 }
15942 }
Linux kernel - Deliverables
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