2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
52 DRM_FORMAT_XRGB8888, \
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2
[] = {
57 COMMON_PRIMARY_FORMATS
,
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4
[] = {
64 COMMON_PRIMARY_FORMATS
, \
67 DRM_FORMAT_XRGB2101010
,
68 DRM_FORMAT_ARGB2101010
,
69 DRM_FORMAT_XBGR2101010
,
70 DRM_FORMAT_ABGR2101010
,
74 static const uint32_t intel_cursor_formats
[] = {
78 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
80 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
82 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
83 struct intel_crtc_state
*pipe_config
);
85 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
86 int x
, int y
, struct drm_framebuffer
*old_fb
,
87 struct drm_atomic_state
*state
);
88 static int intel_framebuffer_init(struct drm_device
*dev
,
89 struct intel_framebuffer
*ifb
,
90 struct drm_mode_fb_cmd2
*mode_cmd
,
91 struct drm_i915_gem_object
*obj
);
92 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
93 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
95 struct intel_link_m_n
*m_n
,
96 struct intel_link_m_n
*m2_n2
);
97 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
98 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
99 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
100 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
101 const struct intel_crtc_state
*pipe_config
);
102 static void chv_prepare_pll(struct intel_crtc
*crtc
,
103 const struct intel_crtc_state
*pipe_config
);
104 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
105 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
106 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
107 struct intel_crtc_state
*crtc_state
);
108 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
111 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
113 if (!connector
->mst_port
)
114 return connector
->encoder
;
116 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
125 int p2_slow
, p2_fast
;
128 typedef struct intel_limit intel_limit_t
;
130 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
135 intel_pch_rawclk(struct drm_device
*dev
)
137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
139 WARN_ON(!HAS_PCH_SPLIT(dev
));
141 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
144 static inline u32
/* units of 100MHz */
145 intel_fdi_link_freq(struct drm_device
*dev
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
154 static const intel_limit_t intel_limits_i8xx_dac
= {
155 .dot
= { .min
= 25000, .max
= 350000 },
156 .vco
= { .min
= 908000, .max
= 1512000 },
157 .n
= { .min
= 2, .max
= 16 },
158 .m
= { .min
= 96, .max
= 140 },
159 .m1
= { .min
= 18, .max
= 26 },
160 .m2
= { .min
= 6, .max
= 16 },
161 .p
= { .min
= 4, .max
= 128 },
162 .p1
= { .min
= 2, .max
= 33 },
163 .p2
= { .dot_limit
= 165000,
164 .p2_slow
= 4, .p2_fast
= 2 },
167 static const intel_limit_t intel_limits_i8xx_dvo
= {
168 .dot
= { .min
= 25000, .max
= 350000 },
169 .vco
= { .min
= 908000, .max
= 1512000 },
170 .n
= { .min
= 2, .max
= 16 },
171 .m
= { .min
= 96, .max
= 140 },
172 .m1
= { .min
= 18, .max
= 26 },
173 .m2
= { .min
= 6, .max
= 16 },
174 .p
= { .min
= 4, .max
= 128 },
175 .p1
= { .min
= 2, .max
= 33 },
176 .p2
= { .dot_limit
= 165000,
177 .p2_slow
= 4, .p2_fast
= 4 },
180 static const intel_limit_t intel_limits_i8xx_lvds
= {
181 .dot
= { .min
= 25000, .max
= 350000 },
182 .vco
= { .min
= 908000, .max
= 1512000 },
183 .n
= { .min
= 2, .max
= 16 },
184 .m
= { .min
= 96, .max
= 140 },
185 .m1
= { .min
= 18, .max
= 26 },
186 .m2
= { .min
= 6, .max
= 16 },
187 .p
= { .min
= 4, .max
= 128 },
188 .p1
= { .min
= 1, .max
= 6 },
189 .p2
= { .dot_limit
= 165000,
190 .p2_slow
= 14, .p2_fast
= 7 },
193 static const intel_limit_t intel_limits_i9xx_sdvo
= {
194 .dot
= { .min
= 20000, .max
= 400000 },
195 .vco
= { .min
= 1400000, .max
= 2800000 },
196 .n
= { .min
= 1, .max
= 6 },
197 .m
= { .min
= 70, .max
= 120 },
198 .m1
= { .min
= 8, .max
= 18 },
199 .m2
= { .min
= 3, .max
= 7 },
200 .p
= { .min
= 5, .max
= 80 },
201 .p1
= { .min
= 1, .max
= 8 },
202 .p2
= { .dot_limit
= 200000,
203 .p2_slow
= 10, .p2_fast
= 5 },
206 static const intel_limit_t intel_limits_i9xx_lvds
= {
207 .dot
= { .min
= 20000, .max
= 400000 },
208 .vco
= { .min
= 1400000, .max
= 2800000 },
209 .n
= { .min
= 1, .max
= 6 },
210 .m
= { .min
= 70, .max
= 120 },
211 .m1
= { .min
= 8, .max
= 18 },
212 .m2
= { .min
= 3, .max
= 7 },
213 .p
= { .min
= 7, .max
= 98 },
214 .p1
= { .min
= 1, .max
= 8 },
215 .p2
= { .dot_limit
= 112000,
216 .p2_slow
= 14, .p2_fast
= 7 },
220 static const intel_limit_t intel_limits_g4x_sdvo
= {
221 .dot
= { .min
= 25000, .max
= 270000 },
222 .vco
= { .min
= 1750000, .max
= 3500000},
223 .n
= { .min
= 1, .max
= 4 },
224 .m
= { .min
= 104, .max
= 138 },
225 .m1
= { .min
= 17, .max
= 23 },
226 .m2
= { .min
= 5, .max
= 11 },
227 .p
= { .min
= 10, .max
= 30 },
228 .p1
= { .min
= 1, .max
= 3},
229 .p2
= { .dot_limit
= 270000,
235 static const intel_limit_t intel_limits_g4x_hdmi
= {
236 .dot
= { .min
= 22000, .max
= 400000 },
237 .vco
= { .min
= 1750000, .max
= 3500000},
238 .n
= { .min
= 1, .max
= 4 },
239 .m
= { .min
= 104, .max
= 138 },
240 .m1
= { .min
= 16, .max
= 23 },
241 .m2
= { .min
= 5, .max
= 11 },
242 .p
= { .min
= 5, .max
= 80 },
243 .p1
= { .min
= 1, .max
= 8},
244 .p2
= { .dot_limit
= 165000,
245 .p2_slow
= 10, .p2_fast
= 5 },
248 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
249 .dot
= { .min
= 20000, .max
= 115000 },
250 .vco
= { .min
= 1750000, .max
= 3500000 },
251 .n
= { .min
= 1, .max
= 3 },
252 .m
= { .min
= 104, .max
= 138 },
253 .m1
= { .min
= 17, .max
= 23 },
254 .m2
= { .min
= 5, .max
= 11 },
255 .p
= { .min
= 28, .max
= 112 },
256 .p1
= { .min
= 2, .max
= 8 },
257 .p2
= { .dot_limit
= 0,
258 .p2_slow
= 14, .p2_fast
= 14
262 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
263 .dot
= { .min
= 80000, .max
= 224000 },
264 .vco
= { .min
= 1750000, .max
= 3500000 },
265 .n
= { .min
= 1, .max
= 3 },
266 .m
= { .min
= 104, .max
= 138 },
267 .m1
= { .min
= 17, .max
= 23 },
268 .m2
= { .min
= 5, .max
= 11 },
269 .p
= { .min
= 14, .max
= 42 },
270 .p1
= { .min
= 2, .max
= 6 },
271 .p2
= { .dot_limit
= 0,
272 .p2_slow
= 7, .p2_fast
= 7
276 static const intel_limit_t intel_limits_pineview_sdvo
= {
277 .dot
= { .min
= 20000, .max
= 400000},
278 .vco
= { .min
= 1700000, .max
= 3500000 },
279 /* Pineview's Ncounter is a ring counter */
280 .n
= { .min
= 3, .max
= 6 },
281 .m
= { .min
= 2, .max
= 256 },
282 /* Pineview only has one combined m divider, which we treat as m2. */
283 .m1
= { .min
= 0, .max
= 0 },
284 .m2
= { .min
= 0, .max
= 254 },
285 .p
= { .min
= 5, .max
= 80 },
286 .p1
= { .min
= 1, .max
= 8 },
287 .p2
= { .dot_limit
= 200000,
288 .p2_slow
= 10, .p2_fast
= 5 },
291 static const intel_limit_t intel_limits_pineview_lvds
= {
292 .dot
= { .min
= 20000, .max
= 400000 },
293 .vco
= { .min
= 1700000, .max
= 3500000 },
294 .n
= { .min
= 3, .max
= 6 },
295 .m
= { .min
= 2, .max
= 256 },
296 .m1
= { .min
= 0, .max
= 0 },
297 .m2
= { .min
= 0, .max
= 254 },
298 .p
= { .min
= 7, .max
= 112 },
299 .p1
= { .min
= 1, .max
= 8 },
300 .p2
= { .dot_limit
= 112000,
301 .p2_slow
= 14, .p2_fast
= 14 },
304 /* Ironlake / Sandybridge
306 * We calculate clock using (register_value + 2) for N/M1/M2, so here
307 * the range value for them is (actual_value - 2).
309 static const intel_limit_t intel_limits_ironlake_dac
= {
310 .dot
= { .min
= 25000, .max
= 350000 },
311 .vco
= { .min
= 1760000, .max
= 3510000 },
312 .n
= { .min
= 1, .max
= 5 },
313 .m
= { .min
= 79, .max
= 127 },
314 .m1
= { .min
= 12, .max
= 22 },
315 .m2
= { .min
= 5, .max
= 9 },
316 .p
= { .min
= 5, .max
= 80 },
317 .p1
= { .min
= 1, .max
= 8 },
318 .p2
= { .dot_limit
= 225000,
319 .p2_slow
= 10, .p2_fast
= 5 },
322 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
323 .dot
= { .min
= 25000, .max
= 350000 },
324 .vco
= { .min
= 1760000, .max
= 3510000 },
325 .n
= { .min
= 1, .max
= 3 },
326 .m
= { .min
= 79, .max
= 118 },
327 .m1
= { .min
= 12, .max
= 22 },
328 .m2
= { .min
= 5, .max
= 9 },
329 .p
= { .min
= 28, .max
= 112 },
330 .p1
= { .min
= 2, .max
= 8 },
331 .p2
= { .dot_limit
= 225000,
332 .p2_slow
= 14, .p2_fast
= 14 },
335 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
336 .dot
= { .min
= 25000, .max
= 350000 },
337 .vco
= { .min
= 1760000, .max
= 3510000 },
338 .n
= { .min
= 1, .max
= 3 },
339 .m
= { .min
= 79, .max
= 127 },
340 .m1
= { .min
= 12, .max
= 22 },
341 .m2
= { .min
= 5, .max
= 9 },
342 .p
= { .min
= 14, .max
= 56 },
343 .p1
= { .min
= 2, .max
= 8 },
344 .p2
= { .dot_limit
= 225000,
345 .p2_slow
= 7, .p2_fast
= 7 },
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 28, .max
= 112 },
357 .p1
= { .min
= 2, .max
= 8 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 14, .p2_fast
= 14 },
362 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
363 .dot
= { .min
= 25000, .max
= 350000 },
364 .vco
= { .min
= 1760000, .max
= 3510000 },
365 .n
= { .min
= 1, .max
= 3 },
366 .m
= { .min
= 79, .max
= 126 },
367 .m1
= { .min
= 12, .max
= 22 },
368 .m2
= { .min
= 5, .max
= 9 },
369 .p
= { .min
= 14, .max
= 42 },
370 .p1
= { .min
= 2, .max
= 6 },
371 .p2
= { .dot_limit
= 225000,
372 .p2_slow
= 7, .p2_fast
= 7 },
375 static const intel_limit_t intel_limits_vlv
= {
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
382 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
383 .vco
= { .min
= 4000000, .max
= 6000000 },
384 .n
= { .min
= 1, .max
= 7 },
385 .m1
= { .min
= 2, .max
= 3 },
386 .m2
= { .min
= 11, .max
= 156 },
387 .p1
= { .min
= 2, .max
= 3 },
388 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
391 static const intel_limit_t intel_limits_chv
= {
393 * These are the data rate limits (measured in fast clocks)
394 * since those are the strictest limits we have. The fast
395 * clock and actual rate limits are more relaxed, so checking
396 * them would make no difference.
398 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
399 .vco
= { .min
= 4800000, .max
= 6480000 },
400 .n
= { .min
= 1, .max
= 1 },
401 .m1
= { .min
= 2, .max
= 2 },
402 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
403 .p1
= { .min
= 2, .max
= 4 },
404 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
407 static const intel_limit_t intel_limits_bxt
= {
408 /* FIXME: find real dot limits */
409 .dot
= { .min
= 0, .max
= INT_MAX
},
410 .vco
= { .min
= 4800000, .max
= 6480000 },
411 .n
= { .min
= 1, .max
= 1 },
412 .m1
= { .min
= 2, .max
= 2 },
413 /* FIXME: find real m2 limits */
414 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
415 .p1
= { .min
= 2, .max
= 4 },
416 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
419 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
421 clock
->m
= clock
->m1
* clock
->m2
;
422 clock
->p
= clock
->p1
* clock
->p2
;
423 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
425 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
426 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
430 * Returns whether any output on the specified pipe is of the specified type
432 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
434 struct drm_device
*dev
= crtc
->base
.dev
;
435 struct intel_encoder
*encoder
;
437 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
438 if (encoder
->type
== type
)
445 * Returns whether any output on the specified pipe will have the specified
446 * type after a staged modeset is complete, i.e., the same as
447 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
450 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
453 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
454 struct drm_connector_state
*connector_state
;
455 struct intel_encoder
*encoder
;
456 int i
, num_connectors
= 0;
458 for (i
= 0; i
< state
->num_connector
; i
++) {
459 if (!state
->connectors
[i
])
462 connector_state
= state
->connector_states
[i
];
463 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
468 encoder
= to_intel_encoder(connector_state
->best_encoder
);
469 if (encoder
->type
== type
)
473 WARN_ON(num_connectors
== 0);
478 static const intel_limit_t
*
479 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
481 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
482 const intel_limit_t
*limit
;
484 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
485 if (intel_is_dual_link_lvds(dev
)) {
486 if (refclk
== 100000)
487 limit
= &intel_limits_ironlake_dual_lvds_100m
;
489 limit
= &intel_limits_ironlake_dual_lvds
;
491 if (refclk
== 100000)
492 limit
= &intel_limits_ironlake_single_lvds_100m
;
494 limit
= &intel_limits_ironlake_single_lvds
;
497 limit
= &intel_limits_ironlake_dac
;
502 static const intel_limit_t
*
503 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
505 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
506 const intel_limit_t
*limit
;
508 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
509 if (intel_is_dual_link_lvds(dev
))
510 limit
= &intel_limits_g4x_dual_channel_lvds
;
512 limit
= &intel_limits_g4x_single_channel_lvds
;
513 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
514 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
515 limit
= &intel_limits_g4x_hdmi
;
516 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
517 limit
= &intel_limits_g4x_sdvo
;
518 } else /* The option is for other outputs */
519 limit
= &intel_limits_i9xx_sdvo
;
524 static const intel_limit_t
*
525 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
527 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
528 const intel_limit_t
*limit
;
531 limit
= &intel_limits_bxt
;
532 else if (HAS_PCH_SPLIT(dev
))
533 limit
= intel_ironlake_limit(crtc_state
, refclk
);
534 else if (IS_G4X(dev
)) {
535 limit
= intel_g4x_limit(crtc_state
);
536 } else if (IS_PINEVIEW(dev
)) {
537 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
538 limit
= &intel_limits_pineview_lvds
;
540 limit
= &intel_limits_pineview_sdvo
;
541 } else if (IS_CHERRYVIEW(dev
)) {
542 limit
= &intel_limits_chv
;
543 } else if (IS_VALLEYVIEW(dev
)) {
544 limit
= &intel_limits_vlv
;
545 } else if (!IS_GEN2(dev
)) {
546 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
547 limit
= &intel_limits_i9xx_lvds
;
549 limit
= &intel_limits_i9xx_sdvo
;
551 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
552 limit
= &intel_limits_i8xx_lvds
;
553 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
554 limit
= &intel_limits_i8xx_dvo
;
556 limit
= &intel_limits_i8xx_dac
;
561 /* m1 is reserved as 0 in Pineview, n is a ring counter */
562 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
564 clock
->m
= clock
->m2
+ 2;
565 clock
->p
= clock
->p1
* clock
->p2
;
566 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
568 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
569 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
572 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
574 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
577 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
579 clock
->m
= i9xx_dpll_compute_m(clock
);
580 clock
->p
= clock
->p1
* clock
->p2
;
581 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
583 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
584 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
587 static void chv_clock(int refclk
, intel_clock_t
*clock
)
589 clock
->m
= clock
->m1
* clock
->m2
;
590 clock
->p
= clock
->p1
* clock
->p2
;
591 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
593 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
595 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
598 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
600 * Returns whether the given set of divisors are valid for a given refclk with
601 * the given connectors.
604 static bool intel_PLL_is_valid(struct drm_device
*dev
,
605 const intel_limit_t
*limit
,
606 const intel_clock_t
*clock
)
608 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
609 INTELPllInvalid("n out of range\n");
610 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
611 INTELPllInvalid("p1 out of range\n");
612 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
613 INTELPllInvalid("m2 out of range\n");
614 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
615 INTELPllInvalid("m1 out of range\n");
617 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
618 if (clock
->m1
<= clock
->m2
)
619 INTELPllInvalid("m1 <= m2\n");
621 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
622 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
623 INTELPllInvalid("p out of range\n");
624 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
625 INTELPllInvalid("m out of range\n");
628 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
629 INTELPllInvalid("vco out of range\n");
630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
633 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
634 INTELPllInvalid("dot out of range\n");
640 i9xx_find_best_dpll(const intel_limit_t
*limit
,
641 struct intel_crtc_state
*crtc_state
,
642 int target
, int refclk
, intel_clock_t
*match_clock
,
643 intel_clock_t
*best_clock
)
645 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
646 struct drm_device
*dev
= crtc
->base
.dev
;
650 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
652 * For LVDS just rely on its current settings for dual-channel.
653 * We haven't figured out how to reliably set up different
654 * single/dual channel state, if we even can.
656 if (intel_is_dual_link_lvds(dev
))
657 clock
.p2
= limit
->p2
.p2_fast
;
659 clock
.p2
= limit
->p2
.p2_slow
;
661 if (target
< limit
->p2
.dot_limit
)
662 clock
.p2
= limit
->p2
.p2_slow
;
664 clock
.p2
= limit
->p2
.p2_fast
;
667 memset(best_clock
, 0, sizeof(*best_clock
));
669 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
671 for (clock
.m2
= limit
->m2
.min
;
672 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
673 if (clock
.m2
>= clock
.m1
)
675 for (clock
.n
= limit
->n
.min
;
676 clock
.n
<= limit
->n
.max
; clock
.n
++) {
677 for (clock
.p1
= limit
->p1
.min
;
678 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
681 i9xx_clock(refclk
, &clock
);
682 if (!intel_PLL_is_valid(dev
, limit
,
686 clock
.p
!= match_clock
->p
)
689 this_err
= abs(clock
.dot
- target
);
690 if (this_err
< err
) {
699 return (err
!= target
);
703 pnv_find_best_dpll(const intel_limit_t
*limit
,
704 struct intel_crtc_state
*crtc_state
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
709 struct drm_device
*dev
= crtc
->base
.dev
;
713 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
715 * For LVDS just rely on its current settings for dual-channel.
716 * We haven't figured out how to reliably set up different
717 * single/dual channel state, if we even can.
719 if (intel_is_dual_link_lvds(dev
))
720 clock
.p2
= limit
->p2
.p2_fast
;
722 clock
.p2
= limit
->p2
.p2_slow
;
724 if (target
< limit
->p2
.dot_limit
)
725 clock
.p2
= limit
->p2
.p2_slow
;
727 clock
.p2
= limit
->p2
.p2_fast
;
730 memset(best_clock
, 0, sizeof(*best_clock
));
732 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
734 for (clock
.m2
= limit
->m2
.min
;
735 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
736 for (clock
.n
= limit
->n
.min
;
737 clock
.n
<= limit
->n
.max
; clock
.n
++) {
738 for (clock
.p1
= limit
->p1
.min
;
739 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
742 pineview_clock(refclk
, &clock
);
743 if (!intel_PLL_is_valid(dev
, limit
,
747 clock
.p
!= match_clock
->p
)
750 this_err
= abs(clock
.dot
- target
);
751 if (this_err
< err
) {
760 return (err
!= target
);
764 g4x_find_best_dpll(const intel_limit_t
*limit
,
765 struct intel_crtc_state
*crtc_state
,
766 int target
, int refclk
, intel_clock_t
*match_clock
,
767 intel_clock_t
*best_clock
)
769 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
770 struct drm_device
*dev
= crtc
->base
.dev
;
774 /* approximately equals target * 0.00585 */
775 int err_most
= (target
>> 8) + (target
>> 9);
778 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
779 if (intel_is_dual_link_lvds(dev
))
780 clock
.p2
= limit
->p2
.p2_fast
;
782 clock
.p2
= limit
->p2
.p2_slow
;
784 if (target
< limit
->p2
.dot_limit
)
785 clock
.p2
= limit
->p2
.p2_slow
;
787 clock
.p2
= limit
->p2
.p2_fast
;
790 memset(best_clock
, 0, sizeof(*best_clock
));
791 max_n
= limit
->n
.max
;
792 /* based on hardware requirement, prefer smaller n to precision */
793 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
794 /* based on hardware requirement, prefere larger m1,m2 */
795 for (clock
.m1
= limit
->m1
.max
;
796 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
797 for (clock
.m2
= limit
->m2
.max
;
798 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
799 for (clock
.p1
= limit
->p1
.max
;
800 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
803 i9xx_clock(refclk
, &clock
);
804 if (!intel_PLL_is_valid(dev
, limit
,
808 this_err
= abs(clock
.dot
- target
);
809 if (this_err
< err_most
) {
823 * Check if the calculated PLL configuration is more optimal compared to the
824 * best configuration and error found so far. Return the calculated error.
826 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
827 const intel_clock_t
*calculated_clock
,
828 const intel_clock_t
*best_clock
,
829 unsigned int best_error_ppm
,
830 unsigned int *error_ppm
)
833 * For CHV ignore the error and consider only the P value.
834 * Prefer a bigger P value based on HW requirements.
836 if (IS_CHERRYVIEW(dev
)) {
839 return calculated_clock
->p
> best_clock
->p
;
842 if (WARN_ON_ONCE(!target_freq
))
845 *error_ppm
= div_u64(1000000ULL *
846 abs(target_freq
- calculated_clock
->dot
),
849 * Prefer a better P value over a better (smaller) error if the error
850 * is small. Ensure this preference for future configurations too by
851 * setting the error to 0.
853 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
859 return *error_ppm
+ 10 < best_error_ppm
;
863 vlv_find_best_dpll(const intel_limit_t
*limit
,
864 struct intel_crtc_state
*crtc_state
,
865 int target
, int refclk
, intel_clock_t
*match_clock
,
866 intel_clock_t
*best_clock
)
868 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
869 struct drm_device
*dev
= crtc
->base
.dev
;
871 unsigned int bestppm
= 1000000;
872 /* min update 19.2 MHz */
873 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
876 target
*= 5; /* fast clock */
878 memset(best_clock
, 0, sizeof(*best_clock
));
880 /* based on hardware requirement, prefer smaller n to precision */
881 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
882 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
883 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
884 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
885 clock
.p
= clock
.p1
* clock
.p2
;
886 /* based on hardware requirement, prefer bigger m1,m2 values */
887 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
890 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
893 vlv_clock(refclk
, &clock
);
895 if (!intel_PLL_is_valid(dev
, limit
,
899 if (!vlv_PLL_is_optimal(dev
, target
,
917 chv_find_best_dpll(const intel_limit_t
*limit
,
918 struct intel_crtc_state
*crtc_state
,
919 int target
, int refclk
, intel_clock_t
*match_clock
,
920 intel_clock_t
*best_clock
)
922 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
923 struct drm_device
*dev
= crtc
->base
.dev
;
924 unsigned int best_error_ppm
;
929 memset(best_clock
, 0, sizeof(*best_clock
));
930 best_error_ppm
= 1000000;
933 * Based on hardware doc, the n always set to 1, and m1 always
934 * set to 2. If requires to support 200Mhz refclk, we need to
935 * revisit this because n may not 1 anymore.
937 clock
.n
= 1, clock
.m1
= 2;
938 target
*= 5; /* fast clock */
940 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
941 for (clock
.p2
= limit
->p2
.p2_fast
;
942 clock
.p2
>= limit
->p2
.p2_slow
;
943 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
944 unsigned int error_ppm
;
946 clock
.p
= clock
.p1
* clock
.p2
;
948 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
949 clock
.n
) << 22, refclk
* clock
.m1
);
951 if (m2
> INT_MAX
/clock
.m1
)
956 chv_clock(refclk
, &clock
);
958 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
961 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
962 best_error_ppm
, &error_ppm
))
966 best_error_ppm
= error_ppm
;
974 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
975 intel_clock_t
*best_clock
)
977 int refclk
= i9xx_get_refclk(crtc_state
, 0);
979 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
980 target_clock
, refclk
, NULL
, best_clock
);
983 bool intel_crtc_active(struct drm_crtc
*crtc
)
985 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
987 /* Be paranoid as we can arrive here with only partial
988 * state retrieved from the hardware during setup.
990 * We can ditch the adjusted_mode.crtc_clock check as soon
991 * as Haswell has gained clock readout/fastboot support.
993 * We can ditch the crtc->primary->fb check as soon as we can
994 * properly reconstruct framebuffers.
996 * FIXME: The intel_crtc->active here should be switched to
997 * crtc->state->active once we have proper CRTC states wired up
1000 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1001 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1004 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1007 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1008 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1010 return intel_crtc
->config
->cpu_transcoder
;
1013 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1016 u32 reg
= PIPEDSL(pipe
);
1021 line_mask
= DSL_LINEMASK_GEN2
;
1023 line_mask
= DSL_LINEMASK_GEN3
;
1025 line1
= I915_READ(reg
) & line_mask
;
1027 line2
= I915_READ(reg
) & line_mask
;
1029 return line1
== line2
;
1033 * intel_wait_for_pipe_off - wait for pipe to turn off
1034 * @crtc: crtc whose pipe to wait for
1036 * After disabling a pipe, we can't wait for vblank in the usual way,
1037 * spinning on the vblank interrupt status bit, since we won't actually
1038 * see an interrupt when the pipe is disabled.
1040 * On Gen4 and above:
1041 * wait for the pipe register state bit to turn off
1044 * wait for the display line value to settle (it usually
1045 * ends up stopping at the start of the next frame).
1048 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1050 struct drm_device
*dev
= crtc
->base
.dev
;
1051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1052 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1053 enum pipe pipe
= crtc
->pipe
;
1055 if (INTEL_INFO(dev
)->gen
>= 4) {
1056 int reg
= PIPECONF(cpu_transcoder
);
1058 /* Wait for the Pipe State to go off */
1059 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1061 WARN(1, "pipe_off wait timed out\n");
1063 /* Wait for the display line to settle */
1064 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1065 WARN(1, "pipe_off wait timed out\n");
1070 * ibx_digital_port_connected - is the specified port connected?
1071 * @dev_priv: i915 private structure
1072 * @port: the port to test
1074 * Returns true if @port is connected, false otherwise.
1076 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1077 struct intel_digital_port
*port
)
1081 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1082 switch (port
->port
) {
1084 bit
= SDE_PORTB_HOTPLUG
;
1087 bit
= SDE_PORTC_HOTPLUG
;
1090 bit
= SDE_PORTD_HOTPLUG
;
1096 switch (port
->port
) {
1098 bit
= SDE_PORTB_HOTPLUG_CPT
;
1101 bit
= SDE_PORTC_HOTPLUG_CPT
;
1104 bit
= SDE_PORTD_HOTPLUG_CPT
;
1111 return I915_READ(SDEISR
) & bit
;
1114 static const char *state_string(bool enabled
)
1116 return enabled
? "on" : "off";
1119 /* Only for pre-ILK configs */
1120 void assert_pll(struct drm_i915_private
*dev_priv
,
1121 enum pipe pipe
, bool state
)
1128 val
= I915_READ(reg
);
1129 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1130 I915_STATE_WARN(cur_state
!= state
,
1131 "PLL state assertion failure (expected %s, current %s)\n",
1132 state_string(state
), state_string(cur_state
));
1135 /* XXX: the dsi pll is shared between MIPI DSI ports */
1136 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1141 mutex_lock(&dev_priv
->dpio_lock
);
1142 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1143 mutex_unlock(&dev_priv
->dpio_lock
);
1145 cur_state
= val
& DSI_PLL_VCO_EN
;
1146 I915_STATE_WARN(cur_state
!= state
,
1147 "DSI PLL state assertion failure (expected %s, current %s)\n",
1148 state_string(state
), state_string(cur_state
));
1150 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1151 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1153 struct intel_shared_dpll
*
1154 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1156 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1158 if (crtc
->config
->shared_dpll
< 0)
1161 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1165 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1166 struct intel_shared_dpll
*pll
,
1170 struct intel_dpll_hw_state hw_state
;
1173 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1176 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1177 I915_STATE_WARN(cur_state
!= state
,
1178 "%s assertion failure (expected %s, current %s)\n",
1179 pll
->name
, state_string(state
), state_string(cur_state
));
1182 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1183 enum pipe pipe
, bool state
)
1188 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1191 if (HAS_DDI(dev_priv
->dev
)) {
1192 /* DDI does not have a specific FDI_TX register */
1193 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1194 val
= I915_READ(reg
);
1195 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1197 reg
= FDI_TX_CTL(pipe
);
1198 val
= I915_READ(reg
);
1199 cur_state
= !!(val
& FDI_TX_ENABLE
);
1201 I915_STATE_WARN(cur_state
!= state
,
1202 "FDI TX state assertion failure (expected %s, current %s)\n",
1203 state_string(state
), state_string(cur_state
));
1205 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1206 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1208 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1209 enum pipe pipe
, bool state
)
1215 reg
= FDI_RX_CTL(pipe
);
1216 val
= I915_READ(reg
);
1217 cur_state
= !!(val
& FDI_RX_ENABLE
);
1218 I915_STATE_WARN(cur_state
!= state
,
1219 "FDI RX state assertion failure (expected %s, current %s)\n",
1220 state_string(state
), state_string(cur_state
));
1222 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1223 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1225 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1231 /* ILK FDI PLL is always enabled */
1232 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1235 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1236 if (HAS_DDI(dev_priv
->dev
))
1239 reg
= FDI_TX_CTL(pipe
);
1240 val
= I915_READ(reg
);
1241 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1244 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1245 enum pipe pipe
, bool state
)
1251 reg
= FDI_RX_CTL(pipe
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1254 I915_STATE_WARN(cur_state
!= state
,
1255 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1256 state_string(state
), state_string(cur_state
));
1259 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1262 struct drm_device
*dev
= dev_priv
->dev
;
1265 enum pipe panel_pipe
= PIPE_A
;
1268 if (WARN_ON(HAS_DDI(dev
)))
1271 if (HAS_PCH_SPLIT(dev
)) {
1274 pp_reg
= PCH_PP_CONTROL
;
1275 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1277 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1278 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1279 panel_pipe
= PIPE_B
;
1280 /* XXX: else fix for eDP */
1281 } else if (IS_VALLEYVIEW(dev
)) {
1282 /* presumably write lock depends on pipe, not port select */
1283 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1286 pp_reg
= PP_CONTROL
;
1287 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1288 panel_pipe
= PIPE_B
;
1291 val
= I915_READ(pp_reg
);
1292 if (!(val
& PANEL_POWER_ON
) ||
1293 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1296 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1297 "panel assertion failure, pipe %c regs locked\n",
1301 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1302 enum pipe pipe
, bool state
)
1304 struct drm_device
*dev
= dev_priv
->dev
;
1307 if (IS_845G(dev
) || IS_I865G(dev
))
1308 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1310 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1312 I915_STATE_WARN(cur_state
!= state
,
1313 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1314 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1316 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1317 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1319 void assert_pipe(struct drm_i915_private
*dev_priv
,
1320 enum pipe pipe
, bool state
)
1325 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1328 /* if we need the pipe quirk it must be always on */
1329 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1330 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1333 if (!intel_display_power_is_enabled(dev_priv
,
1334 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1337 reg
= PIPECONF(cpu_transcoder
);
1338 val
= I915_READ(reg
);
1339 cur_state
= !!(val
& PIPECONF_ENABLE
);
1342 I915_STATE_WARN(cur_state
!= state
,
1343 "pipe %c assertion failure (expected %s, current %s)\n",
1344 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1347 static void assert_plane(struct drm_i915_private
*dev_priv
,
1348 enum plane plane
, bool state
)
1354 reg
= DSPCNTR(plane
);
1355 val
= I915_READ(reg
);
1356 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1357 I915_STATE_WARN(cur_state
!= state
,
1358 "plane %c assertion failure (expected %s, current %s)\n",
1359 plane_name(plane
), state_string(state
), state_string(cur_state
));
1362 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1363 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1365 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1368 struct drm_device
*dev
= dev_priv
->dev
;
1373 /* Primary planes are fixed to pipes on gen4+ */
1374 if (INTEL_INFO(dev
)->gen
>= 4) {
1375 reg
= DSPCNTR(pipe
);
1376 val
= I915_READ(reg
);
1377 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1378 "plane %c assertion failure, should be disabled but not\n",
1383 /* Need to check both planes against the pipe */
1384 for_each_pipe(dev_priv
, i
) {
1386 val
= I915_READ(reg
);
1387 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1388 DISPPLANE_SEL_PIPE_SHIFT
;
1389 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1390 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1391 plane_name(i
), pipe_name(pipe
));
1395 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1398 struct drm_device
*dev
= dev_priv
->dev
;
1402 if (INTEL_INFO(dev
)->gen
>= 9) {
1403 for_each_sprite(dev_priv
, pipe
, sprite
) {
1404 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1405 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1406 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1407 sprite
, pipe_name(pipe
));
1409 } else if (IS_VALLEYVIEW(dev
)) {
1410 for_each_sprite(dev_priv
, pipe
, sprite
) {
1411 reg
= SPCNTR(pipe
, sprite
);
1412 val
= I915_READ(reg
);
1413 I915_STATE_WARN(val
& SP_ENABLE
,
1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1417 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1419 val
= I915_READ(reg
);
1420 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 plane_name(pipe
), pipe_name(pipe
));
1423 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1424 reg
= DVSCNTR(pipe
);
1425 val
= I915_READ(reg
);
1426 I915_STATE_WARN(val
& DVS_ENABLE
,
1427 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1428 plane_name(pipe
), pipe_name(pipe
));
1432 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1434 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1435 drm_crtc_vblank_put(crtc
);
1438 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1443 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1445 val
= I915_READ(PCH_DREF_CONTROL
);
1446 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1447 DREF_SUPERSPREAD_SOURCE_MASK
));
1448 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1451 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1458 reg
= PCH_TRANSCONF(pipe
);
1459 val
= I915_READ(reg
);
1460 enabled
= !!(val
& TRANS_ENABLE
);
1461 I915_STATE_WARN(enabled
,
1462 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1467 enum pipe pipe
, u32 port_sel
, u32 val
)
1469 if ((val
& DP_PORT_EN
) == 0)
1472 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1473 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1474 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1475 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1477 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1478 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1481 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1487 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1488 enum pipe pipe
, u32 val
)
1490 if ((val
& SDVO_ENABLE
) == 0)
1493 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1494 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1496 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1497 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1500 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1506 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1507 enum pipe pipe
, u32 val
)
1509 if ((val
& LVDS_PORT_EN
) == 0)
1512 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1513 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1516 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1522 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1523 enum pipe pipe
, u32 val
)
1525 if ((val
& ADPA_DAC_ENABLE
) == 0)
1527 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1528 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1531 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1537 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1538 enum pipe pipe
, int reg
, u32 port_sel
)
1540 u32 val
= I915_READ(reg
);
1541 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1542 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1543 reg
, pipe_name(pipe
));
1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1546 && (val
& DP_PIPEB_SELECT
),
1547 "IBX PCH dp port still using transcoder B\n");
1550 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1551 enum pipe pipe
, int reg
)
1553 u32 val
= I915_READ(reg
);
1554 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1555 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1556 reg
, pipe_name(pipe
));
1558 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1559 && (val
& SDVO_PIPE_B_SELECT
),
1560 "IBX PCH hdmi port still using transcoder B\n");
1563 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1569 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1570 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1571 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1574 val
= I915_READ(reg
);
1575 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1576 "PCH VGA enabled on transcoder %c, should be disabled\n",
1580 val
= I915_READ(reg
);
1581 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1582 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1585 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1586 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1587 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1590 static void intel_init_dpio(struct drm_device
*dev
)
1592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1594 if (!IS_VALLEYVIEW(dev
))
1598 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1599 * CHV x1 PHY (DP/HDMI D)
1600 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1602 if (IS_CHERRYVIEW(dev
)) {
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1610 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1611 const struct intel_crtc_state
*pipe_config
)
1613 struct drm_device
*dev
= crtc
->base
.dev
;
1614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1615 int reg
= DPLL(crtc
->pipe
);
1616 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1618 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1620 /* No really, not for ILK+ */
1621 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1623 /* PLL is protected by panel, make sure we can write it */
1624 if (IS_MOBILE(dev_priv
->dev
))
1625 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1627 I915_WRITE(reg
, dpll
);
1631 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1632 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1634 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1635 POSTING_READ(DPLL_MD(crtc
->pipe
));
1637 /* We do this three times for luck */
1638 I915_WRITE(reg
, dpll
);
1640 udelay(150); /* wait for warmup */
1641 I915_WRITE(reg
, dpll
);
1643 udelay(150); /* wait for warmup */
1644 I915_WRITE(reg
, dpll
);
1646 udelay(150); /* wait for warmup */
1649 static void chv_enable_pll(struct intel_crtc
*crtc
,
1650 const struct intel_crtc_state
*pipe_config
)
1652 struct drm_device
*dev
= crtc
->base
.dev
;
1653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1654 int pipe
= crtc
->pipe
;
1655 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1658 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1660 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1662 mutex_lock(&dev_priv
->dpio_lock
);
1664 /* Enable back the 10bit clock to display controller */
1665 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1666 tmp
|= DPIO_DCLKP_EN
;
1667 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1670 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1677 /* Check PLL is locked */
1678 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1679 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1681 /* not sure when this should be written */
1682 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1683 POSTING_READ(DPLL_MD(pipe
));
1685 mutex_unlock(&dev_priv
->dpio_lock
);
1688 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1690 struct intel_crtc
*crtc
;
1693 for_each_intel_crtc(dev
, crtc
)
1694 count
+= crtc
->active
&&
1695 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1700 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1702 struct drm_device
*dev
= crtc
->base
.dev
;
1703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1704 int reg
= DPLL(crtc
->pipe
);
1705 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1707 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1709 /* No really, not for ILK+ */
1710 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1712 /* PLL is protected by panel, make sure we can write it */
1713 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1714 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1716 /* Enable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1719 * It appears to be important that we don't enable this
1720 * for the current pipe before otherwise configuring the
1721 * PLL. No idea how this should be handled if multiple
1722 * DVO outputs are enabled simultaneosly.
1724 dpll
|= DPLL_DVO_2X_MODE
;
1725 I915_WRITE(DPLL(!crtc
->pipe
),
1726 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1729 /* Wait for the clocks to stabilize. */
1733 if (INTEL_INFO(dev
)->gen
>= 4) {
1734 I915_WRITE(DPLL_MD(crtc
->pipe
),
1735 crtc
->config
->dpll_hw_state
.dpll_md
);
1737 /* The pixel multiplier can only be updated once the
1738 * DPLL is enabled and the clocks are stable.
1740 * So write it again.
1742 I915_WRITE(reg
, dpll
);
1745 /* We do this three times for luck */
1746 I915_WRITE(reg
, dpll
);
1748 udelay(150); /* wait for warmup */
1749 I915_WRITE(reg
, dpll
);
1751 udelay(150); /* wait for warmup */
1752 I915_WRITE(reg
, dpll
);
1754 udelay(150); /* wait for warmup */
1758 * i9xx_disable_pll - disable a PLL
1759 * @dev_priv: i915 private structure
1760 * @pipe: pipe PLL to disable
1762 * Disable the PLL for @pipe, making sure the pipe is off first.
1764 * Note! This is for pre-ILK only.
1766 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1768 struct drm_device
*dev
= crtc
->base
.dev
;
1769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1770 enum pipe pipe
= crtc
->pipe
;
1772 /* Disable DVO 2x clock on both PLLs if necessary */
1774 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1775 intel_num_dvo_pipes(dev
) == 1) {
1776 I915_WRITE(DPLL(PIPE_B
),
1777 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1778 I915_WRITE(DPLL(PIPE_A
),
1779 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1782 /* Don't disable pipe or pipe PLLs if needed */
1783 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1784 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1787 /* Make sure the pipe isn't still relying on us */
1788 assert_pipe_disabled(dev_priv
, pipe
);
1790 I915_WRITE(DPLL(pipe
), 0);
1791 POSTING_READ(DPLL(pipe
));
1794 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1798 /* Make sure the pipe isn't still relying on us */
1799 assert_pipe_disabled(dev_priv
, pipe
);
1802 * Leave integrated clock source and reference clock enabled for pipe B.
1803 * The latter is needed for VGA hotplug / manual detection.
1806 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1807 I915_WRITE(DPLL(pipe
), val
);
1808 POSTING_READ(DPLL(pipe
));
1812 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1814 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1817 /* Make sure the pipe isn't still relying on us */
1818 assert_pipe_disabled(dev_priv
, pipe
);
1820 /* Set PLL en = 0 */
1821 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1823 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1824 I915_WRITE(DPLL(pipe
), val
);
1825 POSTING_READ(DPLL(pipe
));
1827 mutex_lock(&dev_priv
->dpio_lock
);
1829 /* Disable 10bit clock to display controller */
1830 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1831 val
&= ~DPIO_DCLKP_EN
;
1832 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1834 /* disable left/right clock distribution */
1835 if (pipe
!= PIPE_B
) {
1836 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1837 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1838 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1840 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1841 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1842 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1845 mutex_unlock(&dev_priv
->dpio_lock
);
1848 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1849 struct intel_digital_port
*dport
)
1854 switch (dport
->port
) {
1856 port_mask
= DPLL_PORTB_READY_MASK
;
1860 port_mask
= DPLL_PORTC_READY_MASK
;
1864 port_mask
= DPLL_PORTD_READY_MASK
;
1865 dpll_reg
= DPIO_PHY_STATUS
;
1871 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1872 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1873 port_name(dport
->port
), I915_READ(dpll_reg
));
1876 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1878 struct drm_device
*dev
= crtc
->base
.dev
;
1879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1880 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1882 if (WARN_ON(pll
== NULL
))
1885 WARN_ON(!pll
->config
.crtc_mask
);
1886 if (pll
->active
== 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1889 assert_shared_dpll_disabled(dev_priv
, pll
);
1891 pll
->mode_set(dev_priv
, pll
);
1896 * intel_enable_shared_dpll - enable PCH PLL
1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1903 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1905 struct drm_device
*dev
= crtc
->base
.dev
;
1906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1907 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1909 if (WARN_ON(pll
== NULL
))
1912 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1916 pll
->name
, pll
->active
, pll
->on
,
1917 crtc
->base
.base
.id
);
1919 if (pll
->active
++) {
1921 assert_shared_dpll_enabled(dev_priv
, pll
);
1926 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1928 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1929 pll
->enable(dev_priv
, pll
);
1933 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1935 struct drm_device
*dev
= crtc
->base
.dev
;
1936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1937 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1939 /* PCH only available on ILK+ */
1940 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1941 if (WARN_ON(pll
== NULL
))
1944 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll
->name
, pll
->active
, pll
->on
,
1949 crtc
->base
.base
.id
);
1951 if (WARN_ON(pll
->active
== 0)) {
1952 assert_shared_dpll_disabled(dev_priv
, pll
);
1956 assert_shared_dpll_enabled(dev_priv
, pll
);
1961 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1962 pll
->disable(dev_priv
, pll
);
1965 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1968 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1971 struct drm_device
*dev
= dev_priv
->dev
;
1972 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1973 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1974 uint32_t reg
, val
, pipeconf_val
;
1976 /* PCH only available on ILK+ */
1977 BUG_ON(!HAS_PCH_SPLIT(dev
));
1979 /* Make sure PCH DPLL is enabled */
1980 assert_shared_dpll_enabled(dev_priv
,
1981 intel_crtc_to_shared_dpll(intel_crtc
));
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv
, pipe
);
1985 assert_fdi_rx_enabled(dev_priv
, pipe
);
1987 if (HAS_PCH_CPT(dev
)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg
= TRANS_CHICKEN2(pipe
);
1991 val
= I915_READ(reg
);
1992 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1993 I915_WRITE(reg
, val
);
1996 reg
= PCH_TRANSCONF(pipe
);
1997 val
= I915_READ(reg
);
1998 pipeconf_val
= I915_READ(PIPECONF(pipe
));
2000 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2005 val
&= ~PIPECONF_BPC_MASK
;
2006 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2009 val
&= ~TRANS_INTERLACE_MASK
;
2010 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2011 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2012 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2013 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2015 val
|= TRANS_INTERLACED
;
2017 val
|= TRANS_PROGRESSIVE
;
2019 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2020 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2024 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2025 enum transcoder cpu_transcoder
)
2027 u32 val
, pipeconf_val
;
2029 /* PCH only available on ILK+ */
2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2032 /* FDI must be feeding us bits for PCH ports */
2033 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2034 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2036 /* Workaround: set timing override bit. */
2037 val
= I915_READ(_TRANSA_CHICKEN2
);
2038 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2039 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2042 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2044 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2045 PIPECONF_INTERLACED_ILK
)
2046 val
|= TRANS_INTERLACED
;
2048 val
|= TRANS_PROGRESSIVE
;
2050 I915_WRITE(LPT_TRANSCONF
, val
);
2051 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2052 DRM_ERROR("Failed to enable PCH transcoder\n");
2055 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2058 struct drm_device
*dev
= dev_priv
->dev
;
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv
, pipe
);
2063 assert_fdi_rx_disabled(dev_priv
, pipe
);
2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv
, pipe
);
2068 reg
= PCH_TRANSCONF(pipe
);
2069 val
= I915_READ(reg
);
2070 val
&= ~TRANS_ENABLE
;
2071 I915_WRITE(reg
, val
);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2076 if (!HAS_PCH_IBX(dev
)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg
= TRANS_CHICKEN2(pipe
);
2079 val
= I915_READ(reg
);
2080 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2081 I915_WRITE(reg
, val
);
2085 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2089 val
= I915_READ(LPT_TRANSCONF
);
2090 val
&= ~TRANS_ENABLE
;
2091 I915_WRITE(LPT_TRANSCONF
, val
);
2092 /* wait for PCH transcoder off, transcoder state */
2093 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2094 DRM_ERROR("Failed to disable PCH transcoder\n");
2096 /* Workaround: clear timing override bit. */
2097 val
= I915_READ(_TRANSA_CHICKEN2
);
2098 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2099 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2103 * intel_enable_pipe - enable a pipe, asserting requirements
2104 * @crtc: crtc responsible for the pipe
2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2109 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2111 struct drm_device
*dev
= crtc
->base
.dev
;
2112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2113 enum pipe pipe
= crtc
->pipe
;
2114 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2116 enum pipe pch_transcoder
;
2120 assert_planes_disabled(dev_priv
, pipe
);
2121 assert_cursor_disabled(dev_priv
, pipe
);
2122 assert_sprites_disabled(dev_priv
, pipe
);
2124 if (HAS_PCH_LPT(dev_priv
->dev
))
2125 pch_transcoder
= TRANSCODER_A
;
2127 pch_transcoder
= pipe
;
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2134 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2135 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2136 assert_dsi_pll_enabled(dev_priv
);
2138 assert_pll_enabled(dev_priv
, pipe
);
2140 if (crtc
->config
->has_pch_encoder
) {
2141 /* if driving the PCH, we need FDI enabled */
2142 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2143 assert_fdi_tx_pll_enabled(dev_priv
,
2144 (enum pipe
) cpu_transcoder
);
2146 /* FIXME: assert CPU port conditions for SNB+ */
2149 reg
= PIPECONF(cpu_transcoder
);
2150 val
= I915_READ(reg
);
2151 if (val
& PIPECONF_ENABLE
) {
2152 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2153 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2157 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2169 * Will wait until the pipe has shut down before returning.
2171 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2173 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2174 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2175 enum pipe pipe
= crtc
->pipe
;
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2183 assert_planes_disabled(dev_priv
, pipe
);
2184 assert_cursor_disabled(dev_priv
, pipe
);
2185 assert_sprites_disabled(dev_priv
, pipe
);
2187 reg
= PIPECONF(cpu_transcoder
);
2188 val
= I915_READ(reg
);
2189 if ((val
& PIPECONF_ENABLE
) == 0)
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2196 if (crtc
->config
->double_wide
)
2197 val
&= ~PIPECONF_DOUBLE_WIDE
;
2199 /* Don't disable pipe or pipe PLLs if needed */
2200 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2201 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2202 val
&= ~PIPECONF_ENABLE
;
2204 I915_WRITE(reg
, val
);
2205 if ((val
& PIPECONF_ENABLE
) == 0)
2206 intel_wait_for_pipe_off(crtc
);
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2213 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2216 struct drm_device
*dev
= dev_priv
->dev
;
2217 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2219 I915_WRITE(reg
, I915_READ(reg
));
2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
2228 * Enable @plane on @crtc, making sure that the pipe is running first.
2230 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2231 struct drm_crtc
*crtc
)
2233 struct drm_device
*dev
= plane
->dev
;
2234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2235 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2238 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2240 if (intel_crtc
->primary_enabled
)
2243 intel_crtc
->primary_enabled
= true;
2245 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2249 * BDW signals flip done immediately if the plane
2250 * is disabled, even if the plane enable is already
2251 * armed to occur at the next vblank :(
2253 if (IS_BROADWELL(dev
))
2254 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2258 * intel_disable_primary_hw_plane - disable the primary hardware plane
2259 * @plane: plane to be disabled
2260 * @crtc: crtc for the plane
2262 * Disable @plane on @crtc, making sure that the pipe is running first.
2264 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2265 struct drm_crtc
*crtc
)
2267 struct drm_device
*dev
= plane
->dev
;
2268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2269 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2271 if (WARN_ON(!intel_crtc
->active
))
2274 if (!intel_crtc
->primary_enabled
)
2277 intel_crtc
->primary_enabled
= false;
2279 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2283 static bool need_vtd_wa(struct drm_device
*dev
)
2285 #ifdef CONFIG_INTEL_IOMMU
2286 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2293 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2294 uint64_t fb_format_modifier
)
2296 unsigned int tile_height
;
2297 uint32_t pixel_bytes
;
2299 switch (fb_format_modifier
) {
2300 case DRM_FORMAT_MOD_NONE
:
2303 case I915_FORMAT_MOD_X_TILED
:
2304 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2306 case I915_FORMAT_MOD_Y_TILED
:
2309 case I915_FORMAT_MOD_Yf_TILED
:
2310 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2311 switch (pixel_bytes
) {
2325 "128-bit pixels are not supported for display!");
2331 MISSING_CASE(fb_format_modifier
);
2340 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2341 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2343 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2344 fb_format_modifier
));
2348 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2349 const struct drm_plane_state
*plane_state
)
2351 struct intel_rotation_info
*info
= &view
->rotation_info
;
2353 *view
= i915_ggtt_view_normal
;
2358 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2361 *view
= i915_ggtt_view_rotated
;
2363 info
->height
= fb
->height
;
2364 info
->pixel_format
= fb
->pixel_format
;
2365 info
->pitch
= fb
->pitches
[0];
2366 info
->fb_modifier
= fb
->modifier
[0];
2372 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2373 struct drm_framebuffer
*fb
,
2374 const struct drm_plane_state
*plane_state
,
2375 struct intel_engine_cs
*pipelined
)
2377 struct drm_device
*dev
= fb
->dev
;
2378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2379 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2380 struct i915_ggtt_view view
;
2384 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2386 switch (fb
->modifier
[0]) {
2387 case DRM_FORMAT_MOD_NONE
:
2388 if (INTEL_INFO(dev
)->gen
>= 9)
2389 alignment
= 256 * 1024;
2390 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2391 alignment
= 128 * 1024;
2392 else if (INTEL_INFO(dev
)->gen
>= 4)
2393 alignment
= 4 * 1024;
2395 alignment
= 64 * 1024;
2397 case I915_FORMAT_MOD_X_TILED
:
2398 if (INTEL_INFO(dev
)->gen
>= 9)
2399 alignment
= 256 * 1024;
2401 /* pin() will align the object as required by fence */
2405 case I915_FORMAT_MOD_Y_TILED
:
2406 case I915_FORMAT_MOD_Yf_TILED
:
2407 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2408 "Y tiling bo slipped through, driver bug!\n"))
2410 alignment
= 1 * 1024 * 1024;
2413 MISSING_CASE(fb
->modifier
[0]);
2417 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2421 /* Note that the w/a also requires 64 PTE of padding following the
2422 * bo. We currently fill all unused PTE with the shadow page and so
2423 * we should always have valid PTE following the scanout preventing
2426 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2427 alignment
= 256 * 1024;
2430 * Global gtt pte registers are special registers which actually forward
2431 * writes to a chunk of system memory. Which means that there is no risk
2432 * that the register values disappear as soon as we call
2433 * intel_runtime_pm_put(), so it is correct to wrap only the
2434 * pin/unpin/fence and not more.
2436 intel_runtime_pm_get(dev_priv
);
2438 dev_priv
->mm
.interruptible
= false;
2439 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2442 goto err_interruptible
;
2444 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2445 * fence, whereas 965+ only requires a fence if using
2446 * framebuffer compression. For simplicity, we always install
2447 * a fence as the cost is not that onerous.
2449 ret
= i915_gem_object_get_fence(obj
);
2453 i915_gem_object_pin_fence(obj
);
2455 dev_priv
->mm
.interruptible
= true;
2456 intel_runtime_pm_put(dev_priv
);
2460 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2462 dev_priv
->mm
.interruptible
= true;
2463 intel_runtime_pm_put(dev_priv
);
2467 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2468 const struct drm_plane_state
*plane_state
)
2470 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2471 struct i915_ggtt_view view
;
2474 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2476 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2477 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2479 i915_gem_object_unpin_fence(obj
);
2480 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2483 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2484 * is assumed to be a power-of-two. */
2485 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2486 unsigned int tiling_mode
,
2490 if (tiling_mode
!= I915_TILING_NONE
) {
2491 unsigned int tile_rows
, tiles
;
2496 tiles
= *x
/ (512/cpp
);
2499 return tile_rows
* pitch
* 8 + tiles
* 4096;
2501 unsigned int offset
;
2503 offset
= *y
* pitch
+ *x
* cpp
;
2505 *x
= (offset
& 4095) / cpp
;
2506 return offset
& -4096;
2510 static int i9xx_format_to_fourcc(int format
)
2513 case DISPPLANE_8BPP
:
2514 return DRM_FORMAT_C8
;
2515 case DISPPLANE_BGRX555
:
2516 return DRM_FORMAT_XRGB1555
;
2517 case DISPPLANE_BGRX565
:
2518 return DRM_FORMAT_RGB565
;
2520 case DISPPLANE_BGRX888
:
2521 return DRM_FORMAT_XRGB8888
;
2522 case DISPPLANE_RGBX888
:
2523 return DRM_FORMAT_XBGR8888
;
2524 case DISPPLANE_BGRX101010
:
2525 return DRM_FORMAT_XRGB2101010
;
2526 case DISPPLANE_RGBX101010
:
2527 return DRM_FORMAT_XBGR2101010
;
2531 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2534 case PLANE_CTL_FORMAT_RGB_565
:
2535 return DRM_FORMAT_RGB565
;
2537 case PLANE_CTL_FORMAT_XRGB_8888
:
2540 return DRM_FORMAT_ABGR8888
;
2542 return DRM_FORMAT_XBGR8888
;
2545 return DRM_FORMAT_ARGB8888
;
2547 return DRM_FORMAT_XRGB8888
;
2549 case PLANE_CTL_FORMAT_XRGB_2101010
:
2551 return DRM_FORMAT_XBGR2101010
;
2553 return DRM_FORMAT_XRGB2101010
;
2558 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2559 struct intel_initial_plane_config
*plane_config
)
2561 struct drm_device
*dev
= crtc
->base
.dev
;
2562 struct drm_i915_gem_object
*obj
= NULL
;
2563 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2564 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2565 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2566 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2569 size_aligned
-= base_aligned
;
2571 if (plane_config
->size
== 0)
2574 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2581 obj
->tiling_mode
= plane_config
->tiling
;
2582 if (obj
->tiling_mode
== I915_TILING_X
)
2583 obj
->stride
= fb
->pitches
[0];
2585 mode_cmd
.pixel_format
= fb
->pixel_format
;
2586 mode_cmd
.width
= fb
->width
;
2587 mode_cmd
.height
= fb
->height
;
2588 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2589 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2590 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2592 mutex_lock(&dev
->struct_mutex
);
2593 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2595 DRM_DEBUG_KMS("intel fb init failed\n");
2598 mutex_unlock(&dev
->struct_mutex
);
2600 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2604 drm_gem_object_unreference(&obj
->base
);
2605 mutex_unlock(&dev
->struct_mutex
);
2609 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2611 update_state_fb(struct drm_plane
*plane
)
2613 if (plane
->fb
== plane
->state
->fb
)
2616 if (plane
->state
->fb
)
2617 drm_framebuffer_unreference(plane
->state
->fb
);
2618 plane
->state
->fb
= plane
->fb
;
2619 if (plane
->state
->fb
)
2620 drm_framebuffer_reference(plane
->state
->fb
);
2624 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2625 struct intel_initial_plane_config
*plane_config
)
2627 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2630 struct intel_crtc
*i
;
2631 struct drm_i915_gem_object
*obj
;
2632 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2633 struct drm_framebuffer
*fb
;
2635 if (!plane_config
->fb
)
2638 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2639 fb
= &plane_config
->fb
->base
;
2643 kfree(plane_config
->fb
);
2646 * Failed to alloc the obj, check to see if we should share
2647 * an fb with another CRTC instead
2649 for_each_crtc(dev
, c
) {
2650 i
= to_intel_crtc(c
);
2652 if (c
== &intel_crtc
->base
)
2658 fb
= c
->primary
->fb
;
2662 obj
= intel_fb_obj(fb
);
2663 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2664 drm_framebuffer_reference(fb
);
2672 obj
= intel_fb_obj(fb
);
2673 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2674 dev_priv
->preserve_bios_swizzle
= true;
2677 primary
->state
->crtc
= &intel_crtc
->base
;
2678 primary
->crtc
= &intel_crtc
->base
;
2679 update_state_fb(primary
);
2680 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2683 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2684 struct drm_framebuffer
*fb
,
2687 struct drm_device
*dev
= crtc
->dev
;
2688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2689 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2690 struct drm_i915_gem_object
*obj
;
2691 int plane
= intel_crtc
->plane
;
2692 unsigned long linear_offset
;
2694 u32 reg
= DSPCNTR(plane
);
2697 if (!intel_crtc
->primary_enabled
) {
2699 if (INTEL_INFO(dev
)->gen
>= 4)
2700 I915_WRITE(DSPSURF(plane
), 0);
2702 I915_WRITE(DSPADDR(plane
), 0);
2707 obj
= intel_fb_obj(fb
);
2708 if (WARN_ON(obj
== NULL
))
2711 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2713 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2715 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2717 if (INTEL_INFO(dev
)->gen
< 4) {
2718 if (intel_crtc
->pipe
== PIPE_B
)
2719 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2721 /* pipesrc and dspsize control the size that is scaled from,
2722 * which should always be the user's requested size.
2724 I915_WRITE(DSPSIZE(plane
),
2725 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2726 (intel_crtc
->config
->pipe_src_w
- 1));
2727 I915_WRITE(DSPPOS(plane
), 0);
2728 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2729 I915_WRITE(PRIMSIZE(plane
),
2730 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2731 (intel_crtc
->config
->pipe_src_w
- 1));
2732 I915_WRITE(PRIMPOS(plane
), 0);
2733 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2736 switch (fb
->pixel_format
) {
2738 dspcntr
|= DISPPLANE_8BPP
;
2740 case DRM_FORMAT_XRGB1555
:
2741 case DRM_FORMAT_ARGB1555
:
2742 dspcntr
|= DISPPLANE_BGRX555
;
2744 case DRM_FORMAT_RGB565
:
2745 dspcntr
|= DISPPLANE_BGRX565
;
2747 case DRM_FORMAT_XRGB8888
:
2748 case DRM_FORMAT_ARGB8888
:
2749 dspcntr
|= DISPPLANE_BGRX888
;
2751 case DRM_FORMAT_XBGR8888
:
2752 case DRM_FORMAT_ABGR8888
:
2753 dspcntr
|= DISPPLANE_RGBX888
;
2755 case DRM_FORMAT_XRGB2101010
:
2756 case DRM_FORMAT_ARGB2101010
:
2757 dspcntr
|= DISPPLANE_BGRX101010
;
2759 case DRM_FORMAT_XBGR2101010
:
2760 case DRM_FORMAT_ABGR2101010
:
2761 dspcntr
|= DISPPLANE_RGBX101010
;
2767 if (INTEL_INFO(dev
)->gen
>= 4 &&
2768 obj
->tiling_mode
!= I915_TILING_NONE
)
2769 dspcntr
|= DISPPLANE_TILED
;
2772 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2774 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2776 if (INTEL_INFO(dev
)->gen
>= 4) {
2777 intel_crtc
->dspaddr_offset
=
2778 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2781 linear_offset
-= intel_crtc
->dspaddr_offset
;
2783 intel_crtc
->dspaddr_offset
= linear_offset
;
2786 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2787 dspcntr
|= DISPPLANE_ROTATE_180
;
2789 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2790 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2792 /* Finding the last pixel of the last line of the display
2793 data and adding to linear_offset*/
2795 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2796 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2799 I915_WRITE(reg
, dspcntr
);
2801 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2802 if (INTEL_INFO(dev
)->gen
>= 4) {
2803 I915_WRITE(DSPSURF(plane
),
2804 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2805 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2806 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2808 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2812 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2813 struct drm_framebuffer
*fb
,
2816 struct drm_device
*dev
= crtc
->dev
;
2817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2818 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2819 struct drm_i915_gem_object
*obj
;
2820 int plane
= intel_crtc
->plane
;
2821 unsigned long linear_offset
;
2823 u32 reg
= DSPCNTR(plane
);
2826 if (!intel_crtc
->primary_enabled
) {
2828 I915_WRITE(DSPSURF(plane
), 0);
2833 obj
= intel_fb_obj(fb
);
2834 if (WARN_ON(obj
== NULL
))
2837 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2839 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2841 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2843 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2844 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2846 switch (fb
->pixel_format
) {
2848 dspcntr
|= DISPPLANE_8BPP
;
2850 case DRM_FORMAT_RGB565
:
2851 dspcntr
|= DISPPLANE_BGRX565
;
2853 case DRM_FORMAT_XRGB8888
:
2854 case DRM_FORMAT_ARGB8888
:
2855 dspcntr
|= DISPPLANE_BGRX888
;
2857 case DRM_FORMAT_XBGR8888
:
2858 case DRM_FORMAT_ABGR8888
:
2859 dspcntr
|= DISPPLANE_RGBX888
;
2861 case DRM_FORMAT_XRGB2101010
:
2862 case DRM_FORMAT_ARGB2101010
:
2863 dspcntr
|= DISPPLANE_BGRX101010
;
2865 case DRM_FORMAT_XBGR2101010
:
2866 case DRM_FORMAT_ABGR2101010
:
2867 dspcntr
|= DISPPLANE_RGBX101010
;
2873 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2874 dspcntr
|= DISPPLANE_TILED
;
2876 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2877 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2879 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2880 intel_crtc
->dspaddr_offset
=
2881 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2884 linear_offset
-= intel_crtc
->dspaddr_offset
;
2885 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2886 dspcntr
|= DISPPLANE_ROTATE_180
;
2888 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2889 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2890 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2892 /* Finding the last pixel of the last line of the display
2893 data and adding to linear_offset*/
2895 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2896 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2900 I915_WRITE(reg
, dspcntr
);
2902 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2903 I915_WRITE(DSPSURF(plane
),
2904 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2905 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2906 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2908 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2909 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2914 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2915 uint32_t pixel_format
)
2917 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2920 * The stride is either expressed as a multiple of 64 bytes
2921 * chunks for linear buffers or in number of tiles for tiled
2924 switch (fb_modifier
) {
2925 case DRM_FORMAT_MOD_NONE
:
2927 case I915_FORMAT_MOD_X_TILED
:
2928 if (INTEL_INFO(dev
)->gen
== 2)
2931 case I915_FORMAT_MOD_Y_TILED
:
2932 /* No need to check for old gens and Y tiling since this is
2933 * about the display engine and those will be blocked before
2937 case I915_FORMAT_MOD_Yf_TILED
:
2938 if (bits_per_pixel
== 8)
2943 MISSING_CASE(fb_modifier
);
2948 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2949 struct drm_i915_gem_object
*obj
)
2951 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2953 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2954 view
= &i915_ggtt_view_rotated
;
2956 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2960 * This function detaches (aka. unbinds) unused scalers in hardware
2962 void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2964 struct drm_device
*dev
;
2965 struct drm_i915_private
*dev_priv
;
2966 struct intel_crtc_scaler_state
*scaler_state
;
2969 if (!intel_crtc
|| !intel_crtc
->config
)
2972 dev
= intel_crtc
->base
.dev
;
2973 dev_priv
= dev
->dev_private
;
2974 scaler_state
= &intel_crtc
->config
->scaler_state
;
2976 /* loop through and disable scalers that aren't in use */
2977 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2978 if (!scaler_state
->scalers
[i
].in_use
) {
2979 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, i
), 0);
2980 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, i
), 0);
2981 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, i
), 0);
2982 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2983 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, i
);
2988 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2990 u32 plane_ctl_format
= 0;
2991 switch (pixel_format
) {
2992 case DRM_FORMAT_RGB565
:
2993 plane_ctl_format
= PLANE_CTL_FORMAT_RGB_565
;
2995 case DRM_FORMAT_XBGR8888
:
2996 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2998 case DRM_FORMAT_XRGB8888
:
2999 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
;
3002 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3003 * to be already pre-multiplied. We need to add a knob (or a different
3004 * DRM_FORMAT) for user-space to configure that.
3006 case DRM_FORMAT_ABGR8888
:
3007 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
3008 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3010 case DRM_FORMAT_ARGB8888
:
3011 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
|
3012 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3014 case DRM_FORMAT_XRGB2101010
:
3015 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_2101010
;
3017 case DRM_FORMAT_XBGR2101010
:
3018 plane_ctl_format
= PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3020 case DRM_FORMAT_YUYV
:
3021 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3023 case DRM_FORMAT_YVYU
:
3024 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3026 case DRM_FORMAT_UYVY
:
3027 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3029 case DRM_FORMAT_VYUY
:
3030 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3035 return plane_ctl_format
;
3038 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3040 u32 plane_ctl_tiling
= 0;
3041 switch (fb_modifier
) {
3042 case DRM_FORMAT_MOD_NONE
:
3044 case I915_FORMAT_MOD_X_TILED
:
3045 plane_ctl_tiling
= PLANE_CTL_TILED_X
;
3047 case I915_FORMAT_MOD_Y_TILED
:
3048 plane_ctl_tiling
= PLANE_CTL_TILED_Y
;
3050 case I915_FORMAT_MOD_Yf_TILED
:
3051 plane_ctl_tiling
= PLANE_CTL_TILED_YF
;
3054 MISSING_CASE(fb_modifier
);
3056 return plane_ctl_tiling
;
3059 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3061 u32 plane_ctl_rotation
= 0;
3063 case BIT(DRM_ROTATE_0
):
3065 case BIT(DRM_ROTATE_90
):
3066 plane_ctl_rotation
= PLANE_CTL_ROTATE_90
;
3068 case BIT(DRM_ROTATE_180
):
3069 plane_ctl_rotation
= PLANE_CTL_ROTATE_180
;
3071 case BIT(DRM_ROTATE_270
):
3072 plane_ctl_rotation
= PLANE_CTL_ROTATE_270
;
3075 MISSING_CASE(rotation
);
3078 return plane_ctl_rotation
;
3081 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3082 struct drm_framebuffer
*fb
,
3085 struct drm_device
*dev
= crtc
->dev
;
3086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3087 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3088 struct drm_i915_gem_object
*obj
;
3089 int pipe
= intel_crtc
->pipe
;
3090 u32 plane_ctl
, stride_div
, stride
;
3091 u32 tile_height
, plane_offset
, plane_size
;
3092 unsigned int rotation
;
3093 int x_offset
, y_offset
;
3094 unsigned long surf_addr
;
3095 struct drm_plane
*plane
;
3096 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3097 struct intel_plane_state
*plane_state
;
3098 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3099 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3102 plane
= crtc
->primary
;
3103 plane_state
= to_intel_plane_state(plane
->state
);
3105 if (!intel_crtc
->primary_enabled
) {
3106 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3107 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3108 POSTING_READ(PLANE_CTL(pipe
, 0));
3112 plane_ctl
= PLANE_CTL_ENABLE
|
3113 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3114 PLANE_CTL_PIPE_CSC_ENABLE
;
3116 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3117 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3118 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3120 rotation
= plane
->state
->rotation
;
3121 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3123 obj
= intel_fb_obj(fb
);
3124 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3126 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3129 * FIXME: intel_plane_state->src, dst aren't set when transitional
3130 * update_plane helpers are called from legacy paths.
3131 * Once full atomic crtc is available, below check can be avoided.
3133 if (drm_rect_width(&plane_state
->src
)) {
3134 scaler_id
= plane_state
->scaler_id
;
3135 src_x
= plane_state
->src
.x1
>> 16;
3136 src_y
= plane_state
->src
.y1
>> 16;
3137 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3138 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3139 dst_x
= plane_state
->dst
.x1
;
3140 dst_y
= plane_state
->dst
.y1
;
3141 dst_w
= drm_rect_width(&plane_state
->dst
);
3142 dst_h
= drm_rect_height(&plane_state
->dst
);
3144 WARN_ON(x
!= src_x
|| y
!= src_y
);
3146 src_w
= intel_crtc
->config
->pipe_src_w
;
3147 src_h
= intel_crtc
->config
->pipe_src_h
;
3150 if (intel_rotation_90_or_270(rotation
)) {
3151 /* stride = Surface height in tiles */
3152 tile_height
= intel_tile_height(dev
, fb
->bits_per_pixel
,
3154 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3155 x_offset
= stride
* tile_height
- y
- src_h
;
3157 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3159 stride
= fb
->pitches
[0] / stride_div
;
3162 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3164 plane_offset
= y_offset
<< 16 | x_offset
;
3166 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3167 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3168 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3169 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3171 if (scaler_id
>= 0) {
3172 uint32_t ps_ctrl
= 0;
3174 WARN_ON(!dst_w
|| !dst_h
);
3175 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3176 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3177 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3178 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3179 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3180 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3181 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3183 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3186 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3188 POSTING_READ(PLANE_SURF(pipe
, 0));
3191 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3193 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3194 int x
, int y
, enum mode_set_atomic state
)
3196 struct drm_device
*dev
= crtc
->dev
;
3197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3199 if (dev_priv
->display
.disable_fbc
)
3200 dev_priv
->display
.disable_fbc(dev
);
3202 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3207 static void intel_complete_page_flips(struct drm_device
*dev
)
3209 struct drm_crtc
*crtc
;
3211 for_each_crtc(dev
, crtc
) {
3212 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3213 enum plane plane
= intel_crtc
->plane
;
3215 intel_prepare_page_flip(dev
, plane
);
3216 intel_finish_page_flip_plane(dev
, plane
);
3220 static void intel_update_primary_planes(struct drm_device
*dev
)
3222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3223 struct drm_crtc
*crtc
;
3225 for_each_crtc(dev
, crtc
) {
3226 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3228 drm_modeset_lock(&crtc
->mutex
, NULL
);
3230 * FIXME: Once we have proper support for primary planes (and
3231 * disabling them without disabling the entire crtc) allow again
3232 * a NULL crtc->primary->fb.
3234 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3235 dev_priv
->display
.update_primary_plane(crtc
,
3239 drm_modeset_unlock(&crtc
->mutex
);
3243 void intel_prepare_reset(struct drm_device
*dev
)
3245 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3246 struct intel_crtc
*crtc
;
3248 /* no reset support for gen2 */
3252 /* reset doesn't touch the display */
3253 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3256 drm_modeset_lock_all(dev
);
3259 * Disabling the crtcs gracefully seems nicer. Also the
3260 * g33 docs say we should at least disable all the planes.
3262 for_each_intel_crtc(dev
, crtc
) {
3264 dev_priv
->display
.crtc_disable(&crtc
->base
);
3268 void intel_finish_reset(struct drm_device
*dev
)
3270 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3273 * Flips in the rings will be nuked by the reset,
3274 * so complete all pending flips so that user space
3275 * will get its events and not get stuck.
3277 intel_complete_page_flips(dev
);
3279 /* no reset support for gen2 */
3283 /* reset doesn't touch the display */
3284 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3286 * Flips in the rings have been nuked by the reset,
3287 * so update the base address of all primary
3288 * planes to the the last fb to make sure we're
3289 * showing the correct fb after a reset.
3291 intel_update_primary_planes(dev
);
3296 * The display has been reset as well,
3297 * so need a full re-initialization.
3299 intel_runtime_pm_disable_interrupts(dev_priv
);
3300 intel_runtime_pm_enable_interrupts(dev_priv
);
3302 intel_modeset_init_hw(dev
);
3304 spin_lock_irq(&dev_priv
->irq_lock
);
3305 if (dev_priv
->display
.hpd_irq_setup
)
3306 dev_priv
->display
.hpd_irq_setup(dev
);
3307 spin_unlock_irq(&dev_priv
->irq_lock
);
3309 intel_modeset_setup_hw_state(dev
, true);
3311 intel_hpd_init(dev_priv
);
3313 drm_modeset_unlock_all(dev
);
3317 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3319 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3320 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3321 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3324 /* Big Hammer, we also need to ensure that any pending
3325 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3326 * current scanout is retired before unpinning the old
3329 * This should only fail upon a hung GPU, in which case we
3330 * can safely continue.
3332 dev_priv
->mm
.interruptible
= false;
3333 ret
= i915_gem_object_finish_gpu(obj
);
3334 dev_priv
->mm
.interruptible
= was_interruptible
;
3339 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3341 struct drm_device
*dev
= crtc
->dev
;
3342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3346 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3347 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3350 spin_lock_irq(&dev
->event_lock
);
3351 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3352 spin_unlock_irq(&dev
->event_lock
);
3357 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3359 struct drm_device
*dev
= crtc
->base
.dev
;
3360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3361 const struct drm_display_mode
*adjusted_mode
;
3367 * Update pipe size and adjust fitter if needed: the reason for this is
3368 * that in compute_mode_changes we check the native mode (not the pfit
3369 * mode) to see if we can flip rather than do a full mode set. In the
3370 * fastboot case, we'll flip, but if we don't update the pipesrc and
3371 * pfit state, we'll end up with a big fb scanned out into the wrong
3374 * To fix this properly, we need to hoist the checks up into
3375 * compute_mode_changes (or above), check the actual pfit state and
3376 * whether the platform allows pfit disable with pipe active, and only
3377 * then update the pipesrc and pfit state, even on the flip path.
3380 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3382 I915_WRITE(PIPESRC(crtc
->pipe
),
3383 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3384 (adjusted_mode
->crtc_vdisplay
- 1));
3385 if (!crtc
->config
->pch_pfit
.enabled
&&
3386 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3387 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3388 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3389 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3390 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3392 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3393 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3396 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3398 struct drm_device
*dev
= crtc
->dev
;
3399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3400 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3401 int pipe
= intel_crtc
->pipe
;
3404 /* enable normal train */
3405 reg
= FDI_TX_CTL(pipe
);
3406 temp
= I915_READ(reg
);
3407 if (IS_IVYBRIDGE(dev
)) {
3408 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3409 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3411 temp
&= ~FDI_LINK_TRAIN_NONE
;
3412 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3414 I915_WRITE(reg
, temp
);
3416 reg
= FDI_RX_CTL(pipe
);
3417 temp
= I915_READ(reg
);
3418 if (HAS_PCH_CPT(dev
)) {
3419 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3420 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3422 temp
&= ~FDI_LINK_TRAIN_NONE
;
3423 temp
|= FDI_LINK_TRAIN_NONE
;
3425 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3427 /* wait one idle pattern time */
3431 /* IVB wants error correction enabled */
3432 if (IS_IVYBRIDGE(dev
))
3433 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3434 FDI_FE_ERRC_ENABLE
);
3437 /* The FDI link training functions for ILK/Ibexpeak. */
3438 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3440 struct drm_device
*dev
= crtc
->dev
;
3441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3442 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3443 int pipe
= intel_crtc
->pipe
;
3444 u32 reg
, temp
, tries
;
3446 /* FDI needs bits from pipe first */
3447 assert_pipe_enabled(dev_priv
, pipe
);
3449 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3451 reg
= FDI_RX_IMR(pipe
);
3452 temp
= I915_READ(reg
);
3453 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3454 temp
&= ~FDI_RX_BIT_LOCK
;
3455 I915_WRITE(reg
, temp
);
3459 /* enable CPU FDI TX and PCH FDI RX */
3460 reg
= FDI_TX_CTL(pipe
);
3461 temp
= I915_READ(reg
);
3462 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3463 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3464 temp
&= ~FDI_LINK_TRAIN_NONE
;
3465 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3466 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3468 reg
= FDI_RX_CTL(pipe
);
3469 temp
= I915_READ(reg
);
3470 temp
&= ~FDI_LINK_TRAIN_NONE
;
3471 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3472 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3477 /* Ironlake workaround, enable clock pointer after FDI enable*/
3478 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3479 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3480 FDI_RX_PHASE_SYNC_POINTER_EN
);
3482 reg
= FDI_RX_IIR(pipe
);
3483 for (tries
= 0; tries
< 5; tries
++) {
3484 temp
= I915_READ(reg
);
3485 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3487 if ((temp
& FDI_RX_BIT_LOCK
)) {
3488 DRM_DEBUG_KMS("FDI train 1 done.\n");
3489 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3494 DRM_ERROR("FDI train 1 fail!\n");
3497 reg
= FDI_TX_CTL(pipe
);
3498 temp
= I915_READ(reg
);
3499 temp
&= ~FDI_LINK_TRAIN_NONE
;
3500 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3501 I915_WRITE(reg
, temp
);
3503 reg
= FDI_RX_CTL(pipe
);
3504 temp
= I915_READ(reg
);
3505 temp
&= ~FDI_LINK_TRAIN_NONE
;
3506 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3507 I915_WRITE(reg
, temp
);
3512 reg
= FDI_RX_IIR(pipe
);
3513 for (tries
= 0; tries
< 5; tries
++) {
3514 temp
= I915_READ(reg
);
3515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3517 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3518 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3519 DRM_DEBUG_KMS("FDI train 2 done.\n");
3524 DRM_ERROR("FDI train 2 fail!\n");
3526 DRM_DEBUG_KMS("FDI train done\n");
3530 static const int snb_b_fdi_train_param
[] = {
3531 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3532 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3533 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3534 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3537 /* The FDI link training functions for SNB/Cougarpoint. */
3538 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3540 struct drm_device
*dev
= crtc
->dev
;
3541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3542 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3543 int pipe
= intel_crtc
->pipe
;
3544 u32 reg
, temp
, i
, retry
;
3546 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3548 reg
= FDI_RX_IMR(pipe
);
3549 temp
= I915_READ(reg
);
3550 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3551 temp
&= ~FDI_RX_BIT_LOCK
;
3552 I915_WRITE(reg
, temp
);
3557 /* enable CPU FDI TX and PCH FDI RX */
3558 reg
= FDI_TX_CTL(pipe
);
3559 temp
= I915_READ(reg
);
3560 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3561 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3562 temp
&= ~FDI_LINK_TRAIN_NONE
;
3563 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3564 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3566 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3567 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3569 I915_WRITE(FDI_RX_MISC(pipe
),
3570 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3572 reg
= FDI_RX_CTL(pipe
);
3573 temp
= I915_READ(reg
);
3574 if (HAS_PCH_CPT(dev
)) {
3575 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3576 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3578 temp
&= ~FDI_LINK_TRAIN_NONE
;
3579 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3581 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3586 for (i
= 0; i
< 4; i
++) {
3587 reg
= FDI_TX_CTL(pipe
);
3588 temp
= I915_READ(reg
);
3589 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3590 temp
|= snb_b_fdi_train_param
[i
];
3591 I915_WRITE(reg
, temp
);
3596 for (retry
= 0; retry
< 5; retry
++) {
3597 reg
= FDI_RX_IIR(pipe
);
3598 temp
= I915_READ(reg
);
3599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3600 if (temp
& FDI_RX_BIT_LOCK
) {
3601 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3602 DRM_DEBUG_KMS("FDI train 1 done.\n");
3611 DRM_ERROR("FDI train 1 fail!\n");
3614 reg
= FDI_TX_CTL(pipe
);
3615 temp
= I915_READ(reg
);
3616 temp
&= ~FDI_LINK_TRAIN_NONE
;
3617 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3619 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3621 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3623 I915_WRITE(reg
, temp
);
3625 reg
= FDI_RX_CTL(pipe
);
3626 temp
= I915_READ(reg
);
3627 if (HAS_PCH_CPT(dev
)) {
3628 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3629 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3631 temp
&= ~FDI_LINK_TRAIN_NONE
;
3632 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3634 I915_WRITE(reg
, temp
);
3639 for (i
= 0; i
< 4; i
++) {
3640 reg
= FDI_TX_CTL(pipe
);
3641 temp
= I915_READ(reg
);
3642 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3643 temp
|= snb_b_fdi_train_param
[i
];
3644 I915_WRITE(reg
, temp
);
3649 for (retry
= 0; retry
< 5; retry
++) {
3650 reg
= FDI_RX_IIR(pipe
);
3651 temp
= I915_READ(reg
);
3652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3653 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3654 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3655 DRM_DEBUG_KMS("FDI train 2 done.\n");
3664 DRM_ERROR("FDI train 2 fail!\n");
3666 DRM_DEBUG_KMS("FDI train done.\n");
3669 /* Manual link training for Ivy Bridge A0 parts */
3670 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3672 struct drm_device
*dev
= crtc
->dev
;
3673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3674 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3675 int pipe
= intel_crtc
->pipe
;
3676 u32 reg
, temp
, i
, j
;
3678 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3680 reg
= FDI_RX_IMR(pipe
);
3681 temp
= I915_READ(reg
);
3682 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3683 temp
&= ~FDI_RX_BIT_LOCK
;
3684 I915_WRITE(reg
, temp
);
3689 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3690 I915_READ(FDI_RX_IIR(pipe
)));
3692 /* Try each vswing and preemphasis setting twice before moving on */
3693 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3694 /* disable first in case we need to retry */
3695 reg
= FDI_TX_CTL(pipe
);
3696 temp
= I915_READ(reg
);
3697 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3698 temp
&= ~FDI_TX_ENABLE
;
3699 I915_WRITE(reg
, temp
);
3701 reg
= FDI_RX_CTL(pipe
);
3702 temp
= I915_READ(reg
);
3703 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3704 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3705 temp
&= ~FDI_RX_ENABLE
;
3706 I915_WRITE(reg
, temp
);
3708 /* enable CPU FDI TX and PCH FDI RX */
3709 reg
= FDI_TX_CTL(pipe
);
3710 temp
= I915_READ(reg
);
3711 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3712 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3713 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3714 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3715 temp
|= snb_b_fdi_train_param
[j
/2];
3716 temp
|= FDI_COMPOSITE_SYNC
;
3717 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3719 I915_WRITE(FDI_RX_MISC(pipe
),
3720 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3722 reg
= FDI_RX_CTL(pipe
);
3723 temp
= I915_READ(reg
);
3724 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3725 temp
|= FDI_COMPOSITE_SYNC
;
3726 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3729 udelay(1); /* should be 0.5us */
3731 for (i
= 0; i
< 4; i
++) {
3732 reg
= FDI_RX_IIR(pipe
);
3733 temp
= I915_READ(reg
);
3734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3736 if (temp
& FDI_RX_BIT_LOCK
||
3737 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3738 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3739 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3743 udelay(1); /* should be 0.5us */
3746 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3751 reg
= FDI_TX_CTL(pipe
);
3752 temp
= I915_READ(reg
);
3753 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3754 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3755 I915_WRITE(reg
, temp
);
3757 reg
= FDI_RX_CTL(pipe
);
3758 temp
= I915_READ(reg
);
3759 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3760 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3761 I915_WRITE(reg
, temp
);
3764 udelay(2); /* should be 1.5us */
3766 for (i
= 0; i
< 4; i
++) {
3767 reg
= FDI_RX_IIR(pipe
);
3768 temp
= I915_READ(reg
);
3769 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3771 if (temp
& FDI_RX_SYMBOL_LOCK
||
3772 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3773 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3774 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3778 udelay(2); /* should be 1.5us */
3781 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3785 DRM_DEBUG_KMS("FDI train done.\n");
3788 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3790 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3792 int pipe
= intel_crtc
->pipe
;
3796 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3797 reg
= FDI_RX_CTL(pipe
);
3798 temp
= I915_READ(reg
);
3799 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3800 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3801 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3802 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3807 /* Switch from Rawclk to PCDclk */
3808 temp
= I915_READ(reg
);
3809 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3814 /* Enable CPU FDI TX PLL, always on for Ironlake */
3815 reg
= FDI_TX_CTL(pipe
);
3816 temp
= I915_READ(reg
);
3817 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3818 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3825 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3827 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3829 int pipe
= intel_crtc
->pipe
;
3832 /* Switch from PCDclk to Rawclk */
3833 reg
= FDI_RX_CTL(pipe
);
3834 temp
= I915_READ(reg
);
3835 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3837 /* Disable CPU FDI TX PLL */
3838 reg
= FDI_TX_CTL(pipe
);
3839 temp
= I915_READ(reg
);
3840 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3845 reg
= FDI_RX_CTL(pipe
);
3846 temp
= I915_READ(reg
);
3847 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3849 /* Wait for the clocks to turn off. */
3854 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3856 struct drm_device
*dev
= crtc
->dev
;
3857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3858 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3859 int pipe
= intel_crtc
->pipe
;
3862 /* disable CPU FDI tx and PCH FDI rx */
3863 reg
= FDI_TX_CTL(pipe
);
3864 temp
= I915_READ(reg
);
3865 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3868 reg
= FDI_RX_CTL(pipe
);
3869 temp
= I915_READ(reg
);
3870 temp
&= ~(0x7 << 16);
3871 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3872 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3877 /* Ironlake workaround, disable clock pointer after downing FDI */
3878 if (HAS_PCH_IBX(dev
))
3879 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3881 /* still set train pattern 1 */
3882 reg
= FDI_TX_CTL(pipe
);
3883 temp
= I915_READ(reg
);
3884 temp
&= ~FDI_LINK_TRAIN_NONE
;
3885 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3886 I915_WRITE(reg
, temp
);
3888 reg
= FDI_RX_CTL(pipe
);
3889 temp
= I915_READ(reg
);
3890 if (HAS_PCH_CPT(dev
)) {
3891 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3892 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3894 temp
&= ~FDI_LINK_TRAIN_NONE
;
3895 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3897 /* BPC in FDI rx is consistent with that in PIPECONF */
3898 temp
&= ~(0x07 << 16);
3899 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3900 I915_WRITE(reg
, temp
);
3906 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3908 struct intel_crtc
*crtc
;
3910 /* Note that we don't need to be called with mode_config.lock here
3911 * as our list of CRTC objects is static for the lifetime of the
3912 * device and so cannot disappear as we iterate. Similarly, we can
3913 * happily treat the predicates as racy, atomic checks as userspace
3914 * cannot claim and pin a new fb without at least acquring the
3915 * struct_mutex and so serialising with us.
3917 for_each_intel_crtc(dev
, crtc
) {
3918 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3921 if (crtc
->unpin_work
)
3922 intel_wait_for_vblank(dev
, crtc
->pipe
);
3930 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3932 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3933 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3935 /* ensure that the unpin work is consistent wrt ->pending. */
3937 intel_crtc
->unpin_work
= NULL
;
3940 drm_send_vblank_event(intel_crtc
->base
.dev
,
3944 drm_crtc_vblank_put(&intel_crtc
->base
);
3946 wake_up_all(&dev_priv
->pending_flip_queue
);
3947 queue_work(dev_priv
->wq
, &work
->work
);
3949 trace_i915_flip_complete(intel_crtc
->plane
,
3950 work
->pending_flip_obj
);
3953 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3955 struct drm_device
*dev
= crtc
->dev
;
3956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3958 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3959 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3960 !intel_crtc_has_pending_flip(crtc
),
3962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3964 spin_lock_irq(&dev
->event_lock
);
3965 if (intel_crtc
->unpin_work
) {
3966 WARN_ONCE(1, "Removing stuck page flip\n");
3967 page_flip_completed(intel_crtc
);
3969 spin_unlock_irq(&dev
->event_lock
);
3972 if (crtc
->primary
->fb
) {
3973 mutex_lock(&dev
->struct_mutex
);
3974 intel_finish_fb(crtc
->primary
->fb
);
3975 mutex_unlock(&dev
->struct_mutex
);
3979 /* Program iCLKIP clock to the desired frequency */
3980 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3982 struct drm_device
*dev
= crtc
->dev
;
3983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3984 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3985 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3988 mutex_lock(&dev_priv
->dpio_lock
);
3990 /* It is necessary to ungate the pixclk gate prior to programming
3991 * the divisors, and gate it back when it is done.
3993 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3995 /* Disable SSCCTL */
3996 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3997 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
4001 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
4002 if (clock
== 20000) {
4007 /* The iCLK virtual clock root frequency is in MHz,
4008 * but the adjusted_mode->crtc_clock in in KHz. To get the
4009 * divisors, it is necessary to divide one by another, so we
4010 * convert the virtual clock precision to KHz here for higher
4013 u32 iclk_virtual_root_freq
= 172800 * 1000;
4014 u32 iclk_pi_range
= 64;
4015 u32 desired_divisor
, msb_divisor_value
, pi_value
;
4017 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
4018 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
4019 pi_value
= desired_divisor
% iclk_pi_range
;
4022 divsel
= msb_divisor_value
- 2;
4023 phaseinc
= pi_value
;
4026 /* This should not happen with any sane values */
4027 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4028 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4029 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4030 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4032 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4039 /* Program SSCDIVINTPHASE6 */
4040 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4041 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4042 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4043 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4044 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4045 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4046 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4047 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4049 /* Program SSCAUXDIV */
4050 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4051 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4052 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4053 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4055 /* Enable modulator and associated divider */
4056 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4057 temp
&= ~SBI_SSCCTL_DISABLE
;
4058 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4060 /* Wait for initialization time */
4063 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4065 mutex_unlock(&dev_priv
->dpio_lock
);
4068 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4069 enum pipe pch_transcoder
)
4071 struct drm_device
*dev
= crtc
->base
.dev
;
4072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4073 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4075 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4076 I915_READ(HTOTAL(cpu_transcoder
)));
4077 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4078 I915_READ(HBLANK(cpu_transcoder
)));
4079 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4080 I915_READ(HSYNC(cpu_transcoder
)));
4082 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4083 I915_READ(VTOTAL(cpu_transcoder
)));
4084 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4085 I915_READ(VBLANK(cpu_transcoder
)));
4086 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4087 I915_READ(VSYNC(cpu_transcoder
)));
4088 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4089 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4092 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4097 temp
= I915_READ(SOUTH_CHICKEN1
);
4098 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4101 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4102 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4104 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4106 temp
|= FDI_BC_BIFURCATION_SELECT
;
4108 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4109 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4110 POSTING_READ(SOUTH_CHICKEN1
);
4113 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4115 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4117 switch (intel_crtc
->pipe
) {
4121 if (intel_crtc
->config
->fdi_lanes
> 2)
4122 cpt_set_fdi_bc_bifurcation(dev
, false);
4124 cpt_set_fdi_bc_bifurcation(dev
, true);
4128 cpt_set_fdi_bc_bifurcation(dev
, true);
4137 * Enable PCH resources required for PCH ports:
4139 * - FDI training & RX/TX
4140 * - update transcoder timings
4141 * - DP transcoding bits
4144 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4146 struct drm_device
*dev
= crtc
->dev
;
4147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4148 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4149 int pipe
= intel_crtc
->pipe
;
4152 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4154 if (IS_IVYBRIDGE(dev
))
4155 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4157 /* Write the TU size bits before fdi link training, so that error
4158 * detection works. */
4159 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4160 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4162 /* For PCH output, training FDI link */
4163 dev_priv
->display
.fdi_link_train(crtc
);
4165 /* We need to program the right clock selection before writing the pixel
4166 * mutliplier into the DPLL. */
4167 if (HAS_PCH_CPT(dev
)) {
4170 temp
= I915_READ(PCH_DPLL_SEL
);
4171 temp
|= TRANS_DPLL_ENABLE(pipe
);
4172 sel
= TRANS_DPLLB_SEL(pipe
);
4173 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4177 I915_WRITE(PCH_DPLL_SEL
, temp
);
4180 /* XXX: pch pll's can be enabled any time before we enable the PCH
4181 * transcoder, and we actually should do this to not upset any PCH
4182 * transcoder that already use the clock when we share it.
4184 * Note that enable_shared_dpll tries to do the right thing, but
4185 * get_shared_dpll unconditionally resets the pll - we need that to have
4186 * the right LVDS enable sequence. */
4187 intel_enable_shared_dpll(intel_crtc
);
4189 /* set transcoder timing, panel must allow it */
4190 assert_panel_unlocked(dev_priv
, pipe
);
4191 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4193 intel_fdi_normal_train(crtc
);
4195 /* For PCH DP, enable TRANS_DP_CTL */
4196 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4197 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4198 reg
= TRANS_DP_CTL(pipe
);
4199 temp
= I915_READ(reg
);
4200 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4201 TRANS_DP_SYNC_MASK
|
4203 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
4204 TRANS_DP_ENH_FRAMING
);
4205 temp
|= bpc
<< 9; /* same format but at 11:9 */
4207 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4208 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4209 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4210 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4212 switch (intel_trans_dp_port_sel(crtc
)) {
4214 temp
|= TRANS_DP_PORT_SEL_B
;
4217 temp
|= TRANS_DP_PORT_SEL_C
;
4220 temp
|= TRANS_DP_PORT_SEL_D
;
4226 I915_WRITE(reg
, temp
);
4229 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4232 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4234 struct drm_device
*dev
= crtc
->dev
;
4235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4237 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4239 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4241 lpt_program_iclkip(crtc
);
4243 /* Set transcoder timing. */
4244 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4246 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4249 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4251 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4256 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4257 WARN(1, "bad %s crtc mask\n", pll
->name
);
4261 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4262 if (pll
->config
.crtc_mask
== 0) {
4264 WARN_ON(pll
->active
);
4267 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4270 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4271 struct intel_crtc_state
*crtc_state
)
4273 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4274 struct intel_shared_dpll
*pll
;
4275 enum intel_dpll_id i
;
4277 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4278 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4279 i
= (enum intel_dpll_id
) crtc
->pipe
;
4280 pll
= &dev_priv
->shared_dplls
[i
];
4282 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4283 crtc
->base
.base
.id
, pll
->name
);
4285 WARN_ON(pll
->new_config
->crtc_mask
);
4290 if (IS_BROXTON(dev_priv
->dev
)) {
4291 /* PLL is attached to port in bxt */
4292 struct intel_encoder
*encoder
;
4293 struct intel_digital_port
*intel_dig_port
;
4295 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4296 if (WARN_ON(!encoder
))
4299 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4300 /* 1:1 mapping between ports and PLLs */
4301 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4302 pll
= &dev_priv
->shared_dplls
[i
];
4303 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4304 crtc
->base
.base
.id
, pll
->name
);
4305 WARN_ON(pll
->new_config
->crtc_mask
);
4310 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4311 pll
= &dev_priv
->shared_dplls
[i
];
4313 /* Only want to check enabled timings first */
4314 if (pll
->new_config
->crtc_mask
== 0)
4317 if (memcmp(&crtc_state
->dpll_hw_state
,
4318 &pll
->new_config
->hw_state
,
4319 sizeof(pll
->new_config
->hw_state
)) == 0) {
4320 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4321 crtc
->base
.base
.id
, pll
->name
,
4322 pll
->new_config
->crtc_mask
,
4328 /* Ok no matching timings, maybe there's a free one? */
4329 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4330 pll
= &dev_priv
->shared_dplls
[i
];
4331 if (pll
->new_config
->crtc_mask
== 0) {
4332 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4333 crtc
->base
.base
.id
, pll
->name
);
4341 if (pll
->new_config
->crtc_mask
== 0)
4342 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4344 crtc_state
->shared_dpll
= i
;
4345 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4346 pipe_name(crtc
->pipe
));
4348 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4354 * intel_shared_dpll_start_config - start a new PLL staged config
4355 * @dev_priv: DRM device
4356 * @clear_pipes: mask of pipes that will have their PLLs freed
4358 * Starts a new PLL staged config, copying the current config but
4359 * releasing the references of pipes specified in clear_pipes.
4361 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4362 unsigned clear_pipes
)
4364 struct intel_shared_dpll
*pll
;
4365 enum intel_dpll_id i
;
4367 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4368 pll
= &dev_priv
->shared_dplls
[i
];
4370 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4372 if (!pll
->new_config
)
4375 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4382 pll
= &dev_priv
->shared_dplls
[i
];
4383 kfree(pll
->new_config
);
4384 pll
->new_config
= NULL
;
4390 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4392 struct intel_shared_dpll
*pll
;
4393 enum intel_dpll_id i
;
4395 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4396 pll
= &dev_priv
->shared_dplls
[i
];
4398 WARN_ON(pll
->new_config
== &pll
->config
);
4400 pll
->config
= *pll
->new_config
;
4401 kfree(pll
->new_config
);
4402 pll
->new_config
= NULL
;
4406 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4408 struct intel_shared_dpll
*pll
;
4409 enum intel_dpll_id i
;
4411 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4412 pll
= &dev_priv
->shared_dplls
[i
];
4414 WARN_ON(pll
->new_config
== &pll
->config
);
4416 kfree(pll
->new_config
);
4417 pll
->new_config
= NULL
;
4421 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4424 int dslreg
= PIPEDSL(pipe
);
4427 temp
= I915_READ(dslreg
);
4429 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4430 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4431 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4436 * skl_update_scaler_users - Stages update to crtc's scaler state
4438 * @crtc_state: crtc_state
4439 * @plane: plane (NULL indicates crtc is requesting update)
4440 * @plane_state: plane's state
4441 * @force_detach: request unconditional detachment of scaler
4443 * This function updates scaler state for requested plane or crtc.
4444 * To request scaler usage update for a plane, caller shall pass plane pointer.
4445 * To request scaler usage update for crtc, caller shall pass plane pointer
4449 * 0 - scaler_usage updated successfully
4450 * error - requested scaling cannot be supported or other error condition
4453 skl_update_scaler_users(
4454 struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
,
4455 struct intel_plane
*intel_plane
, struct intel_plane_state
*plane_state
,
4460 int src_w
, src_h
, dst_w
, dst_h
;
4462 struct drm_framebuffer
*fb
;
4463 struct intel_crtc_scaler_state
*scaler_state
;
4464 unsigned int rotation
;
4466 if (!intel_crtc
|| !crtc_state
)
4469 scaler_state
= &crtc_state
->scaler_state
;
4471 idx
= intel_plane
? drm_plane_index(&intel_plane
->base
) : SKL_CRTC_INDEX
;
4472 fb
= intel_plane
? plane_state
->base
.fb
: NULL
;
4475 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
4476 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
4477 dst_w
= drm_rect_width(&plane_state
->dst
);
4478 dst_h
= drm_rect_height(&plane_state
->dst
);
4479 scaler_id
= &plane_state
->scaler_id
;
4480 rotation
= plane_state
->base
.rotation
;
4482 struct drm_display_mode
*adjusted_mode
=
4483 &crtc_state
->base
.adjusted_mode
;
4484 src_w
= crtc_state
->pipe_src_w
;
4485 src_h
= crtc_state
->pipe_src_h
;
4486 dst_w
= adjusted_mode
->hdisplay
;
4487 dst_h
= adjusted_mode
->vdisplay
;
4488 scaler_id
= &scaler_state
->scaler_id
;
4489 rotation
= DRM_ROTATE_0
;
4492 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4493 (src_h
!= dst_w
|| src_w
!= dst_h
):
4494 (src_w
!= dst_w
|| src_h
!= dst_h
);
4497 * if plane is being disabled or scaler is no more required or force detach
4498 * - free scaler binded to this plane/crtc
4499 * - in order to do this, update crtc->scaler_usage
4501 * Here scaler state in crtc_state is set free so that
4502 * scaler can be assigned to other user. Actual register
4503 * update to free the scaler is done in plane/panel-fit programming.
4504 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4506 if (force_detach
|| !need_scaling
|| (intel_plane
&&
4507 (!fb
|| !plane_state
->visible
))) {
4508 if (*scaler_id
>= 0) {
4509 scaler_state
->scaler_users
&= ~(1 << idx
);
4510 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4512 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4513 "crtc_state = %p scaler_users = 0x%x\n",
4514 intel_crtc
->pipe
, *scaler_id
, intel_plane
? "PLANE" : "CRTC",
4515 intel_plane
? intel_plane
->base
.base
.id
:
4516 intel_crtc
->base
.base
.id
, crtc_state
,
4517 scaler_state
->scaler_users
);
4524 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4525 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4527 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4528 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4529 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4530 "size is out of scaler range\n",
4531 intel_plane
? "PLANE" : "CRTC",
4532 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4533 intel_crtc
->pipe
, idx
, src_w
, src_h
, dst_w
, dst_h
);
4537 /* check colorkey */
4538 if (intel_plane
&& intel_plane
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4539 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4540 intel_plane
->base
.base
.id
);
4544 /* Check src format */
4546 switch (fb
->pixel_format
) {
4547 case DRM_FORMAT_RGB565
:
4548 case DRM_FORMAT_XBGR8888
:
4549 case DRM_FORMAT_XRGB8888
:
4550 case DRM_FORMAT_ABGR8888
:
4551 case DRM_FORMAT_ARGB8888
:
4552 case DRM_FORMAT_XRGB2101010
:
4553 case DRM_FORMAT_ARGB2101010
:
4554 case DRM_FORMAT_XBGR2101010
:
4555 case DRM_FORMAT_ABGR2101010
:
4556 case DRM_FORMAT_YUYV
:
4557 case DRM_FORMAT_YVYU
:
4558 case DRM_FORMAT_UYVY
:
4559 case DRM_FORMAT_VYUY
:
4562 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4563 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4568 /* mark this plane as a scaler user in crtc_state */
4569 scaler_state
->scaler_users
|= (1 << idx
);
4570 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4571 "crtc_state = %p scaler_users = 0x%x\n",
4572 intel_plane
? "PLANE" : "CRTC",
4573 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4574 src_w
, src_h
, dst_w
, dst_h
, crtc_state
, scaler_state
->scaler_users
);
4578 static void skylake_pfit_update(struct intel_crtc
*crtc
, int enable
)
4580 struct drm_device
*dev
= crtc
->base
.dev
;
4581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4582 int pipe
= crtc
->pipe
;
4583 struct intel_crtc_scaler_state
*scaler_state
=
4584 &crtc
->config
->scaler_state
;
4586 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4588 /* To update pfit, first update scaler state */
4589 skl_update_scaler_users(crtc
, crtc
->config
, NULL
, NULL
, !enable
);
4590 intel_atomic_setup_scalers(crtc
->base
.dev
, crtc
, crtc
->config
);
4591 skl_detach_scalers(crtc
);
4595 if (crtc
->config
->pch_pfit
.enabled
) {
4598 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4599 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4603 id
= scaler_state
->scaler_id
;
4604 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4605 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4606 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4607 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4609 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4613 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4615 struct drm_device
*dev
= crtc
->base
.dev
;
4616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4617 int pipe
= crtc
->pipe
;
4619 if (crtc
->config
->pch_pfit
.enabled
) {
4620 /* Force use of hard-coded filter coefficients
4621 * as some pre-programmed values are broken,
4624 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4625 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4626 PF_PIPE_SEL_IVB(pipe
));
4628 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4629 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4630 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4634 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4636 struct drm_device
*dev
= crtc
->dev
;
4637 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4638 struct drm_plane
*plane
;
4639 struct intel_plane
*intel_plane
;
4641 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4642 intel_plane
= to_intel_plane(plane
);
4643 if (intel_plane
->pipe
== pipe
)
4644 intel_plane_restore(&intel_plane
->base
);
4649 * Disable a plane internally without actually modifying the plane's state.
4650 * This will allow us to easily restore the plane later by just reprogramming
4653 static void disable_plane_internal(struct drm_plane
*plane
)
4655 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
4656 struct drm_plane_state
*state
=
4657 plane
->funcs
->atomic_duplicate_state(plane
);
4658 struct intel_plane_state
*intel_state
= to_intel_plane_state(state
);
4660 intel_state
->visible
= false;
4661 intel_plane
->commit_plane(plane
, intel_state
);
4663 intel_plane_destroy_state(plane
, state
);
4666 static void intel_disable_sprite_planes(struct drm_crtc
*crtc
)
4668 struct drm_device
*dev
= crtc
->dev
;
4669 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4670 struct drm_plane
*plane
;
4671 struct intel_plane
*intel_plane
;
4673 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4674 intel_plane
= to_intel_plane(plane
);
4675 if (plane
->fb
&& intel_plane
->pipe
== pipe
)
4676 disable_plane_internal(plane
);
4680 void hsw_enable_ips(struct intel_crtc
*crtc
)
4682 struct drm_device
*dev
= crtc
->base
.dev
;
4683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4685 if (!crtc
->config
->ips_enabled
)
4688 /* We can only enable IPS after we enable a plane and wait for a vblank */
4689 intel_wait_for_vblank(dev
, crtc
->pipe
);
4691 assert_plane_enabled(dev_priv
, crtc
->plane
);
4692 if (IS_BROADWELL(dev
)) {
4693 mutex_lock(&dev_priv
->rps
.hw_lock
);
4694 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4695 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4696 /* Quoting Art Runyan: "its not safe to expect any particular
4697 * value in IPS_CTL bit 31 after enabling IPS through the
4698 * mailbox." Moreover, the mailbox may return a bogus state,
4699 * so we need to just enable it and continue on.
4702 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4703 /* The bit only becomes 1 in the next vblank, so this wait here
4704 * is essentially intel_wait_for_vblank. If we don't have this
4705 * and don't wait for vblanks until the end of crtc_enable, then
4706 * the HW state readout code will complain that the expected
4707 * IPS_CTL value is not the one we read. */
4708 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4709 DRM_ERROR("Timed out waiting for IPS enable\n");
4713 void hsw_disable_ips(struct intel_crtc
*crtc
)
4715 struct drm_device
*dev
= crtc
->base
.dev
;
4716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4718 if (!crtc
->config
->ips_enabled
)
4721 assert_plane_enabled(dev_priv
, crtc
->plane
);
4722 if (IS_BROADWELL(dev
)) {
4723 mutex_lock(&dev_priv
->rps
.hw_lock
);
4724 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4725 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4726 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4727 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4728 DRM_ERROR("Timed out waiting for IPS disable\n");
4730 I915_WRITE(IPS_CTL
, 0);
4731 POSTING_READ(IPS_CTL
);
4734 /* We need to wait for a vblank before we can disable the plane. */
4735 intel_wait_for_vblank(dev
, crtc
->pipe
);
4738 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4739 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4741 struct drm_device
*dev
= crtc
->dev
;
4742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4743 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4744 enum pipe pipe
= intel_crtc
->pipe
;
4745 int palreg
= PALETTE(pipe
);
4747 bool reenable_ips
= false;
4749 /* The clocks have to be on to load the palette. */
4750 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4753 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4754 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4755 assert_dsi_pll_enabled(dev_priv
);
4757 assert_pll_enabled(dev_priv
, pipe
);
4760 /* use legacy palette for Ironlake */
4761 if (!HAS_GMCH_DISPLAY(dev
))
4762 palreg
= LGC_PALETTE(pipe
);
4764 /* Workaround : Do not read or write the pipe palette/gamma data while
4765 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4767 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4768 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4769 GAMMA_MODE_MODE_SPLIT
)) {
4770 hsw_disable_ips(intel_crtc
);
4771 reenable_ips
= true;
4774 for (i
= 0; i
< 256; i
++) {
4775 I915_WRITE(palreg
+ 4 * i
,
4776 (intel_crtc
->lut_r
[i
] << 16) |
4777 (intel_crtc
->lut_g
[i
] << 8) |
4778 intel_crtc
->lut_b
[i
]);
4782 hsw_enable_ips(intel_crtc
);
4785 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4787 if (!enable
&& intel_crtc
->overlay
) {
4788 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4791 mutex_lock(&dev
->struct_mutex
);
4792 dev_priv
->mm
.interruptible
= false;
4793 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4794 dev_priv
->mm
.interruptible
= true;
4795 mutex_unlock(&dev
->struct_mutex
);
4798 /* Let userspace switch the overlay on again. In most cases userspace
4799 * has to recompute where to put it anyway.
4803 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4805 struct drm_device
*dev
= crtc
->dev
;
4806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4807 int pipe
= intel_crtc
->pipe
;
4809 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4810 intel_enable_sprite_planes(crtc
);
4811 intel_crtc_update_cursor(crtc
, true);
4812 intel_crtc_dpms_overlay(intel_crtc
, true);
4814 hsw_enable_ips(intel_crtc
);
4816 mutex_lock(&dev
->struct_mutex
);
4817 intel_fbc_update(dev
);
4818 mutex_unlock(&dev
->struct_mutex
);
4821 * FIXME: Once we grow proper nuclear flip support out of this we need
4822 * to compute the mask of flip planes precisely. For the time being
4823 * consider this a flip from a NULL plane.
4825 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4828 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4830 struct drm_device
*dev
= crtc
->dev
;
4831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4833 int pipe
= intel_crtc
->pipe
;
4835 intel_crtc_wait_for_pending_flips(crtc
);
4837 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4838 intel_fbc_disable(dev
);
4840 hsw_disable_ips(intel_crtc
);
4842 intel_crtc_dpms_overlay(intel_crtc
, false);
4843 intel_crtc_update_cursor(crtc
, false);
4844 intel_disable_sprite_planes(crtc
);
4845 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4848 * FIXME: Once we grow proper nuclear flip support out of this we need
4849 * to compute the mask of flip planes precisely. For the time being
4850 * consider this a flip to a NULL plane.
4852 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4855 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4857 struct drm_device
*dev
= crtc
->dev
;
4858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4860 struct intel_encoder
*encoder
;
4861 int pipe
= intel_crtc
->pipe
;
4863 WARN_ON(!crtc
->state
->enable
);
4865 if (intel_crtc
->active
)
4868 if (intel_crtc
->config
->has_pch_encoder
)
4869 intel_prepare_shared_dpll(intel_crtc
);
4871 if (intel_crtc
->config
->has_dp_encoder
)
4872 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4874 intel_set_pipe_timings(intel_crtc
);
4876 if (intel_crtc
->config
->has_pch_encoder
) {
4877 intel_cpu_transcoder_set_m_n(intel_crtc
,
4878 &intel_crtc
->config
->fdi_m_n
, NULL
);
4881 ironlake_set_pipeconf(crtc
);
4883 intel_crtc
->active
= true;
4885 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4886 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4888 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4889 if (encoder
->pre_enable
)
4890 encoder
->pre_enable(encoder
);
4892 if (intel_crtc
->config
->has_pch_encoder
) {
4893 /* Note: FDI PLL enabling _must_ be done before we enable the
4894 * cpu pipes, hence this is separate from all the other fdi/pch
4896 ironlake_fdi_pll_enable(intel_crtc
);
4898 assert_fdi_tx_disabled(dev_priv
, pipe
);
4899 assert_fdi_rx_disabled(dev_priv
, pipe
);
4902 ironlake_pfit_enable(intel_crtc
);
4905 * On ILK+ LUT must be loaded before the pipe is running but with
4908 intel_crtc_load_lut(crtc
);
4910 intel_update_watermarks(crtc
);
4911 intel_enable_pipe(intel_crtc
);
4913 if (intel_crtc
->config
->has_pch_encoder
)
4914 ironlake_pch_enable(crtc
);
4916 assert_vblank_disabled(crtc
);
4917 drm_crtc_vblank_on(crtc
);
4919 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4920 encoder
->enable(encoder
);
4922 if (HAS_PCH_CPT(dev
))
4923 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4925 intel_crtc_enable_planes(crtc
);
4928 /* IPS only exists on ULT machines and is tied to pipe A. */
4929 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4931 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4935 * This implements the workaround described in the "notes" section of the mode
4936 * set sequence documentation. When going from no pipes or single pipe to
4937 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4938 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4940 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4942 struct drm_device
*dev
= crtc
->base
.dev
;
4943 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4945 /* We want to get the other_active_crtc only if there's only 1 other
4947 for_each_intel_crtc(dev
, crtc_it
) {
4948 if (!crtc_it
->active
|| crtc_it
== crtc
)
4951 if (other_active_crtc
)
4954 other_active_crtc
= crtc_it
;
4956 if (!other_active_crtc
)
4959 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4960 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4963 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4965 struct drm_device
*dev
= crtc
->dev
;
4966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4968 struct intel_encoder
*encoder
;
4969 int pipe
= intel_crtc
->pipe
;
4971 WARN_ON(!crtc
->state
->enable
);
4973 if (intel_crtc
->active
)
4976 if (intel_crtc_to_shared_dpll(intel_crtc
))
4977 intel_enable_shared_dpll(intel_crtc
);
4979 if (intel_crtc
->config
->has_dp_encoder
)
4980 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4982 intel_set_pipe_timings(intel_crtc
);
4984 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4985 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4986 intel_crtc
->config
->pixel_multiplier
- 1);
4989 if (intel_crtc
->config
->has_pch_encoder
) {
4990 intel_cpu_transcoder_set_m_n(intel_crtc
,
4991 &intel_crtc
->config
->fdi_m_n
, NULL
);
4994 haswell_set_pipeconf(crtc
);
4996 intel_set_pipe_csc(crtc
);
4998 intel_crtc
->active
= true;
5000 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5001 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5002 if (encoder
->pre_enable
)
5003 encoder
->pre_enable(encoder
);
5005 if (intel_crtc
->config
->has_pch_encoder
) {
5006 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5008 dev_priv
->display
.fdi_link_train(crtc
);
5011 intel_ddi_enable_pipe_clock(intel_crtc
);
5013 if (INTEL_INFO(dev
)->gen
== 9)
5014 skylake_pfit_update(intel_crtc
, 1);
5015 else if (INTEL_INFO(dev
)->gen
< 9)
5016 ironlake_pfit_enable(intel_crtc
);
5018 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5021 * On ILK+ LUT must be loaded before the pipe is running but with
5024 intel_crtc_load_lut(crtc
);
5026 intel_ddi_set_pipe_settings(crtc
);
5027 intel_ddi_enable_transcoder_func(crtc
);
5029 intel_update_watermarks(crtc
);
5030 intel_enable_pipe(intel_crtc
);
5032 if (intel_crtc
->config
->has_pch_encoder
)
5033 lpt_pch_enable(crtc
);
5035 if (intel_crtc
->config
->dp_encoder_is_mst
)
5036 intel_ddi_set_vc_payload_alloc(crtc
, true);
5038 assert_vblank_disabled(crtc
);
5039 drm_crtc_vblank_on(crtc
);
5041 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5042 encoder
->enable(encoder
);
5043 intel_opregion_notify_encoder(encoder
, true);
5046 /* If we change the relative order between pipe/planes enabling, we need
5047 * to change the workaround. */
5048 haswell_mode_set_planes_workaround(intel_crtc
);
5049 intel_crtc_enable_planes(crtc
);
5052 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
5054 struct drm_device
*dev
= crtc
->base
.dev
;
5055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5056 int pipe
= crtc
->pipe
;
5058 /* To avoid upsetting the power well on haswell only disable the pfit if
5059 * it's in use. The hw state code will make sure we get this right. */
5060 if (crtc
->config
->pch_pfit
.enabled
) {
5061 I915_WRITE(PF_CTL(pipe
), 0);
5062 I915_WRITE(PF_WIN_POS(pipe
), 0);
5063 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5067 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5069 struct drm_device
*dev
= crtc
->dev
;
5070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5071 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5072 struct intel_encoder
*encoder
;
5073 int pipe
= intel_crtc
->pipe
;
5076 if (!intel_crtc
->active
)
5079 intel_crtc_disable_planes(crtc
);
5081 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5082 encoder
->disable(encoder
);
5084 drm_crtc_vblank_off(crtc
);
5085 assert_vblank_disabled(crtc
);
5087 if (intel_crtc
->config
->has_pch_encoder
)
5088 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5090 intel_disable_pipe(intel_crtc
);
5092 ironlake_pfit_disable(intel_crtc
);
5094 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5095 if (encoder
->post_disable
)
5096 encoder
->post_disable(encoder
);
5098 if (intel_crtc
->config
->has_pch_encoder
) {
5099 ironlake_fdi_disable(crtc
);
5101 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5103 if (HAS_PCH_CPT(dev
)) {
5104 /* disable TRANS_DP_CTL */
5105 reg
= TRANS_DP_CTL(pipe
);
5106 temp
= I915_READ(reg
);
5107 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5108 TRANS_DP_PORT_SEL_MASK
);
5109 temp
|= TRANS_DP_PORT_SEL_NONE
;
5110 I915_WRITE(reg
, temp
);
5112 /* disable DPLL_SEL */
5113 temp
= I915_READ(PCH_DPLL_SEL
);
5114 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5115 I915_WRITE(PCH_DPLL_SEL
, temp
);
5118 /* disable PCH DPLL */
5119 intel_disable_shared_dpll(intel_crtc
);
5121 ironlake_fdi_pll_disable(intel_crtc
);
5124 intel_crtc
->active
= false;
5125 intel_update_watermarks(crtc
);
5127 mutex_lock(&dev
->struct_mutex
);
5128 intel_fbc_update(dev
);
5129 mutex_unlock(&dev
->struct_mutex
);
5132 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5134 struct drm_device
*dev
= crtc
->dev
;
5135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5136 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5137 struct intel_encoder
*encoder
;
5138 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5140 if (!intel_crtc
->active
)
5143 intel_crtc_disable_planes(crtc
);
5145 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5146 intel_opregion_notify_encoder(encoder
, false);
5147 encoder
->disable(encoder
);
5150 drm_crtc_vblank_off(crtc
);
5151 assert_vblank_disabled(crtc
);
5153 if (intel_crtc
->config
->has_pch_encoder
)
5154 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5156 intel_disable_pipe(intel_crtc
);
5158 if (intel_crtc
->config
->dp_encoder_is_mst
)
5159 intel_ddi_set_vc_payload_alloc(crtc
, false);
5161 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5163 if (INTEL_INFO(dev
)->gen
== 9)
5164 skylake_pfit_update(intel_crtc
, 0);
5165 else if (INTEL_INFO(dev
)->gen
< 9)
5166 ironlake_pfit_disable(intel_crtc
);
5168 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5170 intel_ddi_disable_pipe_clock(intel_crtc
);
5172 if (intel_crtc
->config
->has_pch_encoder
) {
5173 lpt_disable_pch_transcoder(dev_priv
);
5174 intel_ddi_fdi_disable(crtc
);
5177 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5178 if (encoder
->post_disable
)
5179 encoder
->post_disable(encoder
);
5181 intel_crtc
->active
= false;
5182 intel_update_watermarks(crtc
);
5184 mutex_lock(&dev
->struct_mutex
);
5185 intel_fbc_update(dev
);
5186 mutex_unlock(&dev
->struct_mutex
);
5188 if (intel_crtc_to_shared_dpll(intel_crtc
))
5189 intel_disable_shared_dpll(intel_crtc
);
5192 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
5194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5195 intel_put_shared_dpll(intel_crtc
);
5199 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5201 struct drm_device
*dev
= crtc
->base
.dev
;
5202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5203 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5205 if (!pipe_config
->gmch_pfit
.control
)
5209 * The panel fitter should only be adjusted whilst the pipe is disabled,
5210 * according to register description and PRM.
5212 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5213 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5215 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5216 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5218 /* Border color in case we don't scale up to the full screen. Black by
5219 * default, change to something else for debugging. */
5220 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5223 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5227 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5229 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5231 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5233 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5236 return POWER_DOMAIN_PORT_OTHER
;
5240 #define for_each_power_domain(domain, mask) \
5241 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5242 if ((1 << (domain)) & (mask))
5244 enum intel_display_power_domain
5245 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5247 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5248 struct intel_digital_port
*intel_dig_port
;
5250 switch (intel_encoder
->type
) {
5251 case INTEL_OUTPUT_UNKNOWN
:
5252 /* Only DDI platforms should ever use this output type */
5253 WARN_ON_ONCE(!HAS_DDI(dev
));
5254 case INTEL_OUTPUT_DISPLAYPORT
:
5255 case INTEL_OUTPUT_HDMI
:
5256 case INTEL_OUTPUT_EDP
:
5257 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5258 return port_to_power_domain(intel_dig_port
->port
);
5259 case INTEL_OUTPUT_DP_MST
:
5260 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5261 return port_to_power_domain(intel_dig_port
->port
);
5262 case INTEL_OUTPUT_ANALOG
:
5263 return POWER_DOMAIN_PORT_CRT
;
5264 case INTEL_OUTPUT_DSI
:
5265 return POWER_DOMAIN_PORT_DSI
;
5267 return POWER_DOMAIN_PORT_OTHER
;
5271 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5273 struct drm_device
*dev
= crtc
->dev
;
5274 struct intel_encoder
*intel_encoder
;
5275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5276 enum pipe pipe
= intel_crtc
->pipe
;
5278 enum transcoder transcoder
;
5280 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5282 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5283 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5284 if (intel_crtc
->config
->pch_pfit
.enabled
||
5285 intel_crtc
->config
->pch_pfit
.force_thru
)
5286 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5288 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5289 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5294 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5296 struct drm_device
*dev
= state
->dev
;
5297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5298 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
5299 struct intel_crtc
*crtc
;
5302 * First get all needed power domains, then put all unneeded, to avoid
5303 * any unnecessary toggling of the power wells.
5305 for_each_intel_crtc(dev
, crtc
) {
5306 enum intel_display_power_domain domain
;
5308 if (!crtc
->base
.state
->enable
)
5311 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5313 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5314 intel_display_power_get(dev_priv
, domain
);
5317 if (dev_priv
->display
.modeset_global_resources
)
5318 dev_priv
->display
.modeset_global_resources(state
);
5320 for_each_intel_crtc(dev
, crtc
) {
5321 enum intel_display_power_domain domain
;
5323 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5324 intel_display_power_put(dev_priv
, domain
);
5326 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5329 intel_display_set_init_power(dev_priv
, false);
5332 void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5337 uint32_t current_freq
;
5340 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5341 switch (frequency
) {
5343 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5344 ratio
= BXT_DE_PLL_RATIO(60);
5347 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5348 ratio
= BXT_DE_PLL_RATIO(60);
5351 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5352 ratio
= BXT_DE_PLL_RATIO(60);
5355 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5356 ratio
= BXT_DE_PLL_RATIO(60);
5359 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5360 ratio
= BXT_DE_PLL_RATIO(65);
5364 * Bypass frequency with DE PLL disabled. Init ratio, divider
5365 * to suppress GCC warning.
5371 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5376 mutex_lock(&dev_priv
->rps
.hw_lock
);
5377 /* Inform power controller of upcoming frequency change */
5378 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5380 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5383 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5388 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5389 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5390 current_freq
= current_freq
* 500 + 1000;
5393 * DE PLL has to be disabled when
5394 * - setting to 19.2MHz (bypass, PLL isn't used)
5395 * - before setting to 624MHz (PLL needs toggling)
5396 * - before setting to any frequency from 624MHz (PLL needs toggling)
5398 if (frequency
== 19200 || frequency
== 624000 ||
5399 current_freq
== 624000) {
5400 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5402 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5404 DRM_ERROR("timout waiting for DE PLL unlock\n");
5407 if (frequency
!= 19200) {
5410 val
= I915_READ(BXT_DE_PLL_CTL
);
5411 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5413 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5415 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5417 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5418 DRM_ERROR("timeout waiting for DE PLL lock\n");
5420 val
= I915_READ(CDCLK_CTL
);
5421 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5424 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5427 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5428 if (frequency
>= 500000)
5429 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5431 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5432 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5433 val
|= (frequency
- 1000) / 500;
5434 I915_WRITE(CDCLK_CTL
, val
);
5437 mutex_lock(&dev_priv
->rps
.hw_lock
);
5438 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5439 DIV_ROUND_UP(frequency
, 25000));
5440 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5443 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5448 dev_priv
->cdclk_freq
= frequency
;
5451 void broxton_init_cdclk(struct drm_device
*dev
)
5453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5457 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5458 * or else the reset will hang because there is no PCH to respond.
5459 * Move the handshake programming to initialization sequence.
5460 * Previously was left up to BIOS.
5462 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5463 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5464 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5466 /* Enable PG1 for cdclk */
5467 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5469 /* check if cd clock is enabled */
5470 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5471 DRM_DEBUG_KMS("Display already initialized\n");
5477 * - The initial CDCLK needs to be read from VBT.
5478 * Need to make this change after VBT has changes for BXT.
5479 * - check if setting the max (or any) cdclk freq is really necessary
5480 * here, it belongs to modeset time
5482 broxton_set_cdclk(dev
, 624000);
5484 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5485 POSTING_READ(DBUF_CTL
);
5489 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5490 DRM_ERROR("DBuf power enable timeout!\n");
5493 void broxton_uninit_cdclk(struct drm_device
*dev
)
5495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5497 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5498 POSTING_READ(DBUF_CTL
);
5502 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5503 DRM_ERROR("DBuf power disable timeout!\n");
5505 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5506 broxton_set_cdclk(dev
, 19200);
5508 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5511 /* returns HPLL frequency in kHz */
5512 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5514 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5516 /* Obtain SKU information */
5517 mutex_lock(&dev_priv
->dpio_lock
);
5518 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5519 CCK_FUSE_HPLL_FREQ_MASK
;
5520 mutex_unlock(&dev_priv
->dpio_lock
);
5522 return vco_freq
[hpll_freq
] * 1000;
5525 static void vlv_update_cdclk(struct drm_device
*dev
)
5527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5529 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5530 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5531 dev_priv
->cdclk_freq
);
5534 * Program the gmbus_freq based on the cdclk frequency.
5535 * BSpec erroneously claims we should aim for 4MHz, but
5536 * in fact 1MHz is the correct frequency.
5538 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5541 /* Adjust CDclk dividers to allow high res or save power if possible */
5542 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5547 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5548 != dev_priv
->cdclk_freq
);
5550 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5552 else if (cdclk
== 266667)
5557 mutex_lock(&dev_priv
->rps
.hw_lock
);
5558 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5559 val
&= ~DSPFREQGUAR_MASK
;
5560 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5561 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5562 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5563 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5565 DRM_ERROR("timed out waiting for CDclk change\n");
5567 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5569 if (cdclk
== 400000) {
5572 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5574 mutex_lock(&dev_priv
->dpio_lock
);
5575 /* adjust cdclk divider */
5576 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5577 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5579 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5581 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5582 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5584 DRM_ERROR("timed out waiting for CDclk change\n");
5585 mutex_unlock(&dev_priv
->dpio_lock
);
5588 mutex_lock(&dev_priv
->dpio_lock
);
5589 /* adjust self-refresh exit latency value */
5590 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5594 * For high bandwidth configs, we set a higher latency in the bunit
5595 * so that the core display fetch happens in time to avoid underruns.
5597 if (cdclk
== 400000)
5598 val
|= 4500 / 250; /* 4.5 usec */
5600 val
|= 3000 / 250; /* 3.0 usec */
5601 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5602 mutex_unlock(&dev_priv
->dpio_lock
);
5604 vlv_update_cdclk(dev
);
5607 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5612 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5613 != dev_priv
->cdclk_freq
);
5622 MISSING_CASE(cdclk
);
5627 * Specs are full of misinformation, but testing on actual
5628 * hardware has shown that we just need to write the desired
5629 * CCK divider into the Punit register.
5631 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5633 mutex_lock(&dev_priv
->rps
.hw_lock
);
5634 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5635 val
&= ~DSPFREQGUAR_MASK_CHV
;
5636 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5637 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5638 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5639 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5641 DRM_ERROR("timed out waiting for CDclk change\n");
5643 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5645 vlv_update_cdclk(dev
);
5648 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5651 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5652 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5655 * Really only a few cases to deal with, as only 4 CDclks are supported:
5658 * 320/333MHz (depends on HPLL freq)
5660 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5661 * of the lower bin and adjust if needed.
5663 * We seem to get an unstable or solid color picture at 200MHz.
5664 * Not sure what's wrong. For now use 200MHz only when all pipes
5667 if (!IS_CHERRYVIEW(dev_priv
) &&
5668 max_pixclk
> freq_320
*limit
/100)
5670 else if (max_pixclk
> 266667*limit
/100)
5672 else if (max_pixclk
> 0)
5678 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5683 * - remove the guardband, it's not needed on BXT
5684 * - set 19.2MHz bypass frequency if there are no active pipes
5686 if (max_pixclk
> 576000*9/10)
5688 else if (max_pixclk
> 384000*9/10)
5690 else if (max_pixclk
> 288000*9/10)
5692 else if (max_pixclk
> 144000*9/10)
5698 /* compute the max pixel clock for new configuration */
5699 static int intel_mode_max_pixclk(struct drm_atomic_state
*state
)
5701 struct drm_device
*dev
= state
->dev
;
5702 struct intel_crtc
*intel_crtc
;
5703 struct intel_crtc_state
*crtc_state
;
5706 for_each_intel_crtc(dev
, intel_crtc
) {
5707 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
5708 if (IS_ERR(crtc_state
))
5709 return PTR_ERR(crtc_state
);
5711 if (!crtc_state
->base
.enable
)
5714 max_pixclk
= max(max_pixclk
,
5715 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5721 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
,
5722 unsigned *prepare_pipes
)
5724 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
5725 struct intel_crtc
*intel_crtc
;
5726 int max_pixclk
= intel_mode_max_pixclk(state
);
5732 if (IS_VALLEYVIEW(dev_priv
))
5733 cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5735 cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
5737 if (cdclk
== dev_priv
->cdclk_freq
)
5740 /* disable/enable all currently active pipes while we change cdclk */
5741 for_each_intel_crtc(state
->dev
, intel_crtc
)
5742 if (intel_crtc
->base
.state
->enable
)
5743 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
5748 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5750 unsigned int credits
, default_credits
;
5752 if (IS_CHERRYVIEW(dev_priv
))
5753 default_credits
= PFI_CREDIT(12);
5755 default_credits
= PFI_CREDIT(8);
5757 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5758 /* CHV suggested value is 31 or 63 */
5759 if (IS_CHERRYVIEW(dev_priv
))
5760 credits
= PFI_CREDIT_31
;
5762 credits
= PFI_CREDIT(15);
5764 credits
= default_credits
;
5768 * WA - write default credits before re-programming
5769 * FIXME: should we also set the resend bit here?
5771 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5774 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5775 credits
| PFI_CREDIT_RESEND
);
5778 * FIXME is this guaranteed to clear
5779 * immediately or should we poll for it?
5781 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
5784 static void valleyview_modeset_global_resources(struct drm_atomic_state
*state
)
5786 struct drm_device
*dev
= state
->dev
;
5787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5788 int max_pixclk
= intel_mode_max_pixclk(state
);
5791 /* The only reason this can fail is if we fail to add the crtc_state
5792 * to the atomic state. But that can't happen since the call to
5793 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5794 * can't have failed otherwise the mode set would be aborted) added all
5795 * the states already. */
5796 if (WARN_ON(max_pixclk
< 0))
5799 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5801 if (req_cdclk
!= dev_priv
->cdclk_freq
) {
5803 * FIXME: We can end up here with all power domains off, yet
5804 * with a CDCLK frequency other than the minimum. To account
5805 * for this take the PIPE-A power domain, which covers the HW
5806 * blocks needed for the following programming. This can be
5807 * removed once it's guaranteed that we get here either with
5808 * the minimum CDCLK set, or the required power domains
5811 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5813 if (IS_CHERRYVIEW(dev
))
5814 cherryview_set_cdclk(dev
, req_cdclk
);
5816 valleyview_set_cdclk(dev
, req_cdclk
);
5818 vlv_program_pfi_credits(dev_priv
);
5820 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5824 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5826 struct drm_device
*dev
= crtc
->dev
;
5827 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5829 struct intel_encoder
*encoder
;
5830 int pipe
= intel_crtc
->pipe
;
5833 WARN_ON(!crtc
->state
->enable
);
5835 if (intel_crtc
->active
)
5838 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5841 if (IS_CHERRYVIEW(dev
))
5842 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5844 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5847 if (intel_crtc
->config
->has_dp_encoder
)
5848 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5850 intel_set_pipe_timings(intel_crtc
);
5852 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5855 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5856 I915_WRITE(CHV_CANVAS(pipe
), 0);
5859 i9xx_set_pipeconf(intel_crtc
);
5861 intel_crtc
->active
= true;
5863 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5865 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5866 if (encoder
->pre_pll_enable
)
5867 encoder
->pre_pll_enable(encoder
);
5870 if (IS_CHERRYVIEW(dev
))
5871 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5873 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5876 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5877 if (encoder
->pre_enable
)
5878 encoder
->pre_enable(encoder
);
5880 i9xx_pfit_enable(intel_crtc
);
5882 intel_crtc_load_lut(crtc
);
5884 intel_update_watermarks(crtc
);
5885 intel_enable_pipe(intel_crtc
);
5887 assert_vblank_disabled(crtc
);
5888 drm_crtc_vblank_on(crtc
);
5890 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5891 encoder
->enable(encoder
);
5893 intel_crtc_enable_planes(crtc
);
5895 /* Underruns don't raise interrupts, so check manually. */
5896 i9xx_check_fifo_underruns(dev_priv
);
5899 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5901 struct drm_device
*dev
= crtc
->base
.dev
;
5902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5904 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5905 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5908 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5910 struct drm_device
*dev
= crtc
->dev
;
5911 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5913 struct intel_encoder
*encoder
;
5914 int pipe
= intel_crtc
->pipe
;
5916 WARN_ON(!crtc
->state
->enable
);
5918 if (intel_crtc
->active
)
5921 i9xx_set_pll_dividers(intel_crtc
);
5923 if (intel_crtc
->config
->has_dp_encoder
)
5924 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5926 intel_set_pipe_timings(intel_crtc
);
5928 i9xx_set_pipeconf(intel_crtc
);
5930 intel_crtc
->active
= true;
5933 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5935 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5936 if (encoder
->pre_enable
)
5937 encoder
->pre_enable(encoder
);
5939 i9xx_enable_pll(intel_crtc
);
5941 i9xx_pfit_enable(intel_crtc
);
5943 intel_crtc_load_lut(crtc
);
5945 intel_update_watermarks(crtc
);
5946 intel_enable_pipe(intel_crtc
);
5948 assert_vblank_disabled(crtc
);
5949 drm_crtc_vblank_on(crtc
);
5951 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5952 encoder
->enable(encoder
);
5954 intel_crtc_enable_planes(crtc
);
5957 * Gen2 reports pipe underruns whenever all planes are disabled.
5958 * So don't enable underrun reporting before at least some planes
5960 * FIXME: Need to fix the logic to work when we turn off all planes
5961 * but leave the pipe running.
5964 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5966 /* Underruns don't raise interrupts, so check manually. */
5967 i9xx_check_fifo_underruns(dev_priv
);
5970 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5972 struct drm_device
*dev
= crtc
->base
.dev
;
5973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5975 if (!crtc
->config
->gmch_pfit
.control
)
5978 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5980 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5981 I915_READ(PFIT_CONTROL
));
5982 I915_WRITE(PFIT_CONTROL
, 0);
5985 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5987 struct drm_device
*dev
= crtc
->dev
;
5988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5990 struct intel_encoder
*encoder
;
5991 int pipe
= intel_crtc
->pipe
;
5993 if (!intel_crtc
->active
)
5997 * Gen2 reports pipe underruns whenever all planes are disabled.
5998 * So diasble underrun reporting before all the planes get disabled.
5999 * FIXME: Need to fix the logic to work when we turn off all planes
6000 * but leave the pipe running.
6003 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6006 * Vblank time updates from the shadow to live plane control register
6007 * are blocked if the memory self-refresh mode is active at that
6008 * moment. So to make sure the plane gets truly disabled, disable
6009 * first the self-refresh mode. The self-refresh enable bit in turn
6010 * will be checked/applied by the HW only at the next frame start
6011 * event which is after the vblank start event, so we need to have a
6012 * wait-for-vblank between disabling the plane and the pipe.
6014 intel_set_memory_cxsr(dev_priv
, false);
6015 intel_crtc_disable_planes(crtc
);
6018 * On gen2 planes are double buffered but the pipe isn't, so we must
6019 * wait for planes to fully turn off before disabling the pipe.
6020 * We also need to wait on all gmch platforms because of the
6021 * self-refresh mode constraint explained above.
6023 intel_wait_for_vblank(dev
, pipe
);
6025 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6026 encoder
->disable(encoder
);
6028 drm_crtc_vblank_off(crtc
);
6029 assert_vblank_disabled(crtc
);
6031 intel_disable_pipe(intel_crtc
);
6033 i9xx_pfit_disable(intel_crtc
);
6035 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6036 if (encoder
->post_disable
)
6037 encoder
->post_disable(encoder
);
6039 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6040 if (IS_CHERRYVIEW(dev
))
6041 chv_disable_pll(dev_priv
, pipe
);
6042 else if (IS_VALLEYVIEW(dev
))
6043 vlv_disable_pll(dev_priv
, pipe
);
6045 i9xx_disable_pll(intel_crtc
);
6049 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6051 intel_crtc
->active
= false;
6052 intel_update_watermarks(crtc
);
6054 mutex_lock(&dev
->struct_mutex
);
6055 intel_fbc_update(dev
);
6056 mutex_unlock(&dev
->struct_mutex
);
6059 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
6063 /* Master function to enable/disable CRTC and corresponding power wells */
6064 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
6066 struct drm_device
*dev
= crtc
->dev
;
6067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6068 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6069 enum intel_display_power_domain domain
;
6070 unsigned long domains
;
6073 if (!intel_crtc
->active
) {
6074 domains
= get_crtc_power_domains(crtc
);
6075 for_each_power_domain(domain
, domains
)
6076 intel_display_power_get(dev_priv
, domain
);
6077 intel_crtc
->enabled_power_domains
= domains
;
6079 dev_priv
->display
.crtc_enable(crtc
);
6082 if (intel_crtc
->active
) {
6083 dev_priv
->display
.crtc_disable(crtc
);
6085 domains
= intel_crtc
->enabled_power_domains
;
6086 for_each_power_domain(domain
, domains
)
6087 intel_display_power_put(dev_priv
, domain
);
6088 intel_crtc
->enabled_power_domains
= 0;
6094 * Sets the power management mode of the pipe and plane.
6096 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
6098 struct drm_device
*dev
= crtc
->dev
;
6099 struct intel_encoder
*intel_encoder
;
6100 bool enable
= false;
6102 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
6103 enable
|= intel_encoder
->connectors_active
;
6105 intel_crtc_control(crtc
, enable
);
6108 static void intel_crtc_disable(struct drm_crtc
*crtc
)
6110 struct drm_device
*dev
= crtc
->dev
;
6111 struct drm_connector
*connector
;
6112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6114 /* crtc should still be enabled when we disable it. */
6115 WARN_ON(!crtc
->state
->enable
);
6117 dev_priv
->display
.crtc_disable(crtc
);
6118 dev_priv
->display
.off(crtc
);
6120 drm_plane_helper_disable(crtc
->primary
);
6122 /* Update computed state. */
6123 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6124 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6127 if (connector
->encoder
->crtc
!= crtc
)
6130 connector
->dpms
= DRM_MODE_DPMS_OFF
;
6131 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
6135 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6137 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6139 drm_encoder_cleanup(encoder
);
6140 kfree(intel_encoder
);
6143 /* Simple dpms helper for encoders with just one connector, no cloning and only
6144 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6145 * state of the entire output pipe. */
6146 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
6148 if (mode
== DRM_MODE_DPMS_ON
) {
6149 encoder
->connectors_active
= true;
6151 intel_crtc_update_dpms(encoder
->base
.crtc
);
6153 encoder
->connectors_active
= false;
6155 intel_crtc_update_dpms(encoder
->base
.crtc
);
6159 /* Cross check the actual hw state with our own modeset state tracking (and it's
6160 * internal consistency). */
6161 static void intel_connector_check_state(struct intel_connector
*connector
)
6163 if (connector
->get_hw_state(connector
)) {
6164 struct intel_encoder
*encoder
= connector
->encoder
;
6165 struct drm_crtc
*crtc
;
6166 bool encoder_enabled
;
6169 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6170 connector
->base
.base
.id
,
6171 connector
->base
.name
);
6173 /* there is no real hw state for MST connectors */
6174 if (connector
->mst_port
)
6177 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
6178 "wrong connector dpms state\n");
6179 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
6180 "active connector not linked to encoder\n");
6183 I915_STATE_WARN(!encoder
->connectors_active
,
6184 "encoder->connectors_active not set\n");
6186 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
6187 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
6188 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
6191 crtc
= encoder
->base
.crtc
;
6193 I915_STATE_WARN(!crtc
->state
->enable
,
6194 "crtc not enabled\n");
6195 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
6196 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
6197 "encoder active on the wrong pipe\n");
6202 int intel_connector_init(struct intel_connector
*connector
)
6204 struct drm_connector_state
*connector_state
;
6206 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6207 if (!connector_state
)
6210 connector
->base
.state
= connector_state
;
6214 struct intel_connector
*intel_connector_alloc(void)
6216 struct intel_connector
*connector
;
6218 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6222 if (intel_connector_init(connector
) < 0) {
6230 /* Even simpler default implementation, if there's really no special case to
6232 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
6234 /* All the simple cases only support two dpms states. */
6235 if (mode
!= DRM_MODE_DPMS_ON
)
6236 mode
= DRM_MODE_DPMS_OFF
;
6238 if (mode
== connector
->dpms
)
6241 connector
->dpms
= mode
;
6243 /* Only need to change hw state when actually enabled */
6244 if (connector
->encoder
)
6245 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
6247 intel_modeset_check_state(connector
->dev
);
6250 /* Simple connector->get_hw_state implementation for encoders that support only
6251 * one connector and no cloning and hence the encoder state determines the state
6252 * of the connector. */
6253 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6256 struct intel_encoder
*encoder
= connector
->encoder
;
6258 return encoder
->get_hw_state(encoder
, &pipe
);
6261 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6263 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6264 return crtc_state
->fdi_lanes
;
6269 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6270 struct intel_crtc_state
*pipe_config
)
6272 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6273 struct intel_crtc
*other_crtc
;
6274 struct intel_crtc_state
*other_crtc_state
;
6276 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6277 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6278 if (pipe_config
->fdi_lanes
> 4) {
6279 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6280 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6284 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6285 if (pipe_config
->fdi_lanes
> 2) {
6286 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6287 pipe_config
->fdi_lanes
);
6294 if (INTEL_INFO(dev
)->num_pipes
== 2)
6297 /* Ivybridge 3 pipe is really complicated */
6302 if (pipe_config
->fdi_lanes
<= 2)
6305 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6307 intel_atomic_get_crtc_state(state
, other_crtc
);
6308 if (IS_ERR(other_crtc_state
))
6309 return PTR_ERR(other_crtc_state
);
6311 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6312 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6313 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6318 if (pipe_config
->fdi_lanes
> 2) {
6319 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6320 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6324 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6326 intel_atomic_get_crtc_state(state
, other_crtc
);
6327 if (IS_ERR(other_crtc_state
))
6328 return PTR_ERR(other_crtc_state
);
6330 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6331 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6341 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6342 struct intel_crtc_state
*pipe_config
)
6344 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6345 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6346 int lane
, link_bw
, fdi_dotclock
, ret
;
6347 bool needs_recompute
= false;
6350 /* FDI is a binary signal running at ~2.7GHz, encoding
6351 * each output octet as 10 bits. The actual frequency
6352 * is stored as a divider into a 100MHz clock, and the
6353 * mode pixel clock is stored in units of 1KHz.
6354 * Hence the bw of each lane in terms of the mode signal
6357 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6359 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6361 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6362 pipe_config
->pipe_bpp
);
6364 pipe_config
->fdi_lanes
= lane
;
6366 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6367 link_bw
, &pipe_config
->fdi_m_n
);
6369 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6370 intel_crtc
->pipe
, pipe_config
);
6371 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6372 pipe_config
->pipe_bpp
-= 2*3;
6373 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6374 pipe_config
->pipe_bpp
);
6375 needs_recompute
= true;
6376 pipe_config
->bw_constrained
= true;
6381 if (needs_recompute
)
6387 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6388 struct intel_crtc_state
*pipe_config
)
6390 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6391 hsw_crtc_supports_ips(crtc
) &&
6392 pipe_config
->pipe_bpp
<= 24;
6395 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6396 struct intel_crtc_state
*pipe_config
)
6398 struct drm_device
*dev
= crtc
->base
.dev
;
6399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6400 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6403 /* FIXME should check pixel clock limits on all platforms */
6404 if (INTEL_INFO(dev
)->gen
< 4) {
6406 dev_priv
->display
.get_display_clock_speed(dev
);
6409 * Enable pixel doubling when the dot clock
6410 * is > 90% of the (display) core speed.
6412 * GDG double wide on either pipe,
6413 * otherwise pipe A only.
6415 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6416 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6418 pipe_config
->double_wide
= true;
6421 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6426 * Pipe horizontal size must be even in:
6428 * - LVDS dual channel mode
6429 * - Double wide pipe
6431 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6432 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6433 pipe_config
->pipe_src_w
&= ~1;
6435 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6436 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6438 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6439 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6443 hsw_compute_ips_config(crtc
, pipe_config
);
6445 if (pipe_config
->has_pch_encoder
)
6446 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6448 /* FIXME: remove below call once atomic mode set is place and all crtc
6449 * related checks called from atomic_crtc_check function */
6451 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6452 crtc
, pipe_config
->base
.state
);
6453 ret
= intel_atomic_setup_scalers(dev
, crtc
, pipe_config
);
6458 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6460 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6461 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6462 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6465 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
6466 WARN(1, "LCPLL1 not enabled\n");
6467 return 24000; /* 24MHz is the cd freq with NSSC ref */
6470 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6473 linkrate
= (I915_READ(DPLL_CTRL1
) &
6474 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6476 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6477 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6479 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6480 case CDCLK_FREQ_450_432
:
6482 case CDCLK_FREQ_337_308
:
6484 case CDCLK_FREQ_675_617
:
6487 WARN(1, "Unknown cd freq selection\n");
6491 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6492 case CDCLK_FREQ_450_432
:
6494 case CDCLK_FREQ_337_308
:
6496 case CDCLK_FREQ_675_617
:
6499 WARN(1, "Unknown cd freq selection\n");
6503 /* error case, do as if DPLL0 isn't enabled */
6507 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6510 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6511 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6513 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6515 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6517 else if (freq
== LCPLL_CLK_FREQ_450
)
6519 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6521 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6527 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6530 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6531 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6533 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6535 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6537 else if (freq
== LCPLL_CLK_FREQ_450
)
6539 else if (IS_HSW_ULT(dev
))
6545 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6551 if (dev_priv
->hpll_freq
== 0)
6552 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6554 mutex_lock(&dev_priv
->dpio_lock
);
6555 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6556 mutex_unlock(&dev_priv
->dpio_lock
);
6558 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6560 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6561 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6562 "cdclk change in progress\n");
6564 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6567 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6572 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6577 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6582 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6587 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6591 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6593 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6594 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6596 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6598 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6600 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6603 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6604 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6606 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6611 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6615 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6617 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6620 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6621 case GC_DISPLAY_CLOCK_333_MHZ
:
6624 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6630 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6635 static int i855_get_display_clock_speed(struct drm_device
*dev
)
6638 /* Assume that the hardware is in the high speed state. This
6639 * should be the default.
6641 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6642 case GC_CLOCK_133_200
:
6643 case GC_CLOCK_100_200
:
6645 case GC_CLOCK_166_250
:
6647 case GC_CLOCK_100_133
:
6651 /* Shouldn't happen */
6655 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6661 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6663 while (*num
> DATA_LINK_M_N_MASK
||
6664 *den
> DATA_LINK_M_N_MASK
) {
6670 static void compute_m_n(unsigned int m
, unsigned int n
,
6671 uint32_t *ret_m
, uint32_t *ret_n
)
6673 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6674 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6675 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6679 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6680 int pixel_clock
, int link_clock
,
6681 struct intel_link_m_n
*m_n
)
6685 compute_m_n(bits_per_pixel
* pixel_clock
,
6686 link_clock
* nlanes
* 8,
6687 &m_n
->gmch_m
, &m_n
->gmch_n
);
6689 compute_m_n(pixel_clock
, link_clock
,
6690 &m_n
->link_m
, &m_n
->link_n
);
6693 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6695 if (i915
.panel_use_ssc
>= 0)
6696 return i915
.panel_use_ssc
!= 0;
6697 return dev_priv
->vbt
.lvds_use_ssc
6698 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6701 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
6704 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
6705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6708 WARN_ON(!crtc_state
->base
.state
);
6710 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
6712 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6713 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6714 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
6715 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
6716 } else if (!IS_GEN2(dev
)) {
6725 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6727 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6730 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6732 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6735 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6736 struct intel_crtc_state
*crtc_state
,
6737 intel_clock_t
*reduced_clock
)
6739 struct drm_device
*dev
= crtc
->base
.dev
;
6742 if (IS_PINEVIEW(dev
)) {
6743 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6745 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6747 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6749 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6752 crtc_state
->dpll_hw_state
.fp0
= fp
;
6754 crtc
->lowfreq_avail
= false;
6755 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6757 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6758 crtc
->lowfreq_avail
= true;
6760 crtc_state
->dpll_hw_state
.fp1
= fp
;
6764 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6770 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6771 * and set it to a reasonable value instead.
6773 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6774 reg_val
&= 0xffffff00;
6775 reg_val
|= 0x00000030;
6776 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6778 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6779 reg_val
&= 0x8cffffff;
6780 reg_val
= 0x8c000000;
6781 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6783 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6784 reg_val
&= 0xffffff00;
6785 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6787 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6788 reg_val
&= 0x00ffffff;
6789 reg_val
|= 0xb0000000;
6790 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6793 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6794 struct intel_link_m_n
*m_n
)
6796 struct drm_device
*dev
= crtc
->base
.dev
;
6797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6798 int pipe
= crtc
->pipe
;
6800 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6801 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6802 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6803 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6806 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6807 struct intel_link_m_n
*m_n
,
6808 struct intel_link_m_n
*m2_n2
)
6810 struct drm_device
*dev
= crtc
->base
.dev
;
6811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6812 int pipe
= crtc
->pipe
;
6813 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6815 if (INTEL_INFO(dev
)->gen
>= 5) {
6816 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6817 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6818 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6819 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6820 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6821 * for gen < 8) and if DRRS is supported (to make sure the
6822 * registers are not unnecessarily accessed).
6824 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
6825 crtc
->config
->has_drrs
) {
6826 I915_WRITE(PIPE_DATA_M2(transcoder
),
6827 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6828 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6829 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6830 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6833 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6834 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6835 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6836 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6840 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6842 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6845 dp_m_n
= &crtc
->config
->dp_m_n
;
6846 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6847 } else if (m_n
== M2_N2
) {
6850 * M2_N2 registers are not supported. Hence m2_n2 divider value
6851 * needs to be programmed into M1_N1.
6853 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6855 DRM_ERROR("Unsupported divider value\n");
6859 if (crtc
->config
->has_pch_encoder
)
6860 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6862 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6865 static void vlv_update_pll(struct intel_crtc
*crtc
,
6866 struct intel_crtc_state
*pipe_config
)
6871 * Enable DPIO clock input. We should never disable the reference
6872 * clock for pipe B, since VGA hotplug / manual detection depends
6875 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
6876 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
6877 /* We should never disable this, set it here for state tracking */
6878 if (crtc
->pipe
== PIPE_B
)
6879 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6880 dpll
|= DPLL_VCO_ENABLE
;
6881 pipe_config
->dpll_hw_state
.dpll
= dpll
;
6883 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
6884 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6885 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6888 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6889 const struct intel_crtc_state
*pipe_config
)
6891 struct drm_device
*dev
= crtc
->base
.dev
;
6892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6893 int pipe
= crtc
->pipe
;
6895 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6896 u32 coreclk
, reg_val
;
6898 mutex_lock(&dev_priv
->dpio_lock
);
6900 bestn
= pipe_config
->dpll
.n
;
6901 bestm1
= pipe_config
->dpll
.m1
;
6902 bestm2
= pipe_config
->dpll
.m2
;
6903 bestp1
= pipe_config
->dpll
.p1
;
6904 bestp2
= pipe_config
->dpll
.p2
;
6906 /* See eDP HDMI DPIO driver vbios notes doc */
6908 /* PLL B needs special handling */
6910 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6912 /* Set up Tx target for periodic Rcomp update */
6913 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6915 /* Disable target IRef on PLL */
6916 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6917 reg_val
&= 0x00ffffff;
6918 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6920 /* Disable fast lock */
6921 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6923 /* Set idtafcrecal before PLL is enabled */
6924 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6925 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6926 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6927 mdiv
|= (1 << DPIO_K_SHIFT
);
6930 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6931 * but we don't support that).
6932 * Note: don't use the DAC post divider as it seems unstable.
6934 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6935 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6937 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6938 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6940 /* Set HBR and RBR LPF coefficients */
6941 if (pipe_config
->port_clock
== 162000 ||
6942 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
6943 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
6944 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6947 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6950 if (pipe_config
->has_dp_encoder
) {
6951 /* Use SSC source */
6953 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6956 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6958 } else { /* HDMI or VGA */
6959 /* Use bend source */
6961 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6964 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6968 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6969 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6970 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6971 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6972 coreclk
|= 0x01000000;
6973 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6975 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6976 mutex_unlock(&dev_priv
->dpio_lock
);
6979 static void chv_update_pll(struct intel_crtc
*crtc
,
6980 struct intel_crtc_state
*pipe_config
)
6982 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6983 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6985 if (crtc
->pipe
!= PIPE_A
)
6986 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6988 pipe_config
->dpll_hw_state
.dpll_md
=
6989 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6992 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6993 const struct intel_crtc_state
*pipe_config
)
6995 struct drm_device
*dev
= crtc
->base
.dev
;
6996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6997 int pipe
= crtc
->pipe
;
6998 int dpll_reg
= DPLL(crtc
->pipe
);
6999 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7000 u32 loopfilter
, tribuf_calcntr
;
7001 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7005 bestn
= pipe_config
->dpll
.n
;
7006 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7007 bestm1
= pipe_config
->dpll
.m1
;
7008 bestm2
= pipe_config
->dpll
.m2
>> 22;
7009 bestp1
= pipe_config
->dpll
.p1
;
7010 bestp2
= pipe_config
->dpll
.p2
;
7011 vco
= pipe_config
->dpll
.vco
;
7016 * Enable Refclk and SSC
7018 I915_WRITE(dpll_reg
,
7019 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7021 mutex_lock(&dev_priv
->dpio_lock
);
7023 /* p1 and p2 divider */
7024 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7025 5 << DPIO_CHV_S1_DIV_SHIFT
|
7026 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7027 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7028 1 << DPIO_CHV_K_DIV_SHIFT
);
7030 /* Feedback post-divider - m2 */
7031 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7033 /* Feedback refclk divider - n and m1 */
7034 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7035 DPIO_CHV_M1_DIV_BY_2
|
7036 1 << DPIO_CHV_N_DIV_SHIFT
);
7038 /* M2 fraction division */
7040 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7042 /* M2 fraction division enable */
7043 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7044 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7045 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7047 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7048 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7050 /* Program digital lock detect threshold */
7051 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7052 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7053 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7054 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7056 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7057 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7060 if (vco
== 5400000) {
7061 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7062 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7063 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7064 tribuf_calcntr
= 0x9;
7065 } else if (vco
<= 6200000) {
7066 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7067 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7068 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7069 tribuf_calcntr
= 0x9;
7070 } else if (vco
<= 6480000) {
7071 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7072 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7073 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7074 tribuf_calcntr
= 0x8;
7076 /* Not supported. Apply the same limits as in the max case */
7077 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7078 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7079 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7082 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7084 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7085 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7086 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7087 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7090 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7091 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7094 mutex_unlock(&dev_priv
->dpio_lock
);
7098 * vlv_force_pll_on - forcibly enable just the PLL
7099 * @dev_priv: i915 private structure
7100 * @pipe: pipe PLL to enable
7101 * @dpll: PLL configuration
7103 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7104 * in cases where we need the PLL enabled even when @pipe is not going to
7107 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7108 const struct dpll
*dpll
)
7110 struct intel_crtc
*crtc
=
7111 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7112 struct intel_crtc_state pipe_config
= {
7113 .base
.crtc
= &crtc
->base
,
7114 .pixel_multiplier
= 1,
7118 if (IS_CHERRYVIEW(dev
)) {
7119 chv_update_pll(crtc
, &pipe_config
);
7120 chv_prepare_pll(crtc
, &pipe_config
);
7121 chv_enable_pll(crtc
, &pipe_config
);
7123 vlv_update_pll(crtc
, &pipe_config
);
7124 vlv_prepare_pll(crtc
, &pipe_config
);
7125 vlv_enable_pll(crtc
, &pipe_config
);
7130 * vlv_force_pll_off - forcibly disable just the PLL
7131 * @dev_priv: i915 private structure
7132 * @pipe: pipe PLL to disable
7134 * Disable the PLL for @pipe. To be used in cases where we need
7135 * the PLL enabled even when @pipe is not going to be enabled.
7137 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7139 if (IS_CHERRYVIEW(dev
))
7140 chv_disable_pll(to_i915(dev
), pipe
);
7142 vlv_disable_pll(to_i915(dev
), pipe
);
7145 static void i9xx_update_pll(struct intel_crtc
*crtc
,
7146 struct intel_crtc_state
*crtc_state
,
7147 intel_clock_t
*reduced_clock
,
7150 struct drm_device
*dev
= crtc
->base
.dev
;
7151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7154 struct dpll
*clock
= &crtc_state
->dpll
;
7156 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7158 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7159 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7161 dpll
= DPLL_VGA_MODE_DIS
;
7163 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7164 dpll
|= DPLLB_MODE_LVDS
;
7166 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7168 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7169 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7170 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7174 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7176 if (crtc_state
->has_dp_encoder
)
7177 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7179 /* compute bitmask from p1 value */
7180 if (IS_PINEVIEW(dev
))
7181 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7183 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7184 if (IS_G4X(dev
) && reduced_clock
)
7185 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7187 switch (clock
->p2
) {
7189 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7192 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7195 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7198 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7201 if (INTEL_INFO(dev
)->gen
>= 4)
7202 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7204 if (crtc_state
->sdvo_tv_clock
)
7205 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7206 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7207 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7208 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7210 dpll
|= PLL_REF_INPUT_DREFCLK
;
7212 dpll
|= DPLL_VCO_ENABLE
;
7213 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7215 if (INTEL_INFO(dev
)->gen
>= 4) {
7216 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7217 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7218 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7222 static void i8xx_update_pll(struct intel_crtc
*crtc
,
7223 struct intel_crtc_state
*crtc_state
,
7224 intel_clock_t
*reduced_clock
,
7227 struct drm_device
*dev
= crtc
->base
.dev
;
7228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7230 struct dpll
*clock
= &crtc_state
->dpll
;
7232 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7234 dpll
= DPLL_VGA_MODE_DIS
;
7236 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7237 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7240 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7242 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7244 dpll
|= PLL_P2_DIVIDE_BY_4
;
7247 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7248 dpll
|= DPLL_DVO_2X_MODE
;
7250 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7251 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7252 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7254 dpll
|= PLL_REF_INPUT_DREFCLK
;
7256 dpll
|= DPLL_VCO_ENABLE
;
7257 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7260 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7262 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7264 enum pipe pipe
= intel_crtc
->pipe
;
7265 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7266 struct drm_display_mode
*adjusted_mode
=
7267 &intel_crtc
->config
->base
.adjusted_mode
;
7268 uint32_t crtc_vtotal
, crtc_vblank_end
;
7271 /* We need to be careful not to changed the adjusted mode, for otherwise
7272 * the hw state checker will get angry at the mismatch. */
7273 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7274 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7276 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7277 /* the chip adds 2 halflines automatically */
7279 crtc_vblank_end
-= 1;
7281 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7282 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7284 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7285 adjusted_mode
->crtc_htotal
/ 2;
7287 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7290 if (INTEL_INFO(dev
)->gen
> 3)
7291 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7293 I915_WRITE(HTOTAL(cpu_transcoder
),
7294 (adjusted_mode
->crtc_hdisplay
- 1) |
7295 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7296 I915_WRITE(HBLANK(cpu_transcoder
),
7297 (adjusted_mode
->crtc_hblank_start
- 1) |
7298 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7299 I915_WRITE(HSYNC(cpu_transcoder
),
7300 (adjusted_mode
->crtc_hsync_start
- 1) |
7301 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7303 I915_WRITE(VTOTAL(cpu_transcoder
),
7304 (adjusted_mode
->crtc_vdisplay
- 1) |
7305 ((crtc_vtotal
- 1) << 16));
7306 I915_WRITE(VBLANK(cpu_transcoder
),
7307 (adjusted_mode
->crtc_vblank_start
- 1) |
7308 ((crtc_vblank_end
- 1) << 16));
7309 I915_WRITE(VSYNC(cpu_transcoder
),
7310 (adjusted_mode
->crtc_vsync_start
- 1) |
7311 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7313 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7314 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7315 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7317 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7318 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7319 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7321 /* pipesrc controls the size that is scaled from, which should
7322 * always be the user's requested size.
7324 I915_WRITE(PIPESRC(pipe
),
7325 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7326 (intel_crtc
->config
->pipe_src_h
- 1));
7329 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7330 struct intel_crtc_state
*pipe_config
)
7332 struct drm_device
*dev
= crtc
->base
.dev
;
7333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7334 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7337 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7338 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7339 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7340 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7341 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7342 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7343 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7344 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7345 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7347 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7348 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7349 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7350 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7351 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7352 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7353 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7354 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7355 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7357 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7358 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7359 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7360 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7363 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7364 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7365 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7367 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7368 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7371 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7372 struct intel_crtc_state
*pipe_config
)
7374 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7375 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7376 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7377 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7379 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7380 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7381 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7382 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7384 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7386 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7387 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7390 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7392 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7398 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7399 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7400 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7402 if (intel_crtc
->config
->double_wide
)
7403 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7405 /* only g4x and later have fancy bpc/dither controls */
7406 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7407 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7408 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7409 pipeconf
|= PIPECONF_DITHER_EN
|
7410 PIPECONF_DITHER_TYPE_SP
;
7412 switch (intel_crtc
->config
->pipe_bpp
) {
7414 pipeconf
|= PIPECONF_6BPC
;
7417 pipeconf
|= PIPECONF_8BPC
;
7420 pipeconf
|= PIPECONF_10BPC
;
7423 /* Case prevented by intel_choose_pipe_bpp_dither. */
7428 if (HAS_PIPE_CXSR(dev
)) {
7429 if (intel_crtc
->lowfreq_avail
) {
7430 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7431 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7433 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7437 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7438 if (INTEL_INFO(dev
)->gen
< 4 ||
7439 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7440 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7442 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7444 pipeconf
|= PIPECONF_PROGRESSIVE
;
7446 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7447 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7449 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7450 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7453 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7454 struct intel_crtc_state
*crtc_state
)
7456 struct drm_device
*dev
= crtc
->base
.dev
;
7457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7458 int refclk
, num_connectors
= 0;
7459 intel_clock_t clock
, reduced_clock
;
7460 bool ok
, has_reduced_clock
= false;
7461 bool is_lvds
= false, is_dsi
= false;
7462 struct intel_encoder
*encoder
;
7463 const intel_limit_t
*limit
;
7464 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7465 struct drm_connector_state
*connector_state
;
7468 for (i
= 0; i
< state
->num_connector
; i
++) {
7469 if (!state
->connectors
[i
])
7472 connector_state
= state
->connector_states
[i
];
7473 if (connector_state
->crtc
!= &crtc
->base
)
7476 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7478 switch (encoder
->type
) {
7479 case INTEL_OUTPUT_LVDS
:
7482 case INTEL_OUTPUT_DSI
:
7495 if (!crtc_state
->clock_set
) {
7496 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7499 * Returns a set of divisors for the desired target clock with
7500 * the given refclk, or FALSE. The returned values represent
7501 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7504 limit
= intel_limit(crtc_state
, refclk
);
7505 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7506 crtc_state
->port_clock
,
7507 refclk
, NULL
, &clock
);
7509 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7513 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7515 * Ensure we match the reduced clock's P to the target
7516 * clock. If the clocks don't match, we can't switch
7517 * the display clock by using the FP0/FP1. In such case
7518 * we will disable the LVDS downclock feature.
7521 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7522 dev_priv
->lvds_downclock
,
7526 /* Compat-code for transition, will disappear. */
7527 crtc_state
->dpll
.n
= clock
.n
;
7528 crtc_state
->dpll
.m1
= clock
.m1
;
7529 crtc_state
->dpll
.m2
= clock
.m2
;
7530 crtc_state
->dpll
.p1
= clock
.p1
;
7531 crtc_state
->dpll
.p2
= clock
.p2
;
7535 i8xx_update_pll(crtc
, crtc_state
,
7536 has_reduced_clock
? &reduced_clock
: NULL
,
7538 } else if (IS_CHERRYVIEW(dev
)) {
7539 chv_update_pll(crtc
, crtc_state
);
7540 } else if (IS_VALLEYVIEW(dev
)) {
7541 vlv_update_pll(crtc
, crtc_state
);
7543 i9xx_update_pll(crtc
, crtc_state
,
7544 has_reduced_clock
? &reduced_clock
: NULL
,
7551 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7552 struct intel_crtc_state
*pipe_config
)
7554 struct drm_device
*dev
= crtc
->base
.dev
;
7555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7558 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7561 tmp
= I915_READ(PFIT_CONTROL
);
7562 if (!(tmp
& PFIT_ENABLE
))
7565 /* Check whether the pfit is attached to our pipe. */
7566 if (INTEL_INFO(dev
)->gen
< 4) {
7567 if (crtc
->pipe
!= PIPE_B
)
7570 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7574 pipe_config
->gmch_pfit
.control
= tmp
;
7575 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7576 if (INTEL_INFO(dev
)->gen
< 5)
7577 pipe_config
->gmch_pfit
.lvds_border_bits
=
7578 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7581 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7582 struct intel_crtc_state
*pipe_config
)
7584 struct drm_device
*dev
= crtc
->base
.dev
;
7585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7586 int pipe
= pipe_config
->cpu_transcoder
;
7587 intel_clock_t clock
;
7589 int refclk
= 100000;
7591 /* In case of MIPI DPLL will not even be used */
7592 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7595 mutex_lock(&dev_priv
->dpio_lock
);
7596 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7597 mutex_unlock(&dev_priv
->dpio_lock
);
7599 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7600 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7601 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7602 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7603 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7605 vlv_clock(refclk
, &clock
);
7607 /* clock.dot is the fast clock */
7608 pipe_config
->port_clock
= clock
.dot
/ 5;
7612 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7613 struct intel_initial_plane_config
*plane_config
)
7615 struct drm_device
*dev
= crtc
->base
.dev
;
7616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7617 u32 val
, base
, offset
;
7618 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7619 int fourcc
, pixel_format
;
7620 unsigned int aligned_height
;
7621 struct drm_framebuffer
*fb
;
7622 struct intel_framebuffer
*intel_fb
;
7624 val
= I915_READ(DSPCNTR(plane
));
7625 if (!(val
& DISPLAY_PLANE_ENABLE
))
7628 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7630 DRM_DEBUG_KMS("failed to alloc fb\n");
7634 fb
= &intel_fb
->base
;
7636 if (INTEL_INFO(dev
)->gen
>= 4) {
7637 if (val
& DISPPLANE_TILED
) {
7638 plane_config
->tiling
= I915_TILING_X
;
7639 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7643 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7644 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7645 fb
->pixel_format
= fourcc
;
7646 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7648 if (INTEL_INFO(dev
)->gen
>= 4) {
7649 if (plane_config
->tiling
)
7650 offset
= I915_READ(DSPTILEOFF(plane
));
7652 offset
= I915_READ(DSPLINOFF(plane
));
7653 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7655 base
= I915_READ(DSPADDR(plane
));
7657 plane_config
->base
= base
;
7659 val
= I915_READ(PIPESRC(pipe
));
7660 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7661 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7663 val
= I915_READ(DSPSTRIDE(pipe
));
7664 fb
->pitches
[0] = val
& 0xffffffc0;
7666 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7670 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7672 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7673 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7674 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7675 plane_config
->size
);
7677 plane_config
->fb
= intel_fb
;
7680 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7681 struct intel_crtc_state
*pipe_config
)
7683 struct drm_device
*dev
= crtc
->base
.dev
;
7684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7685 int pipe
= pipe_config
->cpu_transcoder
;
7686 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7687 intel_clock_t clock
;
7688 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
7689 int refclk
= 100000;
7691 mutex_lock(&dev_priv
->dpio_lock
);
7692 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7693 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7694 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7695 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7696 mutex_unlock(&dev_priv
->dpio_lock
);
7698 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7699 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
7700 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7701 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7702 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7704 chv_clock(refclk
, &clock
);
7706 /* clock.dot is the fast clock */
7707 pipe_config
->port_clock
= clock
.dot
/ 5;
7710 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7711 struct intel_crtc_state
*pipe_config
)
7713 struct drm_device
*dev
= crtc
->base
.dev
;
7714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7717 if (!intel_display_power_is_enabled(dev_priv
,
7718 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7721 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7722 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7724 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7725 if (!(tmp
& PIPECONF_ENABLE
))
7728 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7729 switch (tmp
& PIPECONF_BPC_MASK
) {
7731 pipe_config
->pipe_bpp
= 18;
7734 pipe_config
->pipe_bpp
= 24;
7736 case PIPECONF_10BPC
:
7737 pipe_config
->pipe_bpp
= 30;
7744 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7745 pipe_config
->limited_color_range
= true;
7747 if (INTEL_INFO(dev
)->gen
< 4)
7748 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7750 intel_get_pipe_timings(crtc
, pipe_config
);
7752 i9xx_get_pfit_config(crtc
, pipe_config
);
7754 if (INTEL_INFO(dev
)->gen
>= 4) {
7755 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7756 pipe_config
->pixel_multiplier
=
7757 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7758 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7759 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7760 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7761 tmp
= I915_READ(DPLL(crtc
->pipe
));
7762 pipe_config
->pixel_multiplier
=
7763 ((tmp
& SDVO_MULTIPLIER_MASK
)
7764 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7766 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7767 * port and will be fixed up in the encoder->get_config
7769 pipe_config
->pixel_multiplier
= 1;
7771 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7772 if (!IS_VALLEYVIEW(dev
)) {
7774 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7775 * on 830. Filter it out here so that we don't
7776 * report errors due to that.
7779 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7781 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7782 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7784 /* Mask out read-only status bits. */
7785 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7786 DPLL_PORTC_READY_MASK
|
7787 DPLL_PORTB_READY_MASK
);
7790 if (IS_CHERRYVIEW(dev
))
7791 chv_crtc_clock_get(crtc
, pipe_config
);
7792 else if (IS_VALLEYVIEW(dev
))
7793 vlv_crtc_clock_get(crtc
, pipe_config
);
7795 i9xx_crtc_clock_get(crtc
, pipe_config
);
7800 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
7802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7803 struct intel_encoder
*encoder
;
7805 bool has_lvds
= false;
7806 bool has_cpu_edp
= false;
7807 bool has_panel
= false;
7808 bool has_ck505
= false;
7809 bool can_ssc
= false;
7811 /* We need to take the global config into account */
7812 for_each_intel_encoder(dev
, encoder
) {
7813 switch (encoder
->type
) {
7814 case INTEL_OUTPUT_LVDS
:
7818 case INTEL_OUTPUT_EDP
:
7820 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7828 if (HAS_PCH_IBX(dev
)) {
7829 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7830 can_ssc
= has_ck505
;
7836 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7837 has_panel
, has_lvds
, has_ck505
);
7839 /* Ironlake: try to setup display ref clock before DPLL
7840 * enabling. This is only under driver's control after
7841 * PCH B stepping, previous chipset stepping should be
7842 * ignoring this setting.
7844 val
= I915_READ(PCH_DREF_CONTROL
);
7846 /* As we must carefully and slowly disable/enable each source in turn,
7847 * compute the final state we want first and check if we need to
7848 * make any changes at all.
7851 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7853 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7855 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7857 final
&= ~DREF_SSC_SOURCE_MASK
;
7858 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7859 final
&= ~DREF_SSC1_ENABLE
;
7862 final
|= DREF_SSC_SOURCE_ENABLE
;
7864 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7865 final
|= DREF_SSC1_ENABLE
;
7868 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7869 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7871 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7873 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7875 final
|= DREF_SSC_SOURCE_DISABLE
;
7876 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7882 /* Always enable nonspread source */
7883 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7886 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7888 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7891 val
&= ~DREF_SSC_SOURCE_MASK
;
7892 val
|= DREF_SSC_SOURCE_ENABLE
;
7894 /* SSC must be turned on before enabling the CPU output */
7895 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7896 DRM_DEBUG_KMS("Using SSC on panel\n");
7897 val
|= DREF_SSC1_ENABLE
;
7899 val
&= ~DREF_SSC1_ENABLE
;
7901 /* Get SSC going before enabling the outputs */
7902 I915_WRITE(PCH_DREF_CONTROL
, val
);
7903 POSTING_READ(PCH_DREF_CONTROL
);
7906 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7908 /* Enable CPU source on CPU attached eDP */
7910 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7911 DRM_DEBUG_KMS("Using SSC on eDP\n");
7912 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7914 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7916 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7918 I915_WRITE(PCH_DREF_CONTROL
, val
);
7919 POSTING_READ(PCH_DREF_CONTROL
);
7922 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7924 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7926 /* Turn off CPU output */
7927 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7929 I915_WRITE(PCH_DREF_CONTROL
, val
);
7930 POSTING_READ(PCH_DREF_CONTROL
);
7933 /* Turn off the SSC source */
7934 val
&= ~DREF_SSC_SOURCE_MASK
;
7935 val
|= DREF_SSC_SOURCE_DISABLE
;
7938 val
&= ~DREF_SSC1_ENABLE
;
7940 I915_WRITE(PCH_DREF_CONTROL
, val
);
7941 POSTING_READ(PCH_DREF_CONTROL
);
7945 BUG_ON(val
!= final
);
7948 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7952 tmp
= I915_READ(SOUTH_CHICKEN2
);
7953 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7954 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7956 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
7957 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7958 DRM_ERROR("FDI mPHY reset assert timeout\n");
7960 tmp
= I915_READ(SOUTH_CHICKEN2
);
7961 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7962 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7964 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
7965 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7966 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7969 /* WaMPhyProgramming:hsw */
7970 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7974 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7975 tmp
&= ~(0xFF << 24);
7976 tmp
|= (0x12 << 24);
7977 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7979 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7981 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7983 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7985 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7987 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7988 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7989 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7991 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7992 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7993 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7995 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
7998 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8000 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8003 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8005 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8008 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8010 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8013 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8015 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8016 tmp
&= ~(0xFF << 16);
8017 tmp
|= (0x1C << 16);
8018 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8020 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8021 tmp
&= ~(0xFF << 16);
8022 tmp
|= (0x1C << 16);
8023 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8025 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8027 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8029 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8031 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8033 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8034 tmp
&= ~(0xF << 28);
8036 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8038 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8039 tmp
&= ~(0xF << 28);
8041 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8044 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8045 * Programming" based on the parameters passed:
8046 * - Sequence to enable CLKOUT_DP
8047 * - Sequence to enable CLKOUT_DP without spread
8048 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8050 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8056 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8058 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
8059 with_fdi
, "LP PCH doesn't have FDI\n"))
8062 mutex_lock(&dev_priv
->dpio_lock
);
8064 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8065 tmp
&= ~SBI_SSCCTL_DISABLE
;
8066 tmp
|= SBI_SSCCTL_PATHALT
;
8067 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8072 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8073 tmp
&= ~SBI_SSCCTL_PATHALT
;
8074 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8077 lpt_reset_fdi_mphy(dev_priv
);
8078 lpt_program_fdi_mphy(dev_priv
);
8082 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8083 SBI_GEN0
: SBI_DBUFF0
;
8084 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8085 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8086 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8088 mutex_unlock(&dev_priv
->dpio_lock
);
8091 /* Sequence to disable CLKOUT_DP */
8092 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8097 mutex_lock(&dev_priv
->dpio_lock
);
8099 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8100 SBI_GEN0
: SBI_DBUFF0
;
8101 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8102 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8103 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8105 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8106 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8107 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8108 tmp
|= SBI_SSCCTL_PATHALT
;
8109 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8112 tmp
|= SBI_SSCCTL_DISABLE
;
8113 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8116 mutex_unlock(&dev_priv
->dpio_lock
);
8119 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8121 struct intel_encoder
*encoder
;
8122 bool has_vga
= false;
8124 for_each_intel_encoder(dev
, encoder
) {
8125 switch (encoder
->type
) {
8126 case INTEL_OUTPUT_ANALOG
:
8135 lpt_enable_clkout_dp(dev
, true, true);
8137 lpt_disable_clkout_dp(dev
);
8141 * Initialize reference clocks when the driver loads
8143 void intel_init_pch_refclk(struct drm_device
*dev
)
8145 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8146 ironlake_init_pch_refclk(dev
);
8147 else if (HAS_PCH_LPT(dev
))
8148 lpt_init_pch_refclk(dev
);
8151 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8153 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8155 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8156 struct drm_connector_state
*connector_state
;
8157 struct intel_encoder
*encoder
;
8158 int num_connectors
= 0, i
;
8159 bool is_lvds
= false;
8161 for (i
= 0; i
< state
->num_connector
; i
++) {
8162 if (!state
->connectors
[i
])
8165 connector_state
= state
->connector_states
[i
];
8166 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8169 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8171 switch (encoder
->type
) {
8172 case INTEL_OUTPUT_LVDS
:
8181 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8182 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8183 dev_priv
->vbt
.lvds_ssc_freq
);
8184 return dev_priv
->vbt
.lvds_ssc_freq
;
8190 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8192 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8194 int pipe
= intel_crtc
->pipe
;
8199 switch (intel_crtc
->config
->pipe_bpp
) {
8201 val
|= PIPECONF_6BPC
;
8204 val
|= PIPECONF_8BPC
;
8207 val
|= PIPECONF_10BPC
;
8210 val
|= PIPECONF_12BPC
;
8213 /* Case prevented by intel_choose_pipe_bpp_dither. */
8217 if (intel_crtc
->config
->dither
)
8218 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8220 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8221 val
|= PIPECONF_INTERLACED_ILK
;
8223 val
|= PIPECONF_PROGRESSIVE
;
8225 if (intel_crtc
->config
->limited_color_range
)
8226 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8228 I915_WRITE(PIPECONF(pipe
), val
);
8229 POSTING_READ(PIPECONF(pipe
));
8233 * Set up the pipe CSC unit.
8235 * Currently only full range RGB to limited range RGB conversion
8236 * is supported, but eventually this should handle various
8237 * RGB<->YCbCr scenarios as well.
8239 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8241 struct drm_device
*dev
= crtc
->dev
;
8242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8243 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8244 int pipe
= intel_crtc
->pipe
;
8245 uint16_t coeff
= 0x7800; /* 1.0 */
8248 * TODO: Check what kind of values actually come out of the pipe
8249 * with these coeff/postoff values and adjust to get the best
8250 * accuracy. Perhaps we even need to take the bpc value into
8254 if (intel_crtc
->config
->limited_color_range
)
8255 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8258 * GY/GU and RY/RU should be the other way around according
8259 * to BSpec, but reality doesn't agree. Just set them up in
8260 * a way that results in the correct picture.
8262 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8263 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8265 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8266 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8268 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8269 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8271 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8272 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8273 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8275 if (INTEL_INFO(dev
)->gen
> 6) {
8276 uint16_t postoff
= 0;
8278 if (intel_crtc
->config
->limited_color_range
)
8279 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8281 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8282 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8283 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8285 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8287 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8289 if (intel_crtc
->config
->limited_color_range
)
8290 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8292 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8296 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8298 struct drm_device
*dev
= crtc
->dev
;
8299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8301 enum pipe pipe
= intel_crtc
->pipe
;
8302 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8307 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8308 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8310 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8311 val
|= PIPECONF_INTERLACED_ILK
;
8313 val
|= PIPECONF_PROGRESSIVE
;
8315 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8316 POSTING_READ(PIPECONF(cpu_transcoder
));
8318 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8319 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8321 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8324 switch (intel_crtc
->config
->pipe_bpp
) {
8326 val
|= PIPEMISC_DITHER_6_BPC
;
8329 val
|= PIPEMISC_DITHER_8_BPC
;
8332 val
|= PIPEMISC_DITHER_10_BPC
;
8335 val
|= PIPEMISC_DITHER_12_BPC
;
8338 /* Case prevented by pipe_config_set_bpp. */
8342 if (intel_crtc
->config
->dither
)
8343 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8345 I915_WRITE(PIPEMISC(pipe
), val
);
8349 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8350 struct intel_crtc_state
*crtc_state
,
8351 intel_clock_t
*clock
,
8352 bool *has_reduced_clock
,
8353 intel_clock_t
*reduced_clock
)
8355 struct drm_device
*dev
= crtc
->dev
;
8356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8358 const intel_limit_t
*limit
;
8359 bool ret
, is_lvds
= false;
8361 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
8363 refclk
= ironlake_get_refclk(crtc_state
);
8366 * Returns a set of divisors for the desired target clock with the given
8367 * refclk, or FALSE. The returned values represent the clock equation:
8368 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8370 limit
= intel_limit(crtc_state
, refclk
);
8371 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8372 crtc_state
->port_clock
,
8373 refclk
, NULL
, clock
);
8377 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
8379 * Ensure we match the reduced clock's P to the target clock.
8380 * If the clocks don't match, we can't switch the display clock
8381 * by using the FP0/FP1. In such case we will disable the LVDS
8382 * downclock feature.
8384 *has_reduced_clock
=
8385 dev_priv
->display
.find_dpll(limit
, crtc_state
,
8386 dev_priv
->lvds_downclock
,
8394 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8397 * Account for spread spectrum to avoid
8398 * oversubscribing the link. Max center spread
8399 * is 2.5%; use 5% for safety's sake.
8401 u32 bps
= target_clock
* bpp
* 21 / 20;
8402 return DIV_ROUND_UP(bps
, link_bw
* 8);
8405 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8407 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8410 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8411 struct intel_crtc_state
*crtc_state
,
8413 intel_clock_t
*reduced_clock
, u32
*fp2
)
8415 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8416 struct drm_device
*dev
= crtc
->dev
;
8417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8418 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8419 struct drm_connector_state
*connector_state
;
8420 struct intel_encoder
*encoder
;
8422 int factor
, num_connectors
= 0, i
;
8423 bool is_lvds
= false, is_sdvo
= false;
8425 for (i
= 0; i
< state
->num_connector
; i
++) {
8426 if (!state
->connectors
[i
])
8429 connector_state
= state
->connector_states
[i
];
8430 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8433 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8435 switch (encoder
->type
) {
8436 case INTEL_OUTPUT_LVDS
:
8439 case INTEL_OUTPUT_SDVO
:
8440 case INTEL_OUTPUT_HDMI
:
8450 /* Enable autotuning of the PLL clock (if permissible) */
8453 if ((intel_panel_use_ssc(dev_priv
) &&
8454 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8455 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8457 } else if (crtc_state
->sdvo_tv_clock
)
8460 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8463 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8469 dpll
|= DPLLB_MODE_LVDS
;
8471 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8473 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8474 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8477 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8478 if (crtc_state
->has_dp_encoder
)
8479 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8481 /* compute bitmask from p1 value */
8482 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8484 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8486 switch (crtc_state
->dpll
.p2
) {
8488 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8491 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8494 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8497 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8501 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8502 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8504 dpll
|= PLL_REF_INPUT_DREFCLK
;
8506 return dpll
| DPLL_VCO_ENABLE
;
8509 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8510 struct intel_crtc_state
*crtc_state
)
8512 struct drm_device
*dev
= crtc
->base
.dev
;
8513 intel_clock_t clock
, reduced_clock
;
8514 u32 dpll
= 0, fp
= 0, fp2
= 0;
8515 bool ok
, has_reduced_clock
= false;
8516 bool is_lvds
= false;
8517 struct intel_shared_dpll
*pll
;
8519 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8521 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8522 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8524 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8525 &has_reduced_clock
, &reduced_clock
);
8526 if (!ok
&& !crtc_state
->clock_set
) {
8527 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8530 /* Compat-code for transition, will disappear. */
8531 if (!crtc_state
->clock_set
) {
8532 crtc_state
->dpll
.n
= clock
.n
;
8533 crtc_state
->dpll
.m1
= clock
.m1
;
8534 crtc_state
->dpll
.m2
= clock
.m2
;
8535 crtc_state
->dpll
.p1
= clock
.p1
;
8536 crtc_state
->dpll
.p2
= clock
.p2
;
8539 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8540 if (crtc_state
->has_pch_encoder
) {
8541 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8542 if (has_reduced_clock
)
8543 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8545 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8546 &fp
, &reduced_clock
,
8547 has_reduced_clock
? &fp2
: NULL
);
8549 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8550 crtc_state
->dpll_hw_state
.fp0
= fp
;
8551 if (has_reduced_clock
)
8552 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8554 crtc_state
->dpll_hw_state
.fp1
= fp
;
8556 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8558 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8559 pipe_name(crtc
->pipe
));
8564 if (is_lvds
&& has_reduced_clock
)
8565 crtc
->lowfreq_avail
= true;
8567 crtc
->lowfreq_avail
= false;
8572 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8573 struct intel_link_m_n
*m_n
)
8575 struct drm_device
*dev
= crtc
->base
.dev
;
8576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8577 enum pipe pipe
= crtc
->pipe
;
8579 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8580 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8581 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8583 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8584 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8585 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8588 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8589 enum transcoder transcoder
,
8590 struct intel_link_m_n
*m_n
,
8591 struct intel_link_m_n
*m2_n2
)
8593 struct drm_device
*dev
= crtc
->base
.dev
;
8594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8595 enum pipe pipe
= crtc
->pipe
;
8597 if (INTEL_INFO(dev
)->gen
>= 5) {
8598 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8599 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8600 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8602 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8603 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8604 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8605 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8606 * gen < 8) and if DRRS is supported (to make sure the
8607 * registers are not unnecessarily read).
8609 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8610 crtc
->config
->has_drrs
) {
8611 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8612 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8613 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8615 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8616 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8617 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8620 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8621 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8622 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8624 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8625 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8626 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8630 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8631 struct intel_crtc_state
*pipe_config
)
8633 if (pipe_config
->has_pch_encoder
)
8634 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8636 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8637 &pipe_config
->dp_m_n
,
8638 &pipe_config
->dp_m2_n2
);
8641 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8642 struct intel_crtc_state
*pipe_config
)
8644 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8645 &pipe_config
->fdi_m_n
, NULL
);
8648 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8649 struct intel_crtc_state
*pipe_config
)
8651 struct drm_device
*dev
= crtc
->base
.dev
;
8652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8653 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8654 uint32_t ps_ctrl
= 0;
8658 /* find scaler attached to this pipe */
8659 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8660 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8661 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8663 pipe_config
->pch_pfit
.enabled
= true;
8664 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8665 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8670 scaler_state
->scaler_id
= id
;
8672 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8674 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8679 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8680 struct intel_initial_plane_config
*plane_config
)
8682 struct drm_device
*dev
= crtc
->base
.dev
;
8683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8684 u32 val
, base
, offset
, stride_mult
, tiling
;
8685 int pipe
= crtc
->pipe
;
8686 int fourcc
, pixel_format
;
8687 unsigned int aligned_height
;
8688 struct drm_framebuffer
*fb
;
8689 struct intel_framebuffer
*intel_fb
;
8691 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8693 DRM_DEBUG_KMS("failed to alloc fb\n");
8697 fb
= &intel_fb
->base
;
8699 val
= I915_READ(PLANE_CTL(pipe
, 0));
8700 if (!(val
& PLANE_CTL_ENABLE
))
8703 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8704 fourcc
= skl_format_to_fourcc(pixel_format
,
8705 val
& PLANE_CTL_ORDER_RGBX
,
8706 val
& PLANE_CTL_ALPHA_MASK
);
8707 fb
->pixel_format
= fourcc
;
8708 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8710 tiling
= val
& PLANE_CTL_TILED_MASK
;
8712 case PLANE_CTL_TILED_LINEAR
:
8713 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8715 case PLANE_CTL_TILED_X
:
8716 plane_config
->tiling
= I915_TILING_X
;
8717 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8719 case PLANE_CTL_TILED_Y
:
8720 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
8722 case PLANE_CTL_TILED_YF
:
8723 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
8726 MISSING_CASE(tiling
);
8730 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8731 plane_config
->base
= base
;
8733 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8735 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8736 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8737 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8739 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8740 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
8742 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8744 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8748 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8750 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8751 pipe_name(pipe
), fb
->width
, fb
->height
,
8752 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8753 plane_config
->size
);
8755 plane_config
->fb
= intel_fb
;
8762 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8763 struct intel_crtc_state
*pipe_config
)
8765 struct drm_device
*dev
= crtc
->base
.dev
;
8766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8769 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8771 if (tmp
& PF_ENABLE
) {
8772 pipe_config
->pch_pfit
.enabled
= true;
8773 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8774 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8776 /* We currently do not free assignements of panel fitters on
8777 * ivb/hsw (since we don't use the higher upscaling modes which
8778 * differentiates them) so just WARN about this case for now. */
8780 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8781 PF_PIPE_SEL_IVB(crtc
->pipe
));
8787 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8788 struct intel_initial_plane_config
*plane_config
)
8790 struct drm_device
*dev
= crtc
->base
.dev
;
8791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8792 u32 val
, base
, offset
;
8793 int pipe
= crtc
->pipe
;
8794 int fourcc
, pixel_format
;
8795 unsigned int aligned_height
;
8796 struct drm_framebuffer
*fb
;
8797 struct intel_framebuffer
*intel_fb
;
8799 val
= I915_READ(DSPCNTR(pipe
));
8800 if (!(val
& DISPLAY_PLANE_ENABLE
))
8803 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8805 DRM_DEBUG_KMS("failed to alloc fb\n");
8809 fb
= &intel_fb
->base
;
8811 if (INTEL_INFO(dev
)->gen
>= 4) {
8812 if (val
& DISPPLANE_TILED
) {
8813 plane_config
->tiling
= I915_TILING_X
;
8814 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8818 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8819 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8820 fb
->pixel_format
= fourcc
;
8821 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8823 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8824 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
8825 offset
= I915_READ(DSPOFFSET(pipe
));
8827 if (plane_config
->tiling
)
8828 offset
= I915_READ(DSPTILEOFF(pipe
));
8830 offset
= I915_READ(DSPLINOFF(pipe
));
8832 plane_config
->base
= base
;
8834 val
= I915_READ(PIPESRC(pipe
));
8835 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8836 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8838 val
= I915_READ(DSPSTRIDE(pipe
));
8839 fb
->pitches
[0] = val
& 0xffffffc0;
8841 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8845 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8847 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8848 pipe_name(pipe
), fb
->width
, fb
->height
,
8849 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8850 plane_config
->size
);
8852 plane_config
->fb
= intel_fb
;
8855 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8856 struct intel_crtc_state
*pipe_config
)
8858 struct drm_device
*dev
= crtc
->base
.dev
;
8859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8862 if (!intel_display_power_is_enabled(dev_priv
,
8863 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8866 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8867 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8869 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8870 if (!(tmp
& PIPECONF_ENABLE
))
8873 switch (tmp
& PIPECONF_BPC_MASK
) {
8875 pipe_config
->pipe_bpp
= 18;
8878 pipe_config
->pipe_bpp
= 24;
8880 case PIPECONF_10BPC
:
8881 pipe_config
->pipe_bpp
= 30;
8883 case PIPECONF_12BPC
:
8884 pipe_config
->pipe_bpp
= 36;
8890 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8891 pipe_config
->limited_color_range
= true;
8893 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8894 struct intel_shared_dpll
*pll
;
8896 pipe_config
->has_pch_encoder
= true;
8898 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8899 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8900 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8902 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8904 if (HAS_PCH_IBX(dev_priv
->dev
)) {
8905 pipe_config
->shared_dpll
=
8906 (enum intel_dpll_id
) crtc
->pipe
;
8908 tmp
= I915_READ(PCH_DPLL_SEL
);
8909 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8910 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
8912 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
8915 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8917 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8918 &pipe_config
->dpll_hw_state
));
8920 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8921 pipe_config
->pixel_multiplier
=
8922 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8923 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8925 ironlake_pch_clock_get(crtc
, pipe_config
);
8927 pipe_config
->pixel_multiplier
= 1;
8930 intel_get_pipe_timings(crtc
, pipe_config
);
8932 ironlake_get_pfit_config(crtc
, pipe_config
);
8937 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8939 struct drm_device
*dev
= dev_priv
->dev
;
8940 struct intel_crtc
*crtc
;
8942 for_each_intel_crtc(dev
, crtc
)
8943 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8944 pipe_name(crtc
->pipe
));
8946 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
8947 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8948 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8949 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8950 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
8951 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8952 "CPU PWM1 enabled\n");
8953 if (IS_HASWELL(dev
))
8954 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8955 "CPU PWM2 enabled\n");
8956 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8957 "PCH PWM1 enabled\n");
8958 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8959 "Utility pin enabled\n");
8960 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8963 * In theory we can still leave IRQs enabled, as long as only the HPD
8964 * interrupts remain enabled. We used to check for that, but since it's
8965 * gen-specific and since we only disable LCPLL after we fully disable
8966 * the interrupts, the check below should be enough.
8968 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8971 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8973 struct drm_device
*dev
= dev_priv
->dev
;
8975 if (IS_HASWELL(dev
))
8976 return I915_READ(D_COMP_HSW
);
8978 return I915_READ(D_COMP_BDW
);
8981 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8983 struct drm_device
*dev
= dev_priv
->dev
;
8985 if (IS_HASWELL(dev
)) {
8986 mutex_lock(&dev_priv
->rps
.hw_lock
);
8987 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8989 DRM_ERROR("Failed to write to D_COMP\n");
8990 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8992 I915_WRITE(D_COMP_BDW
, val
);
8993 POSTING_READ(D_COMP_BDW
);
8998 * This function implements pieces of two sequences from BSpec:
8999 * - Sequence for display software to disable LCPLL
9000 * - Sequence for display software to allow package C8+
9001 * The steps implemented here are just the steps that actually touch the LCPLL
9002 * register. Callers should take care of disabling all the display engine
9003 * functions, doing the mode unset, fixing interrupts, etc.
9005 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9006 bool switch_to_fclk
, bool allow_power_down
)
9010 assert_can_disable_lcpll(dev_priv
);
9012 val
= I915_READ(LCPLL_CTL
);
9014 if (switch_to_fclk
) {
9015 val
|= LCPLL_CD_SOURCE_FCLK
;
9016 I915_WRITE(LCPLL_CTL
, val
);
9018 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9019 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9020 DRM_ERROR("Switching to FCLK failed\n");
9022 val
= I915_READ(LCPLL_CTL
);
9025 val
|= LCPLL_PLL_DISABLE
;
9026 I915_WRITE(LCPLL_CTL
, val
);
9027 POSTING_READ(LCPLL_CTL
);
9029 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9030 DRM_ERROR("LCPLL still locked\n");
9032 val
= hsw_read_dcomp(dev_priv
);
9033 val
|= D_COMP_COMP_DISABLE
;
9034 hsw_write_dcomp(dev_priv
, val
);
9037 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9039 DRM_ERROR("D_COMP RCOMP still in progress\n");
9041 if (allow_power_down
) {
9042 val
= I915_READ(LCPLL_CTL
);
9043 val
|= LCPLL_POWER_DOWN_ALLOW
;
9044 I915_WRITE(LCPLL_CTL
, val
);
9045 POSTING_READ(LCPLL_CTL
);
9050 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9053 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9057 val
= I915_READ(LCPLL_CTL
);
9059 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9060 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9064 * Make sure we're not on PC8 state before disabling PC8, otherwise
9065 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9067 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9069 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9070 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9071 I915_WRITE(LCPLL_CTL
, val
);
9072 POSTING_READ(LCPLL_CTL
);
9075 val
= hsw_read_dcomp(dev_priv
);
9076 val
|= D_COMP_COMP_FORCE
;
9077 val
&= ~D_COMP_COMP_DISABLE
;
9078 hsw_write_dcomp(dev_priv
, val
);
9080 val
= I915_READ(LCPLL_CTL
);
9081 val
&= ~LCPLL_PLL_DISABLE
;
9082 I915_WRITE(LCPLL_CTL
, val
);
9084 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9085 DRM_ERROR("LCPLL not locked yet\n");
9087 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9088 val
= I915_READ(LCPLL_CTL
);
9089 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9090 I915_WRITE(LCPLL_CTL
, val
);
9092 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9093 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9094 DRM_ERROR("Switching back to LCPLL failed\n");
9097 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9101 * Package states C8 and deeper are really deep PC states that can only be
9102 * reached when all the devices on the system allow it, so even if the graphics
9103 * device allows PC8+, it doesn't mean the system will actually get to these
9104 * states. Our driver only allows PC8+ when going into runtime PM.
9106 * The requirements for PC8+ are that all the outputs are disabled, the power
9107 * well is disabled and most interrupts are disabled, and these are also
9108 * requirements for runtime PM. When these conditions are met, we manually do
9109 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9110 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9113 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9114 * the state of some registers, so when we come back from PC8+ we need to
9115 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9116 * need to take care of the registers kept by RC6. Notice that this happens even
9117 * if we don't put the device in PCI D3 state (which is what currently happens
9118 * because of the runtime PM support).
9120 * For more, read "Display Sequences for Package C8" on the hardware
9123 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9125 struct drm_device
*dev
= dev_priv
->dev
;
9128 DRM_DEBUG_KMS("Enabling package C8+\n");
9130 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9131 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9132 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9133 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9136 lpt_disable_clkout_dp(dev
);
9137 hsw_disable_lcpll(dev_priv
, true, true);
9140 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9142 struct drm_device
*dev
= dev_priv
->dev
;
9145 DRM_DEBUG_KMS("Disabling package C8+\n");
9147 hsw_restore_lcpll(dev_priv
);
9148 lpt_init_pch_refclk(dev
);
9150 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9151 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9152 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9153 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9156 intel_prepare_ddi(dev
);
9159 static void broxton_modeset_global_resources(struct drm_atomic_state
*state
)
9161 struct drm_device
*dev
= state
->dev
;
9162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9163 int max_pixclk
= intel_mode_max_pixclk(state
);
9166 /* see the comment in valleyview_modeset_global_resources */
9167 if (WARN_ON(max_pixclk
< 0))
9170 req_cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
9172 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9173 broxton_set_cdclk(dev
, req_cdclk
);
9176 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9177 struct intel_crtc_state
*crtc_state
)
9179 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9182 crtc
->lowfreq_avail
= false;
9187 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9189 struct intel_crtc_state
*pipe_config
)
9193 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9194 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9197 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9198 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9201 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9202 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9205 DRM_ERROR("Incorrect port type\n");
9209 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9211 struct intel_crtc_state
*pipe_config
)
9213 u32 temp
, dpll_ctl1
;
9215 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9216 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9218 switch (pipe_config
->ddi_pll_sel
) {
9221 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9222 * of the shared DPLL framework and thus needs to be read out
9225 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9226 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9229 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9232 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9235 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9240 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9242 struct intel_crtc_state
*pipe_config
)
9244 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9246 switch (pipe_config
->ddi_pll_sel
) {
9247 case PORT_CLK_SEL_WRPLL1
:
9248 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9250 case PORT_CLK_SEL_WRPLL2
:
9251 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9256 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9257 struct intel_crtc_state
*pipe_config
)
9259 struct drm_device
*dev
= crtc
->base
.dev
;
9260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9261 struct intel_shared_dpll
*pll
;
9265 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9267 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9269 if (IS_SKYLAKE(dev
))
9270 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9271 else if (IS_BROXTON(dev
))
9272 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9274 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9276 if (pipe_config
->shared_dpll
>= 0) {
9277 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9279 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9280 &pipe_config
->dpll_hw_state
));
9284 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9285 * DDI E. So just check whether this pipe is wired to DDI E and whether
9286 * the PCH transcoder is on.
9288 if (INTEL_INFO(dev
)->gen
< 9 &&
9289 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9290 pipe_config
->has_pch_encoder
= true;
9292 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9293 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9294 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9296 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9300 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9301 struct intel_crtc_state
*pipe_config
)
9303 struct drm_device
*dev
= crtc
->base
.dev
;
9304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9305 enum intel_display_power_domain pfit_domain
;
9308 if (!intel_display_power_is_enabled(dev_priv
,
9309 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9312 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9313 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9315 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9316 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9317 enum pipe trans_edp_pipe
;
9318 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9320 WARN(1, "unknown pipe linked to edp transcoder\n");
9321 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9322 case TRANS_DDI_EDP_INPUT_A_ON
:
9323 trans_edp_pipe
= PIPE_A
;
9325 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9326 trans_edp_pipe
= PIPE_B
;
9328 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9329 trans_edp_pipe
= PIPE_C
;
9333 if (trans_edp_pipe
== crtc
->pipe
)
9334 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9337 if (!intel_display_power_is_enabled(dev_priv
,
9338 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9341 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9342 if (!(tmp
& PIPECONF_ENABLE
))
9345 haswell_get_ddi_port_state(crtc
, pipe_config
);
9347 intel_get_pipe_timings(crtc
, pipe_config
);
9349 if (INTEL_INFO(dev
)->gen
>= 9) {
9350 skl_init_scalers(dev
, crtc
, pipe_config
);
9353 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9354 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9355 if (INTEL_INFO(dev
)->gen
== 9)
9356 skylake_get_pfit_config(crtc
, pipe_config
);
9357 else if (INTEL_INFO(dev
)->gen
< 9)
9358 ironlake_get_pfit_config(crtc
, pipe_config
);
9360 MISSING_CASE(INTEL_INFO(dev
)->gen
);
9363 pipe_config
->scaler_state
.scaler_id
= -1;
9364 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9367 if (IS_HASWELL(dev
))
9368 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9369 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9371 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9372 pipe_config
->pixel_multiplier
=
9373 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9375 pipe_config
->pixel_multiplier
= 1;
9381 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9383 struct drm_device
*dev
= crtc
->dev
;
9384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9386 uint32_t cntl
= 0, size
= 0;
9389 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9390 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9391 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9395 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9406 cntl
|= CURSOR_ENABLE
|
9407 CURSOR_GAMMA_ENABLE
|
9408 CURSOR_FORMAT_ARGB
|
9409 CURSOR_STRIDE(stride
);
9411 size
= (height
<< 12) | width
;
9414 if (intel_crtc
->cursor_cntl
!= 0 &&
9415 (intel_crtc
->cursor_base
!= base
||
9416 intel_crtc
->cursor_size
!= size
||
9417 intel_crtc
->cursor_cntl
!= cntl
)) {
9418 /* On these chipsets we can only modify the base/size/stride
9419 * whilst the cursor is disabled.
9421 I915_WRITE(_CURACNTR
, 0);
9422 POSTING_READ(_CURACNTR
);
9423 intel_crtc
->cursor_cntl
= 0;
9426 if (intel_crtc
->cursor_base
!= base
) {
9427 I915_WRITE(_CURABASE
, base
);
9428 intel_crtc
->cursor_base
= base
;
9431 if (intel_crtc
->cursor_size
!= size
) {
9432 I915_WRITE(CURSIZE
, size
);
9433 intel_crtc
->cursor_size
= size
;
9436 if (intel_crtc
->cursor_cntl
!= cntl
) {
9437 I915_WRITE(_CURACNTR
, cntl
);
9438 POSTING_READ(_CURACNTR
);
9439 intel_crtc
->cursor_cntl
= cntl
;
9443 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9445 struct drm_device
*dev
= crtc
->dev
;
9446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9447 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9448 int pipe
= intel_crtc
->pipe
;
9453 cntl
= MCURSOR_GAMMA_ENABLE
;
9454 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9456 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9459 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9462 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9465 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
9468 cntl
|= pipe
<< 28; /* Connect to correct pipe */
9470 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
9471 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9474 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
9475 cntl
|= CURSOR_ROTATE_180
;
9477 if (intel_crtc
->cursor_cntl
!= cntl
) {
9478 I915_WRITE(CURCNTR(pipe
), cntl
);
9479 POSTING_READ(CURCNTR(pipe
));
9480 intel_crtc
->cursor_cntl
= cntl
;
9483 /* and commit changes on next vblank */
9484 I915_WRITE(CURBASE(pipe
), base
);
9485 POSTING_READ(CURBASE(pipe
));
9487 intel_crtc
->cursor_base
= base
;
9490 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9491 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
9494 struct drm_device
*dev
= crtc
->dev
;
9495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9497 int pipe
= intel_crtc
->pipe
;
9498 int x
= crtc
->cursor_x
;
9499 int y
= crtc
->cursor_y
;
9500 u32 base
= 0, pos
= 0;
9503 base
= intel_crtc
->cursor_addr
;
9505 if (x
>= intel_crtc
->config
->pipe_src_w
)
9508 if (y
>= intel_crtc
->config
->pipe_src_h
)
9512 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
9515 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9518 pos
|= x
<< CURSOR_X_SHIFT
;
9521 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
9524 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9527 pos
|= y
<< CURSOR_Y_SHIFT
;
9529 if (base
== 0 && intel_crtc
->cursor_base
== 0)
9532 I915_WRITE(CURPOS(pipe
), pos
);
9534 /* ILK+ do this automagically */
9535 if (HAS_GMCH_DISPLAY(dev
) &&
9536 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
9537 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
9538 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
9541 if (IS_845G(dev
) || IS_I865G(dev
))
9542 i845_update_cursor(crtc
, base
);
9544 i9xx_update_cursor(crtc
, base
);
9547 static bool cursor_size_ok(struct drm_device
*dev
,
9548 uint32_t width
, uint32_t height
)
9550 if (width
== 0 || height
== 0)
9554 * 845g/865g are special in that they are only limited by
9555 * the width of their cursors, the height is arbitrary up to
9556 * the precision of the register. Everything else requires
9557 * square cursors, limited to a few power-of-two sizes.
9559 if (IS_845G(dev
) || IS_I865G(dev
)) {
9560 if ((width
& 63) != 0)
9563 if (width
> (IS_845G(dev
) ? 64 : 512))
9569 switch (width
| height
) {
9584 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
9585 u16
*blue
, uint32_t start
, uint32_t size
)
9587 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
9588 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9590 for (i
= start
; i
< end
; i
++) {
9591 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
9592 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
9593 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
9596 intel_crtc_load_lut(crtc
);
9599 /* VESA 640x480x72Hz mode to set on the pipe */
9600 static struct drm_display_mode load_detect_mode
= {
9601 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9602 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9605 struct drm_framebuffer
*
9606 __intel_framebuffer_create(struct drm_device
*dev
,
9607 struct drm_mode_fb_cmd2
*mode_cmd
,
9608 struct drm_i915_gem_object
*obj
)
9610 struct intel_framebuffer
*intel_fb
;
9613 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9615 drm_gem_object_unreference(&obj
->base
);
9616 return ERR_PTR(-ENOMEM
);
9619 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
9623 return &intel_fb
->base
;
9625 drm_gem_object_unreference(&obj
->base
);
9628 return ERR_PTR(ret
);
9631 static struct drm_framebuffer
*
9632 intel_framebuffer_create(struct drm_device
*dev
,
9633 struct drm_mode_fb_cmd2
*mode_cmd
,
9634 struct drm_i915_gem_object
*obj
)
9636 struct drm_framebuffer
*fb
;
9639 ret
= i915_mutex_lock_interruptible(dev
);
9641 return ERR_PTR(ret
);
9642 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
9643 mutex_unlock(&dev
->struct_mutex
);
9649 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9651 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9652 return ALIGN(pitch
, 64);
9656 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9658 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9659 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9662 static struct drm_framebuffer
*
9663 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9664 struct drm_display_mode
*mode
,
9667 struct drm_i915_gem_object
*obj
;
9668 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9670 obj
= i915_gem_alloc_object(dev
,
9671 intel_framebuffer_size_for_mode(mode
, bpp
));
9673 return ERR_PTR(-ENOMEM
);
9675 mode_cmd
.width
= mode
->hdisplay
;
9676 mode_cmd
.height
= mode
->vdisplay
;
9677 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9679 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9681 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
9684 static struct drm_framebuffer
*
9685 mode_fits_in_fbdev(struct drm_device
*dev
,
9686 struct drm_display_mode
*mode
)
9688 #ifdef CONFIG_DRM_I915_FBDEV
9689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9690 struct drm_i915_gem_object
*obj
;
9691 struct drm_framebuffer
*fb
;
9693 if (!dev_priv
->fbdev
)
9696 if (!dev_priv
->fbdev
->fb
)
9699 obj
= dev_priv
->fbdev
->fb
->obj
;
9702 fb
= &dev_priv
->fbdev
->fb
->base
;
9703 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9704 fb
->bits_per_pixel
))
9707 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9716 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
9717 struct drm_display_mode
*mode
,
9718 struct intel_load_detect_pipe
*old
,
9719 struct drm_modeset_acquire_ctx
*ctx
)
9721 struct intel_crtc
*intel_crtc
;
9722 struct intel_encoder
*intel_encoder
=
9723 intel_attached_encoder(connector
);
9724 struct drm_crtc
*possible_crtc
;
9725 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9726 struct drm_crtc
*crtc
= NULL
;
9727 struct drm_device
*dev
= encoder
->dev
;
9728 struct drm_framebuffer
*fb
;
9729 struct drm_mode_config
*config
= &dev
->mode_config
;
9730 struct drm_atomic_state
*state
= NULL
;
9731 struct drm_connector_state
*connector_state
;
9734 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9735 connector
->base
.id
, connector
->name
,
9736 encoder
->base
.id
, encoder
->name
);
9739 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
9744 * Algorithm gets a little messy:
9746 * - if the connector already has an assigned crtc, use it (but make
9747 * sure it's on first)
9749 * - try to find the first unused crtc that can drive this connector,
9750 * and use that if we find one
9753 /* See if we already have a CRTC for this connector */
9754 if (encoder
->crtc
) {
9755 crtc
= encoder
->crtc
;
9757 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9760 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9764 old
->dpms_mode
= connector
->dpms
;
9765 old
->load_detect_temp
= false;
9767 /* Make sure the crtc and connector are running */
9768 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
9769 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
9774 /* Find an unused one (if possible) */
9775 for_each_crtc(dev
, possible_crtc
) {
9777 if (!(encoder
->possible_crtcs
& (1 << i
)))
9779 if (possible_crtc
->state
->enable
)
9781 /* This can occur when applying the pipe A quirk on resume. */
9782 if (to_intel_crtc(possible_crtc
)->new_enabled
)
9785 crtc
= possible_crtc
;
9790 * If we didn't find an unused CRTC, don't use any.
9793 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9797 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9800 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9803 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
9804 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
9806 intel_crtc
= to_intel_crtc(crtc
);
9807 intel_crtc
->new_enabled
= true;
9808 old
->dpms_mode
= connector
->dpms
;
9809 old
->load_detect_temp
= true;
9810 old
->release_fb
= NULL
;
9812 state
= drm_atomic_state_alloc(dev
);
9816 state
->acquire_ctx
= ctx
;
9818 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9819 if (IS_ERR(connector_state
)) {
9820 ret
= PTR_ERR(connector_state
);
9824 connector_state
->crtc
= crtc
;
9825 connector_state
->best_encoder
= &intel_encoder
->base
;
9828 mode
= &load_detect_mode
;
9830 /* We need a framebuffer large enough to accommodate all accesses
9831 * that the plane may generate whilst we perform load detection.
9832 * We can not rely on the fbcon either being present (we get called
9833 * during its initialisation to detect all boot displays, or it may
9834 * not even exist) or that it is large enough to satisfy the
9837 fb
= mode_fits_in_fbdev(dev
, mode
);
9839 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9840 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
9841 old
->release_fb
= fb
;
9843 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9845 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9849 if (intel_set_mode(crtc
, mode
, 0, 0, fb
, state
)) {
9850 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9851 if (old
->release_fb
)
9852 old
->release_fb
->funcs
->destroy(old
->release_fb
);
9855 crtc
->primary
->crtc
= crtc
;
9857 /* let the connector get through one full cycle before testing */
9858 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
9862 intel_crtc
->new_enabled
= crtc
->state
->enable
;
9865 drm_atomic_state_free(state
);
9869 if (ret
== -EDEADLK
) {
9870 drm_modeset_backoff(ctx
);
9877 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
9878 struct intel_load_detect_pipe
*old
,
9879 struct drm_modeset_acquire_ctx
*ctx
)
9881 struct drm_device
*dev
= connector
->dev
;
9882 struct intel_encoder
*intel_encoder
=
9883 intel_attached_encoder(connector
);
9884 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9885 struct drm_crtc
*crtc
= encoder
->crtc
;
9886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9887 struct drm_atomic_state
*state
;
9888 struct drm_connector_state
*connector_state
;
9890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9891 connector
->base
.id
, connector
->name
,
9892 encoder
->base
.id
, encoder
->name
);
9894 if (old
->load_detect_temp
) {
9895 state
= drm_atomic_state_alloc(dev
);
9899 state
->acquire_ctx
= ctx
;
9901 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9902 if (IS_ERR(connector_state
))
9905 to_intel_connector(connector
)->new_encoder
= NULL
;
9906 intel_encoder
->new_crtc
= NULL
;
9907 intel_crtc
->new_enabled
= false;
9909 connector_state
->best_encoder
= NULL
;
9910 connector_state
->crtc
= NULL
;
9912 intel_set_mode(crtc
, NULL
, 0, 0, NULL
, state
);
9914 drm_atomic_state_free(state
);
9916 if (old
->release_fb
) {
9917 drm_framebuffer_unregister_private(old
->release_fb
);
9918 drm_framebuffer_unreference(old
->release_fb
);
9924 /* Switch crtc and encoder back off if necessary */
9925 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
9926 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
9930 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9931 drm_atomic_state_free(state
);
9934 static int i9xx_pll_refclk(struct drm_device
*dev
,
9935 const struct intel_crtc_state
*pipe_config
)
9937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9938 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9940 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
9941 return dev_priv
->vbt
.lvds_ssc_freq
;
9942 else if (HAS_PCH_SPLIT(dev
))
9944 else if (!IS_GEN2(dev
))
9950 /* Returns the clock of the currently programmed mode of the given pipe. */
9951 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
9952 struct intel_crtc_state
*pipe_config
)
9954 struct drm_device
*dev
= crtc
->base
.dev
;
9955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9956 int pipe
= pipe_config
->cpu_transcoder
;
9957 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9959 intel_clock_t clock
;
9960 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
9962 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
9963 fp
= pipe_config
->dpll_hw_state
.fp0
;
9965 fp
= pipe_config
->dpll_hw_state
.fp1
;
9967 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
9968 if (IS_PINEVIEW(dev
)) {
9969 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
9970 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9972 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
9973 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9976 if (!IS_GEN2(dev
)) {
9977 if (IS_PINEVIEW(dev
))
9978 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
9979 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
9981 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
9982 DPLL_FPA01_P1_POST_DIV_SHIFT
);
9984 switch (dpll
& DPLL_MODE_MASK
) {
9985 case DPLLB_MODE_DAC_SERIAL
:
9986 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
9989 case DPLLB_MODE_LVDS
:
9990 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
9994 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9995 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
9999 if (IS_PINEVIEW(dev
))
10000 pineview_clock(refclk
, &clock
);
10002 i9xx_clock(refclk
, &clock
);
10004 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10005 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10008 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10009 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10011 if (lvds
& LVDS_CLKB_POWER_UP
)
10016 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10019 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10020 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10022 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10028 i9xx_clock(refclk
, &clock
);
10032 * This value includes pixel_multiplier. We will use
10033 * port_clock to compute adjusted_mode.crtc_clock in the
10034 * encoder's get_config() function.
10036 pipe_config
->port_clock
= clock
.dot
;
10039 int intel_dotclock_calculate(int link_freq
,
10040 const struct intel_link_m_n
*m_n
)
10043 * The calculation for the data clock is:
10044 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10045 * But we want to avoid losing precison if possible, so:
10046 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10048 * and the link clock is simpler:
10049 * link_clock = (m * link_clock) / n
10055 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10058 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10059 struct intel_crtc_state
*pipe_config
)
10061 struct drm_device
*dev
= crtc
->base
.dev
;
10063 /* read out port_clock from the DPLL */
10064 i9xx_crtc_clock_get(crtc
, pipe_config
);
10067 * This value does not include pixel_multiplier.
10068 * We will check that port_clock and adjusted_mode.crtc_clock
10069 * agree once we know their relationship in the encoder's
10070 * get_config() function.
10072 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10073 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10074 &pipe_config
->fdi_m_n
);
10077 /** Returns the currently programmed mode of the given pipe. */
10078 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10079 struct drm_crtc
*crtc
)
10081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10083 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10084 struct drm_display_mode
*mode
;
10085 struct intel_crtc_state pipe_config
;
10086 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10087 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10088 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10089 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10090 enum pipe pipe
= intel_crtc
->pipe
;
10092 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10097 * Construct a pipe_config sufficient for getting the clock info
10098 * back out of crtc_clock_get.
10100 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10101 * to use a real value here instead.
10103 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10104 pipe_config
.pixel_multiplier
= 1;
10105 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10106 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10107 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10108 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10110 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10111 mode
->hdisplay
= (htot
& 0xffff) + 1;
10112 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10113 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10114 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10115 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10116 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10117 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10118 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10120 drm_mode_set_name(mode
);
10125 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
10127 struct drm_device
*dev
= crtc
->dev
;
10128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10129 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10131 if (!HAS_GMCH_DISPLAY(dev
))
10134 if (!dev_priv
->lvds_downclock_avail
)
10138 * Since this is called by a timer, we should never get here in
10141 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
10142 int pipe
= intel_crtc
->pipe
;
10143 int dpll_reg
= DPLL(pipe
);
10146 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10148 assert_panel_unlocked(dev_priv
, pipe
);
10150 dpll
= I915_READ(dpll_reg
);
10151 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
10152 I915_WRITE(dpll_reg
, dpll
);
10153 intel_wait_for_vblank(dev
, pipe
);
10154 dpll
= I915_READ(dpll_reg
);
10155 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
10156 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10161 void intel_mark_busy(struct drm_device
*dev
)
10163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10165 if (dev_priv
->mm
.busy
)
10168 intel_runtime_pm_get(dev_priv
);
10169 i915_update_gfx_val(dev_priv
);
10170 if (INTEL_INFO(dev
)->gen
>= 6)
10171 gen6_rps_busy(dev_priv
);
10172 dev_priv
->mm
.busy
= true;
10175 void intel_mark_idle(struct drm_device
*dev
)
10177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10178 struct drm_crtc
*crtc
;
10180 if (!dev_priv
->mm
.busy
)
10183 dev_priv
->mm
.busy
= false;
10185 for_each_crtc(dev
, crtc
) {
10186 if (!crtc
->primary
->fb
)
10189 intel_decrease_pllclock(crtc
);
10192 if (INTEL_INFO(dev
)->gen
>= 6)
10193 gen6_rps_idle(dev
->dev_private
);
10195 intel_runtime_pm_put(dev_priv
);
10198 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
10199 struct intel_crtc_state
*crtc_state
)
10201 kfree(crtc
->config
);
10202 crtc
->config
= crtc_state
;
10203 crtc
->base
.state
= &crtc_state
->base
;
10206 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10208 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10209 struct drm_device
*dev
= crtc
->dev
;
10210 struct intel_unpin_work
*work
;
10212 spin_lock_irq(&dev
->event_lock
);
10213 work
= intel_crtc
->unpin_work
;
10214 intel_crtc
->unpin_work
= NULL
;
10215 spin_unlock_irq(&dev
->event_lock
);
10218 cancel_work_sync(&work
->work
);
10222 intel_crtc_set_state(intel_crtc
, NULL
);
10223 drm_crtc_cleanup(crtc
);
10228 static void intel_unpin_work_fn(struct work_struct
*__work
)
10230 struct intel_unpin_work
*work
=
10231 container_of(__work
, struct intel_unpin_work
, work
);
10232 struct drm_device
*dev
= work
->crtc
->dev
;
10233 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
10235 mutex_lock(&dev
->struct_mutex
);
10236 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
10237 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10239 intel_fbc_update(dev
);
10241 if (work
->flip_queued_req
)
10242 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10243 mutex_unlock(&dev
->struct_mutex
);
10245 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10246 drm_framebuffer_unreference(work
->old_fb
);
10248 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
10249 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
10254 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10255 struct drm_crtc
*crtc
)
10257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10258 struct intel_unpin_work
*work
;
10259 unsigned long flags
;
10261 /* Ignore early vblank irqs */
10262 if (intel_crtc
== NULL
)
10266 * This is called both by irq handlers and the reset code (to complete
10267 * lost pageflips) so needs the full irqsave spinlocks.
10269 spin_lock_irqsave(&dev
->event_lock
, flags
);
10270 work
= intel_crtc
->unpin_work
;
10272 /* Ensure we don't miss a work->pending update ... */
10275 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10276 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10280 page_flip_completed(intel_crtc
);
10282 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10285 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10288 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10290 do_intel_finish_page_flip(dev
, crtc
);
10293 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10296 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10298 do_intel_finish_page_flip(dev
, crtc
);
10301 /* Is 'a' after or equal to 'b'? */
10302 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10304 return !((a
- b
) & 0x80000000);
10307 static bool page_flip_finished(struct intel_crtc
*crtc
)
10309 struct drm_device
*dev
= crtc
->base
.dev
;
10310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10312 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10313 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10317 * The relevant registers doen't exist on pre-ctg.
10318 * As the flip done interrupt doesn't trigger for mmio
10319 * flips on gmch platforms, a flip count check isn't
10320 * really needed there. But since ctg has the registers,
10321 * include it in the check anyway.
10323 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10327 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10328 * used the same base address. In that case the mmio flip might
10329 * have completed, but the CS hasn't even executed the flip yet.
10331 * A flip count check isn't enough as the CS might have updated
10332 * the base address just after start of vblank, but before we
10333 * managed to process the interrupt. This means we'd complete the
10334 * CS flip too soon.
10336 * Combining both checks should get us a good enough result. It may
10337 * still happen that the CS flip has been executed, but has not
10338 * yet actually completed. But in case the base address is the same
10339 * anyway, we don't really care.
10341 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10342 crtc
->unpin_work
->gtt_offset
&&
10343 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
10344 crtc
->unpin_work
->flip_count
);
10347 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10350 struct intel_crtc
*intel_crtc
=
10351 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10352 unsigned long flags
;
10356 * This is called both by irq handlers and the reset code (to complete
10357 * lost pageflips) so needs the full irqsave spinlocks.
10359 * NB: An MMIO update of the plane base pointer will also
10360 * generate a page-flip completion irq, i.e. every modeset
10361 * is also accompanied by a spurious intel_prepare_page_flip().
10363 spin_lock_irqsave(&dev
->event_lock
, flags
);
10364 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10365 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10366 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10369 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
10371 /* Ensure that the work item is consistent when activating it ... */
10373 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
10374 /* and that it is marked active as soon as the irq could fire. */
10378 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10379 struct drm_crtc
*crtc
,
10380 struct drm_framebuffer
*fb
,
10381 struct drm_i915_gem_object
*obj
,
10382 struct intel_engine_cs
*ring
,
10385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10389 ret
= intel_ring_begin(ring
, 6);
10393 /* Can't queue multiple flips, so wait for the previous
10394 * one to finish before executing the next.
10396 if (intel_crtc
->plane
)
10397 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10399 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10400 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10401 intel_ring_emit(ring
, MI_NOOP
);
10402 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10403 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10404 intel_ring_emit(ring
, fb
->pitches
[0]);
10405 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10406 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10408 intel_mark_page_flip_active(intel_crtc
);
10409 __intel_ring_advance(ring
);
10413 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10414 struct drm_crtc
*crtc
,
10415 struct drm_framebuffer
*fb
,
10416 struct drm_i915_gem_object
*obj
,
10417 struct intel_engine_cs
*ring
,
10420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10424 ret
= intel_ring_begin(ring
, 6);
10428 if (intel_crtc
->plane
)
10429 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10431 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10432 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10433 intel_ring_emit(ring
, MI_NOOP
);
10434 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10435 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10436 intel_ring_emit(ring
, fb
->pitches
[0]);
10437 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10438 intel_ring_emit(ring
, MI_NOOP
);
10440 intel_mark_page_flip_active(intel_crtc
);
10441 __intel_ring_advance(ring
);
10445 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10446 struct drm_crtc
*crtc
,
10447 struct drm_framebuffer
*fb
,
10448 struct drm_i915_gem_object
*obj
,
10449 struct intel_engine_cs
*ring
,
10452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10453 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10454 uint32_t pf
, pipesrc
;
10457 ret
= intel_ring_begin(ring
, 4);
10461 /* i965+ uses the linear or tiled offsets from the
10462 * Display Registers (which do not change across a page-flip)
10463 * so we need only reprogram the base address.
10465 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10466 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10467 intel_ring_emit(ring
, fb
->pitches
[0]);
10468 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
10471 /* XXX Enabling the panel-fitter across page-flip is so far
10472 * untested on non-native modes, so ignore it for now.
10473 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10476 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10477 intel_ring_emit(ring
, pf
| pipesrc
);
10479 intel_mark_page_flip_active(intel_crtc
);
10480 __intel_ring_advance(ring
);
10484 static int intel_gen6_queue_flip(struct drm_device
*dev
,
10485 struct drm_crtc
*crtc
,
10486 struct drm_framebuffer
*fb
,
10487 struct drm_i915_gem_object
*obj
,
10488 struct intel_engine_cs
*ring
,
10491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10493 uint32_t pf
, pipesrc
;
10496 ret
= intel_ring_begin(ring
, 4);
10500 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10501 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10502 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
10503 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10505 /* Contrary to the suggestions in the documentation,
10506 * "Enable Panel Fitter" does not seem to be required when page
10507 * flipping with a non-native mode, and worse causes a normal
10509 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10512 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10513 intel_ring_emit(ring
, pf
| pipesrc
);
10515 intel_mark_page_flip_active(intel_crtc
);
10516 __intel_ring_advance(ring
);
10520 static int intel_gen7_queue_flip(struct drm_device
*dev
,
10521 struct drm_crtc
*crtc
,
10522 struct drm_framebuffer
*fb
,
10523 struct drm_i915_gem_object
*obj
,
10524 struct intel_engine_cs
*ring
,
10527 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10528 uint32_t plane_bit
= 0;
10531 switch (intel_crtc
->plane
) {
10533 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
10536 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
10539 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
10542 WARN_ONCE(1, "unknown plane in flip command\n");
10547 if (ring
->id
== RCS
) {
10550 * On Gen 8, SRM is now taking an extra dword to accommodate
10551 * 48bits addresses, and we need a NOOP for the batch size to
10559 * BSpec MI_DISPLAY_FLIP for IVB:
10560 * "The full packet must be contained within the same cache line."
10562 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10563 * cacheline, if we ever start emitting more commands before
10564 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10565 * then do the cacheline alignment, and finally emit the
10568 ret
= intel_ring_cacheline_align(ring
);
10572 ret
= intel_ring_begin(ring
, len
);
10576 /* Unmask the flip-done completion message. Note that the bspec says that
10577 * we should do this for both the BCS and RCS, and that we must not unmask
10578 * more than one flip event at any time (or ensure that one flip message
10579 * can be sent by waiting for flip-done prior to queueing new flips).
10580 * Experimentation says that BCS works despite DERRMR masking all
10581 * flip-done completion events and that unmasking all planes at once
10582 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10583 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10585 if (ring
->id
== RCS
) {
10586 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
10587 intel_ring_emit(ring
, DERRMR
);
10588 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
10589 DERRMR_PIPEB_PRI_FLIP_DONE
|
10590 DERRMR_PIPEC_PRI_FLIP_DONE
));
10592 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
10593 MI_SRM_LRM_GLOBAL_GTT
);
10595 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
10596 MI_SRM_LRM_GLOBAL_GTT
);
10597 intel_ring_emit(ring
, DERRMR
);
10598 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
10599 if (IS_GEN8(dev
)) {
10600 intel_ring_emit(ring
, 0);
10601 intel_ring_emit(ring
, MI_NOOP
);
10605 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
10606 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
10607 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10608 intel_ring_emit(ring
, (MI_NOOP
));
10610 intel_mark_page_flip_active(intel_crtc
);
10611 __intel_ring_advance(ring
);
10615 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
10616 struct drm_i915_gem_object
*obj
)
10619 * This is not being used for older platforms, because
10620 * non-availability of flip done interrupt forces us to use
10621 * CS flips. Older platforms derive flip done using some clever
10622 * tricks involving the flip_pending status bits and vblank irqs.
10623 * So using MMIO flips there would disrupt this mechanism.
10629 if (INTEL_INFO(ring
->dev
)->gen
< 5)
10632 if (i915
.use_mmio_flip
< 0)
10634 else if (i915
.use_mmio_flip
> 0)
10636 else if (i915
.enable_execlists
)
10639 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
10642 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10644 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10646 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
10647 const enum pipe pipe
= intel_crtc
->pipe
;
10650 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
10651 ctl
&= ~PLANE_CTL_TILED_MASK
;
10652 switch (fb
->modifier
[0]) {
10653 case DRM_FORMAT_MOD_NONE
:
10655 case I915_FORMAT_MOD_X_TILED
:
10656 ctl
|= PLANE_CTL_TILED_X
;
10658 case I915_FORMAT_MOD_Y_TILED
:
10659 ctl
|= PLANE_CTL_TILED_Y
;
10661 case I915_FORMAT_MOD_Yf_TILED
:
10662 ctl
|= PLANE_CTL_TILED_YF
;
10665 MISSING_CASE(fb
->modifier
[0]);
10669 * The stride is either expressed as a multiple of 64 bytes chunks for
10670 * linear buffers or in number of tiles for tiled buffers.
10672 stride
= fb
->pitches
[0] /
10673 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
10677 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10678 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10680 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
10681 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
10683 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
10684 POSTING_READ(PLANE_SURF(pipe
, 0));
10687 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10689 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10691 struct intel_framebuffer
*intel_fb
=
10692 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
10693 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10697 reg
= DSPCNTR(intel_crtc
->plane
);
10698 dspcntr
= I915_READ(reg
);
10700 if (obj
->tiling_mode
!= I915_TILING_NONE
)
10701 dspcntr
|= DISPPLANE_TILED
;
10703 dspcntr
&= ~DISPPLANE_TILED
;
10705 I915_WRITE(reg
, dspcntr
);
10707 I915_WRITE(DSPSURF(intel_crtc
->plane
),
10708 intel_crtc
->unpin_work
->gtt_offset
);
10709 POSTING_READ(DSPSURF(intel_crtc
->plane
));
10714 * XXX: This is the temporary way to update the plane registers until we get
10715 * around to using the usual plane update functions for MMIO flips
10717 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10719 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10720 bool atomic_update
;
10721 u32 start_vbl_count
;
10723 intel_mark_page_flip_active(intel_crtc
);
10725 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
10727 if (INTEL_INFO(dev
)->gen
>= 9)
10728 skl_do_mmio_flip(intel_crtc
);
10730 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10731 ilk_do_mmio_flip(intel_crtc
);
10734 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
10737 static void intel_mmio_flip_work_func(struct work_struct
*work
)
10739 struct intel_crtc
*crtc
=
10740 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
10741 struct intel_mmio_flip
*mmio_flip
;
10743 mmio_flip
= &crtc
->mmio_flip
;
10744 if (mmio_flip
->req
)
10745 WARN_ON(__i915_wait_request(mmio_flip
->req
,
10746 crtc
->reset_counter
,
10747 false, NULL
, NULL
) != 0);
10749 intel_do_mmio_flip(crtc
);
10750 if (mmio_flip
->req
) {
10751 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
10752 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
10753 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
10757 static int intel_queue_mmio_flip(struct drm_device
*dev
,
10758 struct drm_crtc
*crtc
,
10759 struct drm_framebuffer
*fb
,
10760 struct drm_i915_gem_object
*obj
,
10761 struct intel_engine_cs
*ring
,
10764 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10766 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
10767 obj
->last_write_req
);
10769 schedule_work(&intel_crtc
->mmio_flip
.work
);
10774 static int intel_default_queue_flip(struct drm_device
*dev
,
10775 struct drm_crtc
*crtc
,
10776 struct drm_framebuffer
*fb
,
10777 struct drm_i915_gem_object
*obj
,
10778 struct intel_engine_cs
*ring
,
10784 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
10785 struct drm_crtc
*crtc
)
10787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10788 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10789 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
10792 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
10795 if (!work
->enable_stall_check
)
10798 if (work
->flip_ready_vblank
== 0) {
10799 if (work
->flip_queued_req
&&
10800 !i915_gem_request_completed(work
->flip_queued_req
, true))
10803 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
10806 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
10809 /* Potential stall - if we see that the flip has happened,
10810 * assume a missed interrupt. */
10811 if (INTEL_INFO(dev
)->gen
>= 4)
10812 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
10814 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
10816 /* There is a potential issue here with a false positive after a flip
10817 * to the same address. We could address this by checking for a
10818 * non-incrementing frame counter.
10820 return addr
== work
->gtt_offset
;
10823 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
10825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10826 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10827 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10828 struct intel_unpin_work
*work
;
10830 WARN_ON(!in_interrupt());
10835 spin_lock(&dev
->event_lock
);
10836 work
= intel_crtc
->unpin_work
;
10837 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
10838 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10839 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
10840 page_flip_completed(intel_crtc
);
10843 if (work
!= NULL
&&
10844 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
10845 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
10846 spin_unlock(&dev
->event_lock
);
10849 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
10850 struct drm_framebuffer
*fb
,
10851 struct drm_pending_vblank_event
*event
,
10852 uint32_t page_flip_flags
)
10854 struct drm_device
*dev
= crtc
->dev
;
10855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10856 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10857 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10858 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10859 struct drm_plane
*primary
= crtc
->primary
;
10860 enum pipe pipe
= intel_crtc
->pipe
;
10861 struct intel_unpin_work
*work
;
10862 struct intel_engine_cs
*ring
;
10867 * drm_mode_page_flip_ioctl() should already catch this, but double
10868 * check to be safe. In the future we may enable pageflipping from
10869 * a disabled primary plane.
10871 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
10874 /* Can't change pixel format via MI display flips. */
10875 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
10879 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10880 * Note that pitch changes could also affect these register.
10882 if (INTEL_INFO(dev
)->gen
> 3 &&
10883 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
10884 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
10887 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
10890 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
10894 work
->event
= event
;
10896 work
->old_fb
= old_fb
;
10897 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
10899 ret
= drm_crtc_vblank_get(crtc
);
10903 /* We borrow the event spin lock for protecting unpin_work */
10904 spin_lock_irq(&dev
->event_lock
);
10905 if (intel_crtc
->unpin_work
) {
10906 /* Before declaring the flip queue wedged, check if
10907 * the hardware completed the operation behind our backs.
10909 if (__intel_pageflip_stall_check(dev
, crtc
)) {
10910 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10911 page_flip_completed(intel_crtc
);
10913 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10914 spin_unlock_irq(&dev
->event_lock
);
10916 drm_crtc_vblank_put(crtc
);
10921 intel_crtc
->unpin_work
= work
;
10922 spin_unlock_irq(&dev
->event_lock
);
10924 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10925 flush_workqueue(dev_priv
->wq
);
10927 /* Reference the objects for the scheduled work. */
10928 drm_framebuffer_reference(work
->old_fb
);
10929 drm_gem_object_reference(&obj
->base
);
10931 crtc
->primary
->fb
= fb
;
10932 update_state_fb(crtc
->primary
);
10934 work
->pending_flip_obj
= obj
;
10936 ret
= i915_mutex_lock_interruptible(dev
);
10940 atomic_inc(&intel_crtc
->unpin_work_count
);
10941 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
10943 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
10944 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
10946 if (IS_VALLEYVIEW(dev
)) {
10947 ring
= &dev_priv
->ring
[BCS
];
10948 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
10949 /* vlv: DISPLAY_FLIP fails to change tiling */
10951 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
10952 ring
= &dev_priv
->ring
[BCS
];
10953 } else if (INTEL_INFO(dev
)->gen
>= 7) {
10954 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
10955 if (ring
== NULL
|| ring
->id
!= RCS
)
10956 ring
= &dev_priv
->ring
[BCS
];
10958 ring
= &dev_priv
->ring
[RCS
];
10961 mmio_flip
= use_mmio_flip(ring
, obj
);
10963 /* When using CS flips, we want to emit semaphores between rings.
10964 * However, when using mmio flips we will create a task to do the
10965 * synchronisation, so all we want here is to pin the framebuffer
10966 * into the display plane and skip any waits.
10968 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
10969 crtc
->primary
->state
,
10970 mmio_flip
? i915_gem_request_get_ring(obj
->last_read_req
) : ring
);
10972 goto cleanup_pending
;
10974 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
10975 + intel_crtc
->dspaddr_offset
;
10978 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
10981 goto cleanup_unpin
;
10983 i915_gem_request_assign(&work
->flip_queued_req
,
10984 obj
->last_write_req
);
10986 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
10989 goto cleanup_unpin
;
10991 i915_gem_request_assign(&work
->flip_queued_req
,
10992 intel_ring_get_request(ring
));
10995 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
10996 work
->enable_stall_check
= true;
10998 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
10999 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11001 intel_fbc_disable(dev
);
11002 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11003 mutex_unlock(&dev
->struct_mutex
);
11005 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11010 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11012 atomic_dec(&intel_crtc
->unpin_work_count
);
11013 mutex_unlock(&dev
->struct_mutex
);
11015 crtc
->primary
->fb
= old_fb
;
11016 update_state_fb(crtc
->primary
);
11018 drm_gem_object_unreference_unlocked(&obj
->base
);
11019 drm_framebuffer_unreference(work
->old_fb
);
11021 spin_lock_irq(&dev
->event_lock
);
11022 intel_crtc
->unpin_work
= NULL
;
11023 spin_unlock_irq(&dev
->event_lock
);
11025 drm_crtc_vblank_put(crtc
);
11031 ret
= intel_plane_restore(primary
);
11032 if (ret
== 0 && event
) {
11033 spin_lock_irq(&dev
->event_lock
);
11034 drm_send_vblank_event(dev
, pipe
, event
);
11035 spin_unlock_irq(&dev
->event_lock
);
11041 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11042 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11043 .load_lut
= intel_crtc_load_lut
,
11044 .atomic_begin
= intel_begin_crtc_commit
,
11045 .atomic_flush
= intel_finish_crtc_commit
,
11049 * intel_modeset_update_staged_output_state
11051 * Updates the staged output configuration state, e.g. after we've read out the
11052 * current hw state.
11054 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
11056 struct intel_crtc
*crtc
;
11057 struct intel_encoder
*encoder
;
11058 struct intel_connector
*connector
;
11060 for_each_intel_connector(dev
, connector
) {
11061 connector
->new_encoder
=
11062 to_intel_encoder(connector
->base
.encoder
);
11065 for_each_intel_encoder(dev
, encoder
) {
11066 encoder
->new_crtc
=
11067 to_intel_crtc(encoder
->base
.crtc
);
11070 for_each_intel_crtc(dev
, crtc
) {
11071 crtc
->new_enabled
= crtc
->base
.state
->enable
;
11075 /* Transitional helper to copy current connector/encoder state to
11076 * connector->state. This is needed so that code that is partially
11077 * converted to atomic does the right thing.
11079 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11081 struct intel_connector
*connector
;
11083 for_each_intel_connector(dev
, connector
) {
11084 if (connector
->base
.encoder
) {
11085 connector
->base
.state
->best_encoder
=
11086 connector
->base
.encoder
;
11087 connector
->base
.state
->crtc
=
11088 connector
->base
.encoder
->crtc
;
11090 connector
->base
.state
->best_encoder
= NULL
;
11091 connector
->base
.state
->crtc
= NULL
;
11097 * intel_modeset_commit_output_state
11099 * This function copies the stage display pipe configuration to the real one.
11101 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
11103 struct intel_crtc
*crtc
;
11104 struct intel_encoder
*encoder
;
11105 struct intel_connector
*connector
;
11107 for_each_intel_connector(dev
, connector
) {
11108 connector
->base
.encoder
= &connector
->new_encoder
->base
;
11111 for_each_intel_encoder(dev
, encoder
) {
11112 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
11115 for_each_intel_crtc(dev
, crtc
) {
11116 crtc
->base
.state
->enable
= crtc
->new_enabled
;
11117 crtc
->base
.enabled
= crtc
->new_enabled
;
11120 intel_modeset_update_connector_atomic_state(dev
);
11124 connected_sink_compute_bpp(struct intel_connector
*connector
,
11125 struct intel_crtc_state
*pipe_config
)
11127 int bpp
= pipe_config
->pipe_bpp
;
11129 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11130 connector
->base
.base
.id
,
11131 connector
->base
.name
);
11133 /* Don't use an invalid EDID bpc value */
11134 if (connector
->base
.display_info
.bpc
&&
11135 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11136 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11137 bpp
, connector
->base
.display_info
.bpc
*3);
11138 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11141 /* Clamp bpp to 8 on screens without EDID 1.4 */
11142 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11143 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11145 pipe_config
->pipe_bpp
= 24;
11150 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11151 struct intel_crtc_state
*pipe_config
)
11153 struct drm_device
*dev
= crtc
->base
.dev
;
11154 struct drm_atomic_state
*state
;
11155 struct intel_connector
*connector
;
11158 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11160 else if (INTEL_INFO(dev
)->gen
>= 5)
11166 pipe_config
->pipe_bpp
= bpp
;
11168 state
= pipe_config
->base
.state
;
11170 /* Clamp display bpp to EDID value */
11171 for (i
= 0; i
< state
->num_connector
; i
++) {
11172 if (!state
->connectors
[i
])
11175 connector
= to_intel_connector(state
->connectors
[i
]);
11176 if (state
->connector_states
[i
]->crtc
!= &crtc
->base
)
11179 connected_sink_compute_bpp(connector
, pipe_config
);
11185 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11187 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11188 "type: 0x%x flags: 0x%x\n",
11190 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11191 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11192 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11193 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11196 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11197 struct intel_crtc_state
*pipe_config
,
11198 const char *context
)
11200 struct drm_device
*dev
= crtc
->base
.dev
;
11201 struct drm_plane
*plane
;
11202 struct intel_plane
*intel_plane
;
11203 struct intel_plane_state
*state
;
11204 struct drm_framebuffer
*fb
;
11206 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11207 context
, pipe_config
, pipe_name(crtc
->pipe
));
11209 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11210 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11211 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11212 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11213 pipe_config
->has_pch_encoder
,
11214 pipe_config
->fdi_lanes
,
11215 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11216 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11217 pipe_config
->fdi_m_n
.tu
);
11218 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11219 pipe_config
->has_dp_encoder
,
11220 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11221 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11222 pipe_config
->dp_m_n
.tu
);
11224 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11225 pipe_config
->has_dp_encoder
,
11226 pipe_config
->dp_m2_n2
.gmch_m
,
11227 pipe_config
->dp_m2_n2
.gmch_n
,
11228 pipe_config
->dp_m2_n2
.link_m
,
11229 pipe_config
->dp_m2_n2
.link_n
,
11230 pipe_config
->dp_m2_n2
.tu
);
11232 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11233 pipe_config
->has_audio
,
11234 pipe_config
->has_infoframe
);
11236 DRM_DEBUG_KMS("requested mode:\n");
11237 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11238 DRM_DEBUG_KMS("adjusted mode:\n");
11239 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11240 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11241 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11242 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11243 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11244 DRM_DEBUG_KMS("num_scalers: %d\n", crtc
->num_scalers
);
11245 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config
->scaler_state
.scaler_users
);
11246 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config
->scaler_state
.scaler_id
);
11247 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11248 pipe_config
->gmch_pfit
.control
,
11249 pipe_config
->gmch_pfit
.pgm_ratios
,
11250 pipe_config
->gmch_pfit
.lvds_border_bits
);
11251 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11252 pipe_config
->pch_pfit
.pos
,
11253 pipe_config
->pch_pfit
.size
,
11254 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11255 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11256 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11258 DRM_DEBUG_KMS("planes on this crtc\n");
11259 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11260 intel_plane
= to_intel_plane(plane
);
11261 if (intel_plane
->pipe
!= crtc
->pipe
)
11264 state
= to_intel_plane_state(plane
->state
);
11265 fb
= state
->base
.fb
;
11267 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11268 "disabled, scaler_id = %d\n",
11269 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11270 plane
->base
.id
, intel_plane
->pipe
,
11271 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
11272 drm_plane_index(plane
), state
->scaler_id
);
11276 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11277 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11278 plane
->base
.id
, intel_plane
->pipe
,
11279 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
11280 drm_plane_index(plane
));
11281 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11282 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
11283 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11285 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
11286 drm_rect_width(&state
->src
) >> 16,
11287 drm_rect_height(&state
->src
) >> 16,
11288 state
->dst
.x1
, state
->dst
.y1
,
11289 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
11293 static bool encoders_cloneable(const struct intel_encoder
*a
,
11294 const struct intel_encoder
*b
)
11296 /* masks could be asymmetric, so check both ways */
11297 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11298 b
->cloneable
& (1 << a
->type
));
11301 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11302 struct intel_crtc
*crtc
,
11303 struct intel_encoder
*encoder
)
11305 struct intel_encoder
*source_encoder
;
11306 struct drm_connector_state
*connector_state
;
11309 for (i
= 0; i
< state
->num_connector
; i
++) {
11310 if (!state
->connectors
[i
])
11313 connector_state
= state
->connector_states
[i
];
11314 if (connector_state
->crtc
!= &crtc
->base
)
11318 to_intel_encoder(connector_state
->best_encoder
);
11319 if (!encoders_cloneable(encoder
, source_encoder
))
11326 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11327 struct intel_crtc
*crtc
)
11329 struct intel_encoder
*encoder
;
11330 struct drm_connector_state
*connector_state
;
11333 for (i
= 0; i
< state
->num_connector
; i
++) {
11334 if (!state
->connectors
[i
])
11337 connector_state
= state
->connector_states
[i
];
11338 if (connector_state
->crtc
!= &crtc
->base
)
11341 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11342 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11349 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11351 struct drm_device
*dev
= state
->dev
;
11352 struct intel_encoder
*encoder
;
11353 struct drm_connector_state
*connector_state
;
11354 unsigned int used_ports
= 0;
11358 * Walk the connector list instead of the encoder
11359 * list to detect the problem on ddi platforms
11360 * where there's just one encoder per digital port.
11362 for (i
= 0; i
< state
->num_connector
; i
++) {
11363 if (!state
->connectors
[i
])
11366 connector_state
= state
->connector_states
[i
];
11367 if (!connector_state
->best_encoder
)
11370 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11372 WARN_ON(!connector_state
->crtc
);
11374 switch (encoder
->type
) {
11375 unsigned int port_mask
;
11376 case INTEL_OUTPUT_UNKNOWN
:
11377 if (WARN_ON(!HAS_DDI(dev
)))
11379 case INTEL_OUTPUT_DISPLAYPORT
:
11380 case INTEL_OUTPUT_HDMI
:
11381 case INTEL_OUTPUT_EDP
:
11382 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
11384 /* the same port mustn't appear more than once */
11385 if (used_ports
& port_mask
)
11388 used_ports
|= port_mask
;
11398 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11400 struct drm_crtc_state tmp_state
;
11401 struct intel_crtc_scaler_state scaler_state
;
11403 /* Clear only the intel specific part of the crtc state excluding scalers */
11404 tmp_state
= crtc_state
->base
;
11405 scaler_state
= crtc_state
->scaler_state
;
11406 memset(crtc_state
, 0, sizeof *crtc_state
);
11407 crtc_state
->base
= tmp_state
;
11408 crtc_state
->scaler_state
= scaler_state
;
11411 static struct intel_crtc_state
*
11412 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11413 struct drm_display_mode
*mode
,
11414 struct drm_atomic_state
*state
)
11416 struct intel_encoder
*encoder
;
11417 struct intel_connector
*connector
;
11418 struct drm_connector_state
*connector_state
;
11419 struct intel_crtc_state
*pipe_config
;
11420 int base_bpp
, ret
= -EINVAL
;
11424 if (!check_encoder_cloning(state
, to_intel_crtc(crtc
))) {
11425 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11426 return ERR_PTR(-EINVAL
);
11429 if (!check_digital_port_conflicts(state
)) {
11430 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11431 return ERR_PTR(-EINVAL
);
11434 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
11435 if (IS_ERR(pipe_config
))
11436 return pipe_config
;
11438 clear_intel_crtc_state(pipe_config
);
11440 pipe_config
->base
.crtc
= crtc
;
11441 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
11442 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
11444 pipe_config
->cpu_transcoder
=
11445 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11446 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
11449 * Sanitize sync polarity flags based on requested ones. If neither
11450 * positive or negative polarity is requested, treat this as meaning
11451 * negative polarity.
11453 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11454 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
11455 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
11457 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11458 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
11459 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
11461 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11462 * plane pixel format and any sink constraints into account. Returns the
11463 * source plane bpp so that dithering can be selected on mismatches
11464 * after encoders and crtc also have had their say. */
11465 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
11471 * Determine the real pipe dimensions. Note that stereo modes can
11472 * increase the actual pipe size due to the frame doubling and
11473 * insertion of additional space for blanks between the frame. This
11474 * is stored in the crtc timings. We use the requested mode to do this
11475 * computation to clearly distinguish it from the adjusted mode, which
11476 * can be changed by the connectors in the below retry loop.
11478 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
11479 &pipe_config
->pipe_src_w
,
11480 &pipe_config
->pipe_src_h
);
11483 /* Ensure the port clock defaults are reset when retrying. */
11484 pipe_config
->port_clock
= 0;
11485 pipe_config
->pixel_multiplier
= 1;
11487 /* Fill in default crtc timings, allow encoders to overwrite them. */
11488 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
11489 CRTC_STEREO_DOUBLE
);
11491 /* Pass our mode to the connectors and the CRTC to give them a chance to
11492 * adjust it according to limitations or connector properties, and also
11493 * a chance to reject the mode entirely.
11495 for (i
= 0; i
< state
->num_connector
; i
++) {
11496 connector
= to_intel_connector(state
->connectors
[i
]);
11500 connector_state
= state
->connector_states
[i
];
11501 if (connector_state
->crtc
!= crtc
)
11504 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11506 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
11507 DRM_DEBUG_KMS("Encoder config failure\n");
11512 /* Set default port clock if not overwritten by the encoder. Needs to be
11513 * done afterwards in case the encoder adjusts the mode. */
11514 if (!pipe_config
->port_clock
)
11515 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
11516 * pipe_config
->pixel_multiplier
;
11518 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
11520 DRM_DEBUG_KMS("CRTC fixup failed\n");
11524 if (ret
== RETRY
) {
11525 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
11530 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11532 goto encoder_retry
;
11535 pipe_config
->dither
= pipe_config
->pipe_bpp
!= base_bpp
;
11536 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11537 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
11539 return pipe_config
;
11541 return ERR_PTR(ret
);
11544 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
11545 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
11547 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
11548 unsigned *prepare_pipes
, unsigned *disable_pipes
)
11550 struct intel_crtc
*intel_crtc
;
11551 struct drm_device
*dev
= crtc
->dev
;
11552 struct intel_encoder
*encoder
;
11553 struct intel_connector
*connector
;
11554 struct drm_crtc
*tmp_crtc
;
11556 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
11558 /* Check which crtcs have changed outputs connected to them, these need
11559 * to be part of the prepare_pipes mask. We don't (yet) support global
11560 * modeset across multiple crtcs, so modeset_pipes will only have one
11561 * bit set at most. */
11562 for_each_intel_connector(dev
, connector
) {
11563 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
11566 if (connector
->base
.encoder
) {
11567 tmp_crtc
= connector
->base
.encoder
->crtc
;
11569 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
11572 if (connector
->new_encoder
)
11574 1 << connector
->new_encoder
->new_crtc
->pipe
;
11577 for_each_intel_encoder(dev
, encoder
) {
11578 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
11581 if (encoder
->base
.crtc
) {
11582 tmp_crtc
= encoder
->base
.crtc
;
11584 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
11587 if (encoder
->new_crtc
)
11588 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
11591 /* Check for pipes that will be enabled/disabled ... */
11592 for_each_intel_crtc(dev
, intel_crtc
) {
11593 if (intel_crtc
->base
.state
->enable
== intel_crtc
->new_enabled
)
11596 if (!intel_crtc
->new_enabled
)
11597 *disable_pipes
|= 1 << intel_crtc
->pipe
;
11599 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
11603 /* set_mode is also used to update properties on life display pipes. */
11604 intel_crtc
= to_intel_crtc(crtc
);
11605 if (intel_crtc
->new_enabled
)
11606 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
11609 * For simplicity do a full modeset on any pipe where the output routing
11610 * changed. We could be more clever, but that would require us to be
11611 * more careful with calling the relevant encoder->mode_set functions.
11613 if (*prepare_pipes
)
11614 *modeset_pipes
= *prepare_pipes
;
11616 /* ... and mask these out. */
11617 *modeset_pipes
&= ~(*disable_pipes
);
11618 *prepare_pipes
&= ~(*disable_pipes
);
11621 * HACK: We don't (yet) fully support global modesets. intel_set_config
11622 * obies this rule, but the modeset restore mode of
11623 * intel_modeset_setup_hw_state does not.
11625 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
11626 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
11628 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11629 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
11632 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
11634 struct drm_encoder
*encoder
;
11635 struct drm_device
*dev
= crtc
->dev
;
11637 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
11638 if (encoder
->crtc
== crtc
)
11645 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
11647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11648 struct intel_encoder
*intel_encoder
;
11649 struct intel_crtc
*intel_crtc
;
11650 struct drm_connector
*connector
;
11652 intel_shared_dpll_commit(dev_priv
);
11654 for_each_intel_encoder(dev
, intel_encoder
) {
11655 if (!intel_encoder
->base
.crtc
)
11658 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
11660 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
11661 intel_encoder
->connectors_active
= false;
11664 intel_modeset_commit_output_state(dev
);
11666 /* Double check state. */
11667 for_each_intel_crtc(dev
, intel_crtc
) {
11668 WARN_ON(intel_crtc
->base
.state
->enable
!= intel_crtc_in_use(&intel_crtc
->base
));
11671 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11672 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
11675 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
11677 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
11678 struct drm_property
*dpms_property
=
11679 dev
->mode_config
.dpms_property
;
11681 connector
->dpms
= DRM_MODE_DPMS_ON
;
11682 drm_object_property_set_value(&connector
->base
,
11686 intel_encoder
= to_intel_encoder(connector
->encoder
);
11687 intel_encoder
->connectors_active
= true;
11693 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11697 if (clock1
== clock2
)
11700 if (!clock1
|| !clock2
)
11703 diff
= abs(clock1
- clock2
);
11705 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11711 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11712 list_for_each_entry((intel_crtc), \
11713 &(dev)->mode_config.crtc_list, \
11715 if (mask & (1 <<(intel_crtc)->pipe))
11718 intel_pipe_config_compare(struct drm_device
*dev
,
11719 struct intel_crtc_state
*current_config
,
11720 struct intel_crtc_state
*pipe_config
)
11722 #define PIPE_CONF_CHECK_X(name) \
11723 if (current_config->name != pipe_config->name) { \
11724 DRM_ERROR("mismatch in " #name " " \
11725 "(expected 0x%08x, found 0x%08x)\n", \
11726 current_config->name, \
11727 pipe_config->name); \
11731 #define PIPE_CONF_CHECK_I(name) \
11732 if (current_config->name != pipe_config->name) { \
11733 DRM_ERROR("mismatch in " #name " " \
11734 "(expected %i, found %i)\n", \
11735 current_config->name, \
11736 pipe_config->name); \
11740 /* This is required for BDW+ where there is only one set of registers for
11741 * switching between high and low RR.
11742 * This macro can be used whenever a comparison has to be made between one
11743 * hw state and multiple sw state variables.
11745 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11746 if ((current_config->name != pipe_config->name) && \
11747 (current_config->alt_name != pipe_config->name)) { \
11748 DRM_ERROR("mismatch in " #name " " \
11749 "(expected %i or %i, found %i)\n", \
11750 current_config->name, \
11751 current_config->alt_name, \
11752 pipe_config->name); \
11756 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11757 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11758 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11759 "(expected %i, found %i)\n", \
11760 current_config->name & (mask), \
11761 pipe_config->name & (mask)); \
11765 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11766 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11767 DRM_ERROR("mismatch in " #name " " \
11768 "(expected %i, found %i)\n", \
11769 current_config->name, \
11770 pipe_config->name); \
11774 #define PIPE_CONF_QUIRK(quirk) \
11775 ((current_config->quirks | pipe_config->quirks) & (quirk))
11777 PIPE_CONF_CHECK_I(cpu_transcoder
);
11779 PIPE_CONF_CHECK_I(has_pch_encoder
);
11780 PIPE_CONF_CHECK_I(fdi_lanes
);
11781 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
11782 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
11783 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
11784 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
11785 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
11787 PIPE_CONF_CHECK_I(has_dp_encoder
);
11789 if (INTEL_INFO(dev
)->gen
< 8) {
11790 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
11791 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
11792 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
11793 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
11794 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
11796 if (current_config
->has_drrs
) {
11797 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
11798 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
11799 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
11800 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
11801 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
11804 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
11805 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
11806 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
11807 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
11808 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
11811 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11812 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11813 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11814 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11815 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11816 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11818 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11819 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11820 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11821 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11822 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11823 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11825 PIPE_CONF_CHECK_I(pixel_multiplier
);
11826 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11827 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
11828 IS_VALLEYVIEW(dev
))
11829 PIPE_CONF_CHECK_I(limited_color_range
);
11830 PIPE_CONF_CHECK_I(has_infoframe
);
11832 PIPE_CONF_CHECK_I(has_audio
);
11834 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11835 DRM_MODE_FLAG_INTERLACE
);
11837 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11838 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11839 DRM_MODE_FLAG_PHSYNC
);
11840 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11841 DRM_MODE_FLAG_NHSYNC
);
11842 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11843 DRM_MODE_FLAG_PVSYNC
);
11844 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11845 DRM_MODE_FLAG_NVSYNC
);
11848 PIPE_CONF_CHECK_I(pipe_src_w
);
11849 PIPE_CONF_CHECK_I(pipe_src_h
);
11852 * FIXME: BIOS likes to set up a cloned config with lvds+external
11853 * screen. Since we don't yet re-compute the pipe config when moving
11854 * just the lvds port away to another pipe the sw tracking won't match.
11856 * Proper atomic modesets with recomputed global state will fix this.
11857 * Until then just don't check gmch state for inherited modes.
11859 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
11860 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
11861 /* pfit ratios are autocomputed by the hw on gen4+ */
11862 if (INTEL_INFO(dev
)->gen
< 4)
11863 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
11864 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
11867 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11868 if (current_config
->pch_pfit
.enabled
) {
11869 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
11870 PIPE_CONF_CHECK_I(pch_pfit
.size
);
11873 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
11875 /* BDW+ don't expose a synchronous way to read the state */
11876 if (IS_HASWELL(dev
))
11877 PIPE_CONF_CHECK_I(ips_enabled
);
11879 PIPE_CONF_CHECK_I(double_wide
);
11881 PIPE_CONF_CHECK_X(ddi_pll_sel
);
11883 PIPE_CONF_CHECK_I(shared_dpll
);
11884 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11885 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11886 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11887 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11888 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11889 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11890 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11891 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11893 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
11894 PIPE_CONF_CHECK_I(pipe_bpp
);
11896 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11897 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11899 #undef PIPE_CONF_CHECK_X
11900 #undef PIPE_CONF_CHECK_I
11901 #undef PIPE_CONF_CHECK_I_ALT
11902 #undef PIPE_CONF_CHECK_FLAGS
11903 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11904 #undef PIPE_CONF_QUIRK
11909 static void check_wm_state(struct drm_device
*dev
)
11911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11912 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11913 struct intel_crtc
*intel_crtc
;
11916 if (INTEL_INFO(dev
)->gen
< 9)
11919 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11920 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11922 for_each_intel_crtc(dev
, intel_crtc
) {
11923 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
11924 const enum pipe pipe
= intel_crtc
->pipe
;
11926 if (!intel_crtc
->active
)
11930 for_each_plane(dev_priv
, pipe
, plane
) {
11931 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
11932 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
11934 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11937 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11938 "(expected (%u,%u), found (%u,%u))\n",
11939 pipe_name(pipe
), plane
+ 1,
11940 sw_entry
->start
, sw_entry
->end
,
11941 hw_entry
->start
, hw_entry
->end
);
11945 hw_entry
= &hw_ddb
.cursor
[pipe
];
11946 sw_entry
= &sw_ddb
->cursor
[pipe
];
11948 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11951 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11952 "(expected (%u,%u), found (%u,%u))\n",
11954 sw_entry
->start
, sw_entry
->end
,
11955 hw_entry
->start
, hw_entry
->end
);
11960 check_connector_state(struct drm_device
*dev
)
11962 struct intel_connector
*connector
;
11964 for_each_intel_connector(dev
, connector
) {
11965 /* This also checks the encoder/connector hw state with the
11966 * ->get_hw_state callbacks. */
11967 intel_connector_check_state(connector
);
11969 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
11970 "connector's staged encoder doesn't match current encoder\n");
11975 check_encoder_state(struct drm_device
*dev
)
11977 struct intel_encoder
*encoder
;
11978 struct intel_connector
*connector
;
11980 for_each_intel_encoder(dev
, encoder
) {
11981 bool enabled
= false;
11982 bool active
= false;
11983 enum pipe pipe
, tracked_pipe
;
11985 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11986 encoder
->base
.base
.id
,
11987 encoder
->base
.name
);
11989 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
11990 "encoder's stage crtc doesn't match current crtc\n");
11991 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
11992 "encoder's active_connectors set, but no crtc\n");
11994 for_each_intel_connector(dev
, connector
) {
11995 if (connector
->base
.encoder
!= &encoder
->base
)
11998 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
12002 * for MST connectors if we unplug the connector is gone
12003 * away but the encoder is still connected to a crtc
12004 * until a modeset happens in response to the hotplug.
12006 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
12009 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12010 "encoder's enabled state mismatch "
12011 "(expected %i, found %i)\n",
12012 !!encoder
->base
.crtc
, enabled
);
12013 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
12014 "active encoder with no crtc\n");
12016 I915_STATE_WARN(encoder
->connectors_active
!= active
,
12017 "encoder's computed active state doesn't match tracked active state "
12018 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
12020 active
= encoder
->get_hw_state(encoder
, &pipe
);
12021 I915_STATE_WARN(active
!= encoder
->connectors_active
,
12022 "encoder's hw state doesn't match sw tracking "
12023 "(expected %i, found %i)\n",
12024 encoder
->connectors_active
, active
);
12026 if (!encoder
->base
.crtc
)
12029 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
12030 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
12031 "active encoder's pipe doesn't match"
12032 "(expected %i, found %i)\n",
12033 tracked_pipe
, pipe
);
12039 check_crtc_state(struct drm_device
*dev
)
12041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12042 struct intel_crtc
*crtc
;
12043 struct intel_encoder
*encoder
;
12044 struct intel_crtc_state pipe_config
;
12046 for_each_intel_crtc(dev
, crtc
) {
12047 bool enabled
= false;
12048 bool active
= false;
12050 memset(&pipe_config
, 0, sizeof(pipe_config
));
12052 DRM_DEBUG_KMS("[CRTC:%d]\n",
12053 crtc
->base
.base
.id
);
12055 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
12056 "active crtc, but not enabled in sw tracking\n");
12058 for_each_intel_encoder(dev
, encoder
) {
12059 if (encoder
->base
.crtc
!= &crtc
->base
)
12062 if (encoder
->connectors_active
)
12066 I915_STATE_WARN(active
!= crtc
->active
,
12067 "crtc's computed active state doesn't match tracked active state "
12068 "(expected %i, found %i)\n", active
, crtc
->active
);
12069 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
12070 "crtc's computed enabled state doesn't match tracked enabled state "
12071 "(expected %i, found %i)\n", enabled
,
12072 crtc
->base
.state
->enable
);
12074 active
= dev_priv
->display
.get_pipe_config(crtc
,
12077 /* hw state is inconsistent with the pipe quirk */
12078 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12079 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12080 active
= crtc
->active
;
12082 for_each_intel_encoder(dev
, encoder
) {
12084 if (encoder
->base
.crtc
!= &crtc
->base
)
12086 if (encoder
->get_hw_state(encoder
, &pipe
))
12087 encoder
->get_config(encoder
, &pipe_config
);
12090 I915_STATE_WARN(crtc
->active
!= active
,
12091 "crtc active state doesn't match with hw state "
12092 "(expected %i, found %i)\n", crtc
->active
, active
);
12095 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
12096 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12097 intel_dump_pipe_config(crtc
, &pipe_config
,
12099 intel_dump_pipe_config(crtc
, crtc
->config
,
12106 check_shared_dpll_state(struct drm_device
*dev
)
12108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12109 struct intel_crtc
*crtc
;
12110 struct intel_dpll_hw_state dpll_hw_state
;
12113 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12114 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12115 int enabled_crtcs
= 0, active_crtcs
= 0;
12118 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12120 DRM_DEBUG_KMS("%s\n", pll
->name
);
12122 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12124 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12125 "more active pll users than references: %i vs %i\n",
12126 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12127 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12128 "pll in active use but not on in sw tracking\n");
12129 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12130 "pll in on but not on in use in sw tracking\n");
12131 I915_STATE_WARN(pll
->on
!= active
,
12132 "pll on state mismatch (expected %i, found %i)\n",
12135 for_each_intel_crtc(dev
, crtc
) {
12136 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12138 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12141 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12142 "pll active crtcs mismatch (expected %i, found %i)\n",
12143 pll
->active
, active_crtcs
);
12144 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12145 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12146 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12148 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12149 sizeof(dpll_hw_state
)),
12150 "pll hw state mismatch\n");
12155 intel_modeset_check_state(struct drm_device
*dev
)
12157 check_wm_state(dev
);
12158 check_connector_state(dev
);
12159 check_encoder_state(dev
);
12160 check_crtc_state(dev
);
12161 check_shared_dpll_state(dev
);
12164 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12168 * FDI already provided one idea for the dotclock.
12169 * Yell if the encoder disagrees.
12171 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12172 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12173 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12176 static void update_scanline_offset(struct intel_crtc
*crtc
)
12178 struct drm_device
*dev
= crtc
->base
.dev
;
12181 * The scanline counter increments at the leading edge of hsync.
12183 * On most platforms it starts counting from vtotal-1 on the
12184 * first active line. That means the scanline counter value is
12185 * always one less than what we would expect. Ie. just after
12186 * start of vblank, which also occurs at start of hsync (on the
12187 * last active line), the scanline counter will read vblank_start-1.
12189 * On gen2 the scanline counter starts counting from 1 instead
12190 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12191 * to keep the value positive), instead of adding one.
12193 * On HSW+ the behaviour of the scanline counter depends on the output
12194 * type. For DP ports it behaves like most other platforms, but on HDMI
12195 * there's an extra 1 line difference. So we need to add two instead of
12196 * one to the value.
12198 if (IS_GEN2(dev
)) {
12199 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
12202 vtotal
= mode
->crtc_vtotal
;
12203 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12206 crtc
->scanline_offset
= vtotal
- 1;
12207 } else if (HAS_DDI(dev
) &&
12208 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12209 crtc
->scanline_offset
= 2;
12211 crtc
->scanline_offset
= 1;
12214 static struct intel_crtc_state
*
12215 intel_modeset_compute_config(struct drm_crtc
*crtc
,
12216 struct drm_display_mode
*mode
,
12217 struct drm_atomic_state
*state
,
12218 unsigned *modeset_pipes
,
12219 unsigned *prepare_pipes
,
12220 unsigned *disable_pipes
)
12222 struct drm_device
*dev
= crtc
->dev
;
12223 struct intel_crtc_state
*pipe_config
= NULL
;
12224 struct intel_crtc
*intel_crtc
;
12227 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12229 return ERR_PTR(ret
);
12231 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
12232 prepare_pipes
, disable_pipes
);
12234 for_each_intel_crtc_masked(dev
, *disable_pipes
, intel_crtc
) {
12235 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12236 if (IS_ERR(pipe_config
))
12237 return pipe_config
;
12239 pipe_config
->base
.enable
= false;
12243 * Note this needs changes when we start tracking multiple modes
12244 * and crtcs. At that point we'll need to compute the whole config
12245 * (i.e. one pipe_config for each crtc) rather than just the one
12248 for_each_intel_crtc_masked(dev
, *modeset_pipes
, intel_crtc
) {
12249 /* FIXME: For now we still expect modeset_pipes has at most
12251 if (WARN_ON(&intel_crtc
->base
!= crtc
))
12254 pipe_config
= intel_modeset_pipe_config(crtc
, mode
, state
);
12255 if (IS_ERR(pipe_config
))
12256 return pipe_config
;
12258 pipe_config
->base
.enable
= true;
12260 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
12264 return intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));;
12267 static int __intel_set_mode_setup_plls(struct drm_atomic_state
*state
,
12268 unsigned modeset_pipes
,
12269 unsigned disable_pipes
)
12271 struct drm_device
*dev
= state
->dev
;
12272 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12273 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
12274 struct intel_crtc
*intel_crtc
;
12277 if (!dev_priv
->display
.crtc_compute_clock
)
12280 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
12284 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
12285 struct intel_crtc_state
*crtc_state
=
12286 intel_atomic_get_crtc_state(state
, intel_crtc
);
12288 /* Modeset pipes should have a new state by now */
12289 if (WARN_ON(IS_ERR(crtc_state
)))
12292 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12295 intel_shared_dpll_abort_config(dev_priv
);
12304 static int __intel_set_mode(struct drm_crtc
*crtc
,
12305 struct drm_display_mode
*mode
,
12306 int x
, int y
, struct drm_framebuffer
*fb
,
12307 struct intel_crtc_state
*pipe_config
,
12308 unsigned modeset_pipes
,
12309 unsigned prepare_pipes
,
12310 unsigned disable_pipes
)
12312 struct drm_device
*dev
= crtc
->dev
;
12313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12314 struct drm_display_mode
*saved_mode
;
12315 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12316 struct intel_crtc_state
*crtc_state_copy
= NULL
;
12317 struct intel_crtc
*intel_crtc
;
12320 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
12324 crtc_state_copy
= kmalloc(sizeof(*crtc_state_copy
), GFP_KERNEL
);
12325 if (!crtc_state_copy
) {
12330 *saved_mode
= crtc
->mode
;
12333 * See if the config requires any additional preparation, e.g.
12334 * to adjust global state with pipes off. We need to do this
12335 * here so we can get the modeset_pipe updated config for the new
12336 * mode set on this crtc. For other crtcs we need to use the
12337 * adjusted_mode bits in the crtc directly.
12339 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
12340 ret
= valleyview_modeset_global_pipes(state
, &prepare_pipes
);
12344 /* may have added more to prepare_pipes than we should */
12345 prepare_pipes
&= ~disable_pipes
;
12348 ret
= __intel_set_mode_setup_plls(state
, modeset_pipes
, disable_pipes
);
12352 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
12353 intel_crtc_disable(&intel_crtc
->base
);
12355 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
12356 if (intel_crtc
->base
.state
->enable
)
12357 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
12360 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12361 * to set it here already despite that we pass it down the callchain.
12363 * Note we'll need to fix this up when we start tracking multiple
12364 * pipes; here we assume a single modeset_pipe and only track the
12365 * single crtc and mode.
12367 if (modeset_pipes
) {
12368 crtc
->mode
= *mode
;
12369 /* mode_set/enable/disable functions rely on a correct pipe
12371 intel_crtc_set_state(to_intel_crtc(crtc
), pipe_config
);
12374 * Calculate and store various constants which
12375 * are later needed by vblank and swap-completion
12376 * timestamping. They are derived from true hwmode.
12378 drm_calc_timestamping_constants(crtc
,
12379 &pipe_config
->base
.adjusted_mode
);
12382 /* Only after disabling all output pipelines that will be changed can we
12383 * update the the output configuration. */
12384 intel_modeset_update_state(dev
, prepare_pipes
);
12386 modeset_update_crtc_power_domains(state
);
12388 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
12389 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
12390 int vdisplay
, hdisplay
;
12392 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
12393 ret
= drm_plane_helper_update(primary
, &intel_crtc
->base
,
12395 hdisplay
, vdisplay
,
12397 hdisplay
<< 16, vdisplay
<< 16);
12400 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12401 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
12402 update_scanline_offset(intel_crtc
);
12404 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
12407 /* FIXME: add subpixel order */
12409 if (ret
&& crtc
->state
->enable
)
12410 crtc
->mode
= *saved_mode
;
12412 if (ret
== 0 && pipe_config
) {
12413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12415 /* The pipe_config will be freed with the atomic state, so
12417 memcpy(crtc_state_copy
, intel_crtc
->config
,
12418 sizeof *crtc_state_copy
);
12419 intel_crtc
->config
= crtc_state_copy
;
12420 intel_crtc
->base
.state
= &crtc_state_copy
->base
;
12422 kfree(crtc_state_copy
);
12429 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
12430 struct drm_display_mode
*mode
,
12431 int x
, int y
, struct drm_framebuffer
*fb
,
12432 struct intel_crtc_state
*pipe_config
,
12433 unsigned modeset_pipes
,
12434 unsigned prepare_pipes
,
12435 unsigned disable_pipes
)
12439 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
12440 prepare_pipes
, disable_pipes
);
12443 intel_modeset_check_state(crtc
->dev
);
12448 static int intel_set_mode(struct drm_crtc
*crtc
,
12449 struct drm_display_mode
*mode
,
12450 int x
, int y
, struct drm_framebuffer
*fb
,
12451 struct drm_atomic_state
*state
)
12453 struct intel_crtc_state
*pipe_config
;
12454 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
12457 pipe_config
= intel_modeset_compute_config(crtc
, mode
, state
,
12462 if (IS_ERR(pipe_config
)) {
12463 ret
= PTR_ERR(pipe_config
);
12467 ret
= intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
12468 modeset_pipes
, prepare_pipes
,
12477 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
12479 struct drm_device
*dev
= crtc
->dev
;
12480 struct drm_atomic_state
*state
;
12481 struct intel_encoder
*encoder
;
12482 struct intel_connector
*connector
;
12483 struct drm_connector_state
*connector_state
;
12485 state
= drm_atomic_state_alloc(dev
);
12487 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12492 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12494 /* The force restore path in the HW readout code relies on the staged
12495 * config still keeping the user requested config while the actual
12496 * state has been overwritten by the configuration read from HW. We
12497 * need to copy the staged config to the atomic state, otherwise the
12498 * mode set will just reapply the state the HW is already in. */
12499 for_each_intel_encoder(dev
, encoder
) {
12500 if (&encoder
->new_crtc
->base
!= crtc
)
12503 for_each_intel_connector(dev
, connector
) {
12504 if (connector
->new_encoder
!= encoder
)
12507 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
12508 if (IS_ERR(connector_state
)) {
12509 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12510 connector
->base
.base
.id
,
12511 connector
->base
.name
,
12512 PTR_ERR(connector_state
));
12516 connector_state
->crtc
= crtc
;
12517 connector_state
->best_encoder
= &encoder
->base
;
12521 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
,
12524 drm_atomic_state_free(state
);
12527 #undef for_each_intel_crtc_masked
12529 static void intel_set_config_free(struct intel_set_config
*config
)
12534 kfree(config
->save_connector_encoders
);
12535 kfree(config
->save_encoder_crtcs
);
12536 kfree(config
->save_crtc_enabled
);
12540 static int intel_set_config_save_state(struct drm_device
*dev
,
12541 struct intel_set_config
*config
)
12543 struct drm_crtc
*crtc
;
12544 struct drm_encoder
*encoder
;
12545 struct drm_connector
*connector
;
12548 config
->save_crtc_enabled
=
12549 kcalloc(dev
->mode_config
.num_crtc
,
12550 sizeof(bool), GFP_KERNEL
);
12551 if (!config
->save_crtc_enabled
)
12554 config
->save_encoder_crtcs
=
12555 kcalloc(dev
->mode_config
.num_encoder
,
12556 sizeof(struct drm_crtc
*), GFP_KERNEL
);
12557 if (!config
->save_encoder_crtcs
)
12560 config
->save_connector_encoders
=
12561 kcalloc(dev
->mode_config
.num_connector
,
12562 sizeof(struct drm_encoder
*), GFP_KERNEL
);
12563 if (!config
->save_connector_encoders
)
12566 /* Copy data. Note that driver private data is not affected.
12567 * Should anything bad happen only the expected state is
12568 * restored, not the drivers personal bookkeeping.
12571 for_each_crtc(dev
, crtc
) {
12572 config
->save_crtc_enabled
[count
++] = crtc
->state
->enable
;
12576 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
12577 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
12581 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
12582 config
->save_connector_encoders
[count
++] = connector
->encoder
;
12588 static void intel_set_config_restore_state(struct drm_device
*dev
,
12589 struct intel_set_config
*config
)
12591 struct intel_crtc
*crtc
;
12592 struct intel_encoder
*encoder
;
12593 struct intel_connector
*connector
;
12597 for_each_intel_crtc(dev
, crtc
) {
12598 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
12602 for_each_intel_encoder(dev
, encoder
) {
12603 encoder
->new_crtc
=
12604 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
12608 for_each_intel_connector(dev
, connector
) {
12609 connector
->new_encoder
=
12610 to_intel_encoder(config
->save_connector_encoders
[count
++]);
12615 is_crtc_connector_off(struct drm_mode_set
*set
)
12619 if (set
->num_connectors
== 0)
12622 if (WARN_ON(set
->connectors
== NULL
))
12625 for (i
= 0; i
< set
->num_connectors
; i
++)
12626 if (set
->connectors
[i
]->encoder
&&
12627 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
12628 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
12635 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
12636 struct intel_set_config
*config
)
12639 /* We should be able to check here if the fb has the same properties
12640 * and then just flip_or_move it */
12641 if (is_crtc_connector_off(set
)) {
12642 config
->mode_changed
= true;
12643 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
12645 * If we have no fb, we can only flip as long as the crtc is
12646 * active, otherwise we need a full mode set. The crtc may
12647 * be active if we've only disabled the primary plane, or
12648 * in fastboot situations.
12650 if (set
->crtc
->primary
->fb
== NULL
) {
12651 struct intel_crtc
*intel_crtc
=
12652 to_intel_crtc(set
->crtc
);
12654 if (intel_crtc
->active
) {
12655 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12656 config
->fb_changed
= true;
12658 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12659 config
->mode_changed
= true;
12661 } else if (set
->fb
== NULL
) {
12662 config
->mode_changed
= true;
12663 } else if (set
->fb
->pixel_format
!=
12664 set
->crtc
->primary
->fb
->pixel_format
) {
12665 config
->mode_changed
= true;
12667 config
->fb_changed
= true;
12671 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
12672 config
->fb_changed
= true;
12674 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
12675 DRM_DEBUG_KMS("modes are different, full mode set\n");
12676 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
12677 drm_mode_debug_printmodeline(set
->mode
);
12678 config
->mode_changed
= true;
12681 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12682 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
12686 intel_modeset_stage_output_state(struct drm_device
*dev
,
12687 struct drm_mode_set
*set
,
12688 struct intel_set_config
*config
,
12689 struct drm_atomic_state
*state
)
12691 struct intel_connector
*connector
;
12692 struct drm_connector_state
*connector_state
;
12693 struct intel_encoder
*encoder
;
12694 struct intel_crtc
*crtc
;
12697 /* The upper layers ensure that we either disable a crtc or have a list
12698 * of connectors. For paranoia, double-check this. */
12699 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
12700 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
12702 for_each_intel_connector(dev
, connector
) {
12703 /* Otherwise traverse passed in connector list and get encoders
12705 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12706 if (set
->connectors
[ro
] == &connector
->base
) {
12707 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
12712 /* If we disable the crtc, disable all its connectors. Also, if
12713 * the connector is on the changing crtc but not on the new
12714 * connector list, disable it. */
12715 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
12716 connector
->base
.encoder
&&
12717 connector
->base
.encoder
->crtc
== set
->crtc
) {
12718 connector
->new_encoder
= NULL
;
12720 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12721 connector
->base
.base
.id
,
12722 connector
->base
.name
);
12726 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
12727 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12728 connector
->base
.base
.id
,
12729 connector
->base
.name
);
12730 config
->mode_changed
= true;
12733 /* connector->new_encoder is now updated for all connectors. */
12735 /* Update crtc of enabled connectors. */
12736 for_each_intel_connector(dev
, connector
) {
12737 struct drm_crtc
*new_crtc
;
12739 if (!connector
->new_encoder
)
12742 new_crtc
= connector
->new_encoder
->base
.crtc
;
12744 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12745 if (set
->connectors
[ro
] == &connector
->base
)
12746 new_crtc
= set
->crtc
;
12749 /* Make sure the new CRTC will work with the encoder */
12750 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
12754 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
12757 drm_atomic_get_connector_state(state
, &connector
->base
);
12758 if (IS_ERR(connector_state
))
12759 return PTR_ERR(connector_state
);
12761 connector_state
->crtc
= new_crtc
;
12762 connector_state
->best_encoder
= &connector
->new_encoder
->base
;
12764 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12765 connector
->base
.base
.id
,
12766 connector
->base
.name
,
12767 new_crtc
->base
.id
);
12770 /* Check for any encoders that needs to be disabled. */
12771 for_each_intel_encoder(dev
, encoder
) {
12772 int num_connectors
= 0;
12773 for_each_intel_connector(dev
, connector
) {
12774 if (connector
->new_encoder
== encoder
) {
12775 WARN_ON(!connector
->new_encoder
->new_crtc
);
12780 if (num_connectors
== 0)
12781 encoder
->new_crtc
= NULL
;
12782 else if (num_connectors
> 1)
12785 /* Only now check for crtc changes so we don't miss encoders
12786 * that will be disabled. */
12787 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
12788 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12789 encoder
->base
.base
.id
,
12790 encoder
->base
.name
);
12791 config
->mode_changed
= true;
12794 /* Now we've also updated encoder->new_crtc for all encoders. */
12795 for_each_intel_connector(dev
, connector
) {
12797 drm_atomic_get_connector_state(state
, &connector
->base
);
12798 if (IS_ERR(connector_state
))
12799 return PTR_ERR(connector_state
);
12801 if (connector
->new_encoder
) {
12802 if (connector
->new_encoder
!= connector
->encoder
)
12803 connector
->encoder
= connector
->new_encoder
;
12805 connector_state
->crtc
= NULL
;
12806 connector_state
->best_encoder
= NULL
;
12809 for_each_intel_crtc(dev
, crtc
) {
12810 crtc
->new_enabled
= false;
12812 for_each_intel_encoder(dev
, encoder
) {
12813 if (encoder
->new_crtc
== crtc
) {
12814 crtc
->new_enabled
= true;
12819 if (crtc
->new_enabled
!= crtc
->base
.state
->enable
) {
12820 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12821 crtc
->base
.base
.id
,
12822 crtc
->new_enabled
? "en" : "dis");
12823 config
->mode_changed
= true;
12830 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
12832 struct drm_device
*dev
= crtc
->base
.dev
;
12833 struct intel_encoder
*encoder
;
12834 struct intel_connector
*connector
;
12836 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12837 pipe_name(crtc
->pipe
));
12839 for_each_intel_connector(dev
, connector
) {
12840 if (connector
->new_encoder
&&
12841 connector
->new_encoder
->new_crtc
== crtc
)
12842 connector
->new_encoder
= NULL
;
12845 for_each_intel_encoder(dev
, encoder
) {
12846 if (encoder
->new_crtc
== crtc
)
12847 encoder
->new_crtc
= NULL
;
12850 crtc
->new_enabled
= false;
12853 static int intel_crtc_set_config(struct drm_mode_set
*set
)
12855 struct drm_device
*dev
;
12856 struct drm_mode_set save_set
;
12857 struct drm_atomic_state
*state
= NULL
;
12858 struct intel_set_config
*config
;
12859 struct intel_crtc_state
*pipe_config
;
12860 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
12864 BUG_ON(!set
->crtc
);
12865 BUG_ON(!set
->crtc
->helper_private
);
12867 /* Enforce sane interface api - has been abused by the fb helper. */
12868 BUG_ON(!set
->mode
&& set
->fb
);
12869 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
12872 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12873 set
->crtc
->base
.id
, set
->fb
->base
.id
,
12874 (int)set
->num_connectors
, set
->x
, set
->y
);
12876 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
12879 dev
= set
->crtc
->dev
;
12882 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
12886 ret
= intel_set_config_save_state(dev
, config
);
12890 save_set
.crtc
= set
->crtc
;
12891 save_set
.mode
= &set
->crtc
->mode
;
12892 save_set
.x
= set
->crtc
->x
;
12893 save_set
.y
= set
->crtc
->y
;
12894 save_set
.fb
= set
->crtc
->primary
->fb
;
12896 /* Compute whether we need a full modeset, only an fb base update or no
12897 * change at all. In the future we might also check whether only the
12898 * mode changed, e.g. for LVDS where we only change the panel fitter in
12900 intel_set_config_compute_mode_changes(set
, config
);
12902 state
= drm_atomic_state_alloc(dev
);
12908 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12910 ret
= intel_modeset_stage_output_state(dev
, set
, config
, state
);
12914 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
12919 if (IS_ERR(pipe_config
)) {
12920 ret
= PTR_ERR(pipe_config
);
12922 } else if (pipe_config
) {
12923 if (pipe_config
->has_audio
!=
12924 to_intel_crtc(set
->crtc
)->config
->has_audio
)
12925 config
->mode_changed
= true;
12928 * Note we have an issue here with infoframes: current code
12929 * only updates them on the full mode set path per hw
12930 * requirements. So here we should be checking for any
12931 * required changes and forcing a mode set.
12935 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
12937 if (config
->mode_changed
) {
12938 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
12939 set
->x
, set
->y
, set
->fb
, pipe_config
,
12940 modeset_pipes
, prepare_pipes
,
12942 } else if (config
->fb_changed
) {
12943 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
12944 struct drm_plane
*primary
= set
->crtc
->primary
;
12945 int vdisplay
, hdisplay
;
12947 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
12948 ret
= drm_plane_helper_update(primary
, set
->crtc
, set
->fb
,
12949 0, 0, hdisplay
, vdisplay
,
12950 set
->x
<< 16, set
->y
<< 16,
12951 hdisplay
<< 16, vdisplay
<< 16);
12954 * We need to make sure the primary plane is re-enabled if it
12955 * has previously been turned off.
12957 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
12958 WARN_ON(!intel_crtc
->active
);
12959 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
12963 * In the fastboot case this may be our only check of the
12964 * state after boot. It would be better to only do it on
12965 * the first update, but we don't have a nice way of doing that
12966 * (and really, set_config isn't used much for high freq page
12967 * flipping, so increasing its cost here shouldn't be a big
12970 if (i915
.fastboot
&& ret
== 0)
12971 intel_modeset_check_state(set
->crtc
->dev
);
12975 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12976 set
->crtc
->base
.id
, ret
);
12978 intel_set_config_restore_state(dev
, config
);
12980 drm_atomic_state_clear(state
);
12983 * HACK: if the pipe was on, but we didn't have a framebuffer,
12984 * force the pipe off to avoid oopsing in the modeset code
12985 * due to fb==NULL. This should only happen during boot since
12986 * we don't yet reconstruct the FB from the hardware state.
12988 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
12989 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
12991 /* Try to restore the config */
12992 if (config
->mode_changed
&&
12993 intel_set_mode(save_set
.crtc
, save_set
.mode
,
12994 save_set
.x
, save_set
.y
, save_set
.fb
,
12996 DRM_ERROR("failed to restore config after modeset failure\n");
13001 drm_atomic_state_free(state
);
13003 intel_set_config_free(config
);
13007 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13008 .gamma_set
= intel_crtc_gamma_set
,
13009 .set_config
= intel_crtc_set_config
,
13010 .destroy
= intel_crtc_destroy
,
13011 .page_flip
= intel_crtc_page_flip
,
13012 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13013 .atomic_destroy_state
= intel_crtc_destroy_state
,
13016 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
13017 struct intel_shared_dpll
*pll
,
13018 struct intel_dpll_hw_state
*hw_state
)
13022 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
13025 val
= I915_READ(PCH_DPLL(pll
->id
));
13026 hw_state
->dpll
= val
;
13027 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
13028 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
13030 return val
& DPLL_VCO_ENABLE
;
13033 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
13034 struct intel_shared_dpll
*pll
)
13036 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
13037 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13040 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13041 struct intel_shared_dpll
*pll
)
13043 /* PCH refclock must be enabled first */
13044 ibx_assert_pch_refclk_enabled(dev_priv
);
13046 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13048 /* Wait for the clocks to stabilize. */
13049 POSTING_READ(PCH_DPLL(pll
->id
));
13052 /* The pixel multiplier can only be updated once the
13053 * DPLL is enabled and the clocks are stable.
13055 * So write it again.
13057 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13058 POSTING_READ(PCH_DPLL(pll
->id
));
13062 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13063 struct intel_shared_dpll
*pll
)
13065 struct drm_device
*dev
= dev_priv
->dev
;
13066 struct intel_crtc
*crtc
;
13068 /* Make sure no transcoder isn't still depending on us. */
13069 for_each_intel_crtc(dev
, crtc
) {
13070 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13071 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13074 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13075 POSTING_READ(PCH_DPLL(pll
->id
));
13079 static char *ibx_pch_dpll_names
[] = {
13084 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13089 dev_priv
->num_shared_dpll
= 2;
13091 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13092 dev_priv
->shared_dplls
[i
].id
= i
;
13093 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13094 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13095 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13096 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13097 dev_priv
->shared_dplls
[i
].get_hw_state
=
13098 ibx_pch_dpll_get_hw_state
;
13102 static void intel_shared_dpll_init(struct drm_device
*dev
)
13104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13107 intel_ddi_pll_init(dev
);
13108 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13109 ibx_pch_dpll_init(dev
);
13111 dev_priv
->num_shared_dpll
= 0;
13113 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13117 * intel_wm_need_update - Check whether watermarks need updating
13118 * @plane: drm plane
13119 * @state: new plane state
13121 * Check current plane state versus the new one to determine whether
13122 * watermarks need to be recalculated.
13124 * Returns true or false.
13126 bool intel_wm_need_update(struct drm_plane
*plane
,
13127 struct drm_plane_state
*state
)
13129 /* Update watermarks on tiling changes. */
13130 if (!plane
->state
->fb
|| !state
->fb
||
13131 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
13132 plane
->state
->rotation
!= state
->rotation
)
13139 * intel_prepare_plane_fb - Prepare fb for usage on plane
13140 * @plane: drm plane to prepare for
13141 * @fb: framebuffer to prepare for presentation
13143 * Prepares a framebuffer for usage on a display plane. Generally this
13144 * involves pinning the underlying object and updating the frontbuffer tracking
13145 * bits. Some older platforms need special physical address handling for
13148 * Returns 0 on success, negative error code on failure.
13151 intel_prepare_plane_fb(struct drm_plane
*plane
,
13152 struct drm_framebuffer
*fb
,
13153 const struct drm_plane_state
*new_state
)
13155 struct drm_device
*dev
= plane
->dev
;
13156 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13157 enum pipe pipe
= intel_plane
->pipe
;
13158 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13159 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13160 unsigned frontbuffer_bits
= 0;
13166 switch (plane
->type
) {
13167 case DRM_PLANE_TYPE_PRIMARY
:
13168 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13170 case DRM_PLANE_TYPE_CURSOR
:
13171 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13173 case DRM_PLANE_TYPE_OVERLAY
:
13174 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
13178 mutex_lock(&dev
->struct_mutex
);
13180 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13181 INTEL_INFO(dev
)->cursor_needs_physical
) {
13182 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13183 ret
= i915_gem_object_attach_phys(obj
, align
);
13185 DRM_DEBUG_KMS("failed to attach phys object\n");
13187 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
13191 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
13193 mutex_unlock(&dev
->struct_mutex
);
13199 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13200 * @plane: drm plane to clean up for
13201 * @fb: old framebuffer that was on plane
13203 * Cleans up a framebuffer that has just been removed from a plane.
13206 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13207 struct drm_framebuffer
*fb
,
13208 const struct drm_plane_state
*old_state
)
13210 struct drm_device
*dev
= plane
->dev
;
13211 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13216 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13217 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13218 mutex_lock(&dev
->struct_mutex
);
13219 intel_unpin_fb_obj(fb
, old_state
);
13220 mutex_unlock(&dev
->struct_mutex
);
13225 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13228 struct drm_device
*dev
;
13229 struct drm_i915_private
*dev_priv
;
13230 int crtc_clock
, cdclk
;
13232 if (!intel_crtc
|| !crtc_state
)
13233 return DRM_PLANE_HELPER_NO_SCALING
;
13235 dev
= intel_crtc
->base
.dev
;
13236 dev_priv
= dev
->dev_private
;
13237 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13238 cdclk
= dev_priv
->display
.get_display_clock_speed(dev
);
13240 if (!crtc_clock
|| !cdclk
)
13241 return DRM_PLANE_HELPER_NO_SCALING
;
13244 * skl max scale is lower of:
13245 * close to 3 but not 3, -1 is for that purpose
13249 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13255 intel_check_primary_plane(struct drm_plane
*plane
,
13256 struct intel_plane_state
*state
)
13258 struct drm_device
*dev
= plane
->dev
;
13259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13260 struct drm_crtc
*crtc
= state
->base
.crtc
;
13261 struct intel_crtc
*intel_crtc
;
13262 struct intel_crtc_state
*crtc_state
;
13263 struct drm_framebuffer
*fb
= state
->base
.fb
;
13264 struct drm_rect
*dest
= &state
->dst
;
13265 struct drm_rect
*src
= &state
->src
;
13266 const struct drm_rect
*clip
= &state
->clip
;
13267 bool can_position
= false;
13268 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13269 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13272 crtc
= crtc
? crtc
: plane
->crtc
;
13273 intel_crtc
= to_intel_crtc(crtc
);
13274 crtc_state
= state
->base
.state
?
13275 intel_atomic_get_crtc_state(state
->base
.state
, intel_crtc
) : NULL
;
13277 if (INTEL_INFO(dev
)->gen
>= 9) {
13279 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
13280 can_position
= true;
13283 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13287 can_position
, true,
13292 if (intel_crtc
->active
) {
13293 intel_crtc
->atomic
.wait_for_flips
= true;
13296 * FBC does not work on some platforms for rotated
13297 * planes, so disable it when rotation is not 0 and
13298 * update it when rotation is set back to 0.
13300 * FIXME: This is redundant with the fbc update done in
13301 * the primary plane enable function except that that
13302 * one is done too late. We eventually need to unify
13305 if (intel_crtc
->primary_enabled
&&
13306 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
13307 dev_priv
->fbc
.crtc
== intel_crtc
&&
13308 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
13309 intel_crtc
->atomic
.disable_fbc
= true;
13312 if (state
->visible
) {
13314 * BDW signals flip done immediately if the plane
13315 * is disabled, even if the plane enable is already
13316 * armed to occur at the next vblank :(
13318 if (IS_BROADWELL(dev
) && !intel_crtc
->primary_enabled
)
13319 intel_crtc
->atomic
.wait_vblank
= true;
13322 intel_crtc
->atomic
.fb_bits
|=
13323 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
13325 intel_crtc
->atomic
.update_fbc
= true;
13327 if (intel_wm_need_update(plane
, &state
->base
))
13328 intel_crtc
->atomic
.update_wm
= true;
13331 if (INTEL_INFO(dev
)->gen
>= 9) {
13332 ret
= skl_update_scaler_users(intel_crtc
, crtc_state
,
13333 to_intel_plane(plane
), state
, 0);
13342 intel_commit_primary_plane(struct drm_plane
*plane
,
13343 struct intel_plane_state
*state
)
13345 struct drm_crtc
*crtc
= state
->base
.crtc
;
13346 struct drm_framebuffer
*fb
= state
->base
.fb
;
13347 struct drm_device
*dev
= plane
->dev
;
13348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13349 struct intel_crtc
*intel_crtc
;
13350 struct drm_rect
*src
= &state
->src
;
13352 crtc
= crtc
? crtc
: plane
->crtc
;
13353 intel_crtc
= to_intel_crtc(crtc
);
13356 crtc
->x
= src
->x1
>> 16;
13357 crtc
->y
= src
->y1
>> 16;
13359 if (intel_crtc
->active
) {
13360 if (state
->visible
) {
13361 /* FIXME: kill this fastboot hack */
13362 intel_update_pipe_size(intel_crtc
);
13364 intel_crtc
->primary_enabled
= true;
13366 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
13370 * If clipping results in a non-visible primary plane,
13371 * we'll disable the primary plane. Note that this is
13372 * a bit different than what happens if userspace
13373 * explicitly disables the plane by passing fb=0
13374 * because plane->fb still gets set and pinned.
13376 intel_disable_primary_hw_plane(plane
, crtc
);
13381 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
13383 struct drm_device
*dev
= crtc
->dev
;
13384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13386 struct intel_plane
*intel_plane
;
13387 struct drm_plane
*p
;
13388 unsigned fb_bits
= 0;
13390 /* Track fb's for any planes being disabled */
13391 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
13392 intel_plane
= to_intel_plane(p
);
13394 if (intel_crtc
->atomic
.disabled_planes
&
13395 (1 << drm_plane_index(p
))) {
13397 case DRM_PLANE_TYPE_PRIMARY
:
13398 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
13400 case DRM_PLANE_TYPE_CURSOR
:
13401 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
13403 case DRM_PLANE_TYPE_OVERLAY
:
13404 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
13408 mutex_lock(&dev
->struct_mutex
);
13409 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
13410 mutex_unlock(&dev
->struct_mutex
);
13414 if (intel_crtc
->atomic
.wait_for_flips
)
13415 intel_crtc_wait_for_pending_flips(crtc
);
13417 if (intel_crtc
->atomic
.disable_fbc
)
13418 intel_fbc_disable(dev
);
13420 if (intel_crtc
->atomic
.pre_disable_primary
)
13421 intel_pre_disable_primary(crtc
);
13423 if (intel_crtc
->atomic
.update_wm
)
13424 intel_update_watermarks(crtc
);
13426 intel_runtime_pm_get(dev_priv
);
13428 /* Perform vblank evasion around commit operation */
13429 if (intel_crtc
->active
)
13430 intel_crtc
->atomic
.evade
=
13431 intel_pipe_update_start(intel_crtc
,
13432 &intel_crtc
->atomic
.start_vbl_count
);
13435 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
13437 struct drm_device
*dev
= crtc
->dev
;
13438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13439 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13440 struct drm_plane
*p
;
13442 if (intel_crtc
->atomic
.evade
)
13443 intel_pipe_update_end(intel_crtc
,
13444 intel_crtc
->atomic
.start_vbl_count
);
13446 intel_runtime_pm_put(dev_priv
);
13448 if (intel_crtc
->atomic
.wait_vblank
)
13449 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
13451 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
13453 if (intel_crtc
->atomic
.update_fbc
) {
13454 mutex_lock(&dev
->struct_mutex
);
13455 intel_fbc_update(dev
);
13456 mutex_unlock(&dev
->struct_mutex
);
13459 if (intel_crtc
->atomic
.post_enable_primary
)
13460 intel_post_enable_primary(crtc
);
13462 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
13463 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
13464 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
13467 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
13471 * intel_plane_destroy - destroy a plane
13472 * @plane: plane to destroy
13474 * Common destruction function for all types of planes (primary, cursor,
13477 void intel_plane_destroy(struct drm_plane
*plane
)
13479 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13480 drm_plane_cleanup(plane
);
13481 kfree(intel_plane
);
13484 const struct drm_plane_funcs intel_plane_funcs
= {
13485 .update_plane
= drm_atomic_helper_update_plane
,
13486 .disable_plane
= drm_atomic_helper_disable_plane
,
13487 .destroy
= intel_plane_destroy
,
13488 .set_property
= drm_atomic_helper_plane_set_property
,
13489 .atomic_get_property
= intel_plane_atomic_get_property
,
13490 .atomic_set_property
= intel_plane_atomic_set_property
,
13491 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13492 .atomic_destroy_state
= intel_plane_destroy_state
,
13496 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13499 struct intel_plane
*primary
;
13500 struct intel_plane_state
*state
;
13501 const uint32_t *intel_primary_formats
;
13504 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13505 if (primary
== NULL
)
13508 state
= intel_create_plane_state(&primary
->base
);
13513 primary
->base
.state
= &state
->base
;
13515 primary
->can_scale
= false;
13516 primary
->max_downscale
= 1;
13517 if (INTEL_INFO(dev
)->gen
>= 9) {
13518 primary
->can_scale
= true;
13520 state
->scaler_id
= -1;
13521 primary
->pipe
= pipe
;
13522 primary
->plane
= pipe
;
13523 primary
->check_plane
= intel_check_primary_plane
;
13524 primary
->commit_plane
= intel_commit_primary_plane
;
13525 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
13526 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13527 primary
->plane
= !pipe
;
13529 if (INTEL_INFO(dev
)->gen
<= 3) {
13530 intel_primary_formats
= intel_primary_formats_gen2
;
13531 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
13533 intel_primary_formats
= intel_primary_formats_gen4
;
13534 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
13537 drm_universal_plane_init(dev
, &primary
->base
, 0,
13538 &intel_plane_funcs
,
13539 intel_primary_formats
, num_formats
,
13540 DRM_PLANE_TYPE_PRIMARY
);
13542 if (INTEL_INFO(dev
)->gen
>= 4)
13543 intel_create_rotation_property(dev
, primary
);
13545 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13547 return &primary
->base
;
13550 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13552 if (!dev
->mode_config
.rotation_property
) {
13553 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13554 BIT(DRM_ROTATE_180
);
13556 if (INTEL_INFO(dev
)->gen
>= 9)
13557 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13559 dev
->mode_config
.rotation_property
=
13560 drm_mode_create_rotation_property(dev
, flags
);
13562 if (dev
->mode_config
.rotation_property
)
13563 drm_object_attach_property(&plane
->base
.base
,
13564 dev
->mode_config
.rotation_property
,
13565 plane
->base
.state
->rotation
);
13569 intel_check_cursor_plane(struct drm_plane
*plane
,
13570 struct intel_plane_state
*state
)
13572 struct drm_crtc
*crtc
= state
->base
.crtc
;
13573 struct drm_device
*dev
= plane
->dev
;
13574 struct drm_framebuffer
*fb
= state
->base
.fb
;
13575 struct drm_rect
*dest
= &state
->dst
;
13576 struct drm_rect
*src
= &state
->src
;
13577 const struct drm_rect
*clip
= &state
->clip
;
13578 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13579 struct intel_crtc
*intel_crtc
;
13583 crtc
= crtc
? crtc
: plane
->crtc
;
13584 intel_crtc
= to_intel_crtc(crtc
);
13586 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13588 DRM_PLANE_HELPER_NO_SCALING
,
13589 DRM_PLANE_HELPER_NO_SCALING
,
13590 true, true, &state
->visible
);
13595 /* if we want to turn off the cursor ignore width and height */
13599 /* Check for which cursor types we support */
13600 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13601 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13602 state
->base
.crtc_w
, state
->base
.crtc_h
);
13606 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13607 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13608 DRM_DEBUG_KMS("buffer is too small\n");
13612 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13613 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13618 if (intel_crtc
->active
) {
13619 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
13620 intel_crtc
->atomic
.update_wm
= true;
13622 intel_crtc
->atomic
.fb_bits
|=
13623 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
13630 intel_commit_cursor_plane(struct drm_plane
*plane
,
13631 struct intel_plane_state
*state
)
13633 struct drm_crtc
*crtc
= state
->base
.crtc
;
13634 struct drm_device
*dev
= plane
->dev
;
13635 struct intel_crtc
*intel_crtc
;
13636 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13639 crtc
= crtc
? crtc
: plane
->crtc
;
13640 intel_crtc
= to_intel_crtc(crtc
);
13642 plane
->fb
= state
->base
.fb
;
13643 crtc
->cursor_x
= state
->base
.crtc_x
;
13644 crtc
->cursor_y
= state
->base
.crtc_y
;
13646 if (intel_crtc
->cursor_bo
== obj
)
13651 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13652 addr
= i915_gem_obj_ggtt_offset(obj
);
13654 addr
= obj
->phys_handle
->busaddr
;
13656 intel_crtc
->cursor_addr
= addr
;
13657 intel_crtc
->cursor_bo
= obj
;
13660 if (intel_crtc
->active
)
13661 intel_crtc_update_cursor(crtc
, state
->visible
);
13664 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13667 struct intel_plane
*cursor
;
13668 struct intel_plane_state
*state
;
13670 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13671 if (cursor
== NULL
)
13674 state
= intel_create_plane_state(&cursor
->base
);
13679 cursor
->base
.state
= &state
->base
;
13681 cursor
->can_scale
= false;
13682 cursor
->max_downscale
= 1;
13683 cursor
->pipe
= pipe
;
13684 cursor
->plane
= pipe
;
13685 state
->scaler_id
= -1;
13686 cursor
->check_plane
= intel_check_cursor_plane
;
13687 cursor
->commit_plane
= intel_commit_cursor_plane
;
13689 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13690 &intel_plane_funcs
,
13691 intel_cursor_formats
,
13692 ARRAY_SIZE(intel_cursor_formats
),
13693 DRM_PLANE_TYPE_CURSOR
);
13695 if (INTEL_INFO(dev
)->gen
>= 4) {
13696 if (!dev
->mode_config
.rotation_property
)
13697 dev
->mode_config
.rotation_property
=
13698 drm_mode_create_rotation_property(dev
,
13699 BIT(DRM_ROTATE_0
) |
13700 BIT(DRM_ROTATE_180
));
13701 if (dev
->mode_config
.rotation_property
)
13702 drm_object_attach_property(&cursor
->base
.base
,
13703 dev
->mode_config
.rotation_property
,
13704 state
->base
.rotation
);
13707 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13709 return &cursor
->base
;
13712 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13713 struct intel_crtc_state
*crtc_state
)
13716 struct intel_scaler
*intel_scaler
;
13717 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13719 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13720 intel_scaler
= &scaler_state
->scalers
[i
];
13721 intel_scaler
->in_use
= 0;
13722 intel_scaler
->id
= i
;
13724 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13727 scaler_state
->scaler_id
= -1;
13730 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13733 struct intel_crtc
*intel_crtc
;
13734 struct intel_crtc_state
*crtc_state
= NULL
;
13735 struct drm_plane
*primary
= NULL
;
13736 struct drm_plane
*cursor
= NULL
;
13739 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13740 if (intel_crtc
== NULL
)
13743 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13746 intel_crtc_set_state(intel_crtc
, crtc_state
);
13747 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13749 /* initialize shared scalers */
13750 if (INTEL_INFO(dev
)->gen
>= 9) {
13751 if (pipe
== PIPE_C
)
13752 intel_crtc
->num_scalers
= 1;
13754 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13756 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13759 primary
= intel_primary_plane_create(dev
, pipe
);
13763 cursor
= intel_cursor_plane_create(dev
, pipe
);
13767 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13768 cursor
, &intel_crtc_funcs
);
13772 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13773 for (i
= 0; i
< 256; i
++) {
13774 intel_crtc
->lut_r
[i
] = i
;
13775 intel_crtc
->lut_g
[i
] = i
;
13776 intel_crtc
->lut_b
[i
] = i
;
13780 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13781 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13783 intel_crtc
->pipe
= pipe
;
13784 intel_crtc
->plane
= pipe
;
13785 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13786 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13787 intel_crtc
->plane
= !pipe
;
13790 intel_crtc
->cursor_base
= ~0;
13791 intel_crtc
->cursor_cntl
= ~0;
13792 intel_crtc
->cursor_size
= ~0;
13794 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13795 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13796 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13797 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13799 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
13801 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13803 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13808 drm_plane_cleanup(primary
);
13810 drm_plane_cleanup(cursor
);
13815 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13817 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13818 struct drm_device
*dev
= connector
->base
.dev
;
13820 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13822 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13823 return INVALID_PIPE
;
13825 return to_intel_crtc(encoder
->crtc
)->pipe
;
13828 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13829 struct drm_file
*file
)
13831 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13832 struct drm_crtc
*drmmode_crtc
;
13833 struct intel_crtc
*crtc
;
13835 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13837 if (!drmmode_crtc
) {
13838 DRM_ERROR("no such CRTC id\n");
13842 crtc
= to_intel_crtc(drmmode_crtc
);
13843 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13848 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13850 struct drm_device
*dev
= encoder
->base
.dev
;
13851 struct intel_encoder
*source_encoder
;
13852 int index_mask
= 0;
13855 for_each_intel_encoder(dev
, source_encoder
) {
13856 if (encoders_cloneable(encoder
, source_encoder
))
13857 index_mask
|= (1 << entry
);
13865 static bool has_edp_a(struct drm_device
*dev
)
13867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13869 if (!IS_MOBILE(dev
))
13872 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13875 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13881 static bool intel_crt_present(struct drm_device
*dev
)
13883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13885 if (INTEL_INFO(dev
)->gen
>= 9)
13888 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13891 if (IS_CHERRYVIEW(dev
))
13894 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13900 static void intel_setup_outputs(struct drm_device
*dev
)
13902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13903 struct intel_encoder
*encoder
;
13904 bool dpd_is_edp
= false;
13906 intel_lvds_init(dev
);
13908 if (intel_crt_present(dev
))
13909 intel_crt_init(dev
);
13911 if (IS_BROXTON(dev
)) {
13913 * FIXME: Broxton doesn't support port detection via the
13914 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13915 * detect the ports.
13917 intel_ddi_init(dev
, PORT_A
);
13918 intel_ddi_init(dev
, PORT_B
);
13919 intel_ddi_init(dev
, PORT_C
);
13920 } else if (HAS_DDI(dev
)) {
13924 * Haswell uses DDI functions to detect digital outputs.
13925 * On SKL pre-D0 the strap isn't connected, so we assume
13928 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13929 /* WaIgnoreDDIAStrap: skl */
13931 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
13932 intel_ddi_init(dev
, PORT_A
);
13934 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13936 found
= I915_READ(SFUSE_STRAP
);
13938 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13939 intel_ddi_init(dev
, PORT_B
);
13940 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13941 intel_ddi_init(dev
, PORT_C
);
13942 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13943 intel_ddi_init(dev
, PORT_D
);
13944 } else if (HAS_PCH_SPLIT(dev
)) {
13946 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13948 if (has_edp_a(dev
))
13949 intel_dp_init(dev
, DP_A
, PORT_A
);
13951 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13952 /* PCH SDVOB multiplex with HDMIB */
13953 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13955 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13956 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13957 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13960 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13961 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13963 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13964 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13966 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13967 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13969 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13970 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13971 } else if (IS_VALLEYVIEW(dev
)) {
13973 * The DP_DETECTED bit is the latched state of the DDC
13974 * SDA pin at boot. However since eDP doesn't require DDC
13975 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13976 * eDP ports may have been muxed to an alternate function.
13977 * Thus we can't rely on the DP_DETECTED bit alone to detect
13978 * eDP ports. Consult the VBT as well as DP_DETECTED to
13979 * detect eDP ports.
13981 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13982 !intel_dp_is_edp(dev
, PORT_B
))
13983 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13985 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13986 intel_dp_is_edp(dev
, PORT_B
))
13987 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13989 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13990 !intel_dp_is_edp(dev
, PORT_C
))
13991 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13993 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
13994 intel_dp_is_edp(dev
, PORT_C
))
13995 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
13997 if (IS_CHERRYVIEW(dev
)) {
13998 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
13999 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
14001 /* eDP not supported on port D, so don't check VBT */
14002 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
14003 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
14006 intel_dsi_init(dev
);
14007 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
14008 bool found
= false;
14010 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14011 DRM_DEBUG_KMS("probing SDVOB\n");
14012 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
14013 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
14014 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14015 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14018 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
14019 intel_dp_init(dev
, DP_B
, PORT_B
);
14022 /* Before G4X SDVOC doesn't have its own detect register */
14024 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14025 DRM_DEBUG_KMS("probing SDVOC\n");
14026 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14029 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14031 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
14032 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14033 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14035 if (SUPPORTS_INTEGRATED_DP(dev
))
14036 intel_dp_init(dev
, DP_C
, PORT_C
);
14039 if (SUPPORTS_INTEGRATED_DP(dev
) &&
14040 (I915_READ(DP_D
) & DP_DETECTED
))
14041 intel_dp_init(dev
, DP_D
, PORT_D
);
14042 } else if (IS_GEN2(dev
))
14043 intel_dvo_init(dev
);
14045 if (SUPPORTS_TV(dev
))
14046 intel_tv_init(dev
);
14048 intel_psr_init(dev
);
14050 for_each_intel_encoder(dev
, encoder
) {
14051 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14052 encoder
->base
.possible_clones
=
14053 intel_encoder_clones(encoder
);
14056 intel_init_pch_refclk(dev
);
14058 drm_helper_move_panel_connectors_to_head(dev
);
14061 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14063 struct drm_device
*dev
= fb
->dev
;
14064 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14066 drm_framebuffer_cleanup(fb
);
14067 mutex_lock(&dev
->struct_mutex
);
14068 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14069 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14070 mutex_unlock(&dev
->struct_mutex
);
14074 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14075 struct drm_file
*file
,
14076 unsigned int *handle
)
14078 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14079 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14081 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14084 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14085 .destroy
= intel_user_framebuffer_destroy
,
14086 .create_handle
= intel_user_framebuffer_create_handle
,
14090 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14091 uint32_t pixel_format
)
14093 u32 gen
= INTEL_INFO(dev
)->gen
;
14096 /* "The stride in bytes must not exceed the of the size of 8K
14097 * pixels and 32K bytes."
14099 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14100 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14102 } else if (gen
>= 4) {
14103 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14107 } else if (gen
>= 3) {
14108 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14113 /* XXX DSPC is limited to 4k tiled */
14118 static int intel_framebuffer_init(struct drm_device
*dev
,
14119 struct intel_framebuffer
*intel_fb
,
14120 struct drm_mode_fb_cmd2
*mode_cmd
,
14121 struct drm_i915_gem_object
*obj
)
14123 unsigned int aligned_height
;
14125 u32 pitch_limit
, stride_alignment
;
14127 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14129 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14130 /* Enforce that fb modifier and tiling mode match, but only for
14131 * X-tiled. This is needed for FBC. */
14132 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14133 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14134 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14138 if (obj
->tiling_mode
== I915_TILING_X
)
14139 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14140 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14141 DRM_DEBUG("No Y tiling for legacy addfb\n");
14146 /* Passed in modifier sanity checking. */
14147 switch (mode_cmd
->modifier
[0]) {
14148 case I915_FORMAT_MOD_Y_TILED
:
14149 case I915_FORMAT_MOD_Yf_TILED
:
14150 if (INTEL_INFO(dev
)->gen
< 9) {
14151 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14152 mode_cmd
->modifier
[0]);
14155 case DRM_FORMAT_MOD_NONE
:
14156 case I915_FORMAT_MOD_X_TILED
:
14159 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14160 mode_cmd
->modifier
[0]);
14164 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14165 mode_cmd
->pixel_format
);
14166 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14167 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14168 mode_cmd
->pitches
[0], stride_alignment
);
14172 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14173 mode_cmd
->pixel_format
);
14174 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14175 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14176 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14177 "tiled" : "linear",
14178 mode_cmd
->pitches
[0], pitch_limit
);
14182 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14183 mode_cmd
->pitches
[0] != obj
->stride
) {
14184 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14185 mode_cmd
->pitches
[0], obj
->stride
);
14189 /* Reject formats not supported by any plane early. */
14190 switch (mode_cmd
->pixel_format
) {
14191 case DRM_FORMAT_C8
:
14192 case DRM_FORMAT_RGB565
:
14193 case DRM_FORMAT_XRGB8888
:
14194 case DRM_FORMAT_ARGB8888
:
14196 case DRM_FORMAT_XRGB1555
:
14197 case DRM_FORMAT_ARGB1555
:
14198 if (INTEL_INFO(dev
)->gen
> 3) {
14199 DRM_DEBUG("unsupported pixel format: %s\n",
14200 drm_get_format_name(mode_cmd
->pixel_format
));
14204 case DRM_FORMAT_XBGR8888
:
14205 case DRM_FORMAT_ABGR8888
:
14206 case DRM_FORMAT_XRGB2101010
:
14207 case DRM_FORMAT_ARGB2101010
:
14208 case DRM_FORMAT_XBGR2101010
:
14209 case DRM_FORMAT_ABGR2101010
:
14210 if (INTEL_INFO(dev
)->gen
< 4) {
14211 DRM_DEBUG("unsupported pixel format: %s\n",
14212 drm_get_format_name(mode_cmd
->pixel_format
));
14216 case DRM_FORMAT_YUYV
:
14217 case DRM_FORMAT_UYVY
:
14218 case DRM_FORMAT_YVYU
:
14219 case DRM_FORMAT_VYUY
:
14220 if (INTEL_INFO(dev
)->gen
< 5) {
14221 DRM_DEBUG("unsupported pixel format: %s\n",
14222 drm_get_format_name(mode_cmd
->pixel_format
));
14227 DRM_DEBUG("unsupported pixel format: %s\n",
14228 drm_get_format_name(mode_cmd
->pixel_format
));
14232 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14233 if (mode_cmd
->offsets
[0] != 0)
14236 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14237 mode_cmd
->pixel_format
,
14238 mode_cmd
->modifier
[0]);
14239 /* FIXME drm helper for size checks (especially planar formats)? */
14240 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14243 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14244 intel_fb
->obj
= obj
;
14245 intel_fb
->obj
->framebuffer_references
++;
14247 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14249 DRM_ERROR("framebuffer init failed %d\n", ret
);
14256 static struct drm_framebuffer
*
14257 intel_user_framebuffer_create(struct drm_device
*dev
,
14258 struct drm_file
*filp
,
14259 struct drm_mode_fb_cmd2
*mode_cmd
)
14261 struct drm_i915_gem_object
*obj
;
14263 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14264 mode_cmd
->handles
[0]));
14265 if (&obj
->base
== NULL
)
14266 return ERR_PTR(-ENOENT
);
14268 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14271 #ifndef CONFIG_DRM_I915_FBDEV
14272 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14277 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14278 .fb_create
= intel_user_framebuffer_create
,
14279 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14280 .atomic_check
= intel_atomic_check
,
14281 .atomic_commit
= intel_atomic_commit
,
14284 /* Set up chip specific display functions */
14285 static void intel_init_display(struct drm_device
*dev
)
14287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14289 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14290 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14291 else if (IS_CHERRYVIEW(dev
))
14292 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14293 else if (IS_VALLEYVIEW(dev
))
14294 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14295 else if (IS_PINEVIEW(dev
))
14296 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14298 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14300 if (INTEL_INFO(dev
)->gen
>= 9) {
14301 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14302 dev_priv
->display
.get_initial_plane_config
=
14303 skylake_get_initial_plane_config
;
14304 dev_priv
->display
.crtc_compute_clock
=
14305 haswell_crtc_compute_clock
;
14306 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14307 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14308 dev_priv
->display
.off
= ironlake_crtc_off
;
14309 dev_priv
->display
.update_primary_plane
=
14310 skylake_update_primary_plane
;
14311 } else if (HAS_DDI(dev
)) {
14312 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14313 dev_priv
->display
.get_initial_plane_config
=
14314 ironlake_get_initial_plane_config
;
14315 dev_priv
->display
.crtc_compute_clock
=
14316 haswell_crtc_compute_clock
;
14317 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14318 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14319 dev_priv
->display
.off
= ironlake_crtc_off
;
14320 dev_priv
->display
.update_primary_plane
=
14321 ironlake_update_primary_plane
;
14322 } else if (HAS_PCH_SPLIT(dev
)) {
14323 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14324 dev_priv
->display
.get_initial_plane_config
=
14325 ironlake_get_initial_plane_config
;
14326 dev_priv
->display
.crtc_compute_clock
=
14327 ironlake_crtc_compute_clock
;
14328 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14329 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14330 dev_priv
->display
.off
= ironlake_crtc_off
;
14331 dev_priv
->display
.update_primary_plane
=
14332 ironlake_update_primary_plane
;
14333 } else if (IS_VALLEYVIEW(dev
)) {
14334 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14335 dev_priv
->display
.get_initial_plane_config
=
14336 i9xx_get_initial_plane_config
;
14337 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14338 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14339 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14340 dev_priv
->display
.off
= i9xx_crtc_off
;
14341 dev_priv
->display
.update_primary_plane
=
14342 i9xx_update_primary_plane
;
14344 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14345 dev_priv
->display
.get_initial_plane_config
=
14346 i9xx_get_initial_plane_config
;
14347 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14348 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14349 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14350 dev_priv
->display
.off
= i9xx_crtc_off
;
14351 dev_priv
->display
.update_primary_plane
=
14352 i9xx_update_primary_plane
;
14355 /* Returns the core display clock speed */
14356 if (IS_SKYLAKE(dev
))
14357 dev_priv
->display
.get_display_clock_speed
=
14358 skylake_get_display_clock_speed
;
14359 else if (IS_BROADWELL(dev
))
14360 dev_priv
->display
.get_display_clock_speed
=
14361 broadwell_get_display_clock_speed
;
14362 else if (IS_HASWELL(dev
))
14363 dev_priv
->display
.get_display_clock_speed
=
14364 haswell_get_display_clock_speed
;
14365 else if (IS_VALLEYVIEW(dev
))
14366 dev_priv
->display
.get_display_clock_speed
=
14367 valleyview_get_display_clock_speed
;
14368 else if (IS_GEN5(dev
))
14369 dev_priv
->display
.get_display_clock_speed
=
14370 ilk_get_display_clock_speed
;
14371 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14372 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
14373 dev_priv
->display
.get_display_clock_speed
=
14374 i945_get_display_clock_speed
;
14375 else if (IS_I915G(dev
))
14376 dev_priv
->display
.get_display_clock_speed
=
14377 i915_get_display_clock_speed
;
14378 else if (IS_I945GM(dev
) || IS_845G(dev
))
14379 dev_priv
->display
.get_display_clock_speed
=
14380 i9xx_misc_get_display_clock_speed
;
14381 else if (IS_PINEVIEW(dev
))
14382 dev_priv
->display
.get_display_clock_speed
=
14383 pnv_get_display_clock_speed
;
14384 else if (IS_I915GM(dev
))
14385 dev_priv
->display
.get_display_clock_speed
=
14386 i915gm_get_display_clock_speed
;
14387 else if (IS_I865G(dev
))
14388 dev_priv
->display
.get_display_clock_speed
=
14389 i865_get_display_clock_speed
;
14390 else if (IS_I85X(dev
))
14391 dev_priv
->display
.get_display_clock_speed
=
14392 i855_get_display_clock_speed
;
14393 else /* 852, 830 */
14394 dev_priv
->display
.get_display_clock_speed
=
14395 i830_get_display_clock_speed
;
14397 if (IS_GEN5(dev
)) {
14398 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14399 } else if (IS_GEN6(dev
)) {
14400 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14401 } else if (IS_IVYBRIDGE(dev
)) {
14402 /* FIXME: detect B0+ stepping and use auto training */
14403 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14404 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14405 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14406 } else if (IS_VALLEYVIEW(dev
)) {
14407 dev_priv
->display
.modeset_global_resources
=
14408 valleyview_modeset_global_resources
;
14409 } else if (IS_BROXTON(dev
)) {
14410 dev_priv
->display
.modeset_global_resources
=
14411 broxton_modeset_global_resources
;
14414 switch (INTEL_INFO(dev
)->gen
) {
14416 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14420 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14425 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14429 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14432 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14433 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14436 /* Drop through - unsupported since execlist only. */
14438 /* Default just returns -ENODEV to indicate unsupported */
14439 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14442 intel_panel_init_backlight_funcs(dev
);
14444 mutex_init(&dev_priv
->pps_mutex
);
14448 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14449 * resume, or other times. This quirk makes sure that's the case for
14450 * affected systems.
14452 static void quirk_pipea_force(struct drm_device
*dev
)
14454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14456 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14457 DRM_INFO("applying pipe a force quirk\n");
14460 static void quirk_pipeb_force(struct drm_device
*dev
)
14462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14464 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14465 DRM_INFO("applying pipe b force quirk\n");
14469 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14471 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14474 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14475 DRM_INFO("applying lvds SSC disable quirk\n");
14479 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14482 static void quirk_invert_brightness(struct drm_device
*dev
)
14484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14485 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14486 DRM_INFO("applying inverted panel brightness quirk\n");
14489 /* Some VBT's incorrectly indicate no backlight is present */
14490 static void quirk_backlight_present(struct drm_device
*dev
)
14492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14493 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14494 DRM_INFO("applying backlight present quirk\n");
14497 struct intel_quirk
{
14499 int subsystem_vendor
;
14500 int subsystem_device
;
14501 void (*hook
)(struct drm_device
*dev
);
14504 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14505 struct intel_dmi_quirk
{
14506 void (*hook
)(struct drm_device
*dev
);
14507 const struct dmi_system_id (*dmi_id_list
)[];
14510 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14512 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14516 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14518 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14520 .callback
= intel_dmi_reverse_brightness
,
14521 .ident
= "NCR Corporation",
14522 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14523 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14526 { } /* terminating entry */
14528 .hook
= quirk_invert_brightness
,
14532 static struct intel_quirk intel_quirks
[] = {
14533 /* HP Mini needs pipe A force quirk (LP: #322104) */
14534 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
14536 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14537 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14539 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14540 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14542 /* 830 needs to leave pipe A & dpll A up */
14543 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14545 /* 830 needs to leave pipe B & dpll B up */
14546 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14548 /* Lenovo U160 cannot use SSC on LVDS */
14549 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14551 /* Sony Vaio Y cannot use SSC on LVDS */
14552 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14554 /* Acer Aspire 5734Z must invert backlight brightness */
14555 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14557 /* Acer/eMachines G725 */
14558 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14560 /* Acer/eMachines e725 */
14561 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14563 /* Acer/Packard Bell NCL20 */
14564 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14566 /* Acer Aspire 4736Z */
14567 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14569 /* Acer Aspire 5336 */
14570 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14572 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14573 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14575 /* Acer C720 Chromebook (Core i3 4005U) */
14576 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14578 /* Apple Macbook 2,1 (Core 2 T7400) */
14579 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14581 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14582 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14584 /* HP Chromebook 14 (Celeron 2955U) */
14585 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14587 /* Dell Chromebook 11 */
14588 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14591 static void intel_init_quirks(struct drm_device
*dev
)
14593 struct pci_dev
*d
= dev
->pdev
;
14596 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14597 struct intel_quirk
*q
= &intel_quirks
[i
];
14599 if (d
->device
== q
->device
&&
14600 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14601 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14602 (d
->subsystem_device
== q
->subsystem_device
||
14603 q
->subsystem_device
== PCI_ANY_ID
))
14606 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14607 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14608 intel_dmi_quirks
[i
].hook(dev
);
14612 /* Disable the VGA plane that we never use */
14613 static void i915_disable_vga(struct drm_device
*dev
)
14615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14617 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14619 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14620 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14621 outb(SR01
, VGA_SR_INDEX
);
14622 sr1
= inb(VGA_SR_DATA
);
14623 outb(sr1
| 1<<5, VGA_SR_DATA
);
14624 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14627 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14628 POSTING_READ(vga_reg
);
14631 void intel_modeset_init_hw(struct drm_device
*dev
)
14633 intel_prepare_ddi(dev
);
14635 if (IS_VALLEYVIEW(dev
))
14636 vlv_update_cdclk(dev
);
14638 intel_init_clock_gating(dev
);
14640 intel_enable_gt_powersave(dev
);
14643 void intel_modeset_init(struct drm_device
*dev
)
14645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14648 struct intel_crtc
*crtc
;
14650 drm_mode_config_init(dev
);
14652 dev
->mode_config
.min_width
= 0;
14653 dev
->mode_config
.min_height
= 0;
14655 dev
->mode_config
.preferred_depth
= 24;
14656 dev
->mode_config
.prefer_shadow
= 1;
14658 dev
->mode_config
.allow_fb_modifiers
= true;
14660 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14662 intel_init_quirks(dev
);
14664 intel_init_pm(dev
);
14666 if (INTEL_INFO(dev
)->num_pipes
== 0)
14669 intel_init_display(dev
);
14670 intel_init_audio(dev
);
14672 if (IS_GEN2(dev
)) {
14673 dev
->mode_config
.max_width
= 2048;
14674 dev
->mode_config
.max_height
= 2048;
14675 } else if (IS_GEN3(dev
)) {
14676 dev
->mode_config
.max_width
= 4096;
14677 dev
->mode_config
.max_height
= 4096;
14679 dev
->mode_config
.max_width
= 8192;
14680 dev
->mode_config
.max_height
= 8192;
14683 if (IS_845G(dev
) || IS_I865G(dev
)) {
14684 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14685 dev
->mode_config
.cursor_height
= 1023;
14686 } else if (IS_GEN2(dev
)) {
14687 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14688 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14690 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14691 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14694 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14696 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14697 INTEL_INFO(dev
)->num_pipes
,
14698 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14700 for_each_pipe(dev_priv
, pipe
) {
14701 intel_crtc_init(dev
, pipe
);
14702 for_each_sprite(dev_priv
, pipe
, sprite
) {
14703 ret
= intel_plane_init(dev
, pipe
, sprite
);
14705 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14706 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14710 intel_init_dpio(dev
);
14712 intel_shared_dpll_init(dev
);
14714 /* Just disable it once at startup */
14715 i915_disable_vga(dev
);
14716 intel_setup_outputs(dev
);
14718 /* Just in case the BIOS is doing something questionable. */
14719 intel_fbc_disable(dev
);
14721 drm_modeset_lock_all(dev
);
14722 intel_modeset_setup_hw_state(dev
, false);
14723 drm_modeset_unlock_all(dev
);
14725 for_each_intel_crtc(dev
, crtc
) {
14730 * Note that reserving the BIOS fb up front prevents us
14731 * from stuffing other stolen allocations like the ring
14732 * on top. This prevents some ugliness at boot time, and
14733 * can even allow for smooth boot transitions if the BIOS
14734 * fb is large enough for the active pipe configuration.
14736 if (dev_priv
->display
.get_initial_plane_config
) {
14737 dev_priv
->display
.get_initial_plane_config(crtc
,
14738 &crtc
->plane_config
);
14740 * If the fb is shared between multiple heads, we'll
14741 * just get the first one.
14743 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
14748 static void intel_enable_pipe_a(struct drm_device
*dev
)
14750 struct intel_connector
*connector
;
14751 struct drm_connector
*crt
= NULL
;
14752 struct intel_load_detect_pipe load_detect_temp
;
14753 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14755 /* We can't just switch on the pipe A, we need to set things up with a
14756 * proper mode and output configuration. As a gross hack, enable pipe A
14757 * by enabling the load detect pipe once. */
14758 for_each_intel_connector(dev
, connector
) {
14759 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14760 crt
= &connector
->base
;
14768 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14769 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14773 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14775 struct drm_device
*dev
= crtc
->base
.dev
;
14776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14779 if (INTEL_INFO(dev
)->num_pipes
== 1)
14782 reg
= DSPCNTR(!crtc
->plane
);
14783 val
= I915_READ(reg
);
14785 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14786 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14792 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14794 struct drm_device
*dev
= crtc
->base
.dev
;
14795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14798 /* Clear any frame start delays used for debugging left by the BIOS */
14799 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14800 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14802 /* restore vblank interrupts to correct state */
14803 drm_crtc_vblank_reset(&crtc
->base
);
14804 if (crtc
->active
) {
14805 update_scanline_offset(crtc
);
14806 drm_crtc_vblank_on(&crtc
->base
);
14809 /* We need to sanitize the plane -> pipe mapping first because this will
14810 * disable the crtc (and hence change the state) if it is wrong. Note
14811 * that gen4+ has a fixed plane -> pipe mapping. */
14812 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14813 struct intel_connector
*connector
;
14816 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14817 crtc
->base
.base
.id
);
14819 /* Pipe has the wrong plane attached and the plane is active.
14820 * Temporarily change the plane mapping and disable everything
14822 plane
= crtc
->plane
;
14823 crtc
->plane
= !plane
;
14824 crtc
->primary_enabled
= true;
14825 dev_priv
->display
.crtc_disable(&crtc
->base
);
14826 crtc
->plane
= plane
;
14828 /* ... and break all links. */
14829 for_each_intel_connector(dev
, connector
) {
14830 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
14833 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14834 connector
->base
.encoder
= NULL
;
14836 /* multiple connectors may have the same encoder:
14837 * handle them and break crtc link separately */
14838 for_each_intel_connector(dev
, connector
)
14839 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
14840 connector
->encoder
->base
.crtc
= NULL
;
14841 connector
->encoder
->connectors_active
= false;
14844 WARN_ON(crtc
->active
);
14845 crtc
->base
.state
->enable
= false;
14846 crtc
->base
.enabled
= false;
14849 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14850 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14851 /* BIOS forgot to enable pipe A, this mostly happens after
14852 * resume. Force-enable the pipe to fix this, the update_dpms
14853 * call below we restore the pipe to the right state, but leave
14854 * the required bits on. */
14855 intel_enable_pipe_a(dev
);
14858 /* Adjust the state of the output pipe according to whether we
14859 * have active connectors/encoders. */
14860 intel_crtc_update_dpms(&crtc
->base
);
14862 if (crtc
->active
!= crtc
->base
.state
->enable
) {
14863 struct intel_encoder
*encoder
;
14865 /* This can happen either due to bugs in the get_hw_state
14866 * functions or because the pipe is force-enabled due to the
14868 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14869 crtc
->base
.base
.id
,
14870 crtc
->base
.state
->enable
? "enabled" : "disabled",
14871 crtc
->active
? "enabled" : "disabled");
14873 crtc
->base
.state
->enable
= crtc
->active
;
14874 crtc
->base
.enabled
= crtc
->active
;
14876 /* Because we only establish the connector -> encoder ->
14877 * crtc links if something is active, this means the
14878 * crtc is now deactivated. Break the links. connector
14879 * -> encoder links are only establish when things are
14880 * actually up, hence no need to break them. */
14881 WARN_ON(crtc
->active
);
14883 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
14884 WARN_ON(encoder
->connectors_active
);
14885 encoder
->base
.crtc
= NULL
;
14889 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14891 * We start out with underrun reporting disabled to avoid races.
14892 * For correct bookkeeping mark this on active crtcs.
14894 * Also on gmch platforms we dont have any hardware bits to
14895 * disable the underrun reporting. Which means we need to start
14896 * out with underrun reporting disabled also on inactive pipes,
14897 * since otherwise we'll complain about the garbage we read when
14898 * e.g. coming up after runtime pm.
14900 * No protection against concurrent access is required - at
14901 * worst a fifo underrun happens which also sets this to false.
14903 crtc
->cpu_fifo_underrun_disabled
= true;
14904 crtc
->pch_fifo_underrun_disabled
= true;
14908 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14910 struct intel_connector
*connector
;
14911 struct drm_device
*dev
= encoder
->base
.dev
;
14913 /* We need to check both for a crtc link (meaning that the
14914 * encoder is active and trying to read from a pipe) and the
14915 * pipe itself being active. */
14916 bool has_active_crtc
= encoder
->base
.crtc
&&
14917 to_intel_crtc(encoder
->base
.crtc
)->active
;
14919 if (encoder
->connectors_active
&& !has_active_crtc
) {
14920 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14921 encoder
->base
.base
.id
,
14922 encoder
->base
.name
);
14924 /* Connector is active, but has no active pipe. This is
14925 * fallout from our resume register restoring. Disable
14926 * the encoder manually again. */
14927 if (encoder
->base
.crtc
) {
14928 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14929 encoder
->base
.base
.id
,
14930 encoder
->base
.name
);
14931 encoder
->disable(encoder
);
14932 if (encoder
->post_disable
)
14933 encoder
->post_disable(encoder
);
14935 encoder
->base
.crtc
= NULL
;
14936 encoder
->connectors_active
= false;
14938 /* Inconsistent output/port/pipe state happens presumably due to
14939 * a bug in one of the get_hw_state functions. Or someplace else
14940 * in our code, like the register restore mess on resume. Clamp
14941 * things to off as a safer default. */
14942 for_each_intel_connector(dev
, connector
) {
14943 if (connector
->encoder
!= encoder
)
14945 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14946 connector
->base
.encoder
= NULL
;
14949 /* Enabled encoders without active connectors will be fixed in
14950 * the crtc fixup. */
14953 void i915_redisable_vga_power_on(struct drm_device
*dev
)
14955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14956 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14958 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14959 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14960 i915_disable_vga(dev
);
14964 void i915_redisable_vga(struct drm_device
*dev
)
14966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14968 /* This function can be called both from intel_modeset_setup_hw_state or
14969 * at a very early point in our resume sequence, where the power well
14970 * structures are not yet restored. Since this function is at a very
14971 * paranoid "someone might have enabled VGA while we were not looking"
14972 * level, just check if the power well is enabled instead of trying to
14973 * follow the "don't touch the power well if we don't need it" policy
14974 * the rest of the driver uses. */
14975 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14978 i915_redisable_vga_power_on(dev
);
14981 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
14983 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
14988 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
14991 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14995 struct intel_crtc
*crtc
;
14996 struct intel_encoder
*encoder
;
14997 struct intel_connector
*connector
;
15000 for_each_intel_crtc(dev
, crtc
) {
15001 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
15003 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
15005 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
15008 crtc
->base
.state
->enable
= crtc
->active
;
15009 crtc
->base
.enabled
= crtc
->active
;
15010 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
15012 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15013 crtc
->base
.base
.id
,
15014 crtc
->active
? "enabled" : "disabled");
15017 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15018 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15020 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15021 &pll
->config
.hw_state
);
15023 pll
->config
.crtc_mask
= 0;
15024 for_each_intel_crtc(dev
, crtc
) {
15025 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15027 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15031 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15032 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15034 if (pll
->config
.crtc_mask
)
15035 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15038 for_each_intel_encoder(dev
, encoder
) {
15041 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15042 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15043 encoder
->base
.crtc
= &crtc
->base
;
15044 encoder
->get_config(encoder
, crtc
->config
);
15046 encoder
->base
.crtc
= NULL
;
15049 encoder
->connectors_active
= false;
15050 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15051 encoder
->base
.base
.id
,
15052 encoder
->base
.name
,
15053 encoder
->base
.crtc
? "enabled" : "disabled",
15057 for_each_intel_connector(dev
, connector
) {
15058 if (connector
->get_hw_state(connector
)) {
15059 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15060 connector
->encoder
->connectors_active
= true;
15061 connector
->base
.encoder
= &connector
->encoder
->base
;
15063 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15064 connector
->base
.encoder
= NULL
;
15066 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15067 connector
->base
.base
.id
,
15068 connector
->base
.name
,
15069 connector
->base
.encoder
? "enabled" : "disabled");
15073 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15074 * and i915 state tracking structures. */
15075 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
15076 bool force_restore
)
15078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15080 struct intel_crtc
*crtc
;
15081 struct intel_encoder
*encoder
;
15084 intel_modeset_readout_hw_state(dev
);
15087 * Now that we have the config, copy it to each CRTC struct
15088 * Note that this could go away if we move to using crtc_config
15089 * checking everywhere.
15091 for_each_intel_crtc(dev
, crtc
) {
15092 if (crtc
->active
&& i915
.fastboot
) {
15093 intel_mode_from_pipe_config(&crtc
->base
.mode
,
15095 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15096 crtc
->base
.base
.id
);
15097 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
15101 /* HW state is read out, now we need to sanitize this mess. */
15102 for_each_intel_encoder(dev
, encoder
) {
15103 intel_sanitize_encoder(encoder
);
15106 for_each_pipe(dev_priv
, pipe
) {
15107 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15108 intel_sanitize_crtc(crtc
);
15109 intel_dump_pipe_config(crtc
, crtc
->config
,
15110 "[setup_hw_state]");
15113 intel_modeset_update_connector_atomic_state(dev
);
15115 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15116 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15118 if (!pll
->on
|| pll
->active
)
15121 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15123 pll
->disable(dev_priv
, pll
);
15128 skl_wm_get_hw_state(dev
);
15129 else if (HAS_PCH_SPLIT(dev
))
15130 ilk_wm_get_hw_state(dev
);
15132 if (force_restore
) {
15133 i915_redisable_vga(dev
);
15136 * We need to use raw interfaces for restoring state to avoid
15137 * checking (bogus) intermediate states.
15139 for_each_pipe(dev_priv
, pipe
) {
15140 struct drm_crtc
*crtc
=
15141 dev_priv
->pipe_to_crtc_mapping
[pipe
];
15143 intel_crtc_restore_mode(crtc
);
15146 intel_modeset_update_staged_output_state(dev
);
15149 intel_modeset_check_state(dev
);
15152 void intel_modeset_gem_init(struct drm_device
*dev
)
15154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15155 struct drm_crtc
*c
;
15156 struct drm_i915_gem_object
*obj
;
15159 mutex_lock(&dev
->struct_mutex
);
15160 intel_init_gt_powersave(dev
);
15161 mutex_unlock(&dev
->struct_mutex
);
15164 * There may be no VBT; and if the BIOS enabled SSC we can
15165 * just keep using it to avoid unnecessary flicker. Whereas if the
15166 * BIOS isn't using it, don't assume it will work even if the VBT
15167 * indicates as much.
15169 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
15170 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15173 intel_modeset_init_hw(dev
);
15175 intel_setup_overlay(dev
);
15178 * Make sure any fbs we allocated at startup are properly
15179 * pinned & fenced. When we do the allocation it's too early
15182 for_each_crtc(dev
, c
) {
15183 obj
= intel_fb_obj(c
->primary
->fb
);
15187 mutex_lock(&dev
->struct_mutex
);
15188 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15192 mutex_unlock(&dev
->struct_mutex
);
15194 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15195 to_intel_crtc(c
)->pipe
);
15196 drm_framebuffer_unreference(c
->primary
->fb
);
15197 c
->primary
->fb
= NULL
;
15198 update_state_fb(c
->primary
);
15202 intel_backlight_register(dev
);
15205 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15207 struct drm_connector
*connector
= &intel_connector
->base
;
15209 intel_panel_destroy_backlight(connector
);
15210 drm_connector_unregister(connector
);
15213 void intel_modeset_cleanup(struct drm_device
*dev
)
15215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15216 struct drm_connector
*connector
;
15218 intel_disable_gt_powersave(dev
);
15220 intel_backlight_unregister(dev
);
15223 * Interrupts and polling as the first thing to avoid creating havoc.
15224 * Too much stuff here (turning of connectors, ...) would
15225 * experience fancy races otherwise.
15227 intel_irq_uninstall(dev_priv
);
15230 * Due to the hpd irq storm handling the hotplug work can re-arm the
15231 * poll handlers. Hence disable polling after hpd handling is shut down.
15233 drm_kms_helper_poll_fini(dev
);
15235 mutex_lock(&dev
->struct_mutex
);
15237 intel_unregister_dsm_handler();
15239 intel_fbc_disable(dev
);
15241 mutex_unlock(&dev
->struct_mutex
);
15243 /* flush any delayed tasks or pending work */
15244 flush_scheduled_work();
15246 /* destroy the backlight and sysfs files before encoders/connectors */
15247 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15248 struct intel_connector
*intel_connector
;
15250 intel_connector
= to_intel_connector(connector
);
15251 intel_connector
->unregister(intel_connector
);
15254 drm_mode_config_cleanup(dev
);
15256 intel_cleanup_overlay(dev
);
15258 mutex_lock(&dev
->struct_mutex
);
15259 intel_cleanup_gt_powersave(dev
);
15260 mutex_unlock(&dev
->struct_mutex
);
15264 * Return which encoder is currently attached for connector.
15266 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15268 return &intel_attached_encoder(connector
)->base
;
15271 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15272 struct intel_encoder
*encoder
)
15274 connector
->encoder
= encoder
;
15275 drm_mode_connector_attach_encoder(&connector
->base
,
15280 * set vga decode state - true == enable VGA decode
15282 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15285 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15288 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15289 DRM_ERROR("failed to read control word\n");
15293 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15297 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15299 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15301 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15302 DRM_ERROR("failed to write control word\n");
15309 struct intel_display_error_state
{
15311 u32 power_well_driver
;
15313 int num_transcoders
;
15315 struct intel_cursor_error_state
{
15320 } cursor
[I915_MAX_PIPES
];
15322 struct intel_pipe_error_state
{
15323 bool power_domain_on
;
15326 } pipe
[I915_MAX_PIPES
];
15328 struct intel_plane_error_state
{
15336 } plane
[I915_MAX_PIPES
];
15338 struct intel_transcoder_error_state
{
15339 bool power_domain_on
;
15340 enum transcoder cpu_transcoder
;
15353 struct intel_display_error_state
*
15354 intel_display_capture_error_state(struct drm_device
*dev
)
15356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15357 struct intel_display_error_state
*error
;
15358 int transcoders
[] = {
15366 if (INTEL_INFO(dev
)->num_pipes
== 0)
15369 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15373 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15374 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15376 for_each_pipe(dev_priv
, i
) {
15377 error
->pipe
[i
].power_domain_on
=
15378 __intel_display_power_is_enabled(dev_priv
,
15379 POWER_DOMAIN_PIPE(i
));
15380 if (!error
->pipe
[i
].power_domain_on
)
15383 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15384 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15385 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15387 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15388 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15389 if (INTEL_INFO(dev
)->gen
<= 3) {
15390 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15391 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15393 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15394 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15395 if (INTEL_INFO(dev
)->gen
>= 4) {
15396 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15397 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15400 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15402 if (HAS_GMCH_DISPLAY(dev
))
15403 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15406 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15407 if (HAS_DDI(dev_priv
->dev
))
15408 error
->num_transcoders
++; /* Account for eDP. */
15410 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15411 enum transcoder cpu_transcoder
= transcoders
[i
];
15413 error
->transcoder
[i
].power_domain_on
=
15414 __intel_display_power_is_enabled(dev_priv
,
15415 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15416 if (!error
->transcoder
[i
].power_domain_on
)
15419 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15421 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15422 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15423 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15424 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15425 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15426 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15427 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15433 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15436 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15437 struct drm_device
*dev
,
15438 struct intel_display_error_state
*error
)
15440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15446 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15447 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15448 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15449 error
->power_well_driver
);
15450 for_each_pipe(dev_priv
, i
) {
15451 err_printf(m
, "Pipe [%d]:\n", i
);
15452 err_printf(m
, " Power: %s\n",
15453 error
->pipe
[i
].power_domain_on
? "on" : "off");
15454 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15455 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15457 err_printf(m
, "Plane [%d]:\n", i
);
15458 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15459 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15460 if (INTEL_INFO(dev
)->gen
<= 3) {
15461 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15462 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15464 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15465 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15466 if (INTEL_INFO(dev
)->gen
>= 4) {
15467 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15468 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15471 err_printf(m
, "Cursor [%d]:\n", i
);
15472 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15473 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15474 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15477 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15478 err_printf(m
, "CPU transcoder: %c\n",
15479 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15480 err_printf(m
, " Power: %s\n",
15481 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15482 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15483 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15484 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15485 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15486 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15487 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15488 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15492 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15494 struct intel_crtc
*crtc
;
15496 for_each_intel_crtc(dev
, crtc
) {
15497 struct intel_unpin_work
*work
;
15499 spin_lock_irq(&dev
->event_lock
);
15501 work
= crtc
->unpin_work
;
15503 if (work
&& work
->event
&&
15504 work
->event
->base
.file_priv
== file
) {
15505 kfree(work
->event
);
15506 work
->event
= NULL
;
15509 spin_unlock_irq(&dev
->event_lock
);