2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
85 int target
, int refclk
, intel_clock_t
*match_clock
,
86 intel_clock_t
*best_clock
);
88 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
89 int target
, int refclk
, intel_clock_t
*match_clock
,
90 intel_clock_t
*best_clock
);
93 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
94 int target
, int refclk
, intel_clock_t
*match_clock
,
95 intel_clock_t
*best_clock
);
97 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
98 int target
, int refclk
, intel_clock_t
*match_clock
,
99 intel_clock_t
*best_clock
);
102 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
103 int target
, int refclk
, intel_clock_t
*match_clock
,
104 intel_clock_t
*best_clock
);
106 static inline u32
/* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
111 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo
= {
117 .dot
= { .min
= 25000, .max
= 350000 },
118 .vco
= { .min
= 930000, .max
= 1400000 },
119 .n
= { .min
= 3, .max
= 16 },
120 .m
= { .min
= 96, .max
= 140 },
121 .m1
= { .min
= 18, .max
= 26 },
122 .m2
= { .min
= 6, .max
= 16 },
123 .p
= { .min
= 4, .max
= 128 },
124 .p1
= { .min
= 2, .max
= 33 },
125 .p2
= { .dot_limit
= 165000,
126 .p2_slow
= 4, .p2_fast
= 2 },
127 .find_pll
= intel_find_best_PLL
,
130 static const intel_limit_t intel_limits_i8xx_lvds
= {
131 .dot
= { .min
= 25000, .max
= 350000 },
132 .vco
= { .min
= 930000, .max
= 1400000 },
133 .n
= { .min
= 3, .max
= 16 },
134 .m
= { .min
= 96, .max
= 140 },
135 .m1
= { .min
= 18, .max
= 26 },
136 .m2
= { .min
= 6, .max
= 16 },
137 .p
= { .min
= 4, .max
= 128 },
138 .p1
= { .min
= 1, .max
= 6 },
139 .p2
= { .dot_limit
= 165000,
140 .p2_slow
= 14, .p2_fast
= 7 },
141 .find_pll
= intel_find_best_PLL
,
144 static const intel_limit_t intel_limits_i9xx_sdvo
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 10, .max
= 22 },
150 .m2
= { .min
= 5, .max
= 9 },
151 .p
= { .min
= 5, .max
= 80 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 200000,
154 .p2_slow
= 10, .p2_fast
= 5 },
155 .find_pll
= intel_find_best_PLL
,
158 static const intel_limit_t intel_limits_i9xx_lvds
= {
159 .dot
= { .min
= 20000, .max
= 400000 },
160 .vco
= { .min
= 1400000, .max
= 2800000 },
161 .n
= { .min
= 1, .max
= 6 },
162 .m
= { .min
= 70, .max
= 120 },
163 .m1
= { .min
= 10, .max
= 22 },
164 .m2
= { .min
= 5, .max
= 9 },
165 .p
= { .min
= 7, .max
= 98 },
166 .p1
= { .min
= 1, .max
= 8 },
167 .p2
= { .dot_limit
= 112000,
168 .p2_slow
= 14, .p2_fast
= 7 },
169 .find_pll
= intel_find_best_PLL
,
173 static const intel_limit_t intel_limits_g4x_sdvo
= {
174 .dot
= { .min
= 25000, .max
= 270000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 17, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 10, .max
= 30 },
181 .p1
= { .min
= 1, .max
= 3},
182 .p2
= { .dot_limit
= 270000,
186 .find_pll
= intel_g4x_find_best_PLL
,
189 static const intel_limit_t intel_limits_g4x_hdmi
= {
190 .dot
= { .min
= 22000, .max
= 400000 },
191 .vco
= { .min
= 1750000, .max
= 3500000},
192 .n
= { .min
= 1, .max
= 4 },
193 .m
= { .min
= 104, .max
= 138 },
194 .m1
= { .min
= 16, .max
= 23 },
195 .m2
= { .min
= 5, .max
= 11 },
196 .p
= { .min
= 5, .max
= 80 },
197 .p1
= { .min
= 1, .max
= 8},
198 .p2
= { .dot_limit
= 165000,
199 .p2_slow
= 10, .p2_fast
= 5 },
200 .find_pll
= intel_g4x_find_best_PLL
,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
204 .dot
= { .min
= 20000, .max
= 115000 },
205 .vco
= { .min
= 1750000, .max
= 3500000 },
206 .n
= { .min
= 1, .max
= 3 },
207 .m
= { .min
= 104, .max
= 138 },
208 .m1
= { .min
= 17, .max
= 23 },
209 .m2
= { .min
= 5, .max
= 11 },
210 .p
= { .min
= 28, .max
= 112 },
211 .p1
= { .min
= 2, .max
= 8 },
212 .p2
= { .dot_limit
= 0,
213 .p2_slow
= 14, .p2_fast
= 14
215 .find_pll
= intel_g4x_find_best_PLL
,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
219 .dot
= { .min
= 80000, .max
= 224000 },
220 .vco
= { .min
= 1750000, .max
= 3500000 },
221 .n
= { .min
= 1, .max
= 3 },
222 .m
= { .min
= 104, .max
= 138 },
223 .m1
= { .min
= 17, .max
= 23 },
224 .m2
= { .min
= 5, .max
= 11 },
225 .p
= { .min
= 14, .max
= 42 },
226 .p1
= { .min
= 2, .max
= 6 },
227 .p2
= { .dot_limit
= 0,
228 .p2_slow
= 7, .p2_fast
= 7
230 .find_pll
= intel_g4x_find_best_PLL
,
233 static const intel_limit_t intel_limits_g4x_display_port
= {
234 .dot
= { .min
= 161670, .max
= 227000 },
235 .vco
= { .min
= 1750000, .max
= 3500000},
236 .n
= { .min
= 1, .max
= 2 },
237 .m
= { .min
= 97, .max
= 108 },
238 .m1
= { .min
= 0x10, .max
= 0x12 },
239 .m2
= { .min
= 0x05, .max
= 0x06 },
240 .p
= { .min
= 10, .max
= 20 },
241 .p1
= { .min
= 1, .max
= 2},
242 .p2
= { .dot_limit
= 0,
243 .p2_slow
= 10, .p2_fast
= 10 },
244 .find_pll
= intel_find_pll_g4x_dp
,
247 static const intel_limit_t intel_limits_pineview_sdvo
= {
248 .dot
= { .min
= 20000, .max
= 400000},
249 .vco
= { .min
= 1700000, .max
= 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n
= { .min
= 3, .max
= 6 },
252 .m
= { .min
= 2, .max
= 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1
= { .min
= 0, .max
= 0 },
255 .m2
= { .min
= 0, .max
= 254 },
256 .p
= { .min
= 5, .max
= 80 },
257 .p1
= { .min
= 1, .max
= 8 },
258 .p2
= { .dot_limit
= 200000,
259 .p2_slow
= 10, .p2_fast
= 5 },
260 .find_pll
= intel_find_best_PLL
,
263 static const intel_limit_t intel_limits_pineview_lvds
= {
264 .dot
= { .min
= 20000, .max
= 400000 },
265 .vco
= { .min
= 1700000, .max
= 3500000 },
266 .n
= { .min
= 3, .max
= 6 },
267 .m
= { .min
= 2, .max
= 256 },
268 .m1
= { .min
= 0, .max
= 0 },
269 .m2
= { .min
= 0, .max
= 254 },
270 .p
= { .min
= 7, .max
= 112 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 112000,
273 .p2_slow
= 14, .p2_fast
= 14 },
274 .find_pll
= intel_find_best_PLL
,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac
= {
283 .dot
= { .min
= 25000, .max
= 350000 },
284 .vco
= { .min
= 1760000, .max
= 3510000 },
285 .n
= { .min
= 1, .max
= 5 },
286 .m
= { .min
= 79, .max
= 127 },
287 .m1
= { .min
= 12, .max
= 22 },
288 .m2
= { .min
= 5, .max
= 9 },
289 .p
= { .min
= 5, .max
= 80 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 225000,
292 .p2_slow
= 10, .p2_fast
= 5 },
293 .find_pll
= intel_g4x_find_best_PLL
,
296 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
297 .dot
= { .min
= 25000, .max
= 350000 },
298 .vco
= { .min
= 1760000, .max
= 3510000 },
299 .n
= { .min
= 1, .max
= 3 },
300 .m
= { .min
= 79, .max
= 118 },
301 .m1
= { .min
= 12, .max
= 22 },
302 .m2
= { .min
= 5, .max
= 9 },
303 .p
= { .min
= 28, .max
= 112 },
304 .p1
= { .min
= 2, .max
= 8 },
305 .p2
= { .dot_limit
= 225000,
306 .p2_slow
= 14, .p2_fast
= 14 },
307 .find_pll
= intel_g4x_find_best_PLL
,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
311 .dot
= { .min
= 25000, .max
= 350000 },
312 .vco
= { .min
= 1760000, .max
= 3510000 },
313 .n
= { .min
= 1, .max
= 3 },
314 .m
= { .min
= 79, .max
= 127 },
315 .m1
= { .min
= 12, .max
= 22 },
316 .m2
= { .min
= 5, .max
= 9 },
317 .p
= { .min
= 14, .max
= 56 },
318 .p1
= { .min
= 2, .max
= 8 },
319 .p2
= { .dot_limit
= 225000,
320 .p2_slow
= 7, .p2_fast
= 7 },
321 .find_pll
= intel_g4x_find_best_PLL
,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
326 .dot
= { .min
= 25000, .max
= 350000 },
327 .vco
= { .min
= 1760000, .max
= 3510000 },
328 .n
= { .min
= 1, .max
= 2 },
329 .m
= { .min
= 79, .max
= 126 },
330 .m1
= { .min
= 12, .max
= 22 },
331 .m2
= { .min
= 5, .max
= 9 },
332 .p
= { .min
= 28, .max
= 112 },
333 .p1
= { .min
= 2, .max
= 8 },
334 .p2
= { .dot_limit
= 225000,
335 .p2_slow
= 14, .p2_fast
= 14 },
336 .find_pll
= intel_g4x_find_best_PLL
,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
340 .dot
= { .min
= 25000, .max
= 350000 },
341 .vco
= { .min
= 1760000, .max
= 3510000 },
342 .n
= { .min
= 1, .max
= 3 },
343 .m
= { .min
= 79, .max
= 126 },
344 .m1
= { .min
= 12, .max
= 22 },
345 .m2
= { .min
= 5, .max
= 9 },
346 .p
= { .min
= 14, .max
= 42 },
347 .p1
= { .min
= 2, .max
= 6 },
348 .p2
= { .dot_limit
= 225000,
349 .p2_slow
= 7, .p2_fast
= 7 },
350 .find_pll
= intel_g4x_find_best_PLL
,
353 static const intel_limit_t intel_limits_ironlake_display_port
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000},
356 .n
= { .min
= 1, .max
= 2 },
357 .m
= { .min
= 81, .max
= 90 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 10, .max
= 20 },
361 .p1
= { .min
= 1, .max
= 2},
362 .p2
= { .dot_limit
= 0,
363 .p2_slow
= 10, .p2_fast
= 10 },
364 .find_pll
= intel_find_pll_ironlake_dp
,
367 static const intel_limit_t intel_limits_vlv_dac
= {
368 .dot
= { .min
= 25000, .max
= 270000 },
369 .vco
= { .min
= 4000000, .max
= 6000000 },
370 .n
= { .min
= 1, .max
= 7 },
371 .m
= { .min
= 22, .max
= 450 }, /* guess */
372 .m1
= { .min
= 2, .max
= 3 },
373 .m2
= { .min
= 11, .max
= 156 },
374 .p
= { .min
= 10, .max
= 30 },
375 .p1
= { .min
= 2, .max
= 3 },
376 .p2
= { .dot_limit
= 270000,
377 .p2_slow
= 2, .p2_fast
= 20 },
378 .find_pll
= intel_vlv_find_best_pll
,
381 static const intel_limit_t intel_limits_vlv_hdmi
= {
382 .dot
= { .min
= 20000, .max
= 165000 },
383 .vco
= { .min
= 5994000, .max
= 4000000 },
384 .n
= { .min
= 1, .max
= 7 },
385 .m
= { .min
= 60, .max
= 300 }, /* guess */
386 .m1
= { .min
= 2, .max
= 3 },
387 .m2
= { .min
= 11, .max
= 156 },
388 .p
= { .min
= 10, .max
= 30 },
389 .p1
= { .min
= 2, .max
= 3 },
390 .p2
= { .dot_limit
= 270000,
391 .p2_slow
= 2, .p2_fast
= 20 },
392 .find_pll
= intel_vlv_find_best_pll
,
395 static const intel_limit_t intel_limits_vlv_dp
= {
396 .dot
= { .min
= 162000, .max
= 270000 },
397 .vco
= { .min
= 5994000, .max
= 4000000 },
398 .n
= { .min
= 1, .max
= 7 },
399 .m
= { .min
= 60, .max
= 300 }, /* guess */
400 .m1
= { .min
= 2, .max
= 3 },
401 .m2
= { .min
= 11, .max
= 156 },
402 .p
= { .min
= 10, .max
= 30 },
403 .p1
= { .min
= 2, .max
= 3 },
404 .p2
= { .dot_limit
= 270000,
405 .p2_slow
= 2, .p2_fast
= 20 },
406 .find_pll
= intel_vlv_find_best_pll
,
409 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
414 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG
, reg
);
421 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val
= I915_READ(DPIO_DATA
);
430 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
434 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
439 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA
, val
);
446 I915_WRITE(DPIO_REG
, reg
);
447 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
456 static void vlv_init_dpio(struct drm_device
*dev
)
458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL
, 0);
462 POSTING_READ(DPIO_CTL
);
463 I915_WRITE(DPIO_CTL
, 1);
464 POSTING_READ(DPIO_CTL
);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
473 static const struct dmi_system_id intel_dual_link_lvds
[] = {
475 .callback
= intel_dual_link_lvds_callback
,
476 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode
> 0)
492 return i915_lvds_channel_mode
== 2;
494 if (dmi_check_system(intel_dual_link_lvds
))
497 if (dev_priv
->lvds_val
)
498 val
= dev_priv
->lvds_val
;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val
= I915_READ(reg
);
506 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
507 val
= dev_priv
->bios_lvds_val
;
508 dev_priv
->lvds_val
= val
;
510 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
513 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
516 struct drm_device
*dev
= crtc
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 const intel_limit_t
*limit
;
520 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
521 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
522 /* LVDS dual channel */
523 if (refclk
== 100000)
524 limit
= &intel_limits_ironlake_dual_lvds_100m
;
526 limit
= &intel_limits_ironlake_dual_lvds
;
528 if (refclk
== 100000)
529 limit
= &intel_limits_ironlake_single_lvds_100m
;
531 limit
= &intel_limits_ironlake_single_lvds
;
533 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
535 limit
= &intel_limits_ironlake_display_port
;
537 limit
= &intel_limits_ironlake_dac
;
542 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
544 struct drm_device
*dev
= crtc
->dev
;
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 const intel_limit_t
*limit
;
548 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
549 if (is_dual_link_lvds(dev_priv
, LVDS
))
550 /* LVDS with dual channel */
551 limit
= &intel_limits_g4x_dual_channel_lvds
;
553 /* LVDS with dual channel */
554 limit
= &intel_limits_g4x_single_channel_lvds
;
555 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
556 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
557 limit
= &intel_limits_g4x_hdmi
;
558 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
559 limit
= &intel_limits_g4x_sdvo
;
560 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
561 limit
= &intel_limits_g4x_display_port
;
562 } else /* The option is for other outputs */
563 limit
= &intel_limits_i9xx_sdvo
;
568 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
570 struct drm_device
*dev
= crtc
->dev
;
571 const intel_limit_t
*limit
;
573 if (HAS_PCH_SPLIT(dev
))
574 limit
= intel_ironlake_limit(crtc
, refclk
);
575 else if (IS_G4X(dev
)) {
576 limit
= intel_g4x_limit(crtc
);
577 } else if (IS_PINEVIEW(dev
)) {
578 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
579 limit
= &intel_limits_pineview_lvds
;
581 limit
= &intel_limits_pineview_sdvo
;
582 } else if (IS_VALLEYVIEW(dev
)) {
583 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
584 limit
= &intel_limits_vlv_dac
;
585 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
586 limit
= &intel_limits_vlv_hdmi
;
588 limit
= &intel_limits_vlv_dp
;
589 } else if (!IS_GEN2(dev
)) {
590 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
591 limit
= &intel_limits_i9xx_lvds
;
593 limit
= &intel_limits_i9xx_sdvo
;
595 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
596 limit
= &intel_limits_i8xx_lvds
;
598 limit
= &intel_limits_i8xx_dvo
;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
606 clock
->m
= clock
->m2
+ 2;
607 clock
->p
= clock
->p1
* clock
->p2
;
608 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
609 clock
->dot
= clock
->vco
/ clock
->p
;
612 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
614 if (IS_PINEVIEW(dev
)) {
615 pineview_clock(refclk
, clock
);
618 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
619 clock
->p
= clock
->p1
* clock
->p2
;
620 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
621 clock
->dot
= clock
->vco
/ clock
->p
;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
629 struct drm_device
*dev
= crtc
->dev
;
630 struct intel_encoder
*encoder
;
632 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
633 if (encoder
->type
== type
)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device
*dev
,
646 const intel_limit_t
*limit
,
647 const intel_clock_t
*clock
)
649 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
652 INTELPllInvalid("p out of range\n");
653 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
660 INTELPllInvalid("m out of range\n");
661 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
662 INTELPllInvalid("n out of range\n");
663 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
676 int target
, int refclk
, intel_clock_t
*match_clock
,
677 intel_clock_t
*best_clock
)
680 struct drm_device
*dev
= crtc
->dev
;
681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
685 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
686 (I915_READ(LVDS
)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv
, LVDS
))
694 clock
.p2
= limit
->p2
.p2_fast
;
696 clock
.p2
= limit
->p2
.p2_slow
;
698 if (target
< limit
->p2
.dot_limit
)
699 clock
.p2
= limit
->p2
.p2_slow
;
701 clock
.p2
= limit
->p2
.p2_fast
;
704 memset(best_clock
, 0, sizeof(*best_clock
));
706 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
708 for (clock
.m2
= limit
->m2
.min
;
709 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
710 /* m1 is always 0 in Pineview */
711 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
713 for (clock
.n
= limit
->n
.min
;
714 clock
.n
<= limit
->n
.max
; clock
.n
++) {
715 for (clock
.p1
= limit
->p1
.min
;
716 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
719 intel_clock(dev
, refclk
, &clock
);
720 if (!intel_PLL_is_valid(dev
, limit
,
724 clock
.p
!= match_clock
->p
)
727 this_err
= abs(clock
.dot
- target
);
728 if (this_err
< err
) {
737 return (err
!= target
);
741 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
742 int target
, int refclk
, intel_clock_t
*match_clock
,
743 intel_clock_t
*best_clock
)
745 struct drm_device
*dev
= crtc
->dev
;
746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 /* approximately equals target * 0.00585 */
751 int err_most
= (target
>> 8) + (target
>> 9);
754 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
757 if (HAS_PCH_SPLIT(dev
))
761 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
763 clock
.p2
= limit
->p2
.p2_fast
;
765 clock
.p2
= limit
->p2
.p2_slow
;
767 if (target
< limit
->p2
.dot_limit
)
768 clock
.p2
= limit
->p2
.p2_slow
;
770 clock
.p2
= limit
->p2
.p2_fast
;
773 memset(best_clock
, 0, sizeof(*best_clock
));
774 max_n
= limit
->n
.max
;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock
.m1
= limit
->m1
.max
;
779 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
780 for (clock
.m2
= limit
->m2
.max
;
781 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
782 for (clock
.p1
= limit
->p1
.max
;
783 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
786 intel_clock(dev
, refclk
, &clock
);
787 if (!intel_PLL_is_valid(dev
, limit
,
791 clock
.p
!= match_clock
->p
)
794 this_err
= abs(clock
.dot
- target
);
795 if (this_err
< err_most
) {
809 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
810 int target
, int refclk
, intel_clock_t
*match_clock
,
811 intel_clock_t
*best_clock
)
813 struct drm_device
*dev
= crtc
->dev
;
816 if (target
< 200000) {
829 intel_clock(dev
, refclk
, &clock
);
830 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
837 int target
, int refclk
, intel_clock_t
*match_clock
,
838 intel_clock_t
*best_clock
)
841 if (target
< 200000) {
854 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
855 clock
.p
= (clock
.p1
* clock
.p2
);
856 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
858 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
862 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
863 int target
, int refclk
, intel_clock_t
*match_clock
,
864 intel_clock_t
*best_clock
)
866 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
868 u32 updrate
, minupdate
, fracbits
, p
;
869 unsigned long bestppm
, ppm
, absppm
;
873 dotclk
= target
* 1000;
876 fastclk
= dotclk
/ (2*100);
880 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
881 bestm1
= bestm2
= bestp1
= bestp2
= 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
885 updrate
= refclk
/ n
;
886 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
887 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
893 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
894 refclk
) / (2*refclk
));
897 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
898 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
899 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
900 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
904 if (absppm
< bestppm
- 10) {
921 best_clock
->n
= bestn
;
922 best_clock
->m1
= bestm1
;
923 best_clock
->m2
= bestm2
;
924 best_clock
->p1
= bestp1
;
925 best_clock
->p2
= bestp2
;
930 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
933 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
935 frame
= I915_READ(frame_reg
);
937 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 int pipestat_reg
= PIPESTAT(pipe
);
954 if (INTEL_INFO(dev
)->gen
>= 5) {
955 ironlake_wait_for_vblank(dev
, pipe
);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg
,
973 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg
) &
977 PIPE_VBLANK_INTERRUPT_STATUS
,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1003 if (INTEL_INFO(dev
)->gen
>= 4) {
1004 int reg
= PIPECONF(pipe
);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1009 WARN(1, "pipe_off wait timed out\n");
1011 u32 last_line
, line_mask
;
1012 int reg
= PIPEDSL(pipe
);
1013 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1016 line_mask
= DSL_LINEMASK_GEN2
;
1018 line_mask
= DSL_LINEMASK_GEN3
;
1020 /* Wait for the display line to settle */
1022 last_line
= I915_READ(reg
) & line_mask
;
1024 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1025 time_after(timeout
, jiffies
));
1026 if (time_after(jiffies
, timeout
))
1027 WARN(1, "pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled
)
1033 return enabled
? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private
*dev_priv
,
1038 enum pipe pipe
, bool state
)
1045 val
= I915_READ(reg
);
1046 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1047 WARN(cur_state
!= state
,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state
), state_string(cur_state
));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1056 struct intel_pch_pll
*pll
,
1057 struct intel_crtc
*crtc
,
1063 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1072 val
= I915_READ(pll
->pll_reg
);
1073 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1074 WARN(cur_state
!= state
,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1082 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1083 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1084 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state
, crtc
->pipe
, pch_dpll
)) {
1087 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1088 WARN(cur_state
!= state
,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll
->pll_reg
== _PCH_DPLL_B
,
1091 state_string(state
),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1101 enum pipe pipe
, bool state
)
1107 if (IS_HASWELL(dev_priv
->dev
)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg
= DDI_FUNC_CTL(pipe
);
1110 val
= I915_READ(reg
);
1111 cur_state
= !!(val
& PIPE_DDI_FUNC_ENABLE
);
1113 reg
= FDI_TX_CTL(pipe
);
1114 val
= I915_READ(reg
);
1115 cur_state
= !!(val
& FDI_TX_ENABLE
);
1117 WARN(cur_state
!= state
,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state
), state_string(cur_state
));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1125 enum pipe pipe
, bool state
)
1131 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg
= FDI_RX_CTL(pipe
);
1136 val
= I915_READ(reg
);
1137 cur_state
= !!(val
& FDI_RX_ENABLE
);
1139 WARN(cur_state
!= state
,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state
), state_string(cur_state
));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv
->info
->gen
== 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv
->dev
))
1160 reg
= FDI_TX_CTL(pipe
);
1161 val
= I915_READ(reg
);
1162 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1171 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg
= FDI_RX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1183 int pp_reg
, lvds_reg
;
1185 enum pipe panel_pipe
= PIPE_A
;
1188 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1189 pp_reg
= PCH_PP_CONTROL
;
1190 lvds_reg
= PCH_LVDS
;
1192 pp_reg
= PP_CONTROL
;
1196 val
= I915_READ(pp_reg
);
1197 if (!(val
& PANEL_POWER_ON
) ||
1198 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1201 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1202 panel_pipe
= PIPE_B
;
1204 WARN(panel_pipe
== pipe
&& locked
,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private
*dev_priv
,
1210 enum pipe pipe
, bool state
)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1220 reg
= PIPECONF(pipe
);
1221 val
= I915_READ(reg
);
1222 cur_state
= !!(val
& PIPECONF_ENABLE
);
1223 WARN(cur_state
!= state
,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1228 static void assert_plane(struct drm_i915_private
*dev_priv
,
1229 enum plane plane
, bool state
)
1235 reg
= DSPCNTR(plane
);
1236 val
= I915_READ(reg
);
1237 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1238 WARN(cur_state
!= state
,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane
), state_string(state
), state_string(cur_state
));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1255 reg
= DSPCNTR(pipe
);
1256 val
= I915_READ(reg
);
1257 WARN((val
& DISPLAY_PLANE_ENABLE
),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i
= 0; i
< 2; i
++) {
1266 val
= I915_READ(reg
);
1267 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1268 DISPPLANE_SEL_PIPE_SHIFT
;
1269 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i
), pipe_name(pipe
));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1280 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val
= I915_READ(PCH_DREF_CONTROL
);
1286 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1287 DREF_SUPERSPREAD_SOURCE_MASK
));
1288 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1298 reg
= TRANSCONF(pipe
);
1299 val
= I915_READ(reg
);
1300 enabled
= !!(val
& TRANS_ENABLE
);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1307 enum pipe pipe
, u32 port_sel
, u32 val
)
1309 if ((val
& DP_PORT_EN
) == 0)
1312 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1313 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1314 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1315 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1318 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1325 enum pipe pipe
, u32 val
)
1327 if ((val
& PORT_ENABLE
) == 0)
1330 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1331 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1334 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1340 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1341 enum pipe pipe
, u32 val
)
1343 if ((val
& LVDS_PORT_EN
) == 0)
1346 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1347 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1350 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1356 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1357 enum pipe pipe
, u32 val
)
1359 if ((val
& ADPA_DAC_ENABLE
) == 0)
1361 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1362 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1365 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1371 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1372 enum pipe pipe
, int reg
, u32 port_sel
)
1374 u32 val
= I915_READ(reg
);
1375 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg
, pipe_name(pipe
));
1379 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_PIPE_B_SELECT
),
1380 "IBX PCH dp port still using transcoder B\n");
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1384 enum pipe pipe
, int reg
)
1386 u32 val
= I915_READ(reg
);
1387 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg
, pipe_name(pipe
));
1391 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_PIPE_B_SELECT
),
1392 "IBX PCH hdmi port still using transcoder B\n");
1395 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1401 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1402 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1403 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1406 val
= I915_READ(reg
);
1407 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1412 val
= I915_READ(reg
);
1413 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1418 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1419 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1431 * Note! This is for pre-ILK only.
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1435 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1445 assert_panel_unlocked(dev_priv
, pipe
);
1448 val
= I915_READ(reg
);
1449 val
|= DPLL_VCO_ENABLE
;
1451 /* We do this three times for luck */
1452 I915_WRITE(reg
, val
);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg
, val
);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg
, val
);
1460 udelay(150); /* wait for warmup */
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1470 * Note! This is for pre-ILK only.
1472 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv
, pipe
);
1485 val
= I915_READ(reg
);
1486 val
&= ~DPLL_VCO_ENABLE
;
1487 I915_WRITE(reg
, val
);
1493 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1495 unsigned long flags
;
1497 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1498 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1504 I915_WRITE(SBI_ADDR
,
1506 I915_WRITE(SBI_DATA
,
1508 I915_WRITE(SBI_CTL_STAT
,
1512 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1519 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1523 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1525 unsigned long flags
;
1528 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1529 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1535 I915_WRITE(SBI_ADDR
,
1537 I915_WRITE(SBI_CTL_STAT
,
1541 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1547 value
= I915_READ(SBI_DATA
);
1550 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1562 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1564 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1565 struct intel_pch_pll
*pll
;
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv
->info
->gen
< 5);
1571 pll
= intel_crtc
->pch_pll
;
1575 if (WARN_ON(pll
->refcount
== 0))
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll
->pll_reg
, pll
->active
, pll
->on
,
1580 intel_crtc
->base
.base
.id
);
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv
);
1585 if (pll
->active
++ && pll
->on
) {
1586 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1593 val
= I915_READ(reg
);
1594 val
|= DPLL_VCO_ENABLE
;
1595 I915_WRITE(reg
, val
);
1602 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1604 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1605 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv
->info
->gen
< 5);
1614 if (WARN_ON(pll
->refcount
== 0))
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll
->pll_reg
, pll
->active
, pll
->on
,
1619 intel_crtc
->base
.base
.id
);
1621 if (WARN_ON(pll
->active
== 0)) {
1622 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1626 if (--pll
->active
) {
1627 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1637 val
= I915_READ(reg
);
1638 val
&= ~DPLL_VCO_ENABLE
;
1639 I915_WRITE(reg
, val
);
1646 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1650 u32 val
, pipeconf_val
;
1651 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv
->info
->gen
< 5);
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv
,
1658 to_intel_crtc(crtc
)->pch_pll
,
1659 to_intel_crtc(crtc
));
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv
, pipe
);
1663 assert_fdi_rx_enabled(dev_priv
, pipe
);
1665 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 reg
= TRANSCONF(pipe
);
1670 val
= I915_READ(reg
);
1671 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1673 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1678 val
&= ~PIPE_BPC_MASK
;
1679 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1682 val
&= ~TRANS_INTERLACE_MASK
;
1683 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1684 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1685 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1686 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1688 val
|= TRANS_INTERLACED
;
1690 val
|= TRANS_PROGRESSIVE
;
1692 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1693 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1697 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv
, pipe
);
1705 assert_fdi_rx_disabled(dev_priv
, pipe
);
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv
, pipe
);
1710 reg
= TRANSCONF(pipe
);
1711 val
= I915_READ(reg
);
1712 val
&= ~TRANS_ENABLE
;
1713 I915_WRITE(reg
, val
);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1728 * @pipe should be %PIPE_A or %PIPE_B.
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1745 assert_pll_enabled(dev_priv
, pipe
);
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1750 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1752 /* FIXME: assert CPU port conditions for SNB+ */
1755 reg
= PIPECONF(pipe
);
1756 val
= I915_READ(reg
);
1757 if (val
& PIPECONF_ENABLE
)
1760 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1761 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 * @pipe should be %PIPE_A or %PIPE_B.
1774 * Will wait until the pipe has shut down before returning.
1776 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1786 assert_planes_disabled(dev_priv
, pipe
);
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1792 reg
= PIPECONF(pipe
);
1793 val
= I915_READ(reg
);
1794 if ((val
& PIPECONF_ENABLE
) == 0)
1797 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1798 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1805 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1808 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1809 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1820 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1821 enum plane plane
, enum pipe pipe
)
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv
, pipe
);
1829 reg
= DSPCNTR(plane
);
1830 val
= I915_READ(reg
);
1831 if (val
& DISPLAY_PLANE_ENABLE
)
1834 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1835 intel_flush_display_plane(dev_priv
, plane
);
1836 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1845 * Disable @plane; should be an independent operation.
1847 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1848 enum plane plane
, enum pipe pipe
)
1853 reg
= DSPCNTR(plane
);
1854 val
= I915_READ(reg
);
1855 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1858 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1859 intel_flush_display_plane(dev_priv
, plane
);
1860 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1864 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1865 struct drm_i915_gem_object
*obj
,
1866 struct intel_ring_buffer
*pipelined
)
1868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1872 switch (obj
->tiling_mode
) {
1873 case I915_TILING_NONE
:
1874 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1875 alignment
= 128 * 1024;
1876 else if (INTEL_INFO(dev
)->gen
>= 4)
1877 alignment
= 4 * 1024;
1879 alignment
= 64 * 1024;
1882 /* pin() will align the object as required by fence */
1886 /* FIXME: Is this true? */
1887 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1893 dev_priv
->mm
.interruptible
= false;
1894 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1896 goto err_interruptible
;
1898 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1899 * fence, whereas 965+ only requires a fence if using
1900 * framebuffer compression. For simplicity, we always install
1901 * a fence as the cost is not that onerous.
1903 ret
= i915_gem_object_get_fence(obj
);
1907 i915_gem_object_pin_fence(obj
);
1909 dev_priv
->mm
.interruptible
= true;
1913 i915_gem_object_unpin(obj
);
1915 dev_priv
->mm
.interruptible
= true;
1919 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1921 i915_gem_object_unpin_fence(obj
);
1922 i915_gem_object_unpin(obj
);
1925 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1926 * is assumed to be a power-of-two. */
1927 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x
, int *y
,
1931 int tile_rows
, tiles
;
1935 tiles
= *x
/ (512/bpp
);
1938 return tile_rows
* pitch
* 8 + tiles
* 4096;
1941 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1944 struct drm_device
*dev
= crtc
->dev
;
1945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1947 struct intel_framebuffer
*intel_fb
;
1948 struct drm_i915_gem_object
*obj
;
1949 int plane
= intel_crtc
->plane
;
1950 unsigned long linear_offset
;
1959 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1963 intel_fb
= to_intel_framebuffer(fb
);
1964 obj
= intel_fb
->obj
;
1966 reg
= DSPCNTR(plane
);
1967 dspcntr
= I915_READ(reg
);
1968 /* Mask out pixel format bits in case we change it */
1969 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1970 switch (fb
->bits_per_pixel
) {
1972 dspcntr
|= DISPPLANE_8BPP
;
1975 if (fb
->depth
== 15)
1976 dspcntr
|= DISPPLANE_15_16BPP
;
1978 dspcntr
|= DISPPLANE_16BPP
;
1982 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1985 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
1988 if (INTEL_INFO(dev
)->gen
>= 4) {
1989 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1990 dspcntr
|= DISPPLANE_TILED
;
1992 dspcntr
&= ~DISPPLANE_TILED
;
1995 I915_WRITE(reg
, dspcntr
);
1997 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1999 if (INTEL_INFO(dev
)->gen
>= 4) {
2000 intel_crtc
->dspaddr_offset
=
2001 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2002 fb
->bits_per_pixel
/ 8,
2004 linear_offset
-= intel_crtc
->dspaddr_offset
;
2006 intel_crtc
->dspaddr_offset
= linear_offset
;
2009 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2010 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2011 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2012 if (INTEL_INFO(dev
)->gen
>= 4) {
2013 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2014 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2015 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2016 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2018 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2024 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2025 struct drm_framebuffer
*fb
, int x
, int y
)
2027 struct drm_device
*dev
= crtc
->dev
;
2028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2029 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2030 struct intel_framebuffer
*intel_fb
;
2031 struct drm_i915_gem_object
*obj
;
2032 int plane
= intel_crtc
->plane
;
2033 unsigned long linear_offset
;
2043 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2047 intel_fb
= to_intel_framebuffer(fb
);
2048 obj
= intel_fb
->obj
;
2050 reg
= DSPCNTR(plane
);
2051 dspcntr
= I915_READ(reg
);
2052 /* Mask out pixel format bits in case we change it */
2053 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2054 switch (fb
->bits_per_pixel
) {
2056 dspcntr
|= DISPPLANE_8BPP
;
2059 if (fb
->depth
!= 16)
2062 dspcntr
|= DISPPLANE_16BPP
;
2066 if (fb
->depth
== 24)
2067 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2068 else if (fb
->depth
== 30)
2069 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2074 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2078 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2079 dspcntr
|= DISPPLANE_TILED
;
2081 dspcntr
&= ~DISPPLANE_TILED
;
2084 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2086 I915_WRITE(reg
, dspcntr
);
2088 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2089 intel_crtc
->dspaddr_offset
=
2090 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2091 fb
->bits_per_pixel
/ 8,
2093 linear_offset
-= intel_crtc
->dspaddr_offset
;
2095 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2096 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2097 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2098 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2099 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2100 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2101 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2107 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2109 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2110 int x
, int y
, enum mode_set_atomic state
)
2112 struct drm_device
*dev
= crtc
->dev
;
2113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2115 if (dev_priv
->display
.disable_fbc
)
2116 dev_priv
->display
.disable_fbc(dev
);
2117 intel_increase_pllclock(crtc
);
2119 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2123 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2125 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2126 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2127 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2130 wait_event(dev_priv
->pending_flip_queue
,
2131 atomic_read(&dev_priv
->mm
.wedged
) ||
2132 atomic_read(&obj
->pending_flip
) == 0);
2134 /* Big Hammer, we also need to ensure that any pending
2135 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2136 * current scanout is retired before unpinning the old
2139 * This should only fail upon a hung GPU, in which case we
2140 * can safely continue.
2142 dev_priv
->mm
.interruptible
= false;
2143 ret
= i915_gem_object_finish_gpu(obj
);
2144 dev_priv
->mm
.interruptible
= was_interruptible
;
2150 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2151 struct drm_framebuffer
*fb
)
2153 struct drm_device
*dev
= crtc
->dev
;
2154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2155 struct drm_i915_master_private
*master_priv
;
2156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2157 struct drm_framebuffer
*old_fb
;
2162 DRM_ERROR("No FB bound\n");
2166 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2167 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2169 dev_priv
->num_pipe
);
2173 mutex_lock(&dev
->struct_mutex
);
2174 ret
= intel_pin_and_fence_fb_obj(dev
,
2175 to_intel_framebuffer(fb
)->obj
,
2178 mutex_unlock(&dev
->struct_mutex
);
2179 DRM_ERROR("pin & fence failed\n");
2184 intel_finish_fb(crtc
->fb
);
2186 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2188 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2189 mutex_unlock(&dev
->struct_mutex
);
2190 DRM_ERROR("failed to update base address\n");
2200 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2201 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2204 intel_update_fbc(dev
);
2205 mutex_unlock(&dev
->struct_mutex
);
2207 if (!dev
->primary
->master
)
2210 master_priv
= dev
->primary
->master
->driver_priv
;
2211 if (!master_priv
->sarea_priv
)
2214 if (intel_crtc
->pipe
) {
2215 master_priv
->sarea_priv
->pipeB_x
= x
;
2216 master_priv
->sarea_priv
->pipeB_y
= y
;
2218 master_priv
->sarea_priv
->pipeA_x
= x
;
2219 master_priv
->sarea_priv
->pipeA_y
= y
;
2225 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2227 struct drm_device
*dev
= crtc
->dev
;
2228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2231 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2232 dpa_ctl
= I915_READ(DP_A
);
2233 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2235 if (clock
< 200000) {
2237 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2238 /* workaround for 160Mhz:
2239 1) program 0x4600c bits 15:0 = 0x8124
2240 2) program 0x46010 bit 0 = 1
2241 3) program 0x46034 bit 24 = 1
2242 4) program 0x64000 bit 14 = 1
2244 temp
= I915_READ(0x4600c);
2246 I915_WRITE(0x4600c, temp
| 0x8124);
2248 temp
= I915_READ(0x46010);
2249 I915_WRITE(0x46010, temp
| 1);
2251 temp
= I915_READ(0x46034);
2252 I915_WRITE(0x46034, temp
| (1 << 24));
2254 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2256 I915_WRITE(DP_A
, dpa_ctl
);
2262 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2264 struct drm_device
*dev
= crtc
->dev
;
2265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2266 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2267 int pipe
= intel_crtc
->pipe
;
2270 /* enable normal train */
2271 reg
= FDI_TX_CTL(pipe
);
2272 temp
= I915_READ(reg
);
2273 if (IS_IVYBRIDGE(dev
)) {
2274 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2275 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2277 temp
&= ~FDI_LINK_TRAIN_NONE
;
2278 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2280 I915_WRITE(reg
, temp
);
2282 reg
= FDI_RX_CTL(pipe
);
2283 temp
= I915_READ(reg
);
2284 if (HAS_PCH_CPT(dev
)) {
2285 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2286 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2288 temp
&= ~FDI_LINK_TRAIN_NONE
;
2289 temp
|= FDI_LINK_TRAIN_NONE
;
2291 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2293 /* wait one idle pattern time */
2297 /* IVB wants error correction enabled */
2298 if (IS_IVYBRIDGE(dev
))
2299 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2300 FDI_FE_ERRC_ENABLE
);
2303 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2308 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2309 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2310 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2311 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2312 POSTING_READ(SOUTH_CHICKEN1
);
2315 /* The FDI link training functions for ILK/Ibexpeak. */
2316 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2318 struct drm_device
*dev
= crtc
->dev
;
2319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2320 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2321 int pipe
= intel_crtc
->pipe
;
2322 int plane
= intel_crtc
->plane
;
2323 u32 reg
, temp
, tries
;
2325 /* FDI needs bits from pipe & plane first */
2326 assert_pipe_enabled(dev_priv
, pipe
);
2327 assert_plane_enabled(dev_priv
, plane
);
2329 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2331 reg
= FDI_RX_IMR(pipe
);
2332 temp
= I915_READ(reg
);
2333 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2334 temp
&= ~FDI_RX_BIT_LOCK
;
2335 I915_WRITE(reg
, temp
);
2339 /* enable CPU FDI TX and PCH FDI RX */
2340 reg
= FDI_TX_CTL(pipe
);
2341 temp
= I915_READ(reg
);
2343 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2344 temp
&= ~FDI_LINK_TRAIN_NONE
;
2345 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2346 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2348 reg
= FDI_RX_CTL(pipe
);
2349 temp
= I915_READ(reg
);
2350 temp
&= ~FDI_LINK_TRAIN_NONE
;
2351 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2352 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2357 /* Ironlake workaround, enable clock pointer after FDI enable*/
2358 if (HAS_PCH_IBX(dev
)) {
2359 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2360 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2361 FDI_RX_PHASE_SYNC_POINTER_EN
);
2364 reg
= FDI_RX_IIR(pipe
);
2365 for (tries
= 0; tries
< 5; tries
++) {
2366 temp
= I915_READ(reg
);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2369 if ((temp
& FDI_RX_BIT_LOCK
)) {
2370 DRM_DEBUG_KMS("FDI train 1 done.\n");
2371 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2376 DRM_ERROR("FDI train 1 fail!\n");
2379 reg
= FDI_TX_CTL(pipe
);
2380 temp
= I915_READ(reg
);
2381 temp
&= ~FDI_LINK_TRAIN_NONE
;
2382 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2383 I915_WRITE(reg
, temp
);
2385 reg
= FDI_RX_CTL(pipe
);
2386 temp
= I915_READ(reg
);
2387 temp
&= ~FDI_LINK_TRAIN_NONE
;
2388 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2389 I915_WRITE(reg
, temp
);
2394 reg
= FDI_RX_IIR(pipe
);
2395 for (tries
= 0; tries
< 5; tries
++) {
2396 temp
= I915_READ(reg
);
2397 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2399 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2400 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2401 DRM_DEBUG_KMS("FDI train 2 done.\n");
2406 DRM_ERROR("FDI train 2 fail!\n");
2408 DRM_DEBUG_KMS("FDI train done\n");
2412 static const int snb_b_fdi_train_param
[] = {
2413 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2414 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2415 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2416 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2419 /* The FDI link training functions for SNB/Cougarpoint. */
2420 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2422 struct drm_device
*dev
= crtc
->dev
;
2423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2424 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2425 int pipe
= intel_crtc
->pipe
;
2426 u32 reg
, temp
, i
, retry
;
2428 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430 reg
= FDI_RX_IMR(pipe
);
2431 temp
= I915_READ(reg
);
2432 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2433 temp
&= ~FDI_RX_BIT_LOCK
;
2434 I915_WRITE(reg
, temp
);
2439 /* enable CPU FDI TX and PCH FDI RX */
2440 reg
= FDI_TX_CTL(pipe
);
2441 temp
= I915_READ(reg
);
2443 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2444 temp
&= ~FDI_LINK_TRAIN_NONE
;
2445 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2446 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2448 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2449 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2451 reg
= FDI_RX_CTL(pipe
);
2452 temp
= I915_READ(reg
);
2453 if (HAS_PCH_CPT(dev
)) {
2454 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2455 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2457 temp
&= ~FDI_LINK_TRAIN_NONE
;
2458 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2460 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2465 if (HAS_PCH_CPT(dev
))
2466 cpt_phase_pointer_enable(dev
, pipe
);
2468 for (i
= 0; i
< 4; i
++) {
2469 reg
= FDI_TX_CTL(pipe
);
2470 temp
= I915_READ(reg
);
2471 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2472 temp
|= snb_b_fdi_train_param
[i
];
2473 I915_WRITE(reg
, temp
);
2478 for (retry
= 0; retry
< 5; retry
++) {
2479 reg
= FDI_RX_IIR(pipe
);
2480 temp
= I915_READ(reg
);
2481 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2482 if (temp
& FDI_RX_BIT_LOCK
) {
2483 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2484 DRM_DEBUG_KMS("FDI train 1 done.\n");
2493 DRM_ERROR("FDI train 1 fail!\n");
2496 reg
= FDI_TX_CTL(pipe
);
2497 temp
= I915_READ(reg
);
2498 temp
&= ~FDI_LINK_TRAIN_NONE
;
2499 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2501 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2503 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2505 I915_WRITE(reg
, temp
);
2507 reg
= FDI_RX_CTL(pipe
);
2508 temp
= I915_READ(reg
);
2509 if (HAS_PCH_CPT(dev
)) {
2510 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2511 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2513 temp
&= ~FDI_LINK_TRAIN_NONE
;
2514 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2516 I915_WRITE(reg
, temp
);
2521 for (i
= 0; i
< 4; i
++) {
2522 reg
= FDI_TX_CTL(pipe
);
2523 temp
= I915_READ(reg
);
2524 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2525 temp
|= snb_b_fdi_train_param
[i
];
2526 I915_WRITE(reg
, temp
);
2531 for (retry
= 0; retry
< 5; retry
++) {
2532 reg
= FDI_RX_IIR(pipe
);
2533 temp
= I915_READ(reg
);
2534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2535 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2536 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2537 DRM_DEBUG_KMS("FDI train 2 done.\n");
2546 DRM_ERROR("FDI train 2 fail!\n");
2548 DRM_DEBUG_KMS("FDI train done.\n");
2551 /* Manual link training for Ivy Bridge A0 parts */
2552 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2554 struct drm_device
*dev
= crtc
->dev
;
2555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2557 int pipe
= intel_crtc
->pipe
;
2560 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562 reg
= FDI_RX_IMR(pipe
);
2563 temp
= I915_READ(reg
);
2564 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2565 temp
&= ~FDI_RX_BIT_LOCK
;
2566 I915_WRITE(reg
, temp
);
2571 /* enable CPU FDI TX and PCH FDI RX */
2572 reg
= FDI_TX_CTL(pipe
);
2573 temp
= I915_READ(reg
);
2575 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2576 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2577 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2578 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2579 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2580 temp
|= FDI_COMPOSITE_SYNC
;
2581 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2583 reg
= FDI_RX_CTL(pipe
);
2584 temp
= I915_READ(reg
);
2585 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2586 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2587 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2588 temp
|= FDI_COMPOSITE_SYNC
;
2589 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2594 if (HAS_PCH_CPT(dev
))
2595 cpt_phase_pointer_enable(dev
, pipe
);
2597 for (i
= 0; i
< 4; i
++) {
2598 reg
= FDI_TX_CTL(pipe
);
2599 temp
= I915_READ(reg
);
2600 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2601 temp
|= snb_b_fdi_train_param
[i
];
2602 I915_WRITE(reg
, temp
);
2607 reg
= FDI_RX_IIR(pipe
);
2608 temp
= I915_READ(reg
);
2609 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2611 if (temp
& FDI_RX_BIT_LOCK
||
2612 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2613 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2614 DRM_DEBUG_KMS("FDI train 1 done.\n");
2619 DRM_ERROR("FDI train 1 fail!\n");
2622 reg
= FDI_TX_CTL(pipe
);
2623 temp
= I915_READ(reg
);
2624 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2625 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2626 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2627 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2628 I915_WRITE(reg
, temp
);
2630 reg
= FDI_RX_CTL(pipe
);
2631 temp
= I915_READ(reg
);
2632 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2633 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2634 I915_WRITE(reg
, temp
);
2639 for (i
= 0; i
< 4; i
++) {
2640 reg
= FDI_TX_CTL(pipe
);
2641 temp
= I915_READ(reg
);
2642 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2643 temp
|= snb_b_fdi_train_param
[i
];
2644 I915_WRITE(reg
, temp
);
2649 reg
= FDI_RX_IIR(pipe
);
2650 temp
= I915_READ(reg
);
2651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2653 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2654 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2655 DRM_DEBUG_KMS("FDI train 2 done.\n");
2660 DRM_ERROR("FDI train 2 fail!\n");
2662 DRM_DEBUG_KMS("FDI train done.\n");
2665 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2667 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2669 int pipe
= intel_crtc
->pipe
;
2672 /* Write the TU size bits so error detection works */
2673 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2674 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2677 reg
= FDI_RX_CTL(pipe
);
2678 temp
= I915_READ(reg
);
2679 temp
&= ~((0x7 << 19) | (0x7 << 16));
2680 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2681 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2682 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2687 /* Switch from Rawclk to PCDclk */
2688 temp
= I915_READ(reg
);
2689 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2694 /* On Haswell, the PLL configuration for ports and pipes is handled
2695 * separately, as part of DDI setup */
2696 if (!IS_HASWELL(dev
)) {
2697 /* Enable CPU FDI TX PLL, always on for Ironlake */
2698 reg
= FDI_TX_CTL(pipe
);
2699 temp
= I915_READ(reg
);
2700 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2701 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2709 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2711 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 int pipe
= intel_crtc
->pipe
;
2716 /* Switch from PCDclk to Rawclk */
2717 reg
= FDI_RX_CTL(pipe
);
2718 temp
= I915_READ(reg
);
2719 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2721 /* Disable CPU FDI TX PLL */
2722 reg
= FDI_TX_CTL(pipe
);
2723 temp
= I915_READ(reg
);
2724 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2729 reg
= FDI_RX_CTL(pipe
);
2730 temp
= I915_READ(reg
);
2731 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2733 /* Wait for the clocks to turn off. */
2738 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2741 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2743 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2744 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2745 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2746 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2747 POSTING_READ(SOUTH_CHICKEN1
);
2749 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2751 struct drm_device
*dev
= crtc
->dev
;
2752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2753 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2754 int pipe
= intel_crtc
->pipe
;
2757 /* disable CPU FDI tx and PCH FDI rx */
2758 reg
= FDI_TX_CTL(pipe
);
2759 temp
= I915_READ(reg
);
2760 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2763 reg
= FDI_RX_CTL(pipe
);
2764 temp
= I915_READ(reg
);
2765 temp
&= ~(0x7 << 16);
2766 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2767 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2772 /* Ironlake workaround, disable clock pointer after downing FDI */
2773 if (HAS_PCH_IBX(dev
)) {
2774 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2775 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2776 I915_READ(FDI_RX_CHICKEN(pipe
) &
2777 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2778 } else if (HAS_PCH_CPT(dev
)) {
2779 cpt_phase_pointer_disable(dev
, pipe
);
2782 /* still set train pattern 1 */
2783 reg
= FDI_TX_CTL(pipe
);
2784 temp
= I915_READ(reg
);
2785 temp
&= ~FDI_LINK_TRAIN_NONE
;
2786 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2787 I915_WRITE(reg
, temp
);
2789 reg
= FDI_RX_CTL(pipe
);
2790 temp
= I915_READ(reg
);
2791 if (HAS_PCH_CPT(dev
)) {
2792 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2793 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2795 temp
&= ~FDI_LINK_TRAIN_NONE
;
2796 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2798 /* BPC in FDI rx is consistent with that in PIPECONF */
2799 temp
&= ~(0x07 << 16);
2800 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2801 I915_WRITE(reg
, temp
);
2807 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2809 struct drm_device
*dev
= crtc
->dev
;
2811 if (crtc
->fb
== NULL
)
2814 mutex_lock(&dev
->struct_mutex
);
2815 intel_finish_fb(crtc
->fb
);
2816 mutex_unlock(&dev
->struct_mutex
);
2819 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2821 struct drm_device
*dev
= crtc
->dev
;
2822 struct intel_encoder
*intel_encoder
;
2825 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2826 * must be driven by its own crtc; no sharing is possible.
2828 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2830 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2831 * CPU handles all others */
2832 if (IS_HASWELL(dev
)) {
2833 /* It is still unclear how this will work on PPT, so throw up a warning */
2834 WARN_ON(!HAS_PCH_LPT(dev
));
2836 if (intel_encoder
->type
== INTEL_OUTPUT_ANALOG
) {
2837 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2840 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2841 intel_encoder
->type
);
2846 switch (intel_encoder
->type
) {
2847 case INTEL_OUTPUT_EDP
:
2848 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
2857 /* Program iCLKIP clock to the desired frequency */
2858 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2860 struct drm_device
*dev
= crtc
->dev
;
2861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2862 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2865 /* It is necessary to ungate the pixclk gate prior to programming
2866 * the divisors, and gate it back when it is done.
2868 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2870 /* Disable SSCCTL */
2871 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2872 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2873 SBI_SSCCTL_DISABLE
);
2875 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2876 if (crtc
->mode
.clock
== 20000) {
2881 /* The iCLK virtual clock root frequency is in MHz,
2882 * but the crtc->mode.clock in in KHz. To get the divisors,
2883 * it is necessary to divide one by another, so we
2884 * convert the virtual clock precision to KHz here for higher
2887 u32 iclk_virtual_root_freq
= 172800 * 1000;
2888 u32 iclk_pi_range
= 64;
2889 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2891 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2892 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2893 pi_value
= desired_divisor
% iclk_pi_range
;
2896 divsel
= msb_divisor_value
- 2;
2897 phaseinc
= pi_value
;
2900 /* This should not happen with any sane values */
2901 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2902 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2904 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2906 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2913 /* Program SSCDIVINTPHASE6 */
2914 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2915 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2916 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2917 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2918 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2919 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2920 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2922 intel_sbi_write(dev_priv
,
2923 SBI_SSCDIVINTPHASE6
,
2926 /* Program SSCAUXDIV */
2927 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
2928 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2929 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2930 intel_sbi_write(dev_priv
,
2935 /* Enable modulator and associated divider */
2936 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
2937 temp
&= ~SBI_SSCCTL_DISABLE
;
2938 intel_sbi_write(dev_priv
,
2942 /* Wait for initialization time */
2945 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2949 * Enable PCH resources required for PCH ports:
2951 * - FDI training & RX/TX
2952 * - update transcoder timings
2953 * - DP transcoding bits
2956 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2958 struct drm_device
*dev
= crtc
->dev
;
2959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2960 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2961 int pipe
= intel_crtc
->pipe
;
2964 assert_transcoder_disabled(dev_priv
, pipe
);
2966 /* For PCH output, training FDI link */
2967 dev_priv
->display
.fdi_link_train(crtc
);
2969 intel_enable_pch_pll(intel_crtc
);
2971 if (HAS_PCH_LPT(dev
)) {
2972 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2973 lpt_program_iclkip(crtc
);
2974 } else if (HAS_PCH_CPT(dev
)) {
2977 temp
= I915_READ(PCH_DPLL_SEL
);
2981 temp
|= TRANSA_DPLL_ENABLE
;
2982 sel
= TRANSA_DPLLB_SEL
;
2985 temp
|= TRANSB_DPLL_ENABLE
;
2986 sel
= TRANSB_DPLLB_SEL
;
2989 temp
|= TRANSC_DPLL_ENABLE
;
2990 sel
= TRANSC_DPLLB_SEL
;
2993 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
2997 I915_WRITE(PCH_DPLL_SEL
, temp
);
3000 /* set transcoder timing, panel must allow it */
3001 assert_panel_unlocked(dev_priv
, pipe
);
3002 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3003 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3004 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3006 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3007 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3008 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3009 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3011 if (!IS_HASWELL(dev
))
3012 intel_fdi_normal_train(crtc
);
3014 /* For PCH DP, enable TRANS_DP_CTL */
3015 if (HAS_PCH_CPT(dev
) &&
3016 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3017 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3018 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3019 reg
= TRANS_DP_CTL(pipe
);
3020 temp
= I915_READ(reg
);
3021 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3022 TRANS_DP_SYNC_MASK
|
3024 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3025 TRANS_DP_ENH_FRAMING
);
3026 temp
|= bpc
<< 9; /* same format but at 11:9 */
3028 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3029 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3030 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3031 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3033 switch (intel_trans_dp_port_sel(crtc
)) {
3035 temp
|= TRANS_DP_PORT_SEL_B
;
3038 temp
|= TRANS_DP_PORT_SEL_C
;
3041 temp
|= TRANS_DP_PORT_SEL_D
;
3044 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3045 temp
|= TRANS_DP_PORT_SEL_B
;
3049 I915_WRITE(reg
, temp
);
3052 intel_enable_transcoder(dev_priv
, pipe
);
3055 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3057 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3062 if (pll
->refcount
== 0) {
3063 WARN(1, "bad PCH PLL refcount\n");
3068 intel_crtc
->pch_pll
= NULL
;
3071 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3073 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3074 struct intel_pch_pll
*pll
;
3077 pll
= intel_crtc
->pch_pll
;
3079 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3080 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3084 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3085 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3086 i
= intel_crtc
->pipe
;
3087 pll
= &dev_priv
->pch_plls
[i
];
3089 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3090 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3095 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3096 pll
= &dev_priv
->pch_plls
[i
];
3098 /* Only want to check enabled timings first */
3099 if (pll
->refcount
== 0)
3102 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3103 fp
== I915_READ(pll
->fp0_reg
)) {
3104 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3105 intel_crtc
->base
.base
.id
,
3106 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3112 /* Ok no matching timings, maybe there's a free one? */
3113 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3114 pll
= &dev_priv
->pch_plls
[i
];
3115 if (pll
->refcount
== 0) {
3116 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3117 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3125 intel_crtc
->pch_pll
= pll
;
3127 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3128 prepare
: /* separate function? */
3129 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3131 /* Wait for the clocks to stabilize before rewriting the regs */
3132 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3133 POSTING_READ(pll
->pll_reg
);
3136 I915_WRITE(pll
->fp0_reg
, fp
);
3137 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3142 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3145 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3148 temp
= I915_READ(dslreg
);
3150 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3151 /* Without this, mode sets may fail silently on FDI */
3152 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3154 I915_WRITE(tc2reg
, 0);
3155 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3156 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3160 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3162 struct drm_device
*dev
= crtc
->dev
;
3163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3164 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3165 struct intel_encoder
*encoder
;
3166 int pipe
= intel_crtc
->pipe
;
3167 int plane
= intel_crtc
->plane
;
3171 WARN_ON(!crtc
->enabled
);
3173 if (intel_crtc
->active
)
3176 intel_crtc
->active
= true;
3177 intel_update_watermarks(dev
);
3179 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3180 temp
= I915_READ(PCH_LVDS
);
3181 if ((temp
& LVDS_PORT_EN
) == 0)
3182 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3185 is_pch_port
= intel_crtc_driving_pch(crtc
);
3188 ironlake_fdi_pll_enable(intel_crtc
);
3190 assert_fdi_tx_disabled(dev_priv
, pipe
);
3191 assert_fdi_rx_disabled(dev_priv
, pipe
);
3194 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3195 if (encoder
->pre_enable
)
3196 encoder
->pre_enable(encoder
);
3198 /* Enable panel fitting for LVDS */
3199 if (dev_priv
->pch_pf_size
&&
3200 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3201 /* Force use of hard-coded filter coefficients
3202 * as some pre-programmed values are broken,
3205 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3206 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3207 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3211 * On ILK+ LUT must be loaded before the pipe is running but with
3214 intel_crtc_load_lut(crtc
);
3216 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3217 intel_enable_plane(dev_priv
, plane
, pipe
);
3220 ironlake_pch_enable(crtc
);
3222 mutex_lock(&dev
->struct_mutex
);
3223 intel_update_fbc(dev
);
3224 mutex_unlock(&dev
->struct_mutex
);
3226 intel_crtc_update_cursor(crtc
, true);
3228 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3229 encoder
->enable(encoder
);
3231 if (HAS_PCH_CPT(dev
))
3232 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3235 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3237 struct drm_device
*dev
= crtc
->dev
;
3238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3239 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3240 struct intel_encoder
*encoder
;
3241 int pipe
= intel_crtc
->pipe
;
3242 int plane
= intel_crtc
->plane
;
3246 if (!intel_crtc
->active
)
3249 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3250 encoder
->disable(encoder
);
3252 intel_crtc_wait_for_pending_flips(crtc
);
3253 drm_vblank_off(dev
, pipe
);
3254 intel_crtc_update_cursor(crtc
, false);
3256 intel_disable_plane(dev_priv
, plane
, pipe
);
3258 if (dev_priv
->cfb_plane
== plane
)
3259 intel_disable_fbc(dev
);
3261 intel_disable_pipe(dev_priv
, pipe
);
3264 I915_WRITE(PF_CTL(pipe
), 0);
3265 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3267 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3268 if (encoder
->post_disable
)
3269 encoder
->post_disable(encoder
);
3271 ironlake_fdi_disable(crtc
);
3273 intel_disable_transcoder(dev_priv
, pipe
);
3275 if (HAS_PCH_CPT(dev
)) {
3276 /* disable TRANS_DP_CTL */
3277 reg
= TRANS_DP_CTL(pipe
);
3278 temp
= I915_READ(reg
);
3279 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3280 temp
|= TRANS_DP_PORT_SEL_NONE
;
3281 I915_WRITE(reg
, temp
);
3283 /* disable DPLL_SEL */
3284 temp
= I915_READ(PCH_DPLL_SEL
);
3287 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3290 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3293 /* C shares PLL A or B */
3294 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3299 I915_WRITE(PCH_DPLL_SEL
, temp
);
3302 /* disable PCH DPLL */
3303 intel_disable_pch_pll(intel_crtc
);
3305 ironlake_fdi_pll_disable(intel_crtc
);
3307 intel_crtc
->active
= false;
3308 intel_update_watermarks(dev
);
3310 mutex_lock(&dev
->struct_mutex
);
3311 intel_update_fbc(dev
);
3312 mutex_unlock(&dev
->struct_mutex
);
3315 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3318 intel_put_pch_pll(intel_crtc
);
3321 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3323 if (!enable
&& intel_crtc
->overlay
) {
3324 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3327 mutex_lock(&dev
->struct_mutex
);
3328 dev_priv
->mm
.interruptible
= false;
3329 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3330 dev_priv
->mm
.interruptible
= true;
3331 mutex_unlock(&dev
->struct_mutex
);
3334 /* Let userspace switch the overlay on again. In most cases userspace
3335 * has to recompute where to put it anyway.
3339 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3341 struct drm_device
*dev
= crtc
->dev
;
3342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3344 struct intel_encoder
*encoder
;
3345 int pipe
= intel_crtc
->pipe
;
3346 int plane
= intel_crtc
->plane
;
3348 WARN_ON(!crtc
->enabled
);
3350 if (intel_crtc
->active
)
3353 intel_crtc
->active
= true;
3354 intel_update_watermarks(dev
);
3356 intel_enable_pll(dev_priv
, pipe
);
3357 intel_enable_pipe(dev_priv
, pipe
, false);
3358 intel_enable_plane(dev_priv
, plane
, pipe
);
3360 intel_crtc_load_lut(crtc
);
3361 intel_update_fbc(dev
);
3363 /* Give the overlay scaler a chance to enable if it's on this pipe */
3364 intel_crtc_dpms_overlay(intel_crtc
, true);
3365 intel_crtc_update_cursor(crtc
, true);
3367 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3368 encoder
->enable(encoder
);
3371 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3373 struct drm_device
*dev
= crtc
->dev
;
3374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3375 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3376 struct intel_encoder
*encoder
;
3377 int pipe
= intel_crtc
->pipe
;
3378 int plane
= intel_crtc
->plane
;
3381 if (!intel_crtc
->active
)
3384 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3385 encoder
->disable(encoder
);
3387 /* Give the overlay scaler a chance to disable if it's on this pipe */
3388 intel_crtc_wait_for_pending_flips(crtc
);
3389 drm_vblank_off(dev
, pipe
);
3390 intel_crtc_dpms_overlay(intel_crtc
, false);
3391 intel_crtc_update_cursor(crtc
, false);
3393 if (dev_priv
->cfb_plane
== plane
)
3394 intel_disable_fbc(dev
);
3396 intel_disable_plane(dev_priv
, plane
, pipe
);
3397 intel_disable_pipe(dev_priv
, pipe
);
3398 intel_disable_pll(dev_priv
, pipe
);
3400 intel_crtc
->active
= false;
3401 intel_update_fbc(dev
);
3402 intel_update_watermarks(dev
);
3405 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3409 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3412 struct drm_device
*dev
= crtc
->dev
;
3413 struct drm_i915_master_private
*master_priv
;
3414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3415 int pipe
= intel_crtc
->pipe
;
3417 if (!dev
->primary
->master
)
3420 master_priv
= dev
->primary
->master
->driver_priv
;
3421 if (!master_priv
->sarea_priv
)
3426 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3427 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3430 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3431 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3434 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3440 * Sets the power management mode of the pipe and plane.
3442 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3444 struct drm_device
*dev
= crtc
->dev
;
3445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3446 struct intel_encoder
*intel_encoder
;
3447 bool enable
= false;
3449 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3450 enable
|= intel_encoder
->connectors_active
;
3453 dev_priv
->display
.crtc_enable(crtc
);
3455 dev_priv
->display
.crtc_disable(crtc
);
3457 intel_crtc_update_sarea(crtc
, enable
);
3460 static void intel_crtc_noop(struct drm_crtc
*crtc
)
3464 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3466 struct drm_device
*dev
= crtc
->dev
;
3467 struct drm_connector
*connector
;
3468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3470 /* crtc should still be enabled when we disable it. */
3471 WARN_ON(!crtc
->enabled
);
3473 dev_priv
->display
.crtc_disable(crtc
);
3474 intel_crtc_update_sarea(crtc
, false);
3475 dev_priv
->display
.off(crtc
);
3477 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3478 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3481 mutex_lock(&dev
->struct_mutex
);
3482 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3483 mutex_unlock(&dev
->struct_mutex
);
3487 /* Update computed state. */
3488 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3489 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3492 if (connector
->encoder
->crtc
!= crtc
)
3495 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3496 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3500 void intel_modeset_disable(struct drm_device
*dev
)
3502 struct drm_crtc
*crtc
;
3504 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3506 intel_crtc_disable(crtc
);
3510 void intel_encoder_noop(struct drm_encoder
*encoder
)
3514 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3516 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3518 drm_encoder_cleanup(encoder
);
3519 kfree(intel_encoder
);
3522 /* Simple dpms helper for encodres with just one connector, no cloning and only
3523 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3524 * state of the entire output pipe. */
3525 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3527 if (mode
== DRM_MODE_DPMS_ON
) {
3528 encoder
->connectors_active
= true;
3530 intel_crtc_update_dpms(encoder
->base
.crtc
);
3532 encoder
->connectors_active
= false;
3534 intel_crtc_update_dpms(encoder
->base
.crtc
);
3538 /* Cross check the actual hw state with our own modeset state tracking (and it's
3539 * internal consistency). */
3540 static void intel_connector_check_state(struct intel_connector
*connector
)
3542 if (connector
->get_hw_state(connector
)) {
3543 struct intel_encoder
*encoder
= connector
->encoder
;
3544 struct drm_crtc
*crtc
;
3545 bool encoder_enabled
;
3548 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3549 connector
->base
.base
.id
,
3550 drm_get_connector_name(&connector
->base
));
3552 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3553 "wrong connector dpms state\n");
3554 WARN(connector
->base
.encoder
!= &encoder
->base
,
3555 "active connector not linked to encoder\n");
3556 WARN(!encoder
->connectors_active
,
3557 "encoder->connectors_active not set\n");
3559 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3560 WARN(!encoder_enabled
, "encoder not enabled\n");
3561 if (WARN_ON(!encoder
->base
.crtc
))
3564 crtc
= encoder
->base
.crtc
;
3566 WARN(!crtc
->enabled
, "crtc not enabled\n");
3567 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3568 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3569 "encoder active on the wrong pipe\n");
3573 /* Even simpler default implementation, if there's really no special case to
3575 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3577 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3579 /* All the simple cases only support two dpms states. */
3580 if (mode
!= DRM_MODE_DPMS_ON
)
3581 mode
= DRM_MODE_DPMS_OFF
;
3583 if (mode
== connector
->dpms
)
3586 connector
->dpms
= mode
;
3588 /* Only need to change hw state when actually enabled */
3589 if (encoder
->base
.crtc
)
3590 intel_encoder_dpms(encoder
, mode
);
3592 WARN_ON(encoder
->connectors_active
!= false);
3594 intel_modeset_check_state(connector
->dev
);
3597 /* Simple connector->get_hw_state implementation for encoders that support only
3598 * one connector and no cloning and hence the encoder state determines the state
3599 * of the connector. */
3600 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3603 struct intel_encoder
*encoder
= connector
->encoder
;
3605 return encoder
->get_hw_state(encoder
, &pipe
);
3608 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3609 const struct drm_display_mode
*mode
,
3610 struct drm_display_mode
*adjusted_mode
)
3612 struct drm_device
*dev
= crtc
->dev
;
3614 if (HAS_PCH_SPLIT(dev
)) {
3615 /* FDI link clock is fixed at 2.7G */
3616 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3620 /* All interlaced capable intel hw wants timings in frames. Note though
3621 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3622 * timings, so we need to be careful not to clobber these.*/
3623 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3624 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3626 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3627 * with a hsync front porch of 0.
3629 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3630 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3636 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3638 return 400000; /* FIXME */
3641 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3646 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3651 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3656 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3660 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3662 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3665 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3666 case GC_DISPLAY_CLOCK_333_MHZ
:
3669 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3675 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3680 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3683 /* Assume that the hardware is in the high speed state. This
3684 * should be the default.
3686 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3687 case GC_CLOCK_133_200
:
3688 case GC_CLOCK_100_200
:
3690 case GC_CLOCK_166_250
:
3692 case GC_CLOCK_100_133
:
3696 /* Shouldn't happen */
3700 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3714 fdi_reduce_ratio(u32
*num
, u32
*den
)
3716 while (*num
> 0xffffff || *den
> 0xffffff) {
3723 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3724 int link_clock
, struct fdi_m_n
*m_n
)
3726 m_n
->tu
= 64; /* default size */
3728 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3729 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3730 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3731 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3733 m_n
->link_m
= pixel_clock
;
3734 m_n
->link_n
= link_clock
;
3735 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3738 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3740 if (i915_panel_use_ssc
>= 0)
3741 return i915_panel_use_ssc
!= 0;
3742 return dev_priv
->lvds_use_ssc
3743 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3747 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3748 * @crtc: CRTC structure
3749 * @mode: requested mode
3751 * A pipe may be connected to one or more outputs. Based on the depth of the
3752 * attached framebuffer, choose a good color depth to use on the pipe.
3754 * If possible, match the pipe depth to the fb depth. In some cases, this
3755 * isn't ideal, because the connected output supports a lesser or restricted
3756 * set of depths. Resolve that here:
3757 * LVDS typically supports only 6bpc, so clamp down in that case
3758 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3759 * Displays may support a restricted set as well, check EDID and clamp as
3761 * DP may want to dither down to 6bpc to fit larger modes
3764 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3765 * true if they don't match).
3767 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
3768 struct drm_framebuffer
*fb
,
3769 unsigned int *pipe_bpp
,
3770 struct drm_display_mode
*mode
)
3772 struct drm_device
*dev
= crtc
->dev
;
3773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3774 struct drm_connector
*connector
;
3775 struct intel_encoder
*intel_encoder
;
3776 unsigned int display_bpc
= UINT_MAX
, bpc
;
3778 /* Walk the encoders & connectors on this crtc, get min bpc */
3779 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3781 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
3782 unsigned int lvds_bpc
;
3784 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
3790 if (lvds_bpc
< display_bpc
) {
3791 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
3792 display_bpc
= lvds_bpc
;
3797 /* Not one of the known troublemakers, check the EDID */
3798 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
3800 if (connector
->encoder
!= &intel_encoder
->base
)
3803 /* Don't use an invalid EDID bpc value */
3804 if (connector
->display_info
.bpc
&&
3805 connector
->display_info
.bpc
< display_bpc
) {
3806 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
3807 display_bpc
= connector
->display_info
.bpc
;
3812 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3813 * through, clamp it down. (Note: >12bpc will be caught below.)
3815 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
3816 if (display_bpc
> 8 && display_bpc
< 12) {
3817 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3820 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3826 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
3827 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3832 * We could just drive the pipe at the highest bpc all the time and
3833 * enable dithering as needed, but that costs bandwidth. So choose
3834 * the minimum value that expresses the full color range of the fb but
3835 * also stays within the max display bpc discovered above.
3838 switch (fb
->depth
) {
3840 bpc
= 8; /* since we go through a colormap */
3844 bpc
= 6; /* min is 18bpp */
3856 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3857 bpc
= min((unsigned int)8, display_bpc
);
3861 display_bpc
= min(display_bpc
, bpc
);
3863 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3866 *pipe_bpp
= display_bpc
* 3;
3868 return display_bpc
!= bpc
;
3871 static int vlv_get_refclk(struct drm_crtc
*crtc
)
3873 struct drm_device
*dev
= crtc
->dev
;
3874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3875 int refclk
= 27000; /* for DP & HDMI */
3877 return 100000; /* only one validated so far */
3879 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
3881 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3882 if (intel_panel_use_ssc(dev_priv
))
3886 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3893 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
3895 struct drm_device
*dev
= crtc
->dev
;
3896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3899 if (IS_VALLEYVIEW(dev
)) {
3900 refclk
= vlv_get_refclk(crtc
);
3901 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3902 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
3903 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3904 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3906 } else if (!IS_GEN2(dev
)) {
3915 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
3916 intel_clock_t
*clock
)
3918 /* SDVO TV has fixed PLL values depend on its clock range,
3919 this mirrors vbios setting. */
3920 if (adjusted_mode
->clock
>= 100000
3921 && adjusted_mode
->clock
< 140500) {
3927 } else if (adjusted_mode
->clock
>= 140500
3928 && adjusted_mode
->clock
<= 200000) {
3937 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
3938 intel_clock_t
*clock
,
3939 intel_clock_t
*reduced_clock
)
3941 struct drm_device
*dev
= crtc
->dev
;
3942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3944 int pipe
= intel_crtc
->pipe
;
3947 if (IS_PINEVIEW(dev
)) {
3948 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
3950 fp2
= (1 << reduced_clock
->n
) << 16 |
3951 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
3953 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
3955 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
3959 I915_WRITE(FP0(pipe
), fp
);
3961 intel_crtc
->lowfreq_avail
= false;
3962 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3963 reduced_clock
&& i915_powersave
) {
3964 I915_WRITE(FP1(pipe
), fp2
);
3965 intel_crtc
->lowfreq_avail
= true;
3967 I915_WRITE(FP1(pipe
), fp
);
3971 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
3972 struct drm_display_mode
*adjusted_mode
)
3974 struct drm_device
*dev
= crtc
->dev
;
3975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3976 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3977 int pipe
= intel_crtc
->pipe
;
3980 temp
= I915_READ(LVDS
);
3981 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3983 temp
|= LVDS_PIPEB_SELECT
;
3985 temp
&= ~LVDS_PIPEB_SELECT
;
3987 /* set the corresponsding LVDS_BORDER bit */
3988 temp
|= dev_priv
->lvds_border_bits
;
3989 /* Set the B0-B3 data pairs corresponding to whether we're going to
3990 * set the DPLLs for dual-channel mode or not.
3993 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3995 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3997 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3998 * appropriately here, but we need to look more thoroughly into how
3999 * panels behave in the two modes.
4001 /* set the dithering flag on LVDS as needed */
4002 if (INTEL_INFO(dev
)->gen
>= 4) {
4003 if (dev_priv
->lvds_dither
)
4004 temp
|= LVDS_ENABLE_DITHER
;
4006 temp
&= ~LVDS_ENABLE_DITHER
;
4008 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4009 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4010 temp
|= LVDS_HSYNC_POLARITY
;
4011 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4012 temp
|= LVDS_VSYNC_POLARITY
;
4013 I915_WRITE(LVDS
, temp
);
4016 static void vlv_update_pll(struct drm_crtc
*crtc
,
4017 struct drm_display_mode
*mode
,
4018 struct drm_display_mode
*adjusted_mode
,
4019 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4020 int refclk
, int num_connectors
)
4022 struct drm_device
*dev
= crtc
->dev
;
4023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4024 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4025 int pipe
= intel_crtc
->pipe
;
4026 u32 dpll
, mdiv
, pdiv
;
4027 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4030 is_hdmi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4038 /* Enable DPIO clock input */
4039 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4040 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4041 I915_WRITE(DPLL(pipe
), dpll
);
4042 POSTING_READ(DPLL(pipe
));
4044 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4045 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4046 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4047 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4048 mdiv
|= (1 << DPIO_K_SHIFT
);
4049 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4050 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4052 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4054 pdiv
= DPIO_REFSEL_OVERRIDE
| (5 << DPIO_PLL_MODESEL_SHIFT
) |
4055 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4056 (8 << DPIO_DRIVER_CTL_SHIFT
) | (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4057 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4059 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x009f0051);
4061 dpll
|= DPLL_VCO_ENABLE
;
4062 I915_WRITE(DPLL(pipe
), dpll
);
4063 POSTING_READ(DPLL(pipe
));
4064 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4065 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4068 u32 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4071 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4075 I915_WRITE(DPLL_MD(pipe
), temp
);
4076 POSTING_READ(DPLL_MD(pipe
));
4079 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x641); /* ??? */
4082 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4083 struct drm_display_mode
*mode
,
4084 struct drm_display_mode
*adjusted_mode
,
4085 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4088 struct drm_device
*dev
= crtc
->dev
;
4089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4090 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4091 int pipe
= intel_crtc
->pipe
;
4095 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4096 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4098 dpll
= DPLL_VGA_MODE_DIS
;
4100 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4101 dpll
|= DPLLB_MODE_LVDS
;
4103 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4105 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4106 if (pixel_multiplier
> 1) {
4107 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4108 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4110 dpll
|= DPLL_DVO_HIGH_SPEED
;
4112 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4113 dpll
|= DPLL_DVO_HIGH_SPEED
;
4115 /* compute bitmask from p1 value */
4116 if (IS_PINEVIEW(dev
))
4117 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4119 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4120 if (IS_G4X(dev
) && reduced_clock
)
4121 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4123 switch (clock
->p2
) {
4125 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4128 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4131 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4134 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4137 if (INTEL_INFO(dev
)->gen
>= 4)
4138 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4140 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4141 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4142 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4143 /* XXX: just matching BIOS for now */
4144 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4146 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4147 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4148 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4150 dpll
|= PLL_REF_INPUT_DREFCLK
;
4152 dpll
|= DPLL_VCO_ENABLE
;
4153 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4154 POSTING_READ(DPLL(pipe
));
4157 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4158 * This is an exception to the general rule that mode_set doesn't turn
4161 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4162 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4164 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4165 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4167 I915_WRITE(DPLL(pipe
), dpll
);
4169 /* Wait for the clocks to stabilize. */
4170 POSTING_READ(DPLL(pipe
));
4173 if (INTEL_INFO(dev
)->gen
>= 4) {
4176 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4178 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4182 I915_WRITE(DPLL_MD(pipe
), temp
);
4184 /* The pixel multiplier can only be updated once the
4185 * DPLL is enabled and the clocks are stable.
4187 * So write it again.
4189 I915_WRITE(DPLL(pipe
), dpll
);
4193 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4194 struct drm_display_mode
*adjusted_mode
,
4195 intel_clock_t
*clock
,
4198 struct drm_device
*dev
= crtc
->dev
;
4199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4201 int pipe
= intel_crtc
->pipe
;
4204 dpll
= DPLL_VGA_MODE_DIS
;
4206 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4207 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4210 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4212 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4214 dpll
|= PLL_P2_DIVIDE_BY_4
;
4217 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4218 /* XXX: just matching BIOS for now */
4219 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4221 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4222 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4223 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4225 dpll
|= PLL_REF_INPUT_DREFCLK
;
4227 dpll
|= DPLL_VCO_ENABLE
;
4228 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4229 POSTING_READ(DPLL(pipe
));
4232 I915_WRITE(DPLL(pipe
), dpll
);
4234 /* Wait for the clocks to stabilize. */
4235 POSTING_READ(DPLL(pipe
));
4238 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4239 * This is an exception to the general rule that mode_set doesn't turn
4242 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4243 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4245 /* The pixel multiplier can only be updated once the
4246 * DPLL is enabled and the clocks are stable.
4248 * So write it again.
4250 I915_WRITE(DPLL(pipe
), dpll
);
4253 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4254 struct drm_display_mode
*mode
,
4255 struct drm_display_mode
*adjusted_mode
,
4257 struct drm_framebuffer
*fb
)
4259 struct drm_device
*dev
= crtc
->dev
;
4260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4261 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4262 int pipe
= intel_crtc
->pipe
;
4263 int plane
= intel_crtc
->plane
;
4264 int refclk
, num_connectors
= 0;
4265 intel_clock_t clock
, reduced_clock
;
4266 u32 dspcntr
, pipeconf
, vsyncshift
;
4267 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4268 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4269 struct intel_encoder
*encoder
;
4270 const intel_limit_t
*limit
;
4273 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4274 switch (encoder
->type
) {
4275 case INTEL_OUTPUT_LVDS
:
4278 case INTEL_OUTPUT_SDVO
:
4279 case INTEL_OUTPUT_HDMI
:
4281 if (encoder
->needs_tv_clock
)
4284 case INTEL_OUTPUT_TVOUT
:
4287 case INTEL_OUTPUT_DISPLAYPORT
:
4295 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4298 * Returns a set of divisors for the desired target clock with the given
4299 * refclk, or FALSE. The returned values represent the clock equation:
4300 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4302 limit
= intel_limit(crtc
, refclk
);
4303 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4306 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4310 /* Ensure that the cursor is valid for the new mode before changing... */
4311 intel_crtc_update_cursor(crtc
, true);
4313 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4315 * Ensure we match the reduced clock's P to the target clock.
4316 * If the clocks don't match, we can't switch the display clock
4317 * by using the FP0/FP1. In such case we will disable the LVDS
4318 * downclock feature.
4320 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4321 dev_priv
->lvds_downclock
,
4327 if (is_sdvo
&& is_tv
)
4328 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4330 i9xx_update_pll_dividers(crtc
, &clock
, has_reduced_clock
?
4331 &reduced_clock
: NULL
);
4334 i8xx_update_pll(crtc
, adjusted_mode
, &clock
, num_connectors
);
4335 else if (IS_VALLEYVIEW(dev
))
4336 vlv_update_pll(crtc
, mode
,adjusted_mode
, &clock
, NULL
,
4337 refclk
, num_connectors
);
4339 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4340 has_reduced_clock
? &reduced_clock
: NULL
,
4343 /* setup pipeconf */
4344 pipeconf
= I915_READ(PIPECONF(pipe
));
4346 /* Set up the display plane register */
4347 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4350 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4352 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4354 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4355 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4358 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4362 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4363 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4365 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4368 /* default to 8bpc */
4369 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4371 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4372 pipeconf
|= PIPECONF_BPP_6
|
4373 PIPECONF_DITHER_EN
|
4374 PIPECONF_DITHER_TYPE_SP
;
4378 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4379 drm_mode_debug_printmodeline(mode
);
4381 if (HAS_PIPE_CXSR(dev
)) {
4382 if (intel_crtc
->lowfreq_avail
) {
4383 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4384 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4386 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4387 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4391 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4392 if (!IS_GEN2(dev
) &&
4393 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4394 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4395 /* the chip adds 2 halflines automatically */
4396 adjusted_mode
->crtc_vtotal
-= 1;
4397 adjusted_mode
->crtc_vblank_end
-= 1;
4398 vsyncshift
= adjusted_mode
->crtc_hsync_start
4399 - adjusted_mode
->crtc_htotal
/2;
4401 pipeconf
|= PIPECONF_PROGRESSIVE
;
4406 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
4408 I915_WRITE(HTOTAL(pipe
),
4409 (adjusted_mode
->crtc_hdisplay
- 1) |
4410 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4411 I915_WRITE(HBLANK(pipe
),
4412 (adjusted_mode
->crtc_hblank_start
- 1) |
4413 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4414 I915_WRITE(HSYNC(pipe
),
4415 (adjusted_mode
->crtc_hsync_start
- 1) |
4416 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4418 I915_WRITE(VTOTAL(pipe
),
4419 (adjusted_mode
->crtc_vdisplay
- 1) |
4420 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4421 I915_WRITE(VBLANK(pipe
),
4422 (adjusted_mode
->crtc_vblank_start
- 1) |
4423 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4424 I915_WRITE(VSYNC(pipe
),
4425 (adjusted_mode
->crtc_vsync_start
- 1) |
4426 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4428 /* pipesrc and dspsize control the size that is scaled from,
4429 * which should always be the user's requested size.
4431 I915_WRITE(DSPSIZE(plane
),
4432 ((mode
->vdisplay
- 1) << 16) |
4433 (mode
->hdisplay
- 1));
4434 I915_WRITE(DSPPOS(plane
), 0);
4435 I915_WRITE(PIPESRC(pipe
),
4436 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4438 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4439 POSTING_READ(PIPECONF(pipe
));
4440 intel_enable_pipe(dev_priv
, pipe
, false);
4442 intel_wait_for_vblank(dev
, pipe
);
4444 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4445 POSTING_READ(DSPCNTR(plane
));
4447 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4449 intel_update_watermarks(dev
);
4455 * Initialize reference clocks when the driver loads
4457 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4460 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4461 struct intel_encoder
*encoder
;
4463 bool has_lvds
= false;
4464 bool has_cpu_edp
= false;
4465 bool has_pch_edp
= false;
4466 bool has_panel
= false;
4467 bool has_ck505
= false;
4468 bool can_ssc
= false;
4470 /* We need to take the global config into account */
4471 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4473 switch (encoder
->type
) {
4474 case INTEL_OUTPUT_LVDS
:
4478 case INTEL_OUTPUT_EDP
:
4480 if (intel_encoder_is_pch_edp(&encoder
->base
))
4488 if (HAS_PCH_IBX(dev
)) {
4489 has_ck505
= dev_priv
->display_clock_mode
;
4490 can_ssc
= has_ck505
;
4496 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4497 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4500 /* Ironlake: try to setup display ref clock before DPLL
4501 * enabling. This is only under driver's control after
4502 * PCH B stepping, previous chipset stepping should be
4503 * ignoring this setting.
4505 temp
= I915_READ(PCH_DREF_CONTROL
);
4506 /* Always enable nonspread source */
4507 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4510 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4512 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4515 temp
&= ~DREF_SSC_SOURCE_MASK
;
4516 temp
|= DREF_SSC_SOURCE_ENABLE
;
4518 /* SSC must be turned on before enabling the CPU output */
4519 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4520 DRM_DEBUG_KMS("Using SSC on panel\n");
4521 temp
|= DREF_SSC1_ENABLE
;
4523 temp
&= ~DREF_SSC1_ENABLE
;
4525 /* Get SSC going before enabling the outputs */
4526 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4527 POSTING_READ(PCH_DREF_CONTROL
);
4530 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4532 /* Enable CPU source on CPU attached eDP */
4534 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4535 DRM_DEBUG_KMS("Using SSC on eDP\n");
4536 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4539 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4541 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4543 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4544 POSTING_READ(PCH_DREF_CONTROL
);
4547 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4549 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4551 /* Turn off CPU output */
4552 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4554 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4555 POSTING_READ(PCH_DREF_CONTROL
);
4558 /* Turn off the SSC source */
4559 temp
&= ~DREF_SSC_SOURCE_MASK
;
4560 temp
|= DREF_SSC_SOURCE_DISABLE
;
4563 temp
&= ~ DREF_SSC1_ENABLE
;
4565 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4566 POSTING_READ(PCH_DREF_CONTROL
);
4571 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4573 struct drm_device
*dev
= crtc
->dev
;
4574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4575 struct intel_encoder
*encoder
;
4576 struct intel_encoder
*edp_encoder
= NULL
;
4577 int num_connectors
= 0;
4578 bool is_lvds
= false;
4580 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4581 switch (encoder
->type
) {
4582 case INTEL_OUTPUT_LVDS
:
4585 case INTEL_OUTPUT_EDP
:
4586 edp_encoder
= encoder
;
4592 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4593 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4594 dev_priv
->lvds_ssc_freq
);
4595 return dev_priv
->lvds_ssc_freq
* 1000;
4601 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
4602 struct drm_display_mode
*adjusted_mode
,
4605 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4606 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4607 int pipe
= intel_crtc
->pipe
;
4610 val
= I915_READ(PIPECONF(pipe
));
4612 val
&= ~PIPE_BPC_MASK
;
4613 switch (intel_crtc
->bpp
) {
4631 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
4633 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
4635 val
&= ~PIPECONF_INTERLACE_MASK
;
4636 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4637 val
|= PIPECONF_INTERLACED_ILK
;
4639 val
|= PIPECONF_PROGRESSIVE
;
4641 I915_WRITE(PIPECONF(pipe
), val
);
4642 POSTING_READ(PIPECONF(pipe
));
4645 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
4646 struct drm_display_mode
*adjusted_mode
,
4647 intel_clock_t
*clock
,
4648 bool *has_reduced_clock
,
4649 intel_clock_t
*reduced_clock
)
4651 struct drm_device
*dev
= crtc
->dev
;
4652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4653 struct intel_encoder
*intel_encoder
;
4655 const intel_limit_t
*limit
;
4656 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
4658 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4659 switch (intel_encoder
->type
) {
4660 case INTEL_OUTPUT_LVDS
:
4663 case INTEL_OUTPUT_SDVO
:
4664 case INTEL_OUTPUT_HDMI
:
4666 if (intel_encoder
->needs_tv_clock
)
4669 case INTEL_OUTPUT_TVOUT
:
4675 refclk
= ironlake_get_refclk(crtc
);
4678 * Returns a set of divisors for the desired target clock with the given
4679 * refclk, or FALSE. The returned values represent the clock equation:
4680 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4682 limit
= intel_limit(crtc
, refclk
);
4683 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4688 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4690 * Ensure we match the reduced clock's P to the target clock.
4691 * If the clocks don't match, we can't switch the display clock
4692 * by using the FP0/FP1. In such case we will disable the LVDS
4693 * downclock feature.
4695 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4696 dev_priv
->lvds_downclock
,
4702 if (is_sdvo
&& is_tv
)
4703 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
4708 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
4709 struct drm_display_mode
*mode
,
4710 struct drm_display_mode
*adjusted_mode
,
4712 struct drm_framebuffer
*fb
)
4714 struct drm_device
*dev
= crtc
->dev
;
4715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4716 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4717 int pipe
= intel_crtc
->pipe
;
4718 int plane
= intel_crtc
->plane
;
4719 int num_connectors
= 0;
4720 intel_clock_t clock
, reduced_clock
;
4721 u32 dpll
, fp
= 0, fp2
= 0;
4722 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4723 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4724 struct intel_encoder
*encoder
, *edp_encoder
= NULL
;
4726 struct fdi_m_n m_n
= {0};
4728 int target_clock
, pixel_multiplier
, lane
, link_bw
, factor
;
4729 unsigned int pipe_bpp
;
4731 bool is_cpu_edp
= false, is_pch_edp
= false;
4733 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4734 switch (encoder
->type
) {
4735 case INTEL_OUTPUT_LVDS
:
4738 case INTEL_OUTPUT_SDVO
:
4739 case INTEL_OUTPUT_HDMI
:
4741 if (encoder
->needs_tv_clock
)
4744 case INTEL_OUTPUT_TVOUT
:
4747 case INTEL_OUTPUT_ANALOG
:
4750 case INTEL_OUTPUT_DISPLAYPORT
:
4753 case INTEL_OUTPUT_EDP
:
4755 if (intel_encoder_is_pch_edp(&encoder
->base
))
4759 edp_encoder
= encoder
;
4766 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
4767 &has_reduced_clock
, &reduced_clock
);
4769 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4773 /* Ensure that the cursor is valid for the new mode before changing... */
4774 intel_crtc_update_cursor(crtc
, true);
4777 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4779 /* CPU eDP doesn't require FDI link, so just set DP M/N
4780 according to current link config */
4782 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
4784 /* FDI is a binary signal running at ~2.7GHz, encoding
4785 * each output octet as 10 bits. The actual frequency
4786 * is stored as a divider into a 100MHz clock, and the
4787 * mode pixel clock is stored in units of 1KHz.
4788 * Hence the bw of each lane in terms of the mode signal
4791 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4794 /* [e]DP over FDI requires target mode clock instead of link clock. */
4796 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
4798 target_clock
= mode
->clock
;
4800 target_clock
= adjusted_mode
->clock
;
4802 /* determine panel color depth */
4803 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &pipe_bpp
, mode
);
4804 if (is_lvds
&& dev_priv
->lvds_dither
)
4807 if (pipe_bpp
!= 18 && pipe_bpp
!= 24 && pipe_bpp
!= 30 &&
4809 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4813 intel_crtc
->bpp
= pipe_bpp
;
4817 * Account for spread spectrum to avoid
4818 * oversubscribing the link. Max center spread
4819 * is 2.5%; use 5% for safety's sake.
4821 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
4822 lane
= bps
/ (link_bw
* 8) + 1;
4825 intel_crtc
->fdi_lanes
= lane
;
4827 if (pixel_multiplier
> 1)
4828 link_bw
*= pixel_multiplier
;
4829 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
4832 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4833 if (has_reduced_clock
)
4834 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4837 /* Enable autotuning of the PLL clock (if permissible) */
4840 if ((intel_panel_use_ssc(dev_priv
) &&
4841 dev_priv
->lvds_ssc_freq
== 100) ||
4842 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4844 } else if (is_sdvo
&& is_tv
)
4847 if (clock
.m
< factor
* clock
.n
)
4853 dpll
|= DPLLB_MODE_LVDS
;
4855 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4857 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4858 if (pixel_multiplier
> 1) {
4859 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4861 dpll
|= DPLL_DVO_HIGH_SPEED
;
4863 if (is_dp
&& !is_cpu_edp
)
4864 dpll
|= DPLL_DVO_HIGH_SPEED
;
4866 /* compute bitmask from p1 value */
4867 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4869 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4873 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4876 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4879 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4882 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4886 if (is_sdvo
&& is_tv
)
4887 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4889 /* XXX: just matching BIOS for now */
4890 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4892 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4893 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4895 dpll
|= PLL_REF_INPUT_DREFCLK
;
4897 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
4898 drm_mode_debug_printmodeline(mode
);
4900 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4901 * pre-Haswell/LPT generation */
4902 if (HAS_PCH_LPT(dev
)) {
4903 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4905 } else if (!is_cpu_edp
) {
4906 struct intel_pch_pll
*pll
;
4908 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
4910 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4915 intel_put_pch_pll(intel_crtc
);
4917 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4918 * This is an exception to the general rule that mode_set doesn't turn
4922 temp
= I915_READ(PCH_LVDS
);
4923 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4924 if (HAS_PCH_CPT(dev
)) {
4925 temp
&= ~PORT_TRANS_SEL_MASK
;
4926 temp
|= PORT_TRANS_SEL_CPT(pipe
);
4929 temp
|= LVDS_PIPEB_SELECT
;
4931 temp
&= ~LVDS_PIPEB_SELECT
;
4934 /* set the corresponsding LVDS_BORDER bit */
4935 temp
|= dev_priv
->lvds_border_bits
;
4936 /* Set the B0-B3 data pairs corresponding to whether we're going to
4937 * set the DPLLs for dual-channel mode or not.
4940 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4942 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4944 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4945 * appropriately here, but we need to look more thoroughly into how
4946 * panels behave in the two modes.
4948 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4949 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4950 temp
|= LVDS_HSYNC_POLARITY
;
4951 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4952 temp
|= LVDS_VSYNC_POLARITY
;
4953 I915_WRITE(PCH_LVDS
, temp
);
4956 if (is_dp
&& !is_cpu_edp
) {
4957 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4959 /* For non-DP output, clear any trans DP clock recovery setting.*/
4960 I915_WRITE(TRANSDATA_M1(pipe
), 0);
4961 I915_WRITE(TRANSDATA_N1(pipe
), 0);
4962 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
4963 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
4966 if (intel_crtc
->pch_pll
) {
4967 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4969 /* Wait for the clocks to stabilize. */
4970 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
4973 /* The pixel multiplier can only be updated once the
4974 * DPLL is enabled and the clocks are stable.
4976 * So write it again.
4978 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4981 intel_crtc
->lowfreq_avail
= false;
4982 if (intel_crtc
->pch_pll
) {
4983 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4984 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
4985 intel_crtc
->lowfreq_avail
= true;
4987 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
4991 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4992 /* the chip adds 2 halflines automatically */
4993 adjusted_mode
->crtc_vtotal
-= 1;
4994 adjusted_mode
->crtc_vblank_end
-= 1;
4995 I915_WRITE(VSYNCSHIFT(pipe
),
4996 adjusted_mode
->crtc_hsync_start
4997 - adjusted_mode
->crtc_htotal
/2);
4999 I915_WRITE(VSYNCSHIFT(pipe
), 0);
5002 I915_WRITE(HTOTAL(pipe
),
5003 (adjusted_mode
->crtc_hdisplay
- 1) |
5004 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5005 I915_WRITE(HBLANK(pipe
),
5006 (adjusted_mode
->crtc_hblank_start
- 1) |
5007 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5008 I915_WRITE(HSYNC(pipe
),
5009 (adjusted_mode
->crtc_hsync_start
- 1) |
5010 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5012 I915_WRITE(VTOTAL(pipe
),
5013 (adjusted_mode
->crtc_vdisplay
- 1) |
5014 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
5015 I915_WRITE(VBLANK(pipe
),
5016 (adjusted_mode
->crtc_vblank_start
- 1) |
5017 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
5018 I915_WRITE(VSYNC(pipe
),
5019 (adjusted_mode
->crtc_vsync_start
- 1) |
5020 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5022 /* pipesrc controls the size that is scaled from, which should
5023 * always be the user's requested size.
5025 I915_WRITE(PIPESRC(pipe
),
5026 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
5028 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5029 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
5030 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
5031 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
5034 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5036 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5038 intel_wait_for_vblank(dev
, pipe
);
5040 /* Set up the display plane register */
5041 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5042 POSTING_READ(DSPCNTR(plane
));
5044 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5046 intel_update_watermarks(dev
);
5048 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5053 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5054 struct drm_display_mode
*mode
,
5055 struct drm_display_mode
*adjusted_mode
,
5057 struct drm_framebuffer
*fb
)
5059 struct drm_device
*dev
= crtc
->dev
;
5060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5061 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5062 int pipe
= intel_crtc
->pipe
;
5065 drm_vblank_pre_modeset(dev
, pipe
);
5067 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5069 drm_vblank_post_modeset(dev
, pipe
);
5074 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5075 int reg_eldv
, uint32_t bits_eldv
,
5076 int reg_elda
, uint32_t bits_elda
,
5079 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5080 uint8_t *eld
= connector
->eld
;
5083 i
= I915_READ(reg_eldv
);
5092 i
= I915_READ(reg_elda
);
5094 I915_WRITE(reg_elda
, i
);
5096 for (i
= 0; i
< eld
[2]; i
++)
5097 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5103 static void g4x_write_eld(struct drm_connector
*connector
,
5104 struct drm_crtc
*crtc
)
5106 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5107 uint8_t *eld
= connector
->eld
;
5112 i
= I915_READ(G4X_AUD_VID_DID
);
5114 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5115 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5117 eldv
= G4X_ELDV_DEVCTG
;
5119 if (intel_eld_uptodate(connector
,
5120 G4X_AUD_CNTL_ST
, eldv
,
5121 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5122 G4X_HDMIW_HDMIEDID
))
5125 i
= I915_READ(G4X_AUD_CNTL_ST
);
5126 i
&= ~(eldv
| G4X_ELD_ADDR
);
5127 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5128 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5133 len
= min_t(uint8_t, eld
[2], len
);
5134 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5135 for (i
= 0; i
< len
; i
++)
5136 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5138 i
= I915_READ(G4X_AUD_CNTL_ST
);
5140 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5143 static void haswell_write_eld(struct drm_connector
*connector
,
5144 struct drm_crtc
*crtc
)
5146 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5147 uint8_t *eld
= connector
->eld
;
5148 struct drm_device
*dev
= crtc
->dev
;
5152 int pipe
= to_intel_crtc(crtc
)->pipe
;
5155 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5156 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5157 int aud_config
= HSW_AUD_CFG(pipe
);
5158 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5161 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5163 /* Audio output enable */
5164 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5165 tmp
= I915_READ(aud_cntrl_st2
);
5166 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5167 I915_WRITE(aud_cntrl_st2
, tmp
);
5169 /* Wait for 1 vertical blank */
5170 intel_wait_for_vblank(dev
, pipe
);
5172 /* Set ELD valid state */
5173 tmp
= I915_READ(aud_cntrl_st2
);
5174 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5175 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5176 I915_WRITE(aud_cntrl_st2
, tmp
);
5177 tmp
= I915_READ(aud_cntrl_st2
);
5178 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5180 /* Enable HDMI mode */
5181 tmp
= I915_READ(aud_config
);
5182 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5183 /* clear N_programing_enable and N_value_index */
5184 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5185 I915_WRITE(aud_config
, tmp
);
5187 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5189 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5191 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5192 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5193 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5194 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5196 I915_WRITE(aud_config
, 0);
5198 if (intel_eld_uptodate(connector
,
5199 aud_cntrl_st2
, eldv
,
5200 aud_cntl_st
, IBX_ELD_ADDRESS
,
5204 i
= I915_READ(aud_cntrl_st2
);
5206 I915_WRITE(aud_cntrl_st2
, i
);
5211 i
= I915_READ(aud_cntl_st
);
5212 i
&= ~IBX_ELD_ADDRESS
;
5213 I915_WRITE(aud_cntl_st
, i
);
5214 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5215 DRM_DEBUG_DRIVER("port num:%d\n", i
);
5217 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5218 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5219 for (i
= 0; i
< len
; i
++)
5220 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5222 i
= I915_READ(aud_cntrl_st2
);
5224 I915_WRITE(aud_cntrl_st2
, i
);
5228 static void ironlake_write_eld(struct drm_connector
*connector
,
5229 struct drm_crtc
*crtc
)
5231 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5232 uint8_t *eld
= connector
->eld
;
5240 int pipe
= to_intel_crtc(crtc
)->pipe
;
5242 if (HAS_PCH_IBX(connector
->dev
)) {
5243 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
5244 aud_config
= IBX_AUD_CFG(pipe
);
5245 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
5246 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5248 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
5249 aud_config
= CPT_AUD_CFG(pipe
);
5250 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
5251 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5254 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5256 i
= I915_READ(aud_cntl_st
);
5257 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5259 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5260 /* operate blindly on all ports */
5261 eldv
= IBX_ELD_VALIDB
;
5262 eldv
|= IBX_ELD_VALIDB
<< 4;
5263 eldv
|= IBX_ELD_VALIDB
<< 8;
5265 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5266 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5269 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5270 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5271 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5272 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5274 I915_WRITE(aud_config
, 0);
5276 if (intel_eld_uptodate(connector
,
5277 aud_cntrl_st2
, eldv
,
5278 aud_cntl_st
, IBX_ELD_ADDRESS
,
5282 i
= I915_READ(aud_cntrl_st2
);
5284 I915_WRITE(aud_cntrl_st2
, i
);
5289 i
= I915_READ(aud_cntl_st
);
5290 i
&= ~IBX_ELD_ADDRESS
;
5291 I915_WRITE(aud_cntl_st
, i
);
5293 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5294 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5295 for (i
= 0; i
< len
; i
++)
5296 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5298 i
= I915_READ(aud_cntrl_st2
);
5300 I915_WRITE(aud_cntrl_st2
, i
);
5303 void intel_write_eld(struct drm_encoder
*encoder
,
5304 struct drm_display_mode
*mode
)
5306 struct drm_crtc
*crtc
= encoder
->crtc
;
5307 struct drm_connector
*connector
;
5308 struct drm_device
*dev
= encoder
->dev
;
5309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5311 connector
= drm_select_eld(encoder
, mode
);
5315 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5317 drm_get_connector_name(connector
),
5318 connector
->encoder
->base
.id
,
5319 drm_get_encoder_name(connector
->encoder
));
5321 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5323 if (dev_priv
->display
.write_eld
)
5324 dev_priv
->display
.write_eld(connector
, crtc
);
5327 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5328 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5330 struct drm_device
*dev
= crtc
->dev
;
5331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5333 int palreg
= PALETTE(intel_crtc
->pipe
);
5336 /* The clocks have to be on to load the palette. */
5337 if (!crtc
->enabled
|| !intel_crtc
->active
)
5340 /* use legacy palette for Ironlake */
5341 if (HAS_PCH_SPLIT(dev
))
5342 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5344 for (i
= 0; i
< 256; i
++) {
5345 I915_WRITE(palreg
+ 4 * i
,
5346 (intel_crtc
->lut_r
[i
] << 16) |
5347 (intel_crtc
->lut_g
[i
] << 8) |
5348 intel_crtc
->lut_b
[i
]);
5352 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5354 struct drm_device
*dev
= crtc
->dev
;
5355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5356 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5357 bool visible
= base
!= 0;
5360 if (intel_crtc
->cursor_visible
== visible
)
5363 cntl
= I915_READ(_CURACNTR
);
5365 /* On these chipsets we can only modify the base whilst
5366 * the cursor is disabled.
5368 I915_WRITE(_CURABASE
, base
);
5370 cntl
&= ~(CURSOR_FORMAT_MASK
);
5371 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5372 cntl
|= CURSOR_ENABLE
|
5373 CURSOR_GAMMA_ENABLE
|
5376 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5377 I915_WRITE(_CURACNTR
, cntl
);
5379 intel_crtc
->cursor_visible
= visible
;
5382 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5384 struct drm_device
*dev
= crtc
->dev
;
5385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5386 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5387 int pipe
= intel_crtc
->pipe
;
5388 bool visible
= base
!= 0;
5390 if (intel_crtc
->cursor_visible
!= visible
) {
5391 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5393 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5394 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5395 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5397 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5398 cntl
|= CURSOR_MODE_DISABLE
;
5400 I915_WRITE(CURCNTR(pipe
), cntl
);
5402 intel_crtc
->cursor_visible
= visible
;
5404 /* and commit changes on next vblank */
5405 I915_WRITE(CURBASE(pipe
), base
);
5408 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5410 struct drm_device
*dev
= crtc
->dev
;
5411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5412 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5413 int pipe
= intel_crtc
->pipe
;
5414 bool visible
= base
!= 0;
5416 if (intel_crtc
->cursor_visible
!= visible
) {
5417 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
5419 cntl
&= ~CURSOR_MODE
;
5420 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5422 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5423 cntl
|= CURSOR_MODE_DISABLE
;
5425 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
5427 intel_crtc
->cursor_visible
= visible
;
5429 /* and commit changes on next vblank */
5430 I915_WRITE(CURBASE_IVB(pipe
), base
);
5433 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5434 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5437 struct drm_device
*dev
= crtc
->dev
;
5438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5439 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5440 int pipe
= intel_crtc
->pipe
;
5441 int x
= intel_crtc
->cursor_x
;
5442 int y
= intel_crtc
->cursor_y
;
5448 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5449 base
= intel_crtc
->cursor_addr
;
5450 if (x
> (int) crtc
->fb
->width
)
5453 if (y
> (int) crtc
->fb
->height
)
5459 if (x
+ intel_crtc
->cursor_width
< 0)
5462 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5465 pos
|= x
<< CURSOR_X_SHIFT
;
5468 if (y
+ intel_crtc
->cursor_height
< 0)
5471 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5474 pos
|= y
<< CURSOR_Y_SHIFT
;
5476 visible
= base
!= 0;
5477 if (!visible
&& !intel_crtc
->cursor_visible
)
5480 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5481 I915_WRITE(CURPOS_IVB(pipe
), pos
);
5482 ivb_update_cursor(crtc
, base
);
5484 I915_WRITE(CURPOS(pipe
), pos
);
5485 if (IS_845G(dev
) || IS_I865G(dev
))
5486 i845_update_cursor(crtc
, base
);
5488 i9xx_update_cursor(crtc
, base
);
5492 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5493 struct drm_file
*file
,
5495 uint32_t width
, uint32_t height
)
5497 struct drm_device
*dev
= crtc
->dev
;
5498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5499 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5500 struct drm_i915_gem_object
*obj
;
5504 /* if we want to turn off the cursor ignore width and height */
5506 DRM_DEBUG_KMS("cursor off\n");
5509 mutex_lock(&dev
->struct_mutex
);
5513 /* Currently we only support 64x64 cursors */
5514 if (width
!= 64 || height
!= 64) {
5515 DRM_ERROR("we currently only support 64x64 cursors\n");
5519 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5520 if (&obj
->base
== NULL
)
5523 if (obj
->base
.size
< width
* height
* 4) {
5524 DRM_ERROR("buffer is to small\n");
5529 /* we only need to pin inside GTT if cursor is non-phy */
5530 mutex_lock(&dev
->struct_mutex
);
5531 if (!dev_priv
->info
->cursor_needs_physical
) {
5532 if (obj
->tiling_mode
) {
5533 DRM_ERROR("cursor cannot be tiled\n");
5538 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
5540 DRM_ERROR("failed to move cursor bo into the GTT\n");
5544 ret
= i915_gem_object_put_fence(obj
);
5546 DRM_ERROR("failed to release fence for cursor");
5550 addr
= obj
->gtt_offset
;
5552 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5553 ret
= i915_gem_attach_phys_object(dev
, obj
,
5554 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5557 DRM_ERROR("failed to attach phys object\n");
5560 addr
= obj
->phys_obj
->handle
->busaddr
;
5564 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5567 if (intel_crtc
->cursor_bo
) {
5568 if (dev_priv
->info
->cursor_needs_physical
) {
5569 if (intel_crtc
->cursor_bo
!= obj
)
5570 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5572 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5573 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5576 mutex_unlock(&dev
->struct_mutex
);
5578 intel_crtc
->cursor_addr
= addr
;
5579 intel_crtc
->cursor_bo
= obj
;
5580 intel_crtc
->cursor_width
= width
;
5581 intel_crtc
->cursor_height
= height
;
5583 intel_crtc_update_cursor(crtc
, true);
5587 i915_gem_object_unpin(obj
);
5589 mutex_unlock(&dev
->struct_mutex
);
5591 drm_gem_object_unreference_unlocked(&obj
->base
);
5595 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5597 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5599 intel_crtc
->cursor_x
= x
;
5600 intel_crtc
->cursor_y
= y
;
5602 intel_crtc_update_cursor(crtc
, true);
5607 /** Sets the color ramps on behalf of RandR */
5608 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5609 u16 blue
, int regno
)
5611 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5613 intel_crtc
->lut_r
[regno
] = red
>> 8;
5614 intel_crtc
->lut_g
[regno
] = green
>> 8;
5615 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5618 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5619 u16
*blue
, int regno
)
5621 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5623 *red
= intel_crtc
->lut_r
[regno
] << 8;
5624 *green
= intel_crtc
->lut_g
[regno
] << 8;
5625 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5628 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5629 u16
*blue
, uint32_t start
, uint32_t size
)
5631 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5632 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5634 for (i
= start
; i
< end
; i
++) {
5635 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5636 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5637 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5640 intel_crtc_load_lut(crtc
);
5644 * Get a pipe with a simple mode set on it for doing load-based monitor
5647 * It will be up to the load-detect code to adjust the pipe as appropriate for
5648 * its requirements. The pipe will be connected to no other encoders.
5650 * Currently this code will only succeed if there is a pipe with no encoders
5651 * configured for it. In the future, it could choose to temporarily disable
5652 * some outputs to free up a pipe for its use.
5654 * \return crtc, or NULL if no pipes are available.
5657 /* VESA 640x480x72Hz mode to set on the pipe */
5658 static struct drm_display_mode load_detect_mode
= {
5659 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5660 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5663 static struct drm_framebuffer
*
5664 intel_framebuffer_create(struct drm_device
*dev
,
5665 struct drm_mode_fb_cmd2
*mode_cmd
,
5666 struct drm_i915_gem_object
*obj
)
5668 struct intel_framebuffer
*intel_fb
;
5671 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5673 drm_gem_object_unreference_unlocked(&obj
->base
);
5674 return ERR_PTR(-ENOMEM
);
5677 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
5679 drm_gem_object_unreference_unlocked(&obj
->base
);
5681 return ERR_PTR(ret
);
5684 return &intel_fb
->base
;
5688 intel_framebuffer_pitch_for_width(int width
, int bpp
)
5690 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
5691 return ALIGN(pitch
, 64);
5695 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
5697 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
5698 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
5701 static struct drm_framebuffer
*
5702 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
5703 struct drm_display_mode
*mode
,
5706 struct drm_i915_gem_object
*obj
;
5707 struct drm_mode_fb_cmd2 mode_cmd
;
5709 obj
= i915_gem_alloc_object(dev
,
5710 intel_framebuffer_size_for_mode(mode
, bpp
));
5712 return ERR_PTR(-ENOMEM
);
5714 mode_cmd
.width
= mode
->hdisplay
;
5715 mode_cmd
.height
= mode
->vdisplay
;
5716 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
5718 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
5720 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
5723 static struct drm_framebuffer
*
5724 mode_fits_in_fbdev(struct drm_device
*dev
,
5725 struct drm_display_mode
*mode
)
5727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5728 struct drm_i915_gem_object
*obj
;
5729 struct drm_framebuffer
*fb
;
5731 if (dev_priv
->fbdev
== NULL
)
5734 obj
= dev_priv
->fbdev
->ifb
.obj
;
5738 fb
= &dev_priv
->fbdev
->ifb
.base
;
5739 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
5740 fb
->bits_per_pixel
))
5743 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
5749 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
5750 struct drm_display_mode
*mode
,
5751 struct intel_load_detect_pipe
*old
)
5753 struct intel_crtc
*intel_crtc
;
5754 struct intel_encoder
*intel_encoder
=
5755 intel_attached_encoder(connector
);
5756 struct drm_crtc
*possible_crtc
;
5757 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5758 struct drm_crtc
*crtc
= NULL
;
5759 struct drm_device
*dev
= encoder
->dev
;
5760 struct drm_framebuffer
*fb
;
5763 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5764 connector
->base
.id
, drm_get_connector_name(connector
),
5765 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5768 * Algorithm gets a little messy:
5770 * - if the connector already has an assigned crtc, use it (but make
5771 * sure it's on first)
5773 * - try to find the first unused crtc that can drive this connector,
5774 * and use that if we find one
5777 /* See if we already have a CRTC for this connector */
5778 if (encoder
->crtc
) {
5779 crtc
= encoder
->crtc
;
5781 old
->dpms_mode
= connector
->dpms
;
5782 old
->load_detect_temp
= false;
5784 /* Make sure the crtc and connector are running */
5785 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
5786 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
5791 /* Find an unused one (if possible) */
5792 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5794 if (!(encoder
->possible_crtcs
& (1 << i
)))
5796 if (!possible_crtc
->enabled
) {
5797 crtc
= possible_crtc
;
5803 * If we didn't find an unused CRTC, don't use any.
5806 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5810 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
5811 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
5813 intel_crtc
= to_intel_crtc(crtc
);
5814 old
->dpms_mode
= connector
->dpms
;
5815 old
->load_detect_temp
= true;
5816 old
->release_fb
= NULL
;
5819 mode
= &load_detect_mode
;
5821 /* We need a framebuffer large enough to accommodate all accesses
5822 * that the plane may generate whilst we perform load detection.
5823 * We can not rely on the fbcon either being present (we get called
5824 * during its initialisation to detect all boot displays, or it may
5825 * not even exist) or that it is large enough to satisfy the
5828 fb
= mode_fits_in_fbdev(dev
, mode
);
5830 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5831 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
5832 old
->release_fb
= fb
;
5834 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5836 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5840 if (!intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
5841 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5842 if (old
->release_fb
)
5843 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5847 /* let the connector get through one full cycle before testing */
5848 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5852 connector
->encoder
= NULL
;
5853 encoder
->crtc
= NULL
;
5857 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
5858 struct intel_load_detect_pipe
*old
)
5860 struct intel_encoder
*intel_encoder
=
5861 intel_attached_encoder(connector
);
5862 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5865 connector
->base
.id
, drm_get_connector_name(connector
),
5866 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5868 if (old
->load_detect_temp
) {
5869 struct drm_crtc
*crtc
= encoder
->crtc
;
5871 to_intel_connector(connector
)->new_encoder
= NULL
;
5872 intel_encoder
->new_crtc
= NULL
;
5873 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
5875 if (old
->release_fb
)
5876 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5881 /* Switch crtc and encoder back off if necessary */
5882 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
5883 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
5886 /* Returns the clock of the currently programmed mode of the given pipe. */
5887 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5891 int pipe
= intel_crtc
->pipe
;
5892 u32 dpll
= I915_READ(DPLL(pipe
));
5894 intel_clock_t clock
;
5896 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5897 fp
= I915_READ(FP0(pipe
));
5899 fp
= I915_READ(FP1(pipe
));
5901 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5902 if (IS_PINEVIEW(dev
)) {
5903 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5904 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5906 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5907 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5910 if (!IS_GEN2(dev
)) {
5911 if (IS_PINEVIEW(dev
))
5912 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5913 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5915 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5916 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5918 switch (dpll
& DPLL_MODE_MASK
) {
5919 case DPLLB_MODE_DAC_SERIAL
:
5920 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5923 case DPLLB_MODE_LVDS
:
5924 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5928 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5929 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5933 /* XXX: Handle the 100Mhz refclk */
5934 intel_clock(dev
, 96000, &clock
);
5936 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5939 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5940 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5943 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5944 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5945 /* XXX: might not be 66MHz */
5946 intel_clock(dev
, 66000, &clock
);
5948 intel_clock(dev
, 48000, &clock
);
5950 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5953 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5954 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5956 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5961 intel_clock(dev
, 48000, &clock
);
5965 /* XXX: It would be nice to validate the clocks, but we can't reuse
5966 * i830PllIsValid() because it relies on the xf86_config connector
5967 * configuration being accurate, which it isn't necessarily.
5973 /** Returns the currently programmed mode of the given pipe. */
5974 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5975 struct drm_crtc
*crtc
)
5977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5978 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5979 int pipe
= intel_crtc
->pipe
;
5980 struct drm_display_mode
*mode
;
5981 int htot
= I915_READ(HTOTAL(pipe
));
5982 int hsync
= I915_READ(HSYNC(pipe
));
5983 int vtot
= I915_READ(VTOTAL(pipe
));
5984 int vsync
= I915_READ(VSYNC(pipe
));
5986 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5990 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5991 mode
->hdisplay
= (htot
& 0xffff) + 1;
5992 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5993 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5994 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5995 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5996 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5997 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5998 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6000 drm_mode_set_name(mode
);
6005 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6007 struct drm_device
*dev
= crtc
->dev
;
6008 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6009 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6010 int pipe
= intel_crtc
->pipe
;
6011 int dpll_reg
= DPLL(pipe
);
6014 if (HAS_PCH_SPLIT(dev
))
6017 if (!dev_priv
->lvds_downclock_avail
)
6020 dpll
= I915_READ(dpll_reg
);
6021 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6022 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6024 assert_panel_unlocked(dev_priv
, pipe
);
6026 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6027 I915_WRITE(dpll_reg
, dpll
);
6028 intel_wait_for_vblank(dev
, pipe
);
6030 dpll
= I915_READ(dpll_reg
);
6031 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6032 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6036 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6038 struct drm_device
*dev
= crtc
->dev
;
6039 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6040 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6042 if (HAS_PCH_SPLIT(dev
))
6045 if (!dev_priv
->lvds_downclock_avail
)
6049 * Since this is called by a timer, we should never get here in
6052 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6053 int pipe
= intel_crtc
->pipe
;
6054 int dpll_reg
= DPLL(pipe
);
6057 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6059 assert_panel_unlocked(dev_priv
, pipe
);
6061 dpll
= I915_READ(dpll_reg
);
6062 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6063 I915_WRITE(dpll_reg
, dpll
);
6064 intel_wait_for_vblank(dev
, pipe
);
6065 dpll
= I915_READ(dpll_reg
);
6066 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6067 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6072 void intel_mark_busy(struct drm_device
*dev
)
6074 i915_update_gfx_val(dev
->dev_private
);
6077 void intel_mark_idle(struct drm_device
*dev
)
6081 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6083 struct drm_device
*dev
= obj
->base
.dev
;
6084 struct drm_crtc
*crtc
;
6086 if (!i915_powersave
)
6089 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6093 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6094 intel_increase_pllclock(crtc
);
6098 void intel_mark_fb_idle(struct drm_i915_gem_object
*obj
)
6100 struct drm_device
*dev
= obj
->base
.dev
;
6101 struct drm_crtc
*crtc
;
6103 if (!i915_powersave
)
6106 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6110 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6111 intel_decrease_pllclock(crtc
);
6115 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6117 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6118 struct drm_device
*dev
= crtc
->dev
;
6119 struct intel_unpin_work
*work
;
6120 unsigned long flags
;
6122 spin_lock_irqsave(&dev
->event_lock
, flags
);
6123 work
= intel_crtc
->unpin_work
;
6124 intel_crtc
->unpin_work
= NULL
;
6125 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6128 cancel_work_sync(&work
->work
);
6132 drm_crtc_cleanup(crtc
);
6137 static void intel_unpin_work_fn(struct work_struct
*__work
)
6139 struct intel_unpin_work
*work
=
6140 container_of(__work
, struct intel_unpin_work
, work
);
6142 mutex_lock(&work
->dev
->struct_mutex
);
6143 intel_unpin_fb_obj(work
->old_fb_obj
);
6144 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6145 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6147 intel_update_fbc(work
->dev
);
6148 mutex_unlock(&work
->dev
->struct_mutex
);
6152 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6153 struct drm_crtc
*crtc
)
6155 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6157 struct intel_unpin_work
*work
;
6158 struct drm_i915_gem_object
*obj
;
6159 struct drm_pending_vblank_event
*e
;
6160 struct timeval tnow
, tvbl
;
6161 unsigned long flags
;
6163 /* Ignore early vblank irqs */
6164 if (intel_crtc
== NULL
)
6167 do_gettimeofday(&tnow
);
6169 spin_lock_irqsave(&dev
->event_lock
, flags
);
6170 work
= intel_crtc
->unpin_work
;
6171 if (work
== NULL
|| !work
->pending
) {
6172 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6176 intel_crtc
->unpin_work
= NULL
;
6180 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6182 /* Called before vblank count and timestamps have
6183 * been updated for the vblank interval of flip
6184 * completion? Need to increment vblank count and
6185 * add one videorefresh duration to returned timestamp
6186 * to account for this. We assume this happened if we
6187 * get called over 0.9 frame durations after the last
6188 * timestamped vblank.
6190 * This calculation can not be used with vrefresh rates
6191 * below 5Hz (10Hz to be on the safe side) without
6192 * promoting to 64 integers.
6194 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
6195 9 * crtc
->framedur_ns
) {
6196 e
->event
.sequence
++;
6197 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
6201 e
->event
.tv_sec
= tvbl
.tv_sec
;
6202 e
->event
.tv_usec
= tvbl
.tv_usec
;
6204 list_add_tail(&e
->base
.link
,
6205 &e
->base
.file_priv
->event_list
);
6206 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6209 drm_vblank_put(dev
, intel_crtc
->pipe
);
6211 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6213 obj
= work
->old_fb_obj
;
6215 atomic_clear_mask(1 << intel_crtc
->plane
,
6216 &obj
->pending_flip
.counter
);
6217 if (atomic_read(&obj
->pending_flip
) == 0)
6218 wake_up(&dev_priv
->pending_flip_queue
);
6220 schedule_work(&work
->work
);
6222 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6225 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6227 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6228 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6230 do_intel_finish_page_flip(dev
, crtc
);
6233 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6235 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6236 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6238 do_intel_finish_page_flip(dev
, crtc
);
6241 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6243 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6244 struct intel_crtc
*intel_crtc
=
6245 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6246 unsigned long flags
;
6248 spin_lock_irqsave(&dev
->event_lock
, flags
);
6249 if (intel_crtc
->unpin_work
) {
6250 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6251 DRM_ERROR("Prepared flip multiple times\n");
6253 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6255 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6258 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6259 struct drm_crtc
*crtc
,
6260 struct drm_framebuffer
*fb
,
6261 struct drm_i915_gem_object
*obj
)
6263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6266 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6269 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6273 ret
= intel_ring_begin(ring
, 6);
6277 /* Can't queue multiple flips, so wait for the previous
6278 * one to finish before executing the next.
6280 if (intel_crtc
->plane
)
6281 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6283 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6284 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6285 intel_ring_emit(ring
, MI_NOOP
);
6286 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6287 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6288 intel_ring_emit(ring
, fb
->pitches
[0]);
6289 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6290 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6291 intel_ring_advance(ring
);
6295 intel_unpin_fb_obj(obj
);
6300 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6301 struct drm_crtc
*crtc
,
6302 struct drm_framebuffer
*fb
,
6303 struct drm_i915_gem_object
*obj
)
6305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6306 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6308 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6311 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6315 ret
= intel_ring_begin(ring
, 6);
6319 if (intel_crtc
->plane
)
6320 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6322 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6323 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6324 intel_ring_emit(ring
, MI_NOOP
);
6325 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6326 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6327 intel_ring_emit(ring
, fb
->pitches
[0]);
6328 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6329 intel_ring_emit(ring
, MI_NOOP
);
6331 intel_ring_advance(ring
);
6335 intel_unpin_fb_obj(obj
);
6340 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6341 struct drm_crtc
*crtc
,
6342 struct drm_framebuffer
*fb
,
6343 struct drm_i915_gem_object
*obj
)
6345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6346 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6347 uint32_t pf
, pipesrc
;
6348 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6351 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6355 ret
= intel_ring_begin(ring
, 4);
6359 /* i965+ uses the linear or tiled offsets from the
6360 * Display Registers (which do not change across a page-flip)
6361 * so we need only reprogram the base address.
6363 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6364 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6365 intel_ring_emit(ring
, fb
->pitches
[0]);
6366 intel_ring_emit(ring
,
6367 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
6370 /* XXX Enabling the panel-fitter across page-flip is so far
6371 * untested on non-native modes, so ignore it for now.
6372 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6375 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6376 intel_ring_emit(ring
, pf
| pipesrc
);
6377 intel_ring_advance(ring
);
6381 intel_unpin_fb_obj(obj
);
6386 static int intel_gen6_queue_flip(struct drm_device
*dev
,
6387 struct drm_crtc
*crtc
,
6388 struct drm_framebuffer
*fb
,
6389 struct drm_i915_gem_object
*obj
)
6391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6392 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6393 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6394 uint32_t pf
, pipesrc
;
6397 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6401 ret
= intel_ring_begin(ring
, 4);
6405 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6406 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6407 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
6408 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6410 /* Contrary to the suggestions in the documentation,
6411 * "Enable Panel Fitter" does not seem to be required when page
6412 * flipping with a non-native mode, and worse causes a normal
6414 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6417 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6418 intel_ring_emit(ring
, pf
| pipesrc
);
6419 intel_ring_advance(ring
);
6423 intel_unpin_fb_obj(obj
);
6429 * On gen7 we currently use the blit ring because (in early silicon at least)
6430 * the render ring doesn't give us interrpts for page flip completion, which
6431 * means clients will hang after the first flip is queued. Fortunately the
6432 * blit ring generates interrupts properly, so use it instead.
6434 static int intel_gen7_queue_flip(struct drm_device
*dev
,
6435 struct drm_crtc
*crtc
,
6436 struct drm_framebuffer
*fb
,
6437 struct drm_i915_gem_object
*obj
)
6439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6440 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6441 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
6442 uint32_t plane_bit
= 0;
6445 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6449 switch(intel_crtc
->plane
) {
6451 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
6454 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
6457 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
6460 WARN_ONCE(1, "unknown plane in flip command\n");
6465 ret
= intel_ring_begin(ring
, 4);
6469 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
6470 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
6471 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6472 intel_ring_emit(ring
, (MI_NOOP
));
6473 intel_ring_advance(ring
);
6477 intel_unpin_fb_obj(obj
);
6482 static int intel_default_queue_flip(struct drm_device
*dev
,
6483 struct drm_crtc
*crtc
,
6484 struct drm_framebuffer
*fb
,
6485 struct drm_i915_gem_object
*obj
)
6490 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6491 struct drm_framebuffer
*fb
,
6492 struct drm_pending_vblank_event
*event
)
6494 struct drm_device
*dev
= crtc
->dev
;
6495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6496 struct intel_framebuffer
*intel_fb
;
6497 struct drm_i915_gem_object
*obj
;
6498 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6499 struct intel_unpin_work
*work
;
6500 unsigned long flags
;
6503 /* Can't change pixel format via MI display flips. */
6504 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
6508 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6509 * Note that pitch changes could also affect these register.
6511 if (INTEL_INFO(dev
)->gen
> 3 &&
6512 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
6513 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
6516 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6520 work
->event
= event
;
6521 work
->dev
= crtc
->dev
;
6522 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6523 work
->old_fb_obj
= intel_fb
->obj
;
6524 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6526 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6530 /* We borrow the event spin lock for protecting unpin_work */
6531 spin_lock_irqsave(&dev
->event_lock
, flags
);
6532 if (intel_crtc
->unpin_work
) {
6533 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6535 drm_vblank_put(dev
, intel_crtc
->pipe
);
6537 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6540 intel_crtc
->unpin_work
= work
;
6541 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6543 intel_fb
= to_intel_framebuffer(fb
);
6544 obj
= intel_fb
->obj
;
6546 ret
= i915_mutex_lock_interruptible(dev
);
6550 /* Reference the objects for the scheduled work. */
6551 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6552 drm_gem_object_reference(&obj
->base
);
6556 work
->pending_flip_obj
= obj
;
6558 work
->enable_stall_check
= true;
6560 /* Block clients from rendering to the new back buffer until
6561 * the flip occurs and the object is no longer visible.
6563 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6565 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
6567 goto cleanup_pending
;
6569 intel_disable_fbc(dev
);
6570 intel_mark_fb_busy(obj
);
6571 mutex_unlock(&dev
->struct_mutex
);
6573 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6578 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6579 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6580 drm_gem_object_unreference(&obj
->base
);
6581 mutex_unlock(&dev
->struct_mutex
);
6584 spin_lock_irqsave(&dev
->event_lock
, flags
);
6585 intel_crtc
->unpin_work
= NULL
;
6586 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6588 drm_vblank_put(dev
, intel_crtc
->pipe
);
6595 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6596 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6597 .load_lut
= intel_crtc_load_lut
,
6598 .disable
= intel_crtc_noop
,
6601 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
6603 struct intel_encoder
*other_encoder
;
6604 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
6609 list_for_each_entry(other_encoder
,
6610 &crtc
->dev
->mode_config
.encoder_list
,
6613 if (&other_encoder
->new_crtc
->base
!= crtc
||
6614 encoder
== other_encoder
)
6623 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
6624 struct drm_crtc
*crtc
)
6626 struct drm_device
*dev
;
6627 struct drm_crtc
*tmp
;
6630 WARN(!crtc
, "checking null crtc?\n");
6634 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
6640 if (encoder
->possible_crtcs
& crtc_mask
)
6646 * intel_modeset_update_staged_output_state
6648 * Updates the staged output configuration state, e.g. after we've read out the
6651 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
6653 struct intel_encoder
*encoder
;
6654 struct intel_connector
*connector
;
6656 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6658 connector
->new_encoder
=
6659 to_intel_encoder(connector
->base
.encoder
);
6662 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6665 to_intel_crtc(encoder
->base
.crtc
);
6670 * intel_modeset_commit_output_state
6672 * This function copies the stage display pipe configuration to the real one.
6674 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
6676 struct intel_encoder
*encoder
;
6677 struct intel_connector
*connector
;
6679 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6681 connector
->base
.encoder
= &connector
->new_encoder
->base
;
6684 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6686 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
6690 static struct drm_display_mode
*
6691 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
6692 struct drm_display_mode
*mode
)
6694 struct drm_device
*dev
= crtc
->dev
;
6695 struct drm_display_mode
*adjusted_mode
;
6696 struct drm_encoder_helper_funcs
*encoder_funcs
;
6697 struct intel_encoder
*encoder
;
6699 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
6701 return ERR_PTR(-ENOMEM
);
6703 /* Pass our mode to the connectors and the CRTC to give them a chance to
6704 * adjust it according to limitations or connector properties, and also
6705 * a chance to reject the mode entirely.
6707 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6710 if (&encoder
->new_crtc
->base
!= crtc
)
6712 encoder_funcs
= encoder
->base
.helper_private
;
6713 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
6715 DRM_DEBUG_KMS("Encoder fixup failed\n");
6720 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
6721 DRM_DEBUG_KMS("CRTC fixup failed\n");
6724 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
6726 return adjusted_mode
;
6728 drm_mode_destroy(dev
, adjusted_mode
);
6729 return ERR_PTR(-EINVAL
);
6732 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6733 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6735 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
6736 unsigned *prepare_pipes
, unsigned *disable_pipes
)
6738 struct intel_crtc
*intel_crtc
;
6739 struct drm_device
*dev
= crtc
->dev
;
6740 struct intel_encoder
*encoder
;
6741 struct intel_connector
*connector
;
6742 struct drm_crtc
*tmp_crtc
;
6744 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
6746 /* Check which crtcs have changed outputs connected to them, these need
6747 * to be part of the prepare_pipes mask. We don't (yet) support global
6748 * modeset across multiple crtcs, so modeset_pipes will only have one
6749 * bit set at most. */
6750 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6752 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
6755 if (connector
->base
.encoder
) {
6756 tmp_crtc
= connector
->base
.encoder
->crtc
;
6758 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
6761 if (connector
->new_encoder
)
6763 1 << connector
->new_encoder
->new_crtc
->pipe
;
6766 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6768 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
6771 if (encoder
->base
.crtc
) {
6772 tmp_crtc
= encoder
->base
.crtc
;
6774 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
6777 if (encoder
->new_crtc
)
6778 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
6781 /* Check for any pipes that will be fully disabled ... */
6782 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
6786 /* Don't try to disable disabled crtcs. */
6787 if (!intel_crtc
->base
.enabled
)
6790 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6792 if (encoder
->new_crtc
== intel_crtc
)
6797 *disable_pipes
|= 1 << intel_crtc
->pipe
;
6801 /* set_mode is also used to update properties on life display pipes. */
6802 intel_crtc
= to_intel_crtc(crtc
);
6804 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
6806 /* We only support modeset on one single crtc, hence we need to do that
6807 * only for the passed in crtc iff we change anything else than just
6810 * This is actually not true, to be fully compatible with the old crtc
6811 * helper we automatically disable _any_ output (i.e. doesn't need to be
6812 * connected to the crtc we're modesetting on) if it's disconnected.
6813 * Which is a rather nutty api (since changed the output configuration
6814 * without userspace's explicit request can lead to confusion), but
6815 * alas. Hence we currently need to modeset on all pipes we prepare. */
6817 *modeset_pipes
= *prepare_pipes
;
6819 /* ... and mask these out. */
6820 *modeset_pipes
&= ~(*disable_pipes
);
6821 *prepare_pipes
&= ~(*disable_pipes
);
6824 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
6826 struct drm_encoder
*encoder
;
6827 struct drm_device
*dev
= crtc
->dev
;
6829 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
6830 if (encoder
->crtc
== crtc
)
6837 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
6839 struct intel_encoder
*intel_encoder
;
6840 struct intel_crtc
*intel_crtc
;
6841 struct drm_connector
*connector
;
6843 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
6845 if (!intel_encoder
->base
.crtc
)
6848 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
6850 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
6851 intel_encoder
->connectors_active
= false;
6854 intel_modeset_commit_output_state(dev
);
6856 /* Update computed state. */
6857 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
6859 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
6862 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6863 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6866 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
6868 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
6869 connector
->dpms
= DRM_MODE_DPMS_ON
;
6871 intel_encoder
= to_intel_encoder(connector
->encoder
);
6872 intel_encoder
->connectors_active
= true;
6878 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6879 list_for_each_entry((intel_crtc), \
6880 &(dev)->mode_config.crtc_list, \
6882 if (mask & (1 <<(intel_crtc)->pipe)) \
6885 intel_modeset_check_state(struct drm_device
*dev
)
6887 struct intel_crtc
*crtc
;
6888 struct intel_encoder
*encoder
;
6889 struct intel_connector
*connector
;
6891 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6893 /* This also checks the encoder/connector hw state with the
6894 * ->get_hw_state callbacks. */
6895 intel_connector_check_state(connector
);
6897 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
6898 "connector's staged encoder doesn't match current encoder\n");
6901 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6903 bool enabled
= false;
6904 bool active
= false;
6905 enum pipe pipe
, tracked_pipe
;
6907 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6908 encoder
->base
.base
.id
,
6909 drm_get_encoder_name(&encoder
->base
));
6911 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
6912 "encoder's stage crtc doesn't match current crtc\n");
6913 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
6914 "encoder's active_connectors set, but no crtc\n");
6916 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6918 if (connector
->base
.encoder
!= &encoder
->base
)
6921 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
6924 WARN(!!encoder
->base
.crtc
!= enabled
,
6925 "encoder's enabled state mismatch "
6926 "(expected %i, found %i)\n",
6927 !!encoder
->base
.crtc
, enabled
);
6928 WARN(active
&& !encoder
->base
.crtc
,
6929 "active encoder with no crtc\n");
6931 WARN(encoder
->connectors_active
!= active
,
6932 "encoder's computed active state doesn't match tracked active state "
6933 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
6935 active
= encoder
->get_hw_state(encoder
, &pipe
);
6936 WARN(active
!= encoder
->connectors_active
,
6937 "encoder's hw state doesn't match sw tracking "
6938 "(expected %i, found %i)\n",
6939 encoder
->connectors_active
, active
);
6941 if (!encoder
->base
.crtc
)
6944 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
6945 WARN(active
&& pipe
!= tracked_pipe
,
6946 "active encoder's pipe doesn't match"
6947 "(expected %i, found %i)\n",
6948 tracked_pipe
, pipe
);
6952 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
6954 bool enabled
= false;
6955 bool active
= false;
6957 DRM_DEBUG_KMS("[CRTC:%d]\n",
6958 crtc
->base
.base
.id
);
6960 WARN(crtc
->active
&& !crtc
->base
.enabled
,
6961 "active crtc, but not enabled in sw tracking\n");
6963 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6965 if (encoder
->base
.crtc
!= &crtc
->base
)
6968 if (encoder
->connectors_active
)
6971 WARN(active
!= crtc
->active
,
6972 "crtc's computed active state doesn't match tracked active state "
6973 "(expected %i, found %i)\n", active
, crtc
->active
);
6974 WARN(enabled
!= crtc
->base
.enabled
,
6975 "crtc's computed enabled state doesn't match tracked enabled state "
6976 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
6978 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
6982 bool intel_set_mode(struct drm_crtc
*crtc
,
6983 struct drm_display_mode
*mode
,
6984 int x
, int y
, struct drm_framebuffer
*fb
)
6986 struct drm_device
*dev
= crtc
->dev
;
6987 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6988 struct drm_display_mode
*adjusted_mode
, saved_mode
, saved_hwmode
;
6989 struct drm_encoder_helper_funcs
*encoder_funcs
;
6990 struct drm_encoder
*encoder
;
6991 struct intel_crtc
*intel_crtc
;
6992 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
6995 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
6996 &prepare_pipes
, &disable_pipes
);
6998 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
6999 modeset_pipes
, prepare_pipes
, disable_pipes
);
7001 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7002 intel_crtc_disable(&intel_crtc
->base
);
7004 saved_hwmode
= crtc
->hwmode
;
7005 saved_mode
= crtc
->mode
;
7007 /* Hack: Because we don't (yet) support global modeset on multiple
7008 * crtcs, we don't keep track of the new mode for more than one crtc.
7009 * Hence simply check whether any bit is set in modeset_pipes in all the
7010 * pieces of code that are not yet converted to deal with mutliple crtcs
7011 * changing their mode at the same time. */
7012 adjusted_mode
= NULL
;
7013 if (modeset_pipes
) {
7014 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7015 if (IS_ERR(adjusted_mode
)) {
7020 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7021 if (intel_crtc
->base
.enabled
)
7022 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7025 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7026 * to set it here already despite that we pass it down the callchain.
7031 /* Only after disabling all output pipelines that will be changed can we
7032 * update the the output configuration. */
7033 intel_modeset_update_state(dev
, prepare_pipes
);
7035 /* Set up the DPLL and any encoders state that needs to adjust or depend
7038 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7039 ret
= !intel_crtc_mode_set(&intel_crtc
->base
,
7040 mode
, adjusted_mode
,
7045 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7047 if (encoder
->crtc
!= &intel_crtc
->base
)
7050 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7051 encoder
->base
.id
, drm_get_encoder_name(encoder
),
7052 mode
->base
.id
, mode
->name
);
7053 encoder_funcs
= encoder
->helper_private
;
7054 encoder_funcs
->mode_set(encoder
, mode
, adjusted_mode
);
7058 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7059 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7060 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7062 if (modeset_pipes
) {
7063 /* Store real post-adjustment hardware mode. */
7064 crtc
->hwmode
= *adjusted_mode
;
7066 /* Calculate and store various constants which
7067 * are later needed by vblank and swap-completion
7068 * timestamping. They are derived from true hwmode.
7070 drm_calc_timestamping_constants(crtc
);
7073 /* FIXME: add subpixel order */
7075 drm_mode_destroy(dev
, adjusted_mode
);
7076 if (!ret
&& crtc
->enabled
) {
7077 crtc
->hwmode
= saved_hwmode
;
7078 crtc
->mode
= saved_mode
;
7080 intel_modeset_check_state(dev
);
7086 #undef for_each_intel_crtc_masked
7088 static void intel_set_config_free(struct intel_set_config
*config
)
7093 kfree(config
->save_connector_encoders
);
7094 kfree(config
->save_encoder_crtcs
);
7098 static int intel_set_config_save_state(struct drm_device
*dev
,
7099 struct intel_set_config
*config
)
7101 struct drm_encoder
*encoder
;
7102 struct drm_connector
*connector
;
7105 config
->save_encoder_crtcs
=
7106 kcalloc(dev
->mode_config
.num_encoder
,
7107 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7108 if (!config
->save_encoder_crtcs
)
7111 config
->save_connector_encoders
=
7112 kcalloc(dev
->mode_config
.num_connector
,
7113 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7114 if (!config
->save_connector_encoders
)
7117 /* Copy data. Note that driver private data is not affected.
7118 * Should anything bad happen only the expected state is
7119 * restored, not the drivers personal bookkeeping.
7122 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7123 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7127 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7128 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7134 static void intel_set_config_restore_state(struct drm_device
*dev
,
7135 struct intel_set_config
*config
)
7137 struct intel_encoder
*encoder
;
7138 struct intel_connector
*connector
;
7142 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7144 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7148 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7149 connector
->new_encoder
=
7150 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7155 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7156 struct intel_set_config
*config
)
7159 /* We should be able to check here if the fb has the same properties
7160 * and then just flip_or_move it */
7161 if (set
->crtc
->fb
!= set
->fb
) {
7162 /* If we have no fb then treat it as a full mode set */
7163 if (set
->crtc
->fb
== NULL
) {
7164 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7165 config
->mode_changed
= true;
7166 } else if (set
->fb
== NULL
) {
7167 config
->mode_changed
= true;
7168 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7169 config
->mode_changed
= true;
7170 } else if (set
->fb
->bits_per_pixel
!=
7171 set
->crtc
->fb
->bits_per_pixel
) {
7172 config
->mode_changed
= true;
7174 config
->fb_changed
= true;
7177 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7178 config
->fb_changed
= true;
7180 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7181 DRM_DEBUG_KMS("modes are different, full mode set\n");
7182 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7183 drm_mode_debug_printmodeline(set
->mode
);
7184 config
->mode_changed
= true;
7189 intel_modeset_stage_output_state(struct drm_device
*dev
,
7190 struct drm_mode_set
*set
,
7191 struct intel_set_config
*config
)
7193 struct drm_crtc
*new_crtc
;
7194 struct intel_connector
*connector
;
7195 struct intel_encoder
*encoder
;
7198 /* The upper layers ensure that we either disabl a crtc or have a list
7199 * of connectors. For paranoia, double-check this. */
7200 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7201 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
7204 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7206 /* Otherwise traverse passed in connector list and get encoders
7208 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7209 if (set
->connectors
[ro
] == &connector
->base
) {
7210 connector
->new_encoder
= connector
->encoder
;
7215 /* If we disable the crtc, disable all its connectors. Also, if
7216 * the connector is on the changing crtc but not on the new
7217 * connector list, disable it. */
7218 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
7219 connector
->base
.encoder
&&
7220 connector
->base
.encoder
->crtc
== set
->crtc
) {
7221 connector
->new_encoder
= NULL
;
7223 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7224 connector
->base
.base
.id
,
7225 drm_get_connector_name(&connector
->base
));
7229 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
7230 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7231 config
->mode_changed
= true;
7234 /* Disable all disconnected encoders. */
7235 if (connector
->base
.status
== connector_status_disconnected
)
7236 connector
->new_encoder
= NULL
;
7238 /* connector->new_encoder is now updated for all connectors. */
7240 /* Update crtc of enabled connectors. */
7242 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7244 if (!connector
->new_encoder
)
7247 new_crtc
= connector
->new_encoder
->base
.crtc
;
7249 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7250 if (set
->connectors
[ro
] == &connector
->base
)
7251 new_crtc
= set
->crtc
;
7254 /* Make sure the new CRTC will work with the encoder */
7255 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
7259 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
7261 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7262 connector
->base
.base
.id
,
7263 drm_get_connector_name(&connector
->base
),
7267 /* Check for any encoders that needs to be disabled. */
7268 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7270 list_for_each_entry(connector
,
7271 &dev
->mode_config
.connector_list
,
7273 if (connector
->new_encoder
== encoder
) {
7274 WARN_ON(!connector
->new_encoder
->new_crtc
);
7279 encoder
->new_crtc
= NULL
;
7281 /* Only now check for crtc changes so we don't miss encoders
7282 * that will be disabled. */
7283 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
7284 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7285 config
->mode_changed
= true;
7288 /* Now we've also updated encoder->new_crtc for all encoders. */
7293 static int intel_crtc_set_config(struct drm_mode_set
*set
)
7295 struct drm_device
*dev
;
7296 struct drm_mode_set save_set
;
7297 struct intel_set_config
*config
;
7303 BUG_ON(!set
->crtc
->helper_private
);
7308 /* The fb helper likes to play gross jokes with ->mode_set_config.
7309 * Unfortunately the crtc helper doesn't do much at all for this case,
7310 * so we have to cope with this madness until the fb helper is fixed up. */
7311 if (set
->fb
&& set
->num_connectors
== 0)
7315 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7316 set
->crtc
->base
.id
, set
->fb
->base
.id
,
7317 (int)set
->num_connectors
, set
->x
, set
->y
);
7319 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
7322 dev
= set
->crtc
->dev
;
7325 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
7329 ret
= intel_set_config_save_state(dev
, config
);
7333 save_set
.crtc
= set
->crtc
;
7334 save_set
.mode
= &set
->crtc
->mode
;
7335 save_set
.x
= set
->crtc
->x
;
7336 save_set
.y
= set
->crtc
->y
;
7337 save_set
.fb
= set
->crtc
->fb
;
7339 /* Compute whether we need a full modeset, only an fb base update or no
7340 * change at all. In the future we might also check whether only the
7341 * mode changed, e.g. for LVDS where we only change the panel fitter in
7343 intel_set_config_compute_mode_changes(set
, config
);
7345 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
7349 if (config
->mode_changed
) {
7351 DRM_DEBUG_KMS("attempting to set mode from"
7353 drm_mode_debug_printmodeline(set
->mode
);
7356 if (!intel_set_mode(set
->crtc
, set
->mode
,
7357 set
->x
, set
->y
, set
->fb
)) {
7358 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7359 set
->crtc
->base
.id
);
7364 if (set
->crtc
->enabled
) {
7365 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7366 for (i
= 0; i
< set
->num_connectors
; i
++) {
7367 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set
->connectors
[i
]->base
.id
,
7368 drm_get_connector_name(set
->connectors
[i
]));
7369 set
->connectors
[i
]->funcs
->dpms(set
->connectors
[i
], DRM_MODE_DPMS_ON
);
7372 } else if (config
->fb_changed
) {
7373 ret
= intel_pipe_set_base(set
->crtc
,
7374 set
->x
, set
->y
, set
->fb
);
7377 intel_set_config_free(config
);
7382 intel_set_config_restore_state(dev
, config
);
7384 /* Try to restore the config */
7385 if (config
->mode_changed
&&
7386 !intel_set_mode(save_set
.crtc
, save_set
.mode
,
7387 save_set
.x
, save_set
.y
, save_set
.fb
))
7388 DRM_ERROR("failed to restore config after modeset failure\n");
7391 intel_set_config_free(config
);
7395 static const struct drm_crtc_funcs intel_crtc_funcs
= {
7396 .cursor_set
= intel_crtc_cursor_set
,
7397 .cursor_move
= intel_crtc_cursor_move
,
7398 .gamma_set
= intel_crtc_gamma_set
,
7399 .set_config
= intel_crtc_set_config
,
7400 .destroy
= intel_crtc_destroy
,
7401 .page_flip
= intel_crtc_page_flip
,
7404 static void intel_pch_pll_init(struct drm_device
*dev
)
7406 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7409 if (dev_priv
->num_pch_pll
== 0) {
7410 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7414 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
7415 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
7416 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
7417 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
7421 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
7423 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7424 struct intel_crtc
*intel_crtc
;
7427 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
7428 if (intel_crtc
== NULL
)
7431 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
7433 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
7434 for (i
= 0; i
< 256; i
++) {
7435 intel_crtc
->lut_r
[i
] = i
;
7436 intel_crtc
->lut_g
[i
] = i
;
7437 intel_crtc
->lut_b
[i
] = i
;
7440 /* Swap pipes & planes for FBC on pre-965 */
7441 intel_crtc
->pipe
= pipe
;
7442 intel_crtc
->plane
= pipe
;
7443 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
7444 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7445 intel_crtc
->plane
= !pipe
;
7448 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
7449 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
7450 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
7451 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
7453 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
7455 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
7458 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
7459 struct drm_file
*file
)
7461 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
7462 struct drm_mode_object
*drmmode_obj
;
7463 struct intel_crtc
*crtc
;
7465 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
7468 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
7469 DRM_MODE_OBJECT_CRTC
);
7472 DRM_ERROR("no such CRTC id\n");
7476 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
7477 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
7482 static int intel_encoder_clones(struct intel_encoder
*encoder
)
7484 struct drm_device
*dev
= encoder
->base
.dev
;
7485 struct intel_encoder
*source_encoder
;
7489 list_for_each_entry(source_encoder
,
7490 &dev
->mode_config
.encoder_list
, base
.head
) {
7492 if (encoder
== source_encoder
)
7493 index_mask
|= (1 << entry
);
7495 /* Intel hw has only one MUX where enocoders could be cloned. */
7496 if (encoder
->cloneable
&& source_encoder
->cloneable
)
7497 index_mask
|= (1 << entry
);
7505 static bool has_edp_a(struct drm_device
*dev
)
7507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7509 if (!IS_MOBILE(dev
))
7512 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
7516 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
7522 static void intel_setup_outputs(struct drm_device
*dev
)
7524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7525 struct intel_encoder
*encoder
;
7526 bool dpd_is_edp
= false;
7529 has_lvds
= intel_lvds_init(dev
);
7530 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
7531 /* disable the panel fitter on everything but LVDS */
7532 I915_WRITE(PFIT_CONTROL
, 0);
7535 if (HAS_PCH_SPLIT(dev
)) {
7536 dpd_is_edp
= intel_dpd_is_edp(dev
);
7539 intel_dp_init(dev
, DP_A
, PORT_A
);
7541 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
7542 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
7545 intel_crt_init(dev
);
7547 if (IS_HASWELL(dev
)) {
7550 /* Haswell uses DDI functions to detect digital outputs */
7551 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
7552 /* DDI A only supports eDP */
7554 intel_ddi_init(dev
, PORT_A
);
7556 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7558 found
= I915_READ(SFUSE_STRAP
);
7560 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
7561 intel_ddi_init(dev
, PORT_B
);
7562 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
7563 intel_ddi_init(dev
, PORT_C
);
7564 if (found
& SFUSE_STRAP_DDID_DETECTED
)
7565 intel_ddi_init(dev
, PORT_D
);
7566 } else if (HAS_PCH_SPLIT(dev
)) {
7569 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
7570 /* PCH SDVOB multiplex with HDMIB */
7571 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
7573 intel_hdmi_init(dev
, HDMIB
, PORT_B
);
7574 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
7575 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
7578 if (I915_READ(HDMIC
) & PORT_DETECTED
)
7579 intel_hdmi_init(dev
, HDMIC
, PORT_C
);
7581 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
7582 intel_hdmi_init(dev
, HDMID
, PORT_D
);
7584 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
7585 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
7587 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
7588 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
7589 } else if (IS_VALLEYVIEW(dev
)) {
7592 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
7593 /* SDVOB multiplex with HDMIB */
7594 found
= intel_sdvo_init(dev
, SDVOB
, true);
7596 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
7597 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
7598 intel_dp_init(dev
, DP_B
, PORT_B
);
7601 if (I915_READ(SDVOC
) & PORT_DETECTED
)
7602 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
7604 /* Shares lanes with HDMI on SDVOC */
7605 if (I915_READ(DP_C
) & DP_DETECTED
)
7606 intel_dp_init(dev
, DP_C
, PORT_C
);
7607 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
7610 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
7611 DRM_DEBUG_KMS("probing SDVOB\n");
7612 found
= intel_sdvo_init(dev
, SDVOB
, true);
7613 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
7614 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7615 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
7618 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
7619 DRM_DEBUG_KMS("probing DP_B\n");
7620 intel_dp_init(dev
, DP_B
, PORT_B
);
7624 /* Before G4X SDVOC doesn't have its own detect register */
7626 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
7627 DRM_DEBUG_KMS("probing SDVOC\n");
7628 found
= intel_sdvo_init(dev
, SDVOC
, false);
7631 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
7633 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
7634 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7635 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
7637 if (SUPPORTS_INTEGRATED_DP(dev
)) {
7638 DRM_DEBUG_KMS("probing DP_C\n");
7639 intel_dp_init(dev
, DP_C
, PORT_C
);
7643 if (SUPPORTS_INTEGRATED_DP(dev
) &&
7644 (I915_READ(DP_D
) & DP_DETECTED
)) {
7645 DRM_DEBUG_KMS("probing DP_D\n");
7646 intel_dp_init(dev
, DP_D
, PORT_D
);
7648 } else if (IS_GEN2(dev
))
7649 intel_dvo_init(dev
);
7651 if (SUPPORTS_TV(dev
))
7654 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7655 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
7656 encoder
->base
.possible_clones
=
7657 intel_encoder_clones(encoder
);
7660 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7661 ironlake_init_pch_refclk(dev
);
7664 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
7666 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
7668 drm_framebuffer_cleanup(fb
);
7669 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
7674 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
7675 struct drm_file
*file
,
7676 unsigned int *handle
)
7678 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
7679 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
7681 return drm_gem_handle_create(file
, &obj
->base
, handle
);
7684 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
7685 .destroy
= intel_user_framebuffer_destroy
,
7686 .create_handle
= intel_user_framebuffer_create_handle
,
7689 int intel_framebuffer_init(struct drm_device
*dev
,
7690 struct intel_framebuffer
*intel_fb
,
7691 struct drm_mode_fb_cmd2
*mode_cmd
,
7692 struct drm_i915_gem_object
*obj
)
7696 if (obj
->tiling_mode
== I915_TILING_Y
)
7699 if (mode_cmd
->pitches
[0] & 63)
7702 switch (mode_cmd
->pixel_format
) {
7703 case DRM_FORMAT_RGB332
:
7704 case DRM_FORMAT_RGB565
:
7705 case DRM_FORMAT_XRGB8888
:
7706 case DRM_FORMAT_XBGR8888
:
7707 case DRM_FORMAT_ARGB8888
:
7708 case DRM_FORMAT_XRGB2101010
:
7709 case DRM_FORMAT_ARGB2101010
:
7710 /* RGB formats are common across chipsets */
7712 case DRM_FORMAT_YUYV
:
7713 case DRM_FORMAT_UYVY
:
7714 case DRM_FORMAT_YVYU
:
7715 case DRM_FORMAT_VYUY
:
7718 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7719 mode_cmd
->pixel_format
);
7723 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
7725 DRM_ERROR("framebuffer init failed %d\n", ret
);
7729 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
7730 intel_fb
->obj
= obj
;
7734 static struct drm_framebuffer
*
7735 intel_user_framebuffer_create(struct drm_device
*dev
,
7736 struct drm_file
*filp
,
7737 struct drm_mode_fb_cmd2
*mode_cmd
)
7739 struct drm_i915_gem_object
*obj
;
7741 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
7742 mode_cmd
->handles
[0]));
7743 if (&obj
->base
== NULL
)
7744 return ERR_PTR(-ENOENT
);
7746 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
7749 static const struct drm_mode_config_funcs intel_mode_funcs
= {
7750 .fb_create
= intel_user_framebuffer_create
,
7751 .output_poll_changed
= intel_fb_output_poll_changed
,
7754 /* Set up chip specific display functions */
7755 static void intel_init_display(struct drm_device
*dev
)
7757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7759 /* We always want a DPMS function */
7760 if (HAS_PCH_SPLIT(dev
)) {
7761 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
7762 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
7763 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
7764 dev_priv
->display
.off
= ironlake_crtc_off
;
7765 dev_priv
->display
.update_plane
= ironlake_update_plane
;
7767 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
7768 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
7769 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
7770 dev_priv
->display
.off
= i9xx_crtc_off
;
7771 dev_priv
->display
.update_plane
= i9xx_update_plane
;
7774 /* Returns the core display clock speed */
7775 if (IS_VALLEYVIEW(dev
))
7776 dev_priv
->display
.get_display_clock_speed
=
7777 valleyview_get_display_clock_speed
;
7778 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
7779 dev_priv
->display
.get_display_clock_speed
=
7780 i945_get_display_clock_speed
;
7781 else if (IS_I915G(dev
))
7782 dev_priv
->display
.get_display_clock_speed
=
7783 i915_get_display_clock_speed
;
7784 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
7785 dev_priv
->display
.get_display_clock_speed
=
7786 i9xx_misc_get_display_clock_speed
;
7787 else if (IS_I915GM(dev
))
7788 dev_priv
->display
.get_display_clock_speed
=
7789 i915gm_get_display_clock_speed
;
7790 else if (IS_I865G(dev
))
7791 dev_priv
->display
.get_display_clock_speed
=
7792 i865_get_display_clock_speed
;
7793 else if (IS_I85X(dev
))
7794 dev_priv
->display
.get_display_clock_speed
=
7795 i855_get_display_clock_speed
;
7797 dev_priv
->display
.get_display_clock_speed
=
7798 i830_get_display_clock_speed
;
7800 if (HAS_PCH_SPLIT(dev
)) {
7802 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
7803 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7804 } else if (IS_GEN6(dev
)) {
7805 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
7806 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7807 } else if (IS_IVYBRIDGE(dev
)) {
7808 /* FIXME: detect B0+ stepping and use auto training */
7809 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
7810 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7811 } else if (IS_HASWELL(dev
)) {
7812 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
7813 dev_priv
->display
.write_eld
= haswell_write_eld
;
7815 dev_priv
->display
.update_wm
= NULL
;
7816 } else if (IS_G4X(dev
)) {
7817 dev_priv
->display
.write_eld
= g4x_write_eld
;
7820 /* Default just returns -ENODEV to indicate unsupported */
7821 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
7823 switch (INTEL_INFO(dev
)->gen
) {
7825 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
7829 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
7834 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
7838 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
7841 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
7847 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7848 * resume, or other times. This quirk makes sure that's the case for
7851 static void quirk_pipea_force(struct drm_device
*dev
)
7853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7855 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7856 DRM_INFO("applying pipe a force quirk\n");
7860 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7862 static void quirk_ssc_force_disable(struct drm_device
*dev
)
7864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7865 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
7866 DRM_INFO("applying lvds SSC disable quirk\n");
7870 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7873 static void quirk_invert_brightness(struct drm_device
*dev
)
7875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7876 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
7877 DRM_INFO("applying inverted panel brightness quirk\n");
7880 struct intel_quirk
{
7882 int subsystem_vendor
;
7883 int subsystem_device
;
7884 void (*hook
)(struct drm_device
*dev
);
7887 static struct intel_quirk intel_quirks
[] = {
7888 /* HP Mini needs pipe A force quirk (LP: #322104) */
7889 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
7891 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7892 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7894 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7895 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7897 /* 855 & before need to leave pipe A & dpll A up */
7898 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7899 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7900 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7902 /* Lenovo U160 cannot use SSC on LVDS */
7903 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
7905 /* Sony Vaio Y cannot use SSC on LVDS */
7906 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
7908 /* Acer Aspire 5734Z must invert backlight brightness */
7909 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
7912 static void intel_init_quirks(struct drm_device
*dev
)
7914 struct pci_dev
*d
= dev
->pdev
;
7917 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
7918 struct intel_quirk
*q
= &intel_quirks
[i
];
7920 if (d
->device
== q
->device
&&
7921 (d
->subsystem_vendor
== q
->subsystem_vendor
||
7922 q
->subsystem_vendor
== PCI_ANY_ID
) &&
7923 (d
->subsystem_device
== q
->subsystem_device
||
7924 q
->subsystem_device
== PCI_ANY_ID
))
7929 /* Disable the VGA plane that we never use */
7930 static void i915_disable_vga(struct drm_device
*dev
)
7932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7936 if (HAS_PCH_SPLIT(dev
))
7937 vga_reg
= CPU_VGACNTRL
;
7941 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7942 outb(SR01
, VGA_SR_INDEX
);
7943 sr1
= inb(VGA_SR_DATA
);
7944 outb(sr1
| 1<<5, VGA_SR_DATA
);
7945 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7948 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
7949 POSTING_READ(vga_reg
);
7952 void intel_modeset_init_hw(struct drm_device
*dev
)
7954 /* We attempt to init the necessary power wells early in the initialization
7955 * time, so the subsystems that expect power to be enabled can work.
7957 intel_init_power_wells(dev
);
7959 intel_prepare_ddi(dev
);
7961 intel_init_clock_gating(dev
);
7963 mutex_lock(&dev
->struct_mutex
);
7964 intel_enable_gt_powersave(dev
);
7965 mutex_unlock(&dev
->struct_mutex
);
7968 void intel_modeset_init(struct drm_device
*dev
)
7970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7973 drm_mode_config_init(dev
);
7975 dev
->mode_config
.min_width
= 0;
7976 dev
->mode_config
.min_height
= 0;
7978 dev
->mode_config
.preferred_depth
= 24;
7979 dev
->mode_config
.prefer_shadow
= 1;
7981 dev
->mode_config
.funcs
= &intel_mode_funcs
;
7983 intel_init_quirks(dev
);
7987 intel_init_display(dev
);
7990 dev
->mode_config
.max_width
= 2048;
7991 dev
->mode_config
.max_height
= 2048;
7992 } else if (IS_GEN3(dev
)) {
7993 dev
->mode_config
.max_width
= 4096;
7994 dev
->mode_config
.max_height
= 4096;
7996 dev
->mode_config
.max_width
= 8192;
7997 dev
->mode_config
.max_height
= 8192;
7999 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
8001 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8002 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
8004 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
8005 intel_crtc_init(dev
, i
);
8006 ret
= intel_plane_init(dev
, i
);
8008 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8011 intel_pch_pll_init(dev
);
8013 /* Just disable it once at startup */
8014 i915_disable_vga(dev
);
8015 intel_setup_outputs(dev
);
8019 intel_connector_break_all_links(struct intel_connector
*connector
)
8021 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8022 connector
->base
.encoder
= NULL
;
8023 connector
->encoder
->connectors_active
= false;
8024 connector
->encoder
->base
.crtc
= NULL
;
8027 static void intel_enable_pipe_a(struct drm_device
*dev
)
8029 struct intel_connector
*connector
;
8030 struct drm_connector
*crt
= NULL
;
8031 struct intel_load_detect_pipe load_detect_temp
;
8033 /* We can't just switch on the pipe A, we need to set things up with a
8034 * proper mode and output configuration. As a gross hack, enable pipe A
8035 * by enabling the load detect pipe once. */
8036 list_for_each_entry(connector
,
8037 &dev
->mode_config
.connector_list
,
8039 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8040 crt
= &connector
->base
;
8048 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8049 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8054 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8056 struct drm_device
*dev
= crtc
->base
.dev
;
8057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8060 /* Clear any frame start delays used for debugging left by the BIOS */
8061 reg
= PIPECONF(crtc
->pipe
);
8062 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8064 /* We need to sanitize the plane -> pipe mapping first because this will
8065 * disable the crtc (and hence change the state) if it is wrong. */
8066 if (!HAS_PCH_SPLIT(dev
)) {
8067 struct intel_connector
*connector
;
8070 reg
= DSPCNTR(crtc
->plane
);
8071 val
= I915_READ(reg
);
8073 if ((val
& DISPLAY_PLANE_ENABLE
) == 0 &&
8074 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8077 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8078 crtc
->base
.base
.id
);
8080 /* Pipe has the wrong plane attached and the plane is active.
8081 * Temporarily change the plane mapping and disable everything
8083 plane
= crtc
->plane
;
8084 crtc
->plane
= !plane
;
8085 dev_priv
->display
.crtc_disable(&crtc
->base
);
8086 crtc
->plane
= plane
;
8088 /* ... and break all links. */
8089 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8091 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8094 intel_connector_break_all_links(connector
);
8097 WARN_ON(crtc
->active
);
8098 crtc
->base
.enabled
= false;
8102 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8103 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8104 /* BIOS forgot to enable pipe A, this mostly happens after
8105 * resume. Force-enable the pipe to fix this, the update_dpms
8106 * call below we restore the pipe to the right state, but leave
8107 * the required bits on. */
8108 intel_enable_pipe_a(dev
);
8111 /* Adjust the state of the output pipe according to whether we
8112 * have active connectors/encoders. */
8113 intel_crtc_update_dpms(&crtc
->base
);
8115 if (crtc
->active
!= crtc
->base
.enabled
) {
8116 struct intel_encoder
*encoder
;
8118 /* This can happen either due to bugs in the get_hw_state
8119 * functions or because the pipe is force-enabled due to the
8121 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8123 crtc
->base
.enabled
? "enabled" : "disabled",
8124 crtc
->active
? "enabled" : "disabled");
8126 crtc
->base
.enabled
= crtc
->active
;
8128 /* Because we only establish the connector -> encoder ->
8129 * crtc links if something is active, this means the
8130 * crtc is now deactivated. Break the links. connector
8131 * -> encoder links are only establish when things are
8132 * actually up, hence no need to break them. */
8133 WARN_ON(crtc
->active
);
8135 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
8136 WARN_ON(encoder
->connectors_active
);
8137 encoder
->base
.crtc
= NULL
;
8142 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
8144 struct intel_connector
*connector
;
8145 struct drm_device
*dev
= encoder
->base
.dev
;
8147 /* We need to check both for a crtc link (meaning that the
8148 * encoder is active and trying to read from a pipe) and the
8149 * pipe itself being active. */
8150 bool has_active_crtc
= encoder
->base
.crtc
&&
8151 to_intel_crtc(encoder
->base
.crtc
)->active
;
8153 if (encoder
->connectors_active
&& !has_active_crtc
) {
8154 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8155 encoder
->base
.base
.id
,
8156 drm_get_encoder_name(&encoder
->base
));
8158 /* Connector is active, but has no active pipe. This is
8159 * fallout from our resume register restoring. Disable
8160 * the encoder manually again. */
8161 if (encoder
->base
.crtc
) {
8162 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8163 encoder
->base
.base
.id
,
8164 drm_get_encoder_name(&encoder
->base
));
8165 encoder
->disable(encoder
);
8168 /* Inconsistent output/port/pipe state happens presumably due to
8169 * a bug in one of the get_hw_state functions. Or someplace else
8170 * in our code, like the register restore mess on resume. Clamp
8171 * things to off as a safer default. */
8172 list_for_each_entry(connector
,
8173 &dev
->mode_config
.connector_list
,
8175 if (connector
->encoder
!= encoder
)
8178 intel_connector_break_all_links(connector
);
8181 /* Enabled encoders without active connectors will be fixed in
8182 * the crtc fixup. */
8185 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8186 * and i915 state tracking structures. */
8187 void intel_modeset_setup_hw_state(struct drm_device
*dev
)
8189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8192 struct intel_crtc
*crtc
;
8193 struct intel_encoder
*encoder
;
8194 struct intel_connector
*connector
;
8196 for_each_pipe(pipe
) {
8197 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8199 tmp
= I915_READ(PIPECONF(pipe
));
8200 if (tmp
& PIPECONF_ENABLE
)
8201 crtc
->active
= true;
8203 crtc
->active
= false;
8205 crtc
->base
.enabled
= crtc
->active
;
8207 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8209 crtc
->active
? "enabled" : "disabled");
8212 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8216 if (encoder
->get_hw_state(encoder
, &pipe
)) {
8217 encoder
->base
.crtc
=
8218 dev_priv
->pipe_to_crtc_mapping
[pipe
];
8220 encoder
->base
.crtc
= NULL
;
8223 encoder
->connectors_active
= false;
8224 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8225 encoder
->base
.base
.id
,
8226 drm_get_encoder_name(&encoder
->base
),
8227 encoder
->base
.crtc
? "enabled" : "disabled",
8231 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8233 if (connector
->get_hw_state(connector
)) {
8234 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
8235 connector
->encoder
->connectors_active
= true;
8236 connector
->base
.encoder
= &connector
->encoder
->base
;
8238 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8239 connector
->base
.encoder
= NULL
;
8241 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8242 connector
->base
.base
.id
,
8243 drm_get_connector_name(&connector
->base
),
8244 connector
->base
.encoder
? "enabled" : "disabled");
8247 /* HW state is read out, now we need to sanitize this mess. */
8248 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8250 intel_sanitize_encoder(encoder
);
8253 for_each_pipe(pipe
) {
8254 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8255 intel_sanitize_crtc(crtc
);
8258 intel_modeset_update_staged_output_state(dev
);
8260 intel_modeset_check_state(dev
);
8263 void intel_modeset_gem_init(struct drm_device
*dev
)
8265 intel_modeset_init_hw(dev
);
8267 intel_setup_overlay(dev
);
8269 intel_modeset_setup_hw_state(dev
);
8272 void intel_modeset_cleanup(struct drm_device
*dev
)
8274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8275 struct drm_crtc
*crtc
;
8276 struct intel_crtc
*intel_crtc
;
8278 drm_kms_helper_poll_fini(dev
);
8279 mutex_lock(&dev
->struct_mutex
);
8281 intel_unregister_dsm_handler();
8284 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8285 /* Skip inactive CRTCs */
8289 intel_crtc
= to_intel_crtc(crtc
);
8290 intel_increase_pllclock(crtc
);
8293 intel_disable_fbc(dev
);
8295 intel_disable_gt_powersave(dev
);
8297 ironlake_teardown_rc6(dev
);
8299 if (IS_VALLEYVIEW(dev
))
8302 mutex_unlock(&dev
->struct_mutex
);
8304 /* Disable the irq before mode object teardown, for the irq might
8305 * enqueue unpin/hotplug work. */
8306 drm_irq_uninstall(dev
);
8307 cancel_work_sync(&dev_priv
->hotplug_work
);
8308 cancel_work_sync(&dev_priv
->rps
.work
);
8310 /* flush any delayed tasks or pending work */
8311 flush_scheduled_work();
8313 drm_mode_config_cleanup(dev
);
8317 * Return which encoder is currently attached for connector.
8319 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
8321 return &intel_attached_encoder(connector
)->base
;
8324 void intel_connector_attach_encoder(struct intel_connector
*connector
,
8325 struct intel_encoder
*encoder
)
8327 connector
->encoder
= encoder
;
8328 drm_mode_connector_attach_encoder(&connector
->base
,
8333 * set vga decode state - true == enable VGA decode
8335 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
8337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8340 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
8342 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
8344 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
8345 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
8349 #ifdef CONFIG_DEBUG_FS
8350 #include <linux/seq_file.h>
8352 struct intel_display_error_state
{
8353 struct intel_cursor_error_state
{
8358 } cursor
[I915_MAX_PIPES
];
8360 struct intel_pipe_error_state
{
8370 } pipe
[I915_MAX_PIPES
];
8372 struct intel_plane_error_state
{
8380 } plane
[I915_MAX_PIPES
];
8383 struct intel_display_error_state
*
8384 intel_display_capture_error_state(struct drm_device
*dev
)
8386 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8387 struct intel_display_error_state
*error
;
8390 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
8395 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
8396 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
8397 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
8399 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
8400 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
8401 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
8402 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
8403 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
8404 if (INTEL_INFO(dev
)->gen
>= 4) {
8405 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
8406 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
8409 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
8410 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
8411 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
8412 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
8413 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
8414 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
8415 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
8416 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
8423 intel_display_print_error_state(struct seq_file
*m
,
8424 struct drm_device
*dev
,
8425 struct intel_display_error_state
*error
)
8427 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8430 seq_printf(m
, "Num Pipes: %d\n", dev_priv
->num_pipe
);
8432 seq_printf(m
, "Pipe [%d]:\n", i
);
8433 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
8434 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
8435 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
8436 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
8437 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
8438 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
8439 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
8440 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
8442 seq_printf(m
, "Plane [%d]:\n", i
);
8443 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
8444 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
8445 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
8446 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
8447 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
8448 if (INTEL_INFO(dev
)->gen
>= 4) {
8449 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
8450 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
8453 seq_printf(m
, "Cursor [%d]:\n", i
);
8454 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
8455 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
8456 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);