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drm/i915: Force clean compilation with -Werror
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg, int ref_freq)
152 {
153 u32 val;
154 int divider;
155
156 mutex_lock(&dev_priv->sb_lock);
157 val = vlv_cck_read(dev_priv, reg);
158 mutex_unlock(&dev_priv->sb_lock);
159
160 divider = val & CCK_FREQUENCY_VALUES;
161
162 WARN((val & CCK_FREQUENCY_STATUS) !=
163 (divider << CCK_FREQUENCY_STATUS_SHIFT),
164 "%s change in progress\n", name);
165
166 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
167 }
168
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170 const char *name, u32 reg)
171 {
172 if (dev_priv->hpll_freq == 0)
173 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
174
175 return vlv_get_cck_clock(dev_priv, name, reg,
176 dev_priv->hpll_freq);
177 }
178
179 static int
180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
181 {
182 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
183 }
184
185 static int
186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
187 {
188 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
189 CCK_DISPLAY_REF_CLOCK_CONTROL);
190 }
191
192 static int
193 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
194 {
195 uint32_t clkcfg;
196
197 /* hrawclock is 1/4 the FSB frequency */
198 clkcfg = I915_READ(CLKCFG);
199 switch (clkcfg & CLKCFG_FSB_MASK) {
200 case CLKCFG_FSB_400:
201 return 100000;
202 case CLKCFG_FSB_533:
203 return 133333;
204 case CLKCFG_FSB_667:
205 return 166667;
206 case CLKCFG_FSB_800:
207 return 200000;
208 case CLKCFG_FSB_1067:
209 return 266667;
210 case CLKCFG_FSB_1333:
211 return 333333;
212 /* these two are just a guess; one of them might be right */
213 case CLKCFG_FSB_1600:
214 case CLKCFG_FSB_1600_ALT:
215 return 400000;
216 default:
217 return 133333;
218 }
219 }
220
221 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
222 {
223 if (HAS_PCH_SPLIT(dev_priv))
224 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
225 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
226 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
227 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
228 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
229 else
230 return; /* no rawclk on other platforms, or no need to know it */
231
232 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
233 }
234
235 static void intel_update_czclk(struct drm_i915_private *dev_priv)
236 {
237 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
238 return;
239
240 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
241 CCK_CZ_CLOCK_CONTROL);
242
243 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
244 }
245
246 static inline u32 /* units of 100MHz */
247 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
248 const struct intel_crtc_state *pipe_config)
249 {
250 if (HAS_DDI(dev_priv))
251 return pipe_config->port_clock; /* SPLL */
252 else if (IS_GEN5(dev_priv))
253 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
254 else
255 return 270000;
256 }
257
258 static const intel_limit_t intel_limits_i8xx_dac = {
259 .dot = { .min = 25000, .max = 350000 },
260 .vco = { .min = 908000, .max = 1512000 },
261 .n = { .min = 2, .max = 16 },
262 .m = { .min = 96, .max = 140 },
263 .m1 = { .min = 18, .max = 26 },
264 .m2 = { .min = 6, .max = 16 },
265 .p = { .min = 4, .max = 128 },
266 .p1 = { .min = 2, .max = 33 },
267 .p2 = { .dot_limit = 165000,
268 .p2_slow = 4, .p2_fast = 2 },
269 };
270
271 static const intel_limit_t intel_limits_i8xx_dvo = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 908000, .max = 1512000 },
274 .n = { .min = 2, .max = 16 },
275 .m = { .min = 96, .max = 140 },
276 .m1 = { .min = 18, .max = 26 },
277 .m2 = { .min = 6, .max = 16 },
278 .p = { .min = 4, .max = 128 },
279 .p1 = { .min = 2, .max = 33 },
280 .p2 = { .dot_limit = 165000,
281 .p2_slow = 4, .p2_fast = 4 },
282 };
283
284 static const intel_limit_t intel_limits_i8xx_lvds = {
285 .dot = { .min = 25000, .max = 350000 },
286 .vco = { .min = 908000, .max = 1512000 },
287 .n = { .min = 2, .max = 16 },
288 .m = { .min = 96, .max = 140 },
289 .m1 = { .min = 18, .max = 26 },
290 .m2 = { .min = 6, .max = 16 },
291 .p = { .min = 4, .max = 128 },
292 .p1 = { .min = 1, .max = 6 },
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 14, .p2_fast = 7 },
295 };
296
297 static const intel_limit_t intel_limits_i9xx_sdvo = {
298 .dot = { .min = 20000, .max = 400000 },
299 .vco = { .min = 1400000, .max = 2800000 },
300 .n = { .min = 1, .max = 6 },
301 .m = { .min = 70, .max = 120 },
302 .m1 = { .min = 8, .max = 18 },
303 .m2 = { .min = 3, .max = 7 },
304 .p = { .min = 5, .max = 80 },
305 .p1 = { .min = 1, .max = 8 },
306 .p2 = { .dot_limit = 200000,
307 .p2_slow = 10, .p2_fast = 5 },
308 };
309
310 static const intel_limit_t intel_limits_i9xx_lvds = {
311 .dot = { .min = 20000, .max = 400000 },
312 .vco = { .min = 1400000, .max = 2800000 },
313 .n = { .min = 1, .max = 6 },
314 .m = { .min = 70, .max = 120 },
315 .m1 = { .min = 8, .max = 18 },
316 .m2 = { .min = 3, .max = 7 },
317 .p = { .min = 7, .max = 98 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 112000,
320 .p2_slow = 14, .p2_fast = 7 },
321 };
322
323
324 static const intel_limit_t intel_limits_g4x_sdvo = {
325 .dot = { .min = 25000, .max = 270000 },
326 .vco = { .min = 1750000, .max = 3500000},
327 .n = { .min = 1, .max = 4 },
328 .m = { .min = 104, .max = 138 },
329 .m1 = { .min = 17, .max = 23 },
330 .m2 = { .min = 5, .max = 11 },
331 .p = { .min = 10, .max = 30 },
332 .p1 = { .min = 1, .max = 3},
333 .p2 = { .dot_limit = 270000,
334 .p2_slow = 10,
335 .p2_fast = 10
336 },
337 };
338
339 static const intel_limit_t intel_limits_g4x_hdmi = {
340 .dot = { .min = 22000, .max = 400000 },
341 .vco = { .min = 1750000, .max = 3500000},
342 .n = { .min = 1, .max = 4 },
343 .m = { .min = 104, .max = 138 },
344 .m1 = { .min = 16, .max = 23 },
345 .m2 = { .min = 5, .max = 11 },
346 .p = { .min = 5, .max = 80 },
347 .p1 = { .min = 1, .max = 8},
348 .p2 = { .dot_limit = 165000,
349 .p2_slow = 10, .p2_fast = 5 },
350 };
351
352 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
353 .dot = { .min = 20000, .max = 115000 },
354 .vco = { .min = 1750000, .max = 3500000 },
355 .n = { .min = 1, .max = 3 },
356 .m = { .min = 104, .max = 138 },
357 .m1 = { .min = 17, .max = 23 },
358 .m2 = { .min = 5, .max = 11 },
359 .p = { .min = 28, .max = 112 },
360 .p1 = { .min = 2, .max = 8 },
361 .p2 = { .dot_limit = 0,
362 .p2_slow = 14, .p2_fast = 14
363 },
364 };
365
366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
367 .dot = { .min = 80000, .max = 224000 },
368 .vco = { .min = 1750000, .max = 3500000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 104, .max = 138 },
371 .m1 = { .min = 17, .max = 23 },
372 .m2 = { .min = 5, .max = 11 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 0,
376 .p2_slow = 7, .p2_fast = 7
377 },
378 };
379
380 static const intel_limit_t intel_limits_pineview_sdvo = {
381 .dot = { .min = 20000, .max = 400000},
382 .vco = { .min = 1700000, .max = 3500000 },
383 /* Pineview's Ncounter is a ring counter */
384 .n = { .min = 3, .max = 6 },
385 .m = { .min = 2, .max = 256 },
386 /* Pineview only has one combined m divider, which we treat as m2. */
387 .m1 = { .min = 0, .max = 0 },
388 .m2 = { .min = 0, .max = 254 },
389 .p = { .min = 5, .max = 80 },
390 .p1 = { .min = 1, .max = 8 },
391 .p2 = { .dot_limit = 200000,
392 .p2_slow = 10, .p2_fast = 5 },
393 };
394
395 static const intel_limit_t intel_limits_pineview_lvds = {
396 .dot = { .min = 20000, .max = 400000 },
397 .vco = { .min = 1700000, .max = 3500000 },
398 .n = { .min = 3, .max = 6 },
399 .m = { .min = 2, .max = 256 },
400 .m1 = { .min = 0, .max = 0 },
401 .m2 = { .min = 0, .max = 254 },
402 .p = { .min = 7, .max = 112 },
403 .p1 = { .min = 1, .max = 8 },
404 .p2 = { .dot_limit = 112000,
405 .p2_slow = 14, .p2_fast = 14 },
406 };
407
408 /* Ironlake / Sandybridge
409 *
410 * We calculate clock using (register_value + 2) for N/M1/M2, so here
411 * the range value for them is (actual_value - 2).
412 */
413 static const intel_limit_t intel_limits_ironlake_dac = {
414 .dot = { .min = 25000, .max = 350000 },
415 .vco = { .min = 1760000, .max = 3510000 },
416 .n = { .min = 1, .max = 5 },
417 .m = { .min = 79, .max = 127 },
418 .m1 = { .min = 12, .max = 22 },
419 .m2 = { .min = 5, .max = 9 },
420 .p = { .min = 5, .max = 80 },
421 .p1 = { .min = 1, .max = 8 },
422 .p2 = { .dot_limit = 225000,
423 .p2_slow = 10, .p2_fast = 5 },
424 };
425
426 static const intel_limit_t intel_limits_ironlake_single_lvds = {
427 .dot = { .min = 25000, .max = 350000 },
428 .vco = { .min = 1760000, .max = 3510000 },
429 .n = { .min = 1, .max = 3 },
430 .m = { .min = 79, .max = 118 },
431 .m1 = { .min = 12, .max = 22 },
432 .m2 = { .min = 5, .max = 9 },
433 .p = { .min = 28, .max = 112 },
434 .p1 = { .min = 2, .max = 8 },
435 .p2 = { .dot_limit = 225000,
436 .p2_slow = 14, .p2_fast = 14 },
437 };
438
439 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
440 .dot = { .min = 25000, .max = 350000 },
441 .vco = { .min = 1760000, .max = 3510000 },
442 .n = { .min = 1, .max = 3 },
443 .m = { .min = 79, .max = 127 },
444 .m1 = { .min = 12, .max = 22 },
445 .m2 = { .min = 5, .max = 9 },
446 .p = { .min = 14, .max = 56 },
447 .p1 = { .min = 2, .max = 8 },
448 .p2 = { .dot_limit = 225000,
449 .p2_slow = 7, .p2_fast = 7 },
450 };
451
452 /* LVDS 100mhz refclk limits. */
453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
454 .dot = { .min = 25000, .max = 350000 },
455 .vco = { .min = 1760000, .max = 3510000 },
456 .n = { .min = 1, .max = 2 },
457 .m = { .min = 79, .max = 126 },
458 .m1 = { .min = 12, .max = 22 },
459 .m2 = { .min = 5, .max = 9 },
460 .p = { .min = 28, .max = 112 },
461 .p1 = { .min = 2, .max = 8 },
462 .p2 = { .dot_limit = 225000,
463 .p2_slow = 14, .p2_fast = 14 },
464 };
465
466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
467 .dot = { .min = 25000, .max = 350000 },
468 .vco = { .min = 1760000, .max = 3510000 },
469 .n = { .min = 1, .max = 3 },
470 .m = { .min = 79, .max = 126 },
471 .m1 = { .min = 12, .max = 22 },
472 .m2 = { .min = 5, .max = 9 },
473 .p = { .min = 14, .max = 42 },
474 .p1 = { .min = 2, .max = 6 },
475 .p2 = { .dot_limit = 225000,
476 .p2_slow = 7, .p2_fast = 7 },
477 };
478
479 static const intel_limit_t intel_limits_vlv = {
480 /*
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
485 */
486 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
487 .vco = { .min = 4000000, .max = 6000000 },
488 .n = { .min = 1, .max = 7 },
489 .m1 = { .min = 2, .max = 3 },
490 .m2 = { .min = 11, .max = 156 },
491 .p1 = { .min = 2, .max = 3 },
492 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
493 };
494
495 static const intel_limit_t intel_limits_chv = {
496 /*
497 * These are the data rate limits (measured in fast clocks)
498 * since those are the strictest limits we have. The fast
499 * clock and actual rate limits are more relaxed, so checking
500 * them would make no difference.
501 */
502 .dot = { .min = 25000 * 5, .max = 540000 * 5},
503 .vco = { .min = 4800000, .max = 6480000 },
504 .n = { .min = 1, .max = 1 },
505 .m1 = { .min = 2, .max = 2 },
506 .m2 = { .min = 24 << 22, .max = 175 << 22 },
507 .p1 = { .min = 2, .max = 4 },
508 .p2 = { .p2_slow = 1, .p2_fast = 14 },
509 };
510
511 static const intel_limit_t intel_limits_bxt = {
512 /* FIXME: find real dot limits */
513 .dot = { .min = 0, .max = INT_MAX },
514 .vco = { .min = 4800000, .max = 6700000 },
515 .n = { .min = 1, .max = 1 },
516 .m1 = { .min = 2, .max = 2 },
517 /* FIXME: find real m2 limits */
518 .m2 = { .min = 2 << 22, .max = 255 << 22 },
519 .p1 = { .min = 2, .max = 4 },
520 .p2 = { .p2_slow = 1, .p2_fast = 20 },
521 };
522
523 static bool
524 needs_modeset(struct drm_crtc_state *state)
525 {
526 return drm_atomic_crtc_needs_modeset(state);
527 }
528
529 /**
530 * Returns whether any output on the specified pipe is of the specified type
531 */
532 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
533 {
534 struct drm_device *dev = crtc->base.dev;
535 struct intel_encoder *encoder;
536
537 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
538 if (encoder->type == type)
539 return true;
540
541 return false;
542 }
543
544 /**
545 * Returns whether any output on the specified pipe will have the specified
546 * type after a staged modeset is complete, i.e., the same as
547 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
548 * encoder->crtc.
549 */
550 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
551 int type)
552 {
553 struct drm_atomic_state *state = crtc_state->base.state;
554 struct drm_connector *connector;
555 struct drm_connector_state *connector_state;
556 struct intel_encoder *encoder;
557 int i, num_connectors = 0;
558
559 for_each_connector_in_state(state, connector, connector_state, i) {
560 if (connector_state->crtc != crtc_state->base.crtc)
561 continue;
562
563 num_connectors++;
564
565 encoder = to_intel_encoder(connector_state->best_encoder);
566 if (encoder->type == type)
567 return true;
568 }
569
570 WARN_ON(num_connectors == 0);
571
572 return false;
573 }
574
575 /*
576 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
577 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
578 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
579 * The helpers' return value is the rate of the clock that is fed to the
580 * display engine's pipe which can be the above fast dot clock rate or a
581 * divided-down version of it.
582 */
583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
584 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
585 {
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592
593 return clock->dot;
594 }
595
596 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
597 {
598 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
599 }
600
601 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
602 {
603 clock->m = i9xx_dpll_compute_m(clock);
604 clock->p = clock->p1 * clock->p2;
605 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
606 return 0;
607 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
608 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
609
610 return clock->dot;
611 }
612
613 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
614 {
615 clock->m = clock->m1 * clock->m2;
616 clock->p = clock->p1 * clock->p2;
617 if (WARN_ON(clock->n == 0 || clock->p == 0))
618 return 0;
619 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
620 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
621
622 return clock->dot / 5;
623 }
624
625 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
626 {
627 clock->m = clock->m1 * clock->m2;
628 clock->p = clock->p1 * clock->p2;
629 if (WARN_ON(clock->n == 0 || clock->p == 0))
630 return 0;
631 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
632 clock->n << 22);
633 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
634
635 return clock->dot / 5;
636 }
637
638 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
639 /**
640 * Returns whether the given set of divisors are valid for a given refclk with
641 * the given connectors.
642 */
643
644 static bool intel_PLL_is_valid(struct drm_device *dev,
645 const intel_limit_t *limit,
646 const intel_clock_t *clock)
647 {
648 if (clock->n < limit->n.min || limit->n.max < clock->n)
649 INTELPllInvalid("n out of range\n");
650 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
651 INTELPllInvalid("p1 out of range\n");
652 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
653 INTELPllInvalid("m2 out of range\n");
654 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
655 INTELPllInvalid("m1 out of range\n");
656
657 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
658 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
659 if (clock->m1 <= clock->m2)
660 INTELPllInvalid("m1 <= m2\n");
661
662 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
663 if (clock->p < limit->p.min || limit->p.max < clock->p)
664 INTELPllInvalid("p out of range\n");
665 if (clock->m < limit->m.min || limit->m.max < clock->m)
666 INTELPllInvalid("m out of range\n");
667 }
668
669 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
670 INTELPllInvalid("vco out of range\n");
671 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
672 * connector, etc., rather than just a single range.
673 */
674 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
675 INTELPllInvalid("dot out of range\n");
676
677 return true;
678 }
679
680 static int
681 i9xx_select_p2_div(const intel_limit_t *limit,
682 const struct intel_crtc_state *crtc_state,
683 int target)
684 {
685 struct drm_device *dev = crtc_state->base.crtc->dev;
686
687 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
688 /*
689 * For LVDS just rely on its current settings for dual-channel.
690 * We haven't figured out how to reliably set up different
691 * single/dual channel state, if we even can.
692 */
693 if (intel_is_dual_link_lvds(dev))
694 return limit->p2.p2_fast;
695 else
696 return limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 return limit->p2.p2_slow;
700 else
701 return limit->p2.p2_fast;
702 }
703 }
704
705 /*
706 * Returns a set of divisors for the desired target clock with the given
707 * refclk, or FALSE. The returned values represent the clock equation:
708 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
709 *
710 * Target and reference clocks are specified in kHz.
711 *
712 * If match_clock is provided, then best_clock P divider must match the P
713 * divider from @match_clock used for LVDS downclocking.
714 */
715 static bool
716 i9xx_find_best_dpll(const intel_limit_t *limit,
717 struct intel_crtc_state *crtc_state,
718 int target, int refclk, intel_clock_t *match_clock,
719 intel_clock_t *best_clock)
720 {
721 struct drm_device *dev = crtc_state->base.crtc->dev;
722 intel_clock_t clock;
723 int err = target;
724
725 memset(best_clock, 0, sizeof(*best_clock));
726
727 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
728
729 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
730 clock.m1++) {
731 for (clock.m2 = limit->m2.min;
732 clock.m2 <= limit->m2.max; clock.m2++) {
733 if (clock.m2 >= clock.m1)
734 break;
735 for (clock.n = limit->n.min;
736 clock.n <= limit->n.max; clock.n++) {
737 for (clock.p1 = limit->p1.min;
738 clock.p1 <= limit->p1.max; clock.p1++) {
739 int this_err;
740
741 i9xx_calc_dpll_params(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
748
749 this_err = abs(clock.dot - target);
750 if (this_err < err) {
751 *best_clock = clock;
752 err = this_err;
753 }
754 }
755 }
756 }
757 }
758
759 return (err != target);
760 }
761
762 /*
763 * Returns a set of divisors for the desired target clock with the given
764 * refclk, or FALSE. The returned values represent the clock equation:
765 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
766 *
767 * Target and reference clocks are specified in kHz.
768 *
769 * If match_clock is provided, then best_clock P divider must match the P
770 * divider from @match_clock used for LVDS downclocking.
771 */
772 static bool
773 pnv_find_best_dpll(const intel_limit_t *limit,
774 struct intel_crtc_state *crtc_state,
775 int target, int refclk, intel_clock_t *match_clock,
776 intel_clock_t *best_clock)
777 {
778 struct drm_device *dev = crtc_state->base.crtc->dev;
779 intel_clock_t clock;
780 int err = target;
781
782 memset(best_clock, 0, sizeof(*best_clock));
783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
786 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
787 clock.m1++) {
788 for (clock.m2 = limit->m2.min;
789 clock.m2 <= limit->m2.max; clock.m2++) {
790 for (clock.n = limit->n.min;
791 clock.n <= limit->n.max; clock.n++) {
792 for (clock.p1 = limit->p1.min;
793 clock.p1 <= limit->p1.max; clock.p1++) {
794 int this_err;
795
796 pnv_calc_dpll_params(refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
799 continue;
800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
803
804 this_err = abs(clock.dot - target);
805 if (this_err < err) {
806 *best_clock = clock;
807 err = this_err;
808 }
809 }
810 }
811 }
812 }
813
814 return (err != target);
815 }
816
817 /*
818 * Returns a set of divisors for the desired target clock with the given
819 * refclk, or FALSE. The returned values represent the clock equation:
820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
821 *
822 * Target and reference clocks are specified in kHz.
823 *
824 * If match_clock is provided, then best_clock P divider must match the P
825 * divider from @match_clock used for LVDS downclocking.
826 */
827 static bool
828 g4x_find_best_dpll(const intel_limit_t *limit,
829 struct intel_crtc_state *crtc_state,
830 int target, int refclk, intel_clock_t *match_clock,
831 intel_clock_t *best_clock)
832 {
833 struct drm_device *dev = crtc_state->base.crtc->dev;
834 intel_clock_t clock;
835 int max_n;
836 bool found = false;
837 /* approximately equals target * 0.00585 */
838 int err_most = (target >> 8) + (target >> 9);
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
843
844 max_n = limit->n.max;
845 /* based on hardware requirement, prefer smaller n to precision */
846 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
847 /* based on hardware requirement, prefere larger m1,m2 */
848 for (clock.m1 = limit->m1.max;
849 clock.m1 >= limit->m1.min; clock.m1--) {
850 for (clock.m2 = limit->m2.max;
851 clock.m2 >= limit->m2.min; clock.m2--) {
852 for (clock.p1 = limit->p1.max;
853 clock.p1 >= limit->p1.min; clock.p1--) {
854 int this_err;
855
856 i9xx_calc_dpll_params(refclk, &clock);
857 if (!intel_PLL_is_valid(dev, limit,
858 &clock))
859 continue;
860
861 this_err = abs(clock.dot - target);
862 if (this_err < err_most) {
863 *best_clock = clock;
864 err_most = this_err;
865 max_n = clock.n;
866 found = true;
867 }
868 }
869 }
870 }
871 }
872 return found;
873 }
874
875 /*
876 * Check if the calculated PLL configuration is more optimal compared to the
877 * best configuration and error found so far. Return the calculated error.
878 */
879 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
880 const intel_clock_t *calculated_clock,
881 const intel_clock_t *best_clock,
882 unsigned int best_error_ppm,
883 unsigned int *error_ppm)
884 {
885 /*
886 * For CHV ignore the error and consider only the P value.
887 * Prefer a bigger P value based on HW requirements.
888 */
889 if (IS_CHERRYVIEW(dev)) {
890 *error_ppm = 0;
891
892 return calculated_clock->p > best_clock->p;
893 }
894
895 if (WARN_ON_ONCE(!target_freq))
896 return false;
897
898 *error_ppm = div_u64(1000000ULL *
899 abs(target_freq - calculated_clock->dot),
900 target_freq);
901 /*
902 * Prefer a better P value over a better (smaller) error if the error
903 * is small. Ensure this preference for future configurations too by
904 * setting the error to 0.
905 */
906 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
907 *error_ppm = 0;
908
909 return true;
910 }
911
912 return *error_ppm + 10 < best_error_ppm;
913 }
914
915 /*
916 * Returns a set of divisors for the desired target clock with the given
917 * refclk, or FALSE. The returned values represent the clock equation:
918 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
919 */
920 static bool
921 vlv_find_best_dpll(const intel_limit_t *limit,
922 struct intel_crtc_state *crtc_state,
923 int target, int refclk, intel_clock_t *match_clock,
924 intel_clock_t *best_clock)
925 {
926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
927 struct drm_device *dev = crtc->base.dev;
928 intel_clock_t clock;
929 unsigned int bestppm = 1000000;
930 /* min update 19.2 MHz */
931 int max_n = min(limit->n.max, refclk / 19200);
932 bool found = false;
933
934 target *= 5; /* fast clock */
935
936 memset(best_clock, 0, sizeof(*best_clock));
937
938 /* based on hardware requirement, prefer smaller n to precision */
939 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
940 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
943 clock.p = clock.p1 * clock.p2;
944 /* based on hardware requirement, prefer bigger m1,m2 values */
945 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
946 unsigned int ppm;
947
948 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
949 refclk * clock.m1);
950
951 vlv_calc_dpll_params(refclk, &clock);
952
953 if (!intel_PLL_is_valid(dev, limit,
954 &clock))
955 continue;
956
957 if (!vlv_PLL_is_optimal(dev, target,
958 &clock,
959 best_clock,
960 bestppm, &ppm))
961 continue;
962
963 *best_clock = clock;
964 bestppm = ppm;
965 found = true;
966 }
967 }
968 }
969 }
970
971 return found;
972 }
973
974 /*
975 * Returns a set of divisors for the desired target clock with the given
976 * refclk, or FALSE. The returned values represent the clock equation:
977 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
978 */
979 static bool
980 chv_find_best_dpll(const intel_limit_t *limit,
981 struct intel_crtc_state *crtc_state,
982 int target, int refclk, intel_clock_t *match_clock,
983 intel_clock_t *best_clock)
984 {
985 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
986 struct drm_device *dev = crtc->base.dev;
987 unsigned int best_error_ppm;
988 intel_clock_t clock;
989 uint64_t m2;
990 int found = false;
991
992 memset(best_clock, 0, sizeof(*best_clock));
993 best_error_ppm = 1000000;
994
995 /*
996 * Based on hardware doc, the n always set to 1, and m1 always
997 * set to 2. If requires to support 200Mhz refclk, we need to
998 * revisit this because n may not 1 anymore.
999 */
1000 clock.n = 1, clock.m1 = 2;
1001 target *= 5; /* fast clock */
1002
1003 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004 for (clock.p2 = limit->p2.p2_fast;
1005 clock.p2 >= limit->p2.p2_slow;
1006 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007 unsigned int error_ppm;
1008
1009 clock.p = clock.p1 * clock.p2;
1010
1011 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1012 clock.n) << 22, refclk * clock.m1);
1013
1014 if (m2 > INT_MAX/clock.m1)
1015 continue;
1016
1017 clock.m2 = m2;
1018
1019 chv_calc_dpll_params(refclk, &clock);
1020
1021 if (!intel_PLL_is_valid(dev, limit, &clock))
1022 continue;
1023
1024 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025 best_error_ppm, &error_ppm))
1026 continue;
1027
1028 *best_clock = clock;
1029 best_error_ppm = error_ppm;
1030 found = true;
1031 }
1032 }
1033
1034 return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1038 intel_clock_t *best_clock)
1039 {
1040 int refclk = 100000;
1041 const intel_limit_t *limit = &intel_limits_bxt;
1042
1043 return chv_find_best_dpll(limit, crtc_state,
1044 target_clock, refclk, NULL, best_clock);
1045 }
1046
1047 bool intel_crtc_active(struct drm_crtc *crtc)
1048 {
1049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1050
1051 /* Be paranoid as we can arrive here with only partial
1052 * state retrieved from the hardware during setup.
1053 *
1054 * We can ditch the adjusted_mode.crtc_clock check as soon
1055 * as Haswell has gained clock readout/fastboot support.
1056 *
1057 * We can ditch the crtc->primary->fb check as soon as we can
1058 * properly reconstruct framebuffers.
1059 *
1060 * FIXME: The intel_crtc->active here should be switched to
1061 * crtc->state->active once we have proper CRTC states wired up
1062 * for atomic.
1063 */
1064 return intel_crtc->active && crtc->primary->state->fb &&
1065 intel_crtc->config->base.adjusted_mode.crtc_clock;
1066 }
1067
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069 enum pipe pipe)
1070 {
1071 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073
1074 return intel_crtc->config->cpu_transcoder;
1075 }
1076
1077 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1078 {
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 i915_reg_t reg = PIPEDSL(pipe);
1081 u32 line1, line2;
1082 u32 line_mask;
1083
1084 if (IS_GEN2(dev))
1085 line_mask = DSL_LINEMASK_GEN2;
1086 else
1087 line_mask = DSL_LINEMASK_GEN3;
1088
1089 line1 = I915_READ(reg) & line_mask;
1090 msleep(5);
1091 line2 = I915_READ(reg) & line_mask;
1092
1093 return line1 == line2;
1094 }
1095
1096 /*
1097 * intel_wait_for_pipe_off - wait for pipe to turn off
1098 * @crtc: crtc whose pipe to wait for
1099 *
1100 * After disabling a pipe, we can't wait for vblank in the usual way,
1101 * spinning on the vblank interrupt status bit, since we won't actually
1102 * see an interrupt when the pipe is disabled.
1103 *
1104 * On Gen4 and above:
1105 * wait for the pipe register state bit to turn off
1106 *
1107 * Otherwise:
1108 * wait for the display line value to settle (it usually
1109 * ends up stopping at the start of the next frame).
1110 *
1111 */
1112 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1113 {
1114 struct drm_device *dev = crtc->base.dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1117 enum pipe pipe = crtc->pipe;
1118
1119 if (INTEL_INFO(dev)->gen >= 4) {
1120 i915_reg_t reg = PIPECONF(cpu_transcoder);
1121
1122 /* Wait for the Pipe State to go off */
1123 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1124 100))
1125 WARN(1, "pipe_off wait timed out\n");
1126 } else {
1127 /* Wait for the display line to settle */
1128 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 }
1131 }
1132
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1136 {
1137 u32 val;
1138 bool cur_state;
1139
1140 val = I915_READ(DPLL(pipe));
1141 cur_state = !!(val & DPLL_VCO_ENABLE);
1142 I915_STATE_WARN(cur_state != state,
1143 "PLL state assertion failure (expected %s, current %s)\n",
1144 onoff(state), onoff(cur_state));
1145 }
1146
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 {
1150 u32 val;
1151 bool cur_state;
1152
1153 mutex_lock(&dev_priv->sb_lock);
1154 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1155 mutex_unlock(&dev_priv->sb_lock);
1156
1157 cur_state = val & DSI_PLL_VCO_EN;
1158 I915_STATE_WARN(cur_state != state,
1159 "DSI PLL state assertion failure (expected %s, current %s)\n",
1160 onoff(state), onoff(cur_state));
1161 }
1162
1163 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1165 {
1166 bool cur_state;
1167 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1168 pipe);
1169
1170 if (HAS_DDI(dev_priv)) {
1171 /* DDI does not have a specific FDI_TX register */
1172 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1173 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1174 } else {
1175 u32 val = I915_READ(FDI_TX_CTL(pipe));
1176 cur_state = !!(val & FDI_TX_ENABLE);
1177 }
1178 I915_STATE_WARN(cur_state != state,
1179 "FDI TX state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1184
1185 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 u32 val;
1189 bool cur_state;
1190
1191 val = I915_READ(FDI_RX_CTL(pipe));
1192 cur_state = !!(val & FDI_RX_ENABLE);
1193 I915_STATE_WARN(cur_state != state,
1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 onoff(state), onoff(cur_state));
1196 }
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202 {
1203 u32 val;
1204
1205 /* ILK FDI PLL is always enabled */
1206 if (INTEL_INFO(dev_priv)->gen == 5)
1207 return;
1208
1209 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210 if (HAS_DDI(dev_priv))
1211 return;
1212
1213 val = I915_READ(FDI_TX_CTL(pipe));
1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 u32 val;
1221 bool cur_state;
1222
1223 val = I915_READ(FDI_RX_CTL(pipe));
1224 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227 onoff(state), onoff(cur_state));
1228 }
1229
1230 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 struct drm_device *dev = dev_priv->dev;
1234 i915_reg_t pp_reg;
1235 u32 val;
1236 enum pipe panel_pipe = PIPE_A;
1237 bool locked = true;
1238
1239 if (WARN_ON(HAS_DDI(dev)))
1240 return;
1241
1242 if (HAS_PCH_SPLIT(dev)) {
1243 u32 port_sel;
1244
1245 pp_reg = PCH_PP_CONTROL;
1246 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1247
1248 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1249 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1250 panel_pipe = PIPE_B;
1251 /* XXX: else fix for eDP */
1252 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1253 /* presumably write lock depends on pipe, not port select */
1254 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1255 panel_pipe = pipe;
1256 } else {
1257 pp_reg = PP_CONTROL;
1258 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1259 panel_pipe = PIPE_B;
1260 }
1261
1262 val = I915_READ(pp_reg);
1263 if (!(val & PANEL_POWER_ON) ||
1264 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1265 locked = false;
1266
1267 I915_STATE_WARN(panel_pipe == pipe && locked,
1268 "panel assertion failure, pipe %c regs locked\n",
1269 pipe_name(pipe));
1270 }
1271
1272 static void assert_cursor(struct drm_i915_private *dev_priv,
1273 enum pipe pipe, bool state)
1274 {
1275 struct drm_device *dev = dev_priv->dev;
1276 bool cur_state;
1277
1278 if (IS_845G(dev) || IS_I865G(dev))
1279 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1280 else
1281 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1282
1283 I915_STATE_WARN(cur_state != state,
1284 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285 pipe_name(pipe), onoff(state), onoff(cur_state));
1286 }
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1289
1290 void assert_pipe(struct drm_i915_private *dev_priv,
1291 enum pipe pipe, bool state)
1292 {
1293 bool cur_state;
1294 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1295 pipe);
1296 enum intel_display_power_domain power_domain;
1297
1298 /* if we need the pipe quirk it must be always on */
1299 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1300 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1301 state = true;
1302
1303 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1304 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1305 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1306 cur_state = !!(val & PIPECONF_ENABLE);
1307
1308 intel_display_power_put(dev_priv, power_domain);
1309 } else {
1310 cur_state = false;
1311 }
1312
1313 I915_STATE_WARN(cur_state != state,
1314 "pipe %c assertion failure (expected %s, current %s)\n",
1315 pipe_name(pipe), onoff(state), onoff(cur_state));
1316 }
1317
1318 static void assert_plane(struct drm_i915_private *dev_priv,
1319 enum plane plane, bool state)
1320 {
1321 u32 val;
1322 bool cur_state;
1323
1324 val = I915_READ(DSPCNTR(plane));
1325 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1326 I915_STATE_WARN(cur_state != state,
1327 "plane %c assertion failure (expected %s, current %s)\n",
1328 plane_name(plane), onoff(state), onoff(cur_state));
1329 }
1330
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1333
1334 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1335 enum pipe pipe)
1336 {
1337 struct drm_device *dev = dev_priv->dev;
1338 int i;
1339
1340 /* Primary planes are fixed to pipes on gen4+ */
1341 if (INTEL_INFO(dev)->gen >= 4) {
1342 u32 val = I915_READ(DSPCNTR(pipe));
1343 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1344 "plane %c assertion failure, should be disabled but not\n",
1345 plane_name(pipe));
1346 return;
1347 }
1348
1349 /* Need to check both planes against the pipe */
1350 for_each_pipe(dev_priv, i) {
1351 u32 val = I915_READ(DSPCNTR(i));
1352 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1353 DISPPLANE_SEL_PIPE_SHIFT;
1354 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1355 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(i), pipe_name(pipe));
1357 }
1358 }
1359
1360 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362 {
1363 struct drm_device *dev = dev_priv->dev;
1364 int sprite;
1365
1366 if (INTEL_INFO(dev)->gen >= 9) {
1367 for_each_sprite(dev_priv, pipe, sprite) {
1368 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1369 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1370 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371 sprite, pipe_name(pipe));
1372 }
1373 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1374 for_each_sprite(dev_priv, pipe, sprite) {
1375 u32 val = I915_READ(SPCNTR(pipe, sprite));
1376 I915_STATE_WARN(val & SP_ENABLE,
1377 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378 sprite_name(pipe, sprite), pipe_name(pipe));
1379 }
1380 } else if (INTEL_INFO(dev)->gen >= 7) {
1381 u32 val = I915_READ(SPRCTL(pipe));
1382 I915_STATE_WARN(val & SPRITE_ENABLE,
1383 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384 plane_name(pipe), pipe_name(pipe));
1385 } else if (INTEL_INFO(dev)->gen >= 5) {
1386 u32 val = I915_READ(DVSCNTR(pipe));
1387 I915_STATE_WARN(val & DVS_ENABLE,
1388 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(pipe), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_vblank_disabled(struct drm_crtc *crtc)
1394 {
1395 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1396 drm_crtc_vblank_put(crtc);
1397 }
1398
1399 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe)
1401 {
1402 u32 val;
1403 bool enabled;
1404
1405 val = I915_READ(PCH_TRANSCONF(pipe));
1406 enabled = !!(val & TRANS_ENABLE);
1407 I915_STATE_WARN(enabled,
1408 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1409 pipe_name(pipe));
1410 }
1411
1412 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, u32 port_sel, u32 val)
1414 {
1415 if ((val & DP_PORT_EN) == 0)
1416 return false;
1417
1418 if (HAS_PCH_CPT(dev_priv)) {
1419 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1420 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421 return false;
1422 } else if (IS_CHERRYVIEW(dev_priv)) {
1423 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424 return false;
1425 } else {
1426 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427 return false;
1428 }
1429 return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe, u32 val)
1434 {
1435 if ((val & SDVO_ENABLE) == 0)
1436 return false;
1437
1438 if (HAS_PCH_CPT(dev_priv)) {
1439 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440 return false;
1441 } else if (IS_CHERRYVIEW(dev_priv)) {
1442 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443 return false;
1444 } else {
1445 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & LVDS_PORT_EN) == 0)
1455 return false;
1456
1457 if (HAS_PCH_CPT(dev_priv)) {
1458 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459 return false;
1460 } else {
1461 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462 return false;
1463 }
1464 return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe, u32 val)
1469 {
1470 if ((val & ADPA_DAC_ENABLE) == 0)
1471 return false;
1472 if (HAS_PCH_CPT(dev_priv)) {
1473 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474 return false;
1475 } else {
1476 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477 return false;
1478 }
1479 return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, i915_reg_t reg,
1484 u32 port_sel)
1485 {
1486 u32 val = I915_READ(reg);
1487 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1488 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489 i915_mmio_reg_offset(reg), pipe_name(pipe));
1490
1491 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1492 && (val & DP_PIPEB_SELECT),
1493 "IBX PCH dp port still using transcoder B\n");
1494 }
1495
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, i915_reg_t reg)
1498 {
1499 u32 val = I915_READ(reg);
1500 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1501 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502 i915_mmio_reg_offset(reg), pipe_name(pipe));
1503
1504 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1505 && (val & SDVO_PIPE_B_SELECT),
1506 "IBX PCH hdmi port still using transcoder B\n");
1507 }
1508
1509 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe)
1511 {
1512 u32 val;
1513
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518 val = I915_READ(PCH_ADPA);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1521 pipe_name(pipe));
1522
1523 val = I915_READ(PCH_LVDS);
1524 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1525 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1526 pipe_name(pipe));
1527
1528 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc,
1534 const struct intel_crtc_state *pipe_config)
1535 {
1536 struct drm_device *dev = crtc->base.dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 enum pipe pipe = crtc->pipe;
1539 i915_reg_t reg = DPLL(pipe);
1540 u32 dpll = pipe_config->dpll_hw_state.dpll;
1541
1542 assert_pipe_disabled(dev_priv, pipe);
1543
1544 /* PLL is protected by panel, make sure we can write it */
1545 assert_panel_unlocked(dev_priv, pipe);
1546
1547 I915_WRITE(reg, dpll);
1548 POSTING_READ(reg);
1549 udelay(150);
1550
1551 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1553
1554 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1555 POSTING_READ(DPLL_MD(pipe));
1556 }
1557
1558 static void chv_enable_pll(struct intel_crtc *crtc,
1559 const struct intel_crtc_state *pipe_config)
1560 {
1561 struct drm_device *dev = crtc->base.dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 enum pipe pipe = crtc->pipe;
1564 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1565 u32 tmp;
1566
1567 assert_pipe_disabled(dev_priv, pipe);
1568
1569 /* PLL is protected by panel, make sure we can write it */
1570 assert_panel_unlocked(dev_priv, pipe);
1571
1572 mutex_lock(&dev_priv->sb_lock);
1573
1574 /* Enable back the 10bit clock to display controller */
1575 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1576 tmp |= DPIO_DCLKP_EN;
1577 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1578
1579 mutex_unlock(&dev_priv->sb_lock);
1580
1581 /*
1582 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1583 */
1584 udelay(1);
1585
1586 /* Enable PLL */
1587 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1588
1589 /* Check PLL is locked */
1590 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1591 DRM_ERROR("PLL %d failed to lock\n", pipe);
1592
1593 if (pipe != PIPE_A) {
1594 /*
1595 * WaPixelRepeatModeFixForC0:chv
1596 *
1597 * DPLLCMD is AWOL. Use chicken bits to propagate
1598 * the value from DPLLBMD to either pipe B or C.
1599 */
1600 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1601 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1602 I915_WRITE(CBR4_VLV, 0);
1603 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1604
1605 /*
1606 * DPLLB VGA mode also seems to cause problems.
1607 * We should always have it disabled.
1608 */
1609 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1610 } else {
1611 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1612 POSTING_READ(DPLL_MD(pipe));
1613 }
1614 }
1615
1616 static int intel_num_dvo_pipes(struct drm_device *dev)
1617 {
1618 struct intel_crtc *crtc;
1619 int count = 0;
1620
1621 for_each_intel_crtc(dev, crtc)
1622 count += crtc->base.state->active &&
1623 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1624
1625 return count;
1626 }
1627
1628 static void i9xx_enable_pll(struct intel_crtc *crtc)
1629 {
1630 struct drm_device *dev = crtc->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 i915_reg_t reg = DPLL(crtc->pipe);
1633 u32 dpll = crtc->config->dpll_hw_state.dpll;
1634
1635 assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637 /* PLL is protected by panel, make sure we can write it */
1638 if (IS_MOBILE(dev) && !IS_I830(dev))
1639 assert_panel_unlocked(dev_priv, crtc->pipe);
1640
1641 /* Enable DVO 2x clock on both PLLs if necessary */
1642 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1643 /*
1644 * It appears to be important that we don't enable this
1645 * for the current pipe before otherwise configuring the
1646 * PLL. No idea how this should be handled if multiple
1647 * DVO outputs are enabled simultaneosly.
1648 */
1649 dpll |= DPLL_DVO_2X_MODE;
1650 I915_WRITE(DPLL(!crtc->pipe),
1651 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1652 }
1653
1654 /*
1655 * Apparently we need to have VGA mode enabled prior to changing
1656 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1657 * dividers, even though the register value does change.
1658 */
1659 I915_WRITE(reg, 0);
1660
1661 I915_WRITE(reg, dpll);
1662
1663 /* Wait for the clocks to stabilize. */
1664 POSTING_READ(reg);
1665 udelay(150);
1666
1667 if (INTEL_INFO(dev)->gen >= 4) {
1668 I915_WRITE(DPLL_MD(crtc->pipe),
1669 crtc->config->dpll_hw_state.dpll_md);
1670 } else {
1671 /* The pixel multiplier can only be updated once the
1672 * DPLL is enabled and the clocks are stable.
1673 *
1674 * So write it again.
1675 */
1676 I915_WRITE(reg, dpll);
1677 }
1678
1679 /* We do this three times for luck */
1680 I915_WRITE(reg, dpll);
1681 POSTING_READ(reg);
1682 udelay(150); /* wait for warmup */
1683 I915_WRITE(reg, dpll);
1684 POSTING_READ(reg);
1685 udelay(150); /* wait for warmup */
1686 I915_WRITE(reg, dpll);
1687 POSTING_READ(reg);
1688 udelay(150); /* wait for warmup */
1689 }
1690
1691 /**
1692 * i9xx_disable_pll - disable a PLL
1693 * @dev_priv: i915 private structure
1694 * @pipe: pipe PLL to disable
1695 *
1696 * Disable the PLL for @pipe, making sure the pipe is off first.
1697 *
1698 * Note! This is for pre-ILK only.
1699 */
1700 static void i9xx_disable_pll(struct intel_crtc *crtc)
1701 {
1702 struct drm_device *dev = crtc->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 enum pipe pipe = crtc->pipe;
1705
1706 /* Disable DVO 2x clock on both PLLs if necessary */
1707 if (IS_I830(dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1709 !intel_num_dvo_pipes(dev)) {
1710 I915_WRITE(DPLL(PIPE_B),
1711 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1712 I915_WRITE(DPLL(PIPE_A),
1713 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1714 }
1715
1716 /* Don't disable pipe or pipe PLLs if needed */
1717 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1718 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1719 return;
1720
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv, pipe);
1723
1724 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1725 POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730 u32 val;
1731
1732 /* Make sure the pipe isn't still relying on us */
1733 assert_pipe_disabled(dev_priv, pipe);
1734
1735 val = DPLL_INTEGRATED_REF_CLK_VLV |
1736 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737 if (pipe != PIPE_A)
1738 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740 I915_WRITE(DPLL(pipe), val);
1741 POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1747 u32 val;
1748
1749 /* Make sure the pipe isn't still relying on us */
1750 assert_pipe_disabled(dev_priv, pipe);
1751
1752 val = DPLL_SSC_REF_CLK_CHV |
1753 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1754 if (pipe != PIPE_A)
1755 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756
1757 I915_WRITE(DPLL(pipe), val);
1758 POSTING_READ(DPLL(pipe));
1759
1760 mutex_lock(&dev_priv->sb_lock);
1761
1762 /* Disable 10bit clock to display controller */
1763 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1764 val &= ~DPIO_DCLKP_EN;
1765 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1766
1767 mutex_unlock(&dev_priv->sb_lock);
1768 }
1769
1770 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1771 struct intel_digital_port *dport,
1772 unsigned int expected_mask)
1773 {
1774 u32 port_mask;
1775 i915_reg_t dpll_reg;
1776
1777 switch (dport->port) {
1778 case PORT_B:
1779 port_mask = DPLL_PORTB_READY_MASK;
1780 dpll_reg = DPLL(0);
1781 break;
1782 case PORT_C:
1783 port_mask = DPLL_PORTC_READY_MASK;
1784 dpll_reg = DPLL(0);
1785 expected_mask <<= 4;
1786 break;
1787 case PORT_D:
1788 port_mask = DPLL_PORTD_READY_MASK;
1789 dpll_reg = DPIO_PHY_STATUS;
1790 break;
1791 default:
1792 BUG();
1793 }
1794
1795 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1796 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1797 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1798 }
1799
1800 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1801 enum pipe pipe)
1802 {
1803 struct drm_device *dev = dev_priv->dev;
1804 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806 i915_reg_t reg;
1807 uint32_t val, pipeconf_val;
1808
1809 /* Make sure PCH DPLL is enabled */
1810 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1811
1812 /* FDI must be feeding us bits for PCH ports */
1813 assert_fdi_tx_enabled(dev_priv, pipe);
1814 assert_fdi_rx_enabled(dev_priv, pipe);
1815
1816 if (HAS_PCH_CPT(dev)) {
1817 /* Workaround: Set the timing override bit before enabling the
1818 * pch transcoder. */
1819 reg = TRANS_CHICKEN2(pipe);
1820 val = I915_READ(reg);
1821 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1822 I915_WRITE(reg, val);
1823 }
1824
1825 reg = PCH_TRANSCONF(pipe);
1826 val = I915_READ(reg);
1827 pipeconf_val = I915_READ(PIPECONF(pipe));
1828
1829 if (HAS_PCH_IBX(dev_priv)) {
1830 /*
1831 * Make the BPC in transcoder be consistent with
1832 * that in pipeconf reg. For HDMI we must use 8bpc
1833 * here for both 8bpc and 12bpc.
1834 */
1835 val &= ~PIPECONF_BPC_MASK;
1836 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1837 val |= PIPECONF_8BPC;
1838 else
1839 val |= pipeconf_val & PIPECONF_BPC_MASK;
1840 }
1841
1842 val &= ~TRANS_INTERLACE_MASK;
1843 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1844 if (HAS_PCH_IBX(dev_priv) &&
1845 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1846 val |= TRANS_LEGACY_INTERLACED_ILK;
1847 else
1848 val |= TRANS_INTERLACED;
1849 else
1850 val |= TRANS_PROGRESSIVE;
1851
1852 I915_WRITE(reg, val | TRANS_ENABLE);
1853 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1854 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1855 }
1856
1857 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1858 enum transcoder cpu_transcoder)
1859 {
1860 u32 val, pipeconf_val;
1861
1862 /* FDI must be feeding us bits for PCH ports */
1863 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1864 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1865
1866 /* Workaround: set timing override bit. */
1867 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1869 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870
1871 val = TRANS_ENABLE;
1872 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1873
1874 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1875 PIPECONF_INTERLACED_ILK)
1876 val |= TRANS_INTERLACED;
1877 else
1878 val |= TRANS_PROGRESSIVE;
1879
1880 I915_WRITE(LPT_TRANSCONF, val);
1881 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1882 DRM_ERROR("Failed to enable PCH transcoder\n");
1883 }
1884
1885 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 struct drm_device *dev = dev_priv->dev;
1889 i915_reg_t reg;
1890 uint32_t val;
1891
1892 /* FDI relies on the transcoder */
1893 assert_fdi_tx_disabled(dev_priv, pipe);
1894 assert_fdi_rx_disabled(dev_priv, pipe);
1895
1896 /* Ports must be off as well */
1897 assert_pch_ports_disabled(dev_priv, pipe);
1898
1899 reg = PCH_TRANSCONF(pipe);
1900 val = I915_READ(reg);
1901 val &= ~TRANS_ENABLE;
1902 I915_WRITE(reg, val);
1903 /* wait for PCH transcoder off, transcoder state */
1904 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1905 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1906
1907 if (HAS_PCH_CPT(dev)) {
1908 /* Workaround: Clear the timing override chicken bit again. */
1909 reg = TRANS_CHICKEN2(pipe);
1910 val = I915_READ(reg);
1911 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1912 I915_WRITE(reg, val);
1913 }
1914 }
1915
1916 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1917 {
1918 u32 val;
1919
1920 val = I915_READ(LPT_TRANSCONF);
1921 val &= ~TRANS_ENABLE;
1922 I915_WRITE(LPT_TRANSCONF, val);
1923 /* wait for PCH transcoder off, transcoder state */
1924 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1925 DRM_ERROR("Failed to disable PCH transcoder\n");
1926
1927 /* Workaround: clear timing override bit. */
1928 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1929 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1930 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1931 }
1932
1933 /**
1934 * intel_enable_pipe - enable a pipe, asserting requirements
1935 * @crtc: crtc responsible for the pipe
1936 *
1937 * Enable @crtc's pipe, making sure that various hardware specific requirements
1938 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1939 */
1940 static void intel_enable_pipe(struct intel_crtc *crtc)
1941 {
1942 struct drm_device *dev = crtc->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 enum pipe pipe = crtc->pipe;
1945 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1946 enum pipe pch_transcoder;
1947 i915_reg_t reg;
1948 u32 val;
1949
1950 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1951
1952 assert_planes_disabled(dev_priv, pipe);
1953 assert_cursor_disabled(dev_priv, pipe);
1954 assert_sprites_disabled(dev_priv, pipe);
1955
1956 if (HAS_PCH_LPT(dev_priv))
1957 pch_transcoder = TRANSCODER_A;
1958 else
1959 pch_transcoder = pipe;
1960
1961 /*
1962 * A pipe without a PLL won't actually be able to drive bits from
1963 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1964 * need the check.
1965 */
1966 if (HAS_GMCH_DISPLAY(dev_priv))
1967 if (crtc->config->has_dsi_encoder)
1968 assert_dsi_pll_enabled(dev_priv);
1969 else
1970 assert_pll_enabled(dev_priv, pipe);
1971 else {
1972 if (crtc->config->has_pch_encoder) {
1973 /* if driving the PCH, we need FDI enabled */
1974 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1975 assert_fdi_tx_pll_enabled(dev_priv,
1976 (enum pipe) cpu_transcoder);
1977 }
1978 /* FIXME: assert CPU port conditions for SNB+ */
1979 }
1980
1981 reg = PIPECONF(cpu_transcoder);
1982 val = I915_READ(reg);
1983 if (val & PIPECONF_ENABLE) {
1984 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1985 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1986 return;
1987 }
1988
1989 I915_WRITE(reg, val | PIPECONF_ENABLE);
1990 POSTING_READ(reg);
1991
1992 /*
1993 * Until the pipe starts DSL will read as 0, which would cause
1994 * an apparent vblank timestamp jump, which messes up also the
1995 * frame count when it's derived from the timestamps. So let's
1996 * wait for the pipe to start properly before we call
1997 * drm_crtc_vblank_on()
1998 */
1999 if (dev->max_vblank_count == 0 &&
2000 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2001 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2002 }
2003
2004 /**
2005 * intel_disable_pipe - disable a pipe, asserting requirements
2006 * @crtc: crtc whose pipes is to be disabled
2007 *
2008 * Disable the pipe of @crtc, making sure that various hardware
2009 * specific requirements are met, if applicable, e.g. plane
2010 * disabled, panel fitter off, etc.
2011 *
2012 * Will wait until the pipe has shut down before returning.
2013 */
2014 static void intel_disable_pipe(struct intel_crtc *crtc)
2015 {
2016 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2017 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2018 enum pipe pipe = crtc->pipe;
2019 i915_reg_t reg;
2020 u32 val;
2021
2022 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2023
2024 /*
2025 * Make sure planes won't keep trying to pump pixels to us,
2026 * or we might hang the display.
2027 */
2028 assert_planes_disabled(dev_priv, pipe);
2029 assert_cursor_disabled(dev_priv, pipe);
2030 assert_sprites_disabled(dev_priv, pipe);
2031
2032 reg = PIPECONF(cpu_transcoder);
2033 val = I915_READ(reg);
2034 if ((val & PIPECONF_ENABLE) == 0)
2035 return;
2036
2037 /*
2038 * Double wide has implications for planes
2039 * so best keep it disabled when not needed.
2040 */
2041 if (crtc->config->double_wide)
2042 val &= ~PIPECONF_DOUBLE_WIDE;
2043
2044 /* Don't disable pipe or pipe PLLs if needed */
2045 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2046 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2047 val &= ~PIPECONF_ENABLE;
2048
2049 I915_WRITE(reg, val);
2050 if ((val & PIPECONF_ENABLE) == 0)
2051 intel_wait_for_pipe_off(crtc);
2052 }
2053
2054 static bool need_vtd_wa(struct drm_device *dev)
2055 {
2056 #ifdef CONFIG_INTEL_IOMMU
2057 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2058 return true;
2059 #endif
2060 return false;
2061 }
2062
2063 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2064 {
2065 return IS_GEN2(dev_priv) ? 2048 : 4096;
2066 }
2067
2068 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2069 uint64_t fb_modifier, unsigned int cpp)
2070 {
2071 switch (fb_modifier) {
2072 case DRM_FORMAT_MOD_NONE:
2073 return cpp;
2074 case I915_FORMAT_MOD_X_TILED:
2075 if (IS_GEN2(dev_priv))
2076 return 128;
2077 else
2078 return 512;
2079 case I915_FORMAT_MOD_Y_TILED:
2080 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2081 return 128;
2082 else
2083 return 512;
2084 case I915_FORMAT_MOD_Yf_TILED:
2085 switch (cpp) {
2086 case 1:
2087 return 64;
2088 case 2:
2089 case 4:
2090 return 128;
2091 case 8:
2092 case 16:
2093 return 256;
2094 default:
2095 MISSING_CASE(cpp);
2096 return cpp;
2097 }
2098 break;
2099 default:
2100 MISSING_CASE(fb_modifier);
2101 return cpp;
2102 }
2103 }
2104
2105 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2106 uint64_t fb_modifier, unsigned int cpp)
2107 {
2108 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2109 return 1;
2110 else
2111 return intel_tile_size(dev_priv) /
2112 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2113 }
2114
2115 /* Return the tile dimensions in pixel units */
2116 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2117 unsigned int *tile_width,
2118 unsigned int *tile_height,
2119 uint64_t fb_modifier,
2120 unsigned int cpp)
2121 {
2122 unsigned int tile_width_bytes =
2123 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2124
2125 *tile_width = tile_width_bytes / cpp;
2126 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2127 }
2128
2129 unsigned int
2130 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2131 uint32_t pixel_format, uint64_t fb_modifier)
2132 {
2133 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2134 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2135
2136 return ALIGN(height, tile_height);
2137 }
2138
2139 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2140 {
2141 unsigned int size = 0;
2142 int i;
2143
2144 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2145 size += rot_info->plane[i].width * rot_info->plane[i].height;
2146
2147 return size;
2148 }
2149
2150 static void
2151 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2152 const struct drm_framebuffer *fb,
2153 unsigned int rotation)
2154 {
2155 if (intel_rotation_90_or_270(rotation)) {
2156 *view = i915_ggtt_view_rotated;
2157 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2158 } else {
2159 *view = i915_ggtt_view_normal;
2160 }
2161 }
2162
2163 static void
2164 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2165 struct drm_framebuffer *fb)
2166 {
2167 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2168 unsigned int tile_size, tile_width, tile_height, cpp;
2169
2170 tile_size = intel_tile_size(dev_priv);
2171
2172 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2173 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2174 fb->modifier[0], cpp);
2175
2176 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2177 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2178
2179 if (info->pixel_format == DRM_FORMAT_NV12) {
2180 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2181 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2182 fb->modifier[1], cpp);
2183
2184 info->uv_offset = fb->offsets[1];
2185 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2186 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2187 }
2188 }
2189
2190 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2191 {
2192 if (INTEL_INFO(dev_priv)->gen >= 9)
2193 return 256 * 1024;
2194 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2195 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2196 return 128 * 1024;
2197 else if (INTEL_INFO(dev_priv)->gen >= 4)
2198 return 4 * 1024;
2199 else
2200 return 0;
2201 }
2202
2203 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2204 uint64_t fb_modifier)
2205 {
2206 switch (fb_modifier) {
2207 case DRM_FORMAT_MOD_NONE:
2208 return intel_linear_alignment(dev_priv);
2209 case I915_FORMAT_MOD_X_TILED:
2210 if (INTEL_INFO(dev_priv)->gen >= 9)
2211 return 256 * 1024;
2212 return 0;
2213 case I915_FORMAT_MOD_Y_TILED:
2214 case I915_FORMAT_MOD_Yf_TILED:
2215 return 1 * 1024 * 1024;
2216 default:
2217 MISSING_CASE(fb_modifier);
2218 return 0;
2219 }
2220 }
2221
2222 int
2223 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2224 unsigned int rotation)
2225 {
2226 struct drm_device *dev = fb->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2229 struct i915_ggtt_view view;
2230 u32 alignment;
2231 int ret;
2232
2233 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2234
2235 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2236
2237 intel_fill_fb_ggtt_view(&view, fb, rotation);
2238
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2242 * the VT-d warning.
2243 */
2244 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2245 alignment = 256 * 1024;
2246
2247 /*
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2253 */
2254 intel_runtime_pm_get(dev_priv);
2255
2256 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2257 &view);
2258 if (ret)
2259 goto err_pm;
2260
2261 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262 * fence, whereas 965+ only requires a fence if using
2263 * framebuffer compression. For simplicity, we always install
2264 * a fence as the cost is not that onerous.
2265 */
2266 if (view.type == I915_GGTT_VIEW_NORMAL) {
2267 ret = i915_gem_object_get_fence(obj);
2268 if (ret == -EDEADLK) {
2269 /*
2270 * -EDEADLK means there are no free fences
2271 * no pending flips.
2272 *
2273 * This is propagated to atomic, but it uses
2274 * -EDEADLK to force a locking recovery, so
2275 * change the returned error to -EBUSY.
2276 */
2277 ret = -EBUSY;
2278 goto err_unpin;
2279 } else if (ret)
2280 goto err_unpin;
2281
2282 i915_gem_object_pin_fence(obj);
2283 }
2284
2285 intel_runtime_pm_put(dev_priv);
2286 return 0;
2287
2288 err_unpin:
2289 i915_gem_object_unpin_from_display_plane(obj, &view);
2290 err_pm:
2291 intel_runtime_pm_put(dev_priv);
2292 return ret;
2293 }
2294
2295 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2296 {
2297 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2298 struct i915_ggtt_view view;
2299
2300 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2301
2302 intel_fill_fb_ggtt_view(&view, fb, rotation);
2303
2304 if (view.type == I915_GGTT_VIEW_NORMAL)
2305 i915_gem_object_unpin_fence(obj);
2306
2307 i915_gem_object_unpin_from_display_plane(obj, &view);
2308 }
2309
2310 /*
2311 * Adjust the tile offset by moving the difference into
2312 * the x/y offsets.
2313 *
2314 * Input tile dimensions and pitch must already be
2315 * rotated to match x and y, and in pixel units.
2316 */
2317 static u32 intel_adjust_tile_offset(int *x, int *y,
2318 unsigned int tile_width,
2319 unsigned int tile_height,
2320 unsigned int tile_size,
2321 unsigned int pitch_tiles,
2322 u32 old_offset,
2323 u32 new_offset)
2324 {
2325 unsigned int tiles;
2326
2327 WARN_ON(old_offset & (tile_size - 1));
2328 WARN_ON(new_offset & (tile_size - 1));
2329 WARN_ON(new_offset > old_offset);
2330
2331 tiles = (old_offset - new_offset) / tile_size;
2332
2333 *y += tiles / pitch_tiles * tile_height;
2334 *x += tiles % pitch_tiles * tile_width;
2335
2336 return new_offset;
2337 }
2338
2339 /*
2340 * Computes the linear offset to the base tile and adjusts
2341 * x, y. bytes per pixel is assumed to be a power-of-two.
2342 *
2343 * In the 90/270 rotated case, x and y are assumed
2344 * to be already rotated to match the rotated GTT view, and
2345 * pitch is the tile_height aligned framebuffer height.
2346 */
2347 u32 intel_compute_tile_offset(int *x, int *y,
2348 const struct drm_framebuffer *fb, int plane,
2349 unsigned int pitch,
2350 unsigned int rotation)
2351 {
2352 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2353 uint64_t fb_modifier = fb->modifier[plane];
2354 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2355 u32 offset, offset_aligned, alignment;
2356
2357 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2358 if (alignment)
2359 alignment--;
2360
2361 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2362 unsigned int tile_size, tile_width, tile_height;
2363 unsigned int tile_rows, tiles, pitch_tiles;
2364
2365 tile_size = intel_tile_size(dev_priv);
2366 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2367 fb_modifier, cpp);
2368
2369 if (intel_rotation_90_or_270(rotation)) {
2370 pitch_tiles = pitch / tile_height;
2371 swap(tile_width, tile_height);
2372 } else {
2373 pitch_tiles = pitch / (tile_width * cpp);
2374 }
2375
2376 tile_rows = *y / tile_height;
2377 *y %= tile_height;
2378
2379 tiles = *x / tile_width;
2380 *x %= tile_width;
2381
2382 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2383 offset_aligned = offset & ~alignment;
2384
2385 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2386 tile_size, pitch_tiles,
2387 offset, offset_aligned);
2388 } else {
2389 offset = *y * pitch + *x * cpp;
2390 offset_aligned = offset & ~alignment;
2391
2392 *y = (offset & alignment) / pitch;
2393 *x = ((offset & alignment) - *y * pitch) / cpp;
2394 }
2395
2396 return offset_aligned;
2397 }
2398
2399 static int i9xx_format_to_fourcc(int format)
2400 {
2401 switch (format) {
2402 case DISPPLANE_8BPP:
2403 return DRM_FORMAT_C8;
2404 case DISPPLANE_BGRX555:
2405 return DRM_FORMAT_XRGB1555;
2406 case DISPPLANE_BGRX565:
2407 return DRM_FORMAT_RGB565;
2408 default:
2409 case DISPPLANE_BGRX888:
2410 return DRM_FORMAT_XRGB8888;
2411 case DISPPLANE_RGBX888:
2412 return DRM_FORMAT_XBGR8888;
2413 case DISPPLANE_BGRX101010:
2414 return DRM_FORMAT_XRGB2101010;
2415 case DISPPLANE_RGBX101010:
2416 return DRM_FORMAT_XBGR2101010;
2417 }
2418 }
2419
2420 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2421 {
2422 switch (format) {
2423 case PLANE_CTL_FORMAT_RGB_565:
2424 return DRM_FORMAT_RGB565;
2425 default:
2426 case PLANE_CTL_FORMAT_XRGB_8888:
2427 if (rgb_order) {
2428 if (alpha)
2429 return DRM_FORMAT_ABGR8888;
2430 else
2431 return DRM_FORMAT_XBGR8888;
2432 } else {
2433 if (alpha)
2434 return DRM_FORMAT_ARGB8888;
2435 else
2436 return DRM_FORMAT_XRGB8888;
2437 }
2438 case PLANE_CTL_FORMAT_XRGB_2101010:
2439 if (rgb_order)
2440 return DRM_FORMAT_XBGR2101010;
2441 else
2442 return DRM_FORMAT_XRGB2101010;
2443 }
2444 }
2445
2446 static bool
2447 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2448 struct intel_initial_plane_config *plane_config)
2449 {
2450 struct drm_device *dev = crtc->base.dev;
2451 struct drm_i915_private *dev_priv = to_i915(dev);
2452 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2453 struct drm_i915_gem_object *obj = NULL;
2454 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2455 struct drm_framebuffer *fb = &plane_config->fb->base;
2456 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2457 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2458 PAGE_SIZE);
2459
2460 size_aligned -= base_aligned;
2461
2462 if (plane_config->size == 0)
2463 return false;
2464
2465 /* If the FB is too big, just don't use it since fbdev is not very
2466 * important and we should probably use that space with FBC or other
2467 * features. */
2468 if (size_aligned * 2 > ggtt->stolen_usable_size)
2469 return false;
2470
2471 mutex_lock(&dev->struct_mutex);
2472
2473 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2474 base_aligned,
2475 base_aligned,
2476 size_aligned);
2477 if (!obj) {
2478 mutex_unlock(&dev->struct_mutex);
2479 return false;
2480 }
2481
2482 obj->tiling_mode = plane_config->tiling;
2483 if (obj->tiling_mode == I915_TILING_X)
2484 obj->stride = fb->pitches[0];
2485
2486 mode_cmd.pixel_format = fb->pixel_format;
2487 mode_cmd.width = fb->width;
2488 mode_cmd.height = fb->height;
2489 mode_cmd.pitches[0] = fb->pitches[0];
2490 mode_cmd.modifier[0] = fb->modifier[0];
2491 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2492
2493 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2494 &mode_cmd, obj)) {
2495 DRM_DEBUG_KMS("intel fb init failed\n");
2496 goto out_unref_obj;
2497 }
2498
2499 mutex_unlock(&dev->struct_mutex);
2500
2501 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2502 return true;
2503
2504 out_unref_obj:
2505 drm_gem_object_unreference(&obj->base);
2506 mutex_unlock(&dev->struct_mutex);
2507 return false;
2508 }
2509
2510 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2511 static void
2512 update_state_fb(struct drm_plane *plane)
2513 {
2514 if (plane->fb == plane->state->fb)
2515 return;
2516
2517 if (plane->state->fb)
2518 drm_framebuffer_unreference(plane->state->fb);
2519 plane->state->fb = plane->fb;
2520 if (plane->state->fb)
2521 drm_framebuffer_reference(plane->state->fb);
2522 }
2523
2524 static void
2525 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2526 struct intel_initial_plane_config *plane_config)
2527 {
2528 struct drm_device *dev = intel_crtc->base.dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct drm_crtc *c;
2531 struct intel_crtc *i;
2532 struct drm_i915_gem_object *obj;
2533 struct drm_plane *primary = intel_crtc->base.primary;
2534 struct drm_plane_state *plane_state = primary->state;
2535 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2536 struct intel_plane *intel_plane = to_intel_plane(primary);
2537 struct intel_plane_state *intel_state =
2538 to_intel_plane_state(plane_state);
2539 struct drm_framebuffer *fb;
2540
2541 if (!plane_config->fb)
2542 return;
2543
2544 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2545 fb = &plane_config->fb->base;
2546 goto valid_fb;
2547 }
2548
2549 kfree(plane_config->fb);
2550
2551 /*
2552 * Failed to alloc the obj, check to see if we should share
2553 * an fb with another CRTC instead
2554 */
2555 for_each_crtc(dev, c) {
2556 i = to_intel_crtc(c);
2557
2558 if (c == &intel_crtc->base)
2559 continue;
2560
2561 if (!i->active)
2562 continue;
2563
2564 fb = c->primary->fb;
2565 if (!fb)
2566 continue;
2567
2568 obj = intel_fb_obj(fb);
2569 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2570 drm_framebuffer_reference(fb);
2571 goto valid_fb;
2572 }
2573 }
2574
2575 /*
2576 * We've failed to reconstruct the BIOS FB. Current display state
2577 * indicates that the primary plane is visible, but has a NULL FB,
2578 * which will lead to problems later if we don't fix it up. The
2579 * simplest solution is to just disable the primary plane now and
2580 * pretend the BIOS never had it enabled.
2581 */
2582 to_intel_plane_state(plane_state)->visible = false;
2583 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2584 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2585 intel_plane->disable_plane(primary, &intel_crtc->base);
2586
2587 return;
2588
2589 valid_fb:
2590 plane_state->src_x = 0;
2591 plane_state->src_y = 0;
2592 plane_state->src_w = fb->width << 16;
2593 plane_state->src_h = fb->height << 16;
2594
2595 plane_state->crtc_x = 0;
2596 plane_state->crtc_y = 0;
2597 plane_state->crtc_w = fb->width;
2598 plane_state->crtc_h = fb->height;
2599
2600 intel_state->src.x1 = plane_state->src_x;
2601 intel_state->src.y1 = plane_state->src_y;
2602 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2603 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2604 intel_state->dst.x1 = plane_state->crtc_x;
2605 intel_state->dst.y1 = plane_state->crtc_y;
2606 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2607 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2608
2609 obj = intel_fb_obj(fb);
2610 if (obj->tiling_mode != I915_TILING_NONE)
2611 dev_priv->preserve_bios_swizzle = true;
2612
2613 drm_framebuffer_reference(fb);
2614 primary->fb = primary->state->fb = fb;
2615 primary->crtc = primary->state->crtc = &intel_crtc->base;
2616 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2617 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2618 }
2619
2620 static void i9xx_update_primary_plane(struct drm_plane *primary,
2621 const struct intel_crtc_state *crtc_state,
2622 const struct intel_plane_state *plane_state)
2623 {
2624 struct drm_device *dev = primary->dev;
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2627 struct drm_framebuffer *fb = plane_state->base.fb;
2628 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2629 int plane = intel_crtc->plane;
2630 u32 linear_offset;
2631 u32 dspcntr;
2632 i915_reg_t reg = DSPCNTR(plane);
2633 unsigned int rotation = plane_state->base.rotation;
2634 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2635 int x = plane_state->src.x1 >> 16;
2636 int y = plane_state->src.y1 >> 16;
2637
2638 dspcntr = DISPPLANE_GAMMA_ENABLE;
2639
2640 dspcntr |= DISPLAY_PLANE_ENABLE;
2641
2642 if (INTEL_INFO(dev)->gen < 4) {
2643 if (intel_crtc->pipe == PIPE_B)
2644 dspcntr |= DISPPLANE_SEL_PIPE_B;
2645
2646 /* pipesrc and dspsize control the size that is scaled from,
2647 * which should always be the user's requested size.
2648 */
2649 I915_WRITE(DSPSIZE(plane),
2650 ((crtc_state->pipe_src_h - 1) << 16) |
2651 (crtc_state->pipe_src_w - 1));
2652 I915_WRITE(DSPPOS(plane), 0);
2653 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2654 I915_WRITE(PRIMSIZE(plane),
2655 ((crtc_state->pipe_src_h - 1) << 16) |
2656 (crtc_state->pipe_src_w - 1));
2657 I915_WRITE(PRIMPOS(plane), 0);
2658 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2659 }
2660
2661 switch (fb->pixel_format) {
2662 case DRM_FORMAT_C8:
2663 dspcntr |= DISPPLANE_8BPP;
2664 break;
2665 case DRM_FORMAT_XRGB1555:
2666 dspcntr |= DISPPLANE_BGRX555;
2667 break;
2668 case DRM_FORMAT_RGB565:
2669 dspcntr |= DISPPLANE_BGRX565;
2670 break;
2671 case DRM_FORMAT_XRGB8888:
2672 dspcntr |= DISPPLANE_BGRX888;
2673 break;
2674 case DRM_FORMAT_XBGR8888:
2675 dspcntr |= DISPPLANE_RGBX888;
2676 break;
2677 case DRM_FORMAT_XRGB2101010:
2678 dspcntr |= DISPPLANE_BGRX101010;
2679 break;
2680 case DRM_FORMAT_XBGR2101010:
2681 dspcntr |= DISPPLANE_RGBX101010;
2682 break;
2683 default:
2684 BUG();
2685 }
2686
2687 if (INTEL_INFO(dev)->gen >= 4 &&
2688 obj->tiling_mode != I915_TILING_NONE)
2689 dspcntr |= DISPPLANE_TILED;
2690
2691 if (IS_G4X(dev))
2692 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2693
2694 linear_offset = y * fb->pitches[0] + x * cpp;
2695
2696 if (INTEL_INFO(dev)->gen >= 4) {
2697 intel_crtc->dspaddr_offset =
2698 intel_compute_tile_offset(&x, &y, fb, 0,
2699 fb->pitches[0], rotation);
2700 linear_offset -= intel_crtc->dspaddr_offset;
2701 } else {
2702 intel_crtc->dspaddr_offset = linear_offset;
2703 }
2704
2705 if (rotation == BIT(DRM_ROTATE_180)) {
2706 dspcntr |= DISPPLANE_ROTATE_180;
2707
2708 x += (crtc_state->pipe_src_w - 1);
2709 y += (crtc_state->pipe_src_h - 1);
2710
2711 /* Finding the last pixel of the last line of the display
2712 data and adding to linear_offset*/
2713 linear_offset +=
2714 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2715 (crtc_state->pipe_src_w - 1) * cpp;
2716 }
2717
2718 intel_crtc->adjusted_x = x;
2719 intel_crtc->adjusted_y = y;
2720
2721 I915_WRITE(reg, dspcntr);
2722
2723 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2724 if (INTEL_INFO(dev)->gen >= 4) {
2725 I915_WRITE(DSPSURF(plane),
2726 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2727 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2728 I915_WRITE(DSPLINOFF(plane), linear_offset);
2729 } else
2730 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2731 POSTING_READ(reg);
2732 }
2733
2734 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2735 struct drm_crtc *crtc)
2736 {
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int plane = intel_crtc->plane;
2741
2742 I915_WRITE(DSPCNTR(plane), 0);
2743 if (INTEL_INFO(dev_priv)->gen >= 4)
2744 I915_WRITE(DSPSURF(plane), 0);
2745 else
2746 I915_WRITE(DSPADDR(plane), 0);
2747 POSTING_READ(DSPCNTR(plane));
2748 }
2749
2750 static void ironlake_update_primary_plane(struct drm_plane *primary,
2751 const struct intel_crtc_state *crtc_state,
2752 const struct intel_plane_state *plane_state)
2753 {
2754 struct drm_device *dev = primary->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2757 struct drm_framebuffer *fb = plane_state->base.fb;
2758 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2759 int plane = intel_crtc->plane;
2760 u32 linear_offset;
2761 u32 dspcntr;
2762 i915_reg_t reg = DSPCNTR(plane);
2763 unsigned int rotation = plane_state->base.rotation;
2764 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2765 int x = plane_state->src.x1 >> 16;
2766 int y = plane_state->src.y1 >> 16;
2767
2768 dspcntr = DISPPLANE_GAMMA_ENABLE;
2769 dspcntr |= DISPLAY_PLANE_ENABLE;
2770
2771 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2772 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2773
2774 switch (fb->pixel_format) {
2775 case DRM_FORMAT_C8:
2776 dspcntr |= DISPPLANE_8BPP;
2777 break;
2778 case DRM_FORMAT_RGB565:
2779 dspcntr |= DISPPLANE_BGRX565;
2780 break;
2781 case DRM_FORMAT_XRGB8888:
2782 dspcntr |= DISPPLANE_BGRX888;
2783 break;
2784 case DRM_FORMAT_XBGR8888:
2785 dspcntr |= DISPPLANE_RGBX888;
2786 break;
2787 case DRM_FORMAT_XRGB2101010:
2788 dspcntr |= DISPPLANE_BGRX101010;
2789 break;
2790 case DRM_FORMAT_XBGR2101010:
2791 dspcntr |= DISPPLANE_RGBX101010;
2792 break;
2793 default:
2794 BUG();
2795 }
2796
2797 if (obj->tiling_mode != I915_TILING_NONE)
2798 dspcntr |= DISPPLANE_TILED;
2799
2800 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2801 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2802
2803 linear_offset = y * fb->pitches[0] + x * cpp;
2804 intel_crtc->dspaddr_offset =
2805 intel_compute_tile_offset(&x, &y, fb, 0,
2806 fb->pitches[0], rotation);
2807 linear_offset -= intel_crtc->dspaddr_offset;
2808 if (rotation == BIT(DRM_ROTATE_180)) {
2809 dspcntr |= DISPPLANE_ROTATE_180;
2810
2811 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2812 x += (crtc_state->pipe_src_w - 1);
2813 y += (crtc_state->pipe_src_h - 1);
2814
2815 /* Finding the last pixel of the last line of the display
2816 data and adding to linear_offset*/
2817 linear_offset +=
2818 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2819 (crtc_state->pipe_src_w - 1) * cpp;
2820 }
2821 }
2822
2823 intel_crtc->adjusted_x = x;
2824 intel_crtc->adjusted_y = y;
2825
2826 I915_WRITE(reg, dspcntr);
2827
2828 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2829 I915_WRITE(DSPSURF(plane),
2830 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2831 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2832 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2833 } else {
2834 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2835 I915_WRITE(DSPLINOFF(plane), linear_offset);
2836 }
2837 POSTING_READ(reg);
2838 }
2839
2840 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2841 uint64_t fb_modifier, uint32_t pixel_format)
2842 {
2843 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2844 return 64;
2845 } else {
2846 int cpp = drm_format_plane_cpp(pixel_format, 0);
2847
2848 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2849 }
2850 }
2851
2852 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2853 struct drm_i915_gem_object *obj,
2854 unsigned int plane)
2855 {
2856 struct i915_ggtt_view view;
2857 struct i915_vma *vma;
2858 u64 offset;
2859
2860 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2861 intel_plane->base.state->rotation);
2862
2863 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2864 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2865 view.type))
2866 return -1;
2867
2868 offset = vma->node.start;
2869
2870 if (plane == 1) {
2871 offset += vma->ggtt_view.params.rotated.uv_start_page *
2872 PAGE_SIZE;
2873 }
2874
2875 WARN_ON(upper_32_bits(offset));
2876
2877 return lower_32_bits(offset);
2878 }
2879
2880 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2881 {
2882 struct drm_device *dev = intel_crtc->base.dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884
2885 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2886 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2887 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2888 }
2889
2890 /*
2891 * This function detaches (aka. unbinds) unused scalers in hardware
2892 */
2893 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2894 {
2895 struct intel_crtc_scaler_state *scaler_state;
2896 int i;
2897
2898 scaler_state = &intel_crtc->config->scaler_state;
2899
2900 /* loop through and disable scalers that aren't in use */
2901 for (i = 0; i < intel_crtc->num_scalers; i++) {
2902 if (!scaler_state->scalers[i].in_use)
2903 skl_detach_scaler(intel_crtc, i);
2904 }
2905 }
2906
2907 u32 skl_plane_ctl_format(uint32_t pixel_format)
2908 {
2909 switch (pixel_format) {
2910 case DRM_FORMAT_C8:
2911 return PLANE_CTL_FORMAT_INDEXED;
2912 case DRM_FORMAT_RGB565:
2913 return PLANE_CTL_FORMAT_RGB_565;
2914 case DRM_FORMAT_XBGR8888:
2915 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2916 case DRM_FORMAT_XRGB8888:
2917 return PLANE_CTL_FORMAT_XRGB_8888;
2918 /*
2919 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2920 * to be already pre-multiplied. We need to add a knob (or a different
2921 * DRM_FORMAT) for user-space to configure that.
2922 */
2923 case DRM_FORMAT_ABGR8888:
2924 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2925 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2926 case DRM_FORMAT_ARGB8888:
2927 return PLANE_CTL_FORMAT_XRGB_8888 |
2928 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2929 case DRM_FORMAT_XRGB2101010:
2930 return PLANE_CTL_FORMAT_XRGB_2101010;
2931 case DRM_FORMAT_XBGR2101010:
2932 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2933 case DRM_FORMAT_YUYV:
2934 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2935 case DRM_FORMAT_YVYU:
2936 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2937 case DRM_FORMAT_UYVY:
2938 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2939 case DRM_FORMAT_VYUY:
2940 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2941 default:
2942 MISSING_CASE(pixel_format);
2943 }
2944
2945 return 0;
2946 }
2947
2948 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2949 {
2950 switch (fb_modifier) {
2951 case DRM_FORMAT_MOD_NONE:
2952 break;
2953 case I915_FORMAT_MOD_X_TILED:
2954 return PLANE_CTL_TILED_X;
2955 case I915_FORMAT_MOD_Y_TILED:
2956 return PLANE_CTL_TILED_Y;
2957 case I915_FORMAT_MOD_Yf_TILED:
2958 return PLANE_CTL_TILED_YF;
2959 default:
2960 MISSING_CASE(fb_modifier);
2961 }
2962
2963 return 0;
2964 }
2965
2966 u32 skl_plane_ctl_rotation(unsigned int rotation)
2967 {
2968 switch (rotation) {
2969 case BIT(DRM_ROTATE_0):
2970 break;
2971 /*
2972 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2973 * while i915 HW rotation is clockwise, thats why this swapping.
2974 */
2975 case BIT(DRM_ROTATE_90):
2976 return PLANE_CTL_ROTATE_270;
2977 case BIT(DRM_ROTATE_180):
2978 return PLANE_CTL_ROTATE_180;
2979 case BIT(DRM_ROTATE_270):
2980 return PLANE_CTL_ROTATE_90;
2981 default:
2982 MISSING_CASE(rotation);
2983 }
2984
2985 return 0;
2986 }
2987
2988 static void skylake_update_primary_plane(struct drm_plane *plane,
2989 const struct intel_crtc_state *crtc_state,
2990 const struct intel_plane_state *plane_state)
2991 {
2992 struct drm_device *dev = plane->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2995 struct drm_framebuffer *fb = plane_state->base.fb;
2996 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2997 int pipe = intel_crtc->pipe;
2998 u32 plane_ctl, stride_div, stride;
2999 u32 tile_height, plane_offset, plane_size;
3000 unsigned int rotation = plane_state->base.rotation;
3001 int x_offset, y_offset;
3002 u32 surf_addr;
3003 int scaler_id = plane_state->scaler_id;
3004 int src_x = plane_state->src.x1 >> 16;
3005 int src_y = plane_state->src.y1 >> 16;
3006 int src_w = drm_rect_width(&plane_state->src) >> 16;
3007 int src_h = drm_rect_height(&plane_state->src) >> 16;
3008 int dst_x = plane_state->dst.x1;
3009 int dst_y = plane_state->dst.y1;
3010 int dst_w = drm_rect_width(&plane_state->dst);
3011 int dst_h = drm_rect_height(&plane_state->dst);
3012
3013 plane_ctl = PLANE_CTL_ENABLE |
3014 PLANE_CTL_PIPE_GAMMA_ENABLE |
3015 PLANE_CTL_PIPE_CSC_ENABLE;
3016
3017 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3018 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3019 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3020 plane_ctl |= skl_plane_ctl_rotation(rotation);
3021
3022 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3023 fb->pixel_format);
3024 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3025
3026 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3027
3028 if (intel_rotation_90_or_270(rotation)) {
3029 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3030
3031 /* stride = Surface height in tiles */
3032 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3033 stride = DIV_ROUND_UP(fb->height, tile_height);
3034 x_offset = stride * tile_height - src_y - src_h;
3035 y_offset = src_x;
3036 plane_size = (src_w - 1) << 16 | (src_h - 1);
3037 } else {
3038 stride = fb->pitches[0] / stride_div;
3039 x_offset = src_x;
3040 y_offset = src_y;
3041 plane_size = (src_h - 1) << 16 | (src_w - 1);
3042 }
3043 plane_offset = y_offset << 16 | x_offset;
3044
3045 intel_crtc->adjusted_x = x_offset;
3046 intel_crtc->adjusted_y = y_offset;
3047
3048 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3049 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3050 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3051 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3052
3053 if (scaler_id >= 0) {
3054 uint32_t ps_ctrl = 0;
3055
3056 WARN_ON(!dst_w || !dst_h);
3057 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3058 crtc_state->scaler_state.scalers[scaler_id].mode;
3059 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3060 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3061 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3062 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3063 I915_WRITE(PLANE_POS(pipe, 0), 0);
3064 } else {
3065 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3066 }
3067
3068 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3069
3070 POSTING_READ(PLANE_SURF(pipe, 0));
3071 }
3072
3073 static void skylake_disable_primary_plane(struct drm_plane *primary,
3074 struct drm_crtc *crtc)
3075 {
3076 struct drm_device *dev = crtc->dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 int pipe = to_intel_crtc(crtc)->pipe;
3079
3080 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3081 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3082 POSTING_READ(PLANE_SURF(pipe, 0));
3083 }
3084
3085 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3086 static int
3087 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3088 int x, int y, enum mode_set_atomic state)
3089 {
3090 /* Support for kgdboc is disabled, this needs a major rework. */
3091 DRM_ERROR("legacy panic handler not supported any more.\n");
3092
3093 return -ENODEV;
3094 }
3095
3096 static void intel_complete_page_flips(struct drm_device *dev)
3097 {
3098 struct drm_crtc *crtc;
3099
3100 for_each_crtc(dev, crtc) {
3101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102 enum plane plane = intel_crtc->plane;
3103
3104 intel_prepare_page_flip(dev, plane);
3105 intel_finish_page_flip_plane(dev, plane);
3106 }
3107 }
3108
3109 static void intel_update_primary_planes(struct drm_device *dev)
3110 {
3111 struct drm_crtc *crtc;
3112
3113 for_each_crtc(dev, crtc) {
3114 struct intel_plane *plane = to_intel_plane(crtc->primary);
3115 struct intel_plane_state *plane_state;
3116
3117 drm_modeset_lock_crtc(crtc, &plane->base);
3118 plane_state = to_intel_plane_state(plane->base.state);
3119
3120 if (plane_state->visible)
3121 plane->update_plane(&plane->base,
3122 to_intel_crtc_state(crtc->state),
3123 plane_state);
3124
3125 drm_modeset_unlock_crtc(crtc);
3126 }
3127 }
3128
3129 void intel_prepare_reset(struct drm_device *dev)
3130 {
3131 /* no reset support for gen2 */
3132 if (IS_GEN2(dev))
3133 return;
3134
3135 /* reset doesn't touch the display */
3136 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3137 return;
3138
3139 drm_modeset_lock_all(dev);
3140 /*
3141 * Disabling the crtcs gracefully seems nicer. Also the
3142 * g33 docs say we should at least disable all the planes.
3143 */
3144 intel_display_suspend(dev);
3145 }
3146
3147 void intel_finish_reset(struct drm_device *dev)
3148 {
3149 struct drm_i915_private *dev_priv = to_i915(dev);
3150
3151 /*
3152 * Flips in the rings will be nuked by the reset,
3153 * so complete all pending flips so that user space
3154 * will get its events and not get stuck.
3155 */
3156 intel_complete_page_flips(dev);
3157
3158 /* no reset support for gen2 */
3159 if (IS_GEN2(dev))
3160 return;
3161
3162 /* reset doesn't touch the display */
3163 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3164 /*
3165 * Flips in the rings have been nuked by the reset,
3166 * so update the base address of all primary
3167 * planes to the the last fb to make sure we're
3168 * showing the correct fb after a reset.
3169 *
3170 * FIXME: Atomic will make this obsolete since we won't schedule
3171 * CS-based flips (which might get lost in gpu resets) any more.
3172 */
3173 intel_update_primary_planes(dev);
3174 return;
3175 }
3176
3177 /*
3178 * The display has been reset as well,
3179 * so need a full re-initialization.
3180 */
3181 intel_runtime_pm_disable_interrupts(dev_priv);
3182 intel_runtime_pm_enable_interrupts(dev_priv);
3183
3184 intel_modeset_init_hw(dev);
3185
3186 spin_lock_irq(&dev_priv->irq_lock);
3187 if (dev_priv->display.hpd_irq_setup)
3188 dev_priv->display.hpd_irq_setup(dev);
3189 spin_unlock_irq(&dev_priv->irq_lock);
3190
3191 intel_display_resume(dev);
3192
3193 intel_hpd_init(dev_priv);
3194
3195 drm_modeset_unlock_all(dev);
3196 }
3197
3198 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3199 {
3200 struct drm_device *dev = crtc->dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3203 bool pending;
3204
3205 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3206 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3207 return false;
3208
3209 spin_lock_irq(&dev->event_lock);
3210 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3211 spin_unlock_irq(&dev->event_lock);
3212
3213 return pending;
3214 }
3215
3216 static void intel_update_pipe_config(struct intel_crtc *crtc,
3217 struct intel_crtc_state *old_crtc_state)
3218 {
3219 struct drm_device *dev = crtc->base.dev;
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3221 struct intel_crtc_state *pipe_config =
3222 to_intel_crtc_state(crtc->base.state);
3223
3224 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3225 crtc->base.mode = crtc->base.state->mode;
3226
3227 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3228 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3229 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3230
3231 /*
3232 * Update pipe size and adjust fitter if needed: the reason for this is
3233 * that in compute_mode_changes we check the native mode (not the pfit
3234 * mode) to see if we can flip rather than do a full mode set. In the
3235 * fastboot case, we'll flip, but if we don't update the pipesrc and
3236 * pfit state, we'll end up with a big fb scanned out into the wrong
3237 * sized surface.
3238 */
3239
3240 I915_WRITE(PIPESRC(crtc->pipe),
3241 ((pipe_config->pipe_src_w - 1) << 16) |
3242 (pipe_config->pipe_src_h - 1));
3243
3244 /* on skylake this is done by detaching scalers */
3245 if (INTEL_INFO(dev)->gen >= 9) {
3246 skl_detach_scalers(crtc);
3247
3248 if (pipe_config->pch_pfit.enabled)
3249 skylake_pfit_enable(crtc);
3250 } else if (HAS_PCH_SPLIT(dev)) {
3251 if (pipe_config->pch_pfit.enabled)
3252 ironlake_pfit_enable(crtc);
3253 else if (old_crtc_state->pch_pfit.enabled)
3254 ironlake_pfit_disable(crtc, true);
3255 }
3256 }
3257
3258 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3259 {
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3263 int pipe = intel_crtc->pipe;
3264 i915_reg_t reg;
3265 u32 temp;
3266
3267 /* enable normal train */
3268 reg = FDI_TX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 if (IS_IVYBRIDGE(dev)) {
3271 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3272 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3273 } else {
3274 temp &= ~FDI_LINK_TRAIN_NONE;
3275 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3276 }
3277 I915_WRITE(reg, temp);
3278
3279 reg = FDI_RX_CTL(pipe);
3280 temp = I915_READ(reg);
3281 if (HAS_PCH_CPT(dev)) {
3282 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3283 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3284 } else {
3285 temp &= ~FDI_LINK_TRAIN_NONE;
3286 temp |= FDI_LINK_TRAIN_NONE;
3287 }
3288 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3289
3290 /* wait one idle pattern time */
3291 POSTING_READ(reg);
3292 udelay(1000);
3293
3294 /* IVB wants error correction enabled */
3295 if (IS_IVYBRIDGE(dev))
3296 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3297 FDI_FE_ERRC_ENABLE);
3298 }
3299
3300 /* The FDI link training functions for ILK/Ibexpeak. */
3301 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306 int pipe = intel_crtc->pipe;
3307 i915_reg_t reg;
3308 u32 temp, tries;
3309
3310 /* FDI needs bits from pipe first */
3311 assert_pipe_enabled(dev_priv, pipe);
3312
3313 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3314 for train result */
3315 reg = FDI_RX_IMR(pipe);
3316 temp = I915_READ(reg);
3317 temp &= ~FDI_RX_SYMBOL_LOCK;
3318 temp &= ~FDI_RX_BIT_LOCK;
3319 I915_WRITE(reg, temp);
3320 I915_READ(reg);
3321 udelay(150);
3322
3323 /* enable CPU FDI TX and PCH FDI RX */
3324 reg = FDI_TX_CTL(pipe);
3325 temp = I915_READ(reg);
3326 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3327 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3328 temp &= ~FDI_LINK_TRAIN_NONE;
3329 temp |= FDI_LINK_TRAIN_PATTERN_1;
3330 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3331
3332 reg = FDI_RX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_LINK_TRAIN_NONE;
3335 temp |= FDI_LINK_TRAIN_PATTERN_1;
3336 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3337
3338 POSTING_READ(reg);
3339 udelay(150);
3340
3341 /* Ironlake workaround, enable clock pointer after FDI enable*/
3342 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3343 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3344 FDI_RX_PHASE_SYNC_POINTER_EN);
3345
3346 reg = FDI_RX_IIR(pipe);
3347 for (tries = 0; tries < 5; tries++) {
3348 temp = I915_READ(reg);
3349 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350
3351 if ((temp & FDI_RX_BIT_LOCK)) {
3352 DRM_DEBUG_KMS("FDI train 1 done.\n");
3353 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3354 break;
3355 }
3356 }
3357 if (tries == 5)
3358 DRM_ERROR("FDI train 1 fail!\n");
3359
3360 /* Train 2 */
3361 reg = FDI_TX_CTL(pipe);
3362 temp = I915_READ(reg);
3363 temp &= ~FDI_LINK_TRAIN_NONE;
3364 temp |= FDI_LINK_TRAIN_PATTERN_2;
3365 I915_WRITE(reg, temp);
3366
3367 reg = FDI_RX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 temp &= ~FDI_LINK_TRAIN_NONE;
3370 temp |= FDI_LINK_TRAIN_PATTERN_2;
3371 I915_WRITE(reg, temp);
3372
3373 POSTING_READ(reg);
3374 udelay(150);
3375
3376 reg = FDI_RX_IIR(pipe);
3377 for (tries = 0; tries < 5; tries++) {
3378 temp = I915_READ(reg);
3379 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3380
3381 if (temp & FDI_RX_SYMBOL_LOCK) {
3382 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3383 DRM_DEBUG_KMS("FDI train 2 done.\n");
3384 break;
3385 }
3386 }
3387 if (tries == 5)
3388 DRM_ERROR("FDI train 2 fail!\n");
3389
3390 DRM_DEBUG_KMS("FDI train done\n");
3391
3392 }
3393
3394 static const int snb_b_fdi_train_param[] = {
3395 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3396 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3397 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3398 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3399 };
3400
3401 /* The FDI link training functions for SNB/Cougarpoint. */
3402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3403 {
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 int pipe = intel_crtc->pipe;
3408 i915_reg_t reg;
3409 u32 temp, i, retry;
3410
3411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3412 for train result */
3413 reg = FDI_RX_IMR(pipe);
3414 temp = I915_READ(reg);
3415 temp &= ~FDI_RX_SYMBOL_LOCK;
3416 temp &= ~FDI_RX_BIT_LOCK;
3417 I915_WRITE(reg, temp);
3418
3419 POSTING_READ(reg);
3420 udelay(150);
3421
3422 /* enable CPU FDI TX and PCH FDI RX */
3423 reg = FDI_TX_CTL(pipe);
3424 temp = I915_READ(reg);
3425 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3426 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3427 temp &= ~FDI_LINK_TRAIN_NONE;
3428 temp |= FDI_LINK_TRAIN_PATTERN_1;
3429 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3430 /* SNB-B */
3431 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3432 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3433
3434 I915_WRITE(FDI_RX_MISC(pipe),
3435 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3436
3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 if (HAS_PCH_CPT(dev)) {
3440 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3441 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3442 } else {
3443 temp &= ~FDI_LINK_TRAIN_NONE;
3444 temp |= FDI_LINK_TRAIN_PATTERN_1;
3445 }
3446 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3447
3448 POSTING_READ(reg);
3449 udelay(150);
3450
3451 for (i = 0; i < 4; i++) {
3452 reg = FDI_TX_CTL(pipe);
3453 temp = I915_READ(reg);
3454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3455 temp |= snb_b_fdi_train_param[i];
3456 I915_WRITE(reg, temp);
3457
3458 POSTING_READ(reg);
3459 udelay(500);
3460
3461 for (retry = 0; retry < 5; retry++) {
3462 reg = FDI_RX_IIR(pipe);
3463 temp = I915_READ(reg);
3464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465 if (temp & FDI_RX_BIT_LOCK) {
3466 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3467 DRM_DEBUG_KMS("FDI train 1 done.\n");
3468 break;
3469 }
3470 udelay(50);
3471 }
3472 if (retry < 5)
3473 break;
3474 }
3475 if (i == 4)
3476 DRM_ERROR("FDI train 1 fail!\n");
3477
3478 /* Train 2 */
3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~FDI_LINK_TRAIN_NONE;
3482 temp |= FDI_LINK_TRAIN_PATTERN_2;
3483 if (IS_GEN6(dev)) {
3484 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3485 /* SNB-B */
3486 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3487 }
3488 I915_WRITE(reg, temp);
3489
3490 reg = FDI_RX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 if (HAS_PCH_CPT(dev)) {
3493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3494 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3495 } else {
3496 temp &= ~FDI_LINK_TRAIN_NONE;
3497 temp |= FDI_LINK_TRAIN_PATTERN_2;
3498 }
3499 I915_WRITE(reg, temp);
3500
3501 POSTING_READ(reg);
3502 udelay(150);
3503
3504 for (i = 0; i < 4; i++) {
3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508 temp |= snb_b_fdi_train_param[i];
3509 I915_WRITE(reg, temp);
3510
3511 POSTING_READ(reg);
3512 udelay(500);
3513
3514 for (retry = 0; retry < 5; retry++) {
3515 reg = FDI_RX_IIR(pipe);
3516 temp = I915_READ(reg);
3517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3518 if (temp & FDI_RX_SYMBOL_LOCK) {
3519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520 DRM_DEBUG_KMS("FDI train 2 done.\n");
3521 break;
3522 }
3523 udelay(50);
3524 }
3525 if (retry < 5)
3526 break;
3527 }
3528 if (i == 4)
3529 DRM_ERROR("FDI train 2 fail!\n");
3530
3531 DRM_DEBUG_KMS("FDI train done.\n");
3532 }
3533
3534 /* Manual link training for Ivy Bridge A0 parts */
3535 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3536 {
3537 struct drm_device *dev = crtc->dev;
3538 struct drm_i915_private *dev_priv = dev->dev_private;
3539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540 int pipe = intel_crtc->pipe;
3541 i915_reg_t reg;
3542 u32 temp, i, j;
3543
3544 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3545 for train result */
3546 reg = FDI_RX_IMR(pipe);
3547 temp = I915_READ(reg);
3548 temp &= ~FDI_RX_SYMBOL_LOCK;
3549 temp &= ~FDI_RX_BIT_LOCK;
3550 I915_WRITE(reg, temp);
3551
3552 POSTING_READ(reg);
3553 udelay(150);
3554
3555 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3556 I915_READ(FDI_RX_IIR(pipe)));
3557
3558 /* Try each vswing and preemphasis setting twice before moving on */
3559 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3560 /* disable first in case we need to retry */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3564 temp &= ~FDI_TX_ENABLE;
3565 I915_WRITE(reg, temp);
3566
3567 reg = FDI_RX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_LINK_TRAIN_AUTO;
3570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571 temp &= ~FDI_RX_ENABLE;
3572 I915_WRITE(reg, temp);
3573
3574 /* enable CPU FDI TX and PCH FDI RX */
3575 reg = FDI_TX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3578 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3581 temp |= snb_b_fdi_train_param[j/2];
3582 temp |= FDI_COMPOSITE_SYNC;
3583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3584
3585 I915_WRITE(FDI_RX_MISC(pipe),
3586 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3587
3588 reg = FDI_RX_CTL(pipe);
3589 temp = I915_READ(reg);
3590 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3591 temp |= FDI_COMPOSITE_SYNC;
3592 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3593
3594 POSTING_READ(reg);
3595 udelay(1); /* should be 0.5us */
3596
3597 for (i = 0; i < 4; i++) {
3598 reg = FDI_RX_IIR(pipe);
3599 temp = I915_READ(reg);
3600 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3601
3602 if (temp & FDI_RX_BIT_LOCK ||
3603 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3604 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3606 i);
3607 break;
3608 }
3609 udelay(1); /* should be 0.5us */
3610 }
3611 if (i == 4) {
3612 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3613 continue;
3614 }
3615
3616 /* Train 2 */
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3620 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3621 I915_WRITE(reg, temp);
3622
3623 reg = FDI_RX_CTL(pipe);
3624 temp = I915_READ(reg);
3625 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3626 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3627 I915_WRITE(reg, temp);
3628
3629 POSTING_READ(reg);
3630 udelay(2); /* should be 1.5us */
3631
3632 for (i = 0; i < 4; i++) {
3633 reg = FDI_RX_IIR(pipe);
3634 temp = I915_READ(reg);
3635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3636
3637 if (temp & FDI_RX_SYMBOL_LOCK ||
3638 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3639 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3641 i);
3642 goto train_done;
3643 }
3644 udelay(2); /* should be 1.5us */
3645 }
3646 if (i == 4)
3647 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3648 }
3649
3650 train_done:
3651 DRM_DEBUG_KMS("FDI train done.\n");
3652 }
3653
3654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3655 {
3656 struct drm_device *dev = intel_crtc->base.dev;
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 int pipe = intel_crtc->pipe;
3659 i915_reg_t reg;
3660 u32 temp;
3661
3662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3663 reg = FDI_RX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3669
3670 POSTING_READ(reg);
3671 udelay(200);
3672
3673 /* Switch from Rawclk to PCDclk */
3674 temp = I915_READ(reg);
3675 I915_WRITE(reg, temp | FDI_PCDCLK);
3676
3677 POSTING_READ(reg);
3678 udelay(200);
3679
3680 /* Enable CPU FDI TX PLL, always on for Ironlake */
3681 reg = FDI_TX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3685
3686 POSTING_READ(reg);
3687 udelay(100);
3688 }
3689 }
3690
3691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3692 {
3693 struct drm_device *dev = intel_crtc->base.dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 int pipe = intel_crtc->pipe;
3696 i915_reg_t reg;
3697 u32 temp;
3698
3699 /* Switch from PCDclk to Rawclk */
3700 reg = FDI_RX_CTL(pipe);
3701 temp = I915_READ(reg);
3702 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3703
3704 /* Disable CPU FDI TX PLL */
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3708
3709 POSTING_READ(reg);
3710 udelay(100);
3711
3712 reg = FDI_RX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3715
3716 /* Wait for the clocks to turn off. */
3717 POSTING_READ(reg);
3718 udelay(100);
3719 }
3720
3721 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3722 {
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726 int pipe = intel_crtc->pipe;
3727 i915_reg_t reg;
3728 u32 temp;
3729
3730 /* disable CPU FDI tx and PCH FDI rx */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3734 POSTING_READ(reg);
3735
3736 reg = FDI_RX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~(0x7 << 16);
3739 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3740 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3741
3742 POSTING_READ(reg);
3743 udelay(100);
3744
3745 /* Ironlake workaround, disable clock pointer after downing FDI */
3746 if (HAS_PCH_IBX(dev))
3747 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3748
3749 /* still set train pattern 1 */
3750 reg = FDI_TX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~FDI_LINK_TRAIN_NONE;
3753 temp |= FDI_LINK_TRAIN_PATTERN_1;
3754 I915_WRITE(reg, temp);
3755
3756 reg = FDI_RX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 if (HAS_PCH_CPT(dev)) {
3759 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3760 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3761 } else {
3762 temp &= ~FDI_LINK_TRAIN_NONE;
3763 temp |= FDI_LINK_TRAIN_PATTERN_1;
3764 }
3765 /* BPC in FDI rx is consistent with that in PIPECONF */
3766 temp &= ~(0x07 << 16);
3767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3768 I915_WRITE(reg, temp);
3769
3770 POSTING_READ(reg);
3771 udelay(100);
3772 }
3773
3774 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3775 {
3776 struct intel_crtc *crtc;
3777
3778 /* Note that we don't need to be called with mode_config.lock here
3779 * as our list of CRTC objects is static for the lifetime of the
3780 * device and so cannot disappear as we iterate. Similarly, we can
3781 * happily treat the predicates as racy, atomic checks as userspace
3782 * cannot claim and pin a new fb without at least acquring the
3783 * struct_mutex and so serialising with us.
3784 */
3785 for_each_intel_crtc(dev, crtc) {
3786 if (atomic_read(&crtc->unpin_work_count) == 0)
3787 continue;
3788
3789 if (crtc->unpin_work)
3790 intel_wait_for_vblank(dev, crtc->pipe);
3791
3792 return true;
3793 }
3794
3795 return false;
3796 }
3797
3798 static void page_flip_completed(struct intel_crtc *intel_crtc)
3799 {
3800 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3801 struct intel_unpin_work *work = intel_crtc->unpin_work;
3802
3803 /* ensure that the unpin work is consistent wrt ->pending. */
3804 smp_rmb();
3805 intel_crtc->unpin_work = NULL;
3806
3807 if (work->event)
3808 drm_send_vblank_event(intel_crtc->base.dev,
3809 intel_crtc->pipe,
3810 work->event);
3811
3812 drm_crtc_vblank_put(&intel_crtc->base);
3813
3814 wake_up_all(&dev_priv->pending_flip_queue);
3815 queue_work(dev_priv->wq, &work->work);
3816
3817 trace_i915_flip_complete(intel_crtc->plane,
3818 work->pending_flip_obj);
3819 }
3820
3821 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3822 {
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 long ret;
3826
3827 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3828
3829 ret = wait_event_interruptible_timeout(
3830 dev_priv->pending_flip_queue,
3831 !intel_crtc_has_pending_flip(crtc),
3832 60*HZ);
3833
3834 if (ret < 0)
3835 return ret;
3836
3837 if (ret == 0) {
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839
3840 spin_lock_irq(&dev->event_lock);
3841 if (intel_crtc->unpin_work) {
3842 WARN_ONCE(1, "Removing stuck page flip\n");
3843 page_flip_completed(intel_crtc);
3844 }
3845 spin_unlock_irq(&dev->event_lock);
3846 }
3847
3848 return 0;
3849 }
3850
3851 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3852 {
3853 u32 temp;
3854
3855 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3856
3857 mutex_lock(&dev_priv->sb_lock);
3858
3859 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3860 temp |= SBI_SSCCTL_DISABLE;
3861 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3862
3863 mutex_unlock(&dev_priv->sb_lock);
3864 }
3865
3866 /* Program iCLKIP clock to the desired frequency */
3867 static void lpt_program_iclkip(struct drm_crtc *crtc)
3868 {
3869 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3870 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3871 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3872 u32 temp;
3873
3874 lpt_disable_iclkip(dev_priv);
3875
3876 /* The iCLK virtual clock root frequency is in MHz,
3877 * but the adjusted_mode->crtc_clock in in KHz. To get the
3878 * divisors, it is necessary to divide one by another, so we
3879 * convert the virtual clock precision to KHz here for higher
3880 * precision.
3881 */
3882 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3883 u32 iclk_virtual_root_freq = 172800 * 1000;
3884 u32 iclk_pi_range = 64;
3885 u32 desired_divisor;
3886
3887 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3888 clock << auxdiv);
3889 divsel = (desired_divisor / iclk_pi_range) - 2;
3890 phaseinc = desired_divisor % iclk_pi_range;
3891
3892 /*
3893 * Near 20MHz is a corner case which is
3894 * out of range for the 7-bit divisor
3895 */
3896 if (divsel <= 0x7f)
3897 break;
3898 }
3899
3900 /* This should not happen with any sane values */
3901 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3902 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3903 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3904 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3905
3906 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3907 clock,
3908 auxdiv,
3909 divsel,
3910 phasedir,
3911 phaseinc);
3912
3913 mutex_lock(&dev_priv->sb_lock);
3914
3915 /* Program SSCDIVINTPHASE6 */
3916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3923 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3924
3925 /* Program SSCAUXDIV */
3926 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3927 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3928 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3929 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3930
3931 /* Enable modulator and associated divider */
3932 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3933 temp &= ~SBI_SSCCTL_DISABLE;
3934 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3935
3936 mutex_unlock(&dev_priv->sb_lock);
3937
3938 /* Wait for initialization time */
3939 udelay(24);
3940
3941 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3942 }
3943
3944 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3945 {
3946 u32 divsel, phaseinc, auxdiv;
3947 u32 iclk_virtual_root_freq = 172800 * 1000;
3948 u32 iclk_pi_range = 64;
3949 u32 desired_divisor;
3950 u32 temp;
3951
3952 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3953 return 0;
3954
3955 mutex_lock(&dev_priv->sb_lock);
3956
3957 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3958 if (temp & SBI_SSCCTL_DISABLE) {
3959 mutex_unlock(&dev_priv->sb_lock);
3960 return 0;
3961 }
3962
3963 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3964 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3965 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3966 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3967 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3968
3969 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3970 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3971 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3972
3973 mutex_unlock(&dev_priv->sb_lock);
3974
3975 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3976
3977 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3978 desired_divisor << auxdiv);
3979 }
3980
3981 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3982 enum pipe pch_transcoder)
3983 {
3984 struct drm_device *dev = crtc->base.dev;
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3986 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3987
3988 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3989 I915_READ(HTOTAL(cpu_transcoder)));
3990 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3991 I915_READ(HBLANK(cpu_transcoder)));
3992 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3993 I915_READ(HSYNC(cpu_transcoder)));
3994
3995 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3996 I915_READ(VTOTAL(cpu_transcoder)));
3997 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3998 I915_READ(VBLANK(cpu_transcoder)));
3999 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4000 I915_READ(VSYNC(cpu_transcoder)));
4001 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4002 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4003 }
4004
4005 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4006 {
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 uint32_t temp;
4009
4010 temp = I915_READ(SOUTH_CHICKEN1);
4011 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4012 return;
4013
4014 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4016
4017 temp &= ~FDI_BC_BIFURCATION_SELECT;
4018 if (enable)
4019 temp |= FDI_BC_BIFURCATION_SELECT;
4020
4021 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4022 I915_WRITE(SOUTH_CHICKEN1, temp);
4023 POSTING_READ(SOUTH_CHICKEN1);
4024 }
4025
4026 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4027 {
4028 struct drm_device *dev = intel_crtc->base.dev;
4029
4030 switch (intel_crtc->pipe) {
4031 case PIPE_A:
4032 break;
4033 case PIPE_B:
4034 if (intel_crtc->config->fdi_lanes > 2)
4035 cpt_set_fdi_bc_bifurcation(dev, false);
4036 else
4037 cpt_set_fdi_bc_bifurcation(dev, true);
4038
4039 break;
4040 case PIPE_C:
4041 cpt_set_fdi_bc_bifurcation(dev, true);
4042
4043 break;
4044 default:
4045 BUG();
4046 }
4047 }
4048
4049 /* Return which DP Port should be selected for Transcoder DP control */
4050 static enum port
4051 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4052 {
4053 struct drm_device *dev = crtc->dev;
4054 struct intel_encoder *encoder;
4055
4056 for_each_encoder_on_crtc(dev, crtc, encoder) {
4057 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4058 encoder->type == INTEL_OUTPUT_EDP)
4059 return enc_to_dig_port(&encoder->base)->port;
4060 }
4061
4062 return -1;
4063 }
4064
4065 /*
4066 * Enable PCH resources required for PCH ports:
4067 * - PCH PLLs
4068 * - FDI training & RX/TX
4069 * - update transcoder timings
4070 * - DP transcoding bits
4071 * - transcoder
4072 */
4073 static void ironlake_pch_enable(struct drm_crtc *crtc)
4074 {
4075 struct drm_device *dev = crtc->dev;
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4078 int pipe = intel_crtc->pipe;
4079 u32 temp;
4080
4081 assert_pch_transcoder_disabled(dev_priv, pipe);
4082
4083 if (IS_IVYBRIDGE(dev))
4084 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4085
4086 /* Write the TU size bits before fdi link training, so that error
4087 * detection works. */
4088 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4089 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4090
4091 /* For PCH output, training FDI link */
4092 dev_priv->display.fdi_link_train(crtc);
4093
4094 /* We need to program the right clock selection before writing the pixel
4095 * mutliplier into the DPLL. */
4096 if (HAS_PCH_CPT(dev)) {
4097 u32 sel;
4098
4099 temp = I915_READ(PCH_DPLL_SEL);
4100 temp |= TRANS_DPLL_ENABLE(pipe);
4101 sel = TRANS_DPLLB_SEL(pipe);
4102 if (intel_crtc->config->shared_dpll ==
4103 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4104 temp |= sel;
4105 else
4106 temp &= ~sel;
4107 I915_WRITE(PCH_DPLL_SEL, temp);
4108 }
4109
4110 /* XXX: pch pll's can be enabled any time before we enable the PCH
4111 * transcoder, and we actually should do this to not upset any PCH
4112 * transcoder that already use the clock when we share it.
4113 *
4114 * Note that enable_shared_dpll tries to do the right thing, but
4115 * get_shared_dpll unconditionally resets the pll - we need that to have
4116 * the right LVDS enable sequence. */
4117 intel_enable_shared_dpll(intel_crtc);
4118
4119 /* set transcoder timing, panel must allow it */
4120 assert_panel_unlocked(dev_priv, pipe);
4121 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4122
4123 intel_fdi_normal_train(crtc);
4124
4125 /* For PCH DP, enable TRANS_DP_CTL */
4126 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4127 const struct drm_display_mode *adjusted_mode =
4128 &intel_crtc->config->base.adjusted_mode;
4129 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4130 i915_reg_t reg = TRANS_DP_CTL(pipe);
4131 temp = I915_READ(reg);
4132 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4133 TRANS_DP_SYNC_MASK |
4134 TRANS_DP_BPC_MASK);
4135 temp |= TRANS_DP_OUTPUT_ENABLE;
4136 temp |= bpc << 9; /* same format but at 11:9 */
4137
4138 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4139 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4140 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4141 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4142
4143 switch (intel_trans_dp_port_sel(crtc)) {
4144 case PORT_B:
4145 temp |= TRANS_DP_PORT_SEL_B;
4146 break;
4147 case PORT_C:
4148 temp |= TRANS_DP_PORT_SEL_C;
4149 break;
4150 case PORT_D:
4151 temp |= TRANS_DP_PORT_SEL_D;
4152 break;
4153 default:
4154 BUG();
4155 }
4156
4157 I915_WRITE(reg, temp);
4158 }
4159
4160 ironlake_enable_pch_transcoder(dev_priv, pipe);
4161 }
4162
4163 static void lpt_pch_enable(struct drm_crtc *crtc)
4164 {
4165 struct drm_device *dev = crtc->dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4168 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4169
4170 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4171
4172 lpt_program_iclkip(crtc);
4173
4174 /* Set transcoder timing. */
4175 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4176
4177 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4178 }
4179
4180 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4181 {
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 i915_reg_t dslreg = PIPEDSL(pipe);
4184 u32 temp;
4185
4186 temp = I915_READ(dslreg);
4187 udelay(500);
4188 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4189 if (wait_for(I915_READ(dslreg) != temp, 5))
4190 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4191 }
4192 }
4193
4194 static int
4195 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4196 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4197 int src_w, int src_h, int dst_w, int dst_h)
4198 {
4199 struct intel_crtc_scaler_state *scaler_state =
4200 &crtc_state->scaler_state;
4201 struct intel_crtc *intel_crtc =
4202 to_intel_crtc(crtc_state->base.crtc);
4203 int need_scaling;
4204
4205 need_scaling = intel_rotation_90_or_270(rotation) ?
4206 (src_h != dst_w || src_w != dst_h):
4207 (src_w != dst_w || src_h != dst_h);
4208
4209 /*
4210 * if plane is being disabled or scaler is no more required or force detach
4211 * - free scaler binded to this plane/crtc
4212 * - in order to do this, update crtc->scaler_usage
4213 *
4214 * Here scaler state in crtc_state is set free so that
4215 * scaler can be assigned to other user. Actual register
4216 * update to free the scaler is done in plane/panel-fit programming.
4217 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4218 */
4219 if (force_detach || !need_scaling) {
4220 if (*scaler_id >= 0) {
4221 scaler_state->scaler_users &= ~(1 << scaler_user);
4222 scaler_state->scalers[*scaler_id].in_use = 0;
4223
4224 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4225 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4226 intel_crtc->pipe, scaler_user, *scaler_id,
4227 scaler_state->scaler_users);
4228 *scaler_id = -1;
4229 }
4230 return 0;
4231 }
4232
4233 /* range checks */
4234 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4235 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4236
4237 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4238 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4239 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4240 "size is out of scaler range\n",
4241 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4242 return -EINVAL;
4243 }
4244
4245 /* mark this plane as a scaler user in crtc_state */
4246 scaler_state->scaler_users |= (1 << scaler_user);
4247 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4248 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4249 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4250 scaler_state->scaler_users);
4251
4252 return 0;
4253 }
4254
4255 /**
4256 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4257 *
4258 * @state: crtc's scaler state
4259 *
4260 * Return
4261 * 0 - scaler_usage updated successfully
4262 * error - requested scaling cannot be supported or other error condition
4263 */
4264 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4265 {
4266 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4267 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4268
4269 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4270 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4271
4272 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4273 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4274 state->pipe_src_w, state->pipe_src_h,
4275 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4276 }
4277
4278 /**
4279 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4280 *
4281 * @state: crtc's scaler state
4282 * @plane_state: atomic plane state to update
4283 *
4284 * Return
4285 * 0 - scaler_usage updated successfully
4286 * error - requested scaling cannot be supported or other error condition
4287 */
4288 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4289 struct intel_plane_state *plane_state)
4290 {
4291
4292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4293 struct intel_plane *intel_plane =
4294 to_intel_plane(plane_state->base.plane);
4295 struct drm_framebuffer *fb = plane_state->base.fb;
4296 int ret;
4297
4298 bool force_detach = !fb || !plane_state->visible;
4299
4300 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4301 intel_plane->base.base.id, intel_crtc->pipe,
4302 drm_plane_index(&intel_plane->base));
4303
4304 ret = skl_update_scaler(crtc_state, force_detach,
4305 drm_plane_index(&intel_plane->base),
4306 &plane_state->scaler_id,
4307 plane_state->base.rotation,
4308 drm_rect_width(&plane_state->src) >> 16,
4309 drm_rect_height(&plane_state->src) >> 16,
4310 drm_rect_width(&plane_state->dst),
4311 drm_rect_height(&plane_state->dst));
4312
4313 if (ret || plane_state->scaler_id < 0)
4314 return ret;
4315
4316 /* check colorkey */
4317 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4318 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4319 intel_plane->base.base.id);
4320 return -EINVAL;
4321 }
4322
4323 /* Check src format */
4324 switch (fb->pixel_format) {
4325 case DRM_FORMAT_RGB565:
4326 case DRM_FORMAT_XBGR8888:
4327 case DRM_FORMAT_XRGB8888:
4328 case DRM_FORMAT_ABGR8888:
4329 case DRM_FORMAT_ARGB8888:
4330 case DRM_FORMAT_XRGB2101010:
4331 case DRM_FORMAT_XBGR2101010:
4332 case DRM_FORMAT_YUYV:
4333 case DRM_FORMAT_YVYU:
4334 case DRM_FORMAT_UYVY:
4335 case DRM_FORMAT_VYUY:
4336 break;
4337 default:
4338 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4339 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4340 return -EINVAL;
4341 }
4342
4343 return 0;
4344 }
4345
4346 static void skylake_scaler_disable(struct intel_crtc *crtc)
4347 {
4348 int i;
4349
4350 for (i = 0; i < crtc->num_scalers; i++)
4351 skl_detach_scaler(crtc, i);
4352 }
4353
4354 static void skylake_pfit_enable(struct intel_crtc *crtc)
4355 {
4356 struct drm_device *dev = crtc->base.dev;
4357 struct drm_i915_private *dev_priv = dev->dev_private;
4358 int pipe = crtc->pipe;
4359 struct intel_crtc_scaler_state *scaler_state =
4360 &crtc->config->scaler_state;
4361
4362 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4363
4364 if (crtc->config->pch_pfit.enabled) {
4365 int id;
4366
4367 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4368 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4369 return;
4370 }
4371
4372 id = scaler_state->scaler_id;
4373 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4374 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4375 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4376 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4377
4378 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4379 }
4380 }
4381
4382 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4383 {
4384 struct drm_device *dev = crtc->base.dev;
4385 struct drm_i915_private *dev_priv = dev->dev_private;
4386 int pipe = crtc->pipe;
4387
4388 if (crtc->config->pch_pfit.enabled) {
4389 /* Force use of hard-coded filter coefficients
4390 * as some pre-programmed values are broken,
4391 * e.g. x201.
4392 */
4393 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4394 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4395 PF_PIPE_SEL_IVB(pipe));
4396 else
4397 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4398 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4399 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4400 }
4401 }
4402
4403 void hsw_enable_ips(struct intel_crtc *crtc)
4404 {
4405 struct drm_device *dev = crtc->base.dev;
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407
4408 if (!crtc->config->ips_enabled)
4409 return;
4410
4411 /*
4412 * We can only enable IPS after we enable a plane and wait for a vblank
4413 * This function is called from post_plane_update, which is run after
4414 * a vblank wait.
4415 */
4416
4417 assert_plane_enabled(dev_priv, crtc->plane);
4418 if (IS_BROADWELL(dev)) {
4419 mutex_lock(&dev_priv->rps.hw_lock);
4420 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4421 mutex_unlock(&dev_priv->rps.hw_lock);
4422 /* Quoting Art Runyan: "its not safe to expect any particular
4423 * value in IPS_CTL bit 31 after enabling IPS through the
4424 * mailbox." Moreover, the mailbox may return a bogus state,
4425 * so we need to just enable it and continue on.
4426 */
4427 } else {
4428 I915_WRITE(IPS_CTL, IPS_ENABLE);
4429 /* The bit only becomes 1 in the next vblank, so this wait here
4430 * is essentially intel_wait_for_vblank. If we don't have this
4431 * and don't wait for vblanks until the end of crtc_enable, then
4432 * the HW state readout code will complain that the expected
4433 * IPS_CTL value is not the one we read. */
4434 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4435 DRM_ERROR("Timed out waiting for IPS enable\n");
4436 }
4437 }
4438
4439 void hsw_disable_ips(struct intel_crtc *crtc)
4440 {
4441 struct drm_device *dev = crtc->base.dev;
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443
4444 if (!crtc->config->ips_enabled)
4445 return;
4446
4447 assert_plane_enabled(dev_priv, crtc->plane);
4448 if (IS_BROADWELL(dev)) {
4449 mutex_lock(&dev_priv->rps.hw_lock);
4450 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4451 mutex_unlock(&dev_priv->rps.hw_lock);
4452 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4453 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4454 DRM_ERROR("Timed out waiting for IPS disable\n");
4455 } else {
4456 I915_WRITE(IPS_CTL, 0);
4457 POSTING_READ(IPS_CTL);
4458 }
4459
4460 /* We need to wait for a vblank before we can disable the plane. */
4461 intel_wait_for_vblank(dev, crtc->pipe);
4462 }
4463
4464 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4465 {
4466 if (intel_crtc->overlay) {
4467 struct drm_device *dev = intel_crtc->base.dev;
4468 struct drm_i915_private *dev_priv = dev->dev_private;
4469
4470 mutex_lock(&dev->struct_mutex);
4471 dev_priv->mm.interruptible = false;
4472 (void) intel_overlay_switch_off(intel_crtc->overlay);
4473 dev_priv->mm.interruptible = true;
4474 mutex_unlock(&dev->struct_mutex);
4475 }
4476
4477 /* Let userspace switch the overlay on again. In most cases userspace
4478 * has to recompute where to put it anyway.
4479 */
4480 }
4481
4482 /**
4483 * intel_post_enable_primary - Perform operations after enabling primary plane
4484 * @crtc: the CRTC whose primary plane was just enabled
4485 *
4486 * Performs potentially sleeping operations that must be done after the primary
4487 * plane is enabled, such as updating FBC and IPS. Note that this may be
4488 * called due to an explicit primary plane update, or due to an implicit
4489 * re-enable that is caused when a sprite plane is updated to no longer
4490 * completely hide the primary plane.
4491 */
4492 static void
4493 intel_post_enable_primary(struct drm_crtc *crtc)
4494 {
4495 struct drm_device *dev = crtc->dev;
4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4498 int pipe = intel_crtc->pipe;
4499
4500 /*
4501 * FIXME IPS should be fine as long as one plane is
4502 * enabled, but in practice it seems to have problems
4503 * when going from primary only to sprite only and vice
4504 * versa.
4505 */
4506 hsw_enable_ips(intel_crtc);
4507
4508 /*
4509 * Gen2 reports pipe underruns whenever all planes are disabled.
4510 * So don't enable underrun reporting before at least some planes
4511 * are enabled.
4512 * FIXME: Need to fix the logic to work when we turn off all planes
4513 * but leave the pipe running.
4514 */
4515 if (IS_GEN2(dev))
4516 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4517
4518 /* Underruns don't always raise interrupts, so check manually. */
4519 intel_check_cpu_fifo_underruns(dev_priv);
4520 intel_check_pch_fifo_underruns(dev_priv);
4521 }
4522
4523 /* FIXME move all this to pre_plane_update() with proper state tracking */
4524 static void
4525 intel_pre_disable_primary(struct drm_crtc *crtc)
4526 {
4527 struct drm_device *dev = crtc->dev;
4528 struct drm_i915_private *dev_priv = dev->dev_private;
4529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4530 int pipe = intel_crtc->pipe;
4531
4532 /*
4533 * Gen2 reports pipe underruns whenever all planes are disabled.
4534 * So diasble underrun reporting before all the planes get disabled.
4535 * FIXME: Need to fix the logic to work when we turn off all planes
4536 * but leave the pipe running.
4537 */
4538 if (IS_GEN2(dev))
4539 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4540
4541 /*
4542 * FIXME IPS should be fine as long as one plane is
4543 * enabled, but in practice it seems to have problems
4544 * when going from primary only to sprite only and vice
4545 * versa.
4546 */
4547 hsw_disable_ips(intel_crtc);
4548 }
4549
4550 /* FIXME get rid of this and use pre_plane_update */
4551 static void
4552 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4553 {
4554 struct drm_device *dev = crtc->dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4557 int pipe = intel_crtc->pipe;
4558
4559 intel_pre_disable_primary(crtc);
4560
4561 /*
4562 * Vblank time updates from the shadow to live plane control register
4563 * are blocked if the memory self-refresh mode is active at that
4564 * moment. So to make sure the plane gets truly disabled, disable
4565 * first the self-refresh mode. The self-refresh enable bit in turn
4566 * will be checked/applied by the HW only at the next frame start
4567 * event which is after the vblank start event, so we need to have a
4568 * wait-for-vblank between disabling the plane and the pipe.
4569 */
4570 if (HAS_GMCH_DISPLAY(dev)) {
4571 intel_set_memory_cxsr(dev_priv, false);
4572 dev_priv->wm.vlv.cxsr = false;
4573 intel_wait_for_vblank(dev, pipe);
4574 }
4575 }
4576
4577 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4578 {
4579 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4580 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4581 struct intel_crtc_state *pipe_config =
4582 to_intel_crtc_state(crtc->base.state);
4583 struct drm_device *dev = crtc->base.dev;
4584 struct drm_plane *primary = crtc->base.primary;
4585 struct drm_plane_state *old_pri_state =
4586 drm_atomic_get_existing_plane_state(old_state, primary);
4587
4588 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4589
4590 crtc->wm.cxsr_allowed = true;
4591
4592 if (pipe_config->update_wm_post && pipe_config->base.active)
4593 intel_update_watermarks(&crtc->base);
4594
4595 if (old_pri_state) {
4596 struct intel_plane_state *primary_state =
4597 to_intel_plane_state(primary->state);
4598 struct intel_plane_state *old_primary_state =
4599 to_intel_plane_state(old_pri_state);
4600
4601 intel_fbc_post_update(crtc);
4602
4603 if (primary_state->visible &&
4604 (needs_modeset(&pipe_config->base) ||
4605 !old_primary_state->visible))
4606 intel_post_enable_primary(&crtc->base);
4607 }
4608 }
4609
4610 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4611 {
4612 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4613 struct drm_device *dev = crtc->base.dev;
4614 struct drm_i915_private *dev_priv = dev->dev_private;
4615 struct intel_crtc_state *pipe_config =
4616 to_intel_crtc_state(crtc->base.state);
4617 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4618 struct drm_plane *primary = crtc->base.primary;
4619 struct drm_plane_state *old_pri_state =
4620 drm_atomic_get_existing_plane_state(old_state, primary);
4621 bool modeset = needs_modeset(&pipe_config->base);
4622
4623 if (old_pri_state) {
4624 struct intel_plane_state *primary_state =
4625 to_intel_plane_state(primary->state);
4626 struct intel_plane_state *old_primary_state =
4627 to_intel_plane_state(old_pri_state);
4628
4629 intel_fbc_pre_update(crtc);
4630
4631 if (old_primary_state->visible &&
4632 (modeset || !primary_state->visible))
4633 intel_pre_disable_primary(&crtc->base);
4634 }
4635
4636 if (pipe_config->disable_cxsr) {
4637 crtc->wm.cxsr_allowed = false;
4638
4639 /*
4640 * Vblank time updates from the shadow to live plane control register
4641 * are blocked if the memory self-refresh mode is active at that
4642 * moment. So to make sure the plane gets truly disabled, disable
4643 * first the self-refresh mode. The self-refresh enable bit in turn
4644 * will be checked/applied by the HW only at the next frame start
4645 * event which is after the vblank start event, so we need to have a
4646 * wait-for-vblank between disabling the plane and the pipe.
4647 */
4648 if (old_crtc_state->base.active) {
4649 intel_set_memory_cxsr(dev_priv, false);
4650 dev_priv->wm.vlv.cxsr = false;
4651 intel_wait_for_vblank(dev, crtc->pipe);
4652 }
4653 }
4654
4655 /*
4656 * IVB workaround: must disable low power watermarks for at least
4657 * one frame before enabling scaling. LP watermarks can be re-enabled
4658 * when scaling is disabled.
4659 *
4660 * WaCxSRDisabledForSpriteScaling:ivb
4661 */
4662 if (pipe_config->disable_lp_wm) {
4663 ilk_disable_lp_wm(dev);
4664 intel_wait_for_vblank(dev, crtc->pipe);
4665 }
4666
4667 /*
4668 * If we're doing a modeset, we're done. No need to do any pre-vblank
4669 * watermark programming here.
4670 */
4671 if (needs_modeset(&pipe_config->base))
4672 return;
4673
4674 /*
4675 * For platforms that support atomic watermarks, program the
4676 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4677 * will be the intermediate values that are safe for both pre- and
4678 * post- vblank; when vblank happens, the 'active' values will be set
4679 * to the final 'target' values and we'll do this again to get the
4680 * optimal watermarks. For gen9+ platforms, the values we program here
4681 * will be the final target values which will get automatically latched
4682 * at vblank time; no further programming will be necessary.
4683 *
4684 * If a platform hasn't been transitioned to atomic watermarks yet,
4685 * we'll continue to update watermarks the old way, if flags tell
4686 * us to.
4687 */
4688 if (dev_priv->display.initial_watermarks != NULL)
4689 dev_priv->display.initial_watermarks(pipe_config);
4690 else if (pipe_config->update_wm_pre)
4691 intel_update_watermarks(&crtc->base);
4692 }
4693
4694 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4695 {
4696 struct drm_device *dev = crtc->dev;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 struct drm_plane *p;
4699 int pipe = intel_crtc->pipe;
4700
4701 intel_crtc_dpms_overlay_disable(intel_crtc);
4702
4703 drm_for_each_plane_mask(p, dev, plane_mask)
4704 to_intel_plane(p)->disable_plane(p, crtc);
4705
4706 /*
4707 * FIXME: Once we grow proper nuclear flip support out of this we need
4708 * to compute the mask of flip planes precisely. For the time being
4709 * consider this a flip to a NULL plane.
4710 */
4711 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4712 }
4713
4714 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4715 {
4716 struct drm_device *dev = crtc->dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719 struct intel_encoder *encoder;
4720 int pipe = intel_crtc->pipe;
4721 struct intel_crtc_state *pipe_config =
4722 to_intel_crtc_state(crtc->state);
4723
4724 if (WARN_ON(intel_crtc->active))
4725 return;
4726
4727 /*
4728 * Sometimes spurious CPU pipe underruns happen during FDI
4729 * training, at least with VGA+HDMI cloning. Suppress them.
4730 *
4731 * On ILK we get an occasional spurious CPU pipe underruns
4732 * between eDP port A enable and vdd enable. Also PCH port
4733 * enable seems to result in the occasional CPU pipe underrun.
4734 *
4735 * Spurious PCH underruns also occur during PCH enabling.
4736 */
4737 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4738 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4739 if (intel_crtc->config->has_pch_encoder)
4740 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4741
4742 if (intel_crtc->config->has_pch_encoder)
4743 intel_prepare_shared_dpll(intel_crtc);
4744
4745 if (intel_crtc->config->has_dp_encoder)
4746 intel_dp_set_m_n(intel_crtc, M1_N1);
4747
4748 intel_set_pipe_timings(intel_crtc);
4749 intel_set_pipe_src_size(intel_crtc);
4750
4751 if (intel_crtc->config->has_pch_encoder) {
4752 intel_cpu_transcoder_set_m_n(intel_crtc,
4753 &intel_crtc->config->fdi_m_n, NULL);
4754 }
4755
4756 ironlake_set_pipeconf(crtc);
4757
4758 intel_crtc->active = true;
4759
4760 for_each_encoder_on_crtc(dev, crtc, encoder)
4761 if (encoder->pre_enable)
4762 encoder->pre_enable(encoder);
4763
4764 if (intel_crtc->config->has_pch_encoder) {
4765 /* Note: FDI PLL enabling _must_ be done before we enable the
4766 * cpu pipes, hence this is separate from all the other fdi/pch
4767 * enabling. */
4768 ironlake_fdi_pll_enable(intel_crtc);
4769 } else {
4770 assert_fdi_tx_disabled(dev_priv, pipe);
4771 assert_fdi_rx_disabled(dev_priv, pipe);
4772 }
4773
4774 ironlake_pfit_enable(intel_crtc);
4775
4776 /*
4777 * On ILK+ LUT must be loaded before the pipe is running but with
4778 * clocks enabled
4779 */
4780 intel_color_load_luts(&pipe_config->base);
4781
4782 if (dev_priv->display.initial_watermarks != NULL)
4783 dev_priv->display.initial_watermarks(intel_crtc->config);
4784 intel_enable_pipe(intel_crtc);
4785
4786 if (intel_crtc->config->has_pch_encoder)
4787 ironlake_pch_enable(crtc);
4788
4789 assert_vblank_disabled(crtc);
4790 drm_crtc_vblank_on(crtc);
4791
4792 for_each_encoder_on_crtc(dev, crtc, encoder)
4793 encoder->enable(encoder);
4794
4795 if (HAS_PCH_CPT(dev))
4796 cpt_verify_modeset(dev, intel_crtc->pipe);
4797
4798 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4799 if (intel_crtc->config->has_pch_encoder)
4800 intel_wait_for_vblank(dev, pipe);
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4802 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4803 }
4804
4805 /* IPS only exists on ULT machines and is tied to pipe A. */
4806 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4807 {
4808 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4809 }
4810
4811 static void haswell_crtc_enable(struct drm_crtc *crtc)
4812 {
4813 struct drm_device *dev = crtc->dev;
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4816 struct intel_encoder *encoder;
4817 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4818 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4819 struct intel_crtc_state *pipe_config =
4820 to_intel_crtc_state(crtc->state);
4821
4822 if (WARN_ON(intel_crtc->active))
4823 return;
4824
4825 if (intel_crtc->config->has_pch_encoder)
4826 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4827 false);
4828
4829 if (intel_crtc->config->shared_dpll)
4830 intel_enable_shared_dpll(intel_crtc);
4831
4832 if (intel_crtc->config->has_dp_encoder)
4833 intel_dp_set_m_n(intel_crtc, M1_N1);
4834
4835 if (!intel_crtc->config->has_dsi_encoder)
4836 intel_set_pipe_timings(intel_crtc);
4837
4838 intel_set_pipe_src_size(intel_crtc);
4839
4840 if (cpu_transcoder != TRANSCODER_EDP &&
4841 !transcoder_is_dsi(cpu_transcoder)) {
4842 I915_WRITE(PIPE_MULT(cpu_transcoder),
4843 intel_crtc->config->pixel_multiplier - 1);
4844 }
4845
4846 if (intel_crtc->config->has_pch_encoder) {
4847 intel_cpu_transcoder_set_m_n(intel_crtc,
4848 &intel_crtc->config->fdi_m_n, NULL);
4849 }
4850
4851 if (!intel_crtc->config->has_dsi_encoder)
4852 haswell_set_pipeconf(crtc);
4853
4854 haswell_set_pipemisc(crtc);
4855
4856 intel_color_set_csc(&pipe_config->base);
4857
4858 intel_crtc->active = true;
4859
4860 if (intel_crtc->config->has_pch_encoder)
4861 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4862 else
4863 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4864
4865 for_each_encoder_on_crtc(dev, crtc, encoder) {
4866 if (encoder->pre_enable)
4867 encoder->pre_enable(encoder);
4868 }
4869
4870 if (intel_crtc->config->has_pch_encoder)
4871 dev_priv->display.fdi_link_train(crtc);
4872
4873 if (!intel_crtc->config->has_dsi_encoder)
4874 intel_ddi_enable_pipe_clock(intel_crtc);
4875
4876 if (INTEL_INFO(dev)->gen >= 9)
4877 skylake_pfit_enable(intel_crtc);
4878 else
4879 ironlake_pfit_enable(intel_crtc);
4880
4881 /*
4882 * On ILK+ LUT must be loaded before the pipe is running but with
4883 * clocks enabled
4884 */
4885 intel_color_load_luts(&pipe_config->base);
4886
4887 intel_ddi_set_pipe_settings(crtc);
4888 if (!intel_crtc->config->has_dsi_encoder)
4889 intel_ddi_enable_transcoder_func(crtc);
4890
4891 if (dev_priv->display.initial_watermarks != NULL)
4892 dev_priv->display.initial_watermarks(pipe_config);
4893 else
4894 intel_update_watermarks(crtc);
4895
4896 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4897 if (!intel_crtc->config->has_dsi_encoder)
4898 intel_enable_pipe(intel_crtc);
4899
4900 if (intel_crtc->config->has_pch_encoder)
4901 lpt_pch_enable(crtc);
4902
4903 if (intel_crtc->config->dp_encoder_is_mst)
4904 intel_ddi_set_vc_payload_alloc(crtc, true);
4905
4906 assert_vblank_disabled(crtc);
4907 drm_crtc_vblank_on(crtc);
4908
4909 for_each_encoder_on_crtc(dev, crtc, encoder) {
4910 encoder->enable(encoder);
4911 intel_opregion_notify_encoder(encoder, true);
4912 }
4913
4914 if (intel_crtc->config->has_pch_encoder) {
4915 intel_wait_for_vblank(dev, pipe);
4916 intel_wait_for_vblank(dev, pipe);
4917 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4918 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4919 true);
4920 }
4921
4922 /* If we change the relative order between pipe/planes enabling, we need
4923 * to change the workaround. */
4924 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4925 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4926 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4927 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4928 }
4929 }
4930
4931 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4932 {
4933 struct drm_device *dev = crtc->base.dev;
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935 int pipe = crtc->pipe;
4936
4937 /* To avoid upsetting the power well on haswell only disable the pfit if
4938 * it's in use. The hw state code will make sure we get this right. */
4939 if (force || crtc->config->pch_pfit.enabled) {
4940 I915_WRITE(PF_CTL(pipe), 0);
4941 I915_WRITE(PF_WIN_POS(pipe), 0);
4942 I915_WRITE(PF_WIN_SZ(pipe), 0);
4943 }
4944 }
4945
4946 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4947 {
4948 struct drm_device *dev = crtc->dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951 struct intel_encoder *encoder;
4952 int pipe = intel_crtc->pipe;
4953
4954 /*
4955 * Sometimes spurious CPU pipe underruns happen when the
4956 * pipe is already disabled, but FDI RX/TX is still enabled.
4957 * Happens at least with VGA+HDMI cloning. Suppress them.
4958 */
4959 if (intel_crtc->config->has_pch_encoder) {
4960 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4961 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4962 }
4963
4964 for_each_encoder_on_crtc(dev, crtc, encoder)
4965 encoder->disable(encoder);
4966
4967 drm_crtc_vblank_off(crtc);
4968 assert_vblank_disabled(crtc);
4969
4970 intel_disable_pipe(intel_crtc);
4971
4972 ironlake_pfit_disable(intel_crtc, false);
4973
4974 if (intel_crtc->config->has_pch_encoder)
4975 ironlake_fdi_disable(crtc);
4976
4977 for_each_encoder_on_crtc(dev, crtc, encoder)
4978 if (encoder->post_disable)
4979 encoder->post_disable(encoder);
4980
4981 if (intel_crtc->config->has_pch_encoder) {
4982 ironlake_disable_pch_transcoder(dev_priv, pipe);
4983
4984 if (HAS_PCH_CPT(dev)) {
4985 i915_reg_t reg;
4986 u32 temp;
4987
4988 /* disable TRANS_DP_CTL */
4989 reg = TRANS_DP_CTL(pipe);
4990 temp = I915_READ(reg);
4991 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4992 TRANS_DP_PORT_SEL_MASK);
4993 temp |= TRANS_DP_PORT_SEL_NONE;
4994 I915_WRITE(reg, temp);
4995
4996 /* disable DPLL_SEL */
4997 temp = I915_READ(PCH_DPLL_SEL);
4998 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4999 I915_WRITE(PCH_DPLL_SEL, temp);
5000 }
5001
5002 ironlake_fdi_pll_disable(intel_crtc);
5003 }
5004
5005 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5006 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5007 }
5008
5009 static void haswell_crtc_disable(struct drm_crtc *crtc)
5010 {
5011 struct drm_device *dev = crtc->dev;
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014 struct intel_encoder *encoder;
5015 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5016
5017 if (intel_crtc->config->has_pch_encoder)
5018 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5019 false);
5020
5021 for_each_encoder_on_crtc(dev, crtc, encoder) {
5022 intel_opregion_notify_encoder(encoder, false);
5023 encoder->disable(encoder);
5024 }
5025
5026 drm_crtc_vblank_off(crtc);
5027 assert_vblank_disabled(crtc);
5028
5029 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5030 if (!intel_crtc->config->has_dsi_encoder)
5031 intel_disable_pipe(intel_crtc);
5032
5033 if (intel_crtc->config->dp_encoder_is_mst)
5034 intel_ddi_set_vc_payload_alloc(crtc, false);
5035
5036 if (!intel_crtc->config->has_dsi_encoder)
5037 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5038
5039 if (INTEL_INFO(dev)->gen >= 9)
5040 skylake_scaler_disable(intel_crtc);
5041 else
5042 ironlake_pfit_disable(intel_crtc, false);
5043
5044 if (!intel_crtc->config->has_dsi_encoder)
5045 intel_ddi_disable_pipe_clock(intel_crtc);
5046
5047 for_each_encoder_on_crtc(dev, crtc, encoder)
5048 if (encoder->post_disable)
5049 encoder->post_disable(encoder);
5050
5051 if (intel_crtc->config->has_pch_encoder) {
5052 lpt_disable_pch_transcoder(dev_priv);
5053 lpt_disable_iclkip(dev_priv);
5054 intel_ddi_fdi_disable(crtc);
5055
5056 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5057 true);
5058 }
5059 }
5060
5061 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5062 {
5063 struct drm_device *dev = crtc->base.dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_crtc_state *pipe_config = crtc->config;
5066
5067 if (!pipe_config->gmch_pfit.control)
5068 return;
5069
5070 /*
5071 * The panel fitter should only be adjusted whilst the pipe is disabled,
5072 * according to register description and PRM.
5073 */
5074 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5075 assert_pipe_disabled(dev_priv, crtc->pipe);
5076
5077 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5078 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5079
5080 /* Border color in case we don't scale up to the full screen. Black by
5081 * default, change to something else for debugging. */
5082 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5083 }
5084
5085 static enum intel_display_power_domain port_to_power_domain(enum port port)
5086 {
5087 switch (port) {
5088 case PORT_A:
5089 return POWER_DOMAIN_PORT_DDI_A_LANES;
5090 case PORT_B:
5091 return POWER_DOMAIN_PORT_DDI_B_LANES;
5092 case PORT_C:
5093 return POWER_DOMAIN_PORT_DDI_C_LANES;
5094 case PORT_D:
5095 return POWER_DOMAIN_PORT_DDI_D_LANES;
5096 case PORT_E:
5097 return POWER_DOMAIN_PORT_DDI_E_LANES;
5098 default:
5099 MISSING_CASE(port);
5100 return POWER_DOMAIN_PORT_OTHER;
5101 }
5102 }
5103
5104 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5105 {
5106 switch (port) {
5107 case PORT_A:
5108 return POWER_DOMAIN_AUX_A;
5109 case PORT_B:
5110 return POWER_DOMAIN_AUX_B;
5111 case PORT_C:
5112 return POWER_DOMAIN_AUX_C;
5113 case PORT_D:
5114 return POWER_DOMAIN_AUX_D;
5115 case PORT_E:
5116 /* FIXME: Check VBT for actual wiring of PORT E */
5117 return POWER_DOMAIN_AUX_D;
5118 default:
5119 MISSING_CASE(port);
5120 return POWER_DOMAIN_AUX_A;
5121 }
5122 }
5123
5124 enum intel_display_power_domain
5125 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5126 {
5127 struct drm_device *dev = intel_encoder->base.dev;
5128 struct intel_digital_port *intel_dig_port;
5129
5130 switch (intel_encoder->type) {
5131 case INTEL_OUTPUT_UNKNOWN:
5132 /* Only DDI platforms should ever use this output type */
5133 WARN_ON_ONCE(!HAS_DDI(dev));
5134 case INTEL_OUTPUT_DISPLAYPORT:
5135 case INTEL_OUTPUT_HDMI:
5136 case INTEL_OUTPUT_EDP:
5137 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5138 return port_to_power_domain(intel_dig_port->port);
5139 case INTEL_OUTPUT_DP_MST:
5140 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5141 return port_to_power_domain(intel_dig_port->port);
5142 case INTEL_OUTPUT_ANALOG:
5143 return POWER_DOMAIN_PORT_CRT;
5144 case INTEL_OUTPUT_DSI:
5145 return POWER_DOMAIN_PORT_DSI;
5146 default:
5147 return POWER_DOMAIN_PORT_OTHER;
5148 }
5149 }
5150
5151 enum intel_display_power_domain
5152 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5153 {
5154 struct drm_device *dev = intel_encoder->base.dev;
5155 struct intel_digital_port *intel_dig_port;
5156
5157 switch (intel_encoder->type) {
5158 case INTEL_OUTPUT_UNKNOWN:
5159 case INTEL_OUTPUT_HDMI:
5160 /*
5161 * Only DDI platforms should ever use these output types.
5162 * We can get here after the HDMI detect code has already set
5163 * the type of the shared encoder. Since we can't be sure
5164 * what's the status of the given connectors, play safe and
5165 * run the DP detection too.
5166 */
5167 WARN_ON_ONCE(!HAS_DDI(dev));
5168 case INTEL_OUTPUT_DISPLAYPORT:
5169 case INTEL_OUTPUT_EDP:
5170 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5171 return port_to_aux_power_domain(intel_dig_port->port);
5172 case INTEL_OUTPUT_DP_MST:
5173 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5174 return port_to_aux_power_domain(intel_dig_port->port);
5175 default:
5176 MISSING_CASE(intel_encoder->type);
5177 return POWER_DOMAIN_AUX_A;
5178 }
5179 }
5180
5181 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5182 struct intel_crtc_state *crtc_state)
5183 {
5184 struct drm_device *dev = crtc->dev;
5185 struct drm_encoder *encoder;
5186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5187 enum pipe pipe = intel_crtc->pipe;
5188 unsigned long mask;
5189 enum transcoder transcoder = crtc_state->cpu_transcoder;
5190
5191 if (!crtc_state->base.active)
5192 return 0;
5193
5194 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5195 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5196 if (crtc_state->pch_pfit.enabled ||
5197 crtc_state->pch_pfit.force_thru)
5198 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5199
5200 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5201 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5202
5203 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5204 }
5205
5206 if (crtc_state->shared_dpll)
5207 mask |= BIT(POWER_DOMAIN_PLLS);
5208
5209 return mask;
5210 }
5211
5212 static unsigned long
5213 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5214 struct intel_crtc_state *crtc_state)
5215 {
5216 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5218 enum intel_display_power_domain domain;
5219 unsigned long domains, new_domains, old_domains;
5220
5221 old_domains = intel_crtc->enabled_power_domains;
5222 intel_crtc->enabled_power_domains = new_domains =
5223 get_crtc_power_domains(crtc, crtc_state);
5224
5225 domains = new_domains & ~old_domains;
5226
5227 for_each_power_domain(domain, domains)
5228 intel_display_power_get(dev_priv, domain);
5229
5230 return old_domains & ~new_domains;
5231 }
5232
5233 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5234 unsigned long domains)
5235 {
5236 enum intel_display_power_domain domain;
5237
5238 for_each_power_domain(domain, domains)
5239 intel_display_power_put(dev_priv, domain);
5240 }
5241
5242 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5243 {
5244 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5245
5246 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5247 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5248 return max_cdclk_freq;
5249 else if (IS_CHERRYVIEW(dev_priv))
5250 return max_cdclk_freq*95/100;
5251 else if (INTEL_INFO(dev_priv)->gen < 4)
5252 return 2*max_cdclk_freq*90/100;
5253 else
5254 return max_cdclk_freq*90/100;
5255 }
5256
5257 static void intel_update_max_cdclk(struct drm_device *dev)
5258 {
5259 struct drm_i915_private *dev_priv = dev->dev_private;
5260
5261 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5262 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5263
5264 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5265 dev_priv->max_cdclk_freq = 675000;
5266 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5267 dev_priv->max_cdclk_freq = 540000;
5268 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5269 dev_priv->max_cdclk_freq = 450000;
5270 else
5271 dev_priv->max_cdclk_freq = 337500;
5272 } else if (IS_BROXTON(dev)) {
5273 dev_priv->max_cdclk_freq = 624000;
5274 } else if (IS_BROADWELL(dev)) {
5275 /*
5276 * FIXME with extra cooling we can allow
5277 * 540 MHz for ULX and 675 Mhz for ULT.
5278 * How can we know if extra cooling is
5279 * available? PCI ID, VTB, something else?
5280 */
5281 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5282 dev_priv->max_cdclk_freq = 450000;
5283 else if (IS_BDW_ULX(dev))
5284 dev_priv->max_cdclk_freq = 450000;
5285 else if (IS_BDW_ULT(dev))
5286 dev_priv->max_cdclk_freq = 540000;
5287 else
5288 dev_priv->max_cdclk_freq = 675000;
5289 } else if (IS_CHERRYVIEW(dev)) {
5290 dev_priv->max_cdclk_freq = 320000;
5291 } else if (IS_VALLEYVIEW(dev)) {
5292 dev_priv->max_cdclk_freq = 400000;
5293 } else {
5294 /* otherwise assume cdclk is fixed */
5295 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5296 }
5297
5298 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5299
5300 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5301 dev_priv->max_cdclk_freq);
5302
5303 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5304 dev_priv->max_dotclk_freq);
5305 }
5306
5307 static void intel_update_cdclk(struct drm_device *dev)
5308 {
5309 struct drm_i915_private *dev_priv = dev->dev_private;
5310
5311 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5312 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5313 dev_priv->cdclk_freq);
5314
5315 /*
5316 * Program the gmbus_freq based on the cdclk frequency.
5317 * BSpec erroneously claims we should aim for 4MHz, but
5318 * in fact 1MHz is the correct frequency.
5319 */
5320 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5321 /*
5322 * Program the gmbus_freq based on the cdclk frequency.
5323 * BSpec erroneously claims we should aim for 4MHz, but
5324 * in fact 1MHz is the correct frequency.
5325 */
5326 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5327 }
5328
5329 if (dev_priv->max_cdclk_freq == 0)
5330 intel_update_max_cdclk(dev);
5331 }
5332
5333 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5334 {
5335 struct drm_i915_private *dev_priv = dev->dev_private;
5336 uint32_t divider;
5337 uint32_t ratio;
5338 uint32_t current_freq;
5339 int ret;
5340
5341 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5342 switch (frequency) {
5343 case 144000:
5344 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5345 ratio = BXT_DE_PLL_RATIO(60);
5346 break;
5347 case 288000:
5348 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5349 ratio = BXT_DE_PLL_RATIO(60);
5350 break;
5351 case 384000:
5352 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5353 ratio = BXT_DE_PLL_RATIO(60);
5354 break;
5355 case 576000:
5356 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5357 ratio = BXT_DE_PLL_RATIO(60);
5358 break;
5359 case 624000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5361 ratio = BXT_DE_PLL_RATIO(65);
5362 break;
5363 case 19200:
5364 /*
5365 * Bypass frequency with DE PLL disabled. Init ratio, divider
5366 * to suppress GCC warning.
5367 */
5368 ratio = 0;
5369 divider = 0;
5370 break;
5371 default:
5372 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5373
5374 return;
5375 }
5376
5377 mutex_lock(&dev_priv->rps.hw_lock);
5378 /* Inform power controller of upcoming frequency change */
5379 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5380 0x80000000);
5381 mutex_unlock(&dev_priv->rps.hw_lock);
5382
5383 if (ret) {
5384 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5385 ret, frequency);
5386 return;
5387 }
5388
5389 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5390 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5391 current_freq = current_freq * 500 + 1000;
5392
5393 /*
5394 * DE PLL has to be disabled when
5395 * - setting to 19.2MHz (bypass, PLL isn't used)
5396 * - before setting to 624MHz (PLL needs toggling)
5397 * - before setting to any frequency from 624MHz (PLL needs toggling)
5398 */
5399 if (frequency == 19200 || frequency == 624000 ||
5400 current_freq == 624000) {
5401 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5402 /* Timeout 200us */
5403 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5404 1))
5405 DRM_ERROR("timout waiting for DE PLL unlock\n");
5406 }
5407
5408 if (frequency != 19200) {
5409 uint32_t val;
5410
5411 val = I915_READ(BXT_DE_PLL_CTL);
5412 val &= ~BXT_DE_PLL_RATIO_MASK;
5413 val |= ratio;
5414 I915_WRITE(BXT_DE_PLL_CTL, val);
5415
5416 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5417 /* Timeout 200us */
5418 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5419 DRM_ERROR("timeout waiting for DE PLL lock\n");
5420
5421 val = I915_READ(CDCLK_CTL);
5422 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5423 val |= divider;
5424 /*
5425 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5426 * enable otherwise.
5427 */
5428 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429 if (frequency >= 500000)
5430 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5431
5432 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5433 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5434 val |= (frequency - 1000) / 500;
5435 I915_WRITE(CDCLK_CTL, val);
5436 }
5437
5438 mutex_lock(&dev_priv->rps.hw_lock);
5439 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5440 DIV_ROUND_UP(frequency, 25000));
5441 mutex_unlock(&dev_priv->rps.hw_lock);
5442
5443 if (ret) {
5444 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5445 ret, frequency);
5446 return;
5447 }
5448
5449 intel_update_cdclk(dev);
5450 }
5451
5452 void broxton_init_cdclk(struct drm_device *dev)
5453 {
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5455 uint32_t val;
5456
5457 /*
5458 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5459 * or else the reset will hang because there is no PCH to respond.
5460 * Move the handshake programming to initialization sequence.
5461 * Previously was left up to BIOS.
5462 */
5463 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5464 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5465 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5466
5467 /* Enable PG1 for cdclk */
5468 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5469
5470 /* check if cd clock is enabled */
5471 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5472 DRM_DEBUG_KMS("Display already initialized\n");
5473 return;
5474 }
5475
5476 /*
5477 * FIXME:
5478 * - The initial CDCLK needs to be read from VBT.
5479 * Need to make this change after VBT has changes for BXT.
5480 * - check if setting the max (or any) cdclk freq is really necessary
5481 * here, it belongs to modeset time
5482 */
5483 broxton_set_cdclk(dev, 624000);
5484
5485 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5486 POSTING_READ(DBUF_CTL);
5487
5488 udelay(10);
5489
5490 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5491 DRM_ERROR("DBuf power enable timeout!\n");
5492 }
5493
5494 void broxton_uninit_cdclk(struct drm_device *dev)
5495 {
5496 struct drm_i915_private *dev_priv = dev->dev_private;
5497
5498 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5499 POSTING_READ(DBUF_CTL);
5500
5501 udelay(10);
5502
5503 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5504 DRM_ERROR("DBuf power disable timeout!\n");
5505
5506 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5507 broxton_set_cdclk(dev, 19200);
5508
5509 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5510 }
5511
5512 static const struct skl_cdclk_entry {
5513 unsigned int freq;
5514 unsigned int vco;
5515 } skl_cdclk_frequencies[] = {
5516 { .freq = 308570, .vco = 8640 },
5517 { .freq = 337500, .vco = 8100 },
5518 { .freq = 432000, .vco = 8640 },
5519 { .freq = 450000, .vco = 8100 },
5520 { .freq = 540000, .vco = 8100 },
5521 { .freq = 617140, .vco = 8640 },
5522 { .freq = 675000, .vco = 8100 },
5523 };
5524
5525 static unsigned int skl_cdclk_decimal(unsigned int freq)
5526 {
5527 return (freq - 1000) / 500;
5528 }
5529
5530 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5531 {
5532 unsigned int i;
5533
5534 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5535 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5536
5537 if (e->freq == freq)
5538 return e->vco;
5539 }
5540
5541 return 8100;
5542 }
5543
5544 static void
5545 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5546 {
5547 unsigned int min_freq;
5548 u32 val;
5549
5550 /* select the minimum CDCLK before enabling DPLL 0 */
5551 val = I915_READ(CDCLK_CTL);
5552 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5553 val |= CDCLK_FREQ_337_308;
5554
5555 if (required_vco == 8640)
5556 min_freq = 308570;
5557 else
5558 min_freq = 337500;
5559
5560 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5561
5562 I915_WRITE(CDCLK_CTL, val);
5563 POSTING_READ(CDCLK_CTL);
5564
5565 /*
5566 * We always enable DPLL0 with the lowest link rate possible, but still
5567 * taking into account the VCO required to operate the eDP panel at the
5568 * desired frequency. The usual DP link rates operate with a VCO of
5569 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5570 * The modeset code is responsible for the selection of the exact link
5571 * rate later on, with the constraint of choosing a frequency that
5572 * works with required_vco.
5573 */
5574 val = I915_READ(DPLL_CTRL1);
5575
5576 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5577 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5578 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5579 if (required_vco == 8640)
5580 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5581 SKL_DPLL0);
5582 else
5583 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5584 SKL_DPLL0);
5585
5586 I915_WRITE(DPLL_CTRL1, val);
5587 POSTING_READ(DPLL_CTRL1);
5588
5589 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5590
5591 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5592 DRM_ERROR("DPLL0 not locked\n");
5593 }
5594
5595 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5596 {
5597 int ret;
5598 u32 val;
5599
5600 /* inform PCU we want to change CDCLK */
5601 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5602 mutex_lock(&dev_priv->rps.hw_lock);
5603 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5604 mutex_unlock(&dev_priv->rps.hw_lock);
5605
5606 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5607 }
5608
5609 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5610 {
5611 unsigned int i;
5612
5613 for (i = 0; i < 15; i++) {
5614 if (skl_cdclk_pcu_ready(dev_priv))
5615 return true;
5616 udelay(10);
5617 }
5618
5619 return false;
5620 }
5621
5622 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5623 {
5624 struct drm_device *dev = dev_priv->dev;
5625 u32 freq_select, pcu_ack;
5626
5627 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5628
5629 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5630 DRM_ERROR("failed to inform PCU about cdclk change\n");
5631 return;
5632 }
5633
5634 /* set CDCLK_CTL */
5635 switch(freq) {
5636 case 450000:
5637 case 432000:
5638 freq_select = CDCLK_FREQ_450_432;
5639 pcu_ack = 1;
5640 break;
5641 case 540000:
5642 freq_select = CDCLK_FREQ_540;
5643 pcu_ack = 2;
5644 break;
5645 case 308570:
5646 case 337500:
5647 default:
5648 freq_select = CDCLK_FREQ_337_308;
5649 pcu_ack = 0;
5650 break;
5651 case 617140:
5652 case 675000:
5653 freq_select = CDCLK_FREQ_675_617;
5654 pcu_ack = 3;
5655 break;
5656 }
5657
5658 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5659 POSTING_READ(CDCLK_CTL);
5660
5661 /* inform PCU of the change */
5662 mutex_lock(&dev_priv->rps.hw_lock);
5663 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5664 mutex_unlock(&dev_priv->rps.hw_lock);
5665
5666 intel_update_cdclk(dev);
5667 }
5668
5669 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5670 {
5671 /* disable DBUF power */
5672 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5673 POSTING_READ(DBUF_CTL);
5674
5675 udelay(10);
5676
5677 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5678 DRM_ERROR("DBuf power disable timeout\n");
5679
5680 /* disable DPLL0 */
5681 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5682 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5683 DRM_ERROR("Couldn't disable DPLL0\n");
5684 }
5685
5686 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5687 {
5688 unsigned int required_vco;
5689
5690 /* DPLL0 not enabled (happens on early BIOS versions) */
5691 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5692 /* enable DPLL0 */
5693 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5694 skl_dpll0_enable(dev_priv, required_vco);
5695 }
5696
5697 /* set CDCLK to the frequency the BIOS chose */
5698 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5699
5700 /* enable DBUF power */
5701 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5702 POSTING_READ(DBUF_CTL);
5703
5704 udelay(10);
5705
5706 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5707 DRM_ERROR("DBuf power enable timeout\n");
5708 }
5709
5710 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5711 {
5712 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5713 uint32_t cdctl = I915_READ(CDCLK_CTL);
5714 int freq = dev_priv->skl_boot_cdclk;
5715
5716 /*
5717 * check if the pre-os intialized the display
5718 * There is SWF18 scratchpad register defined which is set by the
5719 * pre-os which can be used by the OS drivers to check the status
5720 */
5721 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5722 goto sanitize;
5723
5724 /* Is PLL enabled and locked ? */
5725 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5726 goto sanitize;
5727
5728 /* DPLL okay; verify the cdclock
5729 *
5730 * Noticed in some instances that the freq selection is correct but
5731 * decimal part is programmed wrong from BIOS where pre-os does not
5732 * enable display. Verify the same as well.
5733 */
5734 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5735 /* All well; nothing to sanitize */
5736 return false;
5737 sanitize:
5738 /*
5739 * As of now initialize with max cdclk till
5740 * we get dynamic cdclk support
5741 * */
5742 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5743 skl_init_cdclk(dev_priv);
5744
5745 /* we did have to sanitize */
5746 return true;
5747 }
5748
5749 /* Adjust CDclk dividers to allow high res or save power if possible */
5750 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5751 {
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753 u32 val, cmd;
5754
5755 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5756 != dev_priv->cdclk_freq);
5757
5758 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5759 cmd = 2;
5760 else if (cdclk == 266667)
5761 cmd = 1;
5762 else
5763 cmd = 0;
5764
5765 mutex_lock(&dev_priv->rps.hw_lock);
5766 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5767 val &= ~DSPFREQGUAR_MASK;
5768 val |= (cmd << DSPFREQGUAR_SHIFT);
5769 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5770 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5771 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5772 50)) {
5773 DRM_ERROR("timed out waiting for CDclk change\n");
5774 }
5775 mutex_unlock(&dev_priv->rps.hw_lock);
5776
5777 mutex_lock(&dev_priv->sb_lock);
5778
5779 if (cdclk == 400000) {
5780 u32 divider;
5781
5782 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5783
5784 /* adjust cdclk divider */
5785 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5786 val &= ~CCK_FREQUENCY_VALUES;
5787 val |= divider;
5788 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5789
5790 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5791 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5792 50))
5793 DRM_ERROR("timed out waiting for CDclk change\n");
5794 }
5795
5796 /* adjust self-refresh exit latency value */
5797 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5798 val &= ~0x7f;
5799
5800 /*
5801 * For high bandwidth configs, we set a higher latency in the bunit
5802 * so that the core display fetch happens in time to avoid underruns.
5803 */
5804 if (cdclk == 400000)
5805 val |= 4500 / 250; /* 4.5 usec */
5806 else
5807 val |= 3000 / 250; /* 3.0 usec */
5808 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5809
5810 mutex_unlock(&dev_priv->sb_lock);
5811
5812 intel_update_cdclk(dev);
5813 }
5814
5815 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5816 {
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5818 u32 val, cmd;
5819
5820 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5821 != dev_priv->cdclk_freq);
5822
5823 switch (cdclk) {
5824 case 333333:
5825 case 320000:
5826 case 266667:
5827 case 200000:
5828 break;
5829 default:
5830 MISSING_CASE(cdclk);
5831 return;
5832 }
5833
5834 /*
5835 * Specs are full of misinformation, but testing on actual
5836 * hardware has shown that we just need to write the desired
5837 * CCK divider into the Punit register.
5838 */
5839 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5840
5841 mutex_lock(&dev_priv->rps.hw_lock);
5842 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5843 val &= ~DSPFREQGUAR_MASK_CHV;
5844 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5845 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5846 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5847 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5848 50)) {
5849 DRM_ERROR("timed out waiting for CDclk change\n");
5850 }
5851 mutex_unlock(&dev_priv->rps.hw_lock);
5852
5853 intel_update_cdclk(dev);
5854 }
5855
5856 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5857 int max_pixclk)
5858 {
5859 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5860 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5861
5862 /*
5863 * Really only a few cases to deal with, as only 4 CDclks are supported:
5864 * 200MHz
5865 * 267MHz
5866 * 320/333MHz (depends on HPLL freq)
5867 * 400MHz (VLV only)
5868 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5869 * of the lower bin and adjust if needed.
5870 *
5871 * We seem to get an unstable or solid color picture at 200MHz.
5872 * Not sure what's wrong. For now use 200MHz only when all pipes
5873 * are off.
5874 */
5875 if (!IS_CHERRYVIEW(dev_priv) &&
5876 max_pixclk > freq_320*limit/100)
5877 return 400000;
5878 else if (max_pixclk > 266667*limit/100)
5879 return freq_320;
5880 else if (max_pixclk > 0)
5881 return 266667;
5882 else
5883 return 200000;
5884 }
5885
5886 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5887 int max_pixclk)
5888 {
5889 /*
5890 * FIXME:
5891 * - remove the guardband, it's not needed on BXT
5892 * - set 19.2MHz bypass frequency if there are no active pipes
5893 */
5894 if (max_pixclk > 576000*9/10)
5895 return 624000;
5896 else if (max_pixclk > 384000*9/10)
5897 return 576000;
5898 else if (max_pixclk > 288000*9/10)
5899 return 384000;
5900 else if (max_pixclk > 144000*9/10)
5901 return 288000;
5902 else
5903 return 144000;
5904 }
5905
5906 /* Compute the max pixel clock for new configuration. */
5907 static int intel_mode_max_pixclk(struct drm_device *dev,
5908 struct drm_atomic_state *state)
5909 {
5910 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5912 struct drm_crtc *crtc;
5913 struct drm_crtc_state *crtc_state;
5914 unsigned max_pixclk = 0, i;
5915 enum pipe pipe;
5916
5917 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5918 sizeof(intel_state->min_pixclk));
5919
5920 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5921 int pixclk = 0;
5922
5923 if (crtc_state->enable)
5924 pixclk = crtc_state->adjusted_mode.crtc_clock;
5925
5926 intel_state->min_pixclk[i] = pixclk;
5927 }
5928
5929 for_each_pipe(dev_priv, pipe)
5930 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5931
5932 return max_pixclk;
5933 }
5934
5935 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5936 {
5937 struct drm_device *dev = state->dev;
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5939 int max_pixclk = intel_mode_max_pixclk(dev, state);
5940 struct intel_atomic_state *intel_state =
5941 to_intel_atomic_state(state);
5942
5943 if (max_pixclk < 0)
5944 return max_pixclk;
5945
5946 intel_state->cdclk = intel_state->dev_cdclk =
5947 valleyview_calc_cdclk(dev_priv, max_pixclk);
5948
5949 if (!intel_state->active_crtcs)
5950 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5951
5952 return 0;
5953 }
5954
5955 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5956 {
5957 struct drm_device *dev = state->dev;
5958 struct drm_i915_private *dev_priv = dev->dev_private;
5959 int max_pixclk = intel_mode_max_pixclk(dev, state);
5960 struct intel_atomic_state *intel_state =
5961 to_intel_atomic_state(state);
5962
5963 if (max_pixclk < 0)
5964 return max_pixclk;
5965
5966 intel_state->cdclk = intel_state->dev_cdclk =
5967 broxton_calc_cdclk(dev_priv, max_pixclk);
5968
5969 if (!intel_state->active_crtcs)
5970 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5971
5972 return 0;
5973 }
5974
5975 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5976 {
5977 unsigned int credits, default_credits;
5978
5979 if (IS_CHERRYVIEW(dev_priv))
5980 default_credits = PFI_CREDIT(12);
5981 else
5982 default_credits = PFI_CREDIT(8);
5983
5984 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5985 /* CHV suggested value is 31 or 63 */
5986 if (IS_CHERRYVIEW(dev_priv))
5987 credits = PFI_CREDIT_63;
5988 else
5989 credits = PFI_CREDIT(15);
5990 } else {
5991 credits = default_credits;
5992 }
5993
5994 /*
5995 * WA - write default credits before re-programming
5996 * FIXME: should we also set the resend bit here?
5997 */
5998 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5999 default_credits);
6000
6001 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6002 credits | PFI_CREDIT_RESEND);
6003
6004 /*
6005 * FIXME is this guaranteed to clear
6006 * immediately or should we poll for it?
6007 */
6008 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6009 }
6010
6011 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6012 {
6013 struct drm_device *dev = old_state->dev;
6014 struct drm_i915_private *dev_priv = dev->dev_private;
6015 struct intel_atomic_state *old_intel_state =
6016 to_intel_atomic_state(old_state);
6017 unsigned req_cdclk = old_intel_state->dev_cdclk;
6018
6019 /*
6020 * FIXME: We can end up here with all power domains off, yet
6021 * with a CDCLK frequency other than the minimum. To account
6022 * for this take the PIPE-A power domain, which covers the HW
6023 * blocks needed for the following programming. This can be
6024 * removed once it's guaranteed that we get here either with
6025 * the minimum CDCLK set, or the required power domains
6026 * enabled.
6027 */
6028 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6029
6030 if (IS_CHERRYVIEW(dev))
6031 cherryview_set_cdclk(dev, req_cdclk);
6032 else
6033 valleyview_set_cdclk(dev, req_cdclk);
6034
6035 vlv_program_pfi_credits(dev_priv);
6036
6037 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6038 }
6039
6040 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6041 {
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = to_i915(dev);
6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 struct intel_encoder *encoder;
6046 struct intel_crtc_state *pipe_config =
6047 to_intel_crtc_state(crtc->state);
6048 int pipe = intel_crtc->pipe;
6049
6050 if (WARN_ON(intel_crtc->active))
6051 return;
6052
6053 if (intel_crtc->config->has_dp_encoder)
6054 intel_dp_set_m_n(intel_crtc, M1_N1);
6055
6056 intel_set_pipe_timings(intel_crtc);
6057 intel_set_pipe_src_size(intel_crtc);
6058
6059 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6060 struct drm_i915_private *dev_priv = dev->dev_private;
6061
6062 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6063 I915_WRITE(CHV_CANVAS(pipe), 0);
6064 }
6065
6066 i9xx_set_pipeconf(intel_crtc);
6067
6068 intel_crtc->active = true;
6069
6070 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6071
6072 for_each_encoder_on_crtc(dev, crtc, encoder)
6073 if (encoder->pre_pll_enable)
6074 encoder->pre_pll_enable(encoder);
6075
6076 if (!intel_crtc->config->has_dsi_encoder) {
6077 if (IS_CHERRYVIEW(dev)) {
6078 chv_prepare_pll(intel_crtc, intel_crtc->config);
6079 chv_enable_pll(intel_crtc, intel_crtc->config);
6080 } else {
6081 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6082 vlv_enable_pll(intel_crtc, intel_crtc->config);
6083 }
6084 }
6085
6086 for_each_encoder_on_crtc(dev, crtc, encoder)
6087 if (encoder->pre_enable)
6088 encoder->pre_enable(encoder);
6089
6090 i9xx_pfit_enable(intel_crtc);
6091
6092 intel_color_load_luts(&pipe_config->base);
6093
6094 intel_update_watermarks(crtc);
6095 intel_enable_pipe(intel_crtc);
6096
6097 assert_vblank_disabled(crtc);
6098 drm_crtc_vblank_on(crtc);
6099
6100 for_each_encoder_on_crtc(dev, crtc, encoder)
6101 encoder->enable(encoder);
6102 }
6103
6104 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6105 {
6106 struct drm_device *dev = crtc->base.dev;
6107 struct drm_i915_private *dev_priv = dev->dev_private;
6108
6109 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6110 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6111 }
6112
6113 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6114 {
6115 struct drm_device *dev = crtc->dev;
6116 struct drm_i915_private *dev_priv = to_i915(dev);
6117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6118 struct intel_encoder *encoder;
6119 struct intel_crtc_state *pipe_config =
6120 to_intel_crtc_state(crtc->state);
6121 int pipe = intel_crtc->pipe;
6122
6123 if (WARN_ON(intel_crtc->active))
6124 return;
6125
6126 i9xx_set_pll_dividers(intel_crtc);
6127
6128 if (intel_crtc->config->has_dp_encoder)
6129 intel_dp_set_m_n(intel_crtc, M1_N1);
6130
6131 intel_set_pipe_timings(intel_crtc);
6132 intel_set_pipe_src_size(intel_crtc);
6133
6134 i9xx_set_pipeconf(intel_crtc);
6135
6136 intel_crtc->active = true;
6137
6138 if (!IS_GEN2(dev))
6139 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6140
6141 for_each_encoder_on_crtc(dev, crtc, encoder)
6142 if (encoder->pre_enable)
6143 encoder->pre_enable(encoder);
6144
6145 i9xx_enable_pll(intel_crtc);
6146
6147 i9xx_pfit_enable(intel_crtc);
6148
6149 intel_color_load_luts(&pipe_config->base);
6150
6151 intel_update_watermarks(crtc);
6152 intel_enable_pipe(intel_crtc);
6153
6154 assert_vblank_disabled(crtc);
6155 drm_crtc_vblank_on(crtc);
6156
6157 for_each_encoder_on_crtc(dev, crtc, encoder)
6158 encoder->enable(encoder);
6159 }
6160
6161 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6162 {
6163 struct drm_device *dev = crtc->base.dev;
6164 struct drm_i915_private *dev_priv = dev->dev_private;
6165
6166 if (!crtc->config->gmch_pfit.control)
6167 return;
6168
6169 assert_pipe_disabled(dev_priv, crtc->pipe);
6170
6171 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6172 I915_READ(PFIT_CONTROL));
6173 I915_WRITE(PFIT_CONTROL, 0);
6174 }
6175
6176 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6177 {
6178 struct drm_device *dev = crtc->dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181 struct intel_encoder *encoder;
6182 int pipe = intel_crtc->pipe;
6183
6184 /*
6185 * On gen2 planes are double buffered but the pipe isn't, so we must
6186 * wait for planes to fully turn off before disabling the pipe.
6187 */
6188 if (IS_GEN2(dev))
6189 intel_wait_for_vblank(dev, pipe);
6190
6191 for_each_encoder_on_crtc(dev, crtc, encoder)
6192 encoder->disable(encoder);
6193
6194 drm_crtc_vblank_off(crtc);
6195 assert_vblank_disabled(crtc);
6196
6197 intel_disable_pipe(intel_crtc);
6198
6199 i9xx_pfit_disable(intel_crtc);
6200
6201 for_each_encoder_on_crtc(dev, crtc, encoder)
6202 if (encoder->post_disable)
6203 encoder->post_disable(encoder);
6204
6205 if (!intel_crtc->config->has_dsi_encoder) {
6206 if (IS_CHERRYVIEW(dev))
6207 chv_disable_pll(dev_priv, pipe);
6208 else if (IS_VALLEYVIEW(dev))
6209 vlv_disable_pll(dev_priv, pipe);
6210 else
6211 i9xx_disable_pll(intel_crtc);
6212 }
6213
6214 for_each_encoder_on_crtc(dev, crtc, encoder)
6215 if (encoder->post_pll_disable)
6216 encoder->post_pll_disable(encoder);
6217
6218 if (!IS_GEN2(dev))
6219 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6220 }
6221
6222 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6223 {
6224 struct intel_encoder *encoder;
6225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6227 enum intel_display_power_domain domain;
6228 unsigned long domains;
6229
6230 if (!intel_crtc->active)
6231 return;
6232
6233 if (to_intel_plane_state(crtc->primary->state)->visible) {
6234 WARN_ON(intel_crtc->unpin_work);
6235
6236 intel_pre_disable_primary_noatomic(crtc);
6237
6238 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6239 to_intel_plane_state(crtc->primary->state)->visible = false;
6240 }
6241
6242 dev_priv->display.crtc_disable(crtc);
6243
6244 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6245 crtc->base.id);
6246
6247 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6248 crtc->state->active = false;
6249 intel_crtc->active = false;
6250 crtc->enabled = false;
6251 crtc->state->connector_mask = 0;
6252 crtc->state->encoder_mask = 0;
6253
6254 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6255 encoder->base.crtc = NULL;
6256
6257 intel_fbc_disable(intel_crtc);
6258 intel_update_watermarks(crtc);
6259 intel_disable_shared_dpll(intel_crtc);
6260
6261 domains = intel_crtc->enabled_power_domains;
6262 for_each_power_domain(domain, domains)
6263 intel_display_power_put(dev_priv, domain);
6264 intel_crtc->enabled_power_domains = 0;
6265
6266 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6267 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6268 }
6269
6270 /*
6271 * turn all crtc's off, but do not adjust state
6272 * This has to be paired with a call to intel_modeset_setup_hw_state.
6273 */
6274 int intel_display_suspend(struct drm_device *dev)
6275 {
6276 struct drm_i915_private *dev_priv = to_i915(dev);
6277 struct drm_atomic_state *state;
6278 int ret;
6279
6280 state = drm_atomic_helper_suspend(dev);
6281 ret = PTR_ERR_OR_ZERO(state);
6282 if (ret)
6283 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6284 else
6285 dev_priv->modeset_restore_state = state;
6286 return ret;
6287 }
6288
6289 void intel_encoder_destroy(struct drm_encoder *encoder)
6290 {
6291 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6292
6293 drm_encoder_cleanup(encoder);
6294 kfree(intel_encoder);
6295 }
6296
6297 /* Cross check the actual hw state with our own modeset state tracking (and it's
6298 * internal consistency). */
6299 static void intel_connector_verify_state(struct intel_connector *connector)
6300 {
6301 struct drm_crtc *crtc = connector->base.state->crtc;
6302
6303 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6304 connector->base.base.id,
6305 connector->base.name);
6306
6307 if (connector->get_hw_state(connector)) {
6308 struct intel_encoder *encoder = connector->encoder;
6309 struct drm_connector_state *conn_state = connector->base.state;
6310
6311 I915_STATE_WARN(!crtc,
6312 "connector enabled without attached crtc\n");
6313
6314 if (!crtc)
6315 return;
6316
6317 I915_STATE_WARN(!crtc->state->active,
6318 "connector is active, but attached crtc isn't\n");
6319
6320 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6321 return;
6322
6323 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6324 "atomic encoder doesn't match attached encoder\n");
6325
6326 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6327 "attached encoder crtc differs from connector crtc\n");
6328 } else {
6329 I915_STATE_WARN(crtc && crtc->state->active,
6330 "attached crtc is active, but connector isn't\n");
6331 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6332 "best encoder set without crtc!\n");
6333 }
6334 }
6335
6336 int intel_connector_init(struct intel_connector *connector)
6337 {
6338 drm_atomic_helper_connector_reset(&connector->base);
6339
6340 if (!connector->base.state)
6341 return -ENOMEM;
6342
6343 return 0;
6344 }
6345
6346 struct intel_connector *intel_connector_alloc(void)
6347 {
6348 struct intel_connector *connector;
6349
6350 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6351 if (!connector)
6352 return NULL;
6353
6354 if (intel_connector_init(connector) < 0) {
6355 kfree(connector);
6356 return NULL;
6357 }
6358
6359 return connector;
6360 }
6361
6362 /* Simple connector->get_hw_state implementation for encoders that support only
6363 * one connector and no cloning and hence the encoder state determines the state
6364 * of the connector. */
6365 bool intel_connector_get_hw_state(struct intel_connector *connector)
6366 {
6367 enum pipe pipe = 0;
6368 struct intel_encoder *encoder = connector->encoder;
6369
6370 return encoder->get_hw_state(encoder, &pipe);
6371 }
6372
6373 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6374 {
6375 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6376 return crtc_state->fdi_lanes;
6377
6378 return 0;
6379 }
6380
6381 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6382 struct intel_crtc_state *pipe_config)
6383 {
6384 struct drm_atomic_state *state = pipe_config->base.state;
6385 struct intel_crtc *other_crtc;
6386 struct intel_crtc_state *other_crtc_state;
6387
6388 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6389 pipe_name(pipe), pipe_config->fdi_lanes);
6390 if (pipe_config->fdi_lanes > 4) {
6391 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6392 pipe_name(pipe), pipe_config->fdi_lanes);
6393 return -EINVAL;
6394 }
6395
6396 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6397 if (pipe_config->fdi_lanes > 2) {
6398 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6399 pipe_config->fdi_lanes);
6400 return -EINVAL;
6401 } else {
6402 return 0;
6403 }
6404 }
6405
6406 if (INTEL_INFO(dev)->num_pipes == 2)
6407 return 0;
6408
6409 /* Ivybridge 3 pipe is really complicated */
6410 switch (pipe) {
6411 case PIPE_A:
6412 return 0;
6413 case PIPE_B:
6414 if (pipe_config->fdi_lanes <= 2)
6415 return 0;
6416
6417 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6418 other_crtc_state =
6419 intel_atomic_get_crtc_state(state, other_crtc);
6420 if (IS_ERR(other_crtc_state))
6421 return PTR_ERR(other_crtc_state);
6422
6423 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6424 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6425 pipe_name(pipe), pipe_config->fdi_lanes);
6426 return -EINVAL;
6427 }
6428 return 0;
6429 case PIPE_C:
6430 if (pipe_config->fdi_lanes > 2) {
6431 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6432 pipe_name(pipe), pipe_config->fdi_lanes);
6433 return -EINVAL;
6434 }
6435
6436 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6437 other_crtc_state =
6438 intel_atomic_get_crtc_state(state, other_crtc);
6439 if (IS_ERR(other_crtc_state))
6440 return PTR_ERR(other_crtc_state);
6441
6442 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6443 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6444 return -EINVAL;
6445 }
6446 return 0;
6447 default:
6448 BUG();
6449 }
6450 }
6451
6452 #define RETRY 1
6453 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6454 struct intel_crtc_state *pipe_config)
6455 {
6456 struct drm_device *dev = intel_crtc->base.dev;
6457 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6458 int lane, link_bw, fdi_dotclock, ret;
6459 bool needs_recompute = false;
6460
6461 retry:
6462 /* FDI is a binary signal running at ~2.7GHz, encoding
6463 * each output octet as 10 bits. The actual frequency
6464 * is stored as a divider into a 100MHz clock, and the
6465 * mode pixel clock is stored in units of 1KHz.
6466 * Hence the bw of each lane in terms of the mode signal
6467 * is:
6468 */
6469 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6470
6471 fdi_dotclock = adjusted_mode->crtc_clock;
6472
6473 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6474 pipe_config->pipe_bpp);
6475
6476 pipe_config->fdi_lanes = lane;
6477
6478 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6479 link_bw, &pipe_config->fdi_m_n);
6480
6481 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6482 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6483 pipe_config->pipe_bpp -= 2*3;
6484 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6485 pipe_config->pipe_bpp);
6486 needs_recompute = true;
6487 pipe_config->bw_constrained = true;
6488
6489 goto retry;
6490 }
6491
6492 if (needs_recompute)
6493 return RETRY;
6494
6495 return ret;
6496 }
6497
6498 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6499 struct intel_crtc_state *pipe_config)
6500 {
6501 if (pipe_config->pipe_bpp > 24)
6502 return false;
6503
6504 /* HSW can handle pixel rate up to cdclk? */
6505 if (IS_HASWELL(dev_priv))
6506 return true;
6507
6508 /*
6509 * We compare against max which means we must take
6510 * the increased cdclk requirement into account when
6511 * calculating the new cdclk.
6512 *
6513 * Should measure whether using a lower cdclk w/o IPS
6514 */
6515 return ilk_pipe_pixel_rate(pipe_config) <=
6516 dev_priv->max_cdclk_freq * 95 / 100;
6517 }
6518
6519 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6520 struct intel_crtc_state *pipe_config)
6521 {
6522 struct drm_device *dev = crtc->base.dev;
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524
6525 pipe_config->ips_enabled = i915.enable_ips &&
6526 hsw_crtc_supports_ips(crtc) &&
6527 pipe_config_supports_ips(dev_priv, pipe_config);
6528 }
6529
6530 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6531 {
6532 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6533
6534 /* GDG double wide on either pipe, otherwise pipe A only */
6535 return INTEL_INFO(dev_priv)->gen < 4 &&
6536 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6537 }
6538
6539 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6540 struct intel_crtc_state *pipe_config)
6541 {
6542 struct drm_device *dev = crtc->base.dev;
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6545
6546 /* FIXME should check pixel clock limits on all platforms */
6547 if (INTEL_INFO(dev)->gen < 4) {
6548 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6549
6550 /*
6551 * Enable double wide mode when the dot clock
6552 * is > 90% of the (display) core speed.
6553 */
6554 if (intel_crtc_supports_double_wide(crtc) &&
6555 adjusted_mode->crtc_clock > clock_limit) {
6556 clock_limit *= 2;
6557 pipe_config->double_wide = true;
6558 }
6559
6560 if (adjusted_mode->crtc_clock > clock_limit) {
6561 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6562 adjusted_mode->crtc_clock, clock_limit,
6563 yesno(pipe_config->double_wide));
6564 return -EINVAL;
6565 }
6566 }
6567
6568 /*
6569 * Pipe horizontal size must be even in:
6570 * - DVO ganged mode
6571 * - LVDS dual channel mode
6572 * - Double wide pipe
6573 */
6574 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6575 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6576 pipe_config->pipe_src_w &= ~1;
6577
6578 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6579 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6580 */
6581 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6582 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6583 return -EINVAL;
6584
6585 if (HAS_IPS(dev))
6586 hsw_compute_ips_config(crtc, pipe_config);
6587
6588 if (pipe_config->has_pch_encoder)
6589 return ironlake_fdi_compute_config(crtc, pipe_config);
6590
6591 return 0;
6592 }
6593
6594 static int skylake_get_display_clock_speed(struct drm_device *dev)
6595 {
6596 struct drm_i915_private *dev_priv = to_i915(dev);
6597 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6598 uint32_t cdctl = I915_READ(CDCLK_CTL);
6599 uint32_t linkrate;
6600
6601 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6602 return 24000; /* 24MHz is the cd freq with NSSC ref */
6603
6604 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6605 return 540000;
6606
6607 linkrate = (I915_READ(DPLL_CTRL1) &
6608 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6609
6610 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6611 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6612 /* vco 8640 */
6613 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6614 case CDCLK_FREQ_450_432:
6615 return 432000;
6616 case CDCLK_FREQ_337_308:
6617 return 308570;
6618 case CDCLK_FREQ_675_617:
6619 return 617140;
6620 default:
6621 WARN(1, "Unknown cd freq selection\n");
6622 }
6623 } else {
6624 /* vco 8100 */
6625 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6626 case CDCLK_FREQ_450_432:
6627 return 450000;
6628 case CDCLK_FREQ_337_308:
6629 return 337500;
6630 case CDCLK_FREQ_675_617:
6631 return 675000;
6632 default:
6633 WARN(1, "Unknown cd freq selection\n");
6634 }
6635 }
6636
6637 /* error case, do as if DPLL0 isn't enabled */
6638 return 24000;
6639 }
6640
6641 static int broxton_get_display_clock_speed(struct drm_device *dev)
6642 {
6643 struct drm_i915_private *dev_priv = to_i915(dev);
6644 uint32_t cdctl = I915_READ(CDCLK_CTL);
6645 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6646 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6647 int cdclk;
6648
6649 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6650 return 19200;
6651
6652 cdclk = 19200 * pll_ratio / 2;
6653
6654 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6655 case BXT_CDCLK_CD2X_DIV_SEL_1:
6656 return cdclk; /* 576MHz or 624MHz */
6657 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6658 return cdclk * 2 / 3; /* 384MHz */
6659 case BXT_CDCLK_CD2X_DIV_SEL_2:
6660 return cdclk / 2; /* 288MHz */
6661 case BXT_CDCLK_CD2X_DIV_SEL_4:
6662 return cdclk / 4; /* 144MHz */
6663 }
6664
6665 /* error case, do as if DE PLL isn't enabled */
6666 return 19200;
6667 }
6668
6669 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6670 {
6671 struct drm_i915_private *dev_priv = dev->dev_private;
6672 uint32_t lcpll = I915_READ(LCPLL_CTL);
6673 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6674
6675 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6676 return 800000;
6677 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6678 return 450000;
6679 else if (freq == LCPLL_CLK_FREQ_450)
6680 return 450000;
6681 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6682 return 540000;
6683 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6684 return 337500;
6685 else
6686 return 675000;
6687 }
6688
6689 static int haswell_get_display_clock_speed(struct drm_device *dev)
6690 {
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 uint32_t lcpll = I915_READ(LCPLL_CTL);
6693 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6694
6695 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6696 return 800000;
6697 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6698 return 450000;
6699 else if (freq == LCPLL_CLK_FREQ_450)
6700 return 450000;
6701 else if (IS_HSW_ULT(dev))
6702 return 337500;
6703 else
6704 return 540000;
6705 }
6706
6707 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6708 {
6709 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6710 CCK_DISPLAY_CLOCK_CONTROL);
6711 }
6712
6713 static int ilk_get_display_clock_speed(struct drm_device *dev)
6714 {
6715 return 450000;
6716 }
6717
6718 static int i945_get_display_clock_speed(struct drm_device *dev)
6719 {
6720 return 400000;
6721 }
6722
6723 static int i915_get_display_clock_speed(struct drm_device *dev)
6724 {
6725 return 333333;
6726 }
6727
6728 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6729 {
6730 return 200000;
6731 }
6732
6733 static int pnv_get_display_clock_speed(struct drm_device *dev)
6734 {
6735 u16 gcfgc = 0;
6736
6737 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6738
6739 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6740 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6741 return 266667;
6742 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6743 return 333333;
6744 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6745 return 444444;
6746 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6747 return 200000;
6748 default:
6749 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6750 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6751 return 133333;
6752 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6753 return 166667;
6754 }
6755 }
6756
6757 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6758 {
6759 u16 gcfgc = 0;
6760
6761 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6762
6763 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6764 return 133333;
6765 else {
6766 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6767 case GC_DISPLAY_CLOCK_333_MHZ:
6768 return 333333;
6769 default:
6770 case GC_DISPLAY_CLOCK_190_200_MHZ:
6771 return 190000;
6772 }
6773 }
6774 }
6775
6776 static int i865_get_display_clock_speed(struct drm_device *dev)
6777 {
6778 return 266667;
6779 }
6780
6781 static int i85x_get_display_clock_speed(struct drm_device *dev)
6782 {
6783 u16 hpllcc = 0;
6784
6785 /*
6786 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6787 * encoding is different :(
6788 * FIXME is this the right way to detect 852GM/852GMV?
6789 */
6790 if (dev->pdev->revision == 0x1)
6791 return 133333;
6792
6793 pci_bus_read_config_word(dev->pdev->bus,
6794 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6795
6796 /* Assume that the hardware is in the high speed state. This
6797 * should be the default.
6798 */
6799 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6800 case GC_CLOCK_133_200:
6801 case GC_CLOCK_133_200_2:
6802 case GC_CLOCK_100_200:
6803 return 200000;
6804 case GC_CLOCK_166_250:
6805 return 250000;
6806 case GC_CLOCK_100_133:
6807 return 133333;
6808 case GC_CLOCK_133_266:
6809 case GC_CLOCK_133_266_2:
6810 case GC_CLOCK_166_266:
6811 return 266667;
6812 }
6813
6814 /* Shouldn't happen */
6815 return 0;
6816 }
6817
6818 static int i830_get_display_clock_speed(struct drm_device *dev)
6819 {
6820 return 133333;
6821 }
6822
6823 static unsigned int intel_hpll_vco(struct drm_device *dev)
6824 {
6825 struct drm_i915_private *dev_priv = dev->dev_private;
6826 static const unsigned int blb_vco[8] = {
6827 [0] = 3200000,
6828 [1] = 4000000,
6829 [2] = 5333333,
6830 [3] = 4800000,
6831 [4] = 6400000,
6832 };
6833 static const unsigned int pnv_vco[8] = {
6834 [0] = 3200000,
6835 [1] = 4000000,
6836 [2] = 5333333,
6837 [3] = 4800000,
6838 [4] = 2666667,
6839 };
6840 static const unsigned int cl_vco[8] = {
6841 [0] = 3200000,
6842 [1] = 4000000,
6843 [2] = 5333333,
6844 [3] = 6400000,
6845 [4] = 3333333,
6846 [5] = 3566667,
6847 [6] = 4266667,
6848 };
6849 static const unsigned int elk_vco[8] = {
6850 [0] = 3200000,
6851 [1] = 4000000,
6852 [2] = 5333333,
6853 [3] = 4800000,
6854 };
6855 static const unsigned int ctg_vco[8] = {
6856 [0] = 3200000,
6857 [1] = 4000000,
6858 [2] = 5333333,
6859 [3] = 6400000,
6860 [4] = 2666667,
6861 [5] = 4266667,
6862 };
6863 const unsigned int *vco_table;
6864 unsigned int vco;
6865 uint8_t tmp = 0;
6866
6867 /* FIXME other chipsets? */
6868 if (IS_GM45(dev))
6869 vco_table = ctg_vco;
6870 else if (IS_G4X(dev))
6871 vco_table = elk_vco;
6872 else if (IS_CRESTLINE(dev))
6873 vco_table = cl_vco;
6874 else if (IS_PINEVIEW(dev))
6875 vco_table = pnv_vco;
6876 else if (IS_G33(dev))
6877 vco_table = blb_vco;
6878 else
6879 return 0;
6880
6881 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6882
6883 vco = vco_table[tmp & 0x7];
6884 if (vco == 0)
6885 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6886 else
6887 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6888
6889 return vco;
6890 }
6891
6892 static int gm45_get_display_clock_speed(struct drm_device *dev)
6893 {
6894 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6895 uint16_t tmp = 0;
6896
6897 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6898
6899 cdclk_sel = (tmp >> 12) & 0x1;
6900
6901 switch (vco) {
6902 case 2666667:
6903 case 4000000:
6904 case 5333333:
6905 return cdclk_sel ? 333333 : 222222;
6906 case 3200000:
6907 return cdclk_sel ? 320000 : 228571;
6908 default:
6909 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6910 return 222222;
6911 }
6912 }
6913
6914 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6915 {
6916 static const uint8_t div_3200[] = { 16, 10, 8 };
6917 static const uint8_t div_4000[] = { 20, 12, 10 };
6918 static const uint8_t div_5333[] = { 24, 16, 14 };
6919 const uint8_t *div_table;
6920 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6921 uint16_t tmp = 0;
6922
6923 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6924
6925 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6926
6927 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6928 goto fail;
6929
6930 switch (vco) {
6931 case 3200000:
6932 div_table = div_3200;
6933 break;
6934 case 4000000:
6935 div_table = div_4000;
6936 break;
6937 case 5333333:
6938 div_table = div_5333;
6939 break;
6940 default:
6941 goto fail;
6942 }
6943
6944 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6945
6946 fail:
6947 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6948 return 200000;
6949 }
6950
6951 static int g33_get_display_clock_speed(struct drm_device *dev)
6952 {
6953 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6954 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6955 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6956 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6957 const uint8_t *div_table;
6958 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6959 uint16_t tmp = 0;
6960
6961 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6962
6963 cdclk_sel = (tmp >> 4) & 0x7;
6964
6965 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6966 goto fail;
6967
6968 switch (vco) {
6969 case 3200000:
6970 div_table = div_3200;
6971 break;
6972 case 4000000:
6973 div_table = div_4000;
6974 break;
6975 case 4800000:
6976 div_table = div_4800;
6977 break;
6978 case 5333333:
6979 div_table = div_5333;
6980 break;
6981 default:
6982 goto fail;
6983 }
6984
6985 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6986
6987 fail:
6988 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6989 return 190476;
6990 }
6991
6992 static void
6993 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6994 {
6995 while (*num > DATA_LINK_M_N_MASK ||
6996 *den > DATA_LINK_M_N_MASK) {
6997 *num >>= 1;
6998 *den >>= 1;
6999 }
7000 }
7001
7002 static void compute_m_n(unsigned int m, unsigned int n,
7003 uint32_t *ret_m, uint32_t *ret_n)
7004 {
7005 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7006 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7007 intel_reduce_m_n_ratio(ret_m, ret_n);
7008 }
7009
7010 void
7011 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7012 int pixel_clock, int link_clock,
7013 struct intel_link_m_n *m_n)
7014 {
7015 m_n->tu = 64;
7016
7017 compute_m_n(bits_per_pixel * pixel_clock,
7018 link_clock * nlanes * 8,
7019 &m_n->gmch_m, &m_n->gmch_n);
7020
7021 compute_m_n(pixel_clock, link_clock,
7022 &m_n->link_m, &m_n->link_n);
7023 }
7024
7025 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7026 {
7027 if (i915.panel_use_ssc >= 0)
7028 return i915.panel_use_ssc != 0;
7029 return dev_priv->vbt.lvds_use_ssc
7030 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7031 }
7032
7033 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7034 {
7035 return (1 << dpll->n) << 16 | dpll->m2;
7036 }
7037
7038 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7039 {
7040 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7041 }
7042
7043 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7044 struct intel_crtc_state *crtc_state,
7045 intel_clock_t *reduced_clock)
7046 {
7047 struct drm_device *dev = crtc->base.dev;
7048 u32 fp, fp2 = 0;
7049
7050 if (IS_PINEVIEW(dev)) {
7051 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7052 if (reduced_clock)
7053 fp2 = pnv_dpll_compute_fp(reduced_clock);
7054 } else {
7055 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7056 if (reduced_clock)
7057 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7058 }
7059
7060 crtc_state->dpll_hw_state.fp0 = fp;
7061
7062 crtc->lowfreq_avail = false;
7063 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7064 reduced_clock) {
7065 crtc_state->dpll_hw_state.fp1 = fp2;
7066 crtc->lowfreq_avail = true;
7067 } else {
7068 crtc_state->dpll_hw_state.fp1 = fp;
7069 }
7070 }
7071
7072 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7073 pipe)
7074 {
7075 u32 reg_val;
7076
7077 /*
7078 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7079 * and set it to a reasonable value instead.
7080 */
7081 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7082 reg_val &= 0xffffff00;
7083 reg_val |= 0x00000030;
7084 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7085
7086 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7087 reg_val &= 0x8cffffff;
7088 reg_val = 0x8c000000;
7089 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7090
7091 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7092 reg_val &= 0xffffff00;
7093 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7094
7095 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7096 reg_val &= 0x00ffffff;
7097 reg_val |= 0xb0000000;
7098 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7099 }
7100
7101 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7102 struct intel_link_m_n *m_n)
7103 {
7104 struct drm_device *dev = crtc->base.dev;
7105 struct drm_i915_private *dev_priv = dev->dev_private;
7106 int pipe = crtc->pipe;
7107
7108 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7109 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7110 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7111 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7112 }
7113
7114 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7115 struct intel_link_m_n *m_n,
7116 struct intel_link_m_n *m2_n2)
7117 {
7118 struct drm_device *dev = crtc->base.dev;
7119 struct drm_i915_private *dev_priv = dev->dev_private;
7120 int pipe = crtc->pipe;
7121 enum transcoder transcoder = crtc->config->cpu_transcoder;
7122
7123 if (INTEL_INFO(dev)->gen >= 5) {
7124 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7125 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7126 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7127 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7128 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7129 * for gen < 8) and if DRRS is supported (to make sure the
7130 * registers are not unnecessarily accessed).
7131 */
7132 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7133 crtc->config->has_drrs) {
7134 I915_WRITE(PIPE_DATA_M2(transcoder),
7135 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7136 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7137 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7138 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7139 }
7140 } else {
7141 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7142 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7143 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7144 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7145 }
7146 }
7147
7148 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7149 {
7150 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7151
7152 if (m_n == M1_N1) {
7153 dp_m_n = &crtc->config->dp_m_n;
7154 dp_m2_n2 = &crtc->config->dp_m2_n2;
7155 } else if (m_n == M2_N2) {
7156
7157 /*
7158 * M2_N2 registers are not supported. Hence m2_n2 divider value
7159 * needs to be programmed into M1_N1.
7160 */
7161 dp_m_n = &crtc->config->dp_m2_n2;
7162 } else {
7163 DRM_ERROR("Unsupported divider value\n");
7164 return;
7165 }
7166
7167 if (crtc->config->has_pch_encoder)
7168 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7169 else
7170 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7171 }
7172
7173 static void vlv_compute_dpll(struct intel_crtc *crtc,
7174 struct intel_crtc_state *pipe_config)
7175 {
7176 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7177 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7178 DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
7179 if (crtc->pipe != PIPE_A)
7180 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7181
7182 pipe_config->dpll_hw_state.dpll_md =
7183 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7184 }
7185
7186 static void chv_compute_dpll(struct intel_crtc *crtc,
7187 struct intel_crtc_state *pipe_config)
7188 {
7189 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7190 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7191 DPLL_VCO_ENABLE;
7192 if (crtc->pipe != PIPE_A)
7193 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7194
7195 pipe_config->dpll_hw_state.dpll_md =
7196 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7197 }
7198
7199 static void vlv_prepare_pll(struct intel_crtc *crtc,
7200 const struct intel_crtc_state *pipe_config)
7201 {
7202 struct drm_device *dev = crtc->base.dev;
7203 struct drm_i915_private *dev_priv = dev->dev_private;
7204 int pipe = crtc->pipe;
7205 u32 mdiv;
7206 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7207 u32 coreclk, reg_val;
7208
7209 mutex_lock(&dev_priv->sb_lock);
7210
7211 bestn = pipe_config->dpll.n;
7212 bestm1 = pipe_config->dpll.m1;
7213 bestm2 = pipe_config->dpll.m2;
7214 bestp1 = pipe_config->dpll.p1;
7215 bestp2 = pipe_config->dpll.p2;
7216
7217 /* See eDP HDMI DPIO driver vbios notes doc */
7218
7219 /* PLL B needs special handling */
7220 if (pipe == PIPE_B)
7221 vlv_pllb_recal_opamp(dev_priv, pipe);
7222
7223 /* Set up Tx target for periodic Rcomp update */
7224 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7225
7226 /* Disable target IRef on PLL */
7227 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7228 reg_val &= 0x00ffffff;
7229 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7230
7231 /* Disable fast lock */
7232 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7233
7234 /* Set idtafcrecal before PLL is enabled */
7235 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7236 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7237 mdiv |= ((bestn << DPIO_N_SHIFT));
7238 mdiv |= (1 << DPIO_K_SHIFT);
7239
7240 /*
7241 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7242 * but we don't support that).
7243 * Note: don't use the DAC post divider as it seems unstable.
7244 */
7245 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7247
7248 mdiv |= DPIO_ENABLE_CALIBRATION;
7249 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7250
7251 /* Set HBR and RBR LPF coefficients */
7252 if (pipe_config->port_clock == 162000 ||
7253 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7254 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7256 0x009f0003);
7257 else
7258 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7259 0x00d0000f);
7260
7261 if (pipe_config->has_dp_encoder) {
7262 /* Use SSC source */
7263 if (pipe == PIPE_A)
7264 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7265 0x0df40000);
7266 else
7267 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7268 0x0df70000);
7269 } else { /* HDMI or VGA */
7270 /* Use bend source */
7271 if (pipe == PIPE_A)
7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7273 0x0df70000);
7274 else
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7276 0x0df40000);
7277 }
7278
7279 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7280 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7281 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7282 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7283 coreclk |= 0x01000000;
7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7285
7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7287 mutex_unlock(&dev_priv->sb_lock);
7288 }
7289
7290 static void chv_prepare_pll(struct intel_crtc *crtc,
7291 const struct intel_crtc_state *pipe_config)
7292 {
7293 struct drm_device *dev = crtc->base.dev;
7294 struct drm_i915_private *dev_priv = dev->dev_private;
7295 int pipe = crtc->pipe;
7296 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7297 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7298 u32 loopfilter, tribuf_calcntr;
7299 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7300 u32 dpio_val;
7301 int vco;
7302
7303 bestn = pipe_config->dpll.n;
7304 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7305 bestm1 = pipe_config->dpll.m1;
7306 bestm2 = pipe_config->dpll.m2 >> 22;
7307 bestp1 = pipe_config->dpll.p1;
7308 bestp2 = pipe_config->dpll.p2;
7309 vco = pipe_config->dpll.vco;
7310 dpio_val = 0;
7311 loopfilter = 0;
7312
7313 /*
7314 * Enable Refclk and SSC
7315 */
7316 I915_WRITE(dpll_reg,
7317 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7318
7319 mutex_lock(&dev_priv->sb_lock);
7320
7321 /* p1 and p2 divider */
7322 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7323 5 << DPIO_CHV_S1_DIV_SHIFT |
7324 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7325 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7326 1 << DPIO_CHV_K_DIV_SHIFT);
7327
7328 /* Feedback post-divider - m2 */
7329 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7330
7331 /* Feedback refclk divider - n and m1 */
7332 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7333 DPIO_CHV_M1_DIV_BY_2 |
7334 1 << DPIO_CHV_N_DIV_SHIFT);
7335
7336 /* M2 fraction division */
7337 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7338
7339 /* M2 fraction division enable */
7340 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7341 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7342 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7343 if (bestm2_frac)
7344 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7345 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7346
7347 /* Program digital lock detect threshold */
7348 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7349 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7350 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7351 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7352 if (!bestm2_frac)
7353 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7354 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7355
7356 /* Loop filter */
7357 if (vco == 5400000) {
7358 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7359 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7360 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7361 tribuf_calcntr = 0x9;
7362 } else if (vco <= 6200000) {
7363 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7364 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7365 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7366 tribuf_calcntr = 0x9;
7367 } else if (vco <= 6480000) {
7368 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7369 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7370 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7371 tribuf_calcntr = 0x8;
7372 } else {
7373 /* Not supported. Apply the same limits as in the max case */
7374 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7375 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7376 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7377 tribuf_calcntr = 0;
7378 }
7379 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7380
7381 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7382 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7383 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7385
7386 /* AFC Recal */
7387 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7388 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7389 DPIO_AFC_RECAL);
7390
7391 mutex_unlock(&dev_priv->sb_lock);
7392 }
7393
7394 /**
7395 * vlv_force_pll_on - forcibly enable just the PLL
7396 * @dev_priv: i915 private structure
7397 * @pipe: pipe PLL to enable
7398 * @dpll: PLL configuration
7399 *
7400 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7401 * in cases where we need the PLL enabled even when @pipe is not going to
7402 * be enabled.
7403 */
7404 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7405 const struct dpll *dpll)
7406 {
7407 struct intel_crtc *crtc =
7408 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7409 struct intel_crtc_state *pipe_config;
7410
7411 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7412 if (!pipe_config)
7413 return -ENOMEM;
7414
7415 pipe_config->base.crtc = &crtc->base;
7416 pipe_config->pixel_multiplier = 1;
7417 pipe_config->dpll = *dpll;
7418
7419 if (IS_CHERRYVIEW(dev)) {
7420 chv_compute_dpll(crtc, pipe_config);
7421 chv_prepare_pll(crtc, pipe_config);
7422 chv_enable_pll(crtc, pipe_config);
7423 } else {
7424 vlv_compute_dpll(crtc, pipe_config);
7425 vlv_prepare_pll(crtc, pipe_config);
7426 vlv_enable_pll(crtc, pipe_config);
7427 }
7428
7429 kfree(pipe_config);
7430
7431 return 0;
7432 }
7433
7434 /**
7435 * vlv_force_pll_off - forcibly disable just the PLL
7436 * @dev_priv: i915 private structure
7437 * @pipe: pipe PLL to disable
7438 *
7439 * Disable the PLL for @pipe. To be used in cases where we need
7440 * the PLL enabled even when @pipe is not going to be enabled.
7441 */
7442 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7443 {
7444 if (IS_CHERRYVIEW(dev))
7445 chv_disable_pll(to_i915(dev), pipe);
7446 else
7447 vlv_disable_pll(to_i915(dev), pipe);
7448 }
7449
7450 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7451 struct intel_crtc_state *crtc_state,
7452 intel_clock_t *reduced_clock)
7453 {
7454 struct drm_device *dev = crtc->base.dev;
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 u32 dpll;
7457 bool is_sdvo;
7458 struct dpll *clock = &crtc_state->dpll;
7459
7460 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7461
7462 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7463 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7464
7465 dpll = DPLL_VGA_MODE_DIS;
7466
7467 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7468 dpll |= DPLLB_MODE_LVDS;
7469 else
7470 dpll |= DPLLB_MODE_DAC_SERIAL;
7471
7472 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7473 dpll |= (crtc_state->pixel_multiplier - 1)
7474 << SDVO_MULTIPLIER_SHIFT_HIRES;
7475 }
7476
7477 if (is_sdvo)
7478 dpll |= DPLL_SDVO_HIGH_SPEED;
7479
7480 if (crtc_state->has_dp_encoder)
7481 dpll |= DPLL_SDVO_HIGH_SPEED;
7482
7483 /* compute bitmask from p1 value */
7484 if (IS_PINEVIEW(dev))
7485 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7486 else {
7487 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7488 if (IS_G4X(dev) && reduced_clock)
7489 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7490 }
7491 switch (clock->p2) {
7492 case 5:
7493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7494 break;
7495 case 7:
7496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7497 break;
7498 case 10:
7499 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7500 break;
7501 case 14:
7502 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7503 break;
7504 }
7505 if (INTEL_INFO(dev)->gen >= 4)
7506 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7507
7508 if (crtc_state->sdvo_tv_clock)
7509 dpll |= PLL_REF_INPUT_TVCLKINBC;
7510 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7511 intel_panel_use_ssc(dev_priv))
7512 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7513 else
7514 dpll |= PLL_REF_INPUT_DREFCLK;
7515
7516 dpll |= DPLL_VCO_ENABLE;
7517 crtc_state->dpll_hw_state.dpll = dpll;
7518
7519 if (INTEL_INFO(dev)->gen >= 4) {
7520 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7521 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7522 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7523 }
7524 }
7525
7526 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7527 struct intel_crtc_state *crtc_state,
7528 intel_clock_t *reduced_clock)
7529 {
7530 struct drm_device *dev = crtc->base.dev;
7531 struct drm_i915_private *dev_priv = dev->dev_private;
7532 u32 dpll;
7533 struct dpll *clock = &crtc_state->dpll;
7534
7535 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7536
7537 dpll = DPLL_VGA_MODE_DIS;
7538
7539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7540 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7541 } else {
7542 if (clock->p1 == 2)
7543 dpll |= PLL_P1_DIVIDE_BY_TWO;
7544 else
7545 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7546 if (clock->p2 == 4)
7547 dpll |= PLL_P2_DIVIDE_BY_4;
7548 }
7549
7550 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7551 dpll |= DPLL_DVO_2X_MODE;
7552
7553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7554 intel_panel_use_ssc(dev_priv))
7555 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7556 else
7557 dpll |= PLL_REF_INPUT_DREFCLK;
7558
7559 dpll |= DPLL_VCO_ENABLE;
7560 crtc_state->dpll_hw_state.dpll = dpll;
7561 }
7562
7563 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7564 {
7565 struct drm_device *dev = intel_crtc->base.dev;
7566 struct drm_i915_private *dev_priv = dev->dev_private;
7567 enum pipe pipe = intel_crtc->pipe;
7568 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7569 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7570 uint32_t crtc_vtotal, crtc_vblank_end;
7571 int vsyncshift = 0;
7572
7573 /* We need to be careful not to changed the adjusted mode, for otherwise
7574 * the hw state checker will get angry at the mismatch. */
7575 crtc_vtotal = adjusted_mode->crtc_vtotal;
7576 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7577
7578 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7579 /* the chip adds 2 halflines automatically */
7580 crtc_vtotal -= 1;
7581 crtc_vblank_end -= 1;
7582
7583 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7584 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7585 else
7586 vsyncshift = adjusted_mode->crtc_hsync_start -
7587 adjusted_mode->crtc_htotal / 2;
7588 if (vsyncshift < 0)
7589 vsyncshift += adjusted_mode->crtc_htotal;
7590 }
7591
7592 if (INTEL_INFO(dev)->gen > 3)
7593 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7594
7595 I915_WRITE(HTOTAL(cpu_transcoder),
7596 (adjusted_mode->crtc_hdisplay - 1) |
7597 ((adjusted_mode->crtc_htotal - 1) << 16));
7598 I915_WRITE(HBLANK(cpu_transcoder),
7599 (adjusted_mode->crtc_hblank_start - 1) |
7600 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7601 I915_WRITE(HSYNC(cpu_transcoder),
7602 (adjusted_mode->crtc_hsync_start - 1) |
7603 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7604
7605 I915_WRITE(VTOTAL(cpu_transcoder),
7606 (adjusted_mode->crtc_vdisplay - 1) |
7607 ((crtc_vtotal - 1) << 16));
7608 I915_WRITE(VBLANK(cpu_transcoder),
7609 (adjusted_mode->crtc_vblank_start - 1) |
7610 ((crtc_vblank_end - 1) << 16));
7611 I915_WRITE(VSYNC(cpu_transcoder),
7612 (adjusted_mode->crtc_vsync_start - 1) |
7613 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7614
7615 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7616 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7617 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7618 * bits. */
7619 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7620 (pipe == PIPE_B || pipe == PIPE_C))
7621 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7622
7623 }
7624
7625 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7626 {
7627 struct drm_device *dev = intel_crtc->base.dev;
7628 struct drm_i915_private *dev_priv = dev->dev_private;
7629 enum pipe pipe = intel_crtc->pipe;
7630
7631 /* pipesrc controls the size that is scaled from, which should
7632 * always be the user's requested size.
7633 */
7634 I915_WRITE(PIPESRC(pipe),
7635 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7636 (intel_crtc->config->pipe_src_h - 1));
7637 }
7638
7639 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7640 struct intel_crtc_state *pipe_config)
7641 {
7642 struct drm_device *dev = crtc->base.dev;
7643 struct drm_i915_private *dev_priv = dev->dev_private;
7644 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7645 uint32_t tmp;
7646
7647 tmp = I915_READ(HTOTAL(cpu_transcoder));
7648 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7649 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7650 tmp = I915_READ(HBLANK(cpu_transcoder));
7651 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7652 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7653 tmp = I915_READ(HSYNC(cpu_transcoder));
7654 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7655 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7656
7657 tmp = I915_READ(VTOTAL(cpu_transcoder));
7658 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7659 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7660 tmp = I915_READ(VBLANK(cpu_transcoder));
7661 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7662 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7663 tmp = I915_READ(VSYNC(cpu_transcoder));
7664 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7665 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7666
7667 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7668 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7669 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7670 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7671 }
7672 }
7673
7674 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7675 struct intel_crtc_state *pipe_config)
7676 {
7677 struct drm_device *dev = crtc->base.dev;
7678 struct drm_i915_private *dev_priv = dev->dev_private;
7679 u32 tmp;
7680
7681 tmp = I915_READ(PIPESRC(crtc->pipe));
7682 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7683 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7684
7685 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7686 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7687 }
7688
7689 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7690 struct intel_crtc_state *pipe_config)
7691 {
7692 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7693 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7694 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7695 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7696
7697 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7698 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7699 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7700 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7701
7702 mode->flags = pipe_config->base.adjusted_mode.flags;
7703 mode->type = DRM_MODE_TYPE_DRIVER;
7704
7705 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7706 mode->flags |= pipe_config->base.adjusted_mode.flags;
7707
7708 mode->hsync = drm_mode_hsync(mode);
7709 mode->vrefresh = drm_mode_vrefresh(mode);
7710 drm_mode_set_name(mode);
7711 }
7712
7713 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7714 {
7715 struct drm_device *dev = intel_crtc->base.dev;
7716 struct drm_i915_private *dev_priv = dev->dev_private;
7717 uint32_t pipeconf;
7718
7719 pipeconf = 0;
7720
7721 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7722 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7723 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7724
7725 if (intel_crtc->config->double_wide)
7726 pipeconf |= PIPECONF_DOUBLE_WIDE;
7727
7728 /* only g4x and later have fancy bpc/dither controls */
7729 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7730 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7731 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7732 pipeconf |= PIPECONF_DITHER_EN |
7733 PIPECONF_DITHER_TYPE_SP;
7734
7735 switch (intel_crtc->config->pipe_bpp) {
7736 case 18:
7737 pipeconf |= PIPECONF_6BPC;
7738 break;
7739 case 24:
7740 pipeconf |= PIPECONF_8BPC;
7741 break;
7742 case 30:
7743 pipeconf |= PIPECONF_10BPC;
7744 break;
7745 default:
7746 /* Case prevented by intel_choose_pipe_bpp_dither. */
7747 BUG();
7748 }
7749 }
7750
7751 if (HAS_PIPE_CXSR(dev)) {
7752 if (intel_crtc->lowfreq_avail) {
7753 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7754 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7755 } else {
7756 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7757 }
7758 }
7759
7760 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7761 if (INTEL_INFO(dev)->gen < 4 ||
7762 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7763 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7764 else
7765 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7766 } else
7767 pipeconf |= PIPECONF_PROGRESSIVE;
7768
7769 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7770 intel_crtc->config->limited_color_range)
7771 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7772
7773 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7774 POSTING_READ(PIPECONF(intel_crtc->pipe));
7775 }
7776
7777 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7778 struct intel_crtc_state *crtc_state)
7779 {
7780 struct drm_device *dev = crtc->base.dev;
7781 struct drm_i915_private *dev_priv = dev->dev_private;
7782 const intel_limit_t *limit;
7783 int refclk = 48000;
7784
7785 memset(&crtc_state->dpll_hw_state, 0,
7786 sizeof(crtc_state->dpll_hw_state));
7787
7788 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7789 if (intel_panel_use_ssc(dev_priv)) {
7790 refclk = dev_priv->vbt.lvds_ssc_freq;
7791 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7792 }
7793
7794 limit = &intel_limits_i8xx_lvds;
7795 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7796 limit = &intel_limits_i8xx_dvo;
7797 } else {
7798 limit = &intel_limits_i8xx_dac;
7799 }
7800
7801 if (!crtc_state->clock_set &&
7802 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7803 refclk, NULL, &crtc_state->dpll)) {
7804 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7805 return -EINVAL;
7806 }
7807
7808 i8xx_compute_dpll(crtc, crtc_state, NULL);
7809
7810 return 0;
7811 }
7812
7813 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7814 struct intel_crtc_state *crtc_state)
7815 {
7816 struct drm_device *dev = crtc->base.dev;
7817 struct drm_i915_private *dev_priv = dev->dev_private;
7818 const intel_limit_t *limit;
7819 int refclk = 96000;
7820
7821 memset(&crtc_state->dpll_hw_state, 0,
7822 sizeof(crtc_state->dpll_hw_state));
7823
7824 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7825 if (intel_panel_use_ssc(dev_priv)) {
7826 refclk = dev_priv->vbt.lvds_ssc_freq;
7827 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7828 }
7829
7830 if (intel_is_dual_link_lvds(dev))
7831 limit = &intel_limits_g4x_dual_channel_lvds;
7832 else
7833 limit = &intel_limits_g4x_single_channel_lvds;
7834 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7835 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7836 limit = &intel_limits_g4x_hdmi;
7837 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7838 limit = &intel_limits_g4x_sdvo;
7839 } else {
7840 /* The option is for other outputs */
7841 limit = &intel_limits_i9xx_sdvo;
7842 }
7843
7844 if (!crtc_state->clock_set &&
7845 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7846 refclk, NULL, &crtc_state->dpll)) {
7847 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7848 return -EINVAL;
7849 }
7850
7851 i9xx_compute_dpll(crtc, crtc_state, NULL);
7852
7853 return 0;
7854 }
7855
7856 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7857 struct intel_crtc_state *crtc_state)
7858 {
7859 struct drm_device *dev = crtc->base.dev;
7860 struct drm_i915_private *dev_priv = dev->dev_private;
7861 const intel_limit_t *limit;
7862 int refclk = 96000;
7863
7864 memset(&crtc_state->dpll_hw_state, 0,
7865 sizeof(crtc_state->dpll_hw_state));
7866
7867 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7868 if (intel_panel_use_ssc(dev_priv)) {
7869 refclk = dev_priv->vbt.lvds_ssc_freq;
7870 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7871 }
7872
7873 limit = &intel_limits_pineview_lvds;
7874 } else {
7875 limit = &intel_limits_pineview_sdvo;
7876 }
7877
7878 if (!crtc_state->clock_set &&
7879 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7880 refclk, NULL, &crtc_state->dpll)) {
7881 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7882 return -EINVAL;
7883 }
7884
7885 i9xx_compute_dpll(crtc, crtc_state, NULL);
7886
7887 return 0;
7888 }
7889
7890 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7891 struct intel_crtc_state *crtc_state)
7892 {
7893 struct drm_device *dev = crtc->base.dev;
7894 struct drm_i915_private *dev_priv = dev->dev_private;
7895 const intel_limit_t *limit;
7896 int refclk = 96000;
7897
7898 memset(&crtc_state->dpll_hw_state, 0,
7899 sizeof(crtc_state->dpll_hw_state));
7900
7901 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7902 if (intel_panel_use_ssc(dev_priv)) {
7903 refclk = dev_priv->vbt.lvds_ssc_freq;
7904 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7905 }
7906
7907 limit = &intel_limits_i9xx_lvds;
7908 } else {
7909 limit = &intel_limits_i9xx_sdvo;
7910 }
7911
7912 if (!crtc_state->clock_set &&
7913 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7914 refclk, NULL, &crtc_state->dpll)) {
7915 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7916 return -EINVAL;
7917 }
7918
7919 i9xx_compute_dpll(crtc, crtc_state, NULL);
7920
7921 return 0;
7922 }
7923
7924 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7925 struct intel_crtc_state *crtc_state)
7926 {
7927 int refclk = 100000;
7928 const intel_limit_t *limit = &intel_limits_chv;
7929
7930 memset(&crtc_state->dpll_hw_state, 0,
7931 sizeof(crtc_state->dpll_hw_state));
7932
7933 if (crtc_state->has_dsi_encoder)
7934 return 0;
7935
7936 if (!crtc_state->clock_set &&
7937 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7938 refclk, NULL, &crtc_state->dpll)) {
7939 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7940 return -EINVAL;
7941 }
7942
7943 chv_compute_dpll(crtc, crtc_state);
7944
7945 return 0;
7946 }
7947
7948 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7949 struct intel_crtc_state *crtc_state)
7950 {
7951 int refclk = 100000;
7952 const intel_limit_t *limit = &intel_limits_vlv;
7953
7954 memset(&crtc_state->dpll_hw_state, 0,
7955 sizeof(crtc_state->dpll_hw_state));
7956
7957 if (crtc_state->has_dsi_encoder)
7958 return 0;
7959
7960 if (!crtc_state->clock_set &&
7961 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7962 refclk, NULL, &crtc_state->dpll)) {
7963 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7964 return -EINVAL;
7965 }
7966
7967 vlv_compute_dpll(crtc, crtc_state);
7968
7969 return 0;
7970 }
7971
7972 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7973 struct intel_crtc_state *pipe_config)
7974 {
7975 struct drm_device *dev = crtc->base.dev;
7976 struct drm_i915_private *dev_priv = dev->dev_private;
7977 uint32_t tmp;
7978
7979 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7980 return;
7981
7982 tmp = I915_READ(PFIT_CONTROL);
7983 if (!(tmp & PFIT_ENABLE))
7984 return;
7985
7986 /* Check whether the pfit is attached to our pipe. */
7987 if (INTEL_INFO(dev)->gen < 4) {
7988 if (crtc->pipe != PIPE_B)
7989 return;
7990 } else {
7991 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7992 return;
7993 }
7994
7995 pipe_config->gmch_pfit.control = tmp;
7996 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7997 if (INTEL_INFO(dev)->gen < 5)
7998 pipe_config->gmch_pfit.lvds_border_bits =
7999 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8000 }
8001
8002 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8003 struct intel_crtc_state *pipe_config)
8004 {
8005 struct drm_device *dev = crtc->base.dev;
8006 struct drm_i915_private *dev_priv = dev->dev_private;
8007 int pipe = pipe_config->cpu_transcoder;
8008 intel_clock_t clock;
8009 u32 mdiv;
8010 int refclk = 100000;
8011
8012 /* In case of DSI, DPLL will not be used */
8013 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8014 return;
8015
8016 mutex_lock(&dev_priv->sb_lock);
8017 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8018 mutex_unlock(&dev_priv->sb_lock);
8019
8020 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8021 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8022 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8023 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8024 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8025
8026 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8027 }
8028
8029 static void
8030 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8031 struct intel_initial_plane_config *plane_config)
8032 {
8033 struct drm_device *dev = crtc->base.dev;
8034 struct drm_i915_private *dev_priv = dev->dev_private;
8035 u32 val, base, offset;
8036 int pipe = crtc->pipe, plane = crtc->plane;
8037 int fourcc, pixel_format;
8038 unsigned int aligned_height;
8039 struct drm_framebuffer *fb;
8040 struct intel_framebuffer *intel_fb;
8041
8042 val = I915_READ(DSPCNTR(plane));
8043 if (!(val & DISPLAY_PLANE_ENABLE))
8044 return;
8045
8046 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8047 if (!intel_fb) {
8048 DRM_DEBUG_KMS("failed to alloc fb\n");
8049 return;
8050 }
8051
8052 fb = &intel_fb->base;
8053
8054 if (INTEL_INFO(dev)->gen >= 4) {
8055 if (val & DISPPLANE_TILED) {
8056 plane_config->tiling = I915_TILING_X;
8057 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8058 }
8059 }
8060
8061 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8062 fourcc = i9xx_format_to_fourcc(pixel_format);
8063 fb->pixel_format = fourcc;
8064 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8065
8066 if (INTEL_INFO(dev)->gen >= 4) {
8067 if (plane_config->tiling)
8068 offset = I915_READ(DSPTILEOFF(plane));
8069 else
8070 offset = I915_READ(DSPLINOFF(plane));
8071 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8072 } else {
8073 base = I915_READ(DSPADDR(plane));
8074 }
8075 plane_config->base = base;
8076
8077 val = I915_READ(PIPESRC(pipe));
8078 fb->width = ((val >> 16) & 0xfff) + 1;
8079 fb->height = ((val >> 0) & 0xfff) + 1;
8080
8081 val = I915_READ(DSPSTRIDE(pipe));
8082 fb->pitches[0] = val & 0xffffffc0;
8083
8084 aligned_height = intel_fb_align_height(dev, fb->height,
8085 fb->pixel_format,
8086 fb->modifier[0]);
8087
8088 plane_config->size = fb->pitches[0] * aligned_height;
8089
8090 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8091 pipe_name(pipe), plane, fb->width, fb->height,
8092 fb->bits_per_pixel, base, fb->pitches[0],
8093 plane_config->size);
8094
8095 plane_config->fb = intel_fb;
8096 }
8097
8098 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8099 struct intel_crtc_state *pipe_config)
8100 {
8101 struct drm_device *dev = crtc->base.dev;
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 int pipe = pipe_config->cpu_transcoder;
8104 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8105 intel_clock_t clock;
8106 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8107 int refclk = 100000;
8108
8109 /* In case of DSI, DPLL will not be used */
8110 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8111 return;
8112
8113 mutex_lock(&dev_priv->sb_lock);
8114 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8115 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8116 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8117 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8118 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8119 mutex_unlock(&dev_priv->sb_lock);
8120
8121 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8122 clock.m2 = (pll_dw0 & 0xff) << 22;
8123 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8124 clock.m2 |= pll_dw2 & 0x3fffff;
8125 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8126 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8127 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8128
8129 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8130 }
8131
8132 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8133 struct intel_crtc_state *pipe_config)
8134 {
8135 struct drm_device *dev = crtc->base.dev;
8136 struct drm_i915_private *dev_priv = dev->dev_private;
8137 enum intel_display_power_domain power_domain;
8138 uint32_t tmp;
8139 bool ret;
8140
8141 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8142 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8143 return false;
8144
8145 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8146 pipe_config->shared_dpll = NULL;
8147
8148 ret = false;
8149
8150 tmp = I915_READ(PIPECONF(crtc->pipe));
8151 if (!(tmp & PIPECONF_ENABLE))
8152 goto out;
8153
8154 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8155 switch (tmp & PIPECONF_BPC_MASK) {
8156 case PIPECONF_6BPC:
8157 pipe_config->pipe_bpp = 18;
8158 break;
8159 case PIPECONF_8BPC:
8160 pipe_config->pipe_bpp = 24;
8161 break;
8162 case PIPECONF_10BPC:
8163 pipe_config->pipe_bpp = 30;
8164 break;
8165 default:
8166 break;
8167 }
8168 }
8169
8170 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8171 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8172 pipe_config->limited_color_range = true;
8173
8174 if (INTEL_INFO(dev)->gen < 4)
8175 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8176
8177 intel_get_pipe_timings(crtc, pipe_config);
8178 intel_get_pipe_src_size(crtc, pipe_config);
8179
8180 i9xx_get_pfit_config(crtc, pipe_config);
8181
8182 if (INTEL_INFO(dev)->gen >= 4) {
8183 /* No way to read it out on pipes B and C */
8184 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8185 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8186 else
8187 tmp = I915_READ(DPLL_MD(crtc->pipe));
8188 pipe_config->pixel_multiplier =
8189 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8190 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8191 pipe_config->dpll_hw_state.dpll_md = tmp;
8192 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8193 tmp = I915_READ(DPLL(crtc->pipe));
8194 pipe_config->pixel_multiplier =
8195 ((tmp & SDVO_MULTIPLIER_MASK)
8196 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8197 } else {
8198 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8199 * port and will be fixed up in the encoder->get_config
8200 * function. */
8201 pipe_config->pixel_multiplier = 1;
8202 }
8203 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8204 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8205 /*
8206 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8207 * on 830. Filter it out here so that we don't
8208 * report errors due to that.
8209 */
8210 if (IS_I830(dev))
8211 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8212
8213 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8214 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8215 } else {
8216 /* Mask out read-only status bits. */
8217 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8218 DPLL_PORTC_READY_MASK |
8219 DPLL_PORTB_READY_MASK);
8220 }
8221
8222 if (IS_CHERRYVIEW(dev))
8223 chv_crtc_clock_get(crtc, pipe_config);
8224 else if (IS_VALLEYVIEW(dev))
8225 vlv_crtc_clock_get(crtc, pipe_config);
8226 else
8227 i9xx_crtc_clock_get(crtc, pipe_config);
8228
8229 /*
8230 * Normally the dotclock is filled in by the encoder .get_config()
8231 * but in case the pipe is enabled w/o any ports we need a sane
8232 * default.
8233 */
8234 pipe_config->base.adjusted_mode.crtc_clock =
8235 pipe_config->port_clock / pipe_config->pixel_multiplier;
8236
8237 ret = true;
8238
8239 out:
8240 intel_display_power_put(dev_priv, power_domain);
8241
8242 return ret;
8243 }
8244
8245 static void ironlake_init_pch_refclk(struct drm_device *dev)
8246 {
8247 struct drm_i915_private *dev_priv = dev->dev_private;
8248 struct intel_encoder *encoder;
8249 u32 val, final;
8250 bool has_lvds = false;
8251 bool has_cpu_edp = false;
8252 bool has_panel = false;
8253 bool has_ck505 = false;
8254 bool can_ssc = false;
8255
8256 /* We need to take the global config into account */
8257 for_each_intel_encoder(dev, encoder) {
8258 switch (encoder->type) {
8259 case INTEL_OUTPUT_LVDS:
8260 has_panel = true;
8261 has_lvds = true;
8262 break;
8263 case INTEL_OUTPUT_EDP:
8264 has_panel = true;
8265 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8266 has_cpu_edp = true;
8267 break;
8268 default:
8269 break;
8270 }
8271 }
8272
8273 if (HAS_PCH_IBX(dev)) {
8274 has_ck505 = dev_priv->vbt.display_clock_mode;
8275 can_ssc = has_ck505;
8276 } else {
8277 has_ck505 = false;
8278 can_ssc = true;
8279 }
8280
8281 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8282 has_panel, has_lvds, has_ck505);
8283
8284 /* Ironlake: try to setup display ref clock before DPLL
8285 * enabling. This is only under driver's control after
8286 * PCH B stepping, previous chipset stepping should be
8287 * ignoring this setting.
8288 */
8289 val = I915_READ(PCH_DREF_CONTROL);
8290
8291 /* As we must carefully and slowly disable/enable each source in turn,
8292 * compute the final state we want first and check if we need to
8293 * make any changes at all.
8294 */
8295 final = val;
8296 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8297 if (has_ck505)
8298 final |= DREF_NONSPREAD_CK505_ENABLE;
8299 else
8300 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8301
8302 final &= ~DREF_SSC_SOURCE_MASK;
8303 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8304 final &= ~DREF_SSC1_ENABLE;
8305
8306 if (has_panel) {
8307 final |= DREF_SSC_SOURCE_ENABLE;
8308
8309 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8310 final |= DREF_SSC1_ENABLE;
8311
8312 if (has_cpu_edp) {
8313 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8314 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8315 else
8316 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8317 } else
8318 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8319 } else {
8320 final |= DREF_SSC_SOURCE_DISABLE;
8321 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8322 }
8323
8324 if (final == val)
8325 return;
8326
8327 /* Always enable nonspread source */
8328 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8329
8330 if (has_ck505)
8331 val |= DREF_NONSPREAD_CK505_ENABLE;
8332 else
8333 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8334
8335 if (has_panel) {
8336 val &= ~DREF_SSC_SOURCE_MASK;
8337 val |= DREF_SSC_SOURCE_ENABLE;
8338
8339 /* SSC must be turned on before enabling the CPU output */
8340 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8341 DRM_DEBUG_KMS("Using SSC on panel\n");
8342 val |= DREF_SSC1_ENABLE;
8343 } else
8344 val &= ~DREF_SSC1_ENABLE;
8345
8346 /* Get SSC going before enabling the outputs */
8347 I915_WRITE(PCH_DREF_CONTROL, val);
8348 POSTING_READ(PCH_DREF_CONTROL);
8349 udelay(200);
8350
8351 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8352
8353 /* Enable CPU source on CPU attached eDP */
8354 if (has_cpu_edp) {
8355 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8356 DRM_DEBUG_KMS("Using SSC on eDP\n");
8357 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8358 } else
8359 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8360 } else
8361 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8362
8363 I915_WRITE(PCH_DREF_CONTROL, val);
8364 POSTING_READ(PCH_DREF_CONTROL);
8365 udelay(200);
8366 } else {
8367 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8368
8369 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8370
8371 /* Turn off CPU output */
8372 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8373
8374 I915_WRITE(PCH_DREF_CONTROL, val);
8375 POSTING_READ(PCH_DREF_CONTROL);
8376 udelay(200);
8377
8378 /* Turn off the SSC source */
8379 val &= ~DREF_SSC_SOURCE_MASK;
8380 val |= DREF_SSC_SOURCE_DISABLE;
8381
8382 /* Turn off SSC1 */
8383 val &= ~DREF_SSC1_ENABLE;
8384
8385 I915_WRITE(PCH_DREF_CONTROL, val);
8386 POSTING_READ(PCH_DREF_CONTROL);
8387 udelay(200);
8388 }
8389
8390 BUG_ON(val != final);
8391 }
8392
8393 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8394 {
8395 uint32_t tmp;
8396
8397 tmp = I915_READ(SOUTH_CHICKEN2);
8398 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8399 I915_WRITE(SOUTH_CHICKEN2, tmp);
8400
8401 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8402 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8403 DRM_ERROR("FDI mPHY reset assert timeout\n");
8404
8405 tmp = I915_READ(SOUTH_CHICKEN2);
8406 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8407 I915_WRITE(SOUTH_CHICKEN2, tmp);
8408
8409 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8410 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8411 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8412 }
8413
8414 /* WaMPhyProgramming:hsw */
8415 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8416 {
8417 uint32_t tmp;
8418
8419 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8420 tmp &= ~(0xFF << 24);
8421 tmp |= (0x12 << 24);
8422 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8423
8424 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8425 tmp |= (1 << 11);
8426 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8427
8428 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8429 tmp |= (1 << 11);
8430 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8431
8432 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8433 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8434 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8435
8436 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8437 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8438 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8439
8440 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8441 tmp &= ~(7 << 13);
8442 tmp |= (5 << 13);
8443 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8444
8445 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8446 tmp &= ~(7 << 13);
8447 tmp |= (5 << 13);
8448 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8449
8450 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8451 tmp &= ~0xFF;
8452 tmp |= 0x1C;
8453 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8454
8455 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8456 tmp &= ~0xFF;
8457 tmp |= 0x1C;
8458 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8459
8460 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8461 tmp &= ~(0xFF << 16);
8462 tmp |= (0x1C << 16);
8463 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8464
8465 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8466 tmp &= ~(0xFF << 16);
8467 tmp |= (0x1C << 16);
8468 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8469
8470 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8471 tmp |= (1 << 27);
8472 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8473
8474 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8475 tmp |= (1 << 27);
8476 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8477
8478 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8479 tmp &= ~(0xF << 28);
8480 tmp |= (4 << 28);
8481 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8482
8483 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8484 tmp &= ~(0xF << 28);
8485 tmp |= (4 << 28);
8486 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8487 }
8488
8489 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8490 * Programming" based on the parameters passed:
8491 * - Sequence to enable CLKOUT_DP
8492 * - Sequence to enable CLKOUT_DP without spread
8493 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8494 */
8495 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8496 bool with_fdi)
8497 {
8498 struct drm_i915_private *dev_priv = dev->dev_private;
8499 uint32_t reg, tmp;
8500
8501 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8502 with_spread = true;
8503 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8504 with_fdi = false;
8505
8506 mutex_lock(&dev_priv->sb_lock);
8507
8508 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8509 tmp &= ~SBI_SSCCTL_DISABLE;
8510 tmp |= SBI_SSCCTL_PATHALT;
8511 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8512
8513 udelay(24);
8514
8515 if (with_spread) {
8516 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8517 tmp &= ~SBI_SSCCTL_PATHALT;
8518 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8519
8520 if (with_fdi) {
8521 lpt_reset_fdi_mphy(dev_priv);
8522 lpt_program_fdi_mphy(dev_priv);
8523 }
8524 }
8525
8526 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8527 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8528 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8529 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8530
8531 mutex_unlock(&dev_priv->sb_lock);
8532 }
8533
8534 /* Sequence to disable CLKOUT_DP */
8535 static void lpt_disable_clkout_dp(struct drm_device *dev)
8536 {
8537 struct drm_i915_private *dev_priv = dev->dev_private;
8538 uint32_t reg, tmp;
8539
8540 mutex_lock(&dev_priv->sb_lock);
8541
8542 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8543 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8544 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8545 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8546
8547 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8548 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8549 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8550 tmp |= SBI_SSCCTL_PATHALT;
8551 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8552 udelay(32);
8553 }
8554 tmp |= SBI_SSCCTL_DISABLE;
8555 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8556 }
8557
8558 mutex_unlock(&dev_priv->sb_lock);
8559 }
8560
8561 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8562
8563 static const uint16_t sscdivintphase[] = {
8564 [BEND_IDX( 50)] = 0x3B23,
8565 [BEND_IDX( 45)] = 0x3B23,
8566 [BEND_IDX( 40)] = 0x3C23,
8567 [BEND_IDX( 35)] = 0x3C23,
8568 [BEND_IDX( 30)] = 0x3D23,
8569 [BEND_IDX( 25)] = 0x3D23,
8570 [BEND_IDX( 20)] = 0x3E23,
8571 [BEND_IDX( 15)] = 0x3E23,
8572 [BEND_IDX( 10)] = 0x3F23,
8573 [BEND_IDX( 5)] = 0x3F23,
8574 [BEND_IDX( 0)] = 0x0025,
8575 [BEND_IDX( -5)] = 0x0025,
8576 [BEND_IDX(-10)] = 0x0125,
8577 [BEND_IDX(-15)] = 0x0125,
8578 [BEND_IDX(-20)] = 0x0225,
8579 [BEND_IDX(-25)] = 0x0225,
8580 [BEND_IDX(-30)] = 0x0325,
8581 [BEND_IDX(-35)] = 0x0325,
8582 [BEND_IDX(-40)] = 0x0425,
8583 [BEND_IDX(-45)] = 0x0425,
8584 [BEND_IDX(-50)] = 0x0525,
8585 };
8586
8587 /*
8588 * Bend CLKOUT_DP
8589 * steps -50 to 50 inclusive, in steps of 5
8590 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8591 * change in clock period = -(steps / 10) * 5.787 ps
8592 */
8593 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8594 {
8595 uint32_t tmp;
8596 int idx = BEND_IDX(steps);
8597
8598 if (WARN_ON(steps % 5 != 0))
8599 return;
8600
8601 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8602 return;
8603
8604 mutex_lock(&dev_priv->sb_lock);
8605
8606 if (steps % 10 != 0)
8607 tmp = 0xAAAAAAAB;
8608 else
8609 tmp = 0x00000000;
8610 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8611
8612 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8613 tmp &= 0xffff0000;
8614 tmp |= sscdivintphase[idx];
8615 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8616
8617 mutex_unlock(&dev_priv->sb_lock);
8618 }
8619
8620 #undef BEND_IDX
8621
8622 static void lpt_init_pch_refclk(struct drm_device *dev)
8623 {
8624 struct intel_encoder *encoder;
8625 bool has_vga = false;
8626
8627 for_each_intel_encoder(dev, encoder) {
8628 switch (encoder->type) {
8629 case INTEL_OUTPUT_ANALOG:
8630 has_vga = true;
8631 break;
8632 default:
8633 break;
8634 }
8635 }
8636
8637 if (has_vga) {
8638 lpt_bend_clkout_dp(to_i915(dev), 0);
8639 lpt_enable_clkout_dp(dev, true, true);
8640 } else {
8641 lpt_disable_clkout_dp(dev);
8642 }
8643 }
8644
8645 /*
8646 * Initialize reference clocks when the driver loads
8647 */
8648 void intel_init_pch_refclk(struct drm_device *dev)
8649 {
8650 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8651 ironlake_init_pch_refclk(dev);
8652 else if (HAS_PCH_LPT(dev))
8653 lpt_init_pch_refclk(dev);
8654 }
8655
8656 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8657 {
8658 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8660 int pipe = intel_crtc->pipe;
8661 uint32_t val;
8662
8663 val = 0;
8664
8665 switch (intel_crtc->config->pipe_bpp) {
8666 case 18:
8667 val |= PIPECONF_6BPC;
8668 break;
8669 case 24:
8670 val |= PIPECONF_8BPC;
8671 break;
8672 case 30:
8673 val |= PIPECONF_10BPC;
8674 break;
8675 case 36:
8676 val |= PIPECONF_12BPC;
8677 break;
8678 default:
8679 /* Case prevented by intel_choose_pipe_bpp_dither. */
8680 BUG();
8681 }
8682
8683 if (intel_crtc->config->dither)
8684 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8685
8686 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8687 val |= PIPECONF_INTERLACED_ILK;
8688 else
8689 val |= PIPECONF_PROGRESSIVE;
8690
8691 if (intel_crtc->config->limited_color_range)
8692 val |= PIPECONF_COLOR_RANGE_SELECT;
8693
8694 I915_WRITE(PIPECONF(pipe), val);
8695 POSTING_READ(PIPECONF(pipe));
8696 }
8697
8698 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8699 {
8700 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8702 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8703 u32 val = 0;
8704
8705 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8706 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8707
8708 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8709 val |= PIPECONF_INTERLACED_ILK;
8710 else
8711 val |= PIPECONF_PROGRESSIVE;
8712
8713 I915_WRITE(PIPECONF(cpu_transcoder), val);
8714 POSTING_READ(PIPECONF(cpu_transcoder));
8715 }
8716
8717 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8718 {
8719 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8721
8722 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8723 u32 val = 0;
8724
8725 switch (intel_crtc->config->pipe_bpp) {
8726 case 18:
8727 val |= PIPEMISC_DITHER_6_BPC;
8728 break;
8729 case 24:
8730 val |= PIPEMISC_DITHER_8_BPC;
8731 break;
8732 case 30:
8733 val |= PIPEMISC_DITHER_10_BPC;
8734 break;
8735 case 36:
8736 val |= PIPEMISC_DITHER_12_BPC;
8737 break;
8738 default:
8739 /* Case prevented by pipe_config_set_bpp. */
8740 BUG();
8741 }
8742
8743 if (intel_crtc->config->dither)
8744 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8745
8746 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8747 }
8748 }
8749
8750 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8751 {
8752 /*
8753 * Account for spread spectrum to avoid
8754 * oversubscribing the link. Max center spread
8755 * is 2.5%; use 5% for safety's sake.
8756 */
8757 u32 bps = target_clock * bpp * 21 / 20;
8758 return DIV_ROUND_UP(bps, link_bw * 8);
8759 }
8760
8761 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8762 {
8763 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8764 }
8765
8766 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8767 struct intel_crtc_state *crtc_state,
8768 intel_clock_t *reduced_clock)
8769 {
8770 struct drm_crtc *crtc = &intel_crtc->base;
8771 struct drm_device *dev = crtc->dev;
8772 struct drm_i915_private *dev_priv = dev->dev_private;
8773 struct drm_atomic_state *state = crtc_state->base.state;
8774 struct drm_connector *connector;
8775 struct drm_connector_state *connector_state;
8776 struct intel_encoder *encoder;
8777 u32 dpll, fp, fp2;
8778 int factor, i;
8779 bool is_lvds = false, is_sdvo = false;
8780
8781 for_each_connector_in_state(state, connector, connector_state, i) {
8782 if (connector_state->crtc != crtc_state->base.crtc)
8783 continue;
8784
8785 encoder = to_intel_encoder(connector_state->best_encoder);
8786
8787 switch (encoder->type) {
8788 case INTEL_OUTPUT_LVDS:
8789 is_lvds = true;
8790 break;
8791 case INTEL_OUTPUT_SDVO:
8792 case INTEL_OUTPUT_HDMI:
8793 is_sdvo = true;
8794 break;
8795 default:
8796 break;
8797 }
8798 }
8799
8800 /* Enable autotuning of the PLL clock (if permissible) */
8801 factor = 21;
8802 if (is_lvds) {
8803 if ((intel_panel_use_ssc(dev_priv) &&
8804 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8805 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8806 factor = 25;
8807 } else if (crtc_state->sdvo_tv_clock)
8808 factor = 20;
8809
8810 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8811
8812 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8813 fp |= FP_CB_TUNE;
8814
8815 if (reduced_clock) {
8816 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8817
8818 if (reduced_clock->m < factor * reduced_clock->n)
8819 fp2 |= FP_CB_TUNE;
8820 } else {
8821 fp2 = fp;
8822 }
8823
8824 dpll = 0;
8825
8826 if (is_lvds)
8827 dpll |= DPLLB_MODE_LVDS;
8828 else
8829 dpll |= DPLLB_MODE_DAC_SERIAL;
8830
8831 dpll |= (crtc_state->pixel_multiplier - 1)
8832 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8833
8834 if (is_sdvo)
8835 dpll |= DPLL_SDVO_HIGH_SPEED;
8836 if (crtc_state->has_dp_encoder)
8837 dpll |= DPLL_SDVO_HIGH_SPEED;
8838
8839 /* compute bitmask from p1 value */
8840 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8841 /* also FPA1 */
8842 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8843
8844 switch (crtc_state->dpll.p2) {
8845 case 5:
8846 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8847 break;
8848 case 7:
8849 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8850 break;
8851 case 10:
8852 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8853 break;
8854 case 14:
8855 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8856 break;
8857 }
8858
8859 if (is_lvds && intel_panel_use_ssc(dev_priv))
8860 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8861 else
8862 dpll |= PLL_REF_INPUT_DREFCLK;
8863
8864 dpll |= DPLL_VCO_ENABLE;
8865
8866 crtc_state->dpll_hw_state.dpll = dpll;
8867 crtc_state->dpll_hw_state.fp0 = fp;
8868 crtc_state->dpll_hw_state.fp1 = fp2;
8869 }
8870
8871 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8872 struct intel_crtc_state *crtc_state)
8873 {
8874 struct drm_device *dev = crtc->base.dev;
8875 struct drm_i915_private *dev_priv = dev->dev_private;
8876 intel_clock_t reduced_clock;
8877 bool has_reduced_clock = false;
8878 struct intel_shared_dpll *pll;
8879 const intel_limit_t *limit;
8880 int refclk = 120000;
8881
8882 memset(&crtc_state->dpll_hw_state, 0,
8883 sizeof(crtc_state->dpll_hw_state));
8884
8885 crtc->lowfreq_avail = false;
8886
8887 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8888 if (!crtc_state->has_pch_encoder)
8889 return 0;
8890
8891 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8892 if (intel_panel_use_ssc(dev_priv)) {
8893 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8894 dev_priv->vbt.lvds_ssc_freq);
8895 refclk = dev_priv->vbt.lvds_ssc_freq;
8896 }
8897
8898 if (intel_is_dual_link_lvds(dev)) {
8899 if (refclk == 100000)
8900 limit = &intel_limits_ironlake_dual_lvds_100m;
8901 else
8902 limit = &intel_limits_ironlake_dual_lvds;
8903 } else {
8904 if (refclk == 100000)
8905 limit = &intel_limits_ironlake_single_lvds_100m;
8906 else
8907 limit = &intel_limits_ironlake_single_lvds;
8908 }
8909 } else {
8910 limit = &intel_limits_ironlake_dac;
8911 }
8912
8913 if (!crtc_state->clock_set &&
8914 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8915 refclk, NULL, &crtc_state->dpll)) {
8916 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8917 return -EINVAL;
8918 }
8919
8920 ironlake_compute_dpll(crtc, crtc_state,
8921 has_reduced_clock ? &reduced_clock : NULL);
8922
8923 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8924 if (pll == NULL) {
8925 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8926 pipe_name(crtc->pipe));
8927 return -EINVAL;
8928 }
8929
8930 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8931 has_reduced_clock)
8932 crtc->lowfreq_avail = true;
8933
8934 return 0;
8935 }
8936
8937 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8938 struct intel_link_m_n *m_n)
8939 {
8940 struct drm_device *dev = crtc->base.dev;
8941 struct drm_i915_private *dev_priv = dev->dev_private;
8942 enum pipe pipe = crtc->pipe;
8943
8944 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8945 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8946 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8947 & ~TU_SIZE_MASK;
8948 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8949 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8950 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8951 }
8952
8953 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8954 enum transcoder transcoder,
8955 struct intel_link_m_n *m_n,
8956 struct intel_link_m_n *m2_n2)
8957 {
8958 struct drm_device *dev = crtc->base.dev;
8959 struct drm_i915_private *dev_priv = dev->dev_private;
8960 enum pipe pipe = crtc->pipe;
8961
8962 if (INTEL_INFO(dev)->gen >= 5) {
8963 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8964 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8965 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8966 & ~TU_SIZE_MASK;
8967 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8968 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8969 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8970 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8971 * gen < 8) and if DRRS is supported (to make sure the
8972 * registers are not unnecessarily read).
8973 */
8974 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8975 crtc->config->has_drrs) {
8976 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8977 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8978 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8979 & ~TU_SIZE_MASK;
8980 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8981 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8982 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8983 }
8984 } else {
8985 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8986 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8987 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8988 & ~TU_SIZE_MASK;
8989 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8990 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8991 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8992 }
8993 }
8994
8995 void intel_dp_get_m_n(struct intel_crtc *crtc,
8996 struct intel_crtc_state *pipe_config)
8997 {
8998 if (pipe_config->has_pch_encoder)
8999 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9000 else
9001 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9002 &pipe_config->dp_m_n,
9003 &pipe_config->dp_m2_n2);
9004 }
9005
9006 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9007 struct intel_crtc_state *pipe_config)
9008 {
9009 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9010 &pipe_config->fdi_m_n, NULL);
9011 }
9012
9013 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9014 struct intel_crtc_state *pipe_config)
9015 {
9016 struct drm_device *dev = crtc->base.dev;
9017 struct drm_i915_private *dev_priv = dev->dev_private;
9018 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9019 uint32_t ps_ctrl = 0;
9020 int id = -1;
9021 int i;
9022
9023 /* find scaler attached to this pipe */
9024 for (i = 0; i < crtc->num_scalers; i++) {
9025 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9026 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9027 id = i;
9028 pipe_config->pch_pfit.enabled = true;
9029 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9030 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9031 break;
9032 }
9033 }
9034
9035 scaler_state->scaler_id = id;
9036 if (id >= 0) {
9037 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9038 } else {
9039 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9040 }
9041 }
9042
9043 static void
9044 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9045 struct intel_initial_plane_config *plane_config)
9046 {
9047 struct drm_device *dev = crtc->base.dev;
9048 struct drm_i915_private *dev_priv = dev->dev_private;
9049 u32 val, base, offset, stride_mult, tiling;
9050 int pipe = crtc->pipe;
9051 int fourcc, pixel_format;
9052 unsigned int aligned_height;
9053 struct drm_framebuffer *fb;
9054 struct intel_framebuffer *intel_fb;
9055
9056 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9057 if (!intel_fb) {
9058 DRM_DEBUG_KMS("failed to alloc fb\n");
9059 return;
9060 }
9061
9062 fb = &intel_fb->base;
9063
9064 val = I915_READ(PLANE_CTL(pipe, 0));
9065 if (!(val & PLANE_CTL_ENABLE))
9066 goto error;
9067
9068 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9069 fourcc = skl_format_to_fourcc(pixel_format,
9070 val & PLANE_CTL_ORDER_RGBX,
9071 val & PLANE_CTL_ALPHA_MASK);
9072 fb->pixel_format = fourcc;
9073 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9074
9075 tiling = val & PLANE_CTL_TILED_MASK;
9076 switch (tiling) {
9077 case PLANE_CTL_TILED_LINEAR:
9078 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9079 break;
9080 case PLANE_CTL_TILED_X:
9081 plane_config->tiling = I915_TILING_X;
9082 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9083 break;
9084 case PLANE_CTL_TILED_Y:
9085 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9086 break;
9087 case PLANE_CTL_TILED_YF:
9088 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9089 break;
9090 default:
9091 MISSING_CASE(tiling);
9092 goto error;
9093 }
9094
9095 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9096 plane_config->base = base;
9097
9098 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9099
9100 val = I915_READ(PLANE_SIZE(pipe, 0));
9101 fb->height = ((val >> 16) & 0xfff) + 1;
9102 fb->width = ((val >> 0) & 0x1fff) + 1;
9103
9104 val = I915_READ(PLANE_STRIDE(pipe, 0));
9105 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9106 fb->pixel_format);
9107 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9108
9109 aligned_height = intel_fb_align_height(dev, fb->height,
9110 fb->pixel_format,
9111 fb->modifier[0]);
9112
9113 plane_config->size = fb->pitches[0] * aligned_height;
9114
9115 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9116 pipe_name(pipe), fb->width, fb->height,
9117 fb->bits_per_pixel, base, fb->pitches[0],
9118 plane_config->size);
9119
9120 plane_config->fb = intel_fb;
9121 return;
9122
9123 error:
9124 kfree(fb);
9125 }
9126
9127 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9128 struct intel_crtc_state *pipe_config)
9129 {
9130 struct drm_device *dev = crtc->base.dev;
9131 struct drm_i915_private *dev_priv = dev->dev_private;
9132 uint32_t tmp;
9133
9134 tmp = I915_READ(PF_CTL(crtc->pipe));
9135
9136 if (tmp & PF_ENABLE) {
9137 pipe_config->pch_pfit.enabled = true;
9138 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9139 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9140
9141 /* We currently do not free assignements of panel fitters on
9142 * ivb/hsw (since we don't use the higher upscaling modes which
9143 * differentiates them) so just WARN about this case for now. */
9144 if (IS_GEN7(dev)) {
9145 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9146 PF_PIPE_SEL_IVB(crtc->pipe));
9147 }
9148 }
9149 }
9150
9151 static void
9152 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9153 struct intel_initial_plane_config *plane_config)
9154 {
9155 struct drm_device *dev = crtc->base.dev;
9156 struct drm_i915_private *dev_priv = dev->dev_private;
9157 u32 val, base, offset;
9158 int pipe = crtc->pipe;
9159 int fourcc, pixel_format;
9160 unsigned int aligned_height;
9161 struct drm_framebuffer *fb;
9162 struct intel_framebuffer *intel_fb;
9163
9164 val = I915_READ(DSPCNTR(pipe));
9165 if (!(val & DISPLAY_PLANE_ENABLE))
9166 return;
9167
9168 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9169 if (!intel_fb) {
9170 DRM_DEBUG_KMS("failed to alloc fb\n");
9171 return;
9172 }
9173
9174 fb = &intel_fb->base;
9175
9176 if (INTEL_INFO(dev)->gen >= 4) {
9177 if (val & DISPPLANE_TILED) {
9178 plane_config->tiling = I915_TILING_X;
9179 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9180 }
9181 }
9182
9183 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9184 fourcc = i9xx_format_to_fourcc(pixel_format);
9185 fb->pixel_format = fourcc;
9186 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9187
9188 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9189 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9190 offset = I915_READ(DSPOFFSET(pipe));
9191 } else {
9192 if (plane_config->tiling)
9193 offset = I915_READ(DSPTILEOFF(pipe));
9194 else
9195 offset = I915_READ(DSPLINOFF(pipe));
9196 }
9197 plane_config->base = base;
9198
9199 val = I915_READ(PIPESRC(pipe));
9200 fb->width = ((val >> 16) & 0xfff) + 1;
9201 fb->height = ((val >> 0) & 0xfff) + 1;
9202
9203 val = I915_READ(DSPSTRIDE(pipe));
9204 fb->pitches[0] = val & 0xffffffc0;
9205
9206 aligned_height = intel_fb_align_height(dev, fb->height,
9207 fb->pixel_format,
9208 fb->modifier[0]);
9209
9210 plane_config->size = fb->pitches[0] * aligned_height;
9211
9212 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9213 pipe_name(pipe), fb->width, fb->height,
9214 fb->bits_per_pixel, base, fb->pitches[0],
9215 plane_config->size);
9216
9217 plane_config->fb = intel_fb;
9218 }
9219
9220 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9221 struct intel_crtc_state *pipe_config)
9222 {
9223 struct drm_device *dev = crtc->base.dev;
9224 struct drm_i915_private *dev_priv = dev->dev_private;
9225 enum intel_display_power_domain power_domain;
9226 uint32_t tmp;
9227 bool ret;
9228
9229 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9230 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9231 return false;
9232
9233 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9234 pipe_config->shared_dpll = NULL;
9235
9236 ret = false;
9237 tmp = I915_READ(PIPECONF(crtc->pipe));
9238 if (!(tmp & PIPECONF_ENABLE))
9239 goto out;
9240
9241 switch (tmp & PIPECONF_BPC_MASK) {
9242 case PIPECONF_6BPC:
9243 pipe_config->pipe_bpp = 18;
9244 break;
9245 case PIPECONF_8BPC:
9246 pipe_config->pipe_bpp = 24;
9247 break;
9248 case PIPECONF_10BPC:
9249 pipe_config->pipe_bpp = 30;
9250 break;
9251 case PIPECONF_12BPC:
9252 pipe_config->pipe_bpp = 36;
9253 break;
9254 default:
9255 break;
9256 }
9257
9258 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9259 pipe_config->limited_color_range = true;
9260
9261 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9262 struct intel_shared_dpll *pll;
9263 enum intel_dpll_id pll_id;
9264
9265 pipe_config->has_pch_encoder = true;
9266
9267 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9268 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9269 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9270
9271 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9272
9273 if (HAS_PCH_IBX(dev_priv)) {
9274 pll_id = (enum intel_dpll_id) crtc->pipe;
9275 } else {
9276 tmp = I915_READ(PCH_DPLL_SEL);
9277 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9278 pll_id = DPLL_ID_PCH_PLL_B;
9279 else
9280 pll_id= DPLL_ID_PCH_PLL_A;
9281 }
9282
9283 pipe_config->shared_dpll =
9284 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9285 pll = pipe_config->shared_dpll;
9286
9287 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9288 &pipe_config->dpll_hw_state));
9289
9290 tmp = pipe_config->dpll_hw_state.dpll;
9291 pipe_config->pixel_multiplier =
9292 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9293 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9294
9295 ironlake_pch_clock_get(crtc, pipe_config);
9296 } else {
9297 pipe_config->pixel_multiplier = 1;
9298 }
9299
9300 intel_get_pipe_timings(crtc, pipe_config);
9301 intel_get_pipe_src_size(crtc, pipe_config);
9302
9303 ironlake_get_pfit_config(crtc, pipe_config);
9304
9305 ret = true;
9306
9307 out:
9308 intel_display_power_put(dev_priv, power_domain);
9309
9310 return ret;
9311 }
9312
9313 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9314 {
9315 struct drm_device *dev = dev_priv->dev;
9316 struct intel_crtc *crtc;
9317
9318 for_each_intel_crtc(dev, crtc)
9319 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9320 pipe_name(crtc->pipe));
9321
9322 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9323 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9324 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9325 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9326 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9327 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9328 "CPU PWM1 enabled\n");
9329 if (IS_HASWELL(dev))
9330 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9331 "CPU PWM2 enabled\n");
9332 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9333 "PCH PWM1 enabled\n");
9334 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9335 "Utility pin enabled\n");
9336 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9337
9338 /*
9339 * In theory we can still leave IRQs enabled, as long as only the HPD
9340 * interrupts remain enabled. We used to check for that, but since it's
9341 * gen-specific and since we only disable LCPLL after we fully disable
9342 * the interrupts, the check below should be enough.
9343 */
9344 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9345 }
9346
9347 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9348 {
9349 struct drm_device *dev = dev_priv->dev;
9350
9351 if (IS_HASWELL(dev))
9352 return I915_READ(D_COMP_HSW);
9353 else
9354 return I915_READ(D_COMP_BDW);
9355 }
9356
9357 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9358 {
9359 struct drm_device *dev = dev_priv->dev;
9360
9361 if (IS_HASWELL(dev)) {
9362 mutex_lock(&dev_priv->rps.hw_lock);
9363 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9364 val))
9365 DRM_ERROR("Failed to write to D_COMP\n");
9366 mutex_unlock(&dev_priv->rps.hw_lock);
9367 } else {
9368 I915_WRITE(D_COMP_BDW, val);
9369 POSTING_READ(D_COMP_BDW);
9370 }
9371 }
9372
9373 /*
9374 * This function implements pieces of two sequences from BSpec:
9375 * - Sequence for display software to disable LCPLL
9376 * - Sequence for display software to allow package C8+
9377 * The steps implemented here are just the steps that actually touch the LCPLL
9378 * register. Callers should take care of disabling all the display engine
9379 * functions, doing the mode unset, fixing interrupts, etc.
9380 */
9381 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9382 bool switch_to_fclk, bool allow_power_down)
9383 {
9384 uint32_t val;
9385
9386 assert_can_disable_lcpll(dev_priv);
9387
9388 val = I915_READ(LCPLL_CTL);
9389
9390 if (switch_to_fclk) {
9391 val |= LCPLL_CD_SOURCE_FCLK;
9392 I915_WRITE(LCPLL_CTL, val);
9393
9394 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9395 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9396 DRM_ERROR("Switching to FCLK failed\n");
9397
9398 val = I915_READ(LCPLL_CTL);
9399 }
9400
9401 val |= LCPLL_PLL_DISABLE;
9402 I915_WRITE(LCPLL_CTL, val);
9403 POSTING_READ(LCPLL_CTL);
9404
9405 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9406 DRM_ERROR("LCPLL still locked\n");
9407
9408 val = hsw_read_dcomp(dev_priv);
9409 val |= D_COMP_COMP_DISABLE;
9410 hsw_write_dcomp(dev_priv, val);
9411 ndelay(100);
9412
9413 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9414 1))
9415 DRM_ERROR("D_COMP RCOMP still in progress\n");
9416
9417 if (allow_power_down) {
9418 val = I915_READ(LCPLL_CTL);
9419 val |= LCPLL_POWER_DOWN_ALLOW;
9420 I915_WRITE(LCPLL_CTL, val);
9421 POSTING_READ(LCPLL_CTL);
9422 }
9423 }
9424
9425 /*
9426 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9427 * source.
9428 */
9429 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9430 {
9431 uint32_t val;
9432
9433 val = I915_READ(LCPLL_CTL);
9434
9435 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9436 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9437 return;
9438
9439 /*
9440 * Make sure we're not on PC8 state before disabling PC8, otherwise
9441 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9442 */
9443 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9444
9445 if (val & LCPLL_POWER_DOWN_ALLOW) {
9446 val &= ~LCPLL_POWER_DOWN_ALLOW;
9447 I915_WRITE(LCPLL_CTL, val);
9448 POSTING_READ(LCPLL_CTL);
9449 }
9450
9451 val = hsw_read_dcomp(dev_priv);
9452 val |= D_COMP_COMP_FORCE;
9453 val &= ~D_COMP_COMP_DISABLE;
9454 hsw_write_dcomp(dev_priv, val);
9455
9456 val = I915_READ(LCPLL_CTL);
9457 val &= ~LCPLL_PLL_DISABLE;
9458 I915_WRITE(LCPLL_CTL, val);
9459
9460 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9461 DRM_ERROR("LCPLL not locked yet\n");
9462
9463 if (val & LCPLL_CD_SOURCE_FCLK) {
9464 val = I915_READ(LCPLL_CTL);
9465 val &= ~LCPLL_CD_SOURCE_FCLK;
9466 I915_WRITE(LCPLL_CTL, val);
9467
9468 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9469 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9470 DRM_ERROR("Switching back to LCPLL failed\n");
9471 }
9472
9473 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9474 intel_update_cdclk(dev_priv->dev);
9475 }
9476
9477 /*
9478 * Package states C8 and deeper are really deep PC states that can only be
9479 * reached when all the devices on the system allow it, so even if the graphics
9480 * device allows PC8+, it doesn't mean the system will actually get to these
9481 * states. Our driver only allows PC8+ when going into runtime PM.
9482 *
9483 * The requirements for PC8+ are that all the outputs are disabled, the power
9484 * well is disabled and most interrupts are disabled, and these are also
9485 * requirements for runtime PM. When these conditions are met, we manually do
9486 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9487 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9488 * hang the machine.
9489 *
9490 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9491 * the state of some registers, so when we come back from PC8+ we need to
9492 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9493 * need to take care of the registers kept by RC6. Notice that this happens even
9494 * if we don't put the device in PCI D3 state (which is what currently happens
9495 * because of the runtime PM support).
9496 *
9497 * For more, read "Display Sequences for Package C8" on the hardware
9498 * documentation.
9499 */
9500 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9501 {
9502 struct drm_device *dev = dev_priv->dev;
9503 uint32_t val;
9504
9505 DRM_DEBUG_KMS("Enabling package C8+\n");
9506
9507 if (HAS_PCH_LPT_LP(dev)) {
9508 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9509 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9510 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9511 }
9512
9513 lpt_disable_clkout_dp(dev);
9514 hsw_disable_lcpll(dev_priv, true, true);
9515 }
9516
9517 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9518 {
9519 struct drm_device *dev = dev_priv->dev;
9520 uint32_t val;
9521
9522 DRM_DEBUG_KMS("Disabling package C8+\n");
9523
9524 hsw_restore_lcpll(dev_priv);
9525 lpt_init_pch_refclk(dev);
9526
9527 if (HAS_PCH_LPT_LP(dev)) {
9528 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9529 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9530 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9531 }
9532 }
9533
9534 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9535 {
9536 struct drm_device *dev = old_state->dev;
9537 struct intel_atomic_state *old_intel_state =
9538 to_intel_atomic_state(old_state);
9539 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9540
9541 broxton_set_cdclk(dev, req_cdclk);
9542 }
9543
9544 /* compute the max rate for new configuration */
9545 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9546 {
9547 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9548 struct drm_i915_private *dev_priv = state->dev->dev_private;
9549 struct drm_crtc *crtc;
9550 struct drm_crtc_state *cstate;
9551 struct intel_crtc_state *crtc_state;
9552 unsigned max_pixel_rate = 0, i;
9553 enum pipe pipe;
9554
9555 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9556 sizeof(intel_state->min_pixclk));
9557
9558 for_each_crtc_in_state(state, crtc, cstate, i) {
9559 int pixel_rate;
9560
9561 crtc_state = to_intel_crtc_state(cstate);
9562 if (!crtc_state->base.enable) {
9563 intel_state->min_pixclk[i] = 0;
9564 continue;
9565 }
9566
9567 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9568
9569 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9570 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9571 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9572
9573 intel_state->min_pixclk[i] = pixel_rate;
9574 }
9575
9576 for_each_pipe(dev_priv, pipe)
9577 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9578
9579 return max_pixel_rate;
9580 }
9581
9582 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9583 {
9584 struct drm_i915_private *dev_priv = dev->dev_private;
9585 uint32_t val, data;
9586 int ret;
9587
9588 if (WARN((I915_READ(LCPLL_CTL) &
9589 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9590 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9591 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9592 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9593 "trying to change cdclk frequency with cdclk not enabled\n"))
9594 return;
9595
9596 mutex_lock(&dev_priv->rps.hw_lock);
9597 ret = sandybridge_pcode_write(dev_priv,
9598 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9599 mutex_unlock(&dev_priv->rps.hw_lock);
9600 if (ret) {
9601 DRM_ERROR("failed to inform pcode about cdclk change\n");
9602 return;
9603 }
9604
9605 val = I915_READ(LCPLL_CTL);
9606 val |= LCPLL_CD_SOURCE_FCLK;
9607 I915_WRITE(LCPLL_CTL, val);
9608
9609 if (wait_for_us(I915_READ(LCPLL_CTL) &
9610 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9611 DRM_ERROR("Switching to FCLK failed\n");
9612
9613 val = I915_READ(LCPLL_CTL);
9614 val &= ~LCPLL_CLK_FREQ_MASK;
9615
9616 switch (cdclk) {
9617 case 450000:
9618 val |= LCPLL_CLK_FREQ_450;
9619 data = 0;
9620 break;
9621 case 540000:
9622 val |= LCPLL_CLK_FREQ_54O_BDW;
9623 data = 1;
9624 break;
9625 case 337500:
9626 val |= LCPLL_CLK_FREQ_337_5_BDW;
9627 data = 2;
9628 break;
9629 case 675000:
9630 val |= LCPLL_CLK_FREQ_675_BDW;
9631 data = 3;
9632 break;
9633 default:
9634 WARN(1, "invalid cdclk frequency\n");
9635 return;
9636 }
9637
9638 I915_WRITE(LCPLL_CTL, val);
9639
9640 val = I915_READ(LCPLL_CTL);
9641 val &= ~LCPLL_CD_SOURCE_FCLK;
9642 I915_WRITE(LCPLL_CTL, val);
9643
9644 if (wait_for_us((I915_READ(LCPLL_CTL) &
9645 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9646 DRM_ERROR("Switching back to LCPLL failed\n");
9647
9648 mutex_lock(&dev_priv->rps.hw_lock);
9649 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9650 mutex_unlock(&dev_priv->rps.hw_lock);
9651
9652 intel_update_cdclk(dev);
9653
9654 WARN(cdclk != dev_priv->cdclk_freq,
9655 "cdclk requested %d kHz but got %d kHz\n",
9656 cdclk, dev_priv->cdclk_freq);
9657 }
9658
9659 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9660 {
9661 struct drm_i915_private *dev_priv = to_i915(state->dev);
9662 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9663 int max_pixclk = ilk_max_pixel_rate(state);
9664 int cdclk;
9665
9666 /*
9667 * FIXME should also account for plane ratio
9668 * once 64bpp pixel formats are supported.
9669 */
9670 if (max_pixclk > 540000)
9671 cdclk = 675000;
9672 else if (max_pixclk > 450000)
9673 cdclk = 540000;
9674 else if (max_pixclk > 337500)
9675 cdclk = 450000;
9676 else
9677 cdclk = 337500;
9678
9679 if (cdclk > dev_priv->max_cdclk_freq) {
9680 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9681 cdclk, dev_priv->max_cdclk_freq);
9682 return -EINVAL;
9683 }
9684
9685 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9686 if (!intel_state->active_crtcs)
9687 intel_state->dev_cdclk = 337500;
9688
9689 return 0;
9690 }
9691
9692 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9693 {
9694 struct drm_device *dev = old_state->dev;
9695 struct intel_atomic_state *old_intel_state =
9696 to_intel_atomic_state(old_state);
9697 unsigned req_cdclk = old_intel_state->dev_cdclk;
9698
9699 broadwell_set_cdclk(dev, req_cdclk);
9700 }
9701
9702 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9703 struct intel_crtc_state *crtc_state)
9704 {
9705 struct intel_encoder *intel_encoder =
9706 intel_ddi_get_crtc_new_encoder(crtc_state);
9707
9708 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9709 if (!intel_ddi_pll_select(crtc, crtc_state))
9710 return -EINVAL;
9711 }
9712
9713 crtc->lowfreq_avail = false;
9714
9715 return 0;
9716 }
9717
9718 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9719 enum port port,
9720 struct intel_crtc_state *pipe_config)
9721 {
9722 enum intel_dpll_id id;
9723
9724 switch (port) {
9725 case PORT_A:
9726 pipe_config->ddi_pll_sel = SKL_DPLL0;
9727 id = DPLL_ID_SKL_DPLL0;
9728 break;
9729 case PORT_B:
9730 pipe_config->ddi_pll_sel = SKL_DPLL1;
9731 id = DPLL_ID_SKL_DPLL1;
9732 break;
9733 case PORT_C:
9734 pipe_config->ddi_pll_sel = SKL_DPLL2;
9735 id = DPLL_ID_SKL_DPLL2;
9736 break;
9737 default:
9738 DRM_ERROR("Incorrect port type\n");
9739 return;
9740 }
9741
9742 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9743 }
9744
9745 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9746 enum port port,
9747 struct intel_crtc_state *pipe_config)
9748 {
9749 enum intel_dpll_id id;
9750 u32 temp;
9751
9752 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9753 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9754
9755 switch (pipe_config->ddi_pll_sel) {
9756 case SKL_DPLL0:
9757 id = DPLL_ID_SKL_DPLL0;
9758 break;
9759 case SKL_DPLL1:
9760 id = DPLL_ID_SKL_DPLL1;
9761 break;
9762 case SKL_DPLL2:
9763 id = DPLL_ID_SKL_DPLL2;
9764 break;
9765 case SKL_DPLL3:
9766 id = DPLL_ID_SKL_DPLL3;
9767 break;
9768 default:
9769 MISSING_CASE(pipe_config->ddi_pll_sel);
9770 return;
9771 }
9772
9773 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9774 }
9775
9776 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9777 enum port port,
9778 struct intel_crtc_state *pipe_config)
9779 {
9780 enum intel_dpll_id id;
9781
9782 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9783
9784 switch (pipe_config->ddi_pll_sel) {
9785 case PORT_CLK_SEL_WRPLL1:
9786 id = DPLL_ID_WRPLL1;
9787 break;
9788 case PORT_CLK_SEL_WRPLL2:
9789 id = DPLL_ID_WRPLL2;
9790 break;
9791 case PORT_CLK_SEL_SPLL:
9792 id = DPLL_ID_SPLL;
9793 break;
9794 case PORT_CLK_SEL_LCPLL_810:
9795 id = DPLL_ID_LCPLL_810;
9796 break;
9797 case PORT_CLK_SEL_LCPLL_1350:
9798 id = DPLL_ID_LCPLL_1350;
9799 break;
9800 case PORT_CLK_SEL_LCPLL_2700:
9801 id = DPLL_ID_LCPLL_2700;
9802 break;
9803 default:
9804 MISSING_CASE(pipe_config->ddi_pll_sel);
9805 /* fall through */
9806 case PORT_CLK_SEL_NONE:
9807 return;
9808 }
9809
9810 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9811 }
9812
9813 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9814 struct intel_crtc_state *pipe_config,
9815 unsigned long *power_domain_mask)
9816 {
9817 struct drm_device *dev = crtc->base.dev;
9818 struct drm_i915_private *dev_priv = dev->dev_private;
9819 enum intel_display_power_domain power_domain;
9820 u32 tmp;
9821
9822 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9823
9824 /*
9825 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9826 * consistency and less surprising code; it's in always on power).
9827 */
9828 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9829 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9830 enum pipe trans_edp_pipe;
9831 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9832 default:
9833 WARN(1, "unknown pipe linked to edp transcoder\n");
9834 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9835 case TRANS_DDI_EDP_INPUT_A_ON:
9836 trans_edp_pipe = PIPE_A;
9837 break;
9838 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9839 trans_edp_pipe = PIPE_B;
9840 break;
9841 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9842 trans_edp_pipe = PIPE_C;
9843 break;
9844 }
9845
9846 if (trans_edp_pipe == crtc->pipe)
9847 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9848 }
9849
9850 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9851 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9852 return false;
9853 *power_domain_mask |= BIT(power_domain);
9854
9855 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9856
9857 return tmp & PIPECONF_ENABLE;
9858 }
9859
9860 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9861 struct intel_crtc_state *pipe_config,
9862 unsigned long *power_domain_mask)
9863 {
9864 struct drm_device *dev = crtc->base.dev;
9865 struct drm_i915_private *dev_priv = dev->dev_private;
9866 enum intel_display_power_domain power_domain;
9867 enum port port;
9868 enum transcoder cpu_transcoder;
9869 u32 tmp;
9870
9871 pipe_config->has_dsi_encoder = false;
9872
9873 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9874 if (port == PORT_A)
9875 cpu_transcoder = TRANSCODER_DSI_A;
9876 else
9877 cpu_transcoder = TRANSCODER_DSI_C;
9878
9879 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9880 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9881 continue;
9882 *power_domain_mask |= BIT(power_domain);
9883
9884 /*
9885 * The PLL needs to be enabled with a valid divider
9886 * configuration, otherwise accessing DSI registers will hang
9887 * the machine. See BSpec North Display Engine
9888 * registers/MIPI[BXT]. We can break out here early, since we
9889 * need the same DSI PLL to be enabled for both DSI ports.
9890 */
9891 if (!intel_dsi_pll_is_enabled(dev_priv))
9892 break;
9893
9894 /* XXX: this works for video mode only */
9895 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9896 if (!(tmp & DPI_ENABLE))
9897 continue;
9898
9899 tmp = I915_READ(MIPI_CTRL(port));
9900 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9901 continue;
9902
9903 pipe_config->cpu_transcoder = cpu_transcoder;
9904 pipe_config->has_dsi_encoder = true;
9905 break;
9906 }
9907
9908 return pipe_config->has_dsi_encoder;
9909 }
9910
9911 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9912 struct intel_crtc_state *pipe_config)
9913 {
9914 struct drm_device *dev = crtc->base.dev;
9915 struct drm_i915_private *dev_priv = dev->dev_private;
9916 struct intel_shared_dpll *pll;
9917 enum port port;
9918 uint32_t tmp;
9919
9920 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9921
9922 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9923
9924 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9925 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9926 else if (IS_BROXTON(dev))
9927 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9928 else
9929 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9930
9931 pll = pipe_config->shared_dpll;
9932 if (pll) {
9933 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9934 &pipe_config->dpll_hw_state));
9935 }
9936
9937 /*
9938 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9939 * DDI E. So just check whether this pipe is wired to DDI E and whether
9940 * the PCH transcoder is on.
9941 */
9942 if (INTEL_INFO(dev)->gen < 9 &&
9943 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9944 pipe_config->has_pch_encoder = true;
9945
9946 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9947 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9948 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9949
9950 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9951 }
9952 }
9953
9954 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9955 struct intel_crtc_state *pipe_config)
9956 {
9957 struct drm_device *dev = crtc->base.dev;
9958 struct drm_i915_private *dev_priv = dev->dev_private;
9959 enum intel_display_power_domain power_domain;
9960 unsigned long power_domain_mask;
9961 bool active;
9962
9963 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9964 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9965 return false;
9966 power_domain_mask = BIT(power_domain);
9967
9968 pipe_config->shared_dpll = NULL;
9969
9970 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9971
9972 if (IS_BROXTON(dev_priv)) {
9973 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9974 &power_domain_mask);
9975 WARN_ON(active && pipe_config->has_dsi_encoder);
9976 if (pipe_config->has_dsi_encoder)
9977 active = true;
9978 }
9979
9980 if (!active)
9981 goto out;
9982
9983 if (!pipe_config->has_dsi_encoder) {
9984 haswell_get_ddi_port_state(crtc, pipe_config);
9985 intel_get_pipe_timings(crtc, pipe_config);
9986 }
9987
9988 intel_get_pipe_src_size(crtc, pipe_config);
9989
9990 pipe_config->gamma_mode =
9991 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9992
9993 if (INTEL_INFO(dev)->gen >= 9) {
9994 skl_init_scalers(dev, crtc, pipe_config);
9995 }
9996
9997 if (INTEL_INFO(dev)->gen >= 9) {
9998 pipe_config->scaler_state.scaler_id = -1;
9999 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10000 }
10001
10002 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10003 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10004 power_domain_mask |= BIT(power_domain);
10005 if (INTEL_INFO(dev)->gen >= 9)
10006 skylake_get_pfit_config(crtc, pipe_config);
10007 else
10008 ironlake_get_pfit_config(crtc, pipe_config);
10009 }
10010
10011 if (IS_HASWELL(dev))
10012 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10013 (I915_READ(IPS_CTL) & IPS_ENABLE);
10014
10015 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10016 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10017 pipe_config->pixel_multiplier =
10018 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10019 } else {
10020 pipe_config->pixel_multiplier = 1;
10021 }
10022
10023 out:
10024 for_each_power_domain(power_domain, power_domain_mask)
10025 intel_display_power_put(dev_priv, power_domain);
10026
10027 return active;
10028 }
10029
10030 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10031 const struct intel_plane_state *plane_state)
10032 {
10033 struct drm_device *dev = crtc->dev;
10034 struct drm_i915_private *dev_priv = dev->dev_private;
10035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10036 uint32_t cntl = 0, size = 0;
10037
10038 if (plane_state && plane_state->visible) {
10039 unsigned int width = plane_state->base.crtc_w;
10040 unsigned int height = plane_state->base.crtc_h;
10041 unsigned int stride = roundup_pow_of_two(width) * 4;
10042
10043 switch (stride) {
10044 default:
10045 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10046 width, stride);
10047 stride = 256;
10048 /* fallthrough */
10049 case 256:
10050 case 512:
10051 case 1024:
10052 case 2048:
10053 break;
10054 }
10055
10056 cntl |= CURSOR_ENABLE |
10057 CURSOR_GAMMA_ENABLE |
10058 CURSOR_FORMAT_ARGB |
10059 CURSOR_STRIDE(stride);
10060
10061 size = (height << 12) | width;
10062 }
10063
10064 if (intel_crtc->cursor_cntl != 0 &&
10065 (intel_crtc->cursor_base != base ||
10066 intel_crtc->cursor_size != size ||
10067 intel_crtc->cursor_cntl != cntl)) {
10068 /* On these chipsets we can only modify the base/size/stride
10069 * whilst the cursor is disabled.
10070 */
10071 I915_WRITE(CURCNTR(PIPE_A), 0);
10072 POSTING_READ(CURCNTR(PIPE_A));
10073 intel_crtc->cursor_cntl = 0;
10074 }
10075
10076 if (intel_crtc->cursor_base != base) {
10077 I915_WRITE(CURBASE(PIPE_A), base);
10078 intel_crtc->cursor_base = base;
10079 }
10080
10081 if (intel_crtc->cursor_size != size) {
10082 I915_WRITE(CURSIZE, size);
10083 intel_crtc->cursor_size = size;
10084 }
10085
10086 if (intel_crtc->cursor_cntl != cntl) {
10087 I915_WRITE(CURCNTR(PIPE_A), cntl);
10088 POSTING_READ(CURCNTR(PIPE_A));
10089 intel_crtc->cursor_cntl = cntl;
10090 }
10091 }
10092
10093 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10094 const struct intel_plane_state *plane_state)
10095 {
10096 struct drm_device *dev = crtc->dev;
10097 struct drm_i915_private *dev_priv = dev->dev_private;
10098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10099 int pipe = intel_crtc->pipe;
10100 uint32_t cntl = 0;
10101
10102 if (plane_state && plane_state->visible) {
10103 cntl = MCURSOR_GAMMA_ENABLE;
10104 switch (plane_state->base.crtc_w) {
10105 case 64:
10106 cntl |= CURSOR_MODE_64_ARGB_AX;
10107 break;
10108 case 128:
10109 cntl |= CURSOR_MODE_128_ARGB_AX;
10110 break;
10111 case 256:
10112 cntl |= CURSOR_MODE_256_ARGB_AX;
10113 break;
10114 default:
10115 MISSING_CASE(plane_state->base.crtc_w);
10116 return;
10117 }
10118 cntl |= pipe << 28; /* Connect to correct pipe */
10119
10120 if (HAS_DDI(dev))
10121 cntl |= CURSOR_PIPE_CSC_ENABLE;
10122
10123 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10124 cntl |= CURSOR_ROTATE_180;
10125 }
10126
10127 if (intel_crtc->cursor_cntl != cntl) {
10128 I915_WRITE(CURCNTR(pipe), cntl);
10129 POSTING_READ(CURCNTR(pipe));
10130 intel_crtc->cursor_cntl = cntl;
10131 }
10132
10133 /* and commit changes on next vblank */
10134 I915_WRITE(CURBASE(pipe), base);
10135 POSTING_READ(CURBASE(pipe));
10136
10137 intel_crtc->cursor_base = base;
10138 }
10139
10140 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10141 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10142 const struct intel_plane_state *plane_state)
10143 {
10144 struct drm_device *dev = crtc->dev;
10145 struct drm_i915_private *dev_priv = dev->dev_private;
10146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10147 int pipe = intel_crtc->pipe;
10148 u32 base = intel_crtc->cursor_addr;
10149 u32 pos = 0;
10150
10151 if (plane_state) {
10152 int x = plane_state->base.crtc_x;
10153 int y = plane_state->base.crtc_y;
10154
10155 if (x < 0) {
10156 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10157 x = -x;
10158 }
10159 pos |= x << CURSOR_X_SHIFT;
10160
10161 if (y < 0) {
10162 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10163 y = -y;
10164 }
10165 pos |= y << CURSOR_Y_SHIFT;
10166
10167 /* ILK+ do this automagically */
10168 if (HAS_GMCH_DISPLAY(dev) &&
10169 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10170 base += (plane_state->base.crtc_h *
10171 plane_state->base.crtc_w - 1) * 4;
10172 }
10173 }
10174
10175 I915_WRITE(CURPOS(pipe), pos);
10176
10177 if (IS_845G(dev) || IS_I865G(dev))
10178 i845_update_cursor(crtc, base, plane_state);
10179 else
10180 i9xx_update_cursor(crtc, base, plane_state);
10181 }
10182
10183 static bool cursor_size_ok(struct drm_device *dev,
10184 uint32_t width, uint32_t height)
10185 {
10186 if (width == 0 || height == 0)
10187 return false;
10188
10189 /*
10190 * 845g/865g are special in that they are only limited by
10191 * the width of their cursors, the height is arbitrary up to
10192 * the precision of the register. Everything else requires
10193 * square cursors, limited to a few power-of-two sizes.
10194 */
10195 if (IS_845G(dev) || IS_I865G(dev)) {
10196 if ((width & 63) != 0)
10197 return false;
10198
10199 if (width > (IS_845G(dev) ? 64 : 512))
10200 return false;
10201
10202 if (height > 1023)
10203 return false;
10204 } else {
10205 switch (width | height) {
10206 case 256:
10207 case 128:
10208 if (IS_GEN2(dev))
10209 return false;
10210 case 64:
10211 break;
10212 default:
10213 return false;
10214 }
10215 }
10216
10217 return true;
10218 }
10219
10220 /* VESA 640x480x72Hz mode to set on the pipe */
10221 static struct drm_display_mode load_detect_mode = {
10222 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10223 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10224 };
10225
10226 struct drm_framebuffer *
10227 __intel_framebuffer_create(struct drm_device *dev,
10228 struct drm_mode_fb_cmd2 *mode_cmd,
10229 struct drm_i915_gem_object *obj)
10230 {
10231 struct intel_framebuffer *intel_fb;
10232 int ret;
10233
10234 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10235 if (!intel_fb)
10236 return ERR_PTR(-ENOMEM);
10237
10238 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10239 if (ret)
10240 goto err;
10241
10242 return &intel_fb->base;
10243
10244 err:
10245 kfree(intel_fb);
10246 return ERR_PTR(ret);
10247 }
10248
10249 static struct drm_framebuffer *
10250 intel_framebuffer_create(struct drm_device *dev,
10251 struct drm_mode_fb_cmd2 *mode_cmd,
10252 struct drm_i915_gem_object *obj)
10253 {
10254 struct drm_framebuffer *fb;
10255 int ret;
10256
10257 ret = i915_mutex_lock_interruptible(dev);
10258 if (ret)
10259 return ERR_PTR(ret);
10260 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10261 mutex_unlock(&dev->struct_mutex);
10262
10263 return fb;
10264 }
10265
10266 static u32
10267 intel_framebuffer_pitch_for_width(int width, int bpp)
10268 {
10269 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10270 return ALIGN(pitch, 64);
10271 }
10272
10273 static u32
10274 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10275 {
10276 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10277 return PAGE_ALIGN(pitch * mode->vdisplay);
10278 }
10279
10280 static struct drm_framebuffer *
10281 intel_framebuffer_create_for_mode(struct drm_device *dev,
10282 struct drm_display_mode *mode,
10283 int depth, int bpp)
10284 {
10285 struct drm_framebuffer *fb;
10286 struct drm_i915_gem_object *obj;
10287 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10288
10289 obj = i915_gem_alloc_object(dev,
10290 intel_framebuffer_size_for_mode(mode, bpp));
10291 if (obj == NULL)
10292 return ERR_PTR(-ENOMEM);
10293
10294 mode_cmd.width = mode->hdisplay;
10295 mode_cmd.height = mode->vdisplay;
10296 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10297 bpp);
10298 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10299
10300 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10301 if (IS_ERR(fb))
10302 drm_gem_object_unreference_unlocked(&obj->base);
10303
10304 return fb;
10305 }
10306
10307 static struct drm_framebuffer *
10308 mode_fits_in_fbdev(struct drm_device *dev,
10309 struct drm_display_mode *mode)
10310 {
10311 #ifdef CONFIG_DRM_FBDEV_EMULATION
10312 struct drm_i915_private *dev_priv = dev->dev_private;
10313 struct drm_i915_gem_object *obj;
10314 struct drm_framebuffer *fb;
10315
10316 if (!dev_priv->fbdev)
10317 return NULL;
10318
10319 if (!dev_priv->fbdev->fb)
10320 return NULL;
10321
10322 obj = dev_priv->fbdev->fb->obj;
10323 BUG_ON(!obj);
10324
10325 fb = &dev_priv->fbdev->fb->base;
10326 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10327 fb->bits_per_pixel))
10328 return NULL;
10329
10330 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10331 return NULL;
10332
10333 drm_framebuffer_reference(fb);
10334 return fb;
10335 #else
10336 return NULL;
10337 #endif
10338 }
10339
10340 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10341 struct drm_crtc *crtc,
10342 struct drm_display_mode *mode,
10343 struct drm_framebuffer *fb,
10344 int x, int y)
10345 {
10346 struct drm_plane_state *plane_state;
10347 int hdisplay, vdisplay;
10348 int ret;
10349
10350 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10351 if (IS_ERR(plane_state))
10352 return PTR_ERR(plane_state);
10353
10354 if (mode)
10355 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10356 else
10357 hdisplay = vdisplay = 0;
10358
10359 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10360 if (ret)
10361 return ret;
10362 drm_atomic_set_fb_for_plane(plane_state, fb);
10363 plane_state->crtc_x = 0;
10364 plane_state->crtc_y = 0;
10365 plane_state->crtc_w = hdisplay;
10366 plane_state->crtc_h = vdisplay;
10367 plane_state->src_x = x << 16;
10368 plane_state->src_y = y << 16;
10369 plane_state->src_w = hdisplay << 16;
10370 plane_state->src_h = vdisplay << 16;
10371
10372 return 0;
10373 }
10374
10375 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10376 struct drm_display_mode *mode,
10377 struct intel_load_detect_pipe *old,
10378 struct drm_modeset_acquire_ctx *ctx)
10379 {
10380 struct intel_crtc *intel_crtc;
10381 struct intel_encoder *intel_encoder =
10382 intel_attached_encoder(connector);
10383 struct drm_crtc *possible_crtc;
10384 struct drm_encoder *encoder = &intel_encoder->base;
10385 struct drm_crtc *crtc = NULL;
10386 struct drm_device *dev = encoder->dev;
10387 struct drm_framebuffer *fb;
10388 struct drm_mode_config *config = &dev->mode_config;
10389 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10390 struct drm_connector_state *connector_state;
10391 struct intel_crtc_state *crtc_state;
10392 int ret, i = -1;
10393
10394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10395 connector->base.id, connector->name,
10396 encoder->base.id, encoder->name);
10397
10398 old->restore_state = NULL;
10399
10400 retry:
10401 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10402 if (ret)
10403 goto fail;
10404
10405 /*
10406 * Algorithm gets a little messy:
10407 *
10408 * - if the connector already has an assigned crtc, use it (but make
10409 * sure it's on first)
10410 *
10411 * - try to find the first unused crtc that can drive this connector,
10412 * and use that if we find one
10413 */
10414
10415 /* See if we already have a CRTC for this connector */
10416 if (connector->state->crtc) {
10417 crtc = connector->state->crtc;
10418
10419 ret = drm_modeset_lock(&crtc->mutex, ctx);
10420 if (ret)
10421 goto fail;
10422
10423 /* Make sure the crtc and connector are running */
10424 goto found;
10425 }
10426
10427 /* Find an unused one (if possible) */
10428 for_each_crtc(dev, possible_crtc) {
10429 i++;
10430 if (!(encoder->possible_crtcs & (1 << i)))
10431 continue;
10432
10433 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10434 if (ret)
10435 goto fail;
10436
10437 if (possible_crtc->state->enable) {
10438 drm_modeset_unlock(&possible_crtc->mutex);
10439 continue;
10440 }
10441
10442 crtc = possible_crtc;
10443 break;
10444 }
10445
10446 /*
10447 * If we didn't find an unused CRTC, don't use any.
10448 */
10449 if (!crtc) {
10450 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10451 goto fail;
10452 }
10453
10454 found:
10455 intel_crtc = to_intel_crtc(crtc);
10456
10457 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10458 if (ret)
10459 goto fail;
10460
10461 state = drm_atomic_state_alloc(dev);
10462 restore_state = drm_atomic_state_alloc(dev);
10463 if (!state || !restore_state) {
10464 ret = -ENOMEM;
10465 goto fail;
10466 }
10467
10468 state->acquire_ctx = ctx;
10469 restore_state->acquire_ctx = ctx;
10470
10471 connector_state = drm_atomic_get_connector_state(state, connector);
10472 if (IS_ERR(connector_state)) {
10473 ret = PTR_ERR(connector_state);
10474 goto fail;
10475 }
10476
10477 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10478 if (ret)
10479 goto fail;
10480
10481 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10482 if (IS_ERR(crtc_state)) {
10483 ret = PTR_ERR(crtc_state);
10484 goto fail;
10485 }
10486
10487 crtc_state->base.active = crtc_state->base.enable = true;
10488
10489 if (!mode)
10490 mode = &load_detect_mode;
10491
10492 /* We need a framebuffer large enough to accommodate all accesses
10493 * that the plane may generate whilst we perform load detection.
10494 * We can not rely on the fbcon either being present (we get called
10495 * during its initialisation to detect all boot displays, or it may
10496 * not even exist) or that it is large enough to satisfy the
10497 * requested mode.
10498 */
10499 fb = mode_fits_in_fbdev(dev, mode);
10500 if (fb == NULL) {
10501 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10502 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10503 } else
10504 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10505 if (IS_ERR(fb)) {
10506 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10507 goto fail;
10508 }
10509
10510 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10511 if (ret)
10512 goto fail;
10513
10514 drm_framebuffer_unreference(fb);
10515
10516 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10517 if (ret)
10518 goto fail;
10519
10520 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10521 if (!ret)
10522 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10523 if (!ret)
10524 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10525 if (ret) {
10526 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10527 goto fail;
10528 }
10529
10530 ret = drm_atomic_commit(state);
10531 if (ret) {
10532 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10533 goto fail;
10534 }
10535
10536 old->restore_state = restore_state;
10537
10538 /* let the connector get through one full cycle before testing */
10539 intel_wait_for_vblank(dev, intel_crtc->pipe);
10540 return true;
10541
10542 fail:
10543 drm_atomic_state_free(state);
10544 drm_atomic_state_free(restore_state);
10545 restore_state = state = NULL;
10546
10547 if (ret == -EDEADLK) {
10548 drm_modeset_backoff(ctx);
10549 goto retry;
10550 }
10551
10552 return false;
10553 }
10554
10555 void intel_release_load_detect_pipe(struct drm_connector *connector,
10556 struct intel_load_detect_pipe *old,
10557 struct drm_modeset_acquire_ctx *ctx)
10558 {
10559 struct intel_encoder *intel_encoder =
10560 intel_attached_encoder(connector);
10561 struct drm_encoder *encoder = &intel_encoder->base;
10562 struct drm_atomic_state *state = old->restore_state;
10563 int ret;
10564
10565 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10566 connector->base.id, connector->name,
10567 encoder->base.id, encoder->name);
10568
10569 if (!state)
10570 return;
10571
10572 ret = drm_atomic_commit(state);
10573 if (ret) {
10574 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10575 drm_atomic_state_free(state);
10576 }
10577 }
10578
10579 static int i9xx_pll_refclk(struct drm_device *dev,
10580 const struct intel_crtc_state *pipe_config)
10581 {
10582 struct drm_i915_private *dev_priv = dev->dev_private;
10583 u32 dpll = pipe_config->dpll_hw_state.dpll;
10584
10585 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10586 return dev_priv->vbt.lvds_ssc_freq;
10587 else if (HAS_PCH_SPLIT(dev))
10588 return 120000;
10589 else if (!IS_GEN2(dev))
10590 return 96000;
10591 else
10592 return 48000;
10593 }
10594
10595 /* Returns the clock of the currently programmed mode of the given pipe. */
10596 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10597 struct intel_crtc_state *pipe_config)
10598 {
10599 struct drm_device *dev = crtc->base.dev;
10600 struct drm_i915_private *dev_priv = dev->dev_private;
10601 int pipe = pipe_config->cpu_transcoder;
10602 u32 dpll = pipe_config->dpll_hw_state.dpll;
10603 u32 fp;
10604 intel_clock_t clock;
10605 int port_clock;
10606 int refclk = i9xx_pll_refclk(dev, pipe_config);
10607
10608 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10609 fp = pipe_config->dpll_hw_state.fp0;
10610 else
10611 fp = pipe_config->dpll_hw_state.fp1;
10612
10613 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10614 if (IS_PINEVIEW(dev)) {
10615 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10616 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10617 } else {
10618 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10619 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10620 }
10621
10622 if (!IS_GEN2(dev)) {
10623 if (IS_PINEVIEW(dev))
10624 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10625 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10626 else
10627 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10628 DPLL_FPA01_P1_POST_DIV_SHIFT);
10629
10630 switch (dpll & DPLL_MODE_MASK) {
10631 case DPLLB_MODE_DAC_SERIAL:
10632 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10633 5 : 10;
10634 break;
10635 case DPLLB_MODE_LVDS:
10636 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10637 7 : 14;
10638 break;
10639 default:
10640 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10641 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10642 return;
10643 }
10644
10645 if (IS_PINEVIEW(dev))
10646 port_clock = pnv_calc_dpll_params(refclk, &clock);
10647 else
10648 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10649 } else {
10650 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10651 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10652
10653 if (is_lvds) {
10654 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10655 DPLL_FPA01_P1_POST_DIV_SHIFT);
10656
10657 if (lvds & LVDS_CLKB_POWER_UP)
10658 clock.p2 = 7;
10659 else
10660 clock.p2 = 14;
10661 } else {
10662 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10663 clock.p1 = 2;
10664 else {
10665 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10666 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10667 }
10668 if (dpll & PLL_P2_DIVIDE_BY_4)
10669 clock.p2 = 4;
10670 else
10671 clock.p2 = 2;
10672 }
10673
10674 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10675 }
10676
10677 /*
10678 * This value includes pixel_multiplier. We will use
10679 * port_clock to compute adjusted_mode.crtc_clock in the
10680 * encoder's get_config() function.
10681 */
10682 pipe_config->port_clock = port_clock;
10683 }
10684
10685 int intel_dotclock_calculate(int link_freq,
10686 const struct intel_link_m_n *m_n)
10687 {
10688 /*
10689 * The calculation for the data clock is:
10690 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10691 * But we want to avoid losing precison if possible, so:
10692 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10693 *
10694 * and the link clock is simpler:
10695 * link_clock = (m * link_clock) / n
10696 */
10697
10698 if (!m_n->link_n)
10699 return 0;
10700
10701 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10702 }
10703
10704 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10705 struct intel_crtc_state *pipe_config)
10706 {
10707 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10708
10709 /* read out port_clock from the DPLL */
10710 i9xx_crtc_clock_get(crtc, pipe_config);
10711
10712 /*
10713 * In case there is an active pipe without active ports,
10714 * we may need some idea for the dotclock anyway.
10715 * Calculate one based on the FDI configuration.
10716 */
10717 pipe_config->base.adjusted_mode.crtc_clock =
10718 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10719 &pipe_config->fdi_m_n);
10720 }
10721
10722 /** Returns the currently programmed mode of the given pipe. */
10723 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10724 struct drm_crtc *crtc)
10725 {
10726 struct drm_i915_private *dev_priv = dev->dev_private;
10727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10728 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10729 struct drm_display_mode *mode;
10730 struct intel_crtc_state *pipe_config;
10731 int htot = I915_READ(HTOTAL(cpu_transcoder));
10732 int hsync = I915_READ(HSYNC(cpu_transcoder));
10733 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10734 int vsync = I915_READ(VSYNC(cpu_transcoder));
10735 enum pipe pipe = intel_crtc->pipe;
10736
10737 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10738 if (!mode)
10739 return NULL;
10740
10741 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10742 if (!pipe_config) {
10743 kfree(mode);
10744 return NULL;
10745 }
10746
10747 /*
10748 * Construct a pipe_config sufficient for getting the clock info
10749 * back out of crtc_clock_get.
10750 *
10751 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10752 * to use a real value here instead.
10753 */
10754 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10755 pipe_config->pixel_multiplier = 1;
10756 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10757 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10758 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10759 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10760
10761 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10762 mode->hdisplay = (htot & 0xffff) + 1;
10763 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10764 mode->hsync_start = (hsync & 0xffff) + 1;
10765 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10766 mode->vdisplay = (vtot & 0xffff) + 1;
10767 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10768 mode->vsync_start = (vsync & 0xffff) + 1;
10769 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10770
10771 drm_mode_set_name(mode);
10772
10773 kfree(pipe_config);
10774
10775 return mode;
10776 }
10777
10778 void intel_mark_busy(struct drm_device *dev)
10779 {
10780 struct drm_i915_private *dev_priv = dev->dev_private;
10781
10782 if (dev_priv->mm.busy)
10783 return;
10784
10785 intel_runtime_pm_get(dev_priv);
10786 i915_update_gfx_val(dev_priv);
10787 if (INTEL_INFO(dev)->gen >= 6)
10788 gen6_rps_busy(dev_priv);
10789 dev_priv->mm.busy = true;
10790 }
10791
10792 void intel_mark_idle(struct drm_device *dev)
10793 {
10794 struct drm_i915_private *dev_priv = dev->dev_private;
10795
10796 if (!dev_priv->mm.busy)
10797 return;
10798
10799 dev_priv->mm.busy = false;
10800
10801 if (INTEL_INFO(dev)->gen >= 6)
10802 gen6_rps_idle(dev->dev_private);
10803
10804 intel_runtime_pm_put(dev_priv);
10805 }
10806
10807 static void intel_crtc_destroy(struct drm_crtc *crtc)
10808 {
10809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10810 struct drm_device *dev = crtc->dev;
10811 struct intel_unpin_work *work;
10812
10813 spin_lock_irq(&dev->event_lock);
10814 work = intel_crtc->unpin_work;
10815 intel_crtc->unpin_work = NULL;
10816 spin_unlock_irq(&dev->event_lock);
10817
10818 if (work) {
10819 cancel_work_sync(&work->work);
10820 kfree(work);
10821 }
10822
10823 drm_crtc_cleanup(crtc);
10824
10825 kfree(intel_crtc);
10826 }
10827
10828 static void intel_unpin_work_fn(struct work_struct *__work)
10829 {
10830 struct intel_unpin_work *work =
10831 container_of(__work, struct intel_unpin_work, work);
10832 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10833 struct drm_device *dev = crtc->base.dev;
10834 struct drm_plane *primary = crtc->base.primary;
10835
10836 mutex_lock(&dev->struct_mutex);
10837 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10838 drm_gem_object_unreference(&work->pending_flip_obj->base);
10839
10840 if (work->flip_queued_req)
10841 i915_gem_request_assign(&work->flip_queued_req, NULL);
10842 mutex_unlock(&dev->struct_mutex);
10843
10844 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10845 intel_fbc_post_update(crtc);
10846 drm_framebuffer_unreference(work->old_fb);
10847
10848 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10849 atomic_dec(&crtc->unpin_work_count);
10850
10851 kfree(work);
10852 }
10853
10854 static void do_intel_finish_page_flip(struct drm_device *dev,
10855 struct drm_crtc *crtc)
10856 {
10857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10858 struct intel_unpin_work *work;
10859 unsigned long flags;
10860
10861 /* Ignore early vblank irqs */
10862 if (intel_crtc == NULL)
10863 return;
10864
10865 /*
10866 * This is called both by irq handlers and the reset code (to complete
10867 * lost pageflips) so needs the full irqsave spinlocks.
10868 */
10869 spin_lock_irqsave(&dev->event_lock, flags);
10870 work = intel_crtc->unpin_work;
10871
10872 /* Ensure we don't miss a work->pending update ... */
10873 smp_rmb();
10874
10875 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10876 spin_unlock_irqrestore(&dev->event_lock, flags);
10877 return;
10878 }
10879
10880 page_flip_completed(intel_crtc);
10881
10882 spin_unlock_irqrestore(&dev->event_lock, flags);
10883 }
10884
10885 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10886 {
10887 struct drm_i915_private *dev_priv = dev->dev_private;
10888 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10889
10890 do_intel_finish_page_flip(dev, crtc);
10891 }
10892
10893 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10894 {
10895 struct drm_i915_private *dev_priv = dev->dev_private;
10896 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10897
10898 do_intel_finish_page_flip(dev, crtc);
10899 }
10900
10901 /* Is 'a' after or equal to 'b'? */
10902 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10903 {
10904 return !((a - b) & 0x80000000);
10905 }
10906
10907 static bool page_flip_finished(struct intel_crtc *crtc)
10908 {
10909 struct drm_device *dev = crtc->base.dev;
10910 struct drm_i915_private *dev_priv = dev->dev_private;
10911
10912 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10913 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10914 return true;
10915
10916 /*
10917 * The relevant registers doen't exist on pre-ctg.
10918 * As the flip done interrupt doesn't trigger for mmio
10919 * flips on gmch platforms, a flip count check isn't
10920 * really needed there. But since ctg has the registers,
10921 * include it in the check anyway.
10922 */
10923 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10924 return true;
10925
10926 /*
10927 * BDW signals flip done immediately if the plane
10928 * is disabled, even if the plane enable is already
10929 * armed to occur at the next vblank :(
10930 */
10931
10932 /*
10933 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10934 * used the same base address. In that case the mmio flip might
10935 * have completed, but the CS hasn't even executed the flip yet.
10936 *
10937 * A flip count check isn't enough as the CS might have updated
10938 * the base address just after start of vblank, but before we
10939 * managed to process the interrupt. This means we'd complete the
10940 * CS flip too soon.
10941 *
10942 * Combining both checks should get us a good enough result. It may
10943 * still happen that the CS flip has been executed, but has not
10944 * yet actually completed. But in case the base address is the same
10945 * anyway, we don't really care.
10946 */
10947 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10948 crtc->unpin_work->gtt_offset &&
10949 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10950 crtc->unpin_work->flip_count);
10951 }
10952
10953 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10954 {
10955 struct drm_i915_private *dev_priv = dev->dev_private;
10956 struct intel_crtc *intel_crtc =
10957 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10958 unsigned long flags;
10959
10960
10961 /*
10962 * This is called both by irq handlers and the reset code (to complete
10963 * lost pageflips) so needs the full irqsave spinlocks.
10964 *
10965 * NB: An MMIO update of the plane base pointer will also
10966 * generate a page-flip completion irq, i.e. every modeset
10967 * is also accompanied by a spurious intel_prepare_page_flip().
10968 */
10969 spin_lock_irqsave(&dev->event_lock, flags);
10970 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10971 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10972 spin_unlock_irqrestore(&dev->event_lock, flags);
10973 }
10974
10975 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10976 {
10977 /* Ensure that the work item is consistent when activating it ... */
10978 smp_wmb();
10979 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10980 /* and that it is marked active as soon as the irq could fire. */
10981 smp_wmb();
10982 }
10983
10984 static int intel_gen2_queue_flip(struct drm_device *dev,
10985 struct drm_crtc *crtc,
10986 struct drm_framebuffer *fb,
10987 struct drm_i915_gem_object *obj,
10988 struct drm_i915_gem_request *req,
10989 uint32_t flags)
10990 {
10991 struct intel_engine_cs *engine = req->engine;
10992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10993 u32 flip_mask;
10994 int ret;
10995
10996 ret = intel_ring_begin(req, 6);
10997 if (ret)
10998 return ret;
10999
11000 /* Can't queue multiple flips, so wait for the previous
11001 * one to finish before executing the next.
11002 */
11003 if (intel_crtc->plane)
11004 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11005 else
11006 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11007 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11008 intel_ring_emit(engine, MI_NOOP);
11009 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11010 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11011 intel_ring_emit(engine, fb->pitches[0]);
11012 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11013 intel_ring_emit(engine, 0); /* aux display base address, unused */
11014
11015 intel_mark_page_flip_active(intel_crtc->unpin_work);
11016 return 0;
11017 }
11018
11019 static int intel_gen3_queue_flip(struct drm_device *dev,
11020 struct drm_crtc *crtc,
11021 struct drm_framebuffer *fb,
11022 struct drm_i915_gem_object *obj,
11023 struct drm_i915_gem_request *req,
11024 uint32_t flags)
11025 {
11026 struct intel_engine_cs *engine = req->engine;
11027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11028 u32 flip_mask;
11029 int ret;
11030
11031 ret = intel_ring_begin(req, 6);
11032 if (ret)
11033 return ret;
11034
11035 if (intel_crtc->plane)
11036 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11037 else
11038 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11039 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11040 intel_ring_emit(engine, MI_NOOP);
11041 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11042 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11043 intel_ring_emit(engine, fb->pitches[0]);
11044 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11045 intel_ring_emit(engine, MI_NOOP);
11046
11047 intel_mark_page_flip_active(intel_crtc->unpin_work);
11048 return 0;
11049 }
11050
11051 static int intel_gen4_queue_flip(struct drm_device *dev,
11052 struct drm_crtc *crtc,
11053 struct drm_framebuffer *fb,
11054 struct drm_i915_gem_object *obj,
11055 struct drm_i915_gem_request *req,
11056 uint32_t flags)
11057 {
11058 struct intel_engine_cs *engine = req->engine;
11059 struct drm_i915_private *dev_priv = dev->dev_private;
11060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11061 uint32_t pf, pipesrc;
11062 int ret;
11063
11064 ret = intel_ring_begin(req, 4);
11065 if (ret)
11066 return ret;
11067
11068 /* i965+ uses the linear or tiled offsets from the
11069 * Display Registers (which do not change across a page-flip)
11070 * so we need only reprogram the base address.
11071 */
11072 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11073 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11074 intel_ring_emit(engine, fb->pitches[0]);
11075 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11076 obj->tiling_mode);
11077
11078 /* XXX Enabling the panel-fitter across page-flip is so far
11079 * untested on non-native modes, so ignore it for now.
11080 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11081 */
11082 pf = 0;
11083 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11084 intel_ring_emit(engine, pf | pipesrc);
11085
11086 intel_mark_page_flip_active(intel_crtc->unpin_work);
11087 return 0;
11088 }
11089
11090 static int intel_gen6_queue_flip(struct drm_device *dev,
11091 struct drm_crtc *crtc,
11092 struct drm_framebuffer *fb,
11093 struct drm_i915_gem_object *obj,
11094 struct drm_i915_gem_request *req,
11095 uint32_t flags)
11096 {
11097 struct intel_engine_cs *engine = req->engine;
11098 struct drm_i915_private *dev_priv = dev->dev_private;
11099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11100 uint32_t pf, pipesrc;
11101 int ret;
11102
11103 ret = intel_ring_begin(req, 4);
11104 if (ret)
11105 return ret;
11106
11107 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11109 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11110 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11111
11112 /* Contrary to the suggestions in the documentation,
11113 * "Enable Panel Fitter" does not seem to be required when page
11114 * flipping with a non-native mode, and worse causes a normal
11115 * modeset to fail.
11116 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11117 */
11118 pf = 0;
11119 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11120 intel_ring_emit(engine, pf | pipesrc);
11121
11122 intel_mark_page_flip_active(intel_crtc->unpin_work);
11123 return 0;
11124 }
11125
11126 static int intel_gen7_queue_flip(struct drm_device *dev,
11127 struct drm_crtc *crtc,
11128 struct drm_framebuffer *fb,
11129 struct drm_i915_gem_object *obj,
11130 struct drm_i915_gem_request *req,
11131 uint32_t flags)
11132 {
11133 struct intel_engine_cs *engine = req->engine;
11134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11135 uint32_t plane_bit = 0;
11136 int len, ret;
11137
11138 switch (intel_crtc->plane) {
11139 case PLANE_A:
11140 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11141 break;
11142 case PLANE_B:
11143 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11144 break;
11145 case PLANE_C:
11146 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11147 break;
11148 default:
11149 WARN_ONCE(1, "unknown plane in flip command\n");
11150 return -ENODEV;
11151 }
11152
11153 len = 4;
11154 if (engine->id == RCS) {
11155 len += 6;
11156 /*
11157 * On Gen 8, SRM is now taking an extra dword to accommodate
11158 * 48bits addresses, and we need a NOOP for the batch size to
11159 * stay even.
11160 */
11161 if (IS_GEN8(dev))
11162 len += 2;
11163 }
11164
11165 /*
11166 * BSpec MI_DISPLAY_FLIP for IVB:
11167 * "The full packet must be contained within the same cache line."
11168 *
11169 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11170 * cacheline, if we ever start emitting more commands before
11171 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11172 * then do the cacheline alignment, and finally emit the
11173 * MI_DISPLAY_FLIP.
11174 */
11175 ret = intel_ring_cacheline_align(req);
11176 if (ret)
11177 return ret;
11178
11179 ret = intel_ring_begin(req, len);
11180 if (ret)
11181 return ret;
11182
11183 /* Unmask the flip-done completion message. Note that the bspec says that
11184 * we should do this for both the BCS and RCS, and that we must not unmask
11185 * more than one flip event at any time (or ensure that one flip message
11186 * can be sent by waiting for flip-done prior to queueing new flips).
11187 * Experimentation says that BCS works despite DERRMR masking all
11188 * flip-done completion events and that unmasking all planes at once
11189 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11190 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11191 */
11192 if (engine->id == RCS) {
11193 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11194 intel_ring_emit_reg(engine, DERRMR);
11195 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11196 DERRMR_PIPEB_PRI_FLIP_DONE |
11197 DERRMR_PIPEC_PRI_FLIP_DONE));
11198 if (IS_GEN8(dev))
11199 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11200 MI_SRM_LRM_GLOBAL_GTT);
11201 else
11202 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11203 MI_SRM_LRM_GLOBAL_GTT);
11204 intel_ring_emit_reg(engine, DERRMR);
11205 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11206 if (IS_GEN8(dev)) {
11207 intel_ring_emit(engine, 0);
11208 intel_ring_emit(engine, MI_NOOP);
11209 }
11210 }
11211
11212 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11213 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11214 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11215 intel_ring_emit(engine, (MI_NOOP));
11216
11217 intel_mark_page_flip_active(intel_crtc->unpin_work);
11218 return 0;
11219 }
11220
11221 static bool use_mmio_flip(struct intel_engine_cs *engine,
11222 struct drm_i915_gem_object *obj)
11223 {
11224 /*
11225 * This is not being used for older platforms, because
11226 * non-availability of flip done interrupt forces us to use
11227 * CS flips. Older platforms derive flip done using some clever
11228 * tricks involving the flip_pending status bits and vblank irqs.
11229 * So using MMIO flips there would disrupt this mechanism.
11230 */
11231
11232 if (engine == NULL)
11233 return true;
11234
11235 if (INTEL_INFO(engine->dev)->gen < 5)
11236 return false;
11237
11238 if (i915.use_mmio_flip < 0)
11239 return false;
11240 else if (i915.use_mmio_flip > 0)
11241 return true;
11242 else if (i915.enable_execlists)
11243 return true;
11244 else if (obj->base.dma_buf &&
11245 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11246 false))
11247 return true;
11248 else
11249 return engine != i915_gem_request_get_engine(obj->last_write_req);
11250 }
11251
11252 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11253 unsigned int rotation,
11254 struct intel_unpin_work *work)
11255 {
11256 struct drm_device *dev = intel_crtc->base.dev;
11257 struct drm_i915_private *dev_priv = dev->dev_private;
11258 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11259 const enum pipe pipe = intel_crtc->pipe;
11260 u32 ctl, stride, tile_height;
11261
11262 ctl = I915_READ(PLANE_CTL(pipe, 0));
11263 ctl &= ~PLANE_CTL_TILED_MASK;
11264 switch (fb->modifier[0]) {
11265 case DRM_FORMAT_MOD_NONE:
11266 break;
11267 case I915_FORMAT_MOD_X_TILED:
11268 ctl |= PLANE_CTL_TILED_X;
11269 break;
11270 case I915_FORMAT_MOD_Y_TILED:
11271 ctl |= PLANE_CTL_TILED_Y;
11272 break;
11273 case I915_FORMAT_MOD_Yf_TILED:
11274 ctl |= PLANE_CTL_TILED_YF;
11275 break;
11276 default:
11277 MISSING_CASE(fb->modifier[0]);
11278 }
11279
11280 /*
11281 * The stride is either expressed as a multiple of 64 bytes chunks for
11282 * linear buffers or in number of tiles for tiled buffers.
11283 */
11284 if (intel_rotation_90_or_270(rotation)) {
11285 /* stride = Surface height in tiles */
11286 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11287 stride = DIV_ROUND_UP(fb->height, tile_height);
11288 } else {
11289 stride = fb->pitches[0] /
11290 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11291 fb->pixel_format);
11292 }
11293
11294 /*
11295 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11296 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11297 */
11298 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11299 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11300
11301 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11302 POSTING_READ(PLANE_SURF(pipe, 0));
11303 }
11304
11305 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11306 struct intel_unpin_work *work)
11307 {
11308 struct drm_device *dev = intel_crtc->base.dev;
11309 struct drm_i915_private *dev_priv = dev->dev_private;
11310 struct intel_framebuffer *intel_fb =
11311 to_intel_framebuffer(intel_crtc->base.primary->fb);
11312 struct drm_i915_gem_object *obj = intel_fb->obj;
11313 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11314 u32 dspcntr;
11315
11316 dspcntr = I915_READ(reg);
11317
11318 if (obj->tiling_mode != I915_TILING_NONE)
11319 dspcntr |= DISPPLANE_TILED;
11320 else
11321 dspcntr &= ~DISPPLANE_TILED;
11322
11323 I915_WRITE(reg, dspcntr);
11324
11325 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11326 POSTING_READ(DSPSURF(intel_crtc->plane));
11327 }
11328
11329 /*
11330 * XXX: This is the temporary way to update the plane registers until we get
11331 * around to using the usual plane update functions for MMIO flips
11332 */
11333 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11334 {
11335 struct intel_crtc *crtc = mmio_flip->crtc;
11336 struct intel_unpin_work *work;
11337
11338 spin_lock_irq(&crtc->base.dev->event_lock);
11339 work = crtc->unpin_work;
11340 spin_unlock_irq(&crtc->base.dev->event_lock);
11341 if (work == NULL)
11342 return;
11343
11344 intel_mark_page_flip_active(work);
11345
11346 intel_pipe_update_start(crtc);
11347
11348 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11349 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11350 else
11351 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11352 ilk_do_mmio_flip(crtc, work);
11353
11354 intel_pipe_update_end(crtc);
11355 }
11356
11357 static void intel_mmio_flip_work_func(struct work_struct *work)
11358 {
11359 struct intel_mmio_flip *mmio_flip =
11360 container_of(work, struct intel_mmio_flip, work);
11361 struct intel_framebuffer *intel_fb =
11362 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11363 struct drm_i915_gem_object *obj = intel_fb->obj;
11364
11365 if (mmio_flip->req) {
11366 WARN_ON(__i915_wait_request(mmio_flip->req,
11367 mmio_flip->crtc->reset_counter,
11368 false, NULL,
11369 &mmio_flip->i915->rps.mmioflips));
11370 i915_gem_request_unreference__unlocked(mmio_flip->req);
11371 }
11372
11373 /* For framebuffer backed by dmabuf, wait for fence */
11374 if (obj->base.dma_buf)
11375 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11376 false, false,
11377 MAX_SCHEDULE_TIMEOUT) < 0);
11378
11379 intel_do_mmio_flip(mmio_flip);
11380 kfree(mmio_flip);
11381 }
11382
11383 static int intel_queue_mmio_flip(struct drm_device *dev,
11384 struct drm_crtc *crtc,
11385 struct drm_i915_gem_object *obj)
11386 {
11387 struct intel_mmio_flip *mmio_flip;
11388
11389 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11390 if (mmio_flip == NULL)
11391 return -ENOMEM;
11392
11393 mmio_flip->i915 = to_i915(dev);
11394 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11395 mmio_flip->crtc = to_intel_crtc(crtc);
11396 mmio_flip->rotation = crtc->primary->state->rotation;
11397
11398 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11399 schedule_work(&mmio_flip->work);
11400
11401 return 0;
11402 }
11403
11404 static int intel_default_queue_flip(struct drm_device *dev,
11405 struct drm_crtc *crtc,
11406 struct drm_framebuffer *fb,
11407 struct drm_i915_gem_object *obj,
11408 struct drm_i915_gem_request *req,
11409 uint32_t flags)
11410 {
11411 return -ENODEV;
11412 }
11413
11414 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11415 struct drm_crtc *crtc)
11416 {
11417 struct drm_i915_private *dev_priv = dev->dev_private;
11418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11419 struct intel_unpin_work *work = intel_crtc->unpin_work;
11420 u32 addr;
11421
11422 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11423 return true;
11424
11425 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11426 return false;
11427
11428 if (!work->enable_stall_check)
11429 return false;
11430
11431 if (work->flip_ready_vblank == 0) {
11432 if (work->flip_queued_req &&
11433 !i915_gem_request_completed(work->flip_queued_req, true))
11434 return false;
11435
11436 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11437 }
11438
11439 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11440 return false;
11441
11442 /* Potential stall - if we see that the flip has happened,
11443 * assume a missed interrupt. */
11444 if (INTEL_INFO(dev)->gen >= 4)
11445 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11446 else
11447 addr = I915_READ(DSPADDR(intel_crtc->plane));
11448
11449 /* There is a potential issue here with a false positive after a flip
11450 * to the same address. We could address this by checking for a
11451 * non-incrementing frame counter.
11452 */
11453 return addr == work->gtt_offset;
11454 }
11455
11456 void intel_check_page_flip(struct drm_device *dev, int pipe)
11457 {
11458 struct drm_i915_private *dev_priv = dev->dev_private;
11459 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11461 struct intel_unpin_work *work;
11462
11463 WARN_ON(!in_interrupt());
11464
11465 if (crtc == NULL)
11466 return;
11467
11468 spin_lock(&dev->event_lock);
11469 work = intel_crtc->unpin_work;
11470 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11471 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11472 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11473 page_flip_completed(intel_crtc);
11474 work = NULL;
11475 }
11476 if (work != NULL &&
11477 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11478 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11479 spin_unlock(&dev->event_lock);
11480 }
11481
11482 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11483 struct drm_framebuffer *fb,
11484 struct drm_pending_vblank_event *event,
11485 uint32_t page_flip_flags)
11486 {
11487 struct drm_device *dev = crtc->dev;
11488 struct drm_i915_private *dev_priv = dev->dev_private;
11489 struct drm_framebuffer *old_fb = crtc->primary->fb;
11490 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11492 struct drm_plane *primary = crtc->primary;
11493 enum pipe pipe = intel_crtc->pipe;
11494 struct intel_unpin_work *work;
11495 struct intel_engine_cs *engine;
11496 bool mmio_flip;
11497 struct drm_i915_gem_request *request = NULL;
11498 int ret;
11499
11500 /*
11501 * drm_mode_page_flip_ioctl() should already catch this, but double
11502 * check to be safe. In the future we may enable pageflipping from
11503 * a disabled primary plane.
11504 */
11505 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11506 return -EBUSY;
11507
11508 /* Can't change pixel format via MI display flips. */
11509 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11510 return -EINVAL;
11511
11512 /*
11513 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11514 * Note that pitch changes could also affect these register.
11515 */
11516 if (INTEL_INFO(dev)->gen > 3 &&
11517 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11518 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11519 return -EINVAL;
11520
11521 if (i915_terminally_wedged(&dev_priv->gpu_error))
11522 goto out_hang;
11523
11524 work = kzalloc(sizeof(*work), GFP_KERNEL);
11525 if (work == NULL)
11526 return -ENOMEM;
11527
11528 work->event = event;
11529 work->crtc = crtc;
11530 work->old_fb = old_fb;
11531 INIT_WORK(&work->work, intel_unpin_work_fn);
11532
11533 ret = drm_crtc_vblank_get(crtc);
11534 if (ret)
11535 goto free_work;
11536
11537 /* We borrow the event spin lock for protecting unpin_work */
11538 spin_lock_irq(&dev->event_lock);
11539 if (intel_crtc->unpin_work) {
11540 /* Before declaring the flip queue wedged, check if
11541 * the hardware completed the operation behind our backs.
11542 */
11543 if (__intel_pageflip_stall_check(dev, crtc)) {
11544 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11545 page_flip_completed(intel_crtc);
11546 } else {
11547 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11548 spin_unlock_irq(&dev->event_lock);
11549
11550 drm_crtc_vblank_put(crtc);
11551 kfree(work);
11552 return -EBUSY;
11553 }
11554 }
11555 intel_crtc->unpin_work = work;
11556 spin_unlock_irq(&dev->event_lock);
11557
11558 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11559 flush_workqueue(dev_priv->wq);
11560
11561 /* Reference the objects for the scheduled work. */
11562 drm_framebuffer_reference(work->old_fb);
11563 drm_gem_object_reference(&obj->base);
11564
11565 crtc->primary->fb = fb;
11566 update_state_fb(crtc->primary);
11567 intel_fbc_pre_update(intel_crtc);
11568
11569 work->pending_flip_obj = obj;
11570
11571 ret = i915_mutex_lock_interruptible(dev);
11572 if (ret)
11573 goto cleanup;
11574
11575 atomic_inc(&intel_crtc->unpin_work_count);
11576 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11577
11578 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11579 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11580
11581 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11582 engine = &dev_priv->engine[BCS];
11583 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11584 /* vlv: DISPLAY_FLIP fails to change tiling */
11585 engine = NULL;
11586 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11587 engine = &dev_priv->engine[BCS];
11588 } else if (INTEL_INFO(dev)->gen >= 7) {
11589 engine = i915_gem_request_get_engine(obj->last_write_req);
11590 if (engine == NULL || engine->id != RCS)
11591 engine = &dev_priv->engine[BCS];
11592 } else {
11593 engine = &dev_priv->engine[RCS];
11594 }
11595
11596 mmio_flip = use_mmio_flip(engine, obj);
11597
11598 /* When using CS flips, we want to emit semaphores between rings.
11599 * However, when using mmio flips we will create a task to do the
11600 * synchronisation, so all we want here is to pin the framebuffer
11601 * into the display plane and skip any waits.
11602 */
11603 if (!mmio_flip) {
11604 ret = i915_gem_object_sync(obj, engine, &request);
11605 if (ret)
11606 goto cleanup_pending;
11607 }
11608
11609 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11610 if (ret)
11611 goto cleanup_pending;
11612
11613 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11614 obj, 0);
11615 work->gtt_offset += intel_crtc->dspaddr_offset;
11616
11617 if (mmio_flip) {
11618 ret = intel_queue_mmio_flip(dev, crtc, obj);
11619 if (ret)
11620 goto cleanup_unpin;
11621
11622 i915_gem_request_assign(&work->flip_queued_req,
11623 obj->last_write_req);
11624 } else {
11625 if (!request) {
11626 request = i915_gem_request_alloc(engine, NULL);
11627 if (IS_ERR(request)) {
11628 ret = PTR_ERR(request);
11629 goto cleanup_unpin;
11630 }
11631 }
11632
11633 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11634 page_flip_flags);
11635 if (ret)
11636 goto cleanup_unpin;
11637
11638 i915_gem_request_assign(&work->flip_queued_req, request);
11639 }
11640
11641 if (request)
11642 i915_add_request_no_flush(request);
11643
11644 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11645 work->enable_stall_check = true;
11646
11647 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11648 to_intel_plane(primary)->frontbuffer_bit);
11649 mutex_unlock(&dev->struct_mutex);
11650
11651 intel_frontbuffer_flip_prepare(dev,
11652 to_intel_plane(primary)->frontbuffer_bit);
11653
11654 trace_i915_flip_request(intel_crtc->plane, obj);
11655
11656 return 0;
11657
11658 cleanup_unpin:
11659 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11660 cleanup_pending:
11661 if (!IS_ERR_OR_NULL(request))
11662 i915_gem_request_cancel(request);
11663 atomic_dec(&intel_crtc->unpin_work_count);
11664 mutex_unlock(&dev->struct_mutex);
11665 cleanup:
11666 crtc->primary->fb = old_fb;
11667 update_state_fb(crtc->primary);
11668
11669 drm_gem_object_unreference_unlocked(&obj->base);
11670 drm_framebuffer_unreference(work->old_fb);
11671
11672 spin_lock_irq(&dev->event_lock);
11673 intel_crtc->unpin_work = NULL;
11674 spin_unlock_irq(&dev->event_lock);
11675
11676 drm_crtc_vblank_put(crtc);
11677 free_work:
11678 kfree(work);
11679
11680 if (ret == -EIO) {
11681 struct drm_atomic_state *state;
11682 struct drm_plane_state *plane_state;
11683
11684 out_hang:
11685 state = drm_atomic_state_alloc(dev);
11686 if (!state)
11687 return -ENOMEM;
11688 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11689
11690 retry:
11691 plane_state = drm_atomic_get_plane_state(state, primary);
11692 ret = PTR_ERR_OR_ZERO(plane_state);
11693 if (!ret) {
11694 drm_atomic_set_fb_for_plane(plane_state, fb);
11695
11696 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11697 if (!ret)
11698 ret = drm_atomic_commit(state);
11699 }
11700
11701 if (ret == -EDEADLK) {
11702 drm_modeset_backoff(state->acquire_ctx);
11703 drm_atomic_state_clear(state);
11704 goto retry;
11705 }
11706
11707 if (ret)
11708 drm_atomic_state_free(state);
11709
11710 if (ret == 0 && event) {
11711 spin_lock_irq(&dev->event_lock);
11712 drm_send_vblank_event(dev, pipe, event);
11713 spin_unlock_irq(&dev->event_lock);
11714 }
11715 }
11716 return ret;
11717 }
11718
11719
11720 /**
11721 * intel_wm_need_update - Check whether watermarks need updating
11722 * @plane: drm plane
11723 * @state: new plane state
11724 *
11725 * Check current plane state versus the new one to determine whether
11726 * watermarks need to be recalculated.
11727 *
11728 * Returns true or false.
11729 */
11730 static bool intel_wm_need_update(struct drm_plane *plane,
11731 struct drm_plane_state *state)
11732 {
11733 struct intel_plane_state *new = to_intel_plane_state(state);
11734 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11735
11736 /* Update watermarks on tiling or size changes. */
11737 if (new->visible != cur->visible)
11738 return true;
11739
11740 if (!cur->base.fb || !new->base.fb)
11741 return false;
11742
11743 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11744 cur->base.rotation != new->base.rotation ||
11745 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11746 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11747 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11748 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11749 return true;
11750
11751 return false;
11752 }
11753
11754 static bool needs_scaling(struct intel_plane_state *state)
11755 {
11756 int src_w = drm_rect_width(&state->src) >> 16;
11757 int src_h = drm_rect_height(&state->src) >> 16;
11758 int dst_w = drm_rect_width(&state->dst);
11759 int dst_h = drm_rect_height(&state->dst);
11760
11761 return (src_w != dst_w || src_h != dst_h);
11762 }
11763
11764 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11765 struct drm_plane_state *plane_state)
11766 {
11767 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11768 struct drm_crtc *crtc = crtc_state->crtc;
11769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11770 struct drm_plane *plane = plane_state->plane;
11771 struct drm_device *dev = crtc->dev;
11772 struct drm_i915_private *dev_priv = to_i915(dev);
11773 struct intel_plane_state *old_plane_state =
11774 to_intel_plane_state(plane->state);
11775 int idx = intel_crtc->base.base.id, ret;
11776 bool mode_changed = needs_modeset(crtc_state);
11777 bool was_crtc_enabled = crtc->state->active;
11778 bool is_crtc_enabled = crtc_state->active;
11779 bool turn_off, turn_on, visible, was_visible;
11780 struct drm_framebuffer *fb = plane_state->fb;
11781
11782 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11783 plane->type != DRM_PLANE_TYPE_CURSOR) {
11784 ret = skl_update_scaler_plane(
11785 to_intel_crtc_state(crtc_state),
11786 to_intel_plane_state(plane_state));
11787 if (ret)
11788 return ret;
11789 }
11790
11791 was_visible = old_plane_state->visible;
11792 visible = to_intel_plane_state(plane_state)->visible;
11793
11794 if (!was_crtc_enabled && WARN_ON(was_visible))
11795 was_visible = false;
11796
11797 /*
11798 * Visibility is calculated as if the crtc was on, but
11799 * after scaler setup everything depends on it being off
11800 * when the crtc isn't active.
11801 */
11802 if (!is_crtc_enabled)
11803 to_intel_plane_state(plane_state)->visible = visible = false;
11804
11805 if (!was_visible && !visible)
11806 return 0;
11807
11808 if (fb != old_plane_state->base.fb)
11809 pipe_config->fb_changed = true;
11810
11811 turn_off = was_visible && (!visible || mode_changed);
11812 turn_on = visible && (!was_visible || mode_changed);
11813
11814 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11815 plane->base.id, fb ? fb->base.id : -1);
11816
11817 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11818 plane->base.id, was_visible, visible,
11819 turn_off, turn_on, mode_changed);
11820
11821 if (turn_on) {
11822 pipe_config->update_wm_pre = true;
11823
11824 /* must disable cxsr around plane enable/disable */
11825 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11826 pipe_config->disable_cxsr = true;
11827 } else if (turn_off) {
11828 pipe_config->update_wm_post = true;
11829
11830 /* must disable cxsr around plane enable/disable */
11831 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11832 pipe_config->disable_cxsr = true;
11833 } else if (intel_wm_need_update(plane, plane_state)) {
11834 /* FIXME bollocks */
11835 pipe_config->update_wm_pre = true;
11836 pipe_config->update_wm_post = true;
11837 }
11838
11839 /* Pre-gen9 platforms need two-step watermark updates */
11840 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11841 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11842 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11843
11844 if (visible || was_visible)
11845 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11846
11847 /*
11848 * WaCxSRDisabledForSpriteScaling:ivb
11849 *
11850 * cstate->update_wm was already set above, so this flag will
11851 * take effect when we commit and program watermarks.
11852 */
11853 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11854 needs_scaling(to_intel_plane_state(plane_state)) &&
11855 !needs_scaling(old_plane_state))
11856 pipe_config->disable_lp_wm = true;
11857
11858 return 0;
11859 }
11860
11861 static bool encoders_cloneable(const struct intel_encoder *a,
11862 const struct intel_encoder *b)
11863 {
11864 /* masks could be asymmetric, so check both ways */
11865 return a == b || (a->cloneable & (1 << b->type) &&
11866 b->cloneable & (1 << a->type));
11867 }
11868
11869 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11870 struct intel_crtc *crtc,
11871 struct intel_encoder *encoder)
11872 {
11873 struct intel_encoder *source_encoder;
11874 struct drm_connector *connector;
11875 struct drm_connector_state *connector_state;
11876 int i;
11877
11878 for_each_connector_in_state(state, connector, connector_state, i) {
11879 if (connector_state->crtc != &crtc->base)
11880 continue;
11881
11882 source_encoder =
11883 to_intel_encoder(connector_state->best_encoder);
11884 if (!encoders_cloneable(encoder, source_encoder))
11885 return false;
11886 }
11887
11888 return true;
11889 }
11890
11891 static bool check_encoder_cloning(struct drm_atomic_state *state,
11892 struct intel_crtc *crtc)
11893 {
11894 struct intel_encoder *encoder;
11895 struct drm_connector *connector;
11896 struct drm_connector_state *connector_state;
11897 int i;
11898
11899 for_each_connector_in_state(state, connector, connector_state, i) {
11900 if (connector_state->crtc != &crtc->base)
11901 continue;
11902
11903 encoder = to_intel_encoder(connector_state->best_encoder);
11904 if (!check_single_encoder_cloning(state, crtc, encoder))
11905 return false;
11906 }
11907
11908 return true;
11909 }
11910
11911 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11912 struct drm_crtc_state *crtc_state)
11913 {
11914 struct drm_device *dev = crtc->dev;
11915 struct drm_i915_private *dev_priv = dev->dev_private;
11916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11917 struct intel_crtc_state *pipe_config =
11918 to_intel_crtc_state(crtc_state);
11919 struct drm_atomic_state *state = crtc_state->state;
11920 int ret;
11921 bool mode_changed = needs_modeset(crtc_state);
11922
11923 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11924 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11925 return -EINVAL;
11926 }
11927
11928 if (mode_changed && !crtc_state->active)
11929 pipe_config->update_wm_post = true;
11930
11931 if (mode_changed && crtc_state->enable &&
11932 dev_priv->display.crtc_compute_clock &&
11933 !WARN_ON(pipe_config->shared_dpll)) {
11934 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11935 pipe_config);
11936 if (ret)
11937 return ret;
11938 }
11939
11940 if (crtc_state->color_mgmt_changed) {
11941 ret = intel_color_check(crtc, crtc_state);
11942 if (ret)
11943 return ret;
11944 }
11945
11946 ret = 0;
11947 if (dev_priv->display.compute_pipe_wm) {
11948 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11949 if (ret) {
11950 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11951 return ret;
11952 }
11953 }
11954
11955 if (dev_priv->display.compute_intermediate_wm &&
11956 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11957 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11958 return 0;
11959
11960 /*
11961 * Calculate 'intermediate' watermarks that satisfy both the
11962 * old state and the new state. We can program these
11963 * immediately.
11964 */
11965 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11966 intel_crtc,
11967 pipe_config);
11968 if (ret) {
11969 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11970 return ret;
11971 }
11972 }
11973
11974 if (INTEL_INFO(dev)->gen >= 9) {
11975 if (mode_changed)
11976 ret = skl_update_scaler_crtc(pipe_config);
11977
11978 if (!ret)
11979 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11980 pipe_config);
11981 }
11982
11983 return ret;
11984 }
11985
11986 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11987 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11988 .atomic_begin = intel_begin_crtc_commit,
11989 .atomic_flush = intel_finish_crtc_commit,
11990 .atomic_check = intel_crtc_atomic_check,
11991 };
11992
11993 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11994 {
11995 struct intel_connector *connector;
11996
11997 for_each_intel_connector(dev, connector) {
11998 if (connector->base.encoder) {
11999 connector->base.state->best_encoder =
12000 connector->base.encoder;
12001 connector->base.state->crtc =
12002 connector->base.encoder->crtc;
12003 } else {
12004 connector->base.state->best_encoder = NULL;
12005 connector->base.state->crtc = NULL;
12006 }
12007 }
12008 }
12009
12010 static void
12011 connected_sink_compute_bpp(struct intel_connector *connector,
12012 struct intel_crtc_state *pipe_config)
12013 {
12014 int bpp = pipe_config->pipe_bpp;
12015
12016 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12017 connector->base.base.id,
12018 connector->base.name);
12019
12020 /* Don't use an invalid EDID bpc value */
12021 if (connector->base.display_info.bpc &&
12022 connector->base.display_info.bpc * 3 < bpp) {
12023 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12024 bpp, connector->base.display_info.bpc*3);
12025 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12026 }
12027
12028 /* Clamp bpp to default limit on screens without EDID 1.4 */
12029 if (connector->base.display_info.bpc == 0) {
12030 int type = connector->base.connector_type;
12031 int clamp_bpp = 24;
12032
12033 /* Fall back to 18 bpp when DP sink capability is unknown. */
12034 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12035 type == DRM_MODE_CONNECTOR_eDP)
12036 clamp_bpp = 18;
12037
12038 if (bpp > clamp_bpp) {
12039 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12040 bpp, clamp_bpp);
12041 pipe_config->pipe_bpp = clamp_bpp;
12042 }
12043 }
12044 }
12045
12046 static int
12047 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12048 struct intel_crtc_state *pipe_config)
12049 {
12050 struct drm_device *dev = crtc->base.dev;
12051 struct drm_atomic_state *state;
12052 struct drm_connector *connector;
12053 struct drm_connector_state *connector_state;
12054 int bpp, i;
12055
12056 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12057 bpp = 10*3;
12058 else if (INTEL_INFO(dev)->gen >= 5)
12059 bpp = 12*3;
12060 else
12061 bpp = 8*3;
12062
12063
12064 pipe_config->pipe_bpp = bpp;
12065
12066 state = pipe_config->base.state;
12067
12068 /* Clamp display bpp to EDID value */
12069 for_each_connector_in_state(state, connector, connector_state, i) {
12070 if (connector_state->crtc != &crtc->base)
12071 continue;
12072
12073 connected_sink_compute_bpp(to_intel_connector(connector),
12074 pipe_config);
12075 }
12076
12077 return bpp;
12078 }
12079
12080 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12081 {
12082 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12083 "type: 0x%x flags: 0x%x\n",
12084 mode->crtc_clock,
12085 mode->crtc_hdisplay, mode->crtc_hsync_start,
12086 mode->crtc_hsync_end, mode->crtc_htotal,
12087 mode->crtc_vdisplay, mode->crtc_vsync_start,
12088 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12089 }
12090
12091 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12092 struct intel_crtc_state *pipe_config,
12093 const char *context)
12094 {
12095 struct drm_device *dev = crtc->base.dev;
12096 struct drm_plane *plane;
12097 struct intel_plane *intel_plane;
12098 struct intel_plane_state *state;
12099 struct drm_framebuffer *fb;
12100
12101 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12102 context, pipe_config, pipe_name(crtc->pipe));
12103
12104 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12105 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12106 pipe_config->pipe_bpp, pipe_config->dither);
12107 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12108 pipe_config->has_pch_encoder,
12109 pipe_config->fdi_lanes,
12110 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12111 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12112 pipe_config->fdi_m_n.tu);
12113 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12114 pipe_config->has_dp_encoder,
12115 pipe_config->lane_count,
12116 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12117 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12118 pipe_config->dp_m_n.tu);
12119
12120 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12121 pipe_config->has_dp_encoder,
12122 pipe_config->lane_count,
12123 pipe_config->dp_m2_n2.gmch_m,
12124 pipe_config->dp_m2_n2.gmch_n,
12125 pipe_config->dp_m2_n2.link_m,
12126 pipe_config->dp_m2_n2.link_n,
12127 pipe_config->dp_m2_n2.tu);
12128
12129 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12130 pipe_config->has_audio,
12131 pipe_config->has_infoframe);
12132
12133 DRM_DEBUG_KMS("requested mode:\n");
12134 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12135 DRM_DEBUG_KMS("adjusted mode:\n");
12136 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12137 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12138 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12139 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12140 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12141 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12142 crtc->num_scalers,
12143 pipe_config->scaler_state.scaler_users,
12144 pipe_config->scaler_state.scaler_id);
12145 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12146 pipe_config->gmch_pfit.control,
12147 pipe_config->gmch_pfit.pgm_ratios,
12148 pipe_config->gmch_pfit.lvds_border_bits);
12149 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12150 pipe_config->pch_pfit.pos,
12151 pipe_config->pch_pfit.size,
12152 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12153 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12154 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12155
12156 if (IS_BROXTON(dev)) {
12157 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12158 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12159 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12160 pipe_config->ddi_pll_sel,
12161 pipe_config->dpll_hw_state.ebb0,
12162 pipe_config->dpll_hw_state.ebb4,
12163 pipe_config->dpll_hw_state.pll0,
12164 pipe_config->dpll_hw_state.pll1,
12165 pipe_config->dpll_hw_state.pll2,
12166 pipe_config->dpll_hw_state.pll3,
12167 pipe_config->dpll_hw_state.pll6,
12168 pipe_config->dpll_hw_state.pll8,
12169 pipe_config->dpll_hw_state.pll9,
12170 pipe_config->dpll_hw_state.pll10,
12171 pipe_config->dpll_hw_state.pcsdw12);
12172 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12173 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12174 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12175 pipe_config->ddi_pll_sel,
12176 pipe_config->dpll_hw_state.ctrl1,
12177 pipe_config->dpll_hw_state.cfgcr1,
12178 pipe_config->dpll_hw_state.cfgcr2);
12179 } else if (HAS_DDI(dev)) {
12180 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12181 pipe_config->ddi_pll_sel,
12182 pipe_config->dpll_hw_state.wrpll,
12183 pipe_config->dpll_hw_state.spll);
12184 } else {
12185 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12186 "fp0: 0x%x, fp1: 0x%x\n",
12187 pipe_config->dpll_hw_state.dpll,
12188 pipe_config->dpll_hw_state.dpll_md,
12189 pipe_config->dpll_hw_state.fp0,
12190 pipe_config->dpll_hw_state.fp1);
12191 }
12192
12193 DRM_DEBUG_KMS("planes on this crtc\n");
12194 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12195 intel_plane = to_intel_plane(plane);
12196 if (intel_plane->pipe != crtc->pipe)
12197 continue;
12198
12199 state = to_intel_plane_state(plane->state);
12200 fb = state->base.fb;
12201 if (!fb) {
12202 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12203 "disabled, scaler_id = %d\n",
12204 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12205 plane->base.id, intel_plane->pipe,
12206 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12207 drm_plane_index(plane), state->scaler_id);
12208 continue;
12209 }
12210
12211 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12212 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12213 plane->base.id, intel_plane->pipe,
12214 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12215 drm_plane_index(plane));
12216 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12217 fb->base.id, fb->width, fb->height, fb->pixel_format);
12218 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12219 state->scaler_id,
12220 state->src.x1 >> 16, state->src.y1 >> 16,
12221 drm_rect_width(&state->src) >> 16,
12222 drm_rect_height(&state->src) >> 16,
12223 state->dst.x1, state->dst.y1,
12224 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12225 }
12226 }
12227
12228 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12229 {
12230 struct drm_device *dev = state->dev;
12231 struct drm_connector *connector;
12232 unsigned int used_ports = 0;
12233
12234 /*
12235 * Walk the connector list instead of the encoder
12236 * list to detect the problem on ddi platforms
12237 * where there's just one encoder per digital port.
12238 */
12239 drm_for_each_connector(connector, dev) {
12240 struct drm_connector_state *connector_state;
12241 struct intel_encoder *encoder;
12242
12243 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12244 if (!connector_state)
12245 connector_state = connector->state;
12246
12247 if (!connector_state->best_encoder)
12248 continue;
12249
12250 encoder = to_intel_encoder(connector_state->best_encoder);
12251
12252 WARN_ON(!connector_state->crtc);
12253
12254 switch (encoder->type) {
12255 unsigned int port_mask;
12256 case INTEL_OUTPUT_UNKNOWN:
12257 if (WARN_ON(!HAS_DDI(dev)))
12258 break;
12259 case INTEL_OUTPUT_DISPLAYPORT:
12260 case INTEL_OUTPUT_HDMI:
12261 case INTEL_OUTPUT_EDP:
12262 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12263
12264 /* the same port mustn't appear more than once */
12265 if (used_ports & port_mask)
12266 return false;
12267
12268 used_ports |= port_mask;
12269 default:
12270 break;
12271 }
12272 }
12273
12274 return true;
12275 }
12276
12277 static void
12278 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12279 {
12280 struct drm_crtc_state tmp_state;
12281 struct intel_crtc_scaler_state scaler_state;
12282 struct intel_dpll_hw_state dpll_hw_state;
12283 struct intel_shared_dpll *shared_dpll;
12284 uint32_t ddi_pll_sel;
12285 bool force_thru;
12286
12287 /* FIXME: before the switch to atomic started, a new pipe_config was
12288 * kzalloc'd. Code that depends on any field being zero should be
12289 * fixed, so that the crtc_state can be safely duplicated. For now,
12290 * only fields that are know to not cause problems are preserved. */
12291
12292 tmp_state = crtc_state->base;
12293 scaler_state = crtc_state->scaler_state;
12294 shared_dpll = crtc_state->shared_dpll;
12295 dpll_hw_state = crtc_state->dpll_hw_state;
12296 ddi_pll_sel = crtc_state->ddi_pll_sel;
12297 force_thru = crtc_state->pch_pfit.force_thru;
12298
12299 memset(crtc_state, 0, sizeof *crtc_state);
12300
12301 crtc_state->base = tmp_state;
12302 crtc_state->scaler_state = scaler_state;
12303 crtc_state->shared_dpll = shared_dpll;
12304 crtc_state->dpll_hw_state = dpll_hw_state;
12305 crtc_state->ddi_pll_sel = ddi_pll_sel;
12306 crtc_state->pch_pfit.force_thru = force_thru;
12307 }
12308
12309 static int
12310 intel_modeset_pipe_config(struct drm_crtc *crtc,
12311 struct intel_crtc_state *pipe_config)
12312 {
12313 struct drm_atomic_state *state = pipe_config->base.state;
12314 struct intel_encoder *encoder;
12315 struct drm_connector *connector;
12316 struct drm_connector_state *connector_state;
12317 int base_bpp, ret = -EINVAL;
12318 int i;
12319 bool retry = true;
12320
12321 clear_intel_crtc_state(pipe_config);
12322
12323 pipe_config->cpu_transcoder =
12324 (enum transcoder) to_intel_crtc(crtc)->pipe;
12325
12326 /*
12327 * Sanitize sync polarity flags based on requested ones. If neither
12328 * positive or negative polarity is requested, treat this as meaning
12329 * negative polarity.
12330 */
12331 if (!(pipe_config->base.adjusted_mode.flags &
12332 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12333 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12334
12335 if (!(pipe_config->base.adjusted_mode.flags &
12336 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12337 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12338
12339 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12340 pipe_config);
12341 if (base_bpp < 0)
12342 goto fail;
12343
12344 /*
12345 * Determine the real pipe dimensions. Note that stereo modes can
12346 * increase the actual pipe size due to the frame doubling and
12347 * insertion of additional space for blanks between the frame. This
12348 * is stored in the crtc timings. We use the requested mode to do this
12349 * computation to clearly distinguish it from the adjusted mode, which
12350 * can be changed by the connectors in the below retry loop.
12351 */
12352 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12353 &pipe_config->pipe_src_w,
12354 &pipe_config->pipe_src_h);
12355
12356 encoder_retry:
12357 /* Ensure the port clock defaults are reset when retrying. */
12358 pipe_config->port_clock = 0;
12359 pipe_config->pixel_multiplier = 1;
12360
12361 /* Fill in default crtc timings, allow encoders to overwrite them. */
12362 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12363 CRTC_STEREO_DOUBLE);
12364
12365 /* Pass our mode to the connectors and the CRTC to give them a chance to
12366 * adjust it according to limitations or connector properties, and also
12367 * a chance to reject the mode entirely.
12368 */
12369 for_each_connector_in_state(state, connector, connector_state, i) {
12370 if (connector_state->crtc != crtc)
12371 continue;
12372
12373 encoder = to_intel_encoder(connector_state->best_encoder);
12374
12375 if (!(encoder->compute_config(encoder, pipe_config))) {
12376 DRM_DEBUG_KMS("Encoder config failure\n");
12377 goto fail;
12378 }
12379 }
12380
12381 /* Set default port clock if not overwritten by the encoder. Needs to be
12382 * done afterwards in case the encoder adjusts the mode. */
12383 if (!pipe_config->port_clock)
12384 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12385 * pipe_config->pixel_multiplier;
12386
12387 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12388 if (ret < 0) {
12389 DRM_DEBUG_KMS("CRTC fixup failed\n");
12390 goto fail;
12391 }
12392
12393 if (ret == RETRY) {
12394 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12395 ret = -EINVAL;
12396 goto fail;
12397 }
12398
12399 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12400 retry = false;
12401 goto encoder_retry;
12402 }
12403
12404 /* Dithering seems to not pass-through bits correctly when it should, so
12405 * only enable it on 6bpc panels. */
12406 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12407 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12408 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12409
12410 fail:
12411 return ret;
12412 }
12413
12414 static void
12415 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12416 {
12417 struct drm_crtc *crtc;
12418 struct drm_crtc_state *crtc_state;
12419 int i;
12420
12421 /* Double check state. */
12422 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12423 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12424
12425 /* Update hwmode for vblank functions */
12426 if (crtc->state->active)
12427 crtc->hwmode = crtc->state->adjusted_mode;
12428 else
12429 crtc->hwmode.crtc_clock = 0;
12430
12431 /*
12432 * Update legacy state to satisfy fbc code. This can
12433 * be removed when fbc uses the atomic state.
12434 */
12435 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12436 struct drm_plane_state *plane_state = crtc->primary->state;
12437
12438 crtc->primary->fb = plane_state->fb;
12439 crtc->x = plane_state->src_x >> 16;
12440 crtc->y = plane_state->src_y >> 16;
12441 }
12442 }
12443 }
12444
12445 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12446 {
12447 int diff;
12448
12449 if (clock1 == clock2)
12450 return true;
12451
12452 if (!clock1 || !clock2)
12453 return false;
12454
12455 diff = abs(clock1 - clock2);
12456
12457 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12458 return true;
12459
12460 return false;
12461 }
12462
12463 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12464 list_for_each_entry((intel_crtc), \
12465 &(dev)->mode_config.crtc_list, \
12466 base.head) \
12467 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12468
12469 static bool
12470 intel_compare_m_n(unsigned int m, unsigned int n,
12471 unsigned int m2, unsigned int n2,
12472 bool exact)
12473 {
12474 if (m == m2 && n == n2)
12475 return true;
12476
12477 if (exact || !m || !n || !m2 || !n2)
12478 return false;
12479
12480 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12481
12482 if (n > n2) {
12483 while (n > n2) {
12484 m2 <<= 1;
12485 n2 <<= 1;
12486 }
12487 } else if (n < n2) {
12488 while (n < n2) {
12489 m <<= 1;
12490 n <<= 1;
12491 }
12492 }
12493
12494 if (n != n2)
12495 return false;
12496
12497 return intel_fuzzy_clock_check(m, m2);
12498 }
12499
12500 static bool
12501 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12502 struct intel_link_m_n *m2_n2,
12503 bool adjust)
12504 {
12505 if (m_n->tu == m2_n2->tu &&
12506 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12507 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12508 intel_compare_m_n(m_n->link_m, m_n->link_n,
12509 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12510 if (adjust)
12511 *m2_n2 = *m_n;
12512
12513 return true;
12514 }
12515
12516 return false;
12517 }
12518
12519 static bool
12520 intel_pipe_config_compare(struct drm_device *dev,
12521 struct intel_crtc_state *current_config,
12522 struct intel_crtc_state *pipe_config,
12523 bool adjust)
12524 {
12525 bool ret = true;
12526
12527 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12528 do { \
12529 if (!adjust) \
12530 DRM_ERROR(fmt, ##__VA_ARGS__); \
12531 else \
12532 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12533 } while (0)
12534
12535 #define PIPE_CONF_CHECK_X(name) \
12536 if (current_config->name != pipe_config->name) { \
12537 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12538 "(expected 0x%08x, found 0x%08x)\n", \
12539 current_config->name, \
12540 pipe_config->name); \
12541 ret = false; \
12542 }
12543
12544 #define PIPE_CONF_CHECK_I(name) \
12545 if (current_config->name != pipe_config->name) { \
12546 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12547 "(expected %i, found %i)\n", \
12548 current_config->name, \
12549 pipe_config->name); \
12550 ret = false; \
12551 }
12552
12553 #define PIPE_CONF_CHECK_P(name) \
12554 if (current_config->name != pipe_config->name) { \
12555 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12556 "(expected %p, found %p)\n", \
12557 current_config->name, \
12558 pipe_config->name); \
12559 ret = false; \
12560 }
12561
12562 #define PIPE_CONF_CHECK_M_N(name) \
12563 if (!intel_compare_link_m_n(&current_config->name, \
12564 &pipe_config->name,\
12565 adjust)) { \
12566 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12567 "(expected tu %i gmch %i/%i link %i/%i, " \
12568 "found tu %i, gmch %i/%i link %i/%i)\n", \
12569 current_config->name.tu, \
12570 current_config->name.gmch_m, \
12571 current_config->name.gmch_n, \
12572 current_config->name.link_m, \
12573 current_config->name.link_n, \
12574 pipe_config->name.tu, \
12575 pipe_config->name.gmch_m, \
12576 pipe_config->name.gmch_n, \
12577 pipe_config->name.link_m, \
12578 pipe_config->name.link_n); \
12579 ret = false; \
12580 }
12581
12582 /* This is required for BDW+ where there is only one set of registers for
12583 * switching between high and low RR.
12584 * This macro can be used whenever a comparison has to be made between one
12585 * hw state and multiple sw state variables.
12586 */
12587 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12588 if (!intel_compare_link_m_n(&current_config->name, \
12589 &pipe_config->name, adjust) && \
12590 !intel_compare_link_m_n(&current_config->alt_name, \
12591 &pipe_config->name, adjust)) { \
12592 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12593 "(expected tu %i gmch %i/%i link %i/%i, " \
12594 "or tu %i gmch %i/%i link %i/%i, " \
12595 "found tu %i, gmch %i/%i link %i/%i)\n", \
12596 current_config->name.tu, \
12597 current_config->name.gmch_m, \
12598 current_config->name.gmch_n, \
12599 current_config->name.link_m, \
12600 current_config->name.link_n, \
12601 current_config->alt_name.tu, \
12602 current_config->alt_name.gmch_m, \
12603 current_config->alt_name.gmch_n, \
12604 current_config->alt_name.link_m, \
12605 current_config->alt_name.link_n, \
12606 pipe_config->name.tu, \
12607 pipe_config->name.gmch_m, \
12608 pipe_config->name.gmch_n, \
12609 pipe_config->name.link_m, \
12610 pipe_config->name.link_n); \
12611 ret = false; \
12612 }
12613
12614 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12615 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12616 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12617 "(expected %i, found %i)\n", \
12618 current_config->name & (mask), \
12619 pipe_config->name & (mask)); \
12620 ret = false; \
12621 }
12622
12623 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12624 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12625 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12626 "(expected %i, found %i)\n", \
12627 current_config->name, \
12628 pipe_config->name); \
12629 ret = false; \
12630 }
12631
12632 #define PIPE_CONF_QUIRK(quirk) \
12633 ((current_config->quirks | pipe_config->quirks) & (quirk))
12634
12635 PIPE_CONF_CHECK_I(cpu_transcoder);
12636
12637 PIPE_CONF_CHECK_I(has_pch_encoder);
12638 PIPE_CONF_CHECK_I(fdi_lanes);
12639 PIPE_CONF_CHECK_M_N(fdi_m_n);
12640
12641 PIPE_CONF_CHECK_I(has_dp_encoder);
12642 PIPE_CONF_CHECK_I(lane_count);
12643
12644 if (INTEL_INFO(dev)->gen < 8) {
12645 PIPE_CONF_CHECK_M_N(dp_m_n);
12646
12647 if (current_config->has_drrs)
12648 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12649 } else
12650 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12651
12652 PIPE_CONF_CHECK_I(has_dsi_encoder);
12653
12654 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12655 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12656 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12657 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12658 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12659 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12660
12661 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12662 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12663 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12664 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12665 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12666 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12667
12668 PIPE_CONF_CHECK_I(pixel_multiplier);
12669 PIPE_CONF_CHECK_I(has_hdmi_sink);
12670 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12671 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12672 PIPE_CONF_CHECK_I(limited_color_range);
12673 PIPE_CONF_CHECK_I(has_infoframe);
12674
12675 PIPE_CONF_CHECK_I(has_audio);
12676
12677 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12678 DRM_MODE_FLAG_INTERLACE);
12679
12680 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12681 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12682 DRM_MODE_FLAG_PHSYNC);
12683 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12684 DRM_MODE_FLAG_NHSYNC);
12685 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12686 DRM_MODE_FLAG_PVSYNC);
12687 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12688 DRM_MODE_FLAG_NVSYNC);
12689 }
12690
12691 PIPE_CONF_CHECK_X(gmch_pfit.control);
12692 /* pfit ratios are autocomputed by the hw on gen4+ */
12693 if (INTEL_INFO(dev)->gen < 4)
12694 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12695 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12696
12697 if (!adjust) {
12698 PIPE_CONF_CHECK_I(pipe_src_w);
12699 PIPE_CONF_CHECK_I(pipe_src_h);
12700
12701 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12702 if (current_config->pch_pfit.enabled) {
12703 PIPE_CONF_CHECK_X(pch_pfit.pos);
12704 PIPE_CONF_CHECK_X(pch_pfit.size);
12705 }
12706
12707 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12708 }
12709
12710 /* BDW+ don't expose a synchronous way to read the state */
12711 if (IS_HASWELL(dev))
12712 PIPE_CONF_CHECK_I(ips_enabled);
12713
12714 PIPE_CONF_CHECK_I(double_wide);
12715
12716 PIPE_CONF_CHECK_X(ddi_pll_sel);
12717
12718 PIPE_CONF_CHECK_P(shared_dpll);
12719 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12720 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12721 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12722 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12723 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12724 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12725 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12726 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12727 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12728
12729 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12730 PIPE_CONF_CHECK_I(pipe_bpp);
12731
12732 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12733 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12734
12735 #undef PIPE_CONF_CHECK_X
12736 #undef PIPE_CONF_CHECK_I
12737 #undef PIPE_CONF_CHECK_P
12738 #undef PIPE_CONF_CHECK_FLAGS
12739 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12740 #undef PIPE_CONF_QUIRK
12741 #undef INTEL_ERR_OR_DBG_KMS
12742
12743 return ret;
12744 }
12745
12746 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12747 const struct intel_crtc_state *pipe_config)
12748 {
12749 if (pipe_config->has_pch_encoder) {
12750 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12751 &pipe_config->fdi_m_n);
12752 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12753
12754 /*
12755 * FDI already provided one idea for the dotclock.
12756 * Yell if the encoder disagrees.
12757 */
12758 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12759 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12760 fdi_dotclock, dotclock);
12761 }
12762 }
12763
12764 static void verify_wm_state(struct drm_crtc *crtc,
12765 struct drm_crtc_state *new_state)
12766 {
12767 struct drm_device *dev = crtc->dev;
12768 struct drm_i915_private *dev_priv = dev->dev_private;
12769 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12770 struct skl_ddb_entry *hw_entry, *sw_entry;
12771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12772 const enum pipe pipe = intel_crtc->pipe;
12773 int plane;
12774
12775 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12776 return;
12777
12778 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12779 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12780
12781 /* planes */
12782 for_each_plane(dev_priv, pipe, plane) {
12783 hw_entry = &hw_ddb.plane[pipe][plane];
12784 sw_entry = &sw_ddb->plane[pipe][plane];
12785
12786 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12787 continue;
12788
12789 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12790 "(expected (%u,%u), found (%u,%u))\n",
12791 pipe_name(pipe), plane + 1,
12792 sw_entry->start, sw_entry->end,
12793 hw_entry->start, hw_entry->end);
12794 }
12795
12796 /* cursor */
12797 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12798 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12799
12800 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12801 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12802 "(expected (%u,%u), found (%u,%u))\n",
12803 pipe_name(pipe),
12804 sw_entry->start, sw_entry->end,
12805 hw_entry->start, hw_entry->end);
12806 }
12807 }
12808
12809 static void
12810 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12811 {
12812 struct drm_connector *connector;
12813
12814 drm_for_each_connector(connector, dev) {
12815 struct drm_encoder *encoder = connector->encoder;
12816 struct drm_connector_state *state = connector->state;
12817
12818 if (state->crtc != crtc)
12819 continue;
12820
12821 intel_connector_verify_state(to_intel_connector(connector));
12822
12823 I915_STATE_WARN(state->best_encoder != encoder,
12824 "connector's atomic encoder doesn't match legacy encoder\n");
12825 }
12826 }
12827
12828 static void
12829 verify_encoder_state(struct drm_device *dev)
12830 {
12831 struct intel_encoder *encoder;
12832 struct intel_connector *connector;
12833
12834 for_each_intel_encoder(dev, encoder) {
12835 bool enabled = false;
12836 enum pipe pipe;
12837
12838 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12839 encoder->base.base.id,
12840 encoder->base.name);
12841
12842 for_each_intel_connector(dev, connector) {
12843 if (connector->base.state->best_encoder != &encoder->base)
12844 continue;
12845 enabled = true;
12846
12847 I915_STATE_WARN(connector->base.state->crtc !=
12848 encoder->base.crtc,
12849 "connector's crtc doesn't match encoder crtc\n");
12850 }
12851
12852 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12853 "encoder's enabled state mismatch "
12854 "(expected %i, found %i)\n",
12855 !!encoder->base.crtc, enabled);
12856
12857 if (!encoder->base.crtc) {
12858 bool active;
12859
12860 active = encoder->get_hw_state(encoder, &pipe);
12861 I915_STATE_WARN(active,
12862 "encoder detached but still enabled on pipe %c.\n",
12863 pipe_name(pipe));
12864 }
12865 }
12866 }
12867
12868 static void
12869 verify_crtc_state(struct drm_crtc *crtc,
12870 struct drm_crtc_state *old_crtc_state,
12871 struct drm_crtc_state *new_crtc_state)
12872 {
12873 struct drm_device *dev = crtc->dev;
12874 struct drm_i915_private *dev_priv = dev->dev_private;
12875 struct intel_encoder *encoder;
12876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12877 struct intel_crtc_state *pipe_config, *sw_config;
12878 struct drm_atomic_state *old_state;
12879 bool active;
12880
12881 old_state = old_crtc_state->state;
12882 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12883 pipe_config = to_intel_crtc_state(old_crtc_state);
12884 memset(pipe_config, 0, sizeof(*pipe_config));
12885 pipe_config->base.crtc = crtc;
12886 pipe_config->base.state = old_state;
12887
12888 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12889
12890 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12891
12892 /* hw state is inconsistent with the pipe quirk */
12893 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12894 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12895 active = new_crtc_state->active;
12896
12897 I915_STATE_WARN(new_crtc_state->active != active,
12898 "crtc active state doesn't match with hw state "
12899 "(expected %i, found %i)\n", new_crtc_state->active, active);
12900
12901 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12902 "transitional active state does not match atomic hw state "
12903 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12904
12905 for_each_encoder_on_crtc(dev, crtc, encoder) {
12906 enum pipe pipe;
12907
12908 active = encoder->get_hw_state(encoder, &pipe);
12909 I915_STATE_WARN(active != new_crtc_state->active,
12910 "[ENCODER:%i] active %i with crtc active %i\n",
12911 encoder->base.base.id, active, new_crtc_state->active);
12912
12913 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12914 "Encoder connected to wrong pipe %c\n",
12915 pipe_name(pipe));
12916
12917 if (active)
12918 encoder->get_config(encoder, pipe_config);
12919 }
12920
12921 if (!new_crtc_state->active)
12922 return;
12923
12924 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12925
12926 sw_config = to_intel_crtc_state(crtc->state);
12927 if (!intel_pipe_config_compare(dev, sw_config,
12928 pipe_config, false)) {
12929 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12930 intel_dump_pipe_config(intel_crtc, pipe_config,
12931 "[hw state]");
12932 intel_dump_pipe_config(intel_crtc, sw_config,
12933 "[sw state]");
12934 }
12935 }
12936
12937 static void
12938 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12939 struct intel_shared_dpll *pll,
12940 struct drm_crtc *crtc,
12941 struct drm_crtc_state *new_state)
12942 {
12943 struct intel_dpll_hw_state dpll_hw_state;
12944 unsigned crtc_mask;
12945 bool active;
12946
12947 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12948
12949 DRM_DEBUG_KMS("%s\n", pll->name);
12950
12951 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12952
12953 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12954 I915_STATE_WARN(!pll->on && pll->active_mask,
12955 "pll in active use but not on in sw tracking\n");
12956 I915_STATE_WARN(pll->on && !pll->active_mask,
12957 "pll is on but not used by any active crtc\n");
12958 I915_STATE_WARN(pll->on != active,
12959 "pll on state mismatch (expected %i, found %i)\n",
12960 pll->on, active);
12961 }
12962
12963 if (!crtc) {
12964 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12965 "more active pll users than references: %x vs %x\n",
12966 pll->active_mask, pll->config.crtc_mask);
12967
12968 return;
12969 }
12970
12971 crtc_mask = 1 << drm_crtc_index(crtc);
12972
12973 if (new_state->active)
12974 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12975 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12976 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12977 else
12978 I915_STATE_WARN(pll->active_mask & crtc_mask,
12979 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12980 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12981
12982 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12983 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12984 crtc_mask, pll->config.crtc_mask);
12985
12986 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12987 &dpll_hw_state,
12988 sizeof(dpll_hw_state)),
12989 "pll hw state mismatch\n");
12990 }
12991
12992 static void
12993 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12994 struct drm_crtc_state *old_crtc_state,
12995 struct drm_crtc_state *new_crtc_state)
12996 {
12997 struct drm_i915_private *dev_priv = dev->dev_private;
12998 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12999 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13000
13001 if (new_state->shared_dpll)
13002 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13003
13004 if (old_state->shared_dpll &&
13005 old_state->shared_dpll != new_state->shared_dpll) {
13006 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13007 struct intel_shared_dpll *pll = old_state->shared_dpll;
13008
13009 I915_STATE_WARN(pll->active_mask & crtc_mask,
13010 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13011 pipe_name(drm_crtc_index(crtc)));
13012 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13013 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13014 pipe_name(drm_crtc_index(crtc)));
13015 }
13016 }
13017
13018 static void
13019 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13020 struct drm_crtc_state *old_state,
13021 struct drm_crtc_state *new_state)
13022 {
13023 if (!needs_modeset(new_state) &&
13024 !to_intel_crtc_state(new_state)->update_pipe)
13025 return;
13026
13027 verify_wm_state(crtc, new_state);
13028 verify_connector_state(crtc->dev, crtc);
13029 verify_crtc_state(crtc, old_state, new_state);
13030 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13031 }
13032
13033 static void
13034 verify_disabled_dpll_state(struct drm_device *dev)
13035 {
13036 struct drm_i915_private *dev_priv = dev->dev_private;
13037 int i;
13038
13039 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13040 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13041 }
13042
13043 static void
13044 intel_modeset_verify_disabled(struct drm_device *dev)
13045 {
13046 verify_encoder_state(dev);
13047 verify_connector_state(dev, NULL);
13048 verify_disabled_dpll_state(dev);
13049 }
13050
13051 static void update_scanline_offset(struct intel_crtc *crtc)
13052 {
13053 struct drm_device *dev = crtc->base.dev;
13054
13055 /*
13056 * The scanline counter increments at the leading edge of hsync.
13057 *
13058 * On most platforms it starts counting from vtotal-1 on the
13059 * first active line. That means the scanline counter value is
13060 * always one less than what we would expect. Ie. just after
13061 * start of vblank, which also occurs at start of hsync (on the
13062 * last active line), the scanline counter will read vblank_start-1.
13063 *
13064 * On gen2 the scanline counter starts counting from 1 instead
13065 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13066 * to keep the value positive), instead of adding one.
13067 *
13068 * On HSW+ the behaviour of the scanline counter depends on the output
13069 * type. For DP ports it behaves like most other platforms, but on HDMI
13070 * there's an extra 1 line difference. So we need to add two instead of
13071 * one to the value.
13072 */
13073 if (IS_GEN2(dev)) {
13074 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13075 int vtotal;
13076
13077 vtotal = adjusted_mode->crtc_vtotal;
13078 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13079 vtotal /= 2;
13080
13081 crtc->scanline_offset = vtotal - 1;
13082 } else if (HAS_DDI(dev) &&
13083 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13084 crtc->scanline_offset = 2;
13085 } else
13086 crtc->scanline_offset = 1;
13087 }
13088
13089 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13090 {
13091 struct drm_device *dev = state->dev;
13092 struct drm_i915_private *dev_priv = to_i915(dev);
13093 struct intel_shared_dpll_config *shared_dpll = NULL;
13094 struct drm_crtc *crtc;
13095 struct drm_crtc_state *crtc_state;
13096 int i;
13097
13098 if (!dev_priv->display.crtc_compute_clock)
13099 return;
13100
13101 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13103 struct intel_shared_dpll *old_dpll =
13104 to_intel_crtc_state(crtc->state)->shared_dpll;
13105
13106 if (!needs_modeset(crtc_state))
13107 continue;
13108
13109 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13110
13111 if (!old_dpll)
13112 continue;
13113
13114 if (!shared_dpll)
13115 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13116
13117 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13118 }
13119 }
13120
13121 /*
13122 * This implements the workaround described in the "notes" section of the mode
13123 * set sequence documentation. When going from no pipes or single pipe to
13124 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13125 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13126 */
13127 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13128 {
13129 struct drm_crtc_state *crtc_state;
13130 struct intel_crtc *intel_crtc;
13131 struct drm_crtc *crtc;
13132 struct intel_crtc_state *first_crtc_state = NULL;
13133 struct intel_crtc_state *other_crtc_state = NULL;
13134 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13135 int i;
13136
13137 /* look at all crtc's that are going to be enabled in during modeset */
13138 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13139 intel_crtc = to_intel_crtc(crtc);
13140
13141 if (!crtc_state->active || !needs_modeset(crtc_state))
13142 continue;
13143
13144 if (first_crtc_state) {
13145 other_crtc_state = to_intel_crtc_state(crtc_state);
13146 break;
13147 } else {
13148 first_crtc_state = to_intel_crtc_state(crtc_state);
13149 first_pipe = intel_crtc->pipe;
13150 }
13151 }
13152
13153 /* No workaround needed? */
13154 if (!first_crtc_state)
13155 return 0;
13156
13157 /* w/a possibly needed, check how many crtc's are already enabled. */
13158 for_each_intel_crtc(state->dev, intel_crtc) {
13159 struct intel_crtc_state *pipe_config;
13160
13161 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13162 if (IS_ERR(pipe_config))
13163 return PTR_ERR(pipe_config);
13164
13165 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13166
13167 if (!pipe_config->base.active ||
13168 needs_modeset(&pipe_config->base))
13169 continue;
13170
13171 /* 2 or more enabled crtcs means no need for w/a */
13172 if (enabled_pipe != INVALID_PIPE)
13173 return 0;
13174
13175 enabled_pipe = intel_crtc->pipe;
13176 }
13177
13178 if (enabled_pipe != INVALID_PIPE)
13179 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13180 else if (other_crtc_state)
13181 other_crtc_state->hsw_workaround_pipe = first_pipe;
13182
13183 return 0;
13184 }
13185
13186 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13187 {
13188 struct drm_crtc *crtc;
13189 struct drm_crtc_state *crtc_state;
13190 int ret = 0;
13191
13192 /* add all active pipes to the state */
13193 for_each_crtc(state->dev, crtc) {
13194 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13195 if (IS_ERR(crtc_state))
13196 return PTR_ERR(crtc_state);
13197
13198 if (!crtc_state->active || needs_modeset(crtc_state))
13199 continue;
13200
13201 crtc_state->mode_changed = true;
13202
13203 ret = drm_atomic_add_affected_connectors(state, crtc);
13204 if (ret)
13205 break;
13206
13207 ret = drm_atomic_add_affected_planes(state, crtc);
13208 if (ret)
13209 break;
13210 }
13211
13212 return ret;
13213 }
13214
13215 static int intel_modeset_checks(struct drm_atomic_state *state)
13216 {
13217 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13218 struct drm_i915_private *dev_priv = state->dev->dev_private;
13219 struct drm_crtc *crtc;
13220 struct drm_crtc_state *crtc_state;
13221 int ret = 0, i;
13222
13223 if (!check_digital_port_conflicts(state)) {
13224 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13225 return -EINVAL;
13226 }
13227
13228 intel_state->modeset = true;
13229 intel_state->active_crtcs = dev_priv->active_crtcs;
13230
13231 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13232 if (crtc_state->active)
13233 intel_state->active_crtcs |= 1 << i;
13234 else
13235 intel_state->active_crtcs &= ~(1 << i);
13236 }
13237
13238 /*
13239 * See if the config requires any additional preparation, e.g.
13240 * to adjust global state with pipes off. We need to do this
13241 * here so we can get the modeset_pipe updated config for the new
13242 * mode set on this crtc. For other crtcs we need to use the
13243 * adjusted_mode bits in the crtc directly.
13244 */
13245 if (dev_priv->display.modeset_calc_cdclk) {
13246 ret = dev_priv->display.modeset_calc_cdclk(state);
13247
13248 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13249 ret = intel_modeset_all_pipes(state);
13250
13251 if (ret < 0)
13252 return ret;
13253
13254 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13255 intel_state->cdclk, intel_state->dev_cdclk);
13256 } else
13257 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13258
13259 intel_modeset_clear_plls(state);
13260
13261 if (IS_HASWELL(dev_priv))
13262 return haswell_mode_set_planes_workaround(state);
13263
13264 return 0;
13265 }
13266
13267 /*
13268 * Handle calculation of various watermark data at the end of the atomic check
13269 * phase. The code here should be run after the per-crtc and per-plane 'check'
13270 * handlers to ensure that all derived state has been updated.
13271 */
13272 static void calc_watermark_data(struct drm_atomic_state *state)
13273 {
13274 struct drm_device *dev = state->dev;
13275 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13276 struct drm_crtc *crtc;
13277 struct drm_crtc_state *cstate;
13278 struct drm_plane *plane;
13279 struct drm_plane_state *pstate;
13280
13281 /*
13282 * Calculate watermark configuration details now that derived
13283 * plane/crtc state is all properly updated.
13284 */
13285 drm_for_each_crtc(crtc, dev) {
13286 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13287 crtc->state;
13288
13289 if (cstate->active)
13290 intel_state->wm_config.num_pipes_active++;
13291 }
13292 drm_for_each_legacy_plane(plane, dev) {
13293 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13294 plane->state;
13295
13296 if (!to_intel_plane_state(pstate)->visible)
13297 continue;
13298
13299 intel_state->wm_config.sprites_enabled = true;
13300 if (pstate->crtc_w != pstate->src_w >> 16 ||
13301 pstate->crtc_h != pstate->src_h >> 16)
13302 intel_state->wm_config.sprites_scaled = true;
13303 }
13304 }
13305
13306 /**
13307 * intel_atomic_check - validate state object
13308 * @dev: drm device
13309 * @state: state to validate
13310 */
13311 static int intel_atomic_check(struct drm_device *dev,
13312 struct drm_atomic_state *state)
13313 {
13314 struct drm_i915_private *dev_priv = to_i915(dev);
13315 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13316 struct drm_crtc *crtc;
13317 struct drm_crtc_state *crtc_state;
13318 int ret, i;
13319 bool any_ms = false;
13320
13321 ret = drm_atomic_helper_check_modeset(dev, state);
13322 if (ret)
13323 return ret;
13324
13325 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13326 struct intel_crtc_state *pipe_config =
13327 to_intel_crtc_state(crtc_state);
13328
13329 /* Catch I915_MODE_FLAG_INHERITED */
13330 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13331 crtc_state->mode_changed = true;
13332
13333 if (!crtc_state->enable) {
13334 if (needs_modeset(crtc_state))
13335 any_ms = true;
13336 continue;
13337 }
13338
13339 if (!needs_modeset(crtc_state))
13340 continue;
13341
13342 /* FIXME: For only active_changed we shouldn't need to do any
13343 * state recomputation at all. */
13344
13345 ret = drm_atomic_add_affected_connectors(state, crtc);
13346 if (ret)
13347 return ret;
13348
13349 ret = intel_modeset_pipe_config(crtc, pipe_config);
13350 if (ret)
13351 return ret;
13352
13353 if (i915.fastboot &&
13354 intel_pipe_config_compare(dev,
13355 to_intel_crtc_state(crtc->state),
13356 pipe_config, true)) {
13357 crtc_state->mode_changed = false;
13358 to_intel_crtc_state(crtc_state)->update_pipe = true;
13359 }
13360
13361 if (needs_modeset(crtc_state)) {
13362 any_ms = true;
13363
13364 ret = drm_atomic_add_affected_planes(state, crtc);
13365 if (ret)
13366 return ret;
13367 }
13368
13369 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13370 needs_modeset(crtc_state) ?
13371 "[modeset]" : "[fastset]");
13372 }
13373
13374 if (any_ms) {
13375 ret = intel_modeset_checks(state);
13376
13377 if (ret)
13378 return ret;
13379 } else
13380 intel_state->cdclk = dev_priv->cdclk_freq;
13381
13382 ret = drm_atomic_helper_check_planes(dev, state);
13383 if (ret)
13384 return ret;
13385
13386 intel_fbc_choose_crtc(dev_priv, state);
13387 calc_watermark_data(state);
13388
13389 return 0;
13390 }
13391
13392 static int intel_atomic_prepare_commit(struct drm_device *dev,
13393 struct drm_atomic_state *state,
13394 bool async)
13395 {
13396 struct drm_i915_private *dev_priv = dev->dev_private;
13397 struct drm_plane_state *plane_state;
13398 struct drm_crtc_state *crtc_state;
13399 struct drm_plane *plane;
13400 struct drm_crtc *crtc;
13401 int i, ret;
13402
13403 if (async) {
13404 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13405 return -EINVAL;
13406 }
13407
13408 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13409 ret = intel_crtc_wait_for_pending_flips(crtc);
13410 if (ret)
13411 return ret;
13412
13413 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13414 flush_workqueue(dev_priv->wq);
13415 }
13416
13417 ret = mutex_lock_interruptible(&dev->struct_mutex);
13418 if (ret)
13419 return ret;
13420
13421 ret = drm_atomic_helper_prepare_planes(dev, state);
13422 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13423 u32 reset_counter;
13424
13425 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13426 mutex_unlock(&dev->struct_mutex);
13427
13428 for_each_plane_in_state(state, plane, plane_state, i) {
13429 struct intel_plane_state *intel_plane_state =
13430 to_intel_plane_state(plane_state);
13431
13432 if (!intel_plane_state->wait_req)
13433 continue;
13434
13435 ret = __i915_wait_request(intel_plane_state->wait_req,
13436 reset_counter, true,
13437 NULL, NULL);
13438
13439 /* Swallow -EIO errors to allow updates during hw lockup. */
13440 if (ret == -EIO)
13441 ret = 0;
13442
13443 if (ret)
13444 break;
13445 }
13446
13447 if (!ret)
13448 return 0;
13449
13450 mutex_lock(&dev->struct_mutex);
13451 drm_atomic_helper_cleanup_planes(dev, state);
13452 }
13453
13454 mutex_unlock(&dev->struct_mutex);
13455 return ret;
13456 }
13457
13458 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13459 struct drm_i915_private *dev_priv,
13460 unsigned crtc_mask)
13461 {
13462 unsigned last_vblank_count[I915_MAX_PIPES];
13463 enum pipe pipe;
13464 int ret;
13465
13466 if (!crtc_mask)
13467 return;
13468
13469 for_each_pipe(dev_priv, pipe) {
13470 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13471
13472 if (!((1 << pipe) & crtc_mask))
13473 continue;
13474
13475 ret = drm_crtc_vblank_get(crtc);
13476 if (WARN_ON(ret != 0)) {
13477 crtc_mask &= ~(1 << pipe);
13478 continue;
13479 }
13480
13481 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13482 }
13483
13484 for_each_pipe(dev_priv, pipe) {
13485 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13486 long lret;
13487
13488 if (!((1 << pipe) & crtc_mask))
13489 continue;
13490
13491 lret = wait_event_timeout(dev->vblank[pipe].queue,
13492 last_vblank_count[pipe] !=
13493 drm_crtc_vblank_count(crtc),
13494 msecs_to_jiffies(50));
13495
13496 WARN_ON(!lret);
13497
13498 drm_crtc_vblank_put(crtc);
13499 }
13500 }
13501
13502 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13503 {
13504 /* fb updated, need to unpin old fb */
13505 if (crtc_state->fb_changed)
13506 return true;
13507
13508 /* wm changes, need vblank before final wm's */
13509 if (crtc_state->update_wm_post)
13510 return true;
13511
13512 /*
13513 * cxsr is re-enabled after vblank.
13514 * This is already handled by crtc_state->update_wm_post,
13515 * but added for clarity.
13516 */
13517 if (crtc_state->disable_cxsr)
13518 return true;
13519
13520 return false;
13521 }
13522
13523 /**
13524 * intel_atomic_commit - commit validated state object
13525 * @dev: DRM device
13526 * @state: the top-level driver state object
13527 * @async: asynchronous commit
13528 *
13529 * This function commits a top-level state object that has been validated
13530 * with drm_atomic_helper_check().
13531 *
13532 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13533 * we can only handle plane-related operations and do not yet support
13534 * asynchronous commit.
13535 *
13536 * RETURNS
13537 * Zero for success or -errno.
13538 */
13539 static int intel_atomic_commit(struct drm_device *dev,
13540 struct drm_atomic_state *state,
13541 bool async)
13542 {
13543 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13544 struct drm_i915_private *dev_priv = dev->dev_private;
13545 struct drm_crtc_state *old_crtc_state;
13546 struct drm_crtc *crtc;
13547 struct intel_crtc_state *intel_cstate;
13548 int ret = 0, i;
13549 bool hw_check = intel_state->modeset;
13550 unsigned long put_domains[I915_MAX_PIPES] = {};
13551 unsigned crtc_vblank_mask = 0;
13552
13553 ret = intel_atomic_prepare_commit(dev, state, async);
13554 if (ret) {
13555 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13556 return ret;
13557 }
13558
13559 drm_atomic_helper_swap_state(dev, state);
13560 dev_priv->wm.config = intel_state->wm_config;
13561 intel_shared_dpll_commit(state);
13562
13563 if (intel_state->modeset) {
13564 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13565 sizeof(intel_state->min_pixclk));
13566 dev_priv->active_crtcs = intel_state->active_crtcs;
13567 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13568
13569 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13570 }
13571
13572 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13574
13575 if (needs_modeset(crtc->state) ||
13576 to_intel_crtc_state(crtc->state)->update_pipe) {
13577 hw_check = true;
13578
13579 put_domains[to_intel_crtc(crtc)->pipe] =
13580 modeset_get_crtc_power_domains(crtc,
13581 to_intel_crtc_state(crtc->state));
13582 }
13583
13584 if (!needs_modeset(crtc->state))
13585 continue;
13586
13587 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13588
13589 if (old_crtc_state->active) {
13590 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13591 dev_priv->display.crtc_disable(crtc);
13592 intel_crtc->active = false;
13593 intel_fbc_disable(intel_crtc);
13594 intel_disable_shared_dpll(intel_crtc);
13595
13596 /*
13597 * Underruns don't always raise
13598 * interrupts, so check manually.
13599 */
13600 intel_check_cpu_fifo_underruns(dev_priv);
13601 intel_check_pch_fifo_underruns(dev_priv);
13602
13603 if (!crtc->state->active)
13604 intel_update_watermarks(crtc);
13605 }
13606 }
13607
13608 /* Only after disabling all output pipelines that will be changed can we
13609 * update the the output configuration. */
13610 intel_modeset_update_crtc_state(state);
13611
13612 if (intel_state->modeset) {
13613 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13614
13615 if (dev_priv->display.modeset_commit_cdclk &&
13616 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13617 dev_priv->display.modeset_commit_cdclk(state);
13618
13619 intel_modeset_verify_disabled(dev);
13620 }
13621
13622 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13623 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13625 bool modeset = needs_modeset(crtc->state);
13626 struct intel_crtc_state *pipe_config =
13627 to_intel_crtc_state(crtc->state);
13628 bool update_pipe = !modeset && pipe_config->update_pipe;
13629
13630 if (modeset && crtc->state->active) {
13631 update_scanline_offset(to_intel_crtc(crtc));
13632 dev_priv->display.crtc_enable(crtc);
13633 }
13634
13635 if (!modeset)
13636 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13637
13638 if (crtc->state->active &&
13639 drm_atomic_get_existing_plane_state(state, crtc->primary))
13640 intel_fbc_enable(intel_crtc);
13641
13642 if (crtc->state->active &&
13643 (crtc->state->planes_changed || update_pipe))
13644 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13645
13646 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13647 crtc_vblank_mask |= 1 << i;
13648 }
13649
13650 /* FIXME: add subpixel order */
13651
13652 if (!state->legacy_cursor_update)
13653 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13654
13655 /*
13656 * Now that the vblank has passed, we can go ahead and program the
13657 * optimal watermarks on platforms that need two-step watermark
13658 * programming.
13659 *
13660 * TODO: Move this (and other cleanup) to an async worker eventually.
13661 */
13662 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13663 intel_cstate = to_intel_crtc_state(crtc->state);
13664
13665 if (dev_priv->display.optimize_watermarks)
13666 dev_priv->display.optimize_watermarks(intel_cstate);
13667 }
13668
13669 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13670 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13671
13672 if (put_domains[i])
13673 modeset_put_power_domains(dev_priv, put_domains[i]);
13674
13675 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13676 }
13677
13678 if (intel_state->modeset)
13679 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13680
13681 mutex_lock(&dev->struct_mutex);
13682 drm_atomic_helper_cleanup_planes(dev, state);
13683 mutex_unlock(&dev->struct_mutex);
13684
13685 drm_atomic_state_free(state);
13686
13687 /* As one of the primary mmio accessors, KMS has a high likelihood
13688 * of triggering bugs in unclaimed access. After we finish
13689 * modesetting, see if an error has been flagged, and if so
13690 * enable debugging for the next modeset - and hope we catch
13691 * the culprit.
13692 *
13693 * XXX note that we assume display power is on at this point.
13694 * This might hold true now but we need to add pm helper to check
13695 * unclaimed only when the hardware is on, as atomic commits
13696 * can happen also when the device is completely off.
13697 */
13698 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13699
13700 return 0;
13701 }
13702
13703 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13704 {
13705 struct drm_device *dev = crtc->dev;
13706 struct drm_atomic_state *state;
13707 struct drm_crtc_state *crtc_state;
13708 int ret;
13709
13710 state = drm_atomic_state_alloc(dev);
13711 if (!state) {
13712 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13713 crtc->base.id);
13714 return;
13715 }
13716
13717 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13718
13719 retry:
13720 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13721 ret = PTR_ERR_OR_ZERO(crtc_state);
13722 if (!ret) {
13723 if (!crtc_state->active)
13724 goto out;
13725
13726 crtc_state->mode_changed = true;
13727 ret = drm_atomic_commit(state);
13728 }
13729
13730 if (ret == -EDEADLK) {
13731 drm_atomic_state_clear(state);
13732 drm_modeset_backoff(state->acquire_ctx);
13733 goto retry;
13734 }
13735
13736 if (ret)
13737 out:
13738 drm_atomic_state_free(state);
13739 }
13740
13741 #undef for_each_intel_crtc_masked
13742
13743 static const struct drm_crtc_funcs intel_crtc_funcs = {
13744 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13745 .set_config = drm_atomic_helper_set_config,
13746 .set_property = drm_atomic_helper_crtc_set_property,
13747 .destroy = intel_crtc_destroy,
13748 .page_flip = intel_crtc_page_flip,
13749 .atomic_duplicate_state = intel_crtc_duplicate_state,
13750 .atomic_destroy_state = intel_crtc_destroy_state,
13751 };
13752
13753 /**
13754 * intel_prepare_plane_fb - Prepare fb for usage on plane
13755 * @plane: drm plane to prepare for
13756 * @fb: framebuffer to prepare for presentation
13757 *
13758 * Prepares a framebuffer for usage on a display plane. Generally this
13759 * involves pinning the underlying object and updating the frontbuffer tracking
13760 * bits. Some older platforms need special physical address handling for
13761 * cursor planes.
13762 *
13763 * Must be called with struct_mutex held.
13764 *
13765 * Returns 0 on success, negative error code on failure.
13766 */
13767 int
13768 intel_prepare_plane_fb(struct drm_plane *plane,
13769 const struct drm_plane_state *new_state)
13770 {
13771 struct drm_device *dev = plane->dev;
13772 struct drm_framebuffer *fb = new_state->fb;
13773 struct intel_plane *intel_plane = to_intel_plane(plane);
13774 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13775 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13776 int ret = 0;
13777
13778 if (!obj && !old_obj)
13779 return 0;
13780
13781 if (old_obj) {
13782 struct drm_crtc_state *crtc_state =
13783 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13784
13785 /* Big Hammer, we also need to ensure that any pending
13786 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13787 * current scanout is retired before unpinning the old
13788 * framebuffer. Note that we rely on userspace rendering
13789 * into the buffer attached to the pipe they are waiting
13790 * on. If not, userspace generates a GPU hang with IPEHR
13791 * point to the MI_WAIT_FOR_EVENT.
13792 *
13793 * This should only fail upon a hung GPU, in which case we
13794 * can safely continue.
13795 */
13796 if (needs_modeset(crtc_state))
13797 ret = i915_gem_object_wait_rendering(old_obj, true);
13798
13799 /* Swallow -EIO errors to allow updates during hw lockup. */
13800 if (ret && ret != -EIO)
13801 return ret;
13802 }
13803
13804 /* For framebuffer backed by dmabuf, wait for fence */
13805 if (obj && obj->base.dma_buf) {
13806 long lret;
13807
13808 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13809 false, true,
13810 MAX_SCHEDULE_TIMEOUT);
13811 if (lret == -ERESTARTSYS)
13812 return lret;
13813
13814 WARN(lret < 0, "waiting returns %li\n", lret);
13815 }
13816
13817 if (!obj) {
13818 ret = 0;
13819 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13820 INTEL_INFO(dev)->cursor_needs_physical) {
13821 int align = IS_I830(dev) ? 16 * 1024 : 256;
13822 ret = i915_gem_object_attach_phys(obj, align);
13823 if (ret)
13824 DRM_DEBUG_KMS("failed to attach phys object\n");
13825 } else {
13826 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13827 }
13828
13829 if (ret == 0) {
13830 if (obj) {
13831 struct intel_plane_state *plane_state =
13832 to_intel_plane_state(new_state);
13833
13834 i915_gem_request_assign(&plane_state->wait_req,
13835 obj->last_write_req);
13836 }
13837
13838 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13839 }
13840
13841 return ret;
13842 }
13843
13844 /**
13845 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13846 * @plane: drm plane to clean up for
13847 * @fb: old framebuffer that was on plane
13848 *
13849 * Cleans up a framebuffer that has just been removed from a plane.
13850 *
13851 * Must be called with struct_mutex held.
13852 */
13853 void
13854 intel_cleanup_plane_fb(struct drm_plane *plane,
13855 const struct drm_plane_state *old_state)
13856 {
13857 struct drm_device *dev = plane->dev;
13858 struct intel_plane *intel_plane = to_intel_plane(plane);
13859 struct intel_plane_state *old_intel_state;
13860 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13861 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13862
13863 old_intel_state = to_intel_plane_state(old_state);
13864
13865 if (!obj && !old_obj)
13866 return;
13867
13868 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13869 !INTEL_INFO(dev)->cursor_needs_physical))
13870 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13871
13872 /* prepare_fb aborted? */
13873 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13874 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13875 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13876
13877 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13878 }
13879
13880 int
13881 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13882 {
13883 int max_scale;
13884 struct drm_device *dev;
13885 struct drm_i915_private *dev_priv;
13886 int crtc_clock, cdclk;
13887
13888 if (!intel_crtc || !crtc_state->base.enable)
13889 return DRM_PLANE_HELPER_NO_SCALING;
13890
13891 dev = intel_crtc->base.dev;
13892 dev_priv = dev->dev_private;
13893 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13894 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13895
13896 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13897 return DRM_PLANE_HELPER_NO_SCALING;
13898
13899 /*
13900 * skl max scale is lower of:
13901 * close to 3 but not 3, -1 is for that purpose
13902 * or
13903 * cdclk/crtc_clock
13904 */
13905 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13906
13907 return max_scale;
13908 }
13909
13910 static int
13911 intel_check_primary_plane(struct drm_plane *plane,
13912 struct intel_crtc_state *crtc_state,
13913 struct intel_plane_state *state)
13914 {
13915 struct drm_crtc *crtc = state->base.crtc;
13916 struct drm_framebuffer *fb = state->base.fb;
13917 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13918 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13919 bool can_position = false;
13920
13921 if (INTEL_INFO(plane->dev)->gen >= 9) {
13922 /* use scaler when colorkey is not required */
13923 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13924 min_scale = 1;
13925 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13926 }
13927 can_position = true;
13928 }
13929
13930 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13931 &state->dst, &state->clip,
13932 min_scale, max_scale,
13933 can_position, true,
13934 &state->visible);
13935 }
13936
13937 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13938 struct drm_crtc_state *old_crtc_state)
13939 {
13940 struct drm_device *dev = crtc->dev;
13941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13942 struct intel_crtc_state *old_intel_state =
13943 to_intel_crtc_state(old_crtc_state);
13944 bool modeset = needs_modeset(crtc->state);
13945
13946 /* Perform vblank evasion around commit operation */
13947 intel_pipe_update_start(intel_crtc);
13948
13949 if (modeset)
13950 return;
13951
13952 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13953 intel_color_set_csc(crtc->state);
13954 intel_color_load_luts(crtc->state);
13955 }
13956
13957 if (to_intel_crtc_state(crtc->state)->update_pipe)
13958 intel_update_pipe_config(intel_crtc, old_intel_state);
13959 else if (INTEL_INFO(dev)->gen >= 9)
13960 skl_detach_scalers(intel_crtc);
13961 }
13962
13963 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13964 struct drm_crtc_state *old_crtc_state)
13965 {
13966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13967
13968 intel_pipe_update_end(intel_crtc);
13969 }
13970
13971 /**
13972 * intel_plane_destroy - destroy a plane
13973 * @plane: plane to destroy
13974 *
13975 * Common destruction function for all types of planes (primary, cursor,
13976 * sprite).
13977 */
13978 void intel_plane_destroy(struct drm_plane *plane)
13979 {
13980 struct intel_plane *intel_plane = to_intel_plane(plane);
13981 drm_plane_cleanup(plane);
13982 kfree(intel_plane);
13983 }
13984
13985 const struct drm_plane_funcs intel_plane_funcs = {
13986 .update_plane = drm_atomic_helper_update_plane,
13987 .disable_plane = drm_atomic_helper_disable_plane,
13988 .destroy = intel_plane_destroy,
13989 .set_property = drm_atomic_helper_plane_set_property,
13990 .atomic_get_property = intel_plane_atomic_get_property,
13991 .atomic_set_property = intel_plane_atomic_set_property,
13992 .atomic_duplicate_state = intel_plane_duplicate_state,
13993 .atomic_destroy_state = intel_plane_destroy_state,
13994
13995 };
13996
13997 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13998 int pipe)
13999 {
14000 struct intel_plane *primary = NULL;
14001 struct intel_plane_state *state = NULL;
14002 const uint32_t *intel_primary_formats;
14003 unsigned int num_formats;
14004 int ret;
14005
14006 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14007 if (!primary)
14008 goto fail;
14009
14010 state = intel_create_plane_state(&primary->base);
14011 if (!state)
14012 goto fail;
14013 primary->base.state = &state->base;
14014
14015 primary->can_scale = false;
14016 primary->max_downscale = 1;
14017 if (INTEL_INFO(dev)->gen >= 9) {
14018 primary->can_scale = true;
14019 state->scaler_id = -1;
14020 }
14021 primary->pipe = pipe;
14022 primary->plane = pipe;
14023 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14024 primary->check_plane = intel_check_primary_plane;
14025 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14026 primary->plane = !pipe;
14027
14028 if (INTEL_INFO(dev)->gen >= 9) {
14029 intel_primary_formats = skl_primary_formats;
14030 num_formats = ARRAY_SIZE(skl_primary_formats);
14031
14032 primary->update_plane = skylake_update_primary_plane;
14033 primary->disable_plane = skylake_disable_primary_plane;
14034 } else if (HAS_PCH_SPLIT(dev)) {
14035 intel_primary_formats = i965_primary_formats;
14036 num_formats = ARRAY_SIZE(i965_primary_formats);
14037
14038 primary->update_plane = ironlake_update_primary_plane;
14039 primary->disable_plane = i9xx_disable_primary_plane;
14040 } else if (INTEL_INFO(dev)->gen >= 4) {
14041 intel_primary_formats = i965_primary_formats;
14042 num_formats = ARRAY_SIZE(i965_primary_formats);
14043
14044 primary->update_plane = i9xx_update_primary_plane;
14045 primary->disable_plane = i9xx_disable_primary_plane;
14046 } else {
14047 intel_primary_formats = i8xx_primary_formats;
14048 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14049
14050 primary->update_plane = i9xx_update_primary_plane;
14051 primary->disable_plane = i9xx_disable_primary_plane;
14052 }
14053
14054 ret = drm_universal_plane_init(dev, &primary->base, 0,
14055 &intel_plane_funcs,
14056 intel_primary_formats, num_formats,
14057 DRM_PLANE_TYPE_PRIMARY, NULL);
14058 if (ret)
14059 goto fail;
14060
14061 if (INTEL_INFO(dev)->gen >= 4)
14062 intel_create_rotation_property(dev, primary);
14063
14064 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14065
14066 return &primary->base;
14067
14068 fail:
14069 kfree(state);
14070 kfree(primary);
14071
14072 return NULL;
14073 }
14074
14075 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14076 {
14077 if (!dev->mode_config.rotation_property) {
14078 unsigned long flags = BIT(DRM_ROTATE_0) |
14079 BIT(DRM_ROTATE_180);
14080
14081 if (INTEL_INFO(dev)->gen >= 9)
14082 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14083
14084 dev->mode_config.rotation_property =
14085 drm_mode_create_rotation_property(dev, flags);
14086 }
14087 if (dev->mode_config.rotation_property)
14088 drm_object_attach_property(&plane->base.base,
14089 dev->mode_config.rotation_property,
14090 plane->base.state->rotation);
14091 }
14092
14093 static int
14094 intel_check_cursor_plane(struct drm_plane *plane,
14095 struct intel_crtc_state *crtc_state,
14096 struct intel_plane_state *state)
14097 {
14098 struct drm_crtc *crtc = crtc_state->base.crtc;
14099 struct drm_framebuffer *fb = state->base.fb;
14100 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14101 enum pipe pipe = to_intel_plane(plane)->pipe;
14102 unsigned stride;
14103 int ret;
14104
14105 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14106 &state->dst, &state->clip,
14107 DRM_PLANE_HELPER_NO_SCALING,
14108 DRM_PLANE_HELPER_NO_SCALING,
14109 true, true, &state->visible);
14110 if (ret)
14111 return ret;
14112
14113 /* if we want to turn off the cursor ignore width and height */
14114 if (!obj)
14115 return 0;
14116
14117 /* Check for which cursor types we support */
14118 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14119 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14120 state->base.crtc_w, state->base.crtc_h);
14121 return -EINVAL;
14122 }
14123
14124 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14125 if (obj->base.size < stride * state->base.crtc_h) {
14126 DRM_DEBUG_KMS("buffer is too small\n");
14127 return -ENOMEM;
14128 }
14129
14130 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14131 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14132 return -EINVAL;
14133 }
14134
14135 /*
14136 * There's something wrong with the cursor on CHV pipe C.
14137 * If it straddles the left edge of the screen then
14138 * moving it away from the edge or disabling it often
14139 * results in a pipe underrun, and often that can lead to
14140 * dead pipe (constant underrun reported, and it scans
14141 * out just a solid color). To recover from that, the
14142 * display power well must be turned off and on again.
14143 * Refuse the put the cursor into that compromised position.
14144 */
14145 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14146 state->visible && state->base.crtc_x < 0) {
14147 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14148 return -EINVAL;
14149 }
14150
14151 return 0;
14152 }
14153
14154 static void
14155 intel_disable_cursor_plane(struct drm_plane *plane,
14156 struct drm_crtc *crtc)
14157 {
14158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14159
14160 intel_crtc->cursor_addr = 0;
14161 intel_crtc_update_cursor(crtc, NULL);
14162 }
14163
14164 static void
14165 intel_update_cursor_plane(struct drm_plane *plane,
14166 const struct intel_crtc_state *crtc_state,
14167 const struct intel_plane_state *state)
14168 {
14169 struct drm_crtc *crtc = crtc_state->base.crtc;
14170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14171 struct drm_device *dev = plane->dev;
14172 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14173 uint32_t addr;
14174
14175 if (!obj)
14176 addr = 0;
14177 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14178 addr = i915_gem_obj_ggtt_offset(obj);
14179 else
14180 addr = obj->phys_handle->busaddr;
14181
14182 intel_crtc->cursor_addr = addr;
14183 intel_crtc_update_cursor(crtc, state);
14184 }
14185
14186 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14187 int pipe)
14188 {
14189 struct intel_plane *cursor = NULL;
14190 struct intel_plane_state *state = NULL;
14191 int ret;
14192
14193 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14194 if (!cursor)
14195 goto fail;
14196
14197 state = intel_create_plane_state(&cursor->base);
14198 if (!state)
14199 goto fail;
14200 cursor->base.state = &state->base;
14201
14202 cursor->can_scale = false;
14203 cursor->max_downscale = 1;
14204 cursor->pipe = pipe;
14205 cursor->plane = pipe;
14206 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14207 cursor->check_plane = intel_check_cursor_plane;
14208 cursor->update_plane = intel_update_cursor_plane;
14209 cursor->disable_plane = intel_disable_cursor_plane;
14210
14211 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14212 &intel_plane_funcs,
14213 intel_cursor_formats,
14214 ARRAY_SIZE(intel_cursor_formats),
14215 DRM_PLANE_TYPE_CURSOR, NULL);
14216 if (ret)
14217 goto fail;
14218
14219 if (INTEL_INFO(dev)->gen >= 4) {
14220 if (!dev->mode_config.rotation_property)
14221 dev->mode_config.rotation_property =
14222 drm_mode_create_rotation_property(dev,
14223 BIT(DRM_ROTATE_0) |
14224 BIT(DRM_ROTATE_180));
14225 if (dev->mode_config.rotation_property)
14226 drm_object_attach_property(&cursor->base.base,
14227 dev->mode_config.rotation_property,
14228 state->base.rotation);
14229 }
14230
14231 if (INTEL_INFO(dev)->gen >=9)
14232 state->scaler_id = -1;
14233
14234 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14235
14236 return &cursor->base;
14237
14238 fail:
14239 kfree(state);
14240 kfree(cursor);
14241
14242 return NULL;
14243 }
14244
14245 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14246 struct intel_crtc_state *crtc_state)
14247 {
14248 int i;
14249 struct intel_scaler *intel_scaler;
14250 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14251
14252 for (i = 0; i < intel_crtc->num_scalers; i++) {
14253 intel_scaler = &scaler_state->scalers[i];
14254 intel_scaler->in_use = 0;
14255 intel_scaler->mode = PS_SCALER_MODE_DYN;
14256 }
14257
14258 scaler_state->scaler_id = -1;
14259 }
14260
14261 static void intel_crtc_init(struct drm_device *dev, int pipe)
14262 {
14263 struct drm_i915_private *dev_priv = dev->dev_private;
14264 struct intel_crtc *intel_crtc;
14265 struct intel_crtc_state *crtc_state = NULL;
14266 struct drm_plane *primary = NULL;
14267 struct drm_plane *cursor = NULL;
14268 int ret;
14269
14270 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14271 if (intel_crtc == NULL)
14272 return;
14273
14274 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14275 if (!crtc_state)
14276 goto fail;
14277 intel_crtc->config = crtc_state;
14278 intel_crtc->base.state = &crtc_state->base;
14279 crtc_state->base.crtc = &intel_crtc->base;
14280
14281 /* initialize shared scalers */
14282 if (INTEL_INFO(dev)->gen >= 9) {
14283 if (pipe == PIPE_C)
14284 intel_crtc->num_scalers = 1;
14285 else
14286 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14287
14288 skl_init_scalers(dev, intel_crtc, crtc_state);
14289 }
14290
14291 primary = intel_primary_plane_create(dev, pipe);
14292 if (!primary)
14293 goto fail;
14294
14295 cursor = intel_cursor_plane_create(dev, pipe);
14296 if (!cursor)
14297 goto fail;
14298
14299 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14300 cursor, &intel_crtc_funcs, NULL);
14301 if (ret)
14302 goto fail;
14303
14304 /*
14305 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14306 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14307 */
14308 intel_crtc->pipe = pipe;
14309 intel_crtc->plane = pipe;
14310 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14311 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14312 intel_crtc->plane = !pipe;
14313 }
14314
14315 intel_crtc->cursor_base = ~0;
14316 intel_crtc->cursor_cntl = ~0;
14317 intel_crtc->cursor_size = ~0;
14318
14319 intel_crtc->wm.cxsr_allowed = true;
14320
14321 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14322 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14323 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14324 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14325
14326 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14327
14328 intel_color_init(&intel_crtc->base);
14329
14330 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14331 return;
14332
14333 fail:
14334 if (primary)
14335 drm_plane_cleanup(primary);
14336 if (cursor)
14337 drm_plane_cleanup(cursor);
14338 kfree(crtc_state);
14339 kfree(intel_crtc);
14340 }
14341
14342 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14343 {
14344 struct drm_encoder *encoder = connector->base.encoder;
14345 struct drm_device *dev = connector->base.dev;
14346
14347 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14348
14349 if (!encoder || WARN_ON(!encoder->crtc))
14350 return INVALID_PIPE;
14351
14352 return to_intel_crtc(encoder->crtc)->pipe;
14353 }
14354
14355 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14356 struct drm_file *file)
14357 {
14358 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14359 struct drm_crtc *drmmode_crtc;
14360 struct intel_crtc *crtc;
14361
14362 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14363
14364 if (!drmmode_crtc) {
14365 DRM_ERROR("no such CRTC id\n");
14366 return -ENOENT;
14367 }
14368
14369 crtc = to_intel_crtc(drmmode_crtc);
14370 pipe_from_crtc_id->pipe = crtc->pipe;
14371
14372 return 0;
14373 }
14374
14375 static int intel_encoder_clones(struct intel_encoder *encoder)
14376 {
14377 struct drm_device *dev = encoder->base.dev;
14378 struct intel_encoder *source_encoder;
14379 int index_mask = 0;
14380 int entry = 0;
14381
14382 for_each_intel_encoder(dev, source_encoder) {
14383 if (encoders_cloneable(encoder, source_encoder))
14384 index_mask |= (1 << entry);
14385
14386 entry++;
14387 }
14388
14389 return index_mask;
14390 }
14391
14392 static bool has_edp_a(struct drm_device *dev)
14393 {
14394 struct drm_i915_private *dev_priv = dev->dev_private;
14395
14396 if (!IS_MOBILE(dev))
14397 return false;
14398
14399 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14400 return false;
14401
14402 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14403 return false;
14404
14405 return true;
14406 }
14407
14408 static bool intel_crt_present(struct drm_device *dev)
14409 {
14410 struct drm_i915_private *dev_priv = dev->dev_private;
14411
14412 if (INTEL_INFO(dev)->gen >= 9)
14413 return false;
14414
14415 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14416 return false;
14417
14418 if (IS_CHERRYVIEW(dev))
14419 return false;
14420
14421 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14422 return false;
14423
14424 /* DDI E can't be used if DDI A requires 4 lanes */
14425 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14426 return false;
14427
14428 if (!dev_priv->vbt.int_crt_support)
14429 return false;
14430
14431 return true;
14432 }
14433
14434 static void intel_setup_outputs(struct drm_device *dev)
14435 {
14436 struct drm_i915_private *dev_priv = dev->dev_private;
14437 struct intel_encoder *encoder;
14438 bool dpd_is_edp = false;
14439
14440 intel_lvds_init(dev);
14441
14442 if (intel_crt_present(dev))
14443 intel_crt_init(dev);
14444
14445 if (IS_BROXTON(dev)) {
14446 /*
14447 * FIXME: Broxton doesn't support port detection via the
14448 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14449 * detect the ports.
14450 */
14451 intel_ddi_init(dev, PORT_A);
14452 intel_ddi_init(dev, PORT_B);
14453 intel_ddi_init(dev, PORT_C);
14454
14455 intel_dsi_init(dev);
14456 } else if (HAS_DDI(dev)) {
14457 int found;
14458
14459 /*
14460 * Haswell uses DDI functions to detect digital outputs.
14461 * On SKL pre-D0 the strap isn't connected, so we assume
14462 * it's there.
14463 */
14464 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14465 /* WaIgnoreDDIAStrap: skl */
14466 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14467 intel_ddi_init(dev, PORT_A);
14468
14469 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14470 * register */
14471 found = I915_READ(SFUSE_STRAP);
14472
14473 if (found & SFUSE_STRAP_DDIB_DETECTED)
14474 intel_ddi_init(dev, PORT_B);
14475 if (found & SFUSE_STRAP_DDIC_DETECTED)
14476 intel_ddi_init(dev, PORT_C);
14477 if (found & SFUSE_STRAP_DDID_DETECTED)
14478 intel_ddi_init(dev, PORT_D);
14479 /*
14480 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14481 */
14482 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14483 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14484 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14485 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14486 intel_ddi_init(dev, PORT_E);
14487
14488 } else if (HAS_PCH_SPLIT(dev)) {
14489 int found;
14490 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14491
14492 if (has_edp_a(dev))
14493 intel_dp_init(dev, DP_A, PORT_A);
14494
14495 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14496 /* PCH SDVOB multiplex with HDMIB */
14497 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14498 if (!found)
14499 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14500 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14501 intel_dp_init(dev, PCH_DP_B, PORT_B);
14502 }
14503
14504 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14505 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14506
14507 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14508 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14509
14510 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14511 intel_dp_init(dev, PCH_DP_C, PORT_C);
14512
14513 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14514 intel_dp_init(dev, PCH_DP_D, PORT_D);
14515 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14516 /*
14517 * The DP_DETECTED bit is the latched state of the DDC
14518 * SDA pin at boot. However since eDP doesn't require DDC
14519 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14520 * eDP ports may have been muxed to an alternate function.
14521 * Thus we can't rely on the DP_DETECTED bit alone to detect
14522 * eDP ports. Consult the VBT as well as DP_DETECTED to
14523 * detect eDP ports.
14524 */
14525 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14526 !intel_dp_is_edp(dev, PORT_B))
14527 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14528 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14529 intel_dp_is_edp(dev, PORT_B))
14530 intel_dp_init(dev, VLV_DP_B, PORT_B);
14531
14532 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14533 !intel_dp_is_edp(dev, PORT_C))
14534 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14535 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14536 intel_dp_is_edp(dev, PORT_C))
14537 intel_dp_init(dev, VLV_DP_C, PORT_C);
14538
14539 if (IS_CHERRYVIEW(dev)) {
14540 /* eDP not supported on port D, so don't check VBT */
14541 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14542 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14543 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14544 intel_dp_init(dev, CHV_DP_D, PORT_D);
14545 }
14546
14547 intel_dsi_init(dev);
14548 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14549 bool found = false;
14550
14551 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14552 DRM_DEBUG_KMS("probing SDVOB\n");
14553 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14554 if (!found && IS_G4X(dev)) {
14555 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14556 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14557 }
14558
14559 if (!found && IS_G4X(dev))
14560 intel_dp_init(dev, DP_B, PORT_B);
14561 }
14562
14563 /* Before G4X SDVOC doesn't have its own detect register */
14564
14565 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14566 DRM_DEBUG_KMS("probing SDVOC\n");
14567 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14568 }
14569
14570 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14571
14572 if (IS_G4X(dev)) {
14573 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14574 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14575 }
14576 if (IS_G4X(dev))
14577 intel_dp_init(dev, DP_C, PORT_C);
14578 }
14579
14580 if (IS_G4X(dev) &&
14581 (I915_READ(DP_D) & DP_DETECTED))
14582 intel_dp_init(dev, DP_D, PORT_D);
14583 } else if (IS_GEN2(dev))
14584 intel_dvo_init(dev);
14585
14586 if (SUPPORTS_TV(dev))
14587 intel_tv_init(dev);
14588
14589 intel_psr_init(dev);
14590
14591 for_each_intel_encoder(dev, encoder) {
14592 encoder->base.possible_crtcs = encoder->crtc_mask;
14593 encoder->base.possible_clones =
14594 intel_encoder_clones(encoder);
14595 }
14596
14597 intel_init_pch_refclk(dev);
14598
14599 drm_helper_move_panel_connectors_to_head(dev);
14600 }
14601
14602 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14603 {
14604 struct drm_device *dev = fb->dev;
14605 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14606
14607 drm_framebuffer_cleanup(fb);
14608 mutex_lock(&dev->struct_mutex);
14609 WARN_ON(!intel_fb->obj->framebuffer_references--);
14610 drm_gem_object_unreference(&intel_fb->obj->base);
14611 mutex_unlock(&dev->struct_mutex);
14612 kfree(intel_fb);
14613 }
14614
14615 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14616 struct drm_file *file,
14617 unsigned int *handle)
14618 {
14619 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14620 struct drm_i915_gem_object *obj = intel_fb->obj;
14621
14622 if (obj->userptr.mm) {
14623 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14624 return -EINVAL;
14625 }
14626
14627 return drm_gem_handle_create(file, &obj->base, handle);
14628 }
14629
14630 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14631 struct drm_file *file,
14632 unsigned flags, unsigned color,
14633 struct drm_clip_rect *clips,
14634 unsigned num_clips)
14635 {
14636 struct drm_device *dev = fb->dev;
14637 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14638 struct drm_i915_gem_object *obj = intel_fb->obj;
14639
14640 mutex_lock(&dev->struct_mutex);
14641 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14642 mutex_unlock(&dev->struct_mutex);
14643
14644 return 0;
14645 }
14646
14647 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14648 .destroy = intel_user_framebuffer_destroy,
14649 .create_handle = intel_user_framebuffer_create_handle,
14650 .dirty = intel_user_framebuffer_dirty,
14651 };
14652
14653 static
14654 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14655 uint32_t pixel_format)
14656 {
14657 u32 gen = INTEL_INFO(dev)->gen;
14658
14659 if (gen >= 9) {
14660 int cpp = drm_format_plane_cpp(pixel_format, 0);
14661
14662 /* "The stride in bytes must not exceed the of the size of 8K
14663 * pixels and 32K bytes."
14664 */
14665 return min(8192 * cpp, 32768);
14666 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14667 return 32*1024;
14668 } else if (gen >= 4) {
14669 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14670 return 16*1024;
14671 else
14672 return 32*1024;
14673 } else if (gen >= 3) {
14674 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14675 return 8*1024;
14676 else
14677 return 16*1024;
14678 } else {
14679 /* XXX DSPC is limited to 4k tiled */
14680 return 8*1024;
14681 }
14682 }
14683
14684 static int intel_framebuffer_init(struct drm_device *dev,
14685 struct intel_framebuffer *intel_fb,
14686 struct drm_mode_fb_cmd2 *mode_cmd,
14687 struct drm_i915_gem_object *obj)
14688 {
14689 struct drm_i915_private *dev_priv = to_i915(dev);
14690 unsigned int aligned_height;
14691 int ret;
14692 u32 pitch_limit, stride_alignment;
14693
14694 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14695
14696 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14697 /* Enforce that fb modifier and tiling mode match, but only for
14698 * X-tiled. This is needed for FBC. */
14699 if (!!(obj->tiling_mode == I915_TILING_X) !=
14700 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14701 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14702 return -EINVAL;
14703 }
14704 } else {
14705 if (obj->tiling_mode == I915_TILING_X)
14706 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14707 else if (obj->tiling_mode == I915_TILING_Y) {
14708 DRM_DEBUG("No Y tiling for legacy addfb\n");
14709 return -EINVAL;
14710 }
14711 }
14712
14713 /* Passed in modifier sanity checking. */
14714 switch (mode_cmd->modifier[0]) {
14715 case I915_FORMAT_MOD_Y_TILED:
14716 case I915_FORMAT_MOD_Yf_TILED:
14717 if (INTEL_INFO(dev)->gen < 9) {
14718 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14719 mode_cmd->modifier[0]);
14720 return -EINVAL;
14721 }
14722 case DRM_FORMAT_MOD_NONE:
14723 case I915_FORMAT_MOD_X_TILED:
14724 break;
14725 default:
14726 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14727 mode_cmd->modifier[0]);
14728 return -EINVAL;
14729 }
14730
14731 stride_alignment = intel_fb_stride_alignment(dev_priv,
14732 mode_cmd->modifier[0],
14733 mode_cmd->pixel_format);
14734 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14735 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14736 mode_cmd->pitches[0], stride_alignment);
14737 return -EINVAL;
14738 }
14739
14740 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14741 mode_cmd->pixel_format);
14742 if (mode_cmd->pitches[0] > pitch_limit) {
14743 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14744 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14745 "tiled" : "linear",
14746 mode_cmd->pitches[0], pitch_limit);
14747 return -EINVAL;
14748 }
14749
14750 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14751 mode_cmd->pitches[0] != obj->stride) {
14752 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14753 mode_cmd->pitches[0], obj->stride);
14754 return -EINVAL;
14755 }
14756
14757 /* Reject formats not supported by any plane early. */
14758 switch (mode_cmd->pixel_format) {
14759 case DRM_FORMAT_C8:
14760 case DRM_FORMAT_RGB565:
14761 case DRM_FORMAT_XRGB8888:
14762 case DRM_FORMAT_ARGB8888:
14763 break;
14764 case DRM_FORMAT_XRGB1555:
14765 if (INTEL_INFO(dev)->gen > 3) {
14766 DRM_DEBUG("unsupported pixel format: %s\n",
14767 drm_get_format_name(mode_cmd->pixel_format));
14768 return -EINVAL;
14769 }
14770 break;
14771 case DRM_FORMAT_ABGR8888:
14772 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14773 INTEL_INFO(dev)->gen < 9) {
14774 DRM_DEBUG("unsupported pixel format: %s\n",
14775 drm_get_format_name(mode_cmd->pixel_format));
14776 return -EINVAL;
14777 }
14778 break;
14779 case DRM_FORMAT_XBGR8888:
14780 case DRM_FORMAT_XRGB2101010:
14781 case DRM_FORMAT_XBGR2101010:
14782 if (INTEL_INFO(dev)->gen < 4) {
14783 DRM_DEBUG("unsupported pixel format: %s\n",
14784 drm_get_format_name(mode_cmd->pixel_format));
14785 return -EINVAL;
14786 }
14787 break;
14788 case DRM_FORMAT_ABGR2101010:
14789 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14790 DRM_DEBUG("unsupported pixel format: %s\n",
14791 drm_get_format_name(mode_cmd->pixel_format));
14792 return -EINVAL;
14793 }
14794 break;
14795 case DRM_FORMAT_YUYV:
14796 case DRM_FORMAT_UYVY:
14797 case DRM_FORMAT_YVYU:
14798 case DRM_FORMAT_VYUY:
14799 if (INTEL_INFO(dev)->gen < 5) {
14800 DRM_DEBUG("unsupported pixel format: %s\n",
14801 drm_get_format_name(mode_cmd->pixel_format));
14802 return -EINVAL;
14803 }
14804 break;
14805 default:
14806 DRM_DEBUG("unsupported pixel format: %s\n",
14807 drm_get_format_name(mode_cmd->pixel_format));
14808 return -EINVAL;
14809 }
14810
14811 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14812 if (mode_cmd->offsets[0] != 0)
14813 return -EINVAL;
14814
14815 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14816 mode_cmd->pixel_format,
14817 mode_cmd->modifier[0]);
14818 /* FIXME drm helper for size checks (especially planar formats)? */
14819 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14820 return -EINVAL;
14821
14822 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14823 intel_fb->obj = obj;
14824
14825 intel_fill_fb_info(dev_priv, &intel_fb->base);
14826
14827 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14828 if (ret) {
14829 DRM_ERROR("framebuffer init failed %d\n", ret);
14830 return ret;
14831 }
14832
14833 intel_fb->obj->framebuffer_references++;
14834
14835 return 0;
14836 }
14837
14838 static struct drm_framebuffer *
14839 intel_user_framebuffer_create(struct drm_device *dev,
14840 struct drm_file *filp,
14841 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14842 {
14843 struct drm_framebuffer *fb;
14844 struct drm_i915_gem_object *obj;
14845 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14846
14847 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14848 mode_cmd.handles[0]));
14849 if (&obj->base == NULL)
14850 return ERR_PTR(-ENOENT);
14851
14852 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14853 if (IS_ERR(fb))
14854 drm_gem_object_unreference_unlocked(&obj->base);
14855
14856 return fb;
14857 }
14858
14859 #ifndef CONFIG_DRM_FBDEV_EMULATION
14860 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14861 {
14862 }
14863 #endif
14864
14865 static const struct drm_mode_config_funcs intel_mode_funcs = {
14866 .fb_create = intel_user_framebuffer_create,
14867 .output_poll_changed = intel_fbdev_output_poll_changed,
14868 .atomic_check = intel_atomic_check,
14869 .atomic_commit = intel_atomic_commit,
14870 .atomic_state_alloc = intel_atomic_state_alloc,
14871 .atomic_state_clear = intel_atomic_state_clear,
14872 };
14873
14874 /**
14875 * intel_init_display_hooks - initialize the display modesetting hooks
14876 * @dev_priv: device private
14877 */
14878 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14879 {
14880 if (INTEL_INFO(dev_priv)->gen >= 9) {
14881 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14882 dev_priv->display.get_initial_plane_config =
14883 skylake_get_initial_plane_config;
14884 dev_priv->display.crtc_compute_clock =
14885 haswell_crtc_compute_clock;
14886 dev_priv->display.crtc_enable = haswell_crtc_enable;
14887 dev_priv->display.crtc_disable = haswell_crtc_disable;
14888 } else if (HAS_DDI(dev_priv)) {
14889 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14890 dev_priv->display.get_initial_plane_config =
14891 ironlake_get_initial_plane_config;
14892 dev_priv->display.crtc_compute_clock =
14893 haswell_crtc_compute_clock;
14894 dev_priv->display.crtc_enable = haswell_crtc_enable;
14895 dev_priv->display.crtc_disable = haswell_crtc_disable;
14896 } else if (HAS_PCH_SPLIT(dev_priv)) {
14897 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14898 dev_priv->display.get_initial_plane_config =
14899 ironlake_get_initial_plane_config;
14900 dev_priv->display.crtc_compute_clock =
14901 ironlake_crtc_compute_clock;
14902 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14903 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14904 } else if (IS_CHERRYVIEW(dev_priv)) {
14905 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14906 dev_priv->display.get_initial_plane_config =
14907 i9xx_get_initial_plane_config;
14908 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14909 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14910 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14911 } else if (IS_VALLEYVIEW(dev_priv)) {
14912 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14913 dev_priv->display.get_initial_plane_config =
14914 i9xx_get_initial_plane_config;
14915 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14916 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14917 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14918 } else if (IS_G4X(dev_priv)) {
14919 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14920 dev_priv->display.get_initial_plane_config =
14921 i9xx_get_initial_plane_config;
14922 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14923 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14924 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14925 } else if (IS_PINEVIEW(dev_priv)) {
14926 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14927 dev_priv->display.get_initial_plane_config =
14928 i9xx_get_initial_plane_config;
14929 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14930 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14931 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14932 } else if (!IS_GEN2(dev_priv)) {
14933 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14934 dev_priv->display.get_initial_plane_config =
14935 i9xx_get_initial_plane_config;
14936 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14937 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14938 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14939 } else {
14940 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14941 dev_priv->display.get_initial_plane_config =
14942 i9xx_get_initial_plane_config;
14943 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14944 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14945 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14946 }
14947
14948 /* Returns the core display clock speed */
14949 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14950 dev_priv->display.get_display_clock_speed =
14951 skylake_get_display_clock_speed;
14952 else if (IS_BROXTON(dev_priv))
14953 dev_priv->display.get_display_clock_speed =
14954 broxton_get_display_clock_speed;
14955 else if (IS_BROADWELL(dev_priv))
14956 dev_priv->display.get_display_clock_speed =
14957 broadwell_get_display_clock_speed;
14958 else if (IS_HASWELL(dev_priv))
14959 dev_priv->display.get_display_clock_speed =
14960 haswell_get_display_clock_speed;
14961 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14962 dev_priv->display.get_display_clock_speed =
14963 valleyview_get_display_clock_speed;
14964 else if (IS_GEN5(dev_priv))
14965 dev_priv->display.get_display_clock_speed =
14966 ilk_get_display_clock_speed;
14967 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14968 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14969 dev_priv->display.get_display_clock_speed =
14970 i945_get_display_clock_speed;
14971 else if (IS_GM45(dev_priv))
14972 dev_priv->display.get_display_clock_speed =
14973 gm45_get_display_clock_speed;
14974 else if (IS_CRESTLINE(dev_priv))
14975 dev_priv->display.get_display_clock_speed =
14976 i965gm_get_display_clock_speed;
14977 else if (IS_PINEVIEW(dev_priv))
14978 dev_priv->display.get_display_clock_speed =
14979 pnv_get_display_clock_speed;
14980 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14981 dev_priv->display.get_display_clock_speed =
14982 g33_get_display_clock_speed;
14983 else if (IS_I915G(dev_priv))
14984 dev_priv->display.get_display_clock_speed =
14985 i915_get_display_clock_speed;
14986 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14987 dev_priv->display.get_display_clock_speed =
14988 i9xx_misc_get_display_clock_speed;
14989 else if (IS_I915GM(dev_priv))
14990 dev_priv->display.get_display_clock_speed =
14991 i915gm_get_display_clock_speed;
14992 else if (IS_I865G(dev_priv))
14993 dev_priv->display.get_display_clock_speed =
14994 i865_get_display_clock_speed;
14995 else if (IS_I85X(dev_priv))
14996 dev_priv->display.get_display_clock_speed =
14997 i85x_get_display_clock_speed;
14998 else { /* 830 */
14999 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15000 dev_priv->display.get_display_clock_speed =
15001 i830_get_display_clock_speed;
15002 }
15003
15004 if (IS_GEN5(dev_priv)) {
15005 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15006 } else if (IS_GEN6(dev_priv)) {
15007 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15008 } else if (IS_IVYBRIDGE(dev_priv)) {
15009 /* FIXME: detect B0+ stepping and use auto training */
15010 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15011 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15012 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15013 if (IS_BROADWELL(dev_priv)) {
15014 dev_priv->display.modeset_commit_cdclk =
15015 broadwell_modeset_commit_cdclk;
15016 dev_priv->display.modeset_calc_cdclk =
15017 broadwell_modeset_calc_cdclk;
15018 }
15019 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15020 dev_priv->display.modeset_commit_cdclk =
15021 valleyview_modeset_commit_cdclk;
15022 dev_priv->display.modeset_calc_cdclk =
15023 valleyview_modeset_calc_cdclk;
15024 } else if (IS_BROXTON(dev_priv)) {
15025 dev_priv->display.modeset_commit_cdclk =
15026 broxton_modeset_commit_cdclk;
15027 dev_priv->display.modeset_calc_cdclk =
15028 broxton_modeset_calc_cdclk;
15029 }
15030
15031 switch (INTEL_INFO(dev_priv)->gen) {
15032 case 2:
15033 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15034 break;
15035
15036 case 3:
15037 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15038 break;
15039
15040 case 4:
15041 case 5:
15042 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15043 break;
15044
15045 case 6:
15046 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15047 break;
15048 case 7:
15049 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15050 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15051 break;
15052 case 9:
15053 /* Drop through - unsupported since execlist only. */
15054 default:
15055 /* Default just returns -ENODEV to indicate unsupported */
15056 dev_priv->display.queue_flip = intel_default_queue_flip;
15057 }
15058 }
15059
15060 /*
15061 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15062 * resume, or other times. This quirk makes sure that's the case for
15063 * affected systems.
15064 */
15065 static void quirk_pipea_force(struct drm_device *dev)
15066 {
15067 struct drm_i915_private *dev_priv = dev->dev_private;
15068
15069 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15070 DRM_INFO("applying pipe a force quirk\n");
15071 }
15072
15073 static void quirk_pipeb_force(struct drm_device *dev)
15074 {
15075 struct drm_i915_private *dev_priv = dev->dev_private;
15076
15077 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15078 DRM_INFO("applying pipe b force quirk\n");
15079 }
15080
15081 /*
15082 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15083 */
15084 static void quirk_ssc_force_disable(struct drm_device *dev)
15085 {
15086 struct drm_i915_private *dev_priv = dev->dev_private;
15087 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15088 DRM_INFO("applying lvds SSC disable quirk\n");
15089 }
15090
15091 /*
15092 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15093 * brightness value
15094 */
15095 static void quirk_invert_brightness(struct drm_device *dev)
15096 {
15097 struct drm_i915_private *dev_priv = dev->dev_private;
15098 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15099 DRM_INFO("applying inverted panel brightness quirk\n");
15100 }
15101
15102 /* Some VBT's incorrectly indicate no backlight is present */
15103 static void quirk_backlight_present(struct drm_device *dev)
15104 {
15105 struct drm_i915_private *dev_priv = dev->dev_private;
15106 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15107 DRM_INFO("applying backlight present quirk\n");
15108 }
15109
15110 struct intel_quirk {
15111 int device;
15112 int subsystem_vendor;
15113 int subsystem_device;
15114 void (*hook)(struct drm_device *dev);
15115 };
15116
15117 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15118 struct intel_dmi_quirk {
15119 void (*hook)(struct drm_device *dev);
15120 const struct dmi_system_id (*dmi_id_list)[];
15121 };
15122
15123 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15124 {
15125 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15126 return 1;
15127 }
15128
15129 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15130 {
15131 .dmi_id_list = &(const struct dmi_system_id[]) {
15132 {
15133 .callback = intel_dmi_reverse_brightness,
15134 .ident = "NCR Corporation",
15135 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15136 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15137 },
15138 },
15139 { } /* terminating entry */
15140 },
15141 .hook = quirk_invert_brightness,
15142 },
15143 };
15144
15145 static struct intel_quirk intel_quirks[] = {
15146 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15147 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15148
15149 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15150 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15151
15152 /* 830 needs to leave pipe A & dpll A up */
15153 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15154
15155 /* 830 needs to leave pipe B & dpll B up */
15156 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15157
15158 /* Lenovo U160 cannot use SSC on LVDS */
15159 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15160
15161 /* Sony Vaio Y cannot use SSC on LVDS */
15162 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15163
15164 /* Acer Aspire 5734Z must invert backlight brightness */
15165 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15166
15167 /* Acer/eMachines G725 */
15168 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15169
15170 /* Acer/eMachines e725 */
15171 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15172
15173 /* Acer/Packard Bell NCL20 */
15174 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15175
15176 /* Acer Aspire 4736Z */
15177 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15178
15179 /* Acer Aspire 5336 */
15180 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15181
15182 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15183 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15184
15185 /* Acer C720 Chromebook (Core i3 4005U) */
15186 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15187
15188 /* Apple Macbook 2,1 (Core 2 T7400) */
15189 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15190
15191 /* Apple Macbook 4,1 */
15192 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15193
15194 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15195 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15196
15197 /* HP Chromebook 14 (Celeron 2955U) */
15198 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15199
15200 /* Dell Chromebook 11 */
15201 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15202
15203 /* Dell Chromebook 11 (2015 version) */
15204 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15205 };
15206
15207 static void intel_init_quirks(struct drm_device *dev)
15208 {
15209 struct pci_dev *d = dev->pdev;
15210 int i;
15211
15212 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15213 struct intel_quirk *q = &intel_quirks[i];
15214
15215 if (d->device == q->device &&
15216 (d->subsystem_vendor == q->subsystem_vendor ||
15217 q->subsystem_vendor == PCI_ANY_ID) &&
15218 (d->subsystem_device == q->subsystem_device ||
15219 q->subsystem_device == PCI_ANY_ID))
15220 q->hook(dev);
15221 }
15222 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15223 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15224 intel_dmi_quirks[i].hook(dev);
15225 }
15226 }
15227
15228 /* Disable the VGA plane that we never use */
15229 static void i915_disable_vga(struct drm_device *dev)
15230 {
15231 struct drm_i915_private *dev_priv = dev->dev_private;
15232 u8 sr1;
15233 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15234
15235 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15236 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15237 outb(SR01, VGA_SR_INDEX);
15238 sr1 = inb(VGA_SR_DATA);
15239 outb(sr1 | 1<<5, VGA_SR_DATA);
15240 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15241 udelay(300);
15242
15243 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15244 POSTING_READ(vga_reg);
15245 }
15246
15247 void intel_modeset_init_hw(struct drm_device *dev)
15248 {
15249 struct drm_i915_private *dev_priv = dev->dev_private;
15250
15251 intel_update_cdclk(dev);
15252
15253 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15254
15255 intel_init_clock_gating(dev);
15256 intel_enable_gt_powersave(dev);
15257 }
15258
15259 /*
15260 * Calculate what we think the watermarks should be for the state we've read
15261 * out of the hardware and then immediately program those watermarks so that
15262 * we ensure the hardware settings match our internal state.
15263 *
15264 * We can calculate what we think WM's should be by creating a duplicate of the
15265 * current state (which was constructed during hardware readout) and running it
15266 * through the atomic check code to calculate new watermark values in the
15267 * state object.
15268 */
15269 static void sanitize_watermarks(struct drm_device *dev)
15270 {
15271 struct drm_i915_private *dev_priv = to_i915(dev);
15272 struct drm_atomic_state *state;
15273 struct drm_crtc *crtc;
15274 struct drm_crtc_state *cstate;
15275 struct drm_modeset_acquire_ctx ctx;
15276 int ret;
15277 int i;
15278
15279 /* Only supported on platforms that use atomic watermark design */
15280 if (!dev_priv->display.optimize_watermarks)
15281 return;
15282
15283 /*
15284 * We need to hold connection_mutex before calling duplicate_state so
15285 * that the connector loop is protected.
15286 */
15287 drm_modeset_acquire_init(&ctx, 0);
15288 retry:
15289 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15290 if (ret == -EDEADLK) {
15291 drm_modeset_backoff(&ctx);
15292 goto retry;
15293 } else if (WARN_ON(ret)) {
15294 goto fail;
15295 }
15296
15297 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15298 if (WARN_ON(IS_ERR(state)))
15299 goto fail;
15300
15301 /*
15302 * Hardware readout is the only time we don't want to calculate
15303 * intermediate watermarks (since we don't trust the current
15304 * watermarks).
15305 */
15306 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15307
15308 ret = intel_atomic_check(dev, state);
15309 if (ret) {
15310 /*
15311 * If we fail here, it means that the hardware appears to be
15312 * programmed in a way that shouldn't be possible, given our
15313 * understanding of watermark requirements. This might mean a
15314 * mistake in the hardware readout code or a mistake in the
15315 * watermark calculations for a given platform. Raise a WARN
15316 * so that this is noticeable.
15317 *
15318 * If this actually happens, we'll have to just leave the
15319 * BIOS-programmed watermarks untouched and hope for the best.
15320 */
15321 WARN(true, "Could not determine valid watermarks for inherited state\n");
15322 goto fail;
15323 }
15324
15325 /* Write calculated watermark values back */
15326 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15327 for_each_crtc_in_state(state, crtc, cstate, i) {
15328 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15329
15330 cs->wm.need_postvbl_update = true;
15331 dev_priv->display.optimize_watermarks(cs);
15332 }
15333
15334 drm_atomic_state_free(state);
15335 fail:
15336 drm_modeset_drop_locks(&ctx);
15337 drm_modeset_acquire_fini(&ctx);
15338 }
15339
15340 void intel_modeset_init(struct drm_device *dev)
15341 {
15342 struct drm_i915_private *dev_priv = to_i915(dev);
15343 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15344 int sprite, ret;
15345 enum pipe pipe;
15346 struct intel_crtc *crtc;
15347
15348 drm_mode_config_init(dev);
15349
15350 dev->mode_config.min_width = 0;
15351 dev->mode_config.min_height = 0;
15352
15353 dev->mode_config.preferred_depth = 24;
15354 dev->mode_config.prefer_shadow = 1;
15355
15356 dev->mode_config.allow_fb_modifiers = true;
15357
15358 dev->mode_config.funcs = &intel_mode_funcs;
15359
15360 intel_init_quirks(dev);
15361
15362 intel_init_pm(dev);
15363
15364 if (INTEL_INFO(dev)->num_pipes == 0)
15365 return;
15366
15367 /*
15368 * There may be no VBT; and if the BIOS enabled SSC we can
15369 * just keep using it to avoid unnecessary flicker. Whereas if the
15370 * BIOS isn't using it, don't assume it will work even if the VBT
15371 * indicates as much.
15372 */
15373 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15374 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15375 DREF_SSC1_ENABLE);
15376
15377 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15378 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15379 bios_lvds_use_ssc ? "en" : "dis",
15380 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15381 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15382 }
15383 }
15384
15385 if (IS_GEN2(dev)) {
15386 dev->mode_config.max_width = 2048;
15387 dev->mode_config.max_height = 2048;
15388 } else if (IS_GEN3(dev)) {
15389 dev->mode_config.max_width = 4096;
15390 dev->mode_config.max_height = 4096;
15391 } else {
15392 dev->mode_config.max_width = 8192;
15393 dev->mode_config.max_height = 8192;
15394 }
15395
15396 if (IS_845G(dev) || IS_I865G(dev)) {
15397 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15398 dev->mode_config.cursor_height = 1023;
15399 } else if (IS_GEN2(dev)) {
15400 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15401 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15402 } else {
15403 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15404 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15405 }
15406
15407 dev->mode_config.fb_base = ggtt->mappable_base;
15408
15409 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15410 INTEL_INFO(dev)->num_pipes,
15411 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15412
15413 for_each_pipe(dev_priv, pipe) {
15414 intel_crtc_init(dev, pipe);
15415 for_each_sprite(dev_priv, pipe, sprite) {
15416 ret = intel_plane_init(dev, pipe, sprite);
15417 if (ret)
15418 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15419 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15420 }
15421 }
15422
15423 intel_update_czclk(dev_priv);
15424 intel_update_rawclk(dev_priv);
15425 intel_update_cdclk(dev);
15426
15427 intel_shared_dpll_init(dev);
15428
15429 /* Just disable it once at startup */
15430 i915_disable_vga(dev);
15431 intel_setup_outputs(dev);
15432
15433 drm_modeset_lock_all(dev);
15434 intel_modeset_setup_hw_state(dev);
15435 drm_modeset_unlock_all(dev);
15436
15437 for_each_intel_crtc(dev, crtc) {
15438 struct intel_initial_plane_config plane_config = {};
15439
15440 if (!crtc->active)
15441 continue;
15442
15443 /*
15444 * Note that reserving the BIOS fb up front prevents us
15445 * from stuffing other stolen allocations like the ring
15446 * on top. This prevents some ugliness at boot time, and
15447 * can even allow for smooth boot transitions if the BIOS
15448 * fb is large enough for the active pipe configuration.
15449 */
15450 dev_priv->display.get_initial_plane_config(crtc,
15451 &plane_config);
15452
15453 /*
15454 * If the fb is shared between multiple heads, we'll
15455 * just get the first one.
15456 */
15457 intel_find_initial_plane_obj(crtc, &plane_config);
15458 }
15459
15460 /*
15461 * Make sure hardware watermarks really match the state we read out.
15462 * Note that we need to do this after reconstructing the BIOS fb's
15463 * since the watermark calculation done here will use pstate->fb.
15464 */
15465 sanitize_watermarks(dev);
15466 }
15467
15468 static void intel_enable_pipe_a(struct drm_device *dev)
15469 {
15470 struct intel_connector *connector;
15471 struct drm_connector *crt = NULL;
15472 struct intel_load_detect_pipe load_detect_temp;
15473 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15474
15475 /* We can't just switch on the pipe A, we need to set things up with a
15476 * proper mode and output configuration. As a gross hack, enable pipe A
15477 * by enabling the load detect pipe once. */
15478 for_each_intel_connector(dev, connector) {
15479 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15480 crt = &connector->base;
15481 break;
15482 }
15483 }
15484
15485 if (!crt)
15486 return;
15487
15488 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15489 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15490 }
15491
15492 static bool
15493 intel_check_plane_mapping(struct intel_crtc *crtc)
15494 {
15495 struct drm_device *dev = crtc->base.dev;
15496 struct drm_i915_private *dev_priv = dev->dev_private;
15497 u32 val;
15498
15499 if (INTEL_INFO(dev)->num_pipes == 1)
15500 return true;
15501
15502 val = I915_READ(DSPCNTR(!crtc->plane));
15503
15504 if ((val & DISPLAY_PLANE_ENABLE) &&
15505 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15506 return false;
15507
15508 return true;
15509 }
15510
15511 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15512 {
15513 struct drm_device *dev = crtc->base.dev;
15514 struct intel_encoder *encoder;
15515
15516 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15517 return true;
15518
15519 return false;
15520 }
15521
15522 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15523 {
15524 struct drm_device *dev = encoder->base.dev;
15525 struct intel_connector *connector;
15526
15527 for_each_connector_on_encoder(dev, &encoder->base, connector)
15528 return true;
15529
15530 return false;
15531 }
15532
15533 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15534 {
15535 struct drm_device *dev = crtc->base.dev;
15536 struct drm_i915_private *dev_priv = dev->dev_private;
15537 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15538
15539 /* Clear any frame start delays used for debugging left by the BIOS */
15540 if (!transcoder_is_dsi(cpu_transcoder)) {
15541 i915_reg_t reg = PIPECONF(cpu_transcoder);
15542
15543 I915_WRITE(reg,
15544 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15545 }
15546
15547 /* restore vblank interrupts to correct state */
15548 drm_crtc_vblank_reset(&crtc->base);
15549 if (crtc->active) {
15550 struct intel_plane *plane;
15551
15552 drm_crtc_vblank_on(&crtc->base);
15553
15554 /* Disable everything but the primary plane */
15555 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15556 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15557 continue;
15558
15559 plane->disable_plane(&plane->base, &crtc->base);
15560 }
15561 }
15562
15563 /* We need to sanitize the plane -> pipe mapping first because this will
15564 * disable the crtc (and hence change the state) if it is wrong. Note
15565 * that gen4+ has a fixed plane -> pipe mapping. */
15566 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15567 bool plane;
15568
15569 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15570 crtc->base.base.id);
15571
15572 /* Pipe has the wrong plane attached and the plane is active.
15573 * Temporarily change the plane mapping and disable everything
15574 * ... */
15575 plane = crtc->plane;
15576 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15577 crtc->plane = !plane;
15578 intel_crtc_disable_noatomic(&crtc->base);
15579 crtc->plane = plane;
15580 }
15581
15582 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15583 crtc->pipe == PIPE_A && !crtc->active) {
15584 /* BIOS forgot to enable pipe A, this mostly happens after
15585 * resume. Force-enable the pipe to fix this, the update_dpms
15586 * call below we restore the pipe to the right state, but leave
15587 * the required bits on. */
15588 intel_enable_pipe_a(dev);
15589 }
15590
15591 /* Adjust the state of the output pipe according to whether we
15592 * have active connectors/encoders. */
15593 if (crtc->active && !intel_crtc_has_encoders(crtc))
15594 intel_crtc_disable_noatomic(&crtc->base);
15595
15596 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15597 /*
15598 * We start out with underrun reporting disabled to avoid races.
15599 * For correct bookkeeping mark this on active crtcs.
15600 *
15601 * Also on gmch platforms we dont have any hardware bits to
15602 * disable the underrun reporting. Which means we need to start
15603 * out with underrun reporting disabled also on inactive pipes,
15604 * since otherwise we'll complain about the garbage we read when
15605 * e.g. coming up after runtime pm.
15606 *
15607 * No protection against concurrent access is required - at
15608 * worst a fifo underrun happens which also sets this to false.
15609 */
15610 crtc->cpu_fifo_underrun_disabled = true;
15611 crtc->pch_fifo_underrun_disabled = true;
15612 }
15613 }
15614
15615 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15616 {
15617 struct intel_connector *connector;
15618 struct drm_device *dev = encoder->base.dev;
15619
15620 /* We need to check both for a crtc link (meaning that the
15621 * encoder is active and trying to read from a pipe) and the
15622 * pipe itself being active. */
15623 bool has_active_crtc = encoder->base.crtc &&
15624 to_intel_crtc(encoder->base.crtc)->active;
15625
15626 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15627 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15628 encoder->base.base.id,
15629 encoder->base.name);
15630
15631 /* Connector is active, but has no active pipe. This is
15632 * fallout from our resume register restoring. Disable
15633 * the encoder manually again. */
15634 if (encoder->base.crtc) {
15635 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15636 encoder->base.base.id,
15637 encoder->base.name);
15638 encoder->disable(encoder);
15639 if (encoder->post_disable)
15640 encoder->post_disable(encoder);
15641 }
15642 encoder->base.crtc = NULL;
15643
15644 /* Inconsistent output/port/pipe state happens presumably due to
15645 * a bug in one of the get_hw_state functions. Or someplace else
15646 * in our code, like the register restore mess on resume. Clamp
15647 * things to off as a safer default. */
15648 for_each_intel_connector(dev, connector) {
15649 if (connector->encoder != encoder)
15650 continue;
15651 connector->base.dpms = DRM_MODE_DPMS_OFF;
15652 connector->base.encoder = NULL;
15653 }
15654 }
15655 /* Enabled encoders without active connectors will be fixed in
15656 * the crtc fixup. */
15657 }
15658
15659 void i915_redisable_vga_power_on(struct drm_device *dev)
15660 {
15661 struct drm_i915_private *dev_priv = dev->dev_private;
15662 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15663
15664 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15665 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15666 i915_disable_vga(dev);
15667 }
15668 }
15669
15670 void i915_redisable_vga(struct drm_device *dev)
15671 {
15672 struct drm_i915_private *dev_priv = dev->dev_private;
15673
15674 /* This function can be called both from intel_modeset_setup_hw_state or
15675 * at a very early point in our resume sequence, where the power well
15676 * structures are not yet restored. Since this function is at a very
15677 * paranoid "someone might have enabled VGA while we were not looking"
15678 * level, just check if the power well is enabled instead of trying to
15679 * follow the "don't touch the power well if we don't need it" policy
15680 * the rest of the driver uses. */
15681 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15682 return;
15683
15684 i915_redisable_vga_power_on(dev);
15685
15686 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15687 }
15688
15689 static bool primary_get_hw_state(struct intel_plane *plane)
15690 {
15691 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15692
15693 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15694 }
15695
15696 /* FIXME read out full plane state for all planes */
15697 static void readout_plane_state(struct intel_crtc *crtc)
15698 {
15699 struct drm_plane *primary = crtc->base.primary;
15700 struct intel_plane_state *plane_state =
15701 to_intel_plane_state(primary->state);
15702
15703 plane_state->visible = crtc->active &&
15704 primary_get_hw_state(to_intel_plane(primary));
15705
15706 if (plane_state->visible)
15707 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15708 }
15709
15710 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15711 {
15712 struct drm_i915_private *dev_priv = dev->dev_private;
15713 enum pipe pipe;
15714 struct intel_crtc *crtc;
15715 struct intel_encoder *encoder;
15716 struct intel_connector *connector;
15717 int i;
15718
15719 dev_priv->active_crtcs = 0;
15720
15721 for_each_intel_crtc(dev, crtc) {
15722 struct intel_crtc_state *crtc_state = crtc->config;
15723 int pixclk = 0;
15724
15725 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15726 memset(crtc_state, 0, sizeof(*crtc_state));
15727 crtc_state->base.crtc = &crtc->base;
15728
15729 crtc_state->base.active = crtc_state->base.enable =
15730 dev_priv->display.get_pipe_config(crtc, crtc_state);
15731
15732 crtc->base.enabled = crtc_state->base.enable;
15733 crtc->active = crtc_state->base.active;
15734
15735 if (crtc_state->base.active) {
15736 dev_priv->active_crtcs |= 1 << crtc->pipe;
15737
15738 if (IS_BROADWELL(dev_priv)) {
15739 pixclk = ilk_pipe_pixel_rate(crtc_state);
15740
15741 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15742 if (crtc_state->ips_enabled)
15743 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15744 } else if (IS_VALLEYVIEW(dev_priv) ||
15745 IS_CHERRYVIEW(dev_priv) ||
15746 IS_BROXTON(dev_priv))
15747 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15748 else
15749 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15750 }
15751
15752 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15753
15754 readout_plane_state(crtc);
15755
15756 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15757 crtc->base.base.id,
15758 crtc->active ? "enabled" : "disabled");
15759 }
15760
15761 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15762 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15763
15764 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15765 &pll->config.hw_state);
15766 pll->config.crtc_mask = 0;
15767 for_each_intel_crtc(dev, crtc) {
15768 if (crtc->active && crtc->config->shared_dpll == pll)
15769 pll->config.crtc_mask |= 1 << crtc->pipe;
15770 }
15771 pll->active_mask = pll->config.crtc_mask;
15772
15773 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15774 pll->name, pll->config.crtc_mask, pll->on);
15775 }
15776
15777 for_each_intel_encoder(dev, encoder) {
15778 pipe = 0;
15779
15780 if (encoder->get_hw_state(encoder, &pipe)) {
15781 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15782 encoder->base.crtc = &crtc->base;
15783 encoder->get_config(encoder, crtc->config);
15784 } else {
15785 encoder->base.crtc = NULL;
15786 }
15787
15788 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15789 encoder->base.base.id,
15790 encoder->base.name,
15791 encoder->base.crtc ? "enabled" : "disabled",
15792 pipe_name(pipe));
15793 }
15794
15795 for_each_intel_connector(dev, connector) {
15796 if (connector->get_hw_state(connector)) {
15797 connector->base.dpms = DRM_MODE_DPMS_ON;
15798
15799 encoder = connector->encoder;
15800 connector->base.encoder = &encoder->base;
15801
15802 if (encoder->base.crtc &&
15803 encoder->base.crtc->state->active) {
15804 /*
15805 * This has to be done during hardware readout
15806 * because anything calling .crtc_disable may
15807 * rely on the connector_mask being accurate.
15808 */
15809 encoder->base.crtc->state->connector_mask |=
15810 1 << drm_connector_index(&connector->base);
15811 encoder->base.crtc->state->encoder_mask |=
15812 1 << drm_encoder_index(&encoder->base);
15813 }
15814
15815 } else {
15816 connector->base.dpms = DRM_MODE_DPMS_OFF;
15817 connector->base.encoder = NULL;
15818 }
15819 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15820 connector->base.base.id,
15821 connector->base.name,
15822 connector->base.encoder ? "enabled" : "disabled");
15823 }
15824
15825 for_each_intel_crtc(dev, crtc) {
15826 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15827
15828 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15829 if (crtc->base.state->active) {
15830 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15831 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15832 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15833
15834 /*
15835 * The initial mode needs to be set in order to keep
15836 * the atomic core happy. It wants a valid mode if the
15837 * crtc's enabled, so we do the above call.
15838 *
15839 * At this point some state updated by the connectors
15840 * in their ->detect() callback has not run yet, so
15841 * no recalculation can be done yet.
15842 *
15843 * Even if we could do a recalculation and modeset
15844 * right now it would cause a double modeset if
15845 * fbdev or userspace chooses a different initial mode.
15846 *
15847 * If that happens, someone indicated they wanted a
15848 * mode change, which means it's safe to do a full
15849 * recalculation.
15850 */
15851 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15852
15853 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15854 update_scanline_offset(crtc);
15855 }
15856
15857 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15858 }
15859 }
15860
15861 /* Scan out the current hw modeset state,
15862 * and sanitizes it to the current state
15863 */
15864 static void
15865 intel_modeset_setup_hw_state(struct drm_device *dev)
15866 {
15867 struct drm_i915_private *dev_priv = dev->dev_private;
15868 enum pipe pipe;
15869 struct intel_crtc *crtc;
15870 struct intel_encoder *encoder;
15871 int i;
15872
15873 intel_modeset_readout_hw_state(dev);
15874
15875 /* HW state is read out, now we need to sanitize this mess. */
15876 for_each_intel_encoder(dev, encoder) {
15877 intel_sanitize_encoder(encoder);
15878 }
15879
15880 for_each_pipe(dev_priv, pipe) {
15881 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15882 intel_sanitize_crtc(crtc);
15883 intel_dump_pipe_config(crtc, crtc->config,
15884 "[setup_hw_state]");
15885 }
15886
15887 intel_modeset_update_connector_atomic_state(dev);
15888
15889 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15890 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15891
15892 if (!pll->on || pll->active_mask)
15893 continue;
15894
15895 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15896
15897 pll->funcs.disable(dev_priv, pll);
15898 pll->on = false;
15899 }
15900
15901 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15902 vlv_wm_get_hw_state(dev);
15903 else if (IS_GEN9(dev))
15904 skl_wm_get_hw_state(dev);
15905 else if (HAS_PCH_SPLIT(dev))
15906 ilk_wm_get_hw_state(dev);
15907
15908 for_each_intel_crtc(dev, crtc) {
15909 unsigned long put_domains;
15910
15911 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15912 if (WARN_ON(put_domains))
15913 modeset_put_power_domains(dev_priv, put_domains);
15914 }
15915 intel_display_set_init_power(dev_priv, false);
15916
15917 intel_fbc_init_pipe_state(dev_priv);
15918 }
15919
15920 void intel_display_resume(struct drm_device *dev)
15921 {
15922 struct drm_i915_private *dev_priv = to_i915(dev);
15923 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15924 struct drm_modeset_acquire_ctx ctx;
15925 int ret;
15926 bool setup = false;
15927
15928 dev_priv->modeset_restore_state = NULL;
15929
15930 /*
15931 * This is a cludge because with real atomic modeset mode_config.mutex
15932 * won't be taken. Unfortunately some probed state like
15933 * audio_codec_enable is still protected by mode_config.mutex, so lock
15934 * it here for now.
15935 */
15936 mutex_lock(&dev->mode_config.mutex);
15937 drm_modeset_acquire_init(&ctx, 0);
15938
15939 retry:
15940 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15941
15942 if (ret == 0 && !setup) {
15943 setup = true;
15944
15945 intel_modeset_setup_hw_state(dev);
15946 i915_redisable_vga(dev);
15947 }
15948
15949 if (ret == 0 && state) {
15950 struct drm_crtc_state *crtc_state;
15951 struct drm_crtc *crtc;
15952 int i;
15953
15954 state->acquire_ctx = &ctx;
15955
15956 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15957 /*
15958 * Force recalculation even if we restore
15959 * current state. With fast modeset this may not result
15960 * in a modeset when the state is compatible.
15961 */
15962 crtc_state->mode_changed = true;
15963 }
15964
15965 ret = drm_atomic_commit(state);
15966 }
15967
15968 if (ret == -EDEADLK) {
15969 drm_modeset_backoff(&ctx);
15970 goto retry;
15971 }
15972
15973 drm_modeset_drop_locks(&ctx);
15974 drm_modeset_acquire_fini(&ctx);
15975 mutex_unlock(&dev->mode_config.mutex);
15976
15977 if (ret) {
15978 DRM_ERROR("Restoring old state failed with %i\n", ret);
15979 drm_atomic_state_free(state);
15980 }
15981 }
15982
15983 void intel_modeset_gem_init(struct drm_device *dev)
15984 {
15985 struct drm_crtc *c;
15986 struct drm_i915_gem_object *obj;
15987 int ret;
15988
15989 intel_init_gt_powersave(dev);
15990
15991 intel_modeset_init_hw(dev);
15992
15993 intel_setup_overlay(dev);
15994
15995 /*
15996 * Make sure any fbs we allocated at startup are properly
15997 * pinned & fenced. When we do the allocation it's too early
15998 * for this.
15999 */
16000 for_each_crtc(dev, c) {
16001 obj = intel_fb_obj(c->primary->fb);
16002 if (obj == NULL)
16003 continue;
16004
16005 mutex_lock(&dev->struct_mutex);
16006 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16007 c->primary->state->rotation);
16008 mutex_unlock(&dev->struct_mutex);
16009 if (ret) {
16010 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16011 to_intel_crtc(c)->pipe);
16012 drm_framebuffer_unreference(c->primary->fb);
16013 c->primary->fb = NULL;
16014 c->primary->crtc = c->primary->state->crtc = NULL;
16015 update_state_fb(c->primary);
16016 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16017 }
16018 }
16019
16020 intel_backlight_register(dev);
16021 }
16022
16023 void intel_connector_unregister(struct intel_connector *intel_connector)
16024 {
16025 struct drm_connector *connector = &intel_connector->base;
16026
16027 intel_panel_destroy_backlight(connector);
16028 drm_connector_unregister(connector);
16029 }
16030
16031 void intel_modeset_cleanup(struct drm_device *dev)
16032 {
16033 struct drm_i915_private *dev_priv = dev->dev_private;
16034 struct intel_connector *connector;
16035
16036 intel_disable_gt_powersave(dev);
16037
16038 intel_backlight_unregister(dev);
16039
16040 /*
16041 * Interrupts and polling as the first thing to avoid creating havoc.
16042 * Too much stuff here (turning of connectors, ...) would
16043 * experience fancy races otherwise.
16044 */
16045 intel_irq_uninstall(dev_priv);
16046
16047 /*
16048 * Due to the hpd irq storm handling the hotplug work can re-arm the
16049 * poll handlers. Hence disable polling after hpd handling is shut down.
16050 */
16051 drm_kms_helper_poll_fini(dev);
16052
16053 intel_unregister_dsm_handler();
16054
16055 intel_fbc_global_disable(dev_priv);
16056
16057 /* flush any delayed tasks or pending work */
16058 flush_scheduled_work();
16059
16060 /* destroy the backlight and sysfs files before encoders/connectors */
16061 for_each_intel_connector(dev, connector)
16062 connector->unregister(connector);
16063
16064 drm_mode_config_cleanup(dev);
16065
16066 intel_cleanup_overlay(dev);
16067
16068 intel_cleanup_gt_powersave(dev);
16069
16070 intel_teardown_gmbus(dev);
16071 }
16072
16073 /*
16074 * Return which encoder is currently attached for connector.
16075 */
16076 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16077 {
16078 return &intel_attached_encoder(connector)->base;
16079 }
16080
16081 void intel_connector_attach_encoder(struct intel_connector *connector,
16082 struct intel_encoder *encoder)
16083 {
16084 connector->encoder = encoder;
16085 drm_mode_connector_attach_encoder(&connector->base,
16086 &encoder->base);
16087 }
16088
16089 /*
16090 * set vga decode state - true == enable VGA decode
16091 */
16092 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16093 {
16094 struct drm_i915_private *dev_priv = dev->dev_private;
16095 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16096 u16 gmch_ctrl;
16097
16098 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16099 DRM_ERROR("failed to read control word\n");
16100 return -EIO;
16101 }
16102
16103 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16104 return 0;
16105
16106 if (state)
16107 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16108 else
16109 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16110
16111 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16112 DRM_ERROR("failed to write control word\n");
16113 return -EIO;
16114 }
16115
16116 return 0;
16117 }
16118
16119 struct intel_display_error_state {
16120
16121 u32 power_well_driver;
16122
16123 int num_transcoders;
16124
16125 struct intel_cursor_error_state {
16126 u32 control;
16127 u32 position;
16128 u32 base;
16129 u32 size;
16130 } cursor[I915_MAX_PIPES];
16131
16132 struct intel_pipe_error_state {
16133 bool power_domain_on;
16134 u32 source;
16135 u32 stat;
16136 } pipe[I915_MAX_PIPES];
16137
16138 struct intel_plane_error_state {
16139 u32 control;
16140 u32 stride;
16141 u32 size;
16142 u32 pos;
16143 u32 addr;
16144 u32 surface;
16145 u32 tile_offset;
16146 } plane[I915_MAX_PIPES];
16147
16148 struct intel_transcoder_error_state {
16149 bool power_domain_on;
16150 enum transcoder cpu_transcoder;
16151
16152 u32 conf;
16153
16154 u32 htotal;
16155 u32 hblank;
16156 u32 hsync;
16157 u32 vtotal;
16158 u32 vblank;
16159 u32 vsync;
16160 } transcoder[4];
16161 };
16162
16163 struct intel_display_error_state *
16164 intel_display_capture_error_state(struct drm_device *dev)
16165 {
16166 struct drm_i915_private *dev_priv = dev->dev_private;
16167 struct intel_display_error_state *error;
16168 int transcoders[] = {
16169 TRANSCODER_A,
16170 TRANSCODER_B,
16171 TRANSCODER_C,
16172 TRANSCODER_EDP,
16173 };
16174 int i;
16175
16176 if (INTEL_INFO(dev)->num_pipes == 0)
16177 return NULL;
16178
16179 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16180 if (error == NULL)
16181 return NULL;
16182
16183 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16184 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16185
16186 for_each_pipe(dev_priv, i) {
16187 error->pipe[i].power_domain_on =
16188 __intel_display_power_is_enabled(dev_priv,
16189 POWER_DOMAIN_PIPE(i));
16190 if (!error->pipe[i].power_domain_on)
16191 continue;
16192
16193 error->cursor[i].control = I915_READ(CURCNTR(i));
16194 error->cursor[i].position = I915_READ(CURPOS(i));
16195 error->cursor[i].base = I915_READ(CURBASE(i));
16196
16197 error->plane[i].control = I915_READ(DSPCNTR(i));
16198 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16199 if (INTEL_INFO(dev)->gen <= 3) {
16200 error->plane[i].size = I915_READ(DSPSIZE(i));
16201 error->plane[i].pos = I915_READ(DSPPOS(i));
16202 }
16203 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16204 error->plane[i].addr = I915_READ(DSPADDR(i));
16205 if (INTEL_INFO(dev)->gen >= 4) {
16206 error->plane[i].surface = I915_READ(DSPSURF(i));
16207 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16208 }
16209
16210 error->pipe[i].source = I915_READ(PIPESRC(i));
16211
16212 if (HAS_GMCH_DISPLAY(dev))
16213 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16214 }
16215
16216 /* Note: this does not include DSI transcoders. */
16217 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16218 if (HAS_DDI(dev_priv))
16219 error->num_transcoders++; /* Account for eDP. */
16220
16221 for (i = 0; i < error->num_transcoders; i++) {
16222 enum transcoder cpu_transcoder = transcoders[i];
16223
16224 error->transcoder[i].power_domain_on =
16225 __intel_display_power_is_enabled(dev_priv,
16226 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16227 if (!error->transcoder[i].power_domain_on)
16228 continue;
16229
16230 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16231
16232 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16233 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16234 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16235 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16236 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16237 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16238 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16239 }
16240
16241 return error;
16242 }
16243
16244 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16245
16246 void
16247 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16248 struct drm_device *dev,
16249 struct intel_display_error_state *error)
16250 {
16251 struct drm_i915_private *dev_priv = dev->dev_private;
16252 int i;
16253
16254 if (!error)
16255 return;
16256
16257 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16258 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16259 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16260 error->power_well_driver);
16261 for_each_pipe(dev_priv, i) {
16262 err_printf(m, "Pipe [%d]:\n", i);
16263 err_printf(m, " Power: %s\n",
16264 onoff(error->pipe[i].power_domain_on));
16265 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16266 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16267
16268 err_printf(m, "Plane [%d]:\n", i);
16269 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16270 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16271 if (INTEL_INFO(dev)->gen <= 3) {
16272 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16273 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16274 }
16275 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16276 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16277 if (INTEL_INFO(dev)->gen >= 4) {
16278 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16279 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16280 }
16281
16282 err_printf(m, "Cursor [%d]:\n", i);
16283 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16284 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16285 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16286 }
16287
16288 for (i = 0; i < error->num_transcoders; i++) {
16289 err_printf(m, "CPU transcoder: %s\n",
16290 transcoder_name(error->transcoder[i].cpu_transcoder));
16291 err_printf(m, " Power: %s\n",
16292 onoff(error->transcoder[i].power_domain_on));
16293 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16294 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16295 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16296 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16297 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16298 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16299 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16300 }
16301 }
Linux kernel - Deliverables
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